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[qemu.git] / target-mips / op_helper.c
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include "cpu.h"
21 #include "qemu/host-utils.h"
22
23 #include "helper.h"
24
25 #if !defined(CONFIG_USER_ONLY)
26 #include "exec/softmmu_exec.h"
27 #endif /* !defined(CONFIG_USER_ONLY) */
28
29 #ifndef CONFIG_USER_ONLY
30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
31 #endif
32
33 /*****************************************************************************/
34 /* Exceptions processing helpers */
35
36 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
37 uint32_t exception,
38 int error_code,
39 uintptr_t pc)
40 {
41 if (exception < EXCP_SC) {
42 qemu_log("%s: %d %d\n", __func__, exception, error_code);
43 }
44 env->exception_index = exception;
45 env->error_code = error_code;
46
47 if (pc) {
48 /* now we have a real cpu fault */
49 cpu_restore_state(env, pc);
50 }
51
52 cpu_loop_exit(env);
53 }
54
55 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
56 uint32_t exception,
57 uintptr_t pc)
58 {
59 do_raise_exception_err(env, exception, 0, pc);
60 }
61
62 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
63 int error_code)
64 {
65 do_raise_exception_err(env, exception, error_code, 0);
66 }
67
68 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
69 {
70 do_raise_exception(env, exception, 0);
71 }
72
73 #if defined(CONFIG_USER_ONLY)
74 #define HELPER_LD(name, insn, type) \
75 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
76 int mem_idx) \
77 { \
78 return (type) insn##_raw(addr); \
79 }
80 #else
81 #define HELPER_LD(name, insn, type) \
82 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
83 int mem_idx) \
84 { \
85 switch (mem_idx) \
86 { \
87 case 0: return (type) cpu_##insn##_kernel(env, addr); break; \
88 case 1: return (type) cpu_##insn##_super(env, addr); break; \
89 default: \
90 case 2: return (type) cpu_##insn##_user(env, addr); break; \
91 } \
92 }
93 #endif
94 HELPER_LD(lbu, ldub, uint8_t)
95 HELPER_LD(lw, ldl, int32_t)
96 #ifdef TARGET_MIPS64
97 HELPER_LD(ld, ldq, int64_t)
98 #endif
99 #undef HELPER_LD
100
101 #if defined(CONFIG_USER_ONLY)
102 #define HELPER_ST(name, insn, type) \
103 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
104 type val, int mem_idx) \
105 { \
106 insn##_raw(addr, val); \
107 }
108 #else
109 #define HELPER_ST(name, insn, type) \
110 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
111 type val, int mem_idx) \
112 { \
113 switch (mem_idx) \
114 { \
115 case 0: cpu_##insn##_kernel(env, addr, val); break; \
116 case 1: cpu_##insn##_super(env, addr, val); break; \
117 default: \
118 case 2: cpu_##insn##_user(env, addr, val); break; \
119 } \
120 }
121 #endif
122 HELPER_ST(sb, stb, uint8_t)
123 HELPER_ST(sw, stl, uint32_t)
124 #ifdef TARGET_MIPS64
125 HELPER_ST(sd, stq, uint64_t)
126 #endif
127 #undef HELPER_ST
128
129 target_ulong helper_clo (target_ulong arg1)
130 {
131 return clo32(arg1);
132 }
133
134 target_ulong helper_clz (target_ulong arg1)
135 {
136 return clz32(arg1);
137 }
138
139 #if defined(TARGET_MIPS64)
140 target_ulong helper_dclo (target_ulong arg1)
141 {
142 return clo64(arg1);
143 }
144
145 target_ulong helper_dclz (target_ulong arg1)
146 {
147 return clz64(arg1);
148 }
149 #endif /* TARGET_MIPS64 */
150
151 /* 64 bits arithmetic for 32 bits hosts */
152 static inline uint64_t get_HILO(CPUMIPSState *env)
153 {
154 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
155 }
156
157 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
158 {
159 target_ulong tmp;
160 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
161 tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
162 return tmp;
163 }
164
165 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
166 {
167 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
168 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
169 return tmp;
170 }
171
172 /* Multiplication variants of the vr54xx. */
173 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
174 target_ulong arg2)
175 {
176 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
177 (int64_t)(int32_t)arg2));
178 }
179
180 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
181 target_ulong arg2)
182 {
183 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
184 (uint64_t)(uint32_t)arg2);
185 }
186
187 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
188 target_ulong arg2)
189 {
190 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
191 (int64_t)(int32_t)arg2);
192 }
193
194 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
195 target_ulong arg2)
196 {
197 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
198 (int64_t)(int32_t)arg2);
199 }
200
201 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
202 target_ulong arg2)
203 {
204 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
205 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
206 }
207
208 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
209 target_ulong arg2)
210 {
211 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
212 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
213 }
214
215 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
216 target_ulong arg2)
217 {
218 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
219 (int64_t)(int32_t)arg2);
220 }
221
222 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
223 target_ulong arg2)
224 {
225 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
226 (int64_t)(int32_t)arg2);
227 }
228
229 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
230 target_ulong arg2)
231 {
232 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
233 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
234 }
235
236 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
237 target_ulong arg2)
238 {
239 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
240 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
241 }
242
243 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
244 target_ulong arg2)
245 {
246 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
247 }
248
249 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
250 target_ulong arg2)
251 {
252 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
253 (uint64_t)(uint32_t)arg2);
254 }
255
256 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
257 target_ulong arg2)
258 {
259 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
260 (int64_t)(int32_t)arg2);
261 }
262
263 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
264 target_ulong arg2)
265 {
266 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
267 (uint64_t)(uint32_t)arg2);
268 }
269
270 #ifdef TARGET_MIPS64
271 void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
272 {
273 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
274 }
275
276 void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
277 {
278 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
279 }
280 #endif
281
282 #ifndef CONFIG_USER_ONLY
283
284 static inline hwaddr do_translate_address(CPUMIPSState *env,
285 target_ulong address,
286 int rw)
287 {
288 hwaddr lladdr;
289
290 lladdr = cpu_mips_translate_address(env, address, rw);
291
292 if (lladdr == -1LL) {
293 cpu_loop_exit(env);
294 } else {
295 return lladdr;
296 }
297 }
298
299 #define HELPER_LD_ATOMIC(name, insn) \
300 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
301 { \
302 env->lladdr = do_translate_address(env, arg, 0); \
303 env->llval = do_##insn(env, arg, mem_idx); \
304 return env->llval; \
305 }
306 HELPER_LD_ATOMIC(ll, lw)
307 #ifdef TARGET_MIPS64
308 HELPER_LD_ATOMIC(lld, ld)
309 #endif
310 #undef HELPER_LD_ATOMIC
311
312 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
313 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
314 target_ulong arg2, int mem_idx) \
315 { \
316 target_long tmp; \
317 \
318 if (arg2 & almask) { \
319 env->CP0_BadVAddr = arg2; \
320 helper_raise_exception(env, EXCP_AdES); \
321 } \
322 if (do_translate_address(env, arg2, 1) == env->lladdr) { \
323 tmp = do_##ld_insn(env, arg2, mem_idx); \
324 if (tmp == env->llval) { \
325 do_##st_insn(env, arg2, arg1, mem_idx); \
326 return 1; \
327 } \
328 } \
329 return 0; \
330 }
331 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
332 #ifdef TARGET_MIPS64
333 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
334 #endif
335 #undef HELPER_ST_ATOMIC
336 #endif
337
338 #ifdef TARGET_WORDS_BIGENDIAN
339 #define GET_LMASK(v) ((v) & 3)
340 #define GET_OFFSET(addr, offset) (addr + (offset))
341 #else
342 #define GET_LMASK(v) (((v) & 3) ^ 3)
343 #define GET_OFFSET(addr, offset) (addr - (offset))
344 #endif
345
346 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
347 int mem_idx)
348 {
349 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
350
351 if (GET_LMASK(arg2) <= 2)
352 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
353
354 if (GET_LMASK(arg2) <= 1)
355 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
356
357 if (GET_LMASK(arg2) == 0)
358 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
359 }
360
361 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
362 int mem_idx)
363 {
364 do_sb(env, arg2, (uint8_t)arg1, mem_idx);
365
366 if (GET_LMASK(arg2) >= 1)
367 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
368
369 if (GET_LMASK(arg2) >= 2)
370 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
371
372 if (GET_LMASK(arg2) == 3)
373 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
374 }
375
376 #if defined(TARGET_MIPS64)
377 /* "half" load and stores. We must do the memory access inline,
378 or fault handling won't work. */
379
380 #ifdef TARGET_WORDS_BIGENDIAN
381 #define GET_LMASK64(v) ((v) & 7)
382 #else
383 #define GET_LMASK64(v) (((v) & 7) ^ 7)
384 #endif
385
386 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
387 int mem_idx)
388 {
389 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
390
391 if (GET_LMASK64(arg2) <= 6)
392 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
393
394 if (GET_LMASK64(arg2) <= 5)
395 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
396
397 if (GET_LMASK64(arg2) <= 4)
398 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
399
400 if (GET_LMASK64(arg2) <= 3)
401 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
402
403 if (GET_LMASK64(arg2) <= 2)
404 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
405
406 if (GET_LMASK64(arg2) <= 1)
407 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
408
409 if (GET_LMASK64(arg2) <= 0)
410 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
411 }
412
413 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
414 int mem_idx)
415 {
416 do_sb(env, arg2, (uint8_t)arg1, mem_idx);
417
418 if (GET_LMASK64(arg2) >= 1)
419 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
420
421 if (GET_LMASK64(arg2) >= 2)
422 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
423
424 if (GET_LMASK64(arg2) >= 3)
425 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
426
427 if (GET_LMASK64(arg2) >= 4)
428 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
429
430 if (GET_LMASK64(arg2) >= 5)
431 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
432
433 if (GET_LMASK64(arg2) >= 6)
434 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
435
436 if (GET_LMASK64(arg2) == 7)
437 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
438 }
439 #endif /* TARGET_MIPS64 */
440
441 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
442
443 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
444 uint32_t mem_idx)
445 {
446 target_ulong base_reglist = reglist & 0xf;
447 target_ulong do_r31 = reglist & 0x10;
448
449 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
450 target_ulong i;
451
452 for (i = 0; i < base_reglist; i++) {
453 env->active_tc.gpr[multiple_regs[i]] =
454 (target_long)do_lw(env, addr, mem_idx);
455 addr += 4;
456 }
457 }
458
459 if (do_r31) {
460 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
461 }
462 }
463
464 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
465 uint32_t mem_idx)
466 {
467 target_ulong base_reglist = reglist & 0xf;
468 target_ulong do_r31 = reglist & 0x10;
469
470 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
471 target_ulong i;
472
473 for (i = 0; i < base_reglist; i++) {
474 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
475 addr += 4;
476 }
477 }
478
479 if (do_r31) {
480 do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
481 }
482 }
483
484 #if defined(TARGET_MIPS64)
485 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
486 uint32_t mem_idx)
487 {
488 target_ulong base_reglist = reglist & 0xf;
489 target_ulong do_r31 = reglist & 0x10;
490
491 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
492 target_ulong i;
493
494 for (i = 0; i < base_reglist; i++) {
495 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
496 addr += 8;
497 }
498 }
499
500 if (do_r31) {
501 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
502 }
503 }
504
505 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
506 uint32_t mem_idx)
507 {
508 target_ulong base_reglist = reglist & 0xf;
509 target_ulong do_r31 = reglist & 0x10;
510
511 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
512 target_ulong i;
513
514 for (i = 0; i < base_reglist; i++) {
515 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
516 addr += 8;
517 }
518 }
519
520 if (do_r31) {
521 do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
522 }
523 }
524 #endif
525
526 #ifndef CONFIG_USER_ONLY
527 /* SMP helpers. */
528 static bool mips_vpe_is_wfi(MIPSCPU *c)
529 {
530 CPUMIPSState *env = &c->env;
531
532 /* If the VPE is halted but otherwise active, it means it's waiting for
533 an interrupt. */
534 return env->halted && mips_vpe_active(env);
535 }
536
537 static inline void mips_vpe_wake(CPUMIPSState *c)
538 {
539 /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
540 because there might be other conditions that state that c should
541 be sleeping. */
542 cpu_interrupt(c, CPU_INTERRUPT_WAKE);
543 }
544
545 static inline void mips_vpe_sleep(MIPSCPU *cpu)
546 {
547 CPUMIPSState *c = &cpu->env;
548
549 /* The VPE was shut off, really go to bed.
550 Reset any old _WAKE requests. */
551 c->halted = 1;
552 cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
553 }
554
555 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
556 {
557 CPUMIPSState *c = &cpu->env;
558
559 /* FIXME: TC reschedule. */
560 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
561 mips_vpe_wake(c);
562 }
563 }
564
565 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
566 {
567 CPUMIPSState *c = &cpu->env;
568
569 /* FIXME: TC reschedule. */
570 if (!mips_vpe_active(c)) {
571 mips_vpe_sleep(cpu);
572 }
573 }
574
575 /* tc should point to an int with the value of the global TC index.
576 This function will transform it into a local index within the
577 returned CPUMIPSState.
578
579 FIXME: This code assumes that all VPEs have the same number of TCs,
580 which depends on runtime setup. Can probably be fixed by
581 walking the list of CPUMIPSStates. */
582 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
583 {
584 CPUState *cs;
585 CPUMIPSState *other;
586 int vpe_idx;
587 int tc_idx = *tc;
588
589 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
590 /* Not allowed to address other CPUs. */
591 *tc = env->current_tc;
592 return env;
593 }
594
595 cs = CPU(mips_env_get_cpu(env));
596 vpe_idx = tc_idx / cs->nr_threads;
597 *tc = tc_idx % cs->nr_threads;
598 other = qemu_get_cpu(vpe_idx);
599 return other ? other : env;
600 }
601
602 /* The per VPE CP0_Status register shares some fields with the per TC
603 CP0_TCStatus registers. These fields are wired to the same registers,
604 so changes to either of them should be reflected on both registers.
605
606 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
607
608 These helper call synchronizes the regs for a given cpu. */
609
610 /* Called for updates to CP0_Status. */
611 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
612 {
613 int32_t tcstatus, *tcst;
614 uint32_t v = cpu->CP0_Status;
615 uint32_t cu, mx, asid, ksu;
616 uint32_t mask = ((1 << CP0TCSt_TCU3)
617 | (1 << CP0TCSt_TCU2)
618 | (1 << CP0TCSt_TCU1)
619 | (1 << CP0TCSt_TCU0)
620 | (1 << CP0TCSt_TMX)
621 | (3 << CP0TCSt_TKSU)
622 | (0xff << CP0TCSt_TASID));
623
624 cu = (v >> CP0St_CU0) & 0xf;
625 mx = (v >> CP0St_MX) & 0x1;
626 ksu = (v >> CP0St_KSU) & 0x3;
627 asid = env->CP0_EntryHi & 0xff;
628
629 tcstatus = cu << CP0TCSt_TCU0;
630 tcstatus |= mx << CP0TCSt_TMX;
631 tcstatus |= ksu << CP0TCSt_TKSU;
632 tcstatus |= asid;
633
634 if (tc == cpu->current_tc) {
635 tcst = &cpu->active_tc.CP0_TCStatus;
636 } else {
637 tcst = &cpu->tcs[tc].CP0_TCStatus;
638 }
639
640 *tcst &= ~mask;
641 *tcst |= tcstatus;
642 compute_hflags(cpu);
643 }
644
645 /* Called for updates to CP0_TCStatus. */
646 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
647 target_ulong v)
648 {
649 uint32_t status;
650 uint32_t tcu, tmx, tasid, tksu;
651 uint32_t mask = ((1 << CP0St_CU3)
652 | (1 << CP0St_CU2)
653 | (1 << CP0St_CU1)
654 | (1 << CP0St_CU0)
655 | (1 << CP0St_MX)
656 | (3 << CP0St_KSU));
657
658 tcu = (v >> CP0TCSt_TCU0) & 0xf;
659 tmx = (v >> CP0TCSt_TMX) & 0x1;
660 tasid = v & 0xff;
661 tksu = (v >> CP0TCSt_TKSU) & 0x3;
662
663 status = tcu << CP0St_CU0;
664 status |= tmx << CP0St_MX;
665 status |= tksu << CP0St_KSU;
666
667 cpu->CP0_Status &= ~mask;
668 cpu->CP0_Status |= status;
669
670 /* Sync the TASID with EntryHi. */
671 cpu->CP0_EntryHi &= ~0xff;
672 cpu->CP0_EntryHi = tasid;
673
674 compute_hflags(cpu);
675 }
676
677 /* Called for updates to CP0_EntryHi. */
678 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
679 {
680 int32_t *tcst;
681 uint32_t asid, v = cpu->CP0_EntryHi;
682
683 asid = v & 0xff;
684
685 if (tc == cpu->current_tc) {
686 tcst = &cpu->active_tc.CP0_TCStatus;
687 } else {
688 tcst = &cpu->tcs[tc].CP0_TCStatus;
689 }
690
691 *tcst &= ~0xff;
692 *tcst |= asid;
693 }
694
695 /* CP0 helpers */
696 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
697 {
698 return env->mvp->CP0_MVPControl;
699 }
700
701 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
702 {
703 return env->mvp->CP0_MVPConf0;
704 }
705
706 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
707 {
708 return env->mvp->CP0_MVPConf1;
709 }
710
711 target_ulong helper_mfc0_random(CPUMIPSState *env)
712 {
713 return (int32_t)cpu_mips_get_random(env);
714 }
715
716 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
717 {
718 return env->active_tc.CP0_TCStatus;
719 }
720
721 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
722 {
723 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
724 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
725
726 if (other_tc == other->current_tc)
727 return other->active_tc.CP0_TCStatus;
728 else
729 return other->tcs[other_tc].CP0_TCStatus;
730 }
731
732 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
733 {
734 return env->active_tc.CP0_TCBind;
735 }
736
737 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
738 {
739 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
740 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
741
742 if (other_tc == other->current_tc)
743 return other->active_tc.CP0_TCBind;
744 else
745 return other->tcs[other_tc].CP0_TCBind;
746 }
747
748 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
749 {
750 return env->active_tc.PC;
751 }
752
753 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
754 {
755 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
756 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
757
758 if (other_tc == other->current_tc)
759 return other->active_tc.PC;
760 else
761 return other->tcs[other_tc].PC;
762 }
763
764 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
765 {
766 return env->active_tc.CP0_TCHalt;
767 }
768
769 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
770 {
771 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
772 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
773
774 if (other_tc == other->current_tc)
775 return other->active_tc.CP0_TCHalt;
776 else
777 return other->tcs[other_tc].CP0_TCHalt;
778 }
779
780 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
781 {
782 return env->active_tc.CP0_TCContext;
783 }
784
785 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
786 {
787 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
788 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
789
790 if (other_tc == other->current_tc)
791 return other->active_tc.CP0_TCContext;
792 else
793 return other->tcs[other_tc].CP0_TCContext;
794 }
795
796 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
797 {
798 return env->active_tc.CP0_TCSchedule;
799 }
800
801 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
802 {
803 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
804 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
805
806 if (other_tc == other->current_tc)
807 return other->active_tc.CP0_TCSchedule;
808 else
809 return other->tcs[other_tc].CP0_TCSchedule;
810 }
811
812 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
813 {
814 return env->active_tc.CP0_TCScheFBack;
815 }
816
817 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
818 {
819 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
820 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
821
822 if (other_tc == other->current_tc)
823 return other->active_tc.CP0_TCScheFBack;
824 else
825 return other->tcs[other_tc].CP0_TCScheFBack;
826 }
827
828 target_ulong helper_mfc0_count(CPUMIPSState *env)
829 {
830 return (int32_t)cpu_mips_get_count(env);
831 }
832
833 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
834 {
835 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
836 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
837
838 return other->CP0_EntryHi;
839 }
840
841 target_ulong helper_mftc0_cause(CPUMIPSState *env)
842 {
843 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
844 int32_t tccause;
845 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
846
847 if (other_tc == other->current_tc) {
848 tccause = other->CP0_Cause;
849 } else {
850 tccause = other->CP0_Cause;
851 }
852
853 return tccause;
854 }
855
856 target_ulong helper_mftc0_status(CPUMIPSState *env)
857 {
858 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
859 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
860
861 return other->CP0_Status;
862 }
863
864 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
865 {
866 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
867 }
868
869 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
870 {
871 return (int32_t)env->CP0_WatchLo[sel];
872 }
873
874 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
875 {
876 return env->CP0_WatchHi[sel];
877 }
878
879 target_ulong helper_mfc0_debug(CPUMIPSState *env)
880 {
881 target_ulong t0 = env->CP0_Debug;
882 if (env->hflags & MIPS_HFLAG_DM)
883 t0 |= 1 << CP0DB_DM;
884
885 return t0;
886 }
887
888 target_ulong helper_mftc0_debug(CPUMIPSState *env)
889 {
890 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
891 int32_t tcstatus;
892 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
893
894 if (other_tc == other->current_tc)
895 tcstatus = other->active_tc.CP0_Debug_tcstatus;
896 else
897 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
898
899 /* XXX: Might be wrong, check with EJTAG spec. */
900 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
901 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
902 }
903
904 #if defined(TARGET_MIPS64)
905 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
906 {
907 return env->active_tc.PC;
908 }
909
910 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
911 {
912 return env->active_tc.CP0_TCHalt;
913 }
914
915 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
916 {
917 return env->active_tc.CP0_TCContext;
918 }
919
920 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
921 {
922 return env->active_tc.CP0_TCSchedule;
923 }
924
925 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
926 {
927 return env->active_tc.CP0_TCScheFBack;
928 }
929
930 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
931 {
932 return env->lladdr >> env->CP0_LLAddr_shift;
933 }
934
935 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
936 {
937 return env->CP0_WatchLo[sel];
938 }
939 #endif /* TARGET_MIPS64 */
940
941 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
942 {
943 int num = 1;
944 unsigned int tmp = env->tlb->nb_tlb;
945
946 do {
947 tmp >>= 1;
948 num <<= 1;
949 } while (tmp);
950 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
951 }
952
953 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
954 {
955 uint32_t mask = 0;
956 uint32_t newval;
957
958 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
959 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
960 (1 << CP0MVPCo_EVP);
961 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
962 mask |= (1 << CP0MVPCo_STLB);
963 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
964
965 // TODO: Enable/disable shared TLB, enable/disable VPEs.
966
967 env->mvp->CP0_MVPControl = newval;
968 }
969
970 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
971 {
972 uint32_t mask;
973 uint32_t newval;
974
975 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
976 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
977 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
978
979 /* Yield scheduler intercept not implemented. */
980 /* Gating storage scheduler intercept not implemented. */
981
982 // TODO: Enable/disable TCs.
983
984 env->CP0_VPEControl = newval;
985 }
986
987 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
988 {
989 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
990 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
991 uint32_t mask;
992 uint32_t newval;
993
994 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
995 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
996 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
997
998 /* TODO: Enable/disable TCs. */
999
1000 other->CP0_VPEControl = newval;
1001 }
1002
1003 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1004 {
1005 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1006 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1007 /* FIXME: Mask away return zero on read bits. */
1008 return other->CP0_VPEControl;
1009 }
1010
1011 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1012 {
1013 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1014 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1015
1016 return other->CP0_VPEConf0;
1017 }
1018
1019 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1020 {
1021 uint32_t mask = 0;
1022 uint32_t newval;
1023
1024 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1025 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1026 mask |= (0xff << CP0VPEC0_XTC);
1027 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1028 }
1029 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1030
1031 // TODO: TC exclusive handling due to ERL/EXL.
1032
1033 env->CP0_VPEConf0 = newval;
1034 }
1035
1036 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1037 {
1038 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1039 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1040 uint32_t mask = 0;
1041 uint32_t newval;
1042
1043 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1044 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1045
1046 /* TODO: TC exclusive handling due to ERL/EXL. */
1047 other->CP0_VPEConf0 = newval;
1048 }
1049
1050 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1051 {
1052 uint32_t mask = 0;
1053 uint32_t newval;
1054
1055 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1056 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1057 (0xff << CP0VPEC1_NCP1);
1058 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1059
1060 /* UDI not implemented. */
1061 /* CP2 not implemented. */
1062
1063 // TODO: Handle FPU (CP1) binding.
1064
1065 env->CP0_VPEConf1 = newval;
1066 }
1067
1068 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1069 {
1070 /* Yield qualifier inputs not implemented. */
1071 env->CP0_YQMask = 0x00000000;
1072 }
1073
1074 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1075 {
1076 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1077 }
1078
1079 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1080 {
1081 /* Large physaddr (PABITS) not implemented */
1082 /* 1k pages not implemented */
1083 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1084 }
1085
1086 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1087 {
1088 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1089 uint32_t newval;
1090
1091 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1092
1093 env->active_tc.CP0_TCStatus = newval;
1094 sync_c0_tcstatus(env, env->current_tc, newval);
1095 }
1096
1097 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1098 {
1099 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1100 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1101
1102 if (other_tc == other->current_tc)
1103 other->active_tc.CP0_TCStatus = arg1;
1104 else
1105 other->tcs[other_tc].CP0_TCStatus = arg1;
1106 sync_c0_tcstatus(other, other_tc, arg1);
1107 }
1108
1109 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1110 {
1111 uint32_t mask = (1 << CP0TCBd_TBE);
1112 uint32_t newval;
1113
1114 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1115 mask |= (1 << CP0TCBd_CurVPE);
1116 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1117 env->active_tc.CP0_TCBind = newval;
1118 }
1119
1120 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1121 {
1122 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1123 uint32_t mask = (1 << CP0TCBd_TBE);
1124 uint32_t newval;
1125 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1126
1127 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1128 mask |= (1 << CP0TCBd_CurVPE);
1129 if (other_tc == other->current_tc) {
1130 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1131 other->active_tc.CP0_TCBind = newval;
1132 } else {
1133 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1134 other->tcs[other_tc].CP0_TCBind = newval;
1135 }
1136 }
1137
1138 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1139 {
1140 env->active_tc.PC = arg1;
1141 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1142 env->lladdr = 0ULL;
1143 /* MIPS16 not implemented. */
1144 }
1145
1146 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1147 {
1148 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1149 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1150
1151 if (other_tc == other->current_tc) {
1152 other->active_tc.PC = arg1;
1153 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1154 other->lladdr = 0ULL;
1155 /* MIPS16 not implemented. */
1156 } else {
1157 other->tcs[other_tc].PC = arg1;
1158 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1159 other->lladdr = 0ULL;
1160 /* MIPS16 not implemented. */
1161 }
1162 }
1163
1164 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1165 {
1166 MIPSCPU *cpu = mips_env_get_cpu(env);
1167
1168 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1169
1170 // TODO: Halt TC / Restart (if allocated+active) TC.
1171 if (env->active_tc.CP0_TCHalt & 1) {
1172 mips_tc_sleep(cpu, env->current_tc);
1173 } else {
1174 mips_tc_wake(cpu, env->current_tc);
1175 }
1176 }
1177
1178 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1179 {
1180 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1181 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1182 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1183
1184 // TODO: Halt TC / Restart (if allocated+active) TC.
1185
1186 if (other_tc == other->current_tc)
1187 other->active_tc.CP0_TCHalt = arg1;
1188 else
1189 other->tcs[other_tc].CP0_TCHalt = arg1;
1190
1191 if (arg1 & 1) {
1192 mips_tc_sleep(other_cpu, other_tc);
1193 } else {
1194 mips_tc_wake(other_cpu, other_tc);
1195 }
1196 }
1197
1198 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1199 {
1200 env->active_tc.CP0_TCContext = arg1;
1201 }
1202
1203 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1204 {
1205 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1206 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1207
1208 if (other_tc == other->current_tc)
1209 other->active_tc.CP0_TCContext = arg1;
1210 else
1211 other->tcs[other_tc].CP0_TCContext = arg1;
1212 }
1213
1214 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1215 {
1216 env->active_tc.CP0_TCSchedule = arg1;
1217 }
1218
1219 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1220 {
1221 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1222 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1223
1224 if (other_tc == other->current_tc)
1225 other->active_tc.CP0_TCSchedule = arg1;
1226 else
1227 other->tcs[other_tc].CP0_TCSchedule = arg1;
1228 }
1229
1230 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1231 {
1232 env->active_tc.CP0_TCScheFBack = arg1;
1233 }
1234
1235 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1236 {
1237 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1238 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1239
1240 if (other_tc == other->current_tc)
1241 other->active_tc.CP0_TCScheFBack = arg1;
1242 else
1243 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1244 }
1245
1246 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1247 {
1248 /* Large physaddr (PABITS) not implemented */
1249 /* 1k pages not implemented */
1250 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1251 }
1252
1253 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1254 {
1255 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1256 }
1257
1258 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1259 {
1260 /* 1k pages not implemented */
1261 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1262 }
1263
1264 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1265 {
1266 /* SmartMIPS not implemented */
1267 /* Large physaddr (PABITS) not implemented */
1268 /* 1k pages not implemented */
1269 env->CP0_PageGrain = 0;
1270 }
1271
1272 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1273 {
1274 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1275 }
1276
1277 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1278 {
1279 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1280 }
1281
1282 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1283 {
1284 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1285 }
1286
1287 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1288 {
1289 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1290 }
1291
1292 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1293 {
1294 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1295 }
1296
1297 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1298 {
1299 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1300 }
1301
1302 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1303 {
1304 env->CP0_HWREna = arg1 & 0x0000000F;
1305 }
1306
1307 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1308 {
1309 cpu_mips_store_count(env, arg1);
1310 }
1311
1312 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1313 {
1314 target_ulong old, val;
1315
1316 /* 1k pages not implemented */
1317 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1318 #if defined(TARGET_MIPS64)
1319 val &= env->SEGMask;
1320 #endif
1321 old = env->CP0_EntryHi;
1322 env->CP0_EntryHi = val;
1323 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1324 sync_c0_entryhi(env, env->current_tc);
1325 }
1326 /* If the ASID changes, flush qemu's TLB. */
1327 if ((old & 0xFF) != (val & 0xFF))
1328 cpu_mips_tlb_flush(env, 1);
1329 }
1330
1331 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1332 {
1333 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1334 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1335
1336 other->CP0_EntryHi = arg1;
1337 sync_c0_entryhi(other, other_tc);
1338 }
1339
1340 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1341 {
1342 cpu_mips_store_compare(env, arg1);
1343 }
1344
1345 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1346 {
1347 uint32_t val, old;
1348 uint32_t mask = env->CP0_Status_rw_bitmask;
1349
1350 val = arg1 & mask;
1351 old = env->CP0_Status;
1352 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1353 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1354 sync_c0_status(env, env, env->current_tc);
1355 } else {
1356 compute_hflags(env);
1357 }
1358
1359 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1360 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1361 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1362 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1363 env->CP0_Cause);
1364 switch (env->hflags & MIPS_HFLAG_KSU) {
1365 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1366 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1367 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1368 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1369 }
1370 }
1371 }
1372
1373 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1374 {
1375 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1376 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1377
1378 other->CP0_Status = arg1 & ~0xf1000018;
1379 sync_c0_status(env, other, other_tc);
1380 }
1381
1382 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1383 {
1384 /* vectored interrupts not implemented, no performance counters. */
1385 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1386 }
1387
1388 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1389 {
1390 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1391 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1392 }
1393
1394 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1395 {
1396 uint32_t mask = 0x00C00300;
1397 uint32_t old = cpu->CP0_Cause;
1398 int i;
1399
1400 if (cpu->insn_flags & ISA_MIPS32R2) {
1401 mask |= 1 << CP0Ca_DC;
1402 }
1403
1404 cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1405
1406 if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1407 if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1408 cpu_mips_stop_count(cpu);
1409 } else {
1410 cpu_mips_start_count(cpu);
1411 }
1412 }
1413
1414 /* Set/reset software interrupts */
1415 for (i = 0 ; i < 2 ; i++) {
1416 if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1417 cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1418 }
1419 }
1420 }
1421
1422 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1423 {
1424 mtc0_cause(env, arg1);
1425 }
1426
1427 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1428 {
1429 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1430 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1431
1432 mtc0_cause(other, arg1);
1433 }
1434
1435 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1436 {
1437 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1438 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1439
1440 return other->CP0_EPC;
1441 }
1442
1443 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1444 {
1445 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1446 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1447
1448 return other->CP0_EBase;
1449 }
1450
1451 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1452 {
1453 /* vectored interrupts not implemented */
1454 env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1455 }
1456
1457 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1458 {
1459 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1460 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1461 other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1462 }
1463
1464 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1465 {
1466 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1467 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1468
1469 switch (idx) {
1470 case 0: return other->CP0_Config0;
1471 case 1: return other->CP0_Config1;
1472 case 2: return other->CP0_Config2;
1473 case 3: return other->CP0_Config3;
1474 /* 4 and 5 are reserved. */
1475 case 6: return other->CP0_Config6;
1476 case 7: return other->CP0_Config7;
1477 default:
1478 break;
1479 }
1480 return 0;
1481 }
1482
1483 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1484 {
1485 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1486 }
1487
1488 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1489 {
1490 /* tertiary/secondary caches not implemented */
1491 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1492 }
1493
1494 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1495 {
1496 target_long mask = env->CP0_LLAddr_rw_bitmask;
1497 arg1 = arg1 << env->CP0_LLAddr_shift;
1498 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1499 }
1500
1501 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1502 {
1503 /* Watch exceptions for instructions, data loads, data stores
1504 not implemented. */
1505 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1506 }
1507
1508 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1509 {
1510 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1511 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1512 }
1513
1514 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1515 {
1516 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1517 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1518 }
1519
1520 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1521 {
1522 env->CP0_Framemask = arg1; /* XXX */
1523 }
1524
1525 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1526 {
1527 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1528 if (arg1 & (1 << CP0DB_DM))
1529 env->hflags |= MIPS_HFLAG_DM;
1530 else
1531 env->hflags &= ~MIPS_HFLAG_DM;
1532 }
1533
1534 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1535 {
1536 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1537 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1538 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1539
1540 /* XXX: Might be wrong, check with EJTAG spec. */
1541 if (other_tc == other->current_tc)
1542 other->active_tc.CP0_Debug_tcstatus = val;
1543 else
1544 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1545 other->CP0_Debug = (other->CP0_Debug &
1546 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1547 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1548 }
1549
1550 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1551 {
1552 env->CP0_Performance0 = arg1 & 0x000007ff;
1553 }
1554
1555 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1556 {
1557 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1558 }
1559
1560 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1561 {
1562 env->CP0_DataLo = arg1; /* XXX */
1563 }
1564
1565 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1566 {
1567 env->CP0_TagHi = arg1; /* XXX */
1568 }
1569
1570 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1571 {
1572 env->CP0_DataHi = arg1; /* XXX */
1573 }
1574
1575 /* MIPS MT functions */
1576 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1577 {
1578 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1579 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1580
1581 if (other_tc == other->current_tc)
1582 return other->active_tc.gpr[sel];
1583 else
1584 return other->tcs[other_tc].gpr[sel];
1585 }
1586
1587 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1588 {
1589 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1590 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1591
1592 if (other_tc == other->current_tc)
1593 return other->active_tc.LO[sel];
1594 else
1595 return other->tcs[other_tc].LO[sel];
1596 }
1597
1598 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1599 {
1600 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1601 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1602
1603 if (other_tc == other->current_tc)
1604 return other->active_tc.HI[sel];
1605 else
1606 return other->tcs[other_tc].HI[sel];
1607 }
1608
1609 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1610 {
1611 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1612 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1613
1614 if (other_tc == other->current_tc)
1615 return other->active_tc.ACX[sel];
1616 else
1617 return other->tcs[other_tc].ACX[sel];
1618 }
1619
1620 target_ulong helper_mftdsp(CPUMIPSState *env)
1621 {
1622 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1623 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1624
1625 if (other_tc == other->current_tc)
1626 return other->active_tc.DSPControl;
1627 else
1628 return other->tcs[other_tc].DSPControl;
1629 }
1630
1631 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1632 {
1633 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1634 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1635
1636 if (other_tc == other->current_tc)
1637 other->active_tc.gpr[sel] = arg1;
1638 else
1639 other->tcs[other_tc].gpr[sel] = arg1;
1640 }
1641
1642 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1643 {
1644 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1645 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1646
1647 if (other_tc == other->current_tc)
1648 other->active_tc.LO[sel] = arg1;
1649 else
1650 other->tcs[other_tc].LO[sel] = arg1;
1651 }
1652
1653 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1654 {
1655 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1656 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1657
1658 if (other_tc == other->current_tc)
1659 other->active_tc.HI[sel] = arg1;
1660 else
1661 other->tcs[other_tc].HI[sel] = arg1;
1662 }
1663
1664 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1665 {
1666 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1667 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1668
1669 if (other_tc == other->current_tc)
1670 other->active_tc.ACX[sel] = arg1;
1671 else
1672 other->tcs[other_tc].ACX[sel] = arg1;
1673 }
1674
1675 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1676 {
1677 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1678 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1679
1680 if (other_tc == other->current_tc)
1681 other->active_tc.DSPControl = arg1;
1682 else
1683 other->tcs[other_tc].DSPControl = arg1;
1684 }
1685
1686 /* MIPS MT functions */
1687 target_ulong helper_dmt(void)
1688 {
1689 // TODO
1690 return 0;
1691 }
1692
1693 target_ulong helper_emt(void)
1694 {
1695 // TODO
1696 return 0;
1697 }
1698
1699 target_ulong helper_dvpe(CPUMIPSState *env)
1700 {
1701 CPUMIPSState *other_cpu_env = first_cpu;
1702 target_ulong prev = env->mvp->CP0_MVPControl;
1703
1704 do {
1705 /* Turn off all VPEs except the one executing the dvpe. */
1706 if (other_cpu_env != env) {
1707 MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1708
1709 other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1710 mips_vpe_sleep(other_cpu);
1711 }
1712 other_cpu_env = other_cpu_env->next_cpu;
1713 } while (other_cpu_env);
1714 return prev;
1715 }
1716
1717 target_ulong helper_evpe(CPUMIPSState *env)
1718 {
1719 CPUMIPSState *other_cpu_env = first_cpu;
1720 target_ulong prev = env->mvp->CP0_MVPControl;
1721
1722 do {
1723 MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1724
1725 if (other_cpu_env != env
1726 /* If the VPE is WFI, don't disturb its sleep. */
1727 && !mips_vpe_is_wfi(other_cpu)) {
1728 /* Enable the VPE. */
1729 other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1730 mips_vpe_wake(other_cpu_env); /* And wake it up. */
1731 }
1732 other_cpu_env = other_cpu_env->next_cpu;
1733 } while (other_cpu_env);
1734 return prev;
1735 }
1736 #endif /* !CONFIG_USER_ONLY */
1737
1738 void helper_fork(target_ulong arg1, target_ulong arg2)
1739 {
1740 // arg1 = rt, arg2 = rs
1741 arg1 = 0;
1742 // TODO: store to TC register
1743 }
1744
1745 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1746 {
1747 target_long arg1 = arg;
1748
1749 if (arg1 < 0) {
1750 /* No scheduling policy implemented. */
1751 if (arg1 != -2) {
1752 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1753 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1754 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1755 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1756 helper_raise_exception(env, EXCP_THREAD);
1757 }
1758 }
1759 } else if (arg1 == 0) {
1760 if (0 /* TODO: TC underflow */) {
1761 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1762 helper_raise_exception(env, EXCP_THREAD);
1763 } else {
1764 // TODO: Deallocate TC
1765 }
1766 } else if (arg1 > 0) {
1767 /* Yield qualifier inputs not implemented. */
1768 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1769 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1770 helper_raise_exception(env, EXCP_THREAD);
1771 }
1772 return env->CP0_YQMask;
1773 }
1774
1775 #ifndef CONFIG_USER_ONLY
1776 /* TLB management */
1777 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1778 {
1779 /* Flush qemu's TLB and discard all shadowed entries. */
1780 tlb_flush (env, flush_global);
1781 env->tlb->tlb_in_use = env->tlb->nb_tlb;
1782 }
1783
1784 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1785 {
1786 /* Discard entries from env->tlb[first] onwards. */
1787 while (env->tlb->tlb_in_use > first) {
1788 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1789 }
1790 }
1791
1792 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1793 {
1794 r4k_tlb_t *tlb;
1795
1796 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1797 tlb = &env->tlb->mmu.r4k.tlb[idx];
1798 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1799 #if defined(TARGET_MIPS64)
1800 tlb->VPN &= env->SEGMask;
1801 #endif
1802 tlb->ASID = env->CP0_EntryHi & 0xFF;
1803 tlb->PageMask = env->CP0_PageMask;
1804 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1805 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1806 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1807 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1808 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1809 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1810 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1811 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1812 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1813 }
1814
1815 void r4k_helper_tlbwi(CPUMIPSState *env)
1816 {
1817 r4k_tlb_t *tlb;
1818 int idx;
1819 target_ulong VPN;
1820 uint8_t ASID;
1821 bool G, V0, D0, V1, D1;
1822
1823 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1824 tlb = &env->tlb->mmu.r4k.tlb[idx];
1825 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1826 #if defined(TARGET_MIPS64)
1827 VPN &= env->SEGMask;
1828 #endif
1829 ASID = env->CP0_EntryHi & 0xff;
1830 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1831 V0 = (env->CP0_EntryLo0 & 2) != 0;
1832 D0 = (env->CP0_EntryLo0 & 4) != 0;
1833 V1 = (env->CP0_EntryLo1 & 2) != 0;
1834 D1 = (env->CP0_EntryLo1 & 4) != 0;
1835
1836 /* Discard cached TLB entries, unless tlbwi is just upgrading access
1837 permissions on the current entry. */
1838 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1839 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1840 (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1841 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1842 }
1843
1844 r4k_invalidate_tlb(env, idx, 0);
1845 r4k_fill_tlb(env, idx);
1846 }
1847
1848 void r4k_helper_tlbwr(CPUMIPSState *env)
1849 {
1850 int r = cpu_mips_get_random(env);
1851
1852 r4k_invalidate_tlb(env, r, 1);
1853 r4k_fill_tlb(env, r);
1854 }
1855
1856 void r4k_helper_tlbp(CPUMIPSState *env)
1857 {
1858 r4k_tlb_t *tlb;
1859 target_ulong mask;
1860 target_ulong tag;
1861 target_ulong VPN;
1862 uint8_t ASID;
1863 int i;
1864
1865 ASID = env->CP0_EntryHi & 0xFF;
1866 for (i = 0; i < env->tlb->nb_tlb; i++) {
1867 tlb = &env->tlb->mmu.r4k.tlb[i];
1868 /* 1k pages are not supported. */
1869 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1870 tag = env->CP0_EntryHi & ~mask;
1871 VPN = tlb->VPN & ~mask;
1872 #if defined(TARGET_MIPS64)
1873 tag &= env->SEGMask;
1874 #endif
1875 /* Check ASID, virtual page number & size */
1876 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1877 /* TLB match */
1878 env->CP0_Index = i;
1879 break;
1880 }
1881 }
1882 if (i == env->tlb->nb_tlb) {
1883 /* No match. Discard any shadow entries, if any of them match. */
1884 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1885 tlb = &env->tlb->mmu.r4k.tlb[i];
1886 /* 1k pages are not supported. */
1887 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1888 tag = env->CP0_EntryHi & ~mask;
1889 VPN = tlb->VPN & ~mask;
1890 #if defined(TARGET_MIPS64)
1891 tag &= env->SEGMask;
1892 #endif
1893 /* Check ASID, virtual page number & size */
1894 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1895 r4k_mips_tlb_flush_extra (env, i);
1896 break;
1897 }
1898 }
1899
1900 env->CP0_Index |= 0x80000000;
1901 }
1902 }
1903
1904 void r4k_helper_tlbr(CPUMIPSState *env)
1905 {
1906 r4k_tlb_t *tlb;
1907 uint8_t ASID;
1908 int idx;
1909
1910 ASID = env->CP0_EntryHi & 0xFF;
1911 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1912 tlb = &env->tlb->mmu.r4k.tlb[idx];
1913
1914 /* If this will change the current ASID, flush qemu's TLB. */
1915 if (ASID != tlb->ASID)
1916 cpu_mips_tlb_flush (env, 1);
1917
1918 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1919
1920 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1921 env->CP0_PageMask = tlb->PageMask;
1922 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1923 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1924 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1925 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1926 }
1927
1928 void helper_tlbwi(CPUMIPSState *env)
1929 {
1930 env->tlb->helper_tlbwi(env);
1931 }
1932
1933 void helper_tlbwr(CPUMIPSState *env)
1934 {
1935 env->tlb->helper_tlbwr(env);
1936 }
1937
1938 void helper_tlbp(CPUMIPSState *env)
1939 {
1940 env->tlb->helper_tlbp(env);
1941 }
1942
1943 void helper_tlbr(CPUMIPSState *env)
1944 {
1945 env->tlb->helper_tlbr(env);
1946 }
1947
1948 /* Specials */
1949 target_ulong helper_di(CPUMIPSState *env)
1950 {
1951 target_ulong t0 = env->CP0_Status;
1952
1953 env->CP0_Status = t0 & ~(1 << CP0St_IE);
1954 return t0;
1955 }
1956
1957 target_ulong helper_ei(CPUMIPSState *env)
1958 {
1959 target_ulong t0 = env->CP0_Status;
1960
1961 env->CP0_Status = t0 | (1 << CP0St_IE);
1962 return t0;
1963 }
1964
1965 static void debug_pre_eret(CPUMIPSState *env)
1966 {
1967 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1968 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1969 env->active_tc.PC, env->CP0_EPC);
1970 if (env->CP0_Status & (1 << CP0St_ERL))
1971 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1972 if (env->hflags & MIPS_HFLAG_DM)
1973 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1974 qemu_log("\n");
1975 }
1976 }
1977
1978 static void debug_post_eret(CPUMIPSState *env)
1979 {
1980 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1981 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1982 env->active_tc.PC, env->CP0_EPC);
1983 if (env->CP0_Status & (1 << CP0St_ERL))
1984 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1985 if (env->hflags & MIPS_HFLAG_DM)
1986 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1987 switch (env->hflags & MIPS_HFLAG_KSU) {
1988 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1989 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1990 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1991 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1992 }
1993 }
1994 }
1995
1996 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
1997 {
1998 env->active_tc.PC = error_pc & ~(target_ulong)1;
1999 if (error_pc & 1) {
2000 env->hflags |= MIPS_HFLAG_M16;
2001 } else {
2002 env->hflags &= ~(MIPS_HFLAG_M16);
2003 }
2004 }
2005
2006 void helper_eret(CPUMIPSState *env)
2007 {
2008 debug_pre_eret(env);
2009 if (env->CP0_Status & (1 << CP0St_ERL)) {
2010 set_pc(env, env->CP0_ErrorEPC);
2011 env->CP0_Status &= ~(1 << CP0St_ERL);
2012 } else {
2013 set_pc(env, env->CP0_EPC);
2014 env->CP0_Status &= ~(1 << CP0St_EXL);
2015 }
2016 compute_hflags(env);
2017 debug_post_eret(env);
2018 env->lladdr = 1;
2019 }
2020
2021 void helper_deret(CPUMIPSState *env)
2022 {
2023 debug_pre_eret(env);
2024 set_pc(env, env->CP0_DEPC);
2025
2026 env->hflags &= MIPS_HFLAG_DM;
2027 compute_hflags(env);
2028 debug_post_eret(env);
2029 env->lladdr = 1;
2030 }
2031 #endif /* !CONFIG_USER_ONLY */
2032
2033 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2034 {
2035 if ((env->hflags & MIPS_HFLAG_CP0) ||
2036 (env->CP0_HWREna & (1 << 0)))
2037 return env->CP0_EBase & 0x3ff;
2038 else
2039 helper_raise_exception(env, EXCP_RI);
2040
2041 return 0;
2042 }
2043
2044 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2045 {
2046 if ((env->hflags & MIPS_HFLAG_CP0) ||
2047 (env->CP0_HWREna & (1 << 1)))
2048 return env->SYNCI_Step;
2049 else
2050 helper_raise_exception(env, EXCP_RI);
2051
2052 return 0;
2053 }
2054
2055 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2056 {
2057 if ((env->hflags & MIPS_HFLAG_CP0) ||
2058 (env->CP0_HWREna & (1 << 2)))
2059 return env->CP0_Count;
2060 else
2061 helper_raise_exception(env, EXCP_RI);
2062
2063 return 0;
2064 }
2065
2066 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2067 {
2068 if ((env->hflags & MIPS_HFLAG_CP0) ||
2069 (env->CP0_HWREna & (1 << 3)))
2070 return env->CCRes;
2071 else
2072 helper_raise_exception(env, EXCP_RI);
2073
2074 return 0;
2075 }
2076
2077 void helper_pmon(CPUMIPSState *env, int function)
2078 {
2079 function /= 2;
2080 switch (function) {
2081 case 2: /* TODO: char inbyte(int waitflag); */
2082 if (env->active_tc.gpr[4] == 0)
2083 env->active_tc.gpr[2] = -1;
2084 /* Fall through */
2085 case 11: /* TODO: char inbyte (void); */
2086 env->active_tc.gpr[2] = -1;
2087 break;
2088 case 3:
2089 case 12:
2090 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2091 break;
2092 case 17:
2093 break;
2094 case 158:
2095 {
2096 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2097 printf("%s", fmt);
2098 }
2099 break;
2100 }
2101 }
2102
2103 void helper_wait(CPUMIPSState *env)
2104 {
2105 env->halted = 1;
2106 cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE);
2107 helper_raise_exception(env, EXCP_HLT);
2108 }
2109
2110 #if !defined(CONFIG_USER_ONLY)
2111
2112 static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
2113 target_ulong addr, int is_write,
2114 int is_user, uintptr_t retaddr);
2115
2116 #define MMUSUFFIX _mmu
2117 #define ALIGNED_ONLY
2118
2119 #define SHIFT 0
2120 #include "exec/softmmu_template.h"
2121
2122 #define SHIFT 1
2123 #include "exec/softmmu_template.h"
2124
2125 #define SHIFT 2
2126 #include "exec/softmmu_template.h"
2127
2128 #define SHIFT 3
2129 #include "exec/softmmu_template.h"
2130
2131 static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
2132 int is_write, int is_user, uintptr_t retaddr)
2133 {
2134 env->CP0_BadVAddr = addr;
2135 do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2136 }
2137
2138 void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
2139 uintptr_t retaddr)
2140 {
2141 int ret;
2142
2143 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
2144 if (ret) {
2145 do_raise_exception_err(env, env->exception_index,
2146 env->error_code, retaddr);
2147 }
2148 }
2149
2150 void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
2151 int is_write, int is_exec, int unused, int size)
2152 {
2153 if (is_exec)
2154 helper_raise_exception(env, EXCP_IBE);
2155 else
2156 helper_raise_exception(env, EXCP_DBE);
2157 }
2158 #endif /* !CONFIG_USER_ONLY */
2159
2160 /* Complex FPU operations which may need stack space. */
2161
2162 #define FLOAT_TWO32 make_float32(1 << 30)
2163 #define FLOAT_TWO64 make_float64(1ULL << 62)
2164 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2165 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2166
2167 /* convert MIPS rounding mode in FCR31 to IEEE library */
2168 static unsigned int ieee_rm[] = {
2169 float_round_nearest_even,
2170 float_round_to_zero,
2171 float_round_up,
2172 float_round_down
2173 };
2174
2175 static inline void restore_rounding_mode(CPUMIPSState *env)
2176 {
2177 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2178 &env->active_fpu.fp_status);
2179 }
2180
2181 static inline void restore_flush_mode(CPUMIPSState *env)
2182 {
2183 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2184 &env->active_fpu.fp_status);
2185 }
2186
2187 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2188 {
2189 target_ulong arg1;
2190
2191 switch (reg) {
2192 case 0:
2193 arg1 = (int32_t)env->active_fpu.fcr0;
2194 break;
2195 case 25:
2196 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2197 break;
2198 case 26:
2199 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2200 break;
2201 case 28:
2202 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2203 break;
2204 default:
2205 arg1 = (int32_t)env->active_fpu.fcr31;
2206 break;
2207 }
2208
2209 return arg1;
2210 }
2211
2212 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
2213 {
2214 switch(reg) {
2215 case 25:
2216 if (arg1 & 0xffffff00)
2217 return;
2218 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2219 ((arg1 & 0x1) << 23);
2220 break;
2221 case 26:
2222 if (arg1 & 0x007c0000)
2223 return;
2224 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2225 break;
2226 case 28:
2227 if (arg1 & 0x007c0000)
2228 return;
2229 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2230 ((arg1 & 0x4) << 22);
2231 break;
2232 case 31:
2233 if (arg1 & 0x007c0000)
2234 return;
2235 env->active_fpu.fcr31 = arg1;
2236 break;
2237 default:
2238 return;
2239 }
2240 /* set rounding mode */
2241 restore_rounding_mode(env);
2242 /* set flush-to-zero mode */
2243 restore_flush_mode(env);
2244 set_float_exception_flags(0, &env->active_fpu.fp_status);
2245 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2246 do_raise_exception(env, EXCP_FPE, GETPC());
2247 }
2248
2249 static inline int ieee_ex_to_mips(int xcpt)
2250 {
2251 int ret = 0;
2252 if (xcpt) {
2253 if (xcpt & float_flag_invalid) {
2254 ret |= FP_INVALID;
2255 }
2256 if (xcpt & float_flag_overflow) {
2257 ret |= FP_OVERFLOW;
2258 }
2259 if (xcpt & float_flag_underflow) {
2260 ret |= FP_UNDERFLOW;
2261 }
2262 if (xcpt & float_flag_divbyzero) {
2263 ret |= FP_DIV0;
2264 }
2265 if (xcpt & float_flag_inexact) {
2266 ret |= FP_INEXACT;
2267 }
2268 }
2269 return ret;
2270 }
2271
2272 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2273 {
2274 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2275
2276 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2277
2278 if (tmp) {
2279 set_float_exception_flags(0, &env->active_fpu.fp_status);
2280
2281 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2282 do_raise_exception(env, EXCP_FPE, pc);
2283 } else {
2284 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2285 }
2286 }
2287 }
2288
2289 /* Float support.
2290 Single precition routines have a "s" suffix, double precision a
2291 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2292 paired single lower "pl", paired single upper "pu". */
2293
2294 /* unary operations, modifying fp status */
2295 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2296 {
2297 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2298 update_fcr31(env, GETPC());
2299 return fdt0;
2300 }
2301
2302 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2303 {
2304 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2305 update_fcr31(env, GETPC());
2306 return fst0;
2307 }
2308
2309 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2310 {
2311 uint64_t fdt2;
2312
2313 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2314 update_fcr31(env, GETPC());
2315 return fdt2;
2316 }
2317
2318 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2319 {
2320 uint64_t fdt2;
2321
2322 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2323 update_fcr31(env, GETPC());
2324 return fdt2;
2325 }
2326
2327 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2328 {
2329 uint64_t fdt2;
2330
2331 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2332 update_fcr31(env, GETPC());
2333 return fdt2;
2334 }
2335
2336 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2337 {
2338 uint64_t dt2;
2339
2340 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2341 if (get_float_exception_flags(&env->active_fpu.fp_status)
2342 & (float_flag_invalid | float_flag_overflow)) {
2343 dt2 = FP_TO_INT64_OVERFLOW;
2344 }
2345 update_fcr31(env, GETPC());
2346 return dt2;
2347 }
2348
2349 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2350 {
2351 uint64_t dt2;
2352
2353 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2354 if (get_float_exception_flags(&env->active_fpu.fp_status)
2355 & (float_flag_invalid | float_flag_overflow)) {
2356 dt2 = FP_TO_INT64_OVERFLOW;
2357 }
2358 update_fcr31(env, GETPC());
2359 return dt2;
2360 }
2361
2362 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2363 {
2364 uint32_t fst2;
2365 uint32_t fsth2;
2366
2367 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2368 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2369 update_fcr31(env, GETPC());
2370 return ((uint64_t)fsth2 << 32) | fst2;
2371 }
2372
2373 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2374 {
2375 uint32_t wt2;
2376 uint32_t wth2;
2377 int excp, excph;
2378
2379 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2380 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2381 if (excp & (float_flag_overflow | float_flag_invalid)) {
2382 wt2 = FP_TO_INT32_OVERFLOW;
2383 }
2384
2385 set_float_exception_flags(0, &env->active_fpu.fp_status);
2386 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2387 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2388 if (excph & (float_flag_overflow | float_flag_invalid)) {
2389 wth2 = FP_TO_INT32_OVERFLOW;
2390 }
2391
2392 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2393 update_fcr31(env, GETPC());
2394
2395 return ((uint64_t)wth2 << 32) | wt2;
2396 }
2397
2398 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2399 {
2400 uint32_t fst2;
2401
2402 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2403 update_fcr31(env, GETPC());
2404 return fst2;
2405 }
2406
2407 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2408 {
2409 uint32_t fst2;
2410
2411 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2412 update_fcr31(env, GETPC());
2413 return fst2;
2414 }
2415
2416 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2417 {
2418 uint32_t fst2;
2419
2420 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2421 update_fcr31(env, GETPC());
2422 return fst2;
2423 }
2424
2425 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2426 {
2427 uint32_t wt2;
2428
2429 wt2 = wt0;
2430 update_fcr31(env, GETPC());
2431 return wt2;
2432 }
2433
2434 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2435 {
2436 uint32_t wt2;
2437
2438 wt2 = wth0;
2439 update_fcr31(env, GETPC());
2440 return wt2;
2441 }
2442
2443 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2444 {
2445 uint32_t wt2;
2446
2447 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2448 update_fcr31(env, GETPC());
2449 if (get_float_exception_flags(&env->active_fpu.fp_status)
2450 & (float_flag_invalid | float_flag_overflow)) {
2451 wt2 = FP_TO_INT32_OVERFLOW;
2452 }
2453 return wt2;
2454 }
2455
2456 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2457 {
2458 uint32_t wt2;
2459
2460 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2461 if (get_float_exception_flags(&env->active_fpu.fp_status)
2462 & (float_flag_invalid | float_flag_overflow)) {
2463 wt2 = FP_TO_INT32_OVERFLOW;
2464 }
2465 update_fcr31(env, GETPC());
2466 return wt2;
2467 }
2468
2469 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2470 {
2471 uint64_t dt2;
2472
2473 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2474 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2475 restore_rounding_mode(env);
2476 if (get_float_exception_flags(&env->active_fpu.fp_status)
2477 & (float_flag_invalid | float_flag_overflow)) {
2478 dt2 = FP_TO_INT64_OVERFLOW;
2479 }
2480 update_fcr31(env, GETPC());
2481 return dt2;
2482 }
2483
2484 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2485 {
2486 uint64_t dt2;
2487
2488 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2489 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2490 restore_rounding_mode(env);
2491 if (get_float_exception_flags(&env->active_fpu.fp_status)
2492 & (float_flag_invalid | float_flag_overflow)) {
2493 dt2 = FP_TO_INT64_OVERFLOW;
2494 }
2495 update_fcr31(env, GETPC());
2496 return dt2;
2497 }
2498
2499 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2500 {
2501 uint32_t wt2;
2502
2503 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2504 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2505 restore_rounding_mode(env);
2506 if (get_float_exception_flags(&env->active_fpu.fp_status)
2507 & (float_flag_invalid | float_flag_overflow)) {
2508 wt2 = FP_TO_INT32_OVERFLOW;
2509 }
2510 update_fcr31(env, GETPC());
2511 return wt2;
2512 }
2513
2514 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2515 {
2516 uint32_t wt2;
2517
2518 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2519 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2520 restore_rounding_mode(env);
2521 if (get_float_exception_flags(&env->active_fpu.fp_status)
2522 & (float_flag_invalid | float_flag_overflow)) {
2523 wt2 = FP_TO_INT32_OVERFLOW;
2524 }
2525 update_fcr31(env, GETPC());
2526 return wt2;
2527 }
2528
2529 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2530 {
2531 uint64_t dt2;
2532
2533 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2534 if (get_float_exception_flags(&env->active_fpu.fp_status)
2535 & (float_flag_invalid | float_flag_overflow)) {
2536 dt2 = FP_TO_INT64_OVERFLOW;
2537 }
2538 update_fcr31(env, GETPC());
2539 return dt2;
2540 }
2541
2542 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2543 {
2544 uint64_t dt2;
2545
2546 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2547 if (get_float_exception_flags(&env->active_fpu.fp_status)
2548 & (float_flag_invalid | float_flag_overflow)) {
2549 dt2 = FP_TO_INT64_OVERFLOW;
2550 }
2551 update_fcr31(env, GETPC());
2552 return dt2;
2553 }
2554
2555 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2556 {
2557 uint32_t wt2;
2558
2559 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2560 if (get_float_exception_flags(&env->active_fpu.fp_status)
2561 & (float_flag_invalid | float_flag_overflow)) {
2562 wt2 = FP_TO_INT32_OVERFLOW;
2563 }
2564 update_fcr31(env, GETPC());
2565 return wt2;
2566 }
2567
2568 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2569 {
2570 uint32_t wt2;
2571
2572 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2573 if (get_float_exception_flags(&env->active_fpu.fp_status)
2574 & (float_flag_invalid | float_flag_overflow)) {
2575 wt2 = FP_TO_INT32_OVERFLOW;
2576 }
2577 update_fcr31(env, GETPC());
2578 return wt2;
2579 }
2580
2581 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2582 {
2583 uint64_t dt2;
2584
2585 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2586 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2587 restore_rounding_mode(env);
2588 if (get_float_exception_flags(&env->active_fpu.fp_status)
2589 & (float_flag_invalid | float_flag_overflow)) {
2590 dt2 = FP_TO_INT64_OVERFLOW;
2591 }
2592 update_fcr31(env, GETPC());
2593 return dt2;
2594 }
2595
2596 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2597 {
2598 uint64_t dt2;
2599
2600 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2601 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2602 restore_rounding_mode(env);
2603 if (get_float_exception_flags(&env->active_fpu.fp_status)
2604 & (float_flag_invalid | float_flag_overflow)) {
2605 dt2 = FP_TO_INT64_OVERFLOW;
2606 }
2607 update_fcr31(env, GETPC());
2608 return dt2;
2609 }
2610
2611 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2612 {
2613 uint32_t wt2;
2614
2615 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2616 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2617 restore_rounding_mode(env);
2618 if (get_float_exception_flags(&env->active_fpu.fp_status)
2619 & (float_flag_invalid | float_flag_overflow)) {
2620 wt2 = FP_TO_INT32_OVERFLOW;
2621 }
2622 update_fcr31(env, GETPC());
2623 return wt2;
2624 }
2625
2626 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2627 {
2628 uint32_t wt2;
2629
2630 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2631 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2632 restore_rounding_mode(env);
2633 if (get_float_exception_flags(&env->active_fpu.fp_status)
2634 & (float_flag_invalid | float_flag_overflow)) {
2635 wt2 = FP_TO_INT32_OVERFLOW;
2636 }
2637 update_fcr31(env, GETPC());
2638 return wt2;
2639 }
2640
2641 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2642 {
2643 uint64_t dt2;
2644
2645 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2646 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2647 restore_rounding_mode(env);
2648 if (get_float_exception_flags(&env->active_fpu.fp_status)
2649 & (float_flag_invalid | float_flag_overflow)) {
2650 dt2 = FP_TO_INT64_OVERFLOW;
2651 }
2652 update_fcr31(env, GETPC());
2653 return dt2;
2654 }
2655
2656 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2657 {
2658 uint64_t dt2;
2659
2660 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2661 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2662 restore_rounding_mode(env);
2663 if (get_float_exception_flags(&env->active_fpu.fp_status)
2664 & (float_flag_invalid | float_flag_overflow)) {
2665 dt2 = FP_TO_INT64_OVERFLOW;
2666 }
2667 update_fcr31(env, GETPC());
2668 return dt2;
2669 }
2670
2671 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2672 {
2673 uint32_t wt2;
2674
2675 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2676 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2677 restore_rounding_mode(env);
2678 if (get_float_exception_flags(&env->active_fpu.fp_status)
2679 & (float_flag_invalid | float_flag_overflow)) {
2680 wt2 = FP_TO_INT32_OVERFLOW;
2681 }
2682 update_fcr31(env, GETPC());
2683 return wt2;
2684 }
2685
2686 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2687 {
2688 uint32_t wt2;
2689
2690 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2691 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2692 restore_rounding_mode(env);
2693 if (get_float_exception_flags(&env->active_fpu.fp_status)
2694 & (float_flag_invalid | float_flag_overflow)) {
2695 wt2 = FP_TO_INT32_OVERFLOW;
2696 }
2697 update_fcr31(env, GETPC());
2698 return wt2;
2699 }
2700
2701 /* unary operations, not modifying fp status */
2702 #define FLOAT_UNOP(name) \
2703 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2704 { \
2705 return float64_ ## name(fdt0); \
2706 } \
2707 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2708 { \
2709 return float32_ ## name(fst0); \
2710 } \
2711 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2712 { \
2713 uint32_t wt0; \
2714 uint32_t wth0; \
2715 \
2716 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2717 wth0 = float32_ ## name(fdt0 >> 32); \
2718 return ((uint64_t)wth0 << 32) | wt0; \
2719 }
2720 FLOAT_UNOP(abs)
2721 FLOAT_UNOP(chs)
2722 #undef FLOAT_UNOP
2723
2724 /* MIPS specific unary operations */
2725 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2726 {
2727 uint64_t fdt2;
2728
2729 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2730 update_fcr31(env, GETPC());
2731 return fdt2;
2732 }
2733
2734 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2735 {
2736 uint32_t fst2;
2737
2738 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2739 update_fcr31(env, GETPC());
2740 return fst2;
2741 }
2742
2743 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2744 {
2745 uint64_t fdt2;
2746
2747 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2748 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2749 update_fcr31(env, GETPC());
2750 return fdt2;
2751 }
2752
2753 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2754 {
2755 uint32_t fst2;
2756
2757 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2758 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2759 update_fcr31(env, GETPC());
2760 return fst2;
2761 }
2762
2763 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2764 {
2765 uint64_t fdt2;
2766
2767 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2768 update_fcr31(env, GETPC());
2769 return fdt2;
2770 }
2771
2772 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2773 {
2774 uint32_t fst2;
2775
2776 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2777 update_fcr31(env, GETPC());
2778 return fst2;
2779 }
2780
2781 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2782 {
2783 uint32_t fst2;
2784 uint32_t fsth2;
2785
2786 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2787 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2788 update_fcr31(env, GETPC());
2789 return ((uint64_t)fsth2 << 32) | fst2;
2790 }
2791
2792 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2793 {
2794 uint64_t fdt2;
2795
2796 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2797 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2798 update_fcr31(env, GETPC());
2799 return fdt2;
2800 }
2801
2802 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2803 {
2804 uint32_t fst2;
2805
2806 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2807 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2808 update_fcr31(env, GETPC());
2809 return fst2;
2810 }
2811
2812 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2813 {
2814 uint32_t fst2;
2815 uint32_t fsth2;
2816
2817 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2818 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2819 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2820 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2821 update_fcr31(env, GETPC());
2822 return ((uint64_t)fsth2 << 32) | fst2;
2823 }
2824
2825 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2826
2827 /* binary operations */
2828 #define FLOAT_BINOP(name) \
2829 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2830 uint64_t fdt0, uint64_t fdt1) \
2831 { \
2832 uint64_t dt2; \
2833 \
2834 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2835 update_fcr31(env, GETPC()); \
2836 return dt2; \
2837 } \
2838 \
2839 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2840 uint32_t fst0, uint32_t fst1) \
2841 { \
2842 uint32_t wt2; \
2843 \
2844 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2845 update_fcr31(env, GETPC()); \
2846 return wt2; \
2847 } \
2848 \
2849 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2850 uint64_t fdt0, \
2851 uint64_t fdt1) \
2852 { \
2853 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2854 uint32_t fsth0 = fdt0 >> 32; \
2855 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2856 uint32_t fsth1 = fdt1 >> 32; \
2857 uint32_t wt2; \
2858 uint32_t wth2; \
2859 \
2860 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2861 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2862 update_fcr31(env, GETPC()); \
2863 return ((uint64_t)wth2 << 32) | wt2; \
2864 }
2865
2866 FLOAT_BINOP(add)
2867 FLOAT_BINOP(sub)
2868 FLOAT_BINOP(mul)
2869 FLOAT_BINOP(div)
2870 #undef FLOAT_BINOP
2871
2872 /* FMA based operations */
2873 #define FLOAT_FMA(name, type) \
2874 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2875 uint64_t fdt0, uint64_t fdt1, \
2876 uint64_t fdt2) \
2877 { \
2878 fdt0 = float64_muladd(fdt0, fdt1, fdt2, type, \
2879 &env->active_fpu.fp_status); \
2880 update_fcr31(env, GETPC()); \
2881 return fdt0; \
2882 } \
2883 \
2884 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2885 uint32_t fst0, uint32_t fst1, \
2886 uint32_t fst2) \
2887 { \
2888 fst0 = float32_muladd(fst0, fst1, fst2, type, \
2889 &env->active_fpu.fp_status); \
2890 update_fcr31(env, GETPC()); \
2891 return fst0; \
2892 } \
2893 \
2894 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2895 uint64_t fdt0, uint64_t fdt1, \
2896 uint64_t fdt2) \
2897 { \
2898 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2899 uint32_t fsth0 = fdt0 >> 32; \
2900 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2901 uint32_t fsth1 = fdt1 >> 32; \
2902 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2903 uint32_t fsth2 = fdt2 >> 32; \
2904 \
2905 fst0 = float32_muladd(fst0, fst1, fst2, type, \
2906 &env->active_fpu.fp_status); \
2907 fsth0 = float32_muladd(fsth0, fsth1, fsth2, type, \
2908 &env->active_fpu.fp_status); \
2909 update_fcr31(env, GETPC()); \
2910 return ((uint64_t)fsth0 << 32) | fst0; \
2911 }
2912 FLOAT_FMA(madd, 0)
2913 FLOAT_FMA(msub, float_muladd_negate_c)
2914 FLOAT_FMA(nmadd, float_muladd_negate_result)
2915 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2916 #undef FLOAT_FMA
2917
2918 /* MIPS specific binary operations */
2919 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2920 {
2921 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2922 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2923 update_fcr31(env, GETPC());
2924 return fdt2;
2925 }
2926
2927 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2928 {
2929 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2930 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2931 update_fcr31(env, GETPC());
2932 return fst2;
2933 }
2934
2935 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2936 {
2937 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2938 uint32_t fsth0 = fdt0 >> 32;
2939 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2940 uint32_t fsth2 = fdt2 >> 32;
2941
2942 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2943 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2944 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2945 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
2946 update_fcr31(env, GETPC());
2947 return ((uint64_t)fsth2 << 32) | fst2;
2948 }
2949
2950 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2951 {
2952 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2953 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
2954 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2955 update_fcr31(env, GETPC());
2956 return fdt2;
2957 }
2958
2959 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2960 {
2961 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2962 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
2963 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2964 update_fcr31(env, GETPC());
2965 return fst2;
2966 }
2967
2968 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2969 {
2970 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2971 uint32_t fsth0 = fdt0 >> 32;
2972 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2973 uint32_t fsth2 = fdt2 >> 32;
2974
2975 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2976 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2977 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
2978 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
2979 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2980 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2981 update_fcr31(env, GETPC());
2982 return ((uint64_t)fsth2 << 32) | fst2;
2983 }
2984
2985 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
2986 {
2987 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2988 uint32_t fsth0 = fdt0 >> 32;
2989 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2990 uint32_t fsth1 = fdt1 >> 32;
2991 uint32_t fst2;
2992 uint32_t fsth2;
2993
2994 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2995 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
2996 update_fcr31(env, GETPC());
2997 return ((uint64_t)fsth2 << 32) | fst2;
2998 }
2999
3000 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3001 {
3002 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3003 uint32_t fsth0 = fdt0 >> 32;
3004 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3005 uint32_t fsth1 = fdt1 >> 32;
3006 uint32_t fst2;
3007 uint32_t fsth2;
3008
3009 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3010 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3011 update_fcr31(env, GETPC());
3012 return ((uint64_t)fsth2 << 32) | fst2;
3013 }
3014
3015 /* compare operations */
3016 #define FOP_COND_D(op, cond) \
3017 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3018 uint64_t fdt1, int cc) \
3019 { \
3020 int c; \
3021 c = cond; \
3022 update_fcr31(env, GETPC()); \
3023 if (c) \
3024 SET_FP_COND(cc, env->active_fpu); \
3025 else \
3026 CLEAR_FP_COND(cc, env->active_fpu); \
3027 } \
3028 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3029 uint64_t fdt1, int cc) \
3030 { \
3031 int c; \
3032 fdt0 = float64_abs(fdt0); \
3033 fdt1 = float64_abs(fdt1); \
3034 c = cond; \
3035 update_fcr31(env, GETPC()); \
3036 if (c) \
3037 SET_FP_COND(cc, env->active_fpu); \
3038 else \
3039 CLEAR_FP_COND(cc, env->active_fpu); \
3040 }
3041
3042 /* NOTE: the comma operator will make "cond" to eval to false,
3043 * but float64_unordered_quiet() is still called. */
3044 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3045 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3046 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3047 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3048 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3049 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3050 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3051 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3052 /* NOTE: the comma operator will make "cond" to eval to false,
3053 * but float64_unordered() is still called. */
3054 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3055 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3056 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3057 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3058 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3059 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3060 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3061 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3062
3063 #define FOP_COND_S(op, cond) \
3064 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3065 uint32_t fst1, int cc) \
3066 { \
3067 int c; \
3068 c = cond; \
3069 update_fcr31(env, GETPC()); \
3070 if (c) \
3071 SET_FP_COND(cc, env->active_fpu); \
3072 else \
3073 CLEAR_FP_COND(cc, env->active_fpu); \
3074 } \
3075 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3076 uint32_t fst1, int cc) \
3077 { \
3078 int c; \
3079 fst0 = float32_abs(fst0); \
3080 fst1 = float32_abs(fst1); \
3081 c = cond; \
3082 update_fcr31(env, GETPC()); \
3083 if (c) \
3084 SET_FP_COND(cc, env->active_fpu); \
3085 else \
3086 CLEAR_FP_COND(cc, env->active_fpu); \
3087 }
3088
3089 /* NOTE: the comma operator will make "cond" to eval to false,
3090 * but float32_unordered_quiet() is still called. */
3091 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3092 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3093 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3094 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3095 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3096 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3097 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3098 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3099 /* NOTE: the comma operator will make "cond" to eval to false,
3100 * but float32_unordered() is still called. */
3101 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3102 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3103 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3104 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3105 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3106 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3107 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
3108 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3109
3110 #define FOP_COND_PS(op, condl, condh) \
3111 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3112 uint64_t fdt1, int cc) \
3113 { \
3114 uint32_t fst0, fsth0, fst1, fsth1; \
3115 int ch, cl; \
3116 fst0 = fdt0 & 0XFFFFFFFF; \
3117 fsth0 = fdt0 >> 32; \
3118 fst1 = fdt1 & 0XFFFFFFFF; \
3119 fsth1 = fdt1 >> 32; \
3120 cl = condl; \
3121 ch = condh; \
3122 update_fcr31(env, GETPC()); \
3123 if (cl) \
3124 SET_FP_COND(cc, env->active_fpu); \
3125 else \
3126 CLEAR_FP_COND(cc, env->active_fpu); \
3127 if (ch) \
3128 SET_FP_COND(cc + 1, env->active_fpu); \
3129 else \
3130 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3131 } \
3132 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3133 uint64_t fdt1, int cc) \
3134 { \
3135 uint32_t fst0, fsth0, fst1, fsth1; \
3136 int ch, cl; \
3137 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3138 fsth0 = float32_abs(fdt0 >> 32); \
3139 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3140 fsth1 = float32_abs(fdt1 >> 32); \
3141 cl = condl; \
3142 ch = condh; \
3143 update_fcr31(env, GETPC()); \
3144 if (cl) \
3145 SET_FP_COND(cc, env->active_fpu); \
3146 else \
3147 CLEAR_FP_COND(cc, env->active_fpu); \
3148 if (ch) \
3149 SET_FP_COND(cc + 1, env->active_fpu); \
3150 else \
3151 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3152 }
3153
3154 /* NOTE: the comma operator will make "cond" to eval to false,
3155 * but float32_unordered_quiet() is still called. */
3156 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3157 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3158 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3159 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3160 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3161 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3162 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3163 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3164 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3165 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3166 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3167 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3168 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3169 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3170 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3171 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3172 /* NOTE: the comma operator will make "cond" to eval to false,
3173 * but float32_unordered() is still called. */
3174 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3175 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3176 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3177 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3178 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3179 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3180 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3181 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3182 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3183 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3184 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3185 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3186 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
3187 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3188 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3189 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
Qemu copy for testing