target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "host-utils.h"
  22
  23 #include "helper.h"
  24
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "softmmu_exec.h"
  27 #endif /* !defined(CONFIG_USER_ONLY) */
  28
  29 #ifndef CONFIG_USER_ONLY
  30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  31 #endif
  32
  33 /*****************************************************************************/
  34 /* Exceptions processing helpers */
  35
  36 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  37                                                         uint32_t exception,
  38                                                         int error_code,
  39                                                         uintptr_t pc)
  40 {
  41     TranslationBlock *tb;
  42 #if 1
  43     if (exception < 0x100)
  44         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  45 #endif
  46     env->exception_index = exception;
  47     env->error_code = error_code;
  48
  49     if (pc) {
  50         /* now we have a real cpu fault */
  51         tb = tb_find_pc(pc);
  52         if (tb) {
  53             /* the PC is inside the translated code. It means that we have
  54                a virtual CPU fault */
  55             cpu_restore_state(tb, env, pc);
  56         }
  57     }
  58
  59     cpu_loop_exit(env);
  60 }
  61
  62 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  63                                                     uint32_t exception,
  64                                                     uintptr_t pc)
  65 {
  66     do_raise_exception_err(env, exception, 0, pc);
  67 }
  68
  69 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  70                                 int error_code)
  71 {
  72     do_raise_exception_err(env, exception, error_code, 0);
  73 }
  74
  75 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  76 {
  77     do_raise_exception(env, exception, 0);
  78 }
  79
  80 #if defined(CONFIG_USER_ONLY)
  81 #define HELPER_LD(name, insn, type)                                     \
  82 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  83                              int mem_idx)                               \
  84 {                                                                       \
  85     return (type) insn##_raw(addr);                                     \
  86 }
  87 #else
  88 #define HELPER_LD(name, insn, type)                                     \
  89 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  90                              int mem_idx)                               \
  91 {                                                                       \
  92     switch (mem_idx)                                                    \
  93     {                                                                   \
  94     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  95     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  96     default:                                                            \
  97     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  98     }                                                                   \
  99 }
 100 #endif
 101 HELPER_LD(lbu, ldub, uint8_t)
 102 HELPER_LD(lw, ldl, int32_t)
 103 #ifdef TARGET_MIPS64
 104 HELPER_LD(ld, ldq, int64_t)
 105 #endif
 106 #undef HELPER_LD
 107
 108 #if defined(CONFIG_USER_ONLY)
 109 #define HELPER_ST(name, insn, type)                                     \
 110 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 111                              type val, int mem_idx)                     \
 112 {                                                                       \
 113     insn##_raw(addr, val);                                              \
 114 }
 115 #else
 116 #define HELPER_ST(name, insn, type)                                     \
 117 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 118                              type val, int mem_idx)                     \
 119 {                                                                       \
 120     switch (mem_idx)                                                    \
 121     {                                                                   \
 122     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 123     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 124     default:                                                            \
 125     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 126     }                                                                   \
 127 }
 128 #endif
 129 HELPER_ST(sb, stb, uint8_t)
 130 HELPER_ST(sw, stl, uint32_t)
 131 #ifdef TARGET_MIPS64
 132 HELPER_ST(sd, stq, uint64_t)
 133 #endif
 134 #undef HELPER_ST
 135
 136 target_ulong helper_clo (target_ulong arg1)
 137 {
 138     return clo32(arg1);
 139 }
 140
 141 target_ulong helper_clz (target_ulong arg1)
 142 {
 143     return clz32(arg1);
 144 }
 145
 146 #if defined(TARGET_MIPS64)
 147 target_ulong helper_dclo (target_ulong arg1)
 148 {
 149     return clo64(arg1);
 150 }
 151
 152 target_ulong helper_dclz (target_ulong arg1)
 153 {
 154     return clz64(arg1);
 155 }
 156 #endif /* TARGET_MIPS64 */
 157
 158 /* 64 bits arithmetic for 32 bits hosts */
 159 static inline uint64_t get_HILO(CPUMIPSState *env)
 160 {
 161     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 162 }
 163
 164 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 165 {
 166     target_ulong tmp;
 167     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 168     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 169     return tmp;
 170 }
 171
 172 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 173 {
 174     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 175     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 176     return tmp;
 177 }
 178
 179 /* Multiplication variants of the vr54xx. */
 180 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 181                          target_ulong arg2)
 182 {
 183     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 184                                  (int64_t)(int32_t)arg2));
 185 }
 186
 187 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 188                           target_ulong arg2)
 189 {
 190     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 191                        (uint64_t)(uint32_t)arg2);
 192 }
 193
 194 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 195                          target_ulong arg2)
 196 {
 197     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 198                        (int64_t)(int32_t)arg2);
 199 }
 200
 201 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 202                            target_ulong arg2)
 203 {
 204     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 205                        (int64_t)(int32_t)arg2);
 206 }
 207
 208 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 209                           target_ulong arg2)
 210 {
 211     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 212                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 213 }
 214
 215 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 216                             target_ulong arg2)
 217 {
 218     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 219                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 220 }
 221
 222 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 223                          target_ulong arg2)
 224 {
 225     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 226                        (int64_t)(int32_t)arg2);
 227 }
 228
 229 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 230                            target_ulong arg2)
 231 {
 232     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 233                        (int64_t)(int32_t)arg2);
 234 }
 235
 236 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 237                           target_ulong arg2)
 238 {
 239     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 240                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 241 }
 242
 243 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 244                             target_ulong arg2)
 245 {
 246     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 247                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 248 }
 249
 250 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 251                           target_ulong arg2)
 252 {
 253     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 254 }
 255
 256 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 257                            target_ulong arg2)
 258 {
 259     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 260                        (uint64_t)(uint32_t)arg2);
 261 }
 262
 263 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 264                            target_ulong arg2)
 265 {
 266     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 267                        (int64_t)(int32_t)arg2);
 268 }
 269
 270 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 271                             target_ulong arg2)
 272 {
 273     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 274                        (uint64_t)(uint32_t)arg2);
 275 }
 276
 277 #ifdef TARGET_MIPS64
 278 void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
 279 {
 280     muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 281 }
 282
 283 void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
 284 {
 285     mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 286 }
 287 #endif
 288
 289 #ifndef CONFIG_USER_ONLY
 290
 291 static inline hwaddr do_translate_address(CPUMIPSState *env,
 292                                                       target_ulong address,
 293                                                       int rw)
 294 {
 295     hwaddr lladdr;
 296
 297     lladdr = cpu_mips_translate_address(env, address, rw);
 298
 299     if (lladdr == -1LL) {
 300         cpu_loop_exit(env);
 301     } else {
 302         return lladdr;
 303     }
 304 }
 305
 306 #define HELPER_LD_ATOMIC(name, insn)                                          \
 307 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 308 {                                                                             \
 309     env->lladdr = do_translate_address(env, arg, 0);                          \
 310     env->llval = do_##insn(env, arg, mem_idx);                                \
 311     return env->llval;                                                        \
 312 }
 313 HELPER_LD_ATOMIC(ll, lw)
 314 #ifdef TARGET_MIPS64
 315 HELPER_LD_ATOMIC(lld, ld)
 316 #endif
 317 #undef HELPER_LD_ATOMIC
 318
 319 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 320 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 321                            target_ulong arg2, int mem_idx)                    \
 322 {                                                                             \
 323     target_long tmp;                                                          \
 324                                                                               \
 325     if (arg2 & almask) {                                                      \
 326         env->CP0_BadVAddr = arg2;                                             \
 327         helper_raise_exception(env, EXCP_AdES);                               \
 328     }                                                                         \
 329     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 330         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 331         if (tmp == env->llval) {                                              \
 332             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 333             return 1;                                                         \
 334         }                                                                     \
 335     }                                                                         \
 336     return 0;                                                                 \
 337 }
 338 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 339 #ifdef TARGET_MIPS64
 340 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 341 #endif
 342 #undef HELPER_ST_ATOMIC
 343 #endif
 344
 345 #ifdef TARGET_WORDS_BIGENDIAN
 346 #define GET_LMASK(v) ((v) & 3)
 347 #define GET_OFFSET(addr, offset) (addr + (offset))
 348 #else
 349 #define GET_LMASK(v) (((v) & 3) ^ 3)
 350 #define GET_OFFSET(addr, offset) (addr - (offset))
 351 #endif
 352
 353 target_ulong helper_lwl(CPUMIPSState *env, target_ulong arg1,
 354                         target_ulong arg2, int mem_idx)
 355 {
 356     target_ulong tmp;
 357
 358     tmp = do_lbu(env, arg2, mem_idx);
 359     arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
 360
 361     if (GET_LMASK(arg2) <= 2) {
 362         tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx);
 363         arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
 364     }
 365
 366     if (GET_LMASK(arg2) <= 1) {
 367         tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx);
 368         arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
 369     }
 370
 371     if (GET_LMASK(arg2) == 0) {
 372         tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx);
 373         arg1 = (arg1 & 0xFFFFFF00) | tmp;
 374     }
 375     return (int32_t)arg1;
 376 }
 377
 378 target_ulong helper_lwr(CPUMIPSState *env, target_ulong arg1,
 379                         target_ulong arg2, int mem_idx)
 380 {
 381     target_ulong tmp;
 382
 383     tmp = do_lbu(env, arg2, mem_idx);
 384     arg1 = (arg1 & 0xFFFFFF00) | tmp;
 385
 386     if (GET_LMASK(arg2) >= 1) {
 387         tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx);
 388         arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
 389     }
 390
 391     if (GET_LMASK(arg2) >= 2) {
 392         tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx);
 393         arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
 394     }
 395
 396     if (GET_LMASK(arg2) == 3) {
 397         tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx);
 398         arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
 399     }
 400     return (int32_t)arg1;
 401 }
 402
 403 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 404                 int mem_idx)
 405 {
 406     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 407
 408     if (GET_LMASK(arg2) <= 2)
 409         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 410
 411     if (GET_LMASK(arg2) <= 1)
 412         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 413
 414     if (GET_LMASK(arg2) == 0)
 415         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 416 }
 417
 418 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 419                 int mem_idx)
 420 {
 421     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 422
 423     if (GET_LMASK(arg2) >= 1)
 424         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 425
 426     if (GET_LMASK(arg2) >= 2)
 427         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 428
 429     if (GET_LMASK(arg2) == 3)
 430         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 431 }
 432
 433 #if defined(TARGET_MIPS64)
 434 /* "half" load and stores.  We must do the memory access inline,
 435    or fault handling won't work.  */
 436
 437 #ifdef TARGET_WORDS_BIGENDIAN
 438 #define GET_LMASK64(v) ((v) & 7)
 439 #else
 440 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 441 #endif
 442
 443 target_ulong helper_ldl(CPUMIPSState *env, target_ulong arg1,
 444                         target_ulong arg2, int mem_idx)
 445 {
 446     uint64_t tmp;
 447
 448     tmp = do_lbu(env, arg2, mem_idx);
 449     arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
 450
 451     if (GET_LMASK64(arg2) <= 6) {
 452         tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx);
 453         arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
 454     }
 455
 456     if (GET_LMASK64(arg2) <= 5) {
 457         tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx);
 458         arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
 459     }
 460
 461     if (GET_LMASK64(arg2) <= 4) {
 462         tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx);
 463         arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
 464     }
 465
 466     if (GET_LMASK64(arg2) <= 3) {
 467         tmp = do_lbu(env, GET_OFFSET(arg2, 4), mem_idx);
 468         arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
 469     }
 470
 471     if (GET_LMASK64(arg2) <= 2) {
 472         tmp = do_lbu(env, GET_OFFSET(arg2, 5), mem_idx);
 473         arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
 474     }
 475
 476     if (GET_LMASK64(arg2) <= 1) {
 477         tmp = do_lbu(env, GET_OFFSET(arg2, 6), mem_idx);
 478         arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
 479     }
 480
 481     if (GET_LMASK64(arg2) == 0) {
 482         tmp = do_lbu(env, GET_OFFSET(arg2, 7), mem_idx);
 483         arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
 484     }
 485
 486     return arg1;
 487 }
 488
 489 target_ulong helper_ldr(CPUMIPSState *env, target_ulong arg1,
 490                         target_ulong arg2, int mem_idx)
 491 {
 492     uint64_t tmp;
 493
 494     tmp = do_lbu(env, arg2, mem_idx);
 495     arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
 496
 497     if (GET_LMASK64(arg2) >= 1) {
 498         tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx);
 499         arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp  << 8);
 500     }
 501
 502     if (GET_LMASK64(arg2) >= 2) {
 503         tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx);
 504         arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
 505     }
 506
 507     if (GET_LMASK64(arg2) >= 3) {
 508         tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx);
 509         arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
 510     }
 511
 512     if (GET_LMASK64(arg2) >= 4) {
 513         tmp = do_lbu(env, GET_OFFSET(arg2, -4), mem_idx);
 514         arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
 515     }
 516
 517     if (GET_LMASK64(arg2) >= 5) {
 518         tmp = do_lbu(env, GET_OFFSET(arg2, -5), mem_idx);
 519         arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
 520     }
 521
 522     if (GET_LMASK64(arg2) >= 6) {
 523         tmp = do_lbu(env, GET_OFFSET(arg2, -6), mem_idx);
 524         arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
 525     }
 526
 527     if (GET_LMASK64(arg2) == 7) {
 528         tmp = do_lbu(env, GET_OFFSET(arg2, -7), mem_idx);
 529         arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
 530     }
 531
 532     return arg1;
 533 }
 534
 535 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 536                 int mem_idx)
 537 {
 538     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 539
 540     if (GET_LMASK64(arg2) <= 6)
 541         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 542
 543     if (GET_LMASK64(arg2) <= 5)
 544         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 545
 546     if (GET_LMASK64(arg2) <= 4)
 547         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 548
 549     if (GET_LMASK64(arg2) <= 3)
 550         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 551
 552     if (GET_LMASK64(arg2) <= 2)
 553         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 554
 555     if (GET_LMASK64(arg2) <= 1)
 556         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 557
 558     if (GET_LMASK64(arg2) <= 0)
 559         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 560 }
 561
 562 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 563                 int mem_idx)
 564 {
 565     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 566
 567     if (GET_LMASK64(arg2) >= 1)
 568         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 569
 570     if (GET_LMASK64(arg2) >= 2)
 571         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 572
 573     if (GET_LMASK64(arg2) >= 3)
 574         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 575
 576     if (GET_LMASK64(arg2) >= 4)
 577         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 578
 579     if (GET_LMASK64(arg2) >= 5)
 580         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 581
 582     if (GET_LMASK64(arg2) >= 6)
 583         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 584
 585     if (GET_LMASK64(arg2) == 7)
 586         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 587 }
 588 #endif /* TARGET_MIPS64 */
 589
 590 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 591
 592 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 593                 uint32_t mem_idx)
 594 {
 595     target_ulong base_reglist = reglist & 0xf;
 596     target_ulong do_r31 = reglist & 0x10;
 597
 598     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 599         target_ulong i;
 600
 601         for (i = 0; i < base_reglist; i++) {
 602             env->active_tc.gpr[multiple_regs[i]] =
 603                 (target_long)do_lw(env, addr, mem_idx);
 604             addr += 4;
 605         }
 606     }
 607
 608     if (do_r31) {
 609         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 610     }
 611 }
 612
 613 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 614                 uint32_t mem_idx)
 615 {
 616     target_ulong base_reglist = reglist & 0xf;
 617     target_ulong do_r31 = reglist & 0x10;
 618
 619     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 620         target_ulong i;
 621
 622         for (i = 0; i < base_reglist; i++) {
 623             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 624             addr += 4;
 625         }
 626     }
 627
 628     if (do_r31) {
 629         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 630     }
 631 }
 632
 633 #if defined(TARGET_MIPS64)
 634 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 635                 uint32_t mem_idx)
 636 {
 637     target_ulong base_reglist = reglist & 0xf;
 638     target_ulong do_r31 = reglist & 0x10;
 639
 640     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 641         target_ulong i;
 642
 643         for (i = 0; i < base_reglist; i++) {
 644             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 645             addr += 8;
 646         }
 647     }
 648
 649     if (do_r31) {
 650         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 651     }
 652 }
 653
 654 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 655                 uint32_t mem_idx)
 656 {
 657     target_ulong base_reglist = reglist & 0xf;
 658     target_ulong do_r31 = reglist & 0x10;
 659
 660     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 661         target_ulong i;
 662
 663         for (i = 0; i < base_reglist; i++) {
 664             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 665             addr += 8;
 666         }
 667     }
 668
 669     if (do_r31) {
 670         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 671     }
 672 }
 673 #endif
 674
 675 #ifndef CONFIG_USER_ONLY
 676 /* SMP helpers.  */
 677 static bool mips_vpe_is_wfi(MIPSCPU *c)
 678 {
 679     CPUMIPSState *env = &c->env;
 680
 681     /* If the VPE is halted but otherwise active, it means it's waiting for
 682        an interrupt.  */
 683     return env->halted && mips_vpe_active(env);
 684 }
 685
 686 static inline void mips_vpe_wake(CPUMIPSState *c)
 687 {
 688     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 689        because there might be other conditions that state that c should
 690        be sleeping.  */
 691     cpu_interrupt(c, CPU_INTERRUPT_WAKE);
 692 }
 693
 694 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 695 {
 696     CPUMIPSState *c = &cpu->env;
 697
 698     /* The VPE was shut off, really go to bed.
 699        Reset any old _WAKE requests.  */
 700     c->halted = 1;
 701     cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
 702 }
 703
 704 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 705 {
 706     CPUMIPSState *c = &cpu->env;
 707
 708     /* FIXME: TC reschedule.  */
 709     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 710         mips_vpe_wake(c);
 711     }
 712 }
 713
 714 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 715 {
 716     CPUMIPSState *c = &cpu->env;
 717
 718     /* FIXME: TC reschedule.  */
 719     if (!mips_vpe_active(c)) {
 720         mips_vpe_sleep(cpu);
 721     }
 722 }
 723
 724 /* tc should point to an int with the value of the global TC index.
 725    This function will transform it into a local index within the
 726    returned CPUMIPSState.
 727
 728    FIXME: This code assumes that all VPEs have the same number of TCs,
 729           which depends on runtime setup. Can probably be fixed by
 730           walking the list of CPUMIPSStates.  */
 731 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 732 {
 733     CPUMIPSState *other;
 734     int vpe_idx, nr_threads = env->nr_threads;
 735     int tc_idx = *tc;
 736
 737     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 738         /* Not allowed to address other CPUs.  */
 739         *tc = env->current_tc;
 740         return env;
 741     }
 742
 743     vpe_idx = tc_idx / nr_threads;
 744     *tc = tc_idx % nr_threads;
 745     other = qemu_get_cpu(vpe_idx);
 746     return other ? other : env;
 747 }
 748
 749 /* The per VPE CP0_Status register shares some fields with the per TC
 750    CP0_TCStatus registers. These fields are wired to the same registers,
 751    so changes to either of them should be reflected on both registers.
 752
 753    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 754
 755    These helper call synchronizes the regs for a given cpu.  */
 756
 757 /* Called for updates to CP0_Status.  */
 758 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 759 {
 760     int32_t tcstatus, *tcst;
 761     uint32_t v = cpu->CP0_Status;
 762     uint32_t cu, mx, asid, ksu;
 763     uint32_t mask = ((1 << CP0TCSt_TCU3)
 764                        | (1 << CP0TCSt_TCU2)
 765                        | (1 << CP0TCSt_TCU1)
 766                        | (1 << CP0TCSt_TCU0)
 767                        | (1 << CP0TCSt_TMX)
 768                        | (3 << CP0TCSt_TKSU)
 769                        | (0xff << CP0TCSt_TASID));
 770
 771     cu = (v >> CP0St_CU0) & 0xf;
 772     mx = (v >> CP0St_MX) & 0x1;
 773     ksu = (v >> CP0St_KSU) & 0x3;
 774     asid = env->CP0_EntryHi & 0xff;
 775
 776     tcstatus = cu << CP0TCSt_TCU0;
 777     tcstatus |= mx << CP0TCSt_TMX;
 778     tcstatus |= ksu << CP0TCSt_TKSU;
 779     tcstatus |= asid;
 780
 781     if (tc == cpu->current_tc) {
 782         tcst = &cpu->active_tc.CP0_TCStatus;
 783     } else {
 784         tcst = &cpu->tcs[tc].CP0_TCStatus;
 785     }
 786
 787     *tcst &= ~mask;
 788     *tcst |= tcstatus;
 789     compute_hflags(cpu);
 790 }
 791
 792 /* Called for updates to CP0_TCStatus.  */
 793 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 794                              target_ulong v)
 795 {
 796     uint32_t status;
 797     uint32_t tcu, tmx, tasid, tksu;
 798     uint32_t mask = ((1 << CP0St_CU3)
 799                        | (1 << CP0St_CU2)
 800                        | (1 << CP0St_CU1)
 801                        | (1 << CP0St_CU0)
 802                        | (1 << CP0St_MX)
 803                        | (3 << CP0St_KSU));
 804
 805     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 806     tmx = (v >> CP0TCSt_TMX) & 0x1;
 807     tasid = v & 0xff;
 808     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 809
 810     status = tcu << CP0St_CU0;
 811     status |= tmx << CP0St_MX;
 812     status |= tksu << CP0St_KSU;
 813
 814     cpu->CP0_Status &= ~mask;
 815     cpu->CP0_Status |= status;
 816
 817     /* Sync the TASID with EntryHi.  */
 818     cpu->CP0_EntryHi &= ~0xff;
 819     cpu->CP0_EntryHi = tasid;
 820
 821     compute_hflags(cpu);
 822 }
 823
 824 /* Called for updates to CP0_EntryHi.  */
 825 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 826 {
 827     int32_t *tcst;
 828     uint32_t asid, v = cpu->CP0_EntryHi;
 829
 830     asid = v & 0xff;
 831
 832     if (tc == cpu->current_tc) {
 833         tcst = &cpu->active_tc.CP0_TCStatus;
 834     } else {
 835         tcst = &cpu->tcs[tc].CP0_TCStatus;
 836     }
 837
 838     *tcst &= ~0xff;
 839     *tcst |= asid;
 840 }
 841
 842 /* CP0 helpers */
 843 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 844 {
 845     return env->mvp->CP0_MVPControl;
 846 }
 847
 848 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 849 {
 850     return env->mvp->CP0_MVPConf0;
 851 }
 852
 853 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 854 {
 855     return env->mvp->CP0_MVPConf1;
 856 }
 857
 858 target_ulong helper_mfc0_random(CPUMIPSState *env)
 859 {
 860     return (int32_t)cpu_mips_get_random(env);
 861 }
 862
 863 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 864 {
 865     return env->active_tc.CP0_TCStatus;
 866 }
 867
 868 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 869 {
 870     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 871     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 872
 873     if (other_tc == other->current_tc)
 874         return other->active_tc.CP0_TCStatus;
 875     else
 876         return other->tcs[other_tc].CP0_TCStatus;
 877 }
 878
 879 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 880 {
 881     return env->active_tc.CP0_TCBind;
 882 }
 883
 884 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 885 {
 886     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 887     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 888
 889     if (other_tc == other->current_tc)
 890         return other->active_tc.CP0_TCBind;
 891     else
 892         return other->tcs[other_tc].CP0_TCBind;
 893 }
 894
 895 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 896 {
 897     return env->active_tc.PC;
 898 }
 899
 900 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 901 {
 902     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 903     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 904
 905     if (other_tc == other->current_tc)
 906         return other->active_tc.PC;
 907     else
 908         return other->tcs[other_tc].PC;
 909 }
 910
 911 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 912 {
 913     return env->active_tc.CP0_TCHalt;
 914 }
 915
 916 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 917 {
 918     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 919     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 920
 921     if (other_tc == other->current_tc)
 922         return other->active_tc.CP0_TCHalt;
 923     else
 924         return other->tcs[other_tc].CP0_TCHalt;
 925 }
 926
 927 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 928 {
 929     return env->active_tc.CP0_TCContext;
 930 }
 931
 932 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 933 {
 934     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 935     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 936
 937     if (other_tc == other->current_tc)
 938         return other->active_tc.CP0_TCContext;
 939     else
 940         return other->tcs[other_tc].CP0_TCContext;
 941 }
 942
 943 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 944 {
 945     return env->active_tc.CP0_TCSchedule;
 946 }
 947
 948 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 949 {
 950     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 951     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 952
 953     if (other_tc == other->current_tc)
 954         return other->active_tc.CP0_TCSchedule;
 955     else
 956         return other->tcs[other_tc].CP0_TCSchedule;
 957 }
 958
 959 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 960 {
 961     return env->active_tc.CP0_TCScheFBack;
 962 }
 963
 964 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 965 {
 966     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 967     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 968
 969     if (other_tc == other->current_tc)
 970         return other->active_tc.CP0_TCScheFBack;
 971     else
 972         return other->tcs[other_tc].CP0_TCScheFBack;
 973 }
 974
 975 target_ulong helper_mfc0_count(CPUMIPSState *env)
 976 {
 977     return (int32_t)cpu_mips_get_count(env);
 978 }
 979
 980 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 981 {
 982     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 983     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 984
 985     return other->CP0_EntryHi;
 986 }
 987
 988 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 989 {
 990     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 991     int32_t tccause;
 992     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 993
 994     if (other_tc == other->current_tc) {
 995         tccause = other->CP0_Cause;
 996     } else {
 997         tccause = other->CP0_Cause;
 998     }
 999
1000     return tccause;
1001 }
1002
1003 target_ulong helper_mftc0_status(CPUMIPSState *env)
1004 {
1005     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1006     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1007
1008     return other->CP0_Status;
1009 }
1010
1011 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
1012 {
1013     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
1014 }
1015
1016 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
1017 {
1018     return (int32_t)env->CP0_WatchLo[sel];
1019 }
1020
1021 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
1022 {
1023     return env->CP0_WatchHi[sel];
1024 }
1025
1026 target_ulong helper_mfc0_debug(CPUMIPSState *env)
1027 {
1028     target_ulong t0 = env->CP0_Debug;
1029     if (env->hflags & MIPS_HFLAG_DM)
1030         t0 |= 1 << CP0DB_DM;
1031
1032     return t0;
1033 }
1034
1035 target_ulong helper_mftc0_debug(CPUMIPSState *env)
1036 {
1037     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1038     int32_t tcstatus;
1039     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1040
1041     if (other_tc == other->current_tc)
1042         tcstatus = other->active_tc.CP0_Debug_tcstatus;
1043     else
1044         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
1045
1046     /* XXX: Might be wrong, check with EJTAG spec. */
1047     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1048             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1049 }
1050
1051 #if defined(TARGET_MIPS64)
1052 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
1053 {
1054     return env->active_tc.PC;
1055 }
1056
1057 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
1058 {
1059     return env->active_tc.CP0_TCHalt;
1060 }
1061
1062 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
1063 {
1064     return env->active_tc.CP0_TCContext;
1065 }
1066
1067 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
1068 {
1069     return env->active_tc.CP0_TCSchedule;
1070 }
1071
1072 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
1073 {
1074     return env->active_tc.CP0_TCScheFBack;
1075 }
1076
1077 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
1078 {
1079     return env->lladdr >> env->CP0_LLAddr_shift;
1080 }
1081
1082 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
1083 {
1084     return env->CP0_WatchLo[sel];
1085 }
1086 #endif /* TARGET_MIPS64 */
1087
1088 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
1089 {
1090     int num = 1;
1091     unsigned int tmp = env->tlb->nb_tlb;
1092
1093     do {
1094         tmp >>= 1;
1095         num <<= 1;
1096     } while (tmp);
1097     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
1098 }
1099
1100 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
1101 {
1102     uint32_t mask = 0;
1103     uint32_t newval;
1104
1105     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
1106         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
1107                 (1 << CP0MVPCo_EVP);
1108     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1109         mask |= (1 << CP0MVPCo_STLB);
1110     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1111
1112     // TODO: Enable/disable shared TLB, enable/disable VPEs.
1113
1114     env->mvp->CP0_MVPControl = newval;
1115 }
1116
1117 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1118 {
1119     uint32_t mask;
1120     uint32_t newval;
1121
1122     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1123            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1124     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1125
1126     /* Yield scheduler intercept not implemented. */
1127     /* Gating storage scheduler intercept not implemented. */
1128
1129     // TODO: Enable/disable TCs.
1130
1131     env->CP0_VPEControl = newval;
1132 }
1133
1134 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1135 {
1136     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1137     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1138     uint32_t mask;
1139     uint32_t newval;
1140
1141     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1142            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1143     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1144
1145     /* TODO: Enable/disable TCs.  */
1146
1147     other->CP0_VPEControl = newval;
1148 }
1149
1150 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1151 {
1152     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1153     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1154     /* FIXME: Mask away return zero on read bits.  */
1155     return other->CP0_VPEControl;
1156 }
1157
1158 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1159 {
1160     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1161     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1162
1163     return other->CP0_VPEConf0;
1164 }
1165
1166 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1167 {
1168     uint32_t mask = 0;
1169     uint32_t newval;
1170
1171     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1172         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1173             mask |= (0xff << CP0VPEC0_XTC);
1174         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1175     }
1176     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1177
1178     // TODO: TC exclusive handling due to ERL/EXL.
1179
1180     env->CP0_VPEConf0 = newval;
1181 }
1182
1183 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1184 {
1185     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1186     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1187     uint32_t mask = 0;
1188     uint32_t newval;
1189
1190     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1191     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1192
1193     /* TODO: TC exclusive handling due to ERL/EXL.  */
1194     other->CP0_VPEConf0 = newval;
1195 }
1196
1197 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1198 {
1199     uint32_t mask = 0;
1200     uint32_t newval;
1201
1202     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1203         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1204                 (0xff << CP0VPEC1_NCP1);
1205     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1206
1207     /* UDI not implemented. */
1208     /* CP2 not implemented. */
1209
1210     // TODO: Handle FPU (CP1) binding.
1211
1212     env->CP0_VPEConf1 = newval;
1213 }
1214
1215 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1216 {
1217     /* Yield qualifier inputs not implemented. */
1218     env->CP0_YQMask = 0x00000000;
1219 }
1220
1221 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1222 {
1223     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1224 }
1225
1226 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1227 {
1228     /* Large physaddr (PABITS) not implemented */
1229     /* 1k pages not implemented */
1230     env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1231 }
1232
1233 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1234 {
1235     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1236     uint32_t newval;
1237
1238     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1239
1240     env->active_tc.CP0_TCStatus = newval;
1241     sync_c0_tcstatus(env, env->current_tc, newval);
1242 }
1243
1244 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1245 {
1246     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1247     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1248
1249     if (other_tc == other->current_tc)
1250         other->active_tc.CP0_TCStatus = arg1;
1251     else
1252         other->tcs[other_tc].CP0_TCStatus = arg1;
1253     sync_c0_tcstatus(other, other_tc, arg1);
1254 }
1255
1256 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1257 {
1258     uint32_t mask = (1 << CP0TCBd_TBE);
1259     uint32_t newval;
1260
1261     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1262         mask |= (1 << CP0TCBd_CurVPE);
1263     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1264     env->active_tc.CP0_TCBind = newval;
1265 }
1266
1267 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1268 {
1269     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1270     uint32_t mask = (1 << CP0TCBd_TBE);
1271     uint32_t newval;
1272     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1273
1274     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1275         mask |= (1 << CP0TCBd_CurVPE);
1276     if (other_tc == other->current_tc) {
1277         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1278         other->active_tc.CP0_TCBind = newval;
1279     } else {
1280         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1281         other->tcs[other_tc].CP0_TCBind = newval;
1282     }
1283 }
1284
1285 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1286 {
1287     env->active_tc.PC = arg1;
1288     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1289     env->lladdr = 0ULL;
1290     /* MIPS16 not implemented. */
1291 }
1292
1293 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1294 {
1295     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1296     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1297
1298     if (other_tc == other->current_tc) {
1299         other->active_tc.PC = arg1;
1300         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1301         other->lladdr = 0ULL;
1302         /* MIPS16 not implemented. */
1303     } else {
1304         other->tcs[other_tc].PC = arg1;
1305         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1306         other->lladdr = 0ULL;
1307         /* MIPS16 not implemented. */
1308     }
1309 }
1310
1311 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1312 {
1313     MIPSCPU *cpu = mips_env_get_cpu(env);
1314
1315     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1316
1317     // TODO: Halt TC / Restart (if allocated+active) TC.
1318     if (env->active_tc.CP0_TCHalt & 1) {
1319         mips_tc_sleep(cpu, env->current_tc);
1320     } else {
1321         mips_tc_wake(cpu, env->current_tc);
1322     }
1323 }
1324
1325 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1326 {
1327     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1328     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1329     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1330
1331     // TODO: Halt TC / Restart (if allocated+active) TC.
1332
1333     if (other_tc == other->current_tc)
1334         other->active_tc.CP0_TCHalt = arg1;
1335     else
1336         other->tcs[other_tc].CP0_TCHalt = arg1;
1337
1338     if (arg1 & 1) {
1339         mips_tc_sleep(other_cpu, other_tc);
1340     } else {
1341         mips_tc_wake(other_cpu, other_tc);
1342     }
1343 }
1344
1345 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1346 {
1347     env->active_tc.CP0_TCContext = arg1;
1348 }
1349
1350 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1351 {
1352     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1353     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1354
1355     if (other_tc == other->current_tc)
1356         other->active_tc.CP0_TCContext = arg1;
1357     else
1358         other->tcs[other_tc].CP0_TCContext = arg1;
1359 }
1360
1361 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1362 {
1363     env->active_tc.CP0_TCSchedule = arg1;
1364 }
1365
1366 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1367 {
1368     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1369     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1370
1371     if (other_tc == other->current_tc)
1372         other->active_tc.CP0_TCSchedule = arg1;
1373     else
1374         other->tcs[other_tc].CP0_TCSchedule = arg1;
1375 }
1376
1377 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1378 {
1379     env->active_tc.CP0_TCScheFBack = arg1;
1380 }
1381
1382 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1383 {
1384     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1385     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1386
1387     if (other_tc == other->current_tc)
1388         other->active_tc.CP0_TCScheFBack = arg1;
1389     else
1390         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1391 }
1392
1393 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1394 {
1395     /* Large physaddr (PABITS) not implemented */
1396     /* 1k pages not implemented */
1397     env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1398 }
1399
1400 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1401 {
1402     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1403 }
1404
1405 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1406 {
1407     /* 1k pages not implemented */
1408     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1409 }
1410
1411 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1412 {
1413     /* SmartMIPS not implemented */
1414     /* Large physaddr (PABITS) not implemented */
1415     /* 1k pages not implemented */
1416     env->CP0_PageGrain = 0;
1417 }
1418
1419 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1420 {
1421     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1422 }
1423
1424 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1425 {
1426     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1427 }
1428
1429 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1430 {
1431     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1432 }
1433
1434 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1435 {
1436     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1437 }
1438
1439 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1440 {
1441     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1442 }
1443
1444 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1445 {
1446     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1447 }
1448
1449 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1450 {
1451     env->CP0_HWREna = arg1 & 0x0000000F;
1452 }
1453
1454 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1455 {
1456     cpu_mips_store_count(env, arg1);
1457 }
1458
1459 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1460 {
1461     target_ulong old, val;
1462
1463     /* 1k pages not implemented */
1464     val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1465 #if defined(TARGET_MIPS64)
1466     val &= env->SEGMask;
1467 #endif
1468     old = env->CP0_EntryHi;
1469     env->CP0_EntryHi = val;
1470     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1471         sync_c0_entryhi(env, env->current_tc);
1472     }
1473     /* If the ASID changes, flush qemu's TLB.  */
1474     if ((old & 0xFF) != (val & 0xFF))
1475         cpu_mips_tlb_flush(env, 1);
1476 }
1477
1478 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1479 {
1480     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1481     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1482
1483     other->CP0_EntryHi = arg1;
1484     sync_c0_entryhi(other, other_tc);
1485 }
1486
1487 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1488 {
1489     cpu_mips_store_compare(env, arg1);
1490 }
1491
1492 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1493 {
1494     uint32_t val, old;
1495     uint32_t mask = env->CP0_Status_rw_bitmask;
1496
1497     val = arg1 & mask;
1498     old = env->CP0_Status;
1499     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1500     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1501         sync_c0_status(env, env, env->current_tc);
1502     } else {
1503         compute_hflags(env);
1504     }
1505
1506     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1507         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1508                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1509                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1510                 env->CP0_Cause);
1511         switch (env->hflags & MIPS_HFLAG_KSU) {
1512         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1513         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1514         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1515         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1516         }
1517     }
1518 }
1519
1520 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1521 {
1522     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1523     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1524
1525     other->CP0_Status = arg1 & ~0xf1000018;
1526     sync_c0_status(env, other, other_tc);
1527 }
1528
1529 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1530 {
1531     /* vectored interrupts not implemented, no performance counters. */
1532     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1533 }
1534
1535 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1536 {
1537     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1538     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1539 }
1540
1541 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1542 {
1543     uint32_t mask = 0x00C00300;
1544     uint32_t old = cpu->CP0_Cause;
1545     int i;
1546
1547     if (cpu->insn_flags & ISA_MIPS32R2) {
1548         mask |= 1 << CP0Ca_DC;
1549     }
1550
1551     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1552
1553     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1554         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1555             cpu_mips_stop_count(cpu);
1556         } else {
1557             cpu_mips_start_count(cpu);
1558         }
1559     }
1560
1561     /* Set/reset software interrupts */
1562     for (i = 0 ; i < 2 ; i++) {
1563         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1564             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1565         }
1566     }
1567 }
1568
1569 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1570 {
1571     mtc0_cause(env, arg1);
1572 }
1573
1574 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1575 {
1576     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1577     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1578
1579     mtc0_cause(other, arg1);
1580 }
1581
1582 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1583 {
1584     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1585     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1586
1587     return other->CP0_EPC;
1588 }
1589
1590 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1591 {
1592     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1593     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1594
1595     return other->CP0_EBase;
1596 }
1597
1598 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1599 {
1600     /* vectored interrupts not implemented */
1601     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1602 }
1603
1604 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1605 {
1606     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1607     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1608     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1609 }
1610
1611 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1612 {
1613     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1614     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1615
1616     switch (idx) {
1617     case 0: return other->CP0_Config0;
1618     case 1: return other->CP0_Config1;
1619     case 2: return other->CP0_Config2;
1620     case 3: return other->CP0_Config3;
1621     /* 4 and 5 are reserved.  */
1622     case 6: return other->CP0_Config6;
1623     case 7: return other->CP0_Config7;
1624     default:
1625         break;
1626     }
1627     return 0;
1628 }
1629
1630 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1631 {
1632     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1633 }
1634
1635 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1636 {
1637     /* tertiary/secondary caches not implemented */
1638     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1639 }
1640
1641 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1642 {
1643     target_long mask = env->CP0_LLAddr_rw_bitmask;
1644     arg1 = arg1 << env->CP0_LLAddr_shift;
1645     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1646 }
1647
1648 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1649 {
1650     /* Watch exceptions for instructions, data loads, data stores
1651        not implemented. */
1652     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1653 }
1654
1655 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1656 {
1657     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1658     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1659 }
1660
1661 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1662 {
1663     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1664     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1665 }
1666
1667 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1668 {
1669     env->CP0_Framemask = arg1; /* XXX */
1670 }
1671
1672 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1673 {
1674     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1675     if (arg1 & (1 << CP0DB_DM))
1676         env->hflags |= MIPS_HFLAG_DM;
1677     else
1678         env->hflags &= ~MIPS_HFLAG_DM;
1679 }
1680
1681 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1682 {
1683     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1684     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1685     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1686
1687     /* XXX: Might be wrong, check with EJTAG spec. */
1688     if (other_tc == other->current_tc)
1689         other->active_tc.CP0_Debug_tcstatus = val;
1690     else
1691         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1692     other->CP0_Debug = (other->CP0_Debug &
1693                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1694                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1695 }
1696
1697 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1698 {
1699     env->CP0_Performance0 = arg1 & 0x000007ff;
1700 }
1701
1702 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1703 {
1704     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1705 }
1706
1707 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1708 {
1709     env->CP0_DataLo = arg1; /* XXX */
1710 }
1711
1712 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1713 {
1714     env->CP0_TagHi = arg1; /* XXX */
1715 }
1716
1717 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1718 {
1719     env->CP0_DataHi = arg1; /* XXX */
1720 }
1721
1722 /* MIPS MT functions */
1723 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1724 {
1725     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1726     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1727
1728     if (other_tc == other->current_tc)
1729         return other->active_tc.gpr[sel];
1730     else
1731         return other->tcs[other_tc].gpr[sel];
1732 }
1733
1734 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1735 {
1736     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1737     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1738
1739     if (other_tc == other->current_tc)
1740         return other->active_tc.LO[sel];
1741     else
1742         return other->tcs[other_tc].LO[sel];
1743 }
1744
1745 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1746 {
1747     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1748     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1749
1750     if (other_tc == other->current_tc)
1751         return other->active_tc.HI[sel];
1752     else
1753         return other->tcs[other_tc].HI[sel];
1754 }
1755
1756 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1757 {
1758     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1759     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1760
1761     if (other_tc == other->current_tc)
1762         return other->active_tc.ACX[sel];
1763     else
1764         return other->tcs[other_tc].ACX[sel];
1765 }
1766
1767 target_ulong helper_mftdsp(CPUMIPSState *env)
1768 {
1769     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1770     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1771
1772     if (other_tc == other->current_tc)
1773         return other->active_tc.DSPControl;
1774     else
1775         return other->tcs[other_tc].DSPControl;
1776 }
1777
1778 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1779 {
1780     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1781     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1782
1783     if (other_tc == other->current_tc)
1784         other->active_tc.gpr[sel] = arg1;
1785     else
1786         other->tcs[other_tc].gpr[sel] = arg1;
1787 }
1788
1789 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1790 {
1791     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1792     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1793
1794     if (other_tc == other->current_tc)
1795         other->active_tc.LO[sel] = arg1;
1796     else
1797         other->tcs[other_tc].LO[sel] = arg1;
1798 }
1799
1800 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1801 {
1802     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1803     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1804
1805     if (other_tc == other->current_tc)
1806         other->active_tc.HI[sel] = arg1;
1807     else
1808         other->tcs[other_tc].HI[sel] = arg1;
1809 }
1810
1811 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1812 {
1813     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1814     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1815
1816     if (other_tc == other->current_tc)
1817         other->active_tc.ACX[sel] = arg1;
1818     else
1819         other->tcs[other_tc].ACX[sel] = arg1;
1820 }
1821
1822 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1823 {
1824     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1825     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1826
1827     if (other_tc == other->current_tc)
1828         other->active_tc.DSPControl = arg1;
1829     else
1830         other->tcs[other_tc].DSPControl = arg1;
1831 }
1832
1833 /* MIPS MT functions */
1834 target_ulong helper_dmt(void)
1835 {
1836     // TODO
1837      return 0;
1838 }
1839
1840 target_ulong helper_emt(void)
1841 {
1842     // TODO
1843     return 0;
1844 }
1845
1846 target_ulong helper_dvpe(CPUMIPSState *env)
1847 {
1848     CPUMIPSState *other_cpu_env = first_cpu;
1849     target_ulong prev = env->mvp->CP0_MVPControl;
1850
1851     do {
1852         /* Turn off all VPEs except the one executing the dvpe.  */
1853         if (other_cpu_env != env) {
1854             MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1855
1856             other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1857             mips_vpe_sleep(other_cpu);
1858         }
1859         other_cpu_env = other_cpu_env->next_cpu;
1860     } while (other_cpu_env);
1861     return prev;
1862 }
1863
1864 target_ulong helper_evpe(CPUMIPSState *env)
1865 {
1866     CPUMIPSState *other_cpu_env = first_cpu;
1867     target_ulong prev = env->mvp->CP0_MVPControl;
1868
1869     do {
1870         MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1871
1872         if (other_cpu_env != env
1873             /* If the VPE is WFI, don't disturb its sleep.  */
1874             && !mips_vpe_is_wfi(other_cpu)) {
1875             /* Enable the VPE.  */
1876             other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1877             mips_vpe_wake(other_cpu_env); /* And wake it up.  */
1878         }
1879         other_cpu_env = other_cpu_env->next_cpu;
1880     } while (other_cpu_env);
1881     return prev;
1882 }
1883 #endif /* !CONFIG_USER_ONLY */
1884
1885 void helper_fork(target_ulong arg1, target_ulong arg2)
1886 {
1887     // arg1 = rt, arg2 = rs
1888     arg1 = 0;
1889     // TODO: store to TC register
1890 }
1891
1892 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1893 {
1894     target_long arg1 = arg;
1895
1896     if (arg1 < 0) {
1897         /* No scheduling policy implemented. */
1898         if (arg1 != -2) {
1899             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1900                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1901                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1902                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1903                 helper_raise_exception(env, EXCP_THREAD);
1904             }
1905         }
1906     } else if (arg1 == 0) {
1907         if (0 /* TODO: TC underflow */) {
1908             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1909             helper_raise_exception(env, EXCP_THREAD);
1910         } else {
1911             // TODO: Deallocate TC
1912         }
1913     } else if (arg1 > 0) {
1914         /* Yield qualifier inputs not implemented. */
1915         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1916         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1917         helper_raise_exception(env, EXCP_THREAD);
1918     }
1919     return env->CP0_YQMask;
1920 }
1921
1922 #ifndef CONFIG_USER_ONLY
1923 /* TLB management */
1924 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1925 {
1926     /* Flush qemu's TLB and discard all shadowed entries.  */
1927     tlb_flush (env, flush_global);
1928     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1929 }
1930
1931 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1932 {
1933     /* Discard entries from env->tlb[first] onwards.  */
1934     while (env->tlb->tlb_in_use > first) {
1935         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1936     }
1937 }
1938
1939 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1940 {
1941     r4k_tlb_t *tlb;
1942
1943     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1944     tlb = &env->tlb->mmu.r4k.tlb[idx];
1945     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1946 #if defined(TARGET_MIPS64)
1947     tlb->VPN &= env->SEGMask;
1948 #endif
1949     tlb->ASID = env->CP0_EntryHi & 0xFF;
1950     tlb->PageMask = env->CP0_PageMask;
1951     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1952     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1953     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1954     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1955     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1956     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1957     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1958     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1959     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1960 }
1961
1962 void r4k_helper_tlbwi(CPUMIPSState *env)
1963 {
1964     int idx;
1965
1966     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1967
1968     /* Discard cached TLB entries.  We could avoid doing this if the
1969        tlbwi is just upgrading access permissions on the current entry;
1970        that might be a further win.  */
1971     r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
1972
1973     r4k_invalidate_tlb(env, idx, 0);
1974     r4k_fill_tlb(env, idx);
1975 }
1976
1977 void r4k_helper_tlbwr(CPUMIPSState *env)
1978 {
1979     int r = cpu_mips_get_random(env);
1980
1981     r4k_invalidate_tlb(env, r, 1);
1982     r4k_fill_tlb(env, r);
1983 }
1984
1985 void r4k_helper_tlbp(CPUMIPSState *env)
1986 {
1987     r4k_tlb_t *tlb;
1988     target_ulong mask;
1989     target_ulong tag;
1990     target_ulong VPN;
1991     uint8_t ASID;
1992     int i;
1993
1994     ASID = env->CP0_EntryHi & 0xFF;
1995     for (i = 0; i < env->tlb->nb_tlb; i++) {
1996         tlb = &env->tlb->mmu.r4k.tlb[i];
1997         /* 1k pages are not supported. */
1998         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1999         tag = env->CP0_EntryHi & ~mask;
2000         VPN = tlb->VPN & ~mask;
2001         /* Check ASID, virtual page number & size */
2002         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2003             /* TLB match */
2004             env->CP0_Index = i;
2005             break;
2006         }
2007     }
2008     if (i == env->tlb->nb_tlb) {
2009         /* No match.  Discard any shadow entries, if any of them match.  */
2010         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2011             tlb = &env->tlb->mmu.r4k.tlb[i];
2012             /* 1k pages are not supported. */
2013             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2014             tag = env->CP0_EntryHi & ~mask;
2015             VPN = tlb->VPN & ~mask;
2016             /* Check ASID, virtual page number & size */
2017             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2018                 r4k_mips_tlb_flush_extra (env, i);
2019                 break;
2020             }
2021         }
2022
2023         env->CP0_Index |= 0x80000000;
2024     }
2025 }
2026
2027 void r4k_helper_tlbr(CPUMIPSState *env)
2028 {
2029     r4k_tlb_t *tlb;
2030     uint8_t ASID;
2031     int idx;
2032
2033     ASID = env->CP0_EntryHi & 0xFF;
2034     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2035     tlb = &env->tlb->mmu.r4k.tlb[idx];
2036
2037     /* If this will change the current ASID, flush qemu's TLB.  */
2038     if (ASID != tlb->ASID)
2039         cpu_mips_tlb_flush (env, 1);
2040
2041     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2042
2043     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2044     env->CP0_PageMask = tlb->PageMask;
2045     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2046                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
2047     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2048                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
2049 }
2050
2051 void helper_tlbwi(CPUMIPSState *env)
2052 {
2053     env->tlb->helper_tlbwi(env);
2054 }
2055
2056 void helper_tlbwr(CPUMIPSState *env)
2057 {
2058     env->tlb->helper_tlbwr(env);
2059 }
2060
2061 void helper_tlbp(CPUMIPSState *env)
2062 {
2063     env->tlb->helper_tlbp(env);
2064 }
2065
2066 void helper_tlbr(CPUMIPSState *env)
2067 {
2068     env->tlb->helper_tlbr(env);
2069 }
2070
2071 /* Specials */
2072 target_ulong helper_di(CPUMIPSState *env)
2073 {
2074     target_ulong t0 = env->CP0_Status;
2075
2076     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2077     return t0;
2078 }
2079
2080 target_ulong helper_ei(CPUMIPSState *env)
2081 {
2082     target_ulong t0 = env->CP0_Status;
2083
2084     env->CP0_Status = t0 | (1 << CP0St_IE);
2085     return t0;
2086 }
2087
2088 static void debug_pre_eret(CPUMIPSState *env)
2089 {
2090     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2091         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2092                 env->active_tc.PC, env->CP0_EPC);
2093         if (env->CP0_Status & (1 << CP0St_ERL))
2094             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2095         if (env->hflags & MIPS_HFLAG_DM)
2096             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2097         qemu_log("\n");
2098     }
2099 }
2100
2101 static void debug_post_eret(CPUMIPSState *env)
2102 {
2103     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2104         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2105                 env->active_tc.PC, env->CP0_EPC);
2106         if (env->CP0_Status & (1 << CP0St_ERL))
2107             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2108         if (env->hflags & MIPS_HFLAG_DM)
2109             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2110         switch (env->hflags & MIPS_HFLAG_KSU) {
2111         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2112         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2113         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2114         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
2115         }
2116     }
2117 }
2118
2119 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2120 {
2121     env->active_tc.PC = error_pc & ~(target_ulong)1;
2122     if (error_pc & 1) {
2123         env->hflags |= MIPS_HFLAG_M16;
2124     } else {
2125         env->hflags &= ~(MIPS_HFLAG_M16);
2126     }
2127 }
2128
2129 void helper_eret(CPUMIPSState *env)
2130 {
2131     debug_pre_eret(env);
2132     if (env->CP0_Status & (1 << CP0St_ERL)) {
2133         set_pc(env, env->CP0_ErrorEPC);
2134         env->CP0_Status &= ~(1 << CP0St_ERL);
2135     } else {
2136         set_pc(env, env->CP0_EPC);
2137         env->CP0_Status &= ~(1 << CP0St_EXL);
2138     }
2139     compute_hflags(env);
2140     debug_post_eret(env);
2141     env->lladdr = 1;
2142 }
2143
2144 void helper_deret(CPUMIPSState *env)
2145 {
2146     debug_pre_eret(env);
2147     set_pc(env, env->CP0_DEPC);
2148
2149     env->hflags &= MIPS_HFLAG_DM;
2150     compute_hflags(env);
2151     debug_post_eret(env);
2152     env->lladdr = 1;
2153 }
2154 #endif /* !CONFIG_USER_ONLY */
2155
2156 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2157 {
2158     if ((env->hflags & MIPS_HFLAG_CP0) ||
2159         (env->CP0_HWREna & (1 << 0)))
2160         return env->CP0_EBase & 0x3ff;
2161     else
2162         helper_raise_exception(env, EXCP_RI);
2163
2164     return 0;
2165 }
2166
2167 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2168 {
2169     if ((env->hflags & MIPS_HFLAG_CP0) ||
2170         (env->CP0_HWREna & (1 << 1)))
2171         return env->SYNCI_Step;
2172     else
2173         helper_raise_exception(env, EXCP_RI);
2174
2175     return 0;
2176 }
2177
2178 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2179 {
2180     if ((env->hflags & MIPS_HFLAG_CP0) ||
2181         (env->CP0_HWREna & (1 << 2)))
2182         return env->CP0_Count;
2183     else
2184         helper_raise_exception(env, EXCP_RI);
2185
2186     return 0;
2187 }
2188
2189 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2190 {
2191     if ((env->hflags & MIPS_HFLAG_CP0) ||
2192         (env->CP0_HWREna & (1 << 3)))
2193         return env->CCRes;
2194     else
2195         helper_raise_exception(env, EXCP_RI);
2196
2197     return 0;
2198 }
2199
2200 void helper_pmon(CPUMIPSState *env, int function)
2201 {
2202     function /= 2;
2203     switch (function) {
2204     case 2: /* TODO: char inbyte(int waitflag); */
2205         if (env->active_tc.gpr[4] == 0)
2206             env->active_tc.gpr[2] = -1;
2207         /* Fall through */
2208     case 11: /* TODO: char inbyte (void); */
2209         env->active_tc.gpr[2] = -1;
2210         break;
2211     case 3:
2212     case 12:
2213         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2214         break;
2215     case 17:
2216         break;
2217     case 158:
2218         {
2219             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2220             printf("%s", fmt);
2221         }
2222         break;
2223     }
2224 }
2225
2226 void helper_wait(CPUMIPSState *env)
2227 {
2228     env->halted = 1;
2229     cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE);
2230     helper_raise_exception(env, EXCP_HLT);
2231 }
2232
2233 #if !defined(CONFIG_USER_ONLY)
2234
2235 static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
2236                                               target_ulong addr, int is_write,
2237                                               int is_user, uintptr_t retaddr);
2238
2239 #define MMUSUFFIX _mmu
2240 #define ALIGNED_ONLY
2241
2242 #define SHIFT 0
2243 #include "softmmu_template.h"
2244
2245 #define SHIFT 1
2246 #include "softmmu_template.h"
2247
2248 #define SHIFT 2
2249 #include "softmmu_template.h"
2250
2251 #define SHIFT 3
2252 #include "softmmu_template.h"
2253
2254 static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
2255                                 int is_write, int is_user, uintptr_t retaddr)
2256 {
2257     env->CP0_BadVAddr = addr;
2258     do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2259 }
2260
2261 void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
2262               uintptr_t retaddr)
2263 {
2264     int ret;
2265
2266     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
2267     if (ret) {
2268         do_raise_exception_err(env, env->exception_index,
2269                                env->error_code, retaddr);
2270     }
2271 }
2272
2273 void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
2274                            int is_write, int is_exec, int unused, int size)
2275 {
2276     if (is_exec)
2277         helper_raise_exception(env, EXCP_IBE);
2278     else
2279         helper_raise_exception(env, EXCP_DBE);
2280 }
2281 #endif /* !CONFIG_USER_ONLY */
2282
2283 /* Complex FPU operations which may need stack space. */
2284
2285 #define FLOAT_TWO32 make_float32(1 << 30)
2286 #define FLOAT_TWO64 make_float64(1ULL << 62)
2287 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2288 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2289
2290 /* convert MIPS rounding mode in FCR31 to IEEE library */
2291 static unsigned int ieee_rm[] = {
2292     float_round_nearest_even,
2293     float_round_to_zero,
2294     float_round_up,
2295     float_round_down
2296 };
2297
2298 #define RESTORE_ROUNDING_MODE \
2299     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
2300
2301 #define RESTORE_FLUSH_MODE \
2302     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
2303
2304 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2305 {
2306     target_ulong arg1;
2307
2308     switch (reg) {
2309     case 0:
2310         arg1 = (int32_t)env->active_fpu.fcr0;
2311         break;
2312     case 25:
2313         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2314         break;
2315     case 26:
2316         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2317         break;
2318     case 28:
2319         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2320         break;
2321     default:
2322         arg1 = (int32_t)env->active_fpu.fcr31;
2323         break;
2324     }
2325
2326     return arg1;
2327 }
2328
2329 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
2330 {
2331     switch(reg) {
2332     case 25:
2333         if (arg1 & 0xffffff00)
2334             return;
2335         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2336                      ((arg1 & 0x1) << 23);
2337         break;
2338     case 26:
2339         if (arg1 & 0x007c0000)
2340             return;
2341         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2342         break;
2343     case 28:
2344         if (arg1 & 0x007c0000)
2345             return;
2346         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2347                      ((arg1 & 0x4) << 22);
2348         break;
2349     case 31:
2350         if (arg1 & 0x007c0000)
2351             return;
2352         env->active_fpu.fcr31 = arg1;
2353         break;
2354     default:
2355         return;
2356     }
2357     /* set rounding mode */
2358     RESTORE_ROUNDING_MODE;
2359     /* set flush-to-zero mode */
2360     RESTORE_FLUSH_MODE;
2361     set_float_exception_flags(0, &env->active_fpu.fp_status);
2362     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2363         do_raise_exception(env, EXCP_FPE, GETPC());
2364 }
2365
2366 static inline int ieee_ex_to_mips(int xcpt)
2367 {
2368     int ret = 0;
2369     if (xcpt) {
2370         if (xcpt & float_flag_invalid) {
2371             ret |= FP_INVALID;
2372         }
2373         if (xcpt & float_flag_overflow) {
2374             ret |= FP_OVERFLOW;
2375         }
2376         if (xcpt & float_flag_underflow) {
2377             ret |= FP_UNDERFLOW;
2378         }
2379         if (xcpt & float_flag_divbyzero) {
2380             ret |= FP_DIV0;
2381         }
2382         if (xcpt & float_flag_inexact) {
2383             ret |= FP_INEXACT;
2384         }
2385     }
2386     return ret;
2387 }
2388
2389 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2390 {
2391     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2392
2393     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2394
2395     if (tmp) {
2396         set_float_exception_flags(0, &env->active_fpu.fp_status);
2397
2398         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2399             do_raise_exception(env, EXCP_FPE, pc);
2400         } else {
2401             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2402         }
2403     }
2404 }
2405
2406 /* Float support.
2407    Single precition routines have a "s" suffix, double precision a
2408    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2409    paired single lower "pl", paired single upper "pu".  */
2410
2411 /* unary operations, modifying fp status  */
2412 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2413 {
2414     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2415     update_fcr31(env, GETPC());
2416     return fdt0;
2417 }
2418
2419 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2420 {
2421     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2422     update_fcr31(env, GETPC());
2423     return fst0;
2424 }
2425
2426 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2427 {
2428     uint64_t fdt2;
2429
2430     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2431     update_fcr31(env, GETPC());
2432     return fdt2;
2433 }
2434
2435 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2436 {
2437     uint64_t fdt2;
2438
2439     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2440     update_fcr31(env, GETPC());
2441     return fdt2;
2442 }
2443
2444 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2445 {
2446     uint64_t fdt2;
2447
2448     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2449     update_fcr31(env, GETPC());
2450     return fdt2;
2451 }
2452
2453 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2454 {
2455     uint64_t dt2;
2456
2457     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2458     if (get_float_exception_flags(&env->active_fpu.fp_status)
2459         & (float_flag_invalid | float_flag_overflow)) {
2460         dt2 = FP_TO_INT64_OVERFLOW;
2461     }
2462     update_fcr31(env, GETPC());
2463     return dt2;
2464 }
2465
2466 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2467 {
2468     uint64_t dt2;
2469
2470     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2471     if (get_float_exception_flags(&env->active_fpu.fp_status)
2472         & (float_flag_invalid | float_flag_overflow)) {
2473         dt2 = FP_TO_INT64_OVERFLOW;
2474     }
2475     update_fcr31(env, GETPC());
2476     return dt2;
2477 }
2478
2479 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2480 {
2481     uint32_t fst2;
2482     uint32_t fsth2;
2483
2484     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2485     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2486     update_fcr31(env, GETPC());
2487     return ((uint64_t)fsth2 << 32) | fst2;
2488 }
2489
2490 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2491 {
2492     uint32_t wt2;
2493     uint32_t wth2;
2494     int excp, excph;
2495
2496     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2497     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2498     if (excp & (float_flag_overflow | float_flag_invalid)) {
2499         wt2 = FP_TO_INT32_OVERFLOW;
2500     }
2501
2502     set_float_exception_flags(0, &env->active_fpu.fp_status);
2503     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2504     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2505     if (excph & (float_flag_overflow | float_flag_invalid)) {
2506         wth2 = FP_TO_INT32_OVERFLOW;
2507     }
2508
2509     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2510     update_fcr31(env, GETPC());
2511
2512     return ((uint64_t)wth2 << 32) | wt2;
2513 }
2514
2515 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2516 {
2517     uint32_t fst2;
2518
2519     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2520     update_fcr31(env, GETPC());
2521     return fst2;
2522 }
2523
2524 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2525 {
2526     uint32_t fst2;
2527
2528     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2529     update_fcr31(env, GETPC());
2530     return fst2;
2531 }
2532
2533 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2534 {
2535     uint32_t fst2;
2536
2537     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2538     update_fcr31(env, GETPC());
2539     return fst2;
2540 }
2541
2542 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2543 {
2544     uint32_t wt2;
2545
2546     wt2 = wt0;
2547     update_fcr31(env, GETPC());
2548     return wt2;
2549 }
2550
2551 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2552 {
2553     uint32_t wt2;
2554
2555     wt2 = wth0;
2556     update_fcr31(env, GETPC());
2557     return wt2;
2558 }
2559
2560 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2561 {
2562     uint32_t wt2;
2563
2564     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2565     update_fcr31(env, GETPC());
2566     if (get_float_exception_flags(&env->active_fpu.fp_status)
2567         & (float_flag_invalid | float_flag_overflow)) {
2568         wt2 = FP_TO_INT32_OVERFLOW;
2569     }
2570     return wt2;
2571 }
2572
2573 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2574 {
2575     uint32_t wt2;
2576
2577     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2578     if (get_float_exception_flags(&env->active_fpu.fp_status)
2579         & (float_flag_invalid | float_flag_overflow)) {
2580         wt2 = FP_TO_INT32_OVERFLOW;
2581     }
2582     update_fcr31(env, GETPC());
2583     return wt2;
2584 }
2585
2586 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2587 {
2588     uint64_t dt2;
2589
2590     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2591     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2592     RESTORE_ROUNDING_MODE;
2593     if (get_float_exception_flags(&env->active_fpu.fp_status)
2594         & (float_flag_invalid | float_flag_overflow)) {
2595         dt2 = FP_TO_INT64_OVERFLOW;
2596     }
2597     update_fcr31(env, GETPC());
2598     return dt2;
2599 }
2600
2601 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2602 {
2603     uint64_t dt2;
2604
2605     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2606     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2607     RESTORE_ROUNDING_MODE;
2608     if (get_float_exception_flags(&env->active_fpu.fp_status)
2609         & (float_flag_invalid | float_flag_overflow)) {
2610         dt2 = FP_TO_INT64_OVERFLOW;
2611     }
2612     update_fcr31(env, GETPC());
2613     return dt2;
2614 }
2615
2616 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2617 {
2618     uint32_t wt2;
2619
2620     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2621     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2622     RESTORE_ROUNDING_MODE;
2623     if (get_float_exception_flags(&env->active_fpu.fp_status)
2624         & (float_flag_invalid | float_flag_overflow)) {
2625         wt2 = FP_TO_INT32_OVERFLOW;
2626     }
2627     update_fcr31(env, GETPC());
2628     return wt2;
2629 }
2630
2631 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2632 {
2633     uint32_t wt2;
2634
2635     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2636     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2637     RESTORE_ROUNDING_MODE;
2638     if (get_float_exception_flags(&env->active_fpu.fp_status)
2639         & (float_flag_invalid | float_flag_overflow)) {
2640         wt2 = FP_TO_INT32_OVERFLOW;
2641     }
2642     update_fcr31(env, GETPC());
2643     return wt2;
2644 }
2645
2646 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2647 {
2648     uint64_t dt2;
2649
2650     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2651     if (get_float_exception_flags(&env->active_fpu.fp_status)
2652         & (float_flag_invalid | float_flag_overflow)) {
2653         dt2 = FP_TO_INT64_OVERFLOW;
2654     }
2655     update_fcr31(env, GETPC());
2656     return dt2;
2657 }
2658
2659 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2660 {
2661     uint64_t dt2;
2662
2663     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2664     if (get_float_exception_flags(&env->active_fpu.fp_status)
2665         & (float_flag_invalid | float_flag_overflow)) {
2666         dt2 = FP_TO_INT64_OVERFLOW;
2667     }
2668     update_fcr31(env, GETPC());
2669     return dt2;
2670 }
2671
2672 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2673 {
2674     uint32_t wt2;
2675
2676     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2677     if (get_float_exception_flags(&env->active_fpu.fp_status)
2678         & (float_flag_invalid | float_flag_overflow)) {
2679         wt2 = FP_TO_INT32_OVERFLOW;
2680     }
2681     update_fcr31(env, GETPC());
2682     return wt2;
2683 }
2684
2685 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2686 {
2687     uint32_t wt2;
2688
2689     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2690     if (get_float_exception_flags(&env->active_fpu.fp_status)
2691         & (float_flag_invalid | float_flag_overflow)) {
2692         wt2 = FP_TO_INT32_OVERFLOW;
2693     }
2694     update_fcr31(env, GETPC());
2695     return wt2;
2696 }
2697
2698 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2699 {
2700     uint64_t dt2;
2701
2702     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2703     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2704     RESTORE_ROUNDING_MODE;
2705     if (get_float_exception_flags(&env->active_fpu.fp_status)
2706         & (float_flag_invalid | float_flag_overflow)) {
2707         dt2 = FP_TO_INT64_OVERFLOW;
2708     }
2709     update_fcr31(env, GETPC());
2710     return dt2;
2711 }
2712
2713 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2714 {
2715     uint64_t dt2;
2716
2717     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2718     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2719     RESTORE_ROUNDING_MODE;
2720     if (get_float_exception_flags(&env->active_fpu.fp_status)
2721         & (float_flag_invalid | float_flag_overflow)) {
2722         dt2 = FP_TO_INT64_OVERFLOW;
2723     }
2724     update_fcr31(env, GETPC());
2725     return dt2;
2726 }
2727
2728 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2729 {
2730     uint32_t wt2;
2731
2732     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2733     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2734     RESTORE_ROUNDING_MODE;
2735     if (get_float_exception_flags(&env->active_fpu.fp_status)
2736         & (float_flag_invalid | float_flag_overflow)) {
2737         wt2 = FP_TO_INT32_OVERFLOW;
2738     }
2739     update_fcr31(env, GETPC());
2740     return wt2;
2741 }
2742
2743 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2744 {
2745     uint32_t wt2;
2746
2747     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2748     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2749     RESTORE_ROUNDING_MODE;
2750     if (get_float_exception_flags(&env->active_fpu.fp_status)
2751         & (float_flag_invalid | float_flag_overflow)) {
2752         wt2 = FP_TO_INT32_OVERFLOW;
2753     }
2754     update_fcr31(env, GETPC());
2755     return wt2;
2756 }
2757
2758 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2759 {
2760     uint64_t dt2;
2761
2762     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2763     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2764     RESTORE_ROUNDING_MODE;
2765     if (get_float_exception_flags(&env->active_fpu.fp_status)
2766         & (float_flag_invalid | float_flag_overflow)) {
2767         dt2 = FP_TO_INT64_OVERFLOW;
2768     }
2769     update_fcr31(env, GETPC());
2770     return dt2;
2771 }
2772
2773 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2774 {
2775     uint64_t dt2;
2776
2777     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2778     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2779     RESTORE_ROUNDING_MODE;
2780     if (get_float_exception_flags(&env->active_fpu.fp_status)
2781         & (float_flag_invalid | float_flag_overflow)) {
2782         dt2 = FP_TO_INT64_OVERFLOW;
2783     }
2784     update_fcr31(env, GETPC());
2785     return dt2;
2786 }
2787
2788 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2789 {
2790     uint32_t wt2;
2791
2792     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2793     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2794     RESTORE_ROUNDING_MODE;
2795     if (get_float_exception_flags(&env->active_fpu.fp_status)
2796         & (float_flag_invalid | float_flag_overflow)) {
2797         wt2 = FP_TO_INT32_OVERFLOW;
2798     }
2799     update_fcr31(env, GETPC());
2800     return wt2;
2801 }
2802
2803 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2804 {
2805     uint32_t wt2;
2806
2807     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2808     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2809     RESTORE_ROUNDING_MODE;
2810     if (get_float_exception_flags(&env->active_fpu.fp_status)
2811         & (float_flag_invalid | float_flag_overflow)) {
2812         wt2 = FP_TO_INT32_OVERFLOW;
2813     }
2814     update_fcr31(env, GETPC());
2815     return wt2;
2816 }
2817
2818 /* unary operations, not modifying fp status  */
2819 #define FLOAT_UNOP(name)                                       \
2820 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2821 {                                                              \
2822     return float64_ ## name(fdt0);                             \
2823 }                                                              \
2824 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2825 {                                                              \
2826     return float32_ ## name(fst0);                             \
2827 }                                                              \
2828 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2829 {                                                              \
2830     uint32_t wt0;                                              \
2831     uint32_t wth0;                                             \
2832                                                                \
2833     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2834     wth0 = float32_ ## name(fdt0 >> 32);                       \
2835     return ((uint64_t)wth0 << 32) | wt0;                       \
2836 }
2837 FLOAT_UNOP(abs)
2838 FLOAT_UNOP(chs)
2839 #undef FLOAT_UNOP
2840
2841 /* MIPS specific unary operations */
2842 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2843 {
2844     uint64_t fdt2;
2845
2846     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2847     update_fcr31(env, GETPC());
2848     return fdt2;
2849 }
2850
2851 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2852 {
2853     uint32_t fst2;
2854
2855     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2856     update_fcr31(env, GETPC());
2857     return fst2;
2858 }
2859
2860 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2861 {
2862     uint64_t fdt2;
2863
2864     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2865     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2866     update_fcr31(env, GETPC());
2867     return fdt2;
2868 }
2869
2870 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2871 {
2872     uint32_t fst2;
2873
2874     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2875     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2876     update_fcr31(env, GETPC());
2877     return fst2;
2878 }
2879
2880 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2881 {
2882     uint64_t fdt2;
2883
2884     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2885     update_fcr31(env, GETPC());
2886     return fdt2;
2887 }
2888
2889 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2890 {
2891     uint32_t fst2;
2892
2893     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2894     update_fcr31(env, GETPC());
2895     return fst2;
2896 }
2897
2898 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2899 {
2900     uint32_t fst2;
2901     uint32_t fsth2;
2902
2903     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2904     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2905     update_fcr31(env, GETPC());
2906     return ((uint64_t)fsth2 << 32) | fst2;
2907 }
2908
2909 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2910 {
2911     uint64_t fdt2;
2912
2913     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2914     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2915     update_fcr31(env, GETPC());
2916     return fdt2;
2917 }
2918
2919 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2920 {
2921     uint32_t fst2;
2922
2923     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2924     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2925     update_fcr31(env, GETPC());
2926     return fst2;
2927 }
2928
2929 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2930 {
2931     uint32_t fst2;
2932     uint32_t fsth2;
2933
2934     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2935     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2936     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2937     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2938     update_fcr31(env, GETPC());
2939     return ((uint64_t)fsth2 << 32) | fst2;
2940 }
2941
2942 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2943
2944 /* binary operations */
2945 #define FLOAT_BINOP(name)                                          \
2946 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
2947                                      uint64_t fdt0, uint64_t fdt1) \
2948 {                                                                  \
2949     uint64_t dt2;                                                  \
2950                                                                    \
2951     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
2952     update_fcr31(env, GETPC());                                    \
2953     return dt2;                                                    \
2954 }                                                                  \
2955                                                                    \
2956 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
2957                                      uint32_t fst0, uint32_t fst1) \
2958 {                                                                  \
2959     uint32_t wt2;                                                  \
2960                                                                    \
2961     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2962     update_fcr31(env, GETPC());                                    \
2963     return wt2;                                                    \
2964 }                                                                  \
2965                                                                    \
2966 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
2967                                       uint64_t fdt0,               \
2968                                       uint64_t fdt1)               \
2969 {                                                                  \
2970     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
2971     uint32_t fsth0 = fdt0 >> 32;                                   \
2972     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
2973     uint32_t fsth1 = fdt1 >> 32;                                   \
2974     uint32_t wt2;                                                  \
2975     uint32_t wth2;                                                 \
2976                                                                    \
2977     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2978     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
2979     update_fcr31(env, GETPC());                                    \
2980     return ((uint64_t)wth2 << 32) | wt2;                           \
2981 }
2982
2983 FLOAT_BINOP(add)
2984 FLOAT_BINOP(sub)
2985 FLOAT_BINOP(mul)
2986 FLOAT_BINOP(div)
2987 #undef FLOAT_BINOP
2988
2989 /* FMA based operations */
2990 #define FLOAT_FMA(name, type)                                        \
2991 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
2992                                      uint64_t fdt0, uint64_t fdt1,   \
2993                                      uint64_t fdt2)                  \
2994 {                                                                    \
2995     fdt0 = float64_muladd(fdt0, fdt1, fdt2, type,                    \
2996                          &env->active_fpu.fp_status);                \
2997     update_fcr31(env, GETPC());                                      \
2998     return fdt0;                                                     \
2999 }                                                                    \
3000                                                                      \
3001 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3002                                      uint32_t fst0, uint32_t fst1,   \
3003                                      uint32_t fst2)                  \
3004 {                                                                    \
3005     fst0 = float32_muladd(fst0, fst1, fst2, type,                    \
3006                          &env->active_fpu.fp_status);                \
3007     update_fcr31(env, GETPC());                                      \
3008     return fst0;                                                     \
3009 }                                                                    \
3010                                                                      \
3011 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3012                                       uint64_t fdt0, uint64_t fdt1,  \
3013                                       uint64_t fdt2)                 \
3014 {                                                                    \
3015     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3016     uint32_t fsth0 = fdt0 >> 32;                                     \
3017     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3018     uint32_t fsth1 = fdt1 >> 32;                                     \
3019     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3020     uint32_t fsth2 = fdt2 >> 32;                                     \
3021                                                                      \
3022     fst0 = float32_muladd(fst0, fst1, fst2, type,                    \
3023                           &env->active_fpu.fp_status);               \
3024     fsth0 = float32_muladd(fsth0, fsth1, fsth2, type,                \
3025                            &env->active_fpu.fp_status);              \
3026     update_fcr31(env, GETPC());                                      \
3027     return ((uint64_t)fsth0 << 32) | fst0;                           \
3028 }
3029 FLOAT_FMA(madd, 0)
3030 FLOAT_FMA(msub, float_muladd_negate_c)
3031 FLOAT_FMA(nmadd, float_muladd_negate_result)
3032 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3033 #undef FLOAT_FMA
3034
3035 /* MIPS specific binary operations */
3036 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3037 {
3038     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3039     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3040     update_fcr31(env, GETPC());
3041     return fdt2;
3042 }
3043
3044 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3045 {
3046     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3047     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3048     update_fcr31(env, GETPC());
3049     return fst2;
3050 }
3051
3052 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3053 {
3054     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3055     uint32_t fsth0 = fdt0 >> 32;
3056     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3057     uint32_t fsth2 = fdt2 >> 32;
3058
3059     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3060     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3061     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3062     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3063     update_fcr31(env, GETPC());
3064     return ((uint64_t)fsth2 << 32) | fst2;
3065 }
3066
3067 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3068 {
3069     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3070     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3071     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3072     update_fcr31(env, GETPC());
3073     return fdt2;
3074 }
3075
3076 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3077 {
3078     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3079     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3080     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3081     update_fcr31(env, GETPC());
3082     return fst2;
3083 }
3084
3085 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3086 {
3087     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3088     uint32_t fsth0 = fdt0 >> 32;
3089     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3090     uint32_t fsth2 = fdt2 >> 32;
3091
3092     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3093     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3094     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3095     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3096     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3097     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3098     update_fcr31(env, GETPC());
3099     return ((uint64_t)fsth2 << 32) | fst2;
3100 }
3101
3102 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3103 {
3104     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3105     uint32_t fsth0 = fdt0 >> 32;
3106     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3107     uint32_t fsth1 = fdt1 >> 32;
3108     uint32_t fst2;
3109     uint32_t fsth2;
3110
3111     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3112     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3113     update_fcr31(env, GETPC());
3114     return ((uint64_t)fsth2 << 32) | fst2;
3115 }
3116
3117 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3118 {
3119     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3120     uint32_t fsth0 = fdt0 >> 32;
3121     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3122     uint32_t fsth1 = fdt1 >> 32;
3123     uint32_t fst2;
3124     uint32_t fsth2;
3125
3126     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3127     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3128     update_fcr31(env, GETPC());
3129     return ((uint64_t)fsth2 << 32) | fst2;
3130 }
3131
3132 /* compare operations */
3133 #define FOP_COND_D(op, cond)                                   \
3134 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3135                          uint64_t fdt1, int cc)                \
3136 {                                                              \
3137     int c;                                                     \
3138     c = cond;                                                  \
3139     update_fcr31(env, GETPC());                                \
3140     if (c)                                                     \
3141         SET_FP_COND(cc, env->active_fpu);                      \
3142     else                                                       \
3143         CLEAR_FP_COND(cc, env->active_fpu);                    \
3144 }                                                              \
3145 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3146                             uint64_t fdt1, int cc)             \
3147 {                                                              \
3148     int c;                                                     \
3149     fdt0 = float64_abs(fdt0);                                  \
3150     fdt1 = float64_abs(fdt1);                                  \
3151     c = cond;                                                  \
3152     update_fcr31(env, GETPC());                                \
3153     if (c)                                                     \
3154         SET_FP_COND(cc, env->active_fpu);                      \
3155     else                                                       \
3156         CLEAR_FP_COND(cc, env->active_fpu);                    \
3157 }
3158
3159 /* NOTE: the comma operator will make "cond" to eval to false,
3160  * but float64_unordered_quiet() is still called. */
3161 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3162 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3163 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3164 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3165 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3166 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3167 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3168 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3169 /* NOTE: the comma operator will make "cond" to eval to false,
3170  * but float64_unordered() is still called. */
3171 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3172 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3173 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3174 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3175 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3176 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3177 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3178 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3179
3180 #define FOP_COND_S(op, cond)                                   \
3181 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3182                          uint32_t fst1, int cc)                \
3183 {                                                              \
3184     int c;                                                     \
3185     c = cond;                                                  \
3186     update_fcr31(env, GETPC());                                \
3187     if (c)                                                     \
3188         SET_FP_COND(cc, env->active_fpu);                      \
3189     else                                                       \
3190         CLEAR_FP_COND(cc, env->active_fpu);                    \
3191 }                                                              \
3192 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3193                             uint32_t fst1, int cc)             \
3194 {                                                              \
3195     int c;                                                     \
3196     fst0 = float32_abs(fst0);                                  \
3197     fst1 = float32_abs(fst1);                                  \
3198     c = cond;                                                  \
3199     update_fcr31(env, GETPC());                                \
3200     if (c)                                                     \
3201         SET_FP_COND(cc, env->active_fpu);                      \
3202     else                                                       \
3203         CLEAR_FP_COND(cc, env->active_fpu);                    \
3204 }
3205
3206 /* NOTE: the comma operator will make "cond" to eval to false,
3207  * but float32_unordered_quiet() is still called. */
3208 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3209 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3210 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3211 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3212 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3213 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3214 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3215 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3216 /* NOTE: the comma operator will make "cond" to eval to false,
3217  * but float32_unordered() is still called. */
3218 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3219 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3220 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3221 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3222 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3223 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3224 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3225 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3226
3227 #define FOP_COND_PS(op, condl, condh)                           \
3228 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3229                           uint64_t fdt1, int cc)                \
3230 {                                                               \
3231     uint32_t fst0, fsth0, fst1, fsth1;                          \
3232     int ch, cl;                                                 \
3233     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3234     fsth0 = fdt0 >> 32;                                         \
3235     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3236     fsth1 = fdt1 >> 32;                                         \
3237     cl = condl;                                                 \
3238     ch = condh;                                                 \
3239     update_fcr31(env, GETPC());                                 \
3240     if (cl)                                                     \
3241         SET_FP_COND(cc, env->active_fpu);                       \
3242     else                                                        \
3243         CLEAR_FP_COND(cc, env->active_fpu);                     \
3244     if (ch)                                                     \
3245         SET_FP_COND(cc + 1, env->active_fpu);                   \
3246     else                                                        \
3247         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3248 }                                                               \
3249 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3250                              uint64_t fdt1, int cc)             \
3251 {                                                               \
3252     uint32_t fst0, fsth0, fst1, fsth1;                          \
3253     int ch, cl;                                                 \
3254     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3255     fsth0 = float32_abs(fdt0 >> 32);                            \
3256     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3257     fsth1 = float32_abs(fdt1 >> 32);                            \
3258     cl = condl;                                                 \
3259     ch = condh;                                                 \
3260     update_fcr31(env, GETPC());                                 \
3261     if (cl)                                                     \
3262         SET_FP_COND(cc, env->active_fpu);                       \
3263     else                                                        \
3264         CLEAR_FP_COND(cc, env->active_fpu);                     \
3265     if (ch)                                                     \
3266         SET_FP_COND(cc + 1, env->active_fpu);                   \
3267     else                                                        \
3268         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3269 }
3270
3271 /* NOTE: the comma operator will make "cond" to eval to false,
3272  * but float32_unordered_quiet() is still called. */
3273 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3274                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3275 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3276                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3277 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3278                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3279 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3280                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3281 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3282                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3283 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3284                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3285 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3286                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3287 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3288                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3289 /* NOTE: the comma operator will make "cond" to eval to false,
3290  * but float32_unordered() is still called. */
3291 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3292                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3293 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3294                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3295 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3296                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3297 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3298                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3299 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3300                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3301 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3302                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3303 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3304                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3305 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3306                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))