target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22
  23 #include "helper.h"
  24
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "exec/softmmu_exec.h"
  27 #endif /* !defined(CONFIG_USER_ONLY) */
  28
  29 #ifndef CONFIG_USER_ONLY
  30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  31 #endif
  32
  33 /*****************************************************************************/
  34 /* Exceptions processing helpers */
  35
  36 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  37                                                         uint32_t exception,
  38                                                         int error_code,
  39                                                         uintptr_t pc)
  40 {
  41     if (exception < EXCP_SC) {
  42         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  43     }
  44     env->exception_index = exception;
  45     env->error_code = error_code;
  46
  47     if (pc) {
  48         /* now we have a real cpu fault */
  49         cpu_restore_state(env, pc);
  50     }
  51
  52     cpu_loop_exit(env);
  53 }
  54
  55 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  56                                                     uint32_t exception,
  57                                                     uintptr_t pc)
  58 {
  59     do_raise_exception_err(env, exception, 0, pc);
  60 }
  61
  62 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  63                                 int error_code)
  64 {
  65     do_raise_exception_err(env, exception, error_code, 0);
  66 }
  67
  68 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  69 {
  70     do_raise_exception(env, exception, 0);
  71 }
  72
  73 #if defined(CONFIG_USER_ONLY)
  74 #define HELPER_LD(name, insn, type)                                     \
  75 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  76                              int mem_idx)                               \
  77 {                                                                       \
  78     return (type) insn##_raw(addr);                                     \
  79 }
  80 #else
  81 #define HELPER_LD(name, insn, type)                                     \
  82 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  83                              int mem_idx)                               \
  84 {                                                                       \
  85     switch (mem_idx)                                                    \
  86     {                                                                   \
  87     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  88     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  89     default:                                                            \
  90     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  91     }                                                                   \
  92 }
  93 #endif
  94 HELPER_LD(lbu, ldub, uint8_t)
  95 HELPER_LD(lw, ldl, int32_t)
  96 #ifdef TARGET_MIPS64
  97 HELPER_LD(ld, ldq, int64_t)
  98 #endif
  99 #undef HELPER_LD
 100
 101 #if defined(CONFIG_USER_ONLY)
 102 #define HELPER_ST(name, insn, type)                                     \
 103 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 104                              type val, int mem_idx)                     \
 105 {                                                                       \
 106     insn##_raw(addr, val);                                              \
 107 }
 108 #else
 109 #define HELPER_ST(name, insn, type)                                     \
 110 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 111                              type val, int mem_idx)                     \
 112 {                                                                       \
 113     switch (mem_idx)                                                    \
 114     {                                                                   \
 115     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 116     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 117     default:                                                            \
 118     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 119     }                                                                   \
 120 }
 121 #endif
 122 HELPER_ST(sb, stb, uint8_t)
 123 HELPER_ST(sw, stl, uint32_t)
 124 #ifdef TARGET_MIPS64
 125 HELPER_ST(sd, stq, uint64_t)
 126 #endif
 127 #undef HELPER_ST
 128
 129 target_ulong helper_clo (target_ulong arg1)
 130 {
 131     return clo32(arg1);
 132 }
 133
 134 target_ulong helper_clz (target_ulong arg1)
 135 {
 136     return clz32(arg1);
 137 }
 138
 139 #if defined(TARGET_MIPS64)
 140 target_ulong helper_dclo (target_ulong arg1)
 141 {
 142     return clo64(arg1);
 143 }
 144
 145 target_ulong helper_dclz (target_ulong arg1)
 146 {
 147     return clz64(arg1);
 148 }
 149 #endif /* TARGET_MIPS64 */
 150
 151 /* 64 bits arithmetic for 32 bits hosts */
 152 static inline uint64_t get_HILO(CPUMIPSState *env)
 153 {
 154     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 155 }
 156
 157 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 158 {
 159     target_ulong tmp;
 160     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 161     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 162     return tmp;
 163 }
 164
 165 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 166 {
 167     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 168     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 169     return tmp;
 170 }
 171
 172 /* Multiplication variants of the vr54xx. */
 173 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 174                          target_ulong arg2)
 175 {
 176     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 177                                  (int64_t)(int32_t)arg2));
 178 }
 179
 180 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 181                           target_ulong arg2)
 182 {
 183     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 184                        (uint64_t)(uint32_t)arg2);
 185 }
 186
 187 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 188                          target_ulong arg2)
 189 {
 190     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 191                        (int64_t)(int32_t)arg2);
 192 }
 193
 194 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 195                            target_ulong arg2)
 196 {
 197     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 198                        (int64_t)(int32_t)arg2);
 199 }
 200
 201 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 202                           target_ulong arg2)
 203 {
 204     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 205                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 206 }
 207
 208 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 209                             target_ulong arg2)
 210 {
 211     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 212                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 213 }
 214
 215 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 216                          target_ulong arg2)
 217 {
 218     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 219                        (int64_t)(int32_t)arg2);
 220 }
 221
 222 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 223                            target_ulong arg2)
 224 {
 225     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 226                        (int64_t)(int32_t)arg2);
 227 }
 228
 229 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 230                           target_ulong arg2)
 231 {
 232     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 233                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 234 }
 235
 236 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 237                             target_ulong arg2)
 238 {
 239     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 240                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 241 }
 242
 243 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 244                           target_ulong arg2)
 245 {
 246     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 247 }
 248
 249 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 250                            target_ulong arg2)
 251 {
 252     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 253                        (uint64_t)(uint32_t)arg2);
 254 }
 255
 256 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 257                            target_ulong arg2)
 258 {
 259     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 260                        (int64_t)(int32_t)arg2);
 261 }
 262
 263 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 264                             target_ulong arg2)
 265 {
 266     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 267                        (uint64_t)(uint32_t)arg2);
 268 }
 269
 270 #ifdef TARGET_MIPS64
 271 void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
 272 {
 273     muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 274 }
 275
 276 void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
 277 {
 278     mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 279 }
 280 #endif
 281
 282 #ifndef CONFIG_USER_ONLY
 283
 284 static inline hwaddr do_translate_address(CPUMIPSState *env,
 285                                                       target_ulong address,
 286                                                       int rw)
 287 {
 288     hwaddr lladdr;
 289
 290     lladdr = cpu_mips_translate_address(env, address, rw);
 291
 292     if (lladdr == -1LL) {
 293         cpu_loop_exit(env);
 294     } else {
 295         return lladdr;
 296     }
 297 }
 298
 299 #define HELPER_LD_ATOMIC(name, insn)                                          \
 300 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 301 {                                                                             \
 302     env->lladdr = do_translate_address(env, arg, 0);                          \
 303     env->llval = do_##insn(env, arg, mem_idx);                                \
 304     return env->llval;                                                        \
 305 }
 306 HELPER_LD_ATOMIC(ll, lw)
 307 #ifdef TARGET_MIPS64
 308 HELPER_LD_ATOMIC(lld, ld)
 309 #endif
 310 #undef HELPER_LD_ATOMIC
 311
 312 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 313 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 314                            target_ulong arg2, int mem_idx)                    \
 315 {                                                                             \
 316     target_long tmp;                                                          \
 317                                                                               \
 318     if (arg2 & almask) {                                                      \
 319         env->CP0_BadVAddr = arg2;                                             \
 320         helper_raise_exception(env, EXCP_AdES);                               \
 321     }                                                                         \
 322     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 323         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 324         if (tmp == env->llval) {                                              \
 325             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 326             return 1;                                                         \
 327         }                                                                     \
 328     }                                                                         \
 329     return 0;                                                                 \
 330 }
 331 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 332 #ifdef TARGET_MIPS64
 333 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 334 #endif
 335 #undef HELPER_ST_ATOMIC
 336 #endif
 337
 338 #ifdef TARGET_WORDS_BIGENDIAN
 339 #define GET_LMASK(v) ((v) & 3)
 340 #define GET_OFFSET(addr, offset) (addr + (offset))
 341 #else
 342 #define GET_LMASK(v) (((v) & 3) ^ 3)
 343 #define GET_OFFSET(addr, offset) (addr - (offset))
 344 #endif
 345
 346 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 347                 int mem_idx)
 348 {
 349     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 350
 351     if (GET_LMASK(arg2) <= 2)
 352         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 353
 354     if (GET_LMASK(arg2) <= 1)
 355         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 356
 357     if (GET_LMASK(arg2) == 0)
 358         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 359 }
 360
 361 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 362                 int mem_idx)
 363 {
 364     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 365
 366     if (GET_LMASK(arg2) >= 1)
 367         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 368
 369     if (GET_LMASK(arg2) >= 2)
 370         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 371
 372     if (GET_LMASK(arg2) == 3)
 373         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 374 }
 375
 376 #if defined(TARGET_MIPS64)
 377 /* "half" load and stores.  We must do the memory access inline,
 378    or fault handling won't work.  */
 379
 380 #ifdef TARGET_WORDS_BIGENDIAN
 381 #define GET_LMASK64(v) ((v) & 7)
 382 #else
 383 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 384 #endif
 385
 386 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 387                 int mem_idx)
 388 {
 389     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 390
 391     if (GET_LMASK64(arg2) <= 6)
 392         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 393
 394     if (GET_LMASK64(arg2) <= 5)
 395         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 396
 397     if (GET_LMASK64(arg2) <= 4)
 398         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 399
 400     if (GET_LMASK64(arg2) <= 3)
 401         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 402
 403     if (GET_LMASK64(arg2) <= 2)
 404         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 405
 406     if (GET_LMASK64(arg2) <= 1)
 407         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 408
 409     if (GET_LMASK64(arg2) <= 0)
 410         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 411 }
 412
 413 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 414                 int mem_idx)
 415 {
 416     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 417
 418     if (GET_LMASK64(arg2) >= 1)
 419         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 420
 421     if (GET_LMASK64(arg2) >= 2)
 422         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 423
 424     if (GET_LMASK64(arg2) >= 3)
 425         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 426
 427     if (GET_LMASK64(arg2) >= 4)
 428         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 429
 430     if (GET_LMASK64(arg2) >= 5)
 431         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 432
 433     if (GET_LMASK64(arg2) >= 6)
 434         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 435
 436     if (GET_LMASK64(arg2) == 7)
 437         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 438 }
 439 #endif /* TARGET_MIPS64 */
 440
 441 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 442
 443 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 444                 uint32_t mem_idx)
 445 {
 446     target_ulong base_reglist = reglist & 0xf;
 447     target_ulong do_r31 = reglist & 0x10;
 448
 449     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 450         target_ulong i;
 451
 452         for (i = 0; i < base_reglist; i++) {
 453             env->active_tc.gpr[multiple_regs[i]] =
 454                 (target_long)do_lw(env, addr, mem_idx);
 455             addr += 4;
 456         }
 457     }
 458
 459     if (do_r31) {
 460         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 461     }
 462 }
 463
 464 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 465                 uint32_t mem_idx)
 466 {
 467     target_ulong base_reglist = reglist & 0xf;
 468     target_ulong do_r31 = reglist & 0x10;
 469
 470     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 471         target_ulong i;
 472
 473         for (i = 0; i < base_reglist; i++) {
 474             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 475             addr += 4;
 476         }
 477     }
 478
 479     if (do_r31) {
 480         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 481     }
 482 }
 483
 484 #if defined(TARGET_MIPS64)
 485 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 486                 uint32_t mem_idx)
 487 {
 488     target_ulong base_reglist = reglist & 0xf;
 489     target_ulong do_r31 = reglist & 0x10;
 490
 491     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 492         target_ulong i;
 493
 494         for (i = 0; i < base_reglist; i++) {
 495             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 496             addr += 8;
 497         }
 498     }
 499
 500     if (do_r31) {
 501         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 502     }
 503 }
 504
 505 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 506                 uint32_t mem_idx)
 507 {
 508     target_ulong base_reglist = reglist & 0xf;
 509     target_ulong do_r31 = reglist & 0x10;
 510
 511     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 512         target_ulong i;
 513
 514         for (i = 0; i < base_reglist; i++) {
 515             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 516             addr += 8;
 517         }
 518     }
 519
 520     if (do_r31) {
 521         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 522     }
 523 }
 524 #endif
 525
 526 #ifndef CONFIG_USER_ONLY
 527 /* SMP helpers.  */
 528 static bool mips_vpe_is_wfi(MIPSCPU *c)
 529 {
 530     CPUMIPSState *env = &c->env;
 531
 532     /* If the VPE is halted but otherwise active, it means it's waiting for
 533        an interrupt.  */
 534     return env->halted && mips_vpe_active(env);
 535 }
 536
 537 static inline void mips_vpe_wake(CPUMIPSState *c)
 538 {
 539     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 540        because there might be other conditions that state that c should
 541        be sleeping.  */
 542     cpu_interrupt(c, CPU_INTERRUPT_WAKE);
 543 }
 544
 545 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 546 {
 547     CPUMIPSState *c = &cpu->env;
 548
 549     /* The VPE was shut off, really go to bed.
 550        Reset any old _WAKE requests.  */
 551     c->halted = 1;
 552     cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
 553 }
 554
 555 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 556 {
 557     CPUMIPSState *c = &cpu->env;
 558
 559     /* FIXME: TC reschedule.  */
 560     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 561         mips_vpe_wake(c);
 562     }
 563 }
 564
 565 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 566 {
 567     CPUMIPSState *c = &cpu->env;
 568
 569     /* FIXME: TC reschedule.  */
 570     if (!mips_vpe_active(c)) {
 571         mips_vpe_sleep(cpu);
 572     }
 573 }
 574
 575 /**
 576  * mips_cpu_map_tc:
 577  * @env: CPU from which mapping is performed.
 578  * @tc: Should point to an int with the value of the global TC index.
 579  *
 580  * This function will transform @tc into a local index within the
 581  * returned #CPUMIPSState.
 582  */
 583 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 584           which depends on runtime setup. Can probably be fixed by
 585           walking the list of CPUMIPSStates.  */
 586 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 587 {
 588     CPUState *cs;
 589     CPUMIPSState *other;
 590     int vpe_idx;
 591     int tc_idx = *tc;
 592
 593     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 594         /* Not allowed to address other CPUs.  */
 595         *tc = env->current_tc;
 596         return env;
 597     }
 598
 599     cs = CPU(mips_env_get_cpu(env));
 600     vpe_idx = tc_idx / cs->nr_threads;
 601     *tc = tc_idx % cs->nr_threads;
 602     other = qemu_get_cpu(vpe_idx);
 603     return other ? other : env;
 604 }
 605
 606 /* The per VPE CP0_Status register shares some fields with the per TC
 607    CP0_TCStatus registers. These fields are wired to the same registers,
 608    so changes to either of them should be reflected on both registers.
 609
 610    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 611
 612    These helper call synchronizes the regs for a given cpu.  */
 613
 614 /* Called for updates to CP0_Status.  */
 615 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 616 {
 617     int32_t tcstatus, *tcst;
 618     uint32_t v = cpu->CP0_Status;
 619     uint32_t cu, mx, asid, ksu;
 620     uint32_t mask = ((1 << CP0TCSt_TCU3)
 621                        | (1 << CP0TCSt_TCU2)
 622                        | (1 << CP0TCSt_TCU1)
 623                        | (1 << CP0TCSt_TCU0)
 624                        | (1 << CP0TCSt_TMX)
 625                        | (3 << CP0TCSt_TKSU)
 626                        | (0xff << CP0TCSt_TASID));
 627
 628     cu = (v >> CP0St_CU0) & 0xf;
 629     mx = (v >> CP0St_MX) & 0x1;
 630     ksu = (v >> CP0St_KSU) & 0x3;
 631     asid = env->CP0_EntryHi & 0xff;
 632
 633     tcstatus = cu << CP0TCSt_TCU0;
 634     tcstatus |= mx << CP0TCSt_TMX;
 635     tcstatus |= ksu << CP0TCSt_TKSU;
 636     tcstatus |= asid;
 637
 638     if (tc == cpu->current_tc) {
 639         tcst = &cpu->active_tc.CP0_TCStatus;
 640     } else {
 641         tcst = &cpu->tcs[tc].CP0_TCStatus;
 642     }
 643
 644     *tcst &= ~mask;
 645     *tcst |= tcstatus;
 646     compute_hflags(cpu);
 647 }
 648
 649 /* Called for updates to CP0_TCStatus.  */
 650 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 651                              target_ulong v)
 652 {
 653     uint32_t status;
 654     uint32_t tcu, tmx, tasid, tksu;
 655     uint32_t mask = ((1 << CP0St_CU3)
 656                        | (1 << CP0St_CU2)
 657                        | (1 << CP0St_CU1)
 658                        | (1 << CP0St_CU0)
 659                        | (1 << CP0St_MX)
 660                        | (3 << CP0St_KSU));
 661
 662     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 663     tmx = (v >> CP0TCSt_TMX) & 0x1;
 664     tasid = v & 0xff;
 665     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 666
 667     status = tcu << CP0St_CU0;
 668     status |= tmx << CP0St_MX;
 669     status |= tksu << CP0St_KSU;
 670
 671     cpu->CP0_Status &= ~mask;
 672     cpu->CP0_Status |= status;
 673
 674     /* Sync the TASID with EntryHi.  */
 675     cpu->CP0_EntryHi &= ~0xff;
 676     cpu->CP0_EntryHi = tasid;
 677
 678     compute_hflags(cpu);
 679 }
 680
 681 /* Called for updates to CP0_EntryHi.  */
 682 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 683 {
 684     int32_t *tcst;
 685     uint32_t asid, v = cpu->CP0_EntryHi;
 686
 687     asid = v & 0xff;
 688
 689     if (tc == cpu->current_tc) {
 690         tcst = &cpu->active_tc.CP0_TCStatus;
 691     } else {
 692         tcst = &cpu->tcs[tc].CP0_TCStatus;
 693     }
 694
 695     *tcst &= ~0xff;
 696     *tcst |= asid;
 697 }
 698
 699 /* CP0 helpers */
 700 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 701 {
 702     return env->mvp->CP0_MVPControl;
 703 }
 704
 705 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 706 {
 707     return env->mvp->CP0_MVPConf0;
 708 }
 709
 710 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 711 {
 712     return env->mvp->CP0_MVPConf1;
 713 }
 714
 715 target_ulong helper_mfc0_random(CPUMIPSState *env)
 716 {
 717     return (int32_t)cpu_mips_get_random(env);
 718 }
 719
 720 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 721 {
 722     return env->active_tc.CP0_TCStatus;
 723 }
 724
 725 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 726 {
 727     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 728     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 729
 730     if (other_tc == other->current_tc)
 731         return other->active_tc.CP0_TCStatus;
 732     else
 733         return other->tcs[other_tc].CP0_TCStatus;
 734 }
 735
 736 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 737 {
 738     return env->active_tc.CP0_TCBind;
 739 }
 740
 741 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 742 {
 743     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 744     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 745
 746     if (other_tc == other->current_tc)
 747         return other->active_tc.CP0_TCBind;
 748     else
 749         return other->tcs[other_tc].CP0_TCBind;
 750 }
 751
 752 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 753 {
 754     return env->active_tc.PC;
 755 }
 756
 757 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 758 {
 759     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 760     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 761
 762     if (other_tc == other->current_tc)
 763         return other->active_tc.PC;
 764     else
 765         return other->tcs[other_tc].PC;
 766 }
 767
 768 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 769 {
 770     return env->active_tc.CP0_TCHalt;
 771 }
 772
 773 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 774 {
 775     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 776     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 777
 778     if (other_tc == other->current_tc)
 779         return other->active_tc.CP0_TCHalt;
 780     else
 781         return other->tcs[other_tc].CP0_TCHalt;
 782 }
 783
 784 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 785 {
 786     return env->active_tc.CP0_TCContext;
 787 }
 788
 789 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 790 {
 791     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 792     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 793
 794     if (other_tc == other->current_tc)
 795         return other->active_tc.CP0_TCContext;
 796     else
 797         return other->tcs[other_tc].CP0_TCContext;
 798 }
 799
 800 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 801 {
 802     return env->active_tc.CP0_TCSchedule;
 803 }
 804
 805 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 806 {
 807     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 808     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 809
 810     if (other_tc == other->current_tc)
 811         return other->active_tc.CP0_TCSchedule;
 812     else
 813         return other->tcs[other_tc].CP0_TCSchedule;
 814 }
 815
 816 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 817 {
 818     return env->active_tc.CP0_TCScheFBack;
 819 }
 820
 821 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 822 {
 823     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 824     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 825
 826     if (other_tc == other->current_tc)
 827         return other->active_tc.CP0_TCScheFBack;
 828     else
 829         return other->tcs[other_tc].CP0_TCScheFBack;
 830 }
 831
 832 target_ulong helper_mfc0_count(CPUMIPSState *env)
 833 {
 834     return (int32_t)cpu_mips_get_count(env);
 835 }
 836
 837 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 838 {
 839     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 840     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 841
 842     return other->CP0_EntryHi;
 843 }
 844
 845 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 846 {
 847     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 848     int32_t tccause;
 849     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 850
 851     if (other_tc == other->current_tc) {
 852         tccause = other->CP0_Cause;
 853     } else {
 854         tccause = other->CP0_Cause;
 855     }
 856
 857     return tccause;
 858 }
 859
 860 target_ulong helper_mftc0_status(CPUMIPSState *env)
 861 {
 862     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 863     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 864
 865     return other->CP0_Status;
 866 }
 867
 868 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 869 {
 870     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 871 }
 872
 873 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 874 {
 875     return (int32_t)env->CP0_WatchLo[sel];
 876 }
 877
 878 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 879 {
 880     return env->CP0_WatchHi[sel];
 881 }
 882
 883 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 884 {
 885     target_ulong t0 = env->CP0_Debug;
 886     if (env->hflags & MIPS_HFLAG_DM)
 887         t0 |= 1 << CP0DB_DM;
 888
 889     return t0;
 890 }
 891
 892 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 893 {
 894     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 895     int32_t tcstatus;
 896     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 897
 898     if (other_tc == other->current_tc)
 899         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 900     else
 901         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 902
 903     /* XXX: Might be wrong, check with EJTAG spec. */
 904     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 905             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 906 }
 907
 908 #if defined(TARGET_MIPS64)
 909 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 910 {
 911     return env->active_tc.PC;
 912 }
 913
 914 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 915 {
 916     return env->active_tc.CP0_TCHalt;
 917 }
 918
 919 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 920 {
 921     return env->active_tc.CP0_TCContext;
 922 }
 923
 924 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 925 {
 926     return env->active_tc.CP0_TCSchedule;
 927 }
 928
 929 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 930 {
 931     return env->active_tc.CP0_TCScheFBack;
 932 }
 933
 934 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 935 {
 936     return env->lladdr >> env->CP0_LLAddr_shift;
 937 }
 938
 939 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 940 {
 941     return env->CP0_WatchLo[sel];
 942 }
 943 #endif /* TARGET_MIPS64 */
 944
 945 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 946 {
 947     int num = 1;
 948     unsigned int tmp = env->tlb->nb_tlb;
 949
 950     do {
 951         tmp >>= 1;
 952         num <<= 1;
 953     } while (tmp);
 954     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 955 }
 956
 957 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 958 {
 959     uint32_t mask = 0;
 960     uint32_t newval;
 961
 962     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 963         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 964                 (1 << CP0MVPCo_EVP);
 965     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 966         mask |= (1 << CP0MVPCo_STLB);
 967     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 968
 969     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 970
 971     env->mvp->CP0_MVPControl = newval;
 972 }
 973
 974 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 975 {
 976     uint32_t mask;
 977     uint32_t newval;
 978
 979     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 980            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 981     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 982
 983     /* Yield scheduler intercept not implemented. */
 984     /* Gating storage scheduler intercept not implemented. */
 985
 986     // TODO: Enable/disable TCs.
 987
 988     env->CP0_VPEControl = newval;
 989 }
 990
 991 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 992 {
 993     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 994     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 995     uint32_t mask;
 996     uint32_t newval;
 997
 998     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 999            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1000     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1001
1002     /* TODO: Enable/disable TCs.  */
1003
1004     other->CP0_VPEControl = newval;
1005 }
1006
1007 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1008 {
1009     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1010     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1011     /* FIXME: Mask away return zero on read bits.  */
1012     return other->CP0_VPEControl;
1013 }
1014
1015 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1016 {
1017     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1018     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1019
1020     return other->CP0_VPEConf0;
1021 }
1022
1023 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1024 {
1025     uint32_t mask = 0;
1026     uint32_t newval;
1027
1028     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1029         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1030             mask |= (0xff << CP0VPEC0_XTC);
1031         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1032     }
1033     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1034
1035     // TODO: TC exclusive handling due to ERL/EXL.
1036
1037     env->CP0_VPEConf0 = newval;
1038 }
1039
1040 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1041 {
1042     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1043     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1044     uint32_t mask = 0;
1045     uint32_t newval;
1046
1047     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1048     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1049
1050     /* TODO: TC exclusive handling due to ERL/EXL.  */
1051     other->CP0_VPEConf0 = newval;
1052 }
1053
1054 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1055 {
1056     uint32_t mask = 0;
1057     uint32_t newval;
1058
1059     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1060         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1061                 (0xff << CP0VPEC1_NCP1);
1062     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1063
1064     /* UDI not implemented. */
1065     /* CP2 not implemented. */
1066
1067     // TODO: Handle FPU (CP1) binding.
1068
1069     env->CP0_VPEConf1 = newval;
1070 }
1071
1072 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1073 {
1074     /* Yield qualifier inputs not implemented. */
1075     env->CP0_YQMask = 0x00000000;
1076 }
1077
1078 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1079 {
1080     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1081 }
1082
1083 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1084 {
1085     /* Large physaddr (PABITS) not implemented */
1086     /* 1k pages not implemented */
1087     env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1088 }
1089
1090 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1091 {
1092     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1093     uint32_t newval;
1094
1095     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1096
1097     env->active_tc.CP0_TCStatus = newval;
1098     sync_c0_tcstatus(env, env->current_tc, newval);
1099 }
1100
1101 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1102 {
1103     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1104     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1105
1106     if (other_tc == other->current_tc)
1107         other->active_tc.CP0_TCStatus = arg1;
1108     else
1109         other->tcs[other_tc].CP0_TCStatus = arg1;
1110     sync_c0_tcstatus(other, other_tc, arg1);
1111 }
1112
1113 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1114 {
1115     uint32_t mask = (1 << CP0TCBd_TBE);
1116     uint32_t newval;
1117
1118     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1119         mask |= (1 << CP0TCBd_CurVPE);
1120     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1121     env->active_tc.CP0_TCBind = newval;
1122 }
1123
1124 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1125 {
1126     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1127     uint32_t mask = (1 << CP0TCBd_TBE);
1128     uint32_t newval;
1129     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1130
1131     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1132         mask |= (1 << CP0TCBd_CurVPE);
1133     if (other_tc == other->current_tc) {
1134         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1135         other->active_tc.CP0_TCBind = newval;
1136     } else {
1137         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1138         other->tcs[other_tc].CP0_TCBind = newval;
1139     }
1140 }
1141
1142 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1143 {
1144     env->active_tc.PC = arg1;
1145     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1146     env->lladdr = 0ULL;
1147     /* MIPS16 not implemented. */
1148 }
1149
1150 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1151 {
1152     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1153     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1154
1155     if (other_tc == other->current_tc) {
1156         other->active_tc.PC = arg1;
1157         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1158         other->lladdr = 0ULL;
1159         /* MIPS16 not implemented. */
1160     } else {
1161         other->tcs[other_tc].PC = arg1;
1162         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1163         other->lladdr = 0ULL;
1164         /* MIPS16 not implemented. */
1165     }
1166 }
1167
1168 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1169 {
1170     MIPSCPU *cpu = mips_env_get_cpu(env);
1171
1172     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1173
1174     // TODO: Halt TC / Restart (if allocated+active) TC.
1175     if (env->active_tc.CP0_TCHalt & 1) {
1176         mips_tc_sleep(cpu, env->current_tc);
1177     } else {
1178         mips_tc_wake(cpu, env->current_tc);
1179     }
1180 }
1181
1182 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1183 {
1184     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1185     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1186     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1187
1188     // TODO: Halt TC / Restart (if allocated+active) TC.
1189
1190     if (other_tc == other->current_tc)
1191         other->active_tc.CP0_TCHalt = arg1;
1192     else
1193         other->tcs[other_tc].CP0_TCHalt = arg1;
1194
1195     if (arg1 & 1) {
1196         mips_tc_sleep(other_cpu, other_tc);
1197     } else {
1198         mips_tc_wake(other_cpu, other_tc);
1199     }
1200 }
1201
1202 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1203 {
1204     env->active_tc.CP0_TCContext = arg1;
1205 }
1206
1207 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1208 {
1209     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1210     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1211
1212     if (other_tc == other->current_tc)
1213         other->active_tc.CP0_TCContext = arg1;
1214     else
1215         other->tcs[other_tc].CP0_TCContext = arg1;
1216 }
1217
1218 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1219 {
1220     env->active_tc.CP0_TCSchedule = arg1;
1221 }
1222
1223 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1224 {
1225     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1226     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1227
1228     if (other_tc == other->current_tc)
1229         other->active_tc.CP0_TCSchedule = arg1;
1230     else
1231         other->tcs[other_tc].CP0_TCSchedule = arg1;
1232 }
1233
1234 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1235 {
1236     env->active_tc.CP0_TCScheFBack = arg1;
1237 }
1238
1239 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1240 {
1241     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1242     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1243
1244     if (other_tc == other->current_tc)
1245         other->active_tc.CP0_TCScheFBack = arg1;
1246     else
1247         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1248 }
1249
1250 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1251 {
1252     /* Large physaddr (PABITS) not implemented */
1253     /* 1k pages not implemented */
1254     env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1255 }
1256
1257 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1258 {
1259     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1260 }
1261
1262 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1263 {
1264     /* 1k pages not implemented */
1265     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1266 }
1267
1268 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1269 {
1270     /* SmartMIPS not implemented */
1271     /* Large physaddr (PABITS) not implemented */
1272     /* 1k pages not implemented */
1273     env->CP0_PageGrain = 0;
1274 }
1275
1276 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1277 {
1278     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1279 }
1280
1281 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1282 {
1283     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1284 }
1285
1286 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1287 {
1288     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1289 }
1290
1291 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1292 {
1293     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1294 }
1295
1296 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1297 {
1298     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1299 }
1300
1301 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1302 {
1303     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1304 }
1305
1306 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1307 {
1308     env->CP0_HWREna = arg1 & 0x0000000F;
1309 }
1310
1311 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1312 {
1313     cpu_mips_store_count(env, arg1);
1314 }
1315
1316 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1317 {
1318     target_ulong old, val;
1319
1320     /* 1k pages not implemented */
1321     val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1322 #if defined(TARGET_MIPS64)
1323     val &= env->SEGMask;
1324 #endif
1325     old = env->CP0_EntryHi;
1326     env->CP0_EntryHi = val;
1327     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1328         sync_c0_entryhi(env, env->current_tc);
1329     }
1330     /* If the ASID changes, flush qemu's TLB.  */
1331     if ((old & 0xFF) != (val & 0xFF))
1332         cpu_mips_tlb_flush(env, 1);
1333 }
1334
1335 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1336 {
1337     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1338     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1339
1340     other->CP0_EntryHi = arg1;
1341     sync_c0_entryhi(other, other_tc);
1342 }
1343
1344 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1345 {
1346     cpu_mips_store_compare(env, arg1);
1347 }
1348
1349 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1350 {
1351     uint32_t val, old;
1352     uint32_t mask = env->CP0_Status_rw_bitmask;
1353
1354     val = arg1 & mask;
1355     old = env->CP0_Status;
1356     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1357     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1358         sync_c0_status(env, env, env->current_tc);
1359     } else {
1360         compute_hflags(env);
1361     }
1362
1363     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1364         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1365                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1366                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1367                 env->CP0_Cause);
1368         switch (env->hflags & MIPS_HFLAG_KSU) {
1369         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1370         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1371         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1372         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1373         }
1374     }
1375 }
1376
1377 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1378 {
1379     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1380     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1381
1382     other->CP0_Status = arg1 & ~0xf1000018;
1383     sync_c0_status(env, other, other_tc);
1384 }
1385
1386 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1387 {
1388     /* vectored interrupts not implemented, no performance counters. */
1389     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1390 }
1391
1392 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1393 {
1394     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1395     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1396 }
1397
1398 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1399 {
1400     uint32_t mask = 0x00C00300;
1401     uint32_t old = cpu->CP0_Cause;
1402     int i;
1403
1404     if (cpu->insn_flags & ISA_MIPS32R2) {
1405         mask |= 1 << CP0Ca_DC;
1406     }
1407
1408     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1409
1410     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1411         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1412             cpu_mips_stop_count(cpu);
1413         } else {
1414             cpu_mips_start_count(cpu);
1415         }
1416     }
1417
1418     /* Set/reset software interrupts */
1419     for (i = 0 ; i < 2 ; i++) {
1420         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1421             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1422         }
1423     }
1424 }
1425
1426 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1427 {
1428     mtc0_cause(env, arg1);
1429 }
1430
1431 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1432 {
1433     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1434     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1435
1436     mtc0_cause(other, arg1);
1437 }
1438
1439 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1440 {
1441     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1442     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1443
1444     return other->CP0_EPC;
1445 }
1446
1447 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1448 {
1449     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1450     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1451
1452     return other->CP0_EBase;
1453 }
1454
1455 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1456 {
1457     /* vectored interrupts not implemented */
1458     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1459 }
1460
1461 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1462 {
1463     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1464     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1465     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1466 }
1467
1468 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1469 {
1470     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1471     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1472
1473     switch (idx) {
1474     case 0: return other->CP0_Config0;
1475     case 1: return other->CP0_Config1;
1476     case 2: return other->CP0_Config2;
1477     case 3: return other->CP0_Config3;
1478     /* 4 and 5 are reserved.  */
1479     case 6: return other->CP0_Config6;
1480     case 7: return other->CP0_Config7;
1481     default:
1482         break;
1483     }
1484     return 0;
1485 }
1486
1487 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1488 {
1489     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1490 }
1491
1492 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1493 {
1494     /* tertiary/secondary caches not implemented */
1495     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1496 }
1497
1498 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1499 {
1500     target_long mask = env->CP0_LLAddr_rw_bitmask;
1501     arg1 = arg1 << env->CP0_LLAddr_shift;
1502     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1503 }
1504
1505 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1506 {
1507     /* Watch exceptions for instructions, data loads, data stores
1508        not implemented. */
1509     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1510 }
1511
1512 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1513 {
1514     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1515     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1516 }
1517
1518 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1519 {
1520     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1521     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1522 }
1523
1524 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1525 {
1526     env->CP0_Framemask = arg1; /* XXX */
1527 }
1528
1529 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1530 {
1531     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1532     if (arg1 & (1 << CP0DB_DM))
1533         env->hflags |= MIPS_HFLAG_DM;
1534     else
1535         env->hflags &= ~MIPS_HFLAG_DM;
1536 }
1537
1538 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1539 {
1540     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1541     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1542     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1543
1544     /* XXX: Might be wrong, check with EJTAG spec. */
1545     if (other_tc == other->current_tc)
1546         other->active_tc.CP0_Debug_tcstatus = val;
1547     else
1548         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1549     other->CP0_Debug = (other->CP0_Debug &
1550                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1551                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1552 }
1553
1554 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1555 {
1556     env->CP0_Performance0 = arg1 & 0x000007ff;
1557 }
1558
1559 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1560 {
1561     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1562 }
1563
1564 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1565 {
1566     env->CP0_DataLo = arg1; /* XXX */
1567 }
1568
1569 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1570 {
1571     env->CP0_TagHi = arg1; /* XXX */
1572 }
1573
1574 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1575 {
1576     env->CP0_DataHi = arg1; /* XXX */
1577 }
1578
1579 /* MIPS MT functions */
1580 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1581 {
1582     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1583     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1584
1585     if (other_tc == other->current_tc)
1586         return other->active_tc.gpr[sel];
1587     else
1588         return other->tcs[other_tc].gpr[sel];
1589 }
1590
1591 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1592 {
1593     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1594     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1595
1596     if (other_tc == other->current_tc)
1597         return other->active_tc.LO[sel];
1598     else
1599         return other->tcs[other_tc].LO[sel];
1600 }
1601
1602 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1603 {
1604     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1605     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1606
1607     if (other_tc == other->current_tc)
1608         return other->active_tc.HI[sel];
1609     else
1610         return other->tcs[other_tc].HI[sel];
1611 }
1612
1613 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1614 {
1615     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1616     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1617
1618     if (other_tc == other->current_tc)
1619         return other->active_tc.ACX[sel];
1620     else
1621         return other->tcs[other_tc].ACX[sel];
1622 }
1623
1624 target_ulong helper_mftdsp(CPUMIPSState *env)
1625 {
1626     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1627     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1628
1629     if (other_tc == other->current_tc)
1630         return other->active_tc.DSPControl;
1631     else
1632         return other->tcs[other_tc].DSPControl;
1633 }
1634
1635 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1636 {
1637     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1638     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1639
1640     if (other_tc == other->current_tc)
1641         other->active_tc.gpr[sel] = arg1;
1642     else
1643         other->tcs[other_tc].gpr[sel] = arg1;
1644 }
1645
1646 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1647 {
1648     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1649     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1650
1651     if (other_tc == other->current_tc)
1652         other->active_tc.LO[sel] = arg1;
1653     else
1654         other->tcs[other_tc].LO[sel] = arg1;
1655 }
1656
1657 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1658 {
1659     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1660     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1661
1662     if (other_tc == other->current_tc)
1663         other->active_tc.HI[sel] = arg1;
1664     else
1665         other->tcs[other_tc].HI[sel] = arg1;
1666 }
1667
1668 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1669 {
1670     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1671     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1672
1673     if (other_tc == other->current_tc)
1674         other->active_tc.ACX[sel] = arg1;
1675     else
1676         other->tcs[other_tc].ACX[sel] = arg1;
1677 }
1678
1679 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1680 {
1681     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1682     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1683
1684     if (other_tc == other->current_tc)
1685         other->active_tc.DSPControl = arg1;
1686     else
1687         other->tcs[other_tc].DSPControl = arg1;
1688 }
1689
1690 /* MIPS MT functions */
1691 target_ulong helper_dmt(void)
1692 {
1693     // TODO
1694      return 0;
1695 }
1696
1697 target_ulong helper_emt(void)
1698 {
1699     // TODO
1700     return 0;
1701 }
1702
1703 target_ulong helper_dvpe(CPUMIPSState *env)
1704 {
1705     CPUMIPSState *other_cpu_env = first_cpu;
1706     target_ulong prev = env->mvp->CP0_MVPControl;
1707
1708     do {
1709         /* Turn off all VPEs except the one executing the dvpe.  */
1710         if (other_cpu_env != env) {
1711             MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1712
1713             other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1714             mips_vpe_sleep(other_cpu);
1715         }
1716         other_cpu_env = other_cpu_env->next_cpu;
1717     } while (other_cpu_env);
1718     return prev;
1719 }
1720
1721 target_ulong helper_evpe(CPUMIPSState *env)
1722 {
1723     CPUMIPSState *other_cpu_env = first_cpu;
1724     target_ulong prev = env->mvp->CP0_MVPControl;
1725
1726     do {
1727         MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1728
1729         if (other_cpu_env != env
1730             /* If the VPE is WFI, don't disturb its sleep.  */
1731             && !mips_vpe_is_wfi(other_cpu)) {
1732             /* Enable the VPE.  */
1733             other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1734             mips_vpe_wake(other_cpu_env); /* And wake it up.  */
1735         }
1736         other_cpu_env = other_cpu_env->next_cpu;
1737     } while (other_cpu_env);
1738     return prev;
1739 }
1740 #endif /* !CONFIG_USER_ONLY */
1741
1742 void helper_fork(target_ulong arg1, target_ulong arg2)
1743 {
1744     // arg1 = rt, arg2 = rs
1745     arg1 = 0;
1746     // TODO: store to TC register
1747 }
1748
1749 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1750 {
1751     target_long arg1 = arg;
1752
1753     if (arg1 < 0) {
1754         /* No scheduling policy implemented. */
1755         if (arg1 != -2) {
1756             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1757                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1758                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1759                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1760                 helper_raise_exception(env, EXCP_THREAD);
1761             }
1762         }
1763     } else if (arg1 == 0) {
1764         if (0 /* TODO: TC underflow */) {
1765             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1766             helper_raise_exception(env, EXCP_THREAD);
1767         } else {
1768             // TODO: Deallocate TC
1769         }
1770     } else if (arg1 > 0) {
1771         /* Yield qualifier inputs not implemented. */
1772         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1773         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1774         helper_raise_exception(env, EXCP_THREAD);
1775     }
1776     return env->CP0_YQMask;
1777 }
1778
1779 #ifndef CONFIG_USER_ONLY
1780 /* TLB management */
1781 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1782 {
1783     /* Flush qemu's TLB and discard all shadowed entries.  */
1784     tlb_flush (env, flush_global);
1785     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1786 }
1787
1788 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1789 {
1790     /* Discard entries from env->tlb[first] onwards.  */
1791     while (env->tlb->tlb_in_use > first) {
1792         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1793     }
1794 }
1795
1796 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1797 {
1798     r4k_tlb_t *tlb;
1799
1800     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1801     tlb = &env->tlb->mmu.r4k.tlb[idx];
1802     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1803 #if defined(TARGET_MIPS64)
1804     tlb->VPN &= env->SEGMask;
1805 #endif
1806     tlb->ASID = env->CP0_EntryHi & 0xFF;
1807     tlb->PageMask = env->CP0_PageMask;
1808     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1809     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1810     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1811     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1812     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1813     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1814     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1815     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1816     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1817 }
1818
1819 void r4k_helper_tlbwi(CPUMIPSState *env)
1820 {
1821     r4k_tlb_t *tlb;
1822     int idx;
1823     target_ulong VPN;
1824     uint8_t ASID;
1825     bool G, V0, D0, V1, D1;
1826
1827     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1828     tlb = &env->tlb->mmu.r4k.tlb[idx];
1829     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1830 #if defined(TARGET_MIPS64)
1831     VPN &= env->SEGMask;
1832 #endif
1833     ASID = env->CP0_EntryHi & 0xff;
1834     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1835     V0 = (env->CP0_EntryLo0 & 2) != 0;
1836     D0 = (env->CP0_EntryLo0 & 4) != 0;
1837     V1 = (env->CP0_EntryLo1 & 2) != 0;
1838     D1 = (env->CP0_EntryLo1 & 4) != 0;
1839
1840     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1841        permissions on the current entry. */
1842     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1843         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1844         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1845         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1846     }
1847
1848     r4k_invalidate_tlb(env, idx, 0);
1849     r4k_fill_tlb(env, idx);
1850 }
1851
1852 void r4k_helper_tlbwr(CPUMIPSState *env)
1853 {
1854     int r = cpu_mips_get_random(env);
1855
1856     r4k_invalidate_tlb(env, r, 1);
1857     r4k_fill_tlb(env, r);
1858 }
1859
1860 void r4k_helper_tlbp(CPUMIPSState *env)
1861 {
1862     r4k_tlb_t *tlb;
1863     target_ulong mask;
1864     target_ulong tag;
1865     target_ulong VPN;
1866     uint8_t ASID;
1867     int i;
1868
1869     ASID = env->CP0_EntryHi & 0xFF;
1870     for (i = 0; i < env->tlb->nb_tlb; i++) {
1871         tlb = &env->tlb->mmu.r4k.tlb[i];
1872         /* 1k pages are not supported. */
1873         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1874         tag = env->CP0_EntryHi & ~mask;
1875         VPN = tlb->VPN & ~mask;
1876 #if defined(TARGET_MIPS64)
1877         tag &= env->SEGMask;
1878 #endif
1879         /* Check ASID, virtual page number & size */
1880         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1881             /* TLB match */
1882             env->CP0_Index = i;
1883             break;
1884         }
1885     }
1886     if (i == env->tlb->nb_tlb) {
1887         /* No match.  Discard any shadow entries, if any of them match.  */
1888         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1889             tlb = &env->tlb->mmu.r4k.tlb[i];
1890             /* 1k pages are not supported. */
1891             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1892             tag = env->CP0_EntryHi & ~mask;
1893             VPN = tlb->VPN & ~mask;
1894 #if defined(TARGET_MIPS64)
1895             tag &= env->SEGMask;
1896 #endif
1897             /* Check ASID, virtual page number & size */
1898             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1899                 r4k_mips_tlb_flush_extra (env, i);
1900                 break;
1901             }
1902         }
1903
1904         env->CP0_Index |= 0x80000000;
1905     }
1906 }
1907
1908 void r4k_helper_tlbr(CPUMIPSState *env)
1909 {
1910     r4k_tlb_t *tlb;
1911     uint8_t ASID;
1912     int idx;
1913
1914     ASID = env->CP0_EntryHi & 0xFF;
1915     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1916     tlb = &env->tlb->mmu.r4k.tlb[idx];
1917
1918     /* If this will change the current ASID, flush qemu's TLB.  */
1919     if (ASID != tlb->ASID)
1920         cpu_mips_tlb_flush (env, 1);
1921
1922     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1923
1924     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1925     env->CP0_PageMask = tlb->PageMask;
1926     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1927                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1928     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1929                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1930 }
1931
1932 void helper_tlbwi(CPUMIPSState *env)
1933 {
1934     env->tlb->helper_tlbwi(env);
1935 }
1936
1937 void helper_tlbwr(CPUMIPSState *env)
1938 {
1939     env->tlb->helper_tlbwr(env);
1940 }
1941
1942 void helper_tlbp(CPUMIPSState *env)
1943 {
1944     env->tlb->helper_tlbp(env);
1945 }
1946
1947 void helper_tlbr(CPUMIPSState *env)
1948 {
1949     env->tlb->helper_tlbr(env);
1950 }
1951
1952 /* Specials */
1953 target_ulong helper_di(CPUMIPSState *env)
1954 {
1955     target_ulong t0 = env->CP0_Status;
1956
1957     env->CP0_Status = t0 & ~(1 << CP0St_IE);
1958     return t0;
1959 }
1960
1961 target_ulong helper_ei(CPUMIPSState *env)
1962 {
1963     target_ulong t0 = env->CP0_Status;
1964
1965     env->CP0_Status = t0 | (1 << CP0St_IE);
1966     return t0;
1967 }
1968
1969 static void debug_pre_eret(CPUMIPSState *env)
1970 {
1971     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1972         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1973                 env->active_tc.PC, env->CP0_EPC);
1974         if (env->CP0_Status & (1 << CP0St_ERL))
1975             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1976         if (env->hflags & MIPS_HFLAG_DM)
1977             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1978         qemu_log("\n");
1979     }
1980 }
1981
1982 static void debug_post_eret(CPUMIPSState *env)
1983 {
1984     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1985         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1986                 env->active_tc.PC, env->CP0_EPC);
1987         if (env->CP0_Status & (1 << CP0St_ERL))
1988             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1989         if (env->hflags & MIPS_HFLAG_DM)
1990             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1991         switch (env->hflags & MIPS_HFLAG_KSU) {
1992         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1993         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1994         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1995         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1996         }
1997     }
1998 }
1999
2000 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2001 {
2002     env->active_tc.PC = error_pc & ~(target_ulong)1;
2003     if (error_pc & 1) {
2004         env->hflags |= MIPS_HFLAG_M16;
2005     } else {
2006         env->hflags &= ~(MIPS_HFLAG_M16);
2007     }
2008 }
2009
2010 void helper_eret(CPUMIPSState *env)
2011 {
2012     debug_pre_eret(env);
2013     if (env->CP0_Status & (1 << CP0St_ERL)) {
2014         set_pc(env, env->CP0_ErrorEPC);
2015         env->CP0_Status &= ~(1 << CP0St_ERL);
2016     } else {
2017         set_pc(env, env->CP0_EPC);
2018         env->CP0_Status &= ~(1 << CP0St_EXL);
2019     }
2020     compute_hflags(env);
2021     debug_post_eret(env);
2022     env->lladdr = 1;
2023 }
2024
2025 void helper_deret(CPUMIPSState *env)
2026 {
2027     debug_pre_eret(env);
2028     set_pc(env, env->CP0_DEPC);
2029
2030     env->hflags &= MIPS_HFLAG_DM;
2031     compute_hflags(env);
2032     debug_post_eret(env);
2033     env->lladdr = 1;
2034 }
2035 #endif /* !CONFIG_USER_ONLY */
2036
2037 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2038 {
2039     if ((env->hflags & MIPS_HFLAG_CP0) ||
2040         (env->CP0_HWREna & (1 << 0)))
2041         return env->CP0_EBase & 0x3ff;
2042     else
2043         helper_raise_exception(env, EXCP_RI);
2044
2045     return 0;
2046 }
2047
2048 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2049 {
2050     if ((env->hflags & MIPS_HFLAG_CP0) ||
2051         (env->CP0_HWREna & (1 << 1)))
2052         return env->SYNCI_Step;
2053     else
2054         helper_raise_exception(env, EXCP_RI);
2055
2056     return 0;
2057 }
2058
2059 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2060 {
2061     if ((env->hflags & MIPS_HFLAG_CP0) ||
2062         (env->CP0_HWREna & (1 << 2)))
2063         return env->CP0_Count;
2064     else
2065         helper_raise_exception(env, EXCP_RI);
2066
2067     return 0;
2068 }
2069
2070 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2071 {
2072     if ((env->hflags & MIPS_HFLAG_CP0) ||
2073         (env->CP0_HWREna & (1 << 3)))
2074         return env->CCRes;
2075     else
2076         helper_raise_exception(env, EXCP_RI);
2077
2078     return 0;
2079 }
2080
2081 void helper_pmon(CPUMIPSState *env, int function)
2082 {
2083     function /= 2;
2084     switch (function) {
2085     case 2: /* TODO: char inbyte(int waitflag); */
2086         if (env->active_tc.gpr[4] == 0)
2087             env->active_tc.gpr[2] = -1;
2088         /* Fall through */
2089     case 11: /* TODO: char inbyte (void); */
2090         env->active_tc.gpr[2] = -1;
2091         break;
2092     case 3:
2093     case 12:
2094         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2095         break;
2096     case 17:
2097         break;
2098     case 158:
2099         {
2100             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2101             printf("%s", fmt);
2102         }
2103         break;
2104     }
2105 }
2106
2107 void helper_wait(CPUMIPSState *env)
2108 {
2109     env->halted = 1;
2110     cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE);
2111     helper_raise_exception(env, EXCP_HLT);
2112 }
2113
2114 #if !defined(CONFIG_USER_ONLY)
2115
2116 static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
2117                                               target_ulong addr, int is_write,
2118                                               int is_user, uintptr_t retaddr);
2119
2120 #define MMUSUFFIX _mmu
2121 #define ALIGNED_ONLY
2122
2123 #define SHIFT 0
2124 #include "exec/softmmu_template.h"
2125
2126 #define SHIFT 1
2127 #include "exec/softmmu_template.h"
2128
2129 #define SHIFT 2
2130 #include "exec/softmmu_template.h"
2131
2132 #define SHIFT 3
2133 #include "exec/softmmu_template.h"
2134
2135 static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
2136                                 int is_write, int is_user, uintptr_t retaddr)
2137 {
2138     env->CP0_BadVAddr = addr;
2139     do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2140 }
2141
2142 void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
2143               uintptr_t retaddr)
2144 {
2145     int ret;
2146
2147     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
2148     if (ret) {
2149         do_raise_exception_err(env, env->exception_index,
2150                                env->error_code, retaddr);
2151     }
2152 }
2153
2154 void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
2155                            int is_write, int is_exec, int unused, int size)
2156 {
2157     if (is_exec)
2158         helper_raise_exception(env, EXCP_IBE);
2159     else
2160         helper_raise_exception(env, EXCP_DBE);
2161 }
2162 #endif /* !CONFIG_USER_ONLY */
2163
2164 /* Complex FPU operations which may need stack space. */
2165
2166 #define FLOAT_TWO32 make_float32(1 << 30)
2167 #define FLOAT_TWO64 make_float64(1ULL << 62)
2168 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2169 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2170
2171 /* convert MIPS rounding mode in FCR31 to IEEE library */
2172 static unsigned int ieee_rm[] = {
2173     float_round_nearest_even,
2174     float_round_to_zero,
2175     float_round_up,
2176     float_round_down
2177 };
2178
2179 static inline void restore_rounding_mode(CPUMIPSState *env)
2180 {
2181     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2182                             &env->active_fpu.fp_status);
2183 }
2184
2185 static inline void restore_flush_mode(CPUMIPSState *env)
2186 {
2187     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2188                       &env->active_fpu.fp_status);
2189 }
2190
2191 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2192 {
2193     target_ulong arg1;
2194
2195     switch (reg) {
2196     case 0:
2197         arg1 = (int32_t)env->active_fpu.fcr0;
2198         break;
2199     case 25:
2200         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2201         break;
2202     case 26:
2203         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2204         break;
2205     case 28:
2206         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2207         break;
2208     default:
2209         arg1 = (int32_t)env->active_fpu.fcr31;
2210         break;
2211     }
2212
2213     return arg1;
2214 }
2215
2216 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
2217 {
2218     switch(reg) {
2219     case 25:
2220         if (arg1 & 0xffffff00)
2221             return;
2222         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2223                      ((arg1 & 0x1) << 23);
2224         break;
2225     case 26:
2226         if (arg1 & 0x007c0000)
2227             return;
2228         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2229         break;
2230     case 28:
2231         if (arg1 & 0x007c0000)
2232             return;
2233         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2234                      ((arg1 & 0x4) << 22);
2235         break;
2236     case 31:
2237         if (arg1 & 0x007c0000)
2238             return;
2239         env->active_fpu.fcr31 = arg1;
2240         break;
2241     default:
2242         return;
2243     }
2244     /* set rounding mode */
2245     restore_rounding_mode(env);
2246     /* set flush-to-zero mode */
2247     restore_flush_mode(env);
2248     set_float_exception_flags(0, &env->active_fpu.fp_status);
2249     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2250         do_raise_exception(env, EXCP_FPE, GETPC());
2251 }
2252
2253 static inline int ieee_ex_to_mips(int xcpt)
2254 {
2255     int ret = 0;
2256     if (xcpt) {
2257         if (xcpt & float_flag_invalid) {
2258             ret |= FP_INVALID;
2259         }
2260         if (xcpt & float_flag_overflow) {
2261             ret |= FP_OVERFLOW;
2262         }
2263         if (xcpt & float_flag_underflow) {
2264             ret |= FP_UNDERFLOW;
2265         }
2266         if (xcpt & float_flag_divbyzero) {
2267             ret |= FP_DIV0;
2268         }
2269         if (xcpt & float_flag_inexact) {
2270             ret |= FP_INEXACT;
2271         }
2272     }
2273     return ret;
2274 }
2275
2276 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2277 {
2278     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2279
2280     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2281
2282     if (tmp) {
2283         set_float_exception_flags(0, &env->active_fpu.fp_status);
2284
2285         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2286             do_raise_exception(env, EXCP_FPE, pc);
2287         } else {
2288             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2289         }
2290     }
2291 }
2292
2293 /* Float support.
2294    Single precition routines have a "s" suffix, double precision a
2295    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2296    paired single lower "pl", paired single upper "pu".  */
2297
2298 /* unary operations, modifying fp status  */
2299 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2300 {
2301     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2302     update_fcr31(env, GETPC());
2303     return fdt0;
2304 }
2305
2306 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2307 {
2308     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2309     update_fcr31(env, GETPC());
2310     return fst0;
2311 }
2312
2313 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2314 {
2315     uint64_t fdt2;
2316
2317     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2318     update_fcr31(env, GETPC());
2319     return fdt2;
2320 }
2321
2322 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2323 {
2324     uint64_t fdt2;
2325
2326     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2327     update_fcr31(env, GETPC());
2328     return fdt2;
2329 }
2330
2331 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2332 {
2333     uint64_t fdt2;
2334
2335     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2336     update_fcr31(env, GETPC());
2337     return fdt2;
2338 }
2339
2340 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2341 {
2342     uint64_t dt2;
2343
2344     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2345     if (get_float_exception_flags(&env->active_fpu.fp_status)
2346         & (float_flag_invalid | float_flag_overflow)) {
2347         dt2 = FP_TO_INT64_OVERFLOW;
2348     }
2349     update_fcr31(env, GETPC());
2350     return dt2;
2351 }
2352
2353 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2354 {
2355     uint64_t dt2;
2356
2357     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2358     if (get_float_exception_flags(&env->active_fpu.fp_status)
2359         & (float_flag_invalid | float_flag_overflow)) {
2360         dt2 = FP_TO_INT64_OVERFLOW;
2361     }
2362     update_fcr31(env, GETPC());
2363     return dt2;
2364 }
2365
2366 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2367 {
2368     uint32_t fst2;
2369     uint32_t fsth2;
2370
2371     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2372     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2373     update_fcr31(env, GETPC());
2374     return ((uint64_t)fsth2 << 32) | fst2;
2375 }
2376
2377 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2378 {
2379     uint32_t wt2;
2380     uint32_t wth2;
2381     int excp, excph;
2382
2383     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2384     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2385     if (excp & (float_flag_overflow | float_flag_invalid)) {
2386         wt2 = FP_TO_INT32_OVERFLOW;
2387     }
2388
2389     set_float_exception_flags(0, &env->active_fpu.fp_status);
2390     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2391     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2392     if (excph & (float_flag_overflow | float_flag_invalid)) {
2393         wth2 = FP_TO_INT32_OVERFLOW;
2394     }
2395
2396     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2397     update_fcr31(env, GETPC());
2398
2399     return ((uint64_t)wth2 << 32) | wt2;
2400 }
2401
2402 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2403 {
2404     uint32_t fst2;
2405
2406     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2407     update_fcr31(env, GETPC());
2408     return fst2;
2409 }
2410
2411 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2412 {
2413     uint32_t fst2;
2414
2415     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2416     update_fcr31(env, GETPC());
2417     return fst2;
2418 }
2419
2420 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2421 {
2422     uint32_t fst2;
2423
2424     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2425     update_fcr31(env, GETPC());
2426     return fst2;
2427 }
2428
2429 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2430 {
2431     uint32_t wt2;
2432
2433     wt2 = wt0;
2434     update_fcr31(env, GETPC());
2435     return wt2;
2436 }
2437
2438 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2439 {
2440     uint32_t wt2;
2441
2442     wt2 = wth0;
2443     update_fcr31(env, GETPC());
2444     return wt2;
2445 }
2446
2447 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2448 {
2449     uint32_t wt2;
2450
2451     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2452     update_fcr31(env, GETPC());
2453     if (get_float_exception_flags(&env->active_fpu.fp_status)
2454         & (float_flag_invalid | float_flag_overflow)) {
2455         wt2 = FP_TO_INT32_OVERFLOW;
2456     }
2457     return wt2;
2458 }
2459
2460 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2461 {
2462     uint32_t wt2;
2463
2464     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2465     if (get_float_exception_flags(&env->active_fpu.fp_status)
2466         & (float_flag_invalid | float_flag_overflow)) {
2467         wt2 = FP_TO_INT32_OVERFLOW;
2468     }
2469     update_fcr31(env, GETPC());
2470     return wt2;
2471 }
2472
2473 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2474 {
2475     uint64_t dt2;
2476
2477     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2478     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2479     restore_rounding_mode(env);
2480     if (get_float_exception_flags(&env->active_fpu.fp_status)
2481         & (float_flag_invalid | float_flag_overflow)) {
2482         dt2 = FP_TO_INT64_OVERFLOW;
2483     }
2484     update_fcr31(env, GETPC());
2485     return dt2;
2486 }
2487
2488 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2489 {
2490     uint64_t dt2;
2491
2492     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2493     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2494     restore_rounding_mode(env);
2495     if (get_float_exception_flags(&env->active_fpu.fp_status)
2496         & (float_flag_invalid | float_flag_overflow)) {
2497         dt2 = FP_TO_INT64_OVERFLOW;
2498     }
2499     update_fcr31(env, GETPC());
2500     return dt2;
2501 }
2502
2503 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2504 {
2505     uint32_t wt2;
2506
2507     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2508     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2509     restore_rounding_mode(env);
2510     if (get_float_exception_flags(&env->active_fpu.fp_status)
2511         & (float_flag_invalid | float_flag_overflow)) {
2512         wt2 = FP_TO_INT32_OVERFLOW;
2513     }
2514     update_fcr31(env, GETPC());
2515     return wt2;
2516 }
2517
2518 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2519 {
2520     uint32_t wt2;
2521
2522     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2523     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2524     restore_rounding_mode(env);
2525     if (get_float_exception_flags(&env->active_fpu.fp_status)
2526         & (float_flag_invalid | float_flag_overflow)) {
2527         wt2 = FP_TO_INT32_OVERFLOW;
2528     }
2529     update_fcr31(env, GETPC());
2530     return wt2;
2531 }
2532
2533 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2534 {
2535     uint64_t dt2;
2536
2537     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2538     if (get_float_exception_flags(&env->active_fpu.fp_status)
2539         & (float_flag_invalid | float_flag_overflow)) {
2540         dt2 = FP_TO_INT64_OVERFLOW;
2541     }
2542     update_fcr31(env, GETPC());
2543     return dt2;
2544 }
2545
2546 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2547 {
2548     uint64_t dt2;
2549
2550     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2551     if (get_float_exception_flags(&env->active_fpu.fp_status)
2552         & (float_flag_invalid | float_flag_overflow)) {
2553         dt2 = FP_TO_INT64_OVERFLOW;
2554     }
2555     update_fcr31(env, GETPC());
2556     return dt2;
2557 }
2558
2559 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2560 {
2561     uint32_t wt2;
2562
2563     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2564     if (get_float_exception_flags(&env->active_fpu.fp_status)
2565         & (float_flag_invalid | float_flag_overflow)) {
2566         wt2 = FP_TO_INT32_OVERFLOW;
2567     }
2568     update_fcr31(env, GETPC());
2569     return wt2;
2570 }
2571
2572 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2573 {
2574     uint32_t wt2;
2575
2576     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2577     if (get_float_exception_flags(&env->active_fpu.fp_status)
2578         & (float_flag_invalid | float_flag_overflow)) {
2579         wt2 = FP_TO_INT32_OVERFLOW;
2580     }
2581     update_fcr31(env, GETPC());
2582     return wt2;
2583 }
2584
2585 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2586 {
2587     uint64_t dt2;
2588
2589     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2590     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2591     restore_rounding_mode(env);
2592     if (get_float_exception_flags(&env->active_fpu.fp_status)
2593         & (float_flag_invalid | float_flag_overflow)) {
2594         dt2 = FP_TO_INT64_OVERFLOW;
2595     }
2596     update_fcr31(env, GETPC());
2597     return dt2;
2598 }
2599
2600 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2601 {
2602     uint64_t dt2;
2603
2604     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2605     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2606     restore_rounding_mode(env);
2607     if (get_float_exception_flags(&env->active_fpu.fp_status)
2608         & (float_flag_invalid | float_flag_overflow)) {
2609         dt2 = FP_TO_INT64_OVERFLOW;
2610     }
2611     update_fcr31(env, GETPC());
2612     return dt2;
2613 }
2614
2615 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2616 {
2617     uint32_t wt2;
2618
2619     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2620     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2621     restore_rounding_mode(env);
2622     if (get_float_exception_flags(&env->active_fpu.fp_status)
2623         & (float_flag_invalid | float_flag_overflow)) {
2624         wt2 = FP_TO_INT32_OVERFLOW;
2625     }
2626     update_fcr31(env, GETPC());
2627     return wt2;
2628 }
2629
2630 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2631 {
2632     uint32_t wt2;
2633
2634     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2635     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2636     restore_rounding_mode(env);
2637     if (get_float_exception_flags(&env->active_fpu.fp_status)
2638         & (float_flag_invalid | float_flag_overflow)) {
2639         wt2 = FP_TO_INT32_OVERFLOW;
2640     }
2641     update_fcr31(env, GETPC());
2642     return wt2;
2643 }
2644
2645 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2646 {
2647     uint64_t dt2;
2648
2649     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2650     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2651     restore_rounding_mode(env);
2652     if (get_float_exception_flags(&env->active_fpu.fp_status)
2653         & (float_flag_invalid | float_flag_overflow)) {
2654         dt2 = FP_TO_INT64_OVERFLOW;
2655     }
2656     update_fcr31(env, GETPC());
2657     return dt2;
2658 }
2659
2660 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2661 {
2662     uint64_t dt2;
2663
2664     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2665     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2666     restore_rounding_mode(env);
2667     if (get_float_exception_flags(&env->active_fpu.fp_status)
2668         & (float_flag_invalid | float_flag_overflow)) {
2669         dt2 = FP_TO_INT64_OVERFLOW;
2670     }
2671     update_fcr31(env, GETPC());
2672     return dt2;
2673 }
2674
2675 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2676 {
2677     uint32_t wt2;
2678
2679     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2680     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2681     restore_rounding_mode(env);
2682     if (get_float_exception_flags(&env->active_fpu.fp_status)
2683         & (float_flag_invalid | float_flag_overflow)) {
2684         wt2 = FP_TO_INT32_OVERFLOW;
2685     }
2686     update_fcr31(env, GETPC());
2687     return wt2;
2688 }
2689
2690 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2691 {
2692     uint32_t wt2;
2693
2694     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2695     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2696     restore_rounding_mode(env);
2697     if (get_float_exception_flags(&env->active_fpu.fp_status)
2698         & (float_flag_invalid | float_flag_overflow)) {
2699         wt2 = FP_TO_INT32_OVERFLOW;
2700     }
2701     update_fcr31(env, GETPC());
2702     return wt2;
2703 }
2704
2705 /* unary operations, not modifying fp status  */
2706 #define FLOAT_UNOP(name)                                       \
2707 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2708 {                                                              \
2709     return float64_ ## name(fdt0);                             \
2710 }                                                              \
2711 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2712 {                                                              \
2713     return float32_ ## name(fst0);                             \
2714 }                                                              \
2715 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2716 {                                                              \
2717     uint32_t wt0;                                              \
2718     uint32_t wth0;                                             \
2719                                                                \
2720     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2721     wth0 = float32_ ## name(fdt0 >> 32);                       \
2722     return ((uint64_t)wth0 << 32) | wt0;                       \
2723 }
2724 FLOAT_UNOP(abs)
2725 FLOAT_UNOP(chs)
2726 #undef FLOAT_UNOP
2727
2728 /* MIPS specific unary operations */
2729 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2730 {
2731     uint64_t fdt2;
2732
2733     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2734     update_fcr31(env, GETPC());
2735     return fdt2;
2736 }
2737
2738 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2739 {
2740     uint32_t fst2;
2741
2742     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2743     update_fcr31(env, GETPC());
2744     return fst2;
2745 }
2746
2747 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2748 {
2749     uint64_t fdt2;
2750
2751     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2752     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2753     update_fcr31(env, GETPC());
2754     return fdt2;
2755 }
2756
2757 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2758 {
2759     uint32_t fst2;
2760
2761     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2762     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2763     update_fcr31(env, GETPC());
2764     return fst2;
2765 }
2766
2767 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2768 {
2769     uint64_t fdt2;
2770
2771     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2772     update_fcr31(env, GETPC());
2773     return fdt2;
2774 }
2775
2776 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2777 {
2778     uint32_t fst2;
2779
2780     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2781     update_fcr31(env, GETPC());
2782     return fst2;
2783 }
2784
2785 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2786 {
2787     uint32_t fst2;
2788     uint32_t fsth2;
2789
2790     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2791     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2792     update_fcr31(env, GETPC());
2793     return ((uint64_t)fsth2 << 32) | fst2;
2794 }
2795
2796 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2797 {
2798     uint64_t fdt2;
2799
2800     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2801     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2802     update_fcr31(env, GETPC());
2803     return fdt2;
2804 }
2805
2806 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2807 {
2808     uint32_t fst2;
2809
2810     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2811     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2812     update_fcr31(env, GETPC());
2813     return fst2;
2814 }
2815
2816 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2817 {
2818     uint32_t fst2;
2819     uint32_t fsth2;
2820
2821     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2822     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2823     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2824     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2825     update_fcr31(env, GETPC());
2826     return ((uint64_t)fsth2 << 32) | fst2;
2827 }
2828
2829 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2830
2831 /* binary operations */
2832 #define FLOAT_BINOP(name)                                          \
2833 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
2834                                      uint64_t fdt0, uint64_t fdt1) \
2835 {                                                                  \
2836     uint64_t dt2;                                                  \
2837                                                                    \
2838     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
2839     update_fcr31(env, GETPC());                                    \
2840     return dt2;                                                    \
2841 }                                                                  \
2842                                                                    \
2843 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
2844                                      uint32_t fst0, uint32_t fst1) \
2845 {                                                                  \
2846     uint32_t wt2;                                                  \
2847                                                                    \
2848     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2849     update_fcr31(env, GETPC());                                    \
2850     return wt2;                                                    \
2851 }                                                                  \
2852                                                                    \
2853 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
2854                                       uint64_t fdt0,               \
2855                                       uint64_t fdt1)               \
2856 {                                                                  \
2857     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
2858     uint32_t fsth0 = fdt0 >> 32;                                   \
2859     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
2860     uint32_t fsth1 = fdt1 >> 32;                                   \
2861     uint32_t wt2;                                                  \
2862     uint32_t wth2;                                                 \
2863                                                                    \
2864     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2865     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
2866     update_fcr31(env, GETPC());                                    \
2867     return ((uint64_t)wth2 << 32) | wt2;                           \
2868 }
2869
2870 FLOAT_BINOP(add)
2871 FLOAT_BINOP(sub)
2872 FLOAT_BINOP(mul)
2873 FLOAT_BINOP(div)
2874 #undef FLOAT_BINOP
2875
2876 /* FMA based operations */
2877 #define FLOAT_FMA(name, type)                                        \
2878 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
2879                                      uint64_t fdt0, uint64_t fdt1,   \
2880                                      uint64_t fdt2)                  \
2881 {                                                                    \
2882     fdt0 = float64_muladd(fdt0, fdt1, fdt2, type,                    \
2883                          &env->active_fpu.fp_status);                \
2884     update_fcr31(env, GETPC());                                      \
2885     return fdt0;                                                     \
2886 }                                                                    \
2887                                                                      \
2888 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
2889                                      uint32_t fst0, uint32_t fst1,   \
2890                                      uint32_t fst2)                  \
2891 {                                                                    \
2892     fst0 = float32_muladd(fst0, fst1, fst2, type,                    \
2893                          &env->active_fpu.fp_status);                \
2894     update_fcr31(env, GETPC());                                      \
2895     return fst0;                                                     \
2896 }                                                                    \
2897                                                                      \
2898 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
2899                                       uint64_t fdt0, uint64_t fdt1,  \
2900                                       uint64_t fdt2)                 \
2901 {                                                                    \
2902     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
2903     uint32_t fsth0 = fdt0 >> 32;                                     \
2904     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
2905     uint32_t fsth1 = fdt1 >> 32;                                     \
2906     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
2907     uint32_t fsth2 = fdt2 >> 32;                                     \
2908                                                                      \
2909     fst0 = float32_muladd(fst0, fst1, fst2, type,                    \
2910                           &env->active_fpu.fp_status);               \
2911     fsth0 = float32_muladd(fsth0, fsth1, fsth2, type,                \
2912                            &env->active_fpu.fp_status);              \
2913     update_fcr31(env, GETPC());                                      \
2914     return ((uint64_t)fsth0 << 32) | fst0;                           \
2915 }
2916 FLOAT_FMA(madd, 0)
2917 FLOAT_FMA(msub, float_muladd_negate_c)
2918 FLOAT_FMA(nmadd, float_muladd_negate_result)
2919 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2920 #undef FLOAT_FMA
2921
2922 /* MIPS specific binary operations */
2923 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2924 {
2925     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2926     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2927     update_fcr31(env, GETPC());
2928     return fdt2;
2929 }
2930
2931 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2932 {
2933     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2934     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2935     update_fcr31(env, GETPC());
2936     return fst2;
2937 }
2938
2939 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2940 {
2941     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2942     uint32_t fsth0 = fdt0 >> 32;
2943     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2944     uint32_t fsth2 = fdt2 >> 32;
2945
2946     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2947     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2948     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2949     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
2950     update_fcr31(env, GETPC());
2951     return ((uint64_t)fsth2 << 32) | fst2;
2952 }
2953
2954 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2955 {
2956     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2957     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
2958     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2959     update_fcr31(env, GETPC());
2960     return fdt2;
2961 }
2962
2963 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2964 {
2965     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2966     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
2967     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2968     update_fcr31(env, GETPC());
2969     return fst2;
2970 }
2971
2972 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2973 {
2974     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2975     uint32_t fsth0 = fdt0 >> 32;
2976     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2977     uint32_t fsth2 = fdt2 >> 32;
2978
2979     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2980     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2981     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
2982     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
2983     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2984     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2985     update_fcr31(env, GETPC());
2986     return ((uint64_t)fsth2 << 32) | fst2;
2987 }
2988
2989 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
2990 {
2991     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2992     uint32_t fsth0 = fdt0 >> 32;
2993     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2994     uint32_t fsth1 = fdt1 >> 32;
2995     uint32_t fst2;
2996     uint32_t fsth2;
2997
2998     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2999     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3000     update_fcr31(env, GETPC());
3001     return ((uint64_t)fsth2 << 32) | fst2;
3002 }
3003
3004 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3005 {
3006     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3007     uint32_t fsth0 = fdt0 >> 32;
3008     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3009     uint32_t fsth1 = fdt1 >> 32;
3010     uint32_t fst2;
3011     uint32_t fsth2;
3012
3013     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3014     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3015     update_fcr31(env, GETPC());
3016     return ((uint64_t)fsth2 << 32) | fst2;
3017 }
3018
3019 /* compare operations */
3020 #define FOP_COND_D(op, cond)                                   \
3021 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3022                          uint64_t fdt1, int cc)                \
3023 {                                                              \
3024     int c;                                                     \
3025     c = cond;                                                  \
3026     update_fcr31(env, GETPC());                                \
3027     if (c)                                                     \
3028         SET_FP_COND(cc, env->active_fpu);                      \
3029     else                                                       \
3030         CLEAR_FP_COND(cc, env->active_fpu);                    \
3031 }                                                              \
3032 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3033                             uint64_t fdt1, int cc)             \
3034 {                                                              \
3035     int c;                                                     \
3036     fdt0 = float64_abs(fdt0);                                  \
3037     fdt1 = float64_abs(fdt1);                                  \
3038     c = cond;                                                  \
3039     update_fcr31(env, GETPC());                                \
3040     if (c)                                                     \
3041         SET_FP_COND(cc, env->active_fpu);                      \
3042     else                                                       \
3043         CLEAR_FP_COND(cc, env->active_fpu);                    \
3044 }
3045
3046 /* NOTE: the comma operator will make "cond" to eval to false,
3047  * but float64_unordered_quiet() is still called. */
3048 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3049 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3050 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3051 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3052 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3053 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3054 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3055 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3056 /* NOTE: the comma operator will make "cond" to eval to false,
3057  * but float64_unordered() is still called. */
3058 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3059 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3060 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3061 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3062 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3063 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3064 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3065 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3066
3067 #define FOP_COND_S(op, cond)                                   \
3068 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3069                          uint32_t fst1, int cc)                \
3070 {                                                              \
3071     int c;                                                     \
3072     c = cond;                                                  \
3073     update_fcr31(env, GETPC());                                \
3074     if (c)                                                     \
3075         SET_FP_COND(cc, env->active_fpu);                      \
3076     else                                                       \
3077         CLEAR_FP_COND(cc, env->active_fpu);                    \
3078 }                                                              \
3079 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3080                             uint32_t fst1, int cc)             \
3081 {                                                              \
3082     int c;                                                     \
3083     fst0 = float32_abs(fst0);                                  \
3084     fst1 = float32_abs(fst1);                                  \
3085     c = cond;                                                  \
3086     update_fcr31(env, GETPC());                                \
3087     if (c)                                                     \
3088         SET_FP_COND(cc, env->active_fpu);                      \
3089     else                                                       \
3090         CLEAR_FP_COND(cc, env->active_fpu);                    \
3091 }
3092
3093 /* NOTE: the comma operator will make "cond" to eval to false,
3094  * but float32_unordered_quiet() is still called. */
3095 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3096 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3097 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3098 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3099 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3100 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3101 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3102 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3103 /* NOTE: the comma operator will make "cond" to eval to false,
3104  * but float32_unordered() is still called. */
3105 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3106 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3107 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3108 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3109 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3110 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3111 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3112 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3113
3114 #define FOP_COND_PS(op, condl, condh)                           \
3115 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3116                           uint64_t fdt1, int cc)                \
3117 {                                                               \
3118     uint32_t fst0, fsth0, fst1, fsth1;                          \
3119     int ch, cl;                                                 \
3120     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3121     fsth0 = fdt0 >> 32;                                         \
3122     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3123     fsth1 = fdt1 >> 32;                                         \
3124     cl = condl;                                                 \
3125     ch = condh;                                                 \
3126     update_fcr31(env, GETPC());                                 \
3127     if (cl)                                                     \
3128         SET_FP_COND(cc, env->active_fpu);                       \
3129     else                                                        \
3130         CLEAR_FP_COND(cc, env->active_fpu);                     \
3131     if (ch)                                                     \
3132         SET_FP_COND(cc + 1, env->active_fpu);                   \
3133     else                                                        \
3134         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3135 }                                                               \
3136 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3137                              uint64_t fdt1, int cc)             \
3138 {                                                               \
3139     uint32_t fst0, fsth0, fst1, fsth1;                          \
3140     int ch, cl;                                                 \
3141     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3142     fsth0 = float32_abs(fdt0 >> 32);                            \
3143     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3144     fsth1 = float32_abs(fdt1 >> 32);                            \
3145     cl = condl;                                                 \
3146     ch = condh;                                                 \
3147     update_fcr31(env, GETPC());                                 \
3148     if (cl)                                                     \
3149         SET_FP_COND(cc, env->active_fpu);                       \
3150     else                                                        \
3151         CLEAR_FP_COND(cc, env->active_fpu);                     \
3152     if (ch)                                                     \
3153         SET_FP_COND(cc + 1, env->active_fpu);                   \
3154     else                                                        \
3155         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3156 }
3157
3158 /* NOTE: the comma operator will make "cond" to eval to false,
3159  * but float32_unordered_quiet() is still called. */
3160 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3161                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3162 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3163                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3164 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3165                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3166 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3167                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3168 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3169                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3170 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3171                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3172 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3173                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3174 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3175                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3176 /* NOTE: the comma operator will make "cond" to eval to false,
3177  * but float32_unordered() is still called. */
3178 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3179                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3180 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3181                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3182 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3183                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3184 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3185                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3186 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3187                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3188 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3189                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3190 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3191                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3192 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3193                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))