target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include <stdlib.h>
  21 #include "exec.h"
  22
  23 #include "host-utils.h"
  24
  25 #include "helper.h"
  26 /*****************************************************************************/
  27 /* Exceptions processing helpers */
  28
  29 void helper_raise_exception_err (uint32_t exception, int error_code)
  30 {
  31 #if 1
  32     if (exception < 0x100)
  33         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  34 #endif
  35     env->exception_index = exception;
  36     env->error_code = error_code;
  37     cpu_loop_exit();
  38 }
  39
  40 void helper_raise_exception (uint32_t exception)
  41 {
  42     helper_raise_exception_err(exception, 0);
  43 }
  44
  45 void helper_interrupt_restart (void)
  46 {
  47     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
  48         !(env->CP0_Status & (1 << CP0St_ERL)) &&
  49         !(env->hflags & MIPS_HFLAG_DM) &&
  50         (env->CP0_Status & (1 << CP0St_IE)) &&
  51         (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
  52         env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
  53         helper_raise_exception(EXCP_EXT_INTERRUPT);
  54     }
  55 }
  56
  57 #if !defined(CONFIG_USER_ONLY)
  58 static void do_restore_state (void *pc_ptr)
  59 {
  60     TranslationBlock *tb;
  61     unsigned long pc = (unsigned long) pc_ptr;
  62
  63     tb = tb_find_pc (pc);
  64     if (tb) {
  65         cpu_restore_state (tb, env, pc, NULL);
  66     }
  67 }
  68 #endif
  69
  70 target_ulong helper_clo (target_ulong t0)
  71 {
  72     return clo32(t0);
  73 }
  74
  75 target_ulong helper_clz (target_ulong t0)
  76 {
  77     return clz32(t0);
  78 }
  79
  80 #if defined(TARGET_MIPS64)
  81 target_ulong helper_dclo (target_ulong t0)
  82 {
  83     return clo64(t0);
  84 }
  85
  86 target_ulong helper_dclz (target_ulong t0)
  87 {
  88     return clz64(t0);
  89 }
  90 #endif /* TARGET_MIPS64 */
  91
  92 /* 64 bits arithmetic for 32 bits hosts */
  93 static inline uint64_t get_HILO (void)
  94 {
  95     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
  96 }
  97
  98 static inline void set_HILO (uint64_t HILO)
  99 {
 100     env->active_tc.LO[0] = (int32_t)HILO;
 101     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 102 }
 103
 104 static inline void set_HIT0_LO (target_ulong t0, uint64_t HILO)
 105 {
 106     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 107     t0 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 108 }
 109
 110 static inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)
 111 {
 112     t0 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 113     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 114 }
 115
 116 #if TARGET_LONG_BITS > HOST_LONG_BITS
 117 void helper_madd (target_ulong t0, target_ulong t1)
 118 {
 119     int64_t tmp;
 120
 121     tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
 122     set_HILO((int64_t)get_HILO() + tmp);
 123 }
 124
 125 void helper_maddu (target_ulong t0, target_ulong t1)
 126 {
 127     uint64_t tmp;
 128
 129     tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
 130     set_HILO(get_HILO() + tmp);
 131 }
 132
 133 void helper_msub (target_ulong t0, target_ulong t1)
 134 {
 135     int64_t tmp;
 136
 137     tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
 138     set_HILO((int64_t)get_HILO() - tmp);
 139 }
 140
 141 void helper_msubu (target_ulong t0, target_ulong t1)
 142 {
 143     uint64_t tmp;
 144
 145     tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
 146     set_HILO(get_HILO() - tmp);
 147 }
 148 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
 149
 150 /* Multiplication variants of the vr54xx. */
 151 target_ulong helper_muls (target_ulong t0, target_ulong t1)
 152 {
 153     set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
 154
 155     return t0;
 156 }
 157
 158 target_ulong helper_mulsu (target_ulong t0, target_ulong t1)
 159 {
 160     set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
 161
 162     return t0;
 163 }
 164
 165 target_ulong helper_macc (target_ulong t0, target_ulong t1)
 166 {
 167     set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
 168
 169     return t0;
 170 }
 171
 172 target_ulong helper_macchi (target_ulong t0, target_ulong t1)
 173 {
 174     set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
 175
 176     return t0;
 177 }
 178
 179 target_ulong helper_maccu (target_ulong t0, target_ulong t1)
 180 {
 181     set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
 182
 183     return t0;
 184 }
 185
 186 target_ulong helper_macchiu (target_ulong t0, target_ulong t1)
 187 {
 188     set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
 189
 190     return t0;
 191 }
 192
 193 target_ulong helper_msac (target_ulong t0, target_ulong t1)
 194 {
 195     set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
 196
 197     return t0;
 198 }
 199
 200 target_ulong helper_msachi (target_ulong t0, target_ulong t1)
 201 {
 202     set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
 203
 204     return t0;
 205 }
 206
 207 target_ulong helper_msacu (target_ulong t0, target_ulong t1)
 208 {
 209     set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
 210
 211     return t0;
 212 }
 213
 214 target_ulong helper_msachiu (target_ulong t0, target_ulong t1)
 215 {
 216     set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
 217
 218     return t0;
 219 }
 220
 221 target_ulong helper_mulhi (target_ulong t0, target_ulong t1)
 222 {
 223     set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
 224
 225     return t0;
 226 }
 227
 228 target_ulong helper_mulhiu (target_ulong t0, target_ulong t1)
 229 {
 230     set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
 231
 232     return t0;
 233 }
 234
 235 target_ulong helper_mulshi (target_ulong t0, target_ulong t1)
 236 {
 237     set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
 238
 239     return t0;
 240 }
 241
 242 target_ulong helper_mulshiu (target_ulong t0, target_ulong t1)
 243 {
 244     set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
 245
 246     return t0;
 247 }
 248
 249 #ifdef TARGET_MIPS64
 250 void helper_dmult (target_ulong t0, target_ulong t1)
 251 {
 252     muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
 253 }
 254
 255 void helper_dmultu (target_ulong t0, target_ulong t1)
 256 {
 257     mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
 258 }
 259 #endif
 260
 261 #ifdef TARGET_WORDS_BIGENDIAN
 262 #define GET_LMASK(v) ((v) & 3)
 263 #define GET_OFFSET(addr, offset) (addr + (offset))
 264 #else
 265 #define GET_LMASK(v) (((v) & 3) ^ 3)
 266 #define GET_OFFSET(addr, offset) (addr - (offset))
 267 #endif
 268
 269 target_ulong helper_lwl(target_ulong t0, target_ulong t1, int mem_idx)
 270 {
 271     target_ulong tmp;
 272
 273 #ifdef CONFIG_USER_ONLY
 274 #define ldfun ldub_raw
 275 #else
 276     int (*ldfun)(target_ulong);
 277
 278     switch (mem_idx)
 279     {
 280     case 0: ldfun = ldub_kernel; break;
 281     case 1: ldfun = ldub_super; break;
 282     default:
 283     case 2: ldfun = ldub_user; break;
 284     }
 285 #endif
 286     tmp = ldfun(t0);
 287     t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
 288
 289     if (GET_LMASK(t0) <= 2) {
 290         tmp = ldfun(GET_OFFSET(t0, 1));
 291         t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
 292     }
 293
 294     if (GET_LMASK(t0) <= 1) {
 295         tmp = ldfun(GET_OFFSET(t0, 2));
 296         t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
 297     }
 298
 299     if (GET_LMASK(t0) == 0) {
 300         tmp = ldfun(GET_OFFSET(t0, 3));
 301         t1 = (t1 & 0xFFFFFF00) | tmp;
 302     }
 303     return (int32_t)t1;
 304 }
 305
 306 target_ulong helper_lwr(target_ulong t0, target_ulong t1, int mem_idx)
 307 {
 308     target_ulong tmp;
 309
 310 #ifdef CONFIG_USER_ONLY
 311 #define ldfun ldub_raw
 312 #else
 313     int (*ldfun)(target_ulong);
 314
 315     switch (mem_idx)
 316     {
 317     case 0: ldfun = ldub_kernel; break;
 318     case 1: ldfun = ldub_super; break;
 319     default:
 320     case 2: ldfun = ldub_user; break;
 321     }
 322 #endif
 323     tmp = ldfun(t0);
 324     t1 = (t1 & 0xFFFFFF00) | tmp;
 325
 326     if (GET_LMASK(t0) >= 1) {
 327         tmp = ldfun(GET_OFFSET(t0, -1));
 328         t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
 329     }
 330
 331     if (GET_LMASK(t0) >= 2) {
 332         tmp = ldfun(GET_OFFSET(t0, -2));
 333         t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
 334     }
 335
 336     if (GET_LMASK(t0) == 3) {
 337         tmp = ldfun(GET_OFFSET(t0, -3));
 338         t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
 339     }
 340     return (int32_t)t1;
 341 }
 342
 343 void helper_swl(target_ulong t0, target_ulong t1, int mem_idx)
 344 {
 345 #ifdef CONFIG_USER_ONLY
 346 #define stfun stb_raw
 347 #else
 348     void (*stfun)(target_ulong, int);
 349
 350     switch (mem_idx)
 351     {
 352     case 0: stfun = stb_kernel; break;
 353     case 1: stfun = stb_super; break;
 354     default:
 355     case 2: stfun = stb_user; break;
 356     }
 357 #endif
 358     stfun(t0, (uint8_t)(t1 >> 24));
 359
 360     if (GET_LMASK(t0) <= 2)
 361         stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16));
 362
 363     if (GET_LMASK(t0) <= 1)
 364         stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8));
 365
 366     if (GET_LMASK(t0) == 0)
 367         stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
 368 }
 369
 370 void helper_swr(target_ulong t0, target_ulong t1, int mem_idx)
 371 {
 372 #ifdef CONFIG_USER_ONLY
 373 #define stfun stb_raw
 374 #else
 375     void (*stfun)(target_ulong, int);
 376
 377     switch (mem_idx)
 378     {
 379     case 0: stfun = stb_kernel; break;
 380     case 1: stfun = stb_super; break;
 381     default:
 382     case 2: stfun = stb_user; break;
 383     }
 384 #endif
 385     stfun(t0, (uint8_t)t1);
 386
 387     if (GET_LMASK(t0) >= 1)
 388         stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
 389
 390     if (GET_LMASK(t0) >= 2)
 391         stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
 392
 393     if (GET_LMASK(t0) == 3)
 394         stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
 395 }
 396
 397 #if defined(TARGET_MIPS64)
 398 /* "half" load and stores.  We must do the memory access inline,
 399    or fault handling won't work.  */
 400
 401 #ifdef TARGET_WORDS_BIGENDIAN
 402 #define GET_LMASK64(v) ((v) & 7)
 403 #else
 404 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 405 #endif
 406
 407 target_ulong helper_ldl(target_ulong t0, target_ulong t1, int mem_idx)
 408 {
 409     uint64_t tmp;
 410
 411 #ifdef CONFIG_USER_ONLY
 412 #define ldfun ldub_raw
 413 #else
 414     int (*ldfun)(target_ulong);
 415
 416     switch (mem_idx)
 417     {
 418     case 0: ldfun = ldub_kernel; break;
 419     case 1: ldfun = ldub_super; break;
 420     default:
 421     case 2: ldfun = ldub_user; break;
 422     }
 423 #endif
 424     tmp = ldfun(t0);
 425     t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
 426
 427     if (GET_LMASK64(t0) <= 6) {
 428         tmp = ldfun(GET_OFFSET(t0, 1));
 429         t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
 430     }
 431
 432     if (GET_LMASK64(t0) <= 5) {
 433         tmp = ldfun(GET_OFFSET(t0, 2));
 434         t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
 435     }
 436
 437     if (GET_LMASK64(t0) <= 4) {
 438         tmp = ldfun(GET_OFFSET(t0, 3));
 439         t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
 440     }
 441
 442     if (GET_LMASK64(t0) <= 3) {
 443         tmp = ldfun(GET_OFFSET(t0, 4));
 444         t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
 445     }
 446
 447     if (GET_LMASK64(t0) <= 2) {
 448         tmp = ldfun(GET_OFFSET(t0, 5));
 449         t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
 450     }
 451
 452     if (GET_LMASK64(t0) <= 1) {
 453         tmp = ldfun(GET_OFFSET(t0, 6));
 454         t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
 455     }
 456
 457     if (GET_LMASK64(t0) == 0) {
 458         tmp = ldfun(GET_OFFSET(t0, 7));
 459         t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
 460     }
 461
 462     return t1;
 463 }
 464
 465 target_ulong helper_ldr(target_ulong t0, target_ulong t1, int mem_idx)
 466 {
 467     uint64_t tmp;
 468
 469 #ifdef CONFIG_USER_ONLY
 470 #define ldfun ldub_raw
 471 #else
 472     int (*ldfun)(target_ulong);
 473
 474     switch (mem_idx)
 475     {
 476     case 0: ldfun = ldub_kernel; break;
 477     case 1: ldfun = ldub_super; break;
 478     default:
 479     case 2: ldfun = ldub_user; break;
 480     }
 481 #endif
 482     tmp = ldfun(t0);
 483     t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
 484
 485     if (GET_LMASK64(t0) >= 1) {
 486         tmp = ldfun(GET_OFFSET(t0, -1));
 487         t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp  << 8);
 488     }
 489
 490     if (GET_LMASK64(t0) >= 2) {
 491         tmp = ldfun(GET_OFFSET(t0, -2));
 492         t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
 493     }
 494
 495     if (GET_LMASK64(t0) >= 3) {
 496         tmp = ldfun(GET_OFFSET(t0, -3));
 497         t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
 498     }
 499
 500     if (GET_LMASK64(t0) >= 4) {
 501         tmp = ldfun(GET_OFFSET(t0, -4));
 502         t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
 503     }
 504
 505     if (GET_LMASK64(t0) >= 5) {
 506         tmp = ldfun(GET_OFFSET(t0, -5));
 507         t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
 508     }
 509
 510     if (GET_LMASK64(t0) >= 6) {
 511         tmp = ldfun(GET_OFFSET(t0, -6));
 512         t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
 513     }
 514
 515     if (GET_LMASK64(t0) == 7) {
 516         tmp = ldfun(GET_OFFSET(t0, -7));
 517         t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
 518     }
 519
 520     return t1;
 521 }
 522
 523 void helper_sdl(target_ulong t0, target_ulong t1, int mem_idx)
 524 {
 525 #ifdef CONFIG_USER_ONLY
 526 #define stfun stb_raw
 527 #else
 528     void (*stfun)(target_ulong, int);
 529
 530     switch (mem_idx)
 531     {
 532     case 0: stfun = stb_kernel; break;
 533     case 1: stfun = stb_super; break;
 534     default:
 535     case 2: stfun = stb_user; break;
 536     }
 537 #endif
 538     stfun(t0, (uint8_t)(t1 >> 56));
 539
 540     if (GET_LMASK64(t0) <= 6)
 541         stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48));
 542
 543     if (GET_LMASK64(t0) <= 5)
 544         stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40));
 545
 546     if (GET_LMASK64(t0) <= 4)
 547         stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32));
 548
 549     if (GET_LMASK64(t0) <= 3)
 550         stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24));
 551
 552     if (GET_LMASK64(t0) <= 2)
 553         stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16));
 554
 555     if (GET_LMASK64(t0) <= 1)
 556         stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8));
 557
 558     if (GET_LMASK64(t0) <= 0)
 559         stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
 560 }
 561
 562 void helper_sdr(target_ulong t0, target_ulong t1, int mem_idx)
 563 {
 564 #ifdef CONFIG_USER_ONLY
 565 #define stfun stb_raw
 566 #else
 567     void (*stfun)(target_ulong, int);
 568
 569     switch (mem_idx)
 570     {
 571     case 0: stfun = stb_kernel; break;
 572     case 1: stfun = stb_super; break;
 573      default:
 574     case 2: stfun = stb_user; break;
 575     }
 576 #endif
 577     stfun(t0, (uint8_t)t1);
 578
 579     if (GET_LMASK64(t0) >= 1)
 580         stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
 581
 582     if (GET_LMASK64(t0) >= 2)
 583         stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
 584
 585     if (GET_LMASK64(t0) >= 3)
 586         stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
 587
 588     if (GET_LMASK64(t0) >= 4)
 589         stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32));
 590
 591     if (GET_LMASK64(t0) >= 5)
 592         stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40));
 593
 594     if (GET_LMASK64(t0) >= 6)
 595         stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48));
 596
 597     if (GET_LMASK64(t0) == 7)
 598         stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56));
 599 }
 600 #endif /* TARGET_MIPS64 */
 601
 602 #ifndef CONFIG_USER_ONLY
 603 /* CP0 helpers */
 604 target_ulong helper_mfc0_mvpcontrol (void)
 605 {
 606     return env->mvp->CP0_MVPControl;
 607 }
 608
 609 target_ulong helper_mfc0_mvpconf0 (void)
 610 {
 611     return env->mvp->CP0_MVPConf0;
 612 }
 613
 614 target_ulong helper_mfc0_mvpconf1 (void)
 615 {
 616     return env->mvp->CP0_MVPConf1;
 617 }
 618
 619 target_ulong helper_mfc0_random (void)
 620 {
 621     return (int32_t)cpu_mips_get_random(env);
 622 }
 623
 624 target_ulong helper_mfc0_tcstatus (void)
 625 {
 626     return env->active_tc.CP0_TCStatus;
 627 }
 628
 629 target_ulong helper_mftc0_tcstatus(void)
 630 {
 631     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 632
 633     if (other_tc == env->current_tc)
 634         return env->active_tc.CP0_TCStatus;
 635     else
 636         return env->tcs[other_tc].CP0_TCStatus;
 637 }
 638
 639 target_ulong helper_mfc0_tcbind (void)
 640 {
 641     return env->active_tc.CP0_TCBind;
 642 }
 643
 644 target_ulong helper_mftc0_tcbind(void)
 645 {
 646     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 647
 648     if (other_tc == env->current_tc)
 649         return env->active_tc.CP0_TCBind;
 650     else
 651         return env->tcs[other_tc].CP0_TCBind;
 652 }
 653
 654 target_ulong helper_mfc0_tcrestart (void)
 655 {
 656     return env->active_tc.PC;
 657 }
 658
 659 target_ulong helper_mftc0_tcrestart(void)
 660 {
 661     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 662
 663     if (other_tc == env->current_tc)
 664         return env->active_tc.PC;
 665     else
 666         return env->tcs[other_tc].PC;
 667 }
 668
 669 target_ulong helper_mfc0_tchalt (void)
 670 {
 671     return env->active_tc.CP0_TCHalt;
 672 }
 673
 674 target_ulong helper_mftc0_tchalt(void)
 675 {
 676     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 677
 678     if (other_tc == env->current_tc)
 679         return env->active_tc.CP0_TCHalt;
 680     else
 681         return env->tcs[other_tc].CP0_TCHalt;
 682 }
 683
 684 target_ulong helper_mfc0_tccontext (void)
 685 {
 686     return env->active_tc.CP0_TCContext;
 687 }
 688
 689 target_ulong helper_mftc0_tccontext(void)
 690 {
 691     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 692
 693     if (other_tc == env->current_tc)
 694         return env->active_tc.CP0_TCContext;
 695     else
 696         return env->tcs[other_tc].CP0_TCContext;
 697 }
 698
 699 target_ulong helper_mfc0_tcschedule (void)
 700 {
 701     return env->active_tc.CP0_TCSchedule;
 702 }
 703
 704 target_ulong helper_mftc0_tcschedule(void)
 705 {
 706     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 707
 708     if (other_tc == env->current_tc)
 709         return env->active_tc.CP0_TCSchedule;
 710     else
 711         return env->tcs[other_tc].CP0_TCSchedule;
 712 }
 713
 714 target_ulong helper_mfc0_tcschefback (void)
 715 {
 716     return env->active_tc.CP0_TCScheFBack;
 717 }
 718
 719 target_ulong helper_mftc0_tcschefback(void)
 720 {
 721     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 722
 723     if (other_tc == env->current_tc)
 724         return env->active_tc.CP0_TCScheFBack;
 725     else
 726         return env->tcs[other_tc].CP0_TCScheFBack;
 727 }
 728
 729 target_ulong helper_mfc0_count (void)
 730 {
 731     return (int32_t)cpu_mips_get_count(env);
 732 }
 733
 734 target_ulong helper_mftc0_entryhi(void)
 735 {
 736     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 737     int32_t tcstatus;
 738
 739     if (other_tc == env->current_tc)
 740         tcstatus = env->active_tc.CP0_TCStatus;
 741     else
 742         tcstatus = env->tcs[other_tc].CP0_TCStatus;
 743
 744     return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
 745 }
 746
 747 target_ulong helper_mftc0_status(void)
 748 {
 749     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 750     target_ulong t0;
 751     int32_t tcstatus;
 752
 753     if (other_tc == env->current_tc)
 754         tcstatus = env->active_tc.CP0_TCStatus;
 755     else
 756         tcstatus = env->tcs[other_tc].CP0_TCStatus;
 757
 758     t0 = env->CP0_Status & ~0xf1000018;
 759     t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
 760     t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
 761     t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
 762
 763     return t0;
 764 }
 765
 766 target_ulong helper_mfc0_lladdr (void)
 767 {
 768     return (int32_t)env->CP0_LLAddr >> 4;
 769 }
 770
 771 target_ulong helper_mfc0_watchlo (uint32_t sel)
 772 {
 773     return (int32_t)env->CP0_WatchLo[sel];
 774 }
 775
 776 target_ulong helper_mfc0_watchhi (uint32_t sel)
 777 {
 778     return env->CP0_WatchHi[sel];
 779 }
 780
 781 target_ulong helper_mfc0_debug (void)
 782 {
 783     target_ulong t0 = env->CP0_Debug;
 784     if (env->hflags & MIPS_HFLAG_DM)
 785         t0 |= 1 << CP0DB_DM;
 786
 787     return t0;
 788 }
 789
 790 target_ulong helper_mftc0_debug(void)
 791 {
 792     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 793     int32_t tcstatus;
 794
 795     if (other_tc == env->current_tc)
 796         tcstatus = env->active_tc.CP0_Debug_tcstatus;
 797     else
 798         tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus;
 799
 800     /* XXX: Might be wrong, check with EJTAG spec. */
 801     return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 802             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 803 }
 804
 805 #if defined(TARGET_MIPS64)
 806 target_ulong helper_dmfc0_tcrestart (void)
 807 {
 808     return env->active_tc.PC;
 809 }
 810
 811 target_ulong helper_dmfc0_tchalt (void)
 812 {
 813     return env->active_tc.CP0_TCHalt;
 814 }
 815
 816 target_ulong helper_dmfc0_tccontext (void)
 817 {
 818     return env->active_tc.CP0_TCContext;
 819 }
 820
 821 target_ulong helper_dmfc0_tcschedule (void)
 822 {
 823     return env->active_tc.CP0_TCSchedule;
 824 }
 825
 826 target_ulong helper_dmfc0_tcschefback (void)
 827 {
 828     return env->active_tc.CP0_TCScheFBack;
 829 }
 830
 831 target_ulong helper_dmfc0_lladdr (void)
 832 {
 833     return env->CP0_LLAddr >> 4;
 834 }
 835
 836 target_ulong helper_dmfc0_watchlo (uint32_t sel)
 837 {
 838     return env->CP0_WatchLo[sel];
 839 }
 840 #endif /* TARGET_MIPS64 */
 841
 842 void helper_mtc0_index (target_ulong t0)
 843 {
 844     int num = 1;
 845     unsigned int tmp = env->tlb->nb_tlb;
 846
 847     do {
 848         tmp >>= 1;
 849         num <<= 1;
 850     } while (tmp);
 851     env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));
 852 }
 853
 854 void helper_mtc0_mvpcontrol (target_ulong t0)
 855 {
 856     uint32_t mask = 0;
 857     uint32_t newval;
 858
 859     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 860         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 861                 (1 << CP0MVPCo_EVP);
 862     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 863         mask |= (1 << CP0MVPCo_STLB);
 864     newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask);
 865
 866     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 867
 868     env->mvp->CP0_MVPControl = newval;
 869 }
 870
 871 void helper_mtc0_vpecontrol (target_ulong t0)
 872 {
 873     uint32_t mask;
 874     uint32_t newval;
 875
 876     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 877            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 878     newval = (env->CP0_VPEControl & ~mask) | (t0 & mask);
 879
 880     /* Yield scheduler intercept not implemented. */
 881     /* Gating storage scheduler intercept not implemented. */
 882
 883     // TODO: Enable/disable TCs.
 884
 885     env->CP0_VPEControl = newval;
 886 }
 887
 888 void helper_mtc0_vpeconf0 (target_ulong t0)
 889 {
 890     uint32_t mask = 0;
 891     uint32_t newval;
 892
 893     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
 894         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
 895             mask |= (0xff << CP0VPEC0_XTC);
 896         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
 897     }
 898     newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask);
 899
 900     // TODO: TC exclusive handling due to ERL/EXL.
 901
 902     env->CP0_VPEConf0 = newval;
 903 }
 904
 905 void helper_mtc0_vpeconf1 (target_ulong t0)
 906 {
 907     uint32_t mask = 0;
 908     uint32_t newval;
 909
 910     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 911         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
 912                 (0xff << CP0VPEC1_NCP1);
 913     newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask);
 914
 915     /* UDI not implemented. */
 916     /* CP2 not implemented. */
 917
 918     // TODO: Handle FPU (CP1) binding.
 919
 920     env->CP0_VPEConf1 = newval;
 921 }
 922
 923 void helper_mtc0_yqmask (target_ulong t0)
 924 {
 925     /* Yield qualifier inputs not implemented. */
 926     env->CP0_YQMask = 0x00000000;
 927 }
 928
 929 void helper_mtc0_vpeopt (target_ulong t0)
 930 {
 931     env->CP0_VPEOpt = t0 & 0x0000ffff;
 932 }
 933
 934 void helper_mtc0_entrylo0 (target_ulong t0)
 935 {
 936     /* Large physaddr (PABITS) not implemented */
 937     /* 1k pages not implemented */
 938     env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
 939 }
 940
 941 void helper_mtc0_tcstatus (target_ulong t0)
 942 {
 943     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
 944     uint32_t newval;
 945
 946     newval = (env->active_tc.CP0_TCStatus & ~mask) | (t0 & mask);
 947
 948     // TODO: Sync with CP0_Status.
 949
 950     env->active_tc.CP0_TCStatus = newval;
 951 }
 952
 953 void helper_mttc0_tcstatus (target_ulong t0)
 954 {
 955     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 956
 957     // TODO: Sync with CP0_Status.
 958
 959     if (other_tc == env->current_tc)
 960         env->active_tc.CP0_TCStatus = t0;
 961     else
 962         env->tcs[other_tc].CP0_TCStatus = t0;
 963 }
 964
 965 void helper_mtc0_tcbind (target_ulong t0)
 966 {
 967     uint32_t mask = (1 << CP0TCBd_TBE);
 968     uint32_t newval;
 969
 970     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 971         mask |= (1 << CP0TCBd_CurVPE);
 972     newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
 973     env->active_tc.CP0_TCBind = newval;
 974 }
 975
 976 void helper_mttc0_tcbind (target_ulong t0)
 977 {
 978     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 979     uint32_t mask = (1 << CP0TCBd_TBE);
 980     uint32_t newval;
 981
 982     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 983         mask |= (1 << CP0TCBd_CurVPE);
 984     if (other_tc == env->current_tc) {
 985         newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
 986         env->active_tc.CP0_TCBind = newval;
 987     } else {
 988         newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (t0 & mask);
 989         env->tcs[other_tc].CP0_TCBind = newval;
 990     }
 991 }
 992
 993 void helper_mtc0_tcrestart (target_ulong t0)
 994 {
 995     env->active_tc.PC = t0;
 996     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
 997     env->CP0_LLAddr = 0ULL;
 998     /* MIPS16 not implemented. */
 999 }
1000
1001 void helper_mttc0_tcrestart (target_ulong t0)
1002 {
1003     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1004
1005     if (other_tc == env->current_tc) {
1006         env->active_tc.PC = t0;
1007         env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1008         env->CP0_LLAddr = 0ULL;
1009         /* MIPS16 not implemented. */
1010     } else {
1011         env->tcs[other_tc].PC = t0;
1012         env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1013         env->CP0_LLAddr = 0ULL;
1014         /* MIPS16 not implemented. */
1015     }
1016 }
1017
1018 void helper_mtc0_tchalt (target_ulong t0)
1019 {
1020     env->active_tc.CP0_TCHalt = t0 & 0x1;
1021
1022     // TODO: Halt TC / Restart (if allocated+active) TC.
1023 }
1024
1025 void helper_mttc0_tchalt (target_ulong t0)
1026 {
1027     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1028
1029     // TODO: Halt TC / Restart (if allocated+active) TC.
1030
1031     if (other_tc == env->current_tc)
1032         env->active_tc.CP0_TCHalt = t0;
1033     else
1034         env->tcs[other_tc].CP0_TCHalt = t0;
1035 }
1036
1037 void helper_mtc0_tccontext (target_ulong t0)
1038 {
1039     env->active_tc.CP0_TCContext = t0;
1040 }
1041
1042 void helper_mttc0_tccontext (target_ulong t0)
1043 {
1044     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1045
1046     if (other_tc == env->current_tc)
1047         env->active_tc.CP0_TCContext = t0;
1048     else
1049         env->tcs[other_tc].CP0_TCContext = t0;
1050 }
1051
1052 void helper_mtc0_tcschedule (target_ulong t0)
1053 {
1054     env->active_tc.CP0_TCSchedule = t0;
1055 }
1056
1057 void helper_mttc0_tcschedule (target_ulong t0)
1058 {
1059     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1060
1061     if (other_tc == env->current_tc)
1062         env->active_tc.CP0_TCSchedule = t0;
1063     else
1064         env->tcs[other_tc].CP0_TCSchedule = t0;
1065 }
1066
1067 void helper_mtc0_tcschefback (target_ulong t0)
1068 {
1069     env->active_tc.CP0_TCScheFBack = t0;
1070 }
1071
1072 void helper_mttc0_tcschefback (target_ulong t0)
1073 {
1074     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1075
1076     if (other_tc == env->current_tc)
1077         env->active_tc.CP0_TCScheFBack = t0;
1078     else
1079         env->tcs[other_tc].CP0_TCScheFBack = t0;
1080 }
1081
1082 void helper_mtc0_entrylo1 (target_ulong t0)
1083 {
1084     /* Large physaddr (PABITS) not implemented */
1085     /* 1k pages not implemented */
1086     env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
1087 }
1088
1089 void helper_mtc0_context (target_ulong t0)
1090 {
1091     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF);
1092 }
1093
1094 void helper_mtc0_pagemask (target_ulong t0)
1095 {
1096     /* 1k pages not implemented */
1097     env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1098 }
1099
1100 void helper_mtc0_pagegrain (target_ulong t0)
1101 {
1102     /* SmartMIPS not implemented */
1103     /* Large physaddr (PABITS) not implemented */
1104     /* 1k pages not implemented */
1105     env->CP0_PageGrain = 0;
1106 }
1107
1108 void helper_mtc0_wired (target_ulong t0)
1109 {
1110     env->CP0_Wired = t0 % env->tlb->nb_tlb;
1111 }
1112
1113 void helper_mtc0_srsconf0 (target_ulong t0)
1114 {
1115     env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask;
1116 }
1117
1118 void helper_mtc0_srsconf1 (target_ulong t0)
1119 {
1120     env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask;
1121 }
1122
1123 void helper_mtc0_srsconf2 (target_ulong t0)
1124 {
1125     env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask;
1126 }
1127
1128 void helper_mtc0_srsconf3 (target_ulong t0)
1129 {
1130     env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask;
1131 }
1132
1133 void helper_mtc0_srsconf4 (target_ulong t0)
1134 {
1135     env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask;
1136 }
1137
1138 void helper_mtc0_hwrena (target_ulong t0)
1139 {
1140     env->CP0_HWREna = t0 & 0x0000000F;
1141 }
1142
1143 void helper_mtc0_count (target_ulong t0)
1144 {
1145     cpu_mips_store_count(env, t0);
1146 }
1147
1148 void helper_mtc0_entryhi (target_ulong t0)
1149 {
1150     target_ulong old, val;
1151
1152     /* 1k pages not implemented */
1153     val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1154 #if defined(TARGET_MIPS64)
1155     val &= env->SEGMask;
1156 #endif
1157     old = env->CP0_EntryHi;
1158     env->CP0_EntryHi = val;
1159     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1160         uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
1161         env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
1162     }
1163     /* If the ASID changes, flush qemu's TLB.  */
1164     if ((old & 0xFF) != (val & 0xFF))
1165         cpu_mips_tlb_flush(env, 1);
1166 }
1167
1168 void helper_mttc0_entryhi(target_ulong t0)
1169 {
1170     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1171     int32_t tcstatus;
1172
1173     env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff);
1174     if (other_tc == env->current_tc) {
1175         tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (t0 & 0xff);
1176         env->active_tc.CP0_TCStatus = tcstatus;
1177     } else {
1178         tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (t0 & 0xff);
1179         env->tcs[other_tc].CP0_TCStatus = tcstatus;
1180     }
1181 }
1182
1183 void helper_mtc0_compare (target_ulong t0)
1184 {
1185     cpu_mips_store_compare(env, t0);
1186 }
1187
1188 void helper_mtc0_status (target_ulong t0)
1189 {
1190     uint32_t val, old;
1191     uint32_t mask = env->CP0_Status_rw_bitmask;
1192
1193     val = t0 & mask;
1194     old = env->CP0_Status;
1195     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1196     compute_hflags(env);
1197     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1198         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1199                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1200                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1201                 env->CP0_Cause);
1202         switch (env->hflags & MIPS_HFLAG_KSU) {
1203         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1204         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1205         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1206         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1207         }
1208     }
1209     cpu_mips_update_irq(env);
1210 }
1211
1212 void helper_mttc0_status(target_ulong t0)
1213 {
1214     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1215     int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
1216
1217     env->CP0_Status = t0 & ~0xf1000018;
1218     tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0));
1219     tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1220     tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
1221     if (other_tc == env->current_tc)
1222         env->active_tc.CP0_TCStatus = tcstatus;
1223     else
1224         env->tcs[other_tc].CP0_TCStatus = tcstatus;
1225 }
1226
1227 void helper_mtc0_intctl (target_ulong t0)
1228 {
1229     /* vectored interrupts not implemented, no performance counters. */
1230     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0);
1231 }
1232
1233 void helper_mtc0_srsctl (target_ulong t0)
1234 {
1235     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1236     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask);
1237 }
1238
1239 void helper_mtc0_cause (target_ulong t0)
1240 {
1241     uint32_t mask = 0x00C00300;
1242     uint32_t old = env->CP0_Cause;
1243
1244     if (env->insn_flags & ISA_MIPS32R2)
1245         mask |= 1 << CP0Ca_DC;
1246
1247     env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask);
1248
1249     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1250         if (env->CP0_Cause & (1 << CP0Ca_DC))
1251             cpu_mips_stop_count(env);
1252         else
1253             cpu_mips_start_count(env);
1254     }
1255
1256     /* Handle the software interrupt as an hardware one, as they
1257        are very similar */
1258     if (t0 & CP0Ca_IP_mask) {
1259         cpu_mips_update_irq(env);
1260     }
1261 }
1262
1263 void helper_mtc0_ebase (target_ulong t0)
1264 {
1265     /* vectored interrupts not implemented */
1266     /* Multi-CPU not implemented */
1267     env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000);
1268 }
1269
1270 void helper_mtc0_config0 (target_ulong t0)
1271 {
1272     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007);
1273 }
1274
1275 void helper_mtc0_config2 (target_ulong t0)
1276 {
1277     /* tertiary/secondary caches not implemented */
1278     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1279 }
1280
1281 void helper_mtc0_watchlo (target_ulong t0, uint32_t sel)
1282 {
1283     /* Watch exceptions for instructions, data loads, data stores
1284        not implemented. */
1285     env->CP0_WatchLo[sel] = (t0 & ~0x7);
1286 }
1287
1288 void helper_mtc0_watchhi (target_ulong t0, uint32_t sel)
1289 {
1290     env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
1291     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
1292 }
1293
1294 void helper_mtc0_xcontext (target_ulong t0)
1295 {
1296     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1297     env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask);
1298 }
1299
1300 void helper_mtc0_framemask (target_ulong t0)
1301 {
1302     env->CP0_Framemask = t0; /* XXX */
1303 }
1304
1305 void helper_mtc0_debug (target_ulong t0)
1306 {
1307     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120);
1308     if (t0 & (1 << CP0DB_DM))
1309         env->hflags |= MIPS_HFLAG_DM;
1310     else
1311         env->hflags &= ~MIPS_HFLAG_DM;
1312 }
1313
1314 void helper_mttc0_debug(target_ulong t0)
1315 {
1316     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1317     uint32_t val = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1318
1319     /* XXX: Might be wrong, check with EJTAG spec. */
1320     if (other_tc == env->current_tc)
1321         env->active_tc.CP0_Debug_tcstatus = val;
1322     else
1323         env->tcs[other_tc].CP0_Debug_tcstatus = val;
1324     env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1325                      (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1326 }
1327
1328 void helper_mtc0_performance0 (target_ulong t0)
1329 {
1330     env->CP0_Performance0 = t0 & 0x000007ff;
1331 }
1332
1333 void helper_mtc0_taglo (target_ulong t0)
1334 {
1335     env->CP0_TagLo = t0 & 0xFFFFFCF6;
1336 }
1337
1338 void helper_mtc0_datalo (target_ulong t0)
1339 {
1340     env->CP0_DataLo = t0; /* XXX */
1341 }
1342
1343 void helper_mtc0_taghi (target_ulong t0)
1344 {
1345     env->CP0_TagHi = t0; /* XXX */
1346 }
1347
1348 void helper_mtc0_datahi (target_ulong t0)
1349 {
1350     env->CP0_DataHi = t0; /* XXX */
1351 }
1352
1353 /* MIPS MT functions */
1354 target_ulong helper_mftgpr(uint32_t sel)
1355 {
1356     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1357
1358     if (other_tc == env->current_tc)
1359         return env->active_tc.gpr[sel];
1360     else
1361         return env->tcs[other_tc].gpr[sel];
1362 }
1363
1364 target_ulong helper_mftlo(uint32_t sel)
1365 {
1366     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1367
1368     if (other_tc == env->current_tc)
1369         return env->active_tc.LO[sel];
1370     else
1371         return env->tcs[other_tc].LO[sel];
1372 }
1373
1374 target_ulong helper_mfthi(uint32_t sel)
1375 {
1376     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1377
1378     if (other_tc == env->current_tc)
1379         return env->active_tc.HI[sel];
1380     else
1381         return env->tcs[other_tc].HI[sel];
1382 }
1383
1384 target_ulong helper_mftacx(uint32_t sel)
1385 {
1386     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1387
1388     if (other_tc == env->current_tc)
1389         return env->active_tc.ACX[sel];
1390     else
1391         return env->tcs[other_tc].ACX[sel];
1392 }
1393
1394 target_ulong helper_mftdsp(void)
1395 {
1396     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1397
1398     if (other_tc == env->current_tc)
1399         return env->active_tc.DSPControl;
1400     else
1401         return env->tcs[other_tc].DSPControl;
1402 }
1403
1404 void helper_mttgpr(target_ulong t0, uint32_t sel)
1405 {
1406     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1407
1408     if (other_tc == env->current_tc)
1409         env->active_tc.gpr[sel] = t0;
1410     else
1411         env->tcs[other_tc].gpr[sel] = t0;
1412 }
1413
1414 void helper_mttlo(target_ulong t0, uint32_t sel)
1415 {
1416     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1417
1418     if (other_tc == env->current_tc)
1419         env->active_tc.LO[sel] = t0;
1420     else
1421         env->tcs[other_tc].LO[sel] = t0;
1422 }
1423
1424 void helper_mtthi(target_ulong t0, uint32_t sel)
1425 {
1426     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1427
1428     if (other_tc == env->current_tc)
1429         env->active_tc.HI[sel] = t0;
1430     else
1431         env->tcs[other_tc].HI[sel] = t0;
1432 }
1433
1434 void helper_mttacx(target_ulong t0, uint32_t sel)
1435 {
1436     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1437
1438     if (other_tc == env->current_tc)
1439         env->active_tc.ACX[sel] = t0;
1440     else
1441         env->tcs[other_tc].ACX[sel] = t0;
1442 }
1443
1444 void helper_mttdsp(target_ulong t0)
1445 {
1446     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1447
1448     if (other_tc == env->current_tc)
1449         env->active_tc.DSPControl = t0;
1450     else
1451         env->tcs[other_tc].DSPControl = t0;
1452 }
1453
1454 /* MIPS MT functions */
1455 target_ulong helper_dmt(target_ulong t0)
1456 {
1457     // TODO
1458     t0 = 0;
1459     // rt = t0
1460
1461     return t0;
1462 }
1463
1464 target_ulong helper_emt(target_ulong t0)
1465 {
1466     // TODO
1467     t0 = 0;
1468     // rt = t0
1469
1470     return t0;
1471 }
1472
1473 target_ulong helper_dvpe(target_ulong t0)
1474 {
1475     // TODO
1476     t0 = 0;
1477     // rt = t0
1478
1479     return t0;
1480 }
1481
1482 target_ulong helper_evpe(target_ulong t0)
1483 {
1484     // TODO
1485     t0 = 0;
1486     // rt = t0
1487
1488     return t0;
1489 }
1490 #endif /* !CONFIG_USER_ONLY */
1491
1492 void helper_fork(target_ulong t0, target_ulong t1)
1493 {
1494     // t0 = rt, t1 = rs
1495     t0 = 0;
1496     // TODO: store to TC register
1497 }
1498
1499 target_ulong helper_yield(target_ulong t0)
1500 {
1501     if (t0 < 0) {
1502         /* No scheduling policy implemented. */
1503         if (t0 != -2) {
1504             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1505                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1506                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1507                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1508                 helper_raise_exception(EXCP_THREAD);
1509             }
1510         }
1511     } else if (t0 == 0) {
1512         if (0 /* TODO: TC underflow */) {
1513             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1514             helper_raise_exception(EXCP_THREAD);
1515         } else {
1516             // TODO: Deallocate TC
1517         }
1518     } else if (t0 > 0) {
1519         /* Yield qualifier inputs not implemented. */
1520         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1521         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1522         helper_raise_exception(EXCP_THREAD);
1523     }
1524     return env->CP0_YQMask;
1525 }
1526
1527 #ifndef CONFIG_USER_ONLY
1528 /* TLB management */
1529 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1530 {
1531     /* Flush qemu's TLB and discard all shadowed entries.  */
1532     tlb_flush (env, flush_global);
1533     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1534 }
1535
1536 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
1537 {
1538     /* Discard entries from env->tlb[first] onwards.  */
1539     while (env->tlb->tlb_in_use > first) {
1540         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1541     }
1542 }
1543
1544 static void r4k_fill_tlb (int idx)
1545 {
1546     r4k_tlb_t *tlb;
1547
1548     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1549     tlb = &env->tlb->mmu.r4k.tlb[idx];
1550     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1551 #if defined(TARGET_MIPS64)
1552     tlb->VPN &= env->SEGMask;
1553 #endif
1554     tlb->ASID = env->CP0_EntryHi & 0xFF;
1555     tlb->PageMask = env->CP0_PageMask;
1556     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1557     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1558     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1559     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1560     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1561     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1562     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1563     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1564     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1565 }
1566
1567 void r4k_helper_tlbwi (void)
1568 {
1569     int idx;
1570
1571     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1572
1573     /* Discard cached TLB entries.  We could avoid doing this if the
1574        tlbwi is just upgrading access permissions on the current entry;
1575        that might be a further win.  */
1576     r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
1577
1578     r4k_invalidate_tlb(env, idx, 0);
1579     r4k_fill_tlb(idx);
1580 }
1581
1582 void r4k_helper_tlbwr (void)
1583 {
1584     int r = cpu_mips_get_random(env);
1585
1586     r4k_invalidate_tlb(env, r, 1);
1587     r4k_fill_tlb(r);
1588 }
1589
1590 void r4k_helper_tlbp (void)
1591 {
1592     r4k_tlb_t *tlb;
1593     target_ulong mask;
1594     target_ulong tag;
1595     target_ulong VPN;
1596     uint8_t ASID;
1597     int i;
1598
1599     ASID = env->CP0_EntryHi & 0xFF;
1600     for (i = 0; i < env->tlb->nb_tlb; i++) {
1601         tlb = &env->tlb->mmu.r4k.tlb[i];
1602         /* 1k pages are not supported. */
1603         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1604         tag = env->CP0_EntryHi & ~mask;
1605         VPN = tlb->VPN & ~mask;
1606         /* Check ASID, virtual page number & size */
1607         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1608             /* TLB match */
1609             env->CP0_Index = i;
1610             break;
1611         }
1612     }
1613     if (i == env->tlb->nb_tlb) {
1614         /* No match.  Discard any shadow entries, if any of them match.  */
1615         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1616             tlb = &env->tlb->mmu.r4k.tlb[i];
1617             /* 1k pages are not supported. */
1618             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1619             tag = env->CP0_EntryHi & ~mask;
1620             VPN = tlb->VPN & ~mask;
1621             /* Check ASID, virtual page number & size */
1622             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1623                 r4k_mips_tlb_flush_extra (env, i);
1624                 break;
1625             }
1626         }
1627
1628         env->CP0_Index |= 0x80000000;
1629     }
1630 }
1631
1632 void r4k_helper_tlbr (void)
1633 {
1634     r4k_tlb_t *tlb;
1635     uint8_t ASID;
1636     int idx;
1637
1638     ASID = env->CP0_EntryHi & 0xFF;
1639     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1640     tlb = &env->tlb->mmu.r4k.tlb[idx];
1641
1642     /* If this will change the current ASID, flush qemu's TLB.  */
1643     if (ASID != tlb->ASID)
1644         cpu_mips_tlb_flush (env, 1);
1645
1646     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1647
1648     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1649     env->CP0_PageMask = tlb->PageMask;
1650     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1651                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1652     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1653                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1654 }
1655
1656 void helper_tlbwi(void)
1657 {
1658     env->tlb->helper_tlbwi();
1659 }
1660
1661 void helper_tlbwr(void)
1662 {
1663     env->tlb->helper_tlbwr();
1664 }
1665
1666 void helper_tlbp(void)
1667 {
1668     env->tlb->helper_tlbp();
1669 }
1670
1671 void helper_tlbr(void)
1672 {
1673     env->tlb->helper_tlbr();
1674 }
1675
1676 /* Specials */
1677 target_ulong helper_di (void)
1678 {
1679     target_ulong t0 = env->CP0_Status;
1680
1681     env->CP0_Status = t0 & ~(1 << CP0St_IE);
1682     cpu_mips_update_irq(env);
1683
1684     return t0;
1685 }
1686
1687 target_ulong helper_ei (void)
1688 {
1689     target_ulong t0 = env->CP0_Status;
1690
1691     env->CP0_Status = t0 | (1 << CP0St_IE);
1692     cpu_mips_update_irq(env);
1693
1694     return t0;
1695 }
1696
1697 static void debug_pre_eret (void)
1698 {
1699     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1700         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1701                 env->active_tc.PC, env->CP0_EPC);
1702         if (env->CP0_Status & (1 << CP0St_ERL))
1703             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1704         if (env->hflags & MIPS_HFLAG_DM)
1705             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1706         qemu_log("\n");
1707     }
1708 }
1709
1710 static void debug_post_eret (void)
1711 {
1712     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1713         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1714                 env->active_tc.PC, env->CP0_EPC);
1715         if (env->CP0_Status & (1 << CP0St_ERL))
1716             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1717         if (env->hflags & MIPS_HFLAG_DM)
1718             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1719         switch (env->hflags & MIPS_HFLAG_KSU) {
1720         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1721         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1722         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1723         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1724         }
1725     }
1726 }
1727
1728 void helper_eret (void)
1729 {
1730     debug_pre_eret();
1731     if (env->CP0_Status & (1 << CP0St_ERL)) {
1732         env->active_tc.PC = env->CP0_ErrorEPC;
1733         env->CP0_Status &= ~(1 << CP0St_ERL);
1734     } else {
1735         env->active_tc.PC = env->CP0_EPC;
1736         env->CP0_Status &= ~(1 << CP0St_EXL);
1737     }
1738     compute_hflags(env);
1739     debug_post_eret();
1740     env->CP0_LLAddr = 1;
1741 }
1742
1743 void helper_deret (void)
1744 {
1745     debug_pre_eret();
1746     env->active_tc.PC = env->CP0_DEPC;
1747     env->hflags &= MIPS_HFLAG_DM;
1748     compute_hflags(env);
1749     debug_post_eret();
1750     env->CP0_LLAddr = 1;
1751 }
1752 #endif /* !CONFIG_USER_ONLY */
1753
1754 target_ulong helper_rdhwr_cpunum(void)
1755 {
1756     if ((env->hflags & MIPS_HFLAG_CP0) ||
1757         (env->CP0_HWREna & (1 << 0)))
1758         return env->CP0_EBase & 0x3ff;
1759     else
1760         helper_raise_exception(EXCP_RI);
1761
1762     return 0;
1763 }
1764
1765 target_ulong helper_rdhwr_synci_step(void)
1766 {
1767     if ((env->hflags & MIPS_HFLAG_CP0) ||
1768         (env->CP0_HWREna & (1 << 1)))
1769         return env->SYNCI_Step;
1770     else
1771         helper_raise_exception(EXCP_RI);
1772
1773     return 0;
1774 }
1775
1776 target_ulong helper_rdhwr_cc(void)
1777 {
1778     if ((env->hflags & MIPS_HFLAG_CP0) ||
1779         (env->CP0_HWREna & (1 << 2)))
1780         return env->CP0_Count;
1781     else
1782         helper_raise_exception(EXCP_RI);
1783
1784     return 0;
1785 }
1786
1787 target_ulong helper_rdhwr_ccres(void)
1788 {
1789     if ((env->hflags & MIPS_HFLAG_CP0) ||
1790         (env->CP0_HWREna & (1 << 3)))
1791         return env->CCRes;
1792     else
1793         helper_raise_exception(EXCP_RI);
1794
1795     return 0;
1796 }
1797
1798 void helper_pmon (int function)
1799 {
1800     function /= 2;
1801     switch (function) {
1802     case 2: /* TODO: char inbyte(int waitflag); */
1803         if (env->active_tc.gpr[4] == 0)
1804             env->active_tc.gpr[2] = -1;
1805         /* Fall through */
1806     case 11: /* TODO: char inbyte (void); */
1807         env->active_tc.gpr[2] = -1;
1808         break;
1809     case 3:
1810     case 12:
1811         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
1812         break;
1813     case 17:
1814         break;
1815     case 158:
1816         {
1817             unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
1818             printf("%s", fmt);
1819         }
1820         break;
1821     }
1822 }
1823
1824 void helper_wait (void)
1825 {
1826     env->halted = 1;
1827     helper_raise_exception(EXCP_HLT);
1828 }
1829
1830 #if !defined(CONFIG_USER_ONLY)
1831
1832 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1833
1834 #define MMUSUFFIX _mmu
1835 #define ALIGNED_ONLY
1836
1837 #define SHIFT 0
1838 #include "softmmu_template.h"
1839
1840 #define SHIFT 1
1841 #include "softmmu_template.h"
1842
1843 #define SHIFT 2
1844 #include "softmmu_template.h"
1845
1846 #define SHIFT 3
1847 #include "softmmu_template.h"
1848
1849 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1850 {
1851     env->CP0_BadVAddr = addr;
1852     do_restore_state (retaddr);
1853     helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
1854 }
1855
1856 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
1857 {
1858     TranslationBlock *tb;
1859     CPUState *saved_env;
1860     unsigned long pc;
1861     int ret;
1862
1863     /* XXX: hack to restore env in all cases, even if not called from
1864        generated code */
1865     saved_env = env;
1866     env = cpu_single_env;
1867     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
1868     if (ret) {
1869         if (retaddr) {
1870             /* now we have a real cpu fault */
1871             pc = (unsigned long)retaddr;
1872             tb = tb_find_pc(pc);
1873             if (tb) {
1874                 /* the PC is inside the translated code. It means that we have
1875                    a virtual CPU fault */
1876                 cpu_restore_state(tb, env, pc, NULL);
1877             }
1878         }
1879         helper_raise_exception_err(env->exception_index, env->error_code);
1880     }
1881     env = saved_env;
1882 }
1883
1884 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1885                           int unused, int size)
1886 {
1887     if (is_exec)
1888         helper_raise_exception(EXCP_IBE);
1889     else
1890         helper_raise_exception(EXCP_DBE);
1891 }
1892 #endif /* !CONFIG_USER_ONLY */
1893
1894 /* Complex FPU operations which may need stack space. */
1895
1896 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1897 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1898 #define FLOAT_TWO32 make_float32(1 << 30)
1899 #define FLOAT_TWO64 make_float64(1ULL << 62)
1900 #define FLOAT_QNAN32 0x7fbfffff
1901 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
1902 #define FLOAT_SNAN32 0x7fffffff
1903 #define FLOAT_SNAN64 0x7fffffffffffffffULL
1904
1905 /* convert MIPS rounding mode in FCR31 to IEEE library */
1906 unsigned int ieee_rm[] = {
1907     float_round_nearest_even,
1908     float_round_to_zero,
1909     float_round_up,
1910     float_round_down
1911 };
1912
1913 #define RESTORE_ROUNDING_MODE \
1914     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1915
1916 target_ulong helper_cfc1 (uint32_t reg)
1917 {
1918     target_ulong t0;
1919
1920     switch (reg) {
1921     case 0:
1922         t0 = (int32_t)env->active_fpu.fcr0;
1923         break;
1924     case 25:
1925         t0 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
1926         break;
1927     case 26:
1928         t0 = env->active_fpu.fcr31 & 0x0003f07c;
1929         break;
1930     case 28:
1931         t0 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
1932         break;
1933     default:
1934         t0 = (int32_t)env->active_fpu.fcr31;
1935         break;
1936     }
1937
1938     return t0;
1939 }
1940
1941 void helper_ctc1 (target_ulong t0, uint32_t reg)
1942 {
1943     switch(reg) {
1944     case 25:
1945         if (t0 & 0xffffff00)
1946             return;
1947         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) |
1948                      ((t0 & 0x1) << 23);
1949         break;
1950     case 26:
1951         if (t0 & 0x007c0000)
1952             return;
1953         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c);
1954         break;
1955     case 28:
1956         if (t0 & 0x007c0000)
1957             return;
1958         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (t0 & 0x00000f83) |
1959                      ((t0 & 0x4) << 22);
1960         break;
1961     case 31:
1962         if (t0 & 0x007c0000)
1963             return;
1964         env->active_fpu.fcr31 = t0;
1965         break;
1966     default:
1967         return;
1968     }
1969     /* set rounding mode */
1970     RESTORE_ROUNDING_MODE;
1971     set_float_exception_flags(0, &env->active_fpu.fp_status);
1972     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
1973         helper_raise_exception(EXCP_FPE);
1974 }
1975
1976 static inline char ieee_ex_to_mips(char xcpt)
1977 {
1978     return (xcpt & float_flag_inexact) >> 5 |
1979            (xcpt & float_flag_underflow) >> 3 |
1980            (xcpt & float_flag_overflow) >> 1 |
1981            (xcpt & float_flag_divbyzero) << 1 |
1982            (xcpt & float_flag_invalid) << 4;
1983 }
1984
1985 static inline char mips_ex_to_ieee(char xcpt)
1986 {
1987     return (xcpt & FP_INEXACT) << 5 |
1988            (xcpt & FP_UNDERFLOW) << 3 |
1989            (xcpt & FP_OVERFLOW) << 1 |
1990            (xcpt & FP_DIV0) >> 1 |
1991            (xcpt & FP_INVALID) >> 4;
1992 }
1993
1994 static inline void update_fcr31(void)
1995 {
1996     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
1997
1998     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
1999     if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
2000         helper_raise_exception(EXCP_FPE);
2001     else
2002         UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2003 }
2004
2005 /* Float support.
2006    Single precition routines have a "s" suffix, double precision a
2007    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2008    paired single lower "pl", paired single upper "pu".  */
2009
2010 /* unary operations, modifying fp status  */
2011 uint64_t helper_float_sqrt_d(uint64_t fdt0)
2012 {
2013     return float64_sqrt(fdt0, &env->active_fpu.fp_status);
2014 }
2015
2016 uint32_t helper_float_sqrt_s(uint32_t fst0)
2017 {
2018     return float32_sqrt(fst0, &env->active_fpu.fp_status);
2019 }
2020
2021 uint64_t helper_float_cvtd_s(uint32_t fst0)
2022 {
2023     uint64_t fdt2;
2024
2025     set_float_exception_flags(0, &env->active_fpu.fp_status);
2026     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2027     update_fcr31();
2028     return fdt2;
2029 }
2030
2031 uint64_t helper_float_cvtd_w(uint32_t wt0)
2032 {
2033     uint64_t fdt2;
2034
2035     set_float_exception_flags(0, &env->active_fpu.fp_status);
2036     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2037     update_fcr31();
2038     return fdt2;
2039 }
2040
2041 uint64_t helper_float_cvtd_l(uint64_t dt0)
2042 {
2043     uint64_t fdt2;
2044
2045     set_float_exception_flags(0, &env->active_fpu.fp_status);
2046     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2047     update_fcr31();
2048     return fdt2;
2049 }
2050
2051 uint64_t helper_float_cvtl_d(uint64_t fdt0)
2052 {
2053     uint64_t dt2;
2054
2055     set_float_exception_flags(0, &env->active_fpu.fp_status);
2056     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2057     update_fcr31();
2058     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2059         dt2 = FLOAT_SNAN64;
2060     return dt2;
2061 }
2062
2063 uint64_t helper_float_cvtl_s(uint32_t fst0)
2064 {
2065     uint64_t dt2;
2066
2067     set_float_exception_flags(0, &env->active_fpu.fp_status);
2068     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2069     update_fcr31();
2070     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2071         dt2 = FLOAT_SNAN64;
2072     return dt2;
2073 }
2074
2075 uint64_t helper_float_cvtps_pw(uint64_t dt0)
2076 {
2077     uint32_t fst2;
2078     uint32_t fsth2;
2079
2080     set_float_exception_flags(0, &env->active_fpu.fp_status);
2081     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2082     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2083     update_fcr31();
2084     return ((uint64_t)fsth2 << 32) | fst2;
2085 }
2086
2087 uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
2088 {
2089     uint32_t wt2;
2090     uint32_t wth2;
2091
2092     set_float_exception_flags(0, &env->active_fpu.fp_status);
2093     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2094     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2095     update_fcr31();
2096     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
2097         wt2 = FLOAT_SNAN32;
2098         wth2 = FLOAT_SNAN32;
2099     }
2100     return ((uint64_t)wth2 << 32) | wt2;
2101 }
2102
2103 uint32_t helper_float_cvts_d(uint64_t fdt0)
2104 {
2105     uint32_t fst2;
2106
2107     set_float_exception_flags(0, &env->active_fpu.fp_status);
2108     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2109     update_fcr31();
2110     return fst2;
2111 }
2112
2113 uint32_t helper_float_cvts_w(uint32_t wt0)
2114 {
2115     uint32_t fst2;
2116
2117     set_float_exception_flags(0, &env->active_fpu.fp_status);
2118     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2119     update_fcr31();
2120     return fst2;
2121 }
2122
2123 uint32_t helper_float_cvts_l(uint64_t dt0)
2124 {
2125     uint32_t fst2;
2126
2127     set_float_exception_flags(0, &env->active_fpu.fp_status);
2128     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2129     update_fcr31();
2130     return fst2;
2131 }
2132
2133 uint32_t helper_float_cvts_pl(uint32_t wt0)
2134 {
2135     uint32_t wt2;
2136
2137     set_float_exception_flags(0, &env->active_fpu.fp_status);
2138     wt2 = wt0;
2139     update_fcr31();
2140     return wt2;
2141 }
2142
2143 uint32_t helper_float_cvts_pu(uint32_t wth0)
2144 {
2145     uint32_t wt2;
2146
2147     set_float_exception_flags(0, &env->active_fpu.fp_status);
2148     wt2 = wth0;
2149     update_fcr31();
2150     return wt2;
2151 }
2152
2153 uint32_t helper_float_cvtw_s(uint32_t fst0)
2154 {
2155     uint32_t wt2;
2156
2157     set_float_exception_flags(0, &env->active_fpu.fp_status);
2158     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2159     update_fcr31();
2160     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2161         wt2 = FLOAT_SNAN32;
2162     return wt2;
2163 }
2164
2165 uint32_t helper_float_cvtw_d(uint64_t fdt0)
2166 {
2167     uint32_t wt2;
2168
2169     set_float_exception_flags(0, &env->active_fpu.fp_status);
2170     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2171     update_fcr31();
2172     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2173         wt2 = FLOAT_SNAN32;
2174     return wt2;
2175 }
2176
2177 uint64_t helper_float_roundl_d(uint64_t fdt0)
2178 {
2179     uint64_t dt2;
2180
2181     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2182     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2183     RESTORE_ROUNDING_MODE;
2184     update_fcr31();
2185     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2186         dt2 = FLOAT_SNAN64;
2187     return dt2;
2188 }
2189
2190 uint64_t helper_float_roundl_s(uint32_t fst0)
2191 {
2192     uint64_t dt2;
2193
2194     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2195     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2196     RESTORE_ROUNDING_MODE;
2197     update_fcr31();
2198     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2199         dt2 = FLOAT_SNAN64;
2200     return dt2;
2201 }
2202
2203 uint32_t helper_float_roundw_d(uint64_t fdt0)
2204 {
2205     uint32_t wt2;
2206
2207     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2208     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2209     RESTORE_ROUNDING_MODE;
2210     update_fcr31();
2211     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2212         wt2 = FLOAT_SNAN32;
2213     return wt2;
2214 }
2215
2216 uint32_t helper_float_roundw_s(uint32_t fst0)
2217 {
2218     uint32_t wt2;
2219
2220     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2221     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2222     RESTORE_ROUNDING_MODE;
2223     update_fcr31();
2224     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2225         wt2 = FLOAT_SNAN32;
2226     return wt2;
2227 }
2228
2229 uint64_t helper_float_truncl_d(uint64_t fdt0)
2230 {
2231     uint64_t dt2;
2232
2233     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2234     update_fcr31();
2235     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2236         dt2 = FLOAT_SNAN64;
2237     return dt2;
2238 }
2239
2240 uint64_t helper_float_truncl_s(uint32_t fst0)
2241 {
2242     uint64_t dt2;
2243
2244     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2245     update_fcr31();
2246     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2247         dt2 = FLOAT_SNAN64;
2248     return dt2;
2249 }
2250
2251 uint32_t helper_float_truncw_d(uint64_t fdt0)
2252 {
2253     uint32_t wt2;
2254
2255     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2256     update_fcr31();
2257     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2258         wt2 = FLOAT_SNAN32;
2259     return wt2;
2260 }
2261
2262 uint32_t helper_float_truncw_s(uint32_t fst0)
2263 {
2264     uint32_t wt2;
2265
2266     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2267     update_fcr31();
2268     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2269         wt2 = FLOAT_SNAN32;
2270     return wt2;
2271 }
2272
2273 uint64_t helper_float_ceill_d(uint64_t fdt0)
2274 {
2275     uint64_t dt2;
2276
2277     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2278     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2279     RESTORE_ROUNDING_MODE;
2280     update_fcr31();
2281     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2282         dt2 = FLOAT_SNAN64;
2283     return dt2;
2284 }
2285
2286 uint64_t helper_float_ceill_s(uint32_t fst0)
2287 {
2288     uint64_t dt2;
2289
2290     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2291     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2292     RESTORE_ROUNDING_MODE;
2293     update_fcr31();
2294     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2295         dt2 = FLOAT_SNAN64;
2296     return dt2;
2297 }
2298
2299 uint32_t helper_float_ceilw_d(uint64_t fdt0)
2300 {
2301     uint32_t wt2;
2302
2303     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2304     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2305     RESTORE_ROUNDING_MODE;
2306     update_fcr31();
2307     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2308         wt2 = FLOAT_SNAN32;
2309     return wt2;
2310 }
2311
2312 uint32_t helper_float_ceilw_s(uint32_t fst0)
2313 {
2314     uint32_t wt2;
2315
2316     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2317     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2318     RESTORE_ROUNDING_MODE;
2319     update_fcr31();
2320     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2321         wt2 = FLOAT_SNAN32;
2322     return wt2;
2323 }
2324
2325 uint64_t helper_float_floorl_d(uint64_t fdt0)
2326 {
2327     uint64_t dt2;
2328
2329     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2330     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2331     RESTORE_ROUNDING_MODE;
2332     update_fcr31();
2333     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2334         dt2 = FLOAT_SNAN64;
2335     return dt2;
2336 }
2337
2338 uint64_t helper_float_floorl_s(uint32_t fst0)
2339 {
2340     uint64_t dt2;
2341
2342     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2343     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2344     RESTORE_ROUNDING_MODE;
2345     update_fcr31();
2346     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2347         dt2 = FLOAT_SNAN64;
2348     return dt2;
2349 }
2350
2351 uint32_t helper_float_floorw_d(uint64_t fdt0)
2352 {
2353     uint32_t wt2;
2354
2355     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2356     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2357     RESTORE_ROUNDING_MODE;
2358     update_fcr31();
2359     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2360         wt2 = FLOAT_SNAN32;
2361     return wt2;
2362 }
2363
2364 uint32_t helper_float_floorw_s(uint32_t fst0)
2365 {
2366     uint32_t wt2;
2367
2368     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2369     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2370     RESTORE_ROUNDING_MODE;
2371     update_fcr31();
2372     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2373         wt2 = FLOAT_SNAN32;
2374     return wt2;
2375 }
2376
2377 /* unary operations, not modifying fp status  */
2378 #define FLOAT_UNOP(name)                                       \
2379 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2380 {                                                              \
2381     return float64_ ## name(fdt0);                             \
2382 }                                                              \
2383 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2384 {                                                              \
2385     return float32_ ## name(fst0);                             \
2386 }                                                              \
2387 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2388 {                                                              \
2389     uint32_t wt0;                                              \
2390     uint32_t wth0;                                             \
2391                                                                \
2392     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2393     wth0 = float32_ ## name(fdt0 >> 32);                       \
2394     return ((uint64_t)wth0 << 32) | wt0;                       \
2395 }
2396 FLOAT_UNOP(abs)
2397 FLOAT_UNOP(chs)
2398 #undef FLOAT_UNOP
2399
2400 /* MIPS specific unary operations */
2401 uint64_t helper_float_recip_d(uint64_t fdt0)
2402 {
2403     uint64_t fdt2;
2404
2405     set_float_exception_flags(0, &env->active_fpu.fp_status);
2406     fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2407     update_fcr31();
2408     return fdt2;
2409 }
2410
2411 uint32_t helper_float_recip_s(uint32_t fst0)
2412 {
2413     uint32_t fst2;
2414
2415     set_float_exception_flags(0, &env->active_fpu.fp_status);
2416     fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2417     update_fcr31();
2418     return fst2;
2419 }
2420
2421 uint64_t helper_float_rsqrt_d(uint64_t fdt0)
2422 {
2423     uint64_t fdt2;
2424
2425     set_float_exception_flags(0, &env->active_fpu.fp_status);
2426     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2427     fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2428     update_fcr31();
2429     return fdt2;
2430 }
2431
2432 uint32_t helper_float_rsqrt_s(uint32_t fst0)
2433 {
2434     uint32_t fst2;
2435
2436     set_float_exception_flags(0, &env->active_fpu.fp_status);
2437     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2438     fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2439     update_fcr31();
2440     return fst2;
2441 }
2442
2443 uint64_t helper_float_recip1_d(uint64_t fdt0)
2444 {
2445     uint64_t fdt2;
2446
2447     set_float_exception_flags(0, &env->active_fpu.fp_status);
2448     fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2449     update_fcr31();
2450     return fdt2;
2451 }
2452
2453 uint32_t helper_float_recip1_s(uint32_t fst0)
2454 {
2455     uint32_t fst2;
2456
2457     set_float_exception_flags(0, &env->active_fpu.fp_status);
2458     fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2459     update_fcr31();
2460     return fst2;
2461 }
2462
2463 uint64_t helper_float_recip1_ps(uint64_t fdt0)
2464 {
2465     uint32_t fst2;
2466     uint32_t fsth2;
2467
2468     set_float_exception_flags(0, &env->active_fpu.fp_status);
2469     fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2470     fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
2471     update_fcr31();
2472     return ((uint64_t)fsth2 << 32) | fst2;
2473 }
2474
2475 uint64_t helper_float_rsqrt1_d(uint64_t fdt0)
2476 {
2477     uint64_t fdt2;
2478
2479     set_float_exception_flags(0, &env->active_fpu.fp_status);
2480     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2481     fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2482     update_fcr31();
2483     return fdt2;
2484 }
2485
2486 uint32_t helper_float_rsqrt1_s(uint32_t fst0)
2487 {
2488     uint32_t fst2;
2489
2490     set_float_exception_flags(0, &env->active_fpu.fp_status);
2491     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2492     fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2493     update_fcr31();
2494     return fst2;
2495 }
2496
2497 uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
2498 {
2499     uint32_t fst2;
2500     uint32_t fsth2;
2501
2502     set_float_exception_flags(0, &env->active_fpu.fp_status);
2503     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2504     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2505     fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2506     fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
2507     update_fcr31();
2508     return ((uint64_t)fsth2 << 32) | fst2;
2509 }
2510
2511 #define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
2512
2513 /* binary operations */
2514 #define FLOAT_BINOP(name)                                          \
2515 uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1)     \
2516 {                                                                  \
2517     uint64_t dt2;                                                  \
2518                                                                    \
2519     set_float_exception_flags(0, &env->active_fpu.fp_status);            \
2520     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
2521     update_fcr31();                                                \
2522     if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID)                \
2523         dt2 = FLOAT_QNAN64;                                        \
2524     return dt2;                                                    \
2525 }                                                                  \
2526                                                                    \
2527 uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1)     \
2528 {                                                                  \
2529     uint32_t wt2;                                                  \
2530                                                                    \
2531     set_float_exception_flags(0, &env->active_fpu.fp_status);            \
2532     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2533     update_fcr31();                                                \
2534     if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID)                \
2535         wt2 = FLOAT_QNAN32;                                        \
2536     return wt2;                                                    \
2537 }                                                                  \
2538                                                                    \
2539 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1)    \
2540 {                                                                  \
2541     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
2542     uint32_t fsth0 = fdt0 >> 32;                                   \
2543     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
2544     uint32_t fsth1 = fdt1 >> 32;                                   \
2545     uint32_t wt2;                                                  \
2546     uint32_t wth2;                                                 \
2547                                                                    \
2548     set_float_exception_flags(0, &env->active_fpu.fp_status);            \
2549     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2550     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
2551     update_fcr31();                                                \
2552     if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) {              \
2553         wt2 = FLOAT_QNAN32;                                        \
2554         wth2 = FLOAT_QNAN32;                                       \
2555     }                                                              \
2556     return ((uint64_t)wth2 << 32) | wt2;                           \
2557 }
2558
2559 FLOAT_BINOP(add)
2560 FLOAT_BINOP(sub)
2561 FLOAT_BINOP(mul)
2562 FLOAT_BINOP(div)
2563 #undef FLOAT_BINOP
2564
2565 /* ternary operations */
2566 #define FLOAT_TERNOP(name1, name2)                                        \
2567 uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1,  \
2568                                            uint64_t fdt2)                 \
2569 {                                                                         \
2570     fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status);          \
2571     return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status);          \
2572 }                                                                         \
2573                                                                           \
2574 uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1,  \
2575                                            uint32_t fst2)                 \
2576 {                                                                         \
2577     fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
2578     return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
2579 }                                                                         \
2580                                                                           \
2581 uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
2582                                             uint64_t fdt2)                \
2583 {                                                                         \
2584     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                                    \
2585     uint32_t fsth0 = fdt0 >> 32;                                          \
2586     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                                    \
2587     uint32_t fsth1 = fdt1 >> 32;                                          \
2588     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                                    \
2589     uint32_t fsth2 = fdt2 >> 32;                                          \
2590                                                                           \
2591     fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
2592     fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status);       \
2593     fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
2594     fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status);       \
2595     return ((uint64_t)fsth2 << 32) | fst2;                                \
2596 }
2597
2598 FLOAT_TERNOP(mul, add)
2599 FLOAT_TERNOP(mul, sub)
2600 #undef FLOAT_TERNOP
2601
2602 /* negated ternary operations */
2603 #define FLOAT_NTERNOP(name1, name2)                                       \
2604 uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2605                                            uint64_t fdt2)                 \
2606 {                                                                         \
2607     fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status);          \
2608     fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status);          \
2609     return float64_chs(fdt2);                                             \
2610 }                                                                         \
2611                                                                           \
2612 uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2613                                            uint32_t fst2)                 \
2614 {                                                                         \
2615     fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
2616     fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
2617     return float32_chs(fst2);                                             \
2618 }                                                                         \
2619                                                                           \
2620 uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
2621                                            uint64_t fdt2)                 \
2622 {                                                                         \
2623     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                                    \
2624     uint32_t fsth0 = fdt0 >> 32;                                          \
2625     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                                    \
2626     uint32_t fsth1 = fdt1 >> 32;                                          \
2627     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                                    \
2628     uint32_t fsth2 = fdt2 >> 32;                                          \
2629                                                                           \
2630     fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
2631     fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status);       \
2632     fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
2633     fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status);       \
2634     fst2 = float32_chs(fst2);                                             \
2635     fsth2 = float32_chs(fsth2);                                           \
2636     return ((uint64_t)fsth2 << 32) | fst2;                                \
2637 }
2638
2639 FLOAT_NTERNOP(mul, add)
2640 FLOAT_NTERNOP(mul, sub)
2641 #undef FLOAT_NTERNOP
2642
2643 /* MIPS specific binary operations */
2644 uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
2645 {
2646     set_float_exception_flags(0, &env->active_fpu.fp_status);
2647     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2648     fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
2649     update_fcr31();
2650     return fdt2;
2651 }
2652
2653 uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2)
2654 {
2655     set_float_exception_flags(0, &env->active_fpu.fp_status);
2656     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2657     fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2658     update_fcr31();
2659     return fst2;
2660 }
2661
2662 uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
2663 {
2664     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2665     uint32_t fsth0 = fdt0 >> 32;
2666     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2667     uint32_t fsth2 = fdt2 >> 32;
2668
2669     set_float_exception_flags(0, &env->active_fpu.fp_status);
2670     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2671     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2672     fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2673     fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
2674     update_fcr31();
2675     return ((uint64_t)fsth2 << 32) | fst2;
2676 }
2677
2678 uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
2679 {
2680     set_float_exception_flags(0, &env->active_fpu.fp_status);
2681     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2682     fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
2683     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2684     update_fcr31();
2685     return fdt2;
2686 }
2687
2688 uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
2689 {
2690     set_float_exception_flags(0, &env->active_fpu.fp_status);
2691     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2692     fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2693     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2694     update_fcr31();
2695     return fst2;
2696 }
2697
2698 uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
2699 {
2700     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2701     uint32_t fsth0 = fdt0 >> 32;
2702     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2703     uint32_t fsth2 = fdt2 >> 32;
2704
2705     set_float_exception_flags(0, &env->active_fpu.fp_status);
2706     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2707     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2708     fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2709     fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
2710     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2711     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2712     update_fcr31();
2713     return ((uint64_t)fsth2 << 32) | fst2;
2714 }
2715
2716 uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
2717 {
2718     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2719     uint32_t fsth0 = fdt0 >> 32;
2720     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2721     uint32_t fsth1 = fdt1 >> 32;
2722     uint32_t fst2;
2723     uint32_t fsth2;
2724
2725     set_float_exception_flags(0, &env->active_fpu.fp_status);
2726     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2727     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
2728     update_fcr31();
2729     return ((uint64_t)fsth2 << 32) | fst2;
2730 }
2731
2732 uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
2733 {
2734     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2735     uint32_t fsth0 = fdt0 >> 32;
2736     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2737     uint32_t fsth1 = fdt1 >> 32;
2738     uint32_t fst2;
2739     uint32_t fsth2;
2740
2741     set_float_exception_flags(0, &env->active_fpu.fp_status);
2742     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
2743     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
2744     update_fcr31();
2745     return ((uint64_t)fsth2 << 32) | fst2;
2746 }
2747
2748 /* compare operations */
2749 #define FOP_COND_D(op, cond)                                   \
2750 void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc)    \
2751 {                                                              \
2752     int c = cond;                                              \
2753     update_fcr31();                                            \
2754     if (c)                                                     \
2755         SET_FP_COND(cc, env->active_fpu);                      \
2756     else                                                       \
2757         CLEAR_FP_COND(cc, env->active_fpu);                    \
2758 }                                                              \
2759 void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2760 {                                                              \
2761     int c;                                                     \
2762     fdt0 = float64_abs(fdt0);                                  \
2763     fdt1 = float64_abs(fdt1);                                  \
2764     c = cond;                                                  \
2765     update_fcr31();                                            \
2766     if (c)                                                     \
2767         SET_FP_COND(cc, env->active_fpu);                      \
2768     else                                                       \
2769         CLEAR_FP_COND(cc, env->active_fpu);                    \
2770 }
2771
2772 static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
2773 {
2774     if (float64_is_signaling_nan(a) ||
2775         float64_is_signaling_nan(b) ||
2776         (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2777         float_raise(float_flag_invalid, status);
2778         return 1;
2779     } else if (float64_is_nan(a) || float64_is_nan(b)) {
2780         return 1;
2781     } else {
2782         return 0;
2783     }
2784 }
2785
2786 /* NOTE: the comma operator will make "cond" to eval to false,
2787  * but float*_is_unordered() is still called. */
2788 FOP_COND_D(f,   (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2789 FOP_COND_D(un,  float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
2790 FOP_COND_D(eq,  !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2791 FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2792 FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2793 FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2794 FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2795 FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2796 /* NOTE: the comma operator will make "cond" to eval to false,
2797  * but float*_is_unordered() is still called. */
2798 FOP_COND_D(sf,  (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2799 FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
2800 FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2801 FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2802 FOP_COND_D(lt,  !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2803 FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2804 FOP_COND_D(le,  !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2805 FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2806
2807 #define FOP_COND_S(op, cond)                                   \
2808 void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc)    \
2809 {                                                              \
2810     int c = cond;                                              \
2811     update_fcr31();                                            \
2812     if (c)                                                     \
2813         SET_FP_COND(cc, env->active_fpu);                      \
2814     else                                                       \
2815         CLEAR_FP_COND(cc, env->active_fpu);                    \
2816 }                                                              \
2817 void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2818 {                                                              \
2819     int c;                                                     \
2820     fst0 = float32_abs(fst0);                                  \
2821     fst1 = float32_abs(fst1);                                  \
2822     c = cond;                                                  \
2823     update_fcr31();                                            \
2824     if (c)                                                     \
2825         SET_FP_COND(cc, env->active_fpu);                      \
2826     else                                                       \
2827         CLEAR_FP_COND(cc, env->active_fpu);                    \
2828 }
2829
2830 static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
2831 {
2832     if (float32_is_signaling_nan(a) ||
2833         float32_is_signaling_nan(b) ||
2834         (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2835         float_raise(float_flag_invalid, status);
2836         return 1;
2837     } else if (float32_is_nan(a) || float32_is_nan(b)) {
2838         return 1;
2839     } else {
2840         return 0;
2841     }
2842 }
2843
2844 /* NOTE: the comma operator will make "cond" to eval to false,
2845  * but float*_is_unordered() is still called. */
2846 FOP_COND_S(f,   (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
2847 FOP_COND_S(un,  float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
2848 FOP_COND_S(eq,  !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2849 FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2850 FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2851 FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2852 FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2853 FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2854 /* NOTE: the comma operator will make "cond" to eval to false,
2855  * but float*_is_unordered() is still called. */
2856 FOP_COND_S(sf,  (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
2857 FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
2858 FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2859 FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2860 FOP_COND_S(lt,  !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2861 FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2862 FOP_COND_S(le,  !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2863 FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2864
2865 #define FOP_COND_PS(op, condl, condh)                           \
2866 void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc)    \
2867 {                                                               \
2868     uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF);             \
2869     uint32_t fsth0 = float32_abs(fdt0 >> 32);                   \
2870     uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF);             \
2871     uint32_t fsth1 = float32_abs(fdt1 >> 32);                   \
2872     int cl = condl;                                             \
2873     int ch = condh;                                             \
2874                                                                 \
2875     update_fcr31();                                             \
2876     if (cl)                                                     \
2877         SET_FP_COND(cc, env->active_fpu);                       \
2878     else                                                        \
2879         CLEAR_FP_COND(cc, env->active_fpu);                     \
2880     if (ch)                                                     \
2881         SET_FP_COND(cc + 1, env->active_fpu);                   \
2882     else                                                        \
2883         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
2884 }                                                               \
2885 void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2886 {                                                               \
2887     uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF);             \
2888     uint32_t fsth0 = float32_abs(fdt0 >> 32);                   \
2889     uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF);             \
2890     uint32_t fsth1 = float32_abs(fdt1 >> 32);                   \
2891     int cl = condl;                                             \
2892     int ch = condh;                                             \
2893                                                                 \
2894     update_fcr31();                                             \
2895     if (cl)                                                     \
2896         SET_FP_COND(cc, env->active_fpu);                       \
2897     else                                                        \
2898         CLEAR_FP_COND(cc, env->active_fpu);                     \
2899     if (ch)                                                     \
2900         SET_FP_COND(cc + 1, env->active_fpu);                   \
2901     else                                                        \
2902         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
2903 }
2904
2905 /* NOTE: the comma operator will make "cond" to eval to false,
2906  * but float*_is_unordered() is still called. */
2907 FOP_COND_PS(f,   (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
2908                  (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2909 FOP_COND_PS(un,  float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
2910                  float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
2911 FOP_COND_PS(eq,  !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)   && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2912                  !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2913 FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2914                  float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2915 FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)   && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2916                  !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2917 FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2918                  float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2919 FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)   && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2920                  !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2921 FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2922                  float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2923 /* NOTE: the comma operator will make "cond" to eval to false,
2924  * but float*_is_unordered() is still called. */
2925 FOP_COND_PS(sf,  (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
2926                  (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2927 FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
2928                  float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
2929 FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)   && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2930                  !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2931 FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2932                  float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2933 FOP_COND_PS(lt,  !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)   && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2934                  !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2935 FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2936                  float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2937 FOP_COND_PS(le,  !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)   && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2938                  !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2939 FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2940                  float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))