target-mips/op_mem.c

   1 /*
   2  *  MIPS emulation memory micro-operations for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* Standard loads and stores */
  22 void glue(op_lb, MEMSUFFIX) (void)
  23 {
  24     T0 = glue(ldsb, MEMSUFFIX)(T0);
  25     RETURN();
  26 }
  27
  28 void glue(op_lbu, MEMSUFFIX) (void)
  29 {
  30     T0 = glue(ldub, MEMSUFFIX)(T0);
  31     RETURN();
  32 }
  33
  34 void glue(op_sb, MEMSUFFIX) (void)
  35 {
  36     glue(stb, MEMSUFFIX)(T0, T1);
  37     RETURN();
  38 }
  39
  40 void glue(op_lh, MEMSUFFIX) (void)
  41 {
  42     T0 = glue(ldsw, MEMSUFFIX)(T0);
  43     RETURN();
  44 }
  45
  46 void glue(op_lhu, MEMSUFFIX) (void)
  47 {
  48     T0 = glue(lduw, MEMSUFFIX)(T0);
  49     RETURN();
  50 }
  51
  52 void glue(op_sh, MEMSUFFIX) (void)
  53 {
  54     glue(stw, MEMSUFFIX)(T0, T1);
  55     RETURN();
  56 }
  57
  58 void glue(op_lw, MEMSUFFIX) (void)
  59 {
  60     T0 = glue(ldl, MEMSUFFIX)(T0);
  61     RETURN();
  62 }
  63
  64 void glue(op_lwu, MEMSUFFIX) (void)
  65 {
  66     T0 = glue(ldl, MEMSUFFIX)(T0);
  67     RETURN();
  68 }
  69
  70 void glue(op_sw, MEMSUFFIX) (void)
  71 {
  72     glue(stl, MEMSUFFIX)(T0, T1);
  73     RETURN();
  74 }
  75
  76 /* "half" load and stores.  We must do the memory access inline,
  77    or fault handling won't work.  */
  78 /* XXX: This is broken, CP0_BADVADDR has the wrong (aligned) value. */
  79 void glue(op_lwl, MEMSUFFIX) (void)
  80 {
  81     uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
  82     CALL_FROM_TB1(glue(do_lwl, MEMSUFFIX), tmp);
  83     RETURN();
  84 }
  85
  86 void glue(op_lwr, MEMSUFFIX) (void)
  87 {
  88     uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
  89     CALL_FROM_TB1(glue(do_lwr, MEMSUFFIX), tmp);
  90     RETURN();
  91 }
  92
  93 void glue(op_swl, MEMSUFFIX) (void)
  94 {
  95     uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
  96     tmp = CALL_FROM_TB1(glue(do_swl, MEMSUFFIX), tmp);
  97     glue(stl, MEMSUFFIX)(T0 & ~3, tmp);
  98     RETURN();
  99 }
 100
 101 void glue(op_swr, MEMSUFFIX) (void)
 102 {
 103     uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
 104     tmp = CALL_FROM_TB1(glue(do_swr, MEMSUFFIX), tmp);
 105     glue(stl, MEMSUFFIX)(T0 & ~3, tmp);
 106     RETURN();
 107 }
 108
 109 void glue(op_ll, MEMSUFFIX) (void)
 110 {
 111     T1 = T0;
 112     T0 = glue(ldl, MEMSUFFIX)(T0);
 113     env->CP0_LLAddr = T1;
 114     RETURN();
 115 }
 116
 117 void glue(op_sc, MEMSUFFIX) (void)
 118 {
 119     CALL_FROM_TB0(dump_sc);
 120     if (T0 == env->CP0_LLAddr) {
 121         glue(stl, MEMSUFFIX)(T0, T1);
 122         T0 = 1;
 123     } else {
 124         T0 = 0;
 125     }
 126     RETURN();
 127 }
 128
 129 #ifdef TARGET_MIPS64
 130 void glue(op_ld, MEMSUFFIX) (void)
 131 {
 132     T0 = glue(ldq, MEMSUFFIX)(T0);
 133     RETURN();
 134 }
 135
 136 void glue(op_sd, MEMSUFFIX) (void)
 137 {
 138     glue(stq, MEMSUFFIX)(T0, T1);
 139     RETURN();
 140 }
 141
 142 /* "half" load and stores.  We must do the memory access inline,
 143    or fault handling won't work.  */
 144 void glue(op_ldl, MEMSUFFIX) (void)
 145 {
 146     target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
 147     CALL_FROM_TB1(glue(do_ldl, MEMSUFFIX), tmp);
 148     RETURN();
 149 }
 150
 151 void glue(op_ldr, MEMSUFFIX) (void)
 152 {
 153     target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
 154     CALL_FROM_TB1(glue(do_ldr, MEMSUFFIX), tmp);
 155     RETURN();
 156 }
 157
 158 void glue(op_sdl, MEMSUFFIX) (void)
 159 {
 160     target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
 161     tmp = CALL_FROM_TB1(glue(do_sdl, MEMSUFFIX), tmp);
 162     glue(stq, MEMSUFFIX)(T0 & ~7, tmp);
 163     RETURN();
 164 }
 165
 166 void glue(op_sdr, MEMSUFFIX) (void)
 167 {
 168     target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
 169     tmp = CALL_FROM_TB1(glue(do_sdr, MEMSUFFIX), tmp);
 170     glue(stq, MEMSUFFIX)(T0 & ~7, tmp);
 171     RETURN();
 172 }
 173
 174 void glue(op_lld, MEMSUFFIX) (void)
 175 {
 176     T1 = T0;
 177     T0 = glue(ldq, MEMSUFFIX)(T0);
 178     env->CP0_LLAddr = T1;
 179     RETURN();
 180 }
 181
 182 void glue(op_scd, MEMSUFFIX) (void)
 183 {
 184     CALL_FROM_TB0(dump_sc);
 185     if (T0 == env->CP0_LLAddr) {
 186         glue(stq, MEMSUFFIX)(T0, T1);
 187         T0 = 1;
 188     } else {
 189         T0 = 0;
 190     }
 191     RETURN();
 192 }
 193 #endif /* TARGET_MIPS64 */
 194
 195 void glue(op_lwc1, MEMSUFFIX) (void)
 196 {
 197     WT0 = glue(ldl, MEMSUFFIX)(T0);
 198     RETURN();
 199 }
 200 void glue(op_swc1, MEMSUFFIX) (void)
 201 {
 202     glue(stl, MEMSUFFIX)(T0, WT0);
 203     RETURN();
 204 }
 205 void glue(op_ldc1, MEMSUFFIX) (void)
 206 {
 207     DT0 = glue(ldq, MEMSUFFIX)(T0);
 208     RETURN();
 209 }
 210 void glue(op_sdc1, MEMSUFFIX) (void)
 211 {
 212     glue(stq, MEMSUFFIX)(T0, DT0);
 213     RETURN();
 214 }