]>
git.proxmox.com Git - qemu.git/blob - target-mips/translate.c
2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
32 #include "qemu-common.h"
38 //#define MIPS_DEBUG_DISAS
39 //#define MIPS_DEBUG_SIGN_EXTENSIONS
41 /* MIPS major opcodes */
42 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
45 /* indirect opcode tables */
46 OPC_SPECIAL
= (0x00 << 26),
47 OPC_REGIMM
= (0x01 << 26),
48 OPC_CP0
= (0x10 << 26),
49 OPC_CP1
= (0x11 << 26),
50 OPC_CP2
= (0x12 << 26),
51 OPC_CP3
= (0x13 << 26),
52 OPC_SPECIAL2
= (0x1C << 26),
53 OPC_SPECIAL3
= (0x1F << 26),
54 /* arithmetic with immediate */
55 OPC_ADDI
= (0x08 << 26),
56 OPC_ADDIU
= (0x09 << 26),
57 OPC_SLTI
= (0x0A << 26),
58 OPC_SLTIU
= (0x0B << 26),
59 /* logic with immediate */
60 OPC_ANDI
= (0x0C << 26),
61 OPC_ORI
= (0x0D << 26),
62 OPC_XORI
= (0x0E << 26),
63 OPC_LUI
= (0x0F << 26),
64 /* arithmetic with immediate */
65 OPC_DADDI
= (0x18 << 26),
66 OPC_DADDIU
= (0x19 << 26),
67 /* Jump and branches */
69 OPC_JAL
= (0x03 << 26),
70 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
71 OPC_BEQL
= (0x14 << 26),
72 OPC_BNE
= (0x05 << 26),
73 OPC_BNEL
= (0x15 << 26),
74 OPC_BLEZ
= (0x06 << 26),
75 OPC_BLEZL
= (0x16 << 26),
76 OPC_BGTZ
= (0x07 << 26),
77 OPC_BGTZL
= (0x17 << 26),
78 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
80 OPC_LDL
= (0x1A << 26),
81 OPC_LDR
= (0x1B << 26),
82 OPC_LB
= (0x20 << 26),
83 OPC_LH
= (0x21 << 26),
84 OPC_LWL
= (0x22 << 26),
85 OPC_LW
= (0x23 << 26),
86 OPC_LBU
= (0x24 << 26),
87 OPC_LHU
= (0x25 << 26),
88 OPC_LWR
= (0x26 << 26),
89 OPC_LWU
= (0x27 << 26),
90 OPC_SB
= (0x28 << 26),
91 OPC_SH
= (0x29 << 26),
92 OPC_SWL
= (0x2A << 26),
93 OPC_SW
= (0x2B << 26),
94 OPC_SDL
= (0x2C << 26),
95 OPC_SDR
= (0x2D << 26),
96 OPC_SWR
= (0x2E << 26),
97 OPC_LL
= (0x30 << 26),
98 OPC_LLD
= (0x34 << 26),
99 OPC_LD
= (0x37 << 26),
100 OPC_SC
= (0x38 << 26),
101 OPC_SCD
= (0x3C << 26),
102 OPC_SD
= (0x3F << 26),
103 /* Floating point load/store */
104 OPC_LWC1
= (0x31 << 26),
105 OPC_LWC2
= (0x32 << 26),
106 OPC_LDC1
= (0x35 << 26),
107 OPC_LDC2
= (0x36 << 26),
108 OPC_SWC1
= (0x39 << 26),
109 OPC_SWC2
= (0x3A << 26),
110 OPC_SDC1
= (0x3D << 26),
111 OPC_SDC2
= (0x3E << 26),
112 /* MDMX ASE specific */
113 OPC_MDMX
= (0x1E << 26),
114 /* Cache and prefetch */
115 OPC_CACHE
= (0x2F << 26),
116 OPC_PREF
= (0x33 << 26),
117 /* Reserved major opcode */
118 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
121 /* MIPS special opcodes */
122 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
126 OPC_SLL
= 0x00 | OPC_SPECIAL
,
127 /* NOP is SLL r0, r0, 0 */
128 /* SSNOP is SLL r0, r0, 1 */
129 /* EHB is SLL r0, r0, 3 */
130 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
131 OPC_SRA
= 0x03 | OPC_SPECIAL
,
132 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
133 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
134 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
135 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
136 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
137 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
138 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
139 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
140 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
141 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
142 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
143 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
144 /* Multiplication / division */
145 OPC_MULT
= 0x18 | OPC_SPECIAL
,
146 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
147 OPC_DIV
= 0x1A | OPC_SPECIAL
,
148 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
149 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
150 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
151 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
152 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
153 /* 2 registers arithmetic / logic */
154 OPC_ADD
= 0x20 | OPC_SPECIAL
,
155 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
156 OPC_SUB
= 0x22 | OPC_SPECIAL
,
157 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
158 OPC_AND
= 0x24 | OPC_SPECIAL
,
159 OPC_OR
= 0x25 | OPC_SPECIAL
,
160 OPC_XOR
= 0x26 | OPC_SPECIAL
,
161 OPC_NOR
= 0x27 | OPC_SPECIAL
,
162 OPC_SLT
= 0x2A | OPC_SPECIAL
,
163 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
164 OPC_DADD
= 0x2C | OPC_SPECIAL
,
165 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
166 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
167 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
169 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
170 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
172 OPC_TGE
= 0x30 | OPC_SPECIAL
,
173 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
174 OPC_TLT
= 0x32 | OPC_SPECIAL
,
175 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
176 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
177 OPC_TNE
= 0x36 | OPC_SPECIAL
,
178 /* HI / LO registers load & stores */
179 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
180 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
181 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
182 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
183 /* Conditional moves */
184 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
185 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
187 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
190 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* unofficial */
191 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
192 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
193 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* unofficial */
194 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
196 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
197 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
198 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
199 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
200 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
201 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
202 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
205 /* Multiplication variants of the vr54xx. */
206 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
209 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
210 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
211 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
212 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
213 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
214 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
215 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
216 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
217 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
218 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
219 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
220 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
221 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
222 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
225 /* REGIMM (rt field) opcodes */
226 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
229 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
230 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
231 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
232 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
233 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
234 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
235 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
236 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
237 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
238 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
239 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
240 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
241 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
242 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
243 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
246 /* Special2 opcodes */
247 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
250 /* Multiply & xxx operations */
251 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
252 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
253 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
254 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
255 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
257 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
258 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
259 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
260 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
262 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
265 /* Special3 opcodes */
266 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
269 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
270 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
271 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
272 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
273 OPC_INS
= 0x04 | OPC_SPECIAL3
,
274 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
275 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
276 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
277 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
278 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
279 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
280 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
281 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
285 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
288 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
289 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
290 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
294 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
297 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
298 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
301 /* Coprocessor 0 (rs field) */
302 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
305 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
306 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
307 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
308 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
309 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
310 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
311 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
312 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
313 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
314 OPC_C0
= (0x10 << 21) | OPC_CP0
,
315 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
316 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
320 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
323 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
324 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
325 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
326 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
327 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
328 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
331 /* Coprocessor 0 (with rs == C0) */
332 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
335 OPC_TLBR
= 0x01 | OPC_C0
,
336 OPC_TLBWI
= 0x02 | OPC_C0
,
337 OPC_TLBWR
= 0x06 | OPC_C0
,
338 OPC_TLBP
= 0x08 | OPC_C0
,
339 OPC_RFE
= 0x10 | OPC_C0
,
340 OPC_ERET
= 0x18 | OPC_C0
,
341 OPC_DERET
= 0x1F | OPC_C0
,
342 OPC_WAIT
= 0x20 | OPC_C0
,
345 /* Coprocessor 1 (rs field) */
346 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
349 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
350 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
351 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
352 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
353 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
354 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
355 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
356 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
357 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
358 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
359 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
360 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
361 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
362 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
363 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
364 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
365 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
366 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
369 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
370 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
373 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
374 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
375 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
376 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
380 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
381 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
385 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
386 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
389 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
392 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
393 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
394 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
395 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
396 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
397 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
398 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
399 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
400 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
403 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
406 OPC_LWXC1
= 0x00 | OPC_CP3
,
407 OPC_LDXC1
= 0x01 | OPC_CP3
,
408 OPC_LUXC1
= 0x05 | OPC_CP3
,
409 OPC_SWXC1
= 0x08 | OPC_CP3
,
410 OPC_SDXC1
= 0x09 | OPC_CP3
,
411 OPC_SUXC1
= 0x0D | OPC_CP3
,
412 OPC_PREFX
= 0x0F | OPC_CP3
,
413 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
414 OPC_MADD_S
= 0x20 | OPC_CP3
,
415 OPC_MADD_D
= 0x21 | OPC_CP3
,
416 OPC_MADD_PS
= 0x26 | OPC_CP3
,
417 OPC_MSUB_S
= 0x28 | OPC_CP3
,
418 OPC_MSUB_D
= 0x29 | OPC_CP3
,
419 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
420 OPC_NMADD_S
= 0x30 | OPC_CP3
,
421 OPC_NMADD_D
= 0x31 | OPC_CP3
,
422 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
423 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
424 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
425 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
428 /* global register indices */
429 static TCGv_ptr cpu_env
;
430 static TCGv cpu_gpr
[32], cpu_PC
;
431 static TCGv cpu_HI
[MIPS_DSP_ACC
], cpu_LO
[MIPS_DSP_ACC
], cpu_ACX
[MIPS_DSP_ACC
];
432 static TCGv cpu_dspctrl
, btarget
, bcond
;
433 static TCGv_i32 hflags
;
434 static TCGv_i32 fpu_fcr0
, fpu_fcr31
;
436 #include "gen-icount.h"
438 #define gen_helper_0i(name, arg) do { \
439 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
440 gen_helper_##name(helper_tmp); \
441 tcg_temp_free_i32(helper_tmp); \
444 #define gen_helper_1i(name, arg1, arg2) do { \
445 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
446 gen_helper_##name(arg1, helper_tmp); \
447 tcg_temp_free_i32(helper_tmp); \
450 #define gen_helper_2i(name, arg1, arg2, arg3) do { \
451 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
452 gen_helper_##name(arg1, arg2, helper_tmp); \
453 tcg_temp_free_i32(helper_tmp); \
456 #define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
457 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
458 gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
459 tcg_temp_free_i32(helper_tmp); \
462 typedef struct DisasContext
{
463 struct TranslationBlock
*tb
;
464 target_ulong pc
, saved_pc
;
466 int singlestep_enabled
;
467 /* Routine used to access memory */
469 uint32_t hflags
, saved_hflags
;
471 target_ulong btarget
;
475 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
476 * exception condition */
477 BS_STOP
= 1, /* We want to stop translation for any reason */
478 BS_BRANCH
= 2, /* We reached a branch condition */
479 BS_EXCP
= 3, /* We reached an exception condition */
482 static const char *regnames
[] =
483 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
484 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
485 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
486 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
488 static const char *regnames_HI
[] =
489 { "HI0", "HI1", "HI2", "HI3", };
491 static const char *regnames_LO
[] =
492 { "LO0", "LO1", "LO2", "LO3", };
494 static const char *regnames_ACX
[] =
495 { "ACX0", "ACX1", "ACX2", "ACX3", };
497 static const char *fregnames
[] =
498 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
499 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
500 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
501 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
503 #ifdef MIPS_DEBUG_DISAS
504 #define MIPS_DEBUG(fmt, ...) \
505 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
506 TARGET_FMT_lx ": %08x " fmt "\n", \
507 ctx->pc, ctx->opcode , ## __VA_ARGS__)
508 #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
510 #define MIPS_DEBUG(fmt, ...) do { } while(0)
511 #define LOG_DISAS(...) do { } while (0)
514 #define MIPS_INVAL(op) \
516 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
517 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
520 /* General purpose registers moves. */
521 static inline void gen_load_gpr (TCGv t
, int reg
)
524 tcg_gen_movi_tl(t
, 0);
526 tcg_gen_mov_tl(t
, cpu_gpr
[reg
]);
529 static inline void gen_store_gpr (TCGv t
, int reg
)
532 tcg_gen_mov_tl(cpu_gpr
[reg
], t
);
535 /* Moves to/from ACX register. */
536 static inline void gen_load_ACX (TCGv t
, int reg
)
538 tcg_gen_mov_tl(t
, cpu_ACX
[reg
]);
541 static inline void gen_store_ACX (TCGv t
, int reg
)
543 tcg_gen_mov_tl(cpu_ACX
[reg
], t
);
546 /* Moves to/from shadow registers. */
547 static inline void gen_load_srsgpr (int from
, int to
)
549 TCGv t0
= tcg_temp_new();
552 tcg_gen_movi_tl(t0
, 0);
554 TCGv_i32 t2
= tcg_temp_new_i32();
555 TCGv_ptr addr
= tcg_temp_new_ptr();
557 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
558 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
559 tcg_gen_andi_i32(t2
, t2
, 0xf);
560 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
561 tcg_gen_ext_i32_ptr(addr
, t2
);
562 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
564 tcg_gen_ld_tl(t0
, addr
, sizeof(target_ulong
) * from
);
565 tcg_temp_free_ptr(addr
);
566 tcg_temp_free_i32(t2
);
568 gen_store_gpr(t0
, to
);
572 static inline void gen_store_srsgpr (int from
, int to
)
575 TCGv t0
= tcg_temp_new();
576 TCGv_i32 t2
= tcg_temp_new_i32();
577 TCGv_ptr addr
= tcg_temp_new_ptr();
579 gen_load_gpr(t0
, from
);
580 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
581 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
582 tcg_gen_andi_i32(t2
, t2
, 0xf);
583 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
584 tcg_gen_ext_i32_ptr(addr
, t2
);
585 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
587 tcg_gen_st_tl(t0
, addr
, sizeof(target_ulong
) * to
);
588 tcg_temp_free_ptr(addr
);
589 tcg_temp_free_i32(t2
);
594 /* Floating point register moves. */
595 static inline void gen_load_fpr32 (TCGv_i32 t
, int reg
)
597 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
600 static inline void gen_store_fpr32 (TCGv_i32 t
, int reg
)
602 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
605 static inline void gen_load_fpr32h (TCGv_i32 t
, int reg
)
607 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
610 static inline void gen_store_fpr32h (TCGv_i32 t
, int reg
)
612 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
615 static inline void gen_load_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
617 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
618 tcg_gen_ld_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
620 TCGv_i32 t0
= tcg_temp_new_i32();
621 TCGv_i32 t1
= tcg_temp_new_i32();
622 gen_load_fpr32(t0
, reg
& ~1);
623 gen_load_fpr32(t1
, reg
| 1);
624 tcg_gen_concat_i32_i64(t
, t0
, t1
);
625 tcg_temp_free_i32(t0
);
626 tcg_temp_free_i32(t1
);
630 static inline void gen_store_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
632 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
633 tcg_gen_st_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
635 TCGv_i64 t0
= tcg_temp_new_i64();
636 TCGv_i32 t1
= tcg_temp_new_i32();
637 tcg_gen_trunc_i64_i32(t1
, t
);
638 gen_store_fpr32(t1
, reg
& ~1);
639 tcg_gen_shri_i64(t0
, t
, 32);
640 tcg_gen_trunc_i64_i32(t1
, t0
);
641 gen_store_fpr32(t1
, reg
| 1);
642 tcg_temp_free_i32(t1
);
643 tcg_temp_free_i64(t0
);
647 static inline int get_fp_bit (int cc
)
655 #define FOP_CONDS(type, fmt, bits) \
656 static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \
657 TCGv_i##bits b, int cc) \
660 case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\
661 case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\
662 case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\
663 case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\
664 case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\
665 case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\
666 case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\
667 case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\
668 case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\
669 case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\
670 case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\
671 case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\
672 case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\
673 case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\
674 case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\
675 case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\
681 FOP_CONDS(abs
, d
, 64)
683 FOP_CONDS(abs
, s
, 32)
685 FOP_CONDS(abs
, ps
, 64)
689 #define OP_COND(name, cond) \
690 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, TCGv t1) \
692 int l1 = gen_new_label(); \
693 int l2 = gen_new_label(); \
695 tcg_gen_brcond_tl(cond, t0, t1, l1); \
696 tcg_gen_movi_tl(ret, 0); \
699 tcg_gen_movi_tl(ret, 1); \
702 OP_COND(eq
, TCG_COND_EQ
);
703 OP_COND(ne
, TCG_COND_NE
);
704 OP_COND(ge
, TCG_COND_GE
);
705 OP_COND(geu
, TCG_COND_GEU
);
706 OP_COND(lt
, TCG_COND_LT
);
707 OP_COND(ltu
, TCG_COND_LTU
);
710 #define OP_CONDI(name, cond) \
711 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, target_ulong val) \
713 int l1 = gen_new_label(); \
714 int l2 = gen_new_label(); \
716 tcg_gen_brcondi_tl(cond, t0, val, l1); \
717 tcg_gen_movi_tl(ret, 0); \
720 tcg_gen_movi_tl(ret, 1); \
723 OP_CONDI(lti
, TCG_COND_LT
);
724 OP_CONDI(ltiu
, TCG_COND_LTU
);
727 #define OP_CONDZ(name, cond) \
728 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0) \
730 int l1 = gen_new_label(); \
731 int l2 = gen_new_label(); \
733 tcg_gen_brcondi_tl(cond, t0, 0, l1); \
734 tcg_gen_movi_tl(ret, 0); \
737 tcg_gen_movi_tl(ret, 1); \
740 OP_CONDZ(gez
, TCG_COND_GE
);
741 OP_CONDZ(gtz
, TCG_COND_GT
);
742 OP_CONDZ(lez
, TCG_COND_LE
);
743 OP_CONDZ(ltz
, TCG_COND_LT
);
746 static inline void gen_save_pc(target_ulong pc
)
748 tcg_gen_movi_tl(cpu_PC
, pc
);
751 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
753 LOG_DISAS("hflags %08x saved %08x\n", ctx
->hflags
, ctx
->saved_hflags
);
754 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
755 gen_save_pc(ctx
->pc
);
756 ctx
->saved_pc
= ctx
->pc
;
758 if (ctx
->hflags
!= ctx
->saved_hflags
) {
759 tcg_gen_movi_i32(hflags
, ctx
->hflags
);
760 ctx
->saved_hflags
= ctx
->hflags
;
761 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
767 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
773 static inline void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
775 ctx
->saved_hflags
= ctx
->hflags
;
776 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
782 ctx
->btarget
= env
->btarget
;
788 generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
790 TCGv_i32 texcp
= tcg_const_i32(excp
);
791 TCGv_i32 terr
= tcg_const_i32(err
);
792 save_cpu_state(ctx
, 1);
793 gen_helper_raise_exception_err(texcp
, terr
);
794 tcg_temp_free_i32(terr
);
795 tcg_temp_free_i32(texcp
);
799 generate_exception (DisasContext
*ctx
, int excp
)
801 save_cpu_state(ctx
, 1);
802 gen_helper_0i(raise_exception
, excp
);
805 /* Addresses computation */
806 static inline void gen_op_addr_add (DisasContext
*ctx
, TCGv ret
, TCGv arg0
, TCGv arg1
)
808 tcg_gen_add_tl(ret
, arg0
, arg1
);
810 #if defined(TARGET_MIPS64)
811 /* For compatibility with 32-bit code, data reference in user mode
812 with Status_UX = 0 should be casted to 32-bit and sign extended.
813 See the MIPS64 PRA manual, section 4.10. */
814 if (((ctx
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
815 !(ctx
->hflags
& MIPS_HFLAG_UX
)) {
816 tcg_gen_ext32s_i64(ret
, ret
);
821 static inline void check_cp0_enabled(DisasContext
*ctx
)
823 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
824 generate_exception_err(ctx
, EXCP_CpU
, 0);
827 static inline void check_cp1_enabled(DisasContext
*ctx
)
829 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
830 generate_exception_err(ctx
, EXCP_CpU
, 1);
833 /* Verify that the processor is running with COP1X instructions enabled.
834 This is associated with the nabla symbol in the MIPS32 and MIPS64
837 static inline void check_cop1x(DisasContext
*ctx
)
839 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
840 generate_exception(ctx
, EXCP_RI
);
843 /* Verify that the processor is running with 64-bit floating-point
844 operations enabled. */
846 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
848 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
849 generate_exception(ctx
, EXCP_RI
);
853 * Verify if floating point register is valid; an operation is not defined
854 * if bit 0 of any register specification is set and the FR bit in the
855 * Status register equals zero, since the register numbers specify an
856 * even-odd pair of adjacent coprocessor general registers. When the FR bit
857 * in the Status register equals one, both even and odd register numbers
858 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
860 * Multiple 64 bit wide registers can be checked by calling
861 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
863 static inline void check_cp1_registers(DisasContext
*ctx
, int regs
)
865 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
866 generate_exception(ctx
, EXCP_RI
);
869 /* This code generates a "reserved instruction" exception if the
870 CPU does not support the instruction set corresponding to flags. */
871 static inline void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
873 if (unlikely(!(env
->insn_flags
& flags
)))
874 generate_exception(ctx
, EXCP_RI
);
877 /* This code generates a "reserved instruction" exception if 64-bit
878 instructions are not enabled. */
879 static inline void check_mips_64(DisasContext
*ctx
)
881 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
882 generate_exception(ctx
, EXCP_RI
);
885 /* load/store instructions. */
886 #define OP_LD(insn,fname) \
887 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
889 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
896 #if defined(TARGET_MIPS64)
902 #define OP_ST(insn,fname) \
903 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
905 tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
910 #if defined(TARGET_MIPS64)
915 #ifdef CONFIG_USER_ONLY
916 #define OP_LD_ATOMIC(insn,fname) \
917 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
919 TCGv t0 = tcg_temp_new(); \
920 tcg_gen_mov_tl(t0, arg1); \
921 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
922 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
923 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
927 #define OP_LD_ATOMIC(insn,fname) \
928 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
930 gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \
933 OP_LD_ATOMIC(ll
,ld32s
);
934 #if defined(TARGET_MIPS64)
935 OP_LD_ATOMIC(lld
,ld64
);
939 #ifdef CONFIG_USER_ONLY
940 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
941 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
943 TCGv t0 = tcg_temp_new(); \
944 int l1 = gen_new_label(); \
945 int l2 = gen_new_label(); \
947 tcg_gen_andi_tl(t0, arg2, almask); \
948 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
949 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
950 generate_exception(ctx, EXCP_AdES); \
952 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
953 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
954 tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
955 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
956 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \
957 gen_helper_0i(raise_exception, EXCP_SC); \
959 tcg_gen_movi_tl(t0, 0); \
960 gen_store_gpr(t0, rt); \
964 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
965 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
967 TCGv t0 = tcg_temp_new(); \
968 gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \
969 gen_store_gpr(t0, rt); \
973 OP_ST_ATOMIC(sc
,st32
,ld32s
,0x3);
974 #if defined(TARGET_MIPS64)
975 OP_ST_ATOMIC(scd
,st64
,ld64
,0x7);
980 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
981 int base
, int16_t offset
)
983 const char *opn
= "ldst";
984 TCGv t0
= tcg_temp_new();
985 TCGv t1
= tcg_temp_new();
988 tcg_gen_movi_tl(t0
, offset
);
989 } else if (offset
== 0) {
990 gen_load_gpr(t0
, base
);
992 tcg_gen_movi_tl(t0
, offset
);
993 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], t0
);
995 /* Don't do NOP if destination is zero: we must perform the actual
998 #if defined(TARGET_MIPS64)
1000 save_cpu_state(ctx
, 0);
1001 op_ldst_lwu(t0
, t0
, ctx
);
1002 gen_store_gpr(t0
, rt
);
1006 save_cpu_state(ctx
, 0);
1007 op_ldst_ld(t0
, t0
, ctx
);
1008 gen_store_gpr(t0
, rt
);
1012 save_cpu_state(ctx
, 0);
1013 op_ldst_lld(t0
, t0
, ctx
);
1014 gen_store_gpr(t0
, rt
);
1018 save_cpu_state(ctx
, 0);
1019 gen_load_gpr(t1
, rt
);
1020 op_ldst_sd(t1
, t0
, ctx
);
1024 save_cpu_state(ctx
, 1);
1025 gen_load_gpr(t1
, rt
);
1026 gen_helper_3i(ldl
, t1
, t1
, t0
, ctx
->mem_idx
);
1027 gen_store_gpr(t1
, rt
);
1031 save_cpu_state(ctx
, 1);
1032 gen_load_gpr(t1
, rt
);
1033 gen_helper_2i(sdl
, t1
, t0
, ctx
->mem_idx
);
1037 save_cpu_state(ctx
, 1);
1038 gen_load_gpr(t1
, rt
);
1039 gen_helper_3i(ldr
, t1
, t1
, t0
, ctx
->mem_idx
);
1040 gen_store_gpr(t1
, rt
);
1044 save_cpu_state(ctx
, 1);
1045 gen_load_gpr(t1
, rt
);
1046 gen_helper_2i(sdr
, t1
, t0
, ctx
->mem_idx
);
1051 save_cpu_state(ctx
, 0);
1052 op_ldst_lw(t0
, t0
, ctx
);
1053 gen_store_gpr(t0
, rt
);
1057 save_cpu_state(ctx
, 0);
1058 gen_load_gpr(t1
, rt
);
1059 op_ldst_sw(t1
, t0
, ctx
);
1063 save_cpu_state(ctx
, 0);
1064 op_ldst_lh(t0
, t0
, ctx
);
1065 gen_store_gpr(t0
, rt
);
1069 save_cpu_state(ctx
, 0);
1070 gen_load_gpr(t1
, rt
);
1071 op_ldst_sh(t1
, t0
, ctx
);
1075 save_cpu_state(ctx
, 0);
1076 op_ldst_lhu(t0
, t0
, ctx
);
1077 gen_store_gpr(t0
, rt
);
1081 save_cpu_state(ctx
, 0);
1082 op_ldst_lb(t0
, t0
, ctx
);
1083 gen_store_gpr(t0
, rt
);
1087 save_cpu_state(ctx
, 0);
1088 gen_load_gpr(t1
, rt
);
1089 op_ldst_sb(t1
, t0
, ctx
);
1093 save_cpu_state(ctx
, 0);
1094 op_ldst_lbu(t0
, t0
, ctx
);
1095 gen_store_gpr(t0
, rt
);
1099 save_cpu_state(ctx
, 1);
1100 gen_load_gpr(t1
, rt
);
1101 gen_helper_3i(lwl
, t1
, t1
, t0
, ctx
->mem_idx
);
1102 gen_store_gpr(t1
, rt
);
1106 save_cpu_state(ctx
, 1);
1107 gen_load_gpr(t1
, rt
);
1108 gen_helper_2i(swl
, t1
, t0
, ctx
->mem_idx
);
1112 save_cpu_state(ctx
, 1);
1113 gen_load_gpr(t1
, rt
);
1114 gen_helper_3i(lwr
, t1
, t1
, t0
, ctx
->mem_idx
);
1115 gen_store_gpr(t1
, rt
);
1119 save_cpu_state(ctx
, 1);
1120 gen_load_gpr(t1
, rt
);
1121 gen_helper_2i(swr
, t1
, t0
, ctx
->mem_idx
);
1125 save_cpu_state(ctx
, 1);
1126 op_ldst_ll(t0
, t0
, ctx
);
1127 gen_store_gpr(t0
, rt
);
1131 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1136 /* Store conditional */
1137 static void gen_st_cond (DisasContext
*ctx
, uint32_t opc
, int rt
,
1138 int base
, int16_t offset
)
1140 const char *opn
= "st_cond";
1143 t0
= tcg_temp_local_new();
1146 tcg_gen_movi_tl(t0
, offset
);
1147 } else if (offset
== 0) {
1148 gen_load_gpr(t0
, base
);
1150 tcg_gen_movi_tl(t0
, offset
);
1151 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], t0
);
1153 /* Don't do NOP if destination is zero: we must perform the actual
1156 t1
= tcg_temp_local_new();
1157 gen_load_gpr(t1
, rt
);
1159 #if defined(TARGET_MIPS64)
1161 save_cpu_state(ctx
, 0);
1162 op_ldst_scd(t1
, t0
, rt
, ctx
);
1167 save_cpu_state(ctx
, 1);
1168 op_ldst_sc(t1
, t0
, rt
, ctx
);
1172 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1177 /* Load and store */
1178 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1179 int base
, int16_t offset
)
1181 const char *opn
= "flt_ldst";
1182 TCGv t0
= tcg_temp_new();
1185 tcg_gen_movi_tl(t0
, offset
);
1186 } else if (offset
== 0) {
1187 gen_load_gpr(t0
, base
);
1189 tcg_gen_movi_tl(t0
, offset
);
1190 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], t0
);
1192 /* Don't do NOP if destination is zero: we must perform the actual
1197 TCGv_i32 fp0
= tcg_temp_new_i32();
1199 tcg_gen_qemu_ld32s(t0
, t0
, ctx
->mem_idx
);
1200 tcg_gen_trunc_tl_i32(fp0
, t0
);
1201 gen_store_fpr32(fp0
, ft
);
1202 tcg_temp_free_i32(fp0
);
1208 TCGv_i32 fp0
= tcg_temp_new_i32();
1209 TCGv t1
= tcg_temp_new();
1211 gen_load_fpr32(fp0
, ft
);
1212 tcg_gen_extu_i32_tl(t1
, fp0
);
1213 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
1215 tcg_temp_free_i32(fp0
);
1221 TCGv_i64 fp0
= tcg_temp_new_i64();
1223 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
1224 gen_store_fpr64(ctx
, fp0
, ft
);
1225 tcg_temp_free_i64(fp0
);
1231 TCGv_i64 fp0
= tcg_temp_new_i64();
1233 gen_load_fpr64(ctx
, fp0
, ft
);
1234 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
1235 tcg_temp_free_i64(fp0
);
1241 generate_exception(ctx
, EXCP_RI
);
1244 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1249 /* Arithmetic with immediate operand */
1250 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1251 int rt
, int rs
, int16_t imm
)
1253 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1254 const char *opn
= "imm arith";
1256 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1257 /* If no destination, treat it as a NOP.
1258 For addi, we must generate the overflow exception when needed. */
1265 TCGv t0
= tcg_temp_local_new();
1266 TCGv t1
= tcg_temp_new();
1267 TCGv t2
= tcg_temp_new();
1268 int l1
= gen_new_label();
1270 gen_load_gpr(t1
, rs
);
1271 tcg_gen_addi_tl(t0
, t1
, uimm
);
1272 tcg_gen_ext32s_tl(t0
, t0
);
1274 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
1275 tcg_gen_xori_tl(t2
, t0
, uimm
);
1276 tcg_gen_and_tl(t1
, t1
, t2
);
1278 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1280 /* operands of same sign, result different sign */
1281 generate_exception(ctx
, EXCP_OVERFLOW
);
1283 tcg_gen_ext32s_tl(t0
, t0
);
1284 gen_store_gpr(t0
, rt
);
1291 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1292 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
1294 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1298 #if defined(TARGET_MIPS64)
1301 TCGv t0
= tcg_temp_local_new();
1302 TCGv t1
= tcg_temp_new();
1303 TCGv t2
= tcg_temp_new();
1304 int l1
= gen_new_label();
1306 gen_load_gpr(t1
, rs
);
1307 tcg_gen_addi_tl(t0
, t1
, uimm
);
1309 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
1310 tcg_gen_xori_tl(t2
, t0
, uimm
);
1311 tcg_gen_and_tl(t1
, t1
, t2
);
1313 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1315 /* operands of same sign, result different sign */
1316 generate_exception(ctx
, EXCP_OVERFLOW
);
1318 gen_store_gpr(t0
, rt
);
1325 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1327 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1333 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1336 /* Logic with immediate operand */
1337 static void gen_logic_imm (CPUState
*env
, uint32_t opc
, int rt
, int rs
, int16_t imm
)
1340 const char *opn
= "imm logic";
1343 /* If no destination, treat it as a NOP. */
1347 uimm
= (uint16_t)imm
;
1350 if (likely(rs
!= 0))
1351 tcg_gen_andi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1353 tcg_gen_movi_tl(cpu_gpr
[rt
], 0);
1358 tcg_gen_ori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1360 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1364 if (likely(rs
!= 0))
1365 tcg_gen_xori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1367 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1371 tcg_gen_movi_tl(cpu_gpr
[rt
], imm
<< 16);
1375 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1378 /* Set on less than with immediate operand */
1379 static void gen_slt_imm (CPUState
*env
, uint32_t opc
, int rt
, int rs
, int16_t imm
)
1381 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1382 const char *opn
= "imm arith";
1386 /* If no destination, treat it as a NOP. */
1390 t0
= tcg_temp_new();
1391 gen_load_gpr(t0
, rs
);
1394 gen_op_lti(cpu_gpr
[rt
], t0
, uimm
);
1398 gen_op_ltiu(cpu_gpr
[rt
], t0
, uimm
);
1402 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1406 /* Shifts with immediate operand */
1407 static void gen_shift_imm(CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1408 int rt
, int rs
, int16_t imm
)
1410 target_ulong uimm
= ((uint16_t)imm
) & 0x1f;
1411 const char *opn
= "imm shift";
1415 /* If no destination, treat it as a NOP. */
1420 t0
= tcg_temp_new();
1421 gen_load_gpr(t0
, rs
);
1424 tcg_gen_shli_tl(t0
, t0
, uimm
);
1425 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1429 tcg_gen_ext32s_tl(t0
, t0
);
1430 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
1434 switch ((ctx
->opcode
>> 21) & 0x1f) {
1437 tcg_gen_ext32u_tl(t0
, t0
);
1438 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1440 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1445 /* rotr is decoded as srl on non-R2 CPUs */
1446 if (env
->insn_flags
& ISA_MIPS32R2
) {
1448 TCGv_i32 t1
= tcg_temp_new_i32();
1450 tcg_gen_trunc_tl_i32(t1
, t0
);
1451 tcg_gen_rotri_i32(t1
, t1
, uimm
);
1452 tcg_gen_ext_i32_tl(cpu_gpr
[rt
], t1
);
1453 tcg_temp_free_i32(t1
);
1455 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1460 tcg_gen_ext32u_tl(t0
, t0
);
1461 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1463 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1469 MIPS_INVAL("invalid srl flag");
1470 generate_exception(ctx
, EXCP_RI
);
1474 #if defined(TARGET_MIPS64)
1476 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
);
1480 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
1484 switch ((ctx
->opcode
>> 21) & 0x1f) {
1486 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1490 /* drotr is decoded as dsrl on non-R2 CPUs */
1491 if (env
->insn_flags
& ISA_MIPS32R2
) {
1493 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
);
1495 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
1499 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1504 MIPS_INVAL("invalid dsrl flag");
1505 generate_exception(ctx
, EXCP_RI
);
1510 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1514 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1518 switch ((ctx
->opcode
>> 21) & 0x1f) {
1520 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1524 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1525 if (env
->insn_flags
& ISA_MIPS32R2
) {
1526 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1529 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1534 MIPS_INVAL("invalid dsrl32 flag");
1535 generate_exception(ctx
, EXCP_RI
);
1541 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1546 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1547 int rd
, int rs
, int rt
)
1549 const char *opn
= "arith";
1551 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1552 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1553 /* If no destination, treat it as a NOP.
1554 For add & sub, we must generate the overflow exception when needed. */
1562 TCGv t0
= tcg_temp_local_new();
1563 TCGv t1
= tcg_temp_new();
1564 TCGv t2
= tcg_temp_new();
1565 int l1
= gen_new_label();
1567 gen_load_gpr(t1
, rs
);
1568 gen_load_gpr(t2
, rt
);
1569 tcg_gen_add_tl(t0
, t1
, t2
);
1570 tcg_gen_ext32s_tl(t0
, t0
);
1571 tcg_gen_xor_tl(t1
, t1
, t2
);
1572 tcg_gen_not_tl(t1
, t1
);
1573 tcg_gen_xor_tl(t2
, t0
, t2
);
1574 tcg_gen_and_tl(t1
, t1
, t2
);
1576 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1578 /* operands of same sign, result different sign */
1579 generate_exception(ctx
, EXCP_OVERFLOW
);
1581 gen_store_gpr(t0
, rd
);
1587 if (rs
!= 0 && rt
!= 0) {
1588 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1589 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1590 } else if (rs
== 0 && rt
!= 0) {
1591 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1592 } else if (rs
!= 0 && rt
== 0) {
1593 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1595 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1601 TCGv t0
= tcg_temp_local_new();
1602 TCGv t1
= tcg_temp_new();
1603 TCGv t2
= tcg_temp_new();
1604 int l1
= gen_new_label();
1606 gen_load_gpr(t1
, rs
);
1607 gen_load_gpr(t2
, rt
);
1608 tcg_gen_sub_tl(t0
, t1
, t2
);
1609 tcg_gen_ext32s_tl(t0
, t0
);
1610 tcg_gen_xor_tl(t2
, t1
, t2
);
1611 tcg_gen_xor_tl(t1
, t0
, t1
);
1612 tcg_gen_and_tl(t1
, t1
, t2
);
1614 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1616 /* operands of different sign, first operand and result different sign */
1617 generate_exception(ctx
, EXCP_OVERFLOW
);
1619 gen_store_gpr(t0
, rd
);
1625 if (rs
!= 0 && rt
!= 0) {
1626 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1627 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1628 } else if (rs
== 0 && rt
!= 0) {
1629 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1630 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1631 } else if (rs
!= 0 && rt
== 0) {
1632 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1634 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1638 #if defined(TARGET_MIPS64)
1641 TCGv t0
= tcg_temp_local_new();
1642 TCGv t1
= tcg_temp_new();
1643 TCGv t2
= tcg_temp_new();
1644 int l1
= gen_new_label();
1646 gen_load_gpr(t1
, rs
);
1647 gen_load_gpr(t2
, rt
);
1648 tcg_gen_add_tl(t0
, t1
, t2
);
1649 tcg_gen_xor_tl(t1
, t1
, t2
);
1650 tcg_gen_not_tl(t1
, t1
);
1651 tcg_gen_xor_tl(t2
, t0
, t2
);
1652 tcg_gen_and_tl(t1
, t1
, t2
);
1654 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1656 /* operands of same sign, result different sign */
1657 generate_exception(ctx
, EXCP_OVERFLOW
);
1659 gen_store_gpr(t0
, rd
);
1665 if (rs
!= 0 && rt
!= 0) {
1666 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1667 } else if (rs
== 0 && rt
!= 0) {
1668 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1669 } else if (rs
!= 0 && rt
== 0) {
1670 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1672 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1678 TCGv t0
= tcg_temp_local_new();
1679 TCGv t1
= tcg_temp_new();
1680 TCGv t2
= tcg_temp_new();
1681 int l1
= gen_new_label();
1683 gen_load_gpr(t1
, rs
);
1684 gen_load_gpr(t2
, rt
);
1685 tcg_gen_sub_tl(t0
, t1
, t2
);
1686 tcg_gen_xor_tl(t2
, t1
, t2
);
1687 tcg_gen_xor_tl(t1
, t0
, t1
);
1688 tcg_gen_and_tl(t1
, t1
, t2
);
1690 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1692 /* operands of different sign, first operand and result different sign */
1693 generate_exception(ctx
, EXCP_OVERFLOW
);
1695 gen_store_gpr(t0
, rd
);
1701 if (rs
!= 0 && rt
!= 0) {
1702 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1703 } else if (rs
== 0 && rt
!= 0) {
1704 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1705 } else if (rs
!= 0 && rt
== 0) {
1706 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1708 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1714 if (likely(rs
!= 0 && rt
!= 0)) {
1715 tcg_gen_mul_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1716 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1718 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1723 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1726 /* Conditional move */
1727 static void gen_cond_move (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1729 const char *opn
= "cond move";
1733 /* If no destination, treat it as a NOP.
1734 For add & sub, we must generate the overflow exception when needed. */
1739 l1
= gen_new_label();
1742 if (likely(rt
!= 0))
1743 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rt
], 0, l1
);
1749 if (likely(rt
!= 0))
1750 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rt
], 0, l1
);
1755 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1757 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1760 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1764 static void gen_logic (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1766 const char *opn
= "logic";
1769 /* If no destination, treat it as a NOP. */
1776 if (likely(rs
!= 0 && rt
!= 0)) {
1777 tcg_gen_and_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1779 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1784 if (rs
!= 0 && rt
!= 0) {
1785 tcg_gen_nor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1786 } else if (rs
== 0 && rt
!= 0) {
1787 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1788 } else if (rs
!= 0 && rt
== 0) {
1789 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1791 tcg_gen_movi_tl(cpu_gpr
[rd
], ~((target_ulong
)0));
1796 if (likely(rs
!= 0 && rt
!= 0)) {
1797 tcg_gen_or_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1798 } else if (rs
== 0 && rt
!= 0) {
1799 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1800 } else if (rs
!= 0 && rt
== 0) {
1801 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1803 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1808 if (likely(rs
!= 0 && rt
!= 0)) {
1809 tcg_gen_xor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1810 } else if (rs
== 0 && rt
!= 0) {
1811 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1812 } else if (rs
!= 0 && rt
== 0) {
1813 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1815 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1820 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1823 /* Set on lower than */
1824 static void gen_slt (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1826 const char *opn
= "slt";
1830 /* If no destination, treat it as a NOP. */
1835 t0
= tcg_temp_new();
1836 t1
= tcg_temp_new();
1837 gen_load_gpr(t0
, rs
);
1838 gen_load_gpr(t1
, rt
);
1841 gen_op_lt(cpu_gpr
[rd
], t0
, t1
);
1845 gen_op_ltu(cpu_gpr
[rd
], t0
, t1
);
1849 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1855 static void gen_shift (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1856 int rd
, int rs
, int rt
)
1858 const char *opn
= "shifts";
1862 /* If no destination, treat it as a NOP.
1863 For add & sub, we must generate the overflow exception when needed. */
1868 t0
= tcg_temp_new();
1869 t1
= tcg_temp_new();
1870 gen_load_gpr(t0
, rs
);
1871 gen_load_gpr(t1
, rt
);
1874 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1875 tcg_gen_shl_tl(t0
, t1
, t0
);
1876 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1880 tcg_gen_ext32s_tl(t1
, t1
);
1881 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1882 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
1886 switch ((ctx
->opcode
>> 6) & 0x1f) {
1888 tcg_gen_ext32u_tl(t1
, t1
);
1889 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1890 tcg_gen_shr_tl(t0
, t1
, t0
);
1891 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1895 /* rotrv is decoded as srlv on non-R2 CPUs */
1896 if (env
->insn_flags
& ISA_MIPS32R2
) {
1897 TCGv_i32 t2
= tcg_temp_new_i32();
1898 TCGv_i32 t3
= tcg_temp_new_i32();
1900 tcg_gen_trunc_tl_i32(t2
, t0
);
1901 tcg_gen_trunc_tl_i32(t3
, t1
);
1902 tcg_gen_andi_i32(t2
, t2
, 0x1f);
1903 tcg_gen_rotr_i32(t2
, t3
, t2
);
1904 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
1905 tcg_temp_free_i32(t2
);
1906 tcg_temp_free_i32(t3
);
1909 tcg_gen_ext32u_tl(t1
, t1
);
1910 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1911 tcg_gen_shr_tl(t0
, t1
, t0
);
1912 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1917 MIPS_INVAL("invalid srlv flag");
1918 generate_exception(ctx
, EXCP_RI
);
1922 #if defined(TARGET_MIPS64)
1924 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1925 tcg_gen_shl_tl(cpu_gpr
[rd
], t1
, t0
);
1929 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1930 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
1934 switch ((ctx
->opcode
>> 6) & 0x1f) {
1936 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1937 tcg_gen_shr_tl(cpu_gpr
[rd
], t1
, t0
);
1941 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1942 if (env
->insn_flags
& ISA_MIPS32R2
) {
1943 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1944 tcg_gen_rotr_tl(cpu_gpr
[rd
], t1
, t0
);
1947 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1948 tcg_gen_shr_tl(t0
, t1
, t0
);
1953 MIPS_INVAL("invalid dsrlv flag");
1954 generate_exception(ctx
, EXCP_RI
);
1960 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1965 /* Arithmetic on HI/LO registers */
1966 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1968 const char *opn
= "hilo";
1970 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1977 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_HI
[0]);
1981 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_LO
[0]);
1986 tcg_gen_mov_tl(cpu_HI
[0], cpu_gpr
[reg
]);
1988 tcg_gen_movi_tl(cpu_HI
[0], 0);
1993 tcg_gen_mov_tl(cpu_LO
[0], cpu_gpr
[reg
]);
1995 tcg_gen_movi_tl(cpu_LO
[0], 0);
1999 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
2002 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
2005 const char *opn
= "mul/div";
2011 #if defined(TARGET_MIPS64)
2015 t0
= tcg_temp_local_new();
2016 t1
= tcg_temp_local_new();
2019 t0
= tcg_temp_new();
2020 t1
= tcg_temp_new();
2024 gen_load_gpr(t0
, rs
);
2025 gen_load_gpr(t1
, rt
);
2029 int l1
= gen_new_label();
2030 int l2
= gen_new_label();
2032 tcg_gen_ext32s_tl(t0
, t0
);
2033 tcg_gen_ext32s_tl(t1
, t1
);
2034 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2035 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
2036 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
2038 tcg_gen_mov_tl(cpu_LO
[0], t0
);
2039 tcg_gen_movi_tl(cpu_HI
[0], 0);
2042 tcg_gen_div_tl(cpu_LO
[0], t0
, t1
);
2043 tcg_gen_rem_tl(cpu_HI
[0], t0
, t1
);
2044 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
2045 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
2052 int l1
= gen_new_label();
2054 tcg_gen_ext32u_tl(t0
, t0
);
2055 tcg_gen_ext32u_tl(t1
, t1
);
2056 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2057 tcg_gen_divu_tl(cpu_LO
[0], t0
, t1
);
2058 tcg_gen_remu_tl(cpu_HI
[0], t0
, t1
);
2059 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
2060 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
2067 TCGv_i64 t2
= tcg_temp_new_i64();
2068 TCGv_i64 t3
= tcg_temp_new_i64();
2070 tcg_gen_ext_tl_i64(t2
, t0
);
2071 tcg_gen_ext_tl_i64(t3
, t1
);
2072 tcg_gen_mul_i64(t2
, t2
, t3
);
2073 tcg_temp_free_i64(t3
);
2074 tcg_gen_trunc_i64_tl(t0
, t2
);
2075 tcg_gen_shri_i64(t2
, t2
, 32);
2076 tcg_gen_trunc_i64_tl(t1
, t2
);
2077 tcg_temp_free_i64(t2
);
2078 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2079 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2085 TCGv_i64 t2
= tcg_temp_new_i64();
2086 TCGv_i64 t3
= tcg_temp_new_i64();
2088 tcg_gen_ext32u_tl(t0
, t0
);
2089 tcg_gen_ext32u_tl(t1
, t1
);
2090 tcg_gen_extu_tl_i64(t2
, t0
);
2091 tcg_gen_extu_tl_i64(t3
, t1
);
2092 tcg_gen_mul_i64(t2
, t2
, t3
);
2093 tcg_temp_free_i64(t3
);
2094 tcg_gen_trunc_i64_tl(t0
, t2
);
2095 tcg_gen_shri_i64(t2
, t2
, 32);
2096 tcg_gen_trunc_i64_tl(t1
, t2
);
2097 tcg_temp_free_i64(t2
);
2098 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2099 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2103 #if defined(TARGET_MIPS64)
2106 int l1
= gen_new_label();
2107 int l2
= gen_new_label();
2109 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2110 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
2111 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
2112 tcg_gen_mov_tl(cpu_LO
[0], t0
);
2113 tcg_gen_movi_tl(cpu_HI
[0], 0);
2116 tcg_gen_div_i64(cpu_LO
[0], t0
, t1
);
2117 tcg_gen_rem_i64(cpu_HI
[0], t0
, t1
);
2124 int l1
= gen_new_label();
2126 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2127 tcg_gen_divu_i64(cpu_LO
[0], t0
, t1
);
2128 tcg_gen_remu_i64(cpu_HI
[0], t0
, t1
);
2134 gen_helper_dmult(t0
, t1
);
2138 gen_helper_dmultu(t0
, t1
);
2144 TCGv_i64 t2
= tcg_temp_new_i64();
2145 TCGv_i64 t3
= tcg_temp_new_i64();
2147 tcg_gen_ext_tl_i64(t2
, t0
);
2148 tcg_gen_ext_tl_i64(t3
, t1
);
2149 tcg_gen_mul_i64(t2
, t2
, t3
);
2150 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2151 tcg_gen_add_i64(t2
, t2
, t3
);
2152 tcg_temp_free_i64(t3
);
2153 tcg_gen_trunc_i64_tl(t0
, t2
);
2154 tcg_gen_shri_i64(t2
, t2
, 32);
2155 tcg_gen_trunc_i64_tl(t1
, t2
);
2156 tcg_temp_free_i64(t2
);
2157 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2158 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2164 TCGv_i64 t2
= tcg_temp_new_i64();
2165 TCGv_i64 t3
= tcg_temp_new_i64();
2167 tcg_gen_ext32u_tl(t0
, t0
);
2168 tcg_gen_ext32u_tl(t1
, t1
);
2169 tcg_gen_extu_tl_i64(t2
, t0
);
2170 tcg_gen_extu_tl_i64(t3
, t1
);
2171 tcg_gen_mul_i64(t2
, t2
, t3
);
2172 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2173 tcg_gen_add_i64(t2
, t2
, t3
);
2174 tcg_temp_free_i64(t3
);
2175 tcg_gen_trunc_i64_tl(t0
, t2
);
2176 tcg_gen_shri_i64(t2
, t2
, 32);
2177 tcg_gen_trunc_i64_tl(t1
, t2
);
2178 tcg_temp_free_i64(t2
);
2179 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2180 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2186 TCGv_i64 t2
= tcg_temp_new_i64();
2187 TCGv_i64 t3
= tcg_temp_new_i64();
2189 tcg_gen_ext_tl_i64(t2
, t0
);
2190 tcg_gen_ext_tl_i64(t3
, t1
);
2191 tcg_gen_mul_i64(t2
, t2
, t3
);
2192 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2193 tcg_gen_sub_i64(t2
, t3
, t2
);
2194 tcg_temp_free_i64(t3
);
2195 tcg_gen_trunc_i64_tl(t0
, t2
);
2196 tcg_gen_shri_i64(t2
, t2
, 32);
2197 tcg_gen_trunc_i64_tl(t1
, t2
);
2198 tcg_temp_free_i64(t2
);
2199 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2200 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2206 TCGv_i64 t2
= tcg_temp_new_i64();
2207 TCGv_i64 t3
= tcg_temp_new_i64();
2209 tcg_gen_ext32u_tl(t0
, t0
);
2210 tcg_gen_ext32u_tl(t1
, t1
);
2211 tcg_gen_extu_tl_i64(t2
, t0
);
2212 tcg_gen_extu_tl_i64(t3
, t1
);
2213 tcg_gen_mul_i64(t2
, t2
, t3
);
2214 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2215 tcg_gen_sub_i64(t2
, t3
, t2
);
2216 tcg_temp_free_i64(t3
);
2217 tcg_gen_trunc_i64_tl(t0
, t2
);
2218 tcg_gen_shri_i64(t2
, t2
, 32);
2219 tcg_gen_trunc_i64_tl(t1
, t2
);
2220 tcg_temp_free_i64(t2
);
2221 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2222 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2228 generate_exception(ctx
, EXCP_RI
);
2231 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
2237 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
2238 int rd
, int rs
, int rt
)
2240 const char *opn
= "mul vr54xx";
2241 TCGv t0
= tcg_temp_new();
2242 TCGv t1
= tcg_temp_new();
2244 gen_load_gpr(t0
, rs
);
2245 gen_load_gpr(t1
, rt
);
2248 case OPC_VR54XX_MULS
:
2249 gen_helper_muls(t0
, t0
, t1
);
2252 case OPC_VR54XX_MULSU
:
2253 gen_helper_mulsu(t0
, t0
, t1
);
2256 case OPC_VR54XX_MACC
:
2257 gen_helper_macc(t0
, t0
, t1
);
2260 case OPC_VR54XX_MACCU
:
2261 gen_helper_maccu(t0
, t0
, t1
);
2264 case OPC_VR54XX_MSAC
:
2265 gen_helper_msac(t0
, t0
, t1
);
2268 case OPC_VR54XX_MSACU
:
2269 gen_helper_msacu(t0
, t0
, t1
);
2272 case OPC_VR54XX_MULHI
:
2273 gen_helper_mulhi(t0
, t0
, t1
);
2276 case OPC_VR54XX_MULHIU
:
2277 gen_helper_mulhiu(t0
, t0
, t1
);
2280 case OPC_VR54XX_MULSHI
:
2281 gen_helper_mulshi(t0
, t0
, t1
);
2284 case OPC_VR54XX_MULSHIU
:
2285 gen_helper_mulshiu(t0
, t0
, t1
);
2288 case OPC_VR54XX_MACCHI
:
2289 gen_helper_macchi(t0
, t0
, t1
);
2292 case OPC_VR54XX_MACCHIU
:
2293 gen_helper_macchiu(t0
, t0
, t1
);
2296 case OPC_VR54XX_MSACHI
:
2297 gen_helper_msachi(t0
, t0
, t1
);
2300 case OPC_VR54XX_MSACHIU
:
2301 gen_helper_msachiu(t0
, t0
, t1
);
2305 MIPS_INVAL("mul vr54xx");
2306 generate_exception(ctx
, EXCP_RI
);
2309 gen_store_gpr(t0
, rd
);
2310 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2317 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
2320 const char *opn
= "CLx";
2328 t0
= tcg_temp_new();
2329 gen_load_gpr(t0
, rs
);
2332 gen_helper_clo(cpu_gpr
[rd
], t0
);
2336 gen_helper_clz(cpu_gpr
[rd
], t0
);
2339 #if defined(TARGET_MIPS64)
2341 gen_helper_dclo(cpu_gpr
[rd
], t0
);
2345 gen_helper_dclz(cpu_gpr
[rd
], t0
);
2350 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
2355 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
2356 int rs
, int rt
, int16_t imm
)
2359 TCGv t0
= tcg_temp_new();
2360 TCGv t1
= tcg_temp_new();
2363 /* Load needed operands */
2371 /* Compare two registers */
2373 gen_load_gpr(t0
, rs
);
2374 gen_load_gpr(t1
, rt
);
2384 /* Compare register to immediate */
2385 if (rs
!= 0 || imm
!= 0) {
2386 gen_load_gpr(t0
, rs
);
2387 tcg_gen_movi_tl(t1
, (int32_t)imm
);
2394 case OPC_TEQ
: /* rs == rs */
2395 case OPC_TEQI
: /* r0 == 0 */
2396 case OPC_TGE
: /* rs >= rs */
2397 case OPC_TGEI
: /* r0 >= 0 */
2398 case OPC_TGEU
: /* rs >= rs unsigned */
2399 case OPC_TGEIU
: /* r0 >= 0 unsigned */
2401 generate_exception(ctx
, EXCP_TRAP
);
2403 case OPC_TLT
: /* rs < rs */
2404 case OPC_TLTI
: /* r0 < 0 */
2405 case OPC_TLTU
: /* rs < rs unsigned */
2406 case OPC_TLTIU
: /* r0 < 0 unsigned */
2407 case OPC_TNE
: /* rs != rs */
2408 case OPC_TNEI
: /* r0 != 0 */
2409 /* Never trap: treat as NOP. */
2413 int l1
= gen_new_label();
2418 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, t1
, l1
);
2422 tcg_gen_brcond_tl(TCG_COND_LT
, t0
, t1
, l1
);
2426 tcg_gen_brcond_tl(TCG_COND_LTU
, t0
, t1
, l1
);
2430 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
2434 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
2438 tcg_gen_brcond_tl(TCG_COND_EQ
, t0
, t1
, l1
);
2441 generate_exception(ctx
, EXCP_TRAP
);
2448 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
2450 TranslationBlock
*tb
;
2452 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
2453 likely(!ctx
->singlestep_enabled
)) {
2456 tcg_gen_exit_tb((long)tb
+ n
);
2459 if (ctx
->singlestep_enabled
) {
2460 save_cpu_state(ctx
, 0);
2461 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
2467 /* Branches (before delay slot) */
2468 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
2469 int rs
, int rt
, int32_t offset
)
2471 target_ulong btgt
= -1;
2473 int bcond_compute
= 0;
2474 TCGv t0
= tcg_temp_new();
2475 TCGv t1
= tcg_temp_new();
2477 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2478 #ifdef MIPS_DEBUG_DISAS
2479 LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n", ctx
->pc
);
2481 generate_exception(ctx
, EXCP_RI
);
2485 /* Load needed operands */
2491 /* Compare two registers */
2493 gen_load_gpr(t0
, rs
);
2494 gen_load_gpr(t1
, rt
);
2497 btgt
= ctx
->pc
+ 4 + offset
;
2511 /* Compare to zero */
2513 gen_load_gpr(t0
, rs
);
2516 btgt
= ctx
->pc
+ 4 + offset
;
2520 /* Jump to immediate */
2521 btgt
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
2525 /* Jump to register */
2526 if (offset
!= 0 && offset
!= 16) {
2527 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2528 others are reserved. */
2529 MIPS_INVAL("jump hint");
2530 generate_exception(ctx
, EXCP_RI
);
2533 gen_load_gpr(btarget
, rs
);
2536 MIPS_INVAL("branch/jump");
2537 generate_exception(ctx
, EXCP_RI
);
2540 if (bcond_compute
== 0) {
2541 /* No condition to be computed */
2543 case OPC_BEQ
: /* rx == rx */
2544 case OPC_BEQL
: /* rx == rx likely */
2545 case OPC_BGEZ
: /* 0 >= 0 */
2546 case OPC_BGEZL
: /* 0 >= 0 likely */
2547 case OPC_BLEZ
: /* 0 <= 0 */
2548 case OPC_BLEZL
: /* 0 <= 0 likely */
2550 ctx
->hflags
|= MIPS_HFLAG_B
;
2551 MIPS_DEBUG("balways");
2553 case OPC_BGEZAL
: /* 0 >= 0 */
2554 case OPC_BGEZALL
: /* 0 >= 0 likely */
2555 /* Always take and link */
2557 ctx
->hflags
|= MIPS_HFLAG_B
;
2558 MIPS_DEBUG("balways and link");
2560 case OPC_BNE
: /* rx != rx */
2561 case OPC_BGTZ
: /* 0 > 0 */
2562 case OPC_BLTZ
: /* 0 < 0 */
2564 MIPS_DEBUG("bnever (NOP)");
2566 case OPC_BLTZAL
: /* 0 < 0 */
2567 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
2568 MIPS_DEBUG("bnever and link");
2570 case OPC_BLTZALL
: /* 0 < 0 likely */
2571 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
2572 /* Skip the instruction in the delay slot */
2573 MIPS_DEBUG("bnever, link and skip");
2576 case OPC_BNEL
: /* rx != rx likely */
2577 case OPC_BGTZL
: /* 0 > 0 likely */
2578 case OPC_BLTZL
: /* 0 < 0 likely */
2579 /* Skip the instruction in the delay slot */
2580 MIPS_DEBUG("bnever and skip");
2584 ctx
->hflags
|= MIPS_HFLAG_B
;
2585 MIPS_DEBUG("j " TARGET_FMT_lx
, btgt
);
2589 ctx
->hflags
|= MIPS_HFLAG_B
;
2590 MIPS_DEBUG("jal " TARGET_FMT_lx
, btgt
);
2593 ctx
->hflags
|= MIPS_HFLAG_BR
;
2594 MIPS_DEBUG("jr %s", regnames
[rs
]);
2598 ctx
->hflags
|= MIPS_HFLAG_BR
;
2599 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
2602 MIPS_INVAL("branch/jump");
2603 generate_exception(ctx
, EXCP_RI
);
2609 gen_op_eq(bcond
, t0
, t1
);
2610 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
2611 regnames
[rs
], regnames
[rt
], btgt
);
2614 gen_op_eq(bcond
, t0
, t1
);
2615 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
2616 regnames
[rs
], regnames
[rt
], btgt
);
2619 gen_op_ne(bcond
, t0
, t1
);
2620 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
2621 regnames
[rs
], regnames
[rt
], btgt
);
2624 gen_op_ne(bcond
, t0
, t1
);
2625 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
2626 regnames
[rs
], regnames
[rt
], btgt
);
2629 gen_op_gez(bcond
, t0
);
2630 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2633 gen_op_gez(bcond
, t0
);
2634 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2637 gen_op_gez(bcond
, t0
);
2638 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2642 gen_op_gez(bcond
, t0
);
2644 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2647 gen_op_gtz(bcond
, t0
);
2648 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2651 gen_op_gtz(bcond
, t0
);
2652 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2655 gen_op_lez(bcond
, t0
);
2656 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2659 gen_op_lez(bcond
, t0
);
2660 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2663 gen_op_ltz(bcond
, t0
);
2664 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2667 gen_op_ltz(bcond
, t0
);
2668 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2671 gen_op_ltz(bcond
, t0
);
2673 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2675 ctx
->hflags
|= MIPS_HFLAG_BC
;
2678 gen_op_ltz(bcond
, t0
);
2680 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2682 ctx
->hflags
|= MIPS_HFLAG_BL
;
2685 MIPS_INVAL("conditional branch/jump");
2686 generate_exception(ctx
, EXCP_RI
);
2690 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2691 blink
, ctx
->hflags
, btgt
);
2693 ctx
->btarget
= btgt
;
2695 tcg_gen_movi_tl(cpu_gpr
[blink
], ctx
->pc
+ 8);
2703 /* special3 bitfield operations */
2704 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2705 int rs
, int lsb
, int msb
)
2707 TCGv t0
= tcg_temp_new();
2708 TCGv t1
= tcg_temp_new();
2711 gen_load_gpr(t1
, rs
);
2716 tcg_gen_shri_tl(t0
, t1
, lsb
);
2718 tcg_gen_andi_tl(t0
, t0
, (1 << (msb
+ 1)) - 1);
2720 tcg_gen_ext32s_tl(t0
, t0
);
2723 #if defined(TARGET_MIPS64)
2725 tcg_gen_shri_tl(t0
, t1
, lsb
);
2727 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1 + 32)) - 1);
2731 tcg_gen_shri_tl(t0
, t1
, lsb
+ 32);
2732 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2735 tcg_gen_shri_tl(t0
, t1
, lsb
);
2736 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2742 mask
= ((msb
- lsb
+ 1 < 32) ? ((1 << (msb
- lsb
+ 1)) - 1) : ~0) << lsb
;
2743 gen_load_gpr(t0
, rt
);
2744 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2745 tcg_gen_shli_tl(t1
, t1
, lsb
);
2746 tcg_gen_andi_tl(t1
, t1
, mask
);
2747 tcg_gen_or_tl(t0
, t0
, t1
);
2748 tcg_gen_ext32s_tl(t0
, t0
);
2750 #if defined(TARGET_MIPS64)
2754 mask
= ((msb
- lsb
+ 1 + 32 < 64) ? ((1ULL << (msb
- lsb
+ 1 + 32)) - 1) : ~0ULL) << lsb
;
2755 gen_load_gpr(t0
, rt
);
2756 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2757 tcg_gen_shli_tl(t1
, t1
, lsb
);
2758 tcg_gen_andi_tl(t1
, t1
, mask
);
2759 tcg_gen_or_tl(t0
, t0
, t1
);
2764 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << (lsb
+ 32);
2765 gen_load_gpr(t0
, rt
);
2766 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2767 tcg_gen_shli_tl(t1
, t1
, lsb
+ 32);
2768 tcg_gen_andi_tl(t1
, t1
, mask
);
2769 tcg_gen_or_tl(t0
, t0
, t1
);
2774 gen_load_gpr(t0
, rt
);
2775 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2776 gen_load_gpr(t0
, rt
);
2777 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2778 tcg_gen_shli_tl(t1
, t1
, lsb
);
2779 tcg_gen_andi_tl(t1
, t1
, mask
);
2780 tcg_gen_or_tl(t0
, t0
, t1
);
2785 MIPS_INVAL("bitops");
2786 generate_exception(ctx
, EXCP_RI
);
2791 gen_store_gpr(t0
, rt
);
2796 static void gen_bshfl (DisasContext
*ctx
, uint32_t op2
, int rt
, int rd
)
2801 /* If no destination, treat it as a NOP. */
2806 t0
= tcg_temp_new();
2807 gen_load_gpr(t0
, rt
);
2811 TCGv t1
= tcg_temp_new();
2813 tcg_gen_shri_tl(t1
, t0
, 8);
2814 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF);
2815 tcg_gen_shli_tl(t0
, t0
, 8);
2816 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF);
2817 tcg_gen_or_tl(t0
, t0
, t1
);
2819 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
2823 tcg_gen_ext8s_tl(cpu_gpr
[rd
], t0
);
2826 tcg_gen_ext16s_tl(cpu_gpr
[rd
], t0
);
2828 #if defined(TARGET_MIPS64)
2831 TCGv t1
= tcg_temp_new();
2833 tcg_gen_shri_tl(t1
, t0
, 8);
2834 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF00FF00FFULL
);
2835 tcg_gen_shli_tl(t0
, t0
, 8);
2836 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF00FF00FFULL
);
2837 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
2843 TCGv t1
= tcg_temp_new();
2845 tcg_gen_shri_tl(t1
, t0
, 16);
2846 tcg_gen_andi_tl(t1
, t1
, 0x0000FFFF0000FFFFULL
);
2847 tcg_gen_shli_tl(t0
, t0
, 16);
2848 tcg_gen_andi_tl(t0
, t0
, ~0x0000FFFF0000FFFFULL
);
2849 tcg_gen_or_tl(t0
, t0
, t1
);
2850 tcg_gen_shri_tl(t1
, t0
, 32);
2851 tcg_gen_shli_tl(t0
, t0
, 32);
2852 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
2858 MIPS_INVAL("bsfhl");
2859 generate_exception(ctx
, EXCP_RI
);
2866 #ifndef CONFIG_USER_ONLY
2867 /* CP0 (MMU and control) */
2868 static inline void gen_mfc0_load32 (TCGv arg
, target_ulong off
)
2870 TCGv_i32 t0
= tcg_temp_new_i32();
2872 tcg_gen_ld_i32(t0
, cpu_env
, off
);
2873 tcg_gen_ext_i32_tl(arg
, t0
);
2874 tcg_temp_free_i32(t0
);
2877 static inline void gen_mfc0_load64 (TCGv arg
, target_ulong off
)
2879 tcg_gen_ld_tl(arg
, cpu_env
, off
);
2880 tcg_gen_ext32s_tl(arg
, arg
);
2883 static inline void gen_mtc0_store32 (TCGv arg
, target_ulong off
)
2885 TCGv_i32 t0
= tcg_temp_new_i32();
2887 tcg_gen_trunc_tl_i32(t0
, arg
);
2888 tcg_gen_st_i32(t0
, cpu_env
, off
);
2889 tcg_temp_free_i32(t0
);
2892 static inline void gen_mtc0_store64 (TCGv arg
, target_ulong off
)
2894 tcg_gen_ext32s_tl(arg
, arg
);
2895 tcg_gen_st_tl(arg
, cpu_env
, off
);
2898 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
2900 const char *rn
= "invalid";
2903 check_insn(env
, ctx
, ISA_MIPS32
);
2909 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Index
));
2913 check_insn(env
, ctx
, ASE_MT
);
2914 gen_helper_mfc0_mvpcontrol(arg
);
2918 check_insn(env
, ctx
, ASE_MT
);
2919 gen_helper_mfc0_mvpconf0(arg
);
2923 check_insn(env
, ctx
, ASE_MT
);
2924 gen_helper_mfc0_mvpconf1(arg
);
2934 gen_helper_mfc0_random(arg
);
2938 check_insn(env
, ctx
, ASE_MT
);
2939 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEControl
));
2943 check_insn(env
, ctx
, ASE_MT
);
2944 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf0
));
2948 check_insn(env
, ctx
, ASE_MT
);
2949 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf1
));
2953 check_insn(env
, ctx
, ASE_MT
);
2954 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_YQMask
));
2958 check_insn(env
, ctx
, ASE_MT
);
2959 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_VPESchedule
));
2963 check_insn(env
, ctx
, ASE_MT
);
2964 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_VPEScheFBack
));
2965 rn
= "VPEScheFBack";
2968 check_insn(env
, ctx
, ASE_MT
);
2969 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEOpt
));
2979 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
2980 tcg_gen_ext32s_tl(arg
, arg
);
2984 check_insn(env
, ctx
, ASE_MT
);
2985 gen_helper_mfc0_tcstatus(arg
);
2989 check_insn(env
, ctx
, ASE_MT
);
2990 gen_helper_mfc0_tcbind(arg
);
2994 check_insn(env
, ctx
, ASE_MT
);
2995 gen_helper_mfc0_tcrestart(arg
);
2999 check_insn(env
, ctx
, ASE_MT
);
3000 gen_helper_mfc0_tchalt(arg
);
3004 check_insn(env
, ctx
, ASE_MT
);
3005 gen_helper_mfc0_tccontext(arg
);
3009 check_insn(env
, ctx
, ASE_MT
);
3010 gen_helper_mfc0_tcschedule(arg
);
3014 check_insn(env
, ctx
, ASE_MT
);
3015 gen_helper_mfc0_tcschefback(arg
);
3025 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
3026 tcg_gen_ext32s_tl(arg
, arg
);
3036 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_Context
));
3037 tcg_gen_ext32s_tl(arg
, arg
);
3041 // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
3042 rn
= "ContextConfig";
3051 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageMask
));
3055 check_insn(env
, ctx
, ISA_MIPS32R2
);
3056 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageGrain
));
3066 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Wired
));
3070 check_insn(env
, ctx
, ISA_MIPS32R2
);
3071 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf0
));
3075 check_insn(env
, ctx
, ISA_MIPS32R2
);
3076 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf1
));
3080 check_insn(env
, ctx
, ISA_MIPS32R2
);
3081 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf2
));
3085 check_insn(env
, ctx
, ISA_MIPS32R2
);
3086 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf3
));
3090 check_insn(env
, ctx
, ISA_MIPS32R2
);
3091 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf4
));
3101 check_insn(env
, ctx
, ISA_MIPS32R2
);
3102 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_HWREna
));
3112 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
3113 tcg_gen_ext32s_tl(arg
, arg
);
3123 /* Mark as an IO operation because we read the time. */
3126 gen_helper_mfc0_count(arg
);
3129 ctx
->bstate
= BS_STOP
;
3133 /* 6,7 are implementation dependent */
3141 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
3142 tcg_gen_ext32s_tl(arg
, arg
);
3152 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Compare
));
3155 /* 6,7 are implementation dependent */
3163 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Status
));
3167 check_insn(env
, ctx
, ISA_MIPS32R2
);
3168 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_IntCtl
));
3172 check_insn(env
, ctx
, ISA_MIPS32R2
);
3173 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSCtl
));
3177 check_insn(env
, ctx
, ISA_MIPS32R2
);
3178 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSMap
));
3188 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Cause
));
3198 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
3199 tcg_gen_ext32s_tl(arg
, arg
);
3209 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PRid
));
3213 check_insn(env
, ctx
, ISA_MIPS32R2
);
3214 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_EBase
));
3224 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config0
));
3228 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config1
));
3232 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config2
));
3236 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config3
));
3239 /* 4,5 are reserved */
3240 /* 6,7 are implementation dependent */
3242 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config6
));
3246 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config7
));
3256 gen_helper_mfc0_lladdr(arg
);
3266 gen_helper_1i(mfc0_watchlo
, arg
, sel
);
3276 gen_helper_1i(mfc0_watchhi
, arg
, sel
);
3286 #if defined(TARGET_MIPS64)
3287 check_insn(env
, ctx
, ISA_MIPS3
);
3288 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
3289 tcg_gen_ext32s_tl(arg
, arg
);
3298 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3301 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Framemask
));
3309 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3310 rn
= "'Diagnostic"; /* implementation dependent */
3315 gen_helper_mfc0_debug(arg
); /* EJTAG support */
3319 // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
3320 rn
= "TraceControl";
3323 // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
3324 rn
= "TraceControl2";
3327 // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
3328 rn
= "UserTraceData";
3331 // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
3342 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
3343 tcg_gen_ext32s_tl(arg
, arg
);
3353 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Performance0
));
3354 rn
= "Performance0";
3357 // gen_helper_mfc0_performance1(arg);
3358 rn
= "Performance1";
3361 // gen_helper_mfc0_performance2(arg);
3362 rn
= "Performance2";
3365 // gen_helper_mfc0_performance3(arg);
3366 rn
= "Performance3";
3369 // gen_helper_mfc0_performance4(arg);
3370 rn
= "Performance4";
3373 // gen_helper_mfc0_performance5(arg);
3374 rn
= "Performance5";
3377 // gen_helper_mfc0_performance6(arg);
3378 rn
= "Performance6";
3381 // gen_helper_mfc0_performance7(arg);
3382 rn
= "Performance7";
3389 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3395 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3408 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagLo
));
3415 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataLo
));
3428 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagHi
));
3435 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataHi
));
3445 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
3446 tcg_gen_ext32s_tl(arg
, arg
);
3457 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DESAVE
));
3467 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3471 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3472 generate_exception(ctx
, EXCP_RI
);
3475 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
3477 const char *rn
= "invalid";
3480 check_insn(env
, ctx
, ISA_MIPS32
);
3489 gen_helper_mtc0_index(arg
);
3493 check_insn(env
, ctx
, ASE_MT
);
3494 gen_helper_mtc0_mvpcontrol(arg
);
3498 check_insn(env
, ctx
, ASE_MT
);
3503 check_insn(env
, ctx
, ASE_MT
);
3518 check_insn(env
, ctx
, ASE_MT
);
3519 gen_helper_mtc0_vpecontrol(arg
);
3523 check_insn(env
, ctx
, ASE_MT
);
3524 gen_helper_mtc0_vpeconf0(arg
);
3528 check_insn(env
, ctx
, ASE_MT
);
3529 gen_helper_mtc0_vpeconf1(arg
);
3533 check_insn(env
, ctx
, ASE_MT
);
3534 gen_helper_mtc0_yqmask(arg
);
3538 check_insn(env
, ctx
, ASE_MT
);
3539 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_VPESchedule
));
3543 check_insn(env
, ctx
, ASE_MT
);
3544 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_VPEScheFBack
));
3545 rn
= "VPEScheFBack";
3548 check_insn(env
, ctx
, ASE_MT
);
3549 gen_helper_mtc0_vpeopt(arg
);
3559 gen_helper_mtc0_entrylo0(arg
);
3563 check_insn(env
, ctx
, ASE_MT
);
3564 gen_helper_mtc0_tcstatus(arg
);
3568 check_insn(env
, ctx
, ASE_MT
);
3569 gen_helper_mtc0_tcbind(arg
);
3573 check_insn(env
, ctx
, ASE_MT
);
3574 gen_helper_mtc0_tcrestart(arg
);
3578 check_insn(env
, ctx
, ASE_MT
);
3579 gen_helper_mtc0_tchalt(arg
);
3583 check_insn(env
, ctx
, ASE_MT
);
3584 gen_helper_mtc0_tccontext(arg
);
3588 check_insn(env
, ctx
, ASE_MT
);
3589 gen_helper_mtc0_tcschedule(arg
);
3593 check_insn(env
, ctx
, ASE_MT
);
3594 gen_helper_mtc0_tcschefback(arg
);
3604 gen_helper_mtc0_entrylo1(arg
);
3614 gen_helper_mtc0_context(arg
);
3618 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
3619 rn
= "ContextConfig";
3628 gen_helper_mtc0_pagemask(arg
);
3632 check_insn(env
, ctx
, ISA_MIPS32R2
);
3633 gen_helper_mtc0_pagegrain(arg
);
3643 gen_helper_mtc0_wired(arg
);
3647 check_insn(env
, ctx
, ISA_MIPS32R2
);
3648 gen_helper_mtc0_srsconf0(arg
);
3652 check_insn(env
, ctx
, ISA_MIPS32R2
);
3653 gen_helper_mtc0_srsconf1(arg
);
3657 check_insn(env
, ctx
, ISA_MIPS32R2
);
3658 gen_helper_mtc0_srsconf2(arg
);
3662 check_insn(env
, ctx
, ISA_MIPS32R2
);
3663 gen_helper_mtc0_srsconf3(arg
);
3667 check_insn(env
, ctx
, ISA_MIPS32R2
);
3668 gen_helper_mtc0_srsconf4(arg
);
3678 check_insn(env
, ctx
, ISA_MIPS32R2
);
3679 gen_helper_mtc0_hwrena(arg
);
3693 gen_helper_mtc0_count(arg
);
3696 /* 6,7 are implementation dependent */
3704 gen_helper_mtc0_entryhi(arg
);
3714 gen_helper_mtc0_compare(arg
);
3717 /* 6,7 are implementation dependent */
3725 save_cpu_state(ctx
, 1);
3726 gen_helper_mtc0_status(arg
);
3727 /* BS_STOP isn't good enough here, hflags may have changed. */
3728 gen_save_pc(ctx
->pc
+ 4);
3729 ctx
->bstate
= BS_EXCP
;
3733 check_insn(env
, ctx
, ISA_MIPS32R2
);
3734 gen_helper_mtc0_intctl(arg
);
3735 /* Stop translation as we may have switched the execution mode */
3736 ctx
->bstate
= BS_STOP
;
3740 check_insn(env
, ctx
, ISA_MIPS32R2
);
3741 gen_helper_mtc0_srsctl(arg
);
3742 /* Stop translation as we may have switched the execution mode */
3743 ctx
->bstate
= BS_STOP
;
3747 check_insn(env
, ctx
, ISA_MIPS32R2
);
3748 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_SRSMap
));
3749 /* Stop translation as we may have switched the execution mode */
3750 ctx
->bstate
= BS_STOP
;
3760 save_cpu_state(ctx
, 1);
3761 gen_helper_mtc0_cause(arg
);
3771 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_EPC
));
3785 check_insn(env
, ctx
, ISA_MIPS32R2
);
3786 gen_helper_mtc0_ebase(arg
);
3796 gen_helper_mtc0_config0(arg
);
3798 /* Stop translation as we may have switched the execution mode */
3799 ctx
->bstate
= BS_STOP
;
3802 /* ignored, read only */
3806 gen_helper_mtc0_config2(arg
);
3808 /* Stop translation as we may have switched the execution mode */
3809 ctx
->bstate
= BS_STOP
;
3812 /* ignored, read only */
3815 /* 4,5 are reserved */
3816 /* 6,7 are implementation dependent */
3826 rn
= "Invalid config selector";
3833 gen_helper_mtc0_lladdr(arg
);
3843 gen_helper_1i(mtc0_watchlo
, arg
, sel
);
3853 gen_helper_1i(mtc0_watchhi
, arg
, sel
);
3863 #if defined(TARGET_MIPS64)
3864 check_insn(env
, ctx
, ISA_MIPS3
);
3865 gen_helper_mtc0_xcontext(arg
);
3874 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3877 gen_helper_mtc0_framemask(arg
);
3886 rn
= "Diagnostic"; /* implementation dependent */
3891 gen_helper_mtc0_debug(arg
); /* EJTAG support */
3892 /* BS_STOP isn't good enough here, hflags may have changed. */
3893 gen_save_pc(ctx
->pc
+ 4);
3894 ctx
->bstate
= BS_EXCP
;
3898 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
3899 rn
= "TraceControl";
3900 /* Stop translation as we may have switched the execution mode */
3901 ctx
->bstate
= BS_STOP
;
3904 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
3905 rn
= "TraceControl2";
3906 /* Stop translation as we may have switched the execution mode */
3907 ctx
->bstate
= BS_STOP
;
3910 /* Stop translation as we may have switched the execution mode */
3911 ctx
->bstate
= BS_STOP
;
3912 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
3913 rn
= "UserTraceData";
3914 /* Stop translation as we may have switched the execution mode */
3915 ctx
->bstate
= BS_STOP
;
3918 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
3919 /* Stop translation as we may have switched the execution mode */
3920 ctx
->bstate
= BS_STOP
;
3931 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_DEPC
));
3941 gen_helper_mtc0_performance0(arg
);
3942 rn
= "Performance0";
3945 // gen_helper_mtc0_performance1(arg);
3946 rn
= "Performance1";
3949 // gen_helper_mtc0_performance2(arg);
3950 rn
= "Performance2";
3953 // gen_helper_mtc0_performance3(arg);
3954 rn
= "Performance3";
3957 // gen_helper_mtc0_performance4(arg);
3958 rn
= "Performance4";
3961 // gen_helper_mtc0_performance5(arg);
3962 rn
= "Performance5";
3965 // gen_helper_mtc0_performance6(arg);
3966 rn
= "Performance6";
3969 // gen_helper_mtc0_performance7(arg);
3970 rn
= "Performance7";
3996 gen_helper_mtc0_taglo(arg
);
4003 gen_helper_mtc0_datalo(arg
);
4016 gen_helper_mtc0_taghi(arg
);
4023 gen_helper_mtc0_datahi(arg
);
4034 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_ErrorEPC
));
4045 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_DESAVE
));
4051 /* Stop translation as we may have switched the execution mode */
4052 ctx
->bstate
= BS_STOP
;
4057 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4058 /* For simplicity assume that all writes can cause interrupts. */
4061 ctx
->bstate
= BS_STOP
;
4066 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4067 generate_exception(ctx
, EXCP_RI
);
4070 #if defined(TARGET_MIPS64)
4071 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
4073 const char *rn
= "invalid";
4076 check_insn(env
, ctx
, ISA_MIPS64
);
4082 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Index
));
4086 check_insn(env
, ctx
, ASE_MT
);
4087 gen_helper_mfc0_mvpcontrol(arg
);
4091 check_insn(env
, ctx
, ASE_MT
);
4092 gen_helper_mfc0_mvpconf0(arg
);
4096 check_insn(env
, ctx
, ASE_MT
);
4097 gen_helper_mfc0_mvpconf1(arg
);
4107 gen_helper_mfc0_random(arg
);
4111 check_insn(env
, ctx
, ASE_MT
);
4112 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEControl
));
4116 check_insn(env
, ctx
, ASE_MT
);
4117 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf0
));
4121 check_insn(env
, ctx
, ASE_MT
);
4122 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf1
));
4126 check_insn(env
, ctx
, ASE_MT
);
4127 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_YQMask
));
4131 check_insn(env
, ctx
, ASE_MT
);
4132 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4136 check_insn(env
, ctx
, ASE_MT
);
4137 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4138 rn
= "VPEScheFBack";
4141 check_insn(env
, ctx
, ASE_MT
);
4142 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEOpt
));
4152 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
4156 check_insn(env
, ctx
, ASE_MT
);
4157 gen_helper_mfc0_tcstatus(arg
);
4161 check_insn(env
, ctx
, ASE_MT
);
4162 gen_helper_mfc0_tcbind(arg
);
4166 check_insn(env
, ctx
, ASE_MT
);
4167 gen_helper_dmfc0_tcrestart(arg
);
4171 check_insn(env
, ctx
, ASE_MT
);
4172 gen_helper_dmfc0_tchalt(arg
);
4176 check_insn(env
, ctx
, ASE_MT
);
4177 gen_helper_dmfc0_tccontext(arg
);
4181 check_insn(env
, ctx
, ASE_MT
);
4182 gen_helper_dmfc0_tcschedule(arg
);
4186 check_insn(env
, ctx
, ASE_MT
);
4187 gen_helper_dmfc0_tcschefback(arg
);
4197 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
4207 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_Context
));
4211 // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
4212 rn
= "ContextConfig";
4221 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageMask
));
4225 check_insn(env
, ctx
, ISA_MIPS32R2
);
4226 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageGrain
));
4236 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Wired
));
4240 check_insn(env
, ctx
, ISA_MIPS32R2
);
4241 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf0
));
4245 check_insn(env
, ctx
, ISA_MIPS32R2
);
4246 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf1
));
4250 check_insn(env
, ctx
, ISA_MIPS32R2
);
4251 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf2
));
4255 check_insn(env
, ctx
, ISA_MIPS32R2
);
4256 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf3
));
4260 check_insn(env
, ctx
, ISA_MIPS32R2
);
4261 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf4
));
4271 check_insn(env
, ctx
, ISA_MIPS32R2
);
4272 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_HWREna
));
4282 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
4292 /* Mark as an IO operation because we read the time. */
4295 gen_helper_mfc0_count(arg
);
4298 ctx
->bstate
= BS_STOP
;
4302 /* 6,7 are implementation dependent */
4310 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
4320 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Compare
));
4323 /* 6,7 are implementation dependent */
4331 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Status
));
4335 check_insn(env
, ctx
, ISA_MIPS32R2
);
4336 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_IntCtl
));
4340 check_insn(env
, ctx
, ISA_MIPS32R2
);
4341 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSCtl
));
4345 check_insn(env
, ctx
, ISA_MIPS32R2
);
4346 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSMap
));
4356 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Cause
));
4366 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4376 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PRid
));
4380 check_insn(env
, ctx
, ISA_MIPS32R2
);
4381 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_EBase
));
4391 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config0
));
4395 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config1
));
4399 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config2
));
4403 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config3
));
4406 /* 6,7 are implementation dependent */
4408 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config6
));
4412 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config7
));
4422 gen_helper_dmfc0_lladdr(arg
);
4432 gen_helper_1i(dmfc0_watchlo
, arg
, sel
);
4442 gen_helper_1i(mfc0_watchhi
, arg
, sel
);
4452 check_insn(env
, ctx
, ISA_MIPS3
);
4453 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
4461 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4464 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Framemask
));
4472 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4473 rn
= "'Diagnostic"; /* implementation dependent */
4478 gen_helper_mfc0_debug(arg
); /* EJTAG support */
4482 // gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
4483 rn
= "TraceControl";
4486 // gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
4487 rn
= "TraceControl2";
4490 // gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
4491 rn
= "UserTraceData";
4494 // gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
4505 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4515 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Performance0
));
4516 rn
= "Performance0";
4519 // gen_helper_dmfc0_performance1(arg);
4520 rn
= "Performance1";
4523 // gen_helper_dmfc0_performance2(arg);
4524 rn
= "Performance2";
4527 // gen_helper_dmfc0_performance3(arg);
4528 rn
= "Performance3";
4531 // gen_helper_dmfc0_performance4(arg);
4532 rn
= "Performance4";
4535 // gen_helper_dmfc0_performance5(arg);
4536 rn
= "Performance5";
4539 // gen_helper_dmfc0_performance6(arg);
4540 rn
= "Performance6";
4543 // gen_helper_dmfc0_performance7(arg);
4544 rn
= "Performance7";
4551 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4558 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4571 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagLo
));
4578 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataLo
));
4591 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagHi
));
4598 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataHi
));
4608 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
4619 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DESAVE
));
4629 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4633 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4634 generate_exception(ctx
, EXCP_RI
);
4637 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
4639 const char *rn
= "invalid";
4642 check_insn(env
, ctx
, ISA_MIPS64
);
4651 gen_helper_mtc0_index(arg
);
4655 check_insn(env
, ctx
, ASE_MT
);
4656 gen_helper_mtc0_mvpcontrol(arg
);
4660 check_insn(env
, ctx
, ASE_MT
);
4665 check_insn(env
, ctx
, ASE_MT
);
4680 check_insn(env
, ctx
, ASE_MT
);
4681 gen_helper_mtc0_vpecontrol(arg
);
4685 check_insn(env
, ctx
, ASE_MT
);
4686 gen_helper_mtc0_vpeconf0(arg
);
4690 check_insn(env
, ctx
, ASE_MT
);
4691 gen_helper_mtc0_vpeconf1(arg
);
4695 check_insn(env
, ctx
, ASE_MT
);
4696 gen_helper_mtc0_yqmask(arg
);
4700 check_insn(env
, ctx
, ASE_MT
);
4701 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4705 check_insn(env
, ctx
, ASE_MT
);
4706 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4707 rn
= "VPEScheFBack";
4710 check_insn(env
, ctx
, ASE_MT
);
4711 gen_helper_mtc0_vpeopt(arg
);
4721 gen_helper_mtc0_entrylo0(arg
);
4725 check_insn(env
, ctx
, ASE_MT
);
4726 gen_helper_mtc0_tcstatus(arg
);
4730 check_insn(env
, ctx
, ASE_MT
);
4731 gen_helper_mtc0_tcbind(arg
);
4735 check_insn(env
, ctx
, ASE_MT
);
4736 gen_helper_mtc0_tcrestart(arg
);
4740 check_insn(env
, ctx
, ASE_MT
);
4741 gen_helper_mtc0_tchalt(arg
);
4745 check_insn(env
, ctx
, ASE_MT
);
4746 gen_helper_mtc0_tccontext(arg
);
4750 check_insn(env
, ctx
, ASE_MT
);
4751 gen_helper_mtc0_tcschedule(arg
);
4755 check_insn(env
, ctx
, ASE_MT
);
4756 gen_helper_mtc0_tcschefback(arg
);
4766 gen_helper_mtc0_entrylo1(arg
);
4776 gen_helper_mtc0_context(arg
);
4780 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
4781 rn
= "ContextConfig";
4790 gen_helper_mtc0_pagemask(arg
);
4794 check_insn(env
, ctx
, ISA_MIPS32R2
);
4795 gen_helper_mtc0_pagegrain(arg
);
4805 gen_helper_mtc0_wired(arg
);
4809 check_insn(env
, ctx
, ISA_MIPS32R2
);
4810 gen_helper_mtc0_srsconf0(arg
);
4814 check_insn(env
, ctx
, ISA_MIPS32R2
);
4815 gen_helper_mtc0_srsconf1(arg
);
4819 check_insn(env
, ctx
, ISA_MIPS32R2
);
4820 gen_helper_mtc0_srsconf2(arg
);
4824 check_insn(env
, ctx
, ISA_MIPS32R2
);
4825 gen_helper_mtc0_srsconf3(arg
);
4829 check_insn(env
, ctx
, ISA_MIPS32R2
);
4830 gen_helper_mtc0_srsconf4(arg
);
4840 check_insn(env
, ctx
, ISA_MIPS32R2
);
4841 gen_helper_mtc0_hwrena(arg
);
4855 gen_helper_mtc0_count(arg
);
4858 /* 6,7 are implementation dependent */
4862 /* Stop translation as we may have switched the execution mode */
4863 ctx
->bstate
= BS_STOP
;
4868 gen_helper_mtc0_entryhi(arg
);
4878 gen_helper_mtc0_compare(arg
);
4881 /* 6,7 are implementation dependent */
4885 /* Stop translation as we may have switched the execution mode */
4886 ctx
->bstate
= BS_STOP
;
4891 save_cpu_state(ctx
, 1);
4892 gen_helper_mtc0_status(arg
);
4893 /* BS_STOP isn't good enough here, hflags may have changed. */
4894 gen_save_pc(ctx
->pc
+ 4);
4895 ctx
->bstate
= BS_EXCP
;
4899 check_insn(env
, ctx
, ISA_MIPS32R2
);
4900 gen_helper_mtc0_intctl(arg
);
4901 /* Stop translation as we may have switched the execution mode */
4902 ctx
->bstate
= BS_STOP
;
4906 check_insn(env
, ctx
, ISA_MIPS32R2
);
4907 gen_helper_mtc0_srsctl(arg
);
4908 /* Stop translation as we may have switched the execution mode */
4909 ctx
->bstate
= BS_STOP
;
4913 check_insn(env
, ctx
, ISA_MIPS32R2
);
4914 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_SRSMap
));
4915 /* Stop translation as we may have switched the execution mode */
4916 ctx
->bstate
= BS_STOP
;
4926 save_cpu_state(ctx
, 1);
4927 gen_helper_mtc0_cause(arg
);
4937 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4951 check_insn(env
, ctx
, ISA_MIPS32R2
);
4952 gen_helper_mtc0_ebase(arg
);
4962 gen_helper_mtc0_config0(arg
);
4964 /* Stop translation as we may have switched the execution mode */
4965 ctx
->bstate
= BS_STOP
;
4968 /* ignored, read only */
4972 gen_helper_mtc0_config2(arg
);
4974 /* Stop translation as we may have switched the execution mode */
4975 ctx
->bstate
= BS_STOP
;
4981 /* 6,7 are implementation dependent */
4983 rn
= "Invalid config selector";
4990 gen_helper_mtc0_lladdr(arg
);
5000 gen_helper_1i(mtc0_watchlo
, arg
, sel
);
5010 gen_helper_1i(mtc0_watchhi
, arg
, sel
);
5020 check_insn(env
, ctx
, ISA_MIPS3
);
5021 gen_helper_mtc0_xcontext(arg
);
5029 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5032 gen_helper_mtc0_framemask(arg
);
5041 rn
= "Diagnostic"; /* implementation dependent */
5046 gen_helper_mtc0_debug(arg
); /* EJTAG support */
5047 /* BS_STOP isn't good enough here, hflags may have changed. */
5048 gen_save_pc(ctx
->pc
+ 4);
5049 ctx
->bstate
= BS_EXCP
;
5053 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
5054 /* Stop translation as we may have switched the execution mode */
5055 ctx
->bstate
= BS_STOP
;
5056 rn
= "TraceControl";
5059 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
5060 /* Stop translation as we may have switched the execution mode */
5061 ctx
->bstate
= BS_STOP
;
5062 rn
= "TraceControl2";
5065 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
5066 /* Stop translation as we may have switched the execution mode */
5067 ctx
->bstate
= BS_STOP
;
5068 rn
= "UserTraceData";
5071 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
5072 /* Stop translation as we may have switched the execution mode */
5073 ctx
->bstate
= BS_STOP
;
5084 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
5094 gen_helper_mtc0_performance0(arg
);
5095 rn
= "Performance0";
5098 // gen_helper_mtc0_performance1(arg);
5099 rn
= "Performance1";
5102 // gen_helper_mtc0_performance2(arg);
5103 rn
= "Performance2";
5106 // gen_helper_mtc0_performance3(arg);
5107 rn
= "Performance3";
5110 // gen_helper_mtc0_performance4(arg);
5111 rn
= "Performance4";
5114 // gen_helper_mtc0_performance5(arg);
5115 rn
= "Performance5";
5118 // gen_helper_mtc0_performance6(arg);
5119 rn
= "Performance6";
5122 // gen_helper_mtc0_performance7(arg);
5123 rn
= "Performance7";
5149 gen_helper_mtc0_taglo(arg
);
5156 gen_helper_mtc0_datalo(arg
);
5169 gen_helper_mtc0_taghi(arg
);
5176 gen_helper_mtc0_datahi(arg
);
5187 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
5198 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_DESAVE
));
5204 /* Stop translation as we may have switched the execution mode */
5205 ctx
->bstate
= BS_STOP
;
5210 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5211 /* For simplicity assume that all writes can cause interrupts. */
5214 ctx
->bstate
= BS_STOP
;
5219 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5220 generate_exception(ctx
, EXCP_RI
);
5222 #endif /* TARGET_MIPS64 */
5224 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
,
5225 int u
, int sel
, int h
)
5227 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5228 TCGv t0
= tcg_temp_local_new();
5230 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5231 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5232 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5233 tcg_gen_movi_tl(t0
, -1);
5234 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5235 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5236 tcg_gen_movi_tl(t0
, -1);
5242 gen_helper_mftc0_tcstatus(t0
);
5245 gen_helper_mftc0_tcbind(t0
);
5248 gen_helper_mftc0_tcrestart(t0
);
5251 gen_helper_mftc0_tchalt(t0
);
5254 gen_helper_mftc0_tccontext(t0
);
5257 gen_helper_mftc0_tcschedule(t0
);
5260 gen_helper_mftc0_tcschefback(t0
);
5263 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5270 gen_helper_mftc0_entryhi(t0
);
5273 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5279 gen_helper_mftc0_status(t0
);
5282 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5288 gen_helper_mftc0_debug(t0
);
5291 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5296 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5298 } else switch (sel
) {
5299 /* GPR registers. */
5301 gen_helper_1i(mftgpr
, t0
, rt
);
5303 /* Auxiliary CPU registers */
5307 gen_helper_1i(mftlo
, t0
, 0);
5310 gen_helper_1i(mfthi
, t0
, 0);
5313 gen_helper_1i(mftacx
, t0
, 0);
5316 gen_helper_1i(mftlo
, t0
, 1);
5319 gen_helper_1i(mfthi
, t0
, 1);
5322 gen_helper_1i(mftacx
, t0
, 1);
5325 gen_helper_1i(mftlo
, t0
, 2);
5328 gen_helper_1i(mfthi
, t0
, 2);
5331 gen_helper_1i(mftacx
, t0
, 2);
5334 gen_helper_1i(mftlo
, t0
, 3);
5337 gen_helper_1i(mfthi
, t0
, 3);
5340 gen_helper_1i(mftacx
, t0
, 3);
5343 gen_helper_mftdsp(t0
);
5349 /* Floating point (COP1). */
5351 /* XXX: For now we support only a single FPU context. */
5353 TCGv_i32 fp0
= tcg_temp_new_i32();
5355 gen_load_fpr32(fp0
, rt
);
5356 tcg_gen_ext_i32_tl(t0
, fp0
);
5357 tcg_temp_free_i32(fp0
);
5359 TCGv_i32 fp0
= tcg_temp_new_i32();
5361 gen_load_fpr32h(fp0
, rt
);
5362 tcg_gen_ext_i32_tl(t0
, fp0
);
5363 tcg_temp_free_i32(fp0
);
5367 /* XXX: For now we support only a single FPU context. */
5368 gen_helper_1i(cfc1
, t0
, rt
);
5370 /* COP2: Not implemented. */
5377 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5378 gen_store_gpr(t0
, rd
);
5384 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5385 generate_exception(ctx
, EXCP_RI
);
5388 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
, int rt
,
5389 int u
, int sel
, int h
)
5391 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5392 TCGv t0
= tcg_temp_local_new();
5394 gen_load_gpr(t0
, rt
);
5395 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5396 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5397 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5399 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5400 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5407 gen_helper_mttc0_tcstatus(t0
);
5410 gen_helper_mttc0_tcbind(t0
);
5413 gen_helper_mttc0_tcrestart(t0
);
5416 gen_helper_mttc0_tchalt(t0
);
5419 gen_helper_mttc0_tccontext(t0
);
5422 gen_helper_mttc0_tcschedule(t0
);
5425 gen_helper_mttc0_tcschefback(t0
);
5428 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5435 gen_helper_mttc0_entryhi(t0
);
5438 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5444 gen_helper_mttc0_status(t0
);
5447 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5453 gen_helper_mttc0_debug(t0
);
5456 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5461 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5463 } else switch (sel
) {
5464 /* GPR registers. */
5466 gen_helper_1i(mttgpr
, t0
, rd
);
5468 /* Auxiliary CPU registers */
5472 gen_helper_1i(mttlo
, t0
, 0);
5475 gen_helper_1i(mtthi
, t0
, 0);
5478 gen_helper_1i(mttacx
, t0
, 0);
5481 gen_helper_1i(mttlo
, t0
, 1);
5484 gen_helper_1i(mtthi
, t0
, 1);
5487 gen_helper_1i(mttacx
, t0
, 1);
5490 gen_helper_1i(mttlo
, t0
, 2);
5493 gen_helper_1i(mtthi
, t0
, 2);
5496 gen_helper_1i(mttacx
, t0
, 2);
5499 gen_helper_1i(mttlo
, t0
, 3);
5502 gen_helper_1i(mtthi
, t0
, 3);
5505 gen_helper_1i(mttacx
, t0
, 3);
5508 gen_helper_mttdsp(t0
);
5514 /* Floating point (COP1). */
5516 /* XXX: For now we support only a single FPU context. */
5518 TCGv_i32 fp0
= tcg_temp_new_i32();
5520 tcg_gen_trunc_tl_i32(fp0
, t0
);
5521 gen_store_fpr32(fp0
, rd
);
5522 tcg_temp_free_i32(fp0
);
5524 TCGv_i32 fp0
= tcg_temp_new_i32();
5526 tcg_gen_trunc_tl_i32(fp0
, t0
);
5527 gen_store_fpr32h(fp0
, rd
);
5528 tcg_temp_free_i32(fp0
);
5532 /* XXX: For now we support only a single FPU context. */
5533 gen_helper_1i(ctc1
, t0
, rd
);
5535 /* COP2: Not implemented. */
5542 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5548 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5549 generate_exception(ctx
, EXCP_RI
);
5552 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
5554 const char *opn
= "ldst";
5562 gen_mfc0(env
, ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
5567 TCGv t0
= tcg_temp_new();
5569 gen_load_gpr(t0
, rt
);
5570 gen_mtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5575 #if defined(TARGET_MIPS64)
5577 check_insn(env
, ctx
, ISA_MIPS3
);
5582 gen_dmfc0(env
, ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
5586 check_insn(env
, ctx
, ISA_MIPS3
);
5588 TCGv t0
= tcg_temp_new();
5590 gen_load_gpr(t0
, rt
);
5591 gen_dmtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5598 check_insn(env
, ctx
, ASE_MT
);
5603 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
5604 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5608 check_insn(env
, ctx
, ASE_MT
);
5609 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
5610 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5615 if (!env
->tlb
->helper_tlbwi
)
5621 if (!env
->tlb
->helper_tlbwr
)
5627 if (!env
->tlb
->helper_tlbp
)
5633 if (!env
->tlb
->helper_tlbr
)
5639 check_insn(env
, ctx
, ISA_MIPS2
);
5641 ctx
->bstate
= BS_EXCP
;
5645 check_insn(env
, ctx
, ISA_MIPS32
);
5646 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5648 generate_exception(ctx
, EXCP_RI
);
5651 ctx
->bstate
= BS_EXCP
;
5656 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
5657 /* If we get an exception, we want to restart at next instruction */
5659 save_cpu_state(ctx
, 1);
5662 ctx
->bstate
= BS_EXCP
;
5667 generate_exception(ctx
, EXCP_RI
);
5670 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
5672 #endif /* !CONFIG_USER_ONLY */
5674 /* CP1 Branches (before delay slot) */
5675 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
5676 int32_t cc
, int32_t offset
)
5678 target_ulong btarget
;
5679 const char *opn
= "cp1 cond branch";
5680 TCGv_i32 t0
= tcg_temp_new_i32();
5683 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5685 btarget
= ctx
->pc
+ 4 + offset
;
5689 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5690 tcg_gen_not_i32(t0
, t0
);
5691 tcg_gen_andi_i32(t0
, t0
, 1);
5692 tcg_gen_extu_i32_tl(bcond
, t0
);
5696 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5697 tcg_gen_not_i32(t0
, t0
);
5698 tcg_gen_andi_i32(t0
, t0
, 1);
5699 tcg_gen_extu_i32_tl(bcond
, t0
);
5703 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5704 tcg_gen_andi_i32(t0
, t0
, 1);
5705 tcg_gen_extu_i32_tl(bcond
, t0
);
5709 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5710 tcg_gen_andi_i32(t0
, t0
, 1);
5711 tcg_gen_extu_i32_tl(bcond
, t0
);
5714 ctx
->hflags
|= MIPS_HFLAG_BL
;
5718 TCGv_i32 t1
= tcg_temp_new_i32();
5719 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5720 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5721 tcg_gen_or_i32(t0
, t0
, t1
);
5722 tcg_temp_free_i32(t1
);
5723 tcg_gen_not_i32(t0
, t0
);
5724 tcg_gen_andi_i32(t0
, t0
, 1);
5725 tcg_gen_extu_i32_tl(bcond
, t0
);
5731 TCGv_i32 t1
= tcg_temp_new_i32();
5732 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5733 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5734 tcg_gen_or_i32(t0
, t0
, t1
);
5735 tcg_temp_free_i32(t1
);
5736 tcg_gen_andi_i32(t0
, t0
, 1);
5737 tcg_gen_extu_i32_tl(bcond
, t0
);
5743 TCGv_i32 t1
= tcg_temp_new_i32();
5744 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5745 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5746 tcg_gen_or_i32(t0
, t0
, t1
);
5747 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
5748 tcg_gen_or_i32(t0
, t0
, t1
);
5749 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
5750 tcg_gen_or_i32(t0
, t0
, t1
);
5751 tcg_temp_free_i32(t1
);
5752 tcg_gen_not_i32(t0
, t0
);
5753 tcg_gen_andi_i32(t0
, t0
, 1);
5754 tcg_gen_extu_i32_tl(bcond
, t0
);
5760 TCGv_i32 t1
= tcg_temp_new_i32();
5761 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5762 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5763 tcg_gen_or_i32(t0
, t0
, t1
);
5764 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
5765 tcg_gen_or_i32(t0
, t0
, t1
);
5766 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
5767 tcg_gen_or_i32(t0
, t0
, t1
);
5768 tcg_temp_free_i32(t1
);
5769 tcg_gen_andi_i32(t0
, t0
, 1);
5770 tcg_gen_extu_i32_tl(bcond
, t0
);
5774 ctx
->hflags
|= MIPS_HFLAG_BC
;
5778 generate_exception (ctx
, EXCP_RI
);
5781 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
5782 ctx
->hflags
, btarget
);
5783 ctx
->btarget
= btarget
;
5786 tcg_temp_free_i32(t0
);
5789 /* Coprocessor 1 (FPU) */
5791 #define FOP(func, fmt) (((fmt) << 21) | (func))
5793 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
5795 const char *opn
= "cp1 move";
5796 TCGv t0
= tcg_temp_new();
5801 TCGv_i32 fp0
= tcg_temp_new_i32();
5803 gen_load_fpr32(fp0
, fs
);
5804 tcg_gen_ext_i32_tl(t0
, fp0
);
5805 tcg_temp_free_i32(fp0
);
5807 gen_store_gpr(t0
, rt
);
5811 gen_load_gpr(t0
, rt
);
5813 TCGv_i32 fp0
= tcg_temp_new_i32();
5815 tcg_gen_trunc_tl_i32(fp0
, t0
);
5816 gen_store_fpr32(fp0
, fs
);
5817 tcg_temp_free_i32(fp0
);
5822 gen_helper_1i(cfc1
, t0
, fs
);
5823 gen_store_gpr(t0
, rt
);
5827 gen_load_gpr(t0
, rt
);
5828 gen_helper_1i(ctc1
, t0
, fs
);
5831 #if defined(TARGET_MIPS64)
5833 gen_load_fpr64(ctx
, t0
, fs
);
5834 gen_store_gpr(t0
, rt
);
5838 gen_load_gpr(t0
, rt
);
5839 gen_store_fpr64(ctx
, t0
, fs
);
5845 TCGv_i32 fp0
= tcg_temp_new_i32();
5847 gen_load_fpr32h(fp0
, fs
);
5848 tcg_gen_ext_i32_tl(t0
, fp0
);
5849 tcg_temp_free_i32(fp0
);
5851 gen_store_gpr(t0
, rt
);
5855 gen_load_gpr(t0
, rt
);
5857 TCGv_i32 fp0
= tcg_temp_new_i32();
5859 tcg_gen_trunc_tl_i32(fp0
, t0
);
5860 gen_store_fpr32h(fp0
, fs
);
5861 tcg_temp_free_i32(fp0
);
5867 generate_exception (ctx
, EXCP_RI
);
5870 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
5876 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
5892 l1
= gen_new_label();
5893 t0
= tcg_temp_new_i32();
5894 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
5895 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5896 tcg_temp_free_i32(t0
);
5898 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5900 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
5905 static inline void gen_movcf_s (int fs
, int fd
, int cc
, int tf
)
5908 TCGv_i32 t0
= tcg_temp_new_i32();
5909 int l1
= gen_new_label();
5916 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
5917 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5918 gen_load_fpr32(t0
, fs
);
5919 gen_store_fpr32(t0
, fd
);
5921 tcg_temp_free_i32(t0
);
5924 static inline void gen_movcf_d (DisasContext
*ctx
, int fs
, int fd
, int cc
, int tf
)
5927 TCGv_i32 t0
= tcg_temp_new_i32();
5929 int l1
= gen_new_label();
5936 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
5937 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5938 tcg_temp_free_i32(t0
);
5939 fp0
= tcg_temp_new_i64();
5940 gen_load_fpr64(ctx
, fp0
, fs
);
5941 gen_store_fpr64(ctx
, fp0
, fd
);
5942 tcg_temp_free_i64(fp0
);
5946 static inline void gen_movcf_ps (int fs
, int fd
, int cc
, int tf
)
5949 TCGv_i32 t0
= tcg_temp_new_i32();
5950 int l1
= gen_new_label();
5951 int l2
= gen_new_label();
5958 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
5959 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5960 gen_load_fpr32(t0
, fs
);
5961 gen_store_fpr32(t0
, fd
);
5964 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
+1));
5965 tcg_gen_brcondi_i32(cond
, t0
, 0, l2
);
5966 gen_load_fpr32h(t0
, fs
);
5967 gen_store_fpr32h(t0
, fd
);
5968 tcg_temp_free_i32(t0
);
5973 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
5974 int ft
, int fs
, int fd
, int cc
)
5976 const char *opn
= "farith";
5977 const char *condnames
[] = {
5995 const char *condnames_abs
[] = {
6013 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
6014 uint32_t func
= ctx
->opcode
& 0x3f;
6016 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
6019 TCGv_i32 fp0
= tcg_temp_new_i32();
6020 TCGv_i32 fp1
= tcg_temp_new_i32();
6022 gen_load_fpr32(fp0
, fs
);
6023 gen_load_fpr32(fp1
, ft
);
6024 gen_helper_float_add_s(fp0
, fp0
, fp1
);
6025 tcg_temp_free_i32(fp1
);
6026 gen_store_fpr32(fp0
, fd
);
6027 tcg_temp_free_i32(fp0
);
6034 TCGv_i32 fp0
= tcg_temp_new_i32();
6035 TCGv_i32 fp1
= tcg_temp_new_i32();
6037 gen_load_fpr32(fp0
, fs
);
6038 gen_load_fpr32(fp1
, ft
);
6039 gen_helper_float_sub_s(fp0
, fp0
, fp1
);
6040 tcg_temp_free_i32(fp1
);
6041 gen_store_fpr32(fp0
, fd
);
6042 tcg_temp_free_i32(fp0
);
6049 TCGv_i32 fp0
= tcg_temp_new_i32();
6050 TCGv_i32 fp1
= tcg_temp_new_i32();
6052 gen_load_fpr32(fp0
, fs
);
6053 gen_load_fpr32(fp1
, ft
);
6054 gen_helper_float_mul_s(fp0
, fp0
, fp1
);
6055 tcg_temp_free_i32(fp1
);
6056 gen_store_fpr32(fp0
, fd
);
6057 tcg_temp_free_i32(fp0
);
6064 TCGv_i32 fp0
= tcg_temp_new_i32();
6065 TCGv_i32 fp1
= tcg_temp_new_i32();
6067 gen_load_fpr32(fp0
, fs
);
6068 gen_load_fpr32(fp1
, ft
);
6069 gen_helper_float_div_s(fp0
, fp0
, fp1
);
6070 tcg_temp_free_i32(fp1
);
6071 gen_store_fpr32(fp0
, fd
);
6072 tcg_temp_free_i32(fp0
);
6079 TCGv_i32 fp0
= tcg_temp_new_i32();
6081 gen_load_fpr32(fp0
, fs
);
6082 gen_helper_float_sqrt_s(fp0
, fp0
);
6083 gen_store_fpr32(fp0
, fd
);
6084 tcg_temp_free_i32(fp0
);
6090 TCGv_i32 fp0
= tcg_temp_new_i32();
6092 gen_load_fpr32(fp0
, fs
);
6093 gen_helper_float_abs_s(fp0
, fp0
);
6094 gen_store_fpr32(fp0
, fd
);
6095 tcg_temp_free_i32(fp0
);
6101 TCGv_i32 fp0
= tcg_temp_new_i32();
6103 gen_load_fpr32(fp0
, fs
);
6104 gen_store_fpr32(fp0
, fd
);
6105 tcg_temp_free_i32(fp0
);
6111 TCGv_i32 fp0
= tcg_temp_new_i32();
6113 gen_load_fpr32(fp0
, fs
);
6114 gen_helper_float_chs_s(fp0
, fp0
);
6115 gen_store_fpr32(fp0
, fd
);
6116 tcg_temp_free_i32(fp0
);
6121 check_cp1_64bitmode(ctx
);
6123 TCGv_i32 fp32
= tcg_temp_new_i32();
6124 TCGv_i64 fp64
= tcg_temp_new_i64();
6126 gen_load_fpr32(fp32
, fs
);
6127 gen_helper_float_roundl_s(fp64
, fp32
);
6128 tcg_temp_free_i32(fp32
);
6129 gen_store_fpr64(ctx
, fp64
, fd
);
6130 tcg_temp_free_i64(fp64
);
6135 check_cp1_64bitmode(ctx
);
6137 TCGv_i32 fp32
= tcg_temp_new_i32();
6138 TCGv_i64 fp64
= tcg_temp_new_i64();
6140 gen_load_fpr32(fp32
, fs
);
6141 gen_helper_float_truncl_s(fp64
, fp32
);
6142 tcg_temp_free_i32(fp32
);
6143 gen_store_fpr64(ctx
, fp64
, fd
);
6144 tcg_temp_free_i64(fp64
);
6149 check_cp1_64bitmode(ctx
);
6151 TCGv_i32 fp32
= tcg_temp_new_i32();
6152 TCGv_i64 fp64
= tcg_temp_new_i64();
6154 gen_load_fpr32(fp32
, fs
);
6155 gen_helper_float_ceill_s(fp64
, fp32
);
6156 tcg_temp_free_i32(fp32
);
6157 gen_store_fpr64(ctx
, fp64
, fd
);
6158 tcg_temp_free_i64(fp64
);
6163 check_cp1_64bitmode(ctx
);
6165 TCGv_i32 fp32
= tcg_temp_new_i32();
6166 TCGv_i64 fp64
= tcg_temp_new_i64();
6168 gen_load_fpr32(fp32
, fs
);
6169 gen_helper_float_floorl_s(fp64
, fp32
);
6170 tcg_temp_free_i32(fp32
);
6171 gen_store_fpr64(ctx
, fp64
, fd
);
6172 tcg_temp_free_i64(fp64
);
6178 TCGv_i32 fp0
= tcg_temp_new_i32();
6180 gen_load_fpr32(fp0
, fs
);
6181 gen_helper_float_roundw_s(fp0
, fp0
);
6182 gen_store_fpr32(fp0
, fd
);
6183 tcg_temp_free_i32(fp0
);
6189 TCGv_i32 fp0
= tcg_temp_new_i32();
6191 gen_load_fpr32(fp0
, fs
);
6192 gen_helper_float_truncw_s(fp0
, fp0
);
6193 gen_store_fpr32(fp0
, fd
);
6194 tcg_temp_free_i32(fp0
);
6200 TCGv_i32 fp0
= tcg_temp_new_i32();
6202 gen_load_fpr32(fp0
, fs
);
6203 gen_helper_float_ceilw_s(fp0
, fp0
);
6204 gen_store_fpr32(fp0
, fd
);
6205 tcg_temp_free_i32(fp0
);
6211 TCGv_i32 fp0
= tcg_temp_new_i32();
6213 gen_load_fpr32(fp0
, fs
);
6214 gen_helper_float_floorw_s(fp0
, fp0
);
6215 gen_store_fpr32(fp0
, fd
);
6216 tcg_temp_free_i32(fp0
);
6221 gen_movcf_s(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6226 int l1
= gen_new_label();
6230 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6232 fp0
= tcg_temp_new_i32();
6233 gen_load_fpr32(fp0
, fs
);
6234 gen_store_fpr32(fp0
, fd
);
6235 tcg_temp_free_i32(fp0
);
6242 int l1
= gen_new_label();
6246 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6247 fp0
= tcg_temp_new_i32();
6248 gen_load_fpr32(fp0
, fs
);
6249 gen_store_fpr32(fp0
, fd
);
6250 tcg_temp_free_i32(fp0
);
6259 TCGv_i32 fp0
= tcg_temp_new_i32();
6261 gen_load_fpr32(fp0
, fs
);
6262 gen_helper_float_recip_s(fp0
, fp0
);
6263 gen_store_fpr32(fp0
, fd
);
6264 tcg_temp_free_i32(fp0
);
6271 TCGv_i32 fp0
= tcg_temp_new_i32();
6273 gen_load_fpr32(fp0
, fs
);
6274 gen_helper_float_rsqrt_s(fp0
, fp0
);
6275 gen_store_fpr32(fp0
, fd
);
6276 tcg_temp_free_i32(fp0
);
6281 check_cp1_64bitmode(ctx
);
6283 TCGv_i32 fp0
= tcg_temp_new_i32();
6284 TCGv_i32 fp1
= tcg_temp_new_i32();
6286 gen_load_fpr32(fp0
, fs
);
6287 gen_load_fpr32(fp1
, fd
);
6288 gen_helper_float_recip2_s(fp0
, fp0
, fp1
);
6289 tcg_temp_free_i32(fp1
);
6290 gen_store_fpr32(fp0
, fd
);
6291 tcg_temp_free_i32(fp0
);
6296 check_cp1_64bitmode(ctx
);
6298 TCGv_i32 fp0
= tcg_temp_new_i32();
6300 gen_load_fpr32(fp0
, fs
);
6301 gen_helper_float_recip1_s(fp0
, fp0
);
6302 gen_store_fpr32(fp0
, fd
);
6303 tcg_temp_free_i32(fp0
);
6308 check_cp1_64bitmode(ctx
);
6310 TCGv_i32 fp0
= tcg_temp_new_i32();
6312 gen_load_fpr32(fp0
, fs
);
6313 gen_helper_float_rsqrt1_s(fp0
, fp0
);
6314 gen_store_fpr32(fp0
, fd
);
6315 tcg_temp_free_i32(fp0
);
6320 check_cp1_64bitmode(ctx
);
6322 TCGv_i32 fp0
= tcg_temp_new_i32();
6323 TCGv_i32 fp1
= tcg_temp_new_i32();
6325 gen_load_fpr32(fp0
, fs
);
6326 gen_load_fpr32(fp1
, ft
);
6327 gen_helper_float_rsqrt2_s(fp0
, fp0
, fp1
);
6328 tcg_temp_free_i32(fp1
);
6329 gen_store_fpr32(fp0
, fd
);
6330 tcg_temp_free_i32(fp0
);
6335 check_cp1_registers(ctx
, fd
);
6337 TCGv_i32 fp32
= tcg_temp_new_i32();
6338 TCGv_i64 fp64
= tcg_temp_new_i64();
6340 gen_load_fpr32(fp32
, fs
);
6341 gen_helper_float_cvtd_s(fp64
, fp32
);
6342 tcg_temp_free_i32(fp32
);
6343 gen_store_fpr64(ctx
, fp64
, fd
);
6344 tcg_temp_free_i64(fp64
);
6350 TCGv_i32 fp0
= tcg_temp_new_i32();
6352 gen_load_fpr32(fp0
, fs
);
6353 gen_helper_float_cvtw_s(fp0
, fp0
);
6354 gen_store_fpr32(fp0
, fd
);
6355 tcg_temp_free_i32(fp0
);
6360 check_cp1_64bitmode(ctx
);
6362 TCGv_i32 fp32
= tcg_temp_new_i32();
6363 TCGv_i64 fp64
= tcg_temp_new_i64();
6365 gen_load_fpr32(fp32
, fs
);
6366 gen_helper_float_cvtl_s(fp64
, fp32
);
6367 tcg_temp_free_i32(fp32
);
6368 gen_store_fpr64(ctx
, fp64
, fd
);
6369 tcg_temp_free_i64(fp64
);
6374 check_cp1_64bitmode(ctx
);
6376 TCGv_i64 fp64
= tcg_temp_new_i64();
6377 TCGv_i32 fp32_0
= tcg_temp_new_i32();
6378 TCGv_i32 fp32_1
= tcg_temp_new_i32();
6380 gen_load_fpr32(fp32_0
, fs
);
6381 gen_load_fpr32(fp32_1
, ft
);
6382 tcg_gen_concat_i32_i64(fp64
, fp32_0
, fp32_1
);
6383 tcg_temp_free_i32(fp32_1
);
6384 tcg_temp_free_i32(fp32_0
);
6385 gen_store_fpr64(ctx
, fp64
, fd
);
6386 tcg_temp_free_i64(fp64
);
6407 TCGv_i32 fp0
= tcg_temp_new_i32();
6408 TCGv_i32 fp1
= tcg_temp_new_i32();
6410 gen_load_fpr32(fp0
, fs
);
6411 gen_load_fpr32(fp1
, ft
);
6412 if (ctx
->opcode
& (1 << 6)) {
6414 gen_cmpabs_s(func
-48, fp0
, fp1
, cc
);
6415 opn
= condnames_abs
[func
-48];
6417 gen_cmp_s(func
-48, fp0
, fp1
, cc
);
6418 opn
= condnames
[func
-48];
6420 tcg_temp_free_i32(fp0
);
6421 tcg_temp_free_i32(fp1
);
6425 check_cp1_registers(ctx
, fs
| ft
| fd
);
6427 TCGv_i64 fp0
= tcg_temp_new_i64();
6428 TCGv_i64 fp1
= tcg_temp_new_i64();
6430 gen_load_fpr64(ctx
, fp0
, fs
);
6431 gen_load_fpr64(ctx
, fp1
, ft
);
6432 gen_helper_float_add_d(fp0
, fp0
, fp1
);
6433 tcg_temp_free_i64(fp1
);
6434 gen_store_fpr64(ctx
, fp0
, fd
);
6435 tcg_temp_free_i64(fp0
);
6441 check_cp1_registers(ctx
, fs
| ft
| fd
);
6443 TCGv_i64 fp0
= tcg_temp_new_i64();
6444 TCGv_i64 fp1
= tcg_temp_new_i64();
6446 gen_load_fpr64(ctx
, fp0
, fs
);
6447 gen_load_fpr64(ctx
, fp1
, ft
);
6448 gen_helper_float_sub_d(fp0
, fp0
, fp1
);
6449 tcg_temp_free_i64(fp1
);
6450 gen_store_fpr64(ctx
, fp0
, fd
);
6451 tcg_temp_free_i64(fp0
);
6457 check_cp1_registers(ctx
, fs
| ft
| fd
);
6459 TCGv_i64 fp0
= tcg_temp_new_i64();
6460 TCGv_i64 fp1
= tcg_temp_new_i64();
6462 gen_load_fpr64(ctx
, fp0
, fs
);
6463 gen_load_fpr64(ctx
, fp1
, ft
);
6464 gen_helper_float_mul_d(fp0
, fp0
, fp1
);
6465 tcg_temp_free_i64(fp1
);
6466 gen_store_fpr64(ctx
, fp0
, fd
);
6467 tcg_temp_free_i64(fp0
);
6473 check_cp1_registers(ctx
, fs
| ft
| fd
);
6475 TCGv_i64 fp0
= tcg_temp_new_i64();
6476 TCGv_i64 fp1
= tcg_temp_new_i64();
6478 gen_load_fpr64(ctx
, fp0
, fs
);
6479 gen_load_fpr64(ctx
, fp1
, ft
);
6480 gen_helper_float_div_d(fp0
, fp0
, fp1
);
6481 tcg_temp_free_i64(fp1
);
6482 gen_store_fpr64(ctx
, fp0
, fd
);
6483 tcg_temp_free_i64(fp0
);
6489 check_cp1_registers(ctx
, fs
| fd
);
6491 TCGv_i64 fp0
= tcg_temp_new_i64();
6493 gen_load_fpr64(ctx
, fp0
, fs
);
6494 gen_helper_float_sqrt_d(fp0
, fp0
);
6495 gen_store_fpr64(ctx
, fp0
, fd
);
6496 tcg_temp_free_i64(fp0
);
6501 check_cp1_registers(ctx
, fs
| fd
);
6503 TCGv_i64 fp0
= tcg_temp_new_i64();
6505 gen_load_fpr64(ctx
, fp0
, fs
);
6506 gen_helper_float_abs_d(fp0
, fp0
);
6507 gen_store_fpr64(ctx
, fp0
, fd
);
6508 tcg_temp_free_i64(fp0
);
6513 check_cp1_registers(ctx
, fs
| fd
);
6515 TCGv_i64 fp0
= tcg_temp_new_i64();
6517 gen_load_fpr64(ctx
, fp0
, fs
);
6518 gen_store_fpr64(ctx
, fp0
, fd
);
6519 tcg_temp_free_i64(fp0
);
6524 check_cp1_registers(ctx
, fs
| fd
);
6526 TCGv_i64 fp0
= tcg_temp_new_i64();
6528 gen_load_fpr64(ctx
, fp0
, fs
);
6529 gen_helper_float_chs_d(fp0
, fp0
);
6530 gen_store_fpr64(ctx
, fp0
, fd
);
6531 tcg_temp_free_i64(fp0
);
6536 check_cp1_64bitmode(ctx
);
6538 TCGv_i64 fp0
= tcg_temp_new_i64();
6540 gen_load_fpr64(ctx
, fp0
, fs
);
6541 gen_helper_float_roundl_d(fp0
, fp0
);
6542 gen_store_fpr64(ctx
, fp0
, fd
);
6543 tcg_temp_free_i64(fp0
);
6548 check_cp1_64bitmode(ctx
);
6550 TCGv_i64 fp0
= tcg_temp_new_i64();
6552 gen_load_fpr64(ctx
, fp0
, fs
);
6553 gen_helper_float_truncl_d(fp0
, fp0
);
6554 gen_store_fpr64(ctx
, fp0
, fd
);
6555 tcg_temp_free_i64(fp0
);
6560 check_cp1_64bitmode(ctx
);
6562 TCGv_i64 fp0
= tcg_temp_new_i64();
6564 gen_load_fpr64(ctx
, fp0
, fs
);
6565 gen_helper_float_ceill_d(fp0
, fp0
);
6566 gen_store_fpr64(ctx
, fp0
, fd
);
6567 tcg_temp_free_i64(fp0
);
6572 check_cp1_64bitmode(ctx
);
6574 TCGv_i64 fp0
= tcg_temp_new_i64();
6576 gen_load_fpr64(ctx
, fp0
, fs
);
6577 gen_helper_float_floorl_d(fp0
, fp0
);
6578 gen_store_fpr64(ctx
, fp0
, fd
);
6579 tcg_temp_free_i64(fp0
);
6584 check_cp1_registers(ctx
, fs
);
6586 TCGv_i32 fp32
= tcg_temp_new_i32();
6587 TCGv_i64 fp64
= tcg_temp_new_i64();
6589 gen_load_fpr64(ctx
, fp64
, fs
);
6590 gen_helper_float_roundw_d(fp32
, fp64
);
6591 tcg_temp_free_i64(fp64
);
6592 gen_store_fpr32(fp32
, fd
);
6593 tcg_temp_free_i32(fp32
);
6598 check_cp1_registers(ctx
, fs
);
6600 TCGv_i32 fp32
= tcg_temp_new_i32();
6601 TCGv_i64 fp64
= tcg_temp_new_i64();
6603 gen_load_fpr64(ctx
, fp64
, fs
);
6604 gen_helper_float_truncw_d(fp32
, fp64
);
6605 tcg_temp_free_i64(fp64
);
6606 gen_store_fpr32(fp32
, fd
);
6607 tcg_temp_free_i32(fp32
);
6612 check_cp1_registers(ctx
, fs
);
6614 TCGv_i32 fp32
= tcg_temp_new_i32();
6615 TCGv_i64 fp64
= tcg_temp_new_i64();
6617 gen_load_fpr64(ctx
, fp64
, fs
);
6618 gen_helper_float_ceilw_d(fp32
, fp64
);
6619 tcg_temp_free_i64(fp64
);
6620 gen_store_fpr32(fp32
, fd
);
6621 tcg_temp_free_i32(fp32
);
6626 check_cp1_registers(ctx
, fs
);
6628 TCGv_i32 fp32
= tcg_temp_new_i32();
6629 TCGv_i64 fp64
= tcg_temp_new_i64();
6631 gen_load_fpr64(ctx
, fp64
, fs
);
6632 gen_helper_float_floorw_d(fp32
, fp64
);
6633 tcg_temp_free_i64(fp64
);
6634 gen_store_fpr32(fp32
, fd
);
6635 tcg_temp_free_i32(fp32
);
6640 gen_movcf_d(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6645 int l1
= gen_new_label();
6649 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6651 fp0
= tcg_temp_new_i64();
6652 gen_load_fpr64(ctx
, fp0
, fs
);
6653 gen_store_fpr64(ctx
, fp0
, fd
);
6654 tcg_temp_free_i64(fp0
);
6661 int l1
= gen_new_label();
6665 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6666 fp0
= tcg_temp_new_i64();
6667 gen_load_fpr64(ctx
, fp0
, fs
);
6668 gen_store_fpr64(ctx
, fp0
, fd
);
6669 tcg_temp_free_i64(fp0
);
6676 check_cp1_64bitmode(ctx
);
6678 TCGv_i64 fp0
= tcg_temp_new_i64();
6680 gen_load_fpr64(ctx
, fp0
, fs
);
6681 gen_helper_float_recip_d(fp0
, fp0
);
6682 gen_store_fpr64(ctx
, fp0
, fd
);
6683 tcg_temp_free_i64(fp0
);
6688 check_cp1_64bitmode(ctx
);
6690 TCGv_i64 fp0
= tcg_temp_new_i64();
6692 gen_load_fpr64(ctx
, fp0
, fs
);
6693 gen_helper_float_rsqrt_d(fp0
, fp0
);
6694 gen_store_fpr64(ctx
, fp0
, fd
);
6695 tcg_temp_free_i64(fp0
);
6700 check_cp1_64bitmode(ctx
);
6702 TCGv_i64 fp0
= tcg_temp_new_i64();
6703 TCGv_i64 fp1
= tcg_temp_new_i64();
6705 gen_load_fpr64(ctx
, fp0
, fs
);
6706 gen_load_fpr64(ctx
, fp1
, ft
);
6707 gen_helper_float_recip2_d(fp0
, fp0
, fp1
);
6708 tcg_temp_free_i64(fp1
);
6709 gen_store_fpr64(ctx
, fp0
, fd
);
6710 tcg_temp_free_i64(fp0
);
6715 check_cp1_64bitmode(ctx
);
6717 TCGv_i64 fp0
= tcg_temp_new_i64();
6719 gen_load_fpr64(ctx
, fp0
, fs
);
6720 gen_helper_float_recip1_d(fp0
, fp0
);
6721 gen_store_fpr64(ctx
, fp0
, fd
);
6722 tcg_temp_free_i64(fp0
);
6727 check_cp1_64bitmode(ctx
);
6729 TCGv_i64 fp0
= tcg_temp_new_i64();
6731 gen_load_fpr64(ctx
, fp0
, fs
);
6732 gen_helper_float_rsqrt1_d(fp0
, fp0
);
6733 gen_store_fpr64(ctx
, fp0
, fd
);
6734 tcg_temp_free_i64(fp0
);
6739 check_cp1_64bitmode(ctx
);
6741 TCGv_i64 fp0
= tcg_temp_new_i64();
6742 TCGv_i64 fp1
= tcg_temp_new_i64();
6744 gen_load_fpr64(ctx
, fp0
, fs
);
6745 gen_load_fpr64(ctx
, fp1
, ft
);
6746 gen_helper_float_rsqrt2_d(fp0
, fp0
, fp1
);
6747 tcg_temp_free_i64(fp1
);
6748 gen_store_fpr64(ctx
, fp0
, fd
);
6749 tcg_temp_free_i64(fp0
);
6770 TCGv_i64 fp0
= tcg_temp_new_i64();
6771 TCGv_i64 fp1
= tcg_temp_new_i64();
6773 gen_load_fpr64(ctx
, fp0
, fs
);
6774 gen_load_fpr64(ctx
, fp1
, ft
);
6775 if (ctx
->opcode
& (1 << 6)) {
6777 check_cp1_registers(ctx
, fs
| ft
);
6778 gen_cmpabs_d(func
-48, fp0
, fp1
, cc
);
6779 opn
= condnames_abs
[func
-48];
6781 check_cp1_registers(ctx
, fs
| ft
);
6782 gen_cmp_d(func
-48, fp0
, fp1
, cc
);
6783 opn
= condnames
[func
-48];
6785 tcg_temp_free_i64(fp0
);
6786 tcg_temp_free_i64(fp1
);
6790 check_cp1_registers(ctx
, fs
);
6792 TCGv_i32 fp32
= tcg_temp_new_i32();
6793 TCGv_i64 fp64
= tcg_temp_new_i64();
6795 gen_load_fpr64(ctx
, fp64
, fs
);
6796 gen_helper_float_cvts_d(fp32
, fp64
);
6797 tcg_temp_free_i64(fp64
);
6798 gen_store_fpr32(fp32
, fd
);
6799 tcg_temp_free_i32(fp32
);
6804 check_cp1_registers(ctx
, fs
);
6806 TCGv_i32 fp32
= tcg_temp_new_i32();
6807 TCGv_i64 fp64
= tcg_temp_new_i64();
6809 gen_load_fpr64(ctx
, fp64
, fs
);
6810 gen_helper_float_cvtw_d(fp32
, fp64
);
6811 tcg_temp_free_i64(fp64
);
6812 gen_store_fpr32(fp32
, fd
);
6813 tcg_temp_free_i32(fp32
);
6818 check_cp1_64bitmode(ctx
);
6820 TCGv_i64 fp0
= tcg_temp_new_i64();
6822 gen_load_fpr64(ctx
, fp0
, fs
);
6823 gen_helper_float_cvtl_d(fp0
, fp0
);
6824 gen_store_fpr64(ctx
, fp0
, fd
);
6825 tcg_temp_free_i64(fp0
);
6831 TCGv_i32 fp0
= tcg_temp_new_i32();
6833 gen_load_fpr32(fp0
, fs
);
6834 gen_helper_float_cvts_w(fp0
, fp0
);
6835 gen_store_fpr32(fp0
, fd
);
6836 tcg_temp_free_i32(fp0
);
6841 check_cp1_registers(ctx
, fd
);
6843 TCGv_i32 fp32
= tcg_temp_new_i32();
6844 TCGv_i64 fp64
= tcg_temp_new_i64();
6846 gen_load_fpr32(fp32
, fs
);
6847 gen_helper_float_cvtd_w(fp64
, fp32
);
6848 tcg_temp_free_i32(fp32
);
6849 gen_store_fpr64(ctx
, fp64
, fd
);
6850 tcg_temp_free_i64(fp64
);
6855 check_cp1_64bitmode(ctx
);
6857 TCGv_i32 fp32
= tcg_temp_new_i32();
6858 TCGv_i64 fp64
= tcg_temp_new_i64();
6860 gen_load_fpr64(ctx
, fp64
, fs
);
6861 gen_helper_float_cvts_l(fp32
, fp64
);
6862 tcg_temp_free_i64(fp64
);
6863 gen_store_fpr32(fp32
, fd
);
6864 tcg_temp_free_i32(fp32
);
6869 check_cp1_64bitmode(ctx
);
6871 TCGv_i64 fp0
= tcg_temp_new_i64();
6873 gen_load_fpr64(ctx
, fp0
, fs
);
6874 gen_helper_float_cvtd_l(fp0
, fp0
);
6875 gen_store_fpr64(ctx
, fp0
, fd
);
6876 tcg_temp_free_i64(fp0
);
6881 check_cp1_64bitmode(ctx
);
6883 TCGv_i64 fp0
= tcg_temp_new_i64();
6885 gen_load_fpr64(ctx
, fp0
, fs
);
6886 gen_helper_float_cvtps_pw(fp0
, fp0
);
6887 gen_store_fpr64(ctx
, fp0
, fd
);
6888 tcg_temp_free_i64(fp0
);
6893 check_cp1_64bitmode(ctx
);
6895 TCGv_i64 fp0
= tcg_temp_new_i64();
6896 TCGv_i64 fp1
= tcg_temp_new_i64();
6898 gen_load_fpr64(ctx
, fp0
, fs
);
6899 gen_load_fpr64(ctx
, fp1
, ft
);
6900 gen_helper_float_add_ps(fp0
, fp0
, fp1
);
6901 tcg_temp_free_i64(fp1
);
6902 gen_store_fpr64(ctx
, fp0
, fd
);
6903 tcg_temp_free_i64(fp0
);
6908 check_cp1_64bitmode(ctx
);
6910 TCGv_i64 fp0
= tcg_temp_new_i64();
6911 TCGv_i64 fp1
= tcg_temp_new_i64();
6913 gen_load_fpr64(ctx
, fp0
, fs
);
6914 gen_load_fpr64(ctx
, fp1
, ft
);
6915 gen_helper_float_sub_ps(fp0
, fp0
, fp1
);
6916 tcg_temp_free_i64(fp1
);
6917 gen_store_fpr64(ctx
, fp0
, fd
);
6918 tcg_temp_free_i64(fp0
);
6923 check_cp1_64bitmode(ctx
);
6925 TCGv_i64 fp0
= tcg_temp_new_i64();
6926 TCGv_i64 fp1
= tcg_temp_new_i64();
6928 gen_load_fpr64(ctx
, fp0
, fs
);
6929 gen_load_fpr64(ctx
, fp1
, ft
);
6930 gen_helper_float_mul_ps(fp0
, fp0
, fp1
);
6931 tcg_temp_free_i64(fp1
);
6932 gen_store_fpr64(ctx
, fp0
, fd
);
6933 tcg_temp_free_i64(fp0
);
6938 check_cp1_64bitmode(ctx
);
6940 TCGv_i64 fp0
= tcg_temp_new_i64();
6942 gen_load_fpr64(ctx
, fp0
, fs
);
6943 gen_helper_float_abs_ps(fp0
, fp0
);
6944 gen_store_fpr64(ctx
, fp0
, fd
);
6945 tcg_temp_free_i64(fp0
);
6950 check_cp1_64bitmode(ctx
);
6952 TCGv_i64 fp0
= tcg_temp_new_i64();
6954 gen_load_fpr64(ctx
, fp0
, fs
);
6955 gen_store_fpr64(ctx
, fp0
, fd
);
6956 tcg_temp_free_i64(fp0
);
6961 check_cp1_64bitmode(ctx
);
6963 TCGv_i64 fp0
= tcg_temp_new_i64();
6965 gen_load_fpr64(ctx
, fp0
, fs
);
6966 gen_helper_float_chs_ps(fp0
, fp0
);
6967 gen_store_fpr64(ctx
, fp0
, fd
);
6968 tcg_temp_free_i64(fp0
);
6973 check_cp1_64bitmode(ctx
);
6974 gen_movcf_ps(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6978 check_cp1_64bitmode(ctx
);
6980 int l1
= gen_new_label();
6984 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6985 fp0
= tcg_temp_new_i64();
6986 gen_load_fpr64(ctx
, fp0
, fs
);
6987 gen_store_fpr64(ctx
, fp0
, fd
);
6988 tcg_temp_free_i64(fp0
);
6994 check_cp1_64bitmode(ctx
);
6996 int l1
= gen_new_label();
7000 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
7001 fp0
= tcg_temp_new_i64();
7002 gen_load_fpr64(ctx
, fp0
, fs
);
7003 gen_store_fpr64(ctx
, fp0
, fd
);
7004 tcg_temp_free_i64(fp0
);
7011 check_cp1_64bitmode(ctx
);
7013 TCGv_i64 fp0
= tcg_temp_new_i64();
7014 TCGv_i64 fp1
= tcg_temp_new_i64();
7016 gen_load_fpr64(ctx
, fp0
, ft
);
7017 gen_load_fpr64(ctx
, fp1
, fs
);
7018 gen_helper_float_addr_ps(fp0
, fp0
, fp1
);
7019 tcg_temp_free_i64(fp1
);
7020 gen_store_fpr64(ctx
, fp0
, fd
);
7021 tcg_temp_free_i64(fp0
);
7026 check_cp1_64bitmode(ctx
);
7028 TCGv_i64 fp0
= tcg_temp_new_i64();
7029 TCGv_i64 fp1
= tcg_temp_new_i64();
7031 gen_load_fpr64(ctx
, fp0
, ft
);
7032 gen_load_fpr64(ctx
, fp1
, fs
);
7033 gen_helper_float_mulr_ps(fp0
, fp0
, fp1
);
7034 tcg_temp_free_i64(fp1
);
7035 gen_store_fpr64(ctx
, fp0
, fd
);
7036 tcg_temp_free_i64(fp0
);
7041 check_cp1_64bitmode(ctx
);
7043 TCGv_i64 fp0
= tcg_temp_new_i64();
7044 TCGv_i64 fp1
= tcg_temp_new_i64();
7046 gen_load_fpr64(ctx
, fp0
, fs
);
7047 gen_load_fpr64(ctx
, fp1
, fd
);
7048 gen_helper_float_recip2_ps(fp0
, fp0
, fp1
);
7049 tcg_temp_free_i64(fp1
);
7050 gen_store_fpr64(ctx
, fp0
, fd
);
7051 tcg_temp_free_i64(fp0
);
7056 check_cp1_64bitmode(ctx
);
7058 TCGv_i64 fp0
= tcg_temp_new_i64();
7060 gen_load_fpr64(ctx
, fp0
, fs
);
7061 gen_helper_float_recip1_ps(fp0
, fp0
);
7062 gen_store_fpr64(ctx
, fp0
, fd
);
7063 tcg_temp_free_i64(fp0
);
7068 check_cp1_64bitmode(ctx
);
7070 TCGv_i64 fp0
= tcg_temp_new_i64();
7072 gen_load_fpr64(ctx
, fp0
, fs
);
7073 gen_helper_float_rsqrt1_ps(fp0
, fp0
);
7074 gen_store_fpr64(ctx
, fp0
, fd
);
7075 tcg_temp_free_i64(fp0
);
7080 check_cp1_64bitmode(ctx
);
7082 TCGv_i64 fp0
= tcg_temp_new_i64();
7083 TCGv_i64 fp1
= tcg_temp_new_i64();
7085 gen_load_fpr64(ctx
, fp0
, fs
);
7086 gen_load_fpr64(ctx
, fp1
, ft
);
7087 gen_helper_float_rsqrt2_ps(fp0
, fp0
, fp1
);
7088 tcg_temp_free_i64(fp1
);
7089 gen_store_fpr64(ctx
, fp0
, fd
);
7090 tcg_temp_free_i64(fp0
);
7095 check_cp1_64bitmode(ctx
);
7097 TCGv_i32 fp0
= tcg_temp_new_i32();
7099 gen_load_fpr32h(fp0
, fs
);
7100 gen_helper_float_cvts_pu(fp0
, fp0
);
7101 gen_store_fpr32(fp0
, fd
);
7102 tcg_temp_free_i32(fp0
);
7107 check_cp1_64bitmode(ctx
);
7109 TCGv_i64 fp0
= tcg_temp_new_i64();
7111 gen_load_fpr64(ctx
, fp0
, fs
);
7112 gen_helper_float_cvtpw_ps(fp0
, fp0
);
7113 gen_store_fpr64(ctx
, fp0
, fd
);
7114 tcg_temp_free_i64(fp0
);
7119 check_cp1_64bitmode(ctx
);
7121 TCGv_i32 fp0
= tcg_temp_new_i32();
7123 gen_load_fpr32(fp0
, fs
);
7124 gen_helper_float_cvts_pl(fp0
, fp0
);
7125 gen_store_fpr32(fp0
, fd
);
7126 tcg_temp_free_i32(fp0
);
7131 check_cp1_64bitmode(ctx
);
7133 TCGv_i32 fp0
= tcg_temp_new_i32();
7134 TCGv_i32 fp1
= tcg_temp_new_i32();
7136 gen_load_fpr32(fp0
, fs
);
7137 gen_load_fpr32(fp1
, ft
);
7138 gen_store_fpr32h(fp0
, fd
);
7139 gen_store_fpr32(fp1
, fd
);
7140 tcg_temp_free_i32(fp0
);
7141 tcg_temp_free_i32(fp1
);
7146 check_cp1_64bitmode(ctx
);
7148 TCGv_i32 fp0
= tcg_temp_new_i32();
7149 TCGv_i32 fp1
= tcg_temp_new_i32();
7151 gen_load_fpr32(fp0
, fs
);
7152 gen_load_fpr32h(fp1
, ft
);
7153 gen_store_fpr32(fp1
, fd
);
7154 gen_store_fpr32h(fp0
, fd
);
7155 tcg_temp_free_i32(fp0
);
7156 tcg_temp_free_i32(fp1
);
7161 check_cp1_64bitmode(ctx
);
7163 TCGv_i32 fp0
= tcg_temp_new_i32();
7164 TCGv_i32 fp1
= tcg_temp_new_i32();
7166 gen_load_fpr32h(fp0
, fs
);
7167 gen_load_fpr32(fp1
, ft
);
7168 gen_store_fpr32(fp1
, fd
);
7169 gen_store_fpr32h(fp0
, fd
);
7170 tcg_temp_free_i32(fp0
);
7171 tcg_temp_free_i32(fp1
);
7176 check_cp1_64bitmode(ctx
);
7178 TCGv_i32 fp0
= tcg_temp_new_i32();
7179 TCGv_i32 fp1
= tcg_temp_new_i32();
7181 gen_load_fpr32h(fp0
, fs
);
7182 gen_load_fpr32h(fp1
, ft
);
7183 gen_store_fpr32(fp1
, fd
);
7184 gen_store_fpr32h(fp0
, fd
);
7185 tcg_temp_free_i32(fp0
);
7186 tcg_temp_free_i32(fp1
);
7206 check_cp1_64bitmode(ctx
);
7208 TCGv_i64 fp0
= tcg_temp_new_i64();
7209 TCGv_i64 fp1
= tcg_temp_new_i64();
7211 gen_load_fpr64(ctx
, fp0
, fs
);
7212 gen_load_fpr64(ctx
, fp1
, ft
);
7213 if (ctx
->opcode
& (1 << 6)) {
7214 gen_cmpabs_ps(func
-48, fp0
, fp1
, cc
);
7215 opn
= condnames_abs
[func
-48];
7217 gen_cmp_ps(func
-48, fp0
, fp1
, cc
);
7218 opn
= condnames
[func
-48];
7220 tcg_temp_free_i64(fp0
);
7221 tcg_temp_free_i64(fp1
);
7226 generate_exception (ctx
, EXCP_RI
);
7231 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
7234 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
7237 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
7242 /* Coprocessor 3 (FPU) */
7243 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
7244 int fd
, int fs
, int base
, int index
)
7246 const char *opn
= "extended float load/store";
7248 TCGv t0
= tcg_temp_new();
7251 gen_load_gpr(t0
, index
);
7252 } else if (index
== 0) {
7253 gen_load_gpr(t0
, base
);
7255 gen_load_gpr(t0
, index
);
7256 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], t0
);
7258 /* Don't do NOP if destination is zero: we must perform the actual
7260 save_cpu_state(ctx
, 0);
7265 TCGv_i32 fp0
= tcg_temp_new_i32();
7267 tcg_gen_qemu_ld32s(t0
, t0
, ctx
->mem_idx
);
7268 tcg_gen_trunc_tl_i32(fp0
, t0
);
7269 gen_store_fpr32(fp0
, fd
);
7270 tcg_temp_free_i32(fp0
);
7276 check_cp1_registers(ctx
, fd
);
7278 TCGv_i64 fp0
= tcg_temp_new_i64();
7280 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7281 gen_store_fpr64(ctx
, fp0
, fd
);
7282 tcg_temp_free_i64(fp0
);
7287 check_cp1_64bitmode(ctx
);
7288 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7290 TCGv_i64 fp0
= tcg_temp_new_i64();
7292 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7293 gen_store_fpr64(ctx
, fp0
, fd
);
7294 tcg_temp_free_i64(fp0
);
7301 TCGv_i32 fp0
= tcg_temp_new_i32();
7302 TCGv t1
= tcg_temp_new();
7304 gen_load_fpr32(fp0
, fs
);
7305 tcg_gen_extu_i32_tl(t1
, fp0
);
7306 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
7307 tcg_temp_free_i32(fp0
);
7315 check_cp1_registers(ctx
, fs
);
7317 TCGv_i64 fp0
= tcg_temp_new_i64();
7319 gen_load_fpr64(ctx
, fp0
, fs
);
7320 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7321 tcg_temp_free_i64(fp0
);
7327 check_cp1_64bitmode(ctx
);
7328 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7330 TCGv_i64 fp0
= tcg_temp_new_i64();
7332 gen_load_fpr64(ctx
, fp0
, fs
);
7333 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7334 tcg_temp_free_i64(fp0
);
7341 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
7342 regnames
[index
], regnames
[base
]);
7345 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
7346 int fd
, int fr
, int fs
, int ft
)
7348 const char *opn
= "flt3_arith";
7352 check_cp1_64bitmode(ctx
);
7354 TCGv t0
= tcg_temp_local_new();
7355 TCGv_i32 fp
= tcg_temp_new_i32();
7356 TCGv_i32 fph
= tcg_temp_new_i32();
7357 int l1
= gen_new_label();
7358 int l2
= gen_new_label();
7360 gen_load_gpr(t0
, fr
);
7361 tcg_gen_andi_tl(t0
, t0
, 0x7);
7363 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7364 gen_load_fpr32(fp
, fs
);
7365 gen_load_fpr32h(fph
, fs
);
7366 gen_store_fpr32(fp
, fd
);
7367 gen_store_fpr32h(fph
, fd
);
7370 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
7372 #ifdef TARGET_WORDS_BIGENDIAN
7373 gen_load_fpr32(fp
, fs
);
7374 gen_load_fpr32h(fph
, ft
);
7375 gen_store_fpr32h(fp
, fd
);
7376 gen_store_fpr32(fph
, fd
);
7378 gen_load_fpr32h(fph
, fs
);
7379 gen_load_fpr32(fp
, ft
);
7380 gen_store_fpr32(fph
, fd
);
7381 gen_store_fpr32h(fp
, fd
);
7384 tcg_temp_free_i32(fp
);
7385 tcg_temp_free_i32(fph
);
7392 TCGv_i32 fp0
= tcg_temp_new_i32();
7393 TCGv_i32 fp1
= tcg_temp_new_i32();
7394 TCGv_i32 fp2
= tcg_temp_new_i32();
7396 gen_load_fpr32(fp0
, fs
);
7397 gen_load_fpr32(fp1
, ft
);
7398 gen_load_fpr32(fp2
, fr
);
7399 gen_helper_float_muladd_s(fp2
, fp0
, fp1
, fp2
);
7400 tcg_temp_free_i32(fp0
);
7401 tcg_temp_free_i32(fp1
);
7402 gen_store_fpr32(fp2
, fd
);
7403 tcg_temp_free_i32(fp2
);
7409 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7411 TCGv_i64 fp0
= tcg_temp_new_i64();
7412 TCGv_i64 fp1
= tcg_temp_new_i64();
7413 TCGv_i64 fp2
= tcg_temp_new_i64();
7415 gen_load_fpr64(ctx
, fp0
, fs
);
7416 gen_load_fpr64(ctx
, fp1
, ft
);
7417 gen_load_fpr64(ctx
, fp2
, fr
);
7418 gen_helper_float_muladd_d(fp2
, fp0
, fp1
, fp2
);
7419 tcg_temp_free_i64(fp0
);
7420 tcg_temp_free_i64(fp1
);
7421 gen_store_fpr64(ctx
, fp2
, fd
);
7422 tcg_temp_free_i64(fp2
);
7427 check_cp1_64bitmode(ctx
);
7429 TCGv_i64 fp0
= tcg_temp_new_i64();
7430 TCGv_i64 fp1
= tcg_temp_new_i64();
7431 TCGv_i64 fp2
= tcg_temp_new_i64();
7433 gen_load_fpr64(ctx
, fp0
, fs
);
7434 gen_load_fpr64(ctx
, fp1
, ft
);
7435 gen_load_fpr64(ctx
, fp2
, fr
);
7436 gen_helper_float_muladd_ps(fp2
, fp0
, fp1
, fp2
);
7437 tcg_temp_free_i64(fp0
);
7438 tcg_temp_free_i64(fp1
);
7439 gen_store_fpr64(ctx
, fp2
, fd
);
7440 tcg_temp_free_i64(fp2
);
7447 TCGv_i32 fp0
= tcg_temp_new_i32();
7448 TCGv_i32 fp1
= tcg_temp_new_i32();
7449 TCGv_i32 fp2
= tcg_temp_new_i32();
7451 gen_load_fpr32(fp0
, fs
);
7452 gen_load_fpr32(fp1
, ft
);
7453 gen_load_fpr32(fp2
, fr
);
7454 gen_helper_float_mulsub_s(fp2
, fp0
, fp1
, fp2
);
7455 tcg_temp_free_i32(fp0
);
7456 tcg_temp_free_i32(fp1
);
7457 gen_store_fpr32(fp2
, fd
);
7458 tcg_temp_free_i32(fp2
);
7464 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7466 TCGv_i64 fp0
= tcg_temp_new_i64();
7467 TCGv_i64 fp1
= tcg_temp_new_i64();
7468 TCGv_i64 fp2
= tcg_temp_new_i64();
7470 gen_load_fpr64(ctx
, fp0
, fs
);
7471 gen_load_fpr64(ctx
, fp1
, ft
);
7472 gen_load_fpr64(ctx
, fp2
, fr
);
7473 gen_helper_float_mulsub_d(fp2
, fp0
, fp1
, fp2
);
7474 tcg_temp_free_i64(fp0
);
7475 tcg_temp_free_i64(fp1
);
7476 gen_store_fpr64(ctx
, fp2
, fd
);
7477 tcg_temp_free_i64(fp2
);
7482 check_cp1_64bitmode(ctx
);
7484 TCGv_i64 fp0
= tcg_temp_new_i64();
7485 TCGv_i64 fp1
= tcg_temp_new_i64();
7486 TCGv_i64 fp2
= tcg_temp_new_i64();
7488 gen_load_fpr64(ctx
, fp0
, fs
);
7489 gen_load_fpr64(ctx
, fp1
, ft
);
7490 gen_load_fpr64(ctx
, fp2
, fr
);
7491 gen_helper_float_mulsub_ps(fp2
, fp0
, fp1
, fp2
);
7492 tcg_temp_free_i64(fp0
);
7493 tcg_temp_free_i64(fp1
);
7494 gen_store_fpr64(ctx
, fp2
, fd
);
7495 tcg_temp_free_i64(fp2
);
7502 TCGv_i32 fp0
= tcg_temp_new_i32();
7503 TCGv_i32 fp1
= tcg_temp_new_i32();
7504 TCGv_i32 fp2
= tcg_temp_new_i32();
7506 gen_load_fpr32(fp0
, fs
);
7507 gen_load_fpr32(fp1
, ft
);
7508 gen_load_fpr32(fp2
, fr
);
7509 gen_helper_float_nmuladd_s(fp2
, fp0
, fp1
, fp2
);
7510 tcg_temp_free_i32(fp0
);
7511 tcg_temp_free_i32(fp1
);
7512 gen_store_fpr32(fp2
, fd
);
7513 tcg_temp_free_i32(fp2
);
7519 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7521 TCGv_i64 fp0
= tcg_temp_new_i64();
7522 TCGv_i64 fp1
= tcg_temp_new_i64();
7523 TCGv_i64 fp2
= tcg_temp_new_i64();
7525 gen_load_fpr64(ctx
, fp0
, fs
);
7526 gen_load_fpr64(ctx
, fp1
, ft
);
7527 gen_load_fpr64(ctx
, fp2
, fr
);
7528 gen_helper_float_nmuladd_d(fp2
, fp0
, fp1
, fp2
);
7529 tcg_temp_free_i64(fp0
);
7530 tcg_temp_free_i64(fp1
);
7531 gen_store_fpr64(ctx
, fp2
, fd
);
7532 tcg_temp_free_i64(fp2
);
7537 check_cp1_64bitmode(ctx
);
7539 TCGv_i64 fp0
= tcg_temp_new_i64();
7540 TCGv_i64 fp1
= tcg_temp_new_i64();
7541 TCGv_i64 fp2
= tcg_temp_new_i64();
7543 gen_load_fpr64(ctx
, fp0
, fs
);
7544 gen_load_fpr64(ctx
, fp1
, ft
);
7545 gen_load_fpr64(ctx
, fp2
, fr
);
7546 gen_helper_float_nmuladd_ps(fp2
, fp0
, fp1
, fp2
);
7547 tcg_temp_free_i64(fp0
);
7548 tcg_temp_free_i64(fp1
);
7549 gen_store_fpr64(ctx
, fp2
, fd
);
7550 tcg_temp_free_i64(fp2
);
7557 TCGv_i32 fp0
= tcg_temp_new_i32();
7558 TCGv_i32 fp1
= tcg_temp_new_i32();
7559 TCGv_i32 fp2
= tcg_temp_new_i32();
7561 gen_load_fpr32(fp0
, fs
);
7562 gen_load_fpr32(fp1
, ft
);
7563 gen_load_fpr32(fp2
, fr
);
7564 gen_helper_float_nmulsub_s(fp2
, fp0
, fp1
, fp2
);
7565 tcg_temp_free_i32(fp0
);
7566 tcg_temp_free_i32(fp1
);
7567 gen_store_fpr32(fp2
, fd
);
7568 tcg_temp_free_i32(fp2
);
7574 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7576 TCGv_i64 fp0
= tcg_temp_new_i64();
7577 TCGv_i64 fp1
= tcg_temp_new_i64();
7578 TCGv_i64 fp2
= tcg_temp_new_i64();
7580 gen_load_fpr64(ctx
, fp0
, fs
);
7581 gen_load_fpr64(ctx
, fp1
, ft
);
7582 gen_load_fpr64(ctx
, fp2
, fr
);
7583 gen_helper_float_nmulsub_d(fp2
, fp0
, fp1
, fp2
);
7584 tcg_temp_free_i64(fp0
);
7585 tcg_temp_free_i64(fp1
);
7586 gen_store_fpr64(ctx
, fp2
, fd
);
7587 tcg_temp_free_i64(fp2
);
7592 check_cp1_64bitmode(ctx
);
7594 TCGv_i64 fp0
= tcg_temp_new_i64();
7595 TCGv_i64 fp1
= tcg_temp_new_i64();
7596 TCGv_i64 fp2
= tcg_temp_new_i64();
7598 gen_load_fpr64(ctx
, fp0
, fs
);
7599 gen_load_fpr64(ctx
, fp1
, ft
);
7600 gen_load_fpr64(ctx
, fp2
, fr
);
7601 gen_helper_float_nmulsub_ps(fp2
, fp0
, fp1
, fp2
);
7602 tcg_temp_free_i64(fp0
);
7603 tcg_temp_free_i64(fp1
);
7604 gen_store_fpr64(ctx
, fp2
, fd
);
7605 tcg_temp_free_i64(fp2
);
7611 generate_exception (ctx
, EXCP_RI
);
7614 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
7615 fregnames
[fs
], fregnames
[ft
]);
7618 /* ISA extensions (ASEs) */
7619 /* MIPS16 extension to MIPS32 */
7620 /* SmartMIPS extension to MIPS32 */
7622 #if defined(TARGET_MIPS64)
7624 /* MDMX extension to MIPS64 */
7628 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
7632 uint32_t op
, op1
, op2
;
7635 /* make sure instructions are on a word boundary */
7636 if (ctx
->pc
& 0x3) {
7637 env
->CP0_BadVAddr
= ctx
->pc
;
7638 generate_exception(ctx
, EXCP_AdEL
);
7642 /* Handle blikely not taken case */
7643 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
7644 int l1
= gen_new_label();
7646 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
7647 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
7648 tcg_gen_movi_i32(hflags
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
7649 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
7653 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
7654 tcg_gen_debug_insn_start(ctx
->pc
);
7656 op
= MASK_OP_MAJOR(ctx
->opcode
);
7657 rs
= (ctx
->opcode
>> 21) & 0x1f;
7658 rt
= (ctx
->opcode
>> 16) & 0x1f;
7659 rd
= (ctx
->opcode
>> 11) & 0x1f;
7660 sa
= (ctx
->opcode
>> 6) & 0x1f;
7661 imm
= (int16_t)ctx
->opcode
;
7664 op1
= MASK_SPECIAL(ctx
->opcode
);
7666 case OPC_SLL
: /* Shift with immediate */
7669 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7671 case OPC_MOVN
: /* Conditional move */
7673 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7674 gen_cond_move(env
, op1
, rd
, rs
, rt
);
7676 case OPC_ADD
... OPC_SUBU
:
7677 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7679 case OPC_SLLV
: /* Shifts */
7682 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
7684 case OPC_SLT
: /* Set on less than */
7686 gen_slt(env
, op1
, rd
, rs
, rt
);
7688 case OPC_AND
: /* Logic*/
7692 gen_logic(env
, op1
, rd
, rs
, rt
);
7694 case OPC_MULT
... OPC_DIVU
:
7696 check_insn(env
, ctx
, INSN_VR54XX
);
7697 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
7698 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
7700 gen_muldiv(ctx
, op1
, rs
, rt
);
7702 case OPC_JR
... OPC_JALR
:
7703 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
7705 case OPC_TGE
... OPC_TEQ
: /* Traps */
7707 gen_trap(ctx
, op1
, rs
, rt
, -1);
7709 case OPC_MFHI
: /* Move from HI/LO */
7711 gen_HILO(ctx
, op1
, rd
);
7714 case OPC_MTLO
: /* Move to HI/LO */
7715 gen_HILO(ctx
, op1
, rs
);
7717 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
7718 #ifdef MIPS_STRICT_STANDARD
7719 MIPS_INVAL("PMON / selsl");
7720 generate_exception(ctx
, EXCP_RI
);
7722 gen_helper_0i(pmon
, sa
);
7726 generate_exception(ctx
, EXCP_SYSCALL
);
7727 ctx
->bstate
= BS_STOP
;
7730 generate_exception(ctx
, EXCP_BREAK
);
7733 #ifdef MIPS_STRICT_STANDARD
7735 generate_exception(ctx
, EXCP_RI
);
7737 /* Implemented as RI exception for now. */
7738 MIPS_INVAL("spim (unofficial)");
7739 generate_exception(ctx
, EXCP_RI
);
7747 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7748 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7749 check_cp1_enabled(ctx
);
7750 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
7751 (ctx
->opcode
>> 16) & 1);
7753 generate_exception_err(ctx
, EXCP_CpU
, 1);
7757 #if defined(TARGET_MIPS64)
7758 /* MIPS64 specific opcodes */
7765 check_insn(env
, ctx
, ISA_MIPS3
);
7767 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7769 case OPC_DADD
... OPC_DSUBU
:
7770 check_insn(env
, ctx
, ISA_MIPS3
);
7772 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7777 check_insn(env
, ctx
, ISA_MIPS3
);
7779 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
7781 case OPC_DMULT
... OPC_DDIVU
:
7782 check_insn(env
, ctx
, ISA_MIPS3
);
7784 gen_muldiv(ctx
, op1
, rs
, rt
);
7787 default: /* Invalid */
7788 MIPS_INVAL("special");
7789 generate_exception(ctx
, EXCP_RI
);
7794 op1
= MASK_SPECIAL2(ctx
->opcode
);
7796 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
7797 case OPC_MSUB
... OPC_MSUBU
:
7798 check_insn(env
, ctx
, ISA_MIPS32
);
7799 gen_muldiv(ctx
, op1
, rs
, rt
);
7802 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7806 check_insn(env
, ctx
, ISA_MIPS32
);
7807 gen_cl(ctx
, op1
, rd
, rs
);
7810 /* XXX: not clear which exception should be raised
7811 * when in debug mode...
7813 check_insn(env
, ctx
, ISA_MIPS32
);
7814 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
7815 generate_exception(ctx
, EXCP_DBp
);
7817 generate_exception(ctx
, EXCP_DBp
);
7821 #if defined(TARGET_MIPS64)
7824 check_insn(env
, ctx
, ISA_MIPS64
);
7826 gen_cl(ctx
, op1
, rd
, rs
);
7829 default: /* Invalid */
7830 MIPS_INVAL("special2");
7831 generate_exception(ctx
, EXCP_RI
);
7836 op1
= MASK_SPECIAL3(ctx
->opcode
);
7840 check_insn(env
, ctx
, ISA_MIPS32R2
);
7841 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7844 check_insn(env
, ctx
, ISA_MIPS32R2
);
7845 op2
= MASK_BSHFL(ctx
->opcode
);
7846 gen_bshfl(ctx
, op2
, rt
, rd
);
7849 check_insn(env
, ctx
, ISA_MIPS32R2
);
7851 TCGv t0
= tcg_temp_new();
7855 save_cpu_state(ctx
, 1);
7856 gen_helper_rdhwr_cpunum(t0
);
7857 gen_store_gpr(t0
, rt
);
7860 save_cpu_state(ctx
, 1);
7861 gen_helper_rdhwr_synci_step(t0
);
7862 gen_store_gpr(t0
, rt
);
7865 save_cpu_state(ctx
, 1);
7866 gen_helper_rdhwr_cc(t0
);
7867 gen_store_gpr(t0
, rt
);
7870 save_cpu_state(ctx
, 1);
7871 gen_helper_rdhwr_ccres(t0
);
7872 gen_store_gpr(t0
, rt
);
7875 #if defined(CONFIG_USER_ONLY)
7876 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, tls_value
));
7877 gen_store_gpr(t0
, rt
);
7880 /* XXX: Some CPUs implement this in hardware.
7881 Not supported yet. */
7883 default: /* Invalid */
7884 MIPS_INVAL("rdhwr");
7885 generate_exception(ctx
, EXCP_RI
);
7892 check_insn(env
, ctx
, ASE_MT
);
7894 TCGv t0
= tcg_temp_new();
7895 TCGv t1
= tcg_temp_new();
7897 gen_load_gpr(t0
, rt
);
7898 gen_load_gpr(t1
, rs
);
7899 gen_helper_fork(t0
, t1
);
7905 check_insn(env
, ctx
, ASE_MT
);
7907 TCGv t0
= tcg_temp_new();
7909 save_cpu_state(ctx
, 1);
7910 gen_load_gpr(t0
, rs
);
7911 gen_helper_yield(t0
, t0
);
7912 gen_store_gpr(t0
, rd
);
7916 #if defined(TARGET_MIPS64)
7917 case OPC_DEXTM
... OPC_DEXT
:
7918 case OPC_DINSM
... OPC_DINS
:
7919 check_insn(env
, ctx
, ISA_MIPS64R2
);
7921 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7924 check_insn(env
, ctx
, ISA_MIPS64R2
);
7926 op2
= MASK_DBSHFL(ctx
->opcode
);
7927 gen_bshfl(ctx
, op2
, rt
, rd
);
7930 default: /* Invalid */
7931 MIPS_INVAL("special3");
7932 generate_exception(ctx
, EXCP_RI
);
7937 op1
= MASK_REGIMM(ctx
->opcode
);
7939 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
7940 case OPC_BLTZAL
... OPC_BGEZALL
:
7941 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
7943 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
7945 gen_trap(ctx
, op1
, rs
, -1, imm
);
7948 check_insn(env
, ctx
, ISA_MIPS32R2
);
7951 default: /* Invalid */
7952 MIPS_INVAL("regimm");
7953 generate_exception(ctx
, EXCP_RI
);
7958 check_cp0_enabled(ctx
);
7959 op1
= MASK_CP0(ctx
->opcode
);
7965 #if defined(TARGET_MIPS64)
7969 #ifndef CONFIG_USER_ONLY
7970 gen_cp0(env
, ctx
, op1
, rt
, rd
);
7971 #endif /* !CONFIG_USER_ONLY */
7973 case OPC_C0_FIRST
... OPC_C0_LAST
:
7974 #ifndef CONFIG_USER_ONLY
7975 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
7976 #endif /* !CONFIG_USER_ONLY */
7979 #ifndef CONFIG_USER_ONLY
7981 TCGv t0
= tcg_temp_new();
7983 op2
= MASK_MFMC0(ctx
->opcode
);
7986 check_insn(env
, ctx
, ASE_MT
);
7987 gen_helper_dmt(t0
, t0
);
7988 gen_store_gpr(t0
, rt
);
7991 check_insn(env
, ctx
, ASE_MT
);
7992 gen_helper_emt(t0
, t0
);
7993 gen_store_gpr(t0
, rt
);
7996 check_insn(env
, ctx
, ASE_MT
);
7997 gen_helper_dvpe(t0
, t0
);
7998 gen_store_gpr(t0
, rt
);
8001 check_insn(env
, ctx
, ASE_MT
);
8002 gen_helper_evpe(t0
, t0
);
8003 gen_store_gpr(t0
, rt
);
8006 check_insn(env
, ctx
, ISA_MIPS32R2
);
8007 save_cpu_state(ctx
, 1);
8009 gen_store_gpr(t0
, rt
);
8010 /* Stop translation as we may have switched the execution mode */
8011 ctx
->bstate
= BS_STOP
;
8014 check_insn(env
, ctx
, ISA_MIPS32R2
);
8015 save_cpu_state(ctx
, 1);
8017 gen_store_gpr(t0
, rt
);
8018 /* Stop translation as we may have switched the execution mode */
8019 ctx
->bstate
= BS_STOP
;
8021 default: /* Invalid */
8022 MIPS_INVAL("mfmc0");
8023 generate_exception(ctx
, EXCP_RI
);
8028 #endif /* !CONFIG_USER_ONLY */
8031 check_insn(env
, ctx
, ISA_MIPS32R2
);
8032 gen_load_srsgpr(rt
, rd
);
8035 check_insn(env
, ctx
, ISA_MIPS32R2
);
8036 gen_store_srsgpr(rt
, rd
);
8040 generate_exception(ctx
, EXCP_RI
);
8044 case OPC_ADDI
: /* Arithmetic with immediate opcode */
8046 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8048 case OPC_SLTI
: /* Set on less than with immediate opcode */
8050 gen_slt_imm(env
, op
, rt
, rs
, imm
);
8052 case OPC_ANDI
: /* Arithmetic with immediate opcode */
8056 gen_logic_imm(env
, op
, rt
, rs
, imm
);
8058 case OPC_J
... OPC_JAL
: /* Jump */
8059 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
8060 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
8062 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
8063 case OPC_BEQL
... OPC_BGTZL
:
8064 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
8066 case OPC_LB
... OPC_LWR
: /* Load and stores */
8067 case OPC_SB
... OPC_SW
:
8070 gen_ldst(ctx
, op
, rt
, rs
, imm
);
8073 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
8076 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
8080 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
8084 /* Floating point (COP1). */
8089 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8090 check_cp1_enabled(ctx
);
8091 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
8093 generate_exception_err(ctx
, EXCP_CpU
, 1);
8098 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8099 check_cp1_enabled(ctx
);
8100 op1
= MASK_CP1(ctx
->opcode
);
8104 check_insn(env
, ctx
, ISA_MIPS32R2
);
8109 gen_cp1(ctx
, op1
, rt
, rd
);
8111 #if defined(TARGET_MIPS64)
8114 check_insn(env
, ctx
, ISA_MIPS3
);
8115 gen_cp1(ctx
, op1
, rt
, rd
);
8121 check_insn(env
, ctx
, ASE_MIPS3D
);
8124 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
8125 (rt
>> 2) & 0x7, imm
<< 2);
8132 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
8137 generate_exception (ctx
, EXCP_RI
);
8141 generate_exception_err(ctx
, EXCP_CpU
, 1);
8151 /* COP2: Not implemented. */
8152 generate_exception_err(ctx
, EXCP_CpU
, 2);
8156 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8157 check_cp1_enabled(ctx
);
8158 op1
= MASK_CP3(ctx
->opcode
);
8166 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
8184 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
8188 generate_exception (ctx
, EXCP_RI
);
8192 generate_exception_err(ctx
, EXCP_CpU
, 1);
8196 #if defined(TARGET_MIPS64)
8197 /* MIPS64 opcodes */
8199 case OPC_LDL
... OPC_LDR
:
8200 case OPC_SDL
... OPC_SDR
:
8204 check_insn(env
, ctx
, ISA_MIPS3
);
8206 gen_ldst(ctx
, op
, rt
, rs
, imm
);
8209 check_insn(env
, ctx
, ISA_MIPS3
);
8211 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
8215 check_insn(env
, ctx
, ISA_MIPS3
);
8217 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8221 check_insn(env
, ctx
, ASE_MIPS16
);
8222 /* MIPS16: Not implemented. */
8224 check_insn(env
, ctx
, ASE_MDMX
);
8225 /* MDMX: Not implemented. */
8226 default: /* Invalid */
8227 MIPS_INVAL("major opcode");
8228 generate_exception(ctx
, EXCP_RI
);
8231 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
8232 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
8233 /* Branches completion */
8234 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
8235 ctx
->bstate
= BS_BRANCH
;
8236 save_cpu_state(ctx
, 0);
8237 /* FIXME: Need to clear can_do_io. */
8240 /* unconditional branch */
8241 MIPS_DEBUG("unconditional branch");
8242 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8245 /* blikely taken case */
8246 MIPS_DEBUG("blikely branch taken");
8247 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8250 /* Conditional branch */
8251 MIPS_DEBUG("conditional branch");
8253 int l1
= gen_new_label();
8255 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
8256 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
8258 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8262 /* unconditional branch to register */
8263 MIPS_DEBUG("branch to register");
8264 tcg_gen_mov_tl(cpu_PC
, btarget
);
8265 if (ctx
->singlestep_enabled
) {
8266 save_cpu_state(ctx
, 0);
8267 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8272 MIPS_DEBUG("unknown branch");
8279 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
8283 target_ulong pc_start
;
8284 uint16_t *gen_opc_end
;
8291 qemu_log("search pc %d\n", search_pc
);
8294 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
8297 ctx
.singlestep_enabled
= env
->singlestep_enabled
;
8299 ctx
.bstate
= BS_NONE
;
8300 /* Restore delay slot state from the tb context. */
8301 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
8302 restore_cpu_state(env
, &ctx
);
8303 #ifdef CONFIG_USER_ONLY
8304 ctx
.mem_idx
= MIPS_HFLAG_UM
;
8306 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
8309 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8311 max_insns
= CF_COUNT_MASK
;
8313 qemu_log_mask(CPU_LOG_TB_CPU
, "------------------------------------------------\n");
8314 /* FIXME: This may print out stale hflags from env... */
8315 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, 0);
8317 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb
, ctx
.mem_idx
, ctx
.hflags
);
8319 while (ctx
.bstate
== BS_NONE
) {
8320 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
8321 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
8322 if (bp
->pc
== ctx
.pc
) {
8323 save_cpu_state(&ctx
, 1);
8324 ctx
.bstate
= BS_BRANCH
;
8325 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8326 /* Include the breakpoint location or the tb won't
8327 * be flushed when it must be. */
8329 goto done_generating
;
8335 j
= gen_opc_ptr
- gen_opc_buf
;
8339 gen_opc_instr_start
[lj
++] = 0;
8341 gen_opc_pc
[lj
] = ctx
.pc
;
8342 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
8343 gen_opc_instr_start
[lj
] = 1;
8344 gen_opc_icount
[lj
] = num_insns
;
8346 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8348 ctx
.opcode
= ldl_code(ctx
.pc
);
8349 decode_opc(env
, &ctx
);
8353 /* Execute a branch and its delay slot as a single instruction.
8354 This is what GDB expects and is consistent with what the
8355 hardware does (e.g. if a delay slot instruction faults, the
8356 reported PC is the PC of the branch). */
8357 if (env
->singlestep_enabled
&& (ctx
.hflags
& MIPS_HFLAG_BMASK
) == 0)
8360 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
8363 if (gen_opc_ptr
>= gen_opc_end
)
8366 if (num_insns
>= max_insns
)
8372 if (tb
->cflags
& CF_LAST_IO
)
8374 if (env
->singlestep_enabled
&& ctx
.bstate
!= BS_BRANCH
) {
8375 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
8376 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8378 switch (ctx
.bstate
) {
8380 gen_helper_interrupt_restart();
8381 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8384 save_cpu_state(&ctx
, 0);
8385 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8388 gen_helper_interrupt_restart();
8397 gen_icount_end(tb
, num_insns
);
8398 *gen_opc_ptr
= INDEX_op_end
;
8400 j
= gen_opc_ptr
- gen_opc_buf
;
8403 gen_opc_instr_start
[lj
++] = 0;
8405 tb
->size
= ctx
.pc
- pc_start
;
8406 tb
->icount
= num_insns
;
8410 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8411 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8412 log_target_disas(pc_start
, ctx
.pc
- pc_start
, 0);
8415 qemu_log_mask(CPU_LOG_TB_CPU
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
8419 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
8421 gen_intermediate_code_internal(env
, tb
, 0);
8424 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
8426 gen_intermediate_code_internal(env
, tb
, 1);
8429 static void fpu_dump_state(CPUState
*env
, FILE *f
,
8430 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8434 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
8436 #define printfpr(fp) \
8439 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
8440 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
8441 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
8444 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
8445 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
8446 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
8447 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
8448 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
8453 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
8454 env
->active_fpu
.fcr0
, env
->active_fpu
.fcr31
, is_fpu64
, env
->active_fpu
.fp_status
,
8455 get_float_exception_flags(&env
->active_fpu
.fp_status
));
8456 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
8457 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
8458 printfpr(&env
->active_fpu
.fpr
[i
]);
8464 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8465 /* Debug help: The architecture requires 32bit code to maintain proper
8466 sign-extended values on 64bit machines. */
8468 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
8471 cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
8472 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8477 if (!SIGN_EXT_P(env
->active_tc
.PC
))
8478 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->active_tc
.PC
);
8479 if (!SIGN_EXT_P(env
->active_tc
.HI
[0]))
8480 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->active_tc
.HI
[0]);
8481 if (!SIGN_EXT_P(env
->active_tc
.LO
[0]))
8482 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->active_tc
.LO
[0]);
8483 if (!SIGN_EXT_P(env
->btarget
))
8484 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
8486 for (i
= 0; i
< 32; i
++) {
8487 if (!SIGN_EXT_P(env
->active_tc
.gpr
[i
]))
8488 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->active_tc
.gpr
[i
]);
8491 if (!SIGN_EXT_P(env
->CP0_EPC
))
8492 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
8493 if (!SIGN_EXT_P(env
->lladdr
))
8494 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->lladdr
);
8498 void cpu_dump_state (CPUState
*env
, FILE *f
,
8499 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8504 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
8505 env
->active_tc
.PC
, env
->active_tc
.HI
[0], env
->active_tc
.LO
[0],
8506 env
->hflags
, env
->btarget
, env
->bcond
);
8507 for (i
= 0; i
< 32; i
++) {
8509 cpu_fprintf(f
, "GPR%02d:", i
);
8510 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->active_tc
.gpr
[i
]);
8512 cpu_fprintf(f
, "\n");
8515 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
8516 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
8517 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
8518 env
->CP0_Config0
, env
->CP0_Config1
, env
->lladdr
);
8519 if (env
->hflags
& MIPS_HFLAG_FPU
)
8520 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
8521 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8522 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
8526 static void mips_tcg_init(void)
8531 /* Initialize various static tables. */
8535 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
8536 TCGV_UNUSED(cpu_gpr
[0]);
8537 for (i
= 1; i
< 32; i
++)
8538 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
8539 offsetof(CPUState
, active_tc
.gpr
[i
]),
8541 cpu_PC
= tcg_global_mem_new(TCG_AREG0
,
8542 offsetof(CPUState
, active_tc
.PC
), "PC");
8543 for (i
= 0; i
< MIPS_DSP_ACC
; i
++) {
8544 cpu_HI
[i
] = tcg_global_mem_new(TCG_AREG0
,
8545 offsetof(CPUState
, active_tc
.HI
[i
]),
8547 cpu_LO
[i
] = tcg_global_mem_new(TCG_AREG0
,
8548 offsetof(CPUState
, active_tc
.LO
[i
]),
8550 cpu_ACX
[i
] = tcg_global_mem_new(TCG_AREG0
,
8551 offsetof(CPUState
, active_tc
.ACX
[i
]),
8554 cpu_dspctrl
= tcg_global_mem_new(TCG_AREG0
,
8555 offsetof(CPUState
, active_tc
.DSPControl
),
8557 bcond
= tcg_global_mem_new(TCG_AREG0
,
8558 offsetof(CPUState
, bcond
), "bcond");
8559 btarget
= tcg_global_mem_new(TCG_AREG0
,
8560 offsetof(CPUState
, btarget
), "btarget");
8561 hflags
= tcg_global_mem_new_i32(TCG_AREG0
,
8562 offsetof(CPUState
, hflags
), "hflags");
8564 fpu_fcr0
= tcg_global_mem_new_i32(TCG_AREG0
,
8565 offsetof(CPUState
, active_fpu
.fcr0
),
8567 fpu_fcr31
= tcg_global_mem_new_i32(TCG_AREG0
,
8568 offsetof(CPUState
, active_fpu
.fcr31
),
8571 /* register helpers */
8572 #define GEN_HELPER 2
8578 #include "translate_init.c"
8580 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
8583 const mips_def_t
*def
;
8585 def
= cpu_mips_find_by_name(cpu_model
);
8588 env
= qemu_mallocz(sizeof(CPUMIPSState
));
8589 env
->cpu_model
= def
;
8590 env
->cpu_model_str
= cpu_model
;
8593 #ifndef CONFIG_USER_ONLY
8600 qemu_init_vcpu(env
);
8604 void cpu_reset (CPUMIPSState
*env
)
8606 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
8607 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
8608 log_cpu_state(env
, 0);
8611 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
8614 /* Reset registers to their default values */
8615 env
->CP0_PRid
= env
->cpu_model
->CP0_PRid
;
8616 env
->CP0_Config0
= env
->cpu_model
->CP0_Config0
;
8617 #ifdef TARGET_WORDS_BIGENDIAN
8618 env
->CP0_Config0
|= (1 << CP0C0_BE
);
8620 env
->CP0_Config1
= env
->cpu_model
->CP0_Config1
;
8621 env
->CP0_Config2
= env
->cpu_model
->CP0_Config2
;
8622 env
->CP0_Config3
= env
->cpu_model
->CP0_Config3
;
8623 env
->CP0_Config6
= env
->cpu_model
->CP0_Config6
;
8624 env
->CP0_Config7
= env
->cpu_model
->CP0_Config7
;
8625 env
->CP0_LLAddr_rw_bitmask
= env
->cpu_model
->CP0_LLAddr_rw_bitmask
8626 << env
->cpu_model
->CP0_LLAddr_shift
;
8627 env
->CP0_LLAddr_shift
= env
->cpu_model
->CP0_LLAddr_shift
;
8628 env
->SYNCI_Step
= env
->cpu_model
->SYNCI_Step
;
8629 env
->CCRes
= env
->cpu_model
->CCRes
;
8630 env
->CP0_Status_rw_bitmask
= env
->cpu_model
->CP0_Status_rw_bitmask
;
8631 env
->CP0_TCStatus_rw_bitmask
= env
->cpu_model
->CP0_TCStatus_rw_bitmask
;
8632 env
->CP0_SRSCtl
= env
->cpu_model
->CP0_SRSCtl
;
8633 env
->current_tc
= 0;
8634 env
->SEGBITS
= env
->cpu_model
->SEGBITS
;
8635 env
->SEGMask
= (target_ulong
)((1ULL << env
->cpu_model
->SEGBITS
) - 1);
8636 #if defined(TARGET_MIPS64)
8637 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
8638 env
->SEGMask
|= 3ULL << 62;
8641 env
->PABITS
= env
->cpu_model
->PABITS
;
8642 env
->PAMask
= (target_ulong
)((1ULL << env
->cpu_model
->PABITS
) - 1);
8643 env
->CP0_SRSConf0_rw_bitmask
= env
->cpu_model
->CP0_SRSConf0_rw_bitmask
;
8644 env
->CP0_SRSConf0
= env
->cpu_model
->CP0_SRSConf0
;
8645 env
->CP0_SRSConf1_rw_bitmask
= env
->cpu_model
->CP0_SRSConf1_rw_bitmask
;
8646 env
->CP0_SRSConf1
= env
->cpu_model
->CP0_SRSConf1
;
8647 env
->CP0_SRSConf2_rw_bitmask
= env
->cpu_model
->CP0_SRSConf2_rw_bitmask
;
8648 env
->CP0_SRSConf2
= env
->cpu_model
->CP0_SRSConf2
;
8649 env
->CP0_SRSConf3_rw_bitmask
= env
->cpu_model
->CP0_SRSConf3_rw_bitmask
;
8650 env
->CP0_SRSConf3
= env
->cpu_model
->CP0_SRSConf3
;
8651 env
->CP0_SRSConf4_rw_bitmask
= env
->cpu_model
->CP0_SRSConf4_rw_bitmask
;
8652 env
->CP0_SRSConf4
= env
->cpu_model
->CP0_SRSConf4
;
8653 env
->insn_flags
= env
->cpu_model
->insn_flags
;
8655 #if defined(CONFIG_USER_ONLY)
8656 env
->hflags
= MIPS_HFLAG_UM
;
8657 /* Enable access to the SYNCI_Step register. */
8658 env
->CP0_HWREna
|= (1 << 1);
8659 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8660 env
->hflags
|= MIPS_HFLAG_FPU
;
8662 #ifdef TARGET_MIPS64
8663 if (env
->active_fpu
.fcr0
& (1 << FCR0_F64
)) {
8664 env
->hflags
|= MIPS_HFLAG_F64
;
8668 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
8669 /* If the exception was raised from a delay slot,
8670 come back to the jump. */
8671 env
->CP0_ErrorEPC
= env
->active_tc
.PC
- 4;
8673 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
8675 env
->active_tc
.PC
= (int32_t)0xBFC00000;
8676 env
->CP0_Random
= env
->tlb
->nb_tlb
- 1;
8677 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
8679 /* SMP not implemented */
8680 env
->CP0_EBase
= 0x80000000;
8681 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
8682 /* vectored interrupts not implemented, timer on int 7,
8683 no performance counters. */
8684 env
->CP0_IntCtl
= 0xe0000000;
8688 for (i
= 0; i
< 7; i
++) {
8689 env
->CP0_WatchLo
[i
] = 0;
8690 env
->CP0_WatchHi
[i
] = 0x80000000;
8692 env
->CP0_WatchLo
[7] = 0;
8693 env
->CP0_WatchHi
[7] = 0;
8695 /* Count register increments in debug mode, EJTAG version 1 */
8696 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
8697 env
->hflags
= MIPS_HFLAG_CP0
;
8699 #if defined(TARGET_MIPS64)
8700 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
8701 env
->hflags
|= MIPS_HFLAG_64
;
8704 env
->exception_index
= EXCP_NONE
;
8707 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
8708 unsigned long searched_pc
, int pc_pos
, void *puc
)
8710 env
->active_tc
.PC
= gen_opc_pc
[pc_pos
];
8711 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
8712 env
->hflags
|= gen_opc_hflags
[pc_pos
];