]>
git.proxmox.com Git - qemu.git/blob - target-mips/translate.c
2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 //#define MIPS_DEBUG_DISAS
34 //#define MIPS_DEBUG_SIGN_EXTENSIONS
35 //#define MIPS_SINGLE_STEP
37 #ifdef USE_DIRECT_JUMP
40 #define TBPARAM(x) (long)(x)
44 #define DEF(s, n, copy_size) INDEX_op_ ## s,
50 static uint16_t *gen_opc_ptr
;
51 static uint32_t *gen_opparam_ptr
;
55 /* MIPS major opcodes */
56 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
59 /* indirect opcode tables */
60 OPC_SPECIAL
= (0x00 << 26),
61 OPC_REGIMM
= (0x01 << 26),
62 OPC_CP0
= (0x10 << 26),
63 OPC_CP1
= (0x11 << 26),
64 OPC_CP2
= (0x12 << 26),
65 OPC_CP3
= (0x13 << 26),
66 OPC_SPECIAL2
= (0x1C << 26),
67 OPC_SPECIAL3
= (0x1F << 26),
68 /* arithmetic with immediate */
69 OPC_ADDI
= (0x08 << 26),
70 OPC_ADDIU
= (0x09 << 26),
71 OPC_SLTI
= (0x0A << 26),
72 OPC_SLTIU
= (0x0B << 26),
73 OPC_ANDI
= (0x0C << 26),
74 OPC_ORI
= (0x0D << 26),
75 OPC_XORI
= (0x0E << 26),
76 OPC_LUI
= (0x0F << 26),
77 OPC_DADDI
= (0x18 << 26),
78 OPC_DADDIU
= (0x19 << 26),
79 /* Jump and branches */
81 OPC_JAL
= (0x03 << 26),
82 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
83 OPC_BEQL
= (0x14 << 26),
84 OPC_BNE
= (0x05 << 26),
85 OPC_BNEL
= (0x15 << 26),
86 OPC_BLEZ
= (0x06 << 26),
87 OPC_BLEZL
= (0x16 << 26),
88 OPC_BGTZ
= (0x07 << 26),
89 OPC_BGTZL
= (0x17 << 26),
90 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
92 OPC_LDL
= (0x1A << 26),
93 OPC_LDR
= (0x1B << 26),
94 OPC_LB
= (0x20 << 26),
95 OPC_LH
= (0x21 << 26),
96 OPC_LWL
= (0x22 << 26),
97 OPC_LW
= (0x23 << 26),
98 OPC_LBU
= (0x24 << 26),
99 OPC_LHU
= (0x25 << 26),
100 OPC_LWR
= (0x26 << 26),
101 OPC_LWU
= (0x27 << 26),
102 OPC_SB
= (0x28 << 26),
103 OPC_SH
= (0x29 << 26),
104 OPC_SWL
= (0x2A << 26),
105 OPC_SW
= (0x2B << 26),
106 OPC_SDL
= (0x2C << 26),
107 OPC_SDR
= (0x2D << 26),
108 OPC_SWR
= (0x2E << 26),
109 OPC_LL
= (0x30 << 26),
110 OPC_LLD
= (0x34 << 26),
111 OPC_LD
= (0x37 << 26),
112 OPC_SC
= (0x38 << 26),
113 OPC_SCD
= (0x3C << 26),
114 OPC_SD
= (0x3F << 26),
115 /* Floating point load/store */
116 OPC_LWC1
= (0x31 << 26),
117 OPC_LWC2
= (0x32 << 26),
118 OPC_LDC1
= (0x35 << 26),
119 OPC_LDC2
= (0x36 << 26),
120 OPC_SWC1
= (0x39 << 26),
121 OPC_SWC2
= (0x3A << 26),
122 OPC_SDC1
= (0x3D << 26),
123 OPC_SDC2
= (0x3E << 26),
124 /* MDMX ASE specific */
125 OPC_MDMX
= (0x1E << 26),
126 /* Cache and prefetch */
127 OPC_CACHE
= (0x2F << 26),
128 OPC_PREF
= (0x33 << 26),
129 /* Reserved major opcode */
130 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
133 /* MIPS special opcodes */
134 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
138 OPC_SLL
= 0x00 | OPC_SPECIAL
,
139 /* NOP is SLL r0, r0, 0 */
140 /* SSNOP is SLL r0, r0, 1 */
141 /* EHB is SLL r0, r0, 3 */
142 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
143 OPC_SRA
= 0x03 | OPC_SPECIAL
,
144 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
145 OPC_SRLV
= 0x06 | OPC_SPECIAL
,
146 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
147 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
148 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
149 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
150 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
151 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
152 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
153 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
154 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
155 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
156 /* Multiplication / division */
157 OPC_MULT
= 0x18 | OPC_SPECIAL
,
158 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
159 OPC_DIV
= 0x1A | OPC_SPECIAL
,
160 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
161 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
162 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
163 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
164 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
165 /* 2 registers arithmetic / logic */
166 OPC_ADD
= 0x20 | OPC_SPECIAL
,
167 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
168 OPC_SUB
= 0x22 | OPC_SPECIAL
,
169 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
170 OPC_AND
= 0x24 | OPC_SPECIAL
,
171 OPC_OR
= 0x25 | OPC_SPECIAL
,
172 OPC_XOR
= 0x26 | OPC_SPECIAL
,
173 OPC_NOR
= 0x27 | OPC_SPECIAL
,
174 OPC_SLT
= 0x2A | OPC_SPECIAL
,
175 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
176 OPC_DADD
= 0x2C | OPC_SPECIAL
,
177 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
178 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
179 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
181 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
182 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
184 OPC_TGE
= 0x30 | OPC_SPECIAL
,
185 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
186 OPC_TLT
= 0x32 | OPC_SPECIAL
,
187 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
188 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
189 OPC_TNE
= 0x36 | OPC_SPECIAL
,
190 /* HI / LO registers load & stores */
191 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
192 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
193 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
194 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
195 /* Conditional moves */
196 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
197 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
199 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
202 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* inofficial */
203 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
204 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
205 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* inofficial */
206 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
208 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
209 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
210 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
211 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
212 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
213 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
214 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
217 /* REGIMM (rt field) opcodes */
218 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
221 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
222 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
223 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
224 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
225 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
226 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
227 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
228 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
229 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
230 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
231 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
232 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
233 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
234 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
235 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
238 /* Special2 opcodes */
239 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
242 /* Multiply & xxx operations */
243 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
244 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
245 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
246 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
247 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
249 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
250 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
251 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
252 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
254 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
257 /* Special3 opcodes */
258 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
261 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
262 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
263 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
264 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
265 OPC_INS
= 0x04 | OPC_SPECIAL3
,
266 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
267 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
268 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
269 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
270 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
271 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
275 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
278 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
279 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
280 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
284 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
287 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
288 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
291 /* Coprocessor 0 (rs field) */
292 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
295 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
296 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
297 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
298 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
299 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
300 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
301 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
302 OPC_C0
= (0x10 << 21) | OPC_CP0
,
303 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
304 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
308 #define MASK_MFMC0(op) MASK_CP0(op) | (op & ((0x0C << 11) | (1 << 5)))
311 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
312 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
315 /* Coprocessor 0 (with rs == C0) */
316 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
319 OPC_TLBR
= 0x01 | OPC_C0
,
320 OPC_TLBWI
= 0x02 | OPC_C0
,
321 OPC_TLBWR
= 0x06 | OPC_C0
,
322 OPC_TLBP
= 0x08 | OPC_C0
,
323 OPC_RFE
= 0x10 | OPC_C0
,
324 OPC_ERET
= 0x18 | OPC_C0
,
325 OPC_DERET
= 0x1F | OPC_C0
,
326 OPC_WAIT
= 0x20 | OPC_C0
,
329 /* Coprocessor 1 (rs field) */
330 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
333 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
334 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
335 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
336 OPC_MFHCI
= (0x03 << 21) | OPC_CP1
,
337 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
338 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
339 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
340 OPC_MTHCI
= (0x07 << 21) | OPC_CP1
,
341 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
342 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
343 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
344 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
345 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
346 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
347 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
351 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
352 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
353 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
354 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
357 #define MASK_CP1_BCOND(op) MASK_CP1(op) | (op & (0x3 << 16))
358 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
360 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
361 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
363 const unsigned char *regnames
[] =
364 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
365 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
366 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
367 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
369 /* Warning: no function for r0 register (hard wired to zero) */
370 #define GEN32(func, NAME) \
371 static GenOpFunc *NAME ## _table [32] = { \
372 NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
373 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
374 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
375 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
376 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
377 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
378 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
379 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
381 static inline void func(int n) \
383 NAME ## _table[n](); \
386 /* General purpose registers moves */
387 GEN32(gen_op_load_gpr_T0
, gen_op_load_gpr_T0_gpr
);
388 GEN32(gen_op_load_gpr_T1
, gen_op_load_gpr_T1_gpr
);
389 GEN32(gen_op_load_gpr_T2
, gen_op_load_gpr_T2_gpr
);
391 GEN32(gen_op_store_T0_gpr
, gen_op_store_T0_gpr_gpr
);
392 GEN32(gen_op_store_T1_gpr
, gen_op_store_T1_gpr_gpr
);
394 static const char *fregnames
[] =
395 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
396 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
397 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
398 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
400 # define SFGEN32(func, NAME) \
401 static GenOpFunc *NAME ## _table [32] = { \
402 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
403 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
404 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
405 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
406 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
407 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
408 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
409 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
411 static inline void func(int n) \
413 NAME ## _table[n](); \
416 # define DFGEN32(func, NAME) \
417 static GenOpFunc *NAME ## _table [32] = { \
418 NAME ## 0, 0, NAME ## 2, 0, \
419 NAME ## 4, 0, NAME ## 6, 0, \
420 NAME ## 8, 0, NAME ## 10, 0, \
421 NAME ## 12, 0, NAME ## 14, 0, \
422 NAME ## 16, 0, NAME ## 18, 0, \
423 NAME ## 20, 0, NAME ## 22, 0, \
424 NAME ## 24, 0, NAME ## 26, 0, \
425 NAME ## 28, 0, NAME ## 30, 0, \
427 static inline void func(int n) \
429 NAME ## _table[n](); \
432 SFGEN32(gen_op_load_fpr_WT0
, gen_op_load_fpr_WT0_fpr
);
433 SFGEN32(gen_op_store_fpr_WT0
, gen_op_store_fpr_WT0_fpr
);
435 SFGEN32(gen_op_load_fpr_WT1
, gen_op_load_fpr_WT1_fpr
);
436 SFGEN32(gen_op_store_fpr_WT1
, gen_op_store_fpr_WT1_fpr
);
438 SFGEN32(gen_op_load_fpr_WT2
, gen_op_load_fpr_WT2_fpr
);
439 SFGEN32(gen_op_store_fpr_WT2
, gen_op_store_fpr_WT2_fpr
);
441 DFGEN32(gen_op_load_fpr_DT0
, gen_op_load_fpr_DT0_fpr
);
442 DFGEN32(gen_op_store_fpr_DT0
, gen_op_store_fpr_DT0_fpr
);
444 DFGEN32(gen_op_load_fpr_DT1
, gen_op_load_fpr_DT1_fpr
);
445 DFGEN32(gen_op_store_fpr_DT1
, gen_op_store_fpr_DT1_fpr
);
447 DFGEN32(gen_op_load_fpr_DT2
, gen_op_load_fpr_DT2_fpr
);
448 DFGEN32(gen_op_store_fpr_DT2
, gen_op_store_fpr_DT2_fpr
);
450 #define FOP_CONDS(fmt) \
451 static GenOpFunc * cond_ ## fmt ## _table[16] = { \
452 gen_op_cmp_ ## fmt ## _f, \
453 gen_op_cmp_ ## fmt ## _un, \
454 gen_op_cmp_ ## fmt ## _eq, \
455 gen_op_cmp_ ## fmt ## _ueq, \
456 gen_op_cmp_ ## fmt ## _olt, \
457 gen_op_cmp_ ## fmt ## _ult, \
458 gen_op_cmp_ ## fmt ## _ole, \
459 gen_op_cmp_ ## fmt ## _ule, \
460 gen_op_cmp_ ## fmt ## _sf, \
461 gen_op_cmp_ ## fmt ## _ngle, \
462 gen_op_cmp_ ## fmt ## _seq, \
463 gen_op_cmp_ ## fmt ## _ngl, \
464 gen_op_cmp_ ## fmt ## _lt, \
465 gen_op_cmp_ ## fmt ## _nge, \
466 gen_op_cmp_ ## fmt ## _le, \
467 gen_op_cmp_ ## fmt ## _ngt, \
469 static inline void gen_cmp_ ## fmt(int n) \
471 cond_ ## fmt ## _table[n](); \
477 typedef struct DisasContext
{
478 struct TranslationBlock
*tb
;
479 target_ulong pc
, saved_pc
;
481 /* Routine used to access memory */
483 uint32_t hflags
, saved_hflags
;
486 target_ulong btarget
;
490 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
491 * exception condition
493 BS_STOP
= 1, /* We want to stop translation for any reason */
494 BS_BRANCH
= 2, /* We reached a branch condition */
495 BS_EXCP
= 3, /* We reached an exception condition */
498 #if defined MIPS_DEBUG_DISAS
499 #define MIPS_DEBUG(fmt, args...) \
501 if (loglevel & CPU_LOG_TB_IN_ASM) { \
502 fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
503 ctx->pc, ctx->opcode , ##args); \
507 #define MIPS_DEBUG(fmt, args...) do { } while(0)
510 #define MIPS_INVAL(op) \
512 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
513 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
516 #define GEN_LOAD_REG_TN(Tn, Rn) \
519 glue(gen_op_reset_, Tn)(); \
521 glue(gen_op_load_gpr_, Tn)(Rn); \
525 #define GEN_LOAD_IMM_TN(Tn, Imm) \
528 glue(gen_op_reset_, Tn)(); \
530 glue(gen_op_set_, Tn)(Imm); \
534 #define GEN_STORE_TN_REG(Rn, Tn) \
537 glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
541 #define GEN_LOAD_FREG_FTN(FTn, Fn) \
543 glue(gen_op_load_fpr_, FTn)(Fn); \
546 #define GEN_STORE_FTN_FREG(Fn, FTn) \
548 glue(gen_op_store_fpr_, FTn)(Fn); \
551 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
553 #if defined MIPS_DEBUG_DISAS
554 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
555 fprintf(logfile
, "hflags %08x saved %08x\n",
556 ctx
->hflags
, ctx
->saved_hflags
);
559 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
560 gen_op_save_pc(ctx
->pc
);
561 ctx
->saved_pc
= ctx
->pc
;
563 if (ctx
->hflags
!= ctx
->saved_hflags
) {
564 gen_op_save_state(ctx
->hflags
);
565 ctx
->saved_hflags
= ctx
->hflags
;
566 if (ctx
->hflags
& MIPS_HFLAG_BR
) {
567 gen_op_save_breg_target();
568 } else if (ctx
->hflags
& MIPS_HFLAG_B
) {
569 gen_op_save_btarget(ctx
->btarget
);
570 } else if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
572 gen_op_save_btarget(ctx
->btarget
);
577 static inline void generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
579 #if defined MIPS_DEBUG_DISAS
580 if (loglevel
& CPU_LOG_TB_IN_ASM
)
581 fprintf(logfile
, "%s: raise exception %d\n", __func__
, excp
);
583 save_cpu_state(ctx
, 1);
585 gen_op_raise_exception(excp
);
587 gen_op_raise_exception_err(excp
, err
);
588 ctx
->bstate
= BS_EXCP
;
591 static inline void generate_exception (DisasContext
*ctx
, int excp
)
593 generate_exception_err (ctx
, excp
, 0);
596 #if defined(CONFIG_USER_ONLY)
597 #define op_ldst(name) gen_op_##name##_raw()
598 #define OP_LD_TABLE(width)
599 #define OP_ST_TABLE(width)
601 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
602 #define OP_LD_TABLE(width) \
603 static GenOpFunc *gen_op_l##width[] = { \
604 &gen_op_l##width##_user, \
605 &gen_op_l##width##_kernel, \
607 #define OP_ST_TABLE(width) \
608 static GenOpFunc *gen_op_s##width[] = { \
609 &gen_op_s##width##_user, \
610 &gen_op_s##width##_kernel, \
614 #ifdef MIPS_HAS_MIPS64
645 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
646 int base
, int16_t offset
)
648 const char *opn
= "unk";
651 GEN_LOAD_IMM_TN(T0
, offset
);
652 } else if (offset
== 0) {
653 gen_op_load_gpr_T0(base
);
655 gen_op_load_gpr_T0(base
);
656 gen_op_set_T1(offset
);
659 /* Don't do NOP if destination is zero: we must perform the actual
663 #ifdef MIPS_HAS_MIPS64
666 GEN_STORE_TN_REG(rt
, T0
);
671 GEN_STORE_TN_REG(rt
, T0
);
675 GEN_LOAD_REG_TN(T1
, rt
);
680 GEN_LOAD_REG_TN(T1
, rt
);
686 GEN_STORE_TN_REG(rt
, T0
);
690 GEN_LOAD_REG_TN(T1
, rt
);
696 GEN_STORE_TN_REG(rt
, T0
);
700 GEN_LOAD_REG_TN(T1
, rt
);
707 GEN_STORE_TN_REG(rt
, T0
);
712 GEN_STORE_TN_REG(rt
, T0
);
716 GEN_LOAD_REG_TN(T1
, rt
);
722 GEN_STORE_TN_REG(rt
, T0
);
726 GEN_LOAD_REG_TN(T1
, rt
);
732 GEN_STORE_TN_REG(rt
, T0
);
737 GEN_STORE_TN_REG(rt
, T0
);
741 GEN_LOAD_REG_TN(T1
, rt
);
747 GEN_STORE_TN_REG(rt
, T0
);
751 GEN_LOAD_REG_TN(T1
, rt
);
753 GEN_STORE_TN_REG(rt
, T0
);
757 GEN_LOAD_REG_TN(T1
, rt
);
762 GEN_LOAD_REG_TN(T1
, rt
);
764 GEN_STORE_TN_REG(rt
, T0
);
768 GEN_LOAD_REG_TN(T1
, rt
);
774 GEN_STORE_TN_REG(rt
, T0
);
778 GEN_LOAD_REG_TN(T1
, rt
);
780 GEN_STORE_TN_REG(rt
, T0
);
784 MIPS_INVAL("load/store");
785 generate_exception(ctx
, EXCP_RI
);
788 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
792 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
793 int base
, int16_t offset
)
795 const char *opn
= "unk";
798 GEN_LOAD_IMM_TN(T0
, offset
);
799 } else if (offset
== 0) {
800 gen_op_load_gpr_T0(base
);
802 gen_op_load_gpr_T0(base
);
803 gen_op_set_T1(offset
);
806 /* Don't do NOP if destination is zero: we must perform the actual
812 GEN_STORE_FTN_FREG(ft
, WT0
);
816 GEN_LOAD_FREG_FTN(WT0
, ft
);
822 GEN_STORE_FTN_FREG(ft
, DT0
);
826 GEN_LOAD_FREG_FTN(DT0
, ft
);
831 MIPS_INVAL("float load/store");
832 generate_exception_err(ctx
, EXCP_CpU
, 1);
835 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
838 /* Arithmetic with immediate operand */
839 static void gen_arith_imm (DisasContext
*ctx
, uint32_t opc
, int rt
,
843 const char *opn
= "unk";
845 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
846 /* if no destination, treat it as a NOP
847 * For addi, we must generate the overflow exception when needed.
852 if (opc
== OPC_ADDI
|| opc
== OPC_ADDIU
||
853 opc
== OPC_DADDI
|| opc
== OPC_DADDIU
||
854 opc
== OPC_SLTI
|| opc
== OPC_SLTIU
)
855 uimm
= (int32_t)imm
; /* Sign extend to 32 bits */
857 uimm
= (uint16_t)imm
;
858 if (opc
!= OPC_LUI
) {
859 GEN_LOAD_REG_TN(T0
, rs
);
860 GEN_LOAD_IMM_TN(T1
, uimm
);
863 GEN_LOAD_IMM_TN(T0
, uimm
);
867 save_cpu_state(ctx
, 1);
875 #ifdef MIPS_HAS_MIPS64
877 save_cpu_state(ctx
, 1);
918 if ((ctx
->opcode
>> 21) & 1) {
926 #ifdef MIPS_HAS_MIPS64
936 if ((ctx
->opcode
>> 21) & 1) {
953 if ((ctx
->opcode
>> 21) & 1) {
963 MIPS_INVAL("imm arith");
964 generate_exception(ctx
, EXCP_RI
);
967 GEN_STORE_TN_REG(rt
, T0
);
968 MIPS_DEBUG("%s %s, %s, %x", opn
, regnames
[rt
], regnames
[rs
], uimm
);
972 static void gen_arith (DisasContext
*ctx
, uint32_t opc
,
973 int rd
, int rs
, int rt
)
975 const char *opn
= "unk";
977 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
978 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
979 /* if no destination, treat it as a NOP
980 * For add & sub, we must generate the overflow exception when needed.
985 GEN_LOAD_REG_TN(T0
, rs
);
986 GEN_LOAD_REG_TN(T1
, rt
);
989 save_cpu_state(ctx
, 1);
998 save_cpu_state(ctx
, 1);
1006 #ifdef MIPS_HAS_MIPS64
1008 save_cpu_state(ctx
, 1);
1017 save_cpu_state(ctx
, 1);
1071 if ((ctx
->opcode
>> 6) & 1) {
1079 #ifdef MIPS_HAS_MIPS64
1089 if ((ctx
->opcode
>> 6) & 1) {
1099 MIPS_INVAL("arith");
1100 generate_exception(ctx
, EXCP_RI
);
1103 GEN_STORE_TN_REG(rd
, T0
);
1105 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1108 /* Arithmetic on HI/LO registers */
1109 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1111 const char *opn
= "unk";
1113 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1114 /* Treat as a NOP */
1121 GEN_STORE_TN_REG(reg
, T0
);
1126 GEN_STORE_TN_REG(reg
, T0
);
1130 GEN_LOAD_REG_TN(T0
, reg
);
1135 GEN_LOAD_REG_TN(T0
, reg
);
1141 generate_exception(ctx
, EXCP_RI
);
1144 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1147 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1150 const char *opn
= "unk";
1152 GEN_LOAD_REG_TN(T0
, rs
);
1153 GEN_LOAD_REG_TN(T1
, rt
);
1171 #ifdef MIPS_HAS_MIPS64
1206 MIPS_INVAL("mul/div");
1207 generate_exception(ctx
, EXCP_RI
);
1210 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
1213 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
1216 const char *opn
= "unk";
1218 /* Treat as a NOP */
1222 GEN_LOAD_REG_TN(T0
, rs
);
1232 #ifdef MIPS_HAS_MIPS64
1244 generate_exception(ctx
, EXCP_RI
);
1247 gen_op_store_T0_gpr(rd
);
1248 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
1252 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
1253 int rs
, int rt
, int16_t imm
)
1258 /* Load needed operands */
1266 /* Compare two registers */
1268 GEN_LOAD_REG_TN(T0
, rs
);
1269 GEN_LOAD_REG_TN(T1
, rt
);
1279 /* Compare register to immediate */
1280 if (rs
!= 0 || imm
!= 0) {
1281 GEN_LOAD_REG_TN(T0
, rs
);
1282 GEN_LOAD_IMM_TN(T1
, (int32_t)imm
);
1289 case OPC_TEQ
: /* rs == rs */
1290 case OPC_TEQI
: /* r0 == 0 */
1291 case OPC_TGE
: /* rs >= rs */
1292 case OPC_TGEI
: /* r0 >= 0 */
1293 case OPC_TGEU
: /* rs >= rs unsigned */
1294 case OPC_TGEIU
: /* r0 >= 0 unsigned */
1298 case OPC_TLT
: /* rs < rs */
1299 case OPC_TLTI
: /* r0 < 0 */
1300 case OPC_TLTU
: /* rs < rs unsigned */
1301 case OPC_TLTIU
: /* r0 < 0 unsigned */
1302 case OPC_TNE
: /* rs != rs */
1303 case OPC_TNEI
: /* r0 != 0 */
1304 /* Never trap: treat as NOP */
1308 generate_exception(ctx
, EXCP_RI
);
1339 generate_exception(ctx
, EXCP_RI
);
1343 save_cpu_state(ctx
, 1);
1345 ctx
->bstate
= BS_STOP
;
1348 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
1350 TranslationBlock
*tb
;
1352 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
1354 gen_op_goto_tb0(TBPARAM(tb
));
1356 gen_op_goto_tb1(TBPARAM(tb
));
1357 gen_op_save_pc(dest
);
1358 gen_op_set_T0((long)tb
+ n
);
1361 gen_op_save_pc(dest
);
1367 /* Branches (before delay slot) */
1368 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
1369 int rs
, int rt
, int32_t offset
)
1371 target_ulong btarget
;
1377 /* Load needed operands */
1383 /* Compare two registers */
1385 GEN_LOAD_REG_TN(T0
, rs
);
1386 GEN_LOAD_REG_TN(T1
, rt
);
1389 btarget
= ctx
->pc
+ 4 + offset
;
1403 /* Compare to zero */
1405 gen_op_load_gpr_T0(rs
);
1408 btarget
= ctx
->pc
+ 4 + offset
;
1412 /* Jump to immediate */
1413 btarget
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | offset
;
1417 /* Jump to register */
1418 if (offset
!= 0 && offset
!= 16) {
1419 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
1420 others are reserved. */
1421 generate_exception(ctx
, EXCP_RI
);
1424 GEN_LOAD_REG_TN(T2
, rs
);
1427 MIPS_INVAL("branch/jump");
1428 generate_exception(ctx
, EXCP_RI
);
1432 /* No condition to be computed */
1434 case OPC_BEQ
: /* rx == rx */
1435 case OPC_BEQL
: /* rx == rx likely */
1436 case OPC_BGEZ
: /* 0 >= 0 */
1437 case OPC_BGEZL
: /* 0 >= 0 likely */
1438 case OPC_BLEZ
: /* 0 <= 0 */
1439 case OPC_BLEZL
: /* 0 <= 0 likely */
1441 ctx
->hflags
|= MIPS_HFLAG_B
;
1442 MIPS_DEBUG("balways");
1444 case OPC_BGEZAL
: /* 0 >= 0 */
1445 case OPC_BGEZALL
: /* 0 >= 0 likely */
1446 /* Always take and link */
1448 ctx
->hflags
|= MIPS_HFLAG_B
;
1449 MIPS_DEBUG("balways and link");
1451 case OPC_BNE
: /* rx != rx */
1452 case OPC_BGTZ
: /* 0 > 0 */
1453 case OPC_BLTZ
: /* 0 < 0 */
1454 /* Treated as NOP */
1455 MIPS_DEBUG("bnever (NOP)");
1457 case OPC_BLTZAL
: /* 0 < 0 */
1458 gen_op_set_T0(ctx
->pc
+ 8);
1459 gen_op_store_T0_gpr(31);
1461 case OPC_BLTZALL
: /* 0 < 0 likely */
1462 gen_op_set_T0(ctx
->pc
+ 8);
1463 gen_op_store_T0_gpr(31);
1464 gen_goto_tb(ctx
, 0, ctx
->pc
+ 4);
1466 case OPC_BNEL
: /* rx != rx likely */
1467 case OPC_BGTZL
: /* 0 > 0 likely */
1468 case OPC_BLTZL
: /* 0 < 0 likely */
1469 /* Skip the instruction in the delay slot */
1470 MIPS_DEBUG("bnever and skip");
1471 gen_goto_tb(ctx
, 0, ctx
->pc
+ 4);
1474 ctx
->hflags
|= MIPS_HFLAG_B
;
1475 MIPS_DEBUG("j %08x", btarget
);
1479 ctx
->hflags
|= MIPS_HFLAG_B
;
1480 MIPS_DEBUG("jal %08x", btarget
);
1483 ctx
->hflags
|= MIPS_HFLAG_BR
;
1484 MIPS_DEBUG("jr %s", regnames
[rs
]);
1488 ctx
->hflags
|= MIPS_HFLAG_BR
;
1489 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
1492 MIPS_INVAL("branch/jump");
1493 generate_exception(ctx
, EXCP_RI
);
1500 MIPS_DEBUG("beq %s, %s, %08x",
1501 regnames
[rs
], regnames
[rt
], btarget
);
1505 MIPS_DEBUG("beql %s, %s, %08x",
1506 regnames
[rs
], regnames
[rt
], btarget
);
1510 MIPS_DEBUG("bne %s, %s, %08x",
1511 regnames
[rs
], regnames
[rt
], btarget
);
1515 MIPS_DEBUG("bnel %s, %s, %08x",
1516 regnames
[rs
], regnames
[rt
], btarget
);
1520 MIPS_DEBUG("bgez %s, %08x", regnames
[rs
], btarget
);
1524 MIPS_DEBUG("bgezl %s, %08x", regnames
[rs
], btarget
);
1528 MIPS_DEBUG("bgezal %s, %08x", regnames
[rs
], btarget
);
1534 MIPS_DEBUG("bgezall %s, %08x", regnames
[rs
], btarget
);
1538 MIPS_DEBUG("bgtz %s, %08x", regnames
[rs
], btarget
);
1542 MIPS_DEBUG("bgtzl %s, %08x", regnames
[rs
], btarget
);
1546 MIPS_DEBUG("blez %s, %08x", regnames
[rs
], btarget
);
1550 MIPS_DEBUG("blezl %s, %08x", regnames
[rs
], btarget
);
1554 MIPS_DEBUG("bltz %s, %08x", regnames
[rs
], btarget
);
1558 MIPS_DEBUG("bltzl %s, %08x", regnames
[rs
], btarget
);
1563 MIPS_DEBUG("bltzal %s, %08x", regnames
[rs
], btarget
);
1565 ctx
->hflags
|= MIPS_HFLAG_BC
;
1570 MIPS_DEBUG("bltzall %s, %08x", regnames
[rs
], btarget
);
1572 ctx
->hflags
|= MIPS_HFLAG_BL
;
1577 MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
1578 blink
, ctx
->hflags
, btarget
);
1579 ctx
->btarget
= btarget
;
1581 gen_op_set_T0(ctx
->pc
+ 8);
1582 gen_op_store_T0_gpr(blink
);
1587 /* special3 bitfield operations */
1588 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
1589 int rs
, int lsb
, int msb
)
1591 GEN_LOAD_REG_TN(T1
, rs
);
1596 gen_op_ext(lsb
, msb
+ 1);
1601 gen_op_ext(lsb
, msb
+ 1 + 32);
1606 gen_op_ext(lsb
+ 32, msb
+ 1);
1609 gen_op_ext(lsb
, msb
+ 1);
1614 GEN_LOAD_REG_TN(T2
, rt
);
1615 gen_op_ins(lsb
, msb
- lsb
+ 1);
1620 GEN_LOAD_REG_TN(T2
, rt
);
1621 gen_op_ins(lsb
, msb
- lsb
+ 1 + 32);
1626 GEN_LOAD_REG_TN(T2
, rt
);
1627 gen_op_ins(lsb
+ 32, msb
- lsb
+ 1);
1632 GEN_LOAD_REG_TN(T2
, rt
);
1633 gen_op_ins(lsb
, msb
- lsb
+ 1);
1637 MIPS_INVAL("bitops");
1638 generate_exception(ctx
, EXCP_RI
);
1641 GEN_STORE_TN_REG(rt
, T0
);
1644 /* CP0 (MMU and control) */
1645 static void gen_mfc0 (DisasContext
*ctx
, int reg
, int sel
)
1647 const char *rn
= "invalid";
1653 gen_op_mfc0_index();
1657 // gen_op_mfc0_mvpcontrol(); /* MT ASE */
1661 // gen_op_mfc0_mvpconf0(); /* MT ASE */
1665 // gen_op_mfc0_mvpconf1(); /* MT ASE */
1675 gen_op_mfc0_random();
1679 // gen_op_mfc0_vpecontrol(); /* MT ASE */
1683 // gen_op_mfc0_vpeconf0(); /* MT ASE */
1687 // gen_op_mfc0_vpeconf1(); /* MT ASE */
1691 // gen_op_mfc0_YQMask(); /* MT ASE */
1695 // gen_op_mfc0_vpeschedule(); /* MT ASE */
1699 // gen_op_mfc0_vpeschefback(); /* MT ASE */
1700 rn
= "VPEScheFBack";
1703 // gen_op_mfc0_vpeopt(); /* MT ASE */
1713 gen_op_mfc0_entrylo0();
1717 // gen_op_mfc0_tcstatus(); /* MT ASE */
1721 // gen_op_mfc0_tcbind(); /* MT ASE */
1725 // gen_op_mfc0_tcrestart(); /* MT ASE */
1729 // gen_op_mfc0_tchalt(); /* MT ASE */
1733 // gen_op_mfc0_tccontext(); /* MT ASE */
1737 // gen_op_mfc0_tcschedule(); /* MT ASE */
1741 // gen_op_mfc0_tcschefback(); /* MT ASE */
1751 gen_op_mfc0_entrylo1();
1761 gen_op_mfc0_context();
1765 // gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
1766 rn
= "ContextConfig";
1775 gen_op_mfc0_pagemask();
1779 gen_op_mfc0_pagegrain();
1789 gen_op_mfc0_wired();
1793 // gen_op_mfc0_srsconf0(); /* shadow registers */
1797 // gen_op_mfc0_srsconf1(); /* shadow registers */
1801 // gen_op_mfc0_srsconf2(); /* shadow registers */
1805 // gen_op_mfc0_srsconf3(); /* shadow registers */
1809 // gen_op_mfc0_srsconf4(); /* shadow registers */
1819 gen_op_mfc0_hwrena();
1829 gen_op_mfc0_badvaddr();
1839 gen_op_mfc0_count();
1842 /* 6,7 are implementation dependent */
1850 gen_op_mfc0_entryhi();
1860 gen_op_mfc0_compare();
1863 /* 6,7 are implementation dependent */
1871 gen_op_mfc0_status();
1875 gen_op_mfc0_intctl();
1879 gen_op_mfc0_srsctl();
1883 // gen_op_mfc0_srsmap(); /* shadow registers */
1893 gen_op_mfc0_cause();
1917 gen_op_mfc0_ebase();
1927 gen_op_mfc0_config0();
1931 gen_op_mfc0_config1();
1935 gen_op_mfc0_config2();
1939 gen_op_mfc0_config3();
1942 /* 6,7 are implementation dependent */
1950 gen_op_mfc0_lladdr();
1960 gen_op_mfc0_watchlo0();
1964 // gen_op_mfc0_watchlo1();
1968 // gen_op_mfc0_watchlo2();
1972 // gen_op_mfc0_watchlo3();
1976 // gen_op_mfc0_watchlo4();
1980 // gen_op_mfc0_watchlo5();
1984 // gen_op_mfc0_watchlo6();
1988 // gen_op_mfc0_watchlo7();
1998 gen_op_mfc0_watchhi0();
2002 // gen_op_mfc0_watchhi1();
2006 // gen_op_mfc0_watchhi2();
2010 // gen_op_mfc0_watchhi3();
2014 // gen_op_mfc0_watchhi4();
2018 // gen_op_mfc0_watchhi5();
2022 // gen_op_mfc0_watchhi6();
2026 // gen_op_mfc0_watchhi7();
2036 /* 64 bit MMU only */
2037 gen_op_mfc0_xcontext();
2045 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2048 gen_op_mfc0_framemask();
2057 rn
= "'Diagnostic"; /* implementation dependent */
2062 gen_op_mfc0_debug(); /* EJTAG support */
2066 // gen_op_mfc0_tracecontrol(); /* PDtrace support */
2067 rn
= "TraceControl";
2070 // gen_op_mfc0_tracecontrol2(); /* PDtrace support */
2071 rn
= "TraceControl2";
2074 // gen_op_mfc0_usertracedata(); /* PDtrace support */
2075 rn
= "UserTraceData";
2078 // gen_op_mfc0_debug(); /* PDtrace support */
2088 gen_op_mfc0_depc(); /* EJTAG support */
2098 gen_op_mfc0_performance0();
2099 rn
= "Performance0";
2102 // gen_op_mfc0_performance1();
2103 rn
= "Performance1";
2106 // gen_op_mfc0_performance2();
2107 rn
= "Performance2";
2110 // gen_op_mfc0_performance3();
2111 rn
= "Performance3";
2114 // gen_op_mfc0_performance4();
2115 rn
= "Performance4";
2118 // gen_op_mfc0_performance5();
2119 rn
= "Performance5";
2122 // gen_op_mfc0_performance6();
2123 rn
= "Performance6";
2126 // gen_op_mfc0_performance7();
2127 rn
= "Performance7";
2152 gen_op_mfc0_taglo();
2159 gen_op_mfc0_datalo();
2172 gen_op_mfc0_taghi();
2179 gen_op_mfc0_datahi();
2189 gen_op_mfc0_errorepc();
2199 gen_op_mfc0_desave(); /* EJTAG support */
2209 #if defined MIPS_DEBUG_DISAS
2210 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2211 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
2218 #if defined MIPS_DEBUG_DISAS
2219 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2220 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
2224 generate_exception(ctx
, EXCP_RI
);
2227 static void gen_mtc0 (DisasContext
*ctx
, int reg
, int sel
)
2229 const char *rn
= "invalid";
2235 gen_op_mtc0_index();
2239 // gen_op_mtc0_mvpcontrol(); /* MT ASE */
2243 // gen_op_mtc0_mvpconf0(); /* MT ASE */
2247 // gen_op_mtc0_mvpconf1(); /* MT ASE */
2261 // gen_op_mtc0_vpecontrol(); /* MT ASE */
2265 // gen_op_mtc0_vpeconf0(); /* MT ASE */
2269 // gen_op_mtc0_vpeconf1(); /* MT ASE */
2273 // gen_op_mtc0_YQMask(); /* MT ASE */
2277 // gen_op_mtc0_vpeschedule(); /* MT ASE */
2281 // gen_op_mtc0_vpeschefback(); /* MT ASE */
2282 rn
= "VPEScheFBack";
2285 // gen_op_mtc0_vpeopt(); /* MT ASE */
2295 gen_op_mtc0_entrylo0();
2299 // gen_op_mtc0_tcstatus(); /* MT ASE */
2303 // gen_op_mtc0_tcbind(); /* MT ASE */
2307 // gen_op_mtc0_tcrestart(); /* MT ASE */
2311 // gen_op_mtc0_tchalt(); /* MT ASE */
2315 // gen_op_mtc0_tccontext(); /* MT ASE */
2319 // gen_op_mtc0_tcschedule(); /* MT ASE */
2323 // gen_op_mtc0_tcschefback(); /* MT ASE */
2333 gen_op_mtc0_entrylo1();
2343 gen_op_mtc0_context();
2347 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
2348 rn
= "ContextConfig";
2357 gen_op_mtc0_pagemask();
2361 gen_op_mtc0_pagegrain();
2371 gen_op_mtc0_wired();
2375 // gen_op_mtc0_srsconf0(); /* shadow registers */
2379 // gen_op_mtc0_srsconf1(); /* shadow registers */
2383 // gen_op_mtc0_srsconf2(); /* shadow registers */
2387 // gen_op_mtc0_srsconf3(); /* shadow registers */
2391 // gen_op_mtc0_srsconf4(); /* shadow registers */
2401 gen_op_mtc0_hwrena();
2415 gen_op_mtc0_count();
2418 /* 6,7 are implementation dependent */
2422 /* Stop translation as we may have switched the execution mode */
2423 ctx
->bstate
= BS_STOP
;
2428 gen_op_mtc0_entryhi();
2438 gen_op_mtc0_compare();
2441 /* 6,7 are implementation dependent */
2445 /* Stop translation as we may have switched the execution mode */
2446 ctx
->bstate
= BS_STOP
;
2451 gen_op_mtc0_status();
2455 gen_op_mtc0_intctl();
2459 gen_op_mtc0_srsctl();
2463 // gen_op_mtc0_srsmap(); /* shadow registers */
2469 /* Stop translation as we may have switched the execution mode */
2470 ctx
->bstate
= BS_STOP
;
2475 gen_op_mtc0_cause();
2481 /* Stop translation as we may have switched the execution mode */
2482 ctx
->bstate
= BS_STOP
;
2501 gen_op_mtc0_ebase();
2511 gen_op_mtc0_config0();
2519 gen_op_mtc0_config2();
2526 /* 6,7 are implementation dependent */
2528 rn
= "Invalid config selector";
2531 /* Stop translation as we may have switched the execution mode */
2532 ctx
->bstate
= BS_STOP
;
2547 gen_op_mtc0_watchlo0();
2551 // gen_op_mtc0_watchlo1();
2555 // gen_op_mtc0_watchlo2();
2559 // gen_op_mtc0_watchlo3();
2563 // gen_op_mtc0_watchlo4();
2567 // gen_op_mtc0_watchlo5();
2571 // gen_op_mtc0_watchlo6();
2575 // gen_op_mtc0_watchlo7();
2585 gen_op_mtc0_watchhi0();
2589 // gen_op_mtc0_watchhi1();
2593 // gen_op_mtc0_watchhi2();
2597 // gen_op_mtc0_watchhi3();
2601 // gen_op_mtc0_watchhi4();
2605 // gen_op_mtc0_watchhi5();
2609 // gen_op_mtc0_watchhi6();
2613 // gen_op_mtc0_watchhi7();
2623 /* 64 bit MMU only */
2624 gen_op_mtc0_xcontext();
2632 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2635 gen_op_mtc0_framemask();
2644 rn
= "Diagnostic"; /* implementation dependent */
2649 gen_op_mtc0_debug(); /* EJTAG support */
2653 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
2654 rn
= "TraceControl";
2657 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
2658 rn
= "TraceControl2";
2661 // gen_op_mtc0_usertracedata(); /* PDtrace support */
2662 rn
= "UserTraceData";
2665 // gen_op_mtc0_debug(); /* PDtrace support */
2671 /* Stop translation as we may have switched the execution mode */
2672 ctx
->bstate
= BS_STOP
;
2677 gen_op_mtc0_depc(); /* EJTAG support */
2687 gen_op_mtc0_performance0();
2688 rn
= "Performance0";
2691 // gen_op_mtc0_performance1();
2692 rn
= "Performance1";
2695 // gen_op_mtc0_performance2();
2696 rn
= "Performance2";
2699 // gen_op_mtc0_performance3();
2700 rn
= "Performance3";
2703 // gen_op_mtc0_performance4();
2704 rn
= "Performance4";
2707 // gen_op_mtc0_performance5();
2708 rn
= "Performance5";
2711 // gen_op_mtc0_performance6();
2712 rn
= "Performance6";
2715 // gen_op_mtc0_performance7();
2716 rn
= "Performance7";
2742 gen_op_mtc0_taglo();
2749 gen_op_mtc0_datalo();
2762 gen_op_mtc0_taghi();
2769 gen_op_mtc0_datahi();
2780 gen_op_mtc0_errorepc();
2790 gen_op_mtc0_desave(); /* EJTAG support */
2796 /* Stop translation as we may have switched the execution mode */
2797 ctx
->bstate
= BS_STOP
;
2802 #if defined MIPS_DEBUG_DISAS
2803 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2804 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
2811 #if defined MIPS_DEBUG_DISAS
2812 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2813 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
2817 generate_exception(ctx
, EXCP_RI
);
2820 static void gen_dmfc0 (DisasContext
*ctx
, int reg
, int sel
)
2822 const char *rn
= "invalid";
2828 gen_op_mfc0_index();
2832 // gen_op_dmfc0_mvpcontrol(); /* MT ASE */
2836 // gen_op_dmfc0_mvpconf0(); /* MT ASE */
2840 // gen_op_dmfc0_mvpconf1(); /* MT ASE */
2850 gen_op_mfc0_random();
2854 // gen_op_dmfc0_vpecontrol(); /* MT ASE */
2858 // gen_op_dmfc0_vpeconf0(); /* MT ASE */
2862 // gen_op_dmfc0_vpeconf1(); /* MT ASE */
2866 // gen_op_dmfc0_YQMask(); /* MT ASE */
2870 // gen_op_dmfc0_vpeschedule(); /* MT ASE */
2874 // gen_op_dmfc0_vpeschefback(); /* MT ASE */
2875 rn
= "VPEScheFBack";
2878 // gen_op_dmfc0_vpeopt(); /* MT ASE */
2888 gen_op_dmfc0_entrylo0();
2892 // gen_op_dmfc0_tcstatus(); /* MT ASE */
2896 // gen_op_dmfc0_tcbind(); /* MT ASE */
2900 // gen_op_dmfc0_tcrestart(); /* MT ASE */
2904 // gen_op_dmfc0_tchalt(); /* MT ASE */
2908 // gen_op_dmfc0_tccontext(); /* MT ASE */
2912 // gen_op_dmfc0_tcschedule(); /* MT ASE */
2916 // gen_op_dmfc0_tcschefback(); /* MT ASE */
2926 gen_op_dmfc0_entrylo1();
2936 gen_op_dmfc0_context();
2940 // gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
2941 rn
= "ContextConfig";
2950 gen_op_mfc0_pagemask();
2954 gen_op_mfc0_pagegrain();
2964 gen_op_mfc0_wired();
2968 // gen_op_dmfc0_srsconf0(); /* shadow registers */
2972 // gen_op_dmfc0_srsconf1(); /* shadow registers */
2976 // gen_op_dmfc0_srsconf2(); /* shadow registers */
2980 // gen_op_dmfc0_srsconf3(); /* shadow registers */
2984 // gen_op_dmfc0_srsconf4(); /* shadow registers */
2994 gen_op_mfc0_hwrena();
3004 gen_op_dmfc0_badvaddr();
3014 gen_op_mfc0_count();
3017 /* 6,7 are implementation dependent */
3025 gen_op_dmfc0_entryhi();
3035 gen_op_mfc0_compare();
3038 /* 6,7 are implementation dependent */
3046 gen_op_mfc0_status();
3050 gen_op_mfc0_intctl();
3054 gen_op_mfc0_srsctl();
3058 gen_op_mfc0_srsmap(); /* shadow registers */
3068 gen_op_mfc0_cause();
3092 gen_op_mfc0_ebase();
3102 gen_op_mfc0_config0();
3106 gen_op_mfc0_config1();
3110 gen_op_mfc0_config2();
3114 gen_op_mfc0_config3();
3117 /* 6,7 are implementation dependent */
3125 gen_op_dmfc0_lladdr();
3135 gen_op_dmfc0_watchlo0();
3139 // gen_op_dmfc0_watchlo1();
3143 // gen_op_dmfc0_watchlo2();
3147 // gen_op_dmfc0_watchlo3();
3151 // gen_op_dmfc0_watchlo4();
3155 // gen_op_dmfc0_watchlo5();
3159 // gen_op_dmfc0_watchlo6();
3163 // gen_op_dmfc0_watchlo7();
3173 gen_op_mfc0_watchhi0();
3177 // gen_op_mfc0_watchhi1();
3181 // gen_op_mfc0_watchhi2();
3185 // gen_op_mfc0_watchhi3();
3189 // gen_op_mfc0_watchhi4();
3193 // gen_op_mfc0_watchhi5();
3197 // gen_op_mfc0_watchhi6();
3201 // gen_op_mfc0_watchhi7();
3211 /* 64 bit MMU only */
3212 gen_op_dmfc0_xcontext();
3220 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3223 gen_op_mfc0_framemask();
3232 rn
= "'Diagnostic"; /* implementation dependent */
3237 gen_op_mfc0_debug(); /* EJTAG support */
3241 // gen_op_dmfc0_tracecontrol(); /* PDtrace support */
3242 rn
= "TraceControl";
3245 // gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
3246 rn
= "TraceControl2";
3249 // gen_op_dmfc0_usertracedata(); /* PDtrace support */
3250 rn
= "UserTraceData";
3253 // gen_op_dmfc0_debug(); /* PDtrace support */
3263 gen_op_dmfc0_depc(); /* EJTAG support */
3273 gen_op_mfc0_performance0();
3274 rn
= "Performance0";
3277 // gen_op_dmfc0_performance1();
3278 rn
= "Performance1";
3281 // gen_op_dmfc0_performance2();
3282 rn
= "Performance2";
3285 // gen_op_dmfc0_performance3();
3286 rn
= "Performance3";
3289 // gen_op_dmfc0_performance4();
3290 rn
= "Performance4";
3293 // gen_op_dmfc0_performance5();
3294 rn
= "Performance5";
3297 // gen_op_dmfc0_performance6();
3298 rn
= "Performance6";
3301 // gen_op_dmfc0_performance7();
3302 rn
= "Performance7";
3327 gen_op_mfc0_taglo();
3334 gen_op_mfc0_datalo();
3347 gen_op_mfc0_taghi();
3354 gen_op_mfc0_datahi();
3364 gen_op_dmfc0_errorepc();
3374 gen_op_mfc0_desave(); /* EJTAG support */
3384 #if defined MIPS_DEBUG_DISAS
3385 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3386 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
3393 #if defined MIPS_DEBUG_DISAS
3394 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3395 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
3399 generate_exception(ctx
, EXCP_RI
);
3402 static void gen_dmtc0 (DisasContext
*ctx
, int reg
, int sel
)
3404 const char *rn
= "invalid";
3410 gen_op_mtc0_index();
3414 // gen_op_dmtc0_mvpcontrol(); /* MT ASE */
3418 // gen_op_dmtc0_mvpconf0(); /* MT ASE */
3422 // gen_op_dmtc0_mvpconf1(); /* MT ASE */
3436 // gen_op_dmtc0_vpecontrol(); /* MT ASE */
3440 // gen_op_dmtc0_vpeconf0(); /* MT ASE */
3444 // gen_op_dmtc0_vpeconf1(); /* MT ASE */
3448 // gen_op_dmtc0_YQMask(); /* MT ASE */
3452 // gen_op_dmtc0_vpeschedule(); /* MT ASE */
3456 // gen_op_dmtc0_vpeschefback(); /* MT ASE */
3457 rn
= "VPEScheFBack";
3460 // gen_op_dmtc0_vpeopt(); /* MT ASE */
3470 gen_op_dmtc0_entrylo0();
3474 // gen_op_dmtc0_tcstatus(); /* MT ASE */
3478 // gen_op_dmtc0_tcbind(); /* MT ASE */
3482 // gen_op_dmtc0_tcrestart(); /* MT ASE */
3486 // gen_op_dmtc0_tchalt(); /* MT ASE */
3490 // gen_op_dmtc0_tccontext(); /* MT ASE */
3494 // gen_op_dmtc0_tcschedule(); /* MT ASE */
3498 // gen_op_dmtc0_tcschefback(); /* MT ASE */
3508 gen_op_dmtc0_entrylo1();
3518 gen_op_dmtc0_context();
3522 // gen_op_dmtc0_contextconfig(); /* SmartMIPS ASE */
3523 rn
= "ContextConfig";
3532 gen_op_mtc0_pagemask();
3536 gen_op_mtc0_pagegrain();
3546 gen_op_mtc0_wired();
3550 // gen_op_dmtc0_srsconf0(); /* shadow registers */
3554 // gen_op_dmtc0_srsconf1(); /* shadow registers */
3558 // gen_op_dmtc0_srsconf2(); /* shadow registers */
3562 // gen_op_dmtc0_srsconf3(); /* shadow registers */
3566 // gen_op_dmtc0_srsconf4(); /* shadow registers */
3576 gen_op_mtc0_hwrena();
3590 gen_op_mtc0_count();
3593 /* 6,7 are implementation dependent */
3597 /* Stop translation as we may have switched the execution mode */
3598 ctx
->bstate
= BS_STOP
;
3603 gen_op_mtc0_entryhi();
3613 gen_op_mtc0_compare();
3616 /* 6,7 are implementation dependent */
3620 /* Stop translation as we may have switched the execution mode */
3621 ctx
->bstate
= BS_STOP
;
3626 gen_op_mtc0_status();
3630 gen_op_mtc0_intctl();
3634 gen_op_mtc0_srsctl();
3638 gen_op_mtc0_srsmap(); /* shadow registers */
3644 /* Stop translation as we may have switched the execution mode */
3645 ctx
->bstate
= BS_STOP
;
3650 gen_op_mtc0_cause();
3656 /* Stop translation as we may have switched the execution mode */
3657 ctx
->bstate
= BS_STOP
;
3676 gen_op_mtc0_ebase();
3686 gen_op_mtc0_config0();
3694 gen_op_mtc0_config2();
3701 /* 6,7 are implementation dependent */
3703 rn
= "Invalid config selector";
3706 /* Stop translation as we may have switched the execution mode */
3707 ctx
->bstate
= BS_STOP
;
3722 gen_op_dmtc0_watchlo0();
3726 // gen_op_dmtc0_watchlo1();
3730 // gen_op_dmtc0_watchlo2();
3734 // gen_op_dmtc0_watchlo3();
3738 // gen_op_dmtc0_watchlo4();
3742 // gen_op_dmtc0_watchlo5();
3746 // gen_op_dmtc0_watchlo6();
3750 // gen_op_dmtc0_watchlo7();
3760 gen_op_mtc0_watchhi0();
3764 // gen_op_dmtc0_watchhi1();
3768 // gen_op_dmtc0_watchhi2();
3772 // gen_op_dmtc0_watchhi3();
3776 // gen_op_dmtc0_watchhi4();
3780 // gen_op_dmtc0_watchhi5();
3784 // gen_op_dmtc0_watchhi6();
3788 // gen_op_dmtc0_watchhi7();
3798 /* 64 bit MMU only */
3799 gen_op_dmtc0_xcontext();
3807 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3810 gen_op_mtc0_framemask();
3819 rn
= "Diagnostic"; /* implementation dependent */
3824 gen_op_mtc0_debug(); /* EJTAG support */
3828 // gen_op_dmtc0_tracecontrol(); /* PDtrace support */
3829 rn
= "TraceControl";
3832 // gen_op_dmtc0_tracecontrol2(); /* PDtrace support */
3833 rn
= "TraceControl2";
3836 // gen_op_dmtc0_usertracedata(); /* PDtrace support */
3837 rn
= "UserTraceData";
3840 // gen_op_dmtc0_debug(); /* PDtrace support */
3846 /* Stop translation as we may have switched the execution mode */
3847 ctx
->bstate
= BS_STOP
;
3852 gen_op_dmtc0_depc(); /* EJTAG support */
3862 gen_op_mtc0_performance0();
3863 rn
= "Performance0";
3866 // gen_op_dmtc0_performance1();
3867 rn
= "Performance1";
3870 // gen_op_dmtc0_performance2();
3871 rn
= "Performance2";
3874 // gen_op_dmtc0_performance3();
3875 rn
= "Performance3";
3878 // gen_op_dmtc0_performance4();
3879 rn
= "Performance4";
3882 // gen_op_dmtc0_performance5();
3883 rn
= "Performance5";
3886 // gen_op_dmtc0_performance6();
3887 rn
= "Performance6";
3890 // gen_op_dmtc0_performance7();
3891 rn
= "Performance7";
3917 gen_op_mtc0_taglo();
3924 gen_op_mtc0_datalo();
3937 gen_op_mtc0_taghi();
3944 gen_op_mtc0_datahi();
3955 gen_op_dmtc0_errorepc();
3965 gen_op_mtc0_desave(); /* EJTAG support */
3971 /* Stop translation as we may have switched the execution mode */
3972 ctx
->bstate
= BS_STOP
;
3977 #if defined MIPS_DEBUG_DISAS
3978 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3979 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
3986 #if defined MIPS_DEBUG_DISAS
3987 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3988 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
3992 generate_exception(ctx
, EXCP_RI
);
3995 static void gen_cp0 (DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
3997 const char *opn
= "unk";
3999 if ((!ctx
->CP0_Status
& (1 << CP0St_CU0
) &&
4000 (ctx
->hflags
& MIPS_HFLAG_UM
)) &&
4001 !(ctx
->hflags
& MIPS_HFLAG_ERL
) &&
4002 !(ctx
->hflags
& MIPS_HFLAG_EXL
)) {
4003 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4004 fprintf(logfile
, "CP0 is not usable\n");
4006 generate_exception (ctx
, EXCP_CpU
);
4016 gen_mfc0(ctx
, rd
, ctx
->opcode
& 0x7);
4017 gen_op_store_T0_gpr(rt
);
4021 /* If we get an exception, we want to restart at next instruction */
4022 /* XXX: breaks for mtc in delay slot */
4024 save_cpu_state(ctx
, 1);
4026 GEN_LOAD_REG_TN(T0
, rt
);
4027 gen_mtc0(ctx
, rd
, ctx
->opcode
& 0x7);
4035 gen_dmfc0(ctx
, rd
, ctx
->opcode
& 0x7);
4036 gen_op_store_T0_gpr(rt
);
4040 /* If we get an exception, we want to restart at next instruction */
4041 /* XXX: breaks for dmtc in delay slot */
4043 save_cpu_state(ctx
, 1);
4045 GEN_LOAD_REG_TN(T0
, rt
);
4046 gen_dmtc0(ctx
, rd
, ctx
->opcode
& 0x7);
4049 #if defined(MIPS_USES_R4K_TLB)
4069 save_cpu_state(ctx
, 0);
4071 ctx
->bstate
= BS_EXCP
;
4075 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
4076 generate_exception(ctx
, EXCP_RI
);
4078 save_cpu_state(ctx
, 0);
4080 ctx
->bstate
= BS_EXCP
;
4085 /* If we get an exception, we want to restart at next instruction */
4087 save_cpu_state(ctx
, 1);
4090 ctx
->bstate
= BS_EXCP
;
4093 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4094 fprintf(logfile
, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
4095 ctx
->opcode
, ctx
->opcode
>> 26, ctx
->opcode
& 0x3F,
4096 ((ctx
->opcode
>> 16) & 0x1F));
4098 generate_exception(ctx
, EXCP_RI
);
4101 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
4104 /* CP1 Branches (before delay slot) */
4105 static void gen_compute_branch1 (DisasContext
*ctx
, uint32_t op
,
4108 target_ulong btarget
;
4110 btarget
= ctx
->pc
+ 4 + offset
;
4115 MIPS_DEBUG("bc1f " TARGET_FMT_lx
, btarget
);
4119 MIPS_DEBUG("bc1fl " TARGET_FMT_lx
, btarget
);
4123 MIPS_DEBUG("bc1t " TARGET_FMT_lx
, btarget
);
4125 ctx
->hflags
|= MIPS_HFLAG_BC
;
4129 MIPS_DEBUG("bc1tl " TARGET_FMT_lx
, btarget
);
4131 ctx
->hflags
|= MIPS_HFLAG_BL
;
4134 MIPS_INVAL("cp1 branch/jump");
4135 generate_exception_err (ctx
, EXCP_RI
, 1);
4140 MIPS_DEBUG("enter ds: cond %02x target " TARGET_FMT_lx
,
4141 ctx
->hflags
, btarget
);
4142 ctx
->btarget
= btarget
;
4147 /* Coprocessor 1 (FPU) */
4148 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
4150 const char *opn
= "unk";
4154 GEN_LOAD_FREG_FTN(WT0
, fs
);
4156 GEN_STORE_TN_REG(rt
, T0
);
4160 GEN_LOAD_REG_TN(T0
, rt
);
4162 GEN_STORE_FTN_FREG(fs
, WT0
);
4166 if (fs
!= 0 && fs
!= 31) {
4167 MIPS_INVAL("cfc1 freg");
4168 generate_exception_err (ctx
, EXCP_RI
, 1);
4171 GEN_LOAD_IMM_TN(T1
, fs
);
4173 GEN_STORE_TN_REG(rt
, T0
);
4177 if (fs
!= 0 && fs
!= 31) {
4178 MIPS_INVAL("ctc1 freg");
4179 generate_exception_err (ctx
, EXCP_RI
, 1);
4182 GEN_LOAD_IMM_TN(T1
, fs
);
4183 GEN_LOAD_REG_TN(T0
, rt
);
4189 /* Not implemented, fallthrough. */
4191 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4192 fprintf(logfile
, "Invalid CP1 opcode: %08x %03x %03x %03x\n",
4193 ctx
->opcode
, ctx
->opcode
>> 26, ctx
->opcode
& 0x3F,
4194 ((ctx
->opcode
>> 16) & 0x1F));
4196 generate_exception_err (ctx
, EXCP_RI
, 1);
4199 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
4202 /* verify if floating point register is valid; an operation is not defined
4203 * if bit 0 of any register specification is set and the FR bit in the
4204 * Status register equals zero, since the register numbers specify an
4205 * even-odd pair of adjacent coprocessor general registers. When the FR bit
4206 * in the Status register equals one, both even and odd register numbers
4207 * are valid. This limitation exists only for 64 bit wide (d,l) registers.
4209 * Multiple 64 bit wide registers can be checked by calling
4210 * CHECK_FR(ctx, freg1 | freg2 | ... | fregN);
4212 #define CHECK_FR(ctx, freg) do { \
4213 if (!((ctx)->CP0_Status & (1<<CP0St_FR)) && ((freg) & 1)) { \
4214 generate_exception_err (ctx, EXCP_RI, 1); \
4219 #define FOP(func, fmt) (((fmt) << 21) | (func))
4221 static void gen_farith (DisasContext
*ctx
, uint32_t op1
, int ft
, int fs
, int fd
)
4223 const char *opn
= "unk";
4224 const char *condnames
[] = {
4243 uint32_t func
= ctx
->opcode
& 0x3f;
4245 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
4247 CHECK_FR(ctx
, fs
| ft
| fd
);
4248 GEN_LOAD_FREG_FTN(DT0
, fs
);
4249 GEN_LOAD_FREG_FTN(DT1
, ft
);
4250 gen_op_float_add_d();
4251 GEN_STORE_FTN_FREG(fd
, DT2
);
4256 CHECK_FR(ctx
, fs
| ft
| fd
);
4257 GEN_LOAD_FREG_FTN(DT0
, fs
);
4258 GEN_LOAD_FREG_FTN(DT1
, ft
);
4259 gen_op_float_sub_d();
4260 GEN_STORE_FTN_FREG(fd
, DT2
);
4265 CHECK_FR(ctx
, fs
| ft
| fd
);
4266 GEN_LOAD_FREG_FTN(DT0
, fs
);
4267 GEN_LOAD_FREG_FTN(DT1
, ft
);
4268 gen_op_float_mul_d();
4269 GEN_STORE_FTN_FREG(fd
, DT2
);
4274 CHECK_FR(ctx
, fs
| ft
| fd
);
4275 GEN_LOAD_FREG_FTN(DT0
, fs
);
4276 GEN_LOAD_FREG_FTN(DT1
, ft
);
4277 gen_op_float_div_d();
4278 GEN_STORE_FTN_FREG(fd
, DT2
);
4283 CHECK_FR(ctx
, fs
| fd
);
4284 GEN_LOAD_FREG_FTN(DT0
, fs
);
4285 gen_op_float_sqrt_d();
4286 GEN_STORE_FTN_FREG(fd
, DT2
);
4290 CHECK_FR(ctx
, fs
| fd
);
4291 GEN_LOAD_FREG_FTN(DT0
, fs
);
4292 gen_op_float_abs_d();
4293 GEN_STORE_FTN_FREG(fd
, DT2
);
4297 CHECK_FR(ctx
, fs
| fd
);
4298 GEN_LOAD_FREG_FTN(DT0
, fs
);
4299 gen_op_float_mov_d();
4300 GEN_STORE_FTN_FREG(fd
, DT2
);
4304 CHECK_FR(ctx
, fs
| fd
);
4305 GEN_LOAD_FREG_FTN(DT0
, fs
);
4306 gen_op_float_chs_d();
4307 GEN_STORE_FTN_FREG(fd
, DT2
);
4316 GEN_LOAD_FREG_FTN(DT0
, fs
);
4317 gen_op_float_roundw_d();
4318 GEN_STORE_FTN_FREG(fd
, WT2
);
4323 GEN_LOAD_FREG_FTN(DT0
, fs
);
4324 gen_op_float_truncw_d();
4325 GEN_STORE_FTN_FREG(fd
, WT2
);
4330 GEN_LOAD_FREG_FTN(DT0
, fs
);
4331 gen_op_float_ceilw_d();
4332 GEN_STORE_FTN_FREG(fd
, WT2
);
4337 GEN_LOAD_FREG_FTN(DT0
, fs
);
4338 gen_op_float_floorw_d();
4339 GEN_STORE_FTN_FREG(fd
, WT2
);
4344 GEN_LOAD_FREG_FTN(WT0
, fs
);
4345 gen_op_float_cvtd_s();
4346 GEN_STORE_FTN_FREG(fd
, DT2
);
4351 GEN_LOAD_FREG_FTN(WT0
, fs
);
4352 gen_op_float_cvtd_w();
4353 GEN_STORE_FTN_FREG(fd
, DT2
);
4372 CHECK_FR(ctx
, fs
| ft
);
4373 GEN_LOAD_FREG_FTN(DT0
, fs
);
4374 GEN_LOAD_FREG_FTN(DT1
, ft
);
4376 opn
= condnames
[func
-48];
4379 GEN_LOAD_FREG_FTN(WT0
, fs
);
4380 GEN_LOAD_FREG_FTN(WT1
, ft
);
4381 gen_op_float_add_s();
4382 GEN_STORE_FTN_FREG(fd
, WT2
);
4387 GEN_LOAD_FREG_FTN(WT0
, fs
);
4388 GEN_LOAD_FREG_FTN(WT1
, ft
);
4389 gen_op_float_sub_s();
4390 GEN_STORE_FTN_FREG(fd
, WT2
);
4395 GEN_LOAD_FREG_FTN(WT0
, fs
);
4396 GEN_LOAD_FREG_FTN(WT1
, ft
);
4397 gen_op_float_mul_s();
4398 GEN_STORE_FTN_FREG(fd
, WT2
);
4403 GEN_LOAD_FREG_FTN(WT0
, fs
);
4404 GEN_LOAD_FREG_FTN(WT1
, ft
);
4405 gen_op_float_div_s();
4406 GEN_STORE_FTN_FREG(fd
, WT2
);
4411 GEN_LOAD_FREG_FTN(WT0
, fs
);
4412 gen_op_float_sqrt_s();
4413 GEN_STORE_FTN_FREG(fd
, WT2
);
4417 GEN_LOAD_FREG_FTN(WT0
, fs
);
4418 gen_op_float_abs_s();
4419 GEN_STORE_FTN_FREG(fd
, WT2
);
4423 GEN_LOAD_FREG_FTN(WT0
, fs
);
4424 gen_op_float_mov_s();
4425 GEN_STORE_FTN_FREG(fd
, WT2
);
4429 GEN_LOAD_FREG_FTN(WT0
, fs
);
4430 gen_op_float_chs_s();
4431 GEN_STORE_FTN_FREG(fd
, WT2
);
4435 GEN_LOAD_FREG_FTN(WT0
, fs
);
4436 gen_op_float_roundw_s();
4437 GEN_STORE_FTN_FREG(fd
, WT2
);
4441 GEN_LOAD_FREG_FTN(WT0
, fs
);
4442 gen_op_float_truncw_s();
4443 GEN_STORE_FTN_FREG(fd
, WT2
);
4448 GEN_LOAD_FREG_FTN(DT0
, fs
);
4449 gen_op_float_cvts_d();
4450 GEN_STORE_FTN_FREG(fd
, WT2
);
4454 GEN_LOAD_FREG_FTN(WT0
, fs
);
4455 gen_op_float_cvts_w();
4456 GEN_STORE_FTN_FREG(fd
, WT2
);
4460 GEN_LOAD_FREG_FTN(WT0
, fs
);
4461 gen_op_float_cvtw_s();
4462 GEN_STORE_FTN_FREG(fd
, WT2
);
4467 GEN_LOAD_FREG_FTN(DT0
, fs
);
4468 gen_op_float_cvtw_d();
4469 GEN_STORE_FTN_FREG(fd
, WT2
);
4488 GEN_LOAD_FREG_FTN(WT0
, fs
);
4489 GEN_LOAD_FREG_FTN(WT1
, ft
);
4491 opn
= condnames
[func
-48];
4494 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4495 fprintf(logfile
, "Invalid FP arith function: %08x %03x %03x %03x\n",
4496 ctx
->opcode
, ctx
->opcode
>> 26, ctx
->opcode
& 0x3F,
4497 ((ctx
->opcode
>> 16) & 0x1F));
4499 generate_exception_err (ctx
, EXCP_RI
, 1);
4503 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
4505 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
4508 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
4513 ccbit
= 1 << (24 + cc
);
4517 gen_op_movf(ccbit
, rd
, rs
);
4519 gen_op_movt(ccbit
, rd
, rs
);
4522 /* ISA extensions (ASEs) */
4523 /* MIPS16 extension to MIPS32 */
4524 /* SmartMIPS extension to MIPS32 */
4526 #ifdef MIPS_HAS_MIPS64
4527 /* Coprocessor 3 (FPU) */
4529 /* MDMX extension to MIPS64 */
4530 /* MIPS-3D extension to MIPS64 */
4534 static void gen_blikely(DisasContext
*ctx
)
4537 l1
= gen_new_label();
4539 gen_op_save_state(ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
4540 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
4544 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
4548 uint32_t op
, op1
, op2
;
4551 /* make sure instructions are on a word boundary */
4552 if (ctx
->pc
& 0x3) {
4553 generate_exception(ctx
, EXCP_AdEL
);
4557 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
4558 /* Handle blikely not taken case */
4559 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
4562 op
= MASK_OP_MAJOR(ctx
->opcode
);
4563 rs
= (ctx
->opcode
>> 21) & 0x1f;
4564 rt
= (ctx
->opcode
>> 16) & 0x1f;
4565 rd
= (ctx
->opcode
>> 11) & 0x1f;
4566 sa
= (ctx
->opcode
>> 6) & 0x1f;
4567 imm
= (int16_t)ctx
->opcode
;
4570 op1
= MASK_SPECIAL(ctx
->opcode
);
4572 case OPC_SLL
: /* Arithmetic with immediate */
4573 case OPC_SRL
... OPC_SRA
:
4574 gen_arith_imm(ctx
, op1
, rd
, rt
, sa
);
4576 case OPC_SLLV
: /* Arithmetic */
4577 case OPC_SRLV
... OPC_SRAV
:
4578 case OPC_MOVZ
... OPC_MOVN
:
4579 case OPC_ADD
... OPC_NOR
:
4580 case OPC_SLT
... OPC_SLTU
:
4581 gen_arith(ctx
, op1
, rd
, rs
, rt
);
4583 case OPC_MULT
... OPC_DIVU
:
4584 gen_muldiv(ctx
, op1
, rs
, rt
);
4586 case OPC_JR
... OPC_JALR
:
4587 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
4589 case OPC_TGE
... OPC_TEQ
: /* Traps */
4591 gen_trap(ctx
, op1
, rs
, rt
, -1);
4593 case OPC_MFHI
: /* Move from HI/LO */
4595 gen_HILO(ctx
, op1
, rd
);
4598 case OPC_MTLO
: /* Move to HI/LO */
4599 gen_HILO(ctx
, op1
, rs
);
4601 case OPC_PMON
: /* Pmon entry point */
4605 generate_exception(ctx
, EXCP_SYSCALL
);
4606 ctx
->bstate
= BS_EXCP
;
4609 generate_exception(ctx
, EXCP_BREAK
);
4611 case OPC_SPIM
: /* SPIM ? */
4612 /* Implemented as RI exception for now. */
4613 MIPS_INVAL("spim (unofficial)");
4614 generate_exception(ctx
, EXCP_RI
);
4617 /* Treat as a noop. */
4621 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
4622 gen_op_cp1_enabled();
4623 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
4624 (ctx
->opcode
>> 16) & 1);
4626 generate_exception(ctx
, EXCP_RI
);
4630 #ifdef MIPS_HAS_MIPS64
4631 /* MIPS64 specific opcodes */
4633 case OPC_DSRL
... OPC_DSRA
:
4635 case OPC_DSRL32
... OPC_DSRA32
:
4636 gen_arith_imm(ctx
, op1
, rd
, rt
, sa
);
4639 case OPC_DSRLV
... OPC_DSRAV
:
4640 case OPC_DADD
... OPC_DSUBU
:
4641 gen_arith(ctx
, op1
, rd
, rs
, rt
);
4643 case OPC_DMULT
... OPC_DDIVU
:
4644 gen_muldiv(ctx
, op1
, rs
, rt
);
4647 default: /* Invalid */
4648 MIPS_INVAL("special");
4649 generate_exception(ctx
, EXCP_RI
);
4654 op1
= MASK_SPECIAL2(ctx
->opcode
);
4656 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
4657 case OPC_MSUB
... OPC_MSUBU
:
4658 gen_muldiv(ctx
, op1
, rs
, rt
);
4661 gen_arith(ctx
, op1
, rd
, rs
, rt
);
4663 case OPC_CLZ
... OPC_CLO
:
4664 gen_cl(ctx
, op1
, rd
, rs
);
4667 /* XXX: not clear which exception should be raised
4668 * when in debug mode...
4670 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
4671 generate_exception(ctx
, EXCP_DBp
);
4673 generate_exception(ctx
, EXCP_DBp
);
4675 /* Treat as a noop */
4677 #ifdef MIPS_HAS_MIPS64
4678 case OPC_DCLZ
... OPC_DCLO
:
4679 gen_cl(ctx
, op1
, rd
, rs
);
4682 default: /* Invalid */
4683 MIPS_INVAL("special2");
4684 generate_exception(ctx
, EXCP_RI
);
4689 op1
= MASK_SPECIAL3(ctx
->opcode
);
4693 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
4696 op2
= MASK_BSHFL(ctx
->opcode
);
4699 GEN_LOAD_REG_TN(T1
, rt
);
4703 GEN_LOAD_REG_TN(T1
, rt
);
4707 GEN_LOAD_REG_TN(T1
, rt
);
4710 default: /* Invalid */
4711 MIPS_INVAL("bshfl");
4712 generate_exception(ctx
, EXCP_RI
);
4715 GEN_STORE_TN_REG(rd
, T0
);
4720 gen_op_rdhwr_cpunum();
4723 gen_op_rdhwr_synci_step();
4729 gen_op_rdhwr_ccres();
4731 #if defined (CONFIG_USER_ONLY)
4733 gen_op_tls_value ();
4734 GEN_STORE_TN_REG(rt
, T0
);
4737 default: /* Invalid */
4738 MIPS_INVAL("rdhwr");
4739 generate_exception(ctx
, EXCP_RI
);
4742 GEN_STORE_TN_REG(rt
, T0
);
4744 #ifdef MIPS_HAS_MIPS64
4745 case OPC_DEXTM
... OPC_DEXT
:
4746 case OPC_DINSM
... OPC_DINS
:
4747 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
4750 op2
= MASK_DBSHFL(ctx
->opcode
);
4753 GEN_LOAD_REG_TN(T1
, rt
);
4757 GEN_LOAD_REG_TN(T1
, rt
);
4760 default: /* Invalid */
4761 MIPS_INVAL("dbshfl");
4762 generate_exception(ctx
, EXCP_RI
);
4765 GEN_STORE_TN_REG(rd
, T0
);
4767 default: /* Invalid */
4768 MIPS_INVAL("special3");
4769 generate_exception(ctx
, EXCP_RI
);
4774 op1
= MASK_REGIMM(ctx
->opcode
);
4776 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
4777 case OPC_BLTZAL
... OPC_BGEZALL
:
4778 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
4780 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
4782 gen_trap(ctx
, op1
, rs
, -1, imm
);
4787 default: /* Invalid */
4788 MIPS_INVAL("REGIMM");
4789 generate_exception(ctx
, EXCP_RI
);
4794 op1
= MASK_CP0(ctx
->opcode
);
4798 #ifdef MIPS_HAS_MIPS64
4802 gen_cp0(ctx
, op1
, rt
, rd
);
4804 case OPC_C0_FIRST
... OPC_C0_LAST
:
4805 gen_cp0(ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
4808 op2
= MASK_MFMC0(ctx
->opcode
);
4812 /* Stop translation as we may have switched the execution mode */
4813 ctx
->bstate
= BS_STOP
;
4817 /* Stop translation as we may have switched the execution mode */
4818 ctx
->bstate
= BS_STOP
;
4820 default: /* Invalid */
4821 MIPS_INVAL("MFMC0");
4822 generate_exception(ctx
, EXCP_RI
);
4825 GEN_STORE_TN_REG(rt
, T0
);
4827 /* Shadow registers (not implemented). */
4831 generate_exception(ctx
, EXCP_RI
);
4835 case OPC_ADDI
... OPC_LUI
: /* Arithmetic with immediate opcode */
4836 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
4838 case OPC_J
... OPC_JAL
: /* Jump */
4839 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
4840 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
4842 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
4843 case OPC_BEQL
... OPC_BGTZL
:
4844 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
4846 case OPC_LB
... OPC_LWR
: /* Load and stores */
4847 case OPC_SB
... OPC_SW
:
4851 gen_ldst(ctx
, op
, rt
, rs
, imm
);
4854 /* Treat as a noop */
4857 /* Treat as a noop */
4860 /* Floating point. */
4865 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
4866 save_cpu_state(ctx
, 1);
4867 gen_op_cp1_enabled();
4868 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
4870 generate_exception_err(ctx
, EXCP_CpU
, 1);
4875 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
4876 save_cpu_state(ctx
, 1);
4877 gen_op_cp1_enabled();
4878 op1
= MASK_CP1(ctx
->opcode
);
4884 #ifdef MIPS_HAS_MIPS64
4888 gen_cp1(ctx
, op1
, rt
, rd
);
4891 gen_compute_branch1(ctx
, MASK_CP1_BCOND(ctx
->opcode
), imm
<< 2);
4897 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
);
4900 generate_exception_err(ctx
, EXCP_RI
, 1);
4904 generate_exception_err(ctx
, EXCP_CpU
, 1);
4914 /* COP2: Not implemented. */
4915 generate_exception_err(ctx
, EXCP_CpU
, 2);
4919 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
4920 gen_op_cp1_enabled();
4921 op1
= MASK_CP3(ctx
->opcode
);
4923 /* Not implemented */
4925 generate_exception_err(ctx
, EXCP_RI
, 1);
4929 generate_exception(ctx
, EXCP_RI
);
4933 #ifdef MIPS_HAS_MIPS64
4934 /* MIPS64 opcodes */
4936 case OPC_LDL
... OPC_LDR
:
4937 case OPC_SDL
... OPC_SDR
:
4942 gen_ldst(ctx
, op
, rt
, rs
, imm
);
4944 case OPC_DADDI
... OPC_DADDIU
:
4945 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
4948 #ifdef MIPS_HAS_MIPS16
4950 /* MIPS16: Not implemented. */
4952 #ifdef MIPS_HAS_MDMX
4954 /* MDMX: Not implemented. */
4956 default: /* Invalid */
4958 generate_exception(ctx
, EXCP_RI
);
4961 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
4962 int hflags
= ctx
->hflags
;
4963 /* Branches completion */
4964 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
4965 ctx
->bstate
= BS_BRANCH
;
4966 save_cpu_state(ctx
, 0);
4967 switch (hflags
& MIPS_HFLAG_BMASK
) {
4969 /* unconditional branch */
4970 MIPS_DEBUG("unconditional branch");
4971 gen_goto_tb(ctx
, 0, ctx
->btarget
);
4974 /* blikely taken case */
4975 MIPS_DEBUG("blikely branch taken");
4976 gen_goto_tb(ctx
, 0, ctx
->btarget
);
4979 /* Conditional branch */
4980 MIPS_DEBUG("conditional branch");
4983 l1
= gen_new_label();
4985 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
4987 gen_goto_tb(ctx
, 0, ctx
->btarget
);
4991 /* unconditional branch to register */
4992 MIPS_DEBUG("branch to register");
4996 MIPS_DEBUG("unknown branch");
5002 int gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
5005 DisasContext ctx
, *ctxp
= &ctx
;
5006 target_ulong pc_start
;
5007 uint16_t *gen_opc_end
;
5010 if (search_pc
&& loglevel
)
5011 fprintf (logfile
, "search pc %d\n", search_pc
);
5014 gen_opc_ptr
= gen_opc_buf
;
5015 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
5016 gen_opparam_ptr
= gen_opparam_buf
;
5021 ctx
.bstate
= BS_NONE
;
5022 /* Restore delay slot state from the tb context. */
5023 ctx
.hflags
= tb
->flags
;
5024 ctx
.saved_hflags
= ctx
.hflags
;
5025 if (ctx
.hflags
& MIPS_HFLAG_BR
) {
5026 gen_op_restore_breg_target();
5027 } else if (ctx
.hflags
& MIPS_HFLAG_B
) {
5028 ctx
.btarget
= env
->btarget
;
5029 } else if (ctx
.hflags
& MIPS_HFLAG_BMASK
) {
5030 /* If we are in the delay slot of a conditional branch,
5031 * restore the branch condition from env->bcond to T2
5033 ctx
.btarget
= env
->btarget
;
5034 gen_op_restore_bcond();
5036 #if defined(CONFIG_USER_ONLY)
5039 ctx
.mem_idx
= !((ctx
.hflags
& MIPS_HFLAG_MODE
) == MIPS_HFLAG_UM
);
5041 ctx
.CP0_Status
= env
->CP0_Status
;
5043 if (loglevel
& CPU_LOG_TB_CPU
) {
5044 fprintf(logfile
, "------------------------------------------------\n");
5045 /* FIXME: This may print out stale hflags from env... */
5046 cpu_dump_state(env
, logfile
, fprintf
, 0);
5049 #if defined MIPS_DEBUG_DISAS
5050 if (loglevel
& CPU_LOG_TB_IN_ASM
)
5051 fprintf(logfile
, "\ntb %p super %d cond %04x\n",
5052 tb
, ctx
.mem_idx
, ctx
.hflags
);
5054 while (ctx
.bstate
== BS_NONE
&& gen_opc_ptr
< gen_opc_end
) {
5055 if (env
->nb_breakpoints
> 0) {
5056 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
5057 if (env
->breakpoints
[j
] == ctx
.pc
) {
5058 save_cpu_state(ctxp
, 1);
5059 ctx
.bstate
= BS_BRANCH
;
5061 goto done_generating
;
5067 j
= gen_opc_ptr
- gen_opc_buf
;
5071 gen_opc_instr_start
[lj
++] = 0;
5073 gen_opc_pc
[lj
] = ctx
.pc
;
5074 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
5075 gen_opc_instr_start
[lj
] = 1;
5077 ctx
.opcode
= ldl_code(ctx
.pc
);
5078 decode_opc(env
, &ctx
);
5081 if (env
->singlestep_enabled
)
5084 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
5087 #if defined (MIPS_SINGLE_STEP)
5091 if (env
->singlestep_enabled
) {
5092 save_cpu_state(ctxp
, ctx
.bstate
== BS_NONE
);
5094 goto done_generating
;
5096 else if (ctx
.bstate
!= BS_BRANCH
&& ctx
.bstate
!= BS_EXCP
) {
5097 save_cpu_state(ctxp
, 0);
5098 gen_goto_tb(&ctx
, 0, ctx
.pc
);
5101 /* Generate the return instruction */
5104 *gen_opc_ptr
= INDEX_op_end
;
5106 j
= gen_opc_ptr
- gen_opc_buf
;
5109 gen_opc_instr_start
[lj
++] = 0;
5112 tb
->size
= ctx
.pc
- pc_start
;
5115 #if defined MIPS_DEBUG_DISAS
5116 if (loglevel
& CPU_LOG_TB_IN_ASM
)
5117 fprintf(logfile
, "\n");
5119 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
5120 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
5121 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
5122 fprintf(logfile
, "\n");
5124 if (loglevel
& CPU_LOG_TB_OP
) {
5125 fprintf(logfile
, "OP:\n");
5126 dump_ops(gen_opc_buf
, gen_opparam_buf
);
5127 fprintf(logfile
, "\n");
5129 if (loglevel
& CPU_LOG_TB_CPU
) {
5130 fprintf(logfile
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
5137 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
5139 return gen_intermediate_code_internal(env
, tb
, 0);
5142 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
5144 return gen_intermediate_code_internal(env
, tb
, 1);
5147 void fpu_dump_state(CPUState
*env
, FILE *f
,
5148 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
5153 # define printfpr(fp) do { \
5154 fpu_fprintf(f, "w:%08x d:%08lx%08lx fd:%g fs:%g\n", \
5155 (fp)->w[FP_ENDIAN_IDX], (fp)->w[0], (fp)->w[1], (fp)->fd, (fp)->fs[FP_ENDIAN_IDX]); \
5158 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d\n",
5159 env
->fcr0
, env
->fcr31
,
5160 (env
->CP0_Status
& (1 << CP0St_FR
)) != 0);
5161 fpu_fprintf(f
, "FT0: "); printfpr(&env
->ft0
);
5162 fpu_fprintf(f
, "FT1: "); printfpr(&env
->ft1
);
5163 fpu_fprintf(f
, "FT2: "); printfpr(&env
->ft2
);
5164 for(i
= 0; i
< 32; i
+= 2) {
5165 fpu_fprintf(f
, "%s: ", fregnames
[i
]);
5166 printfpr(FPR(env
, i
));
5172 void dump_fpu (CPUState
*env
)
5175 fprintf(logfile
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
5176 env
->PC
, env
->HI
, env
->LO
, env
->hflags
, env
->btarget
, env
->bcond
);
5177 fpu_dump_state(env
, logfile
, fprintf
, 0);
5181 #if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
5182 /* Debug help: The architecture requires 32bit code to maintain proper
5183 sign-extened values on 64bit machines. */
5185 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
5187 void cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
5188 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
5193 if (!SIGN_EXT_P(env
->PC
))
5194 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->PC
);
5195 if (!SIGN_EXT_P(env
->HI
))
5196 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->HI
);
5197 if (!SIGN_EXT_P(env
->LO
))
5198 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->LO
);
5199 if (!SIGN_EXT_P(env
->btarget
))
5200 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
5202 for (i
= 0; i
< 32; i
++) {
5203 if (!SIGN_EXT_P(env
->gpr
[i
]))
5204 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->gpr
[i
]);
5207 if (!SIGN_EXT_P(env
->CP0_EPC
))
5208 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
5209 if (!SIGN_EXT_P(env
->CP0_LLAddr
))
5210 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->CP0_LLAddr
);
5214 void cpu_dump_state (CPUState
*env
, FILE *f
,
5215 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
5221 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
5222 env
->PC
, env
->HI
, env
->LO
, env
->hflags
, env
->btarget
, env
->bcond
);
5223 for (i
= 0; i
< 32; i
++) {
5225 cpu_fprintf(f
, "GPR%02d:", i
);
5226 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->gpr
[i
]);
5228 cpu_fprintf(f
, "\n");
5231 c0_status
= env
->CP0_Status
;
5232 if (env
->hflags
& MIPS_HFLAG_UM
)
5233 c0_status
|= (1 << CP0St_UM
);
5234 if (env
->hflags
& MIPS_HFLAG_ERL
)
5235 c0_status
|= (1 << CP0St_ERL
);
5236 if (env
->hflags
& MIPS_HFLAG_EXL
)
5237 c0_status
|= (1 << CP0St_EXL
);
5239 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
5240 c0_status
, env
->CP0_Cause
, env
->CP0_EPC
);
5241 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
5242 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
5243 if (c0_status
& (1 << CP0St_CU1
))
5244 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
5245 #if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
5246 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
5250 CPUMIPSState
*cpu_mips_init (void)
5254 env
= qemu_mallocz(sizeof(CPUMIPSState
));
5262 void cpu_reset (CPUMIPSState
*env
)
5264 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
5269 #if !defined(CONFIG_USER_ONLY)
5270 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
5271 /* If the exception was raised from a delay slot,
5272 * come back to the jump. */
5273 env
->CP0_ErrorEPC
= env
->PC
- 4;
5274 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
5276 env
->CP0_ErrorEPC
= env
->PC
;
5278 env
->PC
= (int32_t)0xBFC00000;
5279 #if defined (MIPS_USES_R4K_TLB)
5280 env
->CP0_Random
= MIPS_TLB_NB
- 1;
5281 env
->tlb_in_use
= MIPS_TLB_NB
;
5284 /* SMP not implemented */
5285 env
->CP0_EBase
= 0x80000000;
5286 env
->CP0_Config2
= MIPS_CONFIG2
;
5287 env
->CP0_Config3
= MIPS_CONFIG3
;
5288 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
5289 env
->CP0_WatchLo
= 0;
5290 env
->hflags
= MIPS_HFLAG_ERL
;
5291 /* Count register increments in debug mode, EJTAG version 1 */
5292 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
5294 env
->exception_index
= EXCP_NONE
;
5295 #if defined(CONFIG_USER_ONLY)
5296 env
->hflags
|= MIPS_HFLAG_UM
;
5297 env
->user_mode_only
= 1;
5299 env
->fcr0
= MIPS_FCR0
;
5300 /* XXX some guesswork here, values are CPU specific */
5301 env
->SYNCI_Step
= 16;
5305 #include "translate_init.c"