target-mips/translate_init.c

   1 /*
   2  *  MIPS emulation for qemu: CPU initialisation routines.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *  Copyright (c) 2007 Herve Poussineau
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /* CPU / CPU family specific config register values. */
  23
  24 /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
  25    uncached coherency */
  26 #define MIPS_CONFIG0                                              \
  27   ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) |      \
  28    (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) |    \
  29    (0x2 << CP0C0_K0))
  30
  31 /* Have config2, no coprocessor2 attached, no MDMX support attached,
  32    no performance counters, watch registers present,
  33    no code compression, EJTAG present, no FPU */
  34 #define MIPS_CONFIG1                                              \
  35 ((1 << CP0C1_M) |                                                 \
  36  (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
  37  (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |            \
  38  (0 << CP0C1_FP))
  39
  40 /* Have config3, no tertiary/secondary caches implemented */
  41 #define MIPS_CONFIG2                                              \
  42 ((1 << CP0C2_M))
  43
  44 /* No config4, no DSP ASE, no large physaddr,
  45    no external interrupt controller, no vectored interupts,
  46    no 1kb pages, no SmartMIPS ASE, no trace logic */
  47 #define MIPS_CONFIG3                                              \
  48 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
  49  (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
  50  (0 << CP0C3_SM) | (0 << CP0C3_TL))
  51
  52 /* Define a implementation number of 1.
  53    Define a major version 1, minor version 0. */
  54 #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
  55
  56 struct mips_def_t {
  57     const unsigned char *name;
  58     int32_t CP0_PRid;
  59     int32_t CP0_Config0;
  60     int32_t CP0_Config1;
  61     int32_t CP0_Config2;
  62     int32_t CP0_Config3;
  63     int32_t CP0_Config6;
  64     int32_t CP0_Config7;
  65     int32_t SYNCI_Step;
  66     int32_t CCRes;
  67     int32_t CP0_Status_rw_bitmask;
  68     int32_t CP0_TCStatus_rw_bitmask;
  69     int32_t CP0_SRSCtl;
  70     int32_t CP1_fcr0;
  71     int32_t SEGBITS;
  72     int32_t CP0_SRSConf0_rw_bitmask;
  73     int32_t CP0_SRSConf0;
  74     int32_t CP0_SRSConf1_rw_bitmask;
  75     int32_t CP0_SRSConf1;
  76     int32_t CP0_SRSConf2_rw_bitmask;
  77     int32_t CP0_SRSConf2;
  78     int32_t CP0_SRSConf3_rw_bitmask;
  79     int32_t CP0_SRSConf3;
  80     int32_t CP0_SRSConf4_rw_bitmask;
  81     int32_t CP0_SRSConf4;
  82     int insn_flags;
  83 };
  84
  85 /*****************************************************************************/
  86 /* MIPS CPU definitions */
  87 static mips_def_t mips_defs[] =
  88 {
  89     {
  90         .name = "4Kc",
  91         .CP0_PRid = 0x00018000,
  92         .CP0_Config0 = MIPS_CONFIG0,
  93         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
  94                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  95                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
  96         .CP0_Config2 = MIPS_CONFIG2,
  97         .CP0_Config3 = MIPS_CONFIG3,
  98         .SYNCI_Step = 32,
  99         .CCRes = 2,
 100         .CP0_Status_rw_bitmask = 0x1278FF17,
 101         .insn_flags = CPU_MIPS32 | ASE_MIPS16,
 102     },
 103     {
 104         .name = "4KEcR1",
 105         .CP0_PRid = 0x00018400,
 106         .CP0_Config0 = MIPS_CONFIG0,
 107         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 108                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 109                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 110         .CP0_Config2 = MIPS_CONFIG2,
 111         .CP0_Config3 = MIPS_CONFIG3,
 112         .SYNCI_Step = 32,
 113         .CCRes = 2,
 114         .CP0_Status_rw_bitmask = 0x1278FF17,
 115         .insn_flags = CPU_MIPS32 | ASE_MIPS16,
 116     },
 117     {
 118         .name = "4KEc",
 119         .CP0_PRid = 0x00019000,
 120         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
 121         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 122                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 123                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 124         .CP0_Config2 = MIPS_CONFIG2,
 125         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 126         .SYNCI_Step = 32,
 127         .CCRes = 2,
 128         .CP0_Status_rw_bitmask = 0x1278FF17,
 129         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 130     },
 131     {
 132         .name = "24Kc",
 133         .CP0_PRid = 0x00019300,
 134         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
 135         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 136                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 137                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 138         .CP0_Config2 = MIPS_CONFIG2,
 139         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 140         .SYNCI_Step = 32,
 141         .CCRes = 2,
 142         /* No DSP implemented. */
 143         .CP0_Status_rw_bitmask = 0x1278FF1F,
 144         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
 145     },
 146     {
 147         .name = "24Kf",
 148         .CP0_PRid = 0x00019300,
 149         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
 150         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 151                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 152                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 153         .CP0_Config2 = MIPS_CONFIG2,
 154         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 155         .SYNCI_Step = 32,
 156         .CCRes = 2,
 157         /* No DSP implemented. */
 158         .CP0_Status_rw_bitmask = 0x3678FF1F,
 159         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 160                     (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
 161         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
 162     },
 163     {
 164         .name = "34Kf",
 165         .CP0_PRid = 0x00019500,
 166         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
 167         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 168                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 169                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 170         .CP0_Config2 = MIPS_CONFIG2,
 171         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT),
 172         .SYNCI_Step = 32,
 173         .CCRes = 2,
 174         /* No DSP implemented. */
 175         .CP0_Status_rw_bitmask = 0x3678FF1F,
 176         /* No DSP implemented. */
 177         .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
 178                     (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
 179                     (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
 180                     (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
 181                     (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
 182                     (0xff << CP0TCSt_TASID),
 183         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 184                     (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
 185         .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
 186         .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
 187         .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
 188                     (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
 189         .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
 190         .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
 191                     (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
 192         .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
 193         .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
 194                     (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
 195         .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
 196         .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
 197                     (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
 198         .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
 199         .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
 200                     (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
 201         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
 202     },
 203 #if defined(TARGET_MIPS64)
 204     {
 205         .name = "R4000",
 206         .CP0_PRid = 0x00000400,
 207         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
 208         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
 209                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 210                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 211         .CP0_Config2 = MIPS_CONFIG2,
 212         .CP0_Config3 = MIPS_CONFIG3,
 213         .SYNCI_Step = 16,
 214         .CCRes = 2,
 215         .CP0_Status_rw_bitmask = 0x3678FFFF,
 216         /* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
 217         .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
 218         .SEGBITS = 40,
 219         .insn_flags = CPU_MIPS3,
 220     },
 221     {
 222         .name = "5Kc",
 223         .CP0_PRid = 0x00018100,
 224         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
 225         .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
 226                     (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 227                     (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 228                     (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 229         .CP0_Config2 = MIPS_CONFIG2,
 230         .CP0_Config3 = MIPS_CONFIG3,
 231         .SYNCI_Step = 32,
 232         .CCRes = 2,
 233         .CP0_Status_rw_bitmask = 0x32F8FFFF,
 234         .SEGBITS = 42,
 235         .insn_flags = CPU_MIPS64,
 236     },
 237     {
 238         .name = "5Kf",
 239         .CP0_PRid = 0x00018100,
 240         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
 241         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
 242                     (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 243                     (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 244                     (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 245         .CP0_Config2 = MIPS_CONFIG2,
 246         .CP0_Config3 = MIPS_CONFIG3,
 247         .SYNCI_Step = 32,
 248         .CCRes = 2,
 249         .CP0_Status_rw_bitmask = 0x36F8FFFF,
 250         /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
 251         .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
 252                     (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
 253         .SEGBITS = 42,
 254         .insn_flags = CPU_MIPS64,
 255     },
 256     {
 257         .name = "20Kc",
 258         /* We emulate a later version of the 20Kc, earlier ones had a broken
 259            WAIT instruction. */
 260         .CP0_PRid = 0x000182a0,
 261         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (1 << CP0C0_VI),
 262         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
 263                     (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 264                     (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 265                     (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 266         .CP0_Config2 = MIPS_CONFIG2,
 267         .CP0_Config3 = MIPS_CONFIG3,
 268         .SYNCI_Step = 32,
 269         .CCRes = 2,
 270         .CP0_Status_rw_bitmask = 0x36FBFFFF,
 271         /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
 272         .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
 273                     (1 << FCR0_D) | (1 << FCR0_S) |
 274                     (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
 275         .SEGBITS = 40,
 276         .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
 277     },
 278     {
 279         /* A generic CPU providing MIPS64 Release 2 features.
 280            FIXME: Eventually this should be replaced by a real CPU model. */
 281         .name = "MIPS64R2-generic",
 282         .CP0_PRid = 0x00000000,
 283         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (0x1 << CP0C0_AR),
 284         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
 285                     (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 286                     (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 287                     (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 288         .CP0_Config2 = MIPS_CONFIG2,
 289         .CP0_Config3 = MIPS_CONFIG3,
 290         .SYNCI_Step = 32,
 291         .CCRes = 2,
 292         .CP0_Status_rw_bitmask = 0x36FBFFFF,
 293         .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_L) |
 294                     (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
 295                     (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
 296         .SEGBITS = 40,
 297         .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
 298     },
 299 #endif
 300 };
 301
 302 static const mips_def_t *cpu_mips_find_by_name (const unsigned char *name)
 303 {
 304     int i;
 305
 306     for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
 307         if (strcasecmp(name, mips_defs[i].name) == 0) {
 308             return &mips_defs[i];
 309         }
 310     }
 311     return NULL;
 312 }
 313
 314 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
 315 {
 316     int i;
 317
 318     for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
 319         (*cpu_fprintf)(f, "MIPS '%s'\n",
 320                        mips_defs[i].name);
 321     }
 322 }
 323
 324 #ifndef CONFIG_USER_ONLY
 325 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 326 {
 327     env->tlb->nb_tlb = 1;
 328     env->tlb->map_address = &no_mmu_map_address;
 329 }
 330
 331 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 332 {
 333     env->tlb->nb_tlb = 1;
 334     env->tlb->map_address = &fixed_mmu_map_address;
 335 }
 336
 337 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 338 {
 339     env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
 340     env->tlb->map_address = &r4k_map_address;
 341     env->tlb->do_tlbwi = r4k_do_tlbwi;
 342     env->tlb->do_tlbwr = r4k_do_tlbwr;
 343     env->tlb->do_tlbp = r4k_do_tlbp;
 344     env->tlb->do_tlbr = r4k_do_tlbr;
 345 }
 346
 347 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
 348 {
 349     env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
 350
 351     /* There are more full-featured MMU variants in older MIPS CPUs,
 352        R3000, R6000 and R8000 come to mind. If we ever support them,
 353        this check will need to look up a different place than those
 354        newfangled config registers. */
 355     switch ((env->CP0_Config0 >> CP0C0_MT) & 3) {
 356         case 0:
 357             no_mmu_init(env, def);
 358             break;
 359         case 1:
 360             r4k_mmu_init(env, def);
 361             break;
 362         case 3:
 363             fixed_mmu_init(env, def);
 364             break;
 365         default:
 366             cpu_abort(env, "MMU type not supported\n");
 367     }
 368     env->CP0_Random = env->tlb->nb_tlb - 1;
 369     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 370 }
 371 #endif /* CONFIG_USER_ONLY */
 372
 373 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
 374 {
 375     env->fpu = qemu_mallocz(sizeof(CPUMIPSFPUContext));
 376
 377     env->fpu->fcr0 = def->CP1_fcr0;
 378 #ifdef CONFIG_USER_ONLY
 379     if (env->CP0_Config1 & (1 << CP0C1_FP))
 380         env->hflags |= MIPS_HFLAG_FPU;
 381     if (env->fpu->fcr0 & (1 << FCR0_F64))
 382         env->hflags |= MIPS_HFLAG_F64;
 383 #endif
 384 }
 385
 386 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
 387 {
 388     env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
 389
 390     /* MVPConf1 implemented, TLB sharable, no gating storage support,
 391        programmable cache partitioning implemented, number of allocatable
 392        and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
 393        implemented, 5 TCs implemented. */
 394     env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
 395                              (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
 396 #ifndef CONFIG_USER_ONLY
 397                              /* Usermode has no TLB support */
 398                              (env->tlb->nb_tlb << CP0MVPC0_PTLBE) |
 399 #endif
 400 // TODO: actually do 2 VPEs.
 401 //                             (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
 402 //                             (0x04 << CP0MVPC0_PTC);
 403                              (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
 404                              (0x04 << CP0MVPC0_PTC);
 405     /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
 406        no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
 407     env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
 408                              (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
 409                              (0x1 << CP0MVPC1_PCP1);
 410 }
 411
 412 static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
 413 {
 414     env->CP0_PRid = def->CP0_PRid;
 415     env->CP0_Config0 = def->CP0_Config0;
 416 #ifdef TARGET_WORDS_BIGENDIAN
 417     env->CP0_Config0 |= (1 << CP0C0_BE);
 418 #endif
 419     env->CP0_Config1 = def->CP0_Config1;
 420     env->CP0_Config2 = def->CP0_Config2;
 421     env->CP0_Config3 = def->CP0_Config3;
 422     env->CP0_Config6 = def->CP0_Config6;
 423     env->CP0_Config7 = def->CP0_Config7;
 424     env->SYNCI_Step = def->SYNCI_Step;
 425     env->CCRes = def->CCRes;
 426     env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask;
 427     env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask;
 428     env->CP0_SRSCtl = def->CP0_SRSCtl;
 429 #if defined(TARGET_MIPS64)
 430     if (def->insn_flags & ISA_MIPS3)
 431     {
 432         env->hflags |= MIPS_HFLAG_64;
 433         env->SEGBITS = def->SEGBITS;
 434         env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1);
 435     } else {
 436         env->SEGBITS = 32;
 437         env->SEGMask = 0xFFFFFFFF;
 438     }
 439 #endif
 440     env->CP0_SRSConf0_rw_bitmask = def->CP0_SRSConf0_rw_bitmask;
 441     env->CP0_SRSConf0 = def->CP0_SRSConf0;
 442     env->CP0_SRSConf1_rw_bitmask = def->CP0_SRSConf1_rw_bitmask;
 443     env->CP0_SRSConf1 = def->CP0_SRSConf1;
 444     env->CP0_SRSConf2_rw_bitmask = def->CP0_SRSConf2_rw_bitmask;
 445     env->CP0_SRSConf2 = def->CP0_SRSConf2;
 446     env->CP0_SRSConf3_rw_bitmask = def->CP0_SRSConf3_rw_bitmask;
 447     env->CP0_SRSConf3 = def->CP0_SRSConf3;
 448     env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask;
 449     env->CP0_SRSConf4 = def->CP0_SRSConf4;
 450     env->insn_flags = def->insn_flags;
 451
 452 #ifndef CONFIG_USER_ONLY
 453     mmu_init(env, def);
 454 #endif
 455     fpu_init(env, def);
 456     mvp_init(env, def);
 457     return 0;
 458 }