target-openrisc/cpu.h

   1 /*
   2  * OpenRISC virtual CPU header.
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef CPU_OPENRISC_H
  21 #define CPU_OPENRISC_H
  22
  23 #define TARGET_LONG_BITS 32
  24 #define ELF_MACHINE    EM_OPENRISC
  25
  26 #define CPUArchState struct CPUOpenRISCState
  27
  28 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl.  */
  29 struct OpenRISCCPU;
  30
  31 #include "config.h"
  32 #include "qemu-common.h"
  33 #include "cpu-defs.h"
  34 #include "softfloat.h"
  35 #include "qemu/cpu.h"
  36 #include "error.h"
  37
  38 #define TYPE_OPENRISC_CPU "or32-cpu"
  39
  40 #define OPENRISC_CPU_CLASS(klass) \
  41     OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
  42 #define OPENRISC_CPU(obj) \
  43     OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
  44 #define OPENRISC_CPU_GET_CLASS(obj) \
  45     OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
  46
  47 /**
  48  * OpenRISCCPUClass:
  49  * @parent_reset: The parent class' reset handler.
  50  *
  51  * A OpenRISC CPU model.
  52  */
  53 typedef struct OpenRISCCPUClass {
  54     /*< private >*/
  55     CPUClass parent_class;
  56     /*< public >*/
  57
  58     void (*parent_reset)(CPUState *cpu);
  59 } OpenRISCCPUClass;
  60
  61 #define NB_MMU_MODES    3
  62
  63 enum {
  64     MMU_NOMMU_IDX = 0,
  65     MMU_SUPERVISOR_IDX = 1,
  66     MMU_USER_IDX = 2,
  67 };
  68
  69 #define TARGET_PAGE_BITS 13
  70
  71 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  73
  74 #define SET_FP_CAUSE(reg, v)    do {\
  75                                     (reg) = ((reg) & ~(0x3f << 12)) | \
  76                                             ((v & 0x3f) << 12);\
  77                                 } while (0)
  78 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  79 #define UPDATE_FP_FLAGS(reg, v)   do {\
  80                                       (reg) |= ((v & 0x1f) << 2);\
  81                                   } while (0)
  82
  83 /* Internal flags, delay slot flag */
  84 #define D_FLAG    1
  85
  86 /* Interrupt */
  87 #define NR_IRQS  32
  88
  89 /* Registers */
  90 enum {
  91     R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10,
  92     R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,
  93     R21, R22, R23, R24, R25, R26, R27, R28, R29, R30,
  94     R31
  95 };
  96
  97 /* Register aliases */
  98 enum {
  99     R_ZERO = R0,
 100     R_SP = R1,
 101     R_FP = R2,
 102     R_LR = R9,
 103     R_RV = R11,
 104     R_RVH = R12
 105 };
 106
 107 /* Unit presece register */
 108 enum {
 109     UPR_UP = (1 << 0),
 110     UPR_DCP = (1 << 1),
 111     UPR_ICP = (1 << 2),
 112     UPR_DMP = (1 << 3),
 113     UPR_IMP = (1 << 4),
 114     UPR_MP = (1 << 5),
 115     UPR_DUP = (1 << 6),
 116     UPR_PCUR = (1 << 7),
 117     UPR_PMP = (1 << 8),
 118     UPR_PICP = (1 << 9),
 119     UPR_TTP = (1 << 10),
 120     UPR_CUP = (255 << 24),
 121 };
 122
 123 /* CPU configure register */
 124 enum {
 125     CPUCFGR_NSGF = (15 << 0),
 126     CPUCFGR_CGF = (1 << 4),
 127     CPUCFGR_OB32S = (1 << 5),
 128     CPUCFGR_OB64S = (1 << 6),
 129     CPUCFGR_OF32S = (1 << 7),
 130     CPUCFGR_OF64S = (1 << 8),
 131     CPUCFGR_OV64S = (1 << 9),
 132 };
 133
 134 /* DMMU configure register */
 135 enum {
 136     DMMUCFGR_NTW = (3 << 0),
 137     DMMUCFGR_NTS = (7 << 2),
 138     DMMUCFGR_NAE = (7 << 5),
 139     DMMUCFGR_CRI = (1 << 8),
 140     DMMUCFGR_PRI = (1 << 9),
 141     DMMUCFGR_TEIRI = (1 << 10),
 142     DMMUCFGR_HTR = (1 << 11),
 143 };
 144
 145 /* IMMU configure register */
 146 enum {
 147     IMMUCFGR_NTW = (3 << 0),
 148     IMMUCFGR_NTS = (7 << 2),
 149     IMMUCFGR_NAE = (7 << 5),
 150     IMMUCFGR_CRI = (1 << 8),
 151     IMMUCFGR_PRI = (1 << 9),
 152     IMMUCFGR_TEIRI = (1 << 10),
 153     IMMUCFGR_HTR = (1 << 11),
 154 };
 155
 156 /* Float point control status register */
 157 enum {
 158     FPCSR_FPEE = 1,
 159     FPCSR_RM = (3 << 1),
 160     FPCSR_OVF = (1 << 3),
 161     FPCSR_UNF = (1 << 4),
 162     FPCSR_SNF = (1 << 5),
 163     FPCSR_QNF = (1 << 6),
 164     FPCSR_ZF = (1 << 7),
 165     FPCSR_IXF = (1 << 8),
 166     FPCSR_IVF = (1 << 9),
 167     FPCSR_INF = (1 << 10),
 168     FPCSR_DZF = (1 << 11),
 169 };
 170
 171 /* Exceptions indices */
 172 enum {
 173     EXCP_RESET    = 0x1,
 174     EXCP_BUSERR   = 0x2,
 175     EXCP_DPF      = 0x3,
 176     EXCP_IPF      = 0x4,
 177     EXCP_TICK     = 0x5,
 178     EXCP_ALIGN    = 0x6,
 179     EXCP_ILLEGAL  = 0x7,
 180     EXCP_INT      = 0x8,
 181     EXCP_DTLBMISS = 0x9,
 182     EXCP_ITLBMISS = 0xa,
 183     EXCP_RANGE    = 0xb,
 184     EXCP_SYSCALL  = 0xc,
 185     EXCP_FPE      = 0xd,
 186     EXCP_TRAP     = 0xe,
 187     EXCP_NR,
 188 };
 189
 190 /* Supervisor register */
 191 enum {
 192     SR_SM = (1 << 0),
 193     SR_TEE = (1 << 1),
 194     SR_IEE = (1 << 2),
 195     SR_DCE = (1 << 3),
 196     SR_ICE = (1 << 4),
 197     SR_DME = (1 << 5),
 198     SR_IME = (1 << 6),
 199     SR_LEE = (1 << 7),
 200     SR_CE  = (1 << 8),
 201     SR_F   = (1 << 9),
 202     SR_CY  = (1 << 10),
 203     SR_OV  = (1 << 11),
 204     SR_OVE = (1 << 12),
 205     SR_DSX = (1 << 13),
 206     SR_EPH = (1 << 14),
 207     SR_FO  = (1 << 15),
 208     SR_SUMRA = (1 << 16),
 209     SR_SCE = (1 << 17),
 210 };
 211
 212 /* OpenRISC Hardware Capabilities */
 213 enum {
 214     OPENRISC_FEATURE_NSGF = (15 << 0),
 215     OPENRISC_FEATURE_CGF = (1 << 4),
 216     OPENRISC_FEATURE_OB32S = (1 << 5),
 217     OPENRISC_FEATURE_OB64S = (1 << 6),
 218     OPENRISC_FEATURE_OF32S = (1 << 7),
 219     OPENRISC_FEATURE_OF64S = (1 << 8),
 220     OPENRISC_FEATURE_OV64S = (1 << 9),
 221 };
 222
 223 /* Tick Timer Mode Register */
 224 enum {
 225     TTMR_TP = (0xfffffff),
 226     TTMR_IP = (1 << 28),
 227     TTMR_IE = (1 << 29),
 228     TTMR_M  = (3 << 30),
 229 };
 230
 231 /* Timer Mode */
 232 enum {
 233     TIMER_NONE = (0 << 30),
 234     TIMER_INTR = (1 << 30),
 235     TIMER_SHOT = (2 << 30),
 236     TIMER_CONT = (3 << 30),
 237 };
 238
 239 /* TLB size */
 240 enum {
 241     DTLB_WAYS = 1,
 242     DTLB_SIZE = 64,
 243     DTLB_MASK = (DTLB_SIZE-1),
 244     ITLB_WAYS = 1,
 245     ITLB_SIZE = 64,
 246     ITLB_MASK = (ITLB_SIZE-1),
 247 };
 248
 249 /* TLB prot */
 250 enum {
 251     URE = (1 << 6),
 252     UWE = (1 << 7),
 253     SRE = (1 << 8),
 254     SWE = (1 << 9),
 255
 256     SXE = (1 << 6),
 257     UXE = (1 << 7),
 258 };
 259
 260 /* check if tlb available */
 261 enum {
 262     TLBRET_INVALID = -3,
 263     TLBRET_NOMATCH = -2,
 264     TLBRET_BADADDR = -1,
 265     TLBRET_MATCH = 0
 266 };
 267
 268 typedef struct OpenRISCTLBEntry {
 269     uint32_t mr;
 270     uint32_t tr;
 271 } OpenRISCTLBEntry;
 272
 273 #ifndef CONFIG_USER_ONLY
 274 typedef struct CPUOpenRISCTLBContext {
 275     OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
 276     OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
 277
 278     int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
 279                                          target_phys_addr_t *physical,
 280                                          int *prot,
 281                                          target_ulong address, int rw);
 282     int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
 283                                          target_phys_addr_t *physical,
 284                                          int *prot,
 285                                          target_ulong address, int rw);
 286 } CPUOpenRISCTLBContext;
 287 #endif
 288
 289 typedef struct CPUOpenRISCState {
 290     target_ulong gpr[32];     /* General registers */
 291     target_ulong pc;          /* Program counter */
 292     target_ulong npc;         /* Next PC */
 293     target_ulong ppc;         /* Prev PC */
 294     target_ulong jmp_pc;      /* Jump PC */
 295
 296     target_ulong machi;       /* Multiply register MACHI */
 297     target_ulong maclo;       /* Multiply register MACLO */
 298
 299     target_ulong fpmaddhi;    /* Multiply and add float register FPMADDHI */
 300     target_ulong fpmaddlo;    /* Multiply and add float register FPMADDLO */
 301
 302     target_ulong epcr;        /* Exception PC register */
 303     target_ulong eear;        /* Exception EA register */
 304
 305     uint32_t sr;              /* Supervisor register */
 306     uint32_t vr;              /* Version register */
 307     uint32_t upr;             /* Unit presence register */
 308     uint32_t cpucfgr;         /* CPU configure register */
 309     uint32_t dmmucfgr;        /* DMMU configure register */
 310     uint32_t immucfgr;        /* IMMU configure register */
 311     uint32_t esr;             /* Exception supervisor register */
 312     uint32_t fpcsr;           /* Float register */
 313     float_status fp_status;
 314
 315     uint32_t flags;           /* cpu_flags, we only use it for exception
 316                                  in solt so far.  */
 317     uint32_t btaken;          /* the SR_F bit */
 318
 319     CPU_COMMON
 320
 321 #ifndef CONFIG_USER_ONLY
 322     CPUOpenRISCTLBContext * tlb;
 323
 324     struct QEMUTimer *timer;
 325     uint32_t ttmr;          /* Timer tick mode register */
 326     uint32_t ttcr;          /* Timer tick count register */
 327
 328     uint32_t picmr;         /* Interrupt mask register */
 329     uint32_t picsr;         /* Interrupt contrl register*/
 330 #endif
 331     void *irq[32];          /* Interrupt irq input */
 332 } CPUOpenRISCState;
 333
 334 /**
 335  * OpenRISCCPU:
 336  * @env: #CPUOpenRISCState
 337  *
 338  * A OpenRISC CPU.
 339  */
 340 typedef struct OpenRISCCPU {
 341     /*< private >*/
 342     CPUState parent_obj;
 343     /*< public >*/
 344
 345     CPUOpenRISCState env;
 346
 347     uint32_t feature;       /* CPU Capabilities */
 348 } OpenRISCCPU;
 349
 350 static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
 351 {
 352     return OPENRISC_CPU(container_of(env, OpenRISCCPU, env));
 353 }
 354
 355 #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
 356
 357 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
 358 void openrisc_cpu_realize(Object *obj, Error **errp);
 359
 360 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
 361 int cpu_openrisc_exec(CPUOpenRISCState *s);
 362 void do_interrupt(CPUOpenRISCState *env);
 363 void openrisc_translate_init(void);
 364 int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
 365                                   target_ulong address,
 366                                   int rw, int mmu_idx);
 367
 368 #define cpu_list cpu_openrisc_list
 369 #define cpu_exec cpu_openrisc_exec
 370 #define cpu_gen_code cpu_openrisc_gen_code
 371 #define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault
 372
 373 #ifndef CONFIG_USER_ONLY
 374 /* hw/openrisc_pic.c */
 375 void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
 376
 377 /* hw/openrisc_timer.c */
 378 void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
 379 void cpu_openrisc_count_update(OpenRISCCPU *cpu);
 380 void cpu_openrisc_count_start(OpenRISCCPU *cpu);
 381 void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
 382
 383 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
 384 int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
 385                                 target_phys_addr_t *physical,
 386                                 int *prot, target_ulong address, int rw);
 387 int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
 388                                target_phys_addr_t *physical,
 389                                int *prot, target_ulong address, int rw);
 390 int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
 391                                target_phys_addr_t *physical,
 392                                int *prot, target_ulong address, int rw);
 393 #endif
 394
 395 static inline CPUOpenRISCState *cpu_init(const char *cpu_model)
 396 {
 397     OpenRISCCPU *cpu = cpu_openrisc_init(cpu_model);
 398     if (cpu) {
 399         return &cpu->env;
 400     }
 401     return NULL;
 402 }
 403
 404 #include "cpu-all.h"
 405
 406 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
 407                                         target_ulong *pc,
 408                                         target_ulong *cs_base, int *flags)
 409 {
 410     *pc = env->pc;
 411     *cs_base = 0;
 412     /* D_FLAG -- branch instruction exception */
 413     *flags = (env->flags & D_FLAG);
 414 }
 415
 416 static inline int cpu_mmu_index(CPUOpenRISCState *env)
 417 {
 418     if (!(env->sr & SR_IME)) {
 419         return MMU_NOMMU_IDX;
 420     }
 421     return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
 422 }
 423
 424 #define CPU_INTERRUPT_TIMER   CPU_INTERRUPT_TGT_INT_0
 425 static inline bool cpu_has_work(CPUOpenRISCState *env)
 426 {
 427     return env->interrupt_request & (CPU_INTERRUPT_HARD |
 428                                      CPU_INTERRUPT_TIMER);
 429 }
 430
 431 #include "exec-all.h"
 432
 433 static inline target_ulong cpu_get_pc(CPUOpenRISCState *env)
 434 {
 435     return env->pc;
 436 }
 437
 438 static inline void cpu_pc_from_tb(CPUOpenRISCState *env, TranslationBlock *tb)
 439 {
 440     env->pc = tb->pc;
 441 }
 442
 443 #endif /* CPU_OPENRISC_H */