2 * OpenRISC virtual CPU header.
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef CPU_OPENRISC_H
21 #define CPU_OPENRISC_H
23 #define TARGET_LONG_BITS 32
24 #define ELF_MACHINE EM_OPENRISC
26 #define CPUArchState struct CPUOpenRISCState
28 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
32 #include "qemu-common.h"
34 #include "softfloat.h"
38 #define TYPE_OPENRISC_CPU "or32-cpu"
40 #define OPENRISC_CPU_CLASS(klass) \
41 OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
42 #define OPENRISC_CPU(obj) \
43 OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
44 #define OPENRISC_CPU_GET_CLASS(obj) \
45 OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
49 * @parent_reset: The parent class' reset handler.
51 * A OpenRISC CPU model.
53 typedef struct OpenRISCCPUClass
{
55 CPUClass parent_class
;
58 void (*parent_reset
)(CPUState
*cpu
);
61 #define NB_MMU_MODES 3
65 MMU_SUPERVISOR_IDX
= 1,
69 #define TARGET_PAGE_BITS 13
71 #define TARGET_PHYS_ADDR_SPACE_BITS 32
72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
74 #define SET_FP_CAUSE(reg, v) do {\
75 (reg) = ((reg) & ~(0x3f << 12)) | \
78 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
79 #define UPDATE_FP_FLAGS(reg, v) do {\
80 (reg) |= ((v & 0x1f) << 2);\
83 /* Internal flags, delay slot flag */
91 R0
= 0, R1
, R2
, R3
, R4
, R5
, R6
, R7
, R8
, R9
, R10
,
92 R11
, R12
, R13
, R14
, R15
, R16
, R17
, R18
, R19
, R20
,
93 R21
, R22
, R23
, R24
, R25
, R26
, R27
, R28
, R29
, R30
,
97 /* Register aliases */
107 /* Unit presece register */
120 UPR_CUP
= (255 << 24),
123 /* CPU configure register */
125 CPUCFGR_NSGF
= (15 << 0),
126 CPUCFGR_CGF
= (1 << 4),
127 CPUCFGR_OB32S
= (1 << 5),
128 CPUCFGR_OB64S
= (1 << 6),
129 CPUCFGR_OF32S
= (1 << 7),
130 CPUCFGR_OF64S
= (1 << 8),
131 CPUCFGR_OV64S
= (1 << 9),
134 /* DMMU configure register */
136 DMMUCFGR_NTW
= (3 << 0),
137 DMMUCFGR_NTS
= (7 << 2),
138 DMMUCFGR_NAE
= (7 << 5),
139 DMMUCFGR_CRI
= (1 << 8),
140 DMMUCFGR_PRI
= (1 << 9),
141 DMMUCFGR_TEIRI
= (1 << 10),
142 DMMUCFGR_HTR
= (1 << 11),
145 /* IMMU configure register */
147 IMMUCFGR_NTW
= (3 << 0),
148 IMMUCFGR_NTS
= (7 << 2),
149 IMMUCFGR_NAE
= (7 << 5),
150 IMMUCFGR_CRI
= (1 << 8),
151 IMMUCFGR_PRI
= (1 << 9),
152 IMMUCFGR_TEIRI
= (1 << 10),
153 IMMUCFGR_HTR
= (1 << 11),
156 /* Float point control status register */
160 FPCSR_OVF
= (1 << 3),
161 FPCSR_UNF
= (1 << 4),
162 FPCSR_SNF
= (1 << 5),
163 FPCSR_QNF
= (1 << 6),
165 FPCSR_IXF
= (1 << 8),
166 FPCSR_IVF
= (1 << 9),
167 FPCSR_INF
= (1 << 10),
168 FPCSR_DZF
= (1 << 11),
171 /* Exceptions indices */
190 /* Supervisor register */
208 SR_SUMRA
= (1 << 16),
212 /* OpenRISC Hardware Capabilities */
214 OPENRISC_FEATURE_NSGF
= (15 << 0),
215 OPENRISC_FEATURE_CGF
= (1 << 4),
216 OPENRISC_FEATURE_OB32S
= (1 << 5),
217 OPENRISC_FEATURE_OB64S
= (1 << 6),
218 OPENRISC_FEATURE_OF32S
= (1 << 7),
219 OPENRISC_FEATURE_OF64S
= (1 << 8),
220 OPENRISC_FEATURE_OV64S
= (1 << 9),
227 DTLB_MASK
= (DTLB_SIZE
-1),
230 ITLB_MASK
= (ITLB_SIZE
-1),
244 /* check if tlb available */
252 typedef struct OpenRISCTLBEntry
{
257 #ifndef CONFIG_USER_ONLY
258 typedef struct CPUOpenRISCTLBContext
{
259 OpenRISCTLBEntry itlb
[ITLB_WAYS
][ITLB_SIZE
];
260 OpenRISCTLBEntry dtlb
[DTLB_WAYS
][DTLB_SIZE
];
262 int (*cpu_openrisc_map_address_code
)(struct OpenRISCCPU
*cpu
,
263 target_phys_addr_t
*physical
,
265 target_ulong address
, int rw
);
266 int (*cpu_openrisc_map_address_data
)(struct OpenRISCCPU
*cpu
,
267 target_phys_addr_t
*physical
,
269 target_ulong address
, int rw
);
270 } CPUOpenRISCTLBContext
;
273 typedef struct CPUOpenRISCState
{
274 target_ulong gpr
[32]; /* General registers */
275 target_ulong pc
; /* Program counter */
276 target_ulong npc
; /* Next PC */
277 target_ulong ppc
; /* Prev PC */
278 target_ulong jmp_pc
; /* Jump PC */
280 target_ulong machi
; /* Multiply register MACHI */
281 target_ulong maclo
; /* Multiply register MACLO */
283 target_ulong fpmaddhi
; /* Multiply and add float register FPMADDHI */
284 target_ulong fpmaddlo
; /* Multiply and add float register FPMADDLO */
286 target_ulong epcr
; /* Exception PC register */
287 target_ulong eear
; /* Exception EA register */
289 uint32_t sr
; /* Supervisor register */
290 uint32_t vr
; /* Version register */
291 uint32_t upr
; /* Unit presence register */
292 uint32_t cpucfgr
; /* CPU configure register */
293 uint32_t dmmucfgr
; /* DMMU configure register */
294 uint32_t immucfgr
; /* IMMU configure register */
295 uint32_t esr
; /* Exception supervisor register */
296 uint32_t fpcsr
; /* Float register */
297 float_status fp_status
;
299 uint32_t flags
; /* cpu_flags, we only use it for exception
301 uint32_t btaken
; /* the SR_F bit */
305 #ifndef CONFIG_USER_ONLY
306 CPUOpenRISCTLBContext
* tlb
;
308 struct QEMUTimer
*timer
;
309 uint32_t ttmr
; /* Timer tick mode register */
310 uint32_t ttcr
; /* Timer tick count register */
312 uint32_t picmr
; /* Interrupt mask register */
313 uint32_t picsr
; /* Interrupt contrl register*/
315 void *irq
[32]; /* Interrupt irq input */
320 * @env: #CPUOpenRISCState
324 typedef struct OpenRISCCPU
{
329 CPUOpenRISCState env
;
331 uint32_t feature
; /* CPU Capabilities */
334 static inline OpenRISCCPU
*openrisc_env_get_cpu(CPUOpenRISCState
*env
)
336 return OPENRISC_CPU(container_of(env
, OpenRISCCPU
, env
));
339 #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
341 OpenRISCCPU
*cpu_openrisc_init(const char *cpu_model
);
342 void openrisc_cpu_realize(Object
*obj
, Error
**errp
);
344 void cpu_openrisc_list(FILE *f
, fprintf_function cpu_fprintf
);
345 int cpu_openrisc_exec(CPUOpenRISCState
*s
);
346 void do_interrupt(CPUOpenRISCState
*env
);
347 void openrisc_translate_init(void);
348 int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState
*env
,
349 target_ulong address
,
350 int rw
, int mmu_idx
);
352 #define cpu_list cpu_openrisc_list
353 #define cpu_exec cpu_openrisc_exec
354 #define cpu_gen_code cpu_openrisc_gen_code
355 #define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault
357 #ifndef CONFIG_USER_ONLY
358 void cpu_openrisc_mmu_init(OpenRISCCPU
*cpu
);
359 int cpu_openrisc_get_phys_nommu(OpenRISCCPU
*cpu
,
360 target_phys_addr_t
*physical
,
361 int *prot
, target_ulong address
, int rw
);
362 int cpu_openrisc_get_phys_code(OpenRISCCPU
*cpu
,
363 target_phys_addr_t
*physical
,
364 int *prot
, target_ulong address
, int rw
);
365 int cpu_openrisc_get_phys_data(OpenRISCCPU
*cpu
,
366 target_phys_addr_t
*physical
,
367 int *prot
, target_ulong address
, int rw
);
370 static inline CPUOpenRISCState
*cpu_init(const char *cpu_model
)
372 OpenRISCCPU
*cpu
= cpu_openrisc_init(cpu_model
);
381 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState
*env
,
383 target_ulong
*cs_base
, int *flags
)
387 /* D_FLAG -- branch instruction exception */
388 *flags
= (env
->flags
& D_FLAG
);
391 static inline int cpu_mmu_index(CPUOpenRISCState
*env
)
393 if (!(env
->sr
& SR_IME
)) {
394 return MMU_NOMMU_IDX
;
396 return (env
->sr
& SR_SM
) == 0 ? MMU_USER_IDX
: MMU_SUPERVISOR_IDX
;
399 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
400 static inline bool cpu_has_work(CPUOpenRISCState
*env
)
402 return env
->interrupt_request
& (CPU_INTERRUPT_HARD
|
403 CPU_INTERRUPT_TIMER
);
406 #include "exec-all.h"
408 static inline target_ulong
cpu_get_pc(CPUOpenRISCState
*env
)
413 static inline void cpu_pc_from_tb(CPUOpenRISCState
*env
, TranslationBlock
*tb
)
418 #endif /* CPU_OPENRISC_H */