target-ppc/cpu.h

   1 /*
   2  *  PPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #if !defined (__CPU_PPC_H__)
  21 #define __CPU_PPC_H__
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #include "cpu-defs.h"
  26
  27 //#define USE_OPEN_FIRMWARE
  28
  29 /***                          Sign extend constants                        ***/
  30 /* 8 to 32 bits */
  31 static inline int32_t s_ext8 (uint8_t value)
  32 {
  33     int8_t *tmp = &value;
  34
  35     return *tmp;
  36 }
  37
  38 /* 16 to 32 bits */
  39 static inline int32_t s_ext16 (uint16_t value)
  40 {
  41     int16_t *tmp = &value;
  42
  43     return *tmp;
  44 }
  45
  46 #include "config.h"
  47 #include <setjmp.h>
  48
  49 /* Instruction types */
  50 enum {
  51     PPC_NONE     = 0x0000,
  52     PPC_INTEGER  = 0x0001, /* CPU has integer operations instructions        */
  53     PPC_FLOAT    = 0x0002, /* CPU has floating point operations instructions */
  54     PPC_FLOW     = 0x0004, /* CPU has flow control instructions              */
  55     PPC_MEM      = 0x0008, /* CPU has virtual memory instructions            */
  56     PPC_RES      = 0x0010, /* CPU has ld/st with reservation instructions    */
  57     PPC_CACHE    = 0x0020, /* CPU has cache control instructions             */
  58     PPC_MISC     = 0x0040, /* CPU has spr/msr access instructions            */
  59     PPC_EXTERN   = 0x0080, /* CPU has external control instructions          */
  60     PPC_SEGMENT  = 0x0100, /* CPU has memory segment instructions            */
  61     PPC_CACHE_OPT= 0x0200,
  62     PPC_FLOAT_OPT= 0x0400,
  63     PPC_MEM_OPT  = 0x0800,
  64 };
  65
  66 #define PPC_COMMON  (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |           \
  67                      PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
  68 /* PPC 604 */
  69 #define PPC_604 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |               \
  70                  PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT    \
  71                  PPC_MEM_OPT)
  72 /* PPC 740/745/750/755 (aka G3) has external access instructions */
  73 #define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |               \
  74                  PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)
  75
  76 typedef struct ppc_tb_t ppc_tb_t;
  77
  78 /* Supervisor mode registers */
  79 /* Machine state register */
  80 #define MSR_POW 18
  81 #define MSR_ILE 16
  82 #define MSR_EE  15
  83 #define MSR_PR  14
  84 #define MSR_FP  13
  85 #define MSR_ME  12
  86 #define MSR_FE0 11
  87 #define MSR_SE  10
  88 #define MSR_BE  9
  89 #define MSR_FE1 8
  90 #define MSR_IP 6
  91 #define MSR_IR 5
  92 #define MSR_DR 4
  93 #define MSR_RI 1
  94 #define MSR_LE 0
  95 #define msr_pow env->msr[MSR_POW]
  96 #define msr_ile env->msr[MSR_ILE]
  97 #define msr_ee  env->msr[MSR_EE]
  98 #define msr_pr  env->msr[MSR_PR]
  99 #define msr_fp  env->msr[MSR_FP]
 100 #define msr_me  env->msr[MSR_ME]
 101 #define msr_fe0 env->msr[MSR_FE0]
 102 #define msr_se  env->msr[MSR_SE]
 103 #define msr_be  env->msr[MSR_BE]
 104 #define msr_fe1 env->msr[MSR_FE1]
 105 #define msr_ip  env->msr[MSR_IP]
 106 #define msr_ir  env->msr[MSR_IR]
 107 #define msr_dr  env->msr[MSR_DR]
 108 #define msr_ri  env->msr[MSR_RI]
 109 #define msr_le  env->msr[MSR_LE]
 110
 111 /* Segment registers */
 112 typedef struct CPUPPCState {
 113     /* general purpose registers */
 114     uint32_t gpr[32];
 115     /* floating point registers */
 116     double fpr[32];
 117     /* segment registers */
 118     uint32_t sdr1;
 119     uint32_t sr[16];
 120     /* XER */
 121     uint8_t xer[4];
 122     /* Reservation address */
 123     uint32_t reserve;
 124     /* machine state register */
 125     uint8_t msr[32];
 126     /* condition register */
 127     uint8_t crf[8];
 128     /* floating point status and control register */
 129     uint8_t fpscr[8];
 130     uint32_t nip;
 131     /* special purpose registers */
 132     uint32_t lr;
 133     uint32_t ctr;
 134     /* BATs */
 135     uint32_t DBAT[2][8];
 136     uint32_t IBAT[2][8];
 137     /* all others */
 138     uint32_t spr[1024];
 139     /* qemu dedicated */
 140      /* temporary float registers */
 141     double ft0;
 142     double ft1;
 143     double ft2;
 144     int interrupt_request;
 145     jmp_buf jmp_env;
 146     int exception_index;
 147     int error_code;
 148     int access_type; /* when a memory exception occurs, the access
 149                         type is stored here */
 150     int user_mode_only; /* user mode only simulation */
 151     struct TranslationBlock *current_tb; /* currently executing TB */
 152     /* soft mmu support */
 153     /* in order to avoid passing too many arguments to the memory
 154        write helpers, we store some rarely used information in the CPU
 155        context) */
 156     unsigned long mem_write_pc; /* host pc at which the memory was
 157                                    written */
 158     unsigned long mem_write_vaddr; /* target virtual addr at which the
 159                                       memory was written */
 160     /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
 161     CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
 162     CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
 163
 164     /* ice debug support */
 165     uint32_t breakpoints[MAX_BREAKPOINTS];
 166     int nb_breakpoints;
 167     int singlestep_enabled; /* XXX: should use CPU single step mode instead */
 168
 169     /* Time base and decrementer */
 170     ppc_tb_t *tb_env;
 171
 172     /* Power management */
 173     int power_mode;
 174
 175     /* user data */
 176     void *opaque;
 177 } CPUPPCState;
 178
 179 CPUPPCState *cpu_ppc_init(void);
 180 int cpu_ppc_exec(CPUPPCState *s);
 181 void cpu_ppc_close(CPUPPCState *s);
 182 /* you can call this signal handler from your SIGBUS and SIGSEGV
 183    signal handlers to inform the virtual CPU of exceptions. non zero
 184    is returned if the signal was handled by the virtual CPU.  */
 185 struct siginfo;
 186 int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
 187                            void *puc);
 188
 189 void do_interrupt (CPUPPCState *env);
 190 void cpu_loop_exit(void);
 191
 192 void dump_stack (CPUPPCState *env);
 193
 194 uint32_t _load_xer (CPUPPCState *env);
 195 void _store_xer (CPUPPCState *env, uint32_t value);
 196 uint32_t _load_msr (CPUPPCState *env);
 197 void _store_msr (CPUPPCState *env, uint32_t value);
 198
 199 int cpu_ppc_register (CPUPPCState *env, uint32_t pvr);
 200
 201 /* Time-base and decrementer management */
 202 #ifndef NO_CPU_IO_DEFS
 203 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
 204 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
 205 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
 206 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
 207 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
 208 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
 209 #endif
 210
 211 #define TARGET_PAGE_BITS 12
 212 #include "cpu-all.h"
 213
 214 #define ugpr(n) (env->gpr[n])
 215 #define fprd(n) (env->fpr[n])
 216 #define fprs(n) ((float)env->fpr[n])
 217 #define fpru(n) ((uint32_t)env->fpr[n])
 218 #define fpri(n) ((int32_t)env->fpr[n])
 219
 220 #define SPR_ENCODE(sprn)                               \
 221 (((sprn) >> 5) | (((sprn) & 0x1F) << 5))
 222
 223 /* User mode SPR */
 224 #define spr(n) env->spr[n]
 225 #define XER_SO 31
 226 #define XER_OV 30
 227 #define XER_CA 29
 228 #define XER_BC 0
 229 #define xer_so env->xer[3]
 230 #define xer_ov env->xer[2]
 231 #define xer_ca env->xer[1]
 232 #define xer_bc env->xer[0]
 233
 234 #define MQ     SPR_ENCODE(0)
 235 #define XER    SPR_ENCODE(1)
 236 #define RTCUR  SPR_ENCODE(4)
 237 #define RTCLR  SPR_ENCODE(5)
 238 #define LR     SPR_ENCODE(8)
 239 #define CTR    SPR_ENCODE(9)
 240 /* VEA mode SPR */
 241 #define V_TBL  SPR_ENCODE(268)
 242 #define V_TBU  SPR_ENCODE(269)
 243 /* supervisor mode SPR */
 244 #define DSISR  SPR_ENCODE(18)
 245 #define DAR    SPR_ENCODE(19)
 246 #define RTCUW  SPR_ENCODE(20)
 247 #define RTCLW  SPR_ENCODE(21)
 248 #define DECR   SPR_ENCODE(22)
 249 #define SDR1   SPR_ENCODE(25)
 250 #define SRR0   SPR_ENCODE(26)
 251 #define SRR1   SPR_ENCODE(27)
 252 #define SPRG0  SPR_ENCODE(272)
 253 #define SPRG1  SPR_ENCODE(273)
 254 #define SPRG2  SPR_ENCODE(274)
 255 #define SPRG3  SPR_ENCODE(275)
 256 #define SPRG4  SPR_ENCODE(276)
 257 #define SPRG5  SPR_ENCODE(277)
 258 #define SPRG6  SPR_ENCODE(278)
 259 #define SPRG7  SPR_ENCODE(279)
 260 #define ASR    SPR_ENCODE(280)
 261 #define EAR    SPR_ENCODE(282)
 262 #define O_TBL  SPR_ENCODE(284)
 263 #define O_TBU  SPR_ENCODE(285)
 264 #define PVR    SPR_ENCODE(287)
 265 #define IBAT0U SPR_ENCODE(528)
 266 #define IBAT0L SPR_ENCODE(529)
 267 #define IBAT1U SPR_ENCODE(530)
 268 #define IBAT1L SPR_ENCODE(531)
 269 #define IBAT2U SPR_ENCODE(532)
 270 #define IBAT2L SPR_ENCODE(533)
 271 #define IBAT3U SPR_ENCODE(534)
 272 #define IBAT3L SPR_ENCODE(535)
 273 #define DBAT0U SPR_ENCODE(536)
 274 #define DBAT0L SPR_ENCODE(537)
 275 #define DBAT1U SPR_ENCODE(538)
 276 #define DBAT1L SPR_ENCODE(539)
 277 #define DBAT2U SPR_ENCODE(540)
 278 #define DBAT2L SPR_ENCODE(541)
 279 #define DBAT3U SPR_ENCODE(542)
 280 #define DBAT3L SPR_ENCODE(543)
 281 #define IBAT4U SPR_ENCODE(560)
 282 #define IBAT4L SPR_ENCODE(561)
 283 #define IBAT5U SPR_ENCODE(562)
 284 #define IBAT5L SPR_ENCODE(563)
 285 #define IBAT6U SPR_ENCODE(564)
 286 #define IBAT6L SPR_ENCODE(565)
 287 #define IBAT7U SPR_ENCODE(566)
 288 #define IBAT7L SPR_ENCODE(567)
 289 #define DBAT4U SPR_ENCODE(568)
 290 #define DBAT4L SPR_ENCODE(569)
 291 #define DBAT5U SPR_ENCODE(570)
 292 #define DBAT5L SPR_ENCODE(571)
 293 #define DBAT6U SPR_ENCODE(572)
 294 #define DBAT6L SPR_ENCODE(573)
 295 #define DBAT7U SPR_ENCODE(574)
 296 #define DBAT7L SPR_ENCODE(575)
 297 #define UMMCR0 SPR_ENCODE(936)
 298 #define UPMC1  SPR_ENCODE(937)
 299 #define UPMC2  SPR_ENCODE(938)
 300 #define USIA   SPR_ENCODE(939)
 301 #define UMMCR1 SPR_ENCODE(940)
 302 #define UPMC3  SPR_ENCODE(941)
 303 #define UPMC4  SPR_ENCODE(942)
 304 #define MMCR0  SPR_ENCODE(952)
 305 #define PMC1   SPR_ENCODE(953)
 306 #define PMC2   SPR_ENCODE(954)
 307 #define SIA    SPR_ENCODE(955)
 308 #define MMCR1  SPR_ENCODE(956)
 309 #define PMC3   SPR_ENCODE(957)
 310 #define PMC4   SPR_ENCODE(958)
 311 #define SDA    SPR_ENCODE(959)
 312 #define DMISS  SPR_ENCODE(976)
 313 #define DCMP   SPR_ENCODE(977)
 314 #define DHASH1 SPR_ENCODE(978)
 315 #define DHASH2 SPR_ENCODE(979)
 316 #define IMISS  SPR_ENCODE(980)
 317 #define ICMP   SPR_ENCODE(981)
 318 #define RPA    SPR_ENCODE(982)
 319 #define TCR    SPR_ENCODE(984)
 320 #define IBR    SPR_ENCODE(986)
 321 #define ESASRR SPR_ENCODE(987)
 322 #define SEBR   SPR_ENCODE(990)
 323 #define SER    SPR_ENCODE(991)
 324 #define HID0   SPR_ENCODE(1008)
 325 #define HID1   SPR_ENCODE(1009)
 326 #define IABR   SPR_ENCODE(1010)
 327 #define HID2   SPR_ENCODE(1011)
 328 #define DABR   SPR_ENCODE(1013)
 329 #define L2PM   SPR_ENCODE(1016)
 330 #define L2CR   SPR_ENCODE(1017)
 331 #define ICTC   SPR_ENCODE(1019)
 332 #define THRM1  SPR_ENCODE(1020)
 333 #define THRM2  SPR_ENCODE(1021)
 334 #define THRM3  SPR_ENCODE(1022)
 335 #define SP     SPR_ENCODE(1021)
 336 #define SPR_LP SPR_ENCODE(1022)
 337 #define DABR_MASK 0xFFFFFFF8
 338 #define FPECR  SPR_ENCODE(1022)
 339 #define PIR    SPR_ENCODE(1023)
 340
 341 /* Memory access type :
 342  * may be needed for precise access rights control and precise exceptions.
 343  */
 344 enum {
 345     /* 1 bit to define user level / supervisor access */
 346     ACCESS_USER  = 0x00,
 347     ACCESS_SUPER = 0x01,
 348     /* Type of instruction that generated the access */
 349     ACCESS_CODE  = 0x10, /* Code fetch access                */
 350     ACCESS_INT   = 0x20, /* Integer load/store access        */
 351     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 352     ACCESS_RES   = 0x40, /* load/store with reservation      */
 353     ACCESS_EXT   = 0x50, /* external access                  */
 354     ACCESS_CACHE = 0x60, /* Cache manipulation               */
 355 };
 356
 357 /*****************************************************************************/
 358 /* Exceptions */
 359 enum {
 360     EXCP_NONE          = -1,
 361     /* PPC hardware exceptions : exception vector / 0x100 */
 362     EXCP_RESET         = 0x01, /* System reset                     */
 363     EXCP_MACHINE_CHECK = 0x02, /* Machine check exception          */
 364     EXCP_DSI           = 0x03, /* Impossible memory access         */
 365     EXCP_ISI           = 0x04, /* Impossible instruction fetch     */
 366     EXCP_EXTERNAL      = 0x05, /* External interruption            */
 367     EXCP_ALIGN         = 0x06, /* Alignment exception              */
 368     EXCP_PROGRAM       = 0x07, /* Program exception                */
 369     EXCP_NO_FP         = 0x08, /* No floating point                */
 370     EXCP_DECR          = 0x09, /* Decrementer exception            */
 371     EXCP_RESA          = 0x0A, /* Implementation specific          */
 372     EXCP_RESB          = 0x0B, /* Implementation specific          */
 373     EXCP_SYSCALL       = 0x0C, /* System call                      */
 374     EXCP_TRACE         = 0x0D, /* Trace exception (optional)       */
 375     EXCP_FP_ASSIST     = 0x0E, /* Floating-point assist (optional) */
 376     /* MPC740/745/750 & IBM 750 */
 377     EXCP_PERF          = 0x0F,  /* Performance monitor              */
 378     EXCP_IABR          = 0x13,  /* Instruction address breakpoint   */
 379     EXCP_SMI           = 0x14,  /* System management interrupt      */
 380     EXCP_THRM          = 0x15,  /* Thermal management interrupt     */
 381     /* MPC755 */
 382     EXCP_TLBMISS       = 0x10,  /* Instruction TLB miss             */
 383     EXCP_TLBMISS_DL    = 0x11,  /* Data TLB miss for load           */
 384     EXCP_TLBMISS_DS    = 0x12,  /* Data TLB miss for store          */
 385     EXCP_PPC_MAX       = 0x16,
 386     /* Qemu exception */
 387     EXCP_OFCALL        = 0x20,  /* Call open-firmware emulator      */
 388     EXCP_RTASCALL      = 0x21,  /* Call RTAS emulator               */
 389     /* Special cases where we want to stop translation */
 390     EXCP_MTMSR         = 0x104, /* mtmsr instruction:               */
 391                                 /* may change privilege level       */
 392     EXCP_BRANCH        = 0x108, /* branch instruction               */
 393     EXCP_RFI           = 0x10C, /* return from interrupt            */
 394     EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */
 395 };
 396 /* Error codes */
 397 enum {
 398     /* Exception subtypes for EXCP_DSI                              */
 399     EXCP_DSI_TRANSLATE = 0x01,  /* Data address can't be translated */
 400     EXCP_DSI_NOTSUP    = 0x02,  /* Access type not supported        */
 401     EXCP_DSI_PROT      = 0x03,  /* Memory protection violation      */
 402     EXCP_DSI_EXTERNAL  = 0x04,  /* External access disabled         */
 403     EXCP_DSI_DABR      = 0x05,  /* Data address breakpoint          */
 404     /* flags for EXCP_DSI */
 405     EXCP_DSI_DIRECT    = 0x10,
 406     EXCP_DSI_STORE     = 0x20,
 407     EXCP_DSI_ECXW      = 0x40,
 408     /* Exception subtypes for EXCP_ISI                              */
 409     EXCP_ISI_TRANSLATE = 0x01,  /* Code address can't be translated */
 410     EXCP_ISI_NOEXEC    = 0x02,  /* Try to fetch from a data segment */
 411     EXCP_ISI_GUARD     = 0x03,  /* Fetch from guarded memory        */
 412     EXCP_ISI_PROT      = 0x04,  /* Memory protection violation      */
 413     EXCP_ISI_DIRECT    = 0x05,  /* Trying to fetch from             *
 414                                  * a direct store segment           */
 415     /* Exception subtypes for EXCP_ALIGN                            */
 416     EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception           */
 417     EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store */
 418     EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access    */
 419     EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary */
 420     EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary  */
 421     EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access           */
 422     /* Exception subtypes for EXCP_PROGRAM                          */
 423     /* FP exceptions */
 424     EXCP_FP            = 0x10,
 425     EXCP_FP_OX         = 0x01,  /* FP overflow                      */
 426     EXCP_FP_UX         = 0x02,  /* FP underflow                     */
 427     EXCP_FP_ZX         = 0x03,  /* FP divide by zero                */
 428     EXCP_FP_XX         = 0x04,  /* FP inexact                       */
 429     EXCP_FP_VXNAN      = 0x05,  /* FP invalid SNaN op               */
 430     EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite substraction */
 431     EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide       */
 432     EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide           */
 433     EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero       */
 434     EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare               */
 435     EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation             */
 436     EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root           */
 437     EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion    */
 438     /* Invalid instruction */
 439     EXCP_INVAL         = 0x20,
 440     EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction              */
 441     EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction         */
 442     EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access               */
 443     EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr */
 444     /* Privileged instruction */
 445     EXCP_PRIV          = 0x30,
 446     EXCP_PRIV_OPC      = 0x01,
 447     EXCP_PRIV_REG      = 0x02,
 448     /* Trap */
 449     EXCP_TRAP          = 0x40,
 450 };
 451
 452 /*****************************************************************************/
 453
 454 #endif /* !defined (__CPU_PPC_H__) */