]> git.proxmox.com Git - qemu.git/blob - target-ppc/cpu.h
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
q35: set fw_name
[qemu.git] / target-ppc / cpu.h
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 //#define PPC_EMULATE_32BITS_HYPV
26
27 #if defined (TARGET_PPC64)
28 /* PowerPC 64 definitions */
29 #define TARGET_LONG_BITS 64
30 #define TARGET_PAGE_BITS 12
31
32 /* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35 #define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37 /* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40 #ifdef TARGET_ABI32
41 # define TARGET_VIRT_ADDR_SPACE_BITS 32
42 #else
43 # define TARGET_VIRT_ADDR_SPACE_BITS 64
44 #endif
45
46 #define TARGET_PAGE_BITS_16M 24
47
48 #else /* defined (TARGET_PPC64) */
49 /* PowerPC 32 definitions */
50 #define TARGET_LONG_BITS 32
51
52 #if defined(TARGET_PPCEMB)
53 /* Specific definitions for PowerPC embedded */
54 /* BookE have 36 bits physical address space */
55 #if defined(CONFIG_USER_ONLY)
56 /* It looks like a lot of Linux programs assume page size
57 * is 4kB long. This is evil, but we have to deal with it...
58 */
59 #define TARGET_PAGE_BITS 12
60 #else /* defined(CONFIG_USER_ONLY) */
61 /* Pages can be 1 kB small */
62 #define TARGET_PAGE_BITS 10
63 #endif /* defined(CONFIG_USER_ONLY) */
64 #else /* defined(TARGET_PPCEMB) */
65 /* "standard" PowerPC 32 definitions */
66 #define TARGET_PAGE_BITS 12
67 #endif /* defined(TARGET_PPCEMB) */
68
69 #define TARGET_PHYS_ADDR_SPACE_BITS 36
70 #define TARGET_VIRT_ADDR_SPACE_BITS 32
71
72 #endif /* defined (TARGET_PPC64) */
73
74 #define CPUArchState struct CPUPPCState
75
76 #include "exec/cpu-defs.h"
77
78 #include "fpu/softfloat.h"
79
80 #define TARGET_HAS_ICE 1
81
82 #if defined (TARGET_PPC64)
83 #define ELF_MACHINE EM_PPC64
84 #else
85 #define ELF_MACHINE EM_PPC
86 #endif
87
88 /*****************************************************************************/
89 /* MMU model */
90 typedef enum powerpc_mmu_t powerpc_mmu_t;
91 enum powerpc_mmu_t {
92 POWERPC_MMU_UNKNOWN = 0x00000000,
93 /* Standard 32 bits PowerPC MMU */
94 POWERPC_MMU_32B = 0x00000001,
95 /* PowerPC 6xx MMU with software TLB */
96 POWERPC_MMU_SOFT_6xx = 0x00000002,
97 /* PowerPC 74xx MMU with software TLB */
98 POWERPC_MMU_SOFT_74xx = 0x00000003,
99 /* PowerPC 4xx MMU with software TLB */
100 POWERPC_MMU_SOFT_4xx = 0x00000004,
101 /* PowerPC 4xx MMU with software TLB and zones protections */
102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
103 /* PowerPC MMU in real mode only */
104 POWERPC_MMU_REAL = 0x00000006,
105 /* Freescale MPC8xx MMU model */
106 POWERPC_MMU_MPC8xx = 0x00000007,
107 /* BookE MMU model */
108 POWERPC_MMU_BOOKE = 0x00000008,
109 /* BookE 2.06 MMU model */
110 POWERPC_MMU_BOOKE206 = 0x00000009,
111 /* PowerPC 601 MMU model (specific BATs format) */
112 POWERPC_MMU_601 = 0x0000000A,
113 #if defined(TARGET_PPC64)
114 #define POWERPC_MMU_64 0x00010000
115 #define POWERPC_MMU_1TSEG 0x00020000
116 #define POWERPC_MMU_AMR 0x00040000
117 /* 64 bits PowerPC MMU */
118 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
119 /* Architecture 2.06 variant */
120 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
121 | POWERPC_MMU_AMR | 0x00000003,
122 /* Architecture 2.06 "degraded" (no 1T segments) */
123 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
124 | 0x00000003,
125 /* Architecture 2.06 "degraded" (no 1T segments or AMR) */
126 POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003,
127 #endif /* defined(TARGET_PPC64) */
128 };
129
130 /*****************************************************************************/
131 /* Exception model */
132 typedef enum powerpc_excp_t powerpc_excp_t;
133 enum powerpc_excp_t {
134 POWERPC_EXCP_UNKNOWN = 0,
135 /* Standard PowerPC exception model */
136 POWERPC_EXCP_STD,
137 /* PowerPC 40x exception model */
138 POWERPC_EXCP_40x,
139 /* PowerPC 601 exception model */
140 POWERPC_EXCP_601,
141 /* PowerPC 602 exception model */
142 POWERPC_EXCP_602,
143 /* PowerPC 603 exception model */
144 POWERPC_EXCP_603,
145 /* PowerPC 603e exception model */
146 POWERPC_EXCP_603E,
147 /* PowerPC G2 exception model */
148 POWERPC_EXCP_G2,
149 /* PowerPC 604 exception model */
150 POWERPC_EXCP_604,
151 /* PowerPC 7x0 exception model */
152 POWERPC_EXCP_7x0,
153 /* PowerPC 7x5 exception model */
154 POWERPC_EXCP_7x5,
155 /* PowerPC 74xx exception model */
156 POWERPC_EXCP_74xx,
157 /* BookE exception model */
158 POWERPC_EXCP_BOOKE,
159 #if defined(TARGET_PPC64)
160 /* PowerPC 970 exception model */
161 POWERPC_EXCP_970,
162 /* POWER7 exception model */
163 POWERPC_EXCP_POWER7,
164 #endif /* defined(TARGET_PPC64) */
165 };
166
167 /*****************************************************************************/
168 /* Exception vectors definitions */
169 enum {
170 POWERPC_EXCP_NONE = -1,
171 /* The 64 first entries are used by the PowerPC embedded specification */
172 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
173 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
174 POWERPC_EXCP_DSI = 2, /* Data storage exception */
175 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
176 POWERPC_EXCP_EXTERNAL = 4, /* External input */
177 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
178 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
179 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
180 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
181 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
182 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
183 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
184 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
185 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
186 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
187 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
188 /* Vectors 16 to 31 are reserved */
189 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
190 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
191 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
192 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
193 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
194 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
195 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
196 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
197 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
198 /* Vectors 42 to 63 are reserved */
199 /* Exceptions defined in the PowerPC server specification */
200 POWERPC_EXCP_RESET = 64, /* System reset exception */
201 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
202 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
203 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
204 POWERPC_EXCP_TRACE = 68, /* Trace exception */
205 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
206 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
207 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
208 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
209 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
210 /* 40x specific exceptions */
211 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
212 /* 601 specific exceptions */
213 POWERPC_EXCP_IO = 75, /* IO error exception */
214 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
215 /* 602 specific exceptions */
216 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
217 /* 602/603 specific exceptions */
218 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
219 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
220 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
221 /* Exceptions available on most PowerPC */
222 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
223 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
224 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
225 POWERPC_EXCP_SMI = 84, /* System management interrupt */
226 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
227 /* 7xx/74xx specific exceptions */
228 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
229 /* 74xx specific exceptions */
230 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
231 /* 970FX specific exceptions */
232 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
233 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
234 /* Freescale embedded cores specific exceptions */
235 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
236 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
237 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
238 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
239 /* EOL */
240 POWERPC_EXCP_NB = 96,
241 /* QEMU exceptions: used internally during code translation */
242 POWERPC_EXCP_STOP = 0x200, /* stop translation */
243 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
244 /* QEMU exceptions: special cases we want to stop translation */
245 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
246 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
247 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
248 };
249
250 /* Exceptions error codes */
251 enum {
252 /* Exception subtypes for POWERPC_EXCP_ALIGN */
253 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
254 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
255 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
256 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
257 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
258 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
259 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
260 /* FP exceptions */
261 POWERPC_EXCP_FP = 0x10,
262 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
263 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
264 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
265 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
266 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
267 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
268 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
269 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
270 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
271 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
272 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
273 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
274 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
275 /* Invalid instruction */
276 POWERPC_EXCP_INVAL = 0x20,
277 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
278 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
279 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
280 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
281 /* Privileged instruction */
282 POWERPC_EXCP_PRIV = 0x30,
283 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
284 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
285 /* Trap */
286 POWERPC_EXCP_TRAP = 0x40,
287 };
288
289 /*****************************************************************************/
290 /* Input pins model */
291 typedef enum powerpc_input_t powerpc_input_t;
292 enum powerpc_input_t {
293 PPC_FLAGS_INPUT_UNKNOWN = 0,
294 /* PowerPC 6xx bus */
295 PPC_FLAGS_INPUT_6xx,
296 /* BookE bus */
297 PPC_FLAGS_INPUT_BookE,
298 /* PowerPC 405 bus */
299 PPC_FLAGS_INPUT_405,
300 /* PowerPC 970 bus */
301 PPC_FLAGS_INPUT_970,
302 /* PowerPC POWER7 bus */
303 PPC_FLAGS_INPUT_POWER7,
304 /* PowerPC 401 bus */
305 PPC_FLAGS_INPUT_401,
306 /* Freescale RCPU bus */
307 PPC_FLAGS_INPUT_RCPU,
308 };
309
310 #define PPC_INPUT(env) (env->bus_model)
311
312 /*****************************************************************************/
313 typedef struct opc_handler_t opc_handler_t;
314
315 /*****************************************************************************/
316 /* Types used to describe some PowerPC registers */
317 typedef struct CPUPPCState CPUPPCState;
318 typedef struct ppc_tb_t ppc_tb_t;
319 typedef struct ppc_spr_t ppc_spr_t;
320 typedef struct ppc_dcr_t ppc_dcr_t;
321 typedef union ppc_avr_t ppc_avr_t;
322 typedef union ppc_tlb_t ppc_tlb_t;
323
324 /* SPR access micro-ops generations callbacks */
325 struct ppc_spr_t {
326 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
327 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
328 #if !defined(CONFIG_USER_ONLY)
329 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
330 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
331 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
332 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
333 #endif
334 const char *name;
335 #ifdef CONFIG_KVM
336 /* We (ab)use the fact that all the SPRs will have ids for the
337 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
338 * don't sync this */
339 uint64_t one_reg_id;
340 #endif
341 };
342
343 /* Altivec registers (128 bits) */
344 union ppc_avr_t {
345 float32 f[4];
346 uint8_t u8[16];
347 uint16_t u16[8];
348 uint32_t u32[4];
349 int8_t s8[16];
350 int16_t s16[8];
351 int32_t s32[4];
352 uint64_t u64[2];
353 };
354
355 #if !defined(CONFIG_USER_ONLY)
356 /* Software TLB cache */
357 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
358 struct ppc6xx_tlb_t {
359 target_ulong pte0;
360 target_ulong pte1;
361 target_ulong EPN;
362 };
363
364 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
365 struct ppcemb_tlb_t {
366 uint64_t RPN;
367 target_ulong EPN;
368 target_ulong PID;
369 target_ulong size;
370 uint32_t prot;
371 uint32_t attr; /* Storage attributes */
372 };
373
374 typedef struct ppcmas_tlb_t {
375 uint32_t mas8;
376 uint32_t mas1;
377 uint64_t mas2;
378 uint64_t mas7_3;
379 } ppcmas_tlb_t;
380
381 union ppc_tlb_t {
382 ppc6xx_tlb_t *tlb6;
383 ppcemb_tlb_t *tlbe;
384 ppcmas_tlb_t *tlbm;
385 };
386
387 /* possible TLB variants */
388 #define TLB_NONE 0
389 #define TLB_6XX 1
390 #define TLB_EMB 2
391 #define TLB_MAS 3
392 #endif
393
394 #define SDR_32_HTABORG 0xFFFF0000UL
395 #define SDR_32_HTABMASK 0x000001FFUL
396
397 #if defined(TARGET_PPC64)
398 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
399 #define SDR_64_HTABSIZE 0x000000000000001FULL
400 #endif /* defined(TARGET_PPC64 */
401
402 typedef struct ppc_slb_t ppc_slb_t;
403 struct ppc_slb_t {
404 uint64_t esid;
405 uint64_t vsid;
406 };
407
408 #define SEGMENT_SHIFT_256M 28
409 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
410
411 #define SEGMENT_SHIFT_1T 40
412 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
413
414
415 /*****************************************************************************/
416 /* Machine state register bits definition */
417 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
418 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
419 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
420 #define MSR_SHV 60 /* hypervisor state hflags */
421 #define MSR_CM 31 /* Computation mode for BookE hflags */
422 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
423 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
424 #define MSR_GS 28 /* guest state for BookE */
425 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
426 #define MSR_VR 25 /* altivec available x hflags */
427 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
428 #define MSR_AP 23 /* Access privilege state on 602 hflags */
429 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
430 #define MSR_KEY 19 /* key bit on 603e */
431 #define MSR_POW 18 /* Power management */
432 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
433 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
434 #define MSR_ILE 16 /* Interrupt little-endian mode */
435 #define MSR_EE 15 /* External interrupt enable */
436 #define MSR_PR 14 /* Problem state hflags */
437 #define MSR_FP 13 /* Floating point available hflags */
438 #define MSR_ME 12 /* Machine check interrupt enable */
439 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
440 #define MSR_SE 10 /* Single-step trace enable x hflags */
441 #define MSR_DWE 10 /* Debug wait enable on 405 x */
442 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
443 #define MSR_BE 9 /* Branch trace enable x hflags */
444 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
445 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
446 #define MSR_AL 7 /* AL bit on POWER */
447 #define MSR_EP 6 /* Exception prefix on 601 */
448 #define MSR_IR 5 /* Instruction relocate */
449 #define MSR_DR 4 /* Data relocate */
450 #define MSR_PE 3 /* Protection enable on 403 */
451 #define MSR_PX 2 /* Protection exclusive on 403 x */
452 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
453 #define MSR_RI 1 /* Recoverable interrupt 1 */
454 #define MSR_LE 0 /* Little-endian mode 1 hflags */
455
456 #define msr_sf ((env->msr >> MSR_SF) & 1)
457 #define msr_isf ((env->msr >> MSR_ISF) & 1)
458 #define msr_shv ((env->msr >> MSR_SHV) & 1)
459 #define msr_cm ((env->msr >> MSR_CM) & 1)
460 #define msr_icm ((env->msr >> MSR_ICM) & 1)
461 #define msr_thv ((env->msr >> MSR_THV) & 1)
462 #define msr_gs ((env->msr >> MSR_GS) & 1)
463 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
464 #define msr_vr ((env->msr >> MSR_VR) & 1)
465 #define msr_spe ((env->msr >> MSR_SPE) & 1)
466 #define msr_ap ((env->msr >> MSR_AP) & 1)
467 #define msr_sa ((env->msr >> MSR_SA) & 1)
468 #define msr_key ((env->msr >> MSR_KEY) & 1)
469 #define msr_pow ((env->msr >> MSR_POW) & 1)
470 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
471 #define msr_ce ((env->msr >> MSR_CE) & 1)
472 #define msr_ile ((env->msr >> MSR_ILE) & 1)
473 #define msr_ee ((env->msr >> MSR_EE) & 1)
474 #define msr_pr ((env->msr >> MSR_PR) & 1)
475 #define msr_fp ((env->msr >> MSR_FP) & 1)
476 #define msr_me ((env->msr >> MSR_ME) & 1)
477 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
478 #define msr_se ((env->msr >> MSR_SE) & 1)
479 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
480 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
481 #define msr_be ((env->msr >> MSR_BE) & 1)
482 #define msr_de ((env->msr >> MSR_DE) & 1)
483 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
484 #define msr_al ((env->msr >> MSR_AL) & 1)
485 #define msr_ep ((env->msr >> MSR_EP) & 1)
486 #define msr_ir ((env->msr >> MSR_IR) & 1)
487 #define msr_dr ((env->msr >> MSR_DR) & 1)
488 #define msr_pe ((env->msr >> MSR_PE) & 1)
489 #define msr_px ((env->msr >> MSR_PX) & 1)
490 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
491 #define msr_ri ((env->msr >> MSR_RI) & 1)
492 #define msr_le ((env->msr >> MSR_LE) & 1)
493 /* Hypervisor bit is more specific */
494 #if defined(TARGET_PPC64)
495 #define MSR_HVB (1ULL << MSR_SHV)
496 #define msr_hv msr_shv
497 #else
498 #if defined(PPC_EMULATE_32BITS_HYPV)
499 #define MSR_HVB (1ULL << MSR_THV)
500 #define msr_hv msr_thv
501 #else
502 #define MSR_HVB (0ULL)
503 #define msr_hv (0)
504 #endif
505 #endif
506
507 /* Exception state register bits definition */
508 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
509 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
510 #define ESR_PTR (1 << (63 - 38)) /* Trap */
511 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
512 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
513 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
514 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
515 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
516 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
517 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
518 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
519 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
520 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
521 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
522 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
523 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
524
525 enum {
526 POWERPC_FLAG_NONE = 0x00000000,
527 /* Flag for MSR bit 25 signification (VRE/SPE) */
528 POWERPC_FLAG_SPE = 0x00000001,
529 POWERPC_FLAG_VRE = 0x00000002,
530 /* Flag for MSR bit 17 signification (TGPR/CE) */
531 POWERPC_FLAG_TGPR = 0x00000004,
532 POWERPC_FLAG_CE = 0x00000008,
533 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
534 POWERPC_FLAG_SE = 0x00000010,
535 POWERPC_FLAG_DWE = 0x00000020,
536 POWERPC_FLAG_UBLE = 0x00000040,
537 /* Flag for MSR bit 9 signification (BE/DE) */
538 POWERPC_FLAG_BE = 0x00000080,
539 POWERPC_FLAG_DE = 0x00000100,
540 /* Flag for MSR bit 2 signification (PX/PMM) */
541 POWERPC_FLAG_PX = 0x00000200,
542 POWERPC_FLAG_PMM = 0x00000400,
543 /* Flag for special features */
544 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
545 POWERPC_FLAG_RTC_CLK = 0x00010000,
546 POWERPC_FLAG_BUS_CLK = 0x00020000,
547 /* Has CFAR */
548 POWERPC_FLAG_CFAR = 0x00040000,
549 };
550
551 /*****************************************************************************/
552 /* Floating point status and control register */
553 #define FPSCR_FX 31 /* Floating-point exception summary */
554 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
555 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
556 #define FPSCR_OX 28 /* Floating-point overflow exception */
557 #define FPSCR_UX 27 /* Floating-point underflow exception */
558 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
559 #define FPSCR_XX 25 /* Floating-point inexact exception */
560 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
561 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
562 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
563 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
564 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
565 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
566 #define FPSCR_FR 18 /* Floating-point fraction rounded */
567 #define FPSCR_FI 17 /* Floating-point fraction inexact */
568 #define FPSCR_C 16 /* Floating-point result class descriptor */
569 #define FPSCR_FL 15 /* Floating-point less than or negative */
570 #define FPSCR_FG 14 /* Floating-point greater than or negative */
571 #define FPSCR_FE 13 /* Floating-point equal or zero */
572 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
573 #define FPSCR_FPCC 12 /* Floating-point condition code */
574 #define FPSCR_FPRF 12 /* Floating-point result flags */
575 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
576 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
577 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
578 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
579 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
580 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
581 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
582 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
583 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
584 #define FPSCR_RN1 1
585 #define FPSCR_RN 0 /* Floating-point rounding control */
586 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
587 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
588 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
589 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
590 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
591 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
592 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
593 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
594 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
595 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
596 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
597 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
598 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
599 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
600 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
601 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
602 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
603 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
604 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
605 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
606 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
607 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
608 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
609 /* Invalid operation exception summary */
610 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
611 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
612 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
613 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
614 (1 << FPSCR_VXCVI)))
615 /* exception summary */
616 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
617 /* enabled exception summary */
618 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
619 0x1F)
620
621 /*****************************************************************************/
622 /* Vector status and control register */
623 #define VSCR_NJ 16 /* Vector non-java */
624 #define VSCR_SAT 0 /* Vector saturation */
625 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
626 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
627
628 /*****************************************************************************/
629 /* BookE e500 MMU registers */
630
631 #define MAS0_NV_SHIFT 0
632 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
633
634 #define MAS0_WQ_SHIFT 12
635 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
636 /* Write TLB entry regardless of reservation */
637 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
638 /* Write TLB entry only already in use */
639 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
640 /* Clear TLB entry */
641 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
642
643 #define MAS0_HES_SHIFT 14
644 #define MAS0_HES (1 << MAS0_HES_SHIFT)
645
646 #define MAS0_ESEL_SHIFT 16
647 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
648
649 #define MAS0_TLBSEL_SHIFT 28
650 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
651 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
652 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
653 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
654 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
655
656 #define MAS0_ATSEL_SHIFT 31
657 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
658 #define MAS0_ATSEL_TLB 0
659 #define MAS0_ATSEL_LRAT MAS0_ATSEL
660
661 #define MAS1_TSIZE_SHIFT 7
662 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
663
664 #define MAS1_TS_SHIFT 12
665 #define MAS1_TS (1 << MAS1_TS_SHIFT)
666
667 #define MAS1_IND_SHIFT 13
668 #define MAS1_IND (1 << MAS1_IND_SHIFT)
669
670 #define MAS1_TID_SHIFT 16
671 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
672
673 #define MAS1_IPROT_SHIFT 30
674 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
675
676 #define MAS1_VALID_SHIFT 31
677 #define MAS1_VALID 0x80000000
678
679 #define MAS2_EPN_SHIFT 12
680 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
681
682 #define MAS2_ACM_SHIFT 6
683 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
684
685 #define MAS2_VLE_SHIFT 5
686 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
687
688 #define MAS2_W_SHIFT 4
689 #define MAS2_W (1 << MAS2_W_SHIFT)
690
691 #define MAS2_I_SHIFT 3
692 #define MAS2_I (1 << MAS2_I_SHIFT)
693
694 #define MAS2_M_SHIFT 2
695 #define MAS2_M (1 << MAS2_M_SHIFT)
696
697 #define MAS2_G_SHIFT 1
698 #define MAS2_G (1 << MAS2_G_SHIFT)
699
700 #define MAS2_E_SHIFT 0
701 #define MAS2_E (1 << MAS2_E_SHIFT)
702
703 #define MAS3_RPN_SHIFT 12
704 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
705
706 #define MAS3_U0 0x00000200
707 #define MAS3_U1 0x00000100
708 #define MAS3_U2 0x00000080
709 #define MAS3_U3 0x00000040
710 #define MAS3_UX 0x00000020
711 #define MAS3_SX 0x00000010
712 #define MAS3_UW 0x00000008
713 #define MAS3_SW 0x00000004
714 #define MAS3_UR 0x00000002
715 #define MAS3_SR 0x00000001
716 #define MAS3_SPSIZE_SHIFT 1
717 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
718
719 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
720 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
721 #define MAS4_TIDSELD_MASK 0x00030000
722 #define MAS4_TIDSELD_PID0 0x00000000
723 #define MAS4_TIDSELD_PID1 0x00010000
724 #define MAS4_TIDSELD_PID2 0x00020000
725 #define MAS4_TIDSELD_PIDZ 0x00030000
726 #define MAS4_INDD 0x00008000 /* Default IND */
727 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
728 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
729 #define MAS4_ACMD 0x00000040
730 #define MAS4_VLED 0x00000020
731 #define MAS4_WD 0x00000010
732 #define MAS4_ID 0x00000008
733 #define MAS4_MD 0x00000004
734 #define MAS4_GD 0x00000002
735 #define MAS4_ED 0x00000001
736 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
737 #define MAS4_WIMGED_SHIFT 0
738
739 #define MAS5_SGS 0x80000000
740 #define MAS5_SLPID_MASK 0x00000fff
741
742 #define MAS6_SPID0 0x3fff0000
743 #define MAS6_SPID1 0x00007ffe
744 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
745 #define MAS6_SAS 0x00000001
746 #define MAS6_SPID MAS6_SPID0
747 #define MAS6_SIND 0x00000002 /* Indirect page */
748 #define MAS6_SIND_SHIFT 1
749 #define MAS6_SPID_MASK 0x3fff0000
750 #define MAS6_SPID_SHIFT 16
751 #define MAS6_ISIZE_MASK 0x00000f80
752 #define MAS6_ISIZE_SHIFT 7
753
754 #define MAS7_RPN 0xffffffff
755
756 #define MAS8_TGS 0x80000000
757 #define MAS8_VF 0x40000000
758 #define MAS8_TLBPID 0x00000fff
759
760 /* Bit definitions for MMUCFG */
761 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
762 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
763 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
764 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
765 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
766 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
767 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
768 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
769 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
770
771 /* Bit definitions for MMUCSR0 */
772 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
773 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
774 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
775 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
776 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
777 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
778 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
779 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
780 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
781 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
782
783 /* TLBnCFG encoding */
784 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
785 #define TLBnCFG_HES 0x00002000 /* HW select supported */
786 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
787 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
788 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
789 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
790 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
791 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
792 #define TLBnCFG_MINSIZE_SHIFT 20
793 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
794 #define TLBnCFG_MAXSIZE_SHIFT 16
795 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
796 #define TLBnCFG_ASSOC_SHIFT 24
797
798 /* TLBnPS encoding */
799 #define TLBnPS_4K 0x00000004
800 #define TLBnPS_8K 0x00000008
801 #define TLBnPS_16K 0x00000010
802 #define TLBnPS_32K 0x00000020
803 #define TLBnPS_64K 0x00000040
804 #define TLBnPS_128K 0x00000080
805 #define TLBnPS_256K 0x00000100
806 #define TLBnPS_512K 0x00000200
807 #define TLBnPS_1M 0x00000400
808 #define TLBnPS_2M 0x00000800
809 #define TLBnPS_4M 0x00001000
810 #define TLBnPS_8M 0x00002000
811 #define TLBnPS_16M 0x00004000
812 #define TLBnPS_32M 0x00008000
813 #define TLBnPS_64M 0x00010000
814 #define TLBnPS_128M 0x00020000
815 #define TLBnPS_256M 0x00040000
816 #define TLBnPS_512M 0x00080000
817 #define TLBnPS_1G 0x00100000
818 #define TLBnPS_2G 0x00200000
819 #define TLBnPS_4G 0x00400000
820 #define TLBnPS_8G 0x00800000
821 #define TLBnPS_16G 0x01000000
822 #define TLBnPS_32G 0x02000000
823 #define TLBnPS_64G 0x04000000
824 #define TLBnPS_128G 0x08000000
825 #define TLBnPS_256G 0x10000000
826
827 /* tlbilx action encoding */
828 #define TLBILX_T_ALL 0
829 #define TLBILX_T_TID 1
830 #define TLBILX_T_FULLMATCH 3
831 #define TLBILX_T_CLASS0 4
832 #define TLBILX_T_CLASS1 5
833 #define TLBILX_T_CLASS2 6
834 #define TLBILX_T_CLASS3 7
835
836 /* BookE 2.06 helper defines */
837
838 #define BOOKE206_FLUSH_TLB0 (1 << 0)
839 #define BOOKE206_FLUSH_TLB1 (1 << 1)
840 #define BOOKE206_FLUSH_TLB2 (1 << 2)
841 #define BOOKE206_FLUSH_TLB3 (1 << 3)
842
843 /* number of possible TLBs */
844 #define BOOKE206_MAX_TLBN 4
845
846 /*****************************************************************************/
847 /* Embedded.Processor Control */
848
849 #define DBELL_TYPE_SHIFT 27
850 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
851 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
852 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
853 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
854 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
855 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
856
857 #define DBELL_BRDCAST (1 << 26)
858 #define DBELL_LPIDTAG_SHIFT 14
859 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
860 #define DBELL_PIRTAG_MASK 0x3fff
861
862 /*****************************************************************************/
863 /* Segment page size information, used by recent hash MMUs
864 * The format of this structure mirrors kvm_ppc_smmu_info
865 */
866
867 #define PPC_PAGE_SIZES_MAX_SZ 8
868
869 struct ppc_one_page_size {
870 uint32_t page_shift; /* Page shift (or 0) */
871 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
872 };
873
874 struct ppc_one_seg_page_size {
875 uint32_t page_shift; /* Base page shift of segment (or 0) */
876 uint32_t slb_enc; /* SLB encoding for BookS */
877 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
878 };
879
880 struct ppc_segment_page_sizes {
881 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
882 };
883
884
885 /*****************************************************************************/
886 /* The whole PowerPC CPU context */
887 #define NB_MMU_MODES 3
888
889 struct CPUPPCState {
890 /* First are the most commonly used resources
891 * during translated code execution
892 */
893 /* general purpose registers */
894 target_ulong gpr[32];
895 #if !defined(TARGET_PPC64)
896 /* Storage for GPR MSB, used by the SPE extension */
897 target_ulong gprh[32];
898 #endif
899 /* LR */
900 target_ulong lr;
901 /* CTR */
902 target_ulong ctr;
903 /* condition register */
904 uint32_t crf[8];
905 #if defined(TARGET_PPC64)
906 /* CFAR */
907 target_ulong cfar;
908 #endif
909 /* XER (with SO, OV, CA split out) */
910 target_ulong xer;
911 target_ulong so;
912 target_ulong ov;
913 target_ulong ca;
914 /* Reservation address */
915 target_ulong reserve_addr;
916 /* Reservation value */
917 target_ulong reserve_val;
918 /* Reservation store address */
919 target_ulong reserve_ea;
920 /* Reserved store source register and size */
921 target_ulong reserve_info;
922
923 /* Those ones are used in supervisor mode only */
924 /* machine state register */
925 target_ulong msr;
926 /* temporary general purpose registers */
927 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
928
929 /* Floating point execution context */
930 float_status fp_status;
931 /* floating point registers */
932 float64 fpr[32];
933 /* floating point status and control register */
934 target_ulong fpscr;
935
936 /* Next instruction pointer */
937 target_ulong nip;
938
939 int access_type; /* when a memory exception occurs, the access
940 type is stored here */
941
942 CPU_COMMON
943
944 /* MMU context - only relevant for full system emulation */
945 #if !defined(CONFIG_USER_ONLY)
946 #if defined(TARGET_PPC64)
947 /* PowerPC 64 SLB area */
948 ppc_slb_t slb[64];
949 int slb_nr;
950 #endif
951 /* segment registers */
952 hwaddr htab_base;
953 hwaddr htab_mask;
954 target_ulong sr[32];
955 /* externally stored hash table */
956 uint8_t *external_htab;
957 /* BATs */
958 int nb_BATs;
959 target_ulong DBAT[2][8];
960 target_ulong IBAT[2][8];
961 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
962 int nb_tlb; /* Total number of TLB */
963 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
964 int nb_ways; /* Number of ways in the TLB set */
965 int last_way; /* Last used way used to allocate TLB in a LRU way */
966 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
967 int nb_pids; /* Number of available PID registers */
968 int tlb_type; /* Type of TLB we're dealing with */
969 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
970 /* 403 dedicated access protection registers */
971 target_ulong pb[4];
972 bool tlb_dirty; /* Set to non-zero when modifying TLB */
973 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
974 #endif
975
976 /* Other registers */
977 /* Special purpose registers */
978 target_ulong spr[1024];
979 ppc_spr_t spr_cb[1024];
980 /* Altivec registers */
981 ppc_avr_t avr[32];
982 uint32_t vscr;
983 /* VSX registers */
984 uint64_t vsr[32];
985 /* SPE registers */
986 uint64_t spe_acc;
987 uint32_t spe_fscr;
988 /* SPE and Altivec can share a status since they will never be used
989 * simultaneously */
990 float_status vec_status;
991
992 /* Internal devices resources */
993 /* Time base and decrementer */
994 ppc_tb_t *tb_env;
995 /* Device control registers */
996 ppc_dcr_t *dcr_env;
997
998 int dcache_line_size;
999 int icache_line_size;
1000
1001 /* Those resources are used during exception processing */
1002 /* CPU model definition */
1003 target_ulong msr_mask;
1004 powerpc_mmu_t mmu_model;
1005 powerpc_excp_t excp_model;
1006 powerpc_input_t bus_model;
1007 int bfd_mach;
1008 uint32_t flags;
1009 uint64_t insns_flags;
1010 uint64_t insns_flags2;
1011 #if defined(TARGET_PPC64)
1012 struct ppc_segment_page_sizes sps;
1013 #endif
1014
1015 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1016 uint64_t vpa_addr;
1017 uint64_t slb_shadow_addr, slb_shadow_size;
1018 uint64_t dtl_addr, dtl_size;
1019 #endif /* TARGET_PPC64 */
1020
1021 int error_code;
1022 uint32_t pending_interrupts;
1023 #if !defined(CONFIG_USER_ONLY)
1024 /* This is the IRQ controller, which is implementation dependent
1025 * and only relevant when emulating a complete machine.
1026 */
1027 uint32_t irq_input_state;
1028 void **irq_inputs;
1029 /* Exception vectors */
1030 target_ulong excp_vectors[POWERPC_EXCP_NB];
1031 target_ulong excp_prefix;
1032 target_ulong ivor_mask;
1033 target_ulong ivpr_mask;
1034 target_ulong hreset_vector;
1035 hwaddr mpic_iack;
1036 /* true when the external proxy facility mode is enabled */
1037 bool mpic_proxy;
1038 #endif
1039
1040 /* Those resources are used only during code translation */
1041 /* opcode handlers */
1042 opc_handler_t *opcodes[0x40];
1043
1044 /* Those resources are used only in QEMU core */
1045 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1046 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1047 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1048
1049 /* Power management */
1050 int (*check_pow)(CPUPPCState *env);
1051
1052 #if !defined(CONFIG_USER_ONLY)
1053 void *load_info; /* Holds boot loading state. */
1054 #endif
1055
1056 /* booke timers */
1057
1058 /* Specifies bit locations of the Time Base used to signal a fixed timer
1059 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1060 *
1061 * 0 selects the least significant bit.
1062 * 63 selects the most significant bit.
1063 */
1064 uint8_t fit_period[4];
1065 uint8_t wdt_period[4];
1066 };
1067
1068 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1069 do { \
1070 env->fit_period[0] = (a_); \
1071 env->fit_period[1] = (b_); \
1072 env->fit_period[2] = (c_); \
1073 env->fit_period[3] = (d_); \
1074 } while (0)
1075
1076 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1077 do { \
1078 env->wdt_period[0] = (a_); \
1079 env->wdt_period[1] = (b_); \
1080 env->wdt_period[2] = (c_); \
1081 env->wdt_period[3] = (d_); \
1082 } while (0)
1083
1084 #include "cpu-qom.h"
1085
1086 /*****************************************************************************/
1087 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1088 void ppc_translate_init(void);
1089 int cpu_ppc_exec (CPUPPCState *s);
1090 /* you can call this signal handler from your SIGBUS and SIGSEGV
1091 signal handlers to inform the virtual CPU of exceptions. non zero
1092 is returned if the signal was handled by the virtual CPU. */
1093 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1094 void *puc);
1095 void ppc_hw_interrupt (CPUPPCState *env);
1096 #if defined(CONFIG_USER_ONLY)
1097 int cpu_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
1098 int mmu_idx);
1099 #endif
1100
1101 #if !defined(CONFIG_USER_ONLY)
1102 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1103 #endif /* !defined(CONFIG_USER_ONLY) */
1104 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1105
1106 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1107
1108 /* Time-base and decrementer management */
1109 #ifndef NO_CPU_IO_DEFS
1110 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1111 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1112 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1113 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1114 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1115 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1116 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1117 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1118 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1119 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1120 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1121 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1122 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1123 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1124 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1125 #if !defined(CONFIG_USER_ONLY)
1126 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1127 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1128 target_ulong load_40x_pit (CPUPPCState *env);
1129 void store_40x_pit (CPUPPCState *env, target_ulong val);
1130 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1131 void store_40x_sler (CPUPPCState *env, uint32_t val);
1132 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1133 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1134 void ppc_tlb_invalidate_all (CPUPPCState *env);
1135 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1136 #endif
1137 #endif
1138
1139 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1140
1141 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1142 {
1143 uint64_t gprv;
1144
1145 gprv = env->gpr[gprn];
1146 #if !defined(TARGET_PPC64)
1147 if (env->flags & POWERPC_FLAG_SPE) {
1148 /* If the CPU implements the SPE extension, we have to get the
1149 * high bits of the GPR from the gprh storage area
1150 */
1151 gprv &= 0xFFFFFFFFULL;
1152 gprv |= (uint64_t)env->gprh[gprn] << 32;
1153 }
1154 #endif
1155
1156 return gprv;
1157 }
1158
1159 /* Device control registers */
1160 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1161 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1162
1163 static inline CPUPPCState *cpu_init(const char *cpu_model)
1164 {
1165 PowerPCCPU *cpu = cpu_ppc_init(cpu_model);
1166 if (cpu == NULL) {
1167 return NULL;
1168 }
1169 return &cpu->env;
1170 }
1171
1172 #define cpu_exec cpu_ppc_exec
1173 #define cpu_gen_code cpu_ppc_gen_code
1174 #define cpu_signal_handler cpu_ppc_signal_handler
1175 #define cpu_list ppc_cpu_list
1176
1177 #define CPU_SAVE_VERSION 4
1178
1179 /* MMU modes definitions */
1180 #define MMU_MODE0_SUFFIX _user
1181 #define MMU_MODE1_SUFFIX _kernel
1182 #define MMU_MODE2_SUFFIX _hypv
1183 #define MMU_USER_IDX 0
1184 static inline int cpu_mmu_index (CPUPPCState *env)
1185 {
1186 return env->mmu_idx;
1187 }
1188
1189 #if defined(CONFIG_USER_ONLY)
1190 static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)
1191 {
1192 if (newsp)
1193 env->gpr[1] = newsp;
1194 env->gpr[3] = 0;
1195 }
1196 #endif
1197
1198 #include "exec/cpu-all.h"
1199
1200 /*****************************************************************************/
1201 /* CRF definitions */
1202 #define CRF_LT 3
1203 #define CRF_GT 2
1204 #define CRF_EQ 1
1205 #define CRF_SO 0
1206 #define CRF_CH (1 << CRF_LT)
1207 #define CRF_CL (1 << CRF_GT)
1208 #define CRF_CH_OR_CL (1 << CRF_EQ)
1209 #define CRF_CH_AND_CL (1 << CRF_SO)
1210
1211 /* XER definitions */
1212 #define XER_SO 31
1213 #define XER_OV 30
1214 #define XER_CA 29
1215 #define XER_CMP 8
1216 #define XER_BC 0
1217 #define xer_so (env->so)
1218 #define xer_ov (env->ov)
1219 #define xer_ca (env->ca)
1220 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1221 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1222
1223 /* SPR definitions */
1224 #define SPR_MQ (0x000)
1225 #define SPR_XER (0x001)
1226 #define SPR_601_VRTCU (0x004)
1227 #define SPR_601_VRTCL (0x005)
1228 #define SPR_601_UDECR (0x006)
1229 #define SPR_LR (0x008)
1230 #define SPR_CTR (0x009)
1231 #define SPR_UAMR (0x00C)
1232 #define SPR_DSCR (0x011)
1233 #define SPR_DSISR (0x012)
1234 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1235 #define SPR_601_RTCU (0x014)
1236 #define SPR_601_RTCL (0x015)
1237 #define SPR_DECR (0x016)
1238 #define SPR_SDR1 (0x019)
1239 #define SPR_SRR0 (0x01A)
1240 #define SPR_SRR1 (0x01B)
1241 #define SPR_CFAR (0x01C)
1242 #define SPR_AMR (0x01D)
1243 #define SPR_BOOKE_PID (0x030)
1244 #define SPR_BOOKE_DECAR (0x036)
1245 #define SPR_BOOKE_CSRR0 (0x03A)
1246 #define SPR_BOOKE_CSRR1 (0x03B)
1247 #define SPR_BOOKE_DEAR (0x03D)
1248 #define SPR_BOOKE_ESR (0x03E)
1249 #define SPR_BOOKE_IVPR (0x03F)
1250 #define SPR_MPC_EIE (0x050)
1251 #define SPR_MPC_EID (0x051)
1252 #define SPR_MPC_NRI (0x052)
1253 #define SPR_CTRL (0x088)
1254 #define SPR_MPC_CMPA (0x090)
1255 #define SPR_MPC_CMPB (0x091)
1256 #define SPR_MPC_CMPC (0x092)
1257 #define SPR_MPC_CMPD (0x093)
1258 #define SPR_MPC_ECR (0x094)
1259 #define SPR_MPC_DER (0x095)
1260 #define SPR_MPC_COUNTA (0x096)
1261 #define SPR_MPC_COUNTB (0x097)
1262 #define SPR_UCTRL (0x098)
1263 #define SPR_MPC_CMPE (0x098)
1264 #define SPR_MPC_CMPF (0x099)
1265 #define SPR_MPC_CMPG (0x09A)
1266 #define SPR_MPC_CMPH (0x09B)
1267 #define SPR_MPC_LCTRL1 (0x09C)
1268 #define SPR_MPC_LCTRL2 (0x09D)
1269 #define SPR_UAMOR (0x09D)
1270 #define SPR_MPC_ICTRL (0x09E)
1271 #define SPR_MPC_BAR (0x09F)
1272 #define SPR_VRSAVE (0x100)
1273 #define SPR_USPRG0 (0x100)
1274 #define SPR_USPRG1 (0x101)
1275 #define SPR_USPRG2 (0x102)
1276 #define SPR_USPRG3 (0x103)
1277 #define SPR_USPRG4 (0x104)
1278 #define SPR_USPRG5 (0x105)
1279 #define SPR_USPRG6 (0x106)
1280 #define SPR_USPRG7 (0x107)
1281 #define SPR_VTBL (0x10C)
1282 #define SPR_VTBU (0x10D)
1283 #define SPR_SPRG0 (0x110)
1284 #define SPR_SPRG1 (0x111)
1285 #define SPR_SPRG2 (0x112)
1286 #define SPR_SPRG3 (0x113)
1287 #define SPR_SPRG4 (0x114)
1288 #define SPR_SCOMC (0x114)
1289 #define SPR_SPRG5 (0x115)
1290 #define SPR_SCOMD (0x115)
1291 #define SPR_SPRG6 (0x116)
1292 #define SPR_SPRG7 (0x117)
1293 #define SPR_ASR (0x118)
1294 #define SPR_EAR (0x11A)
1295 #define SPR_TBL (0x11C)
1296 #define SPR_TBU (0x11D)
1297 #define SPR_TBU40 (0x11E)
1298 #define SPR_SVR (0x11E)
1299 #define SPR_BOOKE_PIR (0x11E)
1300 #define SPR_PVR (0x11F)
1301 #define SPR_HSPRG0 (0x130)
1302 #define SPR_BOOKE_DBSR (0x130)
1303 #define SPR_HSPRG1 (0x131)
1304 #define SPR_HDSISR (0x132)
1305 #define SPR_HDAR (0x133)
1306 #define SPR_BOOKE_EPCR (0x133)
1307 #define SPR_SPURR (0x134)
1308 #define SPR_BOOKE_DBCR0 (0x134)
1309 #define SPR_IBCR (0x135)
1310 #define SPR_PURR (0x135)
1311 #define SPR_BOOKE_DBCR1 (0x135)
1312 #define SPR_DBCR (0x136)
1313 #define SPR_HDEC (0x136)
1314 #define SPR_BOOKE_DBCR2 (0x136)
1315 #define SPR_HIOR (0x137)
1316 #define SPR_MBAR (0x137)
1317 #define SPR_RMOR (0x138)
1318 #define SPR_BOOKE_IAC1 (0x138)
1319 #define SPR_HRMOR (0x139)
1320 #define SPR_BOOKE_IAC2 (0x139)
1321 #define SPR_HSRR0 (0x13A)
1322 #define SPR_BOOKE_IAC3 (0x13A)
1323 #define SPR_HSRR1 (0x13B)
1324 #define SPR_BOOKE_IAC4 (0x13B)
1325 #define SPR_LPCR (0x13C)
1326 #define SPR_BOOKE_DAC1 (0x13C)
1327 #define SPR_LPIDR (0x13D)
1328 #define SPR_DABR2 (0x13D)
1329 #define SPR_BOOKE_DAC2 (0x13D)
1330 #define SPR_BOOKE_DVC1 (0x13E)
1331 #define SPR_BOOKE_DVC2 (0x13F)
1332 #define SPR_BOOKE_TSR (0x150)
1333 #define SPR_BOOKE_TCR (0x154)
1334 #define SPR_BOOKE_TLB0PS (0x158)
1335 #define SPR_BOOKE_TLB1PS (0x159)
1336 #define SPR_BOOKE_TLB2PS (0x15A)
1337 #define SPR_BOOKE_TLB3PS (0x15B)
1338 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1339 #define SPR_BOOKE_IVOR0 (0x190)
1340 #define SPR_BOOKE_IVOR1 (0x191)
1341 #define SPR_BOOKE_IVOR2 (0x192)
1342 #define SPR_BOOKE_IVOR3 (0x193)
1343 #define SPR_BOOKE_IVOR4 (0x194)
1344 #define SPR_BOOKE_IVOR5 (0x195)
1345 #define SPR_BOOKE_IVOR6 (0x196)
1346 #define SPR_BOOKE_IVOR7 (0x197)
1347 #define SPR_BOOKE_IVOR8 (0x198)
1348 #define SPR_BOOKE_IVOR9 (0x199)
1349 #define SPR_BOOKE_IVOR10 (0x19A)
1350 #define SPR_BOOKE_IVOR11 (0x19B)
1351 #define SPR_BOOKE_IVOR12 (0x19C)
1352 #define SPR_BOOKE_IVOR13 (0x19D)
1353 #define SPR_BOOKE_IVOR14 (0x19E)
1354 #define SPR_BOOKE_IVOR15 (0x19F)
1355 #define SPR_BOOKE_IVOR38 (0x1B0)
1356 #define SPR_BOOKE_IVOR39 (0x1B1)
1357 #define SPR_BOOKE_IVOR40 (0x1B2)
1358 #define SPR_BOOKE_IVOR41 (0x1B3)
1359 #define SPR_BOOKE_IVOR42 (0x1B4)
1360 #define SPR_BOOKE_SPEFSCR (0x200)
1361 #define SPR_Exxx_BBEAR (0x201)
1362 #define SPR_Exxx_BBTAR (0x202)
1363 #define SPR_Exxx_L1CFG0 (0x203)
1364 #define SPR_Exxx_NPIDR (0x205)
1365 #define SPR_ATBL (0x20E)
1366 #define SPR_ATBU (0x20F)
1367 #define SPR_IBAT0U (0x210)
1368 #define SPR_BOOKE_IVOR32 (0x210)
1369 #define SPR_RCPU_MI_GRA (0x210)
1370 #define SPR_IBAT0L (0x211)
1371 #define SPR_BOOKE_IVOR33 (0x211)
1372 #define SPR_IBAT1U (0x212)
1373 #define SPR_BOOKE_IVOR34 (0x212)
1374 #define SPR_IBAT1L (0x213)
1375 #define SPR_BOOKE_IVOR35 (0x213)
1376 #define SPR_IBAT2U (0x214)
1377 #define SPR_BOOKE_IVOR36 (0x214)
1378 #define SPR_IBAT2L (0x215)
1379 #define SPR_BOOKE_IVOR37 (0x215)
1380 #define SPR_IBAT3U (0x216)
1381 #define SPR_IBAT3L (0x217)
1382 #define SPR_DBAT0U (0x218)
1383 #define SPR_RCPU_L2U_GRA (0x218)
1384 #define SPR_DBAT0L (0x219)
1385 #define SPR_DBAT1U (0x21A)
1386 #define SPR_DBAT1L (0x21B)
1387 #define SPR_DBAT2U (0x21C)
1388 #define SPR_DBAT2L (0x21D)
1389 #define SPR_DBAT3U (0x21E)
1390 #define SPR_DBAT3L (0x21F)
1391 #define SPR_IBAT4U (0x230)
1392 #define SPR_RPCU_BBCMCR (0x230)
1393 #define SPR_MPC_IC_CST (0x230)
1394 #define SPR_Exxx_CTXCR (0x230)
1395 #define SPR_IBAT4L (0x231)
1396 #define SPR_MPC_IC_ADR (0x231)
1397 #define SPR_Exxx_DBCR3 (0x231)
1398 #define SPR_IBAT5U (0x232)
1399 #define SPR_MPC_IC_DAT (0x232)
1400 #define SPR_Exxx_DBCNT (0x232)
1401 #define SPR_IBAT5L (0x233)
1402 #define SPR_IBAT6U (0x234)
1403 #define SPR_IBAT6L (0x235)
1404 #define SPR_IBAT7U (0x236)
1405 #define SPR_IBAT7L (0x237)
1406 #define SPR_DBAT4U (0x238)
1407 #define SPR_RCPU_L2U_MCR (0x238)
1408 #define SPR_MPC_DC_CST (0x238)
1409 #define SPR_Exxx_ALTCTXCR (0x238)
1410 #define SPR_DBAT4L (0x239)
1411 #define SPR_MPC_DC_ADR (0x239)
1412 #define SPR_DBAT5U (0x23A)
1413 #define SPR_BOOKE_MCSRR0 (0x23A)
1414 #define SPR_MPC_DC_DAT (0x23A)
1415 #define SPR_DBAT5L (0x23B)
1416 #define SPR_BOOKE_MCSRR1 (0x23B)
1417 #define SPR_DBAT6U (0x23C)
1418 #define SPR_BOOKE_MCSR (0x23C)
1419 #define SPR_DBAT6L (0x23D)
1420 #define SPR_Exxx_MCAR (0x23D)
1421 #define SPR_DBAT7U (0x23E)
1422 #define SPR_BOOKE_DSRR0 (0x23E)
1423 #define SPR_DBAT7L (0x23F)
1424 #define SPR_BOOKE_DSRR1 (0x23F)
1425 #define SPR_BOOKE_SPRG8 (0x25C)
1426 #define SPR_BOOKE_SPRG9 (0x25D)
1427 #define SPR_BOOKE_MAS0 (0x270)
1428 #define SPR_BOOKE_MAS1 (0x271)
1429 #define SPR_BOOKE_MAS2 (0x272)
1430 #define SPR_BOOKE_MAS3 (0x273)
1431 #define SPR_BOOKE_MAS4 (0x274)
1432 #define SPR_BOOKE_MAS5 (0x275)
1433 #define SPR_BOOKE_MAS6 (0x276)
1434 #define SPR_BOOKE_PID1 (0x279)
1435 #define SPR_BOOKE_PID2 (0x27A)
1436 #define SPR_MPC_DPDR (0x280)
1437 #define SPR_MPC_IMMR (0x288)
1438 #define SPR_BOOKE_TLB0CFG (0x2B0)
1439 #define SPR_BOOKE_TLB1CFG (0x2B1)
1440 #define SPR_BOOKE_TLB2CFG (0x2B2)
1441 #define SPR_BOOKE_TLB3CFG (0x2B3)
1442 #define SPR_BOOKE_EPR (0x2BE)
1443 #define SPR_PERF0 (0x300)
1444 #define SPR_RCPU_MI_RBA0 (0x300)
1445 #define SPR_MPC_MI_CTR (0x300)
1446 #define SPR_PERF1 (0x301)
1447 #define SPR_RCPU_MI_RBA1 (0x301)
1448 #define SPR_PERF2 (0x302)
1449 #define SPR_RCPU_MI_RBA2 (0x302)
1450 #define SPR_MPC_MI_AP (0x302)
1451 #define SPR_MMCRA (0x302)
1452 #define SPR_PERF3 (0x303)
1453 #define SPR_RCPU_MI_RBA3 (0x303)
1454 #define SPR_MPC_MI_EPN (0x303)
1455 #define SPR_PERF4 (0x304)
1456 #define SPR_PERF5 (0x305)
1457 #define SPR_MPC_MI_TWC (0x305)
1458 #define SPR_PERF6 (0x306)
1459 #define SPR_MPC_MI_RPN (0x306)
1460 #define SPR_PERF7 (0x307)
1461 #define SPR_PERF8 (0x308)
1462 #define SPR_RCPU_L2U_RBA0 (0x308)
1463 #define SPR_MPC_MD_CTR (0x308)
1464 #define SPR_PERF9 (0x309)
1465 #define SPR_RCPU_L2U_RBA1 (0x309)
1466 #define SPR_MPC_MD_CASID (0x309)
1467 #define SPR_PERFA (0x30A)
1468 #define SPR_RCPU_L2U_RBA2 (0x30A)
1469 #define SPR_MPC_MD_AP (0x30A)
1470 #define SPR_PERFB (0x30B)
1471 #define SPR_RCPU_L2U_RBA3 (0x30B)
1472 #define SPR_MPC_MD_EPN (0x30B)
1473 #define SPR_PERFC (0x30C)
1474 #define SPR_MPC_MD_TWB (0x30C)
1475 #define SPR_PERFD (0x30D)
1476 #define SPR_MPC_MD_TWC (0x30D)
1477 #define SPR_PERFE (0x30E)
1478 #define SPR_MPC_MD_RPN (0x30E)
1479 #define SPR_PERFF (0x30F)
1480 #define SPR_MPC_MD_TW (0x30F)
1481 #define SPR_UPERF0 (0x310)
1482 #define SPR_UPERF1 (0x311)
1483 #define SPR_UPERF2 (0x312)
1484 #define SPR_UPERF3 (0x313)
1485 #define SPR_UPERF4 (0x314)
1486 #define SPR_UPERF5 (0x315)
1487 #define SPR_UPERF6 (0x316)
1488 #define SPR_UPERF7 (0x317)
1489 #define SPR_UPERF8 (0x318)
1490 #define SPR_UPERF9 (0x319)
1491 #define SPR_UPERFA (0x31A)
1492 #define SPR_UPERFB (0x31B)
1493 #define SPR_UPERFC (0x31C)
1494 #define SPR_UPERFD (0x31D)
1495 #define SPR_UPERFE (0x31E)
1496 #define SPR_UPERFF (0x31F)
1497 #define SPR_RCPU_MI_RA0 (0x320)
1498 #define SPR_MPC_MI_DBCAM (0x320)
1499 #define SPR_RCPU_MI_RA1 (0x321)
1500 #define SPR_MPC_MI_DBRAM0 (0x321)
1501 #define SPR_RCPU_MI_RA2 (0x322)
1502 #define SPR_MPC_MI_DBRAM1 (0x322)
1503 #define SPR_RCPU_MI_RA3 (0x323)
1504 #define SPR_RCPU_L2U_RA0 (0x328)
1505 #define SPR_MPC_MD_DBCAM (0x328)
1506 #define SPR_RCPU_L2U_RA1 (0x329)
1507 #define SPR_MPC_MD_DBRAM0 (0x329)
1508 #define SPR_RCPU_L2U_RA2 (0x32A)
1509 #define SPR_MPC_MD_DBRAM1 (0x32A)
1510 #define SPR_RCPU_L2U_RA3 (0x32B)
1511 #define SPR_440_INV0 (0x370)
1512 #define SPR_440_INV1 (0x371)
1513 #define SPR_440_INV2 (0x372)
1514 #define SPR_440_INV3 (0x373)
1515 #define SPR_440_ITV0 (0x374)
1516 #define SPR_440_ITV1 (0x375)
1517 #define SPR_440_ITV2 (0x376)
1518 #define SPR_440_ITV3 (0x377)
1519 #define SPR_440_CCR1 (0x378)
1520 #define SPR_DCRIPR (0x37B)
1521 #define SPR_PPR (0x380)
1522 #define SPR_750_GQR0 (0x390)
1523 #define SPR_440_DNV0 (0x390)
1524 #define SPR_750_GQR1 (0x391)
1525 #define SPR_440_DNV1 (0x391)
1526 #define SPR_750_GQR2 (0x392)
1527 #define SPR_440_DNV2 (0x392)
1528 #define SPR_750_GQR3 (0x393)
1529 #define SPR_440_DNV3 (0x393)
1530 #define SPR_750_GQR4 (0x394)
1531 #define SPR_440_DTV0 (0x394)
1532 #define SPR_750_GQR5 (0x395)
1533 #define SPR_440_DTV1 (0x395)
1534 #define SPR_750_GQR6 (0x396)
1535 #define SPR_440_DTV2 (0x396)
1536 #define SPR_750_GQR7 (0x397)
1537 #define SPR_440_DTV3 (0x397)
1538 #define SPR_750_THRM4 (0x398)
1539 #define SPR_750CL_HID2 (0x398)
1540 #define SPR_440_DVLIM (0x398)
1541 #define SPR_750_WPAR (0x399)
1542 #define SPR_440_IVLIM (0x399)
1543 #define SPR_750_DMAU (0x39A)
1544 #define SPR_750_DMAL (0x39B)
1545 #define SPR_440_RSTCFG (0x39B)
1546 #define SPR_BOOKE_DCDBTRL (0x39C)
1547 #define SPR_BOOKE_DCDBTRH (0x39D)
1548 #define SPR_BOOKE_ICDBTRL (0x39E)
1549 #define SPR_BOOKE_ICDBTRH (0x39F)
1550 #define SPR_UMMCR2 (0x3A0)
1551 #define SPR_UPMC5 (0x3A1)
1552 #define SPR_UPMC6 (0x3A2)
1553 #define SPR_UBAMR (0x3A7)
1554 #define SPR_UMMCR0 (0x3A8)
1555 #define SPR_UPMC1 (0x3A9)
1556 #define SPR_UPMC2 (0x3AA)
1557 #define SPR_USIAR (0x3AB)
1558 #define SPR_UMMCR1 (0x3AC)
1559 #define SPR_UPMC3 (0x3AD)
1560 #define SPR_UPMC4 (0x3AE)
1561 #define SPR_USDA (0x3AF)
1562 #define SPR_40x_ZPR (0x3B0)
1563 #define SPR_BOOKE_MAS7 (0x3B0)
1564 #define SPR_MMCR2 (0x3B0)
1565 #define SPR_PMC5 (0x3B1)
1566 #define SPR_40x_PID (0x3B1)
1567 #define SPR_PMC6 (0x3B2)
1568 #define SPR_440_MMUCR (0x3B2)
1569 #define SPR_4xx_CCR0 (0x3B3)
1570 #define SPR_BOOKE_EPLC (0x3B3)
1571 #define SPR_405_IAC3 (0x3B4)
1572 #define SPR_BOOKE_EPSC (0x3B4)
1573 #define SPR_405_IAC4 (0x3B5)
1574 #define SPR_405_DVC1 (0x3B6)
1575 #define SPR_405_DVC2 (0x3B7)
1576 #define SPR_BAMR (0x3B7)
1577 #define SPR_MMCR0 (0x3B8)
1578 #define SPR_PMC1 (0x3B9)
1579 #define SPR_40x_SGR (0x3B9)
1580 #define SPR_PMC2 (0x3BA)
1581 #define SPR_40x_DCWR (0x3BA)
1582 #define SPR_SIAR (0x3BB)
1583 #define SPR_405_SLER (0x3BB)
1584 #define SPR_MMCR1 (0x3BC)
1585 #define SPR_405_SU0R (0x3BC)
1586 #define SPR_401_SKR (0x3BC)
1587 #define SPR_PMC3 (0x3BD)
1588 #define SPR_405_DBCR1 (0x3BD)
1589 #define SPR_PMC4 (0x3BE)
1590 #define SPR_SDA (0x3BF)
1591 #define SPR_403_VTBL (0x3CC)
1592 #define SPR_403_VTBU (0x3CD)
1593 #define SPR_DMISS (0x3D0)
1594 #define SPR_DCMP (0x3D1)
1595 #define SPR_HASH1 (0x3D2)
1596 #define SPR_HASH2 (0x3D3)
1597 #define SPR_BOOKE_ICDBDR (0x3D3)
1598 #define SPR_TLBMISS (0x3D4)
1599 #define SPR_IMISS (0x3D4)
1600 #define SPR_40x_ESR (0x3D4)
1601 #define SPR_PTEHI (0x3D5)
1602 #define SPR_ICMP (0x3D5)
1603 #define SPR_40x_DEAR (0x3D5)
1604 #define SPR_PTELO (0x3D6)
1605 #define SPR_RPA (0x3D6)
1606 #define SPR_40x_EVPR (0x3D6)
1607 #define SPR_L3PM (0x3D7)
1608 #define SPR_403_CDBCR (0x3D7)
1609 #define SPR_L3ITCR0 (0x3D8)
1610 #define SPR_TCR (0x3D8)
1611 #define SPR_40x_TSR (0x3D8)
1612 #define SPR_IBR (0x3DA)
1613 #define SPR_40x_TCR (0x3DA)
1614 #define SPR_ESASRR (0x3DB)
1615 #define SPR_40x_PIT (0x3DB)
1616 #define SPR_403_TBL (0x3DC)
1617 #define SPR_403_TBU (0x3DD)
1618 #define SPR_SEBR (0x3DE)
1619 #define SPR_40x_SRR2 (0x3DE)
1620 #define SPR_SER (0x3DF)
1621 #define SPR_40x_SRR3 (0x3DF)
1622 #define SPR_L3OHCR (0x3E8)
1623 #define SPR_L3ITCR1 (0x3E9)
1624 #define SPR_L3ITCR2 (0x3EA)
1625 #define SPR_L3ITCR3 (0x3EB)
1626 #define SPR_HID0 (0x3F0)
1627 #define SPR_40x_DBSR (0x3F0)
1628 #define SPR_HID1 (0x3F1)
1629 #define SPR_IABR (0x3F2)
1630 #define SPR_40x_DBCR0 (0x3F2)
1631 #define SPR_601_HID2 (0x3F2)
1632 #define SPR_Exxx_L1CSR0 (0x3F2)
1633 #define SPR_ICTRL (0x3F3)
1634 #define SPR_HID2 (0x3F3)
1635 #define SPR_750CL_HID4 (0x3F3)
1636 #define SPR_Exxx_L1CSR1 (0x3F3)
1637 #define SPR_440_DBDR (0x3F3)
1638 #define SPR_LDSTDB (0x3F4)
1639 #define SPR_750_TDCL (0x3F4)
1640 #define SPR_40x_IAC1 (0x3F4)
1641 #define SPR_MMUCSR0 (0x3F4)
1642 #define SPR_DABR (0x3F5)
1643 #define DABR_MASK (~(target_ulong)0x7)
1644 #define SPR_Exxx_BUCSR (0x3F5)
1645 #define SPR_40x_IAC2 (0x3F5)
1646 #define SPR_601_HID5 (0x3F5)
1647 #define SPR_40x_DAC1 (0x3F6)
1648 #define SPR_MSSCR0 (0x3F6)
1649 #define SPR_970_HID5 (0x3F6)
1650 #define SPR_MSSSR0 (0x3F7)
1651 #define SPR_MSSCR1 (0x3F7)
1652 #define SPR_DABRX (0x3F7)
1653 #define SPR_40x_DAC2 (0x3F7)
1654 #define SPR_MMUCFG (0x3F7)
1655 #define SPR_LDSTCR (0x3F8)
1656 #define SPR_L2PMCR (0x3F8)
1657 #define SPR_750FX_HID2 (0x3F8)
1658 #define SPR_Exxx_L1FINV0 (0x3F8)
1659 #define SPR_L2CR (0x3F9)
1660 #define SPR_L3CR (0x3FA)
1661 #define SPR_750_TDCH (0x3FA)
1662 #define SPR_IABR2 (0x3FA)
1663 #define SPR_40x_DCCR (0x3FA)
1664 #define SPR_ICTC (0x3FB)
1665 #define SPR_40x_ICCR (0x3FB)
1666 #define SPR_THRM1 (0x3FC)
1667 #define SPR_403_PBL1 (0x3FC)
1668 #define SPR_SP (0x3FD)
1669 #define SPR_THRM2 (0x3FD)
1670 #define SPR_403_PBU1 (0x3FD)
1671 #define SPR_604_HID13 (0x3FD)
1672 #define SPR_LT (0x3FE)
1673 #define SPR_THRM3 (0x3FE)
1674 #define SPR_RCPU_FPECR (0x3FE)
1675 #define SPR_403_PBL2 (0x3FE)
1676 #define SPR_PIR (0x3FF)
1677 #define SPR_403_PBU2 (0x3FF)
1678 #define SPR_601_HID15 (0x3FF)
1679 #define SPR_604_HID15 (0x3FF)
1680 #define SPR_E500_SVR (0x3FF)
1681
1682 /* Disable MAS Interrupt Updates for Hypervisor */
1683 #define EPCR_DMIUH (1 << 22)
1684 /* Disable Guest TLB Management Instructions */
1685 #define EPCR_DGTMI (1 << 23)
1686 /* Guest Interrupt Computation Mode */
1687 #define EPCR_GICM (1 << 24)
1688 /* Interrupt Computation Mode */
1689 #define EPCR_ICM (1 << 25)
1690 /* Disable Embedded Hypervisor Debug */
1691 #define EPCR_DUVD (1 << 26)
1692 /* Instruction Storage Interrupt Directed to Guest State */
1693 #define EPCR_ISIGS (1 << 27)
1694 /* Data Storage Interrupt Directed to Guest State */
1695 #define EPCR_DSIGS (1 << 28)
1696 /* Instruction TLB Error Interrupt Directed to Guest State */
1697 #define EPCR_ITLBGS (1 << 29)
1698 /* Data TLB Error Interrupt Directed to Guest State */
1699 #define EPCR_DTLBGS (1 << 30)
1700 /* External Input Interrupt Directed to Guest State */
1701 #define EPCR_EXTGS (1 << 31)
1702
1703 /*****************************************************************************/
1704 /* PowerPC Instructions types definitions */
1705 enum {
1706 PPC_NONE = 0x0000000000000000ULL,
1707 /* PowerPC base instructions set */
1708 PPC_INSNS_BASE = 0x0000000000000001ULL,
1709 /* integer operations instructions */
1710 #define PPC_INTEGER PPC_INSNS_BASE
1711 /* flow control instructions */
1712 #define PPC_FLOW PPC_INSNS_BASE
1713 /* virtual memory instructions */
1714 #define PPC_MEM PPC_INSNS_BASE
1715 /* ld/st with reservation instructions */
1716 #define PPC_RES PPC_INSNS_BASE
1717 /* spr/msr access instructions */
1718 #define PPC_MISC PPC_INSNS_BASE
1719 /* Deprecated instruction sets */
1720 /* Original POWER instruction set */
1721 PPC_POWER = 0x0000000000000002ULL,
1722 /* POWER2 instruction set extension */
1723 PPC_POWER2 = 0x0000000000000004ULL,
1724 /* Power RTC support */
1725 PPC_POWER_RTC = 0x0000000000000008ULL,
1726 /* Power-to-PowerPC bridge (601) */
1727 PPC_POWER_BR = 0x0000000000000010ULL,
1728 /* 64 bits PowerPC instruction set */
1729 PPC_64B = 0x0000000000000020ULL,
1730 /* New 64 bits extensions (PowerPC 2.0x) */
1731 PPC_64BX = 0x0000000000000040ULL,
1732 /* 64 bits hypervisor extensions */
1733 PPC_64H = 0x0000000000000080ULL,
1734 /* New wait instruction (PowerPC 2.0x) */
1735 PPC_WAIT = 0x0000000000000100ULL,
1736 /* Time base mftb instruction */
1737 PPC_MFTB = 0x0000000000000200ULL,
1738
1739 /* Fixed-point unit extensions */
1740 /* PowerPC 602 specific */
1741 PPC_602_SPEC = 0x0000000000000400ULL,
1742 /* isel instruction */
1743 PPC_ISEL = 0x0000000000000800ULL,
1744 /* popcntb instruction */
1745 PPC_POPCNTB = 0x0000000000001000ULL,
1746 /* string load / store */
1747 PPC_STRING = 0x0000000000002000ULL,
1748
1749 /* Floating-point unit extensions */
1750 /* Optional floating point instructions */
1751 PPC_FLOAT = 0x0000000000010000ULL,
1752 /* New floating-point extensions (PowerPC 2.0x) */
1753 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1754 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1755 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1756 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1757 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1758 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1759 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1760
1761 /* Vector/SIMD extensions */
1762 /* Altivec support */
1763 PPC_ALTIVEC = 0x0000000001000000ULL,
1764 /* PowerPC 2.03 SPE extension */
1765 PPC_SPE = 0x0000000002000000ULL,
1766 /* PowerPC 2.03 SPE single-precision floating-point extension */
1767 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1768 /* PowerPC 2.03 SPE double-precision floating-point extension */
1769 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1770
1771 /* Optional memory control instructions */
1772 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1773 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1774 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1775 /* sync instruction */
1776 PPC_MEM_SYNC = 0x0000000080000000ULL,
1777 /* eieio instruction */
1778 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1779
1780 /* Cache control instructions */
1781 PPC_CACHE = 0x0000000200000000ULL,
1782 /* icbi instruction */
1783 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1784 /* dcbz instruction */
1785 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1786 /* dcba instruction */
1787 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1788 /* Freescale cache locking instructions */
1789 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1790
1791 /* MMU related extensions */
1792 /* external control instructions */
1793 PPC_EXTERN = 0x0000010000000000ULL,
1794 /* segment register access instructions */
1795 PPC_SEGMENT = 0x0000020000000000ULL,
1796 /* PowerPC 6xx TLB management instructions */
1797 PPC_6xx_TLB = 0x0000040000000000ULL,
1798 /* PowerPC 74xx TLB management instructions */
1799 PPC_74xx_TLB = 0x0000080000000000ULL,
1800 /* PowerPC 40x TLB management instructions */
1801 PPC_40x_TLB = 0x0000100000000000ULL,
1802 /* segment register access instructions for PowerPC 64 "bridge" */
1803 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1804 /* SLB management */
1805 PPC_SLBI = 0x0000400000000000ULL,
1806
1807 /* Embedded PowerPC dedicated instructions */
1808 PPC_WRTEE = 0x0001000000000000ULL,
1809 /* PowerPC 40x exception model */
1810 PPC_40x_EXCP = 0x0002000000000000ULL,
1811 /* PowerPC 405 Mac instructions */
1812 PPC_405_MAC = 0x0004000000000000ULL,
1813 /* PowerPC 440 specific instructions */
1814 PPC_440_SPEC = 0x0008000000000000ULL,
1815 /* BookE (embedded) PowerPC specification */
1816 PPC_BOOKE = 0x0010000000000000ULL,
1817 /* mfapidi instruction */
1818 PPC_MFAPIDI = 0x0020000000000000ULL,
1819 /* tlbiva instruction */
1820 PPC_TLBIVA = 0x0040000000000000ULL,
1821 /* tlbivax instruction */
1822 PPC_TLBIVAX = 0x0080000000000000ULL,
1823 /* PowerPC 4xx dedicated instructions */
1824 PPC_4xx_COMMON = 0x0100000000000000ULL,
1825 /* PowerPC 40x ibct instructions */
1826 PPC_40x_ICBT = 0x0200000000000000ULL,
1827 /* rfmci is not implemented in all BookE PowerPC */
1828 PPC_RFMCI = 0x0400000000000000ULL,
1829 /* rfdi instruction */
1830 PPC_RFDI = 0x0800000000000000ULL,
1831 /* DCR accesses */
1832 PPC_DCR = 0x1000000000000000ULL,
1833 /* DCR extended accesse */
1834 PPC_DCRX = 0x2000000000000000ULL,
1835 /* user-mode DCR access, implemented in PowerPC 460 */
1836 PPC_DCRUX = 0x4000000000000000ULL,
1837 /* popcntw and popcntd instructions */
1838 PPC_POPCNTWD = 0x8000000000000000ULL,
1839
1840 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1841 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1842 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1843 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1844 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1845 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1846 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1847 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1848 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1849 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1850 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1851 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1852 | PPC_CACHE | PPC_CACHE_ICBI \
1853 | PPC_CACHE_DCBZ \
1854 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1855 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1856 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1857 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1858 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1859 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1860 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1861 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1862 | PPC_POPCNTWD)
1863
1864 /* extended type values */
1865
1866 /* BookE 2.06 PowerPC specification */
1867 PPC2_BOOKE206 = 0x0000000000000001ULL,
1868 /* VSX (extensions to Altivec / VMX) */
1869 PPC2_VSX = 0x0000000000000002ULL,
1870 /* Decimal Floating Point (DFP) */
1871 PPC2_DFP = 0x0000000000000004ULL,
1872 /* Embedded.Processor Control */
1873 PPC2_PRCNTL = 0x0000000000000008ULL,
1874 /* Byte-reversed, indexed, double-word load and store */
1875 PPC2_DBRX = 0x0000000000000010ULL,
1876 /* Book I 2.05 PowerPC specification */
1877 PPC2_ISA205 = 0x0000000000000020ULL,
1878
1879 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX | PPC2_ISA205)
1880 };
1881
1882 /*****************************************************************************/
1883 /* Memory access type :
1884 * may be needed for precise access rights control and precise exceptions.
1885 */
1886 enum {
1887 /* 1 bit to define user level / supervisor access */
1888 ACCESS_USER = 0x00,
1889 ACCESS_SUPER = 0x01,
1890 /* Type of instruction that generated the access */
1891 ACCESS_CODE = 0x10, /* Code fetch access */
1892 ACCESS_INT = 0x20, /* Integer load/store access */
1893 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1894 ACCESS_RES = 0x40, /* load/store with reservation */
1895 ACCESS_EXT = 0x50, /* external access */
1896 ACCESS_CACHE = 0x60, /* Cache manipulation */
1897 };
1898
1899 /* Hardware interruption sources:
1900 * all those exception can be raised simulteaneously
1901 */
1902 /* Input pins definitions */
1903 enum {
1904 /* 6xx bus input pins */
1905 PPC6xx_INPUT_HRESET = 0,
1906 PPC6xx_INPUT_SRESET = 1,
1907 PPC6xx_INPUT_CKSTP_IN = 2,
1908 PPC6xx_INPUT_MCP = 3,
1909 PPC6xx_INPUT_SMI = 4,
1910 PPC6xx_INPUT_INT = 5,
1911 PPC6xx_INPUT_TBEN = 6,
1912 PPC6xx_INPUT_WAKEUP = 7,
1913 PPC6xx_INPUT_NB,
1914 };
1915
1916 enum {
1917 /* Embedded PowerPC input pins */
1918 PPCBookE_INPUT_HRESET = 0,
1919 PPCBookE_INPUT_SRESET = 1,
1920 PPCBookE_INPUT_CKSTP_IN = 2,
1921 PPCBookE_INPUT_MCP = 3,
1922 PPCBookE_INPUT_SMI = 4,
1923 PPCBookE_INPUT_INT = 5,
1924 PPCBookE_INPUT_CINT = 6,
1925 PPCBookE_INPUT_NB,
1926 };
1927
1928 enum {
1929 /* PowerPC E500 input pins */
1930 PPCE500_INPUT_RESET_CORE = 0,
1931 PPCE500_INPUT_MCK = 1,
1932 PPCE500_INPUT_CINT = 3,
1933 PPCE500_INPUT_INT = 4,
1934 PPCE500_INPUT_DEBUG = 6,
1935 PPCE500_INPUT_NB,
1936 };
1937
1938 enum {
1939 /* PowerPC 40x input pins */
1940 PPC40x_INPUT_RESET_CORE = 0,
1941 PPC40x_INPUT_RESET_CHIP = 1,
1942 PPC40x_INPUT_RESET_SYS = 2,
1943 PPC40x_INPUT_CINT = 3,
1944 PPC40x_INPUT_INT = 4,
1945 PPC40x_INPUT_HALT = 5,
1946 PPC40x_INPUT_DEBUG = 6,
1947 PPC40x_INPUT_NB,
1948 };
1949
1950 enum {
1951 /* RCPU input pins */
1952 PPCRCPU_INPUT_PORESET = 0,
1953 PPCRCPU_INPUT_HRESET = 1,
1954 PPCRCPU_INPUT_SRESET = 2,
1955 PPCRCPU_INPUT_IRQ0 = 3,
1956 PPCRCPU_INPUT_IRQ1 = 4,
1957 PPCRCPU_INPUT_IRQ2 = 5,
1958 PPCRCPU_INPUT_IRQ3 = 6,
1959 PPCRCPU_INPUT_IRQ4 = 7,
1960 PPCRCPU_INPUT_IRQ5 = 8,
1961 PPCRCPU_INPUT_IRQ6 = 9,
1962 PPCRCPU_INPUT_IRQ7 = 10,
1963 PPCRCPU_INPUT_NB,
1964 };
1965
1966 #if defined(TARGET_PPC64)
1967 enum {
1968 /* PowerPC 970 input pins */
1969 PPC970_INPUT_HRESET = 0,
1970 PPC970_INPUT_SRESET = 1,
1971 PPC970_INPUT_CKSTP = 2,
1972 PPC970_INPUT_TBEN = 3,
1973 PPC970_INPUT_MCP = 4,
1974 PPC970_INPUT_INT = 5,
1975 PPC970_INPUT_THINT = 6,
1976 PPC970_INPUT_NB,
1977 };
1978
1979 enum {
1980 /* POWER7 input pins */
1981 POWER7_INPUT_INT = 0,
1982 /* POWER7 probably has other inputs, but we don't care about them
1983 * for any existing machine. We can wire these up when we need
1984 * them */
1985 POWER7_INPUT_NB,
1986 };
1987 #endif
1988
1989 /* Hardware exceptions definitions */
1990 enum {
1991 /* External hardware exception sources */
1992 PPC_INTERRUPT_RESET = 0, /* Reset exception */
1993 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1994 PPC_INTERRUPT_MCK, /* Machine check exception */
1995 PPC_INTERRUPT_EXT, /* External interrupt */
1996 PPC_INTERRUPT_SMI, /* System management interrupt */
1997 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1998 PPC_INTERRUPT_DEBUG, /* External debug exception */
1999 PPC_INTERRUPT_THERM, /* Thermal exception */
2000 /* Internal hardware exception sources */
2001 PPC_INTERRUPT_DECR, /* Decrementer exception */
2002 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2003 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2004 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2005 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2006 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2007 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2008 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2009 };
2010
2011 /* CPU should be reset next, restart from scratch afterwards */
2012 #define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0
2013
2014 /*****************************************************************************/
2015
2016 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2017 {
2018 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2019 }
2020
2021 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2022 {
2023 env->so = (xer >> XER_SO) & 1;
2024 env->ov = (xer >> XER_OV) & 1;
2025 env->ca = (xer >> XER_CA) & 1;
2026 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2027 }
2028
2029 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2030 target_ulong *cs_base, int *flags)
2031 {
2032 *pc = env->nip;
2033 *cs_base = 0;
2034 *flags = env->hflags;
2035 }
2036
2037 static inline void cpu_set_tls(CPUPPCState *env, target_ulong newtls)
2038 {
2039 #if defined(TARGET_PPC64)
2040 /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
2041 binaries on PPC64 yet. */
2042 env->gpr[13] = newtls;
2043 #else
2044 env->gpr[2] = newtls;
2045 #endif
2046 }
2047
2048 #if !defined(CONFIG_USER_ONLY)
2049 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2050 {
2051 uintptr_t tlbml = (uintptr_t)tlbm;
2052 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2053
2054 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2055 }
2056
2057 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2058 {
2059 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2060 int r = tlbncfg & TLBnCFG_N_ENTRY;
2061 return r;
2062 }
2063
2064 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2065 {
2066 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2067 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2068 return r;
2069 }
2070
2071 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2072 {
2073 int id = booke206_tlbm_id(env, tlbm);
2074 int end = 0;
2075 int i;
2076
2077 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2078 end += booke206_tlb_size(env, i);
2079 if (id < end) {
2080 return i;
2081 }
2082 }
2083
2084 cpu_abort(env, "Unknown TLBe: %d\n", id);
2085 return 0;
2086 }
2087
2088 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2089 {
2090 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2091 int tlbid = booke206_tlbm_id(env, tlb);
2092 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2093 }
2094
2095 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2096 target_ulong ea, int way)
2097 {
2098 int r;
2099 uint32_t ways = booke206_tlb_ways(env, tlbn);
2100 int ways_bits = ffs(ways) - 1;
2101 int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2102 int i;
2103
2104 way &= ways - 1;
2105 ea >>= MAS2_EPN_SHIFT;
2106 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2107 r = (ea << ways_bits) | way;
2108
2109 if (r >= booke206_tlb_size(env, tlbn)) {
2110 return NULL;
2111 }
2112
2113 /* bump up to tlbn index */
2114 for (i = 0; i < tlbn; i++) {
2115 r += booke206_tlb_size(env, i);
2116 }
2117
2118 return &env->tlb.tlbm[r];
2119 }
2120
2121 /* returns bitmap of supported page sizes for a given TLB */
2122 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2123 {
2124 bool mav2 = false;
2125 uint32_t ret = 0;
2126
2127 if (mav2) {
2128 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2129 } else {
2130 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2131 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2132 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2133 int i;
2134 for (i = min; i <= max; i++) {
2135 ret |= (1 << (i << 1));
2136 }
2137 }
2138
2139 return ret;
2140 }
2141
2142 #endif
2143
2144 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2145 {
2146 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2147 return msr & (1ULL << MSR_CM);
2148 }
2149
2150 return msr & (1ULL << MSR_SF);
2151 }
2152
2153 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2154
2155 static inline bool cpu_has_work(CPUState *cpu)
2156 {
2157 PowerPCCPU *ppc_cpu = POWERPC_CPU(cpu);
2158 CPUPPCState *env = &ppc_cpu->env;
2159
2160 return msr_ee && (cpu->interrupt_request & CPU_INTERRUPT_HARD);
2161 }
2162
2163 #include "exec/exec-all.h"
2164
2165 static inline void cpu_pc_from_tb(CPUPPCState *env, TranslationBlock *tb)
2166 {
2167 env->nip = tb->pc;
2168 }
2169
2170 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2171
2172 #endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing