]> git.proxmox.com Git - qemu.git/blob - target-ppc/cpu.h
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target-ppc: Remove vestigial PowerPC 620 support
[qemu.git] / target-ppc / cpu.h
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 //#define PPC_EMULATE_32BITS_HYPV
26
27 #if defined (TARGET_PPC64)
28 /* PowerPC 64 definitions */
29 #define TARGET_LONG_BITS 64
30 #define TARGET_PAGE_BITS 12
31
32 /* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35 #define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37 /* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40 #ifdef TARGET_ABI32
41 # define TARGET_VIRT_ADDR_SPACE_BITS 32
42 #else
43 # define TARGET_VIRT_ADDR_SPACE_BITS 64
44 #endif
45
46 #define TARGET_PAGE_BITS_16M 24
47
48 #else /* defined (TARGET_PPC64) */
49 /* PowerPC 32 definitions */
50 #define TARGET_LONG_BITS 32
51
52 #if defined(TARGET_PPCEMB)
53 /* Specific definitions for PowerPC embedded */
54 /* BookE have 36 bits physical address space */
55 #if defined(CONFIG_USER_ONLY)
56 /* It looks like a lot of Linux programs assume page size
57 * is 4kB long. This is evil, but we have to deal with it...
58 */
59 #define TARGET_PAGE_BITS 12
60 #else /* defined(CONFIG_USER_ONLY) */
61 /* Pages can be 1 kB small */
62 #define TARGET_PAGE_BITS 10
63 #endif /* defined(CONFIG_USER_ONLY) */
64 #else /* defined(TARGET_PPCEMB) */
65 /* "standard" PowerPC 32 definitions */
66 #define TARGET_PAGE_BITS 12
67 #endif /* defined(TARGET_PPCEMB) */
68
69 #define TARGET_PHYS_ADDR_SPACE_BITS 36
70 #define TARGET_VIRT_ADDR_SPACE_BITS 32
71
72 #endif /* defined (TARGET_PPC64) */
73
74 #define CPUArchState struct CPUPPCState
75
76 #include "exec/cpu-defs.h"
77
78 #include "fpu/softfloat.h"
79
80 #define TARGET_HAS_ICE 1
81
82 #if defined (TARGET_PPC64)
83 #define ELF_MACHINE EM_PPC64
84 #else
85 #define ELF_MACHINE EM_PPC
86 #endif
87
88 /*****************************************************************************/
89 /* MMU model */
90 typedef enum powerpc_mmu_t powerpc_mmu_t;
91 enum powerpc_mmu_t {
92 POWERPC_MMU_UNKNOWN = 0x00000000,
93 /* Standard 32 bits PowerPC MMU */
94 POWERPC_MMU_32B = 0x00000001,
95 /* PowerPC 6xx MMU with software TLB */
96 POWERPC_MMU_SOFT_6xx = 0x00000002,
97 /* PowerPC 74xx MMU with software TLB */
98 POWERPC_MMU_SOFT_74xx = 0x00000003,
99 /* PowerPC 4xx MMU with software TLB */
100 POWERPC_MMU_SOFT_4xx = 0x00000004,
101 /* PowerPC 4xx MMU with software TLB and zones protections */
102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
103 /* PowerPC MMU in real mode only */
104 POWERPC_MMU_REAL = 0x00000006,
105 /* Freescale MPC8xx MMU model */
106 POWERPC_MMU_MPC8xx = 0x00000007,
107 /* BookE MMU model */
108 POWERPC_MMU_BOOKE = 0x00000008,
109 /* BookE 2.06 MMU model */
110 POWERPC_MMU_BOOKE206 = 0x00000009,
111 /* PowerPC 601 MMU model (specific BATs format) */
112 POWERPC_MMU_601 = 0x0000000A,
113 #if defined(TARGET_PPC64)
114 #define POWERPC_MMU_64 0x00010000
115 #define POWERPC_MMU_1TSEG 0x00020000
116 /* 64 bits PowerPC MMU */
117 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
118 /* Architecture 2.06 variant */
119 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,
120 /* Architecture 2.06 "degraded" (no 1T segments) */
121 POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003,
122 #endif /* defined(TARGET_PPC64) */
123 };
124
125 /*****************************************************************************/
126 /* Exception model */
127 typedef enum powerpc_excp_t powerpc_excp_t;
128 enum powerpc_excp_t {
129 POWERPC_EXCP_UNKNOWN = 0,
130 /* Standard PowerPC exception model */
131 POWERPC_EXCP_STD,
132 /* PowerPC 40x exception model */
133 POWERPC_EXCP_40x,
134 /* PowerPC 601 exception model */
135 POWERPC_EXCP_601,
136 /* PowerPC 602 exception model */
137 POWERPC_EXCP_602,
138 /* PowerPC 603 exception model */
139 POWERPC_EXCP_603,
140 /* PowerPC 603e exception model */
141 POWERPC_EXCP_603E,
142 /* PowerPC G2 exception model */
143 POWERPC_EXCP_G2,
144 /* PowerPC 604 exception model */
145 POWERPC_EXCP_604,
146 /* PowerPC 7x0 exception model */
147 POWERPC_EXCP_7x0,
148 /* PowerPC 7x5 exception model */
149 POWERPC_EXCP_7x5,
150 /* PowerPC 74xx exception model */
151 POWERPC_EXCP_74xx,
152 /* BookE exception model */
153 POWERPC_EXCP_BOOKE,
154 #if defined(TARGET_PPC64)
155 /* PowerPC 970 exception model */
156 POWERPC_EXCP_970,
157 /* POWER7 exception model */
158 POWERPC_EXCP_POWER7,
159 #endif /* defined(TARGET_PPC64) */
160 };
161
162 /*****************************************************************************/
163 /* Exception vectors definitions */
164 enum {
165 POWERPC_EXCP_NONE = -1,
166 /* The 64 first entries are used by the PowerPC embedded specification */
167 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
168 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
169 POWERPC_EXCP_DSI = 2, /* Data storage exception */
170 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
171 POWERPC_EXCP_EXTERNAL = 4, /* External input */
172 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
173 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
174 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
175 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
176 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
177 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
178 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
179 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
180 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
181 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
182 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
183 /* Vectors 16 to 31 are reserved */
184 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
185 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
186 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
187 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
188 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
189 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
190 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
191 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
192 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
193 /* Vectors 42 to 63 are reserved */
194 /* Exceptions defined in the PowerPC server specification */
195 POWERPC_EXCP_RESET = 64, /* System reset exception */
196 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
197 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
198 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
199 POWERPC_EXCP_TRACE = 68, /* Trace exception */
200 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
201 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
202 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
203 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
204 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
205 /* 40x specific exceptions */
206 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
207 /* 601 specific exceptions */
208 POWERPC_EXCP_IO = 75, /* IO error exception */
209 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
210 /* 602 specific exceptions */
211 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
212 /* 602/603 specific exceptions */
213 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
214 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
215 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
216 /* Exceptions available on most PowerPC */
217 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
218 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
219 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
220 POWERPC_EXCP_SMI = 84, /* System management interrupt */
221 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
222 /* 7xx/74xx specific exceptions */
223 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
224 /* 74xx specific exceptions */
225 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
226 /* 970FX specific exceptions */
227 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
228 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
229 /* Freescale embedded cores specific exceptions */
230 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
231 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
232 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
233 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
234 /* EOL */
235 POWERPC_EXCP_NB = 96,
236 /* QEMU exceptions: used internally during code translation */
237 POWERPC_EXCP_STOP = 0x200, /* stop translation */
238 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
239 /* QEMU exceptions: special cases we want to stop translation */
240 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
241 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
242 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
243 };
244
245 /* Exceptions error codes */
246 enum {
247 /* Exception subtypes for POWERPC_EXCP_ALIGN */
248 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
249 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
250 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
251 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
252 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
253 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
254 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
255 /* FP exceptions */
256 POWERPC_EXCP_FP = 0x10,
257 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
258 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
259 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
260 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
261 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
262 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
263 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
264 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
265 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
266 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
267 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
268 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
269 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
270 /* Invalid instruction */
271 POWERPC_EXCP_INVAL = 0x20,
272 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
273 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
274 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
275 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
276 /* Privileged instruction */
277 POWERPC_EXCP_PRIV = 0x30,
278 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
279 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
280 /* Trap */
281 POWERPC_EXCP_TRAP = 0x40,
282 };
283
284 /*****************************************************************************/
285 /* Input pins model */
286 typedef enum powerpc_input_t powerpc_input_t;
287 enum powerpc_input_t {
288 PPC_FLAGS_INPUT_UNKNOWN = 0,
289 /* PowerPC 6xx bus */
290 PPC_FLAGS_INPUT_6xx,
291 /* BookE bus */
292 PPC_FLAGS_INPUT_BookE,
293 /* PowerPC 405 bus */
294 PPC_FLAGS_INPUT_405,
295 /* PowerPC 970 bus */
296 PPC_FLAGS_INPUT_970,
297 /* PowerPC POWER7 bus */
298 PPC_FLAGS_INPUT_POWER7,
299 /* PowerPC 401 bus */
300 PPC_FLAGS_INPUT_401,
301 /* Freescale RCPU bus */
302 PPC_FLAGS_INPUT_RCPU,
303 };
304
305 #define PPC_INPUT(env) (env->bus_model)
306
307 /*****************************************************************************/
308 typedef struct opc_handler_t opc_handler_t;
309
310 /*****************************************************************************/
311 /* Types used to describe some PowerPC registers */
312 typedef struct CPUPPCState CPUPPCState;
313 typedef struct ppc_tb_t ppc_tb_t;
314 typedef struct ppc_spr_t ppc_spr_t;
315 typedef struct ppc_dcr_t ppc_dcr_t;
316 typedef union ppc_avr_t ppc_avr_t;
317 typedef union ppc_tlb_t ppc_tlb_t;
318
319 /* SPR access micro-ops generations callbacks */
320 struct ppc_spr_t {
321 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
322 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
323 #if !defined(CONFIG_USER_ONLY)
324 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
325 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
326 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
327 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
328 #endif
329 const char *name;
330 #ifdef CONFIG_KVM
331 /* We (ab)use the fact that all the SPRs will have ids for the
332 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
333 * don't sync this */
334 uint64_t one_reg_id;
335 #endif
336 };
337
338 /* Altivec registers (128 bits) */
339 union ppc_avr_t {
340 float32 f[4];
341 uint8_t u8[16];
342 uint16_t u16[8];
343 uint32_t u32[4];
344 int8_t s8[16];
345 int16_t s16[8];
346 int32_t s32[4];
347 uint64_t u64[2];
348 };
349
350 #if !defined(CONFIG_USER_ONLY)
351 /* Software TLB cache */
352 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
353 struct ppc6xx_tlb_t {
354 target_ulong pte0;
355 target_ulong pte1;
356 target_ulong EPN;
357 };
358
359 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
360 struct ppcemb_tlb_t {
361 uint64_t RPN;
362 target_ulong EPN;
363 target_ulong PID;
364 target_ulong size;
365 uint32_t prot;
366 uint32_t attr; /* Storage attributes */
367 };
368
369 typedef struct ppcmas_tlb_t {
370 uint32_t mas8;
371 uint32_t mas1;
372 uint64_t mas2;
373 uint64_t mas7_3;
374 } ppcmas_tlb_t;
375
376 union ppc_tlb_t {
377 ppc6xx_tlb_t *tlb6;
378 ppcemb_tlb_t *tlbe;
379 ppcmas_tlb_t *tlbm;
380 };
381
382 /* possible TLB variants */
383 #define TLB_NONE 0
384 #define TLB_6XX 1
385 #define TLB_EMB 2
386 #define TLB_MAS 3
387 #endif
388
389 #define SDR_32_HTABORG 0xFFFF0000UL
390 #define SDR_32_HTABMASK 0x000001FFUL
391
392 #if defined(TARGET_PPC64)
393 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
394 #define SDR_64_HTABSIZE 0x000000000000001FULL
395 #endif /* defined(TARGET_PPC64 */
396
397 #define HASH_PTE_SIZE_32 8
398 #define HASH_PTE_SIZE_64 16
399
400 typedef struct ppc_slb_t ppc_slb_t;
401 struct ppc_slb_t {
402 uint64_t esid;
403 uint64_t vsid;
404 };
405
406 /* Bits in the SLB ESID word */
407 #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
408 #define SLB_ESID_V 0x0000000008000000ULL /* valid */
409
410 /* Bits in the SLB VSID word */
411 #define SLB_VSID_SHIFT 12
412 #define SLB_VSID_SHIFT_1T 24
413 #define SLB_VSID_SSIZE_SHIFT 62
414 #define SLB_VSID_B 0xc000000000000000ULL
415 #define SLB_VSID_B_256M 0x0000000000000000ULL
416 #define SLB_VSID_B_1T 0x4000000000000000ULL
417 #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
418 #define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
419 #define SLB_VSID_KS 0x0000000000000800ULL
420 #define SLB_VSID_KP 0x0000000000000400ULL
421 #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
422 #define SLB_VSID_L 0x0000000000000100ULL
423 #define SLB_VSID_C 0x0000000000000080ULL /* class */
424 #define SLB_VSID_LP 0x0000000000000030ULL
425 #define SLB_VSID_ATTR 0x0000000000000FFFULL
426
427 #define SEGMENT_SHIFT_256M 28
428 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
429
430 #define SEGMENT_SHIFT_1T 40
431 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
432
433
434 /*****************************************************************************/
435 /* Machine state register bits definition */
436 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
437 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
438 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
439 #define MSR_SHV 60 /* hypervisor state hflags */
440 #define MSR_CM 31 /* Computation mode for BookE hflags */
441 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
442 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
443 #define MSR_GS 28 /* guest state for BookE */
444 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
445 #define MSR_VR 25 /* altivec available x hflags */
446 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
447 #define MSR_AP 23 /* Access privilege state on 602 hflags */
448 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
449 #define MSR_KEY 19 /* key bit on 603e */
450 #define MSR_POW 18 /* Power management */
451 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
452 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
453 #define MSR_ILE 16 /* Interrupt little-endian mode */
454 #define MSR_EE 15 /* External interrupt enable */
455 #define MSR_PR 14 /* Problem state hflags */
456 #define MSR_FP 13 /* Floating point available hflags */
457 #define MSR_ME 12 /* Machine check interrupt enable */
458 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
459 #define MSR_SE 10 /* Single-step trace enable x hflags */
460 #define MSR_DWE 10 /* Debug wait enable on 405 x */
461 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
462 #define MSR_BE 9 /* Branch trace enable x hflags */
463 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
464 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
465 #define MSR_AL 7 /* AL bit on POWER */
466 #define MSR_EP 6 /* Exception prefix on 601 */
467 #define MSR_IR 5 /* Instruction relocate */
468 #define MSR_DR 4 /* Data relocate */
469 #define MSR_PE 3 /* Protection enable on 403 */
470 #define MSR_PX 2 /* Protection exclusive on 403 x */
471 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
472 #define MSR_RI 1 /* Recoverable interrupt 1 */
473 #define MSR_LE 0 /* Little-endian mode 1 hflags */
474
475 #define msr_sf ((env->msr >> MSR_SF) & 1)
476 #define msr_isf ((env->msr >> MSR_ISF) & 1)
477 #define msr_shv ((env->msr >> MSR_SHV) & 1)
478 #define msr_cm ((env->msr >> MSR_CM) & 1)
479 #define msr_icm ((env->msr >> MSR_ICM) & 1)
480 #define msr_thv ((env->msr >> MSR_THV) & 1)
481 #define msr_gs ((env->msr >> MSR_GS) & 1)
482 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
483 #define msr_vr ((env->msr >> MSR_VR) & 1)
484 #define msr_spe ((env->msr >> MSR_SPE) & 1)
485 #define msr_ap ((env->msr >> MSR_AP) & 1)
486 #define msr_sa ((env->msr >> MSR_SA) & 1)
487 #define msr_key ((env->msr >> MSR_KEY) & 1)
488 #define msr_pow ((env->msr >> MSR_POW) & 1)
489 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
490 #define msr_ce ((env->msr >> MSR_CE) & 1)
491 #define msr_ile ((env->msr >> MSR_ILE) & 1)
492 #define msr_ee ((env->msr >> MSR_EE) & 1)
493 #define msr_pr ((env->msr >> MSR_PR) & 1)
494 #define msr_fp ((env->msr >> MSR_FP) & 1)
495 #define msr_me ((env->msr >> MSR_ME) & 1)
496 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
497 #define msr_se ((env->msr >> MSR_SE) & 1)
498 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
499 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
500 #define msr_be ((env->msr >> MSR_BE) & 1)
501 #define msr_de ((env->msr >> MSR_DE) & 1)
502 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
503 #define msr_al ((env->msr >> MSR_AL) & 1)
504 #define msr_ep ((env->msr >> MSR_EP) & 1)
505 #define msr_ir ((env->msr >> MSR_IR) & 1)
506 #define msr_dr ((env->msr >> MSR_DR) & 1)
507 #define msr_pe ((env->msr >> MSR_PE) & 1)
508 #define msr_px ((env->msr >> MSR_PX) & 1)
509 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
510 #define msr_ri ((env->msr >> MSR_RI) & 1)
511 #define msr_le ((env->msr >> MSR_LE) & 1)
512 /* Hypervisor bit is more specific */
513 #if defined(TARGET_PPC64)
514 #define MSR_HVB (1ULL << MSR_SHV)
515 #define msr_hv msr_shv
516 #else
517 #if defined(PPC_EMULATE_32BITS_HYPV)
518 #define MSR_HVB (1ULL << MSR_THV)
519 #define msr_hv msr_thv
520 #else
521 #define MSR_HVB (0ULL)
522 #define msr_hv (0)
523 #endif
524 #endif
525
526 /* Exception state register bits definition */
527 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
528 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
529 #define ESR_PTR (1 << (63 - 38)) /* Trap */
530 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
531 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
532 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
533 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
534 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
535 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
536 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
537 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
538 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
539 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
540 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
541 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
542 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
543
544 enum {
545 POWERPC_FLAG_NONE = 0x00000000,
546 /* Flag for MSR bit 25 signification (VRE/SPE) */
547 POWERPC_FLAG_SPE = 0x00000001,
548 POWERPC_FLAG_VRE = 0x00000002,
549 /* Flag for MSR bit 17 signification (TGPR/CE) */
550 POWERPC_FLAG_TGPR = 0x00000004,
551 POWERPC_FLAG_CE = 0x00000008,
552 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
553 POWERPC_FLAG_SE = 0x00000010,
554 POWERPC_FLAG_DWE = 0x00000020,
555 POWERPC_FLAG_UBLE = 0x00000040,
556 /* Flag for MSR bit 9 signification (BE/DE) */
557 POWERPC_FLAG_BE = 0x00000080,
558 POWERPC_FLAG_DE = 0x00000100,
559 /* Flag for MSR bit 2 signification (PX/PMM) */
560 POWERPC_FLAG_PX = 0x00000200,
561 POWERPC_FLAG_PMM = 0x00000400,
562 /* Flag for special features */
563 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
564 POWERPC_FLAG_RTC_CLK = 0x00010000,
565 POWERPC_FLAG_BUS_CLK = 0x00020000,
566 /* Has CFAR */
567 POWERPC_FLAG_CFAR = 0x00040000,
568 };
569
570 /*****************************************************************************/
571 /* Floating point status and control register */
572 #define FPSCR_FX 31 /* Floating-point exception summary */
573 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
574 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
575 #define FPSCR_OX 28 /* Floating-point overflow exception */
576 #define FPSCR_UX 27 /* Floating-point underflow exception */
577 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
578 #define FPSCR_XX 25 /* Floating-point inexact exception */
579 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
580 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
581 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
582 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
583 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
584 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
585 #define FPSCR_FR 18 /* Floating-point fraction rounded */
586 #define FPSCR_FI 17 /* Floating-point fraction inexact */
587 #define FPSCR_C 16 /* Floating-point result class descriptor */
588 #define FPSCR_FL 15 /* Floating-point less than or negative */
589 #define FPSCR_FG 14 /* Floating-point greater than or negative */
590 #define FPSCR_FE 13 /* Floating-point equal or zero */
591 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
592 #define FPSCR_FPCC 12 /* Floating-point condition code */
593 #define FPSCR_FPRF 12 /* Floating-point result flags */
594 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
595 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
596 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
597 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
598 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
599 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
600 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
601 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
602 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
603 #define FPSCR_RN1 1
604 #define FPSCR_RN 0 /* Floating-point rounding control */
605 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
606 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
607 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
608 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
609 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
610 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
611 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
612 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
613 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
614 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
615 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
616 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
617 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
618 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
619 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
620 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
621 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
622 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
623 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
624 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
625 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
626 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
627 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
628 /* Invalid operation exception summary */
629 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
630 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
631 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
632 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
633 (1 << FPSCR_VXCVI)))
634 /* exception summary */
635 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
636 /* enabled exception summary */
637 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
638 0x1F)
639
640 /*****************************************************************************/
641 /* Vector status and control register */
642 #define VSCR_NJ 16 /* Vector non-java */
643 #define VSCR_SAT 0 /* Vector saturation */
644 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
645 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
646
647 /*****************************************************************************/
648 /* BookE e500 MMU registers */
649
650 #define MAS0_NV_SHIFT 0
651 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
652
653 #define MAS0_WQ_SHIFT 12
654 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
655 /* Write TLB entry regardless of reservation */
656 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
657 /* Write TLB entry only already in use */
658 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
659 /* Clear TLB entry */
660 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
661
662 #define MAS0_HES_SHIFT 14
663 #define MAS0_HES (1 << MAS0_HES_SHIFT)
664
665 #define MAS0_ESEL_SHIFT 16
666 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
667
668 #define MAS0_TLBSEL_SHIFT 28
669 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
670 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
671 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
672 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
673 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
674
675 #define MAS0_ATSEL_SHIFT 31
676 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
677 #define MAS0_ATSEL_TLB 0
678 #define MAS0_ATSEL_LRAT MAS0_ATSEL
679
680 #define MAS1_TSIZE_SHIFT 7
681 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
682
683 #define MAS1_TS_SHIFT 12
684 #define MAS1_TS (1 << MAS1_TS_SHIFT)
685
686 #define MAS1_IND_SHIFT 13
687 #define MAS1_IND (1 << MAS1_IND_SHIFT)
688
689 #define MAS1_TID_SHIFT 16
690 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
691
692 #define MAS1_IPROT_SHIFT 30
693 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
694
695 #define MAS1_VALID_SHIFT 31
696 #define MAS1_VALID 0x80000000
697
698 #define MAS2_EPN_SHIFT 12
699 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
700
701 #define MAS2_ACM_SHIFT 6
702 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
703
704 #define MAS2_VLE_SHIFT 5
705 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
706
707 #define MAS2_W_SHIFT 4
708 #define MAS2_W (1 << MAS2_W_SHIFT)
709
710 #define MAS2_I_SHIFT 3
711 #define MAS2_I (1 << MAS2_I_SHIFT)
712
713 #define MAS2_M_SHIFT 2
714 #define MAS2_M (1 << MAS2_M_SHIFT)
715
716 #define MAS2_G_SHIFT 1
717 #define MAS2_G (1 << MAS2_G_SHIFT)
718
719 #define MAS2_E_SHIFT 0
720 #define MAS2_E (1 << MAS2_E_SHIFT)
721
722 #define MAS3_RPN_SHIFT 12
723 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
724
725 #define MAS3_U0 0x00000200
726 #define MAS3_U1 0x00000100
727 #define MAS3_U2 0x00000080
728 #define MAS3_U3 0x00000040
729 #define MAS3_UX 0x00000020
730 #define MAS3_SX 0x00000010
731 #define MAS3_UW 0x00000008
732 #define MAS3_SW 0x00000004
733 #define MAS3_UR 0x00000002
734 #define MAS3_SR 0x00000001
735 #define MAS3_SPSIZE_SHIFT 1
736 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
737
738 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
739 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
740 #define MAS4_TIDSELD_MASK 0x00030000
741 #define MAS4_TIDSELD_PID0 0x00000000
742 #define MAS4_TIDSELD_PID1 0x00010000
743 #define MAS4_TIDSELD_PID2 0x00020000
744 #define MAS4_TIDSELD_PIDZ 0x00030000
745 #define MAS4_INDD 0x00008000 /* Default IND */
746 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
747 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
748 #define MAS4_ACMD 0x00000040
749 #define MAS4_VLED 0x00000020
750 #define MAS4_WD 0x00000010
751 #define MAS4_ID 0x00000008
752 #define MAS4_MD 0x00000004
753 #define MAS4_GD 0x00000002
754 #define MAS4_ED 0x00000001
755 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
756 #define MAS4_WIMGED_SHIFT 0
757
758 #define MAS5_SGS 0x80000000
759 #define MAS5_SLPID_MASK 0x00000fff
760
761 #define MAS6_SPID0 0x3fff0000
762 #define MAS6_SPID1 0x00007ffe
763 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
764 #define MAS6_SAS 0x00000001
765 #define MAS6_SPID MAS6_SPID0
766 #define MAS6_SIND 0x00000002 /* Indirect page */
767 #define MAS6_SIND_SHIFT 1
768 #define MAS6_SPID_MASK 0x3fff0000
769 #define MAS6_SPID_SHIFT 16
770 #define MAS6_ISIZE_MASK 0x00000f80
771 #define MAS6_ISIZE_SHIFT 7
772
773 #define MAS7_RPN 0xffffffff
774
775 #define MAS8_TGS 0x80000000
776 #define MAS8_VF 0x40000000
777 #define MAS8_TLBPID 0x00000fff
778
779 /* Bit definitions for MMUCFG */
780 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
781 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
782 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
783 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
784 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
785 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
786 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
787 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
788 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
789
790 /* Bit definitions for MMUCSR0 */
791 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
792 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
793 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
794 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
795 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
796 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
797 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
798 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
799 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
800 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
801
802 /* TLBnCFG encoding */
803 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
804 #define TLBnCFG_HES 0x00002000 /* HW select supported */
805 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
806 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
807 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
808 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
809 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
810 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
811 #define TLBnCFG_MINSIZE_SHIFT 20
812 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
813 #define TLBnCFG_MAXSIZE_SHIFT 16
814 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
815 #define TLBnCFG_ASSOC_SHIFT 24
816
817 /* TLBnPS encoding */
818 #define TLBnPS_4K 0x00000004
819 #define TLBnPS_8K 0x00000008
820 #define TLBnPS_16K 0x00000010
821 #define TLBnPS_32K 0x00000020
822 #define TLBnPS_64K 0x00000040
823 #define TLBnPS_128K 0x00000080
824 #define TLBnPS_256K 0x00000100
825 #define TLBnPS_512K 0x00000200
826 #define TLBnPS_1M 0x00000400
827 #define TLBnPS_2M 0x00000800
828 #define TLBnPS_4M 0x00001000
829 #define TLBnPS_8M 0x00002000
830 #define TLBnPS_16M 0x00004000
831 #define TLBnPS_32M 0x00008000
832 #define TLBnPS_64M 0x00010000
833 #define TLBnPS_128M 0x00020000
834 #define TLBnPS_256M 0x00040000
835 #define TLBnPS_512M 0x00080000
836 #define TLBnPS_1G 0x00100000
837 #define TLBnPS_2G 0x00200000
838 #define TLBnPS_4G 0x00400000
839 #define TLBnPS_8G 0x00800000
840 #define TLBnPS_16G 0x01000000
841 #define TLBnPS_32G 0x02000000
842 #define TLBnPS_64G 0x04000000
843 #define TLBnPS_128G 0x08000000
844 #define TLBnPS_256G 0x10000000
845
846 /* tlbilx action encoding */
847 #define TLBILX_T_ALL 0
848 #define TLBILX_T_TID 1
849 #define TLBILX_T_FULLMATCH 3
850 #define TLBILX_T_CLASS0 4
851 #define TLBILX_T_CLASS1 5
852 #define TLBILX_T_CLASS2 6
853 #define TLBILX_T_CLASS3 7
854
855 /* BookE 2.06 helper defines */
856
857 #define BOOKE206_FLUSH_TLB0 (1 << 0)
858 #define BOOKE206_FLUSH_TLB1 (1 << 1)
859 #define BOOKE206_FLUSH_TLB2 (1 << 2)
860 #define BOOKE206_FLUSH_TLB3 (1 << 3)
861
862 /* number of possible TLBs */
863 #define BOOKE206_MAX_TLBN 4
864
865 /*****************************************************************************/
866 /* Embedded.Processor Control */
867
868 #define DBELL_TYPE_SHIFT 27
869 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
870 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
871 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
872 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
873 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
874 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
875
876 #define DBELL_BRDCAST (1 << 26)
877 #define DBELL_LPIDTAG_SHIFT 14
878 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
879 #define DBELL_PIRTAG_MASK 0x3fff
880
881 /*****************************************************************************/
882 /* Segment page size information, used by recent hash MMUs
883 * The format of this structure mirrors kvm_ppc_smmu_info
884 */
885
886 #define PPC_PAGE_SIZES_MAX_SZ 8
887
888 struct ppc_one_page_size {
889 uint32_t page_shift; /* Page shift (or 0) */
890 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
891 };
892
893 struct ppc_one_seg_page_size {
894 uint32_t page_shift; /* Base page shift of segment (or 0) */
895 uint32_t slb_enc; /* SLB encoding for BookS */
896 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
897 };
898
899 struct ppc_segment_page_sizes {
900 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
901 };
902
903
904 /*****************************************************************************/
905 /* The whole PowerPC CPU context */
906 #define NB_MMU_MODES 3
907
908 struct CPUPPCState {
909 /* First are the most commonly used resources
910 * during translated code execution
911 */
912 /* general purpose registers */
913 target_ulong gpr[32];
914 #if !defined(TARGET_PPC64)
915 /* Storage for GPR MSB, used by the SPE extension */
916 target_ulong gprh[32];
917 #endif
918 /* LR */
919 target_ulong lr;
920 /* CTR */
921 target_ulong ctr;
922 /* condition register */
923 uint32_t crf[8];
924 #if defined(TARGET_PPC64)
925 /* CFAR */
926 target_ulong cfar;
927 #endif
928 /* XER (with SO, OV, CA split out) */
929 target_ulong xer;
930 target_ulong so;
931 target_ulong ov;
932 target_ulong ca;
933 /* Reservation address */
934 target_ulong reserve_addr;
935 /* Reservation value */
936 target_ulong reserve_val;
937 /* Reservation store address */
938 target_ulong reserve_ea;
939 /* Reserved store source register and size */
940 target_ulong reserve_info;
941
942 /* Those ones are used in supervisor mode only */
943 /* machine state register */
944 target_ulong msr;
945 /* temporary general purpose registers */
946 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
947
948 /* Floating point execution context */
949 float_status fp_status;
950 /* floating point registers */
951 float64 fpr[32];
952 /* floating point status and control register */
953 target_ulong fpscr;
954
955 /* Next instruction pointer */
956 target_ulong nip;
957
958 int access_type; /* when a memory exception occurs, the access
959 type is stored here */
960
961 CPU_COMMON
962
963 /* MMU context - only relevant for full system emulation */
964 #if !defined(CONFIG_USER_ONLY)
965 #if defined(TARGET_PPC64)
966 /* PowerPC 64 SLB area */
967 ppc_slb_t slb[64];
968 int slb_nr;
969 #endif
970 /* segment registers */
971 hwaddr htab_base;
972 hwaddr htab_mask;
973 target_ulong sr[32];
974 /* externally stored hash table */
975 uint8_t *external_htab;
976 /* BATs */
977 int nb_BATs;
978 target_ulong DBAT[2][8];
979 target_ulong IBAT[2][8];
980 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
981 int nb_tlb; /* Total number of TLB */
982 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
983 int nb_ways; /* Number of ways in the TLB set */
984 int last_way; /* Last used way used to allocate TLB in a LRU way */
985 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
986 int nb_pids; /* Number of available PID registers */
987 int tlb_type; /* Type of TLB we're dealing with */
988 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
989 /* 403 dedicated access protection registers */
990 target_ulong pb[4];
991 bool tlb_dirty; /* Set to non-zero when modifying TLB */
992 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
993 #endif
994
995 /* Other registers */
996 /* Special purpose registers */
997 target_ulong spr[1024];
998 ppc_spr_t spr_cb[1024];
999 /* Altivec registers */
1000 ppc_avr_t avr[32];
1001 uint32_t vscr;
1002 /* VSX registers */
1003 uint64_t vsr[32];
1004 /* SPE registers */
1005 uint64_t spe_acc;
1006 uint32_t spe_fscr;
1007 /* SPE and Altivec can share a status since they will never be used
1008 * simultaneously */
1009 float_status vec_status;
1010
1011 /* Internal devices resources */
1012 /* Time base and decrementer */
1013 ppc_tb_t *tb_env;
1014 /* Device control registers */
1015 ppc_dcr_t *dcr_env;
1016
1017 int dcache_line_size;
1018 int icache_line_size;
1019
1020 /* Those resources are used during exception processing */
1021 /* CPU model definition */
1022 target_ulong msr_mask;
1023 powerpc_mmu_t mmu_model;
1024 powerpc_excp_t excp_model;
1025 powerpc_input_t bus_model;
1026 int bfd_mach;
1027 uint32_t flags;
1028 uint64_t insns_flags;
1029 uint64_t insns_flags2;
1030 #if defined(TARGET_PPC64)
1031 struct ppc_segment_page_sizes sps;
1032 #endif
1033
1034 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1035 uint64_t vpa_addr;
1036 uint64_t slb_shadow_addr, slb_shadow_size;
1037 uint64_t dtl_addr, dtl_size;
1038 #endif /* TARGET_PPC64 */
1039
1040 int error_code;
1041 uint32_t pending_interrupts;
1042 #if !defined(CONFIG_USER_ONLY)
1043 /* This is the IRQ controller, which is implementation dependent
1044 * and only relevant when emulating a complete machine.
1045 */
1046 uint32_t irq_input_state;
1047 void **irq_inputs;
1048 /* Exception vectors */
1049 target_ulong excp_vectors[POWERPC_EXCP_NB];
1050 target_ulong excp_prefix;
1051 target_ulong hreset_excp_prefix;
1052 target_ulong ivor_mask;
1053 target_ulong ivpr_mask;
1054 target_ulong hreset_vector;
1055 hwaddr mpic_iack;
1056 /* true when the external proxy facility mode is enabled */
1057 bool mpic_proxy;
1058 #endif
1059
1060 /* Those resources are used only during code translation */
1061 /* opcode handlers */
1062 opc_handler_t *opcodes[0x40];
1063
1064 /* Those resources are used only in QEMU core */
1065 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1066 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1067 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1068
1069 /* Power management */
1070 int (*check_pow)(CPUPPCState *env);
1071
1072 #if !defined(CONFIG_USER_ONLY)
1073 void *load_info; /* Holds boot loading state. */
1074 #endif
1075
1076 /* booke timers */
1077
1078 /* Specifies bit locations of the Time Base used to signal a fixed timer
1079 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1080 *
1081 * 0 selects the least significant bit.
1082 * 63 selects the most significant bit.
1083 */
1084 uint8_t fit_period[4];
1085 uint8_t wdt_period[4];
1086 };
1087
1088 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1089 do { \
1090 env->fit_period[0] = (a_); \
1091 env->fit_period[1] = (b_); \
1092 env->fit_period[2] = (c_); \
1093 env->fit_period[3] = (d_); \
1094 } while (0)
1095
1096 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1097 do { \
1098 env->wdt_period[0] = (a_); \
1099 env->wdt_period[1] = (b_); \
1100 env->wdt_period[2] = (c_); \
1101 env->wdt_period[3] = (d_); \
1102 } while (0)
1103
1104 #if !defined(CONFIG_USER_ONLY)
1105 /* Context used internally during MMU translations */
1106 typedef struct mmu_ctx_t mmu_ctx_t;
1107 struct mmu_ctx_t {
1108 hwaddr raddr; /* Real address */
1109 hwaddr eaddr; /* Effective address */
1110 int prot; /* Protection bits */
1111 hwaddr hash[2]; /* Pagetable hash values */
1112 target_ulong ptem; /* Virtual segment ID | API */
1113 int key; /* Access key */
1114 int nx; /* Non-execute area */
1115 };
1116 #endif
1117
1118 #include "cpu-qom.h"
1119
1120 /*****************************************************************************/
1121 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1122 void ppc_translate_init(void);
1123 int cpu_ppc_exec (CPUPPCState *s);
1124 /* you can call this signal handler from your SIGBUS and SIGSEGV
1125 signal handlers to inform the virtual CPU of exceptions. non zero
1126 is returned if the signal was handled by the virtual CPU. */
1127 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1128 void *puc);
1129 int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
1130 int mmu_idx);
1131 #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
1132 void ppc_hw_interrupt (CPUPPCState *env);
1133
1134 #if !defined(CONFIG_USER_ONLY)
1135 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1136 #if defined(TARGET_PPC64)
1137 int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
1138 #endif /* defined(TARGET_PPC64) */
1139 #endif /* !defined(CONFIG_USER_ONLY) */
1140 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1141
1142 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1143
1144 /* Time-base and decrementer management */
1145 #ifndef NO_CPU_IO_DEFS
1146 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1147 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1148 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1149 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1150 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1151 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1152 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1153 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1154 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1155 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1156 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1157 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1158 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1159 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1160 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1161 #if !defined(CONFIG_USER_ONLY)
1162 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1163 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1164 target_ulong load_40x_pit (CPUPPCState *env);
1165 void store_40x_pit (CPUPPCState *env, target_ulong val);
1166 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1167 void store_40x_sler (CPUPPCState *env, uint32_t val);
1168 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1169 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1170 int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
1171 hwaddr *raddrp, target_ulong address,
1172 uint32_t pid);
1173 void ppc_tlb_invalidate_all (CPUPPCState *env);
1174 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1175 #endif
1176 #endif
1177
1178 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1179
1180 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1181 {
1182 uint64_t gprv;
1183
1184 gprv = env->gpr[gprn];
1185 #if !defined(TARGET_PPC64)
1186 if (env->flags & POWERPC_FLAG_SPE) {
1187 /* If the CPU implements the SPE extension, we have to get the
1188 * high bits of the GPR from the gprh storage area
1189 */
1190 gprv &= 0xFFFFFFFFULL;
1191 gprv |= (uint64_t)env->gprh[gprn] << 32;
1192 }
1193 #endif
1194
1195 return gprv;
1196 }
1197
1198 /* Device control registers */
1199 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1200 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1201
1202 static inline CPUPPCState *cpu_init(const char *cpu_model)
1203 {
1204 PowerPCCPU *cpu = cpu_ppc_init(cpu_model);
1205 if (cpu == NULL) {
1206 return NULL;
1207 }
1208 return &cpu->env;
1209 }
1210
1211 #define cpu_exec cpu_ppc_exec
1212 #define cpu_gen_code cpu_ppc_gen_code
1213 #define cpu_signal_handler cpu_ppc_signal_handler
1214 #define cpu_list ppc_cpu_list
1215
1216 #define CPU_SAVE_VERSION 4
1217
1218 /* MMU modes definitions */
1219 #define MMU_MODE0_SUFFIX _user
1220 #define MMU_MODE1_SUFFIX _kernel
1221 #define MMU_MODE2_SUFFIX _hypv
1222 #define MMU_USER_IDX 0
1223 static inline int cpu_mmu_index (CPUPPCState *env)
1224 {
1225 return env->mmu_idx;
1226 }
1227
1228 #if defined(CONFIG_USER_ONLY)
1229 static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)
1230 {
1231 if (newsp)
1232 env->gpr[1] = newsp;
1233 env->gpr[3] = 0;
1234 }
1235 #endif
1236
1237 #include "exec/cpu-all.h"
1238
1239 /*****************************************************************************/
1240 /* CRF definitions */
1241 #define CRF_LT 3
1242 #define CRF_GT 2
1243 #define CRF_EQ 1
1244 #define CRF_SO 0
1245 #define CRF_CH (1 << CRF_LT)
1246 #define CRF_CL (1 << CRF_GT)
1247 #define CRF_CH_OR_CL (1 << CRF_EQ)
1248 #define CRF_CH_AND_CL (1 << CRF_SO)
1249
1250 /* XER definitions */
1251 #define XER_SO 31
1252 #define XER_OV 30
1253 #define XER_CA 29
1254 #define XER_CMP 8
1255 #define XER_BC 0
1256 #define xer_so (env->so)
1257 #define xer_ov (env->ov)
1258 #define xer_ca (env->ca)
1259 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1260 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1261
1262 /* SPR definitions */
1263 #define SPR_MQ (0x000)
1264 #define SPR_XER (0x001)
1265 #define SPR_601_VRTCU (0x004)
1266 #define SPR_601_VRTCL (0x005)
1267 #define SPR_601_UDECR (0x006)
1268 #define SPR_LR (0x008)
1269 #define SPR_CTR (0x009)
1270 #define SPR_DSCR (0x011)
1271 #define SPR_DSISR (0x012)
1272 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1273 #define SPR_601_RTCU (0x014)
1274 #define SPR_601_RTCL (0x015)
1275 #define SPR_DECR (0x016)
1276 #define SPR_SDR1 (0x019)
1277 #define SPR_SRR0 (0x01A)
1278 #define SPR_SRR1 (0x01B)
1279 #define SPR_CFAR (0x01C)
1280 #define SPR_AMR (0x01D)
1281 #define SPR_BOOKE_PID (0x030)
1282 #define SPR_BOOKE_DECAR (0x036)
1283 #define SPR_BOOKE_CSRR0 (0x03A)
1284 #define SPR_BOOKE_CSRR1 (0x03B)
1285 #define SPR_BOOKE_DEAR (0x03D)
1286 #define SPR_BOOKE_ESR (0x03E)
1287 #define SPR_BOOKE_IVPR (0x03F)
1288 #define SPR_MPC_EIE (0x050)
1289 #define SPR_MPC_EID (0x051)
1290 #define SPR_MPC_NRI (0x052)
1291 #define SPR_CTRL (0x088)
1292 #define SPR_MPC_CMPA (0x090)
1293 #define SPR_MPC_CMPB (0x091)
1294 #define SPR_MPC_CMPC (0x092)
1295 #define SPR_MPC_CMPD (0x093)
1296 #define SPR_MPC_ECR (0x094)
1297 #define SPR_MPC_DER (0x095)
1298 #define SPR_MPC_COUNTA (0x096)
1299 #define SPR_MPC_COUNTB (0x097)
1300 #define SPR_UCTRL (0x098)
1301 #define SPR_MPC_CMPE (0x098)
1302 #define SPR_MPC_CMPF (0x099)
1303 #define SPR_MPC_CMPG (0x09A)
1304 #define SPR_MPC_CMPH (0x09B)
1305 #define SPR_MPC_LCTRL1 (0x09C)
1306 #define SPR_MPC_LCTRL2 (0x09D)
1307 #define SPR_MPC_ICTRL (0x09E)
1308 #define SPR_MPC_BAR (0x09F)
1309 #define SPR_VRSAVE (0x100)
1310 #define SPR_USPRG0 (0x100)
1311 #define SPR_USPRG1 (0x101)
1312 #define SPR_USPRG2 (0x102)
1313 #define SPR_USPRG3 (0x103)
1314 #define SPR_USPRG4 (0x104)
1315 #define SPR_USPRG5 (0x105)
1316 #define SPR_USPRG6 (0x106)
1317 #define SPR_USPRG7 (0x107)
1318 #define SPR_VTBL (0x10C)
1319 #define SPR_VTBU (0x10D)
1320 #define SPR_SPRG0 (0x110)
1321 #define SPR_SPRG1 (0x111)
1322 #define SPR_SPRG2 (0x112)
1323 #define SPR_SPRG3 (0x113)
1324 #define SPR_SPRG4 (0x114)
1325 #define SPR_SCOMC (0x114)
1326 #define SPR_SPRG5 (0x115)
1327 #define SPR_SCOMD (0x115)
1328 #define SPR_SPRG6 (0x116)
1329 #define SPR_SPRG7 (0x117)
1330 #define SPR_ASR (0x118)
1331 #define SPR_EAR (0x11A)
1332 #define SPR_TBL (0x11C)
1333 #define SPR_TBU (0x11D)
1334 #define SPR_TBU40 (0x11E)
1335 #define SPR_SVR (0x11E)
1336 #define SPR_BOOKE_PIR (0x11E)
1337 #define SPR_PVR (0x11F)
1338 #define SPR_HSPRG0 (0x130)
1339 #define SPR_BOOKE_DBSR (0x130)
1340 #define SPR_HSPRG1 (0x131)
1341 #define SPR_HDSISR (0x132)
1342 #define SPR_HDAR (0x133)
1343 #define SPR_BOOKE_EPCR (0x133)
1344 #define SPR_SPURR (0x134)
1345 #define SPR_BOOKE_DBCR0 (0x134)
1346 #define SPR_IBCR (0x135)
1347 #define SPR_PURR (0x135)
1348 #define SPR_BOOKE_DBCR1 (0x135)
1349 #define SPR_DBCR (0x136)
1350 #define SPR_HDEC (0x136)
1351 #define SPR_BOOKE_DBCR2 (0x136)
1352 #define SPR_HIOR (0x137)
1353 #define SPR_MBAR (0x137)
1354 #define SPR_RMOR (0x138)
1355 #define SPR_BOOKE_IAC1 (0x138)
1356 #define SPR_HRMOR (0x139)
1357 #define SPR_BOOKE_IAC2 (0x139)
1358 #define SPR_HSRR0 (0x13A)
1359 #define SPR_BOOKE_IAC3 (0x13A)
1360 #define SPR_HSRR1 (0x13B)
1361 #define SPR_BOOKE_IAC4 (0x13B)
1362 #define SPR_LPCR (0x13C)
1363 #define SPR_BOOKE_DAC1 (0x13C)
1364 #define SPR_LPIDR (0x13D)
1365 #define SPR_DABR2 (0x13D)
1366 #define SPR_BOOKE_DAC2 (0x13D)
1367 #define SPR_BOOKE_DVC1 (0x13E)
1368 #define SPR_BOOKE_DVC2 (0x13F)
1369 #define SPR_BOOKE_TSR (0x150)
1370 #define SPR_BOOKE_TCR (0x154)
1371 #define SPR_BOOKE_TLB0PS (0x158)
1372 #define SPR_BOOKE_TLB1PS (0x159)
1373 #define SPR_BOOKE_TLB2PS (0x15A)
1374 #define SPR_BOOKE_TLB3PS (0x15B)
1375 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1376 #define SPR_BOOKE_IVOR0 (0x190)
1377 #define SPR_BOOKE_IVOR1 (0x191)
1378 #define SPR_BOOKE_IVOR2 (0x192)
1379 #define SPR_BOOKE_IVOR3 (0x193)
1380 #define SPR_BOOKE_IVOR4 (0x194)
1381 #define SPR_BOOKE_IVOR5 (0x195)
1382 #define SPR_BOOKE_IVOR6 (0x196)
1383 #define SPR_BOOKE_IVOR7 (0x197)
1384 #define SPR_BOOKE_IVOR8 (0x198)
1385 #define SPR_BOOKE_IVOR9 (0x199)
1386 #define SPR_BOOKE_IVOR10 (0x19A)
1387 #define SPR_BOOKE_IVOR11 (0x19B)
1388 #define SPR_BOOKE_IVOR12 (0x19C)
1389 #define SPR_BOOKE_IVOR13 (0x19D)
1390 #define SPR_BOOKE_IVOR14 (0x19E)
1391 #define SPR_BOOKE_IVOR15 (0x19F)
1392 #define SPR_BOOKE_IVOR38 (0x1B0)
1393 #define SPR_BOOKE_IVOR39 (0x1B1)
1394 #define SPR_BOOKE_IVOR40 (0x1B2)
1395 #define SPR_BOOKE_IVOR41 (0x1B3)
1396 #define SPR_BOOKE_IVOR42 (0x1B4)
1397 #define SPR_BOOKE_SPEFSCR (0x200)
1398 #define SPR_Exxx_BBEAR (0x201)
1399 #define SPR_Exxx_BBTAR (0x202)
1400 #define SPR_Exxx_L1CFG0 (0x203)
1401 #define SPR_Exxx_NPIDR (0x205)
1402 #define SPR_ATBL (0x20E)
1403 #define SPR_ATBU (0x20F)
1404 #define SPR_IBAT0U (0x210)
1405 #define SPR_BOOKE_IVOR32 (0x210)
1406 #define SPR_RCPU_MI_GRA (0x210)
1407 #define SPR_IBAT0L (0x211)
1408 #define SPR_BOOKE_IVOR33 (0x211)
1409 #define SPR_IBAT1U (0x212)
1410 #define SPR_BOOKE_IVOR34 (0x212)
1411 #define SPR_IBAT1L (0x213)
1412 #define SPR_BOOKE_IVOR35 (0x213)
1413 #define SPR_IBAT2U (0x214)
1414 #define SPR_BOOKE_IVOR36 (0x214)
1415 #define SPR_IBAT2L (0x215)
1416 #define SPR_BOOKE_IVOR37 (0x215)
1417 #define SPR_IBAT3U (0x216)
1418 #define SPR_IBAT3L (0x217)
1419 #define SPR_DBAT0U (0x218)
1420 #define SPR_RCPU_L2U_GRA (0x218)
1421 #define SPR_DBAT0L (0x219)
1422 #define SPR_DBAT1U (0x21A)
1423 #define SPR_DBAT1L (0x21B)
1424 #define SPR_DBAT2U (0x21C)
1425 #define SPR_DBAT2L (0x21D)
1426 #define SPR_DBAT3U (0x21E)
1427 #define SPR_DBAT3L (0x21F)
1428 #define SPR_IBAT4U (0x230)
1429 #define SPR_RPCU_BBCMCR (0x230)
1430 #define SPR_MPC_IC_CST (0x230)
1431 #define SPR_Exxx_CTXCR (0x230)
1432 #define SPR_IBAT4L (0x231)
1433 #define SPR_MPC_IC_ADR (0x231)
1434 #define SPR_Exxx_DBCR3 (0x231)
1435 #define SPR_IBAT5U (0x232)
1436 #define SPR_MPC_IC_DAT (0x232)
1437 #define SPR_Exxx_DBCNT (0x232)
1438 #define SPR_IBAT5L (0x233)
1439 #define SPR_IBAT6U (0x234)
1440 #define SPR_IBAT6L (0x235)
1441 #define SPR_IBAT7U (0x236)
1442 #define SPR_IBAT7L (0x237)
1443 #define SPR_DBAT4U (0x238)
1444 #define SPR_RCPU_L2U_MCR (0x238)
1445 #define SPR_MPC_DC_CST (0x238)
1446 #define SPR_Exxx_ALTCTXCR (0x238)
1447 #define SPR_DBAT4L (0x239)
1448 #define SPR_MPC_DC_ADR (0x239)
1449 #define SPR_DBAT5U (0x23A)
1450 #define SPR_BOOKE_MCSRR0 (0x23A)
1451 #define SPR_MPC_DC_DAT (0x23A)
1452 #define SPR_DBAT5L (0x23B)
1453 #define SPR_BOOKE_MCSRR1 (0x23B)
1454 #define SPR_DBAT6U (0x23C)
1455 #define SPR_BOOKE_MCSR (0x23C)
1456 #define SPR_DBAT6L (0x23D)
1457 #define SPR_Exxx_MCAR (0x23D)
1458 #define SPR_DBAT7U (0x23E)
1459 #define SPR_BOOKE_DSRR0 (0x23E)
1460 #define SPR_DBAT7L (0x23F)
1461 #define SPR_BOOKE_DSRR1 (0x23F)
1462 #define SPR_BOOKE_SPRG8 (0x25C)
1463 #define SPR_BOOKE_SPRG9 (0x25D)
1464 #define SPR_BOOKE_MAS0 (0x270)
1465 #define SPR_BOOKE_MAS1 (0x271)
1466 #define SPR_BOOKE_MAS2 (0x272)
1467 #define SPR_BOOKE_MAS3 (0x273)
1468 #define SPR_BOOKE_MAS4 (0x274)
1469 #define SPR_BOOKE_MAS5 (0x275)
1470 #define SPR_BOOKE_MAS6 (0x276)
1471 #define SPR_BOOKE_PID1 (0x279)
1472 #define SPR_BOOKE_PID2 (0x27A)
1473 #define SPR_MPC_DPDR (0x280)
1474 #define SPR_MPC_IMMR (0x288)
1475 #define SPR_BOOKE_TLB0CFG (0x2B0)
1476 #define SPR_BOOKE_TLB1CFG (0x2B1)
1477 #define SPR_BOOKE_TLB2CFG (0x2B2)
1478 #define SPR_BOOKE_TLB3CFG (0x2B3)
1479 #define SPR_BOOKE_EPR (0x2BE)
1480 #define SPR_PERF0 (0x300)
1481 #define SPR_RCPU_MI_RBA0 (0x300)
1482 #define SPR_MPC_MI_CTR (0x300)
1483 #define SPR_PERF1 (0x301)
1484 #define SPR_RCPU_MI_RBA1 (0x301)
1485 #define SPR_PERF2 (0x302)
1486 #define SPR_RCPU_MI_RBA2 (0x302)
1487 #define SPR_MPC_MI_AP (0x302)
1488 #define SPR_PERF3 (0x303)
1489 #define SPR_RCPU_MI_RBA3 (0x303)
1490 #define SPR_MPC_MI_EPN (0x303)
1491 #define SPR_PERF4 (0x304)
1492 #define SPR_PERF5 (0x305)
1493 #define SPR_MPC_MI_TWC (0x305)
1494 #define SPR_PERF6 (0x306)
1495 #define SPR_MPC_MI_RPN (0x306)
1496 #define SPR_PERF7 (0x307)
1497 #define SPR_PERF8 (0x308)
1498 #define SPR_RCPU_L2U_RBA0 (0x308)
1499 #define SPR_MPC_MD_CTR (0x308)
1500 #define SPR_PERF9 (0x309)
1501 #define SPR_RCPU_L2U_RBA1 (0x309)
1502 #define SPR_MPC_MD_CASID (0x309)
1503 #define SPR_PERFA (0x30A)
1504 #define SPR_RCPU_L2U_RBA2 (0x30A)
1505 #define SPR_MPC_MD_AP (0x30A)
1506 #define SPR_PERFB (0x30B)
1507 #define SPR_RCPU_L2U_RBA3 (0x30B)
1508 #define SPR_MPC_MD_EPN (0x30B)
1509 #define SPR_PERFC (0x30C)
1510 #define SPR_MPC_MD_TWB (0x30C)
1511 #define SPR_PERFD (0x30D)
1512 #define SPR_MPC_MD_TWC (0x30D)
1513 #define SPR_PERFE (0x30E)
1514 #define SPR_MPC_MD_RPN (0x30E)
1515 #define SPR_PERFF (0x30F)
1516 #define SPR_MPC_MD_TW (0x30F)
1517 #define SPR_UPERF0 (0x310)
1518 #define SPR_UPERF1 (0x311)
1519 #define SPR_UPERF2 (0x312)
1520 #define SPR_UPERF3 (0x313)
1521 #define SPR_UPERF4 (0x314)
1522 #define SPR_UPERF5 (0x315)
1523 #define SPR_UPERF6 (0x316)
1524 #define SPR_UPERF7 (0x317)
1525 #define SPR_UPERF8 (0x318)
1526 #define SPR_UPERF9 (0x319)
1527 #define SPR_UPERFA (0x31A)
1528 #define SPR_UPERFB (0x31B)
1529 #define SPR_UPERFC (0x31C)
1530 #define SPR_UPERFD (0x31D)
1531 #define SPR_UPERFE (0x31E)
1532 #define SPR_UPERFF (0x31F)
1533 #define SPR_RCPU_MI_RA0 (0x320)
1534 #define SPR_MPC_MI_DBCAM (0x320)
1535 #define SPR_RCPU_MI_RA1 (0x321)
1536 #define SPR_MPC_MI_DBRAM0 (0x321)
1537 #define SPR_RCPU_MI_RA2 (0x322)
1538 #define SPR_MPC_MI_DBRAM1 (0x322)
1539 #define SPR_RCPU_MI_RA3 (0x323)
1540 #define SPR_RCPU_L2U_RA0 (0x328)
1541 #define SPR_MPC_MD_DBCAM (0x328)
1542 #define SPR_RCPU_L2U_RA1 (0x329)
1543 #define SPR_MPC_MD_DBRAM0 (0x329)
1544 #define SPR_RCPU_L2U_RA2 (0x32A)
1545 #define SPR_MPC_MD_DBRAM1 (0x32A)
1546 #define SPR_RCPU_L2U_RA3 (0x32B)
1547 #define SPR_440_INV0 (0x370)
1548 #define SPR_440_INV1 (0x371)
1549 #define SPR_440_INV2 (0x372)
1550 #define SPR_440_INV3 (0x373)
1551 #define SPR_440_ITV0 (0x374)
1552 #define SPR_440_ITV1 (0x375)
1553 #define SPR_440_ITV2 (0x376)
1554 #define SPR_440_ITV3 (0x377)
1555 #define SPR_440_CCR1 (0x378)
1556 #define SPR_DCRIPR (0x37B)
1557 #define SPR_PPR (0x380)
1558 #define SPR_750_GQR0 (0x390)
1559 #define SPR_440_DNV0 (0x390)
1560 #define SPR_750_GQR1 (0x391)
1561 #define SPR_440_DNV1 (0x391)
1562 #define SPR_750_GQR2 (0x392)
1563 #define SPR_440_DNV2 (0x392)
1564 #define SPR_750_GQR3 (0x393)
1565 #define SPR_440_DNV3 (0x393)
1566 #define SPR_750_GQR4 (0x394)
1567 #define SPR_440_DTV0 (0x394)
1568 #define SPR_750_GQR5 (0x395)
1569 #define SPR_440_DTV1 (0x395)
1570 #define SPR_750_GQR6 (0x396)
1571 #define SPR_440_DTV2 (0x396)
1572 #define SPR_750_GQR7 (0x397)
1573 #define SPR_440_DTV3 (0x397)
1574 #define SPR_750_THRM4 (0x398)
1575 #define SPR_750CL_HID2 (0x398)
1576 #define SPR_440_DVLIM (0x398)
1577 #define SPR_750_WPAR (0x399)
1578 #define SPR_440_IVLIM (0x399)
1579 #define SPR_750_DMAU (0x39A)
1580 #define SPR_750_DMAL (0x39B)
1581 #define SPR_440_RSTCFG (0x39B)
1582 #define SPR_BOOKE_DCDBTRL (0x39C)
1583 #define SPR_BOOKE_DCDBTRH (0x39D)
1584 #define SPR_BOOKE_ICDBTRL (0x39E)
1585 #define SPR_BOOKE_ICDBTRH (0x39F)
1586 #define SPR_UMMCR2 (0x3A0)
1587 #define SPR_UPMC5 (0x3A1)
1588 #define SPR_UPMC6 (0x3A2)
1589 #define SPR_UBAMR (0x3A7)
1590 #define SPR_UMMCR0 (0x3A8)
1591 #define SPR_UPMC1 (0x3A9)
1592 #define SPR_UPMC2 (0x3AA)
1593 #define SPR_USIAR (0x3AB)
1594 #define SPR_UMMCR1 (0x3AC)
1595 #define SPR_UPMC3 (0x3AD)
1596 #define SPR_UPMC4 (0x3AE)
1597 #define SPR_USDA (0x3AF)
1598 #define SPR_40x_ZPR (0x3B0)
1599 #define SPR_BOOKE_MAS7 (0x3B0)
1600 #define SPR_MMCR2 (0x3B0)
1601 #define SPR_PMC5 (0x3B1)
1602 #define SPR_40x_PID (0x3B1)
1603 #define SPR_PMC6 (0x3B2)
1604 #define SPR_440_MMUCR (0x3B2)
1605 #define SPR_4xx_CCR0 (0x3B3)
1606 #define SPR_BOOKE_EPLC (0x3B3)
1607 #define SPR_405_IAC3 (0x3B4)
1608 #define SPR_BOOKE_EPSC (0x3B4)
1609 #define SPR_405_IAC4 (0x3B5)
1610 #define SPR_405_DVC1 (0x3B6)
1611 #define SPR_405_DVC2 (0x3B7)
1612 #define SPR_BAMR (0x3B7)
1613 #define SPR_MMCR0 (0x3B8)
1614 #define SPR_PMC1 (0x3B9)
1615 #define SPR_40x_SGR (0x3B9)
1616 #define SPR_PMC2 (0x3BA)
1617 #define SPR_40x_DCWR (0x3BA)
1618 #define SPR_SIAR (0x3BB)
1619 #define SPR_405_SLER (0x3BB)
1620 #define SPR_MMCR1 (0x3BC)
1621 #define SPR_405_SU0R (0x3BC)
1622 #define SPR_401_SKR (0x3BC)
1623 #define SPR_PMC3 (0x3BD)
1624 #define SPR_405_DBCR1 (0x3BD)
1625 #define SPR_PMC4 (0x3BE)
1626 #define SPR_SDA (0x3BF)
1627 #define SPR_403_VTBL (0x3CC)
1628 #define SPR_403_VTBU (0x3CD)
1629 #define SPR_DMISS (0x3D0)
1630 #define SPR_DCMP (0x3D1)
1631 #define SPR_HASH1 (0x3D2)
1632 #define SPR_HASH2 (0x3D3)
1633 #define SPR_BOOKE_ICDBDR (0x3D3)
1634 #define SPR_TLBMISS (0x3D4)
1635 #define SPR_IMISS (0x3D4)
1636 #define SPR_40x_ESR (0x3D4)
1637 #define SPR_PTEHI (0x3D5)
1638 #define SPR_ICMP (0x3D5)
1639 #define SPR_40x_DEAR (0x3D5)
1640 #define SPR_PTELO (0x3D6)
1641 #define SPR_RPA (0x3D6)
1642 #define SPR_40x_EVPR (0x3D6)
1643 #define SPR_L3PM (0x3D7)
1644 #define SPR_403_CDBCR (0x3D7)
1645 #define SPR_L3ITCR0 (0x3D8)
1646 #define SPR_TCR (0x3D8)
1647 #define SPR_40x_TSR (0x3D8)
1648 #define SPR_IBR (0x3DA)
1649 #define SPR_40x_TCR (0x3DA)
1650 #define SPR_ESASRR (0x3DB)
1651 #define SPR_40x_PIT (0x3DB)
1652 #define SPR_403_TBL (0x3DC)
1653 #define SPR_403_TBU (0x3DD)
1654 #define SPR_SEBR (0x3DE)
1655 #define SPR_40x_SRR2 (0x3DE)
1656 #define SPR_SER (0x3DF)
1657 #define SPR_40x_SRR3 (0x3DF)
1658 #define SPR_L3OHCR (0x3E8)
1659 #define SPR_L3ITCR1 (0x3E9)
1660 #define SPR_L3ITCR2 (0x3EA)
1661 #define SPR_L3ITCR3 (0x3EB)
1662 #define SPR_HID0 (0x3F0)
1663 #define SPR_40x_DBSR (0x3F0)
1664 #define SPR_HID1 (0x3F1)
1665 #define SPR_IABR (0x3F2)
1666 #define SPR_40x_DBCR0 (0x3F2)
1667 #define SPR_601_HID2 (0x3F2)
1668 #define SPR_Exxx_L1CSR0 (0x3F2)
1669 #define SPR_ICTRL (0x3F3)
1670 #define SPR_HID2 (0x3F3)
1671 #define SPR_750CL_HID4 (0x3F3)
1672 #define SPR_Exxx_L1CSR1 (0x3F3)
1673 #define SPR_440_DBDR (0x3F3)
1674 #define SPR_LDSTDB (0x3F4)
1675 #define SPR_750_TDCL (0x3F4)
1676 #define SPR_40x_IAC1 (0x3F4)
1677 #define SPR_MMUCSR0 (0x3F4)
1678 #define SPR_DABR (0x3F5)
1679 #define DABR_MASK (~(target_ulong)0x7)
1680 #define SPR_Exxx_BUCSR (0x3F5)
1681 #define SPR_40x_IAC2 (0x3F5)
1682 #define SPR_601_HID5 (0x3F5)
1683 #define SPR_40x_DAC1 (0x3F6)
1684 #define SPR_MSSCR0 (0x3F6)
1685 #define SPR_970_HID5 (0x3F6)
1686 #define SPR_MSSSR0 (0x3F7)
1687 #define SPR_MSSCR1 (0x3F7)
1688 #define SPR_DABRX (0x3F7)
1689 #define SPR_40x_DAC2 (0x3F7)
1690 #define SPR_MMUCFG (0x3F7)
1691 #define SPR_LDSTCR (0x3F8)
1692 #define SPR_L2PMCR (0x3F8)
1693 #define SPR_750FX_HID2 (0x3F8)
1694 #define SPR_Exxx_L1FINV0 (0x3F8)
1695 #define SPR_L2CR (0x3F9)
1696 #define SPR_L3CR (0x3FA)
1697 #define SPR_750_TDCH (0x3FA)
1698 #define SPR_IABR2 (0x3FA)
1699 #define SPR_40x_DCCR (0x3FA)
1700 #define SPR_ICTC (0x3FB)
1701 #define SPR_40x_ICCR (0x3FB)
1702 #define SPR_THRM1 (0x3FC)
1703 #define SPR_403_PBL1 (0x3FC)
1704 #define SPR_SP (0x3FD)
1705 #define SPR_THRM2 (0x3FD)
1706 #define SPR_403_PBU1 (0x3FD)
1707 #define SPR_604_HID13 (0x3FD)
1708 #define SPR_LT (0x3FE)
1709 #define SPR_THRM3 (0x3FE)
1710 #define SPR_RCPU_FPECR (0x3FE)
1711 #define SPR_403_PBL2 (0x3FE)
1712 #define SPR_PIR (0x3FF)
1713 #define SPR_403_PBU2 (0x3FF)
1714 #define SPR_601_HID15 (0x3FF)
1715 #define SPR_604_HID15 (0x3FF)
1716 #define SPR_E500_SVR (0x3FF)
1717
1718 /* Disable MAS Interrupt Updates for Hypervisor */
1719 #define EPCR_DMIUH (1 << 22)
1720 /* Disable Guest TLB Management Instructions */
1721 #define EPCR_DGTMI (1 << 23)
1722 /* Guest Interrupt Computation Mode */
1723 #define EPCR_GICM (1 << 24)
1724 /* Interrupt Computation Mode */
1725 #define EPCR_ICM (1 << 25)
1726 /* Disable Embedded Hypervisor Debug */
1727 #define EPCR_DUVD (1 << 26)
1728 /* Instruction Storage Interrupt Directed to Guest State */
1729 #define EPCR_ISIGS (1 << 27)
1730 /* Data Storage Interrupt Directed to Guest State */
1731 #define EPCR_DSIGS (1 << 28)
1732 /* Instruction TLB Error Interrupt Directed to Guest State */
1733 #define EPCR_ITLBGS (1 << 29)
1734 /* Data TLB Error Interrupt Directed to Guest State */
1735 #define EPCR_DTLBGS (1 << 30)
1736 /* External Input Interrupt Directed to Guest State */
1737 #define EPCR_EXTGS (1 << 31)
1738
1739 /*****************************************************************************/
1740 /* PowerPC Instructions types definitions */
1741 enum {
1742 PPC_NONE = 0x0000000000000000ULL,
1743 /* PowerPC base instructions set */
1744 PPC_INSNS_BASE = 0x0000000000000001ULL,
1745 /* integer operations instructions */
1746 #define PPC_INTEGER PPC_INSNS_BASE
1747 /* flow control instructions */
1748 #define PPC_FLOW PPC_INSNS_BASE
1749 /* virtual memory instructions */
1750 #define PPC_MEM PPC_INSNS_BASE
1751 /* ld/st with reservation instructions */
1752 #define PPC_RES PPC_INSNS_BASE
1753 /* spr/msr access instructions */
1754 #define PPC_MISC PPC_INSNS_BASE
1755 /* Deprecated instruction sets */
1756 /* Original POWER instruction set */
1757 PPC_POWER = 0x0000000000000002ULL,
1758 /* POWER2 instruction set extension */
1759 PPC_POWER2 = 0x0000000000000004ULL,
1760 /* Power RTC support */
1761 PPC_POWER_RTC = 0x0000000000000008ULL,
1762 /* Power-to-PowerPC bridge (601) */
1763 PPC_POWER_BR = 0x0000000000000010ULL,
1764 /* 64 bits PowerPC instruction set */
1765 PPC_64B = 0x0000000000000020ULL,
1766 /* New 64 bits extensions (PowerPC 2.0x) */
1767 PPC_64BX = 0x0000000000000040ULL,
1768 /* 64 bits hypervisor extensions */
1769 PPC_64H = 0x0000000000000080ULL,
1770 /* New wait instruction (PowerPC 2.0x) */
1771 PPC_WAIT = 0x0000000000000100ULL,
1772 /* Time base mftb instruction */
1773 PPC_MFTB = 0x0000000000000200ULL,
1774
1775 /* Fixed-point unit extensions */
1776 /* PowerPC 602 specific */
1777 PPC_602_SPEC = 0x0000000000000400ULL,
1778 /* isel instruction */
1779 PPC_ISEL = 0x0000000000000800ULL,
1780 /* popcntb instruction */
1781 PPC_POPCNTB = 0x0000000000001000ULL,
1782 /* string load / store */
1783 PPC_STRING = 0x0000000000002000ULL,
1784
1785 /* Floating-point unit extensions */
1786 /* Optional floating point instructions */
1787 PPC_FLOAT = 0x0000000000010000ULL,
1788 /* New floating-point extensions (PowerPC 2.0x) */
1789 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1790 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1791 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1792 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1793 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1794 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1795 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1796
1797 /* Vector/SIMD extensions */
1798 /* Altivec support */
1799 PPC_ALTIVEC = 0x0000000001000000ULL,
1800 /* PowerPC 2.03 SPE extension */
1801 PPC_SPE = 0x0000000002000000ULL,
1802 /* PowerPC 2.03 SPE single-precision floating-point extension */
1803 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1804 /* PowerPC 2.03 SPE double-precision floating-point extension */
1805 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1806
1807 /* Optional memory control instructions */
1808 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1809 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1810 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1811 /* sync instruction */
1812 PPC_MEM_SYNC = 0x0000000080000000ULL,
1813 /* eieio instruction */
1814 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1815
1816 /* Cache control instructions */
1817 PPC_CACHE = 0x0000000200000000ULL,
1818 /* icbi instruction */
1819 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1820 /* dcbz instruction */
1821 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1822 /* dcba instruction */
1823 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1824 /* Freescale cache locking instructions */
1825 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1826
1827 /* MMU related extensions */
1828 /* external control instructions */
1829 PPC_EXTERN = 0x0000010000000000ULL,
1830 /* segment register access instructions */
1831 PPC_SEGMENT = 0x0000020000000000ULL,
1832 /* PowerPC 6xx TLB management instructions */
1833 PPC_6xx_TLB = 0x0000040000000000ULL,
1834 /* PowerPC 74xx TLB management instructions */
1835 PPC_74xx_TLB = 0x0000080000000000ULL,
1836 /* PowerPC 40x TLB management instructions */
1837 PPC_40x_TLB = 0x0000100000000000ULL,
1838 /* segment register access instructions for PowerPC 64 "bridge" */
1839 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1840 /* SLB management */
1841 PPC_SLBI = 0x0000400000000000ULL,
1842
1843 /* Embedded PowerPC dedicated instructions */
1844 PPC_WRTEE = 0x0001000000000000ULL,
1845 /* PowerPC 40x exception model */
1846 PPC_40x_EXCP = 0x0002000000000000ULL,
1847 /* PowerPC 405 Mac instructions */
1848 PPC_405_MAC = 0x0004000000000000ULL,
1849 /* PowerPC 440 specific instructions */
1850 PPC_440_SPEC = 0x0008000000000000ULL,
1851 /* BookE (embedded) PowerPC specification */
1852 PPC_BOOKE = 0x0010000000000000ULL,
1853 /* mfapidi instruction */
1854 PPC_MFAPIDI = 0x0020000000000000ULL,
1855 /* tlbiva instruction */
1856 PPC_TLBIVA = 0x0040000000000000ULL,
1857 /* tlbivax instruction */
1858 PPC_TLBIVAX = 0x0080000000000000ULL,
1859 /* PowerPC 4xx dedicated instructions */
1860 PPC_4xx_COMMON = 0x0100000000000000ULL,
1861 /* PowerPC 40x ibct instructions */
1862 PPC_40x_ICBT = 0x0200000000000000ULL,
1863 /* rfmci is not implemented in all BookE PowerPC */
1864 PPC_RFMCI = 0x0400000000000000ULL,
1865 /* rfdi instruction */
1866 PPC_RFDI = 0x0800000000000000ULL,
1867 /* DCR accesses */
1868 PPC_DCR = 0x1000000000000000ULL,
1869 /* DCR extended accesse */
1870 PPC_DCRX = 0x2000000000000000ULL,
1871 /* user-mode DCR access, implemented in PowerPC 460 */
1872 PPC_DCRUX = 0x4000000000000000ULL,
1873 /* popcntw and popcntd instructions */
1874 PPC_POPCNTWD = 0x8000000000000000ULL,
1875
1876 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1877 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1878 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1879 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1880 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1881 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1882 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1883 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1884 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1885 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1886 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1887 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1888 | PPC_CACHE | PPC_CACHE_ICBI \
1889 | PPC_CACHE_DCBZ \
1890 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1891 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1892 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1893 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1894 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1895 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1896 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1897 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1898 | PPC_POPCNTWD)
1899
1900 /* extended type values */
1901
1902 /* BookE 2.06 PowerPC specification */
1903 PPC2_BOOKE206 = 0x0000000000000001ULL,
1904 /* VSX (extensions to Altivec / VMX) */
1905 PPC2_VSX = 0x0000000000000002ULL,
1906 /* Decimal Floating Point (DFP) */
1907 PPC2_DFP = 0x0000000000000004ULL,
1908 /* Embedded.Processor Control */
1909 PPC2_PRCNTL = 0x0000000000000008ULL,
1910 /* Byte-reversed, indexed, double-word load and store */
1911 PPC2_DBRX = 0x0000000000000010ULL,
1912
1913 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX)
1914 };
1915
1916 /*****************************************************************************/
1917 /* Memory access type :
1918 * may be needed for precise access rights control and precise exceptions.
1919 */
1920 enum {
1921 /* 1 bit to define user level / supervisor access */
1922 ACCESS_USER = 0x00,
1923 ACCESS_SUPER = 0x01,
1924 /* Type of instruction that generated the access */
1925 ACCESS_CODE = 0x10, /* Code fetch access */
1926 ACCESS_INT = 0x20, /* Integer load/store access */
1927 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1928 ACCESS_RES = 0x40, /* load/store with reservation */
1929 ACCESS_EXT = 0x50, /* external access */
1930 ACCESS_CACHE = 0x60, /* Cache manipulation */
1931 };
1932
1933 /* Hardware interruption sources:
1934 * all those exception can be raised simulteaneously
1935 */
1936 /* Input pins definitions */
1937 enum {
1938 /* 6xx bus input pins */
1939 PPC6xx_INPUT_HRESET = 0,
1940 PPC6xx_INPUT_SRESET = 1,
1941 PPC6xx_INPUT_CKSTP_IN = 2,
1942 PPC6xx_INPUT_MCP = 3,
1943 PPC6xx_INPUT_SMI = 4,
1944 PPC6xx_INPUT_INT = 5,
1945 PPC6xx_INPUT_TBEN = 6,
1946 PPC6xx_INPUT_WAKEUP = 7,
1947 PPC6xx_INPUT_NB,
1948 };
1949
1950 enum {
1951 /* Embedded PowerPC input pins */
1952 PPCBookE_INPUT_HRESET = 0,
1953 PPCBookE_INPUT_SRESET = 1,
1954 PPCBookE_INPUT_CKSTP_IN = 2,
1955 PPCBookE_INPUT_MCP = 3,
1956 PPCBookE_INPUT_SMI = 4,
1957 PPCBookE_INPUT_INT = 5,
1958 PPCBookE_INPUT_CINT = 6,
1959 PPCBookE_INPUT_NB,
1960 };
1961
1962 enum {
1963 /* PowerPC E500 input pins */
1964 PPCE500_INPUT_RESET_CORE = 0,
1965 PPCE500_INPUT_MCK = 1,
1966 PPCE500_INPUT_CINT = 3,
1967 PPCE500_INPUT_INT = 4,
1968 PPCE500_INPUT_DEBUG = 6,
1969 PPCE500_INPUT_NB,
1970 };
1971
1972 enum {
1973 /* PowerPC 40x input pins */
1974 PPC40x_INPUT_RESET_CORE = 0,
1975 PPC40x_INPUT_RESET_CHIP = 1,
1976 PPC40x_INPUT_RESET_SYS = 2,
1977 PPC40x_INPUT_CINT = 3,
1978 PPC40x_INPUT_INT = 4,
1979 PPC40x_INPUT_HALT = 5,
1980 PPC40x_INPUT_DEBUG = 6,
1981 PPC40x_INPUT_NB,
1982 };
1983
1984 enum {
1985 /* RCPU input pins */
1986 PPCRCPU_INPUT_PORESET = 0,
1987 PPCRCPU_INPUT_HRESET = 1,
1988 PPCRCPU_INPUT_SRESET = 2,
1989 PPCRCPU_INPUT_IRQ0 = 3,
1990 PPCRCPU_INPUT_IRQ1 = 4,
1991 PPCRCPU_INPUT_IRQ2 = 5,
1992 PPCRCPU_INPUT_IRQ3 = 6,
1993 PPCRCPU_INPUT_IRQ4 = 7,
1994 PPCRCPU_INPUT_IRQ5 = 8,
1995 PPCRCPU_INPUT_IRQ6 = 9,
1996 PPCRCPU_INPUT_IRQ7 = 10,
1997 PPCRCPU_INPUT_NB,
1998 };
1999
2000 #if defined(TARGET_PPC64)
2001 enum {
2002 /* PowerPC 970 input pins */
2003 PPC970_INPUT_HRESET = 0,
2004 PPC970_INPUT_SRESET = 1,
2005 PPC970_INPUT_CKSTP = 2,
2006 PPC970_INPUT_TBEN = 3,
2007 PPC970_INPUT_MCP = 4,
2008 PPC970_INPUT_INT = 5,
2009 PPC970_INPUT_THINT = 6,
2010 PPC970_INPUT_NB,
2011 };
2012
2013 enum {
2014 /* POWER7 input pins */
2015 POWER7_INPUT_INT = 0,
2016 /* POWER7 probably has other inputs, but we don't care about them
2017 * for any existing machine. We can wire these up when we need
2018 * them */
2019 POWER7_INPUT_NB,
2020 };
2021 #endif
2022
2023 /* Hardware exceptions definitions */
2024 enum {
2025 /* External hardware exception sources */
2026 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2027 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2028 PPC_INTERRUPT_MCK, /* Machine check exception */
2029 PPC_INTERRUPT_EXT, /* External interrupt */
2030 PPC_INTERRUPT_SMI, /* System management interrupt */
2031 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2032 PPC_INTERRUPT_DEBUG, /* External debug exception */
2033 PPC_INTERRUPT_THERM, /* Thermal exception */
2034 /* Internal hardware exception sources */
2035 PPC_INTERRUPT_DECR, /* Decrementer exception */
2036 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2037 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2038 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2039 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2040 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2041 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2042 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2043 };
2044
2045 /* CPU should be reset next, restart from scratch afterwards */
2046 #define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0
2047
2048 /*****************************************************************************/
2049
2050 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2051 {
2052 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2053 }
2054
2055 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2056 {
2057 env->so = (xer >> XER_SO) & 1;
2058 env->ov = (xer >> XER_OV) & 1;
2059 env->ca = (xer >> XER_CA) & 1;
2060 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2061 }
2062
2063 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2064 target_ulong *cs_base, int *flags)
2065 {
2066 *pc = env->nip;
2067 *cs_base = 0;
2068 *flags = env->hflags;
2069 }
2070
2071 static inline void cpu_set_tls(CPUPPCState *env, target_ulong newtls)
2072 {
2073 #if defined(TARGET_PPC64)
2074 /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
2075 binaries on PPC64 yet. */
2076 env->gpr[13] = newtls;
2077 #else
2078 env->gpr[2] = newtls;
2079 #endif
2080 }
2081
2082 #if !defined(CONFIG_USER_ONLY)
2083 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2084 {
2085 uintptr_t tlbml = (uintptr_t)tlbm;
2086 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2087
2088 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2089 }
2090
2091 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2092 {
2093 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2094 int r = tlbncfg & TLBnCFG_N_ENTRY;
2095 return r;
2096 }
2097
2098 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2099 {
2100 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2101 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2102 return r;
2103 }
2104
2105 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2106 {
2107 int id = booke206_tlbm_id(env, tlbm);
2108 int end = 0;
2109 int i;
2110
2111 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2112 end += booke206_tlb_size(env, i);
2113 if (id < end) {
2114 return i;
2115 }
2116 }
2117
2118 cpu_abort(env, "Unknown TLBe: %d\n", id);
2119 return 0;
2120 }
2121
2122 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2123 {
2124 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2125 int tlbid = booke206_tlbm_id(env, tlb);
2126 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2127 }
2128
2129 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2130 target_ulong ea, int way)
2131 {
2132 int r;
2133 uint32_t ways = booke206_tlb_ways(env, tlbn);
2134 int ways_bits = ffs(ways) - 1;
2135 int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2136 int i;
2137
2138 way &= ways - 1;
2139 ea >>= MAS2_EPN_SHIFT;
2140 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2141 r = (ea << ways_bits) | way;
2142
2143 if (r >= booke206_tlb_size(env, tlbn)) {
2144 return NULL;
2145 }
2146
2147 /* bump up to tlbn index */
2148 for (i = 0; i < tlbn; i++) {
2149 r += booke206_tlb_size(env, i);
2150 }
2151
2152 return &env->tlb.tlbm[r];
2153 }
2154
2155 /* returns bitmap of supported page sizes for a given TLB */
2156 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2157 {
2158 bool mav2 = false;
2159 uint32_t ret = 0;
2160
2161 if (mav2) {
2162 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2163 } else {
2164 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2165 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2166 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2167 int i;
2168 for (i = min; i <= max; i++) {
2169 ret |= (1 << (i << 1));
2170 }
2171 }
2172
2173 return ret;
2174 }
2175
2176 #endif
2177
2178 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2179 {
2180 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2181 return msr & (1ULL << MSR_CM);
2182 }
2183
2184 return msr & (1ULL << MSR_SF);
2185 }
2186
2187 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2188
2189 static inline bool cpu_has_work(CPUState *cpu)
2190 {
2191 PowerPCCPU *ppc_cpu = POWERPC_CPU(cpu);
2192 CPUPPCState *env = &ppc_cpu->env;
2193
2194 return msr_ee && (cpu->interrupt_request & CPU_INTERRUPT_HARD);
2195 }
2196
2197 #include "exec/exec-all.h"
2198
2199 static inline void cpu_pc_from_tb(CPUPPCState *env, TranslationBlock *tb)
2200 {
2201 env->nip = tb->pc;
2202 }
2203
2204 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2205
2206 #endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing