2 * PowerPC emulation cpu definitions for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #if !defined (__CPU_PPC_H__)
26 #if defined(TARGET_PPC64) || (HOST_LONG_BITS >= 64)
27 /* When using 64 bits temporary registers,
28 * we can use 64 bits GPR with no extra cost
33 #if defined (TARGET_PPC64)
34 typedef uint64_t ppc_gpr_t
;
35 #define TARGET_LONG_BITS 64
36 #define TARGET_GPR_BITS 64
37 #define REGX "%016" PRIx64
38 #elif defined(TARGET_PPCSPE)
39 /* e500v2 have 36 bits physical address space */
40 #define TARGET_PHYS_ADDR_BITS 64
41 /* GPR are 64 bits: used by vector extension */
42 typedef uint64_t ppc_gpr_t
;
43 #define TARGET_LONG_BITS 32
44 #define TARGET_GPR_BITS 64
45 #define REGX "%016" PRIx64
47 typedef uint32_t ppc_gpr_t
;
48 #define TARGET_LONG_BITS 32
49 #define TARGET_GPR_BITS 32
50 #define REGX "%08" PRIx32
55 #define ADDRX TARGET_FMT_lx
56 #define PADDRX TARGET_FMT_plx
60 #include "softfloat.h"
62 #define TARGET_HAS_ICE 1
64 #if defined (TARGET_PPC64)
65 #define ELF_MACHINE EM_PPC64
67 #define ELF_MACHINE EM_PPC
70 /* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
71 * have different cache line sizes
73 #define ICACHE_LINE_SIZE 32
74 #define DCACHE_LINE_SIZE 32
76 /* XXX: put this in a common place */
77 #define likely(x) __builtin_expect(!!(x), 1)
78 #define unlikely(x) __builtin_expect(!!(x), 0)
80 /*****************************************************************************/
81 /* PVR definitions for most known PowerPC */
83 /* PowerPC 401 cores */
84 CPU_PPC_401A1
= 0x00210000,
85 CPU_PPC_401B2
= 0x00220000,
86 CPU_PPC_401C2
= 0x00230000,
87 CPU_PPC_401D2
= 0x00240000,
88 CPU_PPC_401E2
= 0x00250000,
89 CPU_PPC_401F2
= 0x00260000,
90 CPU_PPC_401G2
= 0x00270000,
91 #define CPU_PPC_401 CPU_PPC_401G2
92 CPU_PPC_IOP480
= 0x40100000, /* 401B2 ? */
93 CPU_PPC_COBRA
= 0x10100000, /* IBM Processor for Network Resources */
94 /* PowerPC 403 cores */
95 CPU_PPC_403GA
= 0x00200011,
96 CPU_PPC_403GB
= 0x00200100,
97 CPU_PPC_403GC
= 0x00200200,
98 CPU_PPC_403GCX
= 0x00201400,
99 #define CPU_PPC_403 CPU_PPC_403GCX
100 /* PowerPC 405 cores */
101 CPU_PPC_405CR
= 0x40110145,
102 #define CPU_PPC_405GP CPU_PPC_405CR
103 CPU_PPC_405EP
= 0x51210950,
104 CPU_PPC_405GPR
= 0x50910951,
105 CPU_PPC_405D2
= 0x20010000,
106 CPU_PPC_405D4
= 0x41810000,
107 #define CPU_PPC_405 CPU_PPC_405D4
108 CPU_PPC_NPE405H
= 0x414100C0,
109 CPU_PPC_NPE405H2
= 0x41410140,
110 CPU_PPC_NPE405L
= 0x416100C0,
111 /* XXX: missing 405LP, LC77700 */
112 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
114 CPU_PPC_STB01000
= xxx
,
117 CPU_PPC_STB01010
= xxx
,
120 CPU_PPC_STB0210
= xxx
,
122 CPU_PPC_STB03
= 0x40310000,
124 CPU_PPC_STB043
= xxx
,
127 CPU_PPC_STB045
= xxx
,
129 CPU_PPC_STB25
= 0x51510950,
131 CPU_PPC_STB130
= xxx
,
134 CPU_PPC_X2VP4
= 0x20010820,
135 #define CPU_PPC_X2VP7 CPU_PPC_X2VP4
136 CPU_PPC_X2VP20
= 0x20010860,
137 #define CPU_PPC_X2VP50 CPU_PPC_X2VP20
138 /* PowerPC 440 cores */
139 CPU_PPC_440EP
= 0x422218D3,
140 #define CPU_PPC_440GR CPU_PPC_440EP
141 CPU_PPC_440GP
= 0x40120481,
142 CPU_PPC_440GX
= 0x51B21850,
143 CPU_PPC_440GXc
= 0x51B21892,
144 CPU_PPC_440GXf
= 0x51B21894,
145 CPU_PPC_440SP
= 0x53221850,
146 CPU_PPC_440SP2
= 0x53221891,
147 CPU_PPC_440SPE
= 0x53421890,
148 /* XXX: missing 440GRX */
149 /* PowerPC 460 cores - TODO */
150 /* PowerPC MPC 5xx cores */
151 CPU_PPC_5xx
= 0x00020020,
152 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
153 CPU_PPC_8xx
= 0x00500000,
154 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
155 CPU_PPC_82xx_HIP3
= 0x00810101,
156 CPU_PPC_82xx_HIP4
= 0x80811014,
157 CPU_PPC_827x
= 0x80822013,
159 CPU_PPC_e200
= 0x81120000,
160 CPU_PPC_e500v110
= 0x80200010,
161 CPU_PPC_e500v120
= 0x80200020,
162 CPU_PPC_e500v210
= 0x80210010,
163 CPU_PPC_e500v220
= 0x80210020,
164 #define CPU_PPC_e500 CPU_PPC_e500v220
165 CPU_PPC_e600
= 0x80040010,
166 /* PowerPC 6xx cores */
167 CPU_PPC_601
= 0x00010001,
168 CPU_PPC_602
= 0x00050100,
169 CPU_PPC_603
= 0x00030100,
170 CPU_PPC_603E
= 0x00060101,
171 CPU_PPC_603P
= 0x00070000,
172 CPU_PPC_603E7v
= 0x00070100,
173 CPU_PPC_603E7v2
= 0x00070201,
174 CPU_PPC_603E7
= 0x00070200,
175 CPU_PPC_603R
= 0x00071201,
176 CPU_PPC_G2
= 0x00810011,
177 CPU_PPC_G2H4
= 0x80811010,
178 CPU_PPC_G2gp
= 0x80821010,
179 CPU_PPC_G2ls
= 0x90810010,
180 CPU_PPC_G2LE
= 0x80820010,
181 CPU_PPC_G2LEgp
= 0x80822010,
182 CPU_PPC_G2LEls
= 0xA0822010,
183 CPU_PPC_604
= 0x00040000,
184 CPU_PPC_604E
= 0x00090100, /* Also 2110 & 2120 */
185 CPU_PPC_604R
= 0x000a0101,
186 /* PowerPC 74x/75x cores (aka G3) */
187 CPU_PPC_74x
= 0x00080000,
188 CPU_PPC_740E
= 0x00080100,
189 CPU_PPC_750E
= 0x00080200,
190 CPU_PPC_755_10
= 0x00083100,
191 CPU_PPC_755_11
= 0x00083101,
192 CPU_PPC_755_20
= 0x00083200,
193 CPU_PPC_755D
= 0x00083202,
194 CPU_PPC_755E
= 0x00083203,
195 #define CPU_PPC_755 CPU_PPC_755E
196 CPU_PPC_74xP
= 0x10080000,
197 CPU_PPC_750CXE21
= 0x00082201,
198 CPU_PPC_750CXE22
= 0x00082212,
199 CPU_PPC_750CXE23
= 0x00082203,
200 CPU_PPC_750CXE24
= 0x00082214,
201 CPU_PPC_750CXE24b
= 0x00083214,
202 CPU_PPC_750CXE31
= 0x00083211,
203 CPU_PPC_750CXE31b
= 0x00083311,
204 #define CPU_PPC_750CXE CPU_PPC_750CXE31b
205 CPU_PPC_750CXR
= 0x00083410,
206 CPU_PPC_750FX10
= 0x70000100,
207 CPU_PPC_750FX20
= 0x70000200,
208 CPU_PPC_750FX21
= 0x70000201,
209 CPU_PPC_750FX22
= 0x70000202,
210 CPU_PPC_750FX23
= 0x70000203,
211 #define CPU_PPC_750FX CPU_PPC_750FX23
212 CPU_PPC_750FL
= 0x700A0203,
213 CPU_PPC_750GX10
= 0x70020100,
214 CPU_PPC_750GX11
= 0x70020101,
215 CPU_PPC_750GX12
= 0x70020102,
216 #define CPU_PPC_750GX CPU_PPC_750GX12
217 CPU_PPC_750GL
= 0x70020102,
218 CPU_PPC_750L30
= 0x00088300,
219 CPU_PPC_750L32
= 0x00088302,
220 CPU_PPC_750CL
= 0x00087200,
221 /* PowerPC 74xx cores (aka G4) */
222 CPU_PPC_7400
= 0x000C0100,
223 CPU_PPC_7410C
= 0x800C1102,
224 CPU_PPC_7410D
= 0x800C1103,
225 CPU_PPC_7410E
= 0x800C1104,
226 CPU_PPC_7441
= 0x80000210,
227 CPU_PPC_7445
= 0x80010100,
228 CPU_PPC_7447
= 0x80020100,
229 CPU_PPC_7447A
= 0x80030101,
230 CPU_PPC_7448
= 0x80040100,
231 CPU_PPC_7450
= 0x80000200,
232 CPU_PPC_7450b
= 0x80000201,
233 CPU_PPC_7451
= 0x80000203,
234 CPU_PPC_7451G
= 0x80000210,
235 CPU_PPC_7455
= 0x80010201,
236 CPU_PPC_7455F
= 0x80010303,
237 CPU_PPC_7455G
= 0x80010304,
238 CPU_PPC_7457
= 0x80020101,
239 CPU_PPC_7457C
= 0x80020102,
240 CPU_PPC_7457A
= 0x80030000,
241 /* 64 bits PowerPC */
242 CPU_PPC_620
= 0x00140000,
243 CPU_PPC_630
= 0x00400000,
244 CPU_PPC_631
= 0x00410000,
245 CPU_PPC_POWER4
= 0x00350000,
246 CPU_PPC_POWER4P
= 0x00380000,
247 CPU_PPC_POWER5
= 0x003A0000,
248 CPU_PPC_POWER5P
= 0x003B0000,
249 CPU_PPC_970
= 0x00390000,
250 CPU_PPC_970FX10
= 0x00391100,
251 CPU_PPC_970FX20
= 0x003C0200,
252 CPU_PPC_970FX21
= 0x003C0201,
253 CPU_PPC_970FX30
= 0x003C0300,
254 CPU_PPC_970FX31
= 0x003C0301,
255 #define CPU_PPC_970FX CPU_PPC_970FX31
256 CPU_PPC_970MP10
= 0x00440100,
257 CPU_PPC_970MP11
= 0x00440101,
258 #define CPU_PPC_970MP CPU_PPC_970MP11
259 CPU_PPC_CELL10
= 0x00700100,
260 CPU_PPC_CELL20
= 0x00700400,
261 CPU_PPC_CELL30
= 0x00700500,
262 CPU_PPC_CELL31
= 0x00700501,
263 #define CPU_PPC_CELL32 CPU_PPC_CELL31
264 #define CPU_PPC_CELL CPU_PPC_CELL32
265 CPU_PPC_RS64
= 0x00330000,
266 CPU_PPC_RS64II
= 0x00340000,
267 CPU_PPC_RS64III
= 0x00360000,
268 CPU_PPC_RS64IV
= 0x00370000,
270 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
271 * POWER2 (RIOS2) & RSC2 (P2SC) here
281 /* System version register (used on MPC 8xxx) */
283 PPC_SVR_8540
= 0x80300000,
284 PPC_SVR_8541E
= 0x807A0010,
285 PPC_SVR_8543v10
= 0x80320010,
286 PPC_SVR_8543v11
= 0x80320011,
287 PPC_SVR_8543v20
= 0x80320020,
288 PPC_SVR_8543Ev10
= 0x803A0010,
289 PPC_SVR_8543Ev11
= 0x803A0011,
290 PPC_SVR_8543Ev20
= 0x803A0020,
291 PPC_SVR_8545
= 0x80310220,
292 PPC_SVR_8545E
= 0x80390220,
293 PPC_SVR_8547E
= 0x80390120,
294 PPC_SCR_8548v10
= 0x80310010,
295 PPC_SCR_8548v11
= 0x80310011,
296 PPC_SCR_8548v20
= 0x80310020,
297 PPC_SVR_8548Ev10
= 0x80390010,
298 PPC_SVR_8548Ev11
= 0x80390011,
299 PPC_SVR_8548Ev20
= 0x80390020,
300 PPC_SVR_8555E
= 0x80790010,
301 PPC_SVR_8560v10
= 0x80700010,
302 PPC_SVR_8560v20
= 0x80700020,
305 /*****************************************************************************/
306 /* Instruction types */
308 PPC_NONE
= 0x00000000,
309 /* integer operations instructions */
310 /* flow control instructions */
311 /* virtual memory instructions */
312 /* ld/st with reservation instructions */
313 /* cache control instructions */
314 /* spr/msr access instructions */
315 PPC_INSNS_BASE
= 0x0000000000000001ULL
,
316 #define PPC_INTEGER PPC_INSNS_BASE
317 #define PPC_FLOW PPC_INSNS_BASE
318 #define PPC_MEM PPC_INSNS_BASE
319 #define PPC_RES PPC_INSNS_BASE
320 #define PPC_CACHE PPC_INSNS_BASE
321 #define PPC_MISC PPC_INSNS_BASE
322 /* floating point operations instructions */
323 PPC_FLOAT
= 0x0000000000000002ULL
,
324 /* more floating point operations instructions */
325 PPC_FLOAT_EXT
= 0x0000000000000004ULL
,
326 /* external control instructions */
327 PPC_EXTERN
= 0x0000000000000008ULL
,
328 /* segment register access instructions */
329 PPC_SEGMENT
= 0x0000000000000010ULL
,
330 /* Optional cache control instructions */
331 PPC_CACHE_OPT
= 0x0000000000000020ULL
,
332 /* Optional floating point op instructions */
333 PPC_FLOAT_OPT
= 0x0000000000000040ULL
,
334 /* Optional memory control instructions */
335 PPC_MEM_TLBIA
= 0x0000000000000080ULL
,
336 PPC_MEM_TLBIE
= 0x0000000000000100ULL
,
337 PPC_MEM_TLBSYNC
= 0x0000000000000200ULL
,
339 PPC_MEM_SYNC
= 0x0000000000000400ULL
,
340 /* PowerPC 6xx TLB management instructions */
341 PPC_6xx_TLB
= 0x0000000000000800ULL
,
342 /* Altivec support */
343 PPC_ALTIVEC
= 0x0000000000001000ULL
,
344 /* Time base support */
345 PPC_TB
= 0x0000000000002000ULL
,
346 /* Embedded PowerPC dedicated instructions */
347 PPC_EMB_COMMON
= 0x0000000000004000ULL
,
348 /* PowerPC 40x exception model */
349 PPC_40x_EXCP
= 0x0000000000008000ULL
,
350 /* PowerPC 40x specific instructions */
351 PPC_40x_SPEC
= 0x0000000000010000ULL
,
352 /* PowerPC 405 Mac instructions */
353 PPC_405_MAC
= 0x0000000000020000ULL
,
354 /* PowerPC 440 specific instructions */
355 PPC_440_SPEC
= 0x0000000000040000ULL
,
356 /* Specific extensions */
357 /* Power-to-PowerPC bridge (601) */
358 PPC_POWER_BR
= 0x0000000000080000ULL
,
359 /* PowerPC 602 specific */
360 PPC_602_SPEC
= 0x0000000000100000ULL
,
361 /* Deprecated instructions */
362 /* Original POWER instruction set */
363 PPC_POWER
= 0x0000000000200000ULL
,
364 /* POWER2 instruction set extension */
365 PPC_POWER2
= 0x0000000000400000ULL
,
366 /* Power RTC support */
367 PPC_POWER_RTC
= 0x0000000000800000ULL
,
368 /* 64 bits PowerPC instructions */
369 /* 64 bits PowerPC instruction set */
370 PPC_64B
= 0x0000000001000000ULL
,
371 /* 64 bits hypervisor extensions */
372 PPC_64H
= 0x0000000002000000ULL
,
373 /* 64 bits PowerPC "bridge" features */
374 PPC_64_BRIDGE
= 0x0000000004000000ULL
,
375 /* BookE (embedded) PowerPC specification */
376 PPC_BOOKE
= 0x0000000008000000ULL
,
378 PPC_MEM_EIEIO
= 0x0000000010000000ULL
,
379 /* e500 vector instructions */
380 PPC_E500_VECTOR
= 0x0000000020000000ULL
,
381 /* PowerPC 4xx dedicated instructions */
382 PPC_4xx_COMMON
= 0x0000000040000000ULL
,
383 /* PowerPC 2.03 specification extensions */
384 PPC_203
= 0x0000000080000000ULL
,
385 /* PowerPC 2.03 SPE extension */
386 PPC_SPE
= 0x0000000100000000ULL
,
387 /* PowerPC 2.03 SPE floating-point extension */
388 PPC_SPEFPU
= 0x0000000200000000ULL
,
390 PPC_SLBI
= 0x0000000400000000ULL
,
393 /* CPU run-time flags (MMU and exception model) */
396 PPC_FLAGS_MMU_MASK
= 0x000000FF,
397 /* Standard 32 bits PowerPC MMU */
398 PPC_FLAGS_MMU_32B
= 0x00000000,
399 /* Standard 64 bits PowerPC MMU */
400 PPC_FLAGS_MMU_64B
= 0x00000001,
401 /* PowerPC 601 MMU */
402 PPC_FLAGS_MMU_601
= 0x00000002,
403 /* PowerPC 6xx MMU with software TLB */
404 PPC_FLAGS_MMU_SOFT_6xx
= 0x00000003,
405 /* PowerPC 4xx MMU with software TLB */
406 PPC_FLAGS_MMU_SOFT_4xx
= 0x00000004,
407 /* PowerPC 403 MMU */
408 PPC_FLAGS_MMU_403
= 0x00000005,
409 /* BookE FSL MMU model */
410 PPC_FLAGS_MMU_BOOKE_FSL
= 0x00000006,
411 /* BookE MMU model */
412 PPC_FLAGS_MMU_BOOKE
= 0x00000007,
413 /* 64 bits "bridge" PowerPC MMU */
414 PPC_FLAGS_MMU_64BRIDGE
= 0x00000008,
415 /* Exception model */
416 PPC_FLAGS_EXCP_MASK
= 0x0000FF00,
417 /* Standard PowerPC exception model */
418 PPC_FLAGS_EXCP_STD
= 0x00000000,
419 /* PowerPC 40x exception model */
420 PPC_FLAGS_EXCP_40x
= 0x00000100,
421 /* PowerPC 601 exception model */
422 PPC_FLAGS_EXCP_601
= 0x00000200,
423 /* PowerPC 602 exception model */
424 PPC_FLAGS_EXCP_602
= 0x00000300,
425 /* PowerPC 603 exception model */
426 PPC_FLAGS_EXCP_603
= 0x00000400,
427 /* PowerPC 604 exception model */
428 PPC_FLAGS_EXCP_604
= 0x00000500,
429 /* PowerPC 7x0 exception model */
430 PPC_FLAGS_EXCP_7x0
= 0x00000600,
431 /* PowerPC 7x5 exception model */
432 PPC_FLAGS_EXCP_7x5
= 0x00000700,
433 /* PowerPC 74xx exception model */
434 PPC_FLAGS_EXCP_74xx
= 0x00000800,
435 /* PowerPC 970 exception model */
436 PPC_FLAGS_EXCP_970
= 0x00000900,
437 /* BookE exception model */
438 PPC_FLAGS_EXCP_BOOKE
= 0x00000A00,
439 /* Input pins model */
440 PPC_FLAGS_INPUT_MASK
= 0x000F0000,
441 PPC_FLAGS_INPUT_6xx
= 0x00000000,
442 PPC_FLAGS_INPUT_BookE
= 0x00010000,
443 PPC_FLAGS_INPUT_40x
= 0x00020000,
444 PPC_FLAGS_INPUT_970
= 0x00030000,
447 #define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
448 #define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
449 #define PPC_INPUT(env) (env->flags & PPC_FLAGS_INPUT_MASK)
451 /*****************************************************************************/
452 /* Supported instruction set definitions */
453 /* This generates an empty opcode table... */
454 #define PPC_INSNS_TODO (PPC_NONE)
455 #define PPC_FLAGS_TODO (0x00000000)
457 /* PowerPC 40x instruction set */
458 #define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON)
460 #define PPC_INSNS_401 (PPC_INSNS_TODO)
461 #define PPC_FLAGS_401 (PPC_FLAGS_TODO)
463 #define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
464 PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \
466 #define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x | \
469 #define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
470 PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \
471 PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \
473 #define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
476 #define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
477 PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
478 #define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
479 PPC_FLAGS_INPUT_BookE)
480 /* Generic BookE PowerPC */
481 #define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
482 PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT)
483 #define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
484 PPC_FLAGS_INPUT_BookE)
486 #define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
487 PPC_CACHE_OPT | PPC_E500_VECTOR)
488 #define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
489 PPC_FLAGS_INPUT_BookE)
490 /* Non-embedded PowerPC */
491 #define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
492 PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
494 #define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
495 #define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601 | \
498 #define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
499 PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
500 #define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602 | \
503 #define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
504 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
505 #define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
508 #define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
509 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
510 #define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
513 #define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
514 PPC_MEM_TLBSYNC | PPC_TB)
515 #define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604 | \
517 /* PowerPC 740/750 (aka G3) */
518 #define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
519 PPC_MEM_TLBSYNC | PPC_TB)
520 #define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0 | \
522 /* PowerPC 745/755 */
523 #define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
524 PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
525 #define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5 | \
527 /* PowerPC 74xx (aka G4) */
528 #define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
529 PPC_MEM_TLBSYNC | PPC_TB)
530 #define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx | \
532 /* PowerPC 970 (aka G5) */
533 #define PPC_INSNS_970 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT | \
534 PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB | \
535 PPC_64B | PPC_64_BRIDGE | PPC_SLBI)
536 #define PPC_FLAGS_970 (PPC_FLAGS_MMU_64BRIDGE | PPC_FLAGS_EXCP_970 | \
539 /* Default PowerPC will be 604/970 */
540 #define PPC_INSNS_PPC32 PPC_INSNS_604
541 #define PPC_FLAGS_PPC32 PPC_FLAGS_604
542 #define PPC_INSNS_PPC64 PPC_INSNS_970
543 #define PPC_FLAGS_PPC64 PPC_FLAGS_970
544 #define PPC_INSNS_DEFAULT PPC_INSNS_604
545 #define PPC_FLAGS_DEFAULT PPC_FLAGS_604
546 typedef struct ppc_def_t ppc_def_t
;
548 /*****************************************************************************/
549 /* Types used to describe some PowerPC registers */
550 typedef struct CPUPPCState CPUPPCState
;
551 typedef struct opc_handler_t opc_handler_t
;
552 typedef struct ppc_tb_t ppc_tb_t
;
553 typedef struct ppc_spr_t ppc_spr_t
;
554 typedef struct ppc_dcr_t ppc_dcr_t
;
555 typedef struct ppc_avr_t ppc_avr_t
;
556 typedef union ppc_tlb_t ppc_tlb_t
;
558 /* SPR access micro-ops generations callbacks */
560 void (*uea_read
)(void *opaque
, int spr_num
);
561 void (*uea_write
)(void *opaque
, int spr_num
);
562 #if !defined(CONFIG_USER_ONLY)
563 void (*oea_read
)(void *opaque
, int spr_num
);
564 void (*oea_write
)(void *opaque
, int spr_num
);
566 const unsigned char *name
;
569 /* Altivec registers (128 bits) */
574 /* Software TLB cache */
575 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t
;
576 struct ppc6xx_tlb_t
{
582 typedef struct ppcemb_tlb_t ppcemb_tlb_t
;
583 struct ppcemb_tlb_t
{
584 target_phys_addr_t RPN
;
589 uint32_t attr
; /* Storage attributes */
597 /*****************************************************************************/
598 /* Machine state register bits definition */
599 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
600 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
601 #define MSR_HV 60 /* hypervisor state hflags */
602 #define MSR_CM 31 /* Computation mode for BookE hflags */
603 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
604 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
605 #define MSR_VR 25 /* altivec available hflags */
606 #define MSR_SPE 25 /* SPE enable for BookE hflags */
607 #define MSR_AP 23 /* Access privilege state on 602 hflags */
608 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
609 #define MSR_KEY 19 /* key bit on 603e */
610 #define MSR_POW 18 /* Power management */
611 #define MSR_WE 18 /* Wait state enable on embedded PowerPC */
612 #define MSR_TGPR 17 /* TGPR usage on 602/603 */
613 #define MSR_TLB 17 /* TLB update on ? */
614 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */
615 #define MSR_ILE 16 /* Interrupt little-endian mode */
616 #define MSR_EE 15 /* External interrupt enable */
617 #define MSR_PR 14 /* Problem state hflags */
618 #define MSR_FP 13 /* Floating point available hflags */
619 #define MSR_ME 12 /* Machine check interrupt enable */
620 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
621 #define MSR_SE 10 /* Single-step trace enable hflags */
622 #define MSR_DWE 10 /* Debug wait enable on 405 */
623 #define MSR_UBLE 10 /* User BTB lock enable on e500 */
624 #define MSR_BE 9 /* Branch trace enable hflags */
625 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */
626 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
627 #define MSR_AL 7 /* AL bit on POWER */
628 #define MSR_IP 6 /* Interrupt prefix */
629 #define MSR_IR 5 /* Instruction relocate */
630 #define MSR_IS 5 /* Instruction address space on embedded PowerPC */
631 #define MSR_DR 4 /* Data relocate */
632 #define MSR_DS 4 /* Data address space on embedded PowerPC */
633 #define MSR_PE 3 /* Protection enable on 403 */
634 #define MSR_EP 3 /* Exception prefix on 601 */
635 #define MSR_PX 2 /* Protection exclusive on 403 */
636 #define MSR_PMM 2 /* Performance monitor mark on POWER */
637 #define MSR_RI 1 /* Recoverable interrupt */
638 #define MSR_LE 0 /* Little-endian mode hflags */
639 #define msr_sf env->msr[MSR_SF]
640 #define msr_isf env->msr[MSR_ISF]
641 #define msr_hv env->msr[MSR_HV]
642 #define msr_cm env->msr[MSR_CM]
643 #define msr_icm env->msr[MSR_ICM]
644 #define msr_ucle env->msr[MSR_UCLE]
645 #define msr_vr env->msr[MSR_VR]
646 #define msr_spe env->msr[MSR_SPE]
647 #define msr_ap env->msr[MSR_AP]
648 #define msr_sa env->msr[MSR_SA]
649 #define msr_key env->msr[MSR_KEY]
650 #define msr_pow env->msr[MSR_POW]
651 #define msr_we env->msr[MSR_WE]
652 #define msr_tgpr env->msr[MSR_TGPR]
653 #define msr_tlb env->msr[MSR_TLB]
654 #define msr_ce env->msr[MSR_CE]
655 #define msr_ile env->msr[MSR_ILE]
656 #define msr_ee env->msr[MSR_EE]
657 #define msr_pr env->msr[MSR_PR]
658 #define msr_fp env->msr[MSR_FP]
659 #define msr_me env->msr[MSR_ME]
660 #define msr_fe0 env->msr[MSR_FE0]
661 #define msr_se env->msr[MSR_SE]
662 #define msr_dwe env->msr[MSR_DWE]
663 #define msr_uble env->msr[MSR_UBLE]
664 #define msr_be env->msr[MSR_BE]
665 #define msr_de env->msr[MSR_DE]
666 #define msr_fe1 env->msr[MSR_FE1]
667 #define msr_al env->msr[MSR_AL]
668 #define msr_ip env->msr[MSR_IP]
669 #define msr_ir env->msr[MSR_IR]
670 #define msr_is env->msr[MSR_IS]
671 #define msr_dr env->msr[MSR_DR]
672 #define msr_ds env->msr[MSR_DS]
673 #define msr_pe env->msr[MSR_PE]
674 #define msr_ep env->msr[MSR_EP]
675 #define msr_px env->msr[MSR_PX]
676 #define msr_pmm env->msr[MSR_PMM]
677 #define msr_ri env->msr[MSR_RI]
678 #define msr_le env->msr[MSR_LE]
680 /*****************************************************************************/
681 /* The whole PowerPC CPU context */
683 /* First are the most commonly used resources
684 * during translated code execution
686 #if TARGET_GPR_BITS > HOST_LONG_BITS
687 /* temporary fixed-point registers
688 * used to emulate 64 bits target on 32 bits hosts
690 target_ulong t0
, t1
, t2
;
692 ppc_avr_t t0_avr
, t1_avr
, t2_avr
;
694 /* general purpose registers */
700 /* condition register */
703 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
705 /* Reservation address */
706 target_ulong reserve
;
708 /* Those ones are used in supervisor mode only */
709 /* machine state register */
711 /* temporary general purpose registers */
712 ppc_gpr_t tgpr
[4]; /* Used to speed-up TLB assist handlers */
714 /* Floating point execution context */
715 /* temporary float registers */
719 float_status fp_status
;
720 /* floating point registers */
722 /* floating point status and control register */
727 int halted
; /* TRUE if the CPU is in suspend state */
729 int access_type
; /* when a memory exception occurs, the access
730 type is stored here */
733 /* Address space register */
735 /* segment registers */
740 target_ulong DBAT
[2][8];
741 target_ulong IBAT
[2][8];
743 /* Other registers */
744 /* Special purpose registers */
745 target_ulong spr
[1024];
746 /* Altivec registers */
751 float_status spe_status
;
754 /* Internal devices resources */
755 /* Time base and decrementer */
757 /* Device control registers */
760 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
761 int nb_tlb
; /* Total number of TLB */
762 int tlb_per_way
; /* Speed-up helper: used to avoid divisions at run time */
763 int nb_ways
; /* Number of ways in the TLB set */
764 int last_way
; /* Last used way used to allocate TLB in a LRU way */
765 int id_tlbs
; /* If 1, MMU has separated TLBs for instructions & data */
766 int nb_pids
; /* Number of available PID registers */
767 ppc_tlb_t
*tlb
; /* TLB is optional. Allocate them only if needed */
768 /* 403 dedicated access protection registers */
771 /* Those resources are used during exception processing */
772 /* CPU model definition */
778 int interrupt_request
;
779 uint32_t pending_interrupts
;
780 #if !defined(CONFIG_USER_ONLY)
781 /* This is the IRQ controller, which is implementation dependant
782 * and only relevant when emulating a complete machine.
784 uint32_t irq_input_state
;
788 /* Those resources are used only during code translation */
789 /* Next instruction pointer */
791 /* SPR translation callbacks */
792 ppc_spr_t spr_cb
[1024];
793 /* opcode handlers */
794 opc_handler_t
*opcodes
[0x40];
796 /* Those resources are used only in Qemu core */
798 int user_mode_only
; /* user mode only simulation */
801 /* Power management */
804 /* temporary hack to handle OSI calls (only used if non NULL) */
805 int (*osi_call
)(struct CPUPPCState
*env
);
808 /* Context used internally during MMU translations */
809 typedef struct mmu_ctx_t mmu_ctx_t
;
811 target_phys_addr_t raddr
; /* Real address */
812 int prot
; /* Protection bits */
813 target_phys_addr_t pg_addr
[2]; /* PTE tables base addresses */
814 target_ulong ptem
; /* Virtual segment ID | API */
815 int key
; /* Access key */
818 /*****************************************************************************/
819 CPUPPCState
*cpu_ppc_init(void);
820 int cpu_ppc_exec(CPUPPCState
*s
);
821 void cpu_ppc_close(CPUPPCState
*s
);
822 /* you can call this signal handler from your SIGBUS and SIGSEGV
823 signal handlers to inform the virtual CPU of exceptions. non zero
824 is returned if the signal was handled by the virtual CPU. */
825 int cpu_ppc_signal_handler(int host_signum
, void *pinfo
,
828 void do_interrupt (CPUPPCState
*env
);
829 void ppc_hw_interrupt (CPUPPCState
*env
);
830 void cpu_loop_exit(void);
832 void dump_stack (CPUPPCState
*env
);
834 #if !defined(CONFIG_USER_ONLY)
835 target_ulong
do_load_ibatu (CPUPPCState
*env
, int nr
);
836 target_ulong
do_load_ibatl (CPUPPCState
*env
, int nr
);
837 void do_store_ibatu (CPUPPCState
*env
, int nr
, target_ulong value
);
838 void do_store_ibatl (CPUPPCState
*env
, int nr
, target_ulong value
);
839 target_ulong
do_load_dbatu (CPUPPCState
*env
, int nr
);
840 target_ulong
do_load_dbatl (CPUPPCState
*env
, int nr
);
841 void do_store_dbatu (CPUPPCState
*env
, int nr
, target_ulong value
);
842 void do_store_dbatl (CPUPPCState
*env
, int nr
, target_ulong value
);
843 target_ulong
do_load_sdr1 (CPUPPCState
*env
);
844 void do_store_sdr1 (CPUPPCState
*env
, target_ulong value
);
845 #if defined(TARGET_PPC64)
846 target_ulong
ppc_load_asr (CPUPPCState
*env
);
847 void ppc_store_asr (CPUPPCState
*env
, target_ulong value
);
849 target_ulong
do_load_sr (CPUPPCState
*env
, int srnum
);
850 void do_store_sr (CPUPPCState
*env
, int srnum
, target_ulong value
);
852 uint32_t ppc_load_xer (CPUPPCState
*env
);
853 void ppc_store_xer (CPUPPCState
*env
, uint32_t value
);
854 target_ulong
do_load_msr (CPUPPCState
*env
);
855 void do_store_msr (CPUPPCState
*env
, target_ulong value
);
856 void ppc_store_msr_32 (CPUPPCState
*env
, uint32_t value
);
858 void do_compute_hflags (CPUPPCState
*env
);
859 void cpu_ppc_reset (void *opaque
);
860 CPUPPCState
*cpu_ppc_init (void);
861 void cpu_ppc_close(CPUPPCState
*env
);
863 int ppc_find_by_name (const unsigned char *name
, ppc_def_t
**def
);
864 int ppc_find_by_pvr (uint32_t apvr
, ppc_def_t
**def
);
865 void ppc_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...));
866 int cpu_ppc_register (CPUPPCState
*env
, ppc_def_t
*def
);
868 /* Time-base and decrementer management */
869 #ifndef NO_CPU_IO_DEFS
870 uint32_t cpu_ppc_load_tbl (CPUPPCState
*env
);
871 uint32_t cpu_ppc_load_tbu (CPUPPCState
*env
);
872 void cpu_ppc_store_tbu (CPUPPCState
*env
, uint32_t value
);
873 void cpu_ppc_store_tbl (CPUPPCState
*env
, uint32_t value
);
874 uint32_t cpu_ppc_load_decr (CPUPPCState
*env
);
875 void cpu_ppc_store_decr (CPUPPCState
*env
, uint32_t value
);
876 uint32_t cpu_ppc601_load_rtcl (CPUPPCState
*env
);
877 uint32_t cpu_ppc601_load_rtcu (CPUPPCState
*env
);
878 #if !defined(CONFIG_USER_ONLY)
879 void cpu_ppc601_store_rtcl (CPUPPCState
*env
, uint32_t value
);
880 void cpu_ppc601_store_rtcu (CPUPPCState
*env
, uint32_t value
);
881 target_ulong
load_40x_pit (CPUPPCState
*env
);
882 void store_40x_pit (CPUPPCState
*env
, target_ulong val
);
883 void store_booke_tcr (CPUPPCState
*env
, target_ulong val
);
884 void store_booke_tsr (CPUPPCState
*env
, target_ulong val
);
885 void ppc_tlb_invalidate_all (CPUPPCState
*env
);
889 /* Device control registers */
890 int ppc_dcr_read (ppc_dcr_t
*dcr_env
, int dcrn
, target_ulong
*valp
);
891 int ppc_dcr_write (ppc_dcr_t
*dcr_env
, int dcrn
, target_ulong val
);
893 #define TARGET_PAGE_BITS 12
896 /*****************************************************************************/
897 /* Registers definitions */
898 #define ugpr(n) (env->gpr[n])
905 #define xer_so env->xer[4]
906 #define xer_ov env->xer[6]
907 #define xer_ca env->xer[2]
908 #define xer_cmp env->xer[1]
909 #define xer_bc env->xer[0]
911 /* SPR definitions */
912 #define SPR_MQ (0x000)
913 #define SPR_XER (0x001)
914 #define SPR_601_VRTCU (0x004)
915 #define SPR_601_VRTCL (0x005)
916 #define SPR_601_UDECR (0x006)
917 #define SPR_LR (0x008)
918 #define SPR_CTR (0x009)
919 #define SPR_DSISR (0x012)
920 #define SPR_DAR (0x013)
921 #define SPR_601_RTCU (0x014)
922 #define SPR_601_RTCL (0x015)
923 #define SPR_DECR (0x016)
924 #define SPR_SDR1 (0x019)
925 #define SPR_SRR0 (0x01A)
926 #define SPR_SRR1 (0x01B)
927 #define SPR_BOOKE_PID (0x030)
928 #define SPR_BOOKE_DECAR (0x036)
929 #define SPR_BOOKE_CSRR0 (0x03A)
930 #define SPR_BOOKE_CSRR1 (0x03B)
931 #define SPR_BOOKE_DEAR (0x03D)
932 #define SPR_BOOKE_ESR (0x03E)
933 #define SPR_BOOKE_IVPR (0x03F)
934 #define SPR_8xx_EIE (0x050)
935 #define SPR_8xx_EID (0x051)
936 #define SPR_8xx_NRE (0x052)
937 #define SPR_58x_CMPA (0x090)
938 #define SPR_58x_CMPB (0x091)
939 #define SPR_58x_CMPC (0x092)
940 #define SPR_58x_CMPD (0x093)
941 #define SPR_58x_ICR (0x094)
942 #define SPR_58x_DER (0x094)
943 #define SPR_58x_COUNTA (0x096)
944 #define SPR_58x_COUNTB (0x097)
945 #define SPR_58x_CMPE (0x098)
946 #define SPR_58x_CMPF (0x099)
947 #define SPR_58x_CMPG (0x09A)
948 #define SPR_58x_CMPH (0x09B)
949 #define SPR_58x_LCTRL1 (0x09C)
950 #define SPR_58x_LCTRL2 (0x09D)
951 #define SPR_58x_ICTRL (0x09E)
952 #define SPR_58x_BAR (0x09F)
953 #define SPR_VRSAVE (0x100)
954 #define SPR_USPRG0 (0x100)
955 #define SPR_USPRG1 (0x101)
956 #define SPR_USPRG2 (0x102)
957 #define SPR_USPRG3 (0x103)
958 #define SPR_USPRG4 (0x104)
959 #define SPR_USPRG5 (0x105)
960 #define SPR_USPRG6 (0x106)
961 #define SPR_USPRG7 (0x107)
962 #define SPR_VTBL (0x10C)
963 #define SPR_VTBU (0x10D)
964 #define SPR_SPRG0 (0x110)
965 #define SPR_SPRG1 (0x111)
966 #define SPR_SPRG2 (0x112)
967 #define SPR_SPRG3 (0x113)
968 #define SPR_SPRG4 (0x114)
969 #define SPR_SCOMC (0x114)
970 #define SPR_SPRG5 (0x115)
971 #define SPR_SCOMD (0x115)
972 #define SPR_SPRG6 (0x116)
973 #define SPR_SPRG7 (0x117)
974 #define SPR_ASR (0x118)
975 #define SPR_EAR (0x11A)
976 #define SPR_TBL (0x11C)
977 #define SPR_TBU (0x11D)
978 #define SPR_SVR (0x11E)
979 #define SPR_BOOKE_PIR (0x11E)
980 #define SPR_PVR (0x11F)
981 #define SPR_HSPRG0 (0x130)
982 #define SPR_BOOKE_DBSR (0x130)
983 #define SPR_HSPRG1 (0x131)
984 #define SPR_BOOKE_DBCR0 (0x134)
985 #define SPR_IBCR (0x135)
986 #define SPR_BOOKE_DBCR1 (0x135)
987 #define SPR_DBCR (0x136)
988 #define SPR_HDEC (0x136)
989 #define SPR_BOOKE_DBCR2 (0x136)
990 #define SPR_HIOR (0x137)
991 #define SPR_MBAR (0x137)
992 #define SPR_RMOR (0x138)
993 #define SPR_BOOKE_IAC1 (0x138)
994 #define SPR_HRMOR (0x139)
995 #define SPR_BOOKE_IAC2 (0x139)
996 #define SPR_HSSR0 (0x13A)
997 #define SPR_BOOKE_IAC3 (0x13A)
998 #define SPR_HSSR1 (0x13B)
999 #define SPR_BOOKE_IAC4 (0x13B)
1000 #define SPR_LPCR (0x13C)
1001 #define SPR_BOOKE_DAC1 (0x13C)
1002 #define SPR_LPIDR (0x13D)
1003 #define SPR_DABR2 (0x13D)
1004 #define SPR_BOOKE_DAC2 (0x13D)
1005 #define SPR_BOOKE_DVC1 (0x13E)
1006 #define SPR_BOOKE_DVC2 (0x13F)
1007 #define SPR_BOOKE_TSR (0x150)
1008 #define SPR_BOOKE_TCR (0x154)
1009 #define SPR_BOOKE_IVOR0 (0x190)
1010 #define SPR_BOOKE_IVOR1 (0x191)
1011 #define SPR_BOOKE_IVOR2 (0x192)
1012 #define SPR_BOOKE_IVOR3 (0x193)
1013 #define SPR_BOOKE_IVOR4 (0x194)
1014 #define SPR_BOOKE_IVOR5 (0x195)
1015 #define SPR_BOOKE_IVOR6 (0x196)
1016 #define SPR_BOOKE_IVOR7 (0x197)
1017 #define SPR_BOOKE_IVOR8 (0x198)
1018 #define SPR_BOOKE_IVOR9 (0x199)
1019 #define SPR_BOOKE_IVOR10 (0x19A)
1020 #define SPR_BOOKE_IVOR11 (0x19B)
1021 #define SPR_BOOKE_IVOR12 (0x19C)
1022 #define SPR_BOOKE_IVOR13 (0x19D)
1023 #define SPR_BOOKE_IVOR14 (0x19E)
1024 #define SPR_BOOKE_IVOR15 (0x19F)
1025 #define SPR_E500_SPEFSCR (0x200)
1026 #define SPR_E500_BBEAR (0x201)
1027 #define SPR_E500_BBTAR (0x202)
1028 #define SPR_BOOKE_ATBL (0x20E)
1029 #define SPR_BOOKE_ATBU (0x20F)
1030 #define SPR_IBAT0U (0x210)
1031 #define SPR_BOOKE_IVOR32 (0x210)
1032 #define SPR_IBAT0L (0x211)
1033 #define SPR_BOOKE_IVOR33 (0x211)
1034 #define SPR_IBAT1U (0x212)
1035 #define SPR_BOOKE_IVOR34 (0x212)
1036 #define SPR_IBAT1L (0x213)
1037 #define SPR_BOOKE_IVOR35 (0x213)
1038 #define SPR_IBAT2U (0x214)
1039 #define SPR_BOOKE_IVOR36 (0x214)
1040 #define SPR_IBAT2L (0x215)
1041 #define SPR_E500_L1CFG0 (0x215)
1042 #define SPR_BOOKE_IVOR37 (0x215)
1043 #define SPR_IBAT3U (0x216)
1044 #define SPR_E500_L1CFG1 (0x216)
1045 #define SPR_IBAT3L (0x217)
1046 #define SPR_DBAT0U (0x218)
1047 #define SPR_DBAT0L (0x219)
1048 #define SPR_DBAT1U (0x21A)
1049 #define SPR_DBAT1L (0x21B)
1050 #define SPR_DBAT2U (0x21C)
1051 #define SPR_DBAT2L (0x21D)
1052 #define SPR_DBAT3U (0x21E)
1053 #define SPR_DBAT3L (0x21F)
1054 #define SPR_IBAT4U (0x230)
1055 #define SPR_IBAT4L (0x231)
1056 #define SPR_IBAT5U (0x232)
1057 #define SPR_IBAT5L (0x233)
1058 #define SPR_IBAT6U (0x234)
1059 #define SPR_IBAT6L (0x235)
1060 #define SPR_IBAT7U (0x236)
1061 #define SPR_IBAT7L (0x237)
1062 #define SPR_DBAT4U (0x238)
1063 #define SPR_DBAT4L (0x239)
1064 #define SPR_DBAT5U (0x23A)
1065 #define SPR_BOOKE_MCSRR0 (0x23A)
1066 #define SPR_DBAT5L (0x23B)
1067 #define SPR_BOOKE_MCSRR1 (0x23B)
1068 #define SPR_DBAT6U (0x23C)
1069 #define SPR_BOOKE_MCSR (0x23C)
1070 #define SPR_DBAT6L (0x23D)
1071 #define SPR_E500_MCAR (0x23D)
1072 #define SPR_DBAT7U (0x23E)
1073 #define SPR_BOOKE_DSRR0 (0x23E)
1074 #define SPR_DBAT7L (0x23F)
1075 #define SPR_BOOKE_DSRR1 (0x23F)
1076 #define SPR_BOOKE_SPRG8 (0x25C)
1077 #define SPR_BOOKE_SPRG9 (0x25D)
1078 #define SPR_BOOKE_MAS0 (0x270)
1079 #define SPR_BOOKE_MAS1 (0x271)
1080 #define SPR_BOOKE_MAS2 (0x272)
1081 #define SPR_BOOKE_MAS3 (0x273)
1082 #define SPR_BOOKE_MAS4 (0x274)
1083 #define SPR_BOOKE_MAS6 (0x276)
1084 #define SPR_BOOKE_PID1 (0x279)
1085 #define SPR_BOOKE_PID2 (0x27A)
1086 #define SPR_BOOKE_TLB0CFG (0x2B0)
1087 #define SPR_BOOKE_TLB1CFG (0x2B1)
1088 #define SPR_BOOKE_TLB2CFG (0x2B2)
1089 #define SPR_BOOKE_TLB3CFG (0x2B3)
1090 #define SPR_BOOKE_EPR (0x2BE)
1091 #define SPR_440_INV0 (0x370)
1092 #define SPR_440_INV1 (0x371)
1093 #define SPR_440_INV2 (0x372)
1094 #define SPR_440_INV3 (0x373)
1095 #define SPR_440_IVT0 (0x374)
1096 #define SPR_440_IVT1 (0x375)
1097 #define SPR_440_IVT2 (0x376)
1098 #define SPR_440_IVT3 (0x377)
1099 #define SPR_440_DNV0 (0x390)
1100 #define SPR_440_DNV1 (0x391)
1101 #define SPR_440_DNV2 (0x392)
1102 #define SPR_440_DNV3 (0x393)
1103 #define SPR_440_DVT0 (0x394)
1104 #define SPR_440_DVT1 (0x395)
1105 #define SPR_440_DVT2 (0x396)
1106 #define SPR_440_DVT3 (0x397)
1107 #define SPR_440_DVLIM (0x398)
1108 #define SPR_440_IVLIM (0x399)
1109 #define SPR_440_RSTCFG (0x39B)
1110 #define SPR_BOOKE_DCBTRL (0x39C)
1111 #define SPR_BOOKE_DCBTRH (0x39D)
1112 #define SPR_BOOKE_ICBTRL (0x39E)
1113 #define SPR_BOOKE_ICBTRH (0x39F)
1114 #define SPR_UMMCR0 (0x3A8)
1115 #define SPR_UPMC1 (0x3A9)
1116 #define SPR_UPMC2 (0x3AA)
1117 #define SPR_USIA (0x3AB)
1118 #define SPR_UMMCR1 (0x3AC)
1119 #define SPR_UPMC3 (0x3AD)
1120 #define SPR_UPMC4 (0x3AE)
1121 #define SPR_USDA (0x3AF)
1122 #define SPR_40x_ZPR (0x3B0)
1123 #define SPR_BOOKE_MAS7 (0x3B0)
1124 #define SPR_40x_PID (0x3B1)
1125 #define SPR_440_MMUCR (0x3B2)
1126 #define SPR_4xx_CCR0 (0x3B3)
1127 #define SPR_BOOKE_EPLC (0x3B3)
1128 #define SPR_405_IAC3 (0x3B4)
1129 #define SPR_BOOKE_EPSC (0x3B4)
1130 #define SPR_405_IAC4 (0x3B5)
1131 #define SPR_405_DVC1 (0x3B6)
1132 #define SPR_405_DVC2 (0x3B7)
1133 #define SPR_MMCR0 (0x3B8)
1134 #define SPR_PMC1 (0x3B9)
1135 #define SPR_40x_SGR (0x3B9)
1136 #define SPR_PMC2 (0x3BA)
1137 #define SPR_40x_DCWR (0x3BA)
1138 #define SPR_SIA (0x3BB)
1139 #define SPR_405_SLER (0x3BB)
1140 #define SPR_MMCR1 (0x3BC)
1141 #define SPR_405_SU0R (0x3BC)
1142 #define SPR_PMC3 (0x3BD)
1143 #define SPR_405_DBCR1 (0x3BD)
1144 #define SPR_PMC4 (0x3BE)
1145 #define SPR_SDA (0x3BF)
1146 #define SPR_403_VTBL (0x3CC)
1147 #define SPR_403_VTBU (0x3CD)
1148 #define SPR_DMISS (0x3D0)
1149 #define SPR_DCMP (0x3D1)
1150 #define SPR_HASH1 (0x3D2)
1151 #define SPR_HASH2 (0x3D3)
1152 #define SPR_BOOKE_ICBDR (0x3D3)
1153 #define SPR_IMISS (0x3D4)
1154 #define SPR_40x_ESR (0x3D4)
1155 #define SPR_ICMP (0x3D5)
1156 #define SPR_40x_DEAR (0x3D5)
1157 #define SPR_RPA (0x3D6)
1158 #define SPR_40x_EVPR (0x3D6)
1159 #define SPR_403_CDBCR (0x3D7)
1160 #define SPR_TCR (0x3D8)
1161 #define SPR_40x_TSR (0x3D8)
1162 #define SPR_IBR (0x3DA)
1163 #define SPR_40x_TCR (0x3DA)
1164 #define SPR_ESASR (0x3DB)
1165 #define SPR_40x_PIT (0x3DB)
1166 #define SPR_403_TBL (0x3DC)
1167 #define SPR_403_TBU (0x3DD)
1168 #define SPR_SEBR (0x3DE)
1169 #define SPR_40x_SRR2 (0x3DE)
1170 #define SPR_SER (0x3DF)
1171 #define SPR_40x_SRR3 (0x3DF)
1172 #define SPR_HID0 (0x3F0)
1173 #define SPR_40x_DBSR (0x3F0)
1174 #define SPR_HID1 (0x3F1)
1175 #define SPR_IABR (0x3F2)
1176 #define SPR_40x_DBCR0 (0x3F2)
1177 #define SPR_601_HID2 (0x3F2)
1178 #define SPR_E500_L1CSR0 (0x3F2)
1179 #define SPR_HID2 (0x3F3)
1180 #define SPR_E500_L1CSR1 (0x3F3)
1181 #define SPR_440_DBDR (0x3F3)
1182 #define SPR_40x_IAC1 (0x3F4)
1183 #define SPR_BOOKE_MMUCSR0 (0x3F4)
1184 #define SPR_DABR (0x3F5)
1185 #define DABR_MASK (~(target_ulong)0x7)
1186 #define SPR_E500_BUCSR (0x3F5)
1187 #define SPR_40x_IAC2 (0x3F5)
1188 #define SPR_601_HID5 (0x3F5)
1189 #define SPR_40x_DAC1 (0x3F6)
1190 #define SPR_40x_DAC2 (0x3F7)
1191 #define SPR_BOOKE_MMUCFG (0x3F7)
1192 #define SPR_L2PM (0x3F8)
1193 #define SPR_750_HID2 (0x3F8)
1194 #define SPR_L2CR (0x3F9)
1195 #define SPR_IABR2 (0x3FA)
1196 #define SPR_40x_DCCR (0x3FA)
1197 #define SPR_ICTC (0x3FB)
1198 #define SPR_40x_ICCR (0x3FB)
1199 #define SPR_THRM1 (0x3FC)
1200 #define SPR_403_PBL1 (0x3FC)
1201 #define SPR_SP (0x3FD)
1202 #define SPR_THRM2 (0x3FD)
1203 #define SPR_403_PBU1 (0x3FD)
1204 #define SPR_LT (0x3FE)
1205 #define SPR_THRM3 (0x3FE)
1206 #define SPR_FPECR (0x3FE)
1207 #define SPR_403_PBL2 (0x3FE)
1208 #define SPR_PIR (0x3FF)
1209 #define SPR_403_PBU2 (0x3FF)
1210 #define SPR_601_HID15 (0x3FF)
1211 #define SPR_E500_SVR (0x3FF)
1213 /*****************************************************************************/
1214 /* Memory access type :
1215 * may be needed for precise access rights control and precise exceptions.
1218 /* 1 bit to define user level / supervisor access */
1220 ACCESS_SUPER
= 0x01,
1221 /* Type of instruction that generated the access */
1222 ACCESS_CODE
= 0x10, /* Code fetch access */
1223 ACCESS_INT
= 0x20, /* Integer load/store access */
1224 ACCESS_FLOAT
= 0x30, /* floating point load/store access */
1225 ACCESS_RES
= 0x40, /* load/store with reservation */
1226 ACCESS_EXT
= 0x50, /* external access */
1227 ACCESS_CACHE
= 0x60, /* Cache manipulation */
1230 /*****************************************************************************/
1232 #define EXCP_NONE -1
1233 /* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
1234 #define EXCP_RESET 0x0100 /* System reset */
1235 #define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */
1236 #define EXCP_DSI 0x0300 /* Data storage exception */
1237 #define EXCP_DSEG 0x0380 /* Data segment exception */
1238 #define EXCP_ISI 0x0400 /* Instruction storage exception */
1239 #define EXCP_ISEG 0x0480 /* Instruction segment exception */
1240 #define EXCP_EXTERNAL 0x0500 /* External interruption */
1241 #define EXCP_ALIGN 0x0600 /* Alignment exception */
1242 #define EXCP_PROGRAM 0x0700 /* Program exception */
1243 #define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */
1244 #define EXCP_DECR 0x0900 /* Decrementer exception */
1245 #define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */
1246 #define EXCP_SYSCALL 0x0C00 /* System call */
1247 #define EXCP_TRACE 0x0D00 /* Trace exception */
1248 #define EXCP_PERF 0x0F00 /* Performance monitor exception */
1249 /* Exceptions defined in PowerPC 32 bits programming environment manual */
1250 #define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */
1251 /* Implementation specific exceptions */
1252 /* 40x exceptions */
1253 #define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */
1254 #define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */
1255 #define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */
1256 #define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */
1257 #define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */
1258 #define EXCP_40x_DEBUG 0x2000 /* Debug exception */
1259 /* 405 specific exceptions */
1260 #define EXCP_405_APU 0x0F20 /* APU unavailable exception */
1261 /* TLB assist exceptions (602/603) */
1262 #define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */
1263 #define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */
1264 #define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */
1265 /* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */
1266 #define EXCP_IABR 0x1300 /* Instruction address breakpoint */
1267 #define EXCP_SMI 0x1400 /* System management interrupt */
1268 /* Altivec related exceptions */
1269 #define EXCP_VPU 0x0F20 /* VPU unavailable exception */
1270 /* 601 specific exceptions */
1271 #define EXCP_601_IO 0x0600 /* IO error exception */
1272 #define EXCP_601_RUNM 0x2000 /* Run mode exception */
1273 /* 602 specific exceptions */
1274 #define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */
1275 #define EXCP_602_EMUL 0x1600 /* Emulation trap exception */
1276 /* G2 specific exceptions */
1277 #define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */
1278 /* MPC740/745/750 & IBM 750 specific exceptions */
1279 #define EXCP_THRM 0x1700 /* Thermal management interrupt */
1280 /* 74xx specific exceptions */
1281 #define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */
1282 /* 970FX specific exceptions */
1283 #define EXCP_970_SOFTP 0x1500 /* Soft patch exception */
1284 #define EXCP_970_MAINT 0x1600 /* Maintenance exception */
1285 #define EXCP_970_THRM 0x1800 /* Thermal exception */
1286 #define EXCP_970_VPUA 0x1700 /* VPU assist exception */
1287 /* SPE related exceptions */
1288 #define EXCP_NO_SPE 0x0F20 /* SPE unavailable exception */
1289 /* End of exception vectors area */
1290 #define EXCP_PPC_MAX 0x4000
1291 /* Qemu exceptions: special cases we want to stop translation */
1292 #define EXCP_MTMSR 0x11000 /* mtmsr instruction: */
1293 /* may change privilege level */
1294 #define EXCP_BRANCH 0x11001 /* branch instruction */
1295 #define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */
1296 #define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ */
1300 /* Exception subtypes for EXCP_ALIGN */
1301 EXCP_ALIGN_FP
= 0x01, /* FP alignment exception */
1302 EXCP_ALIGN_LST
= 0x02, /* Unaligned mult/extern load/store */
1303 EXCP_ALIGN_LE
= 0x03, /* Multiple little-endian access */
1304 EXCP_ALIGN_PROT
= 0x04, /* Access cross protection boundary */
1305 EXCP_ALIGN_BAT
= 0x05, /* Access cross a BAT/seg boundary */
1306 EXCP_ALIGN_CACHE
= 0x06, /* Impossible dcbz access */
1307 /* Exception subtypes for EXCP_PROGRAM */
1310 EXCP_FP_OX
= 0x01, /* FP overflow */
1311 EXCP_FP_UX
= 0x02, /* FP underflow */
1312 EXCP_FP_ZX
= 0x03, /* FP divide by zero */
1313 EXCP_FP_XX
= 0x04, /* FP inexact */
1314 EXCP_FP_VXNAN
= 0x05, /* FP invalid SNaN op */
1315 EXCP_FP_VXISI
= 0x06, /* FP invalid infinite substraction */
1316 EXCP_FP_VXIDI
= 0x07, /* FP invalid infinite divide */
1317 EXCP_FP_VXZDZ
= 0x08, /* FP invalid zero divide */
1318 EXCP_FP_VXIMZ
= 0x09, /* FP invalid infinite * zero */
1319 EXCP_FP_VXVC
= 0x0A, /* FP invalid compare */
1320 EXCP_FP_VXSOFT
= 0x0B, /* FP invalid operation */
1321 EXCP_FP_VXSQRT
= 0x0C, /* FP invalid square root */
1322 EXCP_FP_VXCVI
= 0x0D, /* FP invalid integer conversion */
1323 /* Invalid instruction */
1325 EXCP_INVAL_INVAL
= 0x01, /* Invalid instruction */
1326 EXCP_INVAL_LSWX
= 0x02, /* Invalid lswx instruction */
1327 EXCP_INVAL_SPR
= 0x03, /* Invalid SPR access */
1328 EXCP_INVAL_FP
= 0x04, /* Unimplemented mandatory fp instr */
1329 /* Privileged instruction */
1331 EXCP_PRIV_OPC
= 0x01,
1332 EXCP_PRIV_REG
= 0x02,
1337 /* Hardware interruption sources:
1338 * all those exception can be raised simulteaneously
1340 /* Input pins definitions */
1342 /* 6xx bus input pins */
1343 PPC6xx_INPUT_HRESET
= 0,
1344 PPC6xx_INPUT_SRESET
= 1,
1345 PPC6xx_INPUT_CKSTP_IN
= 2,
1346 PPC6xx_INPUT_MCP
= 3,
1347 PPC6xx_INPUT_SMI
= 4,
1348 PPC6xx_INPUT_INT
= 5,
1352 /* Embedded PowerPC input pins */
1353 PPCBookE_INPUT_HRESET
= 0,
1354 PPCBookE_INPUT_SRESET
= 1,
1355 PPCBookE_INPUT_CKSTP_IN
= 2,
1356 PPCBookE_INPUT_MCP
= 3,
1357 PPCBookE_INPUT_SMI
= 4,
1358 PPCBookE_INPUT_INT
= 5,
1359 PPCBookE_INPUT_CINT
= 6,
1363 /* PowerPC 405 input pins */
1364 PPC405_INPUT_RESET_CORE
= 0,
1365 PPC405_INPUT_RESET_CHIP
= 1,
1366 PPC405_INPUT_RESET_SYS
= 2,
1367 PPC405_INPUT_CINT
= 3,
1368 PPC405_INPUT_INT
= 4,
1369 PPC405_INPUT_HALT
= 5,
1370 PPC405_INPUT_DEBUG
= 6,
1374 /* PowerPC 970 input pins */
1375 PPC970_INPUT_HRESET
= 0,
1376 PPC970_INPUT_SRESET
= 1,
1377 PPC970_INPUT_CKSTP
= 2,
1378 PPC970_INPUT_TBEN
= 3,
1379 PPC970_INPUT_MCP
= 4,
1380 PPC970_INPUT_INT
= 5,
1381 PPC970_INPUT_THINT
= 6,
1384 /* Hardware exceptions definitions */
1386 /* External hardware exception sources */
1387 PPC_INTERRUPT_RESET
= 0, /* Reset exception */
1388 PPC_INTERRUPT_MCK
= 1, /* Machine check exception */
1389 PPC_INTERRUPT_EXT
= 2, /* External interrupt */
1390 PPC_INTERRUPT_SMI
= 3, /* System management interrupt */
1391 PPC_INTERRUPT_CEXT
= 4, /* Critical external interrupt */
1392 PPC_INTERRUPT_DEBUG
= 5, /* External debug exception */
1393 PPC_INTERRUPT_THERM
= 6, /* Thermal exception */
1394 /* Internal hardware exception sources */
1395 PPC_INTERRUPT_DECR
= 7, /* Decrementer exception */
1396 PPC_INTERRUPT_HDECR
= 8, /* Hypervisor decrementer exception */
1397 PPC_INTERRUPT_PIT
= 9, /* Programmable inteval timer interrupt */
1398 PPC_INTERRUPT_FIT
= 10, /* Fixed interval timer interrupt */
1399 PPC_INTERRUPT_WDT
= 11, /* Watchdog timer interrupt */
1402 /*****************************************************************************/
1404 #endif /* !defined (__CPU_PPC_H__) */