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PPC: E500: Use MAS registers instead of internal TLB representation
[qemu.git] / target-ppc / cpu.h
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 //#define PPC_EMULATE_32BITS_HYPV
26
27 #if defined (TARGET_PPC64)
28 /* PowerPC 64 definitions */
29 #define TARGET_LONG_BITS 64
30 #define TARGET_PAGE_BITS 12
31
32 /* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35 #define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37 /* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40 #ifdef TARGET_ABI32
41 # define TARGET_VIRT_ADDR_SPACE_BITS 32
42 #else
43 # define TARGET_VIRT_ADDR_SPACE_BITS 64
44 #endif
45
46 #define TARGET_PAGE_BITS_16M 24
47
48 #else /* defined (TARGET_PPC64) */
49 /* PowerPC 32 definitions */
50 #define TARGET_LONG_BITS 32
51
52 #if defined(TARGET_PPCEMB)
53 /* Specific definitions for PowerPC embedded */
54 /* BookE have 36 bits physical address space */
55 #if defined(CONFIG_USER_ONLY)
56 /* It looks like a lot of Linux programs assume page size
57 * is 4kB long. This is evil, but we have to deal with it...
58 */
59 #define TARGET_PAGE_BITS 12
60 #else /* defined(CONFIG_USER_ONLY) */
61 /* Pages can be 1 kB small */
62 #define TARGET_PAGE_BITS 10
63 #endif /* defined(CONFIG_USER_ONLY) */
64 #else /* defined(TARGET_PPCEMB) */
65 /* "standard" PowerPC 32 definitions */
66 #define TARGET_PAGE_BITS 12
67 #endif /* defined(TARGET_PPCEMB) */
68
69 #define TARGET_PHYS_ADDR_SPACE_BITS 32
70 #define TARGET_VIRT_ADDR_SPACE_BITS 32
71
72 #endif /* defined (TARGET_PPC64) */
73
74 #define CPUState struct CPUPPCState
75
76 #include "cpu-defs.h"
77
78 #include <setjmp.h>
79
80 #include "softfloat.h"
81
82 #define TARGET_HAS_ICE 1
83
84 #if defined (TARGET_PPC64)
85 #define ELF_MACHINE EM_PPC64
86 #else
87 #define ELF_MACHINE EM_PPC
88 #endif
89
90 /*****************************************************************************/
91 /* MMU model */
92 typedef enum powerpc_mmu_t powerpc_mmu_t;
93 enum powerpc_mmu_t {
94 POWERPC_MMU_UNKNOWN = 0x00000000,
95 /* Standard 32 bits PowerPC MMU */
96 POWERPC_MMU_32B = 0x00000001,
97 /* PowerPC 6xx MMU with software TLB */
98 POWERPC_MMU_SOFT_6xx = 0x00000002,
99 /* PowerPC 74xx MMU with software TLB */
100 POWERPC_MMU_SOFT_74xx = 0x00000003,
101 /* PowerPC 4xx MMU with software TLB */
102 POWERPC_MMU_SOFT_4xx = 0x00000004,
103 /* PowerPC 4xx MMU with software TLB and zones protections */
104 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
105 /* PowerPC MMU in real mode only */
106 POWERPC_MMU_REAL = 0x00000006,
107 /* Freescale MPC8xx MMU model */
108 POWERPC_MMU_MPC8xx = 0x00000007,
109 /* BookE MMU model */
110 POWERPC_MMU_BOOKE = 0x00000008,
111 /* BookE 2.06 MMU model */
112 POWERPC_MMU_BOOKE206 = 0x00000009,
113 /* PowerPC 601 MMU model (specific BATs format) */
114 POWERPC_MMU_601 = 0x0000000A,
115 #if defined(TARGET_PPC64)
116 #define POWERPC_MMU_64 0x00010000
117 #define POWERPC_MMU_1TSEG 0x00020000
118 /* 64 bits PowerPC MMU */
119 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
120 /* 620 variant (no segment exceptions) */
121 POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
122 /* Architecture 2.06 variant */
123 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,
124 #endif /* defined(TARGET_PPC64) */
125 };
126
127 /*****************************************************************************/
128 /* Exception model */
129 typedef enum powerpc_excp_t powerpc_excp_t;
130 enum powerpc_excp_t {
131 POWERPC_EXCP_UNKNOWN = 0,
132 /* Standard PowerPC exception model */
133 POWERPC_EXCP_STD,
134 /* PowerPC 40x exception model */
135 POWERPC_EXCP_40x,
136 /* PowerPC 601 exception model */
137 POWERPC_EXCP_601,
138 /* PowerPC 602 exception model */
139 POWERPC_EXCP_602,
140 /* PowerPC 603 exception model */
141 POWERPC_EXCP_603,
142 /* PowerPC 603e exception model */
143 POWERPC_EXCP_603E,
144 /* PowerPC G2 exception model */
145 POWERPC_EXCP_G2,
146 /* PowerPC 604 exception model */
147 POWERPC_EXCP_604,
148 /* PowerPC 7x0 exception model */
149 POWERPC_EXCP_7x0,
150 /* PowerPC 7x5 exception model */
151 POWERPC_EXCP_7x5,
152 /* PowerPC 74xx exception model */
153 POWERPC_EXCP_74xx,
154 /* BookE exception model */
155 POWERPC_EXCP_BOOKE,
156 #if defined(TARGET_PPC64)
157 /* PowerPC 970 exception model */
158 POWERPC_EXCP_970,
159 /* POWER7 exception model */
160 POWERPC_EXCP_POWER7,
161 #endif /* defined(TARGET_PPC64) */
162 };
163
164 /*****************************************************************************/
165 /* Exception vectors definitions */
166 enum {
167 POWERPC_EXCP_NONE = -1,
168 /* The 64 first entries are used by the PowerPC embedded specification */
169 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
170 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
171 POWERPC_EXCP_DSI = 2, /* Data storage exception */
172 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
173 POWERPC_EXCP_EXTERNAL = 4, /* External input */
174 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
175 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
176 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
177 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
178 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
179 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
180 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
181 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
182 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
183 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
184 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
185 /* Vectors 16 to 31 are reserved */
186 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
187 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
188 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
189 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
190 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
191 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
192 /* Vectors 38 to 63 are reserved */
193 /* Exceptions defined in the PowerPC server specification */
194 POWERPC_EXCP_RESET = 64, /* System reset exception */
195 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
196 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
197 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
198 POWERPC_EXCP_TRACE = 68, /* Trace exception */
199 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
200 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
201 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
202 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
203 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
204 /* 40x specific exceptions */
205 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
206 /* 601 specific exceptions */
207 POWERPC_EXCP_IO = 75, /* IO error exception */
208 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
209 /* 602 specific exceptions */
210 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
211 /* 602/603 specific exceptions */
212 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
213 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
214 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
215 /* Exceptions available on most PowerPC */
216 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
217 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
218 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
219 POWERPC_EXCP_SMI = 84, /* System management interrupt */
220 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
221 /* 7xx/74xx specific exceptions */
222 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
223 /* 74xx specific exceptions */
224 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
225 /* 970FX specific exceptions */
226 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
227 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
228 /* Freescale embedded cores specific exceptions */
229 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
230 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
231 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
232 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
233 /* EOL */
234 POWERPC_EXCP_NB = 96,
235 /* Qemu exceptions: used internally during code translation */
236 POWERPC_EXCP_STOP = 0x200, /* stop translation */
237 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
238 /* Qemu exceptions: special cases we want to stop translation */
239 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
240 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
241 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
242 };
243
244 /* Exceptions error codes */
245 enum {
246 /* Exception subtypes for POWERPC_EXCP_ALIGN */
247 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
248 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
249 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
250 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
251 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
252 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
253 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
254 /* FP exceptions */
255 POWERPC_EXCP_FP = 0x10,
256 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
257 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
258 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
259 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
260 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
261 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
262 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
263 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
264 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
265 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
266 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
267 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
268 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
269 /* Invalid instruction */
270 POWERPC_EXCP_INVAL = 0x20,
271 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
272 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
273 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
274 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
275 /* Privileged instruction */
276 POWERPC_EXCP_PRIV = 0x30,
277 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
278 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
279 /* Trap */
280 POWERPC_EXCP_TRAP = 0x40,
281 };
282
283 /*****************************************************************************/
284 /* Input pins model */
285 typedef enum powerpc_input_t powerpc_input_t;
286 enum powerpc_input_t {
287 PPC_FLAGS_INPUT_UNKNOWN = 0,
288 /* PowerPC 6xx bus */
289 PPC_FLAGS_INPUT_6xx,
290 /* BookE bus */
291 PPC_FLAGS_INPUT_BookE,
292 /* PowerPC 405 bus */
293 PPC_FLAGS_INPUT_405,
294 /* PowerPC 970 bus */
295 PPC_FLAGS_INPUT_970,
296 /* PowerPC POWER7 bus */
297 PPC_FLAGS_INPUT_POWER7,
298 /* PowerPC 401 bus */
299 PPC_FLAGS_INPUT_401,
300 /* Freescale RCPU bus */
301 PPC_FLAGS_INPUT_RCPU,
302 };
303
304 #define PPC_INPUT(env) (env->bus_model)
305
306 /*****************************************************************************/
307 typedef struct ppc_def_t ppc_def_t;
308 typedef struct opc_handler_t opc_handler_t;
309
310 /*****************************************************************************/
311 /* Types used to describe some PowerPC registers */
312 typedef struct CPUPPCState CPUPPCState;
313 typedef struct ppc_tb_t ppc_tb_t;
314 typedef struct ppc_spr_t ppc_spr_t;
315 typedef struct ppc_dcr_t ppc_dcr_t;
316 typedef union ppc_avr_t ppc_avr_t;
317 typedef union ppc_tlb_t ppc_tlb_t;
318
319 /* SPR access micro-ops generations callbacks */
320 struct ppc_spr_t {
321 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
322 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
323 #if !defined(CONFIG_USER_ONLY)
324 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
325 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
326 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
327 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
328 #endif
329 const char *name;
330 };
331
332 /* Altivec registers (128 bits) */
333 union ppc_avr_t {
334 float32 f[4];
335 uint8_t u8[16];
336 uint16_t u16[8];
337 uint32_t u32[4];
338 int8_t s8[16];
339 int16_t s16[8];
340 int32_t s32[4];
341 uint64_t u64[2];
342 };
343
344 #if !defined(CONFIG_USER_ONLY)
345 /* Software TLB cache */
346 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
347 struct ppc6xx_tlb_t {
348 target_ulong pte0;
349 target_ulong pte1;
350 target_ulong EPN;
351 };
352
353 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
354 struct ppcemb_tlb_t {
355 target_phys_addr_t RPN;
356 target_ulong EPN;
357 target_ulong PID;
358 target_ulong size;
359 uint32_t prot;
360 uint32_t attr; /* Storage attributes */
361 };
362
363 typedef struct ppcmas_tlb_t {
364 uint32_t mas8;
365 uint32_t mas1;
366 uint64_t mas2;
367 uint64_t mas7_3;
368 } ppcmas_tlb_t;
369
370 union ppc_tlb_t {
371 ppc6xx_tlb_t tlb6;
372 ppcemb_tlb_t tlbe;
373 ppcmas_tlb_t tlbm;
374 };
375 #endif
376
377 #define SDR_32_HTABORG 0xFFFF0000UL
378 #define SDR_32_HTABMASK 0x000001FFUL
379
380 #if defined(TARGET_PPC64)
381 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
382 #define SDR_64_HTABSIZE 0x000000000000001FULL
383 #endif /* defined(TARGET_PPC64 */
384
385 #define HASH_PTE_SIZE_32 8
386 #define HASH_PTE_SIZE_64 16
387
388 typedef struct ppc_slb_t ppc_slb_t;
389 struct ppc_slb_t {
390 uint64_t esid;
391 uint64_t vsid;
392 };
393
394 /* Bits in the SLB ESID word */
395 #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
396 #define SLB_ESID_V 0x0000000008000000ULL /* valid */
397
398 /* Bits in the SLB VSID word */
399 #define SLB_VSID_SHIFT 12
400 #define SLB_VSID_SHIFT_1T 24
401 #define SLB_VSID_SSIZE_SHIFT 62
402 #define SLB_VSID_B 0xc000000000000000ULL
403 #define SLB_VSID_B_256M 0x0000000000000000ULL
404 #define SLB_VSID_B_1T 0x4000000000000000ULL
405 #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
406 #define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
407 #define SLB_VSID_KS 0x0000000000000800ULL
408 #define SLB_VSID_KP 0x0000000000000400ULL
409 #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
410 #define SLB_VSID_L 0x0000000000000100ULL
411 #define SLB_VSID_C 0x0000000000000080ULL /* class */
412 #define SLB_VSID_LP 0x0000000000000030ULL
413 #define SLB_VSID_ATTR 0x0000000000000FFFULL
414
415 #define SEGMENT_SHIFT_256M 28
416 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
417
418 #define SEGMENT_SHIFT_1T 40
419 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
420
421
422 /*****************************************************************************/
423 /* Machine state register bits definition */
424 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
425 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
426 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
427 #define MSR_SHV 60 /* hypervisor state hflags */
428 #define MSR_CM 31 /* Computation mode for BookE hflags */
429 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
430 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
431 #define MSR_GS 28 /* guest state for BookE */
432 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
433 #define MSR_VR 25 /* altivec available x hflags */
434 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
435 #define MSR_AP 23 /* Access privilege state on 602 hflags */
436 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
437 #define MSR_KEY 19 /* key bit on 603e */
438 #define MSR_POW 18 /* Power management */
439 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
440 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
441 #define MSR_ILE 16 /* Interrupt little-endian mode */
442 #define MSR_EE 15 /* External interrupt enable */
443 #define MSR_PR 14 /* Problem state hflags */
444 #define MSR_FP 13 /* Floating point available hflags */
445 #define MSR_ME 12 /* Machine check interrupt enable */
446 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
447 #define MSR_SE 10 /* Single-step trace enable x hflags */
448 #define MSR_DWE 10 /* Debug wait enable on 405 x */
449 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
450 #define MSR_BE 9 /* Branch trace enable x hflags */
451 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
452 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
453 #define MSR_AL 7 /* AL bit on POWER */
454 #define MSR_EP 6 /* Exception prefix on 601 */
455 #define MSR_IR 5 /* Instruction relocate */
456 #define MSR_DR 4 /* Data relocate */
457 #define MSR_PE 3 /* Protection enable on 403 */
458 #define MSR_PX 2 /* Protection exclusive on 403 x */
459 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
460 #define MSR_RI 1 /* Recoverable interrupt 1 */
461 #define MSR_LE 0 /* Little-endian mode 1 hflags */
462
463 #define msr_sf ((env->msr >> MSR_SF) & 1)
464 #define msr_isf ((env->msr >> MSR_ISF) & 1)
465 #define msr_shv ((env->msr >> MSR_SHV) & 1)
466 #define msr_cm ((env->msr >> MSR_CM) & 1)
467 #define msr_icm ((env->msr >> MSR_ICM) & 1)
468 #define msr_thv ((env->msr >> MSR_THV) & 1)
469 #define msr_gs ((env->msr >> MSR_GS) & 1)
470 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
471 #define msr_vr ((env->msr >> MSR_VR) & 1)
472 #define msr_spe ((env->msr >> MSR_SPE) & 1)
473 #define msr_ap ((env->msr >> MSR_AP) & 1)
474 #define msr_sa ((env->msr >> MSR_SA) & 1)
475 #define msr_key ((env->msr >> MSR_KEY) & 1)
476 #define msr_pow ((env->msr >> MSR_POW) & 1)
477 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
478 #define msr_ce ((env->msr >> MSR_CE) & 1)
479 #define msr_ile ((env->msr >> MSR_ILE) & 1)
480 #define msr_ee ((env->msr >> MSR_EE) & 1)
481 #define msr_pr ((env->msr >> MSR_PR) & 1)
482 #define msr_fp ((env->msr >> MSR_FP) & 1)
483 #define msr_me ((env->msr >> MSR_ME) & 1)
484 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
485 #define msr_se ((env->msr >> MSR_SE) & 1)
486 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
487 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
488 #define msr_be ((env->msr >> MSR_BE) & 1)
489 #define msr_de ((env->msr >> MSR_DE) & 1)
490 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
491 #define msr_al ((env->msr >> MSR_AL) & 1)
492 #define msr_ep ((env->msr >> MSR_EP) & 1)
493 #define msr_ir ((env->msr >> MSR_IR) & 1)
494 #define msr_dr ((env->msr >> MSR_DR) & 1)
495 #define msr_pe ((env->msr >> MSR_PE) & 1)
496 #define msr_px ((env->msr >> MSR_PX) & 1)
497 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
498 #define msr_ri ((env->msr >> MSR_RI) & 1)
499 #define msr_le ((env->msr >> MSR_LE) & 1)
500 /* Hypervisor bit is more specific */
501 #if defined(TARGET_PPC64)
502 #define MSR_HVB (1ULL << MSR_SHV)
503 #define msr_hv msr_shv
504 #else
505 #if defined(PPC_EMULATE_32BITS_HYPV)
506 #define MSR_HVB (1ULL << MSR_THV)
507 #define msr_hv msr_thv
508 #else
509 #define MSR_HVB (0ULL)
510 #define msr_hv (0)
511 #endif
512 #endif
513
514 /* Exception state register bits definition */
515 #define ESR_ST 23 /* Exception was caused by a store type access. */
516
517 enum {
518 POWERPC_FLAG_NONE = 0x00000000,
519 /* Flag for MSR bit 25 signification (VRE/SPE) */
520 POWERPC_FLAG_SPE = 0x00000001,
521 POWERPC_FLAG_VRE = 0x00000002,
522 /* Flag for MSR bit 17 signification (TGPR/CE) */
523 POWERPC_FLAG_TGPR = 0x00000004,
524 POWERPC_FLAG_CE = 0x00000008,
525 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
526 POWERPC_FLAG_SE = 0x00000010,
527 POWERPC_FLAG_DWE = 0x00000020,
528 POWERPC_FLAG_UBLE = 0x00000040,
529 /* Flag for MSR bit 9 signification (BE/DE) */
530 POWERPC_FLAG_BE = 0x00000080,
531 POWERPC_FLAG_DE = 0x00000100,
532 /* Flag for MSR bit 2 signification (PX/PMM) */
533 POWERPC_FLAG_PX = 0x00000200,
534 POWERPC_FLAG_PMM = 0x00000400,
535 /* Flag for special features */
536 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
537 POWERPC_FLAG_RTC_CLK = 0x00010000,
538 POWERPC_FLAG_BUS_CLK = 0x00020000,
539 };
540
541 /*****************************************************************************/
542 /* Floating point status and control register */
543 #define FPSCR_FX 31 /* Floating-point exception summary */
544 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
545 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
546 #define FPSCR_OX 28 /* Floating-point overflow exception */
547 #define FPSCR_UX 27 /* Floating-point underflow exception */
548 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
549 #define FPSCR_XX 25 /* Floating-point inexact exception */
550 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
551 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
552 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
553 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
554 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
555 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
556 #define FPSCR_FR 18 /* Floating-point fraction rounded */
557 #define FPSCR_FI 17 /* Floating-point fraction inexact */
558 #define FPSCR_C 16 /* Floating-point result class descriptor */
559 #define FPSCR_FL 15 /* Floating-point less than or negative */
560 #define FPSCR_FG 14 /* Floating-point greater than or negative */
561 #define FPSCR_FE 13 /* Floating-point equal or zero */
562 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
563 #define FPSCR_FPCC 12 /* Floating-point condition code */
564 #define FPSCR_FPRF 12 /* Floating-point result flags */
565 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
566 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
567 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
568 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
569 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
570 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
571 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
572 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
573 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
574 #define FPSCR_RN1 1
575 #define FPSCR_RN 0 /* Floating-point rounding control */
576 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
577 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
578 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
579 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
580 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
581 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
582 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
583 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
584 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
585 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
586 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
587 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
588 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
589 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
590 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
591 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
592 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
593 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
594 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
595 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
596 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
597 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
598 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
599 /* Invalid operation exception summary */
600 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
601 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
602 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
603 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
604 (1 << FPSCR_VXCVI)))
605 /* exception summary */
606 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
607 /* enabled exception summary */
608 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
609 0x1F)
610
611 /*****************************************************************************/
612 /* Vector status and control register */
613 #define VSCR_NJ 16 /* Vector non-java */
614 #define VSCR_SAT 0 /* Vector saturation */
615 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
616 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
617
618 /*****************************************************************************/
619 /* BookE e500 MMU registers */
620
621 #define MAS0_NV_SHIFT 0
622 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
623
624 #define MAS0_WQ_SHIFT 12
625 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
626 /* Write TLB entry regardless of reservation */
627 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
628 /* Write TLB entry only already in use */
629 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
630 /* Clear TLB entry */
631 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
632
633 #define MAS0_HES_SHIFT 14
634 #define MAS0_HES (1 << MAS0_HES_SHIFT)
635
636 #define MAS0_ESEL_SHIFT 16
637 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
638
639 #define MAS0_TLBSEL_SHIFT 28
640 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
641 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
642 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
643 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
644 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
645
646 #define MAS0_ATSEL_SHIFT 31
647 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
648 #define MAS0_ATSEL_TLB 0
649 #define MAS0_ATSEL_LRAT MAS0_ATSEL
650
651 #define MAS1_TSIZE_SHIFT 8
652 #define MAS1_TSIZE_MASK (0xf << MAS1_TSIZE_SHIFT)
653
654 #define MAS1_TS_SHIFT 12
655 #define MAS1_TS (1 << MAS1_TS_SHIFT)
656
657 #define MAS1_IND_SHIFT 13
658 #define MAS1_IND (1 << MAS1_IND_SHIFT)
659
660 #define MAS1_TID_SHIFT 16
661 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
662
663 #define MAS1_IPROT_SHIFT 30
664 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
665
666 #define MAS1_VALID_SHIFT 31
667 #define MAS1_VALID 0x80000000
668
669 #define MAS2_EPN_SHIFT 12
670 #define MAS2_EPN_MASK (0xfffff << MAS2_EPN_SHIFT)
671
672 #define MAS2_ACM_SHIFT 6
673 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
674
675 #define MAS2_VLE_SHIFT 5
676 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
677
678 #define MAS2_W_SHIFT 4
679 #define MAS2_W (1 << MAS2_W_SHIFT)
680
681 #define MAS2_I_SHIFT 3
682 #define MAS2_I (1 << MAS2_I_SHIFT)
683
684 #define MAS2_M_SHIFT 2
685 #define MAS2_M (1 << MAS2_M_SHIFT)
686
687 #define MAS2_G_SHIFT 1
688 #define MAS2_G (1 << MAS2_G_SHIFT)
689
690 #define MAS2_E_SHIFT 0
691 #define MAS2_E (1 << MAS2_E_SHIFT)
692
693 #define MAS3_RPN_SHIFT 12
694 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
695
696 #define MAS3_U0 0x00000200
697 #define MAS3_U1 0x00000100
698 #define MAS3_U2 0x00000080
699 #define MAS3_U3 0x00000040
700 #define MAS3_UX 0x00000020
701 #define MAS3_SX 0x00000010
702 #define MAS3_UW 0x00000008
703 #define MAS3_SW 0x00000004
704 #define MAS3_UR 0x00000002
705 #define MAS3_SR 0x00000001
706 #define MAS3_SPSIZE_SHIFT 1
707 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
708
709 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
710 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
711 #define MAS4_TIDSELD_MASK 0x00030000
712 #define MAS4_TIDSELD_PID0 0x00000000
713 #define MAS4_TIDSELD_PID1 0x00010000
714 #define MAS4_TIDSELD_PID2 0x00020000
715 #define MAS4_TIDSELD_PIDZ 0x00030000
716 #define MAS4_INDD 0x00008000 /* Default IND */
717 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
718 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
719 #define MAS4_ACMD 0x00000040
720 #define MAS4_VLED 0x00000020
721 #define MAS4_WD 0x00000010
722 #define MAS4_ID 0x00000008
723 #define MAS4_MD 0x00000004
724 #define MAS4_GD 0x00000002
725 #define MAS4_ED 0x00000001
726 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
727 #define MAS4_WIMGED_SHIFT 0
728
729 #define MAS5_SGS 0x80000000
730 #define MAS5_SLPID_MASK 0x00000fff
731
732 #define MAS6_SPID0 0x3fff0000
733 #define MAS6_SPID1 0x00007ffe
734 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
735 #define MAS6_SAS 0x00000001
736 #define MAS6_SPID MAS6_SPID0
737 #define MAS6_SIND 0x00000002 /* Indirect page */
738 #define MAS6_SIND_SHIFT 1
739 #define MAS6_SPID_MASK 0x3fff0000
740 #define MAS6_SPID_SHIFT 16
741 #define MAS6_ISIZE_MASK 0x00000f80
742 #define MAS6_ISIZE_SHIFT 7
743
744 #define MAS7_RPN 0xffffffff
745
746 #define MAS8_TGS 0x80000000
747 #define MAS8_VF 0x40000000
748 #define MAS8_TLBPID 0x00000fff
749
750 /* Bit definitions for MMUCFG */
751 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
752 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
753 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
754 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
755 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
756 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
757 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
758 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
759 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
760
761 /* Bit definitions for MMUCSR0 */
762 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
763 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
764 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
765 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
766 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
767 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
768 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
769 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
770 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
771 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
772
773 /* TLBnCFG encoding */
774 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
775 #define TLBnCFG_HES 0x00002000 /* HW select supported */
776 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
777 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
778 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
779 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
780 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
781 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
782 #define TLBnCFG_MINSIZE_SHIFT 20
783 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
784 #define TLBnCFG_MAXSIZE_SHIFT 16
785 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
786 #define TLBnCFG_ASSOC_SHIFT 24
787
788 /* TLBnPS encoding */
789 #define TLBnPS_4K 0x00000004
790 #define TLBnPS_8K 0x00000008
791 #define TLBnPS_16K 0x00000010
792 #define TLBnPS_32K 0x00000020
793 #define TLBnPS_64K 0x00000040
794 #define TLBnPS_128K 0x00000080
795 #define TLBnPS_256K 0x00000100
796 #define TLBnPS_512K 0x00000200
797 #define TLBnPS_1M 0x00000400
798 #define TLBnPS_2M 0x00000800
799 #define TLBnPS_4M 0x00001000
800 #define TLBnPS_8M 0x00002000
801 #define TLBnPS_16M 0x00004000
802 #define TLBnPS_32M 0x00008000
803 #define TLBnPS_64M 0x00010000
804 #define TLBnPS_128M 0x00020000
805 #define TLBnPS_256M 0x00040000
806 #define TLBnPS_512M 0x00080000
807 #define TLBnPS_1G 0x00100000
808 #define TLBnPS_2G 0x00200000
809 #define TLBnPS_4G 0x00400000
810 #define TLBnPS_8G 0x00800000
811 #define TLBnPS_16G 0x01000000
812 #define TLBnPS_32G 0x02000000
813 #define TLBnPS_64G 0x04000000
814 #define TLBnPS_128G 0x08000000
815 #define TLBnPS_256G 0x10000000
816
817 /* tlbilx action encoding */
818 #define TLBILX_T_ALL 0
819 #define TLBILX_T_TID 1
820 #define TLBILX_T_FULLMATCH 3
821 #define TLBILX_T_CLASS0 4
822 #define TLBILX_T_CLASS1 5
823 #define TLBILX_T_CLASS2 6
824 #define TLBILX_T_CLASS3 7
825
826 /* BookE 2.06 helper defines */
827
828 #define BOOKE206_FLUSH_TLB0 (1 << 0)
829 #define BOOKE206_FLUSH_TLB1 (1 << 1)
830 #define BOOKE206_FLUSH_TLB2 (1 << 2)
831 #define BOOKE206_FLUSH_TLB3 (1 << 3)
832
833 /* number of possible TLBs */
834 #define BOOKE206_MAX_TLBN 4
835
836 /*****************************************************************************/
837 /* The whole PowerPC CPU context */
838 #define NB_MMU_MODES 3
839
840 struct CPUPPCState {
841 /* First are the most commonly used resources
842 * during translated code execution
843 */
844 /* general purpose registers */
845 target_ulong gpr[32];
846 #if !defined(TARGET_PPC64)
847 /* Storage for GPR MSB, used by the SPE extension */
848 target_ulong gprh[32];
849 #endif
850 /* LR */
851 target_ulong lr;
852 /* CTR */
853 target_ulong ctr;
854 /* condition register */
855 uint32_t crf[8];
856 /* XER */
857 target_ulong xer;
858 /* Reservation address */
859 target_ulong reserve_addr;
860 /* Reservation value */
861 target_ulong reserve_val;
862 /* Reservation store address */
863 target_ulong reserve_ea;
864 /* Reserved store source register and size */
865 target_ulong reserve_info;
866
867 /* Those ones are used in supervisor mode only */
868 /* machine state register */
869 target_ulong msr;
870 /* temporary general purpose registers */
871 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
872
873 /* Floating point execution context */
874 float_status fp_status;
875 /* floating point registers */
876 float64 fpr[32];
877 /* floating point status and control register */
878 uint32_t fpscr;
879
880 /* Next instruction pointer */
881 target_ulong nip;
882
883 int access_type; /* when a memory exception occurs, the access
884 type is stored here */
885
886 CPU_COMMON
887
888 /* MMU context - only relevant for full system emulation */
889 #if !defined(CONFIG_USER_ONLY)
890 #if defined(TARGET_PPC64)
891 /* Address space register */
892 target_ulong asr;
893 /* PowerPC 64 SLB area */
894 ppc_slb_t slb[64];
895 int slb_nr;
896 #endif
897 /* segment registers */
898 target_phys_addr_t htab_base;
899 target_phys_addr_t htab_mask;
900 target_ulong sr[32];
901 /* externally stored hash table */
902 uint8_t *external_htab;
903 /* BATs */
904 int nb_BATs;
905 target_ulong DBAT[2][8];
906 target_ulong IBAT[2][8];
907 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
908 int nb_tlb; /* Total number of TLB */
909 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
910 int nb_ways; /* Number of ways in the TLB set */
911 int last_way; /* Last used way used to allocate TLB in a LRU way */
912 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
913 int nb_pids; /* Number of available PID registers */
914 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
915 /* 403 dedicated access protection registers */
916 target_ulong pb[4];
917 #endif
918
919 /* Other registers */
920 /* Special purpose registers */
921 target_ulong spr[1024];
922 ppc_spr_t spr_cb[1024];
923 /* Altivec registers */
924 ppc_avr_t avr[32];
925 uint32_t vscr;
926 /* SPE registers */
927 uint64_t spe_acc;
928 uint32_t spe_fscr;
929 /* SPE and Altivec can share a status since they will never be used
930 * simultaneously */
931 float_status vec_status;
932
933 /* Internal devices resources */
934 /* Time base and decrementer */
935 ppc_tb_t *tb_env;
936 /* Device control registers */
937 ppc_dcr_t *dcr_env;
938
939 int dcache_line_size;
940 int icache_line_size;
941
942 /* Those resources are used during exception processing */
943 /* CPU model definition */
944 target_ulong msr_mask;
945 powerpc_mmu_t mmu_model;
946 powerpc_excp_t excp_model;
947 powerpc_input_t bus_model;
948 int bfd_mach;
949 uint32_t flags;
950 uint64_t insns_flags;
951 uint64_t insns_flags2;
952
953 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
954 target_phys_addr_t vpa;
955 target_phys_addr_t slb_shadow;
956 target_phys_addr_t dispatch_trace_log;
957 uint32_t dtl_size;
958 #endif /* TARGET_PPC64 */
959
960 int error_code;
961 uint32_t pending_interrupts;
962 #if !defined(CONFIG_USER_ONLY)
963 /* This is the IRQ controller, which is implementation dependant
964 * and only relevant when emulating a complete machine.
965 */
966 uint32_t irq_input_state;
967 void **irq_inputs;
968 /* Exception vectors */
969 target_ulong excp_vectors[POWERPC_EXCP_NB];
970 target_ulong excp_prefix;
971 target_ulong hreset_excp_prefix;
972 target_ulong ivor_mask;
973 target_ulong ivpr_mask;
974 target_ulong hreset_vector;
975 #endif
976
977 /* Those resources are used only during code translation */
978 /* opcode handlers */
979 opc_handler_t *opcodes[0x40];
980
981 /* Those resources are used only in Qemu core */
982 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
983 target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
984 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
985
986 /* Power management */
987 int power_mode;
988 int (*check_pow)(CPUPPCState *env);
989
990 #if !defined(CONFIG_USER_ONLY)
991 void *load_info; /* Holds boot loading state. */
992 #endif
993 };
994
995 #if !defined(CONFIG_USER_ONLY)
996 /* Context used internally during MMU translations */
997 typedef struct mmu_ctx_t mmu_ctx_t;
998 struct mmu_ctx_t {
999 target_phys_addr_t raddr; /* Real address */
1000 target_phys_addr_t eaddr; /* Effective address */
1001 int prot; /* Protection bits */
1002 target_phys_addr_t hash[2]; /* Pagetable hash values */
1003 target_ulong ptem; /* Virtual segment ID | API */
1004 int key; /* Access key */
1005 int nx; /* Non-execute area */
1006 };
1007 #endif
1008
1009 /*****************************************************************************/
1010 CPUPPCState *cpu_ppc_init (const char *cpu_model);
1011 void ppc_translate_init(void);
1012 int cpu_ppc_exec (CPUPPCState *s);
1013 void cpu_ppc_close (CPUPPCState *s);
1014 /* you can call this signal handler from your SIGBUS and SIGSEGV
1015 signal handlers to inform the virtual CPU of exceptions. non zero
1016 is returned if the signal was handled by the virtual CPU. */
1017 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1018 void *puc);
1019 int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
1020 int mmu_idx, int is_softmmu);
1021 #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
1022 #if !defined(CONFIG_USER_ONLY)
1023 int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
1024 int rw, int access_type);
1025 #endif
1026 void do_interrupt (CPUPPCState *env);
1027 void ppc_hw_interrupt (CPUPPCState *env);
1028
1029 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1030
1031 #if !defined(CONFIG_USER_ONLY)
1032 void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
1033 target_ulong pte0, target_ulong pte1);
1034 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
1035 void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
1036 void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
1037 void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
1038 void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
1039 void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
1040 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1041 #if defined(TARGET_PPC64)
1042 void ppc_store_asr (CPUPPCState *env, target_ulong value);
1043 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
1044 target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
1045 int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
1046 int ppc_load_slb_esid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
1047 int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
1048 #endif /* defined(TARGET_PPC64) */
1049 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
1050 #endif /* !defined(CONFIG_USER_ONLY) */
1051 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1052
1053 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1054
1055 const ppc_def_t *cpu_ppc_find_by_name (const char *name);
1056 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
1057
1058 /* Time-base and decrementer management */
1059 #ifndef NO_CPU_IO_DEFS
1060 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1061 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1062 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1063 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1064 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1065 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1066 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1067 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1068 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1069 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1070 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1071 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1072 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1073 void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
1074 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1075 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1076 #if !defined(CONFIG_USER_ONLY)
1077 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1078 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1079 target_ulong load_40x_pit (CPUPPCState *env);
1080 void store_40x_pit (CPUPPCState *env, target_ulong val);
1081 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1082 void store_40x_sler (CPUPPCState *env, uint32_t val);
1083 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1084 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1085 void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot);
1086 target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb);
1087 int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
1088 target_phys_addr_t *raddrp, target_ulong address,
1089 uint32_t pid, int ext, int i);
1090 int ppcmas_tlb_check(CPUState *env, ppcmas_tlb_t *tlb,
1091 target_phys_addr_t *raddrp, target_ulong address,
1092 uint32_t pid);
1093 void ppc_tlb_invalidate_all (CPUPPCState *env);
1094 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1095 #if defined(TARGET_PPC64)
1096 void ppc_slb_invalidate_all (CPUPPCState *env);
1097 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
1098 #endif
1099 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
1100 #endif
1101 #endif
1102
1103 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1104 {
1105 uint64_t gprv;
1106
1107 gprv = env->gpr[gprn];
1108 #if !defined(TARGET_PPC64)
1109 if (env->flags & POWERPC_FLAG_SPE) {
1110 /* If the CPU implements the SPE extension, we have to get the
1111 * high bits of the GPR from the gprh storage area
1112 */
1113 gprv &= 0xFFFFFFFFULL;
1114 gprv |= (uint64_t)env->gprh[gprn] << 32;
1115 }
1116 #endif
1117
1118 return gprv;
1119 }
1120
1121 /* Device control registers */
1122 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1123 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1124
1125 #define cpu_init cpu_ppc_init
1126 #define cpu_exec cpu_ppc_exec
1127 #define cpu_gen_code cpu_ppc_gen_code
1128 #define cpu_signal_handler cpu_ppc_signal_handler
1129 #define cpu_list ppc_cpu_list
1130
1131 #define CPU_SAVE_VERSION 4
1132
1133 /* MMU modes definitions */
1134 #define MMU_MODE0_SUFFIX _user
1135 #define MMU_MODE1_SUFFIX _kernel
1136 #define MMU_MODE2_SUFFIX _hypv
1137 #define MMU_USER_IDX 0
1138 static inline int cpu_mmu_index (CPUState *env)
1139 {
1140 return env->mmu_idx;
1141 }
1142
1143 #if defined(CONFIG_USER_ONLY)
1144 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
1145 {
1146 if (newsp)
1147 env->gpr[1] = newsp;
1148 env->gpr[3] = 0;
1149 }
1150 #endif
1151
1152 #include "cpu-all.h"
1153
1154 /*****************************************************************************/
1155 /* CRF definitions */
1156 #define CRF_LT 3
1157 #define CRF_GT 2
1158 #define CRF_EQ 1
1159 #define CRF_SO 0
1160 #define CRF_CH (1 << CRF_LT)
1161 #define CRF_CL (1 << CRF_GT)
1162 #define CRF_CH_OR_CL (1 << CRF_EQ)
1163 #define CRF_CH_AND_CL (1 << CRF_SO)
1164
1165 /* XER definitions */
1166 #define XER_SO 31
1167 #define XER_OV 30
1168 #define XER_CA 29
1169 #define XER_CMP 8
1170 #define XER_BC 0
1171 #define xer_so ((env->xer >> XER_SO) & 1)
1172 #define xer_ov ((env->xer >> XER_OV) & 1)
1173 #define xer_ca ((env->xer >> XER_CA) & 1)
1174 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1175 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1176
1177 /* SPR definitions */
1178 #define SPR_MQ (0x000)
1179 #define SPR_XER (0x001)
1180 #define SPR_601_VRTCU (0x004)
1181 #define SPR_601_VRTCL (0x005)
1182 #define SPR_601_UDECR (0x006)
1183 #define SPR_LR (0x008)
1184 #define SPR_CTR (0x009)
1185 #define SPR_DSISR (0x012)
1186 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1187 #define SPR_601_RTCU (0x014)
1188 #define SPR_601_RTCL (0x015)
1189 #define SPR_DECR (0x016)
1190 #define SPR_SDR1 (0x019)
1191 #define SPR_SRR0 (0x01A)
1192 #define SPR_SRR1 (0x01B)
1193 #define SPR_AMR (0x01D)
1194 #define SPR_BOOKE_PID (0x030)
1195 #define SPR_BOOKE_DECAR (0x036)
1196 #define SPR_BOOKE_CSRR0 (0x03A)
1197 #define SPR_BOOKE_CSRR1 (0x03B)
1198 #define SPR_BOOKE_DEAR (0x03D)
1199 #define SPR_BOOKE_ESR (0x03E)
1200 #define SPR_BOOKE_IVPR (0x03F)
1201 #define SPR_MPC_EIE (0x050)
1202 #define SPR_MPC_EID (0x051)
1203 #define SPR_MPC_NRI (0x052)
1204 #define SPR_CTRL (0x088)
1205 #define SPR_MPC_CMPA (0x090)
1206 #define SPR_MPC_CMPB (0x091)
1207 #define SPR_MPC_CMPC (0x092)
1208 #define SPR_MPC_CMPD (0x093)
1209 #define SPR_MPC_ECR (0x094)
1210 #define SPR_MPC_DER (0x095)
1211 #define SPR_MPC_COUNTA (0x096)
1212 #define SPR_MPC_COUNTB (0x097)
1213 #define SPR_UCTRL (0x098)
1214 #define SPR_MPC_CMPE (0x098)
1215 #define SPR_MPC_CMPF (0x099)
1216 #define SPR_MPC_CMPG (0x09A)
1217 #define SPR_MPC_CMPH (0x09B)
1218 #define SPR_MPC_LCTRL1 (0x09C)
1219 #define SPR_MPC_LCTRL2 (0x09D)
1220 #define SPR_MPC_ICTRL (0x09E)
1221 #define SPR_MPC_BAR (0x09F)
1222 #define SPR_VRSAVE (0x100)
1223 #define SPR_USPRG0 (0x100)
1224 #define SPR_USPRG1 (0x101)
1225 #define SPR_USPRG2 (0x102)
1226 #define SPR_USPRG3 (0x103)
1227 #define SPR_USPRG4 (0x104)
1228 #define SPR_USPRG5 (0x105)
1229 #define SPR_USPRG6 (0x106)
1230 #define SPR_USPRG7 (0x107)
1231 #define SPR_VTBL (0x10C)
1232 #define SPR_VTBU (0x10D)
1233 #define SPR_SPRG0 (0x110)
1234 #define SPR_SPRG1 (0x111)
1235 #define SPR_SPRG2 (0x112)
1236 #define SPR_SPRG3 (0x113)
1237 #define SPR_SPRG4 (0x114)
1238 #define SPR_SCOMC (0x114)
1239 #define SPR_SPRG5 (0x115)
1240 #define SPR_SCOMD (0x115)
1241 #define SPR_SPRG6 (0x116)
1242 #define SPR_SPRG7 (0x117)
1243 #define SPR_ASR (0x118)
1244 #define SPR_EAR (0x11A)
1245 #define SPR_TBL (0x11C)
1246 #define SPR_TBU (0x11D)
1247 #define SPR_TBU40 (0x11E)
1248 #define SPR_SVR (0x11E)
1249 #define SPR_BOOKE_PIR (0x11E)
1250 #define SPR_PVR (0x11F)
1251 #define SPR_HSPRG0 (0x130)
1252 #define SPR_BOOKE_DBSR (0x130)
1253 #define SPR_HSPRG1 (0x131)
1254 #define SPR_HDSISR (0x132)
1255 #define SPR_HDAR (0x133)
1256 #define SPR_BOOKE_EPCR (0x133)
1257 #define SPR_SPURR (0x134)
1258 #define SPR_BOOKE_DBCR0 (0x134)
1259 #define SPR_IBCR (0x135)
1260 #define SPR_PURR (0x135)
1261 #define SPR_BOOKE_DBCR1 (0x135)
1262 #define SPR_DBCR (0x136)
1263 #define SPR_HDEC (0x136)
1264 #define SPR_BOOKE_DBCR2 (0x136)
1265 #define SPR_HIOR (0x137)
1266 #define SPR_MBAR (0x137)
1267 #define SPR_RMOR (0x138)
1268 #define SPR_BOOKE_IAC1 (0x138)
1269 #define SPR_HRMOR (0x139)
1270 #define SPR_BOOKE_IAC2 (0x139)
1271 #define SPR_HSRR0 (0x13A)
1272 #define SPR_BOOKE_IAC3 (0x13A)
1273 #define SPR_HSRR1 (0x13B)
1274 #define SPR_BOOKE_IAC4 (0x13B)
1275 #define SPR_LPCR (0x13C)
1276 #define SPR_BOOKE_DAC1 (0x13C)
1277 #define SPR_LPIDR (0x13D)
1278 #define SPR_DABR2 (0x13D)
1279 #define SPR_BOOKE_DAC2 (0x13D)
1280 #define SPR_BOOKE_DVC1 (0x13E)
1281 #define SPR_BOOKE_DVC2 (0x13F)
1282 #define SPR_BOOKE_TSR (0x150)
1283 #define SPR_BOOKE_TCR (0x154)
1284 #define SPR_BOOKE_IVOR0 (0x190)
1285 #define SPR_BOOKE_IVOR1 (0x191)
1286 #define SPR_BOOKE_IVOR2 (0x192)
1287 #define SPR_BOOKE_IVOR3 (0x193)
1288 #define SPR_BOOKE_IVOR4 (0x194)
1289 #define SPR_BOOKE_IVOR5 (0x195)
1290 #define SPR_BOOKE_IVOR6 (0x196)
1291 #define SPR_BOOKE_IVOR7 (0x197)
1292 #define SPR_BOOKE_IVOR8 (0x198)
1293 #define SPR_BOOKE_IVOR9 (0x199)
1294 #define SPR_BOOKE_IVOR10 (0x19A)
1295 #define SPR_BOOKE_IVOR11 (0x19B)
1296 #define SPR_BOOKE_IVOR12 (0x19C)
1297 #define SPR_BOOKE_IVOR13 (0x19D)
1298 #define SPR_BOOKE_IVOR14 (0x19E)
1299 #define SPR_BOOKE_IVOR15 (0x19F)
1300 #define SPR_BOOKE_SPEFSCR (0x200)
1301 #define SPR_Exxx_BBEAR (0x201)
1302 #define SPR_Exxx_BBTAR (0x202)
1303 #define SPR_Exxx_L1CFG0 (0x203)
1304 #define SPR_Exxx_NPIDR (0x205)
1305 #define SPR_ATBL (0x20E)
1306 #define SPR_ATBU (0x20F)
1307 #define SPR_IBAT0U (0x210)
1308 #define SPR_BOOKE_IVOR32 (0x210)
1309 #define SPR_RCPU_MI_GRA (0x210)
1310 #define SPR_IBAT0L (0x211)
1311 #define SPR_BOOKE_IVOR33 (0x211)
1312 #define SPR_IBAT1U (0x212)
1313 #define SPR_BOOKE_IVOR34 (0x212)
1314 #define SPR_IBAT1L (0x213)
1315 #define SPR_BOOKE_IVOR35 (0x213)
1316 #define SPR_IBAT2U (0x214)
1317 #define SPR_BOOKE_IVOR36 (0x214)
1318 #define SPR_IBAT2L (0x215)
1319 #define SPR_BOOKE_IVOR37 (0x215)
1320 #define SPR_IBAT3U (0x216)
1321 #define SPR_IBAT3L (0x217)
1322 #define SPR_DBAT0U (0x218)
1323 #define SPR_RCPU_L2U_GRA (0x218)
1324 #define SPR_DBAT0L (0x219)
1325 #define SPR_DBAT1U (0x21A)
1326 #define SPR_DBAT1L (0x21B)
1327 #define SPR_DBAT2U (0x21C)
1328 #define SPR_DBAT2L (0x21D)
1329 #define SPR_DBAT3U (0x21E)
1330 #define SPR_DBAT3L (0x21F)
1331 #define SPR_IBAT4U (0x230)
1332 #define SPR_RPCU_BBCMCR (0x230)
1333 #define SPR_MPC_IC_CST (0x230)
1334 #define SPR_Exxx_CTXCR (0x230)
1335 #define SPR_IBAT4L (0x231)
1336 #define SPR_MPC_IC_ADR (0x231)
1337 #define SPR_Exxx_DBCR3 (0x231)
1338 #define SPR_IBAT5U (0x232)
1339 #define SPR_MPC_IC_DAT (0x232)
1340 #define SPR_Exxx_DBCNT (0x232)
1341 #define SPR_IBAT5L (0x233)
1342 #define SPR_IBAT6U (0x234)
1343 #define SPR_IBAT6L (0x235)
1344 #define SPR_IBAT7U (0x236)
1345 #define SPR_IBAT7L (0x237)
1346 #define SPR_DBAT4U (0x238)
1347 #define SPR_RCPU_L2U_MCR (0x238)
1348 #define SPR_MPC_DC_CST (0x238)
1349 #define SPR_Exxx_ALTCTXCR (0x238)
1350 #define SPR_DBAT4L (0x239)
1351 #define SPR_MPC_DC_ADR (0x239)
1352 #define SPR_DBAT5U (0x23A)
1353 #define SPR_BOOKE_MCSRR0 (0x23A)
1354 #define SPR_MPC_DC_DAT (0x23A)
1355 #define SPR_DBAT5L (0x23B)
1356 #define SPR_BOOKE_MCSRR1 (0x23B)
1357 #define SPR_DBAT6U (0x23C)
1358 #define SPR_BOOKE_MCSR (0x23C)
1359 #define SPR_DBAT6L (0x23D)
1360 #define SPR_Exxx_MCAR (0x23D)
1361 #define SPR_DBAT7U (0x23E)
1362 #define SPR_BOOKE_DSRR0 (0x23E)
1363 #define SPR_DBAT7L (0x23F)
1364 #define SPR_BOOKE_DSRR1 (0x23F)
1365 #define SPR_BOOKE_SPRG8 (0x25C)
1366 #define SPR_BOOKE_SPRG9 (0x25D)
1367 #define SPR_BOOKE_MAS0 (0x270)
1368 #define SPR_BOOKE_MAS1 (0x271)
1369 #define SPR_BOOKE_MAS2 (0x272)
1370 #define SPR_BOOKE_MAS3 (0x273)
1371 #define SPR_BOOKE_MAS4 (0x274)
1372 #define SPR_BOOKE_MAS5 (0x275)
1373 #define SPR_BOOKE_MAS6 (0x276)
1374 #define SPR_BOOKE_PID1 (0x279)
1375 #define SPR_BOOKE_PID2 (0x27A)
1376 #define SPR_MPC_DPDR (0x280)
1377 #define SPR_MPC_IMMR (0x288)
1378 #define SPR_BOOKE_TLB0CFG (0x2B0)
1379 #define SPR_BOOKE_TLB1CFG (0x2B1)
1380 #define SPR_BOOKE_TLB2CFG (0x2B2)
1381 #define SPR_BOOKE_TLB3CFG (0x2B3)
1382 #define SPR_BOOKE_EPR (0x2BE)
1383 #define SPR_PERF0 (0x300)
1384 #define SPR_RCPU_MI_RBA0 (0x300)
1385 #define SPR_MPC_MI_CTR (0x300)
1386 #define SPR_PERF1 (0x301)
1387 #define SPR_RCPU_MI_RBA1 (0x301)
1388 #define SPR_PERF2 (0x302)
1389 #define SPR_RCPU_MI_RBA2 (0x302)
1390 #define SPR_MPC_MI_AP (0x302)
1391 #define SPR_PERF3 (0x303)
1392 #define SPR_620_PMC1R (0x303)
1393 #define SPR_RCPU_MI_RBA3 (0x303)
1394 #define SPR_MPC_MI_EPN (0x303)
1395 #define SPR_PERF4 (0x304)
1396 #define SPR_620_PMC2R (0x304)
1397 #define SPR_PERF5 (0x305)
1398 #define SPR_MPC_MI_TWC (0x305)
1399 #define SPR_PERF6 (0x306)
1400 #define SPR_MPC_MI_RPN (0x306)
1401 #define SPR_PERF7 (0x307)
1402 #define SPR_PERF8 (0x308)
1403 #define SPR_RCPU_L2U_RBA0 (0x308)
1404 #define SPR_MPC_MD_CTR (0x308)
1405 #define SPR_PERF9 (0x309)
1406 #define SPR_RCPU_L2U_RBA1 (0x309)
1407 #define SPR_MPC_MD_CASID (0x309)
1408 #define SPR_PERFA (0x30A)
1409 #define SPR_RCPU_L2U_RBA2 (0x30A)
1410 #define SPR_MPC_MD_AP (0x30A)
1411 #define SPR_PERFB (0x30B)
1412 #define SPR_620_MMCR0R (0x30B)
1413 #define SPR_RCPU_L2U_RBA3 (0x30B)
1414 #define SPR_MPC_MD_EPN (0x30B)
1415 #define SPR_PERFC (0x30C)
1416 #define SPR_MPC_MD_TWB (0x30C)
1417 #define SPR_PERFD (0x30D)
1418 #define SPR_MPC_MD_TWC (0x30D)
1419 #define SPR_PERFE (0x30E)
1420 #define SPR_MPC_MD_RPN (0x30E)
1421 #define SPR_PERFF (0x30F)
1422 #define SPR_MPC_MD_TW (0x30F)
1423 #define SPR_UPERF0 (0x310)
1424 #define SPR_UPERF1 (0x311)
1425 #define SPR_UPERF2 (0x312)
1426 #define SPR_UPERF3 (0x313)
1427 #define SPR_620_PMC1W (0x313)
1428 #define SPR_UPERF4 (0x314)
1429 #define SPR_620_PMC2W (0x314)
1430 #define SPR_UPERF5 (0x315)
1431 #define SPR_UPERF6 (0x316)
1432 #define SPR_UPERF7 (0x317)
1433 #define SPR_UPERF8 (0x318)
1434 #define SPR_UPERF9 (0x319)
1435 #define SPR_UPERFA (0x31A)
1436 #define SPR_UPERFB (0x31B)
1437 #define SPR_620_MMCR0W (0x31B)
1438 #define SPR_UPERFC (0x31C)
1439 #define SPR_UPERFD (0x31D)
1440 #define SPR_UPERFE (0x31E)
1441 #define SPR_UPERFF (0x31F)
1442 #define SPR_RCPU_MI_RA0 (0x320)
1443 #define SPR_MPC_MI_DBCAM (0x320)
1444 #define SPR_RCPU_MI_RA1 (0x321)
1445 #define SPR_MPC_MI_DBRAM0 (0x321)
1446 #define SPR_RCPU_MI_RA2 (0x322)
1447 #define SPR_MPC_MI_DBRAM1 (0x322)
1448 #define SPR_RCPU_MI_RA3 (0x323)
1449 #define SPR_RCPU_L2U_RA0 (0x328)
1450 #define SPR_MPC_MD_DBCAM (0x328)
1451 #define SPR_RCPU_L2U_RA1 (0x329)
1452 #define SPR_MPC_MD_DBRAM0 (0x329)
1453 #define SPR_RCPU_L2U_RA2 (0x32A)
1454 #define SPR_MPC_MD_DBRAM1 (0x32A)
1455 #define SPR_RCPU_L2U_RA3 (0x32B)
1456 #define SPR_440_INV0 (0x370)
1457 #define SPR_440_INV1 (0x371)
1458 #define SPR_440_INV2 (0x372)
1459 #define SPR_440_INV3 (0x373)
1460 #define SPR_440_ITV0 (0x374)
1461 #define SPR_440_ITV1 (0x375)
1462 #define SPR_440_ITV2 (0x376)
1463 #define SPR_440_ITV3 (0x377)
1464 #define SPR_440_CCR1 (0x378)
1465 #define SPR_DCRIPR (0x37B)
1466 #define SPR_PPR (0x380)
1467 #define SPR_750_GQR0 (0x390)
1468 #define SPR_440_DNV0 (0x390)
1469 #define SPR_750_GQR1 (0x391)
1470 #define SPR_440_DNV1 (0x391)
1471 #define SPR_750_GQR2 (0x392)
1472 #define SPR_440_DNV2 (0x392)
1473 #define SPR_750_GQR3 (0x393)
1474 #define SPR_440_DNV3 (0x393)
1475 #define SPR_750_GQR4 (0x394)
1476 #define SPR_440_DTV0 (0x394)
1477 #define SPR_750_GQR5 (0x395)
1478 #define SPR_440_DTV1 (0x395)
1479 #define SPR_750_GQR6 (0x396)
1480 #define SPR_440_DTV2 (0x396)
1481 #define SPR_750_GQR7 (0x397)
1482 #define SPR_440_DTV3 (0x397)
1483 #define SPR_750_THRM4 (0x398)
1484 #define SPR_750CL_HID2 (0x398)
1485 #define SPR_440_DVLIM (0x398)
1486 #define SPR_750_WPAR (0x399)
1487 #define SPR_440_IVLIM (0x399)
1488 #define SPR_750_DMAU (0x39A)
1489 #define SPR_750_DMAL (0x39B)
1490 #define SPR_440_RSTCFG (0x39B)
1491 #define SPR_BOOKE_DCDBTRL (0x39C)
1492 #define SPR_BOOKE_DCDBTRH (0x39D)
1493 #define SPR_BOOKE_ICDBTRL (0x39E)
1494 #define SPR_BOOKE_ICDBTRH (0x39F)
1495 #define SPR_UMMCR2 (0x3A0)
1496 #define SPR_UPMC5 (0x3A1)
1497 #define SPR_UPMC6 (0x3A2)
1498 #define SPR_UBAMR (0x3A7)
1499 #define SPR_UMMCR0 (0x3A8)
1500 #define SPR_UPMC1 (0x3A9)
1501 #define SPR_UPMC2 (0x3AA)
1502 #define SPR_USIAR (0x3AB)
1503 #define SPR_UMMCR1 (0x3AC)
1504 #define SPR_UPMC3 (0x3AD)
1505 #define SPR_UPMC4 (0x3AE)
1506 #define SPR_USDA (0x3AF)
1507 #define SPR_40x_ZPR (0x3B0)
1508 #define SPR_BOOKE_MAS7 (0x3B0)
1509 #define SPR_620_PMR0 (0x3B0)
1510 #define SPR_MMCR2 (0x3B0)
1511 #define SPR_PMC5 (0x3B1)
1512 #define SPR_40x_PID (0x3B1)
1513 #define SPR_620_PMR1 (0x3B1)
1514 #define SPR_PMC6 (0x3B2)
1515 #define SPR_440_MMUCR (0x3B2)
1516 #define SPR_620_PMR2 (0x3B2)
1517 #define SPR_4xx_CCR0 (0x3B3)
1518 #define SPR_BOOKE_EPLC (0x3B3)
1519 #define SPR_620_PMR3 (0x3B3)
1520 #define SPR_405_IAC3 (0x3B4)
1521 #define SPR_BOOKE_EPSC (0x3B4)
1522 #define SPR_620_PMR4 (0x3B4)
1523 #define SPR_405_IAC4 (0x3B5)
1524 #define SPR_620_PMR5 (0x3B5)
1525 #define SPR_405_DVC1 (0x3B6)
1526 #define SPR_620_PMR6 (0x3B6)
1527 #define SPR_405_DVC2 (0x3B7)
1528 #define SPR_620_PMR7 (0x3B7)
1529 #define SPR_BAMR (0x3B7)
1530 #define SPR_MMCR0 (0x3B8)
1531 #define SPR_620_PMR8 (0x3B8)
1532 #define SPR_PMC1 (0x3B9)
1533 #define SPR_40x_SGR (0x3B9)
1534 #define SPR_620_PMR9 (0x3B9)
1535 #define SPR_PMC2 (0x3BA)
1536 #define SPR_40x_DCWR (0x3BA)
1537 #define SPR_620_PMRA (0x3BA)
1538 #define SPR_SIAR (0x3BB)
1539 #define SPR_405_SLER (0x3BB)
1540 #define SPR_620_PMRB (0x3BB)
1541 #define SPR_MMCR1 (0x3BC)
1542 #define SPR_405_SU0R (0x3BC)
1543 #define SPR_620_PMRC (0x3BC)
1544 #define SPR_401_SKR (0x3BC)
1545 #define SPR_PMC3 (0x3BD)
1546 #define SPR_405_DBCR1 (0x3BD)
1547 #define SPR_620_PMRD (0x3BD)
1548 #define SPR_PMC4 (0x3BE)
1549 #define SPR_620_PMRE (0x3BE)
1550 #define SPR_SDA (0x3BF)
1551 #define SPR_620_PMRF (0x3BF)
1552 #define SPR_403_VTBL (0x3CC)
1553 #define SPR_403_VTBU (0x3CD)
1554 #define SPR_DMISS (0x3D0)
1555 #define SPR_DCMP (0x3D1)
1556 #define SPR_HASH1 (0x3D2)
1557 #define SPR_HASH2 (0x3D3)
1558 #define SPR_BOOKE_ICDBDR (0x3D3)
1559 #define SPR_TLBMISS (0x3D4)
1560 #define SPR_IMISS (0x3D4)
1561 #define SPR_40x_ESR (0x3D4)
1562 #define SPR_PTEHI (0x3D5)
1563 #define SPR_ICMP (0x3D5)
1564 #define SPR_40x_DEAR (0x3D5)
1565 #define SPR_PTELO (0x3D6)
1566 #define SPR_RPA (0x3D6)
1567 #define SPR_40x_EVPR (0x3D6)
1568 #define SPR_L3PM (0x3D7)
1569 #define SPR_403_CDBCR (0x3D7)
1570 #define SPR_L3ITCR0 (0x3D8)
1571 #define SPR_TCR (0x3D8)
1572 #define SPR_40x_TSR (0x3D8)
1573 #define SPR_IBR (0x3DA)
1574 #define SPR_40x_TCR (0x3DA)
1575 #define SPR_ESASRR (0x3DB)
1576 #define SPR_40x_PIT (0x3DB)
1577 #define SPR_403_TBL (0x3DC)
1578 #define SPR_403_TBU (0x3DD)
1579 #define SPR_SEBR (0x3DE)
1580 #define SPR_40x_SRR2 (0x3DE)
1581 #define SPR_SER (0x3DF)
1582 #define SPR_40x_SRR3 (0x3DF)
1583 #define SPR_L3OHCR (0x3E8)
1584 #define SPR_L3ITCR1 (0x3E9)
1585 #define SPR_L3ITCR2 (0x3EA)
1586 #define SPR_L3ITCR3 (0x3EB)
1587 #define SPR_HID0 (0x3F0)
1588 #define SPR_40x_DBSR (0x3F0)
1589 #define SPR_HID1 (0x3F1)
1590 #define SPR_IABR (0x3F2)
1591 #define SPR_40x_DBCR0 (0x3F2)
1592 #define SPR_601_HID2 (0x3F2)
1593 #define SPR_Exxx_L1CSR0 (0x3F2)
1594 #define SPR_ICTRL (0x3F3)
1595 #define SPR_HID2 (0x3F3)
1596 #define SPR_750CL_HID4 (0x3F3)
1597 #define SPR_Exxx_L1CSR1 (0x3F3)
1598 #define SPR_440_DBDR (0x3F3)
1599 #define SPR_LDSTDB (0x3F4)
1600 #define SPR_750_TDCL (0x3F4)
1601 #define SPR_40x_IAC1 (0x3F4)
1602 #define SPR_MMUCSR0 (0x3F4)
1603 #define SPR_DABR (0x3F5)
1604 #define DABR_MASK (~(target_ulong)0x7)
1605 #define SPR_Exxx_BUCSR (0x3F5)
1606 #define SPR_40x_IAC2 (0x3F5)
1607 #define SPR_601_HID5 (0x3F5)
1608 #define SPR_40x_DAC1 (0x3F6)
1609 #define SPR_MSSCR0 (0x3F6)
1610 #define SPR_970_HID5 (0x3F6)
1611 #define SPR_MSSSR0 (0x3F7)
1612 #define SPR_MSSCR1 (0x3F7)
1613 #define SPR_DABRX (0x3F7)
1614 #define SPR_40x_DAC2 (0x3F7)
1615 #define SPR_MMUCFG (0x3F7)
1616 #define SPR_LDSTCR (0x3F8)
1617 #define SPR_L2PMCR (0x3F8)
1618 #define SPR_750FX_HID2 (0x3F8)
1619 #define SPR_620_BUSCSR (0x3F8)
1620 #define SPR_Exxx_L1FINV0 (0x3F8)
1621 #define SPR_L2CR (0x3F9)
1622 #define SPR_620_L2CR (0x3F9)
1623 #define SPR_L3CR (0x3FA)
1624 #define SPR_750_TDCH (0x3FA)
1625 #define SPR_IABR2 (0x3FA)
1626 #define SPR_40x_DCCR (0x3FA)
1627 #define SPR_620_L2SR (0x3FA)
1628 #define SPR_ICTC (0x3FB)
1629 #define SPR_40x_ICCR (0x3FB)
1630 #define SPR_THRM1 (0x3FC)
1631 #define SPR_403_PBL1 (0x3FC)
1632 #define SPR_SP (0x3FD)
1633 #define SPR_THRM2 (0x3FD)
1634 #define SPR_403_PBU1 (0x3FD)
1635 #define SPR_604_HID13 (0x3FD)
1636 #define SPR_LT (0x3FE)
1637 #define SPR_THRM3 (0x3FE)
1638 #define SPR_RCPU_FPECR (0x3FE)
1639 #define SPR_403_PBL2 (0x3FE)
1640 #define SPR_PIR (0x3FF)
1641 #define SPR_403_PBU2 (0x3FF)
1642 #define SPR_601_HID15 (0x3FF)
1643 #define SPR_604_HID15 (0x3FF)
1644 #define SPR_E500_SVR (0x3FF)
1645
1646 /*****************************************************************************/
1647 /* PowerPC Instructions types definitions */
1648 enum {
1649 PPC_NONE = 0x0000000000000000ULL,
1650 /* PowerPC base instructions set */
1651 PPC_INSNS_BASE = 0x0000000000000001ULL,
1652 /* integer operations instructions */
1653 #define PPC_INTEGER PPC_INSNS_BASE
1654 /* flow control instructions */
1655 #define PPC_FLOW PPC_INSNS_BASE
1656 /* virtual memory instructions */
1657 #define PPC_MEM PPC_INSNS_BASE
1658 /* ld/st with reservation instructions */
1659 #define PPC_RES PPC_INSNS_BASE
1660 /* spr/msr access instructions */
1661 #define PPC_MISC PPC_INSNS_BASE
1662 /* Deprecated instruction sets */
1663 /* Original POWER instruction set */
1664 PPC_POWER = 0x0000000000000002ULL,
1665 /* POWER2 instruction set extension */
1666 PPC_POWER2 = 0x0000000000000004ULL,
1667 /* Power RTC support */
1668 PPC_POWER_RTC = 0x0000000000000008ULL,
1669 /* Power-to-PowerPC bridge (601) */
1670 PPC_POWER_BR = 0x0000000000000010ULL,
1671 /* 64 bits PowerPC instruction set */
1672 PPC_64B = 0x0000000000000020ULL,
1673 /* New 64 bits extensions (PowerPC 2.0x) */
1674 PPC_64BX = 0x0000000000000040ULL,
1675 /* 64 bits hypervisor extensions */
1676 PPC_64H = 0x0000000000000080ULL,
1677 /* New wait instruction (PowerPC 2.0x) */
1678 PPC_WAIT = 0x0000000000000100ULL,
1679 /* Time base mftb instruction */
1680 PPC_MFTB = 0x0000000000000200ULL,
1681
1682 /* Fixed-point unit extensions */
1683 /* PowerPC 602 specific */
1684 PPC_602_SPEC = 0x0000000000000400ULL,
1685 /* isel instruction */
1686 PPC_ISEL = 0x0000000000000800ULL,
1687 /* popcntb instruction */
1688 PPC_POPCNTB = 0x0000000000001000ULL,
1689 /* string load / store */
1690 PPC_STRING = 0x0000000000002000ULL,
1691
1692 /* Floating-point unit extensions */
1693 /* Optional floating point instructions */
1694 PPC_FLOAT = 0x0000000000010000ULL,
1695 /* New floating-point extensions (PowerPC 2.0x) */
1696 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1697 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1698 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1699 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1700 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1701 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1702 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1703
1704 /* Vector/SIMD extensions */
1705 /* Altivec support */
1706 PPC_ALTIVEC = 0x0000000001000000ULL,
1707 /* PowerPC 2.03 SPE extension */
1708 PPC_SPE = 0x0000000002000000ULL,
1709 /* PowerPC 2.03 SPE single-precision floating-point extension */
1710 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1711 /* PowerPC 2.03 SPE double-precision floating-point extension */
1712 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1713
1714 /* Optional memory control instructions */
1715 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1716 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1717 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1718 /* sync instruction */
1719 PPC_MEM_SYNC = 0x0000000080000000ULL,
1720 /* eieio instruction */
1721 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1722
1723 /* Cache control instructions */
1724 PPC_CACHE = 0x0000000200000000ULL,
1725 /* icbi instruction */
1726 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1727 /* dcbz instruction with fixed cache line size */
1728 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1729 /* dcbz instruction with tunable cache line size */
1730 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1731 /* dcba instruction */
1732 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1733 /* Freescale cache locking instructions */
1734 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1735
1736 /* MMU related extensions */
1737 /* external control instructions */
1738 PPC_EXTERN = 0x0000010000000000ULL,
1739 /* segment register access instructions */
1740 PPC_SEGMENT = 0x0000020000000000ULL,
1741 /* PowerPC 6xx TLB management instructions */
1742 PPC_6xx_TLB = 0x0000040000000000ULL,
1743 /* PowerPC 74xx TLB management instructions */
1744 PPC_74xx_TLB = 0x0000080000000000ULL,
1745 /* PowerPC 40x TLB management instructions */
1746 PPC_40x_TLB = 0x0000100000000000ULL,
1747 /* segment register access instructions for PowerPC 64 "bridge" */
1748 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1749 /* SLB management */
1750 PPC_SLBI = 0x0000400000000000ULL,
1751
1752 /* Embedded PowerPC dedicated instructions */
1753 PPC_WRTEE = 0x0001000000000000ULL,
1754 /* PowerPC 40x exception model */
1755 PPC_40x_EXCP = 0x0002000000000000ULL,
1756 /* PowerPC 405 Mac instructions */
1757 PPC_405_MAC = 0x0004000000000000ULL,
1758 /* PowerPC 440 specific instructions */
1759 PPC_440_SPEC = 0x0008000000000000ULL,
1760 /* BookE (embedded) PowerPC specification */
1761 PPC_BOOKE = 0x0010000000000000ULL,
1762 /* mfapidi instruction */
1763 PPC_MFAPIDI = 0x0020000000000000ULL,
1764 /* tlbiva instruction */
1765 PPC_TLBIVA = 0x0040000000000000ULL,
1766 /* tlbivax instruction */
1767 PPC_TLBIVAX = 0x0080000000000000ULL,
1768 /* PowerPC 4xx dedicated instructions */
1769 PPC_4xx_COMMON = 0x0100000000000000ULL,
1770 /* PowerPC 40x ibct instructions */
1771 PPC_40x_ICBT = 0x0200000000000000ULL,
1772 /* rfmci is not implemented in all BookE PowerPC */
1773 PPC_RFMCI = 0x0400000000000000ULL,
1774 /* rfdi instruction */
1775 PPC_RFDI = 0x0800000000000000ULL,
1776 /* DCR accesses */
1777 PPC_DCR = 0x1000000000000000ULL,
1778 /* DCR extended accesse */
1779 PPC_DCRX = 0x2000000000000000ULL,
1780 /* user-mode DCR access, implemented in PowerPC 460 */
1781 PPC_DCRUX = 0x4000000000000000ULL,
1782 /* popcntw and popcntd instructions */
1783 PPC_POPCNTWD = 0x8000000000000000ULL,
1784
1785 /* extended type values */
1786
1787 /* BookE 2.06 PowerPC specification */
1788 PPC2_BOOKE206 = 0x0000000000000001ULL,
1789 };
1790
1791 /*****************************************************************************/
1792 /* Memory access type :
1793 * may be needed for precise access rights control and precise exceptions.
1794 */
1795 enum {
1796 /* 1 bit to define user level / supervisor access */
1797 ACCESS_USER = 0x00,
1798 ACCESS_SUPER = 0x01,
1799 /* Type of instruction that generated the access */
1800 ACCESS_CODE = 0x10, /* Code fetch access */
1801 ACCESS_INT = 0x20, /* Integer load/store access */
1802 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1803 ACCESS_RES = 0x40, /* load/store with reservation */
1804 ACCESS_EXT = 0x50, /* external access */
1805 ACCESS_CACHE = 0x60, /* Cache manipulation */
1806 };
1807
1808 /* Hardware interruption sources:
1809 * all those exception can be raised simulteaneously
1810 */
1811 /* Input pins definitions */
1812 enum {
1813 /* 6xx bus input pins */
1814 PPC6xx_INPUT_HRESET = 0,
1815 PPC6xx_INPUT_SRESET = 1,
1816 PPC6xx_INPUT_CKSTP_IN = 2,
1817 PPC6xx_INPUT_MCP = 3,
1818 PPC6xx_INPUT_SMI = 4,
1819 PPC6xx_INPUT_INT = 5,
1820 PPC6xx_INPUT_TBEN = 6,
1821 PPC6xx_INPUT_WAKEUP = 7,
1822 PPC6xx_INPUT_NB,
1823 };
1824
1825 enum {
1826 /* Embedded PowerPC input pins */
1827 PPCBookE_INPUT_HRESET = 0,
1828 PPCBookE_INPUT_SRESET = 1,
1829 PPCBookE_INPUT_CKSTP_IN = 2,
1830 PPCBookE_INPUT_MCP = 3,
1831 PPCBookE_INPUT_SMI = 4,
1832 PPCBookE_INPUT_INT = 5,
1833 PPCBookE_INPUT_CINT = 6,
1834 PPCBookE_INPUT_NB,
1835 };
1836
1837 enum {
1838 /* PowerPC E500 input pins */
1839 PPCE500_INPUT_RESET_CORE = 0,
1840 PPCE500_INPUT_MCK = 1,
1841 PPCE500_INPUT_CINT = 3,
1842 PPCE500_INPUT_INT = 4,
1843 PPCE500_INPUT_DEBUG = 6,
1844 PPCE500_INPUT_NB,
1845 };
1846
1847 enum {
1848 /* PowerPC 40x input pins */
1849 PPC40x_INPUT_RESET_CORE = 0,
1850 PPC40x_INPUT_RESET_CHIP = 1,
1851 PPC40x_INPUT_RESET_SYS = 2,
1852 PPC40x_INPUT_CINT = 3,
1853 PPC40x_INPUT_INT = 4,
1854 PPC40x_INPUT_HALT = 5,
1855 PPC40x_INPUT_DEBUG = 6,
1856 PPC40x_INPUT_NB,
1857 };
1858
1859 enum {
1860 /* RCPU input pins */
1861 PPCRCPU_INPUT_PORESET = 0,
1862 PPCRCPU_INPUT_HRESET = 1,
1863 PPCRCPU_INPUT_SRESET = 2,
1864 PPCRCPU_INPUT_IRQ0 = 3,
1865 PPCRCPU_INPUT_IRQ1 = 4,
1866 PPCRCPU_INPUT_IRQ2 = 5,
1867 PPCRCPU_INPUT_IRQ3 = 6,
1868 PPCRCPU_INPUT_IRQ4 = 7,
1869 PPCRCPU_INPUT_IRQ5 = 8,
1870 PPCRCPU_INPUT_IRQ6 = 9,
1871 PPCRCPU_INPUT_IRQ7 = 10,
1872 PPCRCPU_INPUT_NB,
1873 };
1874
1875 #if defined(TARGET_PPC64)
1876 enum {
1877 /* PowerPC 970 input pins */
1878 PPC970_INPUT_HRESET = 0,
1879 PPC970_INPUT_SRESET = 1,
1880 PPC970_INPUT_CKSTP = 2,
1881 PPC970_INPUT_TBEN = 3,
1882 PPC970_INPUT_MCP = 4,
1883 PPC970_INPUT_INT = 5,
1884 PPC970_INPUT_THINT = 6,
1885 PPC970_INPUT_NB,
1886 };
1887
1888 enum {
1889 /* POWER7 input pins */
1890 POWER7_INPUT_INT = 0,
1891 /* POWER7 probably has other inputs, but we don't care about them
1892 * for any existing machine. We can wire these up when we need
1893 * them */
1894 POWER7_INPUT_NB,
1895 };
1896 #endif
1897
1898 /* Hardware exceptions definitions */
1899 enum {
1900 /* External hardware exception sources */
1901 PPC_INTERRUPT_RESET = 0, /* Reset exception */
1902 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1903 PPC_INTERRUPT_MCK, /* Machine check exception */
1904 PPC_INTERRUPT_EXT, /* External interrupt */
1905 PPC_INTERRUPT_SMI, /* System management interrupt */
1906 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1907 PPC_INTERRUPT_DEBUG, /* External debug exception */
1908 PPC_INTERRUPT_THERM, /* Thermal exception */
1909 /* Internal hardware exception sources */
1910 PPC_INTERRUPT_DECR, /* Decrementer exception */
1911 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1912 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1913 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1914 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1915 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1916 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1917 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
1918 };
1919
1920 /*****************************************************************************/
1921
1922 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
1923 target_ulong *cs_base, int *flags)
1924 {
1925 *pc = env->nip;
1926 *cs_base = 0;
1927 *flags = env->hflags;
1928 }
1929
1930 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
1931 {
1932 #if defined(TARGET_PPC64)
1933 /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
1934 binaries on PPC64 yet. */
1935 env->gpr[13] = newtls;
1936 #else
1937 env->gpr[2] = newtls;
1938 #endif
1939 }
1940
1941 #if !defined(CONFIG_USER_ONLY)
1942 static inline int booke206_tlbm_id(CPUState *env, ppcmas_tlb_t *tlbm)
1943 {
1944 uintptr_t tlbml = (uintptr_t)tlbm;
1945 uintptr_t tlbl = (uintptr_t)env->tlb;
1946
1947 return (tlbml - tlbl) / sizeof(env->tlb[0]);
1948 }
1949
1950 static inline int booke206_tlb_size(CPUState *env, int tlbn)
1951 {
1952 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
1953 int r = tlbncfg & TLBnCFG_N_ENTRY;
1954 return r;
1955 }
1956
1957 static inline int booke206_tlb_ways(CPUState *env, int tlbn)
1958 {
1959 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
1960 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
1961 return r;
1962 }
1963
1964 static inline int booke206_tlbm_to_tlbn(CPUState *env, ppcmas_tlb_t *tlbm)
1965 {
1966 int id = booke206_tlbm_id(env, tlbm);
1967 int end = 0;
1968 int i;
1969
1970 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
1971 end += booke206_tlb_size(env, i);
1972 if (id < end) {
1973 return i;
1974 }
1975 }
1976
1977 cpu_abort(env, "Unknown TLBe: %d\n", id);
1978 return 0;
1979 }
1980
1981 static inline int booke206_tlbm_to_way(CPUState *env, ppcmas_tlb_t *tlb)
1982 {
1983 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
1984 int tlbid = booke206_tlbm_id(env, tlb);
1985 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
1986 }
1987
1988 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUState *env, const int tlbn,
1989 target_ulong ea, int way)
1990 {
1991 int r;
1992 uint32_t ways = booke206_tlb_ways(env, tlbn);
1993 int ways_bits = ffs(ways) - 1;
1994 int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
1995 int i;
1996
1997 way &= ways - 1;
1998 ea >>= MAS2_EPN_SHIFT;
1999 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2000 r = (ea << ways_bits) | way;
2001
2002 /* bump up to tlbn index */
2003 for (i = 0; i < tlbn; i++) {
2004 r += booke206_tlb_size(env, i);
2005 }
2006
2007 return &env->tlb[r].tlbm;
2008 }
2009
2010 #endif
2011
2012 extern void (*cpu_ppc_hypercall)(CPUState *);
2013
2014 #endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing