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Correct ppc popcntb logic, implement popcntw and popcntd
[qemu.git] / target-ppc / cpu.h
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 //#define PPC_EMULATE_32BITS_HYPV
26
27 #if defined (TARGET_PPC64)
28 /* PowerPC 64 definitions */
29 #define TARGET_LONG_BITS 64
30 #define TARGET_PAGE_BITS 12
31
32 /* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35 #define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37 /* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40 #ifdef TARGET_ABI32
41 # define TARGET_VIRT_ADDR_SPACE_BITS 32
42 #else
43 # define TARGET_VIRT_ADDR_SPACE_BITS 64
44 #endif
45
46 #define TARGET_PAGE_BITS_16M 24
47
48 #else /* defined (TARGET_PPC64) */
49 /* PowerPC 32 definitions */
50 #define TARGET_LONG_BITS 32
51
52 #if defined(TARGET_PPCEMB)
53 /* Specific definitions for PowerPC embedded */
54 /* BookE have 36 bits physical address space */
55 #if defined(CONFIG_USER_ONLY)
56 /* It looks like a lot of Linux programs assume page size
57 * is 4kB long. This is evil, but we have to deal with it...
58 */
59 #define TARGET_PAGE_BITS 12
60 #else /* defined(CONFIG_USER_ONLY) */
61 /* Pages can be 1 kB small */
62 #define TARGET_PAGE_BITS 10
63 #endif /* defined(CONFIG_USER_ONLY) */
64 #else /* defined(TARGET_PPCEMB) */
65 /* "standard" PowerPC 32 definitions */
66 #define TARGET_PAGE_BITS 12
67 #endif /* defined(TARGET_PPCEMB) */
68
69 #define TARGET_PHYS_ADDR_SPACE_BITS 32
70 #define TARGET_VIRT_ADDR_SPACE_BITS 32
71
72 #endif /* defined (TARGET_PPC64) */
73
74 #define CPUState struct CPUPPCState
75
76 #include "cpu-defs.h"
77
78 #include <setjmp.h>
79
80 #include "softfloat.h"
81
82 #define TARGET_HAS_ICE 1
83
84 #if defined (TARGET_PPC64)
85 #define ELF_MACHINE EM_PPC64
86 #else
87 #define ELF_MACHINE EM_PPC
88 #endif
89
90 /*****************************************************************************/
91 /* MMU model */
92 typedef enum powerpc_mmu_t powerpc_mmu_t;
93 enum powerpc_mmu_t {
94 POWERPC_MMU_UNKNOWN = 0x00000000,
95 /* Standard 32 bits PowerPC MMU */
96 POWERPC_MMU_32B = 0x00000001,
97 /* PowerPC 6xx MMU with software TLB */
98 POWERPC_MMU_SOFT_6xx = 0x00000002,
99 /* PowerPC 74xx MMU with software TLB */
100 POWERPC_MMU_SOFT_74xx = 0x00000003,
101 /* PowerPC 4xx MMU with software TLB */
102 POWERPC_MMU_SOFT_4xx = 0x00000004,
103 /* PowerPC 4xx MMU with software TLB and zones protections */
104 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
105 /* PowerPC MMU in real mode only */
106 POWERPC_MMU_REAL = 0x00000006,
107 /* Freescale MPC8xx MMU model */
108 POWERPC_MMU_MPC8xx = 0x00000007,
109 /* BookE MMU model */
110 POWERPC_MMU_BOOKE = 0x00000008,
111 /* BookE FSL MMU model */
112 POWERPC_MMU_BOOKE_FSL = 0x00000009,
113 /* PowerPC 601 MMU model (specific BATs format) */
114 POWERPC_MMU_601 = 0x0000000A,
115 #if defined(TARGET_PPC64)
116 #define POWERPC_MMU_64 0x00010000
117 /* 64 bits PowerPC MMU */
118 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
119 /* 620 variant (no segment exceptions) */
120 POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
121 #endif /* defined(TARGET_PPC64) */
122 };
123
124 /*****************************************************************************/
125 /* Exception model */
126 typedef enum powerpc_excp_t powerpc_excp_t;
127 enum powerpc_excp_t {
128 POWERPC_EXCP_UNKNOWN = 0,
129 /* Standard PowerPC exception model */
130 POWERPC_EXCP_STD,
131 /* PowerPC 40x exception model */
132 POWERPC_EXCP_40x,
133 /* PowerPC 601 exception model */
134 POWERPC_EXCP_601,
135 /* PowerPC 602 exception model */
136 POWERPC_EXCP_602,
137 /* PowerPC 603 exception model */
138 POWERPC_EXCP_603,
139 /* PowerPC 603e exception model */
140 POWERPC_EXCP_603E,
141 /* PowerPC G2 exception model */
142 POWERPC_EXCP_G2,
143 /* PowerPC 604 exception model */
144 POWERPC_EXCP_604,
145 /* PowerPC 7x0 exception model */
146 POWERPC_EXCP_7x0,
147 /* PowerPC 7x5 exception model */
148 POWERPC_EXCP_7x5,
149 /* PowerPC 74xx exception model */
150 POWERPC_EXCP_74xx,
151 /* BookE exception model */
152 POWERPC_EXCP_BOOKE,
153 #if defined(TARGET_PPC64)
154 /* PowerPC 970 exception model */
155 POWERPC_EXCP_970,
156 #endif /* defined(TARGET_PPC64) */
157 };
158
159 /*****************************************************************************/
160 /* Exception vectors definitions */
161 enum {
162 POWERPC_EXCP_NONE = -1,
163 /* The 64 first entries are used by the PowerPC embedded specification */
164 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
165 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
166 POWERPC_EXCP_DSI = 2, /* Data storage exception */
167 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
168 POWERPC_EXCP_EXTERNAL = 4, /* External input */
169 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
170 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
171 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
172 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
173 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
174 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
175 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
176 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
177 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
178 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
179 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
180 /* Vectors 16 to 31 are reserved */
181 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
182 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
183 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
184 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
185 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
186 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
187 /* Vectors 38 to 63 are reserved */
188 /* Exceptions defined in the PowerPC server specification */
189 POWERPC_EXCP_RESET = 64, /* System reset exception */
190 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
191 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
192 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
193 POWERPC_EXCP_TRACE = 68, /* Trace exception */
194 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
195 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
196 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
197 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
198 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
199 /* 40x specific exceptions */
200 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
201 /* 601 specific exceptions */
202 POWERPC_EXCP_IO = 75, /* IO error exception */
203 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
204 /* 602 specific exceptions */
205 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
206 /* 602/603 specific exceptions */
207 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
208 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
209 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
210 /* Exceptions available on most PowerPC */
211 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
212 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
213 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
214 POWERPC_EXCP_SMI = 84, /* System management interrupt */
215 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
216 /* 7xx/74xx specific exceptions */
217 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
218 /* 74xx specific exceptions */
219 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
220 /* 970FX specific exceptions */
221 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
222 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
223 /* Freescale embeded cores specific exceptions */
224 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
225 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
226 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
227 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
228 /* EOL */
229 POWERPC_EXCP_NB = 96,
230 /* Qemu exceptions: used internally during code translation */
231 POWERPC_EXCP_STOP = 0x200, /* stop translation */
232 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
233 /* Qemu exceptions: special cases we want to stop translation */
234 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
235 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
236 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
237 };
238
239 /* Exceptions error codes */
240 enum {
241 /* Exception subtypes for POWERPC_EXCP_ALIGN */
242 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
243 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
244 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
245 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
246 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
247 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
248 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
249 /* FP exceptions */
250 POWERPC_EXCP_FP = 0x10,
251 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
252 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
253 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
254 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
255 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
256 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
257 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
258 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
259 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
260 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
261 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
262 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
263 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
264 /* Invalid instruction */
265 POWERPC_EXCP_INVAL = 0x20,
266 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
267 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
268 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
269 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
270 /* Privileged instruction */
271 POWERPC_EXCP_PRIV = 0x30,
272 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
273 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
274 /* Trap */
275 POWERPC_EXCP_TRAP = 0x40,
276 };
277
278 /*****************************************************************************/
279 /* Input pins model */
280 typedef enum powerpc_input_t powerpc_input_t;
281 enum powerpc_input_t {
282 PPC_FLAGS_INPUT_UNKNOWN = 0,
283 /* PowerPC 6xx bus */
284 PPC_FLAGS_INPUT_6xx,
285 /* BookE bus */
286 PPC_FLAGS_INPUT_BookE,
287 /* PowerPC 405 bus */
288 PPC_FLAGS_INPUT_405,
289 /* PowerPC 970 bus */
290 PPC_FLAGS_INPUT_970,
291 /* PowerPC 401 bus */
292 PPC_FLAGS_INPUT_401,
293 /* Freescale RCPU bus */
294 PPC_FLAGS_INPUT_RCPU,
295 };
296
297 #define PPC_INPUT(env) (env->bus_model)
298
299 /*****************************************************************************/
300 typedef struct ppc_def_t ppc_def_t;
301 typedef struct opc_handler_t opc_handler_t;
302
303 /*****************************************************************************/
304 /* Types used to describe some PowerPC registers */
305 typedef struct CPUPPCState CPUPPCState;
306 typedef struct ppc_tb_t ppc_tb_t;
307 typedef struct ppc_spr_t ppc_spr_t;
308 typedef struct ppc_dcr_t ppc_dcr_t;
309 typedef union ppc_avr_t ppc_avr_t;
310 typedef union ppc_tlb_t ppc_tlb_t;
311
312 /* SPR access micro-ops generations callbacks */
313 struct ppc_spr_t {
314 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
315 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
316 #if !defined(CONFIG_USER_ONLY)
317 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
318 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
319 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
320 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
321 #endif
322 const char *name;
323 };
324
325 /* Altivec registers (128 bits) */
326 union ppc_avr_t {
327 float32 f[4];
328 uint8_t u8[16];
329 uint16_t u16[8];
330 uint32_t u32[4];
331 int8_t s8[16];
332 int16_t s16[8];
333 int32_t s32[4];
334 uint64_t u64[2];
335 };
336
337 #if !defined(CONFIG_USER_ONLY)
338 /* Software TLB cache */
339 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
340 struct ppc6xx_tlb_t {
341 target_ulong pte0;
342 target_ulong pte1;
343 target_ulong EPN;
344 };
345
346 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
347 struct ppcemb_tlb_t {
348 target_phys_addr_t RPN;
349 target_ulong EPN;
350 target_ulong PID;
351 target_ulong size;
352 uint32_t prot;
353 uint32_t attr; /* Storage attributes */
354 };
355
356 union ppc_tlb_t {
357 ppc6xx_tlb_t tlb6;
358 ppcemb_tlb_t tlbe;
359 };
360 #endif
361
362 typedef struct ppc_slb_t ppc_slb_t;
363 struct ppc_slb_t {
364 uint64_t esid;
365 uint64_t vsid;
366 };
367
368 /* Bits in the SLB ESID word */
369 #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
370 #define SLB_ESID_V 0x0000000008000000ULL /* valid */
371
372 /* Bits in the SLB VSID word */
373 #define SLB_VSID_SHIFT 12
374 #define SLB_VSID_SSIZE_SHIFT 62
375 #define SLB_VSID_B 0xc000000000000000ULL
376 #define SLB_VSID_B_256M 0x0000000000000000ULL
377 #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
378 #define SLB_VSID_KS 0x0000000000000800ULL
379 #define SLB_VSID_KP 0x0000000000000400ULL
380 #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
381 #define SLB_VSID_L 0x0000000000000100ULL
382 #define SLB_VSID_C 0x0000000000000080ULL /* class */
383 #define SLB_VSID_LP 0x0000000000000030ULL
384 #define SLB_VSID_ATTR 0x0000000000000FFFULL
385
386 #define SEGMENT_SHIFT_256M 28
387 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
388
389 /*****************************************************************************/
390 /* Machine state register bits definition */
391 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
392 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
393 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
394 #define MSR_SHV 60 /* hypervisor state hflags */
395 #define MSR_CM 31 /* Computation mode for BookE hflags */
396 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
397 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
398 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
399 #define MSR_VR 25 /* altivec available x hflags */
400 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
401 #define MSR_AP 23 /* Access privilege state on 602 hflags */
402 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
403 #define MSR_KEY 19 /* key bit on 603e */
404 #define MSR_POW 18 /* Power management */
405 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
406 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
407 #define MSR_ILE 16 /* Interrupt little-endian mode */
408 #define MSR_EE 15 /* External interrupt enable */
409 #define MSR_PR 14 /* Problem state hflags */
410 #define MSR_FP 13 /* Floating point available hflags */
411 #define MSR_ME 12 /* Machine check interrupt enable */
412 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
413 #define MSR_SE 10 /* Single-step trace enable x hflags */
414 #define MSR_DWE 10 /* Debug wait enable on 405 x */
415 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
416 #define MSR_BE 9 /* Branch trace enable x hflags */
417 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
418 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
419 #define MSR_AL 7 /* AL bit on POWER */
420 #define MSR_EP 6 /* Exception prefix on 601 */
421 #define MSR_IR 5 /* Instruction relocate */
422 #define MSR_DR 4 /* Data relocate */
423 #define MSR_PE 3 /* Protection enable on 403 */
424 #define MSR_PX 2 /* Protection exclusive on 403 x */
425 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
426 #define MSR_RI 1 /* Recoverable interrupt 1 */
427 #define MSR_LE 0 /* Little-endian mode 1 hflags */
428
429 #define msr_sf ((env->msr >> MSR_SF) & 1)
430 #define msr_isf ((env->msr >> MSR_ISF) & 1)
431 #define msr_shv ((env->msr >> MSR_SHV) & 1)
432 #define msr_cm ((env->msr >> MSR_CM) & 1)
433 #define msr_icm ((env->msr >> MSR_ICM) & 1)
434 #define msr_thv ((env->msr >> MSR_THV) & 1)
435 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
436 #define msr_vr ((env->msr >> MSR_VR) & 1)
437 #define msr_spe ((env->msr >> MSR_SPE) & 1)
438 #define msr_ap ((env->msr >> MSR_AP) & 1)
439 #define msr_sa ((env->msr >> MSR_SA) & 1)
440 #define msr_key ((env->msr >> MSR_KEY) & 1)
441 #define msr_pow ((env->msr >> MSR_POW) & 1)
442 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
443 #define msr_ce ((env->msr >> MSR_CE) & 1)
444 #define msr_ile ((env->msr >> MSR_ILE) & 1)
445 #define msr_ee ((env->msr >> MSR_EE) & 1)
446 #define msr_pr ((env->msr >> MSR_PR) & 1)
447 #define msr_fp ((env->msr >> MSR_FP) & 1)
448 #define msr_me ((env->msr >> MSR_ME) & 1)
449 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
450 #define msr_se ((env->msr >> MSR_SE) & 1)
451 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
452 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
453 #define msr_be ((env->msr >> MSR_BE) & 1)
454 #define msr_de ((env->msr >> MSR_DE) & 1)
455 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
456 #define msr_al ((env->msr >> MSR_AL) & 1)
457 #define msr_ep ((env->msr >> MSR_EP) & 1)
458 #define msr_ir ((env->msr >> MSR_IR) & 1)
459 #define msr_dr ((env->msr >> MSR_DR) & 1)
460 #define msr_pe ((env->msr >> MSR_PE) & 1)
461 #define msr_px ((env->msr >> MSR_PX) & 1)
462 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
463 #define msr_ri ((env->msr >> MSR_RI) & 1)
464 #define msr_le ((env->msr >> MSR_LE) & 1)
465 /* Hypervisor bit is more specific */
466 #if defined(TARGET_PPC64)
467 #define MSR_HVB (1ULL << MSR_SHV)
468 #define msr_hv msr_shv
469 #else
470 #if defined(PPC_EMULATE_32BITS_HYPV)
471 #define MSR_HVB (1ULL << MSR_THV)
472 #define msr_hv msr_thv
473 #else
474 #define MSR_HVB (0ULL)
475 #define msr_hv (0)
476 #endif
477 #endif
478
479 /* Exception state register bits definition */
480 #define ESR_ST 23 /* Exception was caused by a store type access. */
481
482 enum {
483 POWERPC_FLAG_NONE = 0x00000000,
484 /* Flag for MSR bit 25 signification (VRE/SPE) */
485 POWERPC_FLAG_SPE = 0x00000001,
486 POWERPC_FLAG_VRE = 0x00000002,
487 /* Flag for MSR bit 17 signification (TGPR/CE) */
488 POWERPC_FLAG_TGPR = 0x00000004,
489 POWERPC_FLAG_CE = 0x00000008,
490 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
491 POWERPC_FLAG_SE = 0x00000010,
492 POWERPC_FLAG_DWE = 0x00000020,
493 POWERPC_FLAG_UBLE = 0x00000040,
494 /* Flag for MSR bit 9 signification (BE/DE) */
495 POWERPC_FLAG_BE = 0x00000080,
496 POWERPC_FLAG_DE = 0x00000100,
497 /* Flag for MSR bit 2 signification (PX/PMM) */
498 POWERPC_FLAG_PX = 0x00000200,
499 POWERPC_FLAG_PMM = 0x00000400,
500 /* Flag for special features */
501 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
502 POWERPC_FLAG_RTC_CLK = 0x00010000,
503 POWERPC_FLAG_BUS_CLK = 0x00020000,
504 };
505
506 /*****************************************************************************/
507 /* Floating point status and control register */
508 #define FPSCR_FX 31 /* Floating-point exception summary */
509 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
510 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
511 #define FPSCR_OX 28 /* Floating-point overflow exception */
512 #define FPSCR_UX 27 /* Floating-point underflow exception */
513 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
514 #define FPSCR_XX 25 /* Floating-point inexact exception */
515 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
516 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
517 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
518 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
519 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
520 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
521 #define FPSCR_FR 18 /* Floating-point fraction rounded */
522 #define FPSCR_FI 17 /* Floating-point fraction inexact */
523 #define FPSCR_C 16 /* Floating-point result class descriptor */
524 #define FPSCR_FL 15 /* Floating-point less than or negative */
525 #define FPSCR_FG 14 /* Floating-point greater than or negative */
526 #define FPSCR_FE 13 /* Floating-point equal or zero */
527 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
528 #define FPSCR_FPCC 12 /* Floating-point condition code */
529 #define FPSCR_FPRF 12 /* Floating-point result flags */
530 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
531 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
532 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
533 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
534 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
535 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
536 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
537 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
538 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
539 #define FPSCR_RN1 1
540 #define FPSCR_RN 0 /* Floating-point rounding control */
541 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
542 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
543 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
544 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
545 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
546 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
547 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
548 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
549 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
550 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
551 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
552 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
553 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
554 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
555 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
556 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
557 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
558 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
559 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
560 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
561 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
562 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
563 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
564 /* Invalid operation exception summary */
565 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
566 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
567 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
568 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
569 (1 << FPSCR_VXCVI)))
570 /* exception summary */
571 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
572 /* enabled exception summary */
573 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
574 0x1F)
575
576 /*****************************************************************************/
577 /* Vector status and control register */
578 #define VSCR_NJ 16 /* Vector non-java */
579 #define VSCR_SAT 0 /* Vector saturation */
580 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
581 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
582
583 /*****************************************************************************/
584 /* The whole PowerPC CPU context */
585 #define NB_MMU_MODES 3
586
587 struct CPUPPCState {
588 /* First are the most commonly used resources
589 * during translated code execution
590 */
591 /* general purpose registers */
592 target_ulong gpr[32];
593 #if !defined(TARGET_PPC64)
594 /* Storage for GPR MSB, used by the SPE extension */
595 target_ulong gprh[32];
596 #endif
597 /* LR */
598 target_ulong lr;
599 /* CTR */
600 target_ulong ctr;
601 /* condition register */
602 uint32_t crf[8];
603 /* XER */
604 target_ulong xer;
605 /* Reservation address */
606 target_ulong reserve_addr;
607 /* Reservation value */
608 target_ulong reserve_val;
609 /* Reservation store address */
610 target_ulong reserve_ea;
611 /* Reserved store source register and size */
612 target_ulong reserve_info;
613
614 /* Those ones are used in supervisor mode only */
615 /* machine state register */
616 target_ulong msr;
617 /* temporary general purpose registers */
618 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
619
620 /* Floating point execution context */
621 float_status fp_status;
622 /* floating point registers */
623 float64 fpr[32];
624 /* floating point status and control register */
625 uint32_t fpscr;
626
627 /* Next instruction pointer */
628 target_ulong nip;
629
630 int access_type; /* when a memory exception occurs, the access
631 type is stored here */
632
633 CPU_COMMON
634
635 /* MMU context - only relevant for full system emulation */
636 #if !defined(CONFIG_USER_ONLY)
637 #if defined(TARGET_PPC64)
638 /* Address space register */
639 target_ulong asr;
640 /* PowerPC 64 SLB area */
641 ppc_slb_t slb[64];
642 int slb_nr;
643 #endif
644 /* segment registers */
645 target_ulong sdr1;
646 target_ulong sr[32];
647 /* BATs */
648 int nb_BATs;
649 target_ulong DBAT[2][8];
650 target_ulong IBAT[2][8];
651 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
652 int nb_tlb; /* Total number of TLB */
653 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
654 int nb_ways; /* Number of ways in the TLB set */
655 int last_way; /* Last used way used to allocate TLB in a LRU way */
656 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
657 int nb_pids; /* Number of available PID registers */
658 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
659 /* 403 dedicated access protection registers */
660 target_ulong pb[4];
661 #endif
662
663 /* Other registers */
664 /* Special purpose registers */
665 target_ulong spr[1024];
666 ppc_spr_t spr_cb[1024];
667 /* Altivec registers */
668 ppc_avr_t avr[32];
669 uint32_t vscr;
670 /* SPE registers */
671 uint64_t spe_acc;
672 uint32_t spe_fscr;
673 /* SPE and Altivec can share a status since they will never be used
674 * simultaneously */
675 float_status vec_status;
676
677 /* Internal devices resources */
678 /* Time base and decrementer */
679 ppc_tb_t *tb_env;
680 /* Device control registers */
681 ppc_dcr_t *dcr_env;
682
683 int dcache_line_size;
684 int icache_line_size;
685
686 /* Those resources are used during exception processing */
687 /* CPU model definition */
688 target_ulong msr_mask;
689 powerpc_mmu_t mmu_model;
690 powerpc_excp_t excp_model;
691 powerpc_input_t bus_model;
692 int bfd_mach;
693 uint32_t flags;
694 uint64_t insns_flags;
695
696 int error_code;
697 uint32_t pending_interrupts;
698 #if !defined(CONFIG_USER_ONLY)
699 /* This is the IRQ controller, which is implementation dependant
700 * and only relevant when emulating a complete machine.
701 */
702 uint32_t irq_input_state;
703 void **irq_inputs;
704 /* Exception vectors */
705 target_ulong excp_vectors[POWERPC_EXCP_NB];
706 target_ulong excp_prefix;
707 target_ulong hreset_excp_prefix;
708 target_ulong ivor_mask;
709 target_ulong ivpr_mask;
710 target_ulong hreset_vector;
711 #endif
712
713 /* Those resources are used only during code translation */
714 /* opcode handlers */
715 opc_handler_t *opcodes[0x40];
716
717 /* Those resources are used only in Qemu core */
718 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
719 target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
720 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
721
722 /* Power management */
723 int power_mode;
724 int (*check_pow)(CPUPPCState *env);
725
726 #if !defined(CONFIG_USER_ONLY)
727 void *load_info; /* Holds boot loading state. */
728 #endif
729 };
730
731 #if !defined(CONFIG_USER_ONLY)
732 /* Context used internally during MMU translations */
733 typedef struct mmu_ctx_t mmu_ctx_t;
734 struct mmu_ctx_t {
735 target_phys_addr_t raddr; /* Real address */
736 target_phys_addr_t eaddr; /* Effective address */
737 int prot; /* Protection bits */
738 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
739 target_ulong ptem; /* Virtual segment ID | API */
740 int key; /* Access key */
741 int nx; /* Non-execute area */
742 };
743 #endif
744
745 /*****************************************************************************/
746 CPUPPCState *cpu_ppc_init (const char *cpu_model);
747 void ppc_translate_init(void);
748 int cpu_ppc_exec (CPUPPCState *s);
749 void cpu_ppc_close (CPUPPCState *s);
750 /* you can call this signal handler from your SIGBUS and SIGSEGV
751 signal handlers to inform the virtual CPU of exceptions. non zero
752 is returned if the signal was handled by the virtual CPU. */
753 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
754 void *puc);
755 int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
756 int mmu_idx, int is_softmmu);
757 #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
758 #if !defined(CONFIG_USER_ONLY)
759 int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
760 int rw, int access_type);
761 #endif
762 void do_interrupt (CPUPPCState *env);
763 void ppc_hw_interrupt (CPUPPCState *env);
764
765 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
766
767 #if !defined(CONFIG_USER_ONLY)
768 void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
769 target_ulong pte0, target_ulong pte1);
770 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
771 void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
772 void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
773 void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
774 void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
775 void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
776 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
777 #if defined(TARGET_PPC64)
778 void ppc_store_asr (CPUPPCState *env, target_ulong value);
779 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
780 target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
781 int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
782 int ppc_load_slb_esid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
783 int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
784 #endif /* defined(TARGET_PPC64) */
785 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
786 #endif /* !defined(CONFIG_USER_ONLY) */
787 void ppc_store_msr (CPUPPCState *env, target_ulong value);
788
789 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
790
791 const ppc_def_t *cpu_ppc_find_by_name (const char *name);
792 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
793
794 /* Time-base and decrementer management */
795 #ifndef NO_CPU_IO_DEFS
796 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
797 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
798 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
799 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
800 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
801 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
802 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
803 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
804 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
805 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
806 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
807 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
808 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
809 void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
810 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
811 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
812 #if !defined(CONFIG_USER_ONLY)
813 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
814 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
815 target_ulong load_40x_pit (CPUPPCState *env);
816 void store_40x_pit (CPUPPCState *env, target_ulong val);
817 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
818 void store_40x_sler (CPUPPCState *env, uint32_t val);
819 void store_booke_tcr (CPUPPCState *env, target_ulong val);
820 void store_booke_tsr (CPUPPCState *env, target_ulong val);
821 void ppc_tlb_invalidate_all (CPUPPCState *env);
822 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
823 #if defined(TARGET_PPC64)
824 void ppc_slb_invalidate_all (CPUPPCState *env);
825 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
826 #endif
827 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
828 #endif
829 #endif
830
831 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
832 {
833 uint64_t gprv;
834
835 gprv = env->gpr[gprn];
836 #if !defined(TARGET_PPC64)
837 if (env->flags & POWERPC_FLAG_SPE) {
838 /* If the CPU implements the SPE extension, we have to get the
839 * high bits of the GPR from the gprh storage area
840 */
841 gprv &= 0xFFFFFFFFULL;
842 gprv |= (uint64_t)env->gprh[gprn] << 32;
843 }
844 #endif
845
846 return gprv;
847 }
848
849 /* Device control registers */
850 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
851 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
852
853 #define cpu_init cpu_ppc_init
854 #define cpu_exec cpu_ppc_exec
855 #define cpu_gen_code cpu_ppc_gen_code
856 #define cpu_signal_handler cpu_ppc_signal_handler
857 #define cpu_list ppc_cpu_list
858
859 #define CPU_SAVE_VERSION 4
860
861 /* MMU modes definitions */
862 #define MMU_MODE0_SUFFIX _user
863 #define MMU_MODE1_SUFFIX _kernel
864 #define MMU_MODE2_SUFFIX _hypv
865 #define MMU_USER_IDX 0
866 static inline int cpu_mmu_index (CPUState *env)
867 {
868 return env->mmu_idx;
869 }
870
871 #if defined(CONFIG_USER_ONLY)
872 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
873 {
874 if (newsp)
875 env->gpr[1] = newsp;
876 env->gpr[3] = 0;
877 }
878 #endif
879
880 #include "cpu-all.h"
881
882 /*****************************************************************************/
883 /* CRF definitions */
884 #define CRF_LT 3
885 #define CRF_GT 2
886 #define CRF_EQ 1
887 #define CRF_SO 0
888 #define CRF_CH (1 << CRF_LT)
889 #define CRF_CL (1 << CRF_GT)
890 #define CRF_CH_OR_CL (1 << CRF_EQ)
891 #define CRF_CH_AND_CL (1 << CRF_SO)
892
893 /* XER definitions */
894 #define XER_SO 31
895 #define XER_OV 30
896 #define XER_CA 29
897 #define XER_CMP 8
898 #define XER_BC 0
899 #define xer_so ((env->xer >> XER_SO) & 1)
900 #define xer_ov ((env->xer >> XER_OV) & 1)
901 #define xer_ca ((env->xer >> XER_CA) & 1)
902 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
903 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
904
905 /* SPR definitions */
906 #define SPR_MQ (0x000)
907 #define SPR_XER (0x001)
908 #define SPR_601_VRTCU (0x004)
909 #define SPR_601_VRTCL (0x005)
910 #define SPR_601_UDECR (0x006)
911 #define SPR_LR (0x008)
912 #define SPR_CTR (0x009)
913 #define SPR_DSISR (0x012)
914 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
915 #define SPR_601_RTCU (0x014)
916 #define SPR_601_RTCL (0x015)
917 #define SPR_DECR (0x016)
918 #define SPR_SDR1 (0x019)
919 #define SPR_SRR0 (0x01A)
920 #define SPR_SRR1 (0x01B)
921 #define SPR_AMR (0x01D)
922 #define SPR_BOOKE_PID (0x030)
923 #define SPR_BOOKE_DECAR (0x036)
924 #define SPR_BOOKE_CSRR0 (0x03A)
925 #define SPR_BOOKE_CSRR1 (0x03B)
926 #define SPR_BOOKE_DEAR (0x03D)
927 #define SPR_BOOKE_ESR (0x03E)
928 #define SPR_BOOKE_IVPR (0x03F)
929 #define SPR_MPC_EIE (0x050)
930 #define SPR_MPC_EID (0x051)
931 #define SPR_MPC_NRI (0x052)
932 #define SPR_CTRL (0x088)
933 #define SPR_MPC_CMPA (0x090)
934 #define SPR_MPC_CMPB (0x091)
935 #define SPR_MPC_CMPC (0x092)
936 #define SPR_MPC_CMPD (0x093)
937 #define SPR_MPC_ECR (0x094)
938 #define SPR_MPC_DER (0x095)
939 #define SPR_MPC_COUNTA (0x096)
940 #define SPR_MPC_COUNTB (0x097)
941 #define SPR_UCTRL (0x098)
942 #define SPR_MPC_CMPE (0x098)
943 #define SPR_MPC_CMPF (0x099)
944 #define SPR_MPC_CMPG (0x09A)
945 #define SPR_MPC_CMPH (0x09B)
946 #define SPR_MPC_LCTRL1 (0x09C)
947 #define SPR_MPC_LCTRL2 (0x09D)
948 #define SPR_MPC_ICTRL (0x09E)
949 #define SPR_MPC_BAR (0x09F)
950 #define SPR_VRSAVE (0x100)
951 #define SPR_USPRG0 (0x100)
952 #define SPR_USPRG1 (0x101)
953 #define SPR_USPRG2 (0x102)
954 #define SPR_USPRG3 (0x103)
955 #define SPR_USPRG4 (0x104)
956 #define SPR_USPRG5 (0x105)
957 #define SPR_USPRG6 (0x106)
958 #define SPR_USPRG7 (0x107)
959 #define SPR_VTBL (0x10C)
960 #define SPR_VTBU (0x10D)
961 #define SPR_SPRG0 (0x110)
962 #define SPR_SPRG1 (0x111)
963 #define SPR_SPRG2 (0x112)
964 #define SPR_SPRG3 (0x113)
965 #define SPR_SPRG4 (0x114)
966 #define SPR_SCOMC (0x114)
967 #define SPR_SPRG5 (0x115)
968 #define SPR_SCOMD (0x115)
969 #define SPR_SPRG6 (0x116)
970 #define SPR_SPRG7 (0x117)
971 #define SPR_ASR (0x118)
972 #define SPR_EAR (0x11A)
973 #define SPR_TBL (0x11C)
974 #define SPR_TBU (0x11D)
975 #define SPR_TBU40 (0x11E)
976 #define SPR_SVR (0x11E)
977 #define SPR_BOOKE_PIR (0x11E)
978 #define SPR_PVR (0x11F)
979 #define SPR_HSPRG0 (0x130)
980 #define SPR_BOOKE_DBSR (0x130)
981 #define SPR_HSPRG1 (0x131)
982 #define SPR_HDSISR (0x132)
983 #define SPR_HDAR (0x133)
984 #define SPR_BOOKE_DBCR0 (0x134)
985 #define SPR_IBCR (0x135)
986 #define SPR_PURR (0x135)
987 #define SPR_BOOKE_DBCR1 (0x135)
988 #define SPR_DBCR (0x136)
989 #define SPR_HDEC (0x136)
990 #define SPR_BOOKE_DBCR2 (0x136)
991 #define SPR_HIOR (0x137)
992 #define SPR_MBAR (0x137)
993 #define SPR_RMOR (0x138)
994 #define SPR_BOOKE_IAC1 (0x138)
995 #define SPR_HRMOR (0x139)
996 #define SPR_BOOKE_IAC2 (0x139)
997 #define SPR_HSRR0 (0x13A)
998 #define SPR_BOOKE_IAC3 (0x13A)
999 #define SPR_HSRR1 (0x13B)
1000 #define SPR_BOOKE_IAC4 (0x13B)
1001 #define SPR_LPCR (0x13C)
1002 #define SPR_BOOKE_DAC1 (0x13C)
1003 #define SPR_LPIDR (0x13D)
1004 #define SPR_DABR2 (0x13D)
1005 #define SPR_BOOKE_DAC2 (0x13D)
1006 #define SPR_BOOKE_DVC1 (0x13E)
1007 #define SPR_BOOKE_DVC2 (0x13F)
1008 #define SPR_BOOKE_TSR (0x150)
1009 #define SPR_BOOKE_TCR (0x154)
1010 #define SPR_BOOKE_IVOR0 (0x190)
1011 #define SPR_BOOKE_IVOR1 (0x191)
1012 #define SPR_BOOKE_IVOR2 (0x192)
1013 #define SPR_BOOKE_IVOR3 (0x193)
1014 #define SPR_BOOKE_IVOR4 (0x194)
1015 #define SPR_BOOKE_IVOR5 (0x195)
1016 #define SPR_BOOKE_IVOR6 (0x196)
1017 #define SPR_BOOKE_IVOR7 (0x197)
1018 #define SPR_BOOKE_IVOR8 (0x198)
1019 #define SPR_BOOKE_IVOR9 (0x199)
1020 #define SPR_BOOKE_IVOR10 (0x19A)
1021 #define SPR_BOOKE_IVOR11 (0x19B)
1022 #define SPR_BOOKE_IVOR12 (0x19C)
1023 #define SPR_BOOKE_IVOR13 (0x19D)
1024 #define SPR_BOOKE_IVOR14 (0x19E)
1025 #define SPR_BOOKE_IVOR15 (0x19F)
1026 #define SPR_BOOKE_SPEFSCR (0x200)
1027 #define SPR_Exxx_BBEAR (0x201)
1028 #define SPR_Exxx_BBTAR (0x202)
1029 #define SPR_Exxx_L1CFG0 (0x203)
1030 #define SPR_Exxx_NPIDR (0x205)
1031 #define SPR_ATBL (0x20E)
1032 #define SPR_ATBU (0x20F)
1033 #define SPR_IBAT0U (0x210)
1034 #define SPR_BOOKE_IVOR32 (0x210)
1035 #define SPR_RCPU_MI_GRA (0x210)
1036 #define SPR_IBAT0L (0x211)
1037 #define SPR_BOOKE_IVOR33 (0x211)
1038 #define SPR_IBAT1U (0x212)
1039 #define SPR_BOOKE_IVOR34 (0x212)
1040 #define SPR_IBAT1L (0x213)
1041 #define SPR_BOOKE_IVOR35 (0x213)
1042 #define SPR_IBAT2U (0x214)
1043 #define SPR_BOOKE_IVOR36 (0x214)
1044 #define SPR_IBAT2L (0x215)
1045 #define SPR_BOOKE_IVOR37 (0x215)
1046 #define SPR_IBAT3U (0x216)
1047 #define SPR_IBAT3L (0x217)
1048 #define SPR_DBAT0U (0x218)
1049 #define SPR_RCPU_L2U_GRA (0x218)
1050 #define SPR_DBAT0L (0x219)
1051 #define SPR_DBAT1U (0x21A)
1052 #define SPR_DBAT1L (0x21B)
1053 #define SPR_DBAT2U (0x21C)
1054 #define SPR_DBAT2L (0x21D)
1055 #define SPR_DBAT3U (0x21E)
1056 #define SPR_DBAT3L (0x21F)
1057 #define SPR_IBAT4U (0x230)
1058 #define SPR_RPCU_BBCMCR (0x230)
1059 #define SPR_MPC_IC_CST (0x230)
1060 #define SPR_Exxx_CTXCR (0x230)
1061 #define SPR_IBAT4L (0x231)
1062 #define SPR_MPC_IC_ADR (0x231)
1063 #define SPR_Exxx_DBCR3 (0x231)
1064 #define SPR_IBAT5U (0x232)
1065 #define SPR_MPC_IC_DAT (0x232)
1066 #define SPR_Exxx_DBCNT (0x232)
1067 #define SPR_IBAT5L (0x233)
1068 #define SPR_IBAT6U (0x234)
1069 #define SPR_IBAT6L (0x235)
1070 #define SPR_IBAT7U (0x236)
1071 #define SPR_IBAT7L (0x237)
1072 #define SPR_DBAT4U (0x238)
1073 #define SPR_RCPU_L2U_MCR (0x238)
1074 #define SPR_MPC_DC_CST (0x238)
1075 #define SPR_Exxx_ALTCTXCR (0x238)
1076 #define SPR_DBAT4L (0x239)
1077 #define SPR_MPC_DC_ADR (0x239)
1078 #define SPR_DBAT5U (0x23A)
1079 #define SPR_BOOKE_MCSRR0 (0x23A)
1080 #define SPR_MPC_DC_DAT (0x23A)
1081 #define SPR_DBAT5L (0x23B)
1082 #define SPR_BOOKE_MCSRR1 (0x23B)
1083 #define SPR_DBAT6U (0x23C)
1084 #define SPR_BOOKE_MCSR (0x23C)
1085 #define SPR_DBAT6L (0x23D)
1086 #define SPR_Exxx_MCAR (0x23D)
1087 #define SPR_DBAT7U (0x23E)
1088 #define SPR_BOOKE_DSRR0 (0x23E)
1089 #define SPR_DBAT7L (0x23F)
1090 #define SPR_BOOKE_DSRR1 (0x23F)
1091 #define SPR_BOOKE_SPRG8 (0x25C)
1092 #define SPR_BOOKE_SPRG9 (0x25D)
1093 #define SPR_BOOKE_MAS0 (0x270)
1094 #define SPR_BOOKE_MAS1 (0x271)
1095 #define SPR_BOOKE_MAS2 (0x272)
1096 #define SPR_BOOKE_MAS3 (0x273)
1097 #define SPR_BOOKE_MAS4 (0x274)
1098 #define SPR_BOOKE_MAS5 (0x275)
1099 #define SPR_BOOKE_MAS6 (0x276)
1100 #define SPR_BOOKE_PID1 (0x279)
1101 #define SPR_BOOKE_PID2 (0x27A)
1102 #define SPR_MPC_DPDR (0x280)
1103 #define SPR_MPC_IMMR (0x288)
1104 #define SPR_BOOKE_TLB0CFG (0x2B0)
1105 #define SPR_BOOKE_TLB1CFG (0x2B1)
1106 #define SPR_BOOKE_TLB2CFG (0x2B2)
1107 #define SPR_BOOKE_TLB3CFG (0x2B3)
1108 #define SPR_BOOKE_EPR (0x2BE)
1109 #define SPR_PERF0 (0x300)
1110 #define SPR_RCPU_MI_RBA0 (0x300)
1111 #define SPR_MPC_MI_CTR (0x300)
1112 #define SPR_PERF1 (0x301)
1113 #define SPR_RCPU_MI_RBA1 (0x301)
1114 #define SPR_PERF2 (0x302)
1115 #define SPR_RCPU_MI_RBA2 (0x302)
1116 #define SPR_MPC_MI_AP (0x302)
1117 #define SPR_PERF3 (0x303)
1118 #define SPR_620_PMC1R (0x303)
1119 #define SPR_RCPU_MI_RBA3 (0x303)
1120 #define SPR_MPC_MI_EPN (0x303)
1121 #define SPR_PERF4 (0x304)
1122 #define SPR_620_PMC2R (0x304)
1123 #define SPR_PERF5 (0x305)
1124 #define SPR_MPC_MI_TWC (0x305)
1125 #define SPR_PERF6 (0x306)
1126 #define SPR_MPC_MI_RPN (0x306)
1127 #define SPR_PERF7 (0x307)
1128 #define SPR_PERF8 (0x308)
1129 #define SPR_RCPU_L2U_RBA0 (0x308)
1130 #define SPR_MPC_MD_CTR (0x308)
1131 #define SPR_PERF9 (0x309)
1132 #define SPR_RCPU_L2U_RBA1 (0x309)
1133 #define SPR_MPC_MD_CASID (0x309)
1134 #define SPR_PERFA (0x30A)
1135 #define SPR_RCPU_L2U_RBA2 (0x30A)
1136 #define SPR_MPC_MD_AP (0x30A)
1137 #define SPR_PERFB (0x30B)
1138 #define SPR_620_MMCR0R (0x30B)
1139 #define SPR_RCPU_L2U_RBA3 (0x30B)
1140 #define SPR_MPC_MD_EPN (0x30B)
1141 #define SPR_PERFC (0x30C)
1142 #define SPR_MPC_MD_TWB (0x30C)
1143 #define SPR_PERFD (0x30D)
1144 #define SPR_MPC_MD_TWC (0x30D)
1145 #define SPR_PERFE (0x30E)
1146 #define SPR_MPC_MD_RPN (0x30E)
1147 #define SPR_PERFF (0x30F)
1148 #define SPR_MPC_MD_TW (0x30F)
1149 #define SPR_UPERF0 (0x310)
1150 #define SPR_UPERF1 (0x311)
1151 #define SPR_UPERF2 (0x312)
1152 #define SPR_UPERF3 (0x313)
1153 #define SPR_620_PMC1W (0x313)
1154 #define SPR_UPERF4 (0x314)
1155 #define SPR_620_PMC2W (0x314)
1156 #define SPR_UPERF5 (0x315)
1157 #define SPR_UPERF6 (0x316)
1158 #define SPR_UPERF7 (0x317)
1159 #define SPR_UPERF8 (0x318)
1160 #define SPR_UPERF9 (0x319)
1161 #define SPR_UPERFA (0x31A)
1162 #define SPR_UPERFB (0x31B)
1163 #define SPR_620_MMCR0W (0x31B)
1164 #define SPR_UPERFC (0x31C)
1165 #define SPR_UPERFD (0x31D)
1166 #define SPR_UPERFE (0x31E)
1167 #define SPR_UPERFF (0x31F)
1168 #define SPR_RCPU_MI_RA0 (0x320)
1169 #define SPR_MPC_MI_DBCAM (0x320)
1170 #define SPR_RCPU_MI_RA1 (0x321)
1171 #define SPR_MPC_MI_DBRAM0 (0x321)
1172 #define SPR_RCPU_MI_RA2 (0x322)
1173 #define SPR_MPC_MI_DBRAM1 (0x322)
1174 #define SPR_RCPU_MI_RA3 (0x323)
1175 #define SPR_RCPU_L2U_RA0 (0x328)
1176 #define SPR_MPC_MD_DBCAM (0x328)
1177 #define SPR_RCPU_L2U_RA1 (0x329)
1178 #define SPR_MPC_MD_DBRAM0 (0x329)
1179 #define SPR_RCPU_L2U_RA2 (0x32A)
1180 #define SPR_MPC_MD_DBRAM1 (0x32A)
1181 #define SPR_RCPU_L2U_RA3 (0x32B)
1182 #define SPR_440_INV0 (0x370)
1183 #define SPR_440_INV1 (0x371)
1184 #define SPR_440_INV2 (0x372)
1185 #define SPR_440_INV3 (0x373)
1186 #define SPR_440_ITV0 (0x374)
1187 #define SPR_440_ITV1 (0x375)
1188 #define SPR_440_ITV2 (0x376)
1189 #define SPR_440_ITV3 (0x377)
1190 #define SPR_440_CCR1 (0x378)
1191 #define SPR_DCRIPR (0x37B)
1192 #define SPR_PPR (0x380)
1193 #define SPR_750_GQR0 (0x390)
1194 #define SPR_440_DNV0 (0x390)
1195 #define SPR_750_GQR1 (0x391)
1196 #define SPR_440_DNV1 (0x391)
1197 #define SPR_750_GQR2 (0x392)
1198 #define SPR_440_DNV2 (0x392)
1199 #define SPR_750_GQR3 (0x393)
1200 #define SPR_440_DNV3 (0x393)
1201 #define SPR_750_GQR4 (0x394)
1202 #define SPR_440_DTV0 (0x394)
1203 #define SPR_750_GQR5 (0x395)
1204 #define SPR_440_DTV1 (0x395)
1205 #define SPR_750_GQR6 (0x396)
1206 #define SPR_440_DTV2 (0x396)
1207 #define SPR_750_GQR7 (0x397)
1208 #define SPR_440_DTV3 (0x397)
1209 #define SPR_750_THRM4 (0x398)
1210 #define SPR_750CL_HID2 (0x398)
1211 #define SPR_440_DVLIM (0x398)
1212 #define SPR_750_WPAR (0x399)
1213 #define SPR_440_IVLIM (0x399)
1214 #define SPR_750_DMAU (0x39A)
1215 #define SPR_750_DMAL (0x39B)
1216 #define SPR_440_RSTCFG (0x39B)
1217 #define SPR_BOOKE_DCDBTRL (0x39C)
1218 #define SPR_BOOKE_DCDBTRH (0x39D)
1219 #define SPR_BOOKE_ICDBTRL (0x39E)
1220 #define SPR_BOOKE_ICDBTRH (0x39F)
1221 #define SPR_UMMCR2 (0x3A0)
1222 #define SPR_UPMC5 (0x3A1)
1223 #define SPR_UPMC6 (0x3A2)
1224 #define SPR_UBAMR (0x3A7)
1225 #define SPR_UMMCR0 (0x3A8)
1226 #define SPR_UPMC1 (0x3A9)
1227 #define SPR_UPMC2 (0x3AA)
1228 #define SPR_USIAR (0x3AB)
1229 #define SPR_UMMCR1 (0x3AC)
1230 #define SPR_UPMC3 (0x3AD)
1231 #define SPR_UPMC4 (0x3AE)
1232 #define SPR_USDA (0x3AF)
1233 #define SPR_40x_ZPR (0x3B0)
1234 #define SPR_BOOKE_MAS7 (0x3B0)
1235 #define SPR_620_PMR0 (0x3B0)
1236 #define SPR_MMCR2 (0x3B0)
1237 #define SPR_PMC5 (0x3B1)
1238 #define SPR_40x_PID (0x3B1)
1239 #define SPR_620_PMR1 (0x3B1)
1240 #define SPR_PMC6 (0x3B2)
1241 #define SPR_440_MMUCR (0x3B2)
1242 #define SPR_620_PMR2 (0x3B2)
1243 #define SPR_4xx_CCR0 (0x3B3)
1244 #define SPR_BOOKE_EPLC (0x3B3)
1245 #define SPR_620_PMR3 (0x3B3)
1246 #define SPR_405_IAC3 (0x3B4)
1247 #define SPR_BOOKE_EPSC (0x3B4)
1248 #define SPR_620_PMR4 (0x3B4)
1249 #define SPR_405_IAC4 (0x3B5)
1250 #define SPR_620_PMR5 (0x3B5)
1251 #define SPR_405_DVC1 (0x3B6)
1252 #define SPR_620_PMR6 (0x3B6)
1253 #define SPR_405_DVC2 (0x3B7)
1254 #define SPR_620_PMR7 (0x3B7)
1255 #define SPR_BAMR (0x3B7)
1256 #define SPR_MMCR0 (0x3B8)
1257 #define SPR_620_PMR8 (0x3B8)
1258 #define SPR_PMC1 (0x3B9)
1259 #define SPR_40x_SGR (0x3B9)
1260 #define SPR_620_PMR9 (0x3B9)
1261 #define SPR_PMC2 (0x3BA)
1262 #define SPR_40x_DCWR (0x3BA)
1263 #define SPR_620_PMRA (0x3BA)
1264 #define SPR_SIAR (0x3BB)
1265 #define SPR_405_SLER (0x3BB)
1266 #define SPR_620_PMRB (0x3BB)
1267 #define SPR_MMCR1 (0x3BC)
1268 #define SPR_405_SU0R (0x3BC)
1269 #define SPR_620_PMRC (0x3BC)
1270 #define SPR_401_SKR (0x3BC)
1271 #define SPR_PMC3 (0x3BD)
1272 #define SPR_405_DBCR1 (0x3BD)
1273 #define SPR_620_PMRD (0x3BD)
1274 #define SPR_PMC4 (0x3BE)
1275 #define SPR_620_PMRE (0x3BE)
1276 #define SPR_SDA (0x3BF)
1277 #define SPR_620_PMRF (0x3BF)
1278 #define SPR_403_VTBL (0x3CC)
1279 #define SPR_403_VTBU (0x3CD)
1280 #define SPR_DMISS (0x3D0)
1281 #define SPR_DCMP (0x3D1)
1282 #define SPR_HASH1 (0x3D2)
1283 #define SPR_HASH2 (0x3D3)
1284 #define SPR_BOOKE_ICDBDR (0x3D3)
1285 #define SPR_TLBMISS (0x3D4)
1286 #define SPR_IMISS (0x3D4)
1287 #define SPR_40x_ESR (0x3D4)
1288 #define SPR_PTEHI (0x3D5)
1289 #define SPR_ICMP (0x3D5)
1290 #define SPR_40x_DEAR (0x3D5)
1291 #define SPR_PTELO (0x3D6)
1292 #define SPR_RPA (0x3D6)
1293 #define SPR_40x_EVPR (0x3D6)
1294 #define SPR_L3PM (0x3D7)
1295 #define SPR_403_CDBCR (0x3D7)
1296 #define SPR_L3ITCR0 (0x3D8)
1297 #define SPR_TCR (0x3D8)
1298 #define SPR_40x_TSR (0x3D8)
1299 #define SPR_IBR (0x3DA)
1300 #define SPR_40x_TCR (0x3DA)
1301 #define SPR_ESASRR (0x3DB)
1302 #define SPR_40x_PIT (0x3DB)
1303 #define SPR_403_TBL (0x3DC)
1304 #define SPR_403_TBU (0x3DD)
1305 #define SPR_SEBR (0x3DE)
1306 #define SPR_40x_SRR2 (0x3DE)
1307 #define SPR_SER (0x3DF)
1308 #define SPR_40x_SRR3 (0x3DF)
1309 #define SPR_L3OHCR (0x3E8)
1310 #define SPR_L3ITCR1 (0x3E9)
1311 #define SPR_L3ITCR2 (0x3EA)
1312 #define SPR_L3ITCR3 (0x3EB)
1313 #define SPR_HID0 (0x3F0)
1314 #define SPR_40x_DBSR (0x3F0)
1315 #define SPR_HID1 (0x3F1)
1316 #define SPR_IABR (0x3F2)
1317 #define SPR_40x_DBCR0 (0x3F2)
1318 #define SPR_601_HID2 (0x3F2)
1319 #define SPR_Exxx_L1CSR0 (0x3F2)
1320 #define SPR_ICTRL (0x3F3)
1321 #define SPR_HID2 (0x3F3)
1322 #define SPR_750CL_HID4 (0x3F3)
1323 #define SPR_Exxx_L1CSR1 (0x3F3)
1324 #define SPR_440_DBDR (0x3F3)
1325 #define SPR_LDSTDB (0x3F4)
1326 #define SPR_750_TDCL (0x3F4)
1327 #define SPR_40x_IAC1 (0x3F4)
1328 #define SPR_MMUCSR0 (0x3F4)
1329 #define SPR_DABR (0x3F5)
1330 #define DABR_MASK (~(target_ulong)0x7)
1331 #define SPR_Exxx_BUCSR (0x3F5)
1332 #define SPR_40x_IAC2 (0x3F5)
1333 #define SPR_601_HID5 (0x3F5)
1334 #define SPR_40x_DAC1 (0x3F6)
1335 #define SPR_MSSCR0 (0x3F6)
1336 #define SPR_970_HID5 (0x3F6)
1337 #define SPR_MSSSR0 (0x3F7)
1338 #define SPR_MSSCR1 (0x3F7)
1339 #define SPR_DABRX (0x3F7)
1340 #define SPR_40x_DAC2 (0x3F7)
1341 #define SPR_MMUCFG (0x3F7)
1342 #define SPR_LDSTCR (0x3F8)
1343 #define SPR_L2PMCR (0x3F8)
1344 #define SPR_750FX_HID2 (0x3F8)
1345 #define SPR_620_BUSCSR (0x3F8)
1346 #define SPR_Exxx_L1FINV0 (0x3F8)
1347 #define SPR_L2CR (0x3F9)
1348 #define SPR_620_L2CR (0x3F9)
1349 #define SPR_L3CR (0x3FA)
1350 #define SPR_750_TDCH (0x3FA)
1351 #define SPR_IABR2 (0x3FA)
1352 #define SPR_40x_DCCR (0x3FA)
1353 #define SPR_620_L2SR (0x3FA)
1354 #define SPR_ICTC (0x3FB)
1355 #define SPR_40x_ICCR (0x3FB)
1356 #define SPR_THRM1 (0x3FC)
1357 #define SPR_403_PBL1 (0x3FC)
1358 #define SPR_SP (0x3FD)
1359 #define SPR_THRM2 (0x3FD)
1360 #define SPR_403_PBU1 (0x3FD)
1361 #define SPR_604_HID13 (0x3FD)
1362 #define SPR_LT (0x3FE)
1363 #define SPR_THRM3 (0x3FE)
1364 #define SPR_RCPU_FPECR (0x3FE)
1365 #define SPR_403_PBL2 (0x3FE)
1366 #define SPR_PIR (0x3FF)
1367 #define SPR_403_PBU2 (0x3FF)
1368 #define SPR_601_HID15 (0x3FF)
1369 #define SPR_604_HID15 (0x3FF)
1370 #define SPR_E500_SVR (0x3FF)
1371
1372 /*****************************************************************************/
1373 /* PowerPC Instructions types definitions */
1374 enum {
1375 PPC_NONE = 0x0000000000000000ULL,
1376 /* PowerPC base instructions set */
1377 PPC_INSNS_BASE = 0x0000000000000001ULL,
1378 /* integer operations instructions */
1379 #define PPC_INTEGER PPC_INSNS_BASE
1380 /* flow control instructions */
1381 #define PPC_FLOW PPC_INSNS_BASE
1382 /* virtual memory instructions */
1383 #define PPC_MEM PPC_INSNS_BASE
1384 /* ld/st with reservation instructions */
1385 #define PPC_RES PPC_INSNS_BASE
1386 /* spr/msr access instructions */
1387 #define PPC_MISC PPC_INSNS_BASE
1388 /* Deprecated instruction sets */
1389 /* Original POWER instruction set */
1390 PPC_POWER = 0x0000000000000002ULL,
1391 /* POWER2 instruction set extension */
1392 PPC_POWER2 = 0x0000000000000004ULL,
1393 /* Power RTC support */
1394 PPC_POWER_RTC = 0x0000000000000008ULL,
1395 /* Power-to-PowerPC bridge (601) */
1396 PPC_POWER_BR = 0x0000000000000010ULL,
1397 /* 64 bits PowerPC instruction set */
1398 PPC_64B = 0x0000000000000020ULL,
1399 /* New 64 bits extensions (PowerPC 2.0x) */
1400 PPC_64BX = 0x0000000000000040ULL,
1401 /* 64 bits hypervisor extensions */
1402 PPC_64H = 0x0000000000000080ULL,
1403 /* New wait instruction (PowerPC 2.0x) */
1404 PPC_WAIT = 0x0000000000000100ULL,
1405 /* Time base mftb instruction */
1406 PPC_MFTB = 0x0000000000000200ULL,
1407
1408 /* Fixed-point unit extensions */
1409 /* PowerPC 602 specific */
1410 PPC_602_SPEC = 0x0000000000000400ULL,
1411 /* isel instruction */
1412 PPC_ISEL = 0x0000000000000800ULL,
1413 /* popcntb instruction */
1414 PPC_POPCNTB = 0x0000000000001000ULL,
1415 /* string load / store */
1416 PPC_STRING = 0x0000000000002000ULL,
1417
1418 /* Floating-point unit extensions */
1419 /* Optional floating point instructions */
1420 PPC_FLOAT = 0x0000000000010000ULL,
1421 /* New floating-point extensions (PowerPC 2.0x) */
1422 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1423 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1424 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1425 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1426 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1427 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1428 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1429
1430 /* Vector/SIMD extensions */
1431 /* Altivec support */
1432 PPC_ALTIVEC = 0x0000000001000000ULL,
1433 /* PowerPC 2.03 SPE extension */
1434 PPC_SPE = 0x0000000002000000ULL,
1435 /* PowerPC 2.03 SPE single-precision floating-point extension */
1436 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1437 /* PowerPC 2.03 SPE double-precision floating-point extension */
1438 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1439
1440 /* Optional memory control instructions */
1441 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1442 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1443 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1444 /* sync instruction */
1445 PPC_MEM_SYNC = 0x0000000080000000ULL,
1446 /* eieio instruction */
1447 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1448
1449 /* Cache control instructions */
1450 PPC_CACHE = 0x0000000200000000ULL,
1451 /* icbi instruction */
1452 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1453 /* dcbz instruction with fixed cache line size */
1454 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1455 /* dcbz instruction with tunable cache line size */
1456 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1457 /* dcba instruction */
1458 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1459 /* Freescale cache locking instructions */
1460 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1461
1462 /* MMU related extensions */
1463 /* external control instructions */
1464 PPC_EXTERN = 0x0000010000000000ULL,
1465 /* segment register access instructions */
1466 PPC_SEGMENT = 0x0000020000000000ULL,
1467 /* PowerPC 6xx TLB management instructions */
1468 PPC_6xx_TLB = 0x0000040000000000ULL,
1469 /* PowerPC 74xx TLB management instructions */
1470 PPC_74xx_TLB = 0x0000080000000000ULL,
1471 /* PowerPC 40x TLB management instructions */
1472 PPC_40x_TLB = 0x0000100000000000ULL,
1473 /* segment register access instructions for PowerPC 64 "bridge" */
1474 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1475 /* SLB management */
1476 PPC_SLBI = 0x0000400000000000ULL,
1477
1478 /* Embedded PowerPC dedicated instructions */
1479 PPC_WRTEE = 0x0001000000000000ULL,
1480 /* PowerPC 40x exception model */
1481 PPC_40x_EXCP = 0x0002000000000000ULL,
1482 /* PowerPC 405 Mac instructions */
1483 PPC_405_MAC = 0x0004000000000000ULL,
1484 /* PowerPC 440 specific instructions */
1485 PPC_440_SPEC = 0x0008000000000000ULL,
1486 /* BookE (embedded) PowerPC specification */
1487 PPC_BOOKE = 0x0010000000000000ULL,
1488 /* mfapidi instruction */
1489 PPC_MFAPIDI = 0x0020000000000000ULL,
1490 /* tlbiva instruction */
1491 PPC_TLBIVA = 0x0040000000000000ULL,
1492 /* tlbivax instruction */
1493 PPC_TLBIVAX = 0x0080000000000000ULL,
1494 /* PowerPC 4xx dedicated instructions */
1495 PPC_4xx_COMMON = 0x0100000000000000ULL,
1496 /* PowerPC 40x ibct instructions */
1497 PPC_40x_ICBT = 0x0200000000000000ULL,
1498 /* rfmci is not implemented in all BookE PowerPC */
1499 PPC_RFMCI = 0x0400000000000000ULL,
1500 /* rfdi instruction */
1501 PPC_RFDI = 0x0800000000000000ULL,
1502 /* DCR accesses */
1503 PPC_DCR = 0x1000000000000000ULL,
1504 /* DCR extended accesse */
1505 PPC_DCRX = 0x2000000000000000ULL,
1506 /* user-mode DCR access, implemented in PowerPC 460 */
1507 PPC_DCRUX = 0x4000000000000000ULL,
1508 /* popcntw and popcntd instructions */
1509 PPC_POPCNTWD = 0x8000000000000000ULL,
1510 };
1511
1512 /*****************************************************************************/
1513 /* Memory access type :
1514 * may be needed for precise access rights control and precise exceptions.
1515 */
1516 enum {
1517 /* 1 bit to define user level / supervisor access */
1518 ACCESS_USER = 0x00,
1519 ACCESS_SUPER = 0x01,
1520 /* Type of instruction that generated the access */
1521 ACCESS_CODE = 0x10, /* Code fetch access */
1522 ACCESS_INT = 0x20, /* Integer load/store access */
1523 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1524 ACCESS_RES = 0x40, /* load/store with reservation */
1525 ACCESS_EXT = 0x50, /* external access */
1526 ACCESS_CACHE = 0x60, /* Cache manipulation */
1527 };
1528
1529 /* Hardware interruption sources:
1530 * all those exception can be raised simulteaneously
1531 */
1532 /* Input pins definitions */
1533 enum {
1534 /* 6xx bus input pins */
1535 PPC6xx_INPUT_HRESET = 0,
1536 PPC6xx_INPUT_SRESET = 1,
1537 PPC6xx_INPUT_CKSTP_IN = 2,
1538 PPC6xx_INPUT_MCP = 3,
1539 PPC6xx_INPUT_SMI = 4,
1540 PPC6xx_INPUT_INT = 5,
1541 PPC6xx_INPUT_TBEN = 6,
1542 PPC6xx_INPUT_WAKEUP = 7,
1543 PPC6xx_INPUT_NB,
1544 };
1545
1546 enum {
1547 /* Embedded PowerPC input pins */
1548 PPCBookE_INPUT_HRESET = 0,
1549 PPCBookE_INPUT_SRESET = 1,
1550 PPCBookE_INPUT_CKSTP_IN = 2,
1551 PPCBookE_INPUT_MCP = 3,
1552 PPCBookE_INPUT_SMI = 4,
1553 PPCBookE_INPUT_INT = 5,
1554 PPCBookE_INPUT_CINT = 6,
1555 PPCBookE_INPUT_NB,
1556 };
1557
1558 enum {
1559 /* PowerPC E500 input pins */
1560 PPCE500_INPUT_RESET_CORE = 0,
1561 PPCE500_INPUT_MCK = 1,
1562 PPCE500_INPUT_CINT = 3,
1563 PPCE500_INPUT_INT = 4,
1564 PPCE500_INPUT_DEBUG = 6,
1565 PPCE500_INPUT_NB,
1566 };
1567
1568 enum {
1569 /* PowerPC 40x input pins */
1570 PPC40x_INPUT_RESET_CORE = 0,
1571 PPC40x_INPUT_RESET_CHIP = 1,
1572 PPC40x_INPUT_RESET_SYS = 2,
1573 PPC40x_INPUT_CINT = 3,
1574 PPC40x_INPUT_INT = 4,
1575 PPC40x_INPUT_HALT = 5,
1576 PPC40x_INPUT_DEBUG = 6,
1577 PPC40x_INPUT_NB,
1578 };
1579
1580 enum {
1581 /* RCPU input pins */
1582 PPCRCPU_INPUT_PORESET = 0,
1583 PPCRCPU_INPUT_HRESET = 1,
1584 PPCRCPU_INPUT_SRESET = 2,
1585 PPCRCPU_INPUT_IRQ0 = 3,
1586 PPCRCPU_INPUT_IRQ1 = 4,
1587 PPCRCPU_INPUT_IRQ2 = 5,
1588 PPCRCPU_INPUT_IRQ3 = 6,
1589 PPCRCPU_INPUT_IRQ4 = 7,
1590 PPCRCPU_INPUT_IRQ5 = 8,
1591 PPCRCPU_INPUT_IRQ6 = 9,
1592 PPCRCPU_INPUT_IRQ7 = 10,
1593 PPCRCPU_INPUT_NB,
1594 };
1595
1596 #if defined(TARGET_PPC64)
1597 enum {
1598 /* PowerPC 970 input pins */
1599 PPC970_INPUT_HRESET = 0,
1600 PPC970_INPUT_SRESET = 1,
1601 PPC970_INPUT_CKSTP = 2,
1602 PPC970_INPUT_TBEN = 3,
1603 PPC970_INPUT_MCP = 4,
1604 PPC970_INPUT_INT = 5,
1605 PPC970_INPUT_THINT = 6,
1606 PPC970_INPUT_NB,
1607 };
1608 #endif
1609
1610 /* Hardware exceptions definitions */
1611 enum {
1612 /* External hardware exception sources */
1613 PPC_INTERRUPT_RESET = 0, /* Reset exception */
1614 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1615 PPC_INTERRUPT_MCK, /* Machine check exception */
1616 PPC_INTERRUPT_EXT, /* External interrupt */
1617 PPC_INTERRUPT_SMI, /* System management interrupt */
1618 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1619 PPC_INTERRUPT_DEBUG, /* External debug exception */
1620 PPC_INTERRUPT_THERM, /* Thermal exception */
1621 /* Internal hardware exception sources */
1622 PPC_INTERRUPT_DECR, /* Decrementer exception */
1623 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1624 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1625 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1626 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1627 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1628 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1629 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
1630 };
1631
1632 /*****************************************************************************/
1633
1634 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
1635 target_ulong *cs_base, int *flags)
1636 {
1637 *pc = env->nip;
1638 *cs_base = 0;
1639 *flags = env->hflags;
1640 }
1641
1642 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
1643 {
1644 #if defined(TARGET_PPC64)
1645 /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
1646 binaries on PPC64 yet. */
1647 env->gpr[13] = newtls;
1648 #else
1649 env->gpr[2] = newtls;
1650 #endif
1651 }
1652
1653 extern void (*cpu_ppc_hypercall)(CPUState *);
1654
1655 #endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing