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Merge branch 's390-for-upstream' of git://github.com/agraf/qemu
[qemu.git] / target-ppc / cpu.h
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 //#define PPC_EMULATE_32BITS_HYPV
26
27 #if defined (TARGET_PPC64)
28 /* PowerPC 64 definitions */
29 #define TARGET_LONG_BITS 64
30 #define TARGET_PAGE_BITS 12
31
32 /* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35 #define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37 /* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40 #ifdef TARGET_ABI32
41 # define TARGET_VIRT_ADDR_SPACE_BITS 32
42 #else
43 # define TARGET_VIRT_ADDR_SPACE_BITS 64
44 #endif
45
46 #define TARGET_PAGE_BITS_16M 24
47
48 #else /* defined (TARGET_PPC64) */
49 /* PowerPC 32 definitions */
50 #define TARGET_LONG_BITS 32
51
52 #if defined(TARGET_PPCEMB)
53 /* Specific definitions for PowerPC embedded */
54 /* BookE have 36 bits physical address space */
55 #if defined(CONFIG_USER_ONLY)
56 /* It looks like a lot of Linux programs assume page size
57 * is 4kB long. This is evil, but we have to deal with it...
58 */
59 #define TARGET_PAGE_BITS 12
60 #else /* defined(CONFIG_USER_ONLY) */
61 /* Pages can be 1 kB small */
62 #define TARGET_PAGE_BITS 10
63 #endif /* defined(CONFIG_USER_ONLY) */
64 #else /* defined(TARGET_PPCEMB) */
65 /* "standard" PowerPC 32 definitions */
66 #define TARGET_PAGE_BITS 12
67 #endif /* defined(TARGET_PPCEMB) */
68
69 #define TARGET_PHYS_ADDR_SPACE_BITS 36
70 #define TARGET_VIRT_ADDR_SPACE_BITS 32
71
72 #endif /* defined (TARGET_PPC64) */
73
74 #define CPUArchState struct CPUPPCState
75
76 #include "exec/cpu-defs.h"
77
78 #include "fpu/softfloat.h"
79
80 #define TARGET_HAS_ICE 1
81
82 #if defined (TARGET_PPC64)
83 #define ELF_MACHINE EM_PPC64
84 #else
85 #define ELF_MACHINE EM_PPC
86 #endif
87
88 /*****************************************************************************/
89 /* MMU model */
90 typedef enum powerpc_mmu_t powerpc_mmu_t;
91 enum powerpc_mmu_t {
92 POWERPC_MMU_UNKNOWN = 0x00000000,
93 /* Standard 32 bits PowerPC MMU */
94 POWERPC_MMU_32B = 0x00000001,
95 /* PowerPC 6xx MMU with software TLB */
96 POWERPC_MMU_SOFT_6xx = 0x00000002,
97 /* PowerPC 74xx MMU with software TLB */
98 POWERPC_MMU_SOFT_74xx = 0x00000003,
99 /* PowerPC 4xx MMU with software TLB */
100 POWERPC_MMU_SOFT_4xx = 0x00000004,
101 /* PowerPC 4xx MMU with software TLB and zones protections */
102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
103 /* PowerPC MMU in real mode only */
104 POWERPC_MMU_REAL = 0x00000006,
105 /* Freescale MPC8xx MMU model */
106 POWERPC_MMU_MPC8xx = 0x00000007,
107 /* BookE MMU model */
108 POWERPC_MMU_BOOKE = 0x00000008,
109 /* BookE 2.06 MMU model */
110 POWERPC_MMU_BOOKE206 = 0x00000009,
111 /* PowerPC 601 MMU model (specific BATs format) */
112 POWERPC_MMU_601 = 0x0000000A,
113 #if defined(TARGET_PPC64)
114 #define POWERPC_MMU_64 0x00010000
115 #define POWERPC_MMU_1TSEG 0x00020000
116 /* 64 bits PowerPC MMU */
117 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
118 /* 620 variant (no segment exceptions) */
119 POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
120 /* Architecture 2.06 variant */
121 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,
122 /* Architecture 2.06 "degraded" (no 1T segments) */
123 POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003,
124 #endif /* defined(TARGET_PPC64) */
125 };
126
127 /*****************************************************************************/
128 /* Exception model */
129 typedef enum powerpc_excp_t powerpc_excp_t;
130 enum powerpc_excp_t {
131 POWERPC_EXCP_UNKNOWN = 0,
132 /* Standard PowerPC exception model */
133 POWERPC_EXCP_STD,
134 /* PowerPC 40x exception model */
135 POWERPC_EXCP_40x,
136 /* PowerPC 601 exception model */
137 POWERPC_EXCP_601,
138 /* PowerPC 602 exception model */
139 POWERPC_EXCP_602,
140 /* PowerPC 603 exception model */
141 POWERPC_EXCP_603,
142 /* PowerPC 603e exception model */
143 POWERPC_EXCP_603E,
144 /* PowerPC G2 exception model */
145 POWERPC_EXCP_G2,
146 /* PowerPC 604 exception model */
147 POWERPC_EXCP_604,
148 /* PowerPC 7x0 exception model */
149 POWERPC_EXCP_7x0,
150 /* PowerPC 7x5 exception model */
151 POWERPC_EXCP_7x5,
152 /* PowerPC 74xx exception model */
153 POWERPC_EXCP_74xx,
154 /* BookE exception model */
155 POWERPC_EXCP_BOOKE,
156 #if defined(TARGET_PPC64)
157 /* PowerPC 970 exception model */
158 POWERPC_EXCP_970,
159 /* POWER7 exception model */
160 POWERPC_EXCP_POWER7,
161 #endif /* defined(TARGET_PPC64) */
162 };
163
164 /*****************************************************************************/
165 /* Exception vectors definitions */
166 enum {
167 POWERPC_EXCP_NONE = -1,
168 /* The 64 first entries are used by the PowerPC embedded specification */
169 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
170 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
171 POWERPC_EXCP_DSI = 2, /* Data storage exception */
172 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
173 POWERPC_EXCP_EXTERNAL = 4, /* External input */
174 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
175 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
176 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
177 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
178 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
179 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
180 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
181 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
182 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
183 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
184 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
185 /* Vectors 16 to 31 are reserved */
186 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
187 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
188 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
189 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
190 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
191 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
192 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
193 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
194 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
195 /* Vectors 42 to 63 are reserved */
196 /* Exceptions defined in the PowerPC server specification */
197 POWERPC_EXCP_RESET = 64, /* System reset exception */
198 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
199 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
200 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
201 POWERPC_EXCP_TRACE = 68, /* Trace exception */
202 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
203 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
204 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
205 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
206 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
207 /* 40x specific exceptions */
208 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
209 /* 601 specific exceptions */
210 POWERPC_EXCP_IO = 75, /* IO error exception */
211 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
212 /* 602 specific exceptions */
213 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
214 /* 602/603 specific exceptions */
215 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
216 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
217 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
218 /* Exceptions available on most PowerPC */
219 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
220 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
221 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
222 POWERPC_EXCP_SMI = 84, /* System management interrupt */
223 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
224 /* 7xx/74xx specific exceptions */
225 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
226 /* 74xx specific exceptions */
227 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
228 /* 970FX specific exceptions */
229 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
230 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
231 /* Freescale embedded cores specific exceptions */
232 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
233 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
234 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
235 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
236 /* EOL */
237 POWERPC_EXCP_NB = 96,
238 /* QEMU exceptions: used internally during code translation */
239 POWERPC_EXCP_STOP = 0x200, /* stop translation */
240 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
241 /* QEMU exceptions: special cases we want to stop translation */
242 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
243 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
244 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
245 };
246
247 /* Exceptions error codes */
248 enum {
249 /* Exception subtypes for POWERPC_EXCP_ALIGN */
250 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
251 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
252 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
253 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
254 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
255 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
256 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
257 /* FP exceptions */
258 POWERPC_EXCP_FP = 0x10,
259 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
260 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
261 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
262 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
263 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
264 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
265 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
266 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
267 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
268 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
269 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
270 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
271 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
272 /* Invalid instruction */
273 POWERPC_EXCP_INVAL = 0x20,
274 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
275 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
276 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
277 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
278 /* Privileged instruction */
279 POWERPC_EXCP_PRIV = 0x30,
280 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
281 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
282 /* Trap */
283 POWERPC_EXCP_TRAP = 0x40,
284 };
285
286 /*****************************************************************************/
287 /* Input pins model */
288 typedef enum powerpc_input_t powerpc_input_t;
289 enum powerpc_input_t {
290 PPC_FLAGS_INPUT_UNKNOWN = 0,
291 /* PowerPC 6xx bus */
292 PPC_FLAGS_INPUT_6xx,
293 /* BookE bus */
294 PPC_FLAGS_INPUT_BookE,
295 /* PowerPC 405 bus */
296 PPC_FLAGS_INPUT_405,
297 /* PowerPC 970 bus */
298 PPC_FLAGS_INPUT_970,
299 /* PowerPC POWER7 bus */
300 PPC_FLAGS_INPUT_POWER7,
301 /* PowerPC 401 bus */
302 PPC_FLAGS_INPUT_401,
303 /* Freescale RCPU bus */
304 PPC_FLAGS_INPUT_RCPU,
305 };
306
307 #define PPC_INPUT(env) (env->bus_model)
308
309 /*****************************************************************************/
310 typedef struct opc_handler_t opc_handler_t;
311
312 /*****************************************************************************/
313 /* Types used to describe some PowerPC registers */
314 typedef struct CPUPPCState CPUPPCState;
315 typedef struct ppc_tb_t ppc_tb_t;
316 typedef struct ppc_spr_t ppc_spr_t;
317 typedef struct ppc_dcr_t ppc_dcr_t;
318 typedef union ppc_avr_t ppc_avr_t;
319 typedef union ppc_tlb_t ppc_tlb_t;
320
321 /* SPR access micro-ops generations callbacks */
322 struct ppc_spr_t {
323 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
324 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
325 #if !defined(CONFIG_USER_ONLY)
326 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
327 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
328 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
329 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
330 #endif
331 const char *name;
332 #ifdef CONFIG_KVM
333 /* We (ab)use the fact that all the SPRs will have ids for the
334 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
335 * don't sync this */
336 uint64_t one_reg_id;
337 #endif
338 };
339
340 /* Altivec registers (128 bits) */
341 union ppc_avr_t {
342 float32 f[4];
343 uint8_t u8[16];
344 uint16_t u16[8];
345 uint32_t u32[4];
346 int8_t s8[16];
347 int16_t s16[8];
348 int32_t s32[4];
349 uint64_t u64[2];
350 };
351
352 #if !defined(CONFIG_USER_ONLY)
353 /* Software TLB cache */
354 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
355 struct ppc6xx_tlb_t {
356 target_ulong pte0;
357 target_ulong pte1;
358 target_ulong EPN;
359 };
360
361 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
362 struct ppcemb_tlb_t {
363 uint64_t RPN;
364 target_ulong EPN;
365 target_ulong PID;
366 target_ulong size;
367 uint32_t prot;
368 uint32_t attr; /* Storage attributes */
369 };
370
371 typedef struct ppcmas_tlb_t {
372 uint32_t mas8;
373 uint32_t mas1;
374 uint64_t mas2;
375 uint64_t mas7_3;
376 } ppcmas_tlb_t;
377
378 union ppc_tlb_t {
379 ppc6xx_tlb_t *tlb6;
380 ppcemb_tlb_t *tlbe;
381 ppcmas_tlb_t *tlbm;
382 };
383
384 /* possible TLB variants */
385 #define TLB_NONE 0
386 #define TLB_6XX 1
387 #define TLB_EMB 2
388 #define TLB_MAS 3
389 #endif
390
391 #define SDR_32_HTABORG 0xFFFF0000UL
392 #define SDR_32_HTABMASK 0x000001FFUL
393
394 #if defined(TARGET_PPC64)
395 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
396 #define SDR_64_HTABSIZE 0x000000000000001FULL
397 #endif /* defined(TARGET_PPC64 */
398
399 #define HASH_PTE_SIZE_32 8
400 #define HASH_PTE_SIZE_64 16
401
402 typedef struct ppc_slb_t ppc_slb_t;
403 struct ppc_slb_t {
404 uint64_t esid;
405 uint64_t vsid;
406 };
407
408 /* Bits in the SLB ESID word */
409 #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
410 #define SLB_ESID_V 0x0000000008000000ULL /* valid */
411
412 /* Bits in the SLB VSID word */
413 #define SLB_VSID_SHIFT 12
414 #define SLB_VSID_SHIFT_1T 24
415 #define SLB_VSID_SSIZE_SHIFT 62
416 #define SLB_VSID_B 0xc000000000000000ULL
417 #define SLB_VSID_B_256M 0x0000000000000000ULL
418 #define SLB_VSID_B_1T 0x4000000000000000ULL
419 #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
420 #define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
421 #define SLB_VSID_KS 0x0000000000000800ULL
422 #define SLB_VSID_KP 0x0000000000000400ULL
423 #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
424 #define SLB_VSID_L 0x0000000000000100ULL
425 #define SLB_VSID_C 0x0000000000000080ULL /* class */
426 #define SLB_VSID_LP 0x0000000000000030ULL
427 #define SLB_VSID_ATTR 0x0000000000000FFFULL
428
429 #define SEGMENT_SHIFT_256M 28
430 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
431
432 #define SEGMENT_SHIFT_1T 40
433 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
434
435
436 /*****************************************************************************/
437 /* Machine state register bits definition */
438 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
439 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
440 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
441 #define MSR_SHV 60 /* hypervisor state hflags */
442 #define MSR_CM 31 /* Computation mode for BookE hflags */
443 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
444 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
445 #define MSR_GS 28 /* guest state for BookE */
446 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
447 #define MSR_VR 25 /* altivec available x hflags */
448 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
449 #define MSR_AP 23 /* Access privilege state on 602 hflags */
450 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
451 #define MSR_KEY 19 /* key bit on 603e */
452 #define MSR_POW 18 /* Power management */
453 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
454 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
455 #define MSR_ILE 16 /* Interrupt little-endian mode */
456 #define MSR_EE 15 /* External interrupt enable */
457 #define MSR_PR 14 /* Problem state hflags */
458 #define MSR_FP 13 /* Floating point available hflags */
459 #define MSR_ME 12 /* Machine check interrupt enable */
460 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
461 #define MSR_SE 10 /* Single-step trace enable x hflags */
462 #define MSR_DWE 10 /* Debug wait enable on 405 x */
463 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
464 #define MSR_BE 9 /* Branch trace enable x hflags */
465 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
466 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
467 #define MSR_AL 7 /* AL bit on POWER */
468 #define MSR_EP 6 /* Exception prefix on 601 */
469 #define MSR_IR 5 /* Instruction relocate */
470 #define MSR_DR 4 /* Data relocate */
471 #define MSR_PE 3 /* Protection enable on 403 */
472 #define MSR_PX 2 /* Protection exclusive on 403 x */
473 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
474 #define MSR_RI 1 /* Recoverable interrupt 1 */
475 #define MSR_LE 0 /* Little-endian mode 1 hflags */
476
477 #define msr_sf ((env->msr >> MSR_SF) & 1)
478 #define msr_isf ((env->msr >> MSR_ISF) & 1)
479 #define msr_shv ((env->msr >> MSR_SHV) & 1)
480 #define msr_cm ((env->msr >> MSR_CM) & 1)
481 #define msr_icm ((env->msr >> MSR_ICM) & 1)
482 #define msr_thv ((env->msr >> MSR_THV) & 1)
483 #define msr_gs ((env->msr >> MSR_GS) & 1)
484 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
485 #define msr_vr ((env->msr >> MSR_VR) & 1)
486 #define msr_spe ((env->msr >> MSR_SPE) & 1)
487 #define msr_ap ((env->msr >> MSR_AP) & 1)
488 #define msr_sa ((env->msr >> MSR_SA) & 1)
489 #define msr_key ((env->msr >> MSR_KEY) & 1)
490 #define msr_pow ((env->msr >> MSR_POW) & 1)
491 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
492 #define msr_ce ((env->msr >> MSR_CE) & 1)
493 #define msr_ile ((env->msr >> MSR_ILE) & 1)
494 #define msr_ee ((env->msr >> MSR_EE) & 1)
495 #define msr_pr ((env->msr >> MSR_PR) & 1)
496 #define msr_fp ((env->msr >> MSR_FP) & 1)
497 #define msr_me ((env->msr >> MSR_ME) & 1)
498 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
499 #define msr_se ((env->msr >> MSR_SE) & 1)
500 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
501 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
502 #define msr_be ((env->msr >> MSR_BE) & 1)
503 #define msr_de ((env->msr >> MSR_DE) & 1)
504 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
505 #define msr_al ((env->msr >> MSR_AL) & 1)
506 #define msr_ep ((env->msr >> MSR_EP) & 1)
507 #define msr_ir ((env->msr >> MSR_IR) & 1)
508 #define msr_dr ((env->msr >> MSR_DR) & 1)
509 #define msr_pe ((env->msr >> MSR_PE) & 1)
510 #define msr_px ((env->msr >> MSR_PX) & 1)
511 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
512 #define msr_ri ((env->msr >> MSR_RI) & 1)
513 #define msr_le ((env->msr >> MSR_LE) & 1)
514 /* Hypervisor bit is more specific */
515 #if defined(TARGET_PPC64)
516 #define MSR_HVB (1ULL << MSR_SHV)
517 #define msr_hv msr_shv
518 #else
519 #if defined(PPC_EMULATE_32BITS_HYPV)
520 #define MSR_HVB (1ULL << MSR_THV)
521 #define msr_hv msr_thv
522 #else
523 #define MSR_HVB (0ULL)
524 #define msr_hv (0)
525 #endif
526 #endif
527
528 /* Exception state register bits definition */
529 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
530 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
531 #define ESR_PTR (1 << (63 - 38)) /* Trap */
532 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
533 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
534 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
535 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
536 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
537 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
538 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
539 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
540 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
541 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
542 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
543 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
544 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
545
546 enum {
547 POWERPC_FLAG_NONE = 0x00000000,
548 /* Flag for MSR bit 25 signification (VRE/SPE) */
549 POWERPC_FLAG_SPE = 0x00000001,
550 POWERPC_FLAG_VRE = 0x00000002,
551 /* Flag for MSR bit 17 signification (TGPR/CE) */
552 POWERPC_FLAG_TGPR = 0x00000004,
553 POWERPC_FLAG_CE = 0x00000008,
554 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
555 POWERPC_FLAG_SE = 0x00000010,
556 POWERPC_FLAG_DWE = 0x00000020,
557 POWERPC_FLAG_UBLE = 0x00000040,
558 /* Flag for MSR bit 9 signification (BE/DE) */
559 POWERPC_FLAG_BE = 0x00000080,
560 POWERPC_FLAG_DE = 0x00000100,
561 /* Flag for MSR bit 2 signification (PX/PMM) */
562 POWERPC_FLAG_PX = 0x00000200,
563 POWERPC_FLAG_PMM = 0x00000400,
564 /* Flag for special features */
565 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
566 POWERPC_FLAG_RTC_CLK = 0x00010000,
567 POWERPC_FLAG_BUS_CLK = 0x00020000,
568 /* Has CFAR */
569 POWERPC_FLAG_CFAR = 0x00040000,
570 };
571
572 /*****************************************************************************/
573 /* Floating point status and control register */
574 #define FPSCR_FX 31 /* Floating-point exception summary */
575 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
576 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
577 #define FPSCR_OX 28 /* Floating-point overflow exception */
578 #define FPSCR_UX 27 /* Floating-point underflow exception */
579 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
580 #define FPSCR_XX 25 /* Floating-point inexact exception */
581 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
582 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
583 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
584 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
585 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
586 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
587 #define FPSCR_FR 18 /* Floating-point fraction rounded */
588 #define FPSCR_FI 17 /* Floating-point fraction inexact */
589 #define FPSCR_C 16 /* Floating-point result class descriptor */
590 #define FPSCR_FL 15 /* Floating-point less than or negative */
591 #define FPSCR_FG 14 /* Floating-point greater than or negative */
592 #define FPSCR_FE 13 /* Floating-point equal or zero */
593 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
594 #define FPSCR_FPCC 12 /* Floating-point condition code */
595 #define FPSCR_FPRF 12 /* Floating-point result flags */
596 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
597 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
598 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
599 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
600 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
601 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
602 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
603 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
604 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
605 #define FPSCR_RN1 1
606 #define FPSCR_RN 0 /* Floating-point rounding control */
607 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
608 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
609 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
610 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
611 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
612 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
613 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
614 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
615 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
616 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
617 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
618 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
619 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
620 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
621 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
622 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
623 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
624 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
625 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
626 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
627 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
628 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
629 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
630 /* Invalid operation exception summary */
631 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
632 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
633 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
634 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
635 (1 << FPSCR_VXCVI)))
636 /* exception summary */
637 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
638 /* enabled exception summary */
639 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
640 0x1F)
641
642 /*****************************************************************************/
643 /* Vector status and control register */
644 #define VSCR_NJ 16 /* Vector non-java */
645 #define VSCR_SAT 0 /* Vector saturation */
646 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
647 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
648
649 /*****************************************************************************/
650 /* BookE e500 MMU registers */
651
652 #define MAS0_NV_SHIFT 0
653 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
654
655 #define MAS0_WQ_SHIFT 12
656 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
657 /* Write TLB entry regardless of reservation */
658 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
659 /* Write TLB entry only already in use */
660 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
661 /* Clear TLB entry */
662 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
663
664 #define MAS0_HES_SHIFT 14
665 #define MAS0_HES (1 << MAS0_HES_SHIFT)
666
667 #define MAS0_ESEL_SHIFT 16
668 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
669
670 #define MAS0_TLBSEL_SHIFT 28
671 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
672 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
673 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
674 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
675 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
676
677 #define MAS0_ATSEL_SHIFT 31
678 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
679 #define MAS0_ATSEL_TLB 0
680 #define MAS0_ATSEL_LRAT MAS0_ATSEL
681
682 #define MAS1_TSIZE_SHIFT 7
683 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
684
685 #define MAS1_TS_SHIFT 12
686 #define MAS1_TS (1 << MAS1_TS_SHIFT)
687
688 #define MAS1_IND_SHIFT 13
689 #define MAS1_IND (1 << MAS1_IND_SHIFT)
690
691 #define MAS1_TID_SHIFT 16
692 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
693
694 #define MAS1_IPROT_SHIFT 30
695 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
696
697 #define MAS1_VALID_SHIFT 31
698 #define MAS1_VALID 0x80000000
699
700 #define MAS2_EPN_SHIFT 12
701 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
702
703 #define MAS2_ACM_SHIFT 6
704 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
705
706 #define MAS2_VLE_SHIFT 5
707 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
708
709 #define MAS2_W_SHIFT 4
710 #define MAS2_W (1 << MAS2_W_SHIFT)
711
712 #define MAS2_I_SHIFT 3
713 #define MAS2_I (1 << MAS2_I_SHIFT)
714
715 #define MAS2_M_SHIFT 2
716 #define MAS2_M (1 << MAS2_M_SHIFT)
717
718 #define MAS2_G_SHIFT 1
719 #define MAS2_G (1 << MAS2_G_SHIFT)
720
721 #define MAS2_E_SHIFT 0
722 #define MAS2_E (1 << MAS2_E_SHIFT)
723
724 #define MAS3_RPN_SHIFT 12
725 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
726
727 #define MAS3_U0 0x00000200
728 #define MAS3_U1 0x00000100
729 #define MAS3_U2 0x00000080
730 #define MAS3_U3 0x00000040
731 #define MAS3_UX 0x00000020
732 #define MAS3_SX 0x00000010
733 #define MAS3_UW 0x00000008
734 #define MAS3_SW 0x00000004
735 #define MAS3_UR 0x00000002
736 #define MAS3_SR 0x00000001
737 #define MAS3_SPSIZE_SHIFT 1
738 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
739
740 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
741 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
742 #define MAS4_TIDSELD_MASK 0x00030000
743 #define MAS4_TIDSELD_PID0 0x00000000
744 #define MAS4_TIDSELD_PID1 0x00010000
745 #define MAS4_TIDSELD_PID2 0x00020000
746 #define MAS4_TIDSELD_PIDZ 0x00030000
747 #define MAS4_INDD 0x00008000 /* Default IND */
748 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
749 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
750 #define MAS4_ACMD 0x00000040
751 #define MAS4_VLED 0x00000020
752 #define MAS4_WD 0x00000010
753 #define MAS4_ID 0x00000008
754 #define MAS4_MD 0x00000004
755 #define MAS4_GD 0x00000002
756 #define MAS4_ED 0x00000001
757 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
758 #define MAS4_WIMGED_SHIFT 0
759
760 #define MAS5_SGS 0x80000000
761 #define MAS5_SLPID_MASK 0x00000fff
762
763 #define MAS6_SPID0 0x3fff0000
764 #define MAS6_SPID1 0x00007ffe
765 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
766 #define MAS6_SAS 0x00000001
767 #define MAS6_SPID MAS6_SPID0
768 #define MAS6_SIND 0x00000002 /* Indirect page */
769 #define MAS6_SIND_SHIFT 1
770 #define MAS6_SPID_MASK 0x3fff0000
771 #define MAS6_SPID_SHIFT 16
772 #define MAS6_ISIZE_MASK 0x00000f80
773 #define MAS6_ISIZE_SHIFT 7
774
775 #define MAS7_RPN 0xffffffff
776
777 #define MAS8_TGS 0x80000000
778 #define MAS8_VF 0x40000000
779 #define MAS8_TLBPID 0x00000fff
780
781 /* Bit definitions for MMUCFG */
782 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
783 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
784 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
785 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
786 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
787 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
788 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
789 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
790 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
791
792 /* Bit definitions for MMUCSR0 */
793 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
794 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
795 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
796 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
797 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
798 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
799 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
800 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
801 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
802 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
803
804 /* TLBnCFG encoding */
805 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
806 #define TLBnCFG_HES 0x00002000 /* HW select supported */
807 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
808 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
809 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
810 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
811 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
812 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
813 #define TLBnCFG_MINSIZE_SHIFT 20
814 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
815 #define TLBnCFG_MAXSIZE_SHIFT 16
816 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
817 #define TLBnCFG_ASSOC_SHIFT 24
818
819 /* TLBnPS encoding */
820 #define TLBnPS_4K 0x00000004
821 #define TLBnPS_8K 0x00000008
822 #define TLBnPS_16K 0x00000010
823 #define TLBnPS_32K 0x00000020
824 #define TLBnPS_64K 0x00000040
825 #define TLBnPS_128K 0x00000080
826 #define TLBnPS_256K 0x00000100
827 #define TLBnPS_512K 0x00000200
828 #define TLBnPS_1M 0x00000400
829 #define TLBnPS_2M 0x00000800
830 #define TLBnPS_4M 0x00001000
831 #define TLBnPS_8M 0x00002000
832 #define TLBnPS_16M 0x00004000
833 #define TLBnPS_32M 0x00008000
834 #define TLBnPS_64M 0x00010000
835 #define TLBnPS_128M 0x00020000
836 #define TLBnPS_256M 0x00040000
837 #define TLBnPS_512M 0x00080000
838 #define TLBnPS_1G 0x00100000
839 #define TLBnPS_2G 0x00200000
840 #define TLBnPS_4G 0x00400000
841 #define TLBnPS_8G 0x00800000
842 #define TLBnPS_16G 0x01000000
843 #define TLBnPS_32G 0x02000000
844 #define TLBnPS_64G 0x04000000
845 #define TLBnPS_128G 0x08000000
846 #define TLBnPS_256G 0x10000000
847
848 /* tlbilx action encoding */
849 #define TLBILX_T_ALL 0
850 #define TLBILX_T_TID 1
851 #define TLBILX_T_FULLMATCH 3
852 #define TLBILX_T_CLASS0 4
853 #define TLBILX_T_CLASS1 5
854 #define TLBILX_T_CLASS2 6
855 #define TLBILX_T_CLASS3 7
856
857 /* BookE 2.06 helper defines */
858
859 #define BOOKE206_FLUSH_TLB0 (1 << 0)
860 #define BOOKE206_FLUSH_TLB1 (1 << 1)
861 #define BOOKE206_FLUSH_TLB2 (1 << 2)
862 #define BOOKE206_FLUSH_TLB3 (1 << 3)
863
864 /* number of possible TLBs */
865 #define BOOKE206_MAX_TLBN 4
866
867 /*****************************************************************************/
868 /* Embedded.Processor Control */
869
870 #define DBELL_TYPE_SHIFT 27
871 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
872 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
873 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
874 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
875 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
876 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
877
878 #define DBELL_BRDCAST (1 << 26)
879 #define DBELL_LPIDTAG_SHIFT 14
880 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
881 #define DBELL_PIRTAG_MASK 0x3fff
882
883 /*****************************************************************************/
884 /* Segment page size information, used by recent hash MMUs
885 * The format of this structure mirrors kvm_ppc_smmu_info
886 */
887
888 #define PPC_PAGE_SIZES_MAX_SZ 8
889
890 struct ppc_one_page_size {
891 uint32_t page_shift; /* Page shift (or 0) */
892 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
893 };
894
895 struct ppc_one_seg_page_size {
896 uint32_t page_shift; /* Base page shift of segment (or 0) */
897 uint32_t slb_enc; /* SLB encoding for BookS */
898 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
899 };
900
901 struct ppc_segment_page_sizes {
902 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
903 };
904
905
906 /*****************************************************************************/
907 /* The whole PowerPC CPU context */
908 #define NB_MMU_MODES 3
909
910 struct CPUPPCState {
911 /* First are the most commonly used resources
912 * during translated code execution
913 */
914 /* general purpose registers */
915 target_ulong gpr[32];
916 #if !defined(TARGET_PPC64)
917 /* Storage for GPR MSB, used by the SPE extension */
918 target_ulong gprh[32];
919 #endif
920 /* LR */
921 target_ulong lr;
922 /* CTR */
923 target_ulong ctr;
924 /* condition register */
925 uint32_t crf[8];
926 #if defined(TARGET_PPC64)
927 /* CFAR */
928 target_ulong cfar;
929 #endif
930 /* XER (with SO, OV, CA split out) */
931 target_ulong xer;
932 target_ulong so;
933 target_ulong ov;
934 target_ulong ca;
935 /* Reservation address */
936 target_ulong reserve_addr;
937 /* Reservation value */
938 target_ulong reserve_val;
939 /* Reservation store address */
940 target_ulong reserve_ea;
941 /* Reserved store source register and size */
942 target_ulong reserve_info;
943
944 /* Those ones are used in supervisor mode only */
945 /* machine state register */
946 target_ulong msr;
947 /* temporary general purpose registers */
948 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
949
950 /* Floating point execution context */
951 float_status fp_status;
952 /* floating point registers */
953 float64 fpr[32];
954 /* floating point status and control register */
955 target_ulong fpscr;
956
957 /* Next instruction pointer */
958 target_ulong nip;
959
960 int access_type; /* when a memory exception occurs, the access
961 type is stored here */
962
963 CPU_COMMON
964
965 /* MMU context - only relevant for full system emulation */
966 #if !defined(CONFIG_USER_ONLY)
967 #if defined(TARGET_PPC64)
968 /* Address space register */
969 target_ulong asr;
970 /* PowerPC 64 SLB area */
971 ppc_slb_t slb[64];
972 int slb_nr;
973 #endif
974 /* segment registers */
975 hwaddr htab_base;
976 hwaddr htab_mask;
977 target_ulong sr[32];
978 /* externally stored hash table */
979 uint8_t *external_htab;
980 /* BATs */
981 int nb_BATs;
982 target_ulong DBAT[2][8];
983 target_ulong IBAT[2][8];
984 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
985 int nb_tlb; /* Total number of TLB */
986 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
987 int nb_ways; /* Number of ways in the TLB set */
988 int last_way; /* Last used way used to allocate TLB in a LRU way */
989 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
990 int nb_pids; /* Number of available PID registers */
991 int tlb_type; /* Type of TLB we're dealing with */
992 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
993 /* 403 dedicated access protection registers */
994 target_ulong pb[4];
995 bool tlb_dirty; /* Set to non-zero when modifying TLB */
996 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
997 #endif
998
999 /* Other registers */
1000 /* Special purpose registers */
1001 target_ulong spr[1024];
1002 ppc_spr_t spr_cb[1024];
1003 /* Altivec registers */
1004 ppc_avr_t avr[32];
1005 uint32_t vscr;
1006 /* VSX registers */
1007 uint64_t vsr[32];
1008 /* SPE registers */
1009 uint64_t spe_acc;
1010 uint32_t spe_fscr;
1011 /* SPE and Altivec can share a status since they will never be used
1012 * simultaneously */
1013 float_status vec_status;
1014
1015 /* Internal devices resources */
1016 /* Time base and decrementer */
1017 ppc_tb_t *tb_env;
1018 /* Device control registers */
1019 ppc_dcr_t *dcr_env;
1020
1021 int dcache_line_size;
1022 int icache_line_size;
1023
1024 /* Those resources are used during exception processing */
1025 /* CPU model definition */
1026 target_ulong msr_mask;
1027 powerpc_mmu_t mmu_model;
1028 powerpc_excp_t excp_model;
1029 powerpc_input_t bus_model;
1030 int bfd_mach;
1031 uint32_t flags;
1032 uint64_t insns_flags;
1033 uint64_t insns_flags2;
1034 #if defined(TARGET_PPC64)
1035 struct ppc_segment_page_sizes sps;
1036 #endif
1037
1038 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1039 uint64_t vpa_addr;
1040 uint64_t slb_shadow_addr, slb_shadow_size;
1041 uint64_t dtl_addr, dtl_size;
1042 #endif /* TARGET_PPC64 */
1043
1044 int error_code;
1045 uint32_t pending_interrupts;
1046 #if !defined(CONFIG_USER_ONLY)
1047 /* This is the IRQ controller, which is implementation dependent
1048 * and only relevant when emulating a complete machine.
1049 */
1050 uint32_t irq_input_state;
1051 void **irq_inputs;
1052 /* Exception vectors */
1053 target_ulong excp_vectors[POWERPC_EXCP_NB];
1054 target_ulong excp_prefix;
1055 target_ulong hreset_excp_prefix;
1056 target_ulong ivor_mask;
1057 target_ulong ivpr_mask;
1058 target_ulong hreset_vector;
1059 hwaddr mpic_iack;
1060 /* true when the external proxy facility mode is enabled */
1061 bool mpic_proxy;
1062 #endif
1063
1064 /* Those resources are used only during code translation */
1065 /* opcode handlers */
1066 opc_handler_t *opcodes[0x40];
1067
1068 /* Those resources are used only in QEMU core */
1069 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1070 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1071 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1072
1073 /* Power management */
1074 int (*check_pow)(CPUPPCState *env);
1075
1076 #if !defined(CONFIG_USER_ONLY)
1077 void *load_info; /* Holds boot loading state. */
1078 #endif
1079
1080 /* booke timers */
1081
1082 /* Specifies bit locations of the Time Base used to signal a fixed timer
1083 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1084 *
1085 * 0 selects the least significant bit.
1086 * 63 selects the most significant bit.
1087 */
1088 uint8_t fit_period[4];
1089 uint8_t wdt_period[4];
1090 };
1091
1092 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1093 do { \
1094 env->fit_period[0] = (a_); \
1095 env->fit_period[1] = (b_); \
1096 env->fit_period[2] = (c_); \
1097 env->fit_period[3] = (d_); \
1098 } while (0)
1099
1100 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1101 do { \
1102 env->wdt_period[0] = (a_); \
1103 env->wdt_period[1] = (b_); \
1104 env->wdt_period[2] = (c_); \
1105 env->wdt_period[3] = (d_); \
1106 } while (0)
1107
1108 #if !defined(CONFIG_USER_ONLY)
1109 /* Context used internally during MMU translations */
1110 typedef struct mmu_ctx_t mmu_ctx_t;
1111 struct mmu_ctx_t {
1112 hwaddr raddr; /* Real address */
1113 hwaddr eaddr; /* Effective address */
1114 int prot; /* Protection bits */
1115 hwaddr hash[2]; /* Pagetable hash values */
1116 target_ulong ptem; /* Virtual segment ID | API */
1117 int key; /* Access key */
1118 int nx; /* Non-execute area */
1119 };
1120 #endif
1121
1122 #include "cpu-qom.h"
1123
1124 /*****************************************************************************/
1125 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1126 void ppc_translate_init(void);
1127 int cpu_ppc_exec (CPUPPCState *s);
1128 /* you can call this signal handler from your SIGBUS and SIGSEGV
1129 signal handlers to inform the virtual CPU of exceptions. non zero
1130 is returned if the signal was handled by the virtual CPU. */
1131 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1132 void *puc);
1133 int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
1134 int mmu_idx);
1135 #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
1136 void do_interrupt (CPUPPCState *env);
1137 void ppc_hw_interrupt (CPUPPCState *env);
1138
1139 #if !defined(CONFIG_USER_ONLY)
1140 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1141 #if defined(TARGET_PPC64)
1142 void ppc_store_asr (CPUPPCState *env, target_ulong value);
1143 int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
1144 #endif /* defined(TARGET_PPC64) */
1145 #endif /* !defined(CONFIG_USER_ONLY) */
1146 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1147
1148 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1149
1150 /* Time-base and decrementer management */
1151 #ifndef NO_CPU_IO_DEFS
1152 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1153 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1154 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1155 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1156 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1157 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1158 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1159 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1160 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1161 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1162 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1163 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1164 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1165 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1166 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1167 #if !defined(CONFIG_USER_ONLY)
1168 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1169 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1170 target_ulong load_40x_pit (CPUPPCState *env);
1171 void store_40x_pit (CPUPPCState *env, target_ulong val);
1172 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1173 void store_40x_sler (CPUPPCState *env, uint32_t val);
1174 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1175 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1176 int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
1177 hwaddr *raddrp, target_ulong address,
1178 uint32_t pid);
1179 void ppc_tlb_invalidate_all (CPUPPCState *env);
1180 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1181 #endif
1182 #endif
1183
1184 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1185 {
1186 uint64_t gprv;
1187
1188 gprv = env->gpr[gprn];
1189 #if !defined(TARGET_PPC64)
1190 if (env->flags & POWERPC_FLAG_SPE) {
1191 /* If the CPU implements the SPE extension, we have to get the
1192 * high bits of the GPR from the gprh storage area
1193 */
1194 gprv &= 0xFFFFFFFFULL;
1195 gprv |= (uint64_t)env->gprh[gprn] << 32;
1196 }
1197 #endif
1198
1199 return gprv;
1200 }
1201
1202 /* Device control registers */
1203 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1204 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1205
1206 static inline CPUPPCState *cpu_init(const char *cpu_model)
1207 {
1208 PowerPCCPU *cpu = cpu_ppc_init(cpu_model);
1209 if (cpu == NULL) {
1210 return NULL;
1211 }
1212 return &cpu->env;
1213 }
1214
1215 #define cpu_exec cpu_ppc_exec
1216 #define cpu_gen_code cpu_ppc_gen_code
1217 #define cpu_signal_handler cpu_ppc_signal_handler
1218 #define cpu_list ppc_cpu_list
1219
1220 #define CPU_SAVE_VERSION 4
1221
1222 /* MMU modes definitions */
1223 #define MMU_MODE0_SUFFIX _user
1224 #define MMU_MODE1_SUFFIX _kernel
1225 #define MMU_MODE2_SUFFIX _hypv
1226 #define MMU_USER_IDX 0
1227 static inline int cpu_mmu_index (CPUPPCState *env)
1228 {
1229 return env->mmu_idx;
1230 }
1231
1232 #if defined(CONFIG_USER_ONLY)
1233 static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)
1234 {
1235 if (newsp)
1236 env->gpr[1] = newsp;
1237 env->gpr[3] = 0;
1238 }
1239 #endif
1240
1241 #include "exec/cpu-all.h"
1242
1243 /*****************************************************************************/
1244 /* CRF definitions */
1245 #define CRF_LT 3
1246 #define CRF_GT 2
1247 #define CRF_EQ 1
1248 #define CRF_SO 0
1249 #define CRF_CH (1 << CRF_LT)
1250 #define CRF_CL (1 << CRF_GT)
1251 #define CRF_CH_OR_CL (1 << CRF_EQ)
1252 #define CRF_CH_AND_CL (1 << CRF_SO)
1253
1254 /* XER definitions */
1255 #define XER_SO 31
1256 #define XER_OV 30
1257 #define XER_CA 29
1258 #define XER_CMP 8
1259 #define XER_BC 0
1260 #define xer_so (env->so)
1261 #define xer_ov (env->ov)
1262 #define xer_ca (env->ca)
1263 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1264 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1265
1266 /* SPR definitions */
1267 #define SPR_MQ (0x000)
1268 #define SPR_XER (0x001)
1269 #define SPR_601_VRTCU (0x004)
1270 #define SPR_601_VRTCL (0x005)
1271 #define SPR_601_UDECR (0x006)
1272 #define SPR_LR (0x008)
1273 #define SPR_CTR (0x009)
1274 #define SPR_DSCR (0x011)
1275 #define SPR_DSISR (0x012)
1276 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1277 #define SPR_601_RTCU (0x014)
1278 #define SPR_601_RTCL (0x015)
1279 #define SPR_DECR (0x016)
1280 #define SPR_SDR1 (0x019)
1281 #define SPR_SRR0 (0x01A)
1282 #define SPR_SRR1 (0x01B)
1283 #define SPR_CFAR (0x01C)
1284 #define SPR_AMR (0x01D)
1285 #define SPR_BOOKE_PID (0x030)
1286 #define SPR_BOOKE_DECAR (0x036)
1287 #define SPR_BOOKE_CSRR0 (0x03A)
1288 #define SPR_BOOKE_CSRR1 (0x03B)
1289 #define SPR_BOOKE_DEAR (0x03D)
1290 #define SPR_BOOKE_ESR (0x03E)
1291 #define SPR_BOOKE_IVPR (0x03F)
1292 #define SPR_MPC_EIE (0x050)
1293 #define SPR_MPC_EID (0x051)
1294 #define SPR_MPC_NRI (0x052)
1295 #define SPR_CTRL (0x088)
1296 #define SPR_MPC_CMPA (0x090)
1297 #define SPR_MPC_CMPB (0x091)
1298 #define SPR_MPC_CMPC (0x092)
1299 #define SPR_MPC_CMPD (0x093)
1300 #define SPR_MPC_ECR (0x094)
1301 #define SPR_MPC_DER (0x095)
1302 #define SPR_MPC_COUNTA (0x096)
1303 #define SPR_MPC_COUNTB (0x097)
1304 #define SPR_UCTRL (0x098)
1305 #define SPR_MPC_CMPE (0x098)
1306 #define SPR_MPC_CMPF (0x099)
1307 #define SPR_MPC_CMPG (0x09A)
1308 #define SPR_MPC_CMPH (0x09B)
1309 #define SPR_MPC_LCTRL1 (0x09C)
1310 #define SPR_MPC_LCTRL2 (0x09D)
1311 #define SPR_MPC_ICTRL (0x09E)
1312 #define SPR_MPC_BAR (0x09F)
1313 #define SPR_VRSAVE (0x100)
1314 #define SPR_USPRG0 (0x100)
1315 #define SPR_USPRG1 (0x101)
1316 #define SPR_USPRG2 (0x102)
1317 #define SPR_USPRG3 (0x103)
1318 #define SPR_USPRG4 (0x104)
1319 #define SPR_USPRG5 (0x105)
1320 #define SPR_USPRG6 (0x106)
1321 #define SPR_USPRG7 (0x107)
1322 #define SPR_VTBL (0x10C)
1323 #define SPR_VTBU (0x10D)
1324 #define SPR_SPRG0 (0x110)
1325 #define SPR_SPRG1 (0x111)
1326 #define SPR_SPRG2 (0x112)
1327 #define SPR_SPRG3 (0x113)
1328 #define SPR_SPRG4 (0x114)
1329 #define SPR_SCOMC (0x114)
1330 #define SPR_SPRG5 (0x115)
1331 #define SPR_SCOMD (0x115)
1332 #define SPR_SPRG6 (0x116)
1333 #define SPR_SPRG7 (0x117)
1334 #define SPR_ASR (0x118)
1335 #define SPR_EAR (0x11A)
1336 #define SPR_TBL (0x11C)
1337 #define SPR_TBU (0x11D)
1338 #define SPR_TBU40 (0x11E)
1339 #define SPR_SVR (0x11E)
1340 #define SPR_BOOKE_PIR (0x11E)
1341 #define SPR_PVR (0x11F)
1342 #define SPR_HSPRG0 (0x130)
1343 #define SPR_BOOKE_DBSR (0x130)
1344 #define SPR_HSPRG1 (0x131)
1345 #define SPR_HDSISR (0x132)
1346 #define SPR_HDAR (0x133)
1347 #define SPR_BOOKE_EPCR (0x133)
1348 #define SPR_SPURR (0x134)
1349 #define SPR_BOOKE_DBCR0 (0x134)
1350 #define SPR_IBCR (0x135)
1351 #define SPR_PURR (0x135)
1352 #define SPR_BOOKE_DBCR1 (0x135)
1353 #define SPR_DBCR (0x136)
1354 #define SPR_HDEC (0x136)
1355 #define SPR_BOOKE_DBCR2 (0x136)
1356 #define SPR_HIOR (0x137)
1357 #define SPR_MBAR (0x137)
1358 #define SPR_RMOR (0x138)
1359 #define SPR_BOOKE_IAC1 (0x138)
1360 #define SPR_HRMOR (0x139)
1361 #define SPR_BOOKE_IAC2 (0x139)
1362 #define SPR_HSRR0 (0x13A)
1363 #define SPR_BOOKE_IAC3 (0x13A)
1364 #define SPR_HSRR1 (0x13B)
1365 #define SPR_BOOKE_IAC4 (0x13B)
1366 #define SPR_LPCR (0x13C)
1367 #define SPR_BOOKE_DAC1 (0x13C)
1368 #define SPR_LPIDR (0x13D)
1369 #define SPR_DABR2 (0x13D)
1370 #define SPR_BOOKE_DAC2 (0x13D)
1371 #define SPR_BOOKE_DVC1 (0x13E)
1372 #define SPR_BOOKE_DVC2 (0x13F)
1373 #define SPR_BOOKE_TSR (0x150)
1374 #define SPR_BOOKE_TCR (0x154)
1375 #define SPR_BOOKE_TLB0PS (0x158)
1376 #define SPR_BOOKE_TLB1PS (0x159)
1377 #define SPR_BOOKE_TLB2PS (0x15A)
1378 #define SPR_BOOKE_TLB3PS (0x15B)
1379 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1380 #define SPR_BOOKE_IVOR0 (0x190)
1381 #define SPR_BOOKE_IVOR1 (0x191)
1382 #define SPR_BOOKE_IVOR2 (0x192)
1383 #define SPR_BOOKE_IVOR3 (0x193)
1384 #define SPR_BOOKE_IVOR4 (0x194)
1385 #define SPR_BOOKE_IVOR5 (0x195)
1386 #define SPR_BOOKE_IVOR6 (0x196)
1387 #define SPR_BOOKE_IVOR7 (0x197)
1388 #define SPR_BOOKE_IVOR8 (0x198)
1389 #define SPR_BOOKE_IVOR9 (0x199)
1390 #define SPR_BOOKE_IVOR10 (0x19A)
1391 #define SPR_BOOKE_IVOR11 (0x19B)
1392 #define SPR_BOOKE_IVOR12 (0x19C)
1393 #define SPR_BOOKE_IVOR13 (0x19D)
1394 #define SPR_BOOKE_IVOR14 (0x19E)
1395 #define SPR_BOOKE_IVOR15 (0x19F)
1396 #define SPR_BOOKE_IVOR38 (0x1B0)
1397 #define SPR_BOOKE_IVOR39 (0x1B1)
1398 #define SPR_BOOKE_IVOR40 (0x1B2)
1399 #define SPR_BOOKE_IVOR41 (0x1B3)
1400 #define SPR_BOOKE_IVOR42 (0x1B4)
1401 #define SPR_BOOKE_SPEFSCR (0x200)
1402 #define SPR_Exxx_BBEAR (0x201)
1403 #define SPR_Exxx_BBTAR (0x202)
1404 #define SPR_Exxx_L1CFG0 (0x203)
1405 #define SPR_Exxx_NPIDR (0x205)
1406 #define SPR_ATBL (0x20E)
1407 #define SPR_ATBU (0x20F)
1408 #define SPR_IBAT0U (0x210)
1409 #define SPR_BOOKE_IVOR32 (0x210)
1410 #define SPR_RCPU_MI_GRA (0x210)
1411 #define SPR_IBAT0L (0x211)
1412 #define SPR_BOOKE_IVOR33 (0x211)
1413 #define SPR_IBAT1U (0x212)
1414 #define SPR_BOOKE_IVOR34 (0x212)
1415 #define SPR_IBAT1L (0x213)
1416 #define SPR_BOOKE_IVOR35 (0x213)
1417 #define SPR_IBAT2U (0x214)
1418 #define SPR_BOOKE_IVOR36 (0x214)
1419 #define SPR_IBAT2L (0x215)
1420 #define SPR_BOOKE_IVOR37 (0x215)
1421 #define SPR_IBAT3U (0x216)
1422 #define SPR_IBAT3L (0x217)
1423 #define SPR_DBAT0U (0x218)
1424 #define SPR_RCPU_L2U_GRA (0x218)
1425 #define SPR_DBAT0L (0x219)
1426 #define SPR_DBAT1U (0x21A)
1427 #define SPR_DBAT1L (0x21B)
1428 #define SPR_DBAT2U (0x21C)
1429 #define SPR_DBAT2L (0x21D)
1430 #define SPR_DBAT3U (0x21E)
1431 #define SPR_DBAT3L (0x21F)
1432 #define SPR_IBAT4U (0x230)
1433 #define SPR_RPCU_BBCMCR (0x230)
1434 #define SPR_MPC_IC_CST (0x230)
1435 #define SPR_Exxx_CTXCR (0x230)
1436 #define SPR_IBAT4L (0x231)
1437 #define SPR_MPC_IC_ADR (0x231)
1438 #define SPR_Exxx_DBCR3 (0x231)
1439 #define SPR_IBAT5U (0x232)
1440 #define SPR_MPC_IC_DAT (0x232)
1441 #define SPR_Exxx_DBCNT (0x232)
1442 #define SPR_IBAT5L (0x233)
1443 #define SPR_IBAT6U (0x234)
1444 #define SPR_IBAT6L (0x235)
1445 #define SPR_IBAT7U (0x236)
1446 #define SPR_IBAT7L (0x237)
1447 #define SPR_DBAT4U (0x238)
1448 #define SPR_RCPU_L2U_MCR (0x238)
1449 #define SPR_MPC_DC_CST (0x238)
1450 #define SPR_Exxx_ALTCTXCR (0x238)
1451 #define SPR_DBAT4L (0x239)
1452 #define SPR_MPC_DC_ADR (0x239)
1453 #define SPR_DBAT5U (0x23A)
1454 #define SPR_BOOKE_MCSRR0 (0x23A)
1455 #define SPR_MPC_DC_DAT (0x23A)
1456 #define SPR_DBAT5L (0x23B)
1457 #define SPR_BOOKE_MCSRR1 (0x23B)
1458 #define SPR_DBAT6U (0x23C)
1459 #define SPR_BOOKE_MCSR (0x23C)
1460 #define SPR_DBAT6L (0x23D)
1461 #define SPR_Exxx_MCAR (0x23D)
1462 #define SPR_DBAT7U (0x23E)
1463 #define SPR_BOOKE_DSRR0 (0x23E)
1464 #define SPR_DBAT7L (0x23F)
1465 #define SPR_BOOKE_DSRR1 (0x23F)
1466 #define SPR_BOOKE_SPRG8 (0x25C)
1467 #define SPR_BOOKE_SPRG9 (0x25D)
1468 #define SPR_BOOKE_MAS0 (0x270)
1469 #define SPR_BOOKE_MAS1 (0x271)
1470 #define SPR_BOOKE_MAS2 (0x272)
1471 #define SPR_BOOKE_MAS3 (0x273)
1472 #define SPR_BOOKE_MAS4 (0x274)
1473 #define SPR_BOOKE_MAS5 (0x275)
1474 #define SPR_BOOKE_MAS6 (0x276)
1475 #define SPR_BOOKE_PID1 (0x279)
1476 #define SPR_BOOKE_PID2 (0x27A)
1477 #define SPR_MPC_DPDR (0x280)
1478 #define SPR_MPC_IMMR (0x288)
1479 #define SPR_BOOKE_TLB0CFG (0x2B0)
1480 #define SPR_BOOKE_TLB1CFG (0x2B1)
1481 #define SPR_BOOKE_TLB2CFG (0x2B2)
1482 #define SPR_BOOKE_TLB3CFG (0x2B3)
1483 #define SPR_BOOKE_EPR (0x2BE)
1484 #define SPR_PERF0 (0x300)
1485 #define SPR_RCPU_MI_RBA0 (0x300)
1486 #define SPR_MPC_MI_CTR (0x300)
1487 #define SPR_PERF1 (0x301)
1488 #define SPR_RCPU_MI_RBA1 (0x301)
1489 #define SPR_PERF2 (0x302)
1490 #define SPR_RCPU_MI_RBA2 (0x302)
1491 #define SPR_MPC_MI_AP (0x302)
1492 #define SPR_PERF3 (0x303)
1493 #define SPR_620_PMC1R (0x303)
1494 #define SPR_RCPU_MI_RBA3 (0x303)
1495 #define SPR_MPC_MI_EPN (0x303)
1496 #define SPR_PERF4 (0x304)
1497 #define SPR_620_PMC2R (0x304)
1498 #define SPR_PERF5 (0x305)
1499 #define SPR_MPC_MI_TWC (0x305)
1500 #define SPR_PERF6 (0x306)
1501 #define SPR_MPC_MI_RPN (0x306)
1502 #define SPR_PERF7 (0x307)
1503 #define SPR_PERF8 (0x308)
1504 #define SPR_RCPU_L2U_RBA0 (0x308)
1505 #define SPR_MPC_MD_CTR (0x308)
1506 #define SPR_PERF9 (0x309)
1507 #define SPR_RCPU_L2U_RBA1 (0x309)
1508 #define SPR_MPC_MD_CASID (0x309)
1509 #define SPR_PERFA (0x30A)
1510 #define SPR_RCPU_L2U_RBA2 (0x30A)
1511 #define SPR_MPC_MD_AP (0x30A)
1512 #define SPR_PERFB (0x30B)
1513 #define SPR_620_MMCR0R (0x30B)
1514 #define SPR_RCPU_L2U_RBA3 (0x30B)
1515 #define SPR_MPC_MD_EPN (0x30B)
1516 #define SPR_PERFC (0x30C)
1517 #define SPR_MPC_MD_TWB (0x30C)
1518 #define SPR_PERFD (0x30D)
1519 #define SPR_MPC_MD_TWC (0x30D)
1520 #define SPR_PERFE (0x30E)
1521 #define SPR_MPC_MD_RPN (0x30E)
1522 #define SPR_PERFF (0x30F)
1523 #define SPR_MPC_MD_TW (0x30F)
1524 #define SPR_UPERF0 (0x310)
1525 #define SPR_UPERF1 (0x311)
1526 #define SPR_UPERF2 (0x312)
1527 #define SPR_UPERF3 (0x313)
1528 #define SPR_620_PMC1W (0x313)
1529 #define SPR_UPERF4 (0x314)
1530 #define SPR_620_PMC2W (0x314)
1531 #define SPR_UPERF5 (0x315)
1532 #define SPR_UPERF6 (0x316)
1533 #define SPR_UPERF7 (0x317)
1534 #define SPR_UPERF8 (0x318)
1535 #define SPR_UPERF9 (0x319)
1536 #define SPR_UPERFA (0x31A)
1537 #define SPR_UPERFB (0x31B)
1538 #define SPR_620_MMCR0W (0x31B)
1539 #define SPR_UPERFC (0x31C)
1540 #define SPR_UPERFD (0x31D)
1541 #define SPR_UPERFE (0x31E)
1542 #define SPR_UPERFF (0x31F)
1543 #define SPR_RCPU_MI_RA0 (0x320)
1544 #define SPR_MPC_MI_DBCAM (0x320)
1545 #define SPR_RCPU_MI_RA1 (0x321)
1546 #define SPR_MPC_MI_DBRAM0 (0x321)
1547 #define SPR_RCPU_MI_RA2 (0x322)
1548 #define SPR_MPC_MI_DBRAM1 (0x322)
1549 #define SPR_RCPU_MI_RA3 (0x323)
1550 #define SPR_RCPU_L2U_RA0 (0x328)
1551 #define SPR_MPC_MD_DBCAM (0x328)
1552 #define SPR_RCPU_L2U_RA1 (0x329)
1553 #define SPR_MPC_MD_DBRAM0 (0x329)
1554 #define SPR_RCPU_L2U_RA2 (0x32A)
1555 #define SPR_MPC_MD_DBRAM1 (0x32A)
1556 #define SPR_RCPU_L2U_RA3 (0x32B)
1557 #define SPR_440_INV0 (0x370)
1558 #define SPR_440_INV1 (0x371)
1559 #define SPR_440_INV2 (0x372)
1560 #define SPR_440_INV3 (0x373)
1561 #define SPR_440_ITV0 (0x374)
1562 #define SPR_440_ITV1 (0x375)
1563 #define SPR_440_ITV2 (0x376)
1564 #define SPR_440_ITV3 (0x377)
1565 #define SPR_440_CCR1 (0x378)
1566 #define SPR_DCRIPR (0x37B)
1567 #define SPR_PPR (0x380)
1568 #define SPR_750_GQR0 (0x390)
1569 #define SPR_440_DNV0 (0x390)
1570 #define SPR_750_GQR1 (0x391)
1571 #define SPR_440_DNV1 (0x391)
1572 #define SPR_750_GQR2 (0x392)
1573 #define SPR_440_DNV2 (0x392)
1574 #define SPR_750_GQR3 (0x393)
1575 #define SPR_440_DNV3 (0x393)
1576 #define SPR_750_GQR4 (0x394)
1577 #define SPR_440_DTV0 (0x394)
1578 #define SPR_750_GQR5 (0x395)
1579 #define SPR_440_DTV1 (0x395)
1580 #define SPR_750_GQR6 (0x396)
1581 #define SPR_440_DTV2 (0x396)
1582 #define SPR_750_GQR7 (0x397)
1583 #define SPR_440_DTV3 (0x397)
1584 #define SPR_750_THRM4 (0x398)
1585 #define SPR_750CL_HID2 (0x398)
1586 #define SPR_440_DVLIM (0x398)
1587 #define SPR_750_WPAR (0x399)
1588 #define SPR_440_IVLIM (0x399)
1589 #define SPR_750_DMAU (0x39A)
1590 #define SPR_750_DMAL (0x39B)
1591 #define SPR_440_RSTCFG (0x39B)
1592 #define SPR_BOOKE_DCDBTRL (0x39C)
1593 #define SPR_BOOKE_DCDBTRH (0x39D)
1594 #define SPR_BOOKE_ICDBTRL (0x39E)
1595 #define SPR_BOOKE_ICDBTRH (0x39F)
1596 #define SPR_UMMCR2 (0x3A0)
1597 #define SPR_UPMC5 (0x3A1)
1598 #define SPR_UPMC6 (0x3A2)
1599 #define SPR_UBAMR (0x3A7)
1600 #define SPR_UMMCR0 (0x3A8)
1601 #define SPR_UPMC1 (0x3A9)
1602 #define SPR_UPMC2 (0x3AA)
1603 #define SPR_USIAR (0x3AB)
1604 #define SPR_UMMCR1 (0x3AC)
1605 #define SPR_UPMC3 (0x3AD)
1606 #define SPR_UPMC4 (0x3AE)
1607 #define SPR_USDA (0x3AF)
1608 #define SPR_40x_ZPR (0x3B0)
1609 #define SPR_BOOKE_MAS7 (0x3B0)
1610 #define SPR_620_PMR0 (0x3B0)
1611 #define SPR_MMCR2 (0x3B0)
1612 #define SPR_PMC5 (0x3B1)
1613 #define SPR_40x_PID (0x3B1)
1614 #define SPR_620_PMR1 (0x3B1)
1615 #define SPR_PMC6 (0x3B2)
1616 #define SPR_440_MMUCR (0x3B2)
1617 #define SPR_620_PMR2 (0x3B2)
1618 #define SPR_4xx_CCR0 (0x3B3)
1619 #define SPR_BOOKE_EPLC (0x3B3)
1620 #define SPR_620_PMR3 (0x3B3)
1621 #define SPR_405_IAC3 (0x3B4)
1622 #define SPR_BOOKE_EPSC (0x3B4)
1623 #define SPR_620_PMR4 (0x3B4)
1624 #define SPR_405_IAC4 (0x3B5)
1625 #define SPR_620_PMR5 (0x3B5)
1626 #define SPR_405_DVC1 (0x3B6)
1627 #define SPR_620_PMR6 (0x3B6)
1628 #define SPR_405_DVC2 (0x3B7)
1629 #define SPR_620_PMR7 (0x3B7)
1630 #define SPR_BAMR (0x3B7)
1631 #define SPR_MMCR0 (0x3B8)
1632 #define SPR_620_PMR8 (0x3B8)
1633 #define SPR_PMC1 (0x3B9)
1634 #define SPR_40x_SGR (0x3B9)
1635 #define SPR_620_PMR9 (0x3B9)
1636 #define SPR_PMC2 (0x3BA)
1637 #define SPR_40x_DCWR (0x3BA)
1638 #define SPR_620_PMRA (0x3BA)
1639 #define SPR_SIAR (0x3BB)
1640 #define SPR_405_SLER (0x3BB)
1641 #define SPR_620_PMRB (0x3BB)
1642 #define SPR_MMCR1 (0x3BC)
1643 #define SPR_405_SU0R (0x3BC)
1644 #define SPR_620_PMRC (0x3BC)
1645 #define SPR_401_SKR (0x3BC)
1646 #define SPR_PMC3 (0x3BD)
1647 #define SPR_405_DBCR1 (0x3BD)
1648 #define SPR_620_PMRD (0x3BD)
1649 #define SPR_PMC4 (0x3BE)
1650 #define SPR_620_PMRE (0x3BE)
1651 #define SPR_SDA (0x3BF)
1652 #define SPR_620_PMRF (0x3BF)
1653 #define SPR_403_VTBL (0x3CC)
1654 #define SPR_403_VTBU (0x3CD)
1655 #define SPR_DMISS (0x3D0)
1656 #define SPR_DCMP (0x3D1)
1657 #define SPR_HASH1 (0x3D2)
1658 #define SPR_HASH2 (0x3D3)
1659 #define SPR_BOOKE_ICDBDR (0x3D3)
1660 #define SPR_TLBMISS (0x3D4)
1661 #define SPR_IMISS (0x3D4)
1662 #define SPR_40x_ESR (0x3D4)
1663 #define SPR_PTEHI (0x3D5)
1664 #define SPR_ICMP (0x3D5)
1665 #define SPR_40x_DEAR (0x3D5)
1666 #define SPR_PTELO (0x3D6)
1667 #define SPR_RPA (0x3D6)
1668 #define SPR_40x_EVPR (0x3D6)
1669 #define SPR_L3PM (0x3D7)
1670 #define SPR_403_CDBCR (0x3D7)
1671 #define SPR_L3ITCR0 (0x3D8)
1672 #define SPR_TCR (0x3D8)
1673 #define SPR_40x_TSR (0x3D8)
1674 #define SPR_IBR (0x3DA)
1675 #define SPR_40x_TCR (0x3DA)
1676 #define SPR_ESASRR (0x3DB)
1677 #define SPR_40x_PIT (0x3DB)
1678 #define SPR_403_TBL (0x3DC)
1679 #define SPR_403_TBU (0x3DD)
1680 #define SPR_SEBR (0x3DE)
1681 #define SPR_40x_SRR2 (0x3DE)
1682 #define SPR_SER (0x3DF)
1683 #define SPR_40x_SRR3 (0x3DF)
1684 #define SPR_L3OHCR (0x3E8)
1685 #define SPR_L3ITCR1 (0x3E9)
1686 #define SPR_L3ITCR2 (0x3EA)
1687 #define SPR_L3ITCR3 (0x3EB)
1688 #define SPR_HID0 (0x3F0)
1689 #define SPR_40x_DBSR (0x3F0)
1690 #define SPR_HID1 (0x3F1)
1691 #define SPR_IABR (0x3F2)
1692 #define SPR_40x_DBCR0 (0x3F2)
1693 #define SPR_601_HID2 (0x3F2)
1694 #define SPR_Exxx_L1CSR0 (0x3F2)
1695 #define SPR_ICTRL (0x3F3)
1696 #define SPR_HID2 (0x3F3)
1697 #define SPR_750CL_HID4 (0x3F3)
1698 #define SPR_Exxx_L1CSR1 (0x3F3)
1699 #define SPR_440_DBDR (0x3F3)
1700 #define SPR_LDSTDB (0x3F4)
1701 #define SPR_750_TDCL (0x3F4)
1702 #define SPR_40x_IAC1 (0x3F4)
1703 #define SPR_MMUCSR0 (0x3F4)
1704 #define SPR_DABR (0x3F5)
1705 #define DABR_MASK (~(target_ulong)0x7)
1706 #define SPR_Exxx_BUCSR (0x3F5)
1707 #define SPR_40x_IAC2 (0x3F5)
1708 #define SPR_601_HID5 (0x3F5)
1709 #define SPR_40x_DAC1 (0x3F6)
1710 #define SPR_MSSCR0 (0x3F6)
1711 #define SPR_970_HID5 (0x3F6)
1712 #define SPR_MSSSR0 (0x3F7)
1713 #define SPR_MSSCR1 (0x3F7)
1714 #define SPR_DABRX (0x3F7)
1715 #define SPR_40x_DAC2 (0x3F7)
1716 #define SPR_MMUCFG (0x3F7)
1717 #define SPR_LDSTCR (0x3F8)
1718 #define SPR_L2PMCR (0x3F8)
1719 #define SPR_750FX_HID2 (0x3F8)
1720 #define SPR_620_BUSCSR (0x3F8)
1721 #define SPR_Exxx_L1FINV0 (0x3F8)
1722 #define SPR_L2CR (0x3F9)
1723 #define SPR_620_L2CR (0x3F9)
1724 #define SPR_L3CR (0x3FA)
1725 #define SPR_750_TDCH (0x3FA)
1726 #define SPR_IABR2 (0x3FA)
1727 #define SPR_40x_DCCR (0x3FA)
1728 #define SPR_620_L2SR (0x3FA)
1729 #define SPR_ICTC (0x3FB)
1730 #define SPR_40x_ICCR (0x3FB)
1731 #define SPR_THRM1 (0x3FC)
1732 #define SPR_403_PBL1 (0x3FC)
1733 #define SPR_SP (0x3FD)
1734 #define SPR_THRM2 (0x3FD)
1735 #define SPR_403_PBU1 (0x3FD)
1736 #define SPR_604_HID13 (0x3FD)
1737 #define SPR_LT (0x3FE)
1738 #define SPR_THRM3 (0x3FE)
1739 #define SPR_RCPU_FPECR (0x3FE)
1740 #define SPR_403_PBL2 (0x3FE)
1741 #define SPR_PIR (0x3FF)
1742 #define SPR_403_PBU2 (0x3FF)
1743 #define SPR_601_HID15 (0x3FF)
1744 #define SPR_604_HID15 (0x3FF)
1745 #define SPR_E500_SVR (0x3FF)
1746
1747 /* Disable MAS Interrupt Updates for Hypervisor */
1748 #define EPCR_DMIUH (1 << 22)
1749 /* Disable Guest TLB Management Instructions */
1750 #define EPCR_DGTMI (1 << 23)
1751 /* Guest Interrupt Computation Mode */
1752 #define EPCR_GICM (1 << 24)
1753 /* Interrupt Computation Mode */
1754 #define EPCR_ICM (1 << 25)
1755 /* Disable Embedded Hypervisor Debug */
1756 #define EPCR_DUVD (1 << 26)
1757 /* Instruction Storage Interrupt Directed to Guest State */
1758 #define EPCR_ISIGS (1 << 27)
1759 /* Data Storage Interrupt Directed to Guest State */
1760 #define EPCR_DSIGS (1 << 28)
1761 /* Instruction TLB Error Interrupt Directed to Guest State */
1762 #define EPCR_ITLBGS (1 << 29)
1763 /* Data TLB Error Interrupt Directed to Guest State */
1764 #define EPCR_DTLBGS (1 << 30)
1765 /* External Input Interrupt Directed to Guest State */
1766 #define EPCR_EXTGS (1 << 31)
1767
1768 /*****************************************************************************/
1769 /* PowerPC Instructions types definitions */
1770 enum {
1771 PPC_NONE = 0x0000000000000000ULL,
1772 /* PowerPC base instructions set */
1773 PPC_INSNS_BASE = 0x0000000000000001ULL,
1774 /* integer operations instructions */
1775 #define PPC_INTEGER PPC_INSNS_BASE
1776 /* flow control instructions */
1777 #define PPC_FLOW PPC_INSNS_BASE
1778 /* virtual memory instructions */
1779 #define PPC_MEM PPC_INSNS_BASE
1780 /* ld/st with reservation instructions */
1781 #define PPC_RES PPC_INSNS_BASE
1782 /* spr/msr access instructions */
1783 #define PPC_MISC PPC_INSNS_BASE
1784 /* Deprecated instruction sets */
1785 /* Original POWER instruction set */
1786 PPC_POWER = 0x0000000000000002ULL,
1787 /* POWER2 instruction set extension */
1788 PPC_POWER2 = 0x0000000000000004ULL,
1789 /* Power RTC support */
1790 PPC_POWER_RTC = 0x0000000000000008ULL,
1791 /* Power-to-PowerPC bridge (601) */
1792 PPC_POWER_BR = 0x0000000000000010ULL,
1793 /* 64 bits PowerPC instruction set */
1794 PPC_64B = 0x0000000000000020ULL,
1795 /* New 64 bits extensions (PowerPC 2.0x) */
1796 PPC_64BX = 0x0000000000000040ULL,
1797 /* 64 bits hypervisor extensions */
1798 PPC_64H = 0x0000000000000080ULL,
1799 /* New wait instruction (PowerPC 2.0x) */
1800 PPC_WAIT = 0x0000000000000100ULL,
1801 /* Time base mftb instruction */
1802 PPC_MFTB = 0x0000000000000200ULL,
1803
1804 /* Fixed-point unit extensions */
1805 /* PowerPC 602 specific */
1806 PPC_602_SPEC = 0x0000000000000400ULL,
1807 /* isel instruction */
1808 PPC_ISEL = 0x0000000000000800ULL,
1809 /* popcntb instruction */
1810 PPC_POPCNTB = 0x0000000000001000ULL,
1811 /* string load / store */
1812 PPC_STRING = 0x0000000000002000ULL,
1813
1814 /* Floating-point unit extensions */
1815 /* Optional floating point instructions */
1816 PPC_FLOAT = 0x0000000000010000ULL,
1817 /* New floating-point extensions (PowerPC 2.0x) */
1818 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1819 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1820 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1821 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1822 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1823 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1824 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1825
1826 /* Vector/SIMD extensions */
1827 /* Altivec support */
1828 PPC_ALTIVEC = 0x0000000001000000ULL,
1829 /* PowerPC 2.03 SPE extension */
1830 PPC_SPE = 0x0000000002000000ULL,
1831 /* PowerPC 2.03 SPE single-precision floating-point extension */
1832 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1833 /* PowerPC 2.03 SPE double-precision floating-point extension */
1834 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1835
1836 /* Optional memory control instructions */
1837 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1838 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1839 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1840 /* sync instruction */
1841 PPC_MEM_SYNC = 0x0000000080000000ULL,
1842 /* eieio instruction */
1843 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1844
1845 /* Cache control instructions */
1846 PPC_CACHE = 0x0000000200000000ULL,
1847 /* icbi instruction */
1848 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1849 /* dcbz instruction */
1850 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1851 /* dcba instruction */
1852 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1853 /* Freescale cache locking instructions */
1854 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1855
1856 /* MMU related extensions */
1857 /* external control instructions */
1858 PPC_EXTERN = 0x0000010000000000ULL,
1859 /* segment register access instructions */
1860 PPC_SEGMENT = 0x0000020000000000ULL,
1861 /* PowerPC 6xx TLB management instructions */
1862 PPC_6xx_TLB = 0x0000040000000000ULL,
1863 /* PowerPC 74xx TLB management instructions */
1864 PPC_74xx_TLB = 0x0000080000000000ULL,
1865 /* PowerPC 40x TLB management instructions */
1866 PPC_40x_TLB = 0x0000100000000000ULL,
1867 /* segment register access instructions for PowerPC 64 "bridge" */
1868 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1869 /* SLB management */
1870 PPC_SLBI = 0x0000400000000000ULL,
1871
1872 /* Embedded PowerPC dedicated instructions */
1873 PPC_WRTEE = 0x0001000000000000ULL,
1874 /* PowerPC 40x exception model */
1875 PPC_40x_EXCP = 0x0002000000000000ULL,
1876 /* PowerPC 405 Mac instructions */
1877 PPC_405_MAC = 0x0004000000000000ULL,
1878 /* PowerPC 440 specific instructions */
1879 PPC_440_SPEC = 0x0008000000000000ULL,
1880 /* BookE (embedded) PowerPC specification */
1881 PPC_BOOKE = 0x0010000000000000ULL,
1882 /* mfapidi instruction */
1883 PPC_MFAPIDI = 0x0020000000000000ULL,
1884 /* tlbiva instruction */
1885 PPC_TLBIVA = 0x0040000000000000ULL,
1886 /* tlbivax instruction */
1887 PPC_TLBIVAX = 0x0080000000000000ULL,
1888 /* PowerPC 4xx dedicated instructions */
1889 PPC_4xx_COMMON = 0x0100000000000000ULL,
1890 /* PowerPC 40x ibct instructions */
1891 PPC_40x_ICBT = 0x0200000000000000ULL,
1892 /* rfmci is not implemented in all BookE PowerPC */
1893 PPC_RFMCI = 0x0400000000000000ULL,
1894 /* rfdi instruction */
1895 PPC_RFDI = 0x0800000000000000ULL,
1896 /* DCR accesses */
1897 PPC_DCR = 0x1000000000000000ULL,
1898 /* DCR extended accesse */
1899 PPC_DCRX = 0x2000000000000000ULL,
1900 /* user-mode DCR access, implemented in PowerPC 460 */
1901 PPC_DCRUX = 0x4000000000000000ULL,
1902 /* popcntw and popcntd instructions */
1903 PPC_POPCNTWD = 0x8000000000000000ULL,
1904
1905 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1906 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1907 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1908 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1909 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1910 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1911 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1912 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1913 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1914 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1915 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1916 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1917 | PPC_CACHE | PPC_CACHE_ICBI \
1918 | PPC_CACHE_DCBZ \
1919 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1920 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1921 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1922 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1923 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1924 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1925 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1926 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1927 | PPC_POPCNTWD)
1928
1929 /* extended type values */
1930
1931 /* BookE 2.06 PowerPC specification */
1932 PPC2_BOOKE206 = 0x0000000000000001ULL,
1933 /* VSX (extensions to Altivec / VMX) */
1934 PPC2_VSX = 0x0000000000000002ULL,
1935 /* Decimal Floating Point (DFP) */
1936 PPC2_DFP = 0x0000000000000004ULL,
1937 /* Embedded.Processor Control */
1938 PPC2_PRCNTL = 0x0000000000000008ULL,
1939 /* Byte-reversed, indexed, double-word load and store */
1940 PPC2_DBRX = 0x0000000000000010ULL,
1941
1942 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX)
1943 };
1944
1945 /*****************************************************************************/
1946 /* Memory access type :
1947 * may be needed for precise access rights control and precise exceptions.
1948 */
1949 enum {
1950 /* 1 bit to define user level / supervisor access */
1951 ACCESS_USER = 0x00,
1952 ACCESS_SUPER = 0x01,
1953 /* Type of instruction that generated the access */
1954 ACCESS_CODE = 0x10, /* Code fetch access */
1955 ACCESS_INT = 0x20, /* Integer load/store access */
1956 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1957 ACCESS_RES = 0x40, /* load/store with reservation */
1958 ACCESS_EXT = 0x50, /* external access */
1959 ACCESS_CACHE = 0x60, /* Cache manipulation */
1960 };
1961
1962 /* Hardware interruption sources:
1963 * all those exception can be raised simulteaneously
1964 */
1965 /* Input pins definitions */
1966 enum {
1967 /* 6xx bus input pins */
1968 PPC6xx_INPUT_HRESET = 0,
1969 PPC6xx_INPUT_SRESET = 1,
1970 PPC6xx_INPUT_CKSTP_IN = 2,
1971 PPC6xx_INPUT_MCP = 3,
1972 PPC6xx_INPUT_SMI = 4,
1973 PPC6xx_INPUT_INT = 5,
1974 PPC6xx_INPUT_TBEN = 6,
1975 PPC6xx_INPUT_WAKEUP = 7,
1976 PPC6xx_INPUT_NB,
1977 };
1978
1979 enum {
1980 /* Embedded PowerPC input pins */
1981 PPCBookE_INPUT_HRESET = 0,
1982 PPCBookE_INPUT_SRESET = 1,
1983 PPCBookE_INPUT_CKSTP_IN = 2,
1984 PPCBookE_INPUT_MCP = 3,
1985 PPCBookE_INPUT_SMI = 4,
1986 PPCBookE_INPUT_INT = 5,
1987 PPCBookE_INPUT_CINT = 6,
1988 PPCBookE_INPUT_NB,
1989 };
1990
1991 enum {
1992 /* PowerPC E500 input pins */
1993 PPCE500_INPUT_RESET_CORE = 0,
1994 PPCE500_INPUT_MCK = 1,
1995 PPCE500_INPUT_CINT = 3,
1996 PPCE500_INPUT_INT = 4,
1997 PPCE500_INPUT_DEBUG = 6,
1998 PPCE500_INPUT_NB,
1999 };
2000
2001 enum {
2002 /* PowerPC 40x input pins */
2003 PPC40x_INPUT_RESET_CORE = 0,
2004 PPC40x_INPUT_RESET_CHIP = 1,
2005 PPC40x_INPUT_RESET_SYS = 2,
2006 PPC40x_INPUT_CINT = 3,
2007 PPC40x_INPUT_INT = 4,
2008 PPC40x_INPUT_HALT = 5,
2009 PPC40x_INPUT_DEBUG = 6,
2010 PPC40x_INPUT_NB,
2011 };
2012
2013 enum {
2014 /* RCPU input pins */
2015 PPCRCPU_INPUT_PORESET = 0,
2016 PPCRCPU_INPUT_HRESET = 1,
2017 PPCRCPU_INPUT_SRESET = 2,
2018 PPCRCPU_INPUT_IRQ0 = 3,
2019 PPCRCPU_INPUT_IRQ1 = 4,
2020 PPCRCPU_INPUT_IRQ2 = 5,
2021 PPCRCPU_INPUT_IRQ3 = 6,
2022 PPCRCPU_INPUT_IRQ4 = 7,
2023 PPCRCPU_INPUT_IRQ5 = 8,
2024 PPCRCPU_INPUT_IRQ6 = 9,
2025 PPCRCPU_INPUT_IRQ7 = 10,
2026 PPCRCPU_INPUT_NB,
2027 };
2028
2029 #if defined(TARGET_PPC64)
2030 enum {
2031 /* PowerPC 970 input pins */
2032 PPC970_INPUT_HRESET = 0,
2033 PPC970_INPUT_SRESET = 1,
2034 PPC970_INPUT_CKSTP = 2,
2035 PPC970_INPUT_TBEN = 3,
2036 PPC970_INPUT_MCP = 4,
2037 PPC970_INPUT_INT = 5,
2038 PPC970_INPUT_THINT = 6,
2039 PPC970_INPUT_NB,
2040 };
2041
2042 enum {
2043 /* POWER7 input pins */
2044 POWER7_INPUT_INT = 0,
2045 /* POWER7 probably has other inputs, but we don't care about them
2046 * for any existing machine. We can wire these up when we need
2047 * them */
2048 POWER7_INPUT_NB,
2049 };
2050 #endif
2051
2052 /* Hardware exceptions definitions */
2053 enum {
2054 /* External hardware exception sources */
2055 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2056 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2057 PPC_INTERRUPT_MCK, /* Machine check exception */
2058 PPC_INTERRUPT_EXT, /* External interrupt */
2059 PPC_INTERRUPT_SMI, /* System management interrupt */
2060 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2061 PPC_INTERRUPT_DEBUG, /* External debug exception */
2062 PPC_INTERRUPT_THERM, /* Thermal exception */
2063 /* Internal hardware exception sources */
2064 PPC_INTERRUPT_DECR, /* Decrementer exception */
2065 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2066 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2067 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2068 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2069 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2070 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2071 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2072 };
2073
2074 /* CPU should be reset next, restart from scratch afterwards */
2075 #define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0
2076
2077 /*****************************************************************************/
2078
2079 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2080 {
2081 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2082 }
2083
2084 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2085 {
2086 env->so = (xer >> XER_SO) & 1;
2087 env->ov = (xer >> XER_OV) & 1;
2088 env->ca = (xer >> XER_CA) & 1;
2089 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2090 }
2091
2092 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2093 target_ulong *cs_base, int *flags)
2094 {
2095 *pc = env->nip;
2096 *cs_base = 0;
2097 *flags = env->hflags;
2098 }
2099
2100 static inline void cpu_set_tls(CPUPPCState *env, target_ulong newtls)
2101 {
2102 #if defined(TARGET_PPC64)
2103 /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
2104 binaries on PPC64 yet. */
2105 env->gpr[13] = newtls;
2106 #else
2107 env->gpr[2] = newtls;
2108 #endif
2109 }
2110
2111 #if !defined(CONFIG_USER_ONLY)
2112 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2113 {
2114 uintptr_t tlbml = (uintptr_t)tlbm;
2115 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2116
2117 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2118 }
2119
2120 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2121 {
2122 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2123 int r = tlbncfg & TLBnCFG_N_ENTRY;
2124 return r;
2125 }
2126
2127 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2128 {
2129 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2130 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2131 return r;
2132 }
2133
2134 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2135 {
2136 int id = booke206_tlbm_id(env, tlbm);
2137 int end = 0;
2138 int i;
2139
2140 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2141 end += booke206_tlb_size(env, i);
2142 if (id < end) {
2143 return i;
2144 }
2145 }
2146
2147 cpu_abort(env, "Unknown TLBe: %d\n", id);
2148 return 0;
2149 }
2150
2151 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2152 {
2153 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2154 int tlbid = booke206_tlbm_id(env, tlb);
2155 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2156 }
2157
2158 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2159 target_ulong ea, int way)
2160 {
2161 int r;
2162 uint32_t ways = booke206_tlb_ways(env, tlbn);
2163 int ways_bits = ffs(ways) - 1;
2164 int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2165 int i;
2166
2167 way &= ways - 1;
2168 ea >>= MAS2_EPN_SHIFT;
2169 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2170 r = (ea << ways_bits) | way;
2171
2172 if (r >= booke206_tlb_size(env, tlbn)) {
2173 return NULL;
2174 }
2175
2176 /* bump up to tlbn index */
2177 for (i = 0; i < tlbn; i++) {
2178 r += booke206_tlb_size(env, i);
2179 }
2180
2181 return &env->tlb.tlbm[r];
2182 }
2183
2184 /* returns bitmap of supported page sizes for a given TLB */
2185 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2186 {
2187 bool mav2 = false;
2188 uint32_t ret = 0;
2189
2190 if (mav2) {
2191 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2192 } else {
2193 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2194 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2195 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2196 int i;
2197 for (i = min; i <= max; i++) {
2198 ret |= (1 << (i << 1));
2199 }
2200 }
2201
2202 return ret;
2203 }
2204
2205 #endif
2206
2207 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2208 {
2209 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2210 return msr & (1ULL << MSR_CM);
2211 }
2212
2213 return msr & (1ULL << MSR_SF);
2214 }
2215
2216 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2217
2218 static inline bool cpu_has_work(CPUState *cpu)
2219 {
2220 CPUPPCState *env = &POWERPC_CPU(cpu)->env;
2221
2222 return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
2223 }
2224
2225 #include "exec/exec-all.h"
2226
2227 static inline void cpu_pc_from_tb(CPUPPCState *env, TranslationBlock *tb)
2228 {
2229 env->nip = tb->pc;
2230 }
2231
2232 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2233
2234 #endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing