target-ppc/fpu_helper.c

   1 /*
   2  *  PowerPC floating point and SPE emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "helper.h"
  21
  22 /*****************************************************************************/
  23 /* Floating point operations helpers */
  24 uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg)
  25 {
  26     CPU_FloatU f;
  27     CPU_DoubleU d;
  28
  29     f.l = arg;
  30     d.d = float32_to_float64(f.f, &env->fp_status);
  31     return d.ll;
  32 }
  33
  34 uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg)
  35 {
  36     CPU_FloatU f;
  37     CPU_DoubleU d;
  38
  39     d.ll = arg;
  40     f.f = float64_to_float32(d.d, &env->fp_status);
  41     return f.l;
  42 }
  43
  44 static inline int isden(float64 d)
  45 {
  46     CPU_DoubleU u;
  47
  48     u.d = d;
  49
  50     return ((u.ll >> 52) & 0x7FF) == 0;
  51 }
  52
  53 uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf)
  54 {
  55     CPU_DoubleU farg;
  56     int isneg;
  57     int ret;
  58
  59     farg.ll = arg;
  60     isneg = float64_is_neg(farg.d);
  61     if (unlikely(float64_is_any_nan(farg.d))) {
  62         if (float64_is_signaling_nan(farg.d)) {
  63             /* Signaling NaN: flags are undefined */
  64             ret = 0x00;
  65         } else {
  66             /* Quiet NaN */
  67             ret = 0x11;
  68         }
  69     } else if (unlikely(float64_is_infinity(farg.d))) {
  70         /* +/- infinity */
  71         if (isneg) {
  72             ret = 0x09;
  73         } else {
  74             ret = 0x05;
  75         }
  76     } else {
  77         if (float64_is_zero(farg.d)) {
  78             /* +/- zero */
  79             if (isneg) {
  80                 ret = 0x12;
  81             } else {
  82                 ret = 0x02;
  83             }
  84         } else {
  85             if (isden(farg.d)) {
  86                 /* Denormalized numbers */
  87                 ret = 0x10;
  88             } else {
  89                 /* Normalized numbers */
  90                 ret = 0x00;
  91             }
  92             if (isneg) {
  93                 ret |= 0x08;
  94             } else {
  95                 ret |= 0x04;
  96             }
  97         }
  98     }
  99     if (set_fprf) {
 100         /* We update FPSCR_FPRF */
 101         env->fpscr &= ~(0x1F << FPSCR_FPRF);
 102         env->fpscr |= ret << FPSCR_FPRF;
 103     }
 104     /* We just need fpcc to update Rc1 */
 105     return ret & 0xF;
 106 }
 107
 108 /* Floating-point invalid operations exception */
 109 static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op)
 110 {
 111     uint64_t ret = 0;
 112     int ve;
 113
 114     ve = fpscr_ve;
 115     switch (op) {
 116     case POWERPC_EXCP_FP_VXSNAN:
 117         env->fpscr |= 1 << FPSCR_VXSNAN;
 118         break;
 119     case POWERPC_EXCP_FP_VXSOFT:
 120         env->fpscr |= 1 << FPSCR_VXSOFT;
 121         break;
 122     case POWERPC_EXCP_FP_VXISI:
 123         /* Magnitude subtraction of infinities */
 124         env->fpscr |= 1 << FPSCR_VXISI;
 125         goto update_arith;
 126     case POWERPC_EXCP_FP_VXIDI:
 127         /* Division of infinity by infinity */
 128         env->fpscr |= 1 << FPSCR_VXIDI;
 129         goto update_arith;
 130     case POWERPC_EXCP_FP_VXZDZ:
 131         /* Division of zero by zero */
 132         env->fpscr |= 1 << FPSCR_VXZDZ;
 133         goto update_arith;
 134     case POWERPC_EXCP_FP_VXIMZ:
 135         /* Multiplication of zero by infinity */
 136         env->fpscr |= 1 << FPSCR_VXIMZ;
 137         goto update_arith;
 138     case POWERPC_EXCP_FP_VXVC:
 139         /* Ordered comparison of NaN */
 140         env->fpscr |= 1 << FPSCR_VXVC;
 141         env->fpscr &= ~(0xF << FPSCR_FPCC);
 142         env->fpscr |= 0x11 << FPSCR_FPCC;
 143         /* We must update the target FPR before raising the exception */
 144         if (ve != 0) {
 145             env->exception_index = POWERPC_EXCP_PROGRAM;
 146             env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
 147             /* Update the floating-point enabled exception summary */
 148             env->fpscr |= 1 << FPSCR_FEX;
 149             /* Exception is differed */
 150             ve = 0;
 151         }
 152         break;
 153     case POWERPC_EXCP_FP_VXSQRT:
 154         /* Square root of a negative number */
 155         env->fpscr |= 1 << FPSCR_VXSQRT;
 156     update_arith:
 157         env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
 158         if (ve == 0) {
 159             /* Set the result to quiet NaN */
 160             ret = 0x7FF8000000000000ULL;
 161             env->fpscr &= ~(0xF << FPSCR_FPCC);
 162             env->fpscr |= 0x11 << FPSCR_FPCC;
 163         }
 164         break;
 165     case POWERPC_EXCP_FP_VXCVI:
 166         /* Invalid conversion */
 167         env->fpscr |= 1 << FPSCR_VXCVI;
 168         env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
 169         if (ve == 0) {
 170             /* Set the result to quiet NaN */
 171             ret = 0x7FF8000000000000ULL;
 172             env->fpscr &= ~(0xF << FPSCR_FPCC);
 173             env->fpscr |= 0x11 << FPSCR_FPCC;
 174         }
 175         break;
 176     }
 177     /* Update the floating-point invalid operation summary */
 178     env->fpscr |= 1 << FPSCR_VX;
 179     /* Update the floating-point exception summary */
 180     env->fpscr |= 1 << FPSCR_FX;
 181     if (ve != 0) {
 182         /* Update the floating-point enabled exception summary */
 183         env->fpscr |= 1 << FPSCR_FEX;
 184         if (msr_fe0 != 0 || msr_fe1 != 0) {
 185             helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 186                                        POWERPC_EXCP_FP | op);
 187         }
 188     }
 189     return ret;
 190 }
 191
 192 static inline void float_zero_divide_excp(CPUPPCState *env)
 193 {
 194     env->fpscr |= 1 << FPSCR_ZX;
 195     env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
 196     /* Update the floating-point exception summary */
 197     env->fpscr |= 1 << FPSCR_FX;
 198     if (fpscr_ze != 0) {
 199         /* Update the floating-point enabled exception summary */
 200         env->fpscr |= 1 << FPSCR_FEX;
 201         if (msr_fe0 != 0 || msr_fe1 != 0) {
 202             helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 203                                        POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
 204         }
 205     }
 206 }
 207
 208 static inline void float_overflow_excp(CPUPPCState *env)
 209 {
 210     env->fpscr |= 1 << FPSCR_OX;
 211     /* Update the floating-point exception summary */
 212     env->fpscr |= 1 << FPSCR_FX;
 213     if (fpscr_oe != 0) {
 214         /* XXX: should adjust the result */
 215         /* Update the floating-point enabled exception summary */
 216         env->fpscr |= 1 << FPSCR_FEX;
 217         /* We must update the target FPR before raising the exception */
 218         env->exception_index = POWERPC_EXCP_PROGRAM;
 219         env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
 220     } else {
 221         env->fpscr |= 1 << FPSCR_XX;
 222         env->fpscr |= 1 << FPSCR_FI;
 223     }
 224 }
 225
 226 static inline void float_underflow_excp(CPUPPCState *env)
 227 {
 228     env->fpscr |= 1 << FPSCR_UX;
 229     /* Update the floating-point exception summary */
 230     env->fpscr |= 1 << FPSCR_FX;
 231     if (fpscr_ue != 0) {
 232         /* XXX: should adjust the result */
 233         /* Update the floating-point enabled exception summary */
 234         env->fpscr |= 1 << FPSCR_FEX;
 235         /* We must update the target FPR before raising the exception */
 236         env->exception_index = POWERPC_EXCP_PROGRAM;
 237         env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
 238     }
 239 }
 240
 241 static inline void float_inexact_excp(CPUPPCState *env)
 242 {
 243     env->fpscr |= 1 << FPSCR_XX;
 244     /* Update the floating-point exception summary */
 245     env->fpscr |= 1 << FPSCR_FX;
 246     if (fpscr_xe != 0) {
 247         /* Update the floating-point enabled exception summary */
 248         env->fpscr |= 1 << FPSCR_FEX;
 249         /* We must update the target FPR before raising the exception */
 250         env->exception_index = POWERPC_EXCP_PROGRAM;
 251         env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
 252     }
 253 }
 254
 255 static inline void fpscr_set_rounding_mode(CPUPPCState *env)
 256 {
 257     int rnd_type;
 258
 259     /* Set rounding mode */
 260     switch (fpscr_rn) {
 261     case 0:
 262         /* Best approximation (round to nearest) */
 263         rnd_type = float_round_nearest_even;
 264         break;
 265     case 1:
 266         /* Smaller magnitude (round toward zero) */
 267         rnd_type = float_round_to_zero;
 268         break;
 269     case 2:
 270         /* Round toward +infinite */
 271         rnd_type = float_round_up;
 272         break;
 273     default:
 274     case 3:
 275         /* Round toward -infinite */
 276         rnd_type = float_round_down;
 277         break;
 278     }
 279     set_float_rounding_mode(rnd_type, &env->fp_status);
 280 }
 281
 282 void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
 283 {
 284     int prev;
 285
 286     prev = (env->fpscr >> bit) & 1;
 287     env->fpscr &= ~(1 << bit);
 288     if (prev == 1) {
 289         switch (bit) {
 290         case FPSCR_RN1:
 291         case FPSCR_RN:
 292             fpscr_set_rounding_mode(env);
 293             break;
 294         default:
 295             break;
 296         }
 297     }
 298 }
 299
 300 void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
 301 {
 302     int prev;
 303
 304     prev = (env->fpscr >> bit) & 1;
 305     env->fpscr |= 1 << bit;
 306     if (prev == 0) {
 307         switch (bit) {
 308         case FPSCR_VX:
 309             env->fpscr |= 1 << FPSCR_FX;
 310             if (fpscr_ve) {
 311                 goto raise_ve;
 312             }
 313             break;
 314         case FPSCR_OX:
 315             env->fpscr |= 1 << FPSCR_FX;
 316             if (fpscr_oe) {
 317                 goto raise_oe;
 318             }
 319             break;
 320         case FPSCR_UX:
 321             env->fpscr |= 1 << FPSCR_FX;
 322             if (fpscr_ue) {
 323                 goto raise_ue;
 324             }
 325             break;
 326         case FPSCR_ZX:
 327             env->fpscr |= 1 << FPSCR_FX;
 328             if (fpscr_ze) {
 329                 goto raise_ze;
 330             }
 331             break;
 332         case FPSCR_XX:
 333             env->fpscr |= 1 << FPSCR_FX;
 334             if (fpscr_xe) {
 335                 goto raise_xe;
 336             }
 337             break;
 338         case FPSCR_VXSNAN:
 339         case FPSCR_VXISI:
 340         case FPSCR_VXIDI:
 341         case FPSCR_VXZDZ:
 342         case FPSCR_VXIMZ:
 343         case FPSCR_VXVC:
 344         case FPSCR_VXSOFT:
 345         case FPSCR_VXSQRT:
 346         case FPSCR_VXCVI:
 347             env->fpscr |= 1 << FPSCR_VX;
 348             env->fpscr |= 1 << FPSCR_FX;
 349             if (fpscr_ve != 0) {
 350                 goto raise_ve;
 351             }
 352             break;
 353         case FPSCR_VE:
 354             if (fpscr_vx != 0) {
 355             raise_ve:
 356                 env->error_code = POWERPC_EXCP_FP;
 357                 if (fpscr_vxsnan) {
 358                     env->error_code |= POWERPC_EXCP_FP_VXSNAN;
 359                 }
 360                 if (fpscr_vxisi) {
 361                     env->error_code |= POWERPC_EXCP_FP_VXISI;
 362                 }
 363                 if (fpscr_vxidi) {
 364                     env->error_code |= POWERPC_EXCP_FP_VXIDI;
 365                 }
 366                 if (fpscr_vxzdz) {
 367                     env->error_code |= POWERPC_EXCP_FP_VXZDZ;
 368                 }
 369                 if (fpscr_vximz) {
 370                     env->error_code |= POWERPC_EXCP_FP_VXIMZ;
 371                 }
 372                 if (fpscr_vxvc) {
 373                     env->error_code |= POWERPC_EXCP_FP_VXVC;
 374                 }
 375                 if (fpscr_vxsoft) {
 376                     env->error_code |= POWERPC_EXCP_FP_VXSOFT;
 377                 }
 378                 if (fpscr_vxsqrt) {
 379                     env->error_code |= POWERPC_EXCP_FP_VXSQRT;
 380                 }
 381                 if (fpscr_vxcvi) {
 382                     env->error_code |= POWERPC_EXCP_FP_VXCVI;
 383                 }
 384                 goto raise_excp;
 385             }
 386             break;
 387         case FPSCR_OE:
 388             if (fpscr_ox != 0) {
 389             raise_oe:
 390                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
 391                 goto raise_excp;
 392             }
 393             break;
 394         case FPSCR_UE:
 395             if (fpscr_ux != 0) {
 396             raise_ue:
 397                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
 398                 goto raise_excp;
 399             }
 400             break;
 401         case FPSCR_ZE:
 402             if (fpscr_zx != 0) {
 403             raise_ze:
 404                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
 405                 goto raise_excp;
 406             }
 407             break;
 408         case FPSCR_XE:
 409             if (fpscr_xx != 0) {
 410             raise_xe:
 411                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
 412                 goto raise_excp;
 413             }
 414             break;
 415         case FPSCR_RN1:
 416         case FPSCR_RN:
 417             fpscr_set_rounding_mode(env);
 418             break;
 419         default:
 420             break;
 421         raise_excp:
 422             /* Update the floating-point enabled exception summary */
 423             env->fpscr |= 1 << FPSCR_FEX;
 424             /* We have to update Rc1 before raising the exception */
 425             env->exception_index = POWERPC_EXCP_PROGRAM;
 426             break;
 427         }
 428     }
 429 }
 430
 431 void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
 432 {
 433     /*
 434      * We use only the 32 LSB of the incoming fpr
 435      */
 436     uint32_t prev, new;
 437     int i;
 438
 439     prev = env->fpscr;
 440     new = (uint32_t)arg;
 441     new &= ~0x60000000;
 442     new |= prev & 0x60000000;
 443     for (i = 0; i < 8; i++) {
 444         if (mask & (1 << i)) {
 445             env->fpscr &= ~(0xF << (4 * i));
 446             env->fpscr |= new & (0xF << (4 * i));
 447         }
 448     }
 449     /* Update VX and FEX */
 450     if (fpscr_ix != 0) {
 451         env->fpscr |= 1 << FPSCR_VX;
 452     } else {
 453         env->fpscr &= ~(1 << FPSCR_VX);
 454     }
 455     if ((fpscr_ex & fpscr_eex) != 0) {
 456         env->fpscr |= 1 << FPSCR_FEX;
 457         env->exception_index = POWERPC_EXCP_PROGRAM;
 458         /* XXX: we should compute it properly */
 459         env->error_code = POWERPC_EXCP_FP;
 460     } else {
 461         env->fpscr &= ~(1 << FPSCR_FEX);
 462     }
 463     fpscr_set_rounding_mode(env);
 464 }
 465
 466 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
 467 {
 468     helper_store_fpscr(env, arg, mask);
 469 }
 470
 471 void helper_float_check_status(CPUPPCState *env)
 472 {
 473     if (env->exception_index == POWERPC_EXCP_PROGRAM &&
 474         (env->error_code & POWERPC_EXCP_FP)) {
 475         /* Differred floating-point exception after target FPR update */
 476         if (msr_fe0 != 0 || msr_fe1 != 0) {
 477             helper_raise_exception_err(env, env->exception_index,
 478                                        env->error_code);
 479         }
 480     } else {
 481         int status = get_float_exception_flags(&env->fp_status);
 482         if (status & float_flag_divbyzero) {
 483             float_zero_divide_excp(env);
 484         } else if (status & float_flag_overflow) {
 485             float_overflow_excp(env);
 486         } else if (status & float_flag_underflow) {
 487             float_underflow_excp(env);
 488         } else if (status & float_flag_inexact) {
 489             float_inexact_excp(env);
 490         }
 491     }
 492 }
 493
 494 void helper_reset_fpstatus(CPUPPCState *env)
 495 {
 496     set_float_exception_flags(0, &env->fp_status);
 497 }
 498
 499 /* fadd - fadd. */
 500 uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 501 {
 502     CPU_DoubleU farg1, farg2;
 503
 504     farg1.ll = arg1;
 505     farg2.ll = arg2;
 506
 507     if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
 508                  float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
 509         /* Magnitude subtraction of infinities */
 510         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
 511     } else {
 512         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 513                      float64_is_signaling_nan(farg2.d))) {
 514             /* sNaN addition */
 515             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
 516         }
 517         farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
 518     }
 519
 520     return farg1.ll;
 521 }
 522
 523 /* fsub - fsub. */
 524 uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 525 {
 526     CPU_DoubleU farg1, farg2;
 527
 528     farg1.ll = arg1;
 529     farg2.ll = arg2;
 530
 531     if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
 532                  float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
 533         /* Magnitude subtraction of infinities */
 534         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
 535     } else {
 536         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 537                      float64_is_signaling_nan(farg2.d))) {
 538             /* sNaN subtraction */
 539             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
 540         }
 541         farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
 542     }
 543
 544     return farg1.ll;
 545 }
 546
 547 /* fmul - fmul. */
 548 uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 549 {
 550     CPU_DoubleU farg1, farg2;
 551
 552     farg1.ll = arg1;
 553     farg2.ll = arg2;
 554
 555     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 556                  (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
 557         /* Multiplication of zero by infinity */
 558         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ);
 559     } else {
 560         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 561                      float64_is_signaling_nan(farg2.d))) {
 562             /* sNaN multiplication */
 563             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
 564         }
 565         farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
 566     }
 567
 568     return farg1.ll;
 569 }
 570
 571 /* fdiv - fdiv. */
 572 uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 573 {
 574     CPU_DoubleU farg1, farg2;
 575
 576     farg1.ll = arg1;
 577     farg2.ll = arg2;
 578
 579     if (unlikely(float64_is_infinity(farg1.d) &&
 580                  float64_is_infinity(farg2.d))) {
 581         /* Division of infinity by infinity */
 582         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI);
 583     } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
 584         /* Division of zero by zero */
 585         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ);
 586     } else {
 587         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 588                      float64_is_signaling_nan(farg2.d))) {
 589             /* sNaN division */
 590             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
 591         }
 592         farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
 593     }
 594
 595     return farg1.ll;
 596 }
 597
 598 /* fabs */
 599 uint64_t helper_fabs(CPUPPCState *env, uint64_t arg)
 600 {
 601     CPU_DoubleU farg;
 602
 603     farg.ll = arg;
 604     farg.d = float64_abs(farg.d);
 605     return farg.ll;
 606 }
 607
 608 /* fnabs */
 609 uint64_t helper_fnabs(CPUPPCState *env, uint64_t arg)
 610 {
 611     CPU_DoubleU farg;
 612
 613     farg.ll = arg;
 614     farg.d = float64_abs(farg.d);
 615     farg.d = float64_chs(farg.d);
 616     return farg.ll;
 617 }
 618
 619 /* fneg */
 620 uint64_t helper_fneg(CPUPPCState *env, uint64_t arg)
 621 {
 622     CPU_DoubleU farg;
 623
 624     farg.ll = arg;
 625     farg.d = float64_chs(farg.d);
 626     return farg.ll;
 627 }
 628
 629 /* fctiw - fctiw. */
 630 uint64_t helper_fctiw(CPUPPCState *env, uint64_t arg)
 631 {
 632     CPU_DoubleU farg;
 633
 634     farg.ll = arg;
 635
 636     if (unlikely(float64_is_signaling_nan(farg.d))) {
 637         /* sNaN conversion */
 638         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
 639                                         POWERPC_EXCP_FP_VXCVI);
 640     } else if (unlikely(float64_is_quiet_nan(farg.d) ||
 641                         float64_is_infinity(farg.d))) {
 642         /* qNan / infinity conversion */
 643         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI);
 644     } else {
 645         farg.ll = float64_to_int32(farg.d, &env->fp_status);
 646         /* XXX: higher bits are not supposed to be significant.
 647          *     to make tests easier, return the same as a real PowerPC 750
 648          */
 649         farg.ll |= 0xFFF80000ULL << 32;
 650     }
 651     return farg.ll;
 652 }
 653
 654 /* fctiwz - fctiwz. */
 655 uint64_t helper_fctiwz(CPUPPCState *env, uint64_t arg)
 656 {
 657     CPU_DoubleU farg;
 658
 659     farg.ll = arg;
 660
 661     if (unlikely(float64_is_signaling_nan(farg.d))) {
 662         /* sNaN conversion */
 663         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
 664                                         POWERPC_EXCP_FP_VXCVI);
 665     } else if (unlikely(float64_is_quiet_nan(farg.d) ||
 666                         float64_is_infinity(farg.d))) {
 667         /* qNan / infinity conversion */
 668         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI);
 669     } else {
 670         farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
 671         /* XXX: higher bits are not supposed to be significant.
 672          *     to make tests easier, return the same as a real PowerPC 750
 673          */
 674         farg.ll |= 0xFFF80000ULL << 32;
 675     }
 676     return farg.ll;
 677 }
 678
 679 #if defined(TARGET_PPC64)
 680 /* fcfid - fcfid. */
 681 uint64_t helper_fcfid(CPUPPCState *env, uint64_t arg)
 682 {
 683     CPU_DoubleU farg;
 684
 685     farg.d = int64_to_float64(arg, &env->fp_status);
 686     return farg.ll;
 687 }
 688
 689 /* fctid - fctid. */
 690 uint64_t helper_fctid(CPUPPCState *env, uint64_t arg)
 691 {
 692     CPU_DoubleU farg;
 693
 694     farg.ll = arg;
 695
 696     if (unlikely(float64_is_signaling_nan(farg.d))) {
 697         /* sNaN conversion */
 698         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
 699                                         POWERPC_EXCP_FP_VXCVI);
 700     } else if (unlikely(float64_is_quiet_nan(farg.d) ||
 701                         float64_is_infinity(farg.d))) {
 702         /* qNan / infinity conversion */
 703         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI);
 704     } else {
 705         farg.ll = float64_to_int64(farg.d, &env->fp_status);
 706     }
 707     return farg.ll;
 708 }
 709
 710 /* fctidz - fctidz. */
 711 uint64_t helper_fctidz(CPUPPCState *env, uint64_t arg)
 712 {
 713     CPU_DoubleU farg;
 714
 715     farg.ll = arg;
 716
 717     if (unlikely(float64_is_signaling_nan(farg.d))) {
 718         /* sNaN conversion */
 719         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
 720                                         POWERPC_EXCP_FP_VXCVI);
 721     } else if (unlikely(float64_is_quiet_nan(farg.d) ||
 722                         float64_is_infinity(farg.d))) {
 723         /* qNan / infinity conversion */
 724         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI);
 725     } else {
 726         farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
 727     }
 728     return farg.ll;
 729 }
 730
 731 #endif
 732
 733 static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
 734                               int rounding_mode)
 735 {
 736     CPU_DoubleU farg;
 737
 738     farg.ll = arg;
 739
 740     if (unlikely(float64_is_signaling_nan(farg.d))) {
 741         /* sNaN round */
 742         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
 743                                         POWERPC_EXCP_FP_VXCVI);
 744     } else if (unlikely(float64_is_quiet_nan(farg.d) ||
 745                         float64_is_infinity(farg.d))) {
 746         /* qNan / infinity round */
 747         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI);
 748     } else {
 749         set_float_rounding_mode(rounding_mode, &env->fp_status);
 750         farg.ll = float64_round_to_int(farg.d, &env->fp_status);
 751         /* Restore rounding mode from FPSCR */
 752         fpscr_set_rounding_mode(env);
 753     }
 754     return farg.ll;
 755 }
 756
 757 uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
 758 {
 759     return do_fri(env, arg, float_round_nearest_even);
 760 }
 761
 762 uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
 763 {
 764     return do_fri(env, arg, float_round_to_zero);
 765 }
 766
 767 uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
 768 {
 769     return do_fri(env, arg, float_round_up);
 770 }
 771
 772 uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
 773 {
 774     return do_fri(env, arg, float_round_down);
 775 }
 776
 777 /* fmadd - fmadd. */
 778 uint64_t helper_fmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 779                       uint64_t arg3)
 780 {
 781     CPU_DoubleU farg1, farg2, farg3;
 782
 783     farg1.ll = arg1;
 784     farg2.ll = arg2;
 785     farg3.ll = arg3;
 786
 787     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 788                  (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
 789         /* Multiplication of zero by infinity */
 790         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ);
 791     } else {
 792         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 793                      float64_is_signaling_nan(farg2.d) ||
 794                      float64_is_signaling_nan(farg3.d))) {
 795             /* sNaN operation */
 796             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
 797         }
 798         /* This is the way the PowerPC specification defines it */
 799         float128 ft0_128, ft1_128;
 800
 801         ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
 802         ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
 803         ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 804         if (unlikely(float128_is_infinity(ft0_128) &&
 805                      float64_is_infinity(farg3.d) &&
 806                      float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
 807             /* Magnitude subtraction of infinities */
 808             farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
 809         } else {
 810             ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
 811             ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
 812             farg1.d = float128_to_float64(ft0_128, &env->fp_status);
 813         }
 814     }
 815
 816     return farg1.ll;
 817 }
 818
 819 /* fmsub - fmsub. */
 820 uint64_t helper_fmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 821                       uint64_t arg3)
 822 {
 823     CPU_DoubleU farg1, farg2, farg3;
 824
 825     farg1.ll = arg1;
 826     farg2.ll = arg2;
 827     farg3.ll = arg3;
 828
 829     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 830                  (float64_is_zero(farg1.d) &&
 831                   float64_is_infinity(farg2.d)))) {
 832         /* Multiplication of zero by infinity */
 833         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ);
 834     } else {
 835         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 836                      float64_is_signaling_nan(farg2.d) ||
 837                      float64_is_signaling_nan(farg3.d))) {
 838             /* sNaN operation */
 839             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
 840         }
 841         /* This is the way the PowerPC specification defines it */
 842         float128 ft0_128, ft1_128;
 843
 844         ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
 845         ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
 846         ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 847         if (unlikely(float128_is_infinity(ft0_128) &&
 848                      float64_is_infinity(farg3.d) &&
 849                      float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
 850             /* Magnitude subtraction of infinities */
 851             farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
 852         } else {
 853             ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
 854             ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
 855             farg1.d = float128_to_float64(ft0_128, &env->fp_status);
 856         }
 857     }
 858     return farg1.ll;
 859 }
 860
 861 /* fnmadd - fnmadd. */
 862 uint64_t helper_fnmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 863                        uint64_t arg3)
 864 {
 865     CPU_DoubleU farg1, farg2, farg3;
 866
 867     farg1.ll = arg1;
 868     farg2.ll = arg2;
 869     farg3.ll = arg3;
 870
 871     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 872                  (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
 873         /* Multiplication of zero by infinity */
 874         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ);
 875     } else {
 876         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 877                      float64_is_signaling_nan(farg2.d) ||
 878                      float64_is_signaling_nan(farg3.d))) {
 879             /* sNaN operation */
 880             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
 881         }
 882         /* This is the way the PowerPC specification defines it */
 883         float128 ft0_128, ft1_128;
 884
 885         ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
 886         ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
 887         ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 888         if (unlikely(float128_is_infinity(ft0_128) &&
 889                      float64_is_infinity(farg3.d) &&
 890                      float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
 891             /* Magnitude subtraction of infinities */
 892             farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
 893         } else {
 894             ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
 895             ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
 896             farg1.d = float128_to_float64(ft0_128, &env->fp_status);
 897         }
 898         if (likely(!float64_is_any_nan(farg1.d))) {
 899             farg1.d = float64_chs(farg1.d);
 900         }
 901     }
 902     return farg1.ll;
 903 }
 904
 905 /* fnmsub - fnmsub. */
 906 uint64_t helper_fnmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 907                        uint64_t arg3)
 908 {
 909     CPU_DoubleU farg1, farg2, farg3;
 910
 911     farg1.ll = arg1;
 912     farg2.ll = arg2;
 913     farg3.ll = arg3;
 914
 915     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 916                  (float64_is_zero(farg1.d) &&
 917                   float64_is_infinity(farg2.d)))) {
 918         /* Multiplication of zero by infinity */
 919         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ);
 920     } else {
 921         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 922                      float64_is_signaling_nan(farg2.d) ||
 923                      float64_is_signaling_nan(farg3.d))) {
 924             /* sNaN operation */
 925             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
 926         }
 927         /* This is the way the PowerPC specification defines it */
 928         float128 ft0_128, ft1_128;
 929
 930         ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
 931         ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
 932         ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 933         if (unlikely(float128_is_infinity(ft0_128) &&
 934                      float64_is_infinity(farg3.d) &&
 935                      float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
 936             /* Magnitude subtraction of infinities */
 937             farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
 938         } else {
 939             ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
 940             ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
 941             farg1.d = float128_to_float64(ft0_128, &env->fp_status);
 942         }
 943         if (likely(!float64_is_any_nan(farg1.d))) {
 944             farg1.d = float64_chs(farg1.d);
 945         }
 946     }
 947     return farg1.ll;
 948 }
 949
 950 /* frsp - frsp. */
 951 uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
 952 {
 953     CPU_DoubleU farg;
 954     float32 f32;
 955
 956     farg.ll = arg;
 957
 958     if (unlikely(float64_is_signaling_nan(farg.d))) {
 959         /* sNaN square root */
 960         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
 961     }
 962     f32 = float64_to_float32(farg.d, &env->fp_status);
 963     farg.d = float32_to_float64(f32, &env->fp_status);
 964
 965     return farg.ll;
 966 }
 967
 968 /* fsqrt - fsqrt. */
 969 uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
 970 {
 971     CPU_DoubleU farg;
 972
 973     farg.ll = arg;
 974
 975     if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
 976         /* Square root of a negative nonzero number */
 977         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT);
 978     } else {
 979         if (unlikely(float64_is_signaling_nan(farg.d))) {
 980             /* sNaN square root */
 981             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
 982         }
 983         farg.d = float64_sqrt(farg.d, &env->fp_status);
 984     }
 985     return farg.ll;
 986 }
 987
 988 /* fre - fre. */
 989 uint64_t helper_fre(CPUPPCState *env, uint64_t arg)
 990 {
 991     CPU_DoubleU farg;
 992
 993     farg.ll = arg;
 994
 995     if (unlikely(float64_is_signaling_nan(farg.d))) {
 996         /* sNaN reciprocal */
 997         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
 998     }
 999     farg.d = float64_div(float64_one, farg.d, &env->fp_status);
1000     return farg.d;
1001 }
1002
1003 /* fres - fres. */
1004 uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
1005 {
1006     CPU_DoubleU farg;
1007     float32 f32;
1008
1009     farg.ll = arg;
1010
1011     if (unlikely(float64_is_signaling_nan(farg.d))) {
1012         /* sNaN reciprocal */
1013         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
1014     }
1015     farg.d = float64_div(float64_one, farg.d, &env->fp_status);
1016     f32 = float64_to_float32(farg.d, &env->fp_status);
1017     farg.d = float32_to_float64(f32, &env->fp_status);
1018
1019     return farg.ll;
1020 }
1021
1022 /* frsqrte  - frsqrte. */
1023 uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg)
1024 {
1025     CPU_DoubleU farg;
1026     float32 f32;
1027
1028     farg.ll = arg;
1029
1030     if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
1031         /* Reciprocal square root of a negative nonzero number */
1032         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT);
1033     } else {
1034         if (unlikely(float64_is_signaling_nan(farg.d))) {
1035             /* sNaN reciprocal square root */
1036             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
1037         }
1038         farg.d = float64_sqrt(farg.d, &env->fp_status);
1039         farg.d = float64_div(float64_one, farg.d, &env->fp_status);
1040         f32 = float64_to_float32(farg.d, &env->fp_status);
1041         farg.d = float32_to_float64(f32, &env->fp_status);
1042     }
1043     return farg.ll;
1044 }
1045
1046 /* fsel - fsel. */
1047 uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1048                      uint64_t arg3)
1049 {
1050     CPU_DoubleU farg1;
1051
1052     farg1.ll = arg1;
1053
1054     if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
1055         !float64_is_any_nan(farg1.d)) {
1056         return arg2;
1057     } else {
1058         return arg3;
1059     }
1060 }
1061
1062 void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1063                   uint32_t crfD)
1064 {
1065     CPU_DoubleU farg1, farg2;
1066     uint32_t ret = 0;
1067
1068     farg1.ll = arg1;
1069     farg2.ll = arg2;
1070
1071     if (unlikely(float64_is_any_nan(farg1.d) ||
1072                  float64_is_any_nan(farg2.d))) {
1073         ret = 0x01UL;
1074     } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1075         ret = 0x08UL;
1076     } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1077         ret = 0x04UL;
1078     } else {
1079         ret = 0x02UL;
1080     }
1081
1082     env->fpscr &= ~(0x0F << FPSCR_FPRF);
1083     env->fpscr |= ret << FPSCR_FPRF;
1084     env->crf[crfD] = ret;
1085     if (unlikely(ret == 0x01UL
1086                  && (float64_is_signaling_nan(farg1.d) ||
1087                      float64_is_signaling_nan(farg2.d)))) {
1088         /* sNaN comparison */
1089         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
1090     }
1091 }
1092
1093 void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1094                   uint32_t crfD)
1095 {
1096     CPU_DoubleU farg1, farg2;
1097     uint32_t ret = 0;
1098
1099     farg1.ll = arg1;
1100     farg2.ll = arg2;
1101
1102     if (unlikely(float64_is_any_nan(farg1.d) ||
1103                  float64_is_any_nan(farg2.d))) {
1104         ret = 0x01UL;
1105     } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1106         ret = 0x08UL;
1107     } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1108         ret = 0x04UL;
1109     } else {
1110         ret = 0x02UL;
1111     }
1112
1113     env->fpscr &= ~(0x0F << FPSCR_FPRF);
1114     env->fpscr |= ret << FPSCR_FPRF;
1115     env->crf[crfD] = ret;
1116     if (unlikely(ret == 0x01UL)) {
1117         if (float64_is_signaling_nan(farg1.d) ||
1118             float64_is_signaling_nan(farg2.d)) {
1119             /* sNaN comparison */
1120             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
1121                                   POWERPC_EXCP_FP_VXVC);
1122         } else {
1123             /* qNaN comparison */
1124             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC);
1125         }
1126     }
1127 }
1128
1129 /* Single-precision floating-point conversions */
1130 static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
1131 {
1132     CPU_FloatU u;
1133
1134     u.f = int32_to_float32(val, &env->vec_status);
1135
1136     return u.l;
1137 }
1138
1139 static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
1140 {
1141     CPU_FloatU u;
1142
1143     u.f = uint32_to_float32(val, &env->vec_status);
1144
1145     return u.l;
1146 }
1147
1148 static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
1149 {
1150     CPU_FloatU u;
1151
1152     u.l = val;
1153     /* NaN are not treated the same way IEEE 754 does */
1154     if (unlikely(float32_is_quiet_nan(u.f))) {
1155         return 0;
1156     }
1157
1158     return float32_to_int32(u.f, &env->vec_status);
1159 }
1160
1161 static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
1162 {
1163     CPU_FloatU u;
1164
1165     u.l = val;
1166     /* NaN are not treated the same way IEEE 754 does */
1167     if (unlikely(float32_is_quiet_nan(u.f))) {
1168         return 0;
1169     }
1170
1171     return float32_to_uint32(u.f, &env->vec_status);
1172 }
1173
1174 static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
1175 {
1176     CPU_FloatU u;
1177
1178     u.l = val;
1179     /* NaN are not treated the same way IEEE 754 does */
1180     if (unlikely(float32_is_quiet_nan(u.f))) {
1181         return 0;
1182     }
1183
1184     return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1185 }
1186
1187 static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
1188 {
1189     CPU_FloatU u;
1190
1191     u.l = val;
1192     /* NaN are not treated the same way IEEE 754 does */
1193     if (unlikely(float32_is_quiet_nan(u.f))) {
1194         return 0;
1195     }
1196
1197     return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1198 }
1199
1200 static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
1201 {
1202     CPU_FloatU u;
1203     float32 tmp;
1204
1205     u.f = int32_to_float32(val, &env->vec_status);
1206     tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1207     u.f = float32_div(u.f, tmp, &env->vec_status);
1208
1209     return u.l;
1210 }
1211
1212 static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
1213 {
1214     CPU_FloatU u;
1215     float32 tmp;
1216
1217     u.f = uint32_to_float32(val, &env->vec_status);
1218     tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1219     u.f = float32_div(u.f, tmp, &env->vec_status);
1220
1221     return u.l;
1222 }
1223
1224 static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
1225 {
1226     CPU_FloatU u;
1227     float32 tmp;
1228
1229     u.l = val;
1230     /* NaN are not treated the same way IEEE 754 does */
1231     if (unlikely(float32_is_quiet_nan(u.f))) {
1232         return 0;
1233     }
1234     tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1235     u.f = float32_mul(u.f, tmp, &env->vec_status);
1236
1237     return float32_to_int32(u.f, &env->vec_status);
1238 }
1239
1240 static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
1241 {
1242     CPU_FloatU u;
1243     float32 tmp;
1244
1245     u.l = val;
1246     /* NaN are not treated the same way IEEE 754 does */
1247     if (unlikely(float32_is_quiet_nan(u.f))) {
1248         return 0;
1249     }
1250     tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1251     u.f = float32_mul(u.f, tmp, &env->vec_status);
1252
1253     return float32_to_uint32(u.f, &env->vec_status);
1254 }
1255
1256 #define HELPER_SPE_SINGLE_CONV(name)                              \
1257     uint32_t helper_e##name(CPUPPCState *env, uint32_t val)       \
1258     {                                                             \
1259         return e##name(env, val);                                 \
1260     }
1261 /* efscfsi */
1262 HELPER_SPE_SINGLE_CONV(fscfsi);
1263 /* efscfui */
1264 HELPER_SPE_SINGLE_CONV(fscfui);
1265 /* efscfuf */
1266 HELPER_SPE_SINGLE_CONV(fscfuf);
1267 /* efscfsf */
1268 HELPER_SPE_SINGLE_CONV(fscfsf);
1269 /* efsctsi */
1270 HELPER_SPE_SINGLE_CONV(fsctsi);
1271 /* efsctui */
1272 HELPER_SPE_SINGLE_CONV(fsctui);
1273 /* efsctsiz */
1274 HELPER_SPE_SINGLE_CONV(fsctsiz);
1275 /* efsctuiz */
1276 HELPER_SPE_SINGLE_CONV(fsctuiz);
1277 /* efsctsf */
1278 HELPER_SPE_SINGLE_CONV(fsctsf);
1279 /* efsctuf */
1280 HELPER_SPE_SINGLE_CONV(fsctuf);
1281
1282 #define HELPER_SPE_VECTOR_CONV(name)                            \
1283     uint64_t helper_ev##name(CPUPPCState *env, uint64_t val)    \
1284     {                                                           \
1285         return ((uint64_t)e##name(env, val >> 32) << 32) |      \
1286             (uint64_t)e##name(env, val);                        \
1287     }
1288 /* evfscfsi */
1289 HELPER_SPE_VECTOR_CONV(fscfsi);
1290 /* evfscfui */
1291 HELPER_SPE_VECTOR_CONV(fscfui);
1292 /* evfscfuf */
1293 HELPER_SPE_VECTOR_CONV(fscfuf);
1294 /* evfscfsf */
1295 HELPER_SPE_VECTOR_CONV(fscfsf);
1296 /* evfsctsi */
1297 HELPER_SPE_VECTOR_CONV(fsctsi);
1298 /* evfsctui */
1299 HELPER_SPE_VECTOR_CONV(fsctui);
1300 /* evfsctsiz */
1301 HELPER_SPE_VECTOR_CONV(fsctsiz);
1302 /* evfsctuiz */
1303 HELPER_SPE_VECTOR_CONV(fsctuiz);
1304 /* evfsctsf */
1305 HELPER_SPE_VECTOR_CONV(fsctsf);
1306 /* evfsctuf */
1307 HELPER_SPE_VECTOR_CONV(fsctuf);
1308
1309 /* Single-precision floating-point arithmetic */
1310 static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
1311 {
1312     CPU_FloatU u1, u2;
1313
1314     u1.l = op1;
1315     u2.l = op2;
1316     u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1317     return u1.l;
1318 }
1319
1320 static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
1321 {
1322     CPU_FloatU u1, u2;
1323
1324     u1.l = op1;
1325     u2.l = op2;
1326     u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1327     return u1.l;
1328 }
1329
1330 static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
1331 {
1332     CPU_FloatU u1, u2;
1333
1334     u1.l = op1;
1335     u2.l = op2;
1336     u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1337     return u1.l;
1338 }
1339
1340 static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
1341 {
1342     CPU_FloatU u1, u2;
1343
1344     u1.l = op1;
1345     u2.l = op2;
1346     u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1347     return u1.l;
1348 }
1349
1350 #define HELPER_SPE_SINGLE_ARITH(name)                                   \
1351     uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1352     {                                                                   \
1353         return e##name(env, op1, op2);                                  \
1354     }
1355 /* efsadd */
1356 HELPER_SPE_SINGLE_ARITH(fsadd);
1357 /* efssub */
1358 HELPER_SPE_SINGLE_ARITH(fssub);
1359 /* efsmul */
1360 HELPER_SPE_SINGLE_ARITH(fsmul);
1361 /* efsdiv */
1362 HELPER_SPE_SINGLE_ARITH(fsdiv);
1363
1364 #define HELPER_SPE_VECTOR_ARITH(name)                                   \
1365     uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1366     {                                                                   \
1367         return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) |   \
1368             (uint64_t)e##name(env, op1, op2);                           \
1369     }
1370 /* evfsadd */
1371 HELPER_SPE_VECTOR_ARITH(fsadd);
1372 /* evfssub */
1373 HELPER_SPE_VECTOR_ARITH(fssub);
1374 /* evfsmul */
1375 HELPER_SPE_VECTOR_ARITH(fsmul);
1376 /* evfsdiv */
1377 HELPER_SPE_VECTOR_ARITH(fsdiv);
1378
1379 /* Single-precision floating-point comparisons */
1380 static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1381 {
1382     CPU_FloatU u1, u2;
1383
1384     u1.l = op1;
1385     u2.l = op2;
1386     return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1387 }
1388
1389 static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1390 {
1391     CPU_FloatU u1, u2;
1392
1393     u1.l = op1;
1394     u2.l = op2;
1395     return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1396 }
1397
1398 static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1399 {
1400     CPU_FloatU u1, u2;
1401
1402     u1.l = op1;
1403     u2.l = op2;
1404     return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1405 }
1406
1407 static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1408 {
1409     /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1410     return efscmplt(env, op1, op2);
1411 }
1412
1413 static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1414 {
1415     /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1416     return efscmpgt(env, op1, op2);
1417 }
1418
1419 static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1420 {
1421     /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1422     return efscmpeq(env, op1, op2);
1423 }
1424
1425 #define HELPER_SINGLE_SPE_CMP(name)                                     \
1426     uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1427     {                                                                   \
1428         return e##name(env, op1, op2) << 2;                             \
1429     }
1430 /* efststlt */
1431 HELPER_SINGLE_SPE_CMP(fststlt);
1432 /* efststgt */
1433 HELPER_SINGLE_SPE_CMP(fststgt);
1434 /* efststeq */
1435 HELPER_SINGLE_SPE_CMP(fststeq);
1436 /* efscmplt */
1437 HELPER_SINGLE_SPE_CMP(fscmplt);
1438 /* efscmpgt */
1439 HELPER_SINGLE_SPE_CMP(fscmpgt);
1440 /* efscmpeq */
1441 HELPER_SINGLE_SPE_CMP(fscmpeq);
1442
1443 static inline uint32_t evcmp_merge(int t0, int t1)
1444 {
1445     return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1446 }
1447
1448 #define HELPER_VECTOR_SPE_CMP(name)                                     \
1449     uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1450     {                                                                   \
1451         return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32),          \
1452                            e##name(env, op1, op2));                     \
1453     }
1454 /* evfststlt */
1455 HELPER_VECTOR_SPE_CMP(fststlt);
1456 /* evfststgt */
1457 HELPER_VECTOR_SPE_CMP(fststgt);
1458 /* evfststeq */
1459 HELPER_VECTOR_SPE_CMP(fststeq);
1460 /* evfscmplt */
1461 HELPER_VECTOR_SPE_CMP(fscmplt);
1462 /* evfscmpgt */
1463 HELPER_VECTOR_SPE_CMP(fscmpgt);
1464 /* evfscmpeq */
1465 HELPER_VECTOR_SPE_CMP(fscmpeq);
1466
1467 /* Double-precision floating-point conversion */
1468 uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
1469 {
1470     CPU_DoubleU u;
1471
1472     u.d = int32_to_float64(val, &env->vec_status);
1473
1474     return u.ll;
1475 }
1476
1477 uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
1478 {
1479     CPU_DoubleU u;
1480
1481     u.d = int64_to_float64(val, &env->vec_status);
1482
1483     return u.ll;
1484 }
1485
1486 uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
1487 {
1488     CPU_DoubleU u;
1489
1490     u.d = uint32_to_float64(val, &env->vec_status);
1491
1492     return u.ll;
1493 }
1494
1495 uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
1496 {
1497     CPU_DoubleU u;
1498
1499     u.d = uint64_to_float64(val, &env->vec_status);
1500
1501     return u.ll;
1502 }
1503
1504 uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
1505 {
1506     CPU_DoubleU u;
1507
1508     u.ll = val;
1509     /* NaN are not treated the same way IEEE 754 does */
1510     if (unlikely(float64_is_any_nan(u.d))) {
1511         return 0;
1512     }
1513
1514     return float64_to_int32(u.d, &env->vec_status);
1515 }
1516
1517 uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
1518 {
1519     CPU_DoubleU u;
1520
1521     u.ll = val;
1522     /* NaN are not treated the same way IEEE 754 does */
1523     if (unlikely(float64_is_any_nan(u.d))) {
1524         return 0;
1525     }
1526
1527     return float64_to_uint32(u.d, &env->vec_status);
1528 }
1529
1530 uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
1531 {
1532     CPU_DoubleU u;
1533
1534     u.ll = val;
1535     /* NaN are not treated the same way IEEE 754 does */
1536     if (unlikely(float64_is_any_nan(u.d))) {
1537         return 0;
1538     }
1539
1540     return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1541 }
1542
1543 uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
1544 {
1545     CPU_DoubleU u;
1546
1547     u.ll = val;
1548     /* NaN are not treated the same way IEEE 754 does */
1549     if (unlikely(float64_is_any_nan(u.d))) {
1550         return 0;
1551     }
1552
1553     return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1554 }
1555
1556 uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
1557 {
1558     CPU_DoubleU u;
1559
1560     u.ll = val;
1561     /* NaN are not treated the same way IEEE 754 does */
1562     if (unlikely(float64_is_any_nan(u.d))) {
1563         return 0;
1564     }
1565
1566     return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1567 }
1568
1569 uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
1570 {
1571     CPU_DoubleU u;
1572
1573     u.ll = val;
1574     /* NaN are not treated the same way IEEE 754 does */
1575     if (unlikely(float64_is_any_nan(u.d))) {
1576         return 0;
1577     }
1578
1579     return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1580 }
1581
1582 uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
1583 {
1584     CPU_DoubleU u;
1585     float64 tmp;
1586
1587     u.d = int32_to_float64(val, &env->vec_status);
1588     tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1589     u.d = float64_div(u.d, tmp, &env->vec_status);
1590
1591     return u.ll;
1592 }
1593
1594 uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
1595 {
1596     CPU_DoubleU u;
1597     float64 tmp;
1598
1599     u.d = uint32_to_float64(val, &env->vec_status);
1600     tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1601     u.d = float64_div(u.d, tmp, &env->vec_status);
1602
1603     return u.ll;
1604 }
1605
1606 uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
1607 {
1608     CPU_DoubleU u;
1609     float64 tmp;
1610
1611     u.ll = val;
1612     /* NaN are not treated the same way IEEE 754 does */
1613     if (unlikely(float64_is_any_nan(u.d))) {
1614         return 0;
1615     }
1616     tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1617     u.d = float64_mul(u.d, tmp, &env->vec_status);
1618
1619     return float64_to_int32(u.d, &env->vec_status);
1620 }
1621
1622 uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
1623 {
1624     CPU_DoubleU u;
1625     float64 tmp;
1626
1627     u.ll = val;
1628     /* NaN are not treated the same way IEEE 754 does */
1629     if (unlikely(float64_is_any_nan(u.d))) {
1630         return 0;
1631     }
1632     tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1633     u.d = float64_mul(u.d, tmp, &env->vec_status);
1634
1635     return float64_to_uint32(u.d, &env->vec_status);
1636 }
1637
1638 uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
1639 {
1640     CPU_DoubleU u1;
1641     CPU_FloatU u2;
1642
1643     u1.ll = val;
1644     u2.f = float64_to_float32(u1.d, &env->vec_status);
1645
1646     return u2.l;
1647 }
1648
1649 uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
1650 {
1651     CPU_DoubleU u2;
1652     CPU_FloatU u1;
1653
1654     u1.l = val;
1655     u2.d = float32_to_float64(u1.f, &env->vec_status);
1656
1657     return u2.ll;
1658 }
1659
1660 /* Double precision fixed-point arithmetic */
1661 uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
1662 {
1663     CPU_DoubleU u1, u2;
1664
1665     u1.ll = op1;
1666     u2.ll = op2;
1667     u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1668     return u1.ll;
1669 }
1670
1671 uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
1672 {
1673     CPU_DoubleU u1, u2;
1674
1675     u1.ll = op1;
1676     u2.ll = op2;
1677     u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1678     return u1.ll;
1679 }
1680
1681 uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
1682 {
1683     CPU_DoubleU u1, u2;
1684
1685     u1.ll = op1;
1686     u2.ll = op2;
1687     u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1688     return u1.ll;
1689 }
1690
1691 uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
1692 {
1693     CPU_DoubleU u1, u2;
1694
1695     u1.ll = op1;
1696     u2.ll = op2;
1697     u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1698     return u1.ll;
1699 }
1700
1701 /* Double precision floating point helpers */
1702 uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1703 {
1704     CPU_DoubleU u1, u2;
1705
1706     u1.ll = op1;
1707     u2.ll = op2;
1708     return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1709 }
1710
1711 uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1712 {
1713     CPU_DoubleU u1, u2;
1714
1715     u1.ll = op1;
1716     u2.ll = op2;
1717     return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1718 }
1719
1720 uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1721 {
1722     CPU_DoubleU u1, u2;
1723
1724     u1.ll = op1;
1725     u2.ll = op2;
1726     return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1727 }
1728
1729 uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1730 {
1731     /* XXX: TODO: test special values (NaN, infinites, ...) */
1732     return helper_efdtstlt(env, op1, op2);
1733 }
1734
1735 uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1736 {
1737     /* XXX: TODO: test special values (NaN, infinites, ...) */
1738     return helper_efdtstgt(env, op1, op2);
1739 }
1740
1741 uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1742 {
1743     /* XXX: TODO: test special values (NaN, infinites, ...) */
1744     return helper_efdtsteq(env, op1, op2);
1745 }