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Rework PowerPC exceptions model to make it more versatile:
[qemu.git] / target-ppc / helper.c
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30
31 //#define DEBUG_MMU
32 //#define DEBUG_BATS
33 //#define DEBUG_SOFTWARE_TLB
34 //#define DEBUG_EXCEPTIONS
35 //#define FLUSH_ALL_TLBS
36
37 /*****************************************************************************/
38 /* PowerPC MMU emulation */
39
40 #if defined(CONFIG_USER_ONLY)
41 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
42 int is_user, int is_softmmu)
43 {
44 int exception, error_code;
45
46 if (rw == 2) {
47 exception = POWERPC_EXCP_ISI;
48 error_code = 0;
49 } else {
50 exception = POWERPC_EXCP_DSI;
51 error_code = 0;
52 if (rw)
53 error_code |= 0x02000000;
54 env->spr[SPR_DAR] = address;
55 env->spr[SPR_DSISR] = error_code;
56 }
57 env->exception_index = exception;
58 env->error_code = error_code;
59
60 return 1;
61 }
62
63 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
64 {
65 return addr;
66 }
67
68 #else
69 /* Common routines used by software and hardware TLBs emulation */
70 static inline int pte_is_valid (target_ulong pte0)
71 {
72 return pte0 & 0x80000000 ? 1 : 0;
73 }
74
75 static inline void pte_invalidate (target_ulong *pte0)
76 {
77 *pte0 &= ~0x80000000;
78 }
79
80 #if defined(TARGET_PPC64)
81 static inline int pte64_is_valid (target_ulong pte0)
82 {
83 return pte0 & 0x0000000000000001ULL ? 1 : 0;
84 }
85
86 static inline void pte64_invalidate (target_ulong *pte0)
87 {
88 *pte0 &= ~0x0000000000000001ULL;
89 }
90 #endif
91
92 #define PTE_PTEM_MASK 0x7FFFFFBF
93 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
94 #if defined(TARGET_PPC64)
95 #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
96 #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
97 #endif
98
99 static inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
100 target_ulong pte0, target_ulong pte1,
101 int h, int rw)
102 {
103 target_ulong ptem, mmask;
104 int access, ret, pteh, ptev;
105
106 access = 0;
107 ret = -1;
108 /* Check validity and table match */
109 #if defined(TARGET_PPC64)
110 if (is_64b) {
111 ptev = pte64_is_valid(pte0);
112 pteh = (pte0 >> 1) & 1;
113 } else
114 #endif
115 {
116 ptev = pte_is_valid(pte0);
117 pteh = (pte0 >> 6) & 1;
118 }
119 if (ptev && h == pteh) {
120 /* Check vsid & api */
121 #if defined(TARGET_PPC64)
122 if (is_64b) {
123 ptem = pte0 & PTE64_PTEM_MASK;
124 mmask = PTE64_CHECK_MASK;
125 } else
126 #endif
127 {
128 ptem = pte0 & PTE_PTEM_MASK;
129 mmask = PTE_CHECK_MASK;
130 }
131 if (ptem == ctx->ptem) {
132 if (ctx->raddr != (target_ulong)-1) {
133 /* all matches should have equal RPN, WIMG & PP */
134 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
135 if (loglevel != 0)
136 fprintf(logfile, "Bad RPN/WIMG/PP\n");
137 return -3;
138 }
139 }
140 /* Compute access rights */
141 if (ctx->key == 0) {
142 access = PAGE_READ;
143 if ((pte1 & 0x00000003) != 0x3)
144 access |= PAGE_WRITE;
145 } else {
146 switch (pte1 & 0x00000003) {
147 case 0x0:
148 access = 0;
149 break;
150 case 0x1:
151 case 0x3:
152 access = PAGE_READ;
153 break;
154 case 0x2:
155 access = PAGE_READ | PAGE_WRITE;
156 break;
157 }
158 }
159 /* Keep the matching PTE informations */
160 ctx->raddr = pte1;
161 ctx->prot = access;
162 if ((rw == 0 && (access & PAGE_READ)) ||
163 (rw == 1 && (access & PAGE_WRITE))) {
164 /* Access granted */
165 #if defined (DEBUG_MMU)
166 if (loglevel != 0)
167 fprintf(logfile, "PTE access granted !\n");
168 #endif
169 ret = 0;
170 } else {
171 /* Access right violation */
172 #if defined (DEBUG_MMU)
173 if (loglevel != 0)
174 fprintf(logfile, "PTE access rejected\n");
175 #endif
176 ret = -2;
177 }
178 }
179 }
180
181 return ret;
182 }
183
184 static int pte32_check (mmu_ctx_t *ctx,
185 target_ulong pte0, target_ulong pte1, int h, int rw)
186 {
187 return _pte_check(ctx, 0, pte0, pte1, h, rw);
188 }
189
190 #if defined(TARGET_PPC64)
191 static int pte64_check (mmu_ctx_t *ctx,
192 target_ulong pte0, target_ulong pte1, int h, int rw)
193 {
194 return _pte_check(ctx, 1, pte0, pte1, h, rw);
195 }
196 #endif
197
198 static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
199 int ret, int rw)
200 {
201 int store = 0;
202
203 /* Update page flags */
204 if (!(*pte1p & 0x00000100)) {
205 /* Update accessed flag */
206 *pte1p |= 0x00000100;
207 store = 1;
208 }
209 if (!(*pte1p & 0x00000080)) {
210 if (rw == 1 && ret == 0) {
211 /* Update changed flag */
212 *pte1p |= 0x00000080;
213 store = 1;
214 } else {
215 /* Force page fault for first write access */
216 ctx->prot &= ~PAGE_WRITE;
217 }
218 }
219
220 return store;
221 }
222
223 /* Software driven TLB helpers */
224 static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
225 int way, int is_code)
226 {
227 int nr;
228
229 /* Select TLB num in a way from address */
230 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
231 /* Select TLB way */
232 nr += env->tlb_per_way * way;
233 /* 6xx have separate TLBs for instructions and data */
234 if (is_code && env->id_tlbs == 1)
235 nr += env->nb_tlb;
236
237 return nr;
238 }
239
240 void ppc6xx_tlb_invalidate_all (CPUState *env)
241 {
242 ppc6xx_tlb_t *tlb;
243 int nr, max;
244
245 #if defined (DEBUG_SOFTWARE_TLB) && 0
246 if (loglevel != 0) {
247 fprintf(logfile, "Invalidate all TLBs\n");
248 }
249 #endif
250 /* Invalidate all defined software TLB */
251 max = env->nb_tlb;
252 if (env->id_tlbs == 1)
253 max *= 2;
254 for (nr = 0; nr < max; nr++) {
255 tlb = &env->tlb[nr].tlb6;
256 #if !defined(FLUSH_ALL_TLBS)
257 tlb_flush_page(env, tlb->EPN);
258 #endif
259 pte_invalidate(&tlb->pte0);
260 }
261 #if defined(FLUSH_ALL_TLBS)
262 tlb_flush(env, 1);
263 #endif
264 }
265
266 static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
267 target_ulong eaddr,
268 int is_code, int match_epn)
269 {
270 #if !defined(FLUSH_ALL_TLBS)
271 ppc6xx_tlb_t *tlb;
272 int way, nr;
273
274 /* Invalidate ITLB + DTLB, all ways */
275 for (way = 0; way < env->nb_ways; way++) {
276 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
277 tlb = &env->tlb[nr].tlb6;
278 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
279 #if defined (DEBUG_SOFTWARE_TLB)
280 if (loglevel != 0) {
281 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
282 nr, env->nb_tlb, eaddr);
283 }
284 #endif
285 pte_invalidate(&tlb->pte0);
286 tlb_flush_page(env, tlb->EPN);
287 }
288 }
289 #else
290 /* XXX: PowerPC specification say this is valid as well */
291 ppc6xx_tlb_invalidate_all(env);
292 #endif
293 }
294
295 void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
296 int is_code)
297 {
298 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
299 }
300
301 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
302 target_ulong pte0, target_ulong pte1)
303 {
304 ppc6xx_tlb_t *tlb;
305 int nr;
306
307 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
308 tlb = &env->tlb[nr].tlb6;
309 #if defined (DEBUG_SOFTWARE_TLB)
310 if (loglevel != 0) {
311 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
312 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
313 }
314 #endif
315 /* Invalidate any pending reference in Qemu for this virtual address */
316 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
317 tlb->pte0 = pte0;
318 tlb->pte1 = pte1;
319 tlb->EPN = EPN;
320 /* Store last way for LRU mechanism */
321 env->last_way = way;
322 }
323
324 static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
325 target_ulong eaddr, int rw, int access_type)
326 {
327 ppc6xx_tlb_t *tlb;
328 int nr, best, way;
329 int ret;
330
331 best = -1;
332 ret = -1; /* No TLB found */
333 for (way = 0; way < env->nb_ways; way++) {
334 nr = ppc6xx_tlb_getnum(env, eaddr, way,
335 access_type == ACCESS_CODE ? 1 : 0);
336 tlb = &env->tlb[nr].tlb6;
337 /* This test "emulates" the PTE index match for hardware TLBs */
338 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
339 #if defined (DEBUG_SOFTWARE_TLB)
340 if (loglevel != 0) {
341 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
342 "] <> " ADDRX "\n",
343 nr, env->nb_tlb,
344 pte_is_valid(tlb->pte0) ? "valid" : "inval",
345 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
346 }
347 #endif
348 continue;
349 }
350 #if defined (DEBUG_SOFTWARE_TLB)
351 if (loglevel != 0) {
352 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
353 " %c %c\n",
354 nr, env->nb_tlb,
355 pte_is_valid(tlb->pte0) ? "valid" : "inval",
356 tlb->EPN, eaddr, tlb->pte1,
357 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
358 }
359 #endif
360 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
361 case -3:
362 /* TLB inconsistency */
363 return -1;
364 case -2:
365 /* Access violation */
366 ret = -2;
367 best = nr;
368 break;
369 case -1:
370 default:
371 /* No match */
372 break;
373 case 0:
374 /* access granted */
375 /* XXX: we should go on looping to check all TLBs consistency
376 * but we can speed-up the whole thing as the
377 * result would be undefined if TLBs are not consistent.
378 */
379 ret = 0;
380 best = nr;
381 goto done;
382 }
383 }
384 if (best != -1) {
385 done:
386 #if defined (DEBUG_SOFTWARE_TLB)
387 if (loglevel != 0) {
388 fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
389 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
390 }
391 #endif
392 /* Update page flags */
393 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
394 }
395
396 return ret;
397 }
398
399 /* Perform BAT hit & translation */
400 static int get_bat (CPUState *env, mmu_ctx_t *ctx,
401 target_ulong virtual, int rw, int type)
402 {
403 target_ulong *BATlt, *BATut, *BATu, *BATl;
404 target_ulong base, BEPIl, BEPIu, bl;
405 int i;
406 int ret = -1;
407
408 #if defined (DEBUG_BATS)
409 if (loglevel != 0) {
410 fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
411 type == ACCESS_CODE ? 'I' : 'D', virtual);
412 }
413 #endif
414 switch (type) {
415 case ACCESS_CODE:
416 BATlt = env->IBAT[1];
417 BATut = env->IBAT[0];
418 break;
419 default:
420 BATlt = env->DBAT[1];
421 BATut = env->DBAT[0];
422 break;
423 }
424 #if defined (DEBUG_BATS)
425 if (loglevel != 0) {
426 fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
427 type == ACCESS_CODE ? 'I' : 'D', virtual);
428 }
429 #endif
430 base = virtual & 0xFFFC0000;
431 for (i = 0; i < 4; i++) {
432 BATu = &BATut[i];
433 BATl = &BATlt[i];
434 BEPIu = *BATu & 0xF0000000;
435 BEPIl = *BATu & 0x0FFE0000;
436 bl = (*BATu & 0x00001FFC) << 15;
437 #if defined (DEBUG_BATS)
438 if (loglevel != 0) {
439 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
440 " BATl 0x" ADDRX "\n",
441 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
442 *BATu, *BATl);
443 }
444 #endif
445 if ((virtual & 0xF0000000) == BEPIu &&
446 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
447 /* BAT matches */
448 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
449 (msr_pr == 1 && (*BATu & 0x00000001))) {
450 /* Get physical address */
451 ctx->raddr = (*BATl & 0xF0000000) |
452 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
453 (virtual & 0x0001F000);
454 if (*BATl & 0x00000001)
455 ctx->prot = PAGE_READ;
456 if (*BATl & 0x00000002)
457 ctx->prot = PAGE_WRITE | PAGE_READ;
458 #if defined (DEBUG_BATS)
459 if (loglevel != 0) {
460 fprintf(logfile, "BAT %d match: r 0x" PADDRX
461 " prot=%c%c\n",
462 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
463 ctx->prot & PAGE_WRITE ? 'W' : '-');
464 }
465 #endif
466 ret = 0;
467 break;
468 }
469 }
470 }
471 if (ret < 0) {
472 #if defined (DEBUG_BATS)
473 if (loglevel != 0) {
474 fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
475 for (i = 0; i < 4; i++) {
476 BATu = &BATut[i];
477 BATl = &BATlt[i];
478 BEPIu = *BATu & 0xF0000000;
479 BEPIl = *BATu & 0x0FFE0000;
480 bl = (*BATu & 0x00001FFC) << 15;
481 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
482 " BATl 0x" ADDRX " \n\t"
483 "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
484 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
485 *BATu, *BATl, BEPIu, BEPIl, bl);
486 }
487 }
488 #endif
489 }
490 /* No hit */
491 return ret;
492 }
493
494 /* PTE table lookup */
495 static inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
496 {
497 target_ulong base, pte0, pte1;
498 int i, good = -1;
499 int ret, r;
500
501 ret = -1; /* No entry found */
502 base = ctx->pg_addr[h];
503 for (i = 0; i < 8; i++) {
504 #if defined(TARGET_PPC64)
505 if (is_64b) {
506 pte0 = ldq_phys(base + (i * 16));
507 pte1 = ldq_phys(base + (i * 16) + 8);
508 r = pte64_check(ctx, pte0, pte1, h, rw);
509 } else
510 #endif
511 {
512 pte0 = ldl_phys(base + (i * 8));
513 pte1 = ldl_phys(base + (i * 8) + 4);
514 r = pte32_check(ctx, pte0, pte1, h, rw);
515 }
516 #if defined (DEBUG_MMU)
517 if (loglevel != 0) {
518 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
519 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
520 base + (i * 8), pte0, pte1,
521 (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), ctx->ptem);
522 }
523 #endif
524 switch (r) {
525 case -3:
526 /* PTE inconsistency */
527 return -1;
528 case -2:
529 /* Access violation */
530 ret = -2;
531 good = i;
532 break;
533 case -1:
534 default:
535 /* No PTE match */
536 break;
537 case 0:
538 /* access granted */
539 /* XXX: we should go on looping to check all PTEs consistency
540 * but if we can speed-up the whole thing as the
541 * result would be undefined if PTEs are not consistent.
542 */
543 ret = 0;
544 good = i;
545 goto done;
546 }
547 }
548 if (good != -1) {
549 done:
550 #if defined (DEBUG_MMU)
551 if (loglevel != 0) {
552 fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
553 "ret=%d\n",
554 ctx->raddr, ctx->prot, ret);
555 }
556 #endif
557 /* Update page flags */
558 pte1 = ctx->raddr;
559 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
560 #if defined(TARGET_PPC64)
561 if (is_64b) {
562 stq_phys_notdirty(base + (good * 16) + 8, pte1);
563 } else
564 #endif
565 {
566 stl_phys_notdirty(base + (good * 8) + 4, pte1);
567 }
568 }
569 }
570
571 return ret;
572 }
573
574 static int find_pte32 (mmu_ctx_t *ctx, int h, int rw)
575 {
576 return _find_pte(ctx, 0, h, rw);
577 }
578
579 #if defined(TARGET_PPC64)
580 static int find_pte64 (mmu_ctx_t *ctx, int h, int rw)
581 {
582 return _find_pte(ctx, 1, h, rw);
583 }
584 #endif
585
586 static inline int find_pte (CPUState *env, mmu_ctx_t *ctx, int h, int rw)
587 {
588 #if defined(TARGET_PPC64)
589 if (env->mmu_model == POWERPC_MMU_64B ||
590 env->mmu_model == POWERPC_MMU_64BRIDGE)
591 return find_pte64(ctx, h, rw);
592 #endif
593
594 return find_pte32(ctx, h, rw);
595 }
596
597 static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
598 int sdr_sh,
599 target_phys_addr_t hash,
600 target_phys_addr_t mask)
601 {
602 return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask);
603 }
604
605 #if defined(TARGET_PPC64)
606 static int slb_lookup (CPUState *env, target_ulong eaddr,
607 target_ulong *vsid, target_ulong *page_mask, int *attr)
608 {
609 target_phys_addr_t sr_base;
610 target_ulong mask;
611 uint64_t tmp64;
612 uint32_t tmp;
613 int n, ret;
614 int slb_nr;
615
616 ret = -5;
617 sr_base = env->spr[SPR_ASR];
618 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
619 #if 0 /* XXX: Fix this */
620 slb_nr = env->slb_nr;
621 #else
622 slb_nr = 32;
623 #endif
624 for (n = 0; n < slb_nr; n++) {
625 tmp64 = ldq_phys(sr_base);
626 if (tmp64 & 0x0000000008000000ULL) {
627 /* SLB entry is valid */
628 switch (tmp64 & 0x0000000006000000ULL) {
629 case 0x0000000000000000ULL:
630 /* 256 MB segment */
631 mask = 0xFFFFFFFFF0000000ULL;
632 break;
633 case 0x0000000002000000ULL:
634 /* 1 TB segment */
635 mask = 0xFFFF000000000000ULL;
636 break;
637 case 0x0000000004000000ULL:
638 case 0x0000000006000000ULL:
639 /* Reserved => segment is invalid */
640 continue;
641 }
642 if ((eaddr & mask) == (tmp64 & mask)) {
643 /* SLB match */
644 tmp = ldl_phys(sr_base + 8);
645 *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
646 *page_mask = ~mask;
647 *attr = tmp & 0xFF;
648 ret = 0;
649 break;
650 }
651 }
652 sr_base += 12;
653 }
654
655 return ret;
656 }
657 #endif /* defined(TARGET_PPC64) */
658
659 /* Perform segment based translation */
660 static int get_segment (CPUState *env, mmu_ctx_t *ctx,
661 target_ulong eaddr, int rw, int type)
662 {
663 target_phys_addr_t sdr, hash, mask, sdr_mask;
664 target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
665 #if defined(TARGET_PPC64)
666 int attr;
667 #endif
668 int ds, nx, vsid_sh, sdr_sh;
669 int ret, ret2;
670
671 #if defined(TARGET_PPC64)
672 if (env->mmu_model == POWERPC_MMU_64B) {
673 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
674 if (ret < 0)
675 return ret;
676 ctx->key = ((attr & 0x40) && msr_pr == 1) ||
677 ((attr & 0x80) && msr_pr == 0) ? 1 : 0;
678 ds = 0;
679 nx = attr & 0x20 ? 1 : 0;
680 vsid_mask = 0x00003FFFFFFFFF80ULL;
681 vsid_sh = 7;
682 sdr_sh = 18;
683 sdr_mask = 0x3FF80;
684 } else
685 #endif /* defined(TARGET_PPC64) */
686 {
687 sr = env->sr[eaddr >> 28];
688 page_mask = 0x0FFFFFFF;
689 ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
690 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
691 ds = sr & 0x80000000 ? 1 : 0;
692 nx = sr & 0x10000000 ? 1 : 0;
693 vsid = sr & 0x00FFFFFF;
694 vsid_mask = 0x01FFFFC0;
695 vsid_sh = 6;
696 sdr_sh = 16;
697 sdr_mask = 0xFFC0;
698 #if defined (DEBUG_MMU)
699 if (loglevel != 0) {
700 fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX
701 " nip=0x" ADDRX " lr=0x" ADDRX
702 " ir=%d dr=%d pr=%d %d t=%d\n",
703 eaddr, (int)(eaddr >> 28), sr, env->nip,
704 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
705 }
706 if (!ds && loglevel != 0) {
707 fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",
708 ctx->key, sr & 0x10000000);
709 }
710 #endif
711 }
712 ret = -1;
713 if (!ds) {
714 /* Check if instruction fetch is allowed, if needed */
715 if (type != ACCESS_CODE || nx == 0) {
716 /* Page address translation */
717 pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
718 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
719 /* Primary table address */
720 sdr = env->sdr1;
721 mask = ((sdr & 0x000001FF) << sdr_sh) | sdr_mask;
722 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
723 /* Secondary table address */
724 hash = (~hash) & vsid_mask;
725 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
726 #if defined(TARGET_PPC64)
727 if (env->mmu_model == POWERPC_MMU_64B ||
728 env->mmu_model == POWERPC_MMU_64BRIDGE) {
729 /* Only 5 bits of the page index are used in the AVPN */
730 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
731 } else
732 #endif
733 {
734 ctx->ptem = (vsid << 7) | (pgidx >> 10);
735 }
736 /* Initialize real address with an invalid value */
737 ctx->raddr = (target_ulong)-1;
738 if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
739 /* Software TLB search */
740 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
741 } else {
742 #if defined (DEBUG_MMU)
743 if (loglevel != 0) {
744 fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
745 "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
746 sdr, (uint32_t)vsid, (uint32_t)pgidx,
747 (uint32_t)hash, ctx->pg_addr[0]);
748 }
749 #endif
750 /* Primary table lookup */
751 ret = find_pte(env, ctx, 0, rw);
752 if (ret < 0) {
753 /* Secondary table lookup */
754 #if defined (DEBUG_MMU)
755 if (eaddr != 0xEFFFFFFF && loglevel != 0) {
756 fprintf(logfile,
757 "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
758 "hash=0x%05x pg_addr=0x" PADDRX "\n",
759 sdr, (uint32_t)vsid, (uint32_t)pgidx,
760 (uint32_t)hash, ctx->pg_addr[1]);
761 }
762 #endif
763 ret2 = find_pte(env, ctx, 1, rw);
764 if (ret2 != -1)
765 ret = ret2;
766 }
767 }
768 } else {
769 #if defined (DEBUG_MMU)
770 if (loglevel != 0)
771 fprintf(logfile, "No access allowed\n");
772 #endif
773 ret = -3;
774 }
775 } else {
776 #if defined (DEBUG_MMU)
777 if (loglevel != 0)
778 fprintf(logfile, "direct store...\n");
779 #endif
780 /* Direct-store segment : absolutely *BUGGY* for now */
781 switch (type) {
782 case ACCESS_INT:
783 /* Integer load/store : only access allowed */
784 break;
785 case ACCESS_CODE:
786 /* No code fetch is allowed in direct-store areas */
787 return -4;
788 case ACCESS_FLOAT:
789 /* Floating point load/store */
790 return -4;
791 case ACCESS_RES:
792 /* lwarx, ldarx or srwcx. */
793 return -4;
794 case ACCESS_CACHE:
795 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
796 /* Should make the instruction do no-op.
797 * As it already do no-op, it's quite easy :-)
798 */
799 ctx->raddr = eaddr;
800 return 0;
801 case ACCESS_EXT:
802 /* eciwx or ecowx */
803 return -4;
804 default:
805 if (logfile) {
806 fprintf(logfile, "ERROR: instruction should not need "
807 "address translation\n");
808 }
809 return -4;
810 }
811 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
812 ctx->raddr = eaddr;
813 ret = 2;
814 } else {
815 ret = -2;
816 }
817 }
818
819 return ret;
820 }
821
822 /* Generic TLB check function for embedded PowerPC implementations */
823 static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
824 target_phys_addr_t *raddrp,
825 target_ulong address,
826 uint32_t pid, int ext, int i)
827 {
828 target_ulong mask;
829
830 /* Check valid flag */
831 if (!(tlb->prot & PAGE_VALID)) {
832 if (loglevel != 0)
833 fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
834 return -1;
835 }
836 mask = ~(tlb->size - 1);
837 if (loglevel != 0) {
838 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
839 ADDRX " " ADDRX " %d\n",
840 __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
841 }
842 /* Check PID */
843 if (tlb->PID != 0 && tlb->PID != pid)
844 return -1;
845 /* Check effective address */
846 if ((address & mask) != tlb->EPN)
847 return -1;
848 *raddrp = (tlb->RPN & mask) | (address & ~mask);
849 #if (TARGET_PHYS_ADDR_BITS >= 36)
850 if (ext) {
851 /* Extend the physical address to 36 bits */
852 *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
853 }
854 #endif
855
856 return 0;
857 }
858
859 /* Generic TLB search function for PowerPC embedded implementations */
860 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
861 {
862 ppcemb_tlb_t *tlb;
863 target_phys_addr_t raddr;
864 int i, ret;
865
866 /* Default return value is no match */
867 ret = -1;
868 for (i = 0; i < env->nb_tlb; i++) {
869 tlb = &env->tlb[i].tlbe;
870 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
871 ret = i;
872 break;
873 }
874 }
875
876 return ret;
877 }
878
879 void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
880 uint32_t pid)
881 {
882 ppcemb_tlb_t *tlb;
883 target_phys_addr_t raddr;
884 target_ulong page, end;
885 int i;
886
887 for (i = 0; i < env->nb_tlb; i++) {
888 tlb = &env->tlb[i].tlbe;
889 if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
890 end = tlb->EPN + tlb->size;
891 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
892 tlb_flush_page(env, page);
893 tlb->prot &= ~PAGE_VALID;
894 break;
895 }
896 }
897 }
898
899 /* Helpers specific to PowerPC 40x implementations */
900 void ppc4xx_tlb_invalidate_all (CPUState *env)
901 {
902 ppcemb_tlb_t *tlb;
903 int i;
904
905 for (i = 0; i < env->nb_tlb; i++) {
906 tlb = &env->tlb[i].tlbe;
907 if (tlb->prot & PAGE_VALID) {
908 #if 0 // XXX: TLB have variable sizes then we flush all Qemu TLB.
909 end = tlb->EPN + tlb->size;
910 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
911 tlb_flush_page(env, page);
912 #endif
913 tlb->prot &= ~PAGE_VALID;
914 }
915 }
916 tlb_flush(env, 1);
917 }
918
919 int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
920 target_ulong address, int rw, int access_type)
921 {
922 ppcemb_tlb_t *tlb;
923 target_phys_addr_t raddr;
924 int i, ret, zsel, zpr;
925
926 ret = -1;
927 raddr = -1;
928 for (i = 0; i < env->nb_tlb; i++) {
929 tlb = &env->tlb[i].tlbe;
930 if (ppcemb_tlb_check(env, tlb, &raddr, address,
931 env->spr[SPR_40x_PID], 0, i) < 0)
932 continue;
933 zsel = (tlb->attr >> 4) & 0xF;
934 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
935 if (loglevel != 0) {
936 fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
937 __func__, i, zsel, zpr, rw, tlb->attr);
938 }
939 if (access_type == ACCESS_CODE) {
940 /* Check execute enable bit */
941 switch (zpr) {
942 case 0x2:
943 if (msr_pr)
944 goto check_exec_perm;
945 goto exec_granted;
946 case 0x0:
947 if (msr_pr) {
948 ctx->prot = 0;
949 ret = -3;
950 break;
951 }
952 /* No break here */
953 case 0x1:
954 check_exec_perm:
955 /* Check from TLB entry */
956 if (!(tlb->prot & PAGE_EXEC)) {
957 ret = -3;
958 } else {
959 if (tlb->prot & PAGE_WRITE) {
960 ctx->prot = PAGE_READ | PAGE_WRITE;
961 } else {
962 ctx->prot = PAGE_READ;
963 }
964 ret = 0;
965 }
966 break;
967 case 0x3:
968 exec_granted:
969 /* All accesses granted */
970 ctx->prot = PAGE_READ | PAGE_WRITE;
971 ret = 0;
972 break;
973 }
974 } else {
975 switch (zpr) {
976 case 0x2:
977 if (msr_pr)
978 goto check_rw_perm;
979 goto rw_granted;
980 case 0x0:
981 if (msr_pr) {
982 ctx->prot = 0;
983 ret = -2;
984 break;
985 }
986 /* No break here */
987 case 0x1:
988 check_rw_perm:
989 /* Check from TLB entry */
990 /* Check write protection bit */
991 if (tlb->prot & PAGE_WRITE) {
992 ctx->prot = PAGE_READ | PAGE_WRITE;
993 ret = 0;
994 } else {
995 ctx->prot = PAGE_READ;
996 if (rw)
997 ret = -2;
998 else
999 ret = 0;
1000 }
1001 break;
1002 case 0x3:
1003 rw_granted:
1004 /* All accesses granted */
1005 ctx->prot = PAGE_READ | PAGE_WRITE;
1006 ret = 0;
1007 break;
1008 }
1009 }
1010 if (ret >= 0) {
1011 ctx->raddr = raddr;
1012 if (loglevel != 0) {
1013 fprintf(logfile, "%s: access granted " ADDRX " => " REGX
1014 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1015 ret);
1016 }
1017 return 0;
1018 }
1019 }
1020 if (loglevel != 0) {
1021 fprintf(logfile, "%s: access refused " ADDRX " => " REGX
1022 " %d %d\n", __func__, address, raddr, ctx->prot,
1023 ret);
1024 }
1025
1026 return ret;
1027 }
1028
1029 void store_40x_sler (CPUPPCState *env, uint32_t val)
1030 {
1031 /* XXX: TO BE FIXED */
1032 if (val != 0x00000000) {
1033 cpu_abort(env, "Little-endian regions are not supported by now\n");
1034 }
1035 env->spr[SPR_405_SLER] = val;
1036 }
1037
1038 int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1039 target_ulong address, int rw,
1040 int access_type)
1041 {
1042 ppcemb_tlb_t *tlb;
1043 target_phys_addr_t raddr;
1044 int i, prot, ret;
1045
1046 ret = -1;
1047 raddr = -1;
1048 for (i = 0; i < env->nb_tlb; i++) {
1049 tlb = &env->tlb[i].tlbe;
1050 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1051 env->spr[SPR_BOOKE_PID], 1, i) < 0)
1052 continue;
1053 if (msr_pr)
1054 prot = tlb->prot & 0xF;
1055 else
1056 prot = (tlb->prot >> 4) & 0xF;
1057 /* Check the address space */
1058 if (access_type == ACCESS_CODE) {
1059 if (msr_is != (tlb->attr & 1))
1060 continue;
1061 ctx->prot = prot;
1062 if (prot & PAGE_EXEC) {
1063 ret = 0;
1064 break;
1065 }
1066 ret = -3;
1067 } else {
1068 if (msr_ds != (tlb->attr & 1))
1069 continue;
1070 ctx->prot = prot;
1071 if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1072 ret = 0;
1073 break;
1074 }
1075 ret = -2;
1076 }
1077 }
1078 if (ret >= 0)
1079 ctx->raddr = raddr;
1080
1081 return ret;
1082 }
1083
1084 static int check_physical (CPUState *env, mmu_ctx_t *ctx,
1085 target_ulong eaddr, int rw)
1086 {
1087 int in_plb, ret;
1088
1089 ctx->raddr = eaddr;
1090 ctx->prot = PAGE_READ;
1091 ret = 0;
1092 switch (env->mmu_model) {
1093 case POWERPC_MMU_32B:
1094 case POWERPC_MMU_SOFT_6xx:
1095 case POWERPC_MMU_601:
1096 case POWERPC_MMU_SOFT_4xx:
1097 case POWERPC_MMU_REAL_4xx:
1098 ctx->prot |= PAGE_WRITE;
1099 break;
1100 #if defined(TARGET_PPC64)
1101 case POWERPC_MMU_64B:
1102 case POWERPC_MMU_64BRIDGE:
1103 /* Real address are 60 bits long */
1104 ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
1105 ctx->prot |= PAGE_WRITE;
1106 break;
1107 #endif
1108 case POWERPC_MMU_SOFT_4xx_Z:
1109 if (unlikely(msr_pe != 0)) {
1110 /* 403 family add some particular protections,
1111 * using PBL/PBU registers for accesses with no translation.
1112 */
1113 in_plb =
1114 /* Check PLB validity */
1115 (env->pb[0] < env->pb[1] &&
1116 /* and address in plb area */
1117 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1118 (env->pb[2] < env->pb[3] &&
1119 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1120 if (in_plb ^ msr_px) {
1121 /* Access in protected area */
1122 if (rw == 1) {
1123 /* Access is not allowed */
1124 ret = -2;
1125 }
1126 } else {
1127 /* Read-write access is allowed */
1128 ctx->prot |= PAGE_WRITE;
1129 }
1130 }
1131 break;
1132 case POWERPC_MMU_BOOKE:
1133 ctx->prot |= PAGE_WRITE;
1134 break;
1135 case POWERPC_MMU_BOOKE_FSL:
1136 /* XXX: TODO */
1137 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1138 break;
1139 default:
1140 cpu_abort(env, "Unknown or invalid MMU model\n");
1141 return -1;
1142 }
1143
1144 return ret;
1145 }
1146
1147 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1148 int rw, int access_type, int check_BATs)
1149 {
1150 int ret;
1151 #if 0
1152 if (loglevel != 0) {
1153 fprintf(logfile, "%s\n", __func__);
1154 }
1155 #endif
1156 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1157 (access_type != ACCESS_CODE && msr_dr == 0)) {
1158 /* No address translation */
1159 ret = check_physical(env, ctx, eaddr, rw);
1160 } else {
1161 ret = -1;
1162 switch (env->mmu_model) {
1163 case POWERPC_MMU_32B:
1164 case POWERPC_MMU_SOFT_6xx:
1165 /* Try to find a BAT */
1166 if (check_BATs)
1167 ret = get_bat(env, ctx, eaddr, rw, access_type);
1168 /* No break here */
1169 #if defined(TARGET_PPC64)
1170 case POWERPC_MMU_64B:
1171 case POWERPC_MMU_64BRIDGE:
1172 #endif
1173 if (ret < 0) {
1174 /* We didn't match any BAT entry or don't have BATs */
1175 ret = get_segment(env, ctx, eaddr, rw, access_type);
1176 }
1177 break;
1178 case POWERPC_MMU_SOFT_4xx:
1179 case POWERPC_MMU_SOFT_4xx_Z:
1180 ret = mmu40x_get_physical_address(env, ctx, eaddr,
1181 rw, access_type);
1182 break;
1183 case POWERPC_MMU_601:
1184 /* XXX: TODO */
1185 cpu_abort(env, "601 MMU model not implemented\n");
1186 return -1;
1187 case POWERPC_MMU_BOOKE:
1188 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1189 rw, access_type);
1190 break;
1191 case POWERPC_MMU_BOOKE_FSL:
1192 /* XXX: TODO */
1193 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1194 return -1;
1195 case POWERPC_MMU_REAL_4xx:
1196 cpu_abort(env, "PowerPC 401 does not do any translation\n");
1197 return -1;
1198 default:
1199 cpu_abort(env, "Unknown or invalid MMU model\n");
1200 return -1;
1201 }
1202 }
1203 #if 0
1204 if (loglevel != 0) {
1205 fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
1206 __func__, eaddr, ret, ctx->raddr);
1207 }
1208 #endif
1209
1210 return ret;
1211 }
1212
1213 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
1214 {
1215 mmu_ctx_t ctx;
1216
1217 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
1218 return -1;
1219
1220 return ctx.raddr & TARGET_PAGE_MASK;
1221 }
1222
1223 /* Perform address translation */
1224 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1225 int is_user, int is_softmmu)
1226 {
1227 mmu_ctx_t ctx;
1228 int exception = 0, error_code = 0;
1229 int access_type;
1230 int ret = 0;
1231
1232 if (rw == 2) {
1233 /* code access */
1234 rw = 0;
1235 access_type = ACCESS_CODE;
1236 } else {
1237 /* data access */
1238 /* XXX: put correct access by using cpu_restore_state()
1239 correctly */
1240 access_type = ACCESS_INT;
1241 // access_type = env->access_type;
1242 }
1243 ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
1244 if (ret == 0) {
1245 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
1246 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1247 is_user, is_softmmu);
1248 } else if (ret < 0) {
1249 #if defined (DEBUG_MMU)
1250 if (loglevel != 0)
1251 cpu_dump_state(env, logfile, fprintf, 0);
1252 #endif
1253 if (access_type == ACCESS_CODE) {
1254 exception = POWERPC_EXCP_ISI;
1255 switch (ret) {
1256 case -1:
1257 /* No matches in page tables or TLB */
1258 switch (env->mmu_model) {
1259 case POWERPC_MMU_SOFT_6xx:
1260 exception = POWERPC_EXCP_IFTLB;
1261 env->spr[SPR_IMISS] = address;
1262 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1263 error_code = 1 << 18;
1264 goto tlb_miss;
1265 case POWERPC_MMU_SOFT_4xx:
1266 case POWERPC_MMU_SOFT_4xx_Z:
1267 exception = POWERPC_EXCP_ITLB;
1268 error_code = 0;
1269 env->spr[SPR_40x_DEAR] = address;
1270 env->spr[SPR_40x_ESR] = 0x00000000;
1271 break;
1272 case POWERPC_MMU_32B:
1273 error_code = 0x40000000;
1274 break;
1275 #if defined(TARGET_PPC64)
1276 case POWERPC_MMU_64B:
1277 /* XXX: TODO */
1278 cpu_abort(env, "MMU model not implemented\n");
1279 return -1;
1280 case POWERPC_MMU_64BRIDGE:
1281 /* XXX: TODO */
1282 cpu_abort(env, "MMU model not implemented\n");
1283 return -1;
1284 #endif
1285 case POWERPC_MMU_601:
1286 /* XXX: TODO */
1287 cpu_abort(env, "MMU model not implemented\n");
1288 return -1;
1289 case POWERPC_MMU_BOOKE:
1290 /* XXX: TODO */
1291 cpu_abort(env, "MMU model not implemented\n");
1292 return -1;
1293 case POWERPC_MMU_BOOKE_FSL:
1294 /* XXX: TODO */
1295 cpu_abort(env, "MMU model not implemented\n");
1296 return -1;
1297 case POWERPC_MMU_REAL_4xx:
1298 cpu_abort(env, "PowerPC 401 should never raise any MMU "
1299 "exceptions\n");
1300 return -1;
1301 default:
1302 cpu_abort(env, "Unknown or invalid MMU model\n");
1303 return -1;
1304 }
1305 break;
1306 case -2:
1307 /* Access rights violation */
1308 error_code = 0x08000000;
1309 break;
1310 case -3:
1311 /* No execute protection violation */
1312 error_code = 0x10000000;
1313 break;
1314 case -4:
1315 /* Direct store exception */
1316 /* No code fetch is allowed in direct-store areas */
1317 error_code = 0x10000000;
1318 break;
1319 #if defined(TARGET_PPC64)
1320 case -5:
1321 /* No match in segment table */
1322 exception = POWERPC_EXCP_ISEG;
1323 error_code = 0;
1324 break;
1325 #endif
1326 }
1327 } else {
1328 exception = POWERPC_EXCP_DSI;
1329 switch (ret) {
1330 case -1:
1331 /* No matches in page tables or TLB */
1332 switch (env->mmu_model) {
1333 case POWERPC_MMU_SOFT_6xx:
1334 if (rw == 1) {
1335 exception = POWERPC_EXCP_DSTLB;
1336 error_code = 1 << 16;
1337 } else {
1338 exception = POWERPC_EXCP_DLTLB;
1339 error_code = 0;
1340 }
1341 env->spr[SPR_DMISS] = address;
1342 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1343 tlb_miss:
1344 error_code |= ctx.key << 19;
1345 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1346 env->spr[SPR_HASH2] = ctx.pg_addr[1];
1347 /* Do not alter DAR nor DSISR */
1348 goto out;
1349 case POWERPC_MMU_SOFT_4xx:
1350 case POWERPC_MMU_SOFT_4xx_Z:
1351 exception = POWERPC_EXCP_DTLB;
1352 error_code = 0;
1353 env->spr[SPR_40x_DEAR] = address;
1354 if (rw)
1355 env->spr[SPR_40x_ESR] = 0x00800000;
1356 else
1357 env->spr[SPR_40x_ESR] = 0x00000000;
1358 break;
1359 case POWERPC_MMU_32B:
1360 error_code = 0x40000000;
1361 break;
1362 #if defined(TARGET_PPC64)
1363 case POWERPC_MMU_64B:
1364 /* XXX: TODO */
1365 cpu_abort(env, "MMU model not implemented\n");
1366 return -1;
1367 case POWERPC_MMU_64BRIDGE:
1368 /* XXX: TODO */
1369 cpu_abort(env, "MMU model not implemented\n");
1370 return -1;
1371 #endif
1372 case POWERPC_MMU_601:
1373 /* XXX: TODO */
1374 cpu_abort(env, "MMU model not implemented\n");
1375 return -1;
1376 case POWERPC_MMU_BOOKE:
1377 /* XXX: TODO */
1378 cpu_abort(env, "MMU model not implemented\n");
1379 return -1;
1380 case POWERPC_MMU_BOOKE_FSL:
1381 /* XXX: TODO */
1382 cpu_abort(env, "MMU model not implemented\n");
1383 return -1;
1384 case POWERPC_MMU_REAL_4xx:
1385 cpu_abort(env, "PowerPC 401 should never raise any MMU "
1386 "exceptions\n");
1387 return -1;
1388 default:
1389 cpu_abort(env, "Unknown or invalid MMU model\n");
1390 return -1;
1391 }
1392 break;
1393 case -2:
1394 /* Access rights violation */
1395 error_code = 0x08000000;
1396 break;
1397 case -4:
1398 /* Direct store exception */
1399 switch (access_type) {
1400 case ACCESS_FLOAT:
1401 /* Floating point load/store */
1402 exception = POWERPC_EXCP_ALIGN;
1403 error_code = POWERPC_EXCP_ALIGN_FP;
1404 break;
1405 case ACCESS_RES:
1406 /* lwarx, ldarx or srwcx. */
1407 error_code = 0x04000000;
1408 break;
1409 case ACCESS_EXT:
1410 /* eciwx or ecowx */
1411 error_code = 0x04100000;
1412 break;
1413 default:
1414 printf("DSI: invalid exception (%d)\n", ret);
1415 exception = POWERPC_EXCP_PROGRAM;
1416 error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1417 break;
1418 }
1419 break;
1420 #if defined(TARGET_PPC64)
1421 case -5:
1422 /* No match in segment table */
1423 exception = POWERPC_EXCP_DSEG;
1424 error_code = 0;
1425 break;
1426 #endif
1427 }
1428 if (exception == POWERPC_EXCP_DSI && rw == 1)
1429 error_code |= 0x02000000;
1430 /* Store fault address */
1431 env->spr[SPR_DAR] = address;
1432 env->spr[SPR_DSISR] = error_code;
1433 }
1434 out:
1435 #if 0
1436 printf("%s: set exception to %d %02x\n",
1437 __func__, exception, error_code);
1438 #endif
1439 env->exception_index = exception;
1440 env->error_code = error_code;
1441 ret = 1;
1442 }
1443
1444 return ret;
1445 }
1446
1447 /*****************************************************************************/
1448 /* BATs management */
1449 #if !defined(FLUSH_ALL_TLBS)
1450 static inline void do_invalidate_BAT (CPUPPCState *env,
1451 target_ulong BATu, target_ulong mask)
1452 {
1453 target_ulong base, end, page;
1454
1455 base = BATu & ~0x0001FFFF;
1456 end = base + mask + 0x00020000;
1457 #if defined (DEBUG_BATS)
1458 if (loglevel != 0) {
1459 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
1460 base, end, mask);
1461 }
1462 #endif
1463 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1464 tlb_flush_page(env, page);
1465 #if defined (DEBUG_BATS)
1466 if (loglevel != 0)
1467 fprintf(logfile, "Flush done\n");
1468 #endif
1469 }
1470 #endif
1471
1472 static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
1473 target_ulong value)
1474 {
1475 #if defined (DEBUG_BATS)
1476 if (loglevel != 0) {
1477 fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1478 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
1479 }
1480 #endif
1481 }
1482
1483 target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1484 {
1485 return env->IBAT[0][nr];
1486 }
1487
1488 target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1489 {
1490 return env->IBAT[1][nr];
1491 }
1492
1493 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1494 {
1495 target_ulong mask;
1496
1497 dump_store_bat(env, 'I', 0, nr, value);
1498 if (env->IBAT[0][nr] != value) {
1499 mask = (value << 15) & 0x0FFE0000UL;
1500 #if !defined(FLUSH_ALL_TLBS)
1501 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1502 #endif
1503 /* When storing valid upper BAT, mask BEPI and BRPN
1504 * and invalidate all TLBs covered by this BAT
1505 */
1506 mask = (value << 15) & 0x0FFE0000UL;
1507 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1508 (value & ~0x0001FFFFUL & ~mask);
1509 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1510 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1511 #if !defined(FLUSH_ALL_TLBS)
1512 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1513 #else
1514 tlb_flush(env, 1);
1515 #endif
1516 }
1517 }
1518
1519 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1520 {
1521 dump_store_bat(env, 'I', 1, nr, value);
1522 env->IBAT[1][nr] = value;
1523 }
1524
1525 target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1526 {
1527 return env->DBAT[0][nr];
1528 }
1529
1530 target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1531 {
1532 return env->DBAT[1][nr];
1533 }
1534
1535 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1536 {
1537 target_ulong mask;
1538
1539 dump_store_bat(env, 'D', 0, nr, value);
1540 if (env->DBAT[0][nr] != value) {
1541 /* When storing valid upper BAT, mask BEPI and BRPN
1542 * and invalidate all TLBs covered by this BAT
1543 */
1544 mask = (value << 15) & 0x0FFE0000UL;
1545 #if !defined(FLUSH_ALL_TLBS)
1546 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1547 #endif
1548 mask = (value << 15) & 0x0FFE0000UL;
1549 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1550 (value & ~0x0001FFFFUL & ~mask);
1551 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1552 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1553 #if !defined(FLUSH_ALL_TLBS)
1554 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1555 #else
1556 tlb_flush(env, 1);
1557 #endif
1558 }
1559 }
1560
1561 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1562 {
1563 dump_store_bat(env, 'D', 1, nr, value);
1564 env->DBAT[1][nr] = value;
1565 }
1566
1567
1568 /*****************************************************************************/
1569 /* TLB management */
1570 void ppc_tlb_invalidate_all (CPUPPCState *env)
1571 {
1572 if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
1573 ppc6xx_tlb_invalidate_all(env);
1574 } else if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_4xx)) {
1575 ppc4xx_tlb_invalidate_all(env);
1576 } else {
1577 tlb_flush(env, 1);
1578 }
1579 }
1580
1581 /*****************************************************************************/
1582 /* Special registers manipulation */
1583 #if defined(TARGET_PPC64)
1584 target_ulong ppc_load_asr (CPUPPCState *env)
1585 {
1586 return env->asr;
1587 }
1588
1589 void ppc_store_asr (CPUPPCState *env, target_ulong value)
1590 {
1591 if (env->asr != value) {
1592 env->asr = value;
1593 tlb_flush(env, 1);
1594 }
1595 }
1596 #endif
1597
1598 target_ulong do_load_sdr1 (CPUPPCState *env)
1599 {
1600 return env->sdr1;
1601 }
1602
1603 void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1604 {
1605 #if defined (DEBUG_MMU)
1606 if (loglevel != 0) {
1607 fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
1608 }
1609 #endif
1610 if (env->sdr1 != value) {
1611 env->sdr1 = value;
1612 tlb_flush(env, 1);
1613 }
1614 }
1615
1616 target_ulong do_load_sr (CPUPPCState *env, int srnum)
1617 {
1618 return env->sr[srnum];
1619 }
1620
1621 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1622 {
1623 #if defined (DEBUG_MMU)
1624 if (loglevel != 0) {
1625 fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1626 __func__, srnum, value, env->sr[srnum]);
1627 }
1628 #endif
1629 if (env->sr[srnum] != value) {
1630 env->sr[srnum] = value;
1631 #if !defined(FLUSH_ALL_TLBS) && 0
1632 {
1633 target_ulong page, end;
1634 /* Invalidate 256 MB of virtual memory */
1635 page = (16 << 20) * srnum;
1636 end = page + (16 << 20);
1637 for (; page != end; page += TARGET_PAGE_SIZE)
1638 tlb_flush_page(env, page);
1639 }
1640 #else
1641 tlb_flush(env, 1);
1642 #endif
1643 }
1644 }
1645 #endif /* !defined (CONFIG_USER_ONLY) */
1646
1647 uint32_t ppc_load_xer (CPUPPCState *env)
1648 {
1649 return (xer_so << XER_SO) |
1650 (xer_ov << XER_OV) |
1651 (xer_ca << XER_CA) |
1652 (xer_bc << XER_BC) |
1653 (xer_cmp << XER_CMP);
1654 }
1655
1656 void ppc_store_xer (CPUPPCState *env, uint32_t value)
1657 {
1658 xer_so = (value >> XER_SO) & 0x01;
1659 xer_ov = (value >> XER_OV) & 0x01;
1660 xer_ca = (value >> XER_CA) & 0x01;
1661 xer_cmp = (value >> XER_CMP) & 0xFF;
1662 xer_bc = (value >> XER_BC) & 0x7F;
1663 }
1664
1665 /* Swap temporary saved registers with GPRs */
1666 static inline void swap_gpr_tgpr (CPUPPCState *env)
1667 {
1668 ppc_gpr_t tmp;
1669
1670 tmp = env->gpr[0];
1671 env->gpr[0] = env->tgpr[0];
1672 env->tgpr[0] = tmp;
1673 tmp = env->gpr[1];
1674 env->gpr[1] = env->tgpr[1];
1675 env->tgpr[1] = tmp;
1676 tmp = env->gpr[2];
1677 env->gpr[2] = env->tgpr[2];
1678 env->tgpr[2] = tmp;
1679 tmp = env->gpr[3];
1680 env->gpr[3] = env->tgpr[3];
1681 env->tgpr[3] = tmp;
1682 }
1683
1684 /* GDBstub can read and write MSR... */
1685 target_ulong do_load_msr (CPUPPCState *env)
1686 {
1687 return
1688 #if defined (TARGET_PPC64)
1689 ((target_ulong)msr_sf << MSR_SF) |
1690 ((target_ulong)msr_isf << MSR_ISF) |
1691 ((target_ulong)msr_hv << MSR_HV) |
1692 #endif
1693 ((target_ulong)msr_ucle << MSR_UCLE) |
1694 ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
1695 ((target_ulong)msr_ap << MSR_AP) |
1696 ((target_ulong)msr_sa << MSR_SA) |
1697 ((target_ulong)msr_key << MSR_KEY) |
1698 ((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
1699 ((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
1700 ((target_ulong)msr_ile << MSR_ILE) |
1701 ((target_ulong)msr_ee << MSR_EE) |
1702 ((target_ulong)msr_pr << MSR_PR) |
1703 ((target_ulong)msr_fp << MSR_FP) |
1704 ((target_ulong)msr_me << MSR_ME) |
1705 ((target_ulong)msr_fe0 << MSR_FE0) |
1706 ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
1707 ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
1708 ((target_ulong)msr_fe1 << MSR_FE1) |
1709 ((target_ulong)msr_al << MSR_AL) |
1710 ((target_ulong)msr_ip << MSR_IP) |
1711 ((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
1712 ((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
1713 ((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
1714 ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
1715 ((target_ulong)msr_ri << MSR_RI) |
1716 ((target_ulong)msr_le << MSR_LE);
1717 }
1718
1719 void do_store_msr (CPUPPCState *env, target_ulong value)
1720 {
1721 int enter_pm;
1722
1723 value &= env->msr_mask;
1724 if (((value >> MSR_IR) & 1) != msr_ir ||
1725 ((value >> MSR_DR) & 1) != msr_dr) {
1726 /* Flush all tlb when changing translation mode */
1727 tlb_flush(env, 1);
1728 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1729 }
1730 #if 0
1731 if (loglevel != 0) {
1732 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
1733 }
1734 #endif
1735 switch (env->excp_model) {
1736 case POWERPC_EXCP_602:
1737 case POWERPC_EXCP_603:
1738 case POWERPC_EXCP_603E:
1739 case POWERPC_EXCP_G2:
1740 if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
1741 /* Swap temporary saved registers with GPRs */
1742 swap_gpr_tgpr(env);
1743 }
1744 break;
1745 default:
1746 break;
1747 }
1748 #if defined (TARGET_PPC64)
1749 msr_sf = (value >> MSR_SF) & 1;
1750 msr_isf = (value >> MSR_ISF) & 1;
1751 msr_hv = (value >> MSR_HV) & 1;
1752 #endif
1753 msr_ucle = (value >> MSR_UCLE) & 1;
1754 msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
1755 msr_ap = (value >> MSR_AP) & 1;
1756 msr_sa = (value >> MSR_SA) & 1;
1757 msr_key = (value >> MSR_KEY) & 1;
1758 msr_pow = (value >> MSR_POW) & 1; /* POW / WE */
1759 msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */
1760 msr_ile = (value >> MSR_ILE) & 1;
1761 msr_ee = (value >> MSR_EE) & 1;
1762 msr_pr = (value >> MSR_PR) & 1;
1763 msr_fp = (value >> MSR_FP) & 1;
1764 msr_me = (value >> MSR_ME) & 1;
1765 msr_fe0 = (value >> MSR_FE0) & 1;
1766 msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
1767 msr_be = (value >> MSR_BE) & 1; /* BE / DE */
1768 msr_fe1 = (value >> MSR_FE1) & 1;
1769 msr_al = (value >> MSR_AL) & 1;
1770 msr_ip = (value >> MSR_IP) & 1;
1771 msr_ir = (value >> MSR_IR) & 1; /* IR / IS */
1772 msr_dr = (value >> MSR_DR) & 1; /* DR / DS */
1773 msr_pe = (value >> MSR_PE) & 1; /* PE / EP */
1774 msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
1775 msr_ri = (value >> MSR_RI) & 1;
1776 msr_le = (value >> MSR_LE) & 1;
1777 do_compute_hflags(env);
1778
1779 enter_pm = 0;
1780 switch (env->excp_model) {
1781 case POWERPC_EXCP_603:
1782 case POWERPC_EXCP_603E:
1783 case POWERPC_EXCP_G2:
1784 /* Don't handle SLEEP mode: we should disable all clocks...
1785 * No dynamic power-management.
1786 */
1787 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
1788 enter_pm = 1;
1789 break;
1790 case POWERPC_EXCP_604:
1791 if (msr_pow == 1)
1792 enter_pm = 1;
1793 break;
1794 case POWERPC_EXCP_7x0:
1795 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
1796 enter_pm = 1;
1797 break;
1798 default:
1799 break;
1800 }
1801 if (enter_pm) {
1802 if (likely(!env->halted)) {
1803 /* power save: exit cpu loop */
1804 env->halted = 1;
1805 env->exception_index = EXCP_HLT;
1806 cpu_loop_exit();
1807 }
1808 }
1809 }
1810
1811 #if defined(TARGET_PPC64)
1812 void ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
1813 {
1814 do_store_msr(env,
1815 (do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF));
1816 }
1817 #endif
1818
1819 void do_compute_hflags (CPUPPCState *env)
1820 {
1821 /* Compute current hflags */
1822 env->hflags = (msr_vr << MSR_VR) |
1823 (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
1824 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
1825 (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
1826 #if defined (TARGET_PPC64)
1827 env->hflags |= msr_cm << MSR_CM;
1828 env->hflags |= (uint64_t)msr_sf << MSR_SF;
1829 env->hflags |= (uint64_t)msr_hv << MSR_HV;
1830 #endif
1831 }
1832
1833 /*****************************************************************************/
1834 /* Exception processing */
1835 #if defined (CONFIG_USER_ONLY)
1836 void do_interrupt (CPUState *env)
1837 {
1838 env->exception_index = POWERPC_EXCP_NONE;
1839 env->error_code = 0;
1840 }
1841
1842 void ppc_hw_interrupt (CPUState *env)
1843 {
1844 env->exception_index = POWERPC_EXCP_NONE;
1845 env->error_code = 0;
1846 }
1847 #else /* defined (CONFIG_USER_ONLY) */
1848 static void dump_syscall (CPUState *env)
1849 {
1850 fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1851 " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
1852 env->gpr[0], env->gpr[3], env->gpr[4],
1853 env->gpr[5], env->gpr[6], env->nip);
1854 }
1855
1856 /* Note that this function should be greatly optimized
1857 * when called with a constant excp, from ppc_hw_interrupt
1858 */
1859 static always_inline void powerpc_excp (CPUState *env,
1860 int excp_model, int excp)
1861 {
1862 target_ulong msr, vector;
1863 int srr0, srr1, asrr0, asrr1;
1864
1865 if (loglevel & CPU_LOG_INT) {
1866 fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1867 env->nip, excp, env->error_code);
1868 }
1869 msr = do_load_msr(env);
1870 srr0 = SPR_SRR0;
1871 srr1 = SPR_SRR1;
1872 asrr0 = -1;
1873 asrr1 = -1;
1874 msr &= ~((target_ulong)0x783F0000);
1875 switch (excp) {
1876 case POWERPC_EXCP_NONE:
1877 /* Should never happen */
1878 return;
1879 case POWERPC_EXCP_CRITICAL: /* Critical input */
1880 msr_ri = 0; /* XXX: check this */
1881 switch (excp_model) {
1882 case POWERPC_EXCP_40x:
1883 srr0 = SPR_40x_SRR2;
1884 srr1 = SPR_40x_SRR3;
1885 break;
1886 case POWERPC_EXCP_BOOKE:
1887 srr0 = SPR_BOOKE_CSRR0;
1888 srr1 = SPR_BOOKE_CSRR1;
1889 break;
1890 case POWERPC_EXCP_G2:
1891 break;
1892 default:
1893 goto excp_invalid;
1894 }
1895 goto store_next;
1896 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1897 if (msr_me == 0) {
1898 /* Machine check exception is not enabled */
1899 /* XXX: we may just stop the processor here, to allow debugging */
1900 excp = POWERPC_EXCP_RESET;
1901 goto excp_reset;
1902 }
1903 msr_ri = 0;
1904 msr_me = 0;
1905 #if defined(TARGET_PPC64H)
1906 msr_hv = 1;
1907 #endif
1908 /* XXX: should also have something loaded in DAR / DSISR */
1909 switch (excp_model) {
1910 case POWERPC_EXCP_40x:
1911 srr0 = SPR_40x_SRR2;
1912 srr1 = SPR_40x_SRR3;
1913 break;
1914 case POWERPC_EXCP_BOOKE:
1915 srr0 = SPR_BOOKE_MCSRR0;
1916 srr1 = SPR_BOOKE_MCSRR1;
1917 asrr0 = SPR_BOOKE_CSRR0;
1918 asrr1 = SPR_BOOKE_CSRR1;
1919 break;
1920 default:
1921 break;
1922 }
1923 goto store_next;
1924 case POWERPC_EXCP_DSI: /* Data storage exception */
1925 #if defined (DEBUG_EXCEPTIONS)
1926 if (loglevel != 0) {
1927 fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
1928 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1929 }
1930 #endif
1931 msr_ri = 0;
1932 #if defined(TARGET_PPC64H)
1933 if (lpes1 == 0)
1934 msr_hv = 1;
1935 #endif
1936 goto store_next;
1937 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1938 #if defined (DEBUG_EXCEPTIONS)
1939 if (loglevel != 0) {
1940 fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
1941 "\n", msr, env->nip);
1942 }
1943 #endif
1944 msr_ri = 0;
1945 #if defined(TARGET_PPC64H)
1946 if (lpes1 == 0)
1947 msr_hv = 1;
1948 #endif
1949 msr |= env->error_code;
1950 goto store_next;
1951 case POWERPC_EXCP_EXTERNAL: /* External input */
1952 msr_ri = 0;
1953 #if defined(TARGET_PPC64H)
1954 if (lpes0 == 1)
1955 msr_hv = 1;
1956 #endif
1957 goto store_next;
1958 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1959 msr_ri = 0;
1960 #if defined(TARGET_PPC64H)
1961 if (lpes1 == 0)
1962 msr_hv = 1;
1963 #endif
1964 /* XXX: this is false */
1965 /* Get rS/rD and rA from faulting opcode */
1966 env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1967 goto store_current;
1968 case POWERPC_EXCP_PROGRAM: /* Program exception */
1969 switch (env->error_code & ~0xF) {
1970 case POWERPC_EXCP_FP:
1971 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
1972 #if defined (DEBUG_EXCEPTIONS)
1973 if (loglevel != 0) {
1974 fprintf(logfile, "Ignore floating point exception\n");
1975 }
1976 #endif
1977 return;
1978 }
1979 msr_ri = 0;
1980 #if defined(TARGET_PPC64H)
1981 if (lpes1 == 0)
1982 msr_hv = 1;
1983 #endif
1984 msr |= 0x00100000;
1985 /* Set FX */
1986 env->fpscr[7] |= 0x8;
1987 /* Finally, update FEX */
1988 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1989 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1990 env->fpscr[7] |= 0x4;
1991 if (msr_fe0 != msr_fe1) {
1992 msr |= 0x00010000;
1993 goto store_current;
1994 }
1995 break;
1996 case POWERPC_EXCP_INVAL:
1997 #if defined (DEBUG_EXCEPTIONS)
1998 if (loglevel != 0) {
1999 fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
2000 env->nip);
2001 }
2002 #endif
2003 msr_ri = 0;
2004 #if defined(TARGET_PPC64H)
2005 if (lpes1 == 0)
2006 msr_hv = 1;
2007 #endif
2008 msr |= 0x00080000;
2009 break;
2010 case POWERPC_EXCP_PRIV:
2011 msr_ri = 0;
2012 #if defined(TARGET_PPC64H)
2013 if (lpes1 == 0)
2014 msr_hv = 1;
2015 #endif
2016 msr |= 0x00040000;
2017 break;
2018 case POWERPC_EXCP_TRAP:
2019 msr_ri = 0;
2020 #if defined(TARGET_PPC64H)
2021 if (lpes1 == 0)
2022 msr_hv = 1;
2023 #endif
2024 msr |= 0x00020000;
2025 break;
2026 default:
2027 /* Should never occur */
2028 cpu_abort(env, "Invalid program exception %d. Aborting\n",
2029 env->error_code);
2030 break;
2031 }
2032 goto store_next;
2033 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
2034 msr_ri = 0;
2035 #if defined(TARGET_PPC64H)
2036 if (lpes1 == 0)
2037 msr_hv = 1;
2038 #endif
2039 goto store_current;
2040 case POWERPC_EXCP_SYSCALL: /* System call exception */
2041 /* NOTE: this is a temporary hack to support graphics OSI
2042 calls from the MOL driver */
2043 /* XXX: To be removed */
2044 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2045 env->osi_call) {
2046 if (env->osi_call(env) != 0)
2047 return;
2048 }
2049 if (loglevel & CPU_LOG_INT) {
2050 dump_syscall(env);
2051 }
2052 msr_ri = 0;
2053 #if defined(TARGET_PPC64H)
2054 if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2055 msr_hv = 1;
2056 #endif
2057 goto store_next;
2058 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
2059 msr_ri = 0;
2060 goto store_current;
2061 case POWERPC_EXCP_DECR: /* Decrementer exception */
2062 msr_ri = 0;
2063 #if defined(TARGET_PPC64H)
2064 if (lpes1 == 0)
2065 msr_hv = 1;
2066 #endif
2067 goto store_next;
2068 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
2069 /* FIT on 4xx */
2070 #if defined (DEBUG_EXCEPTIONS)
2071 if (loglevel != 0)
2072 fprintf(logfile, "FIT exception\n");
2073 #endif
2074 msr_ri = 0; /* XXX: check this */
2075 goto store_next;
2076 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
2077 #if defined (DEBUG_EXCEPTIONS)
2078 if (loglevel != 0)
2079 fprintf(logfile, "WDT exception\n");
2080 #endif
2081 switch (excp_model) {
2082 case POWERPC_EXCP_BOOKE:
2083 srr0 = SPR_BOOKE_CSRR0;
2084 srr1 = SPR_BOOKE_CSRR1;
2085 break;
2086 default:
2087 break;
2088 }
2089 msr_ri = 0; /* XXX: check this */
2090 goto store_next;
2091 case POWERPC_EXCP_DTLB: /* Data TLB error */
2092 msr_ri = 0; /* XXX: check this */
2093 goto store_next;
2094 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
2095 msr_ri = 0; /* XXX: check this */
2096 goto store_next;
2097 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
2098 switch (excp_model) {
2099 case POWERPC_EXCP_BOOKE:
2100 srr0 = SPR_BOOKE_DSRR0;
2101 srr1 = SPR_BOOKE_DSRR1;
2102 asrr0 = SPR_BOOKE_CSRR0;
2103 asrr1 = SPR_BOOKE_CSRR1;
2104 break;
2105 default:
2106 break;
2107 }
2108 /* XXX: TODO */
2109 cpu_abort(env, "Debug exception is not implemented yet !\n");
2110 goto store_next;
2111 #if defined(TARGET_PPCEMB)
2112 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
2113 msr_ri = 0; /* XXX: check this */
2114 goto store_current;
2115 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
2116 /* XXX: TODO */
2117 cpu_abort(env, "Embedded floating point data exception "
2118 "is not implemented yet !\n");
2119 goto store_next;
2120 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
2121 /* XXX: TODO */
2122 cpu_abort(env, "Embedded floating point round exception "
2123 "is not implemented yet !\n");
2124 goto store_next;
2125 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
2126 msr_ri = 0;
2127 /* XXX: TODO */
2128 cpu_abort(env,
2129 "Performance counter exception is not implemented yet !\n");
2130 goto store_next;
2131 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
2132 /* XXX: TODO */
2133 cpu_abort(env,
2134 "Embedded doorbell interrupt is not implemented yet !\n");
2135 goto store_next;
2136 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
2137 switch (excp_model) {
2138 case POWERPC_EXCP_BOOKE:
2139 srr0 = SPR_BOOKE_CSRR0;
2140 srr1 = SPR_BOOKE_CSRR1;
2141 break;
2142 default:
2143 break;
2144 }
2145 /* XXX: TODO */
2146 cpu_abort(env, "Embedded doorbell critical interrupt "
2147 "is not implemented yet !\n");
2148 goto store_next;
2149 #endif /* defined(TARGET_PPCEMB) */
2150 case POWERPC_EXCP_RESET: /* System reset exception */
2151 msr_ri = 0;
2152 #if defined(TARGET_PPC64H)
2153 msr_hv = 1;
2154 #endif
2155 excp_reset:
2156 goto store_next;
2157 #if defined(TARGET_PPC64)
2158 case POWERPC_EXCP_DSEG: /* Data segment exception */
2159 msr_ri = 0;
2160 #if defined(TARGET_PPC64H)
2161 if (lpes1 == 0)
2162 msr_hv = 1;
2163 #endif
2164 /* XXX: TODO */
2165 cpu_abort(env, "Data segment exception is not implemented yet !\n");
2166 goto store_next;
2167 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
2168 msr_ri = 0;
2169 #if defined(TARGET_PPC64H)
2170 if (lpes1 == 0)
2171 msr_hv = 1;
2172 #endif
2173 /* XXX: TODO */
2174 cpu_abort(env,
2175 "Instruction segment exception is not implemented yet !\n");
2176 goto store_next;
2177 #endif /* defined(TARGET_PPC64) */
2178 #if defined(TARGET_PPC64H)
2179 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
2180 srr0 = SPR_HSRR0;
2181 srr1 = SPR_HSSR1;
2182 msr_hv = 1;
2183 goto store_next;
2184 #endif
2185 case POWERPC_EXCP_TRACE: /* Trace exception */
2186 msr_ri = 0;
2187 #if defined(TARGET_PPC64H)
2188 if (lpes1 == 0)
2189 msr_hv = 1;
2190 #endif
2191 goto store_next;
2192 #if defined(TARGET_PPC64H)
2193 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
2194 srr0 = SPR_HSRR0;
2195 srr1 = SPR_HSSR1;
2196 msr_hv = 1;
2197 goto store_next;
2198 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
2199 srr0 = SPR_HSRR0;
2200 srr1 = SPR_HSSR1;
2201 msr_hv = 1;
2202 /* XXX: TODO */
2203 cpu_abort(env, "Hypervisor instruction storage exception "
2204 "is not implemented yet !\n");
2205 goto store_next;
2206 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
2207 srr0 = SPR_HSRR0;
2208 srr1 = SPR_HSSR1;
2209 msr_hv = 1;
2210 goto store_next;
2211 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
2212 srr0 = SPR_HSRR0;
2213 srr1 = SPR_HSSR1;
2214 msr_hv = 1;
2215 goto store_next;
2216 #endif /* defined(TARGET_PPC64H) */
2217 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
2218 msr_ri = 0;
2219 #if defined(TARGET_PPC64H)
2220 if (lpes1 == 0)
2221 msr_hv = 1;
2222 #endif
2223 goto store_current;
2224 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
2225 #if defined (DEBUG_EXCEPTIONS)
2226 if (loglevel != 0)
2227 fprintf(logfile, "PIT exception\n");
2228 #endif
2229 msr_ri = 0; /* XXX: check this */
2230 goto store_next;
2231 case POWERPC_EXCP_IO: /* IO error exception */
2232 /* XXX: TODO */
2233 cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2234 goto store_next;
2235 case POWERPC_EXCP_RUNM: /* Run mode exception */
2236 /* XXX: TODO */
2237 cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2238 goto store_next;
2239 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
2240 /* XXX: TODO */
2241 cpu_abort(env, "602 emulation trap exception "
2242 "is not implemented yet !\n");
2243 goto store_next;
2244 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
2245 msr_ri = 0; /* XXX: check this */
2246 #if defined(TARGET_PPC64H) /* XXX: check this */
2247 if (lpes1 == 0)
2248 msr_hv = 1;
2249 #endif
2250 switch (excp_model) {
2251 case POWERPC_EXCP_602:
2252 case POWERPC_EXCP_603:
2253 case POWERPC_EXCP_603E:
2254 case POWERPC_EXCP_G2:
2255 goto tlb_miss_tgpr;
2256 case POWERPC_EXCP_7x5:
2257 goto tlb_miss;
2258 default:
2259 cpu_abort(env, "Invalid instruction TLB miss exception\n");
2260 break;
2261 }
2262 break;
2263 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
2264 msr_ri = 0; /* XXX: check this */
2265 #if defined(TARGET_PPC64H) /* XXX: check this */
2266 if (lpes1 == 0)
2267 msr_hv = 1;
2268 #endif
2269 switch (excp_model) {
2270 case POWERPC_EXCP_602:
2271 case POWERPC_EXCP_603:
2272 case POWERPC_EXCP_603E:
2273 case POWERPC_EXCP_G2:
2274 goto tlb_miss_tgpr;
2275 case POWERPC_EXCP_7x5:
2276 goto tlb_miss;
2277 default:
2278 cpu_abort(env, "Invalid data load TLB miss exception\n");
2279 break;
2280 }
2281 break;
2282 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
2283 msr_ri = 0; /* XXX: check this */
2284 #if defined(TARGET_PPC64H) /* XXX: check this */
2285 if (lpes1 == 0)
2286 msr_hv = 1;
2287 #endif
2288 switch (excp_model) {
2289 case POWERPC_EXCP_602:
2290 case POWERPC_EXCP_603:
2291 case POWERPC_EXCP_603E:
2292 case POWERPC_EXCP_G2:
2293 tlb_miss_tgpr:
2294 /* Swap temporary saved registers with GPRs */
2295 swap_gpr_tgpr(env);
2296 msr_tgpr = 1;
2297 goto tlb_miss;
2298 case POWERPC_EXCP_7x5:
2299 tlb_miss:
2300 #if defined (DEBUG_SOFTWARE_TLB)
2301 if (loglevel != 0) {
2302 const unsigned char *es;
2303 target_ulong *miss, *cmp;
2304 int en;
2305 if (excp == 0x1000) {
2306 es = "I";
2307 en = 'I';
2308 miss = &env->spr[SPR_IMISS];
2309 cmp = &env->spr[SPR_ICMP];
2310 } else {
2311 if (excp == 0x1100)
2312 es = "DL";
2313 else
2314 es = "DS";
2315 en = 'D';
2316 miss = &env->spr[SPR_DMISS];
2317 cmp = &env->spr[SPR_DCMP];
2318 }
2319 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2320 " H1 " ADDRX " H2 " ADDRX " %08x\n",
2321 es, en, *miss, en, *cmp,
2322 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2323 env->error_code);
2324 }
2325 #endif
2326 msr |= env->crf[0] << 28;
2327 msr |= env->error_code; /* key, D/I, S/L bits */
2328 /* Set way using a LRU mechanism */
2329 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2330 break;
2331 default:
2332 cpu_abort(env, "Invalid data store TLB miss exception\n");
2333 break;
2334 }
2335 goto store_next;
2336 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
2337 /* XXX: TODO */
2338 cpu_abort(env, "Floating point assist exception "
2339 "is not implemented yet !\n");
2340 goto store_next;
2341 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
2342 /* XXX: TODO */
2343 cpu_abort(env, "IABR exception is not implemented yet !\n");
2344 goto store_next;
2345 case POWERPC_EXCP_SMI: /* System management interrupt */
2346 /* XXX: TODO */
2347 cpu_abort(env, "SMI exception is not implemented yet !\n");
2348 goto store_next;
2349 case POWERPC_EXCP_THERM: /* Thermal interrupt */
2350 /* XXX: TODO */
2351 cpu_abort(env, "Thermal management exception "
2352 "is not implemented yet !\n");
2353 goto store_next;
2354 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
2355 msr_ri = 0;
2356 #if defined(TARGET_PPC64H)
2357 if (lpes1 == 0)
2358 msr_hv = 1;
2359 #endif
2360 /* XXX: TODO */
2361 cpu_abort(env,
2362 "Performance counter exception is not implemented yet !\n");
2363 goto store_next;
2364 case POWERPC_EXCP_VPUA: /* Vector assist exception */
2365 /* XXX: TODO */
2366 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2367 goto store_next;
2368 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
2369 /* XXX: TODO */
2370 cpu_abort(env,
2371 "970 soft-patch exception is not implemented yet !\n");
2372 goto store_next;
2373 case POWERPC_EXCP_MAINT: /* Maintenance exception */
2374 /* XXX: TODO */
2375 cpu_abort(env,
2376 "970 maintenance exception is not implemented yet !\n");
2377 goto store_next;
2378 default:
2379 excp_invalid:
2380 cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2381 break;
2382 store_current:
2383 /* save current instruction location */
2384 env->spr[srr0] = env->nip - 4;
2385 break;
2386 store_next:
2387 /* save next instruction location */
2388 env->spr[srr0] = env->nip;
2389 break;
2390 }
2391 /* Save MSR */
2392 env->spr[srr1] = msr;
2393 /* If any alternate SRR register are defined, duplicate saved values */
2394 if (asrr0 != -1)
2395 env->spr[asrr0] = env->spr[srr0];
2396 if (asrr1 != -1)
2397 env->spr[asrr1] = env->spr[srr1];
2398 /* If we disactivated any translation, flush TLBs */
2399 if (msr_ir || msr_dr)
2400 tlb_flush(env, 1);
2401 /* reload MSR with correct bits */
2402 msr_ee = 0;
2403 msr_pr = 0;
2404 msr_fp = 0;
2405 msr_fe0 = 0;
2406 msr_se = 0;
2407 msr_be = 0;
2408 msr_fe1 = 0;
2409 msr_ir = 0;
2410 msr_dr = 0;
2411 #if 0 /* Fix this: not on all targets */
2412 msr_pmm = 0;
2413 #endif
2414 msr_le = msr_ile;
2415 do_compute_hflags(env);
2416 /* Jump to handler */
2417 vector = env->excp_vectors[excp];
2418 if (vector == (target_ulong)-1) {
2419 cpu_abort(env, "Raised an exception without defined vector %d\n",
2420 excp);
2421 }
2422 vector |= env->excp_prefix;
2423 #if defined(TARGET_PPC64)
2424 if (excp_model == POWERPC_EXCP_BOOKE) {
2425 msr_cm = msr_icm;
2426 if (!msr_cm)
2427 vector = (uint32_t)vector;
2428 } else {
2429 msr_sf = msr_isf;
2430 if (!msr_sf)
2431 vector = (uint32_t)vector;
2432 }
2433 #endif
2434 env->nip = vector;
2435 /* Reset exception state */
2436 env->exception_index = POWERPC_EXCP_NONE;
2437 env->error_code = 0;
2438 }
2439
2440 void do_interrupt (CPUState *env)
2441 {
2442 powerpc_excp(env, env->excp_model, env->exception_index);
2443 }
2444
2445 void ppc_hw_interrupt (CPUPPCState *env)
2446 {
2447 #if 1
2448 if (loglevel & CPU_LOG_INT) {
2449 fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2450 __func__, env, env->pending_interrupts,
2451 env->interrupt_request, msr_me, msr_ee);
2452 }
2453 #endif
2454 /* External reset */
2455 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2456 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2457 powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2458 return;
2459 }
2460 /* Machine check exception */
2461 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2462 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2463 powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2464 return;
2465 }
2466 #if 0 /* TODO */
2467 /* External debug exception */
2468 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2469 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2470 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2471 return;
2472 }
2473 #endif
2474 #if defined(TARGET_PPC64H)
2475 if ((msr_ee != 0 || msr_hv == 0 || msr_pr == 1) & hdice != 0) {
2476 /* Hypervisor decrementer exception */
2477 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2478 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2479 powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2480 return;
2481 }
2482 }
2483 #endif
2484 if (msr_ce != 0) {
2485 /* External critical interrupt */
2486 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2487 /* Taking a critical external interrupt does not clear the external
2488 * critical interrupt status
2489 */
2490 #if 0
2491 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
2492 #endif
2493 powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2494 return;
2495 }
2496 }
2497 if (msr_ee != 0) {
2498 /* Watchdog timer on embedded PowerPC */
2499 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2500 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2501 powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2502 return;
2503 }
2504 #if defined(TARGET_PPCEMB)
2505 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2506 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2507 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2508 return;
2509 }
2510 #endif
2511 #if defined(TARGET_PPCEMB)
2512 /* External interrupt */
2513 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2514 /* Taking an external interrupt does not clear the external
2515 * interrupt status
2516 */
2517 #if 0
2518 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2519 #endif
2520 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2521 return;
2522 }
2523 #endif
2524 /* Fixed interval timer on embedded PowerPC */
2525 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2526 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2527 powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2528 return;
2529 }
2530 /* Programmable interval timer on embedded PowerPC */
2531 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2532 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2533 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2534 return;
2535 }
2536 /* Decrementer exception */
2537 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2538 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2539 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2540 return;
2541 }
2542 #if !defined(TARGET_PPCEMB)
2543 /* External interrupt */
2544 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2545 /* Taking an external interrupt does not clear the external
2546 * interrupt status
2547 */
2548 #if 0
2549 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2550 #endif
2551 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2552 return;
2553 }
2554 #endif
2555 #if defined(TARGET_PPCEMB)
2556 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2557 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2558 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2559 return;
2560 }
2561 #endif
2562 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2563 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2564 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2565 return;
2566 }
2567 /* Thermal interrupt */
2568 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2569 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2570 powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2571 return;
2572 }
2573 }
2574 }
2575 #endif /* !CONFIG_USER_ONLY */
2576
2577 void cpu_dump_EA (target_ulong EA)
2578 {
2579 FILE *f;
2580
2581 if (logfile) {
2582 f = logfile;
2583 } else {
2584 f = stdout;
2585 return;
2586 }
2587 fprintf(f, "Memory access at address " ADDRX "\n", EA);
2588 }
2589
2590 void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2591 {
2592 FILE *f;
2593
2594 if (logfile) {
2595 f = logfile;
2596 } else {
2597 f = stdout;
2598 return;
2599 }
2600 fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2601 RA, msr);
2602 }
2603
2604 void cpu_ppc_reset (void *opaque)
2605 {
2606 CPUPPCState *env;
2607 int i;
2608
2609 env = opaque;
2610 /* XXX: some of those flags initialisation values could depend
2611 * on the actual PowerPC implementation
2612 */
2613 for (i = 0; i < 63; i++)
2614 env->msr[i] = 0;
2615 #if defined(TARGET_PPC64)
2616 msr_hv = 0; /* Should be 1... */
2617 #endif
2618 msr_ap = 0; /* TO BE CHECKED */
2619 msr_sa = 0; /* TO BE CHECKED */
2620 msr_ip = 0; /* TO BE CHECKED */
2621 #if defined (DO_SINGLE_STEP) && 0
2622 /* Single step trace mode */
2623 msr_se = 1;
2624 msr_be = 1;
2625 #endif
2626 #if defined(CONFIG_USER_ONLY)
2627 msr_fp = 1; /* Allow floating point exceptions */
2628 msr_pr = 1;
2629 #else
2630 env->nip = 0xFFFFFFFC;
2631 ppc_tlb_invalidate_all(env);
2632 #endif
2633 do_compute_hflags(env);
2634 env->reserve = -1;
2635 /* Be sure no exception or interrupt is pending */
2636 env->pending_interrupts = 0;
2637 env->exception_index = POWERPC_EXCP_NONE;
2638 env->error_code = 0;
2639 /* Flush all TLBs */
2640 tlb_flush(env, 1);
2641 }
2642
2643 CPUPPCState *cpu_ppc_init (void)
2644 {
2645 CPUPPCState *env;
2646
2647 env = qemu_mallocz(sizeof(CPUPPCState));
2648 if (!env)
2649 return NULL;
2650 cpu_exec_init(env);
2651 cpu_ppc_reset(env);
2652
2653 return env;
2654 }
2655
2656 void cpu_ppc_close (CPUPPCState *env)
2657 {
2658 /* Should also remove all opcode tables... */
2659 free(env);
2660 }
Qemu copy for testing