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Avoid compilation warnings on 32 bits hosts.
[qemu.git] / target-ppc / helper.c
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30
31 //#define DEBUG_MMU
32 //#define DEBUG_BATS
33 //#define DEBUG_SOFTWARE_TLB
34 //#define DEBUG_EXCEPTIONS
35 //#define FLUSH_ALL_TLBS
36
37 /*****************************************************************************/
38 /* PowerPC MMU emulation */
39
40 #if defined(CONFIG_USER_ONLY)
41 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
42 int is_user, int is_softmmu)
43 {
44 int exception, error_code;
45
46 if (rw == 2) {
47 exception = EXCP_ISI;
48 error_code = 0;
49 } else {
50 exception = EXCP_DSI;
51 error_code = 0;
52 if (rw)
53 error_code |= 0x02000000;
54 env->spr[SPR_DAR] = address;
55 env->spr[SPR_DSISR] = error_code;
56 }
57 env->exception_index = exception;
58 env->error_code = error_code;
59
60 return 1;
61 }
62
63 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
64 {
65 return addr;
66 }
67
68 #else
69 /* Common routines used by software and hardware TLBs emulation */
70 static inline int pte_is_valid (target_ulong pte0)
71 {
72 return pte0 & 0x80000000 ? 1 : 0;
73 }
74
75 static inline void pte_invalidate (target_ulong *pte0)
76 {
77 *pte0 &= ~0x80000000;
78 }
79
80 #if defined(TARGET_PPC64)
81 static inline int pte64_is_valid (target_ulong pte0)
82 {
83 return pte0 & 0x0000000000000001ULL ? 1 : 0;
84 }
85
86 static inline void pte64_invalidate (target_ulong *pte0)
87 {
88 *pte0 &= ~0x0000000000000001ULL;
89 }
90 #endif
91
92 #define PTE_PTEM_MASK 0x7FFFFFBF
93 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
94 #if defined(TARGET_PPC64)
95 #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
96 #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
97 #endif
98
99 static inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
100 target_ulong pte0, target_ulong pte1,
101 int h, int rw)
102 {
103 target_ulong ptem, mmask;
104 int access, ret, pteh, ptev;
105
106 access = 0;
107 ret = -1;
108 /* Check validity and table match */
109 #if defined(TARGET_PPC64)
110 if (is_64b) {
111 ptev = pte64_is_valid(pte0);
112 pteh = (pte0 >> 1) & 1;
113 } else
114 #endif
115 {
116 ptev = pte_is_valid(pte0);
117 pteh = (pte0 >> 6) & 1;
118 }
119 if (ptev && h == pteh) {
120 /* Check vsid & api */
121 #if defined(TARGET_PPC64)
122 if (is_64b) {
123 ptem = pte0 & PTE64_PTEM_MASK;
124 mmask = PTE64_CHECK_MASK;
125 } else
126 #endif
127 {
128 ptem = pte0 & PTE_PTEM_MASK;
129 mmask = PTE_CHECK_MASK;
130 }
131 if (ptem == ctx->ptem) {
132 if (ctx->raddr != (target_ulong)-1) {
133 /* all matches should have equal RPN, WIMG & PP */
134 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
135 if (loglevel != 0)
136 fprintf(logfile, "Bad RPN/WIMG/PP\n");
137 return -3;
138 }
139 }
140 /* Compute access rights */
141 if (ctx->key == 0) {
142 access = PAGE_READ;
143 if ((pte1 & 0x00000003) != 0x3)
144 access |= PAGE_WRITE;
145 } else {
146 switch (pte1 & 0x00000003) {
147 case 0x0:
148 access = 0;
149 break;
150 case 0x1:
151 case 0x3:
152 access = PAGE_READ;
153 break;
154 case 0x2:
155 access = PAGE_READ | PAGE_WRITE;
156 break;
157 }
158 }
159 /* Keep the matching PTE informations */
160 ctx->raddr = pte1;
161 ctx->prot = access;
162 if ((rw == 0 && (access & PAGE_READ)) ||
163 (rw == 1 && (access & PAGE_WRITE))) {
164 /* Access granted */
165 #if defined (DEBUG_MMU)
166 if (loglevel != 0)
167 fprintf(logfile, "PTE access granted !\n");
168 #endif
169 ret = 0;
170 } else {
171 /* Access right violation */
172 #if defined (DEBUG_MMU)
173 if (loglevel != 0)
174 fprintf(logfile, "PTE access rejected\n");
175 #endif
176 ret = -2;
177 }
178 }
179 }
180
181 return ret;
182 }
183
184 static int pte32_check (mmu_ctx_t *ctx,
185 target_ulong pte0, target_ulong pte1, int h, int rw)
186 {
187 return _pte_check(ctx, 0, pte0, pte1, h, rw);
188 }
189
190 #if defined(TARGET_PPC64)
191 static int pte64_check (mmu_ctx_t *ctx,
192 target_ulong pte0, target_ulong pte1, int h, int rw)
193 {
194 return _pte_check(ctx, 1, pte0, pte1, h, rw);
195 }
196 #endif
197
198 static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
199 int ret, int rw)
200 {
201 int store = 0;
202
203 /* Update page flags */
204 if (!(*pte1p & 0x00000100)) {
205 /* Update accessed flag */
206 *pte1p |= 0x00000100;
207 store = 1;
208 }
209 if (!(*pte1p & 0x00000080)) {
210 if (rw == 1 && ret == 0) {
211 /* Update changed flag */
212 *pte1p |= 0x00000080;
213 store = 1;
214 } else {
215 /* Force page fault for first write access */
216 ctx->prot &= ~PAGE_WRITE;
217 }
218 }
219
220 return store;
221 }
222
223 /* Software driven TLB helpers */
224 static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
225 int way, int is_code)
226 {
227 int nr;
228
229 /* Select TLB num in a way from address */
230 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
231 /* Select TLB way */
232 nr += env->tlb_per_way * way;
233 /* 6xx have separate TLBs for instructions and data */
234 if (is_code && env->id_tlbs == 1)
235 nr += env->nb_tlb;
236
237 return nr;
238 }
239
240 void ppc6xx_tlb_invalidate_all (CPUState *env)
241 {
242 ppc6xx_tlb_t *tlb;
243 int nr, max;
244
245 #if defined (DEBUG_SOFTWARE_TLB) && 0
246 if (loglevel != 0) {
247 fprintf(logfile, "Invalidate all TLBs\n");
248 }
249 #endif
250 /* Invalidate all defined software TLB */
251 max = env->nb_tlb;
252 if (env->id_tlbs == 1)
253 max *= 2;
254 for (nr = 0; nr < max; nr++) {
255 tlb = &env->tlb[nr].tlb6;
256 #if !defined(FLUSH_ALL_TLBS)
257 tlb_flush_page(env, tlb->EPN);
258 #endif
259 pte_invalidate(&tlb->pte0);
260 }
261 #if defined(FLUSH_ALL_TLBS)
262 tlb_flush(env, 1);
263 #endif
264 }
265
266 static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
267 target_ulong eaddr,
268 int is_code, int match_epn)
269 {
270 #if !defined(FLUSH_ALL_TLBS)
271 ppc6xx_tlb_t *tlb;
272 int way, nr;
273
274 /* Invalidate ITLB + DTLB, all ways */
275 for (way = 0; way < env->nb_ways; way++) {
276 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
277 tlb = &env->tlb[nr].tlb6;
278 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
279 #if defined (DEBUG_SOFTWARE_TLB)
280 if (loglevel != 0) {
281 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
282 nr, env->nb_tlb, eaddr);
283 }
284 #endif
285 pte_invalidate(&tlb->pte0);
286 tlb_flush_page(env, tlb->EPN);
287 }
288 }
289 #else
290 /* XXX: PowerPC specification say this is valid as well */
291 ppc6xx_tlb_invalidate_all(env);
292 #endif
293 }
294
295 void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
296 int is_code)
297 {
298 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
299 }
300
301 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
302 target_ulong pte0, target_ulong pte1)
303 {
304 ppc6xx_tlb_t *tlb;
305 int nr;
306
307 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
308 tlb = &env->tlb[nr].tlb6;
309 #if defined (DEBUG_SOFTWARE_TLB)
310 if (loglevel != 0) {
311 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
312 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
313 }
314 #endif
315 /* Invalidate any pending reference in Qemu for this virtual address */
316 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
317 tlb->pte0 = pte0;
318 tlb->pte1 = pte1;
319 tlb->EPN = EPN;
320 /* Store last way for LRU mechanism */
321 env->last_way = way;
322 }
323
324 static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
325 target_ulong eaddr, int rw, int access_type)
326 {
327 ppc6xx_tlb_t *tlb;
328 int nr, best, way;
329 int ret;
330
331 best = -1;
332 ret = -1; /* No TLB found */
333 for (way = 0; way < env->nb_ways; way++) {
334 nr = ppc6xx_tlb_getnum(env, eaddr, way,
335 access_type == ACCESS_CODE ? 1 : 0);
336 tlb = &env->tlb[nr].tlb6;
337 /* This test "emulates" the PTE index match for hardware TLBs */
338 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
339 #if defined (DEBUG_SOFTWARE_TLB)
340 if (loglevel != 0) {
341 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
342 "] <> " ADDRX "\n",
343 nr, env->nb_tlb,
344 pte_is_valid(tlb->pte0) ? "valid" : "inval",
345 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
346 }
347 #endif
348 continue;
349 }
350 #if defined (DEBUG_SOFTWARE_TLB)
351 if (loglevel != 0) {
352 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
353 " %c %c\n",
354 nr, env->nb_tlb,
355 pte_is_valid(tlb->pte0) ? "valid" : "inval",
356 tlb->EPN, eaddr, tlb->pte1,
357 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
358 }
359 #endif
360 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
361 case -3:
362 /* TLB inconsistency */
363 return -1;
364 case -2:
365 /* Access violation */
366 ret = -2;
367 best = nr;
368 break;
369 case -1:
370 default:
371 /* No match */
372 break;
373 case 0:
374 /* access granted */
375 /* XXX: we should go on looping to check all TLBs consistency
376 * but we can speed-up the whole thing as the
377 * result would be undefined if TLBs are not consistent.
378 */
379 ret = 0;
380 best = nr;
381 goto done;
382 }
383 }
384 if (best != -1) {
385 done:
386 #if defined (DEBUG_SOFTWARE_TLB)
387 if (loglevel != 0) {
388 fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
389 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
390 }
391 #endif
392 /* Update page flags */
393 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
394 }
395
396 return ret;
397 }
398
399 /* Perform BAT hit & translation */
400 static int get_bat (CPUState *env, mmu_ctx_t *ctx,
401 target_ulong virtual, int rw, int type)
402 {
403 target_ulong *BATlt, *BATut, *BATu, *BATl;
404 target_ulong base, BEPIl, BEPIu, bl;
405 int i;
406 int ret = -1;
407
408 #if defined (DEBUG_BATS)
409 if (loglevel != 0) {
410 fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
411 type == ACCESS_CODE ? 'I' : 'D', virtual);
412 }
413 #endif
414 switch (type) {
415 case ACCESS_CODE:
416 BATlt = env->IBAT[1];
417 BATut = env->IBAT[0];
418 break;
419 default:
420 BATlt = env->DBAT[1];
421 BATut = env->DBAT[0];
422 break;
423 }
424 #if defined (DEBUG_BATS)
425 if (loglevel != 0) {
426 fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
427 type == ACCESS_CODE ? 'I' : 'D', virtual);
428 }
429 #endif
430 base = virtual & 0xFFFC0000;
431 for (i = 0; i < 4; i++) {
432 BATu = &BATut[i];
433 BATl = &BATlt[i];
434 BEPIu = *BATu & 0xF0000000;
435 BEPIl = *BATu & 0x0FFE0000;
436 bl = (*BATu & 0x00001FFC) << 15;
437 #if defined (DEBUG_BATS)
438 if (loglevel != 0) {
439 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
440 " BATl 0x" ADDRX "\n",
441 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
442 *BATu, *BATl);
443 }
444 #endif
445 if ((virtual & 0xF0000000) == BEPIu &&
446 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
447 /* BAT matches */
448 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
449 (msr_pr == 1 && (*BATu & 0x00000001))) {
450 /* Get physical address */
451 ctx->raddr = (*BATl & 0xF0000000) |
452 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
453 (virtual & 0x0001F000);
454 if (*BATl & 0x00000001)
455 ctx->prot = PAGE_READ;
456 if (*BATl & 0x00000002)
457 ctx->prot = PAGE_WRITE | PAGE_READ;
458 #if defined (DEBUG_BATS)
459 if (loglevel != 0) {
460 fprintf(logfile, "BAT %d match: r 0x" PADDRX
461 " prot=%c%c\n",
462 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
463 ctx->prot & PAGE_WRITE ? 'W' : '-');
464 }
465 #endif
466 ret = 0;
467 break;
468 }
469 }
470 }
471 if (ret < 0) {
472 #if defined (DEBUG_BATS)
473 if (loglevel != 0) {
474 fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
475 for (i = 0; i < 4; i++) {
476 BATu = &BATut[i];
477 BATl = &BATlt[i];
478 BEPIu = *BATu & 0xF0000000;
479 BEPIl = *BATu & 0x0FFE0000;
480 bl = (*BATu & 0x00001FFC) << 15;
481 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
482 " BATl 0x" ADDRX " \n\t"
483 "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
484 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
485 *BATu, *BATl, BEPIu, BEPIl, bl);
486 }
487 }
488 #endif
489 }
490 /* No hit */
491 return ret;
492 }
493
494 /* PTE table lookup */
495 static inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
496 {
497 target_ulong base, pte0, pte1;
498 int i, good = -1;
499 int ret, r;
500
501 ret = -1; /* No entry found */
502 base = ctx->pg_addr[h];
503 for (i = 0; i < 8; i++) {
504 #if defined(TARGET_PPC64)
505 if (is_64b) {
506 pte0 = ldq_phys(base + (i * 16));
507 pte1 = ldq_phys(base + (i * 16) + 8);
508 r = pte64_check(ctx, pte0, pte1, h, rw);
509 } else
510 #endif
511 {
512 pte0 = ldl_phys(base + (i * 8));
513 pte1 = ldl_phys(base + (i * 8) + 4);
514 r = pte32_check(ctx, pte0, pte1, h, rw);
515 }
516 #if defined (DEBUG_MMU)
517 if (loglevel != 0) {
518 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
519 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
520 base + (i * 8), pte0, pte1,
521 (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), ctx->ptem);
522 }
523 #endif
524 switch (r) {
525 case -3:
526 /* PTE inconsistency */
527 return -1;
528 case -2:
529 /* Access violation */
530 ret = -2;
531 good = i;
532 break;
533 case -1:
534 default:
535 /* No PTE match */
536 break;
537 case 0:
538 /* access granted */
539 /* XXX: we should go on looping to check all PTEs consistency
540 * but if we can speed-up the whole thing as the
541 * result would be undefined if PTEs are not consistent.
542 */
543 ret = 0;
544 good = i;
545 goto done;
546 }
547 }
548 if (good != -1) {
549 done:
550 #if defined (DEBUG_MMU)
551 if (loglevel != 0) {
552 fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
553 "ret=%d\n",
554 ctx->raddr, ctx->prot, ret);
555 }
556 #endif
557 /* Update page flags */
558 pte1 = ctx->raddr;
559 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
560 #if defined(TARGET_PPC64)
561 if (is_64b) {
562 stq_phys_notdirty(base + (good * 16) + 8, pte1);
563 } else
564 #endif
565 {
566 stl_phys_notdirty(base + (good * 8) + 4, pte1);
567 }
568 }
569 }
570
571 return ret;
572 }
573
574 static int find_pte32 (mmu_ctx_t *ctx, int h, int rw)
575 {
576 return _find_pte(ctx, 0, h, rw);
577 }
578
579 #if defined(TARGET_PPC64)
580 static int find_pte64 (mmu_ctx_t *ctx, int h, int rw)
581 {
582 return _find_pte(ctx, 1, h, rw);
583 }
584 #endif
585
586 static inline int find_pte (CPUState *env, mmu_ctx_t *ctx, int h, int rw)
587 {
588 #if defined(TARGET_PPC64)
589 if (PPC_MMU(env) == PPC_FLAGS_MMU_64B ||
590 PPC_MMU(env) == PPC_FLAGS_MMU_64BRIDGE)
591 return find_pte64(ctx, h, rw);
592 #endif
593
594 return find_pte32(ctx, h, rw);
595 }
596
597 static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
598 int sdr_sh,
599 target_phys_addr_t hash,
600 target_phys_addr_t mask)
601 {
602 return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask);
603 }
604
605 #if defined(TARGET_PPC64)
606 static int slb_lookup (CPUState *env, target_ulong eaddr,
607 target_ulong *vsid, target_ulong *page_mask, int *attr)
608 {
609 target_phys_addr_t sr_base;
610 target_ulong mask;
611 uint64_t tmp64;
612 uint32_t tmp;
613 int n, ret;
614 int slb_nr;
615
616 ret = -5;
617 sr_base = env->spr[SPR_ASR];
618 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
619 #if 0 /* XXX: Fix this */
620 slb_nr = env->slb_nr;
621 #else
622 slb_nr = 32;
623 #endif
624 for (n = 0; n < slb_nr; n++) {
625 tmp64 = ldq_phys(sr_base);
626 if (tmp64 & 0x0000000008000000ULL) {
627 /* SLB entry is valid */
628 switch (tmp64 & 0x0000000006000000ULL) {
629 case 0x0000000000000000ULL:
630 /* 256 MB segment */
631 mask = 0xFFFFFFFFF0000000ULL;
632 break;
633 case 0x0000000002000000ULL:
634 /* 1 TB segment */
635 mask = 0xFFFF000000000000ULL;
636 break;
637 case 0x0000000004000000ULL:
638 case 0x0000000006000000ULL:
639 /* Reserved => segment is invalid */
640 continue;
641 }
642 if ((eaddr & mask) == (tmp64 & mask)) {
643 /* SLB match */
644 tmp = ldl_phys(sr_base + 8);
645 *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
646 *page_mask = ~mask;
647 *attr = tmp & 0xFF;
648 ret = 0;
649 break;
650 }
651 }
652 sr_base += 12;
653 }
654
655 return ret;
656 }
657 #endif /* defined(TARGET_PPC64) */
658
659 /* Perform segment based translation */
660 static int get_segment (CPUState *env, mmu_ctx_t *ctx,
661 target_ulong eaddr, int rw, int type)
662 {
663 target_phys_addr_t sdr, hash, mask, sdr_mask;
664 target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
665 #if defined(TARGET_PPC64)
666 int attr;
667 #endif
668 int ds, nx, vsid_sh, sdr_sh;
669 int ret, ret2;
670
671 #if defined(TARGET_PPC64)
672 if (PPC_MMU(env) == PPC_FLAGS_MMU_64B) {
673 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
674 if (ret < 0)
675 return ret;
676 ctx->key = ((attr & 0x40) && msr_pr == 1) ||
677 ((attr & 0x80) && msr_pr == 0) ? 1 : 0;
678 ds = 0;
679 nx = attr & 0x20 ? 1 : 0;
680 vsid_mask = 0x00003FFFFFFFFF80ULL;
681 vsid_sh = 7;
682 sdr_sh = 18;
683 sdr_mask = 0x3FF80;
684 } else
685 #endif /* defined(TARGET_PPC64) */
686 {
687 sr = env->sr[eaddr >> 28];
688 page_mask = 0x0FFFFFFF;
689 ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
690 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
691 ds = sr & 0x80000000 ? 1 : 0;
692 nx = sr & 0x10000000 ? 1 : 0;
693 vsid = sr & 0x00FFFFFF;
694 vsid_mask = 0x01FFFFC0;
695 vsid_sh = 6;
696 sdr_sh = 16;
697 sdr_mask = 0xFFC0;
698 #if defined (DEBUG_MMU)
699 if (loglevel != 0) {
700 fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX
701 " nip=0x" ADDRX " lr=0x" ADDRX
702 " ir=%d dr=%d pr=%d %d t=%d\n",
703 eaddr, (int)(eaddr >> 28), sr, env->nip,
704 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
705 }
706 if (!ds && loglevel != 0) {
707 fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",
708 ctx->key, sr & 0x10000000);
709 }
710 #endif
711 }
712 ret = -1;
713 if (!ds) {
714 /* Check if instruction fetch is allowed, if needed */
715 if (type != ACCESS_CODE || nx == 0) {
716 /* Page address translation */
717 pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
718 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
719 /* Primary table address */
720 sdr = env->sdr1;
721 mask = ((sdr & 0x000001FF) << sdr_sh) | sdr_mask;
722 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
723 /* Secondary table address */
724 hash = (~hash) & vsid_mask;
725 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
726 #if defined(TARGET_PPC64)
727 if (PPC_MMU(env) == PPC_FLAGS_MMU_64B ||
728 PPC_MMU(env) == PPC_FLAGS_MMU_64BRIDGE) {
729 /* Only 5 bits of the page index are used in the AVPN */
730 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
731 } else
732 #endif
733 {
734 ctx->ptem = (vsid << 7) | (pgidx >> 10);
735 }
736 /* Initialize real address with an invalid value */
737 ctx->raddr = (target_ulong)-1;
738 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
739 /* Software TLB search */
740 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
741 } else {
742 #if defined (DEBUG_MMU)
743 if (loglevel != 0) {
744 fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
745 "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
746 sdr, (uint32_t)vsid, (uint32_t)pgidx,
747 (uint32_t)hash, ctx->pg_addr[0]);
748 }
749 #endif
750 /* Primary table lookup */
751 ret = find_pte(env, ctx, 0, rw);
752 if (ret < 0) {
753 /* Secondary table lookup */
754 #if defined (DEBUG_MMU)
755 if (eaddr != 0xEFFFFFFF && loglevel != 0) {
756 fprintf(logfile,
757 "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
758 "hash=0x%05x pg_addr=0x" PADDRX "\n",
759 sdr, (uint32_t)vsid, (uint32_t)pgidx,
760 (uint32_t)hash, ctx->pg_addr[1]);
761 }
762 #endif
763 ret2 = find_pte(env, ctx, 1, rw);
764 if (ret2 != -1)
765 ret = ret2;
766 }
767 }
768 } else {
769 #if defined (DEBUG_MMU)
770 if (loglevel != 0)
771 fprintf(logfile, "No access allowed\n");
772 #endif
773 ret = -3;
774 }
775 } else {
776 #if defined (DEBUG_MMU)
777 if (loglevel != 0)
778 fprintf(logfile, "direct store...\n");
779 #endif
780 /* Direct-store segment : absolutely *BUGGY* for now */
781 switch (type) {
782 case ACCESS_INT:
783 /* Integer load/store : only access allowed */
784 break;
785 case ACCESS_CODE:
786 /* No code fetch is allowed in direct-store areas */
787 return -4;
788 case ACCESS_FLOAT:
789 /* Floating point load/store */
790 return -4;
791 case ACCESS_RES:
792 /* lwarx, ldarx or srwcx. */
793 return -4;
794 case ACCESS_CACHE:
795 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
796 /* Should make the instruction do no-op.
797 * As it already do no-op, it's quite easy :-)
798 */
799 ctx->raddr = eaddr;
800 return 0;
801 case ACCESS_EXT:
802 /* eciwx or ecowx */
803 return -4;
804 default:
805 if (logfile) {
806 fprintf(logfile, "ERROR: instruction should not need "
807 "address translation\n");
808 }
809 return -4;
810 }
811 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
812 ctx->raddr = eaddr;
813 ret = 2;
814 } else {
815 ret = -2;
816 }
817 }
818
819 return ret;
820 }
821
822 /* Generic TLB check function for embedded PowerPC implementations */
823 static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
824 target_phys_addr_t *raddrp,
825 target_ulong address,
826 uint32_t pid, int ext, int i)
827 {
828 target_ulong mask;
829
830 /* Check valid flag */
831 if (!(tlb->prot & PAGE_VALID)) {
832 if (loglevel != 0)
833 fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
834 return -1;
835 }
836 mask = ~(tlb->size - 1);
837 if (loglevel != 0) {
838 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
839 ADDRX " " ADDRX " %d\n",
840 __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
841 }
842 /* Check PID */
843 if (tlb->PID != 0 && tlb->PID != pid)
844 return -1;
845 /* Check effective address */
846 if ((address & mask) != tlb->EPN)
847 return -1;
848 *raddrp = (tlb->RPN & mask) | (address & ~mask);
849 #if (TARGET_PHYS_ADDR_BITS >= 36)
850 if (ext) {
851 /* Extend the physical address to 36 bits */
852 *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
853 }
854 #endif
855
856 return 0;
857 }
858
859 /* Generic TLB search function for PowerPC embedded implementations */
860 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
861 {
862 ppcemb_tlb_t *tlb;
863 target_phys_addr_t raddr;
864 int i, ret;
865
866 /* Default return value is no match */
867 ret = -1;
868 for (i = 0; i < 64; i++) {
869 tlb = &env->tlb[i].tlbe;
870 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
871 ret = i;
872 break;
873 }
874 }
875
876 return ret;
877 }
878
879 /* Helpers specific to PowerPC 40x implementations */
880 void ppc4xx_tlb_invalidate_all (CPUState *env)
881 {
882 ppcemb_tlb_t *tlb;
883 int i;
884
885 for (i = 0; i < env->nb_tlb; i++) {
886 tlb = &env->tlb[i].tlbe;
887 if (tlb->prot & PAGE_VALID) {
888 #if 0 // XXX: TLB have variable sizes then we flush all Qemu TLB.
889 end = tlb->EPN + tlb->size;
890 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
891 tlb_flush_page(env, page);
892 #endif
893 tlb->prot &= ~PAGE_VALID;
894 }
895 }
896 tlb_flush(env, 1);
897 }
898
899 int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
900 target_ulong address, int rw, int access_type)
901 {
902 ppcemb_tlb_t *tlb;
903 target_phys_addr_t raddr;
904 int i, ret, zsel, zpr;
905
906 ret = -1;
907 raddr = -1;
908 for (i = 0; i < env->nb_tlb; i++) {
909 tlb = &env->tlb[i].tlbe;
910 if (ppcemb_tlb_check(env, tlb, &raddr, address,
911 env->spr[SPR_40x_PID], 0, i) < 0)
912 continue;
913 zsel = (tlb->attr >> 4) & 0xF;
914 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
915 if (loglevel != 0) {
916 fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
917 __func__, i, zsel, zpr, rw, tlb->attr);
918 }
919 if (access_type == ACCESS_CODE) {
920 /* Check execute enable bit */
921 switch (zpr) {
922 case 0x2:
923 if (msr_pr)
924 goto check_exec_perm;
925 goto exec_granted;
926 case 0x0:
927 if (msr_pr) {
928 ctx->prot = 0;
929 ret = -3;
930 break;
931 }
932 /* No break here */
933 case 0x1:
934 check_exec_perm:
935 /* Check from TLB entry */
936 if (!(tlb->prot & PAGE_EXEC)) {
937 ret = -3;
938 } else {
939 if (tlb->prot & PAGE_WRITE) {
940 ctx->prot = PAGE_READ | PAGE_WRITE;
941 } else {
942 ctx->prot = PAGE_READ;
943 }
944 ret = 0;
945 }
946 break;
947 case 0x3:
948 exec_granted:
949 /* All accesses granted */
950 ctx->prot = PAGE_READ | PAGE_WRITE;
951 ret = 0;
952 break;
953 }
954 } else {
955 switch (zpr) {
956 case 0x2:
957 if (msr_pr)
958 goto check_rw_perm;
959 goto rw_granted;
960 case 0x0:
961 if (msr_pr) {
962 ctx->prot = 0;
963 ret = -2;
964 break;
965 }
966 /* No break here */
967 case 0x1:
968 check_rw_perm:
969 /* Check from TLB entry */
970 /* Check write protection bit */
971 if (tlb->prot & PAGE_WRITE) {
972 ctx->prot = PAGE_READ | PAGE_WRITE;
973 ret = 0;
974 } else {
975 ctx->prot = PAGE_READ;
976 if (rw)
977 ret = -2;
978 else
979 ret = 0;
980 }
981 break;
982 case 0x3:
983 rw_granted:
984 /* All accesses granted */
985 ctx->prot = PAGE_READ | PAGE_WRITE;
986 ret = 0;
987 break;
988 }
989 }
990 if (ret >= 0) {
991 ctx->raddr = raddr;
992 if (loglevel != 0) {
993 fprintf(logfile, "%s: access granted " ADDRX " => " REGX
994 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
995 ret);
996 }
997 return 0;
998 }
999 }
1000 if (loglevel != 0) {
1001 fprintf(logfile, "%s: access refused " ADDRX " => " REGX
1002 " %d %d\n", __func__, address, raddr, ctx->prot,
1003 ret);
1004 }
1005
1006 return ret;
1007 }
1008
1009 void store_40x_sler (CPUPPCState *env, uint32_t val)
1010 {
1011 /* XXX: TO BE FIXED */
1012 if (val != 0x00000000) {
1013 cpu_abort(env, "Little-endian regions are not supported by now\n");
1014 }
1015 env->spr[SPR_405_SLER] = val;
1016 }
1017
1018 int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1019 target_ulong address, int rw,
1020 int access_type)
1021 {
1022 ppcemb_tlb_t *tlb;
1023 target_phys_addr_t raddr;
1024 int i, prot, ret;
1025
1026 ret = -1;
1027 raddr = -1;
1028 for (i = 0; i < env->nb_tlb; i++) {
1029 tlb = &env->tlb[i].tlbe;
1030 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1031 env->spr[SPR_BOOKE_PID], 1, i) < 0)
1032 continue;
1033 if (msr_pr)
1034 prot = tlb->prot & 0xF;
1035 else
1036 prot = (tlb->prot >> 4) & 0xF;
1037 /* Check the address space */
1038 if (access_type == ACCESS_CODE) {
1039 if (msr_is != (tlb->attr & 1))
1040 continue;
1041 ctx->prot = prot;
1042 if (prot & PAGE_EXEC) {
1043 ret = 0;
1044 break;
1045 }
1046 ret = -3;
1047 } else {
1048 if (msr_ds != (tlb->attr & 1))
1049 continue;
1050 ctx->prot = prot;
1051 if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1052 ret = 0;
1053 break;
1054 }
1055 ret = -2;
1056 }
1057 }
1058 if (ret >= 0)
1059 ctx->raddr = raddr;
1060
1061 return ret;
1062 }
1063
1064 static int check_physical (CPUState *env, mmu_ctx_t *ctx,
1065 target_ulong eaddr, int rw)
1066 {
1067 int in_plb, ret;
1068
1069 ctx->raddr = eaddr;
1070 ctx->prot = PAGE_READ;
1071 ret = 0;
1072 switch (PPC_MMU(env)) {
1073 case PPC_FLAGS_MMU_32B:
1074 case PPC_FLAGS_MMU_SOFT_6xx:
1075 case PPC_FLAGS_MMU_601:
1076 case PPC_FLAGS_MMU_SOFT_4xx:
1077 case PPC_FLAGS_MMU_401:
1078 ctx->prot |= PAGE_WRITE;
1079 break;
1080 #if defined(TARGET_PPC64)
1081 case PPC_FLAGS_MMU_64B:
1082 case PPC_FLAGS_MMU_64BRIDGE:
1083 /* Real address are 60 bits long */
1084 ctx->raddr &= 0x0FFFFFFFFFFFFFFFUL;
1085 ctx->prot |= PAGE_WRITE;
1086 break;
1087 #endif
1088 case PPC_FLAGS_MMU_403:
1089 if (unlikely(msr_pe != 0)) {
1090 /* 403 family add some particular protections,
1091 * using PBL/PBU registers for accesses with no translation.
1092 */
1093 in_plb =
1094 /* Check PLB validity */
1095 (env->pb[0] < env->pb[1] &&
1096 /* and address in plb area */
1097 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1098 (env->pb[2] < env->pb[3] &&
1099 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1100 if (in_plb ^ msr_px) {
1101 /* Access in protected area */
1102 if (rw == 1) {
1103 /* Access is not allowed */
1104 ret = -2;
1105 }
1106 } else {
1107 /* Read-write access is allowed */
1108 ctx->prot |= PAGE_WRITE;
1109 }
1110 }
1111 case PPC_FLAGS_MMU_BOOKE:
1112 ctx->prot |= PAGE_WRITE;
1113 break;
1114 case PPC_FLAGS_MMU_BOOKE_FSL:
1115 /* XXX: TODO */
1116 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1117 break;
1118 default:
1119 cpu_abort(env, "Unknown or invalid MMU model\n");
1120 return -1;
1121 }
1122
1123 return ret;
1124 }
1125
1126 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1127 int rw, int access_type, int check_BATs)
1128 {
1129 int ret;
1130 #if 0
1131 if (loglevel != 0) {
1132 fprintf(logfile, "%s\n", __func__);
1133 }
1134 #endif
1135 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1136 (access_type != ACCESS_CODE && msr_dr == 0)) {
1137 /* No address translation */
1138 ret = check_physical(env, ctx, eaddr, rw);
1139 } else {
1140 ret = -1;
1141 switch (PPC_MMU(env)) {
1142 case PPC_FLAGS_MMU_32B:
1143 case PPC_FLAGS_MMU_SOFT_6xx:
1144 /* Try to find a BAT */
1145 if (check_BATs)
1146 ret = get_bat(env, ctx, eaddr, rw, access_type);
1147 /* No break here */
1148 #if defined(TARGET_PPC64)
1149 case PPC_FLAGS_MMU_64B:
1150 case PPC_FLAGS_MMU_64BRIDGE:
1151 #endif
1152 if (ret < 0) {
1153 /* We didn't match any BAT entry or don't have BATs */
1154 ret = get_segment(env, ctx, eaddr, rw, access_type);
1155 }
1156 break;
1157 case PPC_FLAGS_MMU_SOFT_4xx:
1158 case PPC_FLAGS_MMU_403:
1159 ret = mmu40x_get_physical_address(env, ctx, eaddr,
1160 rw, access_type);
1161 break;
1162 case PPC_FLAGS_MMU_601:
1163 /* XXX: TODO */
1164 cpu_abort(env, "601 MMU model not implemented\n");
1165 return -1;
1166 case PPC_FLAGS_MMU_BOOKE:
1167 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1168 rw, access_type);
1169 break;
1170 case PPC_FLAGS_MMU_BOOKE_FSL:
1171 /* XXX: TODO */
1172 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1173 return -1;
1174 case PPC_FLAGS_MMU_401:
1175 cpu_abort(env, "PowerPC 401 does not do any translation\n");
1176 return -1;
1177 default:
1178 cpu_abort(env, "Unknown or invalid MMU model\n");
1179 return -1;
1180 }
1181 }
1182 #if 0
1183 if (loglevel != 0) {
1184 fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
1185 __func__, eaddr, ret, ctx->raddr);
1186 }
1187 #endif
1188
1189 return ret;
1190 }
1191
1192 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
1193 {
1194 mmu_ctx_t ctx;
1195
1196 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
1197 return -1;
1198
1199 return ctx.raddr & TARGET_PAGE_MASK;
1200 }
1201
1202 /* Perform address translation */
1203 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1204 int is_user, int is_softmmu)
1205 {
1206 mmu_ctx_t ctx;
1207 int exception = 0, error_code = 0;
1208 int access_type;
1209 int ret = 0;
1210
1211 if (rw == 2) {
1212 /* code access */
1213 rw = 0;
1214 access_type = ACCESS_CODE;
1215 } else {
1216 /* data access */
1217 /* XXX: put correct access by using cpu_restore_state()
1218 correctly */
1219 access_type = ACCESS_INT;
1220 // access_type = env->access_type;
1221 }
1222 ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
1223 if (ret == 0) {
1224 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
1225 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1226 is_user, is_softmmu);
1227 } else if (ret < 0) {
1228 #if defined (DEBUG_MMU)
1229 if (loglevel != 0)
1230 cpu_dump_state(env, logfile, fprintf, 0);
1231 #endif
1232 if (access_type == ACCESS_CODE) {
1233 exception = EXCP_ISI;
1234 switch (ret) {
1235 case -1:
1236 /* No matches in page tables or TLB */
1237 switch (PPC_MMU(env)) {
1238 case PPC_FLAGS_MMU_SOFT_6xx:
1239 exception = EXCP_I_TLBMISS;
1240 env->spr[SPR_IMISS] = address;
1241 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1242 error_code = 1 << 18;
1243 goto tlb_miss;
1244 case PPC_FLAGS_MMU_SOFT_4xx:
1245 case PPC_FLAGS_MMU_403:
1246 exception = EXCP_40x_ITLBMISS;
1247 error_code = 0;
1248 env->spr[SPR_40x_DEAR] = address;
1249 env->spr[SPR_40x_ESR] = 0x00000000;
1250 break;
1251 case PPC_FLAGS_MMU_32B:
1252 error_code = 0x40000000;
1253 break;
1254 #if defined(TARGET_PPC64)
1255 case PPC_FLAGS_MMU_64B:
1256 /* XXX: TODO */
1257 cpu_abort(env, "MMU model not implemented\n");
1258 return -1;
1259 case PPC_FLAGS_MMU_64BRIDGE:
1260 /* XXX: TODO */
1261 cpu_abort(env, "MMU model not implemented\n");
1262 return -1;
1263 #endif
1264 case PPC_FLAGS_MMU_601:
1265 /* XXX: TODO */
1266 cpu_abort(env, "MMU model not implemented\n");
1267 return -1;
1268 case PPC_FLAGS_MMU_BOOKE:
1269 /* XXX: TODO */
1270 cpu_abort(env, "MMU model not implemented\n");
1271 return -1;
1272 case PPC_FLAGS_MMU_BOOKE_FSL:
1273 /* XXX: TODO */
1274 cpu_abort(env, "MMU model not implemented\n");
1275 return -1;
1276 case PPC_FLAGS_MMU_401:
1277 cpu_abort(env, "PowerPC 401 should never raise any MMU "
1278 "exceptions\n");
1279 return -1;
1280 default:
1281 cpu_abort(env, "Unknown or invalid MMU model\n");
1282 return -1;
1283 }
1284 break;
1285 case -2:
1286 /* Access rights violation */
1287 error_code = 0x08000000;
1288 break;
1289 case -3:
1290 /* No execute protection violation */
1291 error_code = 0x10000000;
1292 break;
1293 case -4:
1294 /* Direct store exception */
1295 /* No code fetch is allowed in direct-store areas */
1296 error_code = 0x10000000;
1297 break;
1298 case -5:
1299 /* No match in segment table */
1300 exception = EXCP_ISEG;
1301 error_code = 0;
1302 break;
1303 }
1304 } else {
1305 exception = EXCP_DSI;
1306 switch (ret) {
1307 case -1:
1308 /* No matches in page tables or TLB */
1309 switch (PPC_MMU(env)) {
1310 case PPC_FLAGS_MMU_SOFT_6xx:
1311 if (rw == 1) {
1312 exception = EXCP_DS_TLBMISS;
1313 error_code = 1 << 16;
1314 } else {
1315 exception = EXCP_DL_TLBMISS;
1316 error_code = 0;
1317 }
1318 env->spr[SPR_DMISS] = address;
1319 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1320 tlb_miss:
1321 error_code |= ctx.key << 19;
1322 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1323 env->spr[SPR_HASH2] = ctx.pg_addr[1];
1324 /* Do not alter DAR nor DSISR */
1325 goto out;
1326 case PPC_FLAGS_MMU_SOFT_4xx:
1327 case PPC_FLAGS_MMU_403:
1328 exception = EXCP_40x_DTLBMISS;
1329 error_code = 0;
1330 env->spr[SPR_40x_DEAR] = address;
1331 if (rw)
1332 env->spr[SPR_40x_ESR] = 0x00800000;
1333 else
1334 env->spr[SPR_40x_ESR] = 0x00000000;
1335 break;
1336 case PPC_FLAGS_MMU_32B:
1337 error_code = 0x40000000;
1338 break;
1339 #if defined(TARGET_PPC64)
1340 case PPC_FLAGS_MMU_64B:
1341 /* XXX: TODO */
1342 cpu_abort(env, "MMU model not implemented\n");
1343 return -1;
1344 case PPC_FLAGS_MMU_64BRIDGE:
1345 /* XXX: TODO */
1346 cpu_abort(env, "MMU model not implemented\n");
1347 return -1;
1348 #endif
1349 case PPC_FLAGS_MMU_601:
1350 /* XXX: TODO */
1351 cpu_abort(env, "MMU model not implemented\n");
1352 return -1;
1353 case PPC_FLAGS_MMU_BOOKE:
1354 /* XXX: TODO */
1355 cpu_abort(env, "MMU model not implemented\n");
1356 return -1;
1357 case PPC_FLAGS_MMU_BOOKE_FSL:
1358 /* XXX: TODO */
1359 cpu_abort(env, "MMU model not implemented\n");
1360 return -1;
1361 case PPC_FLAGS_MMU_401:
1362 cpu_abort(env, "PowerPC 401 should never raise any MMU "
1363 "exceptions\n");
1364 return -1;
1365 default:
1366 cpu_abort(env, "Unknown or invalid MMU model\n");
1367 return -1;
1368 }
1369 break;
1370 case -2:
1371 /* Access rights violation */
1372 error_code = 0x08000000;
1373 break;
1374 case -4:
1375 /* Direct store exception */
1376 switch (access_type) {
1377 case ACCESS_FLOAT:
1378 /* Floating point load/store */
1379 exception = EXCP_ALIGN;
1380 error_code = EXCP_ALIGN_FP;
1381 break;
1382 case ACCESS_RES:
1383 /* lwarx, ldarx or srwcx. */
1384 error_code = 0x04000000;
1385 break;
1386 case ACCESS_EXT:
1387 /* eciwx or ecowx */
1388 error_code = 0x04100000;
1389 break;
1390 default:
1391 printf("DSI: invalid exception (%d)\n", ret);
1392 exception = EXCP_PROGRAM;
1393 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
1394 break;
1395 }
1396 break;
1397 case -5:
1398 /* No match in segment table */
1399 exception = EXCP_DSEG;
1400 error_code = 0;
1401 break;
1402 }
1403 if (exception == EXCP_DSI && rw == 1)
1404 error_code |= 0x02000000;
1405 /* Store fault address */
1406 env->spr[SPR_DAR] = address;
1407 env->spr[SPR_DSISR] = error_code;
1408 }
1409 out:
1410 #if 0
1411 printf("%s: set exception to %d %02x\n",
1412 __func__, exception, error_code);
1413 #endif
1414 env->exception_index = exception;
1415 env->error_code = error_code;
1416 ret = 1;
1417 }
1418
1419 return ret;
1420 }
1421
1422 /*****************************************************************************/
1423 /* BATs management */
1424 #if !defined(FLUSH_ALL_TLBS)
1425 static inline void do_invalidate_BAT (CPUPPCState *env,
1426 target_ulong BATu, target_ulong mask)
1427 {
1428 target_ulong base, end, page;
1429
1430 base = BATu & ~0x0001FFFF;
1431 end = base + mask + 0x00020000;
1432 #if defined (DEBUG_BATS)
1433 if (loglevel != 0) {
1434 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
1435 base, end, mask);
1436 }
1437 #endif
1438 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1439 tlb_flush_page(env, page);
1440 #if defined (DEBUG_BATS)
1441 if (loglevel != 0)
1442 fprintf(logfile, "Flush done\n");
1443 #endif
1444 }
1445 #endif
1446
1447 static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
1448 target_ulong value)
1449 {
1450 #if defined (DEBUG_BATS)
1451 if (loglevel != 0) {
1452 fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1453 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
1454 }
1455 #endif
1456 }
1457
1458 target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1459 {
1460 return env->IBAT[0][nr];
1461 }
1462
1463 target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1464 {
1465 return env->IBAT[1][nr];
1466 }
1467
1468 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1469 {
1470 target_ulong mask;
1471
1472 dump_store_bat(env, 'I', 0, nr, value);
1473 if (env->IBAT[0][nr] != value) {
1474 mask = (value << 15) & 0x0FFE0000UL;
1475 #if !defined(FLUSH_ALL_TLBS)
1476 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1477 #endif
1478 /* When storing valid upper BAT, mask BEPI and BRPN
1479 * and invalidate all TLBs covered by this BAT
1480 */
1481 mask = (value << 15) & 0x0FFE0000UL;
1482 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1483 (value & ~0x0001FFFFUL & ~mask);
1484 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1485 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1486 #if !defined(FLUSH_ALL_TLBS)
1487 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1488 #else
1489 tlb_flush(env, 1);
1490 #endif
1491 }
1492 }
1493
1494 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1495 {
1496 dump_store_bat(env, 'I', 1, nr, value);
1497 env->IBAT[1][nr] = value;
1498 }
1499
1500 target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1501 {
1502 return env->DBAT[0][nr];
1503 }
1504
1505 target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1506 {
1507 return env->DBAT[1][nr];
1508 }
1509
1510 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1511 {
1512 target_ulong mask;
1513
1514 dump_store_bat(env, 'D', 0, nr, value);
1515 if (env->DBAT[0][nr] != value) {
1516 /* When storing valid upper BAT, mask BEPI and BRPN
1517 * and invalidate all TLBs covered by this BAT
1518 */
1519 mask = (value << 15) & 0x0FFE0000UL;
1520 #if !defined(FLUSH_ALL_TLBS)
1521 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1522 #endif
1523 mask = (value << 15) & 0x0FFE0000UL;
1524 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1525 (value & ~0x0001FFFFUL & ~mask);
1526 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1527 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1528 #if !defined(FLUSH_ALL_TLBS)
1529 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1530 #else
1531 tlb_flush(env, 1);
1532 #endif
1533 }
1534 }
1535
1536 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1537 {
1538 dump_store_bat(env, 'D', 1, nr, value);
1539 env->DBAT[1][nr] = value;
1540 }
1541
1542
1543 /*****************************************************************************/
1544 /* TLB management */
1545 void ppc_tlb_invalidate_all (CPUPPCState *env)
1546 {
1547 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
1548 ppc6xx_tlb_invalidate_all(env);
1549 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
1550 ppc4xx_tlb_invalidate_all(env);
1551 } else {
1552 tlb_flush(env, 1);
1553 }
1554 }
1555
1556 /*****************************************************************************/
1557 /* Special registers manipulation */
1558 #if defined(TARGET_PPC64)
1559 target_ulong ppc_load_asr (CPUPPCState *env)
1560 {
1561 return env->asr;
1562 }
1563
1564 void ppc_store_asr (CPUPPCState *env, target_ulong value)
1565 {
1566 if (env->asr != value) {
1567 env->asr = value;
1568 tlb_flush(env, 1);
1569 }
1570 }
1571 #endif
1572
1573 target_ulong do_load_sdr1 (CPUPPCState *env)
1574 {
1575 return env->sdr1;
1576 }
1577
1578 void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1579 {
1580 #if defined (DEBUG_MMU)
1581 if (loglevel != 0) {
1582 fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
1583 }
1584 #endif
1585 if (env->sdr1 != value) {
1586 env->sdr1 = value;
1587 tlb_flush(env, 1);
1588 }
1589 }
1590
1591 target_ulong do_load_sr (CPUPPCState *env, int srnum)
1592 {
1593 return env->sr[srnum];
1594 }
1595
1596 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1597 {
1598 #if defined (DEBUG_MMU)
1599 if (loglevel != 0) {
1600 fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1601 __func__, srnum, value, env->sr[srnum]);
1602 }
1603 #endif
1604 if (env->sr[srnum] != value) {
1605 env->sr[srnum] = value;
1606 #if !defined(FLUSH_ALL_TLBS) && 0
1607 {
1608 target_ulong page, end;
1609 /* Invalidate 256 MB of virtual memory */
1610 page = (16 << 20) * srnum;
1611 end = page + (16 << 20);
1612 for (; page != end; page += TARGET_PAGE_SIZE)
1613 tlb_flush_page(env, page);
1614 }
1615 #else
1616 tlb_flush(env, 1);
1617 #endif
1618 }
1619 }
1620 #endif /* !defined (CONFIG_USER_ONLY) */
1621
1622 uint32_t ppc_load_xer (CPUPPCState *env)
1623 {
1624 return (xer_so << XER_SO) |
1625 (xer_ov << XER_OV) |
1626 (xer_ca << XER_CA) |
1627 (xer_bc << XER_BC) |
1628 (xer_cmp << XER_CMP);
1629 }
1630
1631 void ppc_store_xer (CPUPPCState *env, uint32_t value)
1632 {
1633 xer_so = (value >> XER_SO) & 0x01;
1634 xer_ov = (value >> XER_OV) & 0x01;
1635 xer_ca = (value >> XER_CA) & 0x01;
1636 xer_cmp = (value >> XER_CMP) & 0xFF;
1637 xer_bc = (value >> XER_BC) & 0x7F;
1638 }
1639
1640 /* Swap temporary saved registers with GPRs */
1641 static inline void swap_gpr_tgpr (CPUPPCState *env)
1642 {
1643 ppc_gpr_t tmp;
1644
1645 tmp = env->gpr[0];
1646 env->gpr[0] = env->tgpr[0];
1647 env->tgpr[0] = tmp;
1648 tmp = env->gpr[1];
1649 env->gpr[1] = env->tgpr[1];
1650 env->tgpr[1] = tmp;
1651 tmp = env->gpr[2];
1652 env->gpr[2] = env->tgpr[2];
1653 env->tgpr[2] = tmp;
1654 tmp = env->gpr[3];
1655 env->gpr[3] = env->tgpr[3];
1656 env->tgpr[3] = tmp;
1657 }
1658
1659 /* GDBstub can read and write MSR... */
1660 target_ulong do_load_msr (CPUPPCState *env)
1661 {
1662 return
1663 #if defined (TARGET_PPC64)
1664 ((target_ulong)msr_sf << MSR_SF) |
1665 ((target_ulong)msr_isf << MSR_ISF) |
1666 ((target_ulong)msr_hv << MSR_HV) |
1667 #endif
1668 ((target_ulong)msr_ucle << MSR_UCLE) |
1669 ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
1670 ((target_ulong)msr_ap << MSR_AP) |
1671 ((target_ulong)msr_sa << MSR_SA) |
1672 ((target_ulong)msr_key << MSR_KEY) |
1673 ((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
1674 ((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
1675 ((target_ulong)msr_ile << MSR_ILE) |
1676 ((target_ulong)msr_ee << MSR_EE) |
1677 ((target_ulong)msr_pr << MSR_PR) |
1678 ((target_ulong)msr_fp << MSR_FP) |
1679 ((target_ulong)msr_me << MSR_ME) |
1680 ((target_ulong)msr_fe0 << MSR_FE0) |
1681 ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
1682 ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
1683 ((target_ulong)msr_fe1 << MSR_FE1) |
1684 ((target_ulong)msr_al << MSR_AL) |
1685 ((target_ulong)msr_ip << MSR_IP) |
1686 ((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
1687 ((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
1688 ((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
1689 ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
1690 ((target_ulong)msr_ri << MSR_RI) |
1691 ((target_ulong)msr_le << MSR_LE);
1692 }
1693
1694 void do_store_msr (CPUPPCState *env, target_ulong value)
1695 {
1696 int enter_pm;
1697
1698 value &= env->msr_mask;
1699 if (((value >> MSR_IR) & 1) != msr_ir ||
1700 ((value >> MSR_DR) & 1) != msr_dr) {
1701 /* Flush all tlb when changing translation mode */
1702 tlb_flush(env, 1);
1703 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1704 }
1705 #if 0
1706 if (loglevel != 0) {
1707 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
1708 }
1709 #endif
1710 switch (PPC_EXCP(env)) {
1711 case PPC_FLAGS_EXCP_602:
1712 case PPC_FLAGS_EXCP_603:
1713 if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
1714 /* Swap temporary saved registers with GPRs */
1715 swap_gpr_tgpr(env);
1716 }
1717 break;
1718 default:
1719 break;
1720 }
1721 #if defined (TARGET_PPC64)
1722 msr_sf = (value >> MSR_SF) & 1;
1723 msr_isf = (value >> MSR_ISF) & 1;
1724 msr_hv = (value >> MSR_HV) & 1;
1725 #endif
1726 msr_ucle = (value >> MSR_UCLE) & 1;
1727 msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
1728 msr_ap = (value >> MSR_AP) & 1;
1729 msr_sa = (value >> MSR_SA) & 1;
1730 msr_key = (value >> MSR_KEY) & 1;
1731 msr_pow = (value >> MSR_POW) & 1; /* POW / WE */
1732 msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */
1733 msr_ile = (value >> MSR_ILE) & 1;
1734 msr_ee = (value >> MSR_EE) & 1;
1735 msr_pr = (value >> MSR_PR) & 1;
1736 msr_fp = (value >> MSR_FP) & 1;
1737 msr_me = (value >> MSR_ME) & 1;
1738 msr_fe0 = (value >> MSR_FE0) & 1;
1739 msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
1740 msr_be = (value >> MSR_BE) & 1; /* BE / DE */
1741 msr_fe1 = (value >> MSR_FE1) & 1;
1742 msr_al = (value >> MSR_AL) & 1;
1743 msr_ip = (value >> MSR_IP) & 1;
1744 msr_ir = (value >> MSR_IR) & 1; /* IR / IS */
1745 msr_dr = (value >> MSR_DR) & 1; /* DR / DS */
1746 msr_pe = (value >> MSR_PE) & 1; /* PE / EP */
1747 msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
1748 msr_ri = (value >> MSR_RI) & 1;
1749 msr_le = (value >> MSR_LE) & 1;
1750 do_compute_hflags(env);
1751
1752 enter_pm = 0;
1753 switch (PPC_EXCP(env)) {
1754 case PPC_FLAGS_EXCP_603:
1755 /* Don't handle SLEEP mode: we should disable all clocks...
1756 * No dynamic power-management.
1757 */
1758 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
1759 enter_pm = 1;
1760 break;
1761 case PPC_FLAGS_EXCP_604:
1762 if (msr_pow == 1)
1763 enter_pm = 1;
1764 break;
1765 case PPC_FLAGS_EXCP_7x0:
1766 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
1767 enter_pm = 1;
1768 break;
1769 default:
1770 break;
1771 }
1772 if (enter_pm) {
1773 if (likely(!env->halted)) {
1774 /* power save: exit cpu loop */
1775 env->halted = 1;
1776 env->exception_index = EXCP_HLT;
1777 cpu_loop_exit();
1778 }
1779 }
1780 }
1781
1782 #if defined(TARGET_PPC64)
1783 void ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
1784 {
1785 do_store_msr(env,
1786 (do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF));
1787 }
1788 #endif
1789
1790 void do_compute_hflags (CPUPPCState *env)
1791 {
1792 /* Compute current hflags */
1793 env->hflags = (msr_vr << MSR_VR) |
1794 (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
1795 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
1796 (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
1797 #if defined (TARGET_PPC64)
1798 env->hflags |= msr_cm << MSR_CM;
1799 env->hflags |= (uint64_t)msr_sf << MSR_SF;
1800 env->hflags |= (uint64_t)msr_hv << MSR_HV;
1801 #endif
1802 }
1803
1804 /*****************************************************************************/
1805 /* Exception processing */
1806 #if defined (CONFIG_USER_ONLY)
1807 void do_interrupt (CPUState *env)
1808 {
1809 env->exception_index = -1;
1810 }
1811
1812 void ppc_hw_interrupt (CPUState *env)
1813 {
1814 env->exception_index = -1;
1815 }
1816 #else /* defined (CONFIG_USER_ONLY) */
1817 static void dump_syscall (CPUState *env)
1818 {
1819 fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1820 " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
1821 env->gpr[0], env->gpr[3], env->gpr[4],
1822 env->gpr[5], env->gpr[6], env->nip);
1823 }
1824
1825 void do_interrupt (CPUState *env)
1826 {
1827 target_ulong msr, *srr_0, *srr_1, *asrr_0, *asrr_1;
1828 int excp, idx;
1829
1830 excp = env->exception_index;
1831 msr = do_load_msr(env);
1832 /* The default is to use SRR0 & SRR1 to save the exception context */
1833 srr_0 = &env->spr[SPR_SRR0];
1834 srr_1 = &env->spr[SPR_SRR1];
1835 asrr_0 = NULL;
1836 asrr_1 = NULL;
1837 #if defined (DEBUG_EXCEPTIONS)
1838 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) {
1839 if (loglevel != 0) {
1840 fprintf(logfile,
1841 "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1842 env->nip, excp, env->error_code);
1843 cpu_dump_state(env, logfile, fprintf, 0);
1844 }
1845 }
1846 #endif
1847 if (loglevel & CPU_LOG_INT) {
1848 fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1849 env->nip, excp, env->error_code);
1850 }
1851 msr_pow = 0;
1852 idx = -1;
1853 /* Generate informations in save/restore registers */
1854 switch (excp) {
1855 /* Generic PowerPC exceptions */
1856 case EXCP_RESET: /* 0x0100 */
1857 switch (PPC_EXCP(env)) {
1858 case PPC_FLAGS_EXCP_40x:
1859 srr_0 = &env->spr[SPR_40x_SRR2];
1860 srr_1 = &env->spr[SPR_40x_SRR3];
1861 break;
1862 case PPC_FLAGS_EXCP_BOOKE:
1863 idx = 0;
1864 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1865 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1866 break;
1867 default:
1868 if (msr_ip)
1869 excp += 0xFFC00;
1870 excp |= 0xFFC00000;
1871 break;
1872 }
1873 goto store_next;
1874 case EXCP_MACHINE_CHECK: /* 0x0200 */
1875 switch (PPC_EXCP(env)) {
1876 case PPC_FLAGS_EXCP_40x:
1877 srr_0 = &env->spr[SPR_40x_SRR2];
1878 srr_1 = &env->spr[SPR_40x_SRR3];
1879 break;
1880 case PPC_FLAGS_EXCP_BOOKE:
1881 idx = 1;
1882 srr_0 = &env->spr[SPR_BOOKE_MCSRR0];
1883 srr_1 = &env->spr[SPR_BOOKE_MCSRR1];
1884 asrr_0 = &env->spr[SPR_BOOKE_CSRR0];
1885 asrr_1 = &env->spr[SPR_BOOKE_CSRR1];
1886 msr_ce = 0;
1887 break;
1888 default:
1889 break;
1890 }
1891 msr_me = 0;
1892 break;
1893 case EXCP_DSI: /* 0x0300 */
1894 /* Store exception cause */
1895 /* data location address has been stored
1896 * when the fault has been detected
1897 */
1898 idx = 2;
1899 msr &= ~0xFFFF0000;
1900 #if defined (DEBUG_EXCEPTIONS)
1901 if (loglevel != 0) {
1902 fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
1903 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1904 }
1905 #endif
1906 goto store_next;
1907 case EXCP_ISI: /* 0x0400 */
1908 /* Store exception cause */
1909 idx = 3;
1910 msr &= ~0xFFFF0000;
1911 msr |= env->error_code;
1912 #if defined (DEBUG_EXCEPTIONS)
1913 if (loglevel != 0) {
1914 fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
1915 "\n", msr, env->nip);
1916 }
1917 #endif
1918 goto store_next;
1919 case EXCP_EXTERNAL: /* 0x0500 */
1920 idx = 4;
1921 goto store_next;
1922 case EXCP_ALIGN: /* 0x0600 */
1923 if (likely(PPC_EXCP(env) != PPC_FLAGS_EXCP_601)) {
1924 /* Store exception cause */
1925 idx = 5;
1926 /* Get rS/rD and rA from faulting opcode */
1927 env->spr[SPR_DSISR] |=
1928 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1929 /* data location address has been stored
1930 * when the fault has been detected
1931 */
1932 } else {
1933 /* IO error exception on PowerPC 601 */
1934 /* XXX: TODO */
1935 cpu_abort(env,
1936 "601 IO error exception is not implemented yet !\n");
1937 }
1938 goto store_current;
1939 case EXCP_PROGRAM: /* 0x0700 */
1940 idx = 6;
1941 msr &= ~0xFFFF0000;
1942 switch (env->error_code & ~0xF) {
1943 case EXCP_FP:
1944 if (msr_fe0 == 0 && msr_fe1 == 0) {
1945 #if defined (DEBUG_EXCEPTIONS)
1946 if (loglevel != 0) {
1947 fprintf(logfile, "Ignore floating point exception\n");
1948 }
1949 #endif
1950 return;
1951 }
1952 msr |= 0x00100000;
1953 /* Set FX */
1954 env->fpscr[7] |= 0x8;
1955 /* Finally, update FEX */
1956 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1957 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1958 env->fpscr[7] |= 0x4;
1959 break;
1960 case EXCP_INVAL:
1961 #if defined (DEBUG_EXCEPTIONS)
1962 if (loglevel != 0) {
1963 fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
1964 env->nip);
1965 }
1966 #endif
1967 msr |= 0x00080000;
1968 break;
1969 case EXCP_PRIV:
1970 msr |= 0x00040000;
1971 break;
1972 case EXCP_TRAP:
1973 idx = 15;
1974 msr |= 0x00020000;
1975 break;
1976 default:
1977 /* Should never occur */
1978 break;
1979 }
1980 msr |= 0x00010000;
1981 goto store_current;
1982 case EXCP_NO_FP: /* 0x0800 */
1983 idx = 7;
1984 msr &= ~0xFFFF0000;
1985 goto store_current;
1986 case EXCP_DECR:
1987 goto store_next;
1988 case EXCP_SYSCALL: /* 0x0C00 */
1989 idx = 8;
1990 /* NOTE: this is a temporary hack to support graphics OSI
1991 calls from the MOL driver */
1992 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1993 env->osi_call) {
1994 if (env->osi_call(env) != 0)
1995 return;
1996 }
1997 if (loglevel & CPU_LOG_INT) {
1998 dump_syscall(env);
1999 }
2000 goto store_next;
2001 case EXCP_TRACE: /* 0x0D00 */
2002 goto store_next;
2003 case EXCP_PERF: /* 0x0F00 */
2004 /* XXX: TODO */
2005 cpu_abort(env,
2006 "Performance counter exception is not implemented yet !\n");
2007 goto store_next;
2008 /* 32 bits PowerPC specific exceptions */
2009 case EXCP_FP_ASSIST: /* 0x0E00 */
2010 /* XXX: TODO */
2011 cpu_abort(env, "Floating point assist exception "
2012 "is not implemented yet !\n");
2013 goto store_next;
2014 /* 64 bits PowerPC exceptions */
2015 case EXCP_DSEG: /* 0x0380 */
2016 /* XXX: TODO */
2017 cpu_abort(env, "Data segment exception is not implemented yet !\n");
2018 goto store_next;
2019 case EXCP_ISEG: /* 0x0480 */
2020 /* XXX: TODO */
2021 cpu_abort(env,
2022 "Instruction segment exception is not implemented yet !\n");
2023 goto store_next;
2024 case EXCP_HDECR: /* 0x0980 */
2025 /* XXX: TODO */
2026 cpu_abort(env, "Hypervisor decrementer exception is not implemented "
2027 "yet !\n");
2028 goto store_next;
2029 /* Implementation specific exceptions */
2030 case 0x0A00:
2031 if (likely(env->spr[SPR_PVR] == CPU_PPC_G2 ||
2032 env->spr[SPR_PVR] == CPU_PPC_G2LE)) {
2033 /* Critical interrupt on G2 */
2034 /* XXX: TODO */
2035 cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
2036 goto store_next;
2037 } else {
2038 cpu_abort(env, "Invalid exception 0x0A00 !\n");
2039 }
2040 return;
2041 case 0x0F20:
2042 idx = 9;
2043 switch (PPC_EXCP(env)) {
2044 case PPC_FLAGS_EXCP_40x:
2045 /* APU unavailable on 405 */
2046 /* XXX: TODO */
2047 cpu_abort(env,
2048 "APU unavailable exception is not implemented yet !\n");
2049 goto store_next;
2050 case PPC_FLAGS_EXCP_74xx:
2051 /* Altivec unavailable */
2052 /* XXX: TODO */
2053 cpu_abort(env, "Altivec unavailable exception "
2054 "is not implemented yet !\n");
2055 goto store_next;
2056 default:
2057 cpu_abort(env, "Invalid exception 0x0F20 !\n");
2058 break;
2059 }
2060 return;
2061 case 0x1000:
2062 idx = 10;
2063 switch (PPC_EXCP(env)) {
2064 case PPC_FLAGS_EXCP_40x:
2065 /* PIT on 4xx */
2066 msr &= ~0xFFFF0000;
2067 #if defined (DEBUG_EXCEPTIONS)
2068 if (loglevel != 0)
2069 fprintf(logfile, "PIT exception\n");
2070 #endif
2071 goto store_next;
2072 case PPC_FLAGS_EXCP_602:
2073 case PPC_FLAGS_EXCP_603:
2074 /* ITLBMISS on 602/603 */
2075 goto store_gprs;
2076 case PPC_FLAGS_EXCP_7x5:
2077 /* ITLBMISS on 745/755 */
2078 goto tlb_miss;
2079 default:
2080 cpu_abort(env, "Invalid exception 0x1000 !\n");
2081 break;
2082 }
2083 return;
2084 case 0x1010:
2085 idx = 11;
2086 switch (PPC_EXCP(env)) {
2087 case PPC_FLAGS_EXCP_40x:
2088 /* FIT on 4xx */
2089 msr &= ~0xFFFF0000;
2090 #if defined (DEBUG_EXCEPTIONS)
2091 if (loglevel != 0)
2092 fprintf(logfile, "FIT exception\n");
2093 #endif
2094 goto store_next;
2095 default:
2096 cpu_abort(env, "Invalid exception 0x1010 !\n");
2097 break;
2098 }
2099 return;
2100 case 0x1020:
2101 idx = 12;
2102 switch (PPC_EXCP(env)) {
2103 case PPC_FLAGS_EXCP_40x:
2104 /* Watchdog on 4xx */
2105 msr &= ~0xFFFF0000;
2106 #if defined (DEBUG_EXCEPTIONS)
2107 if (loglevel != 0)
2108 fprintf(logfile, "WDT exception\n");
2109 #endif
2110 goto store_next;
2111 case PPC_FLAGS_EXCP_BOOKE:
2112 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
2113 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
2114 break;
2115 default:
2116 cpu_abort(env, "Invalid exception 0x1020 !\n");
2117 break;
2118 }
2119 return;
2120 case 0x1100:
2121 idx = 13;
2122 switch (PPC_EXCP(env)) {
2123 case PPC_FLAGS_EXCP_40x:
2124 /* DTLBMISS on 4xx */
2125 msr &= ~0xFFFF0000;
2126 goto store_next;
2127 case PPC_FLAGS_EXCP_602:
2128 case PPC_FLAGS_EXCP_603:
2129 /* DLTLBMISS on 602/603 */
2130 goto store_gprs;
2131 case PPC_FLAGS_EXCP_7x5:
2132 /* DLTLBMISS on 745/755 */
2133 goto tlb_miss;
2134 default:
2135 cpu_abort(env, "Invalid exception 0x1100 !\n");
2136 break;
2137 }
2138 return;
2139 case 0x1200:
2140 idx = 14;
2141 switch (PPC_EXCP(env)) {
2142 case PPC_FLAGS_EXCP_40x:
2143 /* ITLBMISS on 4xx */
2144 msr &= ~0xFFFF0000;
2145 goto store_next;
2146 case PPC_FLAGS_EXCP_602:
2147 case PPC_FLAGS_EXCP_603:
2148 /* DSTLBMISS on 602/603 */
2149 store_gprs:
2150 /* Swap temporary saved registers with GPRs */
2151 swap_gpr_tgpr(env);
2152 msr_tgpr = 1;
2153 #if defined (DEBUG_SOFTWARE_TLB)
2154 if (loglevel != 0) {
2155 const unsigned char *es;
2156 target_ulong *miss, *cmp;
2157 int en;
2158 if (excp == 0x1000) {
2159 es = "I";
2160 en = 'I';
2161 miss = &env->spr[SPR_IMISS];
2162 cmp = &env->spr[SPR_ICMP];
2163 } else {
2164 if (excp == 0x1100)
2165 es = "DL";
2166 else
2167 es = "DS";
2168 en = 'D';
2169 miss = &env->spr[SPR_DMISS];
2170 cmp = &env->spr[SPR_DCMP];
2171 }
2172 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2173 " H1 " ADDRX " H2 " ADDRX " %08x\n",
2174 es, en, *miss, en, *cmp,
2175 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2176 env->error_code);
2177 }
2178 #endif
2179 goto tlb_miss;
2180 case PPC_FLAGS_EXCP_7x5:
2181 /* DSTLBMISS on 745/755 */
2182 tlb_miss:
2183 msr &= ~0xF83F0000;
2184 msr |= env->crf[0] << 28;
2185 msr |= env->error_code; /* key, D/I, S/L bits */
2186 /* Set way using a LRU mechanism */
2187 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2188 goto store_next;
2189 default:
2190 cpu_abort(env, "Invalid exception 0x1200 !\n");
2191 break;
2192 }
2193 return;
2194 case 0x1300:
2195 switch (PPC_EXCP(env)) {
2196 case PPC_FLAGS_EXCP_601:
2197 case PPC_FLAGS_EXCP_602:
2198 case PPC_FLAGS_EXCP_603:
2199 case PPC_FLAGS_EXCP_604:
2200 case PPC_FLAGS_EXCP_7x0:
2201 case PPC_FLAGS_EXCP_7x5:
2202 /* IABR on 6xx/7xx */
2203 /* XXX: TODO */
2204 cpu_abort(env, "IABR exception is not implemented yet !\n");
2205 goto store_next;
2206 default:
2207 cpu_abort(env, "Invalid exception 0x1300 !\n");
2208 break;
2209 }
2210 return;
2211 case 0x1400:
2212 switch (PPC_EXCP(env)) {
2213 case PPC_FLAGS_EXCP_601:
2214 case PPC_FLAGS_EXCP_602:
2215 case PPC_FLAGS_EXCP_603:
2216 case PPC_FLAGS_EXCP_604:
2217 case PPC_FLAGS_EXCP_7x0:
2218 case PPC_FLAGS_EXCP_7x5:
2219 /* SMI on 6xx/7xx */
2220 /* XXX: TODO */
2221 cpu_abort(env, "SMI exception is not implemented yet !\n");
2222 goto store_next;
2223 default:
2224 cpu_abort(env, "Invalid exception 0x1400 !\n");
2225 break;
2226 }
2227 return;
2228 case 0x1500:
2229 switch (PPC_EXCP(env)) {
2230 case PPC_FLAGS_EXCP_602:
2231 /* Watchdog on 602 */
2232 /* XXX: TODO */
2233 cpu_abort(env,
2234 "602 watchdog exception is not implemented yet !\n");
2235 goto store_next;
2236 case PPC_FLAGS_EXCP_970:
2237 /* Soft patch exception on 970 */
2238 /* XXX: TODO */
2239 cpu_abort(env,
2240 "970 soft-patch exception is not implemented yet !\n");
2241 goto store_next;
2242 case PPC_FLAGS_EXCP_74xx:
2243 /* VPU assist on 74xx */
2244 /* XXX: TODO */
2245 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2246 goto store_next;
2247 default:
2248 cpu_abort(env, "Invalid exception 0x1500 !\n");
2249 break;
2250 }
2251 return;
2252 case 0x1600:
2253 switch (PPC_EXCP(env)) {
2254 case PPC_FLAGS_EXCP_602:
2255 /* Emulation trap on 602 */
2256 /* XXX: TODO */
2257 cpu_abort(env, "602 emulation trap exception "
2258 "is not implemented yet !\n");
2259 goto store_next;
2260 case PPC_FLAGS_EXCP_970:
2261 /* Maintenance exception on 970 */
2262 /* XXX: TODO */
2263 cpu_abort(env,
2264 "970 maintenance exception is not implemented yet !\n");
2265 goto store_next;
2266 default:
2267 cpu_abort(env, "Invalid exception 0x1600 !\n");
2268 break;
2269 }
2270 return;
2271 case 0x1700:
2272 switch (PPC_EXCP(env)) {
2273 case PPC_FLAGS_EXCP_7x0:
2274 case PPC_FLAGS_EXCP_7x5:
2275 /* Thermal management interrupt on G3 */
2276 /* XXX: TODO */
2277 cpu_abort(env, "G3 thermal management exception "
2278 "is not implemented yet !\n");
2279 goto store_next;
2280 case PPC_FLAGS_EXCP_970:
2281 /* VPU assist on 970 */
2282 /* XXX: TODO */
2283 cpu_abort(env,
2284 "970 VPU assist exception is not implemented yet !\n");
2285 goto store_next;
2286 default:
2287 cpu_abort(env, "Invalid exception 0x1700 !\n");
2288 break;
2289 }
2290 return;
2291 case 0x1800:
2292 switch (PPC_EXCP(env)) {
2293 case PPC_FLAGS_EXCP_970:
2294 /* Thermal exception on 970 */
2295 /* XXX: TODO */
2296 cpu_abort(env, "970 thermal management exception "
2297 "is not implemented yet !\n");
2298 goto store_next;
2299 default:
2300 cpu_abort(env, "Invalid exception 0x1800 !\n");
2301 break;
2302 }
2303 return;
2304 case 0x2000:
2305 switch (PPC_EXCP(env)) {
2306 case PPC_FLAGS_EXCP_40x:
2307 /* DEBUG on 4xx */
2308 /* XXX: TODO */
2309 cpu_abort(env, "40x debug exception is not implemented yet !\n");
2310 goto store_next;
2311 case PPC_FLAGS_EXCP_601:
2312 /* Run mode exception on 601 */
2313 /* XXX: TODO */
2314 cpu_abort(env,
2315 "601 run mode exception is not implemented yet !\n");
2316 goto store_next;
2317 case PPC_FLAGS_EXCP_BOOKE:
2318 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
2319 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
2320 break;
2321 default:
2322 cpu_abort(env, "Invalid exception 0x1800 !\n");
2323 break;
2324 }
2325 return;
2326 /* Other exceptions */
2327 /* Qemu internal exceptions:
2328 * we should never come here with those values: abort execution
2329 */
2330 default:
2331 cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
2332 return;
2333 store_current:
2334 /* save current instruction location */
2335 *srr_0 = env->nip - 4;
2336 break;
2337 store_next:
2338 /* save next instruction location */
2339 *srr_0 = env->nip;
2340 break;
2341 }
2342 /* Save msr */
2343 *srr_1 = msr;
2344 if (asrr_0 != NULL)
2345 *asrr_0 = *srr_0;
2346 if (asrr_1 != NULL)
2347 *asrr_1 = *srr_1;
2348 /* If we disactivated any translation, flush TLBs */
2349 if (msr_ir || msr_dr) {
2350 tlb_flush(env, 1);
2351 }
2352 /* reload MSR with correct bits */
2353 msr_ee = 0;
2354 msr_pr = 0;
2355 msr_fp = 0;
2356 msr_fe0 = 0;
2357 msr_se = 0;
2358 msr_be = 0;
2359 msr_fe1 = 0;
2360 msr_ir = 0;
2361 msr_dr = 0;
2362 msr_ri = 0;
2363 msr_le = msr_ile;
2364 if (PPC_EXCP(env) == PPC_FLAGS_EXCP_BOOKE) {
2365 msr_cm = msr_icm;
2366 if (idx == -1 || (idx >= 16 && idx < 32)) {
2367 cpu_abort(env, "Invalid exception index for excp %d %08x idx %d\n",
2368 excp, excp, idx);
2369 }
2370 #if defined(TARGET_PPC64)
2371 if (msr_cm)
2372 env->nip = (uint64_t)env->spr[SPR_BOOKE_IVPR];
2373 else
2374 #endif
2375 env->nip = (uint32_t)env->spr[SPR_BOOKE_IVPR];
2376 if (idx < 16)
2377 env->nip |= env->spr[SPR_BOOKE_IVOR0 + idx];
2378 else if (idx < 38)
2379 env->nip |= env->spr[SPR_BOOKE_IVOR32 + idx - 32];
2380 } else {
2381 msr_sf = msr_isf;
2382 env->nip = excp;
2383 }
2384 do_compute_hflags(env);
2385 /* Jump to handler */
2386 env->exception_index = EXCP_NONE;
2387 }
2388
2389 void ppc_hw_interrupt (CPUPPCState *env)
2390 {
2391 int raised = 0;
2392
2393 #if 1
2394 if (loglevel & CPU_LOG_INT) {
2395 fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2396 __func__, env, env->pending_interrupts,
2397 env->interrupt_request, msr_me, msr_ee);
2398 }
2399 #endif
2400 /* Raise it */
2401 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2402 /* External reset / critical input */
2403 /* XXX: critical input should be handled another way.
2404 * This code is not correct !
2405 */
2406 env->exception_index = EXCP_RESET;
2407 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2408 raised = 1;
2409 }
2410 if (raised == 0 && msr_me != 0) {
2411 /* Machine check exception */
2412 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2413 env->exception_index = EXCP_MACHINE_CHECK;
2414 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2415 raised = 1;
2416 }
2417 }
2418 if (raised == 0 && msr_ee != 0) {
2419 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2420 /* Hypervisor decrementer exception */
2421 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2422 env->exception_index = EXCP_HDECR;
2423 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2424 raised = 1;
2425 } else
2426 #endif
2427 /* Decrementer exception */
2428 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2429 env->exception_index = EXCP_DECR;
2430 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2431 raised = 1;
2432 /* Programmable interval timer on embedded PowerPC */
2433 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2434 env->exception_index = EXCP_40x_PIT;
2435 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2436 raised = 1;
2437 /* Fixed interval timer on embedded PowerPC */
2438 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2439 env->exception_index = EXCP_40x_FIT;
2440 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2441 raised = 1;
2442 /* Watchdog timer on embedded PowerPC */
2443 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2444 env->exception_index = EXCP_40x_WATCHDOG;
2445 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2446 raised = 1;
2447 /* External interrupt */
2448 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2449 env->exception_index = EXCP_EXTERNAL;
2450 /* Taking an external interrupt does not clear the external
2451 * interrupt status
2452 */
2453 #if 0
2454 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2455 #endif
2456 raised = 1;
2457 #if 0 // TODO
2458 /* Thermal interrupt */
2459 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2460 env->exception_index = EXCP_970_THRM;
2461 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2462 raised = 1;
2463 #endif
2464 }
2465 #if 0 // TODO
2466 /* External debug exception */
2467 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2468 env->exception_index = EXCP_xxx;
2469 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2470 raised = 1;
2471 #endif
2472 }
2473 if (raised != 0) {
2474 env->error_code = 0;
2475 do_interrupt(env);
2476 }
2477 }
2478 #endif /* !CONFIG_USER_ONLY */
2479
2480 void cpu_dump_EA (target_ulong EA)
2481 {
2482 FILE *f;
2483
2484 if (logfile) {
2485 f = logfile;
2486 } else {
2487 f = stdout;
2488 return;
2489 }
2490 fprintf(f, "Memory access at address " ADDRX "\n", EA);
2491 }
2492
2493 void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2494 {
2495 FILE *f;
2496
2497 if (logfile) {
2498 f = logfile;
2499 } else {
2500 f = stdout;
2501 return;
2502 }
2503 fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2504 RA, msr);
2505 }
2506
2507 void cpu_ppc_reset (void *opaque)
2508 {
2509 CPUPPCState *env;
2510 int i;
2511
2512 env = opaque;
2513 /* XXX: some of those flags initialisation values could depend
2514 * on the actual PowerPC implementation
2515 */
2516 for (i = 0; i < 63; i++)
2517 env->msr[i] = 0;
2518 #if defined(TARGET_PPC64)
2519 msr_hv = 0; /* Should be 1... */
2520 #endif
2521 msr_ap = 0; /* TO BE CHECKED */
2522 msr_sa = 0; /* TO BE CHECKED */
2523 msr_ip = 0; /* TO BE CHECKED */
2524 #if defined (DO_SINGLE_STEP) && 0
2525 /* Single step trace mode */
2526 msr_se = 1;
2527 msr_be = 1;
2528 #endif
2529 #if defined(CONFIG_USER_ONLY)
2530 msr_fp = 1; /* Allow floating point exceptions */
2531 msr_pr = 1;
2532 #else
2533 env->nip = 0xFFFFFFFC;
2534 ppc_tlb_invalidate_all(env);
2535 #endif
2536 do_compute_hflags(env);
2537 env->reserve = -1;
2538 /* Be sure no exception or interrupt is pending */
2539 env->pending_interrupts = 0;
2540 env->exception_index = EXCP_NONE;
2541 /* Flush all TLBs */
2542 tlb_flush(env, 1);
2543 }
2544
2545 CPUPPCState *cpu_ppc_init (void)
2546 {
2547 CPUPPCState *env;
2548
2549 env = qemu_mallocz(sizeof(CPUPPCState));
2550 if (!env)
2551 return NULL;
2552 cpu_exec_init(env);
2553 cpu_ppc_reset(env);
2554
2555 return env;
2556 }
2557
2558 void cpu_ppc_close (CPUPPCState *env)
2559 {
2560 /* Should also remove all opcode tables... */
2561 free(env);
2562 }
Qemu copy for testing