2 * PowerPC implementation of KVM hooks
4 * Copyright IBM Corp. 2007
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
18 #include <sys/types.h>
19 #include <sys/ioctl.h>
23 #include <linux/kvm.h>
25 #include "qemu-common.h"
26 #include "qemu/timer.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/kvm.h"
31 #include "sysemu/cpus.h"
32 #include "sysemu/device_tree.h"
33 #include "hw/sysbus.h"
34 #include "hw/ppc/spapr.h"
35 #include "mmu-hash64.h"
37 #include "hw/sysbus.h"
38 #include "hw/ppc/spapr.h"
39 #include "hw/ppc/spapr_vio.h"
44 #define dprintf(fmt, ...) \
45 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
47 #define dprintf(fmt, ...) \
51 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
53 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
57 static int cap_interrupt_unset
= false;
58 static int cap_interrupt_level
= false;
59 static int cap_segstate
;
60 static int cap_booke_sregs
;
61 static int cap_ppc_smt
;
62 static int cap_ppc_rma
;
63 static int cap_spapr_tce
;
65 static int cap_one_reg
;
68 /* XXX We have a race condition where we actually have a level triggered
69 * interrupt, but the infrastructure can't expose that yet, so the guest
70 * takes but ignores it, goes to sleep and never gets notified that there's
71 * still an interrupt pending.
73 * As a quick workaround, let's just wake up again 20 ms after we injected
74 * an interrupt. That way we can assure that we're always reinjecting
75 * interrupts in case the guest swallowed them.
77 static QEMUTimer
*idle_timer
;
79 static void kvm_kick_cpu(void *opaque
)
81 PowerPCCPU
*cpu
= opaque
;
83 qemu_cpu_kick(CPU(cpu
));
86 static int kvm_ppc_register_host_cpu_type(void);
88 int kvm_arch_init(KVMState
*s
)
90 cap_interrupt_unset
= kvm_check_extension(s
, KVM_CAP_PPC_UNSET_IRQ
);
91 cap_interrupt_level
= kvm_check_extension(s
, KVM_CAP_PPC_IRQ_LEVEL
);
92 cap_segstate
= kvm_check_extension(s
, KVM_CAP_PPC_SEGSTATE
);
93 cap_booke_sregs
= kvm_check_extension(s
, KVM_CAP_PPC_BOOKE_SREGS
);
94 cap_ppc_smt
= kvm_check_extension(s
, KVM_CAP_PPC_SMT
);
95 cap_ppc_rma
= kvm_check_extension(s
, KVM_CAP_PPC_RMA
);
96 cap_spapr_tce
= kvm_check_extension(s
, KVM_CAP_SPAPR_TCE
);
97 cap_one_reg
= kvm_check_extension(s
, KVM_CAP_ONE_REG
);
98 cap_hior
= kvm_check_extension(s
, KVM_CAP_PPC_HIOR
);
99 cap_epr
= kvm_check_extension(s
, KVM_CAP_PPC_EPR
);
101 if (!cap_interrupt_level
) {
102 fprintf(stderr
, "KVM: Couldn't find level irq capability. Expect the "
103 "VM to stall at times!\n");
106 kvm_ppc_register_host_cpu_type();
111 static int kvm_arch_sync_sregs(PowerPCCPU
*cpu
)
113 CPUPPCState
*cenv
= &cpu
->env
;
114 CPUState
*cs
= CPU(cpu
);
115 struct kvm_sregs sregs
;
118 if (cenv
->excp_model
== POWERPC_EXCP_BOOKE
) {
119 /* What we're really trying to say is "if we're on BookE, we use
120 the native PVR for now". This is the only sane way to check
121 it though, so we potentially confuse users that they can run
122 BookE guests on BookS. Let's hope nobody dares enough :) */
126 fprintf(stderr
, "kvm error: missing PVR setting capability\n");
131 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_SREGS
, &sregs
);
136 sregs
.pvr
= cenv
->spr
[SPR_PVR
];
137 return kvm_vcpu_ioctl(cs
, KVM_SET_SREGS
, &sregs
);
140 /* Set up a shared TLB array with KVM */
141 static int kvm_booke206_tlb_init(PowerPCCPU
*cpu
)
143 CPUPPCState
*env
= &cpu
->env
;
144 CPUState
*cs
= CPU(cpu
);
145 struct kvm_book3e_206_tlb_params params
= {};
146 struct kvm_config_tlb cfg
= {};
147 struct kvm_enable_cap encap
= {};
148 unsigned int entries
= 0;
151 if (!kvm_enabled() ||
152 !kvm_check_extension(cs
->kvm_state
, KVM_CAP_SW_TLB
)) {
156 assert(ARRAY_SIZE(params
.tlb_sizes
) == BOOKE206_MAX_TLBN
);
158 for (i
= 0; i
< BOOKE206_MAX_TLBN
; i
++) {
159 params
.tlb_sizes
[i
] = booke206_tlb_size(env
, i
);
160 params
.tlb_ways
[i
] = booke206_tlb_ways(env
, i
);
161 entries
+= params
.tlb_sizes
[i
];
164 assert(entries
== env
->nb_tlb
);
165 assert(sizeof(struct kvm_book3e_206_tlb_entry
) == sizeof(ppcmas_tlb_t
));
167 env
->tlb_dirty
= true;
169 cfg
.array
= (uintptr_t)env
->tlb
.tlbm
;
170 cfg
.array_len
= sizeof(ppcmas_tlb_t
) * entries
;
171 cfg
.params
= (uintptr_t)¶ms
;
172 cfg
.mmu_type
= KVM_MMU_FSL_BOOKE_NOHV
;
174 encap
.cap
= KVM_CAP_SW_TLB
;
175 encap
.args
[0] = (uintptr_t)&cfg
;
177 ret
= kvm_vcpu_ioctl(cs
, KVM_ENABLE_CAP
, &encap
);
179 fprintf(stderr
, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
180 __func__
, strerror(-ret
));
184 env
->kvm_sw_tlb
= true;
189 #if defined(TARGET_PPC64)
190 static void kvm_get_fallback_smmu_info(PowerPCCPU
*cpu
,
191 struct kvm_ppc_smmu_info
*info
)
193 CPUPPCState
*env
= &cpu
->env
;
194 CPUState
*cs
= CPU(cpu
);
196 memset(info
, 0, sizeof(*info
));
198 /* We don't have the new KVM_PPC_GET_SMMU_INFO ioctl, so
199 * need to "guess" what the supported page sizes are.
201 * For that to work we make a few assumptions:
203 * - If KVM_CAP_PPC_GET_PVINFO is supported we are running "PR"
204 * KVM which only supports 4K and 16M pages, but supports them
205 * regardless of the backing store characteritics. We also don't
206 * support 1T segments.
208 * This is safe as if HV KVM ever supports that capability or PR
209 * KVM grows supports for more page/segment sizes, those versions
210 * will have implemented KVM_CAP_PPC_GET_SMMU_INFO and thus we
211 * will not hit this fallback
213 * - Else we are running HV KVM. This means we only support page
214 * sizes that fit in the backing store. Additionally we only
215 * advertize 64K pages if the processor is ARCH 2.06 and we assume
216 * P7 encodings for the SLB and hash table. Here too, we assume
217 * support for any newer processor will mean a kernel that
218 * implements KVM_CAP_PPC_GET_SMMU_INFO and thus doesn't hit
221 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_PPC_GET_PVINFO
)) {
226 /* Standard 4k base page size segment */
227 info
->sps
[0].page_shift
= 12;
228 info
->sps
[0].slb_enc
= 0;
229 info
->sps
[0].enc
[0].page_shift
= 12;
230 info
->sps
[0].enc
[0].pte_enc
= 0;
232 /* Standard 16M large page size segment */
233 info
->sps
[1].page_shift
= 24;
234 info
->sps
[1].slb_enc
= SLB_VSID_L
;
235 info
->sps
[1].enc
[0].page_shift
= 24;
236 info
->sps
[1].enc
[0].pte_enc
= 0;
240 /* HV KVM has backing store size restrictions */
241 info
->flags
= KVM_PPC_PAGE_SIZES_REAL
;
243 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
244 info
->flags
|= KVM_PPC_1T_SEGMENTS
;
247 if (env
->mmu_model
== POWERPC_MMU_2_06
) {
253 /* Standard 4k base page size segment */
254 info
->sps
[i
].page_shift
= 12;
255 info
->sps
[i
].slb_enc
= 0;
256 info
->sps
[i
].enc
[0].page_shift
= 12;
257 info
->sps
[i
].enc
[0].pte_enc
= 0;
260 /* 64K on MMU 2.06 */
261 if (env
->mmu_model
== POWERPC_MMU_2_06
) {
262 info
->sps
[i
].page_shift
= 16;
263 info
->sps
[i
].slb_enc
= 0x110;
264 info
->sps
[i
].enc
[0].page_shift
= 16;
265 info
->sps
[i
].enc
[0].pte_enc
= 1;
269 /* Standard 16M large page size segment */
270 info
->sps
[i
].page_shift
= 24;
271 info
->sps
[i
].slb_enc
= SLB_VSID_L
;
272 info
->sps
[i
].enc
[0].page_shift
= 24;
273 info
->sps
[i
].enc
[0].pte_enc
= 0;
277 static void kvm_get_smmu_info(PowerPCCPU
*cpu
, struct kvm_ppc_smmu_info
*info
)
279 CPUState
*cs
= CPU(cpu
);
282 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_PPC_GET_SMMU_INFO
)) {
283 ret
= kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_GET_SMMU_INFO
, info
);
289 kvm_get_fallback_smmu_info(cpu
, info
);
292 static long getrampagesize(void)
298 /* guest RAM is backed by normal anonymous pages */
299 return getpagesize();
303 ret
= statfs(mem_path
, &fs
);
304 } while (ret
!= 0 && errno
== EINTR
);
307 fprintf(stderr
, "Couldn't statfs() memory path: %s\n",
312 #define HUGETLBFS_MAGIC 0x958458f6
314 if (fs
.f_type
!= HUGETLBFS_MAGIC
) {
315 /* Explicit mempath, but it's ordinary pages */
316 return getpagesize();
319 /* It's hugepage, return the huge page size */
323 static bool kvm_valid_page_size(uint32_t flags
, long rampgsize
, uint32_t shift
)
325 if (!(flags
& KVM_PPC_PAGE_SIZES_REAL
)) {
329 return (1ul << shift
) <= rampgsize
;
332 static void kvm_fixup_page_sizes(PowerPCCPU
*cpu
)
334 static struct kvm_ppc_smmu_info smmu_info
;
335 static bool has_smmu_info
;
336 CPUPPCState
*env
= &cpu
->env
;
340 /* We only handle page sizes for 64-bit server guests for now */
341 if (!(env
->mmu_model
& POWERPC_MMU_64
)) {
345 /* Collect MMU info from kernel if not already */
346 if (!has_smmu_info
) {
347 kvm_get_smmu_info(cpu
, &smmu_info
);
348 has_smmu_info
= true;
351 rampagesize
= getrampagesize();
353 /* Convert to QEMU form */
354 memset(&env
->sps
, 0, sizeof(env
->sps
));
356 for (ik
= iq
= 0; ik
< KVM_PPC_PAGE_SIZES_MAX_SZ
; ik
++) {
357 struct ppc_one_seg_page_size
*qsps
= &env
->sps
.sps
[iq
];
358 struct kvm_ppc_one_seg_page_size
*ksps
= &smmu_info
.sps
[ik
];
360 if (!kvm_valid_page_size(smmu_info
.flags
, rampagesize
,
364 qsps
->page_shift
= ksps
->page_shift
;
365 qsps
->slb_enc
= ksps
->slb_enc
;
366 for (jk
= jq
= 0; jk
< KVM_PPC_PAGE_SIZES_MAX_SZ
; jk
++) {
367 if (!kvm_valid_page_size(smmu_info
.flags
, rampagesize
,
368 ksps
->enc
[jk
].page_shift
)) {
371 qsps
->enc
[jq
].page_shift
= ksps
->enc
[jk
].page_shift
;
372 qsps
->enc
[jq
].pte_enc
= ksps
->enc
[jk
].pte_enc
;
373 if (++jq
>= PPC_PAGE_SIZES_MAX_SZ
) {
377 if (++iq
>= PPC_PAGE_SIZES_MAX_SZ
) {
381 env
->slb_nr
= smmu_info
.slb_size
;
382 if (smmu_info
.flags
& KVM_PPC_1T_SEGMENTS
) {
383 env
->mmu_model
|= POWERPC_MMU_1TSEG
;
385 env
->mmu_model
&= ~POWERPC_MMU_1TSEG
;
388 #else /* defined (TARGET_PPC64) */
390 static inline void kvm_fixup_page_sizes(PowerPCCPU
*cpu
)
394 #endif /* !defined (TARGET_PPC64) */
396 unsigned long kvm_arch_vcpu_id(CPUState
*cpu
)
398 return cpu
->cpu_index
;
401 int kvm_arch_init_vcpu(CPUState
*cs
)
403 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
404 CPUPPCState
*cenv
= &cpu
->env
;
407 /* Gather server mmu info from KVM and update the CPU state */
408 kvm_fixup_page_sizes(cpu
);
410 /* Synchronize sregs with kvm */
411 ret
= kvm_arch_sync_sregs(cpu
);
416 idle_timer
= qemu_new_timer_ns(vm_clock
, kvm_kick_cpu
, cpu
);
418 /* Some targets support access to KVM's guest TLB. */
419 switch (cenv
->mmu_model
) {
420 case POWERPC_MMU_BOOKE206
:
421 ret
= kvm_booke206_tlb_init(cpu
);
430 void kvm_arch_reset_vcpu(CPUState
*cpu
)
434 static void kvm_sw_tlb_put(PowerPCCPU
*cpu
)
436 CPUPPCState
*env
= &cpu
->env
;
437 CPUState
*cs
= CPU(cpu
);
438 struct kvm_dirty_tlb dirty_tlb
;
439 unsigned char *bitmap
;
442 if (!env
->kvm_sw_tlb
) {
446 bitmap
= g_malloc((env
->nb_tlb
+ 7) / 8);
447 memset(bitmap
, 0xFF, (env
->nb_tlb
+ 7) / 8);
449 dirty_tlb
.bitmap
= (uintptr_t)bitmap
;
450 dirty_tlb
.num_dirty
= env
->nb_tlb
;
452 ret
= kvm_vcpu_ioctl(cs
, KVM_DIRTY_TLB
, &dirty_tlb
);
454 fprintf(stderr
, "%s: KVM_DIRTY_TLB: %s\n",
455 __func__
, strerror(-ret
));
461 static void kvm_get_one_spr(CPUState
*cs
, uint64_t id
, int spr
)
463 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
464 CPUPPCState
*env
= &cpu
->env
;
469 struct kvm_one_reg reg
= {
471 .addr
= (uintptr_t) &val
,
475 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
477 fprintf(stderr
, "Warning: Unable to retrieve SPR %d from KVM: %s\n",
478 spr
, strerror(errno
));
480 switch (id
& KVM_REG_SIZE_MASK
) {
481 case KVM_REG_SIZE_U32
:
482 env
->spr
[spr
] = val
.u32
;
485 case KVM_REG_SIZE_U64
:
486 env
->spr
[spr
] = val
.u64
;
490 /* Don't handle this size yet */
496 static void kvm_put_one_spr(CPUState
*cs
, uint64_t id
, int spr
)
498 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
499 CPUPPCState
*env
= &cpu
->env
;
504 struct kvm_one_reg reg
= {
506 .addr
= (uintptr_t) &val
,
510 switch (id
& KVM_REG_SIZE_MASK
) {
511 case KVM_REG_SIZE_U32
:
512 val
.u32
= env
->spr
[spr
];
515 case KVM_REG_SIZE_U64
:
516 val
.u64
= env
->spr
[spr
];
520 /* Don't handle this size yet */
524 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
526 fprintf(stderr
, "Warning: Unable to set SPR %d to KVM: %s\n",
527 spr
, strerror(errno
));
531 static int kvm_put_fp(CPUState
*cs
)
533 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
534 CPUPPCState
*env
= &cpu
->env
;
535 struct kvm_one_reg reg
;
539 if (env
->insns_flags
& PPC_FLOAT
) {
540 uint64_t fpscr
= env
->fpscr
;
541 bool vsx
= !!(env
->insns_flags2
& PPC2_VSX
);
543 reg
.id
= KVM_REG_PPC_FPSCR
;
544 reg
.addr
= (uintptr_t)&fpscr
;
545 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
547 dprintf("Unable to set FPSCR to KVM: %s\n", strerror(errno
));
551 for (i
= 0; i
< 32; i
++) {
554 vsr
[0] = float64_val(env
->fpr
[i
]);
555 vsr
[1] = env
->vsr
[i
];
556 reg
.addr
= (uintptr_t) &vsr
;
557 reg
.id
= vsx
? KVM_REG_PPC_VSR(i
) : KVM_REG_PPC_FPR(i
);
559 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
561 dprintf("Unable to set %s%d to KVM: %s\n", vsx
? "VSR" : "FPR",
568 if (env
->insns_flags
& PPC_ALTIVEC
) {
569 reg
.id
= KVM_REG_PPC_VSCR
;
570 reg
.addr
= (uintptr_t)&env
->vscr
;
571 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
573 dprintf("Unable to set VSCR to KVM: %s\n", strerror(errno
));
577 for (i
= 0; i
< 32; i
++) {
578 reg
.id
= KVM_REG_PPC_VR(i
);
579 reg
.addr
= (uintptr_t)&env
->avr
[i
];
580 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
582 dprintf("Unable to set VR%d to KVM: %s\n", i
, strerror(errno
));
591 static int kvm_get_fp(CPUState
*cs
)
593 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
594 CPUPPCState
*env
= &cpu
->env
;
595 struct kvm_one_reg reg
;
599 if (env
->insns_flags
& PPC_FLOAT
) {
601 bool vsx
= !!(env
->insns_flags2
& PPC2_VSX
);
603 reg
.id
= KVM_REG_PPC_FPSCR
;
604 reg
.addr
= (uintptr_t)&fpscr
;
605 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
607 dprintf("Unable to get FPSCR from KVM: %s\n", strerror(errno
));
613 for (i
= 0; i
< 32; i
++) {
616 reg
.addr
= (uintptr_t) &vsr
;
617 reg
.id
= vsx
? KVM_REG_PPC_VSR(i
) : KVM_REG_PPC_FPR(i
);
619 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
621 dprintf("Unable to get %s%d from KVM: %s\n",
622 vsx
? "VSR" : "FPR", i
, strerror(errno
));
625 env
->fpr
[i
] = vsr
[0];
627 env
->vsr
[i
] = vsr
[1];
633 if (env
->insns_flags
& PPC_ALTIVEC
) {
634 reg
.id
= KVM_REG_PPC_VSCR
;
635 reg
.addr
= (uintptr_t)&env
->vscr
;
636 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
638 dprintf("Unable to get VSCR from KVM: %s\n", strerror(errno
));
642 for (i
= 0; i
< 32; i
++) {
643 reg
.id
= KVM_REG_PPC_VR(i
);
644 reg
.addr
= (uintptr_t)&env
->avr
[i
];
645 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
647 dprintf("Unable to get VR%d from KVM: %s\n",
657 int kvm_arch_put_registers(CPUState
*cs
, int level
)
659 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
660 CPUPPCState
*env
= &cpu
->env
;
661 struct kvm_regs regs
;
665 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
672 regs
.xer
= cpu_read_xer(env
);
676 regs
.srr0
= env
->spr
[SPR_SRR0
];
677 regs
.srr1
= env
->spr
[SPR_SRR1
];
679 regs
.sprg0
= env
->spr
[SPR_SPRG0
];
680 regs
.sprg1
= env
->spr
[SPR_SPRG1
];
681 regs
.sprg2
= env
->spr
[SPR_SPRG2
];
682 regs
.sprg3
= env
->spr
[SPR_SPRG3
];
683 regs
.sprg4
= env
->spr
[SPR_SPRG4
];
684 regs
.sprg5
= env
->spr
[SPR_SPRG5
];
685 regs
.sprg6
= env
->spr
[SPR_SPRG6
];
686 regs
.sprg7
= env
->spr
[SPR_SPRG7
];
688 regs
.pid
= env
->spr
[SPR_BOOKE_PID
];
690 for (i
= 0;i
< 32; i
++)
691 regs
.gpr
[i
] = env
->gpr
[i
];
693 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_REGS
, ®s
);
699 if (env
->tlb_dirty
) {
701 env
->tlb_dirty
= false;
704 if (cap_segstate
&& (level
>= KVM_PUT_RESET_STATE
)) {
705 struct kvm_sregs sregs
;
707 sregs
.pvr
= env
->spr
[SPR_PVR
];
709 sregs
.u
.s
.sdr1
= env
->spr
[SPR_SDR1
];
713 for (i
= 0; i
< 64; i
++) {
714 sregs
.u
.s
.ppc64
.slb
[i
].slbe
= env
->slb
[i
].esid
;
715 sregs
.u
.s
.ppc64
.slb
[i
].slbv
= env
->slb
[i
].vsid
;
720 for (i
= 0; i
< 16; i
++) {
721 sregs
.u
.s
.ppc32
.sr
[i
] = env
->sr
[i
];
725 for (i
= 0; i
< 8; i
++) {
726 /* Beware. We have to swap upper and lower bits here */
727 sregs
.u
.s
.ppc32
.dbat
[i
] = ((uint64_t)env
->DBAT
[0][i
] << 32)
729 sregs
.u
.s
.ppc32
.ibat
[i
] = ((uint64_t)env
->IBAT
[0][i
] << 32)
733 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_SREGS
, &sregs
);
739 if (cap_hior
&& (level
>= KVM_PUT_RESET_STATE
)) {
740 kvm_put_one_spr(cs
, KVM_REG_PPC_HIOR
, SPR_HIOR
);
746 /* We deliberately ignore errors here, for kernels which have
747 * the ONE_REG calls, but don't support the specific
748 * registers, there's a reasonable chance things will still
749 * work, at least until we try to migrate. */
750 for (i
= 0; i
< 1024; i
++) {
751 uint64_t id
= env
->spr_cb
[i
].one_reg_id
;
754 kvm_put_one_spr(cs
, id
, i
);
762 int kvm_arch_get_registers(CPUState
*cs
)
764 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
765 CPUPPCState
*env
= &cpu
->env
;
766 struct kvm_regs regs
;
767 struct kvm_sregs sregs
;
771 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
776 for (i
= 7; i
>= 0; i
--) {
777 env
->crf
[i
] = cr
& 15;
783 cpu_write_xer(env
, regs
.xer
);
787 env
->spr
[SPR_SRR0
] = regs
.srr0
;
788 env
->spr
[SPR_SRR1
] = regs
.srr1
;
790 env
->spr
[SPR_SPRG0
] = regs
.sprg0
;
791 env
->spr
[SPR_SPRG1
] = regs
.sprg1
;
792 env
->spr
[SPR_SPRG2
] = regs
.sprg2
;
793 env
->spr
[SPR_SPRG3
] = regs
.sprg3
;
794 env
->spr
[SPR_SPRG4
] = regs
.sprg4
;
795 env
->spr
[SPR_SPRG5
] = regs
.sprg5
;
796 env
->spr
[SPR_SPRG6
] = regs
.sprg6
;
797 env
->spr
[SPR_SPRG7
] = regs
.sprg7
;
799 env
->spr
[SPR_BOOKE_PID
] = regs
.pid
;
801 for (i
= 0;i
< 32; i
++)
802 env
->gpr
[i
] = regs
.gpr
[i
];
806 if (cap_booke_sregs
) {
807 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_SREGS
, &sregs
);
812 if (sregs
.u
.e
.features
& KVM_SREGS_E_BASE
) {
813 env
->spr
[SPR_BOOKE_CSRR0
] = sregs
.u
.e
.csrr0
;
814 env
->spr
[SPR_BOOKE_CSRR1
] = sregs
.u
.e
.csrr1
;
815 env
->spr
[SPR_BOOKE_ESR
] = sregs
.u
.e
.esr
;
816 env
->spr
[SPR_BOOKE_DEAR
] = sregs
.u
.e
.dear
;
817 env
->spr
[SPR_BOOKE_MCSR
] = sregs
.u
.e
.mcsr
;
818 env
->spr
[SPR_BOOKE_TSR
] = sregs
.u
.e
.tsr
;
819 env
->spr
[SPR_BOOKE_TCR
] = sregs
.u
.e
.tcr
;
820 env
->spr
[SPR_DECR
] = sregs
.u
.e
.dec
;
821 env
->spr
[SPR_TBL
] = sregs
.u
.e
.tb
& 0xffffffff;
822 env
->spr
[SPR_TBU
] = sregs
.u
.e
.tb
>> 32;
823 env
->spr
[SPR_VRSAVE
] = sregs
.u
.e
.vrsave
;
826 if (sregs
.u
.e
.features
& KVM_SREGS_E_ARCH206
) {
827 env
->spr
[SPR_BOOKE_PIR
] = sregs
.u
.e
.pir
;
828 env
->spr
[SPR_BOOKE_MCSRR0
] = sregs
.u
.e
.mcsrr0
;
829 env
->spr
[SPR_BOOKE_MCSRR1
] = sregs
.u
.e
.mcsrr1
;
830 env
->spr
[SPR_BOOKE_DECAR
] = sregs
.u
.e
.decar
;
831 env
->spr
[SPR_BOOKE_IVPR
] = sregs
.u
.e
.ivpr
;
834 if (sregs
.u
.e
.features
& KVM_SREGS_E_64
) {
835 env
->spr
[SPR_BOOKE_EPCR
] = sregs
.u
.e
.epcr
;
838 if (sregs
.u
.e
.features
& KVM_SREGS_E_SPRG8
) {
839 env
->spr
[SPR_BOOKE_SPRG8
] = sregs
.u
.e
.sprg8
;
842 if (sregs
.u
.e
.features
& KVM_SREGS_E_IVOR
) {
843 env
->spr
[SPR_BOOKE_IVOR0
] = sregs
.u
.e
.ivor_low
[0];
844 env
->spr
[SPR_BOOKE_IVOR1
] = sregs
.u
.e
.ivor_low
[1];
845 env
->spr
[SPR_BOOKE_IVOR2
] = sregs
.u
.e
.ivor_low
[2];
846 env
->spr
[SPR_BOOKE_IVOR3
] = sregs
.u
.e
.ivor_low
[3];
847 env
->spr
[SPR_BOOKE_IVOR4
] = sregs
.u
.e
.ivor_low
[4];
848 env
->spr
[SPR_BOOKE_IVOR5
] = sregs
.u
.e
.ivor_low
[5];
849 env
->spr
[SPR_BOOKE_IVOR6
] = sregs
.u
.e
.ivor_low
[6];
850 env
->spr
[SPR_BOOKE_IVOR7
] = sregs
.u
.e
.ivor_low
[7];
851 env
->spr
[SPR_BOOKE_IVOR8
] = sregs
.u
.e
.ivor_low
[8];
852 env
->spr
[SPR_BOOKE_IVOR9
] = sregs
.u
.e
.ivor_low
[9];
853 env
->spr
[SPR_BOOKE_IVOR10
] = sregs
.u
.e
.ivor_low
[10];
854 env
->spr
[SPR_BOOKE_IVOR11
] = sregs
.u
.e
.ivor_low
[11];
855 env
->spr
[SPR_BOOKE_IVOR12
] = sregs
.u
.e
.ivor_low
[12];
856 env
->spr
[SPR_BOOKE_IVOR13
] = sregs
.u
.e
.ivor_low
[13];
857 env
->spr
[SPR_BOOKE_IVOR14
] = sregs
.u
.e
.ivor_low
[14];
858 env
->spr
[SPR_BOOKE_IVOR15
] = sregs
.u
.e
.ivor_low
[15];
860 if (sregs
.u
.e
.features
& KVM_SREGS_E_SPE
) {
861 env
->spr
[SPR_BOOKE_IVOR32
] = sregs
.u
.e
.ivor_high
[0];
862 env
->spr
[SPR_BOOKE_IVOR33
] = sregs
.u
.e
.ivor_high
[1];
863 env
->spr
[SPR_BOOKE_IVOR34
] = sregs
.u
.e
.ivor_high
[2];
866 if (sregs
.u
.e
.features
& KVM_SREGS_E_PM
) {
867 env
->spr
[SPR_BOOKE_IVOR35
] = sregs
.u
.e
.ivor_high
[3];
870 if (sregs
.u
.e
.features
& KVM_SREGS_E_PC
) {
871 env
->spr
[SPR_BOOKE_IVOR36
] = sregs
.u
.e
.ivor_high
[4];
872 env
->spr
[SPR_BOOKE_IVOR37
] = sregs
.u
.e
.ivor_high
[5];
876 if (sregs
.u
.e
.features
& KVM_SREGS_E_ARCH206_MMU
) {
877 env
->spr
[SPR_BOOKE_MAS0
] = sregs
.u
.e
.mas0
;
878 env
->spr
[SPR_BOOKE_MAS1
] = sregs
.u
.e
.mas1
;
879 env
->spr
[SPR_BOOKE_MAS2
] = sregs
.u
.e
.mas2
;
880 env
->spr
[SPR_BOOKE_MAS3
] = sregs
.u
.e
.mas7_3
& 0xffffffff;
881 env
->spr
[SPR_BOOKE_MAS4
] = sregs
.u
.e
.mas4
;
882 env
->spr
[SPR_BOOKE_MAS6
] = sregs
.u
.e
.mas6
;
883 env
->spr
[SPR_BOOKE_MAS7
] = sregs
.u
.e
.mas7_3
>> 32;
884 env
->spr
[SPR_MMUCFG
] = sregs
.u
.e
.mmucfg
;
885 env
->spr
[SPR_BOOKE_TLB0CFG
] = sregs
.u
.e
.tlbcfg
[0];
886 env
->spr
[SPR_BOOKE_TLB1CFG
] = sregs
.u
.e
.tlbcfg
[1];
889 if (sregs
.u
.e
.features
& KVM_SREGS_EXP
) {
890 env
->spr
[SPR_BOOKE_EPR
] = sregs
.u
.e
.epr
;
893 if (sregs
.u
.e
.features
& KVM_SREGS_E_PD
) {
894 env
->spr
[SPR_BOOKE_EPLC
] = sregs
.u
.e
.eplc
;
895 env
->spr
[SPR_BOOKE_EPSC
] = sregs
.u
.e
.epsc
;
898 if (sregs
.u
.e
.impl_id
== KVM_SREGS_E_IMPL_FSL
) {
899 env
->spr
[SPR_E500_SVR
] = sregs
.u
.e
.impl
.fsl
.svr
;
900 env
->spr
[SPR_Exxx_MCAR
] = sregs
.u
.e
.impl
.fsl
.mcar
;
901 env
->spr
[SPR_HID0
] = sregs
.u
.e
.impl
.fsl
.hid0
;
903 if (sregs
.u
.e
.impl
.fsl
.features
& KVM_SREGS_E_FSL_PIDn
) {
904 env
->spr
[SPR_BOOKE_PID1
] = sregs
.u
.e
.impl
.fsl
.pid1
;
905 env
->spr
[SPR_BOOKE_PID2
] = sregs
.u
.e
.impl
.fsl
.pid2
;
911 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_SREGS
, &sregs
);
916 ppc_store_sdr1(env
, sregs
.u
.s
.sdr1
);
920 for (i
= 0; i
< 64; i
++) {
921 ppc_store_slb(env
, sregs
.u
.s
.ppc64
.slb
[i
].slbe
,
922 sregs
.u
.s
.ppc64
.slb
[i
].slbv
);
927 for (i
= 0; i
< 16; i
++) {
928 env
->sr
[i
] = sregs
.u
.s
.ppc32
.sr
[i
];
932 for (i
= 0; i
< 8; i
++) {
933 env
->DBAT
[0][i
] = sregs
.u
.s
.ppc32
.dbat
[i
] & 0xffffffff;
934 env
->DBAT
[1][i
] = sregs
.u
.s
.ppc32
.dbat
[i
] >> 32;
935 env
->IBAT
[0][i
] = sregs
.u
.s
.ppc32
.ibat
[i
] & 0xffffffff;
936 env
->IBAT
[1][i
] = sregs
.u
.s
.ppc32
.ibat
[i
] >> 32;
941 kvm_get_one_spr(cs
, KVM_REG_PPC_HIOR
, SPR_HIOR
);
947 /* We deliberately ignore errors here, for kernels which have
948 * the ONE_REG calls, but don't support the specific
949 * registers, there's a reasonable chance things will still
950 * work, at least until we try to migrate. */
951 for (i
= 0; i
< 1024; i
++) {
952 uint64_t id
= env
->spr_cb
[i
].one_reg_id
;
955 kvm_get_one_spr(cs
, id
, i
);
963 int kvmppc_set_interrupt(PowerPCCPU
*cpu
, int irq
, int level
)
965 unsigned virq
= level
? KVM_INTERRUPT_SET_LEVEL
: KVM_INTERRUPT_UNSET
;
967 if (irq
!= PPC_INTERRUPT_EXT
) {
971 if (!kvm_enabled() || !cap_interrupt_unset
|| !cap_interrupt_level
) {
975 kvm_vcpu_ioctl(CPU(cpu
), KVM_INTERRUPT
, &virq
);
980 #if defined(TARGET_PPCEMB)
981 #define PPC_INPUT_INT PPC40x_INPUT_INT
982 #elif defined(TARGET_PPC64)
983 #define PPC_INPUT_INT PPC970_INPUT_INT
985 #define PPC_INPUT_INT PPC6xx_INPUT_INT
988 void kvm_arch_pre_run(CPUState
*cs
, struct kvm_run
*run
)
990 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
991 CPUPPCState
*env
= &cpu
->env
;
995 /* PowerPC QEMU tracks the various core input pins (interrupt, critical
996 * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
997 if (!cap_interrupt_level
&&
998 run
->ready_for_interrupt_injection
&&
999 (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1000 (env
->irq_input_state
& (1<<PPC_INPUT_INT
)))
1002 /* For now KVM disregards the 'irq' argument. However, in the
1003 * future KVM could cache it in-kernel to avoid a heavyweight exit
1004 * when reading the UIC.
1006 irq
= KVM_INTERRUPT_SET
;
1008 dprintf("injected interrupt %d\n", irq
);
1009 r
= kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &irq
);
1011 printf("cpu %d fail inject %x\n", cs
->cpu_index
, irq
);
1014 /* Always wake up soon in case the interrupt was level based */
1015 qemu_mod_timer(idle_timer
, qemu_get_clock_ns(vm_clock
) +
1016 (get_ticks_per_sec() / 50));
1019 /* We don't know if there are more interrupts pending after this. However,
1020 * the guest will return to userspace in the course of handling this one
1021 * anyways, so we will get a chance to deliver the rest. */
1024 void kvm_arch_post_run(CPUState
*cpu
, struct kvm_run
*run
)
1028 int kvm_arch_process_async_events(CPUState
*cs
)
1033 static int kvmppc_handle_halt(PowerPCCPU
*cpu
)
1035 CPUState
*cs
= CPU(cpu
);
1036 CPUPPCState
*env
= &cpu
->env
;
1038 if (!(cs
->interrupt_request
& CPU_INTERRUPT_HARD
) && (msr_ee
)) {
1040 env
->exception_index
= EXCP_HLT
;
1046 /* map dcr access to existing qemu dcr emulation */
1047 static int kvmppc_handle_dcr_read(CPUPPCState
*env
, uint32_t dcrn
, uint32_t *data
)
1049 if (ppc_dcr_read(env
->dcr_env
, dcrn
, data
) < 0)
1050 fprintf(stderr
, "Read to unhandled DCR (0x%x)\n", dcrn
);
1055 static int kvmppc_handle_dcr_write(CPUPPCState
*env
, uint32_t dcrn
, uint32_t data
)
1057 if (ppc_dcr_write(env
->dcr_env
, dcrn
, data
) < 0)
1058 fprintf(stderr
, "Write to unhandled DCR (0x%x)\n", dcrn
);
1063 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
1065 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1066 CPUPPCState
*env
= &cpu
->env
;
1069 switch (run
->exit_reason
) {
1071 if (run
->dcr
.is_write
) {
1072 dprintf("handle dcr write\n");
1073 ret
= kvmppc_handle_dcr_write(env
, run
->dcr
.dcrn
, run
->dcr
.data
);
1075 dprintf("handle dcr read\n");
1076 ret
= kvmppc_handle_dcr_read(env
, run
->dcr
.dcrn
, &run
->dcr
.data
);
1080 dprintf("handle halt\n");
1081 ret
= kvmppc_handle_halt(cpu
);
1083 #if defined(TARGET_PPC64)
1084 case KVM_EXIT_PAPR_HCALL
:
1085 dprintf("handle PAPR hypercall\n");
1086 run
->papr_hcall
.ret
= spapr_hypercall(cpu
,
1088 run
->papr_hcall
.args
);
1093 dprintf("handle epr\n");
1094 run
->epr
.epr
= ldl_phys(env
->mpic_iack
);
1098 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
1106 static int read_cpuinfo(const char *field
, char *value
, int len
)
1110 int field_len
= strlen(field
);
1113 f
= fopen("/proc/cpuinfo", "r");
1119 if(!fgets(line
, sizeof(line
), f
)) {
1122 if (!strncmp(line
, field
, field_len
)) {
1123 pstrcpy(value
, len
, line
);
1134 uint32_t kvmppc_get_tbfreq(void)
1138 uint32_t retval
= get_ticks_per_sec();
1140 if (read_cpuinfo("timebase", line
, sizeof(line
))) {
1144 if (!(ns
= strchr(line
, ':'))) {
1154 /* Try to find a device tree node for a CPU with clock-frequency property */
1155 static int kvmppc_find_cpu_dt(char *buf
, int buf_len
)
1157 struct dirent
*dirp
;
1160 if ((dp
= opendir(PROC_DEVTREE_CPU
)) == NULL
) {
1161 printf("Can't open directory " PROC_DEVTREE_CPU
"\n");
1166 while ((dirp
= readdir(dp
)) != NULL
) {
1168 snprintf(buf
, buf_len
, "%s%s/clock-frequency", PROC_DEVTREE_CPU
,
1170 f
= fopen(buf
, "r");
1172 snprintf(buf
, buf_len
, "%s%s", PROC_DEVTREE_CPU
, dirp
->d_name
);
1179 if (buf
[0] == '\0') {
1180 printf("Unknown host!\n");
1187 /* Read a CPU node property from the host device tree that's a single
1188 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1189 * (can't find or open the property, or doesn't understand the
1191 static uint64_t kvmppc_read_int_cpu_dt(const char *propname
)
1201 if (kvmppc_find_cpu_dt(buf
, sizeof(buf
))) {
1205 strncat(buf
, "/", sizeof(buf
) - strlen(buf
));
1206 strncat(buf
, propname
, sizeof(buf
) - strlen(buf
));
1208 f
= fopen(buf
, "rb");
1213 len
= fread(&u
, 1, sizeof(u
), f
);
1217 /* property is a 32-bit quantity */
1218 return be32_to_cpu(u
.v32
);
1220 return be64_to_cpu(u
.v64
);
1226 uint64_t kvmppc_get_clockfreq(void)
1228 return kvmppc_read_int_cpu_dt("clock-frequency");
1231 uint32_t kvmppc_get_vmx(void)
1233 return kvmppc_read_int_cpu_dt("ibm,vmx");
1236 uint32_t kvmppc_get_dfp(void)
1238 return kvmppc_read_int_cpu_dt("ibm,dfp");
1241 static int kvmppc_get_pvinfo(CPUPPCState
*env
, struct kvm_ppc_pvinfo
*pvinfo
)
1243 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
1244 CPUState
*cs
= CPU(cpu
);
1246 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_PPC_GET_PVINFO
) &&
1247 !kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_GET_PVINFO
, pvinfo
)) {
1254 int kvmppc_get_hasidle(CPUPPCState
*env
)
1256 struct kvm_ppc_pvinfo pvinfo
;
1258 if (!kvmppc_get_pvinfo(env
, &pvinfo
) &&
1259 (pvinfo
.flags
& KVM_PPC_PVINFO_FLAGS_EV_IDLE
)) {
1266 int kvmppc_get_hypercall(CPUPPCState
*env
, uint8_t *buf
, int buf_len
)
1268 uint32_t *hc
= (uint32_t*)buf
;
1269 struct kvm_ppc_pvinfo pvinfo
;
1271 if (!kvmppc_get_pvinfo(env
, &pvinfo
)) {
1272 memcpy(buf
, pvinfo
.hcall
, buf_len
);
1277 * Fallback to always fail hypercalls:
1293 void kvmppc_set_papr(PowerPCCPU
*cpu
)
1295 CPUPPCState
*env
= &cpu
->env
;
1296 CPUState
*cs
= CPU(cpu
);
1297 struct kvm_enable_cap cap
= {};
1300 cap
.cap
= KVM_CAP_PPC_PAPR
;
1301 ret
= kvm_vcpu_ioctl(cs
, KVM_ENABLE_CAP
, &cap
);
1304 cpu_abort(env
, "This KVM version does not support PAPR\n");
1308 void kvmppc_set_mpic_proxy(PowerPCCPU
*cpu
, int mpic_proxy
)
1310 CPUPPCState
*env
= &cpu
->env
;
1311 CPUState
*cs
= CPU(cpu
);
1312 struct kvm_enable_cap cap
= {};
1315 cap
.cap
= KVM_CAP_PPC_EPR
;
1316 cap
.args
[0] = mpic_proxy
;
1317 ret
= kvm_vcpu_ioctl(cs
, KVM_ENABLE_CAP
, &cap
);
1319 if (ret
&& mpic_proxy
) {
1320 cpu_abort(env
, "This KVM version does not support EPR\n");
1324 int kvmppc_smt_threads(void)
1326 return cap_ppc_smt
? cap_ppc_smt
: 1;
1330 off_t
kvmppc_alloc_rma(const char *name
, MemoryRegion
*sysmem
)
1335 struct kvm_allocate_rma ret
;
1336 MemoryRegion
*rma_region
;
1338 /* If cap_ppc_rma == 0, contiguous RMA allocation is not supported
1339 * if cap_ppc_rma == 1, contiguous RMA allocation is supported, but
1340 * not necessary on this hardware
1341 * if cap_ppc_rma == 2, contiguous RMA allocation is needed on this hardware
1343 * FIXME: We should allow the user to force contiguous RMA
1344 * allocation in the cap_ppc_rma==1 case.
1346 if (cap_ppc_rma
< 2) {
1350 fd
= kvm_vm_ioctl(kvm_state
, KVM_ALLOCATE_RMA
, &ret
);
1352 fprintf(stderr
, "KVM: Error on KVM_ALLOCATE_RMA: %s\n",
1357 size
= MIN(ret
.rma_size
, 256ul << 20);
1359 rma
= mmap(NULL
, size
, PROT_READ
|PROT_WRITE
, MAP_SHARED
, fd
, 0);
1360 if (rma
== MAP_FAILED
) {
1361 fprintf(stderr
, "KVM: Error mapping RMA: %s\n", strerror(errno
));
1365 rma_region
= g_new(MemoryRegion
, 1);
1366 memory_region_init_ram_ptr(rma_region
, name
, size
, rma
);
1367 vmstate_register_ram_global(rma_region
);
1368 memory_region_add_subregion(sysmem
, 0, rma_region
);
1373 uint64_t kvmppc_rma_size(uint64_t current_size
, unsigned int hash_shift
)
1375 if (cap_ppc_rma
>= 2) {
1376 return current_size
;
1378 return MIN(current_size
,
1379 getrampagesize() << (hash_shift
- 7));
1383 void *kvmppc_create_spapr_tce(uint32_t liobn
, uint32_t window_size
, int *pfd
)
1385 struct kvm_create_spapr_tce args
= {
1387 .window_size
= window_size
,
1393 /* Must set fd to -1 so we don't try to munmap when called for
1394 * destroying the table, which the upper layers -will- do
1397 if (!cap_spapr_tce
) {
1401 fd
= kvm_vm_ioctl(kvm_state
, KVM_CREATE_SPAPR_TCE
, &args
);
1403 fprintf(stderr
, "KVM: Failed to create TCE table for liobn 0x%x\n",
1408 len
= (window_size
/ SPAPR_TCE_PAGE_SIZE
) * sizeof(sPAPRTCE
);
1409 /* FIXME: round this up to page size */
1411 table
= mmap(NULL
, len
, PROT_READ
|PROT_WRITE
, MAP_SHARED
, fd
, 0);
1412 if (table
== MAP_FAILED
) {
1413 fprintf(stderr
, "KVM: Failed to map TCE table for liobn 0x%x\n",
1423 int kvmppc_remove_spapr_tce(void *table
, int fd
, uint32_t window_size
)
1431 len
= (window_size
/ SPAPR_TCE_PAGE_SIZE
)*sizeof(sPAPRTCE
);
1432 if ((munmap(table
, len
) < 0) ||
1434 fprintf(stderr
, "KVM: Unexpected error removing TCE table: %s",
1436 /* Leak the table */
1442 int kvmppc_reset_htab(int shift_hint
)
1444 uint32_t shift
= shift_hint
;
1446 if (!kvm_enabled()) {
1447 /* Full emulation, tell caller to allocate htab itself */
1450 if (kvm_check_extension(kvm_state
, KVM_CAP_PPC_ALLOC_HTAB
)) {
1452 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_ALLOCATE_HTAB
, &shift
);
1453 if (ret
== -ENOTTY
) {
1454 /* At least some versions of PR KVM advertise the
1455 * capability, but don't implement the ioctl(). Oops.
1456 * Return 0 so that we allocate the htab in qemu, as is
1457 * correct for PR. */
1459 } else if (ret
< 0) {
1465 /* We have a kernel that predates the htab reset calls. For PR
1466 * KVM, we need to allocate the htab ourselves, for an HV KVM of
1467 * this era, it has allocated a 16MB fixed size hash table
1468 * already. Kernels of this era have the GET_PVINFO capability
1469 * only on PR, so we use this hack to determine the right
1471 if (kvm_check_extension(kvm_state
, KVM_CAP_PPC_GET_PVINFO
)) {
1472 /* PR - tell caller to allocate htab */
1475 /* HV - assume 16MB kernel allocated htab */
1480 static inline uint32_t mfpvr(void)
1489 static void alter_insns(uint64_t *word
, uint64_t flags
, bool on
)
1498 static void kvmppc_host_cpu_initfn(Object
*obj
)
1500 assert(kvm_enabled());
1503 static void kvmppc_host_cpu_class_init(ObjectClass
*oc
, void *data
)
1505 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
1506 uint32_t vmx
= kvmppc_get_vmx();
1507 uint32_t dfp
= kvmppc_get_dfp();
1509 /* Now fix up the class with information we can query from the host */
1512 /* Only override when we know what the host supports */
1513 alter_insns(&pcc
->insns_flags
, PPC_ALTIVEC
, vmx
> 0);
1514 alter_insns(&pcc
->insns_flags2
, PPC2_VSX
, vmx
> 1);
1517 /* Only override when we know what the host supports */
1518 alter_insns(&pcc
->insns_flags2
, PPC2_DFP
, dfp
);
1522 int kvmppc_fixup_cpu(PowerPCCPU
*cpu
)
1524 CPUState
*cs
= CPU(cpu
);
1527 /* Adjust cpu index for SMT */
1528 smt
= kvmppc_smt_threads();
1529 cs
->cpu_index
= (cs
->cpu_index
/ smp_threads
) * smt
1530 + (cs
->cpu_index
% smp_threads
);
1535 bool kvmppc_has_cap_epr(void)
1540 static int kvm_ppc_register_host_cpu_type(void)
1542 TypeInfo type_info
= {
1543 .name
= TYPE_HOST_POWERPC_CPU
,
1544 .instance_init
= kvmppc_host_cpu_initfn
,
1545 .class_init
= kvmppc_host_cpu_class_init
,
1547 uint32_t host_pvr
= mfpvr();
1548 PowerPCCPUClass
*pvr_pcc
;
1550 pvr_pcc
= ppc_cpu_class_by_pvr(host_pvr
);
1551 if (pvr_pcc
== NULL
) {
1554 type_info
.parent
= object_class_get_name(OBJECT_CLASS(pvr_pcc
));
1555 type_register(&type_info
);
1560 bool kvm_arch_stop_on_emulation_error(CPUState
*cpu
)
1565 int kvm_arch_on_sigbus_vcpu(CPUState
*cpu
, int code
, void *addr
)
1570 int kvm_arch_on_sigbus(int code
, void *addr
)