target-ppc/mmu-hash64.c

   1 /*
   2  *  PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *  Copyright (c) 2013 David Gibson, IBM Corporation
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "cpu.h"
  21 #include "helper.h"
  22 #include "sysemu/kvm.h"
  23 #include "kvm_ppc.h"
  24 #include "mmu-hash64.h"
  25
  26 //#define DEBUG_MMU
  27 //#define DEBUG_SLB
  28
  29 #ifdef DEBUG_MMU
  30 #  define LOG_MMU(...) qemu_log(__VA_ARGS__)
  31 #  define LOG_MMU_STATE(env) log_cpu_state((env), 0)
  32 #else
  33 #  define LOG_MMU(...) do { } while (0)
  34 #  define LOG_MMU_STATE(...) do { } while (0)
  35 #endif
  36
  37 #ifdef DEBUG_SLB
  38 #  define LOG_SLB(...) qemu_log(__VA_ARGS__)
  39 #else
  40 #  define LOG_SLB(...) do { } while (0)
  41 #endif
  42
  43 struct mmu_ctx_hash64 {
  44     hwaddr raddr;      /* Real address              */
  45     int prot;                      /* Protection bits           */
  46     hwaddr hash[2];    /* Pagetable hash values     */
  47     target_ulong ptem;             /* Virtual segment ID | API  */
  48     int key;                       /* Access key                */
  49 };
  50
  51 /*
  52  * SLB handling
  53  */
  54
  55 static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
  56 {
  57     uint64_t esid_256M, esid_1T;
  58     int n;
  59
  60     LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
  61
  62     esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
  63     esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
  64
  65     for (n = 0; n < env->slb_nr; n++) {
  66         ppc_slb_t *slb = &env->slb[n];
  67
  68         LOG_SLB("%s: slot %d %016" PRIx64 " %016"
  69                     PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
  70         /* We check for 1T matches on all MMUs here - if the MMU
  71          * doesn't have 1T segment support, we will have prevented 1T
  72          * entries from being inserted in the slbmte code. */
  73         if (((slb->esid == esid_256M) &&
  74              ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
  75             || ((slb->esid == esid_1T) &&
  76                 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
  77             return slb;
  78         }
  79     }
  80
  81     return NULL;
  82 }
  83
  84 void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
  85 {
  86     int i;
  87     uint64_t slbe, slbv;
  88
  89     cpu_synchronize_state(env);
  90
  91     cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
  92     for (i = 0; i < env->slb_nr; i++) {
  93         slbe = env->slb[i].esid;
  94         slbv = env->slb[i].vsid;
  95         if (slbe == 0 && slbv == 0) {
  96             continue;
  97         }
  98         cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
  99                     i, slbe, slbv);
 100     }
 101 }
 102
 103 void helper_slbia(CPUPPCState *env)
 104 {
 105     int n, do_invalidate;
 106
 107     do_invalidate = 0;
 108     /* XXX: Warning: slbia never invalidates the first segment */
 109     for (n = 1; n < env->slb_nr; n++) {
 110         ppc_slb_t *slb = &env->slb[n];
 111
 112         if (slb->esid & SLB_ESID_V) {
 113             slb->esid &= ~SLB_ESID_V;
 114             /* XXX: given the fact that segment size is 256 MB or 1TB,
 115              *      and we still don't have a tlb_flush_mask(env, n, mask)
 116              *      in QEMU, we just invalidate all TLBs
 117              */
 118             do_invalidate = 1;
 119         }
 120     }
 121     if (do_invalidate) {
 122         tlb_flush(env, 1);
 123     }
 124 }
 125
 126 void helper_slbie(CPUPPCState *env, target_ulong addr)
 127 {
 128     ppc_slb_t *slb;
 129
 130     slb = slb_lookup(env, addr);
 131     if (!slb) {
 132         return;
 133     }
 134
 135     if (slb->esid & SLB_ESID_V) {
 136         slb->esid &= ~SLB_ESID_V;
 137
 138         /* XXX: given the fact that segment size is 256 MB or 1TB,
 139          *      and we still don't have a tlb_flush_mask(env, n, mask)
 140          *      in QEMU, we just invalidate all TLBs
 141          */
 142         tlb_flush(env, 1);
 143     }
 144 }
 145
 146 int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 147 {
 148     int slot = rb & 0xfff;
 149     ppc_slb_t *slb = &env->slb[slot];
 150
 151     if (rb & (0x1000 - env->slb_nr)) {
 152         return -1; /* Reserved bits set or slot too high */
 153     }
 154     if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
 155         return -1; /* Bad segment size */
 156     }
 157     if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
 158         return -1; /* 1T segment on MMU that doesn't support it */
 159     }
 160
 161     /* Mask out the slot number as we store the entry */
 162     slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
 163     slb->vsid = rs;
 164
 165     LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
 166             " %016" PRIx64 "\n", __func__, slot, rb, rs,
 167             slb->esid, slb->vsid);
 168
 169     return 0;
 170 }
 171
 172 static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
 173                              target_ulong *rt)
 174 {
 175     int slot = rb & 0xfff;
 176     ppc_slb_t *slb = &env->slb[slot];
 177
 178     if (slot >= env->slb_nr) {
 179         return -1;
 180     }
 181
 182     *rt = slb->esid;
 183     return 0;
 184 }
 185
 186 static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
 187                              target_ulong *rt)
 188 {
 189     int slot = rb & 0xfff;
 190     ppc_slb_t *slb = &env->slb[slot];
 191
 192     if (slot >= env->slb_nr) {
 193         return -1;
 194     }
 195
 196     *rt = slb->vsid;
 197     return 0;
 198 }
 199
 200 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 201 {
 202     if (ppc_store_slb(env, rb, rs) < 0) {
 203         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 204                                    POWERPC_EXCP_INVAL);
 205     }
 206 }
 207
 208 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
 209 {
 210     target_ulong rt = 0;
 211
 212     if (ppc_load_slb_esid(env, rb, &rt) < 0) {
 213         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 214                                    POWERPC_EXCP_INVAL);
 215     }
 216     return rt;
 217 }
 218
 219 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
 220 {
 221     target_ulong rt = 0;
 222
 223     if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
 224         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 225                                    POWERPC_EXCP_INVAL);
 226     }
 227     return rt;
 228 }
 229
 230 /*
 231  * 64-bit hash table MMU handling
 232  */
 233
 234 static int ppc_hash64_pp_check(int key, int pp, bool nx)
 235 {
 236     int access;
 237
 238     /* Compute access rights */
 239     /* When pp is 4, 5 or 7, the result is undefined. Set it to noaccess */
 240     access = 0;
 241     if (key == 0) {
 242         switch (pp) {
 243         case 0x0:
 244         case 0x1:
 245         case 0x2:
 246             access |= PAGE_WRITE;
 247             /* No break here */
 248         case 0x3:
 249         case 0x6:
 250             access |= PAGE_READ;
 251             break;
 252         }
 253     } else {
 254         switch (pp) {
 255         case 0x0:
 256         case 0x6:
 257             access = 0;
 258             break;
 259         case 0x1:
 260         case 0x3:
 261             access = PAGE_READ;
 262             break;
 263         case 0x2:
 264             access = PAGE_READ | PAGE_WRITE;
 265             break;
 266         }
 267     }
 268     if (!nx) {
 269         access |= PAGE_EXEC;
 270     }
 271
 272     return access;
 273 }
 274
 275 static int ppc_hash64_check_prot(int prot, int rwx)
 276 {
 277     int ret;
 278
 279     if (rwx == 2) {
 280         if (prot & PAGE_EXEC) {
 281             ret = 0;
 282         } else {
 283             ret = -2;
 284         }
 285     } else if (rwx == 1) {
 286         if (prot & PAGE_WRITE) {
 287             ret = 0;
 288         } else {
 289             ret = -2;
 290         }
 291     } else {
 292         if (prot & PAGE_READ) {
 293             ret = 0;
 294         } else {
 295             ret = -2;
 296         }
 297     }
 298
 299     return ret;
 300 }
 301
 302 static bool pte64_match(target_ulong pte0, target_ulong pte1,
 303                         bool secondary, target_ulong ptem)
 304 {
 305     return (pte0 & HPTE64_V_VALID)
 306         && (secondary == !!(pte0 & HPTE64_V_SECONDARY))
 307         && HPTE64_V_COMPARE(pte0, ptem);
 308 }
 309
 310 static int pte64_check(struct mmu_ctx_hash64 *ctx, target_ulong pte0,
 311                        target_ulong pte1, int rwx)
 312 {
 313     int access, ret, pp;
 314     bool nx;
 315
 316     pp = (pte1 & HPTE64_R_PP) | ((pte1 & HPTE64_R_PP0) >> 61);
 317     /* No execute if either noexec or guarded bits set */
 318     nx = (pte1 & HPTE64_R_N) || (pte1 & HPTE64_R_G);
 319     /* Compute access rights */
 320     access = ppc_hash64_pp_check(ctx->key, pp, nx);
 321     /* Keep the matching PTE informations */
 322     ctx->raddr = pte1;
 323     ctx->prot = access;
 324     ret = ppc_hash64_check_prot(ctx->prot, rwx);
 325     if (ret == 0) {
 326         /* Access granted */
 327         LOG_MMU("PTE access granted !\n");
 328     } else {
 329         /* Access right violation */
 330         LOG_MMU("PTE access rejected\n");
 331     }
 332
 333     return ret;
 334 }
 335
 336 static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64 *ctx,
 337                                        target_ulong *pte1p,
 338                                        int ret, int rw)
 339 {
 340     int store = 0;
 341
 342     /* Update page flags */
 343     if (!(*pte1p & HPTE64_R_R)) {
 344         /* Update accessed flag */
 345         *pte1p |= HPTE64_R_R;
 346         store = 1;
 347     }
 348     if (!(*pte1p & HPTE64_R_C)) {
 349         if (rw == 1 && ret == 0) {
 350             /* Update changed flag */
 351             *pte1p |= HPTE64_R_C;
 352             store = 1;
 353         } else {
 354             /* Force page fault for first write access */
 355             ctx->prot &= ~PAGE_WRITE;
 356         }
 357     }
 358
 359     return store;
 360 }
 361
 362 /* PTE table lookup */
 363 static int find_pte64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
 364                       target_ulong eaddr, int h, int rwx, int target_page_bits)
 365 {
 366     hwaddr pteg_off;
 367     target_ulong pte0, pte1;
 368     int i, good = -1;
 369     int ret;
 370
 371     ret = -1; /* No entry found */
 372     pteg_off = (ctx->hash[h] * HASH_PTEG_SIZE_64) & env->htab_mask;
 373     for (i = 0; i < HPTES_PER_GROUP; i++) {
 374         pte0 = ppc_hash64_load_hpte0(env, pteg_off + i*HASH_PTE_SIZE_64);
 375         pte1 = ppc_hash64_load_hpte1(env, pteg_off + i*HASH_PTE_SIZE_64);
 376
 377         LOG_MMU("Load pte from %016" HWADDR_PRIx " => " TARGET_FMT_lx " "
 378                 TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
 379                 pteg_off + (i * 16), pte0, pte1, !!(pte0 & HPTE64_V_VALID),
 380                 h, !!(pte0 & HPTE64_V_SECONDARY), ctx->ptem);
 381
 382         if (pte64_match(pte0, pte1, h, ctx->ptem)) {
 383             good = i;
 384             break;
 385         }
 386     }
 387     if (good != -1) {
 388         ret = pte64_check(ctx, pte0, pte1, rwx);
 389         LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n",
 390                 ctx->raddr, ctx->prot, ret);
 391         /* Update page flags */
 392         pte1 = ctx->raddr;
 393         if (ppc_hash64_pte_update_flags(ctx, &pte1, ret, rwx) == 1) {
 394             ppc_hash64_store_hpte1(env, pteg_off + good * HASH_PTE_SIZE_64, pte1);
 395         }
 396     }
 397
 398     /* We have a TLB that saves 4K pages, so let's
 399      * split a huge page to 4k chunks */
 400     if (target_page_bits != TARGET_PAGE_BITS) {
 401         ctx->raddr |= (eaddr & ((1 << target_page_bits) - 1))
 402                       & TARGET_PAGE_MASK;
 403     }
 404     return ret;
 405 }
 406
 407 static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
 408                                 target_ulong eaddr, int rwx)
 409 {
 410     hwaddr hash;
 411     target_ulong vsid;
 412     int pr, target_page_bits;
 413     int ret, ret2;
 414     ppc_slb_t *slb;
 415     target_ulong pageaddr;
 416     int segment_bits;
 417
 418     /* 1. Handle real mode accesses */
 419     if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
 420         /* Translation is off */
 421         /* In real mode the top 4 effective address bits are ignored */
 422         ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
 423         ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
 424         return 0;
 425     }
 426
 427     /* 2. Translation is on, so look up the SLB */
 428     slb = slb_lookup(env, eaddr);
 429
 430     if (!slb) {
 431         return -5;
 432     }
 433
 434     /* 3. Check for segment level no-execute violation */
 435     if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
 436         return -3;
 437     }
 438
 439     pr = msr_pr;
 440
 441     if (slb->vsid & SLB_VSID_B) {
 442         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
 443         segment_bits = 40;
 444     } else {
 445         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
 446         segment_bits = 28;
 447     }
 448
 449     target_page_bits = (slb->vsid & SLB_VSID_L)
 450         ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
 451     ctx->key = !!(pr ? (slb->vsid & SLB_VSID_KP)
 452                   : (slb->vsid & SLB_VSID_KS));
 453
 454     pageaddr = eaddr & ((1ULL << segment_bits)
 455                             - (1ULL << target_page_bits));
 456     if (slb->vsid & SLB_VSID_B) {
 457         hash = vsid ^ (vsid << 25) ^ (pageaddr >> target_page_bits);
 458     } else {
 459         hash = vsid ^ (pageaddr >> target_page_bits);
 460     }
 461     /* Only 5 bits of the page index are used in the AVPN */
 462     ctx->ptem = (slb->vsid & SLB_VSID_PTEM) |
 463         ((pageaddr >> 16) & ((1ULL << segment_bits) - 0x80));
 464
 465     LOG_MMU("pte segment: key=%d nx %d vsid " TARGET_FMT_lx "\n",
 466             ctx->key, !!(slb->vsid & SLB_VSID_N), vsid);
 467     ret = -1;
 468
 469     /* Page address translation */
 470     LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
 471             " hash " TARGET_FMT_plx "\n",
 472             env->htab_base, env->htab_mask, hash);
 473     ctx->hash[0] = hash;
 474     ctx->hash[1] = ~hash;
 475
 476     LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 477             " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
 478             " hash=" TARGET_FMT_plx "\n",
 479             env->htab_base, env->htab_mask, vsid, ctx->ptem,
 480             ctx->hash[0]);
 481     /* Primary table lookup */
 482     ret = find_pte64(env, ctx, eaddr, 0, rwx, target_page_bits);
 483     if (ret == -1) {
 484         /* Secondary table lookup */
 485         LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 486                 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
 487                 " hash=" TARGET_FMT_plx "\n", env->htab_base,
 488                 env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
 489         ret2 = find_pte64(env, ctx, eaddr, 1, rwx, target_page_bits);
 490         if (ret2 != -1) {
 491             ret = ret2;
 492         }
 493     }
 494
 495     return ret;
 496 }
 497
 498 hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
 499 {
 500     struct mmu_ctx_hash64 ctx;
 501
 502     if (unlikely(ppc_hash64_translate(env, &ctx, addr, 0) != 0)) {
 503         return -1;
 504     }
 505
 506     return ctx.raddr & TARGET_PAGE_MASK;
 507 }
 508
 509 int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rwx,
 510                                 int mmu_idx)
 511 {
 512     struct mmu_ctx_hash64 ctx;
 513     int ret = 0;
 514
 515     ret = ppc_hash64_translate(env, &ctx, address, rwx);
 516     if (ret == 0) {
 517         tlb_set_page(env, address & TARGET_PAGE_MASK,
 518                      ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
 519                      mmu_idx, TARGET_PAGE_SIZE);
 520         ret = 0;
 521     } else if (ret < 0) {
 522         LOG_MMU_STATE(env);
 523         if (rwx == 2) {
 524             switch (ret) {
 525             case -1:
 526                 env->exception_index = POWERPC_EXCP_ISI;
 527                 env->error_code = 0x40000000;
 528                 break;
 529             case -2:
 530                 /* Access rights violation */
 531                 env->exception_index = POWERPC_EXCP_ISI;
 532                 env->error_code = 0x08000000;
 533                 break;
 534             case -3:
 535                 /* No execute protection violation */
 536                 env->exception_index = POWERPC_EXCP_ISI;
 537                 env->error_code = 0x10000000;
 538                 break;
 539             case -5:
 540                 /* No match in segment table */
 541                 env->exception_index = POWERPC_EXCP_ISEG;
 542                 env->error_code = 0;
 543                 break;
 544             }
 545         } else {
 546             switch (ret) {
 547             case -1:
 548                 /* No matches in page tables or TLB */
 549                 env->exception_index = POWERPC_EXCP_DSI;
 550                 env->error_code = 0;
 551                 env->spr[SPR_DAR] = address;
 552                 if (rwx == 1) {
 553                     env->spr[SPR_DSISR] = 0x42000000;
 554                 } else {
 555                     env->spr[SPR_DSISR] = 0x40000000;
 556                 }
 557                 break;
 558             case -2:
 559                 /* Access rights violation */
 560                 env->exception_index = POWERPC_EXCP_DSI;
 561                 env->error_code = 0;
 562                 env->spr[SPR_DAR] = address;
 563                 if (rwx == 1) {
 564                     env->spr[SPR_DSISR] = 0x0A000000;
 565                 } else {
 566                     env->spr[SPR_DSISR] = 0x08000000;
 567                 }
 568                 break;
 569             case -5:
 570                 /* No match in segment table */
 571                 env->exception_index = POWERPC_EXCP_DSEG;
 572                 env->error_code = 0;
 573                 env->spr[SPR_DAR] = address;
 574                 break;
 575             }
 576         }
 577 #if 0
 578         printf("%s: set exception to %d %02x\n", __func__,
 579                env->exception, env->error_code);
 580 #endif
 581         ret = 1;
 582     }
 583
 584     return ret;
 585 }