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PPC: Add dump_mmu() for 6xx
[qemu.git] / target-ppc / mmu_helper.c
1 /*
2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "cpu.h"
20 #include "helper.h"
21 #include "sysemu/kvm.h"
22 #include "kvm_ppc.h"
23 #include "mmu-hash64.h"
24 #include "mmu-hash32.h"
25
26 //#define DEBUG_MMU
27 //#define DEBUG_BATS
28 //#define DEBUG_SOFTWARE_TLB
29 //#define DUMP_PAGE_TABLES
30 //#define DEBUG_SOFTWARE_TLB
31 //#define FLUSH_ALL_TLBS
32
33 #ifdef DEBUG_MMU
34 # define LOG_MMU(...) qemu_log(__VA_ARGS__)
35 # define LOG_MMU_STATE(env) log_cpu_state((env), 0)
36 #else
37 # define LOG_MMU(...) do { } while (0)
38 # define LOG_MMU_STATE(...) do { } while (0)
39 #endif
40
41 #ifdef DEBUG_SOFTWARE_TLB
42 # define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
43 #else
44 # define LOG_SWTLB(...) do { } while (0)
45 #endif
46
47 #ifdef DEBUG_BATS
48 # define LOG_BATS(...) qemu_log(__VA_ARGS__)
49 #else
50 # define LOG_BATS(...) do { } while (0)
51 #endif
52
53 /*****************************************************************************/
54 /* PowerPC MMU emulation */
55
56 /* Context used internally during MMU translations */
57 typedef struct mmu_ctx_t mmu_ctx_t;
58 struct mmu_ctx_t {
59 hwaddr raddr; /* Real address */
60 hwaddr eaddr; /* Effective address */
61 int prot; /* Protection bits */
62 hwaddr hash[2]; /* Pagetable hash values */
63 target_ulong ptem; /* Virtual segment ID | API */
64 int key; /* Access key */
65 int nx; /* Non-execute area */
66 };
67
68 /* Common routines used by software and hardware TLBs emulation */
69 static inline int pte_is_valid(target_ulong pte0)
70 {
71 return pte0 & 0x80000000 ? 1 : 0;
72 }
73
74 static inline void pte_invalidate(target_ulong *pte0)
75 {
76 *pte0 &= ~0x80000000;
77 }
78
79 #define PTE_PTEM_MASK 0x7FFFFFBF
80 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
81
82 static int pp_check(int key, int pp, int nx)
83 {
84 int access;
85
86 /* Compute access rights */
87 access = 0;
88 if (key == 0) {
89 switch (pp) {
90 case 0x0:
91 case 0x1:
92 case 0x2:
93 access |= PAGE_WRITE;
94 /* No break here */
95 case 0x3:
96 access |= PAGE_READ;
97 break;
98 }
99 } else {
100 switch (pp) {
101 case 0x0:
102 access = 0;
103 break;
104 case 0x1:
105 case 0x3:
106 access = PAGE_READ;
107 break;
108 case 0x2:
109 access = PAGE_READ | PAGE_WRITE;
110 break;
111 }
112 }
113 if (nx == 0) {
114 access |= PAGE_EXEC;
115 }
116
117 return access;
118 }
119
120 static int check_prot(int prot, int rw, int access_type)
121 {
122 int ret;
123
124 if (access_type == ACCESS_CODE) {
125 if (prot & PAGE_EXEC) {
126 ret = 0;
127 } else {
128 ret = -2;
129 }
130 } else if (rw) {
131 if (prot & PAGE_WRITE) {
132 ret = 0;
133 } else {
134 ret = -2;
135 }
136 } else {
137 if (prot & PAGE_READ) {
138 ret = 0;
139 } else {
140 ret = -2;
141 }
142 }
143
144 return ret;
145 }
146
147 static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
148 target_ulong pte1, int h, int rw, int type)
149 {
150 target_ulong ptem, mmask;
151 int access, ret, pteh, ptev, pp;
152
153 ret = -1;
154 /* Check validity and table match */
155 ptev = pte_is_valid(pte0);
156 pteh = (pte0 >> 6) & 1;
157 if (ptev && h == pteh) {
158 /* Check vsid & api */
159 ptem = pte0 & PTE_PTEM_MASK;
160 mmask = PTE_CHECK_MASK;
161 pp = pte1 & 0x00000003;
162 if (ptem == ctx->ptem) {
163 if (ctx->raddr != (hwaddr)-1ULL) {
164 /* all matches should have equal RPN, WIMG & PP */
165 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
166 qemu_log("Bad RPN/WIMG/PP\n");
167 return -3;
168 }
169 }
170 /* Compute access rights */
171 access = pp_check(ctx->key, pp, ctx->nx);
172 /* Keep the matching PTE informations */
173 ctx->raddr = pte1;
174 ctx->prot = access;
175 ret = check_prot(ctx->prot, rw, type);
176 if (ret == 0) {
177 /* Access granted */
178 LOG_MMU("PTE access granted !\n");
179 } else {
180 /* Access right violation */
181 LOG_MMU("PTE access rejected\n");
182 }
183 }
184 }
185
186 return ret;
187 }
188
189 static int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
190 int ret, int rw)
191 {
192 int store = 0;
193
194 /* Update page flags */
195 if (!(*pte1p & 0x00000100)) {
196 /* Update accessed flag */
197 *pte1p |= 0x00000100;
198 store = 1;
199 }
200 if (!(*pte1p & 0x00000080)) {
201 if (rw == 1 && ret == 0) {
202 /* Update changed flag */
203 *pte1p |= 0x00000080;
204 store = 1;
205 } else {
206 /* Force page fault for first write access */
207 ctx->prot &= ~PAGE_WRITE;
208 }
209 }
210
211 return store;
212 }
213
214 /* Software driven TLB helpers */
215 static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
216 int way, int is_code)
217 {
218 int nr;
219
220 /* Select TLB num in a way from address */
221 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
222 /* Select TLB way */
223 nr += env->tlb_per_way * way;
224 /* 6xx have separate TLBs for instructions and data */
225 if (is_code && env->id_tlbs == 1) {
226 nr += env->nb_tlb;
227 }
228
229 return nr;
230 }
231
232 static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
233 {
234 ppc6xx_tlb_t *tlb;
235 int nr, max;
236
237 /* LOG_SWTLB("Invalidate all TLBs\n"); */
238 /* Invalidate all defined software TLB */
239 max = env->nb_tlb;
240 if (env->id_tlbs == 1) {
241 max *= 2;
242 }
243 for (nr = 0; nr < max; nr++) {
244 tlb = &env->tlb.tlb6[nr];
245 pte_invalidate(&tlb->pte0);
246 }
247 tlb_flush(env, 1);
248 }
249
250 static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
251 target_ulong eaddr,
252 int is_code, int match_epn)
253 {
254 #if !defined(FLUSH_ALL_TLBS)
255 ppc6xx_tlb_t *tlb;
256 int way, nr;
257
258 /* Invalidate ITLB + DTLB, all ways */
259 for (way = 0; way < env->nb_ways; way++) {
260 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
261 tlb = &env->tlb.tlb6[nr];
262 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
263 LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
264 env->nb_tlb, eaddr);
265 pte_invalidate(&tlb->pte0);
266 tlb_flush_page(env, tlb->EPN);
267 }
268 }
269 #else
270 /* XXX: PowerPC specification say this is valid as well */
271 ppc6xx_tlb_invalidate_all(env);
272 #endif
273 }
274
275 static inline void ppc6xx_tlb_invalidate_virt(CPUPPCState *env,
276 target_ulong eaddr, int is_code)
277 {
278 ppc6xx_tlb_invalidate_virt2(env, eaddr, is_code, 0);
279 }
280
281 static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way,
282 int is_code, target_ulong pte0, target_ulong pte1)
283 {
284 ppc6xx_tlb_t *tlb;
285 int nr;
286
287 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
288 tlb = &env->tlb.tlb6[nr];
289 LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
290 " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
291 /* Invalidate any pending reference in QEMU for this virtual address */
292 ppc6xx_tlb_invalidate_virt2(env, EPN, is_code, 1);
293 tlb->pte0 = pte0;
294 tlb->pte1 = pte1;
295 tlb->EPN = EPN;
296 /* Store last way for LRU mechanism */
297 env->last_way = way;
298 }
299
300 static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
301 target_ulong eaddr, int rw, int access_type)
302 {
303 ppc6xx_tlb_t *tlb;
304 int nr, best, way;
305 int ret;
306
307 best = -1;
308 ret = -1; /* No TLB found */
309 for (way = 0; way < env->nb_ways; way++) {
310 nr = ppc6xx_tlb_getnum(env, eaddr, way,
311 access_type == ACCESS_CODE ? 1 : 0);
312 tlb = &env->tlb.tlb6[nr];
313 /* This test "emulates" the PTE index match for hardware TLBs */
314 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
315 LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx
316 "] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb,
317 pte_is_valid(tlb->pte0) ? "valid" : "inval",
318 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
319 continue;
320 }
321 LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " "
322 TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,
323 pte_is_valid(tlb->pte0) ? "valid" : "inval",
324 tlb->EPN, eaddr, tlb->pte1,
325 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
326 switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
327 case -3:
328 /* TLB inconsistency */
329 return -1;
330 case -2:
331 /* Access violation */
332 ret = -2;
333 best = nr;
334 break;
335 case -1:
336 default:
337 /* No match */
338 break;
339 case 0:
340 /* access granted */
341 /* XXX: we should go on looping to check all TLBs consistency
342 * but we can speed-up the whole thing as the
343 * result would be undefined if TLBs are not consistent.
344 */
345 ret = 0;
346 best = nr;
347 goto done;
348 }
349 }
350 if (best != -1) {
351 done:
352 LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",
353 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
354 /* Update page flags */
355 pte_update_flags(ctx, &env->tlb.tlb6[best].pte1, ret, rw);
356 }
357
358 return ret;
359 }
360
361 /* Perform BAT hit & translation */
362 static inline void bat_size_prot(CPUPPCState *env, target_ulong *blp,
363 int *validp, int *protp, target_ulong *BATu,
364 target_ulong *BATl)
365 {
366 target_ulong bl;
367 int pp, valid, prot;
368
369 bl = (*BATu & 0x00001FFC) << 15;
370 valid = 0;
371 prot = 0;
372 if (((msr_pr == 0) && (*BATu & 0x00000002)) ||
373 ((msr_pr != 0) && (*BATu & 0x00000001))) {
374 valid = 1;
375 pp = *BATl & 0x00000003;
376 if (pp != 0) {
377 prot = PAGE_READ | PAGE_EXEC;
378 if (pp == 0x2) {
379 prot |= PAGE_WRITE;
380 }
381 }
382 }
383 *blp = bl;
384 *validp = valid;
385 *protp = prot;
386 }
387
388 static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
389 target_ulong virtual, int rw, int type)
390 {
391 target_ulong *BATlt, *BATut, *BATu, *BATl;
392 target_ulong BEPIl, BEPIu, bl;
393 int i, valid, prot;
394 int ret = -1;
395
396 LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
397 type == ACCESS_CODE ? 'I' : 'D', virtual);
398 switch (type) {
399 case ACCESS_CODE:
400 BATlt = env->IBAT[1];
401 BATut = env->IBAT[0];
402 break;
403 default:
404 BATlt = env->DBAT[1];
405 BATut = env->DBAT[0];
406 break;
407 }
408 for (i = 0; i < env->nb_BATs; i++) {
409 BATu = &BATut[i];
410 BATl = &BATlt[i];
411 BEPIu = *BATu & 0xF0000000;
412 BEPIl = *BATu & 0x0FFE0000;
413 bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
414 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
415 " BATl " TARGET_FMT_lx "\n", __func__,
416 type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
417 if ((virtual & 0xF0000000) == BEPIu &&
418 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
419 /* BAT matches */
420 if (valid != 0) {
421 /* Get physical address */
422 ctx->raddr = (*BATl & 0xF0000000) |
423 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
424 (virtual & 0x0001F000);
425 /* Compute access rights */
426 ctx->prot = prot;
427 ret = check_prot(ctx->prot, rw, type);
428 if (ret == 0) {
429 LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n",
430 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
431 ctx->prot & PAGE_WRITE ? 'W' : '-');
432 }
433 break;
434 }
435 }
436 }
437 if (ret < 0) {
438 #if defined(DEBUG_BATS)
439 if (qemu_log_enabled()) {
440 LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual);
441 for (i = 0; i < 4; i++) {
442 BATu = &BATut[i];
443 BATl = &BATlt[i];
444 BEPIu = *BATu & 0xF0000000;
445 BEPIl = *BATu & 0x0FFE0000;
446 bl = (*BATu & 0x00001FFC) << 15;
447 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
448 " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
449 TARGET_FMT_lx " " TARGET_FMT_lx "\n",
450 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
451 *BATu, *BATl, BEPIu, BEPIl, bl);
452 }
453 }
454 #endif
455 }
456 /* No hit */
457 return ret;
458 }
459
460 /* Perform segment based translation */
461 static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
462 target_ulong eaddr, int rw, int type)
463 {
464 hwaddr hash;
465 target_ulong vsid;
466 int ds, pr, target_page_bits;
467 int ret;
468 target_ulong sr, pgidx;
469
470 pr = msr_pr;
471 ctx->eaddr = eaddr;
472
473 sr = env->sr[eaddr >> 28];
474 ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
475 ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
476 ds = sr & 0x80000000 ? 1 : 0;
477 ctx->nx = sr & 0x10000000 ? 1 : 0;
478 vsid = sr & 0x00FFFFFF;
479 target_page_bits = TARGET_PAGE_BITS;
480 LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
481 TARGET_FMT_lx " lr=" TARGET_FMT_lx
482 " ir=%d dr=%d pr=%d %d t=%d\n",
483 eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
484 (int)msr_dr, pr != 0 ? 1 : 0, rw, type);
485 pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
486 hash = vsid ^ pgidx;
487 ctx->ptem = (vsid << 7) | (pgidx >> 10);
488
489 LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
490 ctx->key, ds, ctx->nx, vsid);
491 ret = -1;
492 if (!ds) {
493 /* Check if instruction fetch is allowed, if needed */
494 if (type != ACCESS_CODE || ctx->nx == 0) {
495 /* Page address translation */
496 LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
497 " hash " TARGET_FMT_plx "\n",
498 env->htab_base, env->htab_mask, hash);
499 ctx->hash[0] = hash;
500 ctx->hash[1] = ~hash;
501
502 /* Initialize real address with an invalid value */
503 ctx->raddr = (hwaddr)-1ULL;
504 /* Software TLB search */
505 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
506 #if defined(DUMP_PAGE_TABLES)
507 if (qemu_log_enabled()) {
508 hwaddr curaddr;
509 uint32_t a0, a1, a2, a3;
510
511 qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
512 "\n", sdr, mask + 0x80);
513 for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
514 curaddr += 16) {
515 a0 = ldl_phys(curaddr);
516 a1 = ldl_phys(curaddr + 4);
517 a2 = ldl_phys(curaddr + 8);
518 a3 = ldl_phys(curaddr + 12);
519 if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
520 qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
521 curaddr, a0, a1, a2, a3);
522 }
523 }
524 }
525 #endif
526 } else {
527 LOG_MMU("No access allowed\n");
528 ret = -3;
529 }
530 } else {
531 target_ulong sr;
532
533 LOG_MMU("direct store...\n");
534 /* Direct-store segment : absolutely *BUGGY* for now */
535
536 /* Direct-store implies a 32-bit MMU.
537 * Check the Segment Register's bus unit ID (BUID).
538 */
539 sr = env->sr[eaddr >> 28];
540 if ((sr & 0x1FF00000) >> 20 == 0x07f) {
541 /* Memory-forced I/O controller interface access */
542 /* If T=1 and BUID=x'07F', the 601 performs a memory access
543 * to SR[28-31] LA[4-31], bypassing all protection mechanisms.
544 */
545 ctx->raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
546 ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
547 return 0;
548 }
549
550 switch (type) {
551 case ACCESS_INT:
552 /* Integer load/store : only access allowed */
553 break;
554 case ACCESS_CODE:
555 /* No code fetch is allowed in direct-store areas */
556 return -4;
557 case ACCESS_FLOAT:
558 /* Floating point load/store */
559 return -4;
560 case ACCESS_RES:
561 /* lwarx, ldarx or srwcx. */
562 return -4;
563 case ACCESS_CACHE:
564 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
565 /* Should make the instruction do no-op.
566 * As it already do no-op, it's quite easy :-)
567 */
568 ctx->raddr = eaddr;
569 return 0;
570 case ACCESS_EXT:
571 /* eciwx or ecowx */
572 return -4;
573 default:
574 qemu_log("ERROR: instruction should not need "
575 "address translation\n");
576 return -4;
577 }
578 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
579 ctx->raddr = eaddr;
580 ret = 2;
581 } else {
582 ret = -2;
583 }
584 }
585
586 return ret;
587 }
588
589 /* Generic TLB check function for embedded PowerPC implementations */
590 static int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
591 hwaddr *raddrp,
592 target_ulong address, uint32_t pid, int ext,
593 int i)
594 {
595 target_ulong mask;
596
597 /* Check valid flag */
598 if (!(tlb->prot & PAGE_VALID)) {
599 return -1;
600 }
601 mask = ~(tlb->size - 1);
602 LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx " PID %u <=> " TARGET_FMT_lx
603 " " TARGET_FMT_lx " %u %x\n", __func__, i, address, pid, tlb->EPN,
604 mask, (uint32_t)tlb->PID, tlb->prot);
605 /* Check PID */
606 if (tlb->PID != 0 && tlb->PID != pid) {
607 return -1;
608 }
609 /* Check effective address */
610 if ((address & mask) != tlb->EPN) {
611 return -1;
612 }
613 *raddrp = (tlb->RPN & mask) | (address & ~mask);
614 if (ext) {
615 /* Extend the physical address to 36 bits */
616 *raddrp |= (uint64_t)(tlb->RPN & 0xF) << 32;
617 }
618
619 return 0;
620 }
621
622 /* Generic TLB search function for PowerPC embedded implementations */
623 static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address,
624 uint32_t pid)
625 {
626 ppcemb_tlb_t *tlb;
627 hwaddr raddr;
628 int i, ret;
629
630 /* Default return value is no match */
631 ret = -1;
632 for (i = 0; i < env->nb_tlb; i++) {
633 tlb = &env->tlb.tlbe[i];
634 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
635 ret = i;
636 break;
637 }
638 }
639
640 return ret;
641 }
642
643 /* Helpers specific to PowerPC 40x implementations */
644 static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
645 {
646 ppcemb_tlb_t *tlb;
647 int i;
648
649 for (i = 0; i < env->nb_tlb; i++) {
650 tlb = &env->tlb.tlbe[i];
651 tlb->prot &= ~PAGE_VALID;
652 }
653 tlb_flush(env, 1);
654 }
655
656 static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
657 target_ulong eaddr, uint32_t pid)
658 {
659 #if !defined(FLUSH_ALL_TLBS)
660 ppcemb_tlb_t *tlb;
661 hwaddr raddr;
662 target_ulong page, end;
663 int i;
664
665 for (i = 0; i < env->nb_tlb; i++) {
666 tlb = &env->tlb.tlbe[i];
667 if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
668 end = tlb->EPN + tlb->size;
669 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
670 tlb_flush_page(env, page);
671 }
672 tlb->prot &= ~PAGE_VALID;
673 break;
674 }
675 }
676 #else
677 ppc4xx_tlb_invalidate_all(env);
678 #endif
679 }
680
681 static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
682 target_ulong address, int rw,
683 int access_type)
684 {
685 ppcemb_tlb_t *tlb;
686 hwaddr raddr;
687 int i, ret, zsel, zpr, pr;
688
689 ret = -1;
690 raddr = (hwaddr)-1ULL;
691 pr = msr_pr;
692 for (i = 0; i < env->nb_tlb; i++) {
693 tlb = &env->tlb.tlbe[i];
694 if (ppcemb_tlb_check(env, tlb, &raddr, address,
695 env->spr[SPR_40x_PID], 0, i) < 0) {
696 continue;
697 }
698 zsel = (tlb->attr >> 4) & 0xF;
699 zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3;
700 LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
701 __func__, i, zsel, zpr, rw, tlb->attr);
702 /* Check execute enable bit */
703 switch (zpr) {
704 case 0x2:
705 if (pr != 0) {
706 goto check_perms;
707 }
708 /* No break here */
709 case 0x3:
710 /* All accesses granted */
711 ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
712 ret = 0;
713 break;
714 case 0x0:
715 if (pr != 0) {
716 /* Raise Zone protection fault. */
717 env->spr[SPR_40x_ESR] = 1 << 22;
718 ctx->prot = 0;
719 ret = -2;
720 break;
721 }
722 /* No break here */
723 case 0x1:
724 check_perms:
725 /* Check from TLB entry */
726 ctx->prot = tlb->prot;
727 ret = check_prot(ctx->prot, rw, access_type);
728 if (ret == -2) {
729 env->spr[SPR_40x_ESR] = 0;
730 }
731 break;
732 }
733 if (ret >= 0) {
734 ctx->raddr = raddr;
735 LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
736 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
737 ret);
738 return 0;
739 }
740 }
741 LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx
742 " %d %d\n", __func__, address, raddr, ctx->prot, ret);
743
744 return ret;
745 }
746
747 void store_40x_sler(CPUPPCState *env, uint32_t val)
748 {
749 /* XXX: TO BE FIXED */
750 if (val != 0x00000000) {
751 cpu_abort(env, "Little-endian regions are not supported by now\n");
752 }
753 env->spr[SPR_405_SLER] = val;
754 }
755
756 static inline int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
757 hwaddr *raddr, int *prot,
758 target_ulong address, int rw,
759 int access_type, int i)
760 {
761 int ret, prot2;
762
763 if (ppcemb_tlb_check(env, tlb, raddr, address,
764 env->spr[SPR_BOOKE_PID],
765 !env->nb_pids, i) >= 0) {
766 goto found_tlb;
767 }
768
769 if (env->spr[SPR_BOOKE_PID1] &&
770 ppcemb_tlb_check(env, tlb, raddr, address,
771 env->spr[SPR_BOOKE_PID1], 0, i) >= 0) {
772 goto found_tlb;
773 }
774
775 if (env->spr[SPR_BOOKE_PID2] &&
776 ppcemb_tlb_check(env, tlb, raddr, address,
777 env->spr[SPR_BOOKE_PID2], 0, i) >= 0) {
778 goto found_tlb;
779 }
780
781 LOG_SWTLB("%s: TLB entry not found\n", __func__);
782 return -1;
783
784 found_tlb:
785
786 if (msr_pr != 0) {
787 prot2 = tlb->prot & 0xF;
788 } else {
789 prot2 = (tlb->prot >> 4) & 0xF;
790 }
791
792 /* Check the address space */
793 if (access_type == ACCESS_CODE) {
794 if (msr_ir != (tlb->attr & 1)) {
795 LOG_SWTLB("%s: AS doesn't match\n", __func__);
796 return -1;
797 }
798
799 *prot = prot2;
800 if (prot2 & PAGE_EXEC) {
801 LOG_SWTLB("%s: good TLB!\n", __func__);
802 return 0;
803 }
804
805 LOG_SWTLB("%s: no PAGE_EXEC: %x\n", __func__, prot2);
806 ret = -3;
807 } else {
808 if (msr_dr != (tlb->attr & 1)) {
809 LOG_SWTLB("%s: AS doesn't match\n", __func__);
810 return -1;
811 }
812
813 *prot = prot2;
814 if ((!rw && prot2 & PAGE_READ) || (rw && (prot2 & PAGE_WRITE))) {
815 LOG_SWTLB("%s: found TLB!\n", __func__);
816 return 0;
817 }
818
819 LOG_SWTLB("%s: PAGE_READ/WRITE doesn't match: %x\n", __func__, prot2);
820 ret = -2;
821 }
822
823 return ret;
824 }
825
826 static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
827 target_ulong address, int rw,
828 int access_type)
829 {
830 ppcemb_tlb_t *tlb;
831 hwaddr raddr;
832 int i, ret;
833
834 ret = -1;
835 raddr = (hwaddr)-1ULL;
836 for (i = 0; i < env->nb_tlb; i++) {
837 tlb = &env->tlb.tlbe[i];
838 ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw,
839 access_type, i);
840 if (!ret) {
841 break;
842 }
843 }
844
845 if (ret >= 0) {
846 ctx->raddr = raddr;
847 LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
848 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
849 ret);
850 } else {
851 LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx
852 " %d %d\n", __func__, address, raddr, ctx->prot, ret);
853 }
854
855 return ret;
856 }
857
858 static void booke206_flush_tlb(CPUPPCState *env, int flags,
859 const int check_iprot)
860 {
861 int tlb_size;
862 int i, j;
863 ppcmas_tlb_t *tlb = env->tlb.tlbm;
864
865 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
866 if (flags & (1 << i)) {
867 tlb_size = booke206_tlb_size(env, i);
868 for (j = 0; j < tlb_size; j++) {
869 if (!check_iprot || !(tlb[j].mas1 & MAS1_IPROT)) {
870 tlb[j].mas1 &= ~MAS1_VALID;
871 }
872 }
873 }
874 tlb += booke206_tlb_size(env, i);
875 }
876
877 tlb_flush(env, 1);
878 }
879
880 static hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
881 ppcmas_tlb_t *tlb)
882 {
883 int tlbm_size;
884
885 tlbm_size = (tlb->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
886
887 return 1024ULL << tlbm_size;
888 }
889
890 /* TLB check function for MAS based SoftTLBs */
891 static int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
892 hwaddr *raddrp,
893 target_ulong address, uint32_t pid)
894 {
895 target_ulong mask;
896 uint32_t tlb_pid;
897
898 /* Check valid flag */
899 if (!(tlb->mas1 & MAS1_VALID)) {
900 return -1;
901 }
902
903 mask = ~(booke206_tlb_to_page_size(env, tlb) - 1);
904 LOG_SWTLB("%s: TLB ADDR=0x" TARGET_FMT_lx " PID=0x%x MAS1=0x%x MAS2=0x%"
905 PRIx64 " mask=0x" TARGET_FMT_lx " MAS7_3=0x%" PRIx64 " MAS8=%x\n",
906 __func__, address, pid, tlb->mas1, tlb->mas2, mask, tlb->mas7_3,
907 tlb->mas8);
908
909 /* Check PID */
910 tlb_pid = (tlb->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT;
911 if (tlb_pid != 0 && tlb_pid != pid) {
912 return -1;
913 }
914
915 /* Check effective address */
916 if ((address & mask) != (tlb->mas2 & MAS2_EPN_MASK)) {
917 return -1;
918 }
919
920 if (raddrp) {
921 *raddrp = (tlb->mas7_3 & mask) | (address & ~mask);
922 }
923
924 return 0;
925 }
926
927 static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
928 hwaddr *raddr, int *prot,
929 target_ulong address, int rw,
930 int access_type)
931 {
932 int ret;
933 int prot2 = 0;
934
935 if (ppcmas_tlb_check(env, tlb, raddr, address,
936 env->spr[SPR_BOOKE_PID]) >= 0) {
937 goto found_tlb;
938 }
939
940 if (env->spr[SPR_BOOKE_PID1] &&
941 ppcmas_tlb_check(env, tlb, raddr, address,
942 env->spr[SPR_BOOKE_PID1]) >= 0) {
943 goto found_tlb;
944 }
945
946 if (env->spr[SPR_BOOKE_PID2] &&
947 ppcmas_tlb_check(env, tlb, raddr, address,
948 env->spr[SPR_BOOKE_PID2]) >= 0) {
949 goto found_tlb;
950 }
951
952 LOG_SWTLB("%s: TLB entry not found\n", __func__);
953 return -1;
954
955 found_tlb:
956
957 if (msr_pr != 0) {
958 if (tlb->mas7_3 & MAS3_UR) {
959 prot2 |= PAGE_READ;
960 }
961 if (tlb->mas7_3 & MAS3_UW) {
962 prot2 |= PAGE_WRITE;
963 }
964 if (tlb->mas7_3 & MAS3_UX) {
965 prot2 |= PAGE_EXEC;
966 }
967 } else {
968 if (tlb->mas7_3 & MAS3_SR) {
969 prot2 |= PAGE_READ;
970 }
971 if (tlb->mas7_3 & MAS3_SW) {
972 prot2 |= PAGE_WRITE;
973 }
974 if (tlb->mas7_3 & MAS3_SX) {
975 prot2 |= PAGE_EXEC;
976 }
977 }
978
979 /* Check the address space and permissions */
980 if (access_type == ACCESS_CODE) {
981 if (msr_ir != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
982 LOG_SWTLB("%s: AS doesn't match\n", __func__);
983 return -1;
984 }
985
986 *prot = prot2;
987 if (prot2 & PAGE_EXEC) {
988 LOG_SWTLB("%s: good TLB!\n", __func__);
989 return 0;
990 }
991
992 LOG_SWTLB("%s: no PAGE_EXEC: %x\n", __func__, prot2);
993 ret = -3;
994 } else {
995 if (msr_dr != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
996 LOG_SWTLB("%s: AS doesn't match\n", __func__);
997 return -1;
998 }
999
1000 *prot = prot2;
1001 if ((!rw && prot2 & PAGE_READ) || (rw && (prot2 & PAGE_WRITE))) {
1002 LOG_SWTLB("%s: found TLB!\n", __func__);
1003 return 0;
1004 }
1005
1006 LOG_SWTLB("%s: PAGE_READ/WRITE doesn't match: %x\n", __func__, prot2);
1007 ret = -2;
1008 }
1009
1010 return ret;
1011 }
1012
1013 static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
1014 target_ulong address, int rw,
1015 int access_type)
1016 {
1017 ppcmas_tlb_t *tlb;
1018 hwaddr raddr;
1019 int i, j, ret;
1020
1021 ret = -1;
1022 raddr = (hwaddr)-1ULL;
1023
1024 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
1025 int ways = booke206_tlb_ways(env, i);
1026
1027 for (j = 0; j < ways; j++) {
1028 tlb = booke206_get_tlbm(env, i, address, j);
1029 if (!tlb) {
1030 continue;
1031 }
1032 ret = mmubooke206_check_tlb(env, tlb, &raddr, &ctx->prot, address,
1033 rw, access_type);
1034 if (ret != -1) {
1035 goto found_tlb;
1036 }
1037 }
1038 }
1039
1040 found_tlb:
1041
1042 if (ret >= 0) {
1043 ctx->raddr = raddr;
1044 LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
1045 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1046 ret);
1047 } else {
1048 LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx
1049 " %d %d\n", __func__, address, raddr, ctx->prot, ret);
1050 }
1051
1052 return ret;
1053 }
1054
1055 static const char *book3e_tsize_to_str[32] = {
1056 "1K", "2K", "4K", "8K", "16K", "32K", "64K", "128K", "256K", "512K",
1057 "1M", "2M", "4M", "8M", "16M", "32M", "64M", "128M", "256M", "512M",
1058 "1G", "2G", "4G", "8G", "16G", "32G", "64G", "128G", "256G", "512G",
1059 "1T", "2T"
1060 };
1061
1062 static void mmubooke_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
1063 CPUPPCState *env)
1064 {
1065 ppcemb_tlb_t *entry;
1066 int i;
1067
1068 if (kvm_enabled() && !env->kvm_sw_tlb) {
1069 cpu_fprintf(f, "Cannot access KVM TLB\n");
1070 return;
1071 }
1072
1073 cpu_fprintf(f, "\nTLB:\n");
1074 cpu_fprintf(f, "Effective Physical Size PID Prot "
1075 "Attr\n");
1076
1077 entry = &env->tlb.tlbe[0];
1078 for (i = 0; i < env->nb_tlb; i++, entry++) {
1079 hwaddr ea, pa;
1080 target_ulong mask;
1081 uint64_t size = (uint64_t)entry->size;
1082 char size_buf[20];
1083
1084 /* Check valid flag */
1085 if (!(entry->prot & PAGE_VALID)) {
1086 continue;
1087 }
1088
1089 mask = ~(entry->size - 1);
1090 ea = entry->EPN & mask;
1091 pa = entry->RPN & mask;
1092 /* Extend the physical address to 36 bits */
1093 pa |= (hwaddr)(entry->RPN & 0xF) << 32;
1094 size /= 1024;
1095 if (size >= 1024) {
1096 snprintf(size_buf, sizeof(size_buf), "%3" PRId64 "M", size / 1024);
1097 } else {
1098 snprintf(size_buf, sizeof(size_buf), "%3" PRId64 "k", size);
1099 }
1100 cpu_fprintf(f, "0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n",
1101 (uint64_t)ea, (uint64_t)pa, size_buf, (uint32_t)entry->PID,
1102 entry->prot, entry->attr);
1103 }
1104
1105 }
1106
1107 static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf,
1108 CPUPPCState *env, int tlbn, int offset,
1109 int tlbsize)
1110 {
1111 ppcmas_tlb_t *entry;
1112 int i;
1113
1114 cpu_fprintf(f, "\nTLB%d:\n", tlbn);
1115 cpu_fprintf(f, "Effective Physical Size TID TS SRWX"
1116 " URWX WIMGE U0123\n");
1117
1118 entry = &env->tlb.tlbm[offset];
1119 for (i = 0; i < tlbsize; i++, entry++) {
1120 hwaddr ea, pa, size;
1121 int tsize;
1122
1123 if (!(entry->mas1 & MAS1_VALID)) {
1124 continue;
1125 }
1126
1127 tsize = (entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
1128 size = 1024ULL << tsize;
1129 ea = entry->mas2 & ~(size - 1);
1130 pa = entry->mas7_3 & ~(size - 1);
1131
1132 cpu_fprintf(f, "0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c%c"
1133 "U%c%c%c %c%c%c%c%c U%c%c%c%c\n",
1134 (uint64_t)ea, (uint64_t)pa,
1135 book3e_tsize_to_str[tsize],
1136 (entry->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT,
1137 (entry->mas1 & MAS1_TS) >> MAS1_TS_SHIFT,
1138 entry->mas7_3 & MAS3_SR ? 'R' : '-',
1139 entry->mas7_3 & MAS3_SW ? 'W' : '-',
1140 entry->mas7_3 & MAS3_SX ? 'X' : '-',
1141 entry->mas7_3 & MAS3_UR ? 'R' : '-',
1142 entry->mas7_3 & MAS3_UW ? 'W' : '-',
1143 entry->mas7_3 & MAS3_UX ? 'X' : '-',
1144 entry->mas2 & MAS2_W ? 'W' : '-',
1145 entry->mas2 & MAS2_I ? 'I' : '-',
1146 entry->mas2 & MAS2_M ? 'M' : '-',
1147 entry->mas2 & MAS2_G ? 'G' : '-',
1148 entry->mas2 & MAS2_E ? 'E' : '-',
1149 entry->mas7_3 & MAS3_U0 ? '0' : '-',
1150 entry->mas7_3 & MAS3_U1 ? '1' : '-',
1151 entry->mas7_3 & MAS3_U2 ? '2' : '-',
1152 entry->mas7_3 & MAS3_U3 ? '3' : '-');
1153 }
1154 }
1155
1156 static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
1157 CPUPPCState *env)
1158 {
1159 int offset = 0;
1160 int i;
1161
1162 if (kvm_enabled() && !env->kvm_sw_tlb) {
1163 cpu_fprintf(f, "Cannot access KVM TLB\n");
1164 return;
1165 }
1166
1167 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
1168 int size = booke206_tlb_size(env, i);
1169
1170 if (size == 0) {
1171 continue;
1172 }
1173
1174 mmubooke206_dump_one_tlb(f, cpu_fprintf, env, i, offset, size);
1175 offset += size;
1176 }
1177 }
1178
1179 static void mmu6xx_dump_BATs(FILE *f, fprintf_function cpu_fprintf,
1180 CPUPPCState *env, int type)
1181 {
1182 target_ulong *BATlt, *BATut, *BATu, *BATl;
1183 target_ulong BEPIl, BEPIu, bl;
1184 int i;
1185
1186 switch (type) {
1187 case ACCESS_CODE:
1188 BATlt = env->IBAT[1];
1189 BATut = env->IBAT[0];
1190 break;
1191 default:
1192 BATlt = env->DBAT[1];
1193 BATut = env->DBAT[0];
1194 break;
1195 }
1196
1197 for (i = 0; i < env->nb_BATs; i++) {
1198 BATu = &BATut[i];
1199 BATl = &BATlt[i];
1200 BEPIu = *BATu & 0xF0000000;
1201 BEPIl = *BATu & 0x0FFE0000;
1202 bl = (*BATu & 0x00001FFC) << 15;
1203 cpu_fprintf(f, "%s BAT%d BATu " TARGET_FMT_lx
1204 " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
1205 TARGET_FMT_lx " " TARGET_FMT_lx "\n",
1206 type == ACCESS_CODE ? "code" : "data", i,
1207 *BATu, *BATl, BEPIu, BEPIl, bl);
1208 }
1209 }
1210
1211 static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
1212 CPUPPCState *env)
1213 {
1214 ppc6xx_tlb_t *tlb;
1215 target_ulong sr;
1216 int type, way, entry, i;
1217
1218 cpu_fprintf(f, "HTAB base = 0x%"HWADDR_PRIx"\n", env->htab_base);
1219 cpu_fprintf(f, "HTAB mask = 0x%"HWADDR_PRIx"\n", env->htab_mask);
1220
1221 cpu_fprintf(f, "\nSegment registers:\n");
1222 for (i = 0; i < 32; i++) {
1223 sr = env->sr[i];
1224 if (sr & 0x80000000) {
1225 cpu_fprintf(f, "%02d T=%d Ks=%d Kp=%d BUID=0x%03x "
1226 "CNTLR_SPEC=0x%05x\n", i,
1227 sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
1228 sr & 0x20000000 ? 1 : 0, (uint32_t)((sr >> 20) & 0x1FF),
1229 (uint32_t)(sr & 0xFFFFF));
1230 } else {
1231 cpu_fprintf(f, "%02d T=%d Ks=%d Kp=%d N=%d VSID=0x%06x\n", i,
1232 sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0,
1233 sr & 0x20000000 ? 1 : 0, sr & 0x10000000 ? 1 : 0,
1234 (uint32_t)(sr & 0x00FFFFFF));
1235 }
1236 }
1237
1238 cpu_fprintf(f, "\nBATs:\n");
1239 mmu6xx_dump_BATs(f, cpu_fprintf, env, ACCESS_INT);
1240 mmu6xx_dump_BATs(f, cpu_fprintf, env, ACCESS_CODE);
1241
1242 if (env->id_tlbs != 1) {
1243 cpu_fprintf(f, "ERROR: 6xx MMU should have separated TLB"
1244 " for code and data\n");
1245 }
1246
1247 cpu_fprintf(f, "\nTLBs [EPN EPN + SIZE]\n");
1248
1249 for (type = 0; type < 2; type++) {
1250 for (way = 0; way < env->nb_ways; way++) {
1251 for (entry = env->nb_tlb * type + env->tlb_per_way * way;
1252 entry < (env->nb_tlb * type + env->tlb_per_way * (way + 1));
1253 entry++) {
1254
1255 tlb = &env->tlb.tlb6[entry];
1256 cpu_fprintf(f, "%s TLB %02d/%02d way:%d %s ["
1257 TARGET_FMT_lx " " TARGET_FMT_lx "]\n",
1258 type ? "code" : "data", entry % env->nb_tlb,
1259 env->nb_tlb, way,
1260 pte_is_valid(tlb->pte0) ? "valid" : "inval",
1261 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE);
1262 }
1263 }
1264 }
1265 }
1266
1267 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
1268 {
1269 switch (env->mmu_model) {
1270 case POWERPC_MMU_BOOKE:
1271 mmubooke_dump_mmu(f, cpu_fprintf, env);
1272 break;
1273 case POWERPC_MMU_BOOKE206:
1274 mmubooke206_dump_mmu(f, cpu_fprintf, env);
1275 break;
1276 case POWERPC_MMU_SOFT_6xx:
1277 case POWERPC_MMU_SOFT_74xx:
1278 mmu6xx_dump_mmu(f, cpu_fprintf, env);
1279 break;
1280 #if defined(TARGET_PPC64)
1281 case POWERPC_MMU_64B:
1282 case POWERPC_MMU_2_06:
1283 case POWERPC_MMU_2_06a:
1284 case POWERPC_MMU_2_06d:
1285 dump_slb(f, cpu_fprintf, env);
1286 break;
1287 #endif
1288 default:
1289 qemu_log_mask(LOG_UNIMP, "%s: unimplemented\n", __func__);
1290 }
1291 }
1292
1293 static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx,
1294 target_ulong eaddr, int rw)
1295 {
1296 int in_plb, ret;
1297
1298 ctx->raddr = eaddr;
1299 ctx->prot = PAGE_READ | PAGE_EXEC;
1300 ret = 0;
1301 switch (env->mmu_model) {
1302 case POWERPC_MMU_SOFT_6xx:
1303 case POWERPC_MMU_SOFT_74xx:
1304 case POWERPC_MMU_SOFT_4xx:
1305 case POWERPC_MMU_REAL:
1306 case POWERPC_MMU_BOOKE:
1307 ctx->prot |= PAGE_WRITE;
1308 break;
1309
1310 case POWERPC_MMU_SOFT_4xx_Z:
1311 if (unlikely(msr_pe != 0)) {
1312 /* 403 family add some particular protections,
1313 * using PBL/PBU registers for accesses with no translation.
1314 */
1315 in_plb =
1316 /* Check PLB validity */
1317 (env->pb[0] < env->pb[1] &&
1318 /* and address in plb area */
1319 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1320 (env->pb[2] < env->pb[3] &&
1321 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1322 if (in_plb ^ msr_px) {
1323 /* Access in protected area */
1324 if (rw == 1) {
1325 /* Access is not allowed */
1326 ret = -2;
1327 }
1328 } else {
1329 /* Read-write access is allowed */
1330 ctx->prot |= PAGE_WRITE;
1331 }
1332 }
1333 break;
1334
1335 default:
1336 /* Caller's checks mean we should never get here for other models */
1337 abort();
1338 return -1;
1339 }
1340
1341 return ret;
1342 }
1343
1344 static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
1345 target_ulong eaddr, int rw, int access_type)
1346 {
1347 int ret = -1;
1348 bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
1349 || (access_type != ACCESS_CODE && msr_dr == 0);
1350
1351 #if 0
1352 qemu_log("%s\n", __func__);
1353 #endif
1354
1355 switch (env->mmu_model) {
1356 case POWERPC_MMU_SOFT_6xx:
1357 case POWERPC_MMU_SOFT_74xx:
1358 if (real_mode) {
1359 ret = check_physical(env, ctx, eaddr, rw);
1360 } else {
1361 /* Try to find a BAT */
1362 if (env->nb_BATs != 0) {
1363 ret = get_bat_6xx_tlb(env, ctx, eaddr, rw, access_type);
1364 }
1365 if (ret < 0) {
1366 /* We didn't match any BAT entry or don't have BATs */
1367 ret = get_segment_6xx_tlb(env, ctx, eaddr, rw, access_type);
1368 }
1369 }
1370 break;
1371
1372 case POWERPC_MMU_SOFT_4xx:
1373 case POWERPC_MMU_SOFT_4xx_Z:
1374 if (real_mode) {
1375 ret = check_physical(env, ctx, eaddr, rw);
1376 } else {
1377 ret = mmu40x_get_physical_address(env, ctx, eaddr,
1378 rw, access_type);
1379 }
1380 break;
1381 case POWERPC_MMU_BOOKE:
1382 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1383 rw, access_type);
1384 break;
1385 case POWERPC_MMU_BOOKE206:
1386 ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
1387 access_type);
1388 break;
1389 case POWERPC_MMU_MPC8xx:
1390 /* XXX: TODO */
1391 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1392 break;
1393 case POWERPC_MMU_REAL:
1394 if (real_mode) {
1395 ret = check_physical(env, ctx, eaddr, rw);
1396 } else {
1397 cpu_abort(env, "PowerPC in real mode do not do any translation\n");
1398 }
1399 return -1;
1400 default:
1401 cpu_abort(env, "Unknown or invalid MMU model\n");
1402 return -1;
1403 }
1404 #if 0
1405 qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
1406 __func__, eaddr, ret, ctx->raddr);
1407 #endif
1408
1409 return ret;
1410 }
1411
1412 hwaddr cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
1413 {
1414 mmu_ctx_t ctx;
1415
1416 switch (env->mmu_model) {
1417 #if defined(TARGET_PPC64)
1418 case POWERPC_MMU_64B:
1419 case POWERPC_MMU_2_06:
1420 case POWERPC_MMU_2_06a:
1421 case POWERPC_MMU_2_06d:
1422 return ppc_hash64_get_phys_page_debug(env, addr);
1423 #endif
1424
1425 case POWERPC_MMU_32B:
1426 case POWERPC_MMU_601:
1427 return ppc_hash32_get_phys_page_debug(env, addr);
1428
1429 default:
1430 ;
1431 }
1432
1433 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) {
1434 return -1;
1435 }
1436
1437 return ctx.raddr & TARGET_PAGE_MASK;
1438 }
1439
1440 static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
1441 int rw)
1442 {
1443 env->spr[SPR_BOOKE_MAS0] = env->spr[SPR_BOOKE_MAS4] & MAS4_TLBSELD_MASK;
1444 env->spr[SPR_BOOKE_MAS1] = env->spr[SPR_BOOKE_MAS4] & MAS4_TSIZED_MASK;
1445 env->spr[SPR_BOOKE_MAS2] = env->spr[SPR_BOOKE_MAS4] & MAS4_WIMGED_MASK;
1446 env->spr[SPR_BOOKE_MAS3] = 0;
1447 env->spr[SPR_BOOKE_MAS6] = 0;
1448 env->spr[SPR_BOOKE_MAS7] = 0;
1449
1450 /* AS */
1451 if (((rw == 2) && msr_ir) || ((rw != 2) && msr_dr)) {
1452 env->spr[SPR_BOOKE_MAS1] |= MAS1_TS;
1453 env->spr[SPR_BOOKE_MAS6] |= MAS6_SAS;
1454 }
1455
1456 env->spr[SPR_BOOKE_MAS1] |= MAS1_VALID;
1457 env->spr[SPR_BOOKE_MAS2] |= address & MAS2_EPN_MASK;
1458
1459 switch (env->spr[SPR_BOOKE_MAS4] & MAS4_TIDSELD_PIDZ) {
1460 case MAS4_TIDSELD_PID0:
1461 env->spr[SPR_BOOKE_MAS1] |= env->spr[SPR_BOOKE_PID] << MAS1_TID_SHIFT;
1462 break;
1463 case MAS4_TIDSELD_PID1:
1464 env->spr[SPR_BOOKE_MAS1] |= env->spr[SPR_BOOKE_PID1] << MAS1_TID_SHIFT;
1465 break;
1466 case MAS4_TIDSELD_PID2:
1467 env->spr[SPR_BOOKE_MAS1] |= env->spr[SPR_BOOKE_PID2] << MAS1_TID_SHIFT;
1468 break;
1469 }
1470
1471 env->spr[SPR_BOOKE_MAS6] |= env->spr[SPR_BOOKE_PID] << 16;
1472
1473 /* next victim logic */
1474 env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_ESEL_SHIFT;
1475 env->last_way++;
1476 env->last_way &= booke206_tlb_ways(env, 0) - 1;
1477 env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
1478 }
1479
1480 /* Perform address translation */
1481 static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
1482 int rw, int mmu_idx)
1483 {
1484 mmu_ctx_t ctx;
1485 int access_type;
1486 int ret = 0;
1487
1488 if (rw == 2) {
1489 /* code access */
1490 rw = 0;
1491 access_type = ACCESS_CODE;
1492 } else {
1493 /* data access */
1494 access_type = env->access_type;
1495 }
1496 ret = get_physical_address(env, &ctx, address, rw, access_type);
1497 if (ret == 0) {
1498 tlb_set_page(env, address & TARGET_PAGE_MASK,
1499 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1500 mmu_idx, TARGET_PAGE_SIZE);
1501 ret = 0;
1502 } else if (ret < 0) {
1503 LOG_MMU_STATE(env);
1504 if (access_type == ACCESS_CODE) {
1505 switch (ret) {
1506 case -1:
1507 /* No matches in page tables or TLB */
1508 switch (env->mmu_model) {
1509 case POWERPC_MMU_SOFT_6xx:
1510 env->exception_index = POWERPC_EXCP_IFTLB;
1511 env->error_code = 1 << 18;
1512 env->spr[SPR_IMISS] = address;
1513 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1514 goto tlb_miss;
1515 case POWERPC_MMU_SOFT_74xx:
1516 env->exception_index = POWERPC_EXCP_IFTLB;
1517 goto tlb_miss_74xx;
1518 case POWERPC_MMU_SOFT_4xx:
1519 case POWERPC_MMU_SOFT_4xx_Z:
1520 env->exception_index = POWERPC_EXCP_ITLB;
1521 env->error_code = 0;
1522 env->spr[SPR_40x_DEAR] = address;
1523 env->spr[SPR_40x_ESR] = 0x00000000;
1524 break;
1525 case POWERPC_MMU_BOOKE206:
1526 booke206_update_mas_tlb_miss(env, address, rw);
1527 /* fall through */
1528 case POWERPC_MMU_BOOKE:
1529 env->exception_index = POWERPC_EXCP_ITLB;
1530 env->error_code = 0;
1531 env->spr[SPR_BOOKE_DEAR] = address;
1532 return -1;
1533 case POWERPC_MMU_MPC8xx:
1534 /* XXX: TODO */
1535 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1536 break;
1537 case POWERPC_MMU_REAL:
1538 cpu_abort(env, "PowerPC in real mode should never raise "
1539 "any MMU exceptions\n");
1540 return -1;
1541 default:
1542 cpu_abort(env, "Unknown or invalid MMU model\n");
1543 return -1;
1544 }
1545 break;
1546 case -2:
1547 /* Access rights violation */
1548 env->exception_index = POWERPC_EXCP_ISI;
1549 env->error_code = 0x08000000;
1550 break;
1551 case -3:
1552 /* No execute protection violation */
1553 if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
1554 (env->mmu_model == POWERPC_MMU_BOOKE206)) {
1555 env->spr[SPR_BOOKE_ESR] = 0x00000000;
1556 }
1557 env->exception_index = POWERPC_EXCP_ISI;
1558 env->error_code = 0x10000000;
1559 break;
1560 case -4:
1561 /* Direct store exception */
1562 /* No code fetch is allowed in direct-store areas */
1563 env->exception_index = POWERPC_EXCP_ISI;
1564 env->error_code = 0x10000000;
1565 break;
1566 }
1567 } else {
1568 switch (ret) {
1569 case -1:
1570 /* No matches in page tables or TLB */
1571 switch (env->mmu_model) {
1572 case POWERPC_MMU_SOFT_6xx:
1573 if (rw == 1) {
1574 env->exception_index = POWERPC_EXCP_DSTLB;
1575 env->error_code = 1 << 16;
1576 } else {
1577 env->exception_index = POWERPC_EXCP_DLTLB;
1578 env->error_code = 0;
1579 }
1580 env->spr[SPR_DMISS] = address;
1581 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1582 tlb_miss:
1583 env->error_code |= ctx.key << 19;
1584 env->spr[SPR_HASH1] = env->htab_base +
1585 get_pteg_offset32(env, ctx.hash[0]);
1586 env->spr[SPR_HASH2] = env->htab_base +
1587 get_pteg_offset32(env, ctx.hash[1]);
1588 break;
1589 case POWERPC_MMU_SOFT_74xx:
1590 if (rw == 1) {
1591 env->exception_index = POWERPC_EXCP_DSTLB;
1592 } else {
1593 env->exception_index = POWERPC_EXCP_DLTLB;
1594 }
1595 tlb_miss_74xx:
1596 /* Implement LRU algorithm */
1597 env->error_code = ctx.key << 19;
1598 env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1599 ((env->last_way + 1) & (env->nb_ways - 1));
1600 env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
1601 break;
1602 case POWERPC_MMU_SOFT_4xx:
1603 case POWERPC_MMU_SOFT_4xx_Z:
1604 env->exception_index = POWERPC_EXCP_DTLB;
1605 env->error_code = 0;
1606 env->spr[SPR_40x_DEAR] = address;
1607 if (rw) {
1608 env->spr[SPR_40x_ESR] = 0x00800000;
1609 } else {
1610 env->spr[SPR_40x_ESR] = 0x00000000;
1611 }
1612 break;
1613 case POWERPC_MMU_MPC8xx:
1614 /* XXX: TODO */
1615 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1616 break;
1617 case POWERPC_MMU_BOOKE206:
1618 booke206_update_mas_tlb_miss(env, address, rw);
1619 /* fall through */
1620 case POWERPC_MMU_BOOKE:
1621 env->exception_index = POWERPC_EXCP_DTLB;
1622 env->error_code = 0;
1623 env->spr[SPR_BOOKE_DEAR] = address;
1624 env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
1625 return -1;
1626 case POWERPC_MMU_REAL:
1627 cpu_abort(env, "PowerPC in real mode should never raise "
1628 "any MMU exceptions\n");
1629 return -1;
1630 default:
1631 cpu_abort(env, "Unknown or invalid MMU model\n");
1632 return -1;
1633 }
1634 break;
1635 case -2:
1636 /* Access rights violation */
1637 env->exception_index = POWERPC_EXCP_DSI;
1638 env->error_code = 0;
1639 if (env->mmu_model == POWERPC_MMU_SOFT_4xx
1640 || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) {
1641 env->spr[SPR_40x_DEAR] = address;
1642 if (rw) {
1643 env->spr[SPR_40x_ESR] |= 0x00800000;
1644 }
1645 } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
1646 (env->mmu_model == POWERPC_MMU_BOOKE206)) {
1647 env->spr[SPR_BOOKE_DEAR] = address;
1648 env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
1649 } else {
1650 env->spr[SPR_DAR] = address;
1651 if (rw == 1) {
1652 env->spr[SPR_DSISR] = 0x0A000000;
1653 } else {
1654 env->spr[SPR_DSISR] = 0x08000000;
1655 }
1656 }
1657 break;
1658 case -4:
1659 /* Direct store exception */
1660 switch (access_type) {
1661 case ACCESS_FLOAT:
1662 /* Floating point load/store */
1663 env->exception_index = POWERPC_EXCP_ALIGN;
1664 env->error_code = POWERPC_EXCP_ALIGN_FP;
1665 env->spr[SPR_DAR] = address;
1666 break;
1667 case ACCESS_RES:
1668 /* lwarx, ldarx or stwcx. */
1669 env->exception_index = POWERPC_EXCP_DSI;
1670 env->error_code = 0;
1671 env->spr[SPR_DAR] = address;
1672 if (rw == 1) {
1673 env->spr[SPR_DSISR] = 0x06000000;
1674 } else {
1675 env->spr[SPR_DSISR] = 0x04000000;
1676 }
1677 break;
1678 case ACCESS_EXT:
1679 /* eciwx or ecowx */
1680 env->exception_index = POWERPC_EXCP_DSI;
1681 env->error_code = 0;
1682 env->spr[SPR_DAR] = address;
1683 if (rw == 1) {
1684 env->spr[SPR_DSISR] = 0x06100000;
1685 } else {
1686 env->spr[SPR_DSISR] = 0x04100000;
1687 }
1688 break;
1689 default:
1690 printf("DSI: invalid exception (%d)\n", ret);
1691 env->exception_index = POWERPC_EXCP_PROGRAM;
1692 env->error_code =
1693 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1694 env->spr[SPR_DAR] = address;
1695 break;
1696 }
1697 break;
1698 }
1699 }
1700 #if 0
1701 printf("%s: set exception to %d %02x\n", __func__,
1702 env->exception, env->error_code);
1703 #endif
1704 ret = 1;
1705 }
1706
1707 return ret;
1708 }
1709
1710 /*****************************************************************************/
1711 /* BATs management */
1712 #if !defined(FLUSH_ALL_TLBS)
1713 static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
1714 target_ulong mask)
1715 {
1716 target_ulong base, end, page;
1717
1718 base = BATu & ~0x0001FFFF;
1719 end = base + mask + 0x00020000;
1720 LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
1721 TARGET_FMT_lx ")\n", base, end, mask);
1722 for (page = base; page != end; page += TARGET_PAGE_SIZE) {
1723 tlb_flush_page(env, page);
1724 }
1725 LOG_BATS("Flush done\n");
1726 }
1727 #endif
1728
1729 static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr,
1730 target_ulong value)
1731 {
1732 LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID,
1733 nr, ul == 0 ? 'u' : 'l', value, env->nip);
1734 }
1735
1736 void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value)
1737 {
1738 target_ulong mask;
1739
1740 dump_store_bat(env, 'I', 0, nr, value);
1741 if (env->IBAT[0][nr] != value) {
1742 mask = (value << 15) & 0x0FFE0000UL;
1743 #if !defined(FLUSH_ALL_TLBS)
1744 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1745 #endif
1746 /* When storing valid upper BAT, mask BEPI and BRPN
1747 * and invalidate all TLBs covered by this BAT
1748 */
1749 mask = (value << 15) & 0x0FFE0000UL;
1750 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1751 (value & ~0x0001FFFFUL & ~mask);
1752 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1753 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1754 #if !defined(FLUSH_ALL_TLBS)
1755 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1756 #else
1757 tlb_flush(env, 1);
1758 #endif
1759 }
1760 }
1761
1762 void helper_store_ibatl(CPUPPCState *env, uint32_t nr, target_ulong value)
1763 {
1764 dump_store_bat(env, 'I', 1, nr, value);
1765 env->IBAT[1][nr] = value;
1766 }
1767
1768 void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong value)
1769 {
1770 target_ulong mask;
1771
1772 dump_store_bat(env, 'D', 0, nr, value);
1773 if (env->DBAT[0][nr] != value) {
1774 /* When storing valid upper BAT, mask BEPI and BRPN
1775 * and invalidate all TLBs covered by this BAT
1776 */
1777 mask = (value << 15) & 0x0FFE0000UL;
1778 #if !defined(FLUSH_ALL_TLBS)
1779 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1780 #endif
1781 mask = (value << 15) & 0x0FFE0000UL;
1782 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1783 (value & ~0x0001FFFFUL & ~mask);
1784 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1785 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1786 #if !defined(FLUSH_ALL_TLBS)
1787 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1788 #else
1789 tlb_flush(env, 1);
1790 #endif
1791 }
1792 }
1793
1794 void helper_store_dbatl(CPUPPCState *env, uint32_t nr, target_ulong value)
1795 {
1796 dump_store_bat(env, 'D', 1, nr, value);
1797 env->DBAT[1][nr] = value;
1798 }
1799
1800 void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong value)
1801 {
1802 target_ulong mask;
1803 #if defined(FLUSH_ALL_TLBS)
1804 int do_inval;
1805 #endif
1806
1807 dump_store_bat(env, 'I', 0, nr, value);
1808 if (env->IBAT[0][nr] != value) {
1809 #if defined(FLUSH_ALL_TLBS)
1810 do_inval = 0;
1811 #endif
1812 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1813 if (env->IBAT[1][nr] & 0x40) {
1814 /* Invalidate BAT only if it is valid */
1815 #if !defined(FLUSH_ALL_TLBS)
1816 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1817 #else
1818 do_inval = 1;
1819 #endif
1820 }
1821 /* When storing valid upper BAT, mask BEPI and BRPN
1822 * and invalidate all TLBs covered by this BAT
1823 */
1824 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1825 (value & ~0x0001FFFFUL & ~mask);
1826 env->DBAT[0][nr] = env->IBAT[0][nr];
1827 if (env->IBAT[1][nr] & 0x40) {
1828 #if !defined(FLUSH_ALL_TLBS)
1829 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1830 #else
1831 do_inval = 1;
1832 #endif
1833 }
1834 #if defined(FLUSH_ALL_TLBS)
1835 if (do_inval) {
1836 tlb_flush(env, 1);
1837 }
1838 #endif
1839 }
1840 }
1841
1842 void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
1843 {
1844 #if !defined(FLUSH_ALL_TLBS)
1845 target_ulong mask;
1846 #else
1847 int do_inval;
1848 #endif
1849
1850 dump_store_bat(env, 'I', 1, nr, value);
1851 if (env->IBAT[1][nr] != value) {
1852 #if defined(FLUSH_ALL_TLBS)
1853 do_inval = 0;
1854 #endif
1855 if (env->IBAT[1][nr] & 0x40) {
1856 #if !defined(FLUSH_ALL_TLBS)
1857 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1858 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1859 #else
1860 do_inval = 1;
1861 #endif
1862 }
1863 if (value & 0x40) {
1864 #if !defined(FLUSH_ALL_TLBS)
1865 mask = (value << 17) & 0x0FFE0000UL;
1866 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1867 #else
1868 do_inval = 1;
1869 #endif
1870 }
1871 env->IBAT[1][nr] = value;
1872 env->DBAT[1][nr] = value;
1873 #if defined(FLUSH_ALL_TLBS)
1874 if (do_inval) {
1875 tlb_flush(env, 1);
1876 }
1877 #endif
1878 }
1879 }
1880
1881 /*****************************************************************************/
1882 /* TLB management */
1883 void ppc_tlb_invalidate_all(CPUPPCState *env)
1884 {
1885 switch (env->mmu_model) {
1886 case POWERPC_MMU_SOFT_6xx:
1887 case POWERPC_MMU_SOFT_74xx:
1888 ppc6xx_tlb_invalidate_all(env);
1889 break;
1890 case POWERPC_MMU_SOFT_4xx:
1891 case POWERPC_MMU_SOFT_4xx_Z:
1892 ppc4xx_tlb_invalidate_all(env);
1893 break;
1894 case POWERPC_MMU_REAL:
1895 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1896 break;
1897 case POWERPC_MMU_MPC8xx:
1898 /* XXX: TODO */
1899 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1900 break;
1901 case POWERPC_MMU_BOOKE:
1902 tlb_flush(env, 1);
1903 break;
1904 case POWERPC_MMU_BOOKE206:
1905 booke206_flush_tlb(env, -1, 0);
1906 break;
1907 case POWERPC_MMU_32B:
1908 case POWERPC_MMU_601:
1909 #if defined(TARGET_PPC64)
1910 case POWERPC_MMU_64B:
1911 case POWERPC_MMU_2_06:
1912 case POWERPC_MMU_2_06a:
1913 case POWERPC_MMU_2_06d:
1914 #endif /* defined(TARGET_PPC64) */
1915 tlb_flush(env, 1);
1916 break;
1917 default:
1918 /* XXX: TODO */
1919 cpu_abort(env, "Unknown MMU model\n");
1920 break;
1921 }
1922 }
1923
1924 void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
1925 {
1926 #if !defined(FLUSH_ALL_TLBS)
1927 addr &= TARGET_PAGE_MASK;
1928 switch (env->mmu_model) {
1929 case POWERPC_MMU_SOFT_6xx:
1930 case POWERPC_MMU_SOFT_74xx:
1931 ppc6xx_tlb_invalidate_virt(env, addr, 0);
1932 if (env->id_tlbs == 1) {
1933 ppc6xx_tlb_invalidate_virt(env, addr, 1);
1934 }
1935 break;
1936 case POWERPC_MMU_SOFT_4xx:
1937 case POWERPC_MMU_SOFT_4xx_Z:
1938 ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1939 break;
1940 case POWERPC_MMU_REAL:
1941 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1942 break;
1943 case POWERPC_MMU_MPC8xx:
1944 /* XXX: TODO */
1945 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1946 break;
1947 case POWERPC_MMU_BOOKE:
1948 /* XXX: TODO */
1949 cpu_abort(env, "BookE MMU model is not implemented\n");
1950 break;
1951 case POWERPC_MMU_BOOKE206:
1952 /* XXX: TODO */
1953 cpu_abort(env, "BookE 2.06 MMU model is not implemented\n");
1954 break;
1955 case POWERPC_MMU_32B:
1956 case POWERPC_MMU_601:
1957 /* tlbie invalidate TLBs for all segments */
1958 addr &= ~((target_ulong)-1ULL << 28);
1959 /* XXX: this case should be optimized,
1960 * giving a mask to tlb_flush_page
1961 */
1962 tlb_flush_page(env, addr | (0x0 << 28));
1963 tlb_flush_page(env, addr | (0x1 << 28));
1964 tlb_flush_page(env, addr | (0x2 << 28));
1965 tlb_flush_page(env, addr | (0x3 << 28));
1966 tlb_flush_page(env, addr | (0x4 << 28));
1967 tlb_flush_page(env, addr | (0x5 << 28));
1968 tlb_flush_page(env, addr | (0x6 << 28));
1969 tlb_flush_page(env, addr | (0x7 << 28));
1970 tlb_flush_page(env, addr | (0x8 << 28));
1971 tlb_flush_page(env, addr | (0x9 << 28));
1972 tlb_flush_page(env, addr | (0xA << 28));
1973 tlb_flush_page(env, addr | (0xB << 28));
1974 tlb_flush_page(env, addr | (0xC << 28));
1975 tlb_flush_page(env, addr | (0xD << 28));
1976 tlb_flush_page(env, addr | (0xE << 28));
1977 tlb_flush_page(env, addr | (0xF << 28));
1978 break;
1979 #if defined(TARGET_PPC64)
1980 case POWERPC_MMU_64B:
1981 case POWERPC_MMU_2_06:
1982 case POWERPC_MMU_2_06a:
1983 case POWERPC_MMU_2_06d:
1984 /* tlbie invalidate TLBs for all segments */
1985 /* XXX: given the fact that there are too many segments to invalidate,
1986 * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,
1987 * we just invalidate all TLBs
1988 */
1989 tlb_flush(env, 1);
1990 break;
1991 #endif /* defined(TARGET_PPC64) */
1992 default:
1993 /* XXX: TODO */
1994 cpu_abort(env, "Unknown MMU model\n");
1995 break;
1996 }
1997 #else
1998 ppc_tlb_invalidate_all(env);
1999 #endif
2000 }
2001
2002 /*****************************************************************************/
2003 /* Special registers manipulation */
2004 void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
2005 {
2006 LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
2007 if (env->spr[SPR_SDR1] != value) {
2008 env->spr[SPR_SDR1] = value;
2009 #if defined(TARGET_PPC64)
2010 if (env->mmu_model & POWERPC_MMU_64) {
2011 target_ulong htabsize = value & SDR_64_HTABSIZE;
2012
2013 if (htabsize > 28) {
2014 fprintf(stderr, "Invalid HTABSIZE 0x" TARGET_FMT_lx
2015 " stored in SDR1\n", htabsize);
2016 htabsize = 28;
2017 }
2018 env->htab_mask = (1ULL << (htabsize + 18)) - 1;
2019 env->htab_base = value & SDR_64_HTABORG;
2020 } else
2021 #endif /* defined(TARGET_PPC64) */
2022 {
2023 /* FIXME: Should check for valid HTABMASK values */
2024 env->htab_mask = ((value & SDR_32_HTABMASK) << 16) | 0xFFFF;
2025 env->htab_base = value & SDR_32_HTABORG;
2026 }
2027 tlb_flush(env, 1);
2028 }
2029 }
2030
2031 /* Segment registers load and store */
2032 target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
2033 {
2034 #if defined(TARGET_PPC64)
2035 if (env->mmu_model & POWERPC_MMU_64) {
2036 /* XXX */
2037 return 0;
2038 }
2039 #endif
2040 return env->sr[sr_num];
2041 }
2042
2043 void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
2044 {
2045 LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
2046 (int)srnum, value, env->sr[srnum]);
2047 #if defined(TARGET_PPC64)
2048 if (env->mmu_model & POWERPC_MMU_64) {
2049 uint64_t rb = 0, rs = 0;
2050
2051 /* ESID = srnum */
2052 rb |= ((uint32_t)srnum & 0xf) << 28;
2053 /* Set the valid bit */
2054 rb |= 1 << 27;
2055 /* Index = ESID */
2056 rb |= (uint32_t)srnum;
2057
2058 /* VSID = VSID */
2059 rs |= (value & 0xfffffff) << 12;
2060 /* flags = flags */
2061 rs |= ((value >> 27) & 0xf) << 8;
2062
2063 ppc_store_slb(env, rb, rs);
2064 } else
2065 #endif
2066 if (env->sr[srnum] != value) {
2067 env->sr[srnum] = value;
2068 /* Invalidating 256MB of virtual memory in 4kB pages is way longer than
2069 flusing the whole TLB. */
2070 #if !defined(FLUSH_ALL_TLBS) && 0
2071 {
2072 target_ulong page, end;
2073 /* Invalidate 256 MB of virtual memory */
2074 page = (16 << 20) * srnum;
2075 end = page + (16 << 20);
2076 for (; page != end; page += TARGET_PAGE_SIZE) {
2077 tlb_flush_page(env, page);
2078 }
2079 }
2080 #else
2081 tlb_flush(env, 1);
2082 #endif
2083 }
2084 }
2085
2086 /* TLB management */
2087 void helper_tlbia(CPUPPCState *env)
2088 {
2089 ppc_tlb_invalidate_all(env);
2090 }
2091
2092 void helper_tlbie(CPUPPCState *env, target_ulong addr)
2093 {
2094 ppc_tlb_invalidate_one(env, addr);
2095 }
2096
2097 /* Software driven TLBs management */
2098 /* PowerPC 602/603 software TLB load instructions helpers */
2099 static void do_6xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code)
2100 {
2101 target_ulong RPN, CMP, EPN;
2102 int way;
2103
2104 RPN = env->spr[SPR_RPA];
2105 if (is_code) {
2106 CMP = env->spr[SPR_ICMP];
2107 EPN = env->spr[SPR_IMISS];
2108 } else {
2109 CMP = env->spr[SPR_DCMP];
2110 EPN = env->spr[SPR_DMISS];
2111 }
2112 way = (env->spr[SPR_SRR1] >> 17) & 1;
2113 (void)EPN; /* avoid a compiler warning */
2114 LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
2115 " PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP,
2116 RPN, way);
2117 /* Store this TLB */
2118 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2119 way, is_code, CMP, RPN);
2120 }
2121
2122 void helper_6xx_tlbd(CPUPPCState *env, target_ulong EPN)
2123 {
2124 do_6xx_tlb(env, EPN, 0);
2125 }
2126
2127 void helper_6xx_tlbi(CPUPPCState *env, target_ulong EPN)
2128 {
2129 do_6xx_tlb(env, EPN, 1);
2130 }
2131
2132 /* PowerPC 74xx software TLB load instructions helpers */
2133 static void do_74xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code)
2134 {
2135 target_ulong RPN, CMP, EPN;
2136 int way;
2137
2138 RPN = env->spr[SPR_PTELO];
2139 CMP = env->spr[SPR_PTEHI];
2140 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2141 way = env->spr[SPR_TLBMISS] & 0x3;
2142 (void)EPN; /* avoid a compiler warning */
2143 LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
2144 " PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP,
2145 RPN, way);
2146 /* Store this TLB */
2147 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2148 way, is_code, CMP, RPN);
2149 }
2150
2151 void helper_74xx_tlbd(CPUPPCState *env, target_ulong EPN)
2152 {
2153 do_74xx_tlb(env, EPN, 0);
2154 }
2155
2156 void helper_74xx_tlbi(CPUPPCState *env, target_ulong EPN)
2157 {
2158 do_74xx_tlb(env, EPN, 1);
2159 }
2160
2161 /*****************************************************************************/
2162 /* PowerPC 601 specific instructions (POWER bridge) */
2163
2164 target_ulong helper_rac(CPUPPCState *env, target_ulong addr)
2165 {
2166 mmu_ctx_t ctx;
2167 int nb_BATs;
2168 target_ulong ret = 0;
2169
2170 /* We don't have to generate many instances of this instruction,
2171 * as rac is supervisor only.
2172 */
2173 /* XXX: FIX THIS: Pretend we have no BAT */
2174 nb_BATs = env->nb_BATs;
2175 env->nb_BATs = 0;
2176 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0) {
2177 ret = ctx.raddr;
2178 }
2179 env->nb_BATs = nb_BATs;
2180 return ret;
2181 }
2182
2183 static inline target_ulong booke_tlb_to_page_size(int size)
2184 {
2185 return 1024 << (2 * size);
2186 }
2187
2188 static inline int booke_page_size_to_tlb(target_ulong page_size)
2189 {
2190 int size;
2191
2192 switch (page_size) {
2193 case 0x00000400UL:
2194 size = 0x0;
2195 break;
2196 case 0x00001000UL:
2197 size = 0x1;
2198 break;
2199 case 0x00004000UL:
2200 size = 0x2;
2201 break;
2202 case 0x00010000UL:
2203 size = 0x3;
2204 break;
2205 case 0x00040000UL:
2206 size = 0x4;
2207 break;
2208 case 0x00100000UL:
2209 size = 0x5;
2210 break;
2211 case 0x00400000UL:
2212 size = 0x6;
2213 break;
2214 case 0x01000000UL:
2215 size = 0x7;
2216 break;
2217 case 0x04000000UL:
2218 size = 0x8;
2219 break;
2220 case 0x10000000UL:
2221 size = 0x9;
2222 break;
2223 case 0x40000000UL:
2224 size = 0xA;
2225 break;
2226 #if defined(TARGET_PPC64)
2227 case 0x000100000000ULL:
2228 size = 0xB;
2229 break;
2230 case 0x000400000000ULL:
2231 size = 0xC;
2232 break;
2233 case 0x001000000000ULL:
2234 size = 0xD;
2235 break;
2236 case 0x004000000000ULL:
2237 size = 0xE;
2238 break;
2239 case 0x010000000000ULL:
2240 size = 0xF;
2241 break;
2242 #endif
2243 default:
2244 size = -1;
2245 break;
2246 }
2247
2248 return size;
2249 }
2250
2251 /* Helpers for 4xx TLB management */
2252 #define PPC4XX_TLB_ENTRY_MASK 0x0000003f /* Mask for 64 TLB entries */
2253
2254 #define PPC4XX_TLBHI_V 0x00000040
2255 #define PPC4XX_TLBHI_E 0x00000020
2256 #define PPC4XX_TLBHI_SIZE_MIN 0
2257 #define PPC4XX_TLBHI_SIZE_MAX 7
2258 #define PPC4XX_TLBHI_SIZE_DEFAULT 1
2259 #define PPC4XX_TLBHI_SIZE_SHIFT 7
2260 #define PPC4XX_TLBHI_SIZE_MASK 0x00000007
2261
2262 #define PPC4XX_TLBLO_EX 0x00000200
2263 #define PPC4XX_TLBLO_WR 0x00000100
2264 #define PPC4XX_TLBLO_ATTR_MASK 0x000000FF
2265 #define PPC4XX_TLBLO_RPN_MASK 0xFFFFFC00
2266
2267 target_ulong helper_4xx_tlbre_hi(CPUPPCState *env, target_ulong entry)
2268 {
2269 ppcemb_tlb_t *tlb;
2270 target_ulong ret;
2271 int size;
2272
2273 entry &= PPC4XX_TLB_ENTRY_MASK;
2274 tlb = &env->tlb.tlbe[entry];
2275 ret = tlb->EPN;
2276 if (tlb->prot & PAGE_VALID) {
2277 ret |= PPC4XX_TLBHI_V;
2278 }
2279 size = booke_page_size_to_tlb(tlb->size);
2280 if (size < PPC4XX_TLBHI_SIZE_MIN || size > PPC4XX_TLBHI_SIZE_MAX) {
2281 size = PPC4XX_TLBHI_SIZE_DEFAULT;
2282 }
2283 ret |= size << PPC4XX_TLBHI_SIZE_SHIFT;
2284 env->spr[SPR_40x_PID] = tlb->PID;
2285 return ret;
2286 }
2287
2288 target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, target_ulong entry)
2289 {
2290 ppcemb_tlb_t *tlb;
2291 target_ulong ret;
2292
2293 entry &= PPC4XX_TLB_ENTRY_MASK;
2294 tlb = &env->tlb.tlbe[entry];
2295 ret = tlb->RPN;
2296 if (tlb->prot & PAGE_EXEC) {
2297 ret |= PPC4XX_TLBLO_EX;
2298 }
2299 if (tlb->prot & PAGE_WRITE) {
2300 ret |= PPC4XX_TLBLO_WR;
2301 }
2302 return ret;
2303 }
2304
2305 void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
2306 target_ulong val)
2307 {
2308 ppcemb_tlb_t *tlb;
2309 target_ulong page, end;
2310
2311 LOG_SWTLB("%s entry %d val " TARGET_FMT_lx "\n", __func__, (int)entry,
2312 val);
2313 entry &= PPC4XX_TLB_ENTRY_MASK;
2314 tlb = &env->tlb.tlbe[entry];
2315 /* Invalidate previous TLB (if it's valid) */
2316 if (tlb->prot & PAGE_VALID) {
2317 end = tlb->EPN + tlb->size;
2318 LOG_SWTLB("%s: invalidate old TLB %d start " TARGET_FMT_lx " end "
2319 TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
2320 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
2321 tlb_flush_page(env, page);
2322 }
2323 }
2324 tlb->size = booke_tlb_to_page_size((val >> PPC4XX_TLBHI_SIZE_SHIFT)
2325 & PPC4XX_TLBHI_SIZE_MASK);
2326 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2327 * If this ever occurs, one should use the ppcemb target instead
2328 * of the ppc or ppc64 one
2329 */
2330 if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) {
2331 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2332 "are not supported (%d)\n",
2333 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
2334 }
2335 tlb->EPN = val & ~(tlb->size - 1);
2336 if (val & PPC4XX_TLBHI_V) {
2337 tlb->prot |= PAGE_VALID;
2338 if (val & PPC4XX_TLBHI_E) {
2339 /* XXX: TO BE FIXED */
2340 cpu_abort(env,
2341 "Little-endian TLB entries are not supported by now\n");
2342 }
2343 } else {
2344 tlb->prot &= ~PAGE_VALID;
2345 }
2346 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2347 LOG_SWTLB("%s: set up TLB %d RPN " TARGET_FMT_plx " EPN " TARGET_FMT_lx
2348 " size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
2349 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2350 tlb->prot & PAGE_READ ? 'r' : '-',
2351 tlb->prot & PAGE_WRITE ? 'w' : '-',
2352 tlb->prot & PAGE_EXEC ? 'x' : '-',
2353 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2354 /* Invalidate new TLB (if valid) */
2355 if (tlb->prot & PAGE_VALID) {
2356 end = tlb->EPN + tlb->size;
2357 LOG_SWTLB("%s: invalidate TLB %d start " TARGET_FMT_lx " end "
2358 TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
2359 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
2360 tlb_flush_page(env, page);
2361 }
2362 }
2363 }
2364
2365 void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry,
2366 target_ulong val)
2367 {
2368 ppcemb_tlb_t *tlb;
2369
2370 LOG_SWTLB("%s entry %i val " TARGET_FMT_lx "\n", __func__, (int)entry,
2371 val);
2372 entry &= PPC4XX_TLB_ENTRY_MASK;
2373 tlb = &env->tlb.tlbe[entry];
2374 tlb->attr = val & PPC4XX_TLBLO_ATTR_MASK;
2375 tlb->RPN = val & PPC4XX_TLBLO_RPN_MASK;
2376 tlb->prot = PAGE_READ;
2377 if (val & PPC4XX_TLBLO_EX) {
2378 tlb->prot |= PAGE_EXEC;
2379 }
2380 if (val & PPC4XX_TLBLO_WR) {
2381 tlb->prot |= PAGE_WRITE;
2382 }
2383 LOG_SWTLB("%s: set up TLB %d RPN " TARGET_FMT_plx " EPN " TARGET_FMT_lx
2384 " size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
2385 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2386 tlb->prot & PAGE_READ ? 'r' : '-',
2387 tlb->prot & PAGE_WRITE ? 'w' : '-',
2388 tlb->prot & PAGE_EXEC ? 'x' : '-',
2389 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2390 }
2391
2392 target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address)
2393 {
2394 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
2395 }
2396
2397 /* PowerPC 440 TLB management */
2398 void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
2399 target_ulong value)
2400 {
2401 ppcemb_tlb_t *tlb;
2402 target_ulong EPN, RPN, size;
2403 int do_flush_tlbs;
2404
2405 LOG_SWTLB("%s word %d entry %d value " TARGET_FMT_lx "\n",
2406 __func__, word, (int)entry, value);
2407 do_flush_tlbs = 0;
2408 entry &= 0x3F;
2409 tlb = &env->tlb.tlbe[entry];
2410 switch (word) {
2411 default:
2412 /* Just here to please gcc */
2413 case 0:
2414 EPN = value & 0xFFFFFC00;
2415 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN) {
2416 do_flush_tlbs = 1;
2417 }
2418 tlb->EPN = EPN;
2419 size = booke_tlb_to_page_size((value >> 4) & 0xF);
2420 if ((tlb->prot & PAGE_VALID) && tlb->size < size) {
2421 do_flush_tlbs = 1;
2422 }
2423 tlb->size = size;
2424 tlb->attr &= ~0x1;
2425 tlb->attr |= (value >> 8) & 1;
2426 if (value & 0x200) {
2427 tlb->prot |= PAGE_VALID;
2428 } else {
2429 if (tlb->prot & PAGE_VALID) {
2430 tlb->prot &= ~PAGE_VALID;
2431 do_flush_tlbs = 1;
2432 }
2433 }
2434 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
2435 if (do_flush_tlbs) {
2436 tlb_flush(env, 1);
2437 }
2438 break;
2439 case 1:
2440 RPN = value & 0xFFFFFC0F;
2441 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) {
2442 tlb_flush(env, 1);
2443 }
2444 tlb->RPN = RPN;
2445 break;
2446 case 2:
2447 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
2448 tlb->prot = tlb->prot & PAGE_VALID;
2449 if (value & 0x1) {
2450 tlb->prot |= PAGE_READ << 4;
2451 }
2452 if (value & 0x2) {
2453 tlb->prot |= PAGE_WRITE << 4;
2454 }
2455 if (value & 0x4) {
2456 tlb->prot |= PAGE_EXEC << 4;
2457 }
2458 if (value & 0x8) {
2459 tlb->prot |= PAGE_READ;
2460 }
2461 if (value & 0x10) {
2462 tlb->prot |= PAGE_WRITE;
2463 }
2464 if (value & 0x20) {
2465 tlb->prot |= PAGE_EXEC;
2466 }
2467 break;
2468 }
2469 }
2470
2471 target_ulong helper_440_tlbre(CPUPPCState *env, uint32_t word,
2472 target_ulong entry)
2473 {
2474 ppcemb_tlb_t *tlb;
2475 target_ulong ret;
2476 int size;
2477
2478 entry &= 0x3F;
2479 tlb = &env->tlb.tlbe[entry];
2480 switch (word) {
2481 default:
2482 /* Just here to please gcc */
2483 case 0:
2484 ret = tlb->EPN;
2485 size = booke_page_size_to_tlb(tlb->size);
2486 if (size < 0 || size > 0xF) {
2487 size = 1;
2488 }
2489 ret |= size << 4;
2490 if (tlb->attr & 0x1) {
2491 ret |= 0x100;
2492 }
2493 if (tlb->prot & PAGE_VALID) {
2494 ret |= 0x200;
2495 }
2496 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
2497 env->spr[SPR_440_MMUCR] |= tlb->PID;
2498 break;
2499 case 1:
2500 ret = tlb->RPN;
2501 break;
2502 case 2:
2503 ret = tlb->attr & ~0x1;
2504 if (tlb->prot & (PAGE_READ << 4)) {
2505 ret |= 0x1;
2506 }
2507 if (tlb->prot & (PAGE_WRITE << 4)) {
2508 ret |= 0x2;
2509 }
2510 if (tlb->prot & (PAGE_EXEC << 4)) {
2511 ret |= 0x4;
2512 }
2513 if (tlb->prot & PAGE_READ) {
2514 ret |= 0x8;
2515 }
2516 if (tlb->prot & PAGE_WRITE) {
2517 ret |= 0x10;
2518 }
2519 if (tlb->prot & PAGE_EXEC) {
2520 ret |= 0x20;
2521 }
2522 break;
2523 }
2524 return ret;
2525 }
2526
2527 target_ulong helper_440_tlbsx(CPUPPCState *env, target_ulong address)
2528 {
2529 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
2530 }
2531
2532 /* PowerPC BookE 2.06 TLB management */
2533
2534 static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
2535 {
2536 uint32_t tlbncfg = 0;
2537 int esel = (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >> MAS0_ESEL_SHIFT;
2538 int ea = (env->spr[SPR_BOOKE_MAS2] & MAS2_EPN_MASK);
2539 int tlb;
2540
2541 tlb = (env->spr[SPR_BOOKE_MAS0] & MAS0_TLBSEL_MASK) >> MAS0_TLBSEL_SHIFT;
2542 tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlb];
2543
2544 if ((tlbncfg & TLBnCFG_HES) && (env->spr[SPR_BOOKE_MAS0] & MAS0_HES)) {
2545 cpu_abort(env, "we don't support HES yet\n");
2546 }
2547
2548 return booke206_get_tlbm(env, tlb, ea, esel);
2549 }
2550
2551 void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
2552 {
2553 env->spr[pidn] = pid;
2554 /* changing PIDs mean we're in a different address space now */
2555 tlb_flush(env, 1);
2556 }
2557
2558 void helper_booke206_tlbwe(CPUPPCState *env)
2559 {
2560 uint32_t tlbncfg, tlbn;
2561 ppcmas_tlb_t *tlb;
2562 uint32_t size_tlb, size_ps;
2563 target_ulong mask;
2564
2565
2566 switch (env->spr[SPR_BOOKE_MAS0] & MAS0_WQ_MASK) {
2567 case MAS0_WQ_ALWAYS:
2568 /* good to go, write that entry */
2569 break;
2570 case MAS0_WQ_COND:
2571 /* XXX check if reserved */
2572 if (0) {
2573 return;
2574 }
2575 break;
2576 case MAS0_WQ_CLR_RSRV:
2577 /* XXX clear entry */
2578 return;
2579 default:
2580 /* no idea what to do */
2581 return;
2582 }
2583
2584 if (((env->spr[SPR_BOOKE_MAS0] & MAS0_ATSEL) == MAS0_ATSEL_LRAT) &&
2585 !msr_gs) {
2586 /* XXX we don't support direct LRAT setting yet */
2587 fprintf(stderr, "cpu: don't support LRAT setting yet\n");
2588 return;
2589 }
2590
2591 tlbn = (env->spr[SPR_BOOKE_MAS0] & MAS0_TLBSEL_MASK) >> MAS0_TLBSEL_SHIFT;
2592 tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2593
2594 tlb = booke206_cur_tlb(env);
2595
2596 if (!tlb) {
2597 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
2598 POWERPC_EXCP_INVAL |
2599 POWERPC_EXCP_INVAL_INVAL);
2600 }
2601
2602 /* check that we support the targeted size */
2603 size_tlb = (env->spr[SPR_BOOKE_MAS1] & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2604 size_ps = booke206_tlbnps(env, tlbn);
2605 if ((env->spr[SPR_BOOKE_MAS1] & MAS1_VALID) && (tlbncfg & TLBnCFG_AVAIL) &&
2606 !(size_ps & (1 << size_tlb))) {
2607 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
2608 POWERPC_EXCP_INVAL |
2609 POWERPC_EXCP_INVAL_INVAL);
2610 }
2611
2612 if (msr_gs) {
2613 cpu_abort(env, "missing HV implementation\n");
2614 }
2615 tlb->mas7_3 = ((uint64_t)env->spr[SPR_BOOKE_MAS7] << 32) |
2616 env->spr[SPR_BOOKE_MAS3];
2617 tlb->mas1 = env->spr[SPR_BOOKE_MAS1];
2618
2619 /* MAV 1.0 only */
2620 if (!(tlbncfg & TLBnCFG_AVAIL)) {
2621 /* force !AVAIL TLB entries to correct page size */
2622 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2623 /* XXX can be configured in MMUCSR0 */
2624 tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12;
2625 }
2626
2627 /* Make a mask from TLB size to discard invalid bits in EPN field */
2628 mask = ~(booke206_tlb_to_page_size(env, tlb) - 1);
2629 /* Add a mask for page attributes */
2630 mask |= MAS2_ACM | MAS2_VLE | MAS2_W | MAS2_I | MAS2_M | MAS2_G | MAS2_E;
2631
2632 if (!msr_cm) {
2633 /* Executing a tlbwe instruction in 32-bit mode will set
2634 * bits 0:31 of the TLB EPN field to zero.
2635 */
2636 mask &= 0xffffffff;
2637 }
2638
2639 tlb->mas2 = env->spr[SPR_BOOKE_MAS2] & mask;
2640
2641 if (!(tlbncfg & TLBnCFG_IPROT)) {
2642 /* no IPROT supported by TLB */
2643 tlb->mas1 &= ~MAS1_IPROT;
2644 }
2645
2646 if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
2647 tlb_flush_page(env, tlb->mas2 & MAS2_EPN_MASK);
2648 } else {
2649 tlb_flush(env, 1);
2650 }
2651 }
2652
2653 static inline void booke206_tlb_to_mas(CPUPPCState *env, ppcmas_tlb_t *tlb)
2654 {
2655 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2656 int way = booke206_tlbm_to_way(env, tlb);
2657
2658 env->spr[SPR_BOOKE_MAS0] = tlbn << MAS0_TLBSEL_SHIFT;
2659 env->spr[SPR_BOOKE_MAS0] |= way << MAS0_ESEL_SHIFT;
2660 env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
2661
2662 env->spr[SPR_BOOKE_MAS1] = tlb->mas1;
2663 env->spr[SPR_BOOKE_MAS2] = tlb->mas2;
2664 env->spr[SPR_BOOKE_MAS3] = tlb->mas7_3;
2665 env->spr[SPR_BOOKE_MAS7] = tlb->mas7_3 >> 32;
2666 }
2667
2668 void helper_booke206_tlbre(CPUPPCState *env)
2669 {
2670 ppcmas_tlb_t *tlb = NULL;
2671
2672 tlb = booke206_cur_tlb(env);
2673 if (!tlb) {
2674 env->spr[SPR_BOOKE_MAS1] = 0;
2675 } else {
2676 booke206_tlb_to_mas(env, tlb);
2677 }
2678 }
2679
2680 void helper_booke206_tlbsx(CPUPPCState *env, target_ulong address)
2681 {
2682 ppcmas_tlb_t *tlb = NULL;
2683 int i, j;
2684 hwaddr raddr;
2685 uint32_t spid, sas;
2686
2687 spid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID_MASK) >> MAS6_SPID_SHIFT;
2688 sas = env->spr[SPR_BOOKE_MAS6] & MAS6_SAS;
2689
2690 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2691 int ways = booke206_tlb_ways(env, i);
2692
2693 for (j = 0; j < ways; j++) {
2694 tlb = booke206_get_tlbm(env, i, address, j);
2695
2696 if (!tlb) {
2697 continue;
2698 }
2699
2700 if (ppcmas_tlb_check(env, tlb, &raddr, address, spid)) {
2701 continue;
2702 }
2703
2704 if (sas != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
2705 continue;
2706 }
2707
2708 booke206_tlb_to_mas(env, tlb);
2709 return;
2710 }
2711 }
2712
2713 /* no entry found, fill with defaults */
2714 env->spr[SPR_BOOKE_MAS0] = env->spr[SPR_BOOKE_MAS4] & MAS4_TLBSELD_MASK;
2715 env->spr[SPR_BOOKE_MAS1] = env->spr[SPR_BOOKE_MAS4] & MAS4_TSIZED_MASK;
2716 env->spr[SPR_BOOKE_MAS2] = env->spr[SPR_BOOKE_MAS4] & MAS4_WIMGED_MASK;
2717 env->spr[SPR_BOOKE_MAS3] = 0;
2718 env->spr[SPR_BOOKE_MAS7] = 0;
2719
2720 if (env->spr[SPR_BOOKE_MAS6] & MAS6_SAS) {
2721 env->spr[SPR_BOOKE_MAS1] |= MAS1_TS;
2722 }
2723
2724 env->spr[SPR_BOOKE_MAS1] |= (env->spr[SPR_BOOKE_MAS6] >> 16)
2725 << MAS1_TID_SHIFT;
2726
2727 /* next victim logic */
2728 env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_ESEL_SHIFT;
2729 env->last_way++;
2730 env->last_way &= booke206_tlb_ways(env, 0) - 1;
2731 env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
2732 }
2733
2734 static inline void booke206_invalidate_ea_tlb(CPUPPCState *env, int tlbn,
2735 uint32_t ea)
2736 {
2737 int i;
2738 int ways = booke206_tlb_ways(env, tlbn);
2739 target_ulong mask;
2740
2741 for (i = 0; i < ways; i++) {
2742 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, tlbn, ea, i);
2743 if (!tlb) {
2744 continue;
2745 }
2746 mask = ~(booke206_tlb_to_page_size(env, tlb) - 1);
2747 if (((tlb->mas2 & MAS2_EPN_MASK) == (ea & mask)) &&
2748 !(tlb->mas1 & MAS1_IPROT)) {
2749 tlb->mas1 &= ~MAS1_VALID;
2750 }
2751 }
2752 }
2753
2754 void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address)
2755 {
2756 if (address & 0x4) {
2757 /* flush all entries */
2758 if (address & 0x8) {
2759 /* flush all of TLB1 */
2760 booke206_flush_tlb(env, BOOKE206_FLUSH_TLB1, 1);
2761 } else {
2762 /* flush all of TLB0 */
2763 booke206_flush_tlb(env, BOOKE206_FLUSH_TLB0, 0);
2764 }
2765 return;
2766 }
2767
2768 if (address & 0x8) {
2769 /* flush TLB1 entries */
2770 booke206_invalidate_ea_tlb(env, 1, address);
2771 tlb_flush(env, 1);
2772 } else {
2773 /* flush TLB0 entries */
2774 booke206_invalidate_ea_tlb(env, 0, address);
2775 tlb_flush_page(env, address & MAS2_EPN_MASK);
2776 }
2777 }
2778
2779 void helper_booke206_tlbilx0(CPUPPCState *env, target_ulong address)
2780 {
2781 /* XXX missing LPID handling */
2782 booke206_flush_tlb(env, -1, 1);
2783 }
2784
2785 void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
2786 {
2787 int i, j;
2788 int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
2789 ppcmas_tlb_t *tlb = env->tlb.tlbm;
2790 int tlb_size;
2791
2792 /* XXX missing LPID handling */
2793 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2794 tlb_size = booke206_tlb_size(env, i);
2795 for (j = 0; j < tlb_size; j++) {
2796 if (!(tlb[j].mas1 & MAS1_IPROT) &&
2797 ((tlb[j].mas1 & MAS1_TID_MASK) == tid)) {
2798 tlb[j].mas1 &= ~MAS1_VALID;
2799 }
2800 }
2801 tlb += booke206_tlb_size(env, i);
2802 }
2803 tlb_flush(env, 1);
2804 }
2805
2806 void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
2807 {
2808 int i, j;
2809 ppcmas_tlb_t *tlb;
2810 int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
2811 int pid = tid >> MAS6_SPID_SHIFT;
2812 int sgs = env->spr[SPR_BOOKE_MAS5] & MAS5_SGS;
2813 int ind = (env->spr[SPR_BOOKE_MAS6] & MAS6_SIND) ? MAS1_IND : 0;
2814 /* XXX check for unsupported isize and raise an invalid opcode then */
2815 int size = env->spr[SPR_BOOKE_MAS6] & MAS6_ISIZE_MASK;
2816 /* XXX implement MAV2 handling */
2817 bool mav2 = false;
2818
2819 /* XXX missing LPID handling */
2820 /* flush by pid and ea */
2821 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2822 int ways = booke206_tlb_ways(env, i);
2823
2824 for (j = 0; j < ways; j++) {
2825 tlb = booke206_get_tlbm(env, i, address, j);
2826 if (!tlb) {
2827 continue;
2828 }
2829 if ((ppcmas_tlb_check(env, tlb, NULL, address, pid) != 0) ||
2830 (tlb->mas1 & MAS1_IPROT) ||
2831 ((tlb->mas1 & MAS1_IND) != ind) ||
2832 ((tlb->mas8 & MAS8_TGS) != sgs)) {
2833 continue;
2834 }
2835 if (mav2 && ((tlb->mas1 & MAS1_TSIZE_MASK) != size)) {
2836 /* XXX only check when MMUCFG[TWC] || TLBnCFG[HES] */
2837 continue;
2838 }
2839 /* XXX e500mc doesn't match SAS, but other cores might */
2840 tlb->mas1 &= ~MAS1_VALID;
2841 }
2842 }
2843 tlb_flush(env, 1);
2844 }
2845
2846 void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type)
2847 {
2848 int flags = 0;
2849
2850 if (type & 2) {
2851 flags |= BOOKE206_FLUSH_TLB1;
2852 }
2853
2854 if (type & 4) {
2855 flags |= BOOKE206_FLUSH_TLB0;
2856 }
2857
2858 booke206_flush_tlb(env, flags, 1);
2859 }
2860
2861
2862 /*****************************************************************************/
2863
2864 #define MMUSUFFIX _mmu
2865
2866 #define SHIFT 0
2867 #include "exec/softmmu_template.h"
2868
2869 #define SHIFT 1
2870 #include "exec/softmmu_template.h"
2871
2872 #define SHIFT 2
2873 #include "exec/softmmu_template.h"
2874
2875 #define SHIFT 3
2876 #include "exec/softmmu_template.h"
2877
2878 /* try to fill the TLB and return an exception if error. If retaddr is
2879 NULL, it means that the function was called in C code (i.e. not
2880 from generated code or from helper.c) */
2881 /* XXX: fix it to restore all registers */
2882 void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx,
2883 uintptr_t retaddr)
2884 {
2885 CPUState *cpu = ENV_GET_CPU(env);
2886 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2887 int ret;
2888
2889 if (pcc->handle_mmu_fault) {
2890 ret = pcc->handle_mmu_fault(env, addr, is_write, mmu_idx);
2891 } else {
2892 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx);
2893 }
2894 if (unlikely(ret != 0)) {
2895 if (likely(retaddr)) {
2896 /* now we have a real cpu fault */
2897 cpu_restore_state(env, retaddr);
2898 }
2899 helper_raise_exception_err(env, env->exception_index, env->error_code);
2900 }
2901 }
Qemu copy for testing