]>
git.proxmox.com Git - qemu.git/blob - target-ppc/op_helper.c
2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include "op_helper.h"
24 #define MEMSUFFIX _raw
25 #include "op_helper.h"
26 #include "op_helper_mem.h"
27 #if !defined(CONFIG_USER_ONLY)
28 #define MEMSUFFIX _user
29 #include "op_helper.h"
30 #include "op_helper_mem.h"
31 #define MEMSUFFIX _kernel
32 #include "op_helper.h"
33 #include "op_helper_mem.h"
37 //#define DEBUG_EXCEPTIONS
38 //#define DEBUG_SOFTWARE_TLB
39 //#define FLUSH_ALL_TLBS
41 /*****************************************************************************/
42 /* Exceptions processing helpers */
44 void do_raise_exception_err (uint32_t exception
, int error_code
)
47 printf("Raise exception %3x code : %d\n", exception
, error_code
);
51 if (error_code
== EXCP_FP
&& msr_fe0
== 0 && msr_fe1
== 0)
57 env
->exception_index
= exception
;
58 env
->error_code
= error_code
;
62 void do_raise_exception (uint32_t exception
)
64 do_raise_exception_err(exception
, 0);
67 void cpu_dump_EA (target_ulong EA
);
68 void do_print_mem_EA (target_ulong EA
)
73 /*****************************************************************************/
74 /* Registers load and stores */
75 void do_load_cr (void)
77 T0
= (env
->crf
[0] << 28) |
87 void do_store_cr (uint32_t mask
)
91 for (i
= 0, sh
= 7; i
< 8; i
++, sh
--) {
93 env
->crf
[i
] = (T0
>> (sh
* 4)) & 0xFUL
;
97 void do_load_xer (void)
99 T0
= (xer_so
<< XER_SO
) |
103 (xer_cmp
<< XER_CMP
);
106 void do_store_xer (void)
108 xer_so
= (T0
>> XER_SO
) & 0x01;
109 xer_ov
= (T0
>> XER_OV
) & 0x01;
110 xer_ca
= (T0
>> XER_CA
) & 0x01;
111 xer_cmp
= (T0
>> XER_CMP
) & 0xFF;
112 xer_bc
= (T0
>> XER_BC
) & 0x7F;
115 void do_load_fpscr (void)
117 /* The 32 MSB of the target fpr are undefined.
128 #if defined(WORDS_BIGENDIAN)
137 for (i
= 0; i
< 8; i
++)
138 u
.s
.u
[WORD1
] |= env
->fpscr
[i
] << (4 * i
);
142 void do_store_fpscr (uint32_t mask
)
145 * We use only the 32 LSB of the incoming fpr
157 env
->fpscr
[0] = (env
->fpscr
[0] & 0x9) | ((u
.s
.u
[WORD1
] >> 28) & ~0x9);
158 for (i
= 1; i
< 7; i
++) {
159 if (mask
& (1 << (7 - i
)))
160 env
->fpscr
[i
] = (u
.s
.u
[WORD1
] >> (4 * (7 - i
))) & 0xF;
162 /* TODO: update FEX & VX */
163 /* Set rounding mode */
164 switch (env
->fpscr
[0] & 0x3) {
166 /* Best approximation (round to nearest) */
167 rnd_type
= float_round_nearest_even
;
170 /* Smaller magnitude (round toward zero) */
171 rnd_type
= float_round_to_zero
;
174 /* Round toward +infinite */
175 rnd_type
= float_round_up
;
179 /* Round toward -infinite */
180 rnd_type
= float_round_down
;
183 set_float_rounding_mode(rnd_type
, &env
->fp_status
);
186 target_ulong
ppc_load_dump_spr (int sprn
)
189 fprintf(logfile
, "Read SPR %d %03x => " ADDRX
"\n",
190 sprn
, sprn
, env
->spr
[sprn
]);
193 return env
->spr
[sprn
];
196 void ppc_store_dump_spr (int sprn
, target_ulong val
)
199 fprintf(logfile
, "Write SPR %d %03x => " ADDRX
" <= " ADDRX
"\n",
200 sprn
, sprn
, env
->spr
[sprn
], val
);
202 env
->spr
[sprn
] = val
;
205 /*****************************************************************************/
206 /* Fixed point operations helpers */
207 #if defined(TARGET_PPC64)
208 static void add128 (uint64_t *plow
, uint64_t *phigh
, uint64_t a
, uint64_t b
)
217 static void neg128 (uint64_t *plow
, uint64_t *phigh
)
221 add128(plow
, phigh
, 1, 0);
224 static void mul64 (uint64_t *plow
, uint64_t *phigh
, uint64_t a
, uint64_t b
)
226 uint32_t a0
, a1
, b0
, b1
;
235 v
= (uint64_t)a0
* (uint64_t)b0
;
239 v
= (uint64_t)a0
* (uint64_t)b1
;
240 add128(plow
, phigh
, v
<< 32, v
>> 32);
242 v
= (uint64_t)a1
* (uint64_t)b0
;
243 add128(plow
, phigh
, v
<< 32, v
>> 32);
245 v
= (uint64_t)a1
* (uint64_t)b1
;
247 #if defined(DEBUG_MULDIV)
248 printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
249 a
, b
, *phigh
, *plow
);
253 void do_mul64 (uint64_t *plow
, uint64_t *phigh
)
255 mul64(plow
, phigh
, T0
, T1
);
258 static void imul64 (uint64_t *plow
, uint64_t *phigh
, int64_t a
, int64_t b
)
268 mul64(plow
, phigh
, a
, b
);
274 void do_imul64 (uint64_t *plow
, uint64_t *phigh
)
276 imul64(plow
, phigh
, T0
, T1
);
284 if (likely(!((uint32_t)T0
< (uint32_t)T2
||
285 (xer_ca
== 1 && (uint32_t)T0
== (uint32_t)T2
)))) {
292 #if defined(TARGET_PPC64)
293 void do_adde_64 (void)
297 if (likely(!((uint64_t)T0
< (uint64_t)T2
||
298 (xer_ca
== 1 && (uint64_t)T0
== (uint64_t)T2
)))) {
306 void do_addmeo (void)
310 if (likely(!((uint32_t)T1
&
311 ((uint32_t)T1
^ (uint32_t)T0
) & (1UL << 31)))) {
321 #if defined(TARGET_PPC64)
322 void do_addmeo_64 (void)
326 if (likely(!((uint64_t)T1
&
327 ((uint64_t)T1
^ (uint64_t)T0
) & (1ULL << 63)))) {
340 if (likely(!(((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== -1) ||
341 (int32_t)T1
== 0))) {
343 T0
= (int32_t)T0
/ (int32_t)T1
;
347 T0
= (-1) * ((uint32_t)T0
>> 31);
351 #if defined(TARGET_PPC64)
354 if (likely(!(((int64_t)T0
== INT64_MIN
&& (int64_t)T1
== -1ULL) ||
355 (int64_t)T1
== 0))) {
357 T0
= (int64_t)T0
/ (int64_t)T1
;
361 T0
= (-1ULL) * ((uint64_t)T0
>> 63);
366 void do_divwuo (void)
368 if (likely((uint32_t)T1
!= 0)) {
370 T0
= (uint32_t)T0
/ (uint32_t)T1
;
378 #if defined(TARGET_PPC64)
379 void do_divduo (void)
381 if (likely((uint64_t)T1
!= 0)) {
383 T0
= (uint64_t)T0
/ (uint64_t)T1
;
392 void do_mullwo (void)
394 int64_t res
= (int64_t)T0
* (int64_t)T1
;
396 if (likely((int32_t)res
== res
)) {
405 #if defined(TARGET_PPC64)
406 void do_mulldo (void)
412 if (likely(th
== 0)) {
424 if (likely((int32_t)T0
!= INT32_MIN
)) {
433 #if defined(TARGET_PPC64)
434 void do_nego_64 (void)
436 if (likely((int64_t)T0
!= INT64_MIN
)) {
448 T0
= T1
+ ~T0
+ xer_ca
;
449 if (likely((uint32_t)T0
>= (uint32_t)T1
&&
450 (xer_ca
== 0 || (uint32_t)T0
!= (uint32_t)T1
))) {
457 #if defined(TARGET_PPC64)
458 void do_subfe_64 (void)
460 T0
= T1
+ ~T0
+ xer_ca
;
461 if (likely((uint64_t)T0
>= (uint64_t)T1
&&
462 (xer_ca
== 0 || (uint64_t)T0
!= (uint64_t)T1
))) {
470 void do_subfmeo (void)
473 T0
= ~T0
+ xer_ca
- 1;
474 if (likely(!((uint32_t)~T1
& ((uint32_t)~T1
^ (uint32_t)T0
) &
481 if (likely((uint32_t)T1
!= UINT32_MAX
))
485 #if defined(TARGET_PPC64)
486 void do_subfmeo_64 (void)
489 T0
= ~T0
+ xer_ca
- 1;
490 if (likely(!((uint64_t)~T1
& ((uint64_t)~T1
^ (uint64_t)T0
) &
497 if (likely((uint64_t)T1
!= UINT64_MAX
))
502 void do_subfzeo (void)
506 if (likely(!(((uint32_t)~T1
^ UINT32_MAX
) &
507 ((uint32_t)(~T1
) ^ (uint32_t)T0
) & (1UL << 31)))) {
513 if (likely((uint32_t)T0
>= (uint32_t)~T1
)) {
520 #if defined(TARGET_PPC64)
521 void do_subfzeo_64 (void)
525 if (likely(!(((uint64_t)~T1
^ UINT64_MAX
) &
526 ((uint64_t)(~T1
) ^ (uint64_t)T0
) & (1ULL << 63)))) {
532 if (likely((uint64_t)T0
>= (uint64_t)~T1
)) {
540 /* shift right arithmetic helper */
545 if (likely(!(T1
& 0x20UL
))) {
546 if (likely((uint32_t)T1
!= 0)) {
547 ret
= (int32_t)T0
>> (T1
& 0x1fUL
);
548 if (likely(ret
>= 0 || ((int32_t)T0
& ((1 << T1
) - 1)) == 0)) {
558 ret
= (-1) * ((uint32_t)T0
>> 31);
559 if (likely(ret
>= 0 || ((uint32_t)T0
& ~0x80000000UL
) == 0)) {
568 #if defined(TARGET_PPC64)
573 if (likely(!(T1
& 0x40UL
))) {
574 if (likely((uint64_t)T1
!= 0)) {
575 ret
= (int64_t)T0
>> (T1
& 0x3FUL
);
576 if (likely(ret
>= 0 || ((int64_t)T0
& ((1 << T1
) - 1)) == 0)) {
586 ret
= (-1) * ((uint64_t)T0
>> 63);
587 if (likely(ret
>= 0 || ((uint64_t)T0
& ~0x8000000000000000ULL
) == 0)) {
597 static inline int popcnt (uint32_t val
)
601 for (i
= 0; val
!= 0;)
602 val
= val
^ (val
- 1);
607 void do_popcntb (void)
613 for (i
= 0; i
< 32; i
+= 8)
614 ret
|= popcnt((T0
>> i
) & 0xFF) << i
;
618 #if defined(TARGET_PPC64)
619 void do_popcntb_64 (void)
625 for (i
= 0; i
< 64; i
+= 8)
626 ret
|= popcnt((T0
>> i
) & 0xFF) << i
;
631 /*****************************************************************************/
632 /* Floating point operations helpers */
640 p
.i
= float64_to_int32(FT0
, &env
->fp_status
);
641 #if USE_PRECISE_EMULATION
642 /* XXX: higher bits are not supposed to be significant.
643 * to make tests easier, return the same as a real PowerPC 750 (aka G3)
645 p
.i
|= 0xFFF80000ULL
<< 32;
650 void do_fctiwz (void)
657 p
.i
= float64_to_int32_round_to_zero(FT0
, &env
->fp_status
);
658 #if USE_PRECISE_EMULATION
659 /* XXX: higher bits are not supposed to be significant.
660 * to make tests easier, return the same as a real PowerPC 750 (aka G3)
662 p
.i
|= 0xFFF80000ULL
<< 32;
667 #if defined(TARGET_PPC64)
676 FT0
= int64_to_float64(p
.i
, &env
->fp_status
);
686 p
.i
= float64_to_int64(FT0
, &env
->fp_status
);
690 void do_fctidz (void)
697 p
.i
= float64_to_int64_round_to_zero(FT0
, &env
->fp_status
);
703 #if USE_PRECISE_EMULATION
707 float128 ft0_128
, ft1_128
;
709 ft0_128
= float64_to_float128(FT0
, &env
->fp_status
);
710 ft1_128
= float64_to_float128(FT1
, &env
->fp_status
);
711 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
712 ft1_128
= float64_to_float128(FT2
, &env
->fp_status
);
713 ft0_128
= float128_add(ft0_128
, ft1_128
, &env
->fp_status
);
714 FT0
= float128_to_float64(ft0_128
, &env
->fp_status
);
716 /* This is OK on x86 hosts */
717 FT0
= (FT0
* FT1
) + FT2
;
724 float128 ft0_128
, ft1_128
;
726 ft0_128
= float64_to_float128(FT0
, &env
->fp_status
);
727 ft1_128
= float64_to_float128(FT1
, &env
->fp_status
);
728 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
729 ft1_128
= float64_to_float128(FT2
, &env
->fp_status
);
730 ft0_128
= float128_sub(ft0_128
, ft1_128
, &env
->fp_status
);
731 FT0
= float128_to_float64(ft0_128
, &env
->fp_status
);
733 /* This is OK on x86 hosts */
734 FT0
= (FT0
* FT1
) - FT2
;
737 #endif /* USE_PRECISE_EMULATION */
739 void do_fnmadd (void)
741 #if USE_PRECISE_EMULATION
743 float128 ft0_128
, ft1_128
;
745 ft0_128
= float64_to_float128(FT0
, &env
->fp_status
);
746 ft1_128
= float64_to_float128(FT1
, &env
->fp_status
);
747 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
748 ft1_128
= float64_to_float128(FT2
, &env
->fp_status
);
749 ft0_128
= float128_add(ft0_128
, ft1_128
, &env
->fp_status
);
750 FT0
= float128_to_float64(ft0_128
, &env
->fp_status
);
752 /* This is OK on x86 hosts */
753 FT0
= (FT0
* FT1
) + FT2
;
756 FT0
= float64_mul(FT0
, FT1
, &env
->fp_status
);
757 FT0
= float64_add(FT0
, FT2
, &env
->fp_status
);
759 if (likely(!isnan(FT0
)))
760 FT0
= float64_chs(FT0
);
763 void do_fnmsub (void)
765 #if USE_PRECISE_EMULATION
767 float128 ft0_128
, ft1_128
;
769 ft0_128
= float64_to_float128(FT0
, &env
->fp_status
);
770 ft1_128
= float64_to_float128(FT1
, &env
->fp_status
);
771 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
772 ft1_128
= float64_to_float128(FT2
, &env
->fp_status
);
773 ft0_128
= float128_sub(ft0_128
, ft1_128
, &env
->fp_status
);
774 FT0
= float128_to_float64(ft0_128
, &env
->fp_status
);
776 /* This is OK on x86 hosts */
777 FT0
= (FT0
* FT1
) - FT2
;
780 FT0
= float64_mul(FT0
, FT1
, &env
->fp_status
);
781 FT0
= float64_sub(FT0
, FT2
, &env
->fp_status
);
783 if (likely(!isnan(FT0
)))
784 FT0
= float64_chs(FT0
);
789 FT0
= float64_sqrt(FT0
, &env
->fp_status
);
799 if (likely(isnormal(FT0
))) {
800 #if USE_PRECISE_EMULATION
801 FT0
= float64_div(1.0, FT0
, &env
->fp_status
);
802 FT0
= float64_to_float32(FT0
, &env
->fp_status
);
804 FT0
= float32_div(1.0, FT0
, &env
->fp_status
);
808 if (p
.i
== 0x8000000000000000ULL
) {
809 p
.i
= 0xFFF0000000000000ULL
;
810 } else if (p
.i
== 0x0000000000000000ULL
) {
811 p
.i
= 0x7FF0000000000000ULL
;
812 } else if (isnan(FT0
)) {
813 p
.i
= 0x7FF8000000000000ULL
;
814 } else if (FT0
< 0.0) {
815 p
.i
= 0x8000000000000000ULL
;
817 p
.i
= 0x0000000000000000ULL
;
823 void do_frsqrte (void)
830 if (likely(isnormal(FT0
) && FT0
> 0.0)) {
831 FT0
= float64_sqrt(FT0
, &env
->fp_status
);
832 FT0
= float32_div(1.0, FT0
, &env
->fp_status
);
835 if (p
.i
== 0x8000000000000000ULL
) {
836 p
.i
= 0xFFF0000000000000ULL
;
837 } else if (p
.i
== 0x0000000000000000ULL
) {
838 p
.i
= 0x7FF0000000000000ULL
;
839 } else if (isnan(FT0
)) {
840 if (!(p
.i
& 0x0008000000000000ULL
))
841 p
.i
|= 0x000FFFFFFFFFFFFFULL
;
842 } else if (FT0
< 0) {
843 p
.i
= 0x7FF8000000000000ULL
;
845 p
.i
= 0x0000000000000000ULL
;
861 if (likely(!isnan(FT0
) && !isnan(FT1
))) {
862 if (float64_lt(FT0
, FT1
, &env
->fp_status
)) {
864 } else if (!float64_le(FT0
, FT1
, &env
->fp_status
)) {
871 env
->fpscr
[4] |= 0x1;
872 env
->fpscr
[6] |= 0x1;
879 env
->fpscr
[4] &= ~0x1;
880 if (likely(!isnan(FT0
) && !isnan(FT1
))) {
881 if (float64_lt(FT0
, FT1
, &env
->fp_status
)) {
883 } else if (!float64_le(FT0
, FT1
, &env
->fp_status
)) {
890 env
->fpscr
[4] |= 0x1;
891 if (!float64_is_signaling_nan(FT0
) || !float64_is_signaling_nan(FT1
)) {
893 env
->fpscr
[6] |= 0x1;
894 if (!(env
->fpscr
[1] & 0x8))
895 env
->fpscr
[4] |= 0x8;
897 env
->fpscr
[4] |= 0x8;
903 #if !defined (CONFIG_USER_ONLY)
904 void cpu_dump_rfi (target_ulong RA
, target_ulong msr
);
907 #if defined(TARGET_PPC64)
908 if (env
->spr
[SPR_SRR1
] & (1ULL << MSR_SF
)) {
909 env
->nip
= (uint64_t)(env
->spr
[SPR_SRR0
] & ~0x00000003);
910 do_store_msr(env
, (uint64_t)(env
->spr
[SPR_SRR1
] & ~0xFFFF0000UL
));
912 env
->nip
= (uint32_t)(env
->spr
[SPR_SRR0
] & ~0x00000003);
913 ppc_store_msr_32(env
, (uint32_t)(env
->spr
[SPR_SRR1
] & ~0xFFFF0000UL
));
916 env
->nip
= (uint32_t)(env
->spr
[SPR_SRR0
] & ~0x00000003);
917 do_store_msr(env
, (uint32_t)(env
->spr
[SPR_SRR1
] & ~0xFFFF0000UL
));
919 #if defined (DEBUG_OP)
920 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
922 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
925 #if defined(TARGET_PPC64)
928 if (env
->spr
[SPR_SRR1
] & (1ULL << MSR_SF
)) {
929 env
->nip
= (uint64_t)(env
->spr
[SPR_SRR0
] & ~0x00000003);
930 do_store_msr(env
, (uint64_t)(env
->spr
[SPR_SRR1
] & ~0xFFFF0000UL
));
932 env
->nip
= (uint32_t)(env
->spr
[SPR_SRR0
] & ~0x00000003);
933 do_store_msr(env
, (uint32_t)(env
->spr
[SPR_SRR1
] & ~0xFFFF0000UL
));
935 #if defined (DEBUG_OP)
936 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
938 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
943 void do_tw (int flags
)
945 if (!likely(!(((int32_t)T0
< (int32_t)T1
&& (flags
& 0x10)) ||
946 ((int32_t)T0
> (int32_t)T1
&& (flags
& 0x08)) ||
947 ((int32_t)T0
== (int32_t)T1
&& (flags
& 0x04)) ||
948 ((uint32_t)T0
< (uint32_t)T1
&& (flags
& 0x02)) ||
949 ((uint32_t)T0
> (uint32_t)T1
&& (flags
& 0x01))))) {
950 do_raise_exception_err(EXCP_PROGRAM
, EXCP_TRAP
);
954 #if defined(TARGET_PPC64)
955 void do_td (int flags
)
957 if (!likely(!(((int64_t)T0
< (int64_t)T1
&& (flags
& 0x10)) ||
958 ((int64_t)T0
> (int64_t)T1
&& (flags
& 0x08)) ||
959 ((int64_t)T0
== (int64_t)T1
&& (flags
& 0x04)) ||
960 ((uint64_t)T0
< (uint64_t)T1
&& (flags
& 0x02)) ||
961 ((uint64_t)T0
> (uint64_t)T1
&& (flags
& 0x01)))))
962 do_raise_exception_err(EXCP_PROGRAM
, EXCP_TRAP
);
966 /*****************************************************************************/
967 /* PowerPC 601 specific instructions (POWER bridge) */
968 void do_POWER_abso (void)
970 if ((uint32_t)T0
== INT32_MIN
) {
980 void do_POWER_clcs (void)
984 /* Instruction cache line size */
985 T0
= ICACHE_LINE_SIZE
;
988 /* Data cache line size */
989 T0
= DCACHE_LINE_SIZE
;
992 /* Minimum cache line size */
993 T0
= ICACHE_LINE_SIZE
< DCACHE_LINE_SIZE
?
994 ICACHE_LINE_SIZE
: DCACHE_LINE_SIZE
;
997 /* Maximum cache line size */
998 T0
= ICACHE_LINE_SIZE
> DCACHE_LINE_SIZE
?
999 ICACHE_LINE_SIZE
: DCACHE_LINE_SIZE
;
1007 void do_POWER_div (void)
1011 if (((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== -1) || (int32_t)T1
== 0) {
1012 T0
= (long)((-1) * (T0
>> 31));
1013 env
->spr
[SPR_MQ
] = 0;
1015 tmp
= ((uint64_t)T0
<< 32) | env
->spr
[SPR_MQ
];
1016 env
->spr
[SPR_MQ
] = tmp
% T1
;
1017 T0
= tmp
/ (int32_t)T1
;
1021 void do_POWER_divo (void)
1025 if (((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== -1) || (int32_t)T1
== 0) {
1026 T0
= (long)((-1) * (T0
>> 31));
1027 env
->spr
[SPR_MQ
] = 0;
1031 tmp
= ((uint64_t)T0
<< 32) | env
->spr
[SPR_MQ
];
1032 env
->spr
[SPR_MQ
] = tmp
% T1
;
1034 if (tmp
> (int64_t)INT32_MAX
|| tmp
< (int64_t)INT32_MIN
) {
1044 void do_POWER_divs (void)
1046 if (((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== -1) || (int32_t)T1
== 0) {
1047 T0
= (long)((-1) * (T0
>> 31));
1048 env
->spr
[SPR_MQ
] = 0;
1050 env
->spr
[SPR_MQ
] = T0
% T1
;
1051 T0
= (int32_t)T0
/ (int32_t)T1
;
1055 void do_POWER_divso (void)
1057 if (((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== -1) || (int32_t)T1
== 0) {
1058 T0
= (long)((-1) * (T0
>> 31));
1059 env
->spr
[SPR_MQ
] = 0;
1063 T0
= (int32_t)T0
/ (int32_t)T1
;
1064 env
->spr
[SPR_MQ
] = (int32_t)T0
% (int32_t)T1
;
1069 void do_POWER_dozo (void)
1071 if ((int32_t)T1
> (int32_t)T0
) {
1074 if (((uint32_t)(~T2
) ^ (uint32_t)T1
^ UINT32_MAX
) &
1075 ((uint32_t)(~T2
) ^ (uint32_t)T0
) & (1UL << 31)) {
1087 void do_POWER_maskg (void)
1091 if ((uint32_t)T0
== (uint32_t)(T1
+ 1)) {
1094 ret
= (((uint32_t)(-1)) >> ((uint32_t)T0
)) ^
1095 (((uint32_t)(-1) >> ((uint32_t)T1
)) >> 1);
1096 if ((uint32_t)T0
> (uint32_t)T1
)
1102 void do_POWER_mulo (void)
1106 tmp
= (uint64_t)T0
* (uint64_t)T1
;
1107 env
->spr
[SPR_MQ
] = tmp
>> 32;
1109 if (tmp
>> 32 != ((uint64_t)T0
>> 16) * ((uint64_t)T1
>> 16)) {
1117 #if !defined (CONFIG_USER_ONLY)
1118 void do_POWER_rac (void)
1123 /* We don't have to generate many instances of this instruction,
1124 * as rac is supervisor only.
1126 if (get_physical_address(env
, &ctx
, T0
, 0, ACCESS_INT
, 1) == 0)
1131 void do_POWER_rfsvc (void)
1133 env
->nip
= env
->lr
& ~0x00000003UL
;
1134 T0
= env
->ctr
& 0x0000FFFFUL
;
1135 do_store_msr(env
, T0
);
1136 #if defined (DEBUG_OP)
1137 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
1139 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1142 /* PowerPC 601 BAT management helper */
1143 void do_store_601_batu (int nr
)
1145 do_store_ibatu(env
, nr
, (uint32_t)T0
);
1146 env
->DBAT
[0][nr
] = env
->IBAT
[0][nr
];
1147 env
->DBAT
[1][nr
] = env
->IBAT
[1][nr
];
1151 /*****************************************************************************/
1152 /* 602 specific instructions */
1153 /* mfrom is the most crazy instruction ever seen, imho ! */
1154 /* Real implementation uses a ROM table. Do the same */
1155 #define USE_MFROM_ROM_TABLE
1156 void do_op_602_mfrom (void)
1158 if (likely(T0
< 602)) {
1159 #if defined(USE_MFROM_ROM_TABLE)
1160 #include "mfrom_table.c"
1161 T0
= mfrom_ROM_table
[T0
];
1164 /* Extremly decomposed:
1166 * T0 = 256 * log10(10 + 1.0) + 0.5
1169 d
= float64_div(d
, 256, &env
->fp_status
);
1171 d
= exp10(d
); // XXX: use float emulation function
1172 d
= float64_add(d
, 1.0, &env
->fp_status
);
1173 d
= log10(d
); // XXX: use float emulation function
1174 d
= float64_mul(d
, 256, &env
->fp_status
);
1175 d
= float64_add(d
, 0.5, &env
->fp_status
);
1176 T0
= float64_round_to_int(d
, &env
->fp_status
);
1183 /*****************************************************************************/
1184 /* Embedded PowerPC specific helpers */
1185 void do_405_check_ov (void)
1187 if (likely((((uint32_t)T1
^ (uint32_t)T2
) >> 31) ||
1188 !(((uint32_t)T0
^ (uint32_t)T2
) >> 31))) {
1196 void do_405_check_sat (void)
1198 if (!likely((((uint32_t)T1
^ (uint32_t)T2
) >> 31) ||
1199 !(((uint32_t)T0
^ (uint32_t)T2
) >> 31))) {
1200 /* Saturate result */
1209 #if !defined(CONFIG_USER_ONLY)
1210 void do_40x_rfci (void)
1212 env
->nip
= env
->spr
[SPR_40x_SRR2
];
1213 do_store_msr(env
, env
->spr
[SPR_40x_SRR3
] & ~0xFFFF0000);
1214 #if defined (DEBUG_OP)
1215 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
1217 env
->interrupt_request
= CPU_INTERRUPT_EXITTB
;
1222 #if defined(TARGET_PPC64)
1223 if (env
->spr
[SPR_BOOKE_CSRR1
] & (1 << MSR_CM
)) {
1224 env
->nip
= (uint64_t)env
->spr
[SPR_BOOKE_CSRR0
];
1228 env
->nip
= (uint32_t)env
->spr
[SPR_BOOKE_CSRR0
];
1230 do_store_msr(env
, (uint32_t)env
->spr
[SPR_BOOKE_CSRR1
] & ~0x3FFF0000);
1231 #if defined (DEBUG_OP)
1232 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
1234 env
->interrupt_request
= CPU_INTERRUPT_EXITTB
;
1239 #if defined(TARGET_PPC64)
1240 if (env
->spr
[SPR_BOOKE_DSRR1
] & (1 << MSR_CM
)) {
1241 env
->nip
= (uint64_t)env
->spr
[SPR_BOOKE_DSRR0
];
1245 env
->nip
= (uint32_t)env
->spr
[SPR_BOOKE_DSRR0
];
1247 do_store_msr(env
, (uint32_t)env
->spr
[SPR_BOOKE_DSRR1
] & ~0x3FFF0000);
1248 #if defined (DEBUG_OP)
1249 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
1251 env
->interrupt_request
= CPU_INTERRUPT_EXITTB
;
1254 void do_rfmci (void)
1256 #if defined(TARGET_PPC64)
1257 if (env
->spr
[SPR_BOOKE_MCSRR1
] & (1 << MSR_CM
)) {
1258 env
->nip
= (uint64_t)env
->spr
[SPR_BOOKE_MCSRR0
];
1262 env
->nip
= (uint32_t)env
->spr
[SPR_BOOKE_MCSRR0
];
1264 do_store_msr(env
, (uint32_t)env
->spr
[SPR_BOOKE_MCSRR1
] & ~0x3FFF0000);
1265 #if defined (DEBUG_OP)
1266 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
1268 env
->interrupt_request
= CPU_INTERRUPT_EXITTB
;
1271 void do_load_dcr (void)
1275 if (unlikely(env
->dcr_env
== NULL
)) {
1276 if (loglevel
!= 0) {
1277 fprintf(logfile
, "No DCR environment\n");
1279 do_raise_exception_err(EXCP_PROGRAM
, EXCP_INVAL
| EXCP_INVAL_INVAL
);
1280 } else if (unlikely(ppc_dcr_read(env
->dcr_env
, T0
, &val
) != 0)) {
1281 if (loglevel
!= 0) {
1282 fprintf(logfile
, "DCR read error %d %03x\n", (int)T0
, (int)T0
);
1284 do_raise_exception_err(EXCP_PROGRAM
, EXCP_INVAL
| EXCP_PRIV_REG
);
1290 void do_store_dcr (void)
1292 if (unlikely(env
->dcr_env
== NULL
)) {
1293 if (loglevel
!= 0) {
1294 fprintf(logfile
, "No DCR environment\n");
1296 do_raise_exception_err(EXCP_PROGRAM
, EXCP_INVAL
| EXCP_INVAL_INVAL
);
1297 } else if (unlikely(ppc_dcr_write(env
->dcr_env
, T0
, T1
) != 0)) {
1298 if (loglevel
!= 0) {
1299 fprintf(logfile
, "DCR write error %d %03x\n", (int)T0
, (int)T0
);
1301 do_raise_exception_err(EXCP_PROGRAM
, EXCP_INVAL
| EXCP_PRIV_REG
);
1305 void do_load_403_pb (int num
)
1310 void do_store_403_pb (int num
)
1312 if (likely(env
->pb
[num
] != T0
)) {
1314 /* Should be optimized */
1321 void do_440_dlmzb (void)
1327 for (mask
= 0xFF000000; mask
!= 0; mask
= mask
>> 8) {
1328 if ((T0
& mask
) == 0)
1332 for (mask
= 0xFF000000; mask
!= 0; mask
= mask
>> 8) {
1333 if ((T1
& mask
) == 0)
1341 #if defined(TARGET_PPCEMB)
1342 /* SPE extension helpers */
1343 /* Use a table to make this quicker */
1344 static uint8_t hbrev
[16] = {
1345 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1346 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1349 static inline uint8_t byte_reverse (uint8_t val
)
1351 return hbrev
[val
>> 4] | (hbrev
[val
& 0xF] << 4);
1354 static inline uint32_t word_reverse (uint32_t val
)
1356 return byte_reverse(val
>> 24) | (byte_reverse(val
>> 16) << 8) |
1357 (byte_reverse(val
>> 8) << 16) | (byte_reverse(val
) << 24);
1360 #define MASKBITS 16 // Random value - to be fixed
1361 void do_brinc (void)
1363 uint32_t a
, b
, d
, mask
;
1365 mask
= (uint32_t)(-1UL) >> MASKBITS
;
1368 d
= word_reverse(1 + word_reverse(a
| ~mask
));
1369 T0_64
= (T0_64
& ~mask
) | (d
& mask
);
1372 #define DO_SPE_OP2(name) \
1373 void do_ev##name (void) \
1375 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1376 (uint64_t)_do_e##name(T0_64, T1_64); \
1379 #define DO_SPE_OP1(name) \
1380 void do_ev##name (void) \
1382 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1383 (uint64_t)_do_e##name(T0_64); \
1386 /* Fixed-point vector arithmetic */
1387 static inline uint32_t _do_eabs (uint32_t val
)
1389 if (val
!= 0x80000000)
1395 static inline uint32_t _do_eaddw (uint32_t op1
, uint32_t op2
)
1400 static inline int _do_ecntlsw (uint32_t val
)
1402 if (val
& 0x80000000)
1403 return _do_cntlzw(~val
);
1405 return _do_cntlzw(val
);
1408 static inline int _do_ecntlzw (uint32_t val
)
1410 return _do_cntlzw(val
);
1413 static inline uint32_t _do_eneg (uint32_t val
)
1415 if (val
!= 0x80000000)
1421 static inline uint32_t _do_erlw (uint32_t op1
, uint32_t op2
)
1423 return rotl32(op1
, op2
);
1426 static inline uint32_t _do_erndw (uint32_t val
)
1428 return (val
+ 0x000080000000) & 0xFFFF0000;
1431 static inline uint32_t _do_eslw (uint32_t op1
, uint32_t op2
)
1433 /* No error here: 6 bits are used */
1434 return op1
<< (op2
& 0x3F);
1437 static inline int32_t _do_esrws (int32_t op1
, uint32_t op2
)
1439 /* No error here: 6 bits are used */
1440 return op1
>> (op2
& 0x3F);
1443 static inline uint32_t _do_esrwu (uint32_t op1
, uint32_t op2
)
1445 /* No error here: 6 bits are used */
1446 return op1
>> (op2
& 0x3F);
1449 static inline uint32_t _do_esubfw (uint32_t op1
, uint32_t op2
)
1477 /* evsel is a little bit more complicated... */
1478 static inline uint32_t _do_esel (uint32_t op1
, uint32_t op2
, int n
)
1486 void do_evsel (void)
1488 T0_64
= ((uint64_t)_do_esel(T0_64
>> 32, T1_64
>> 32, T0
>> 3) << 32) |
1489 (uint64_t)_do_esel(T0_64
, T1_64
, (T0
>> 2) & 1);
1492 /* Fixed-point vector comparisons */
1493 #define DO_SPE_CMP(name) \
1494 void do_ev##name (void) \
1496 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
1497 T1_64 >> 32) << 32, \
1498 _do_e##name(T0_64, T1_64)); \
1501 static inline uint32_t _do_evcmp_merge (int t0
, int t1
)
1503 return (t0
<< 3) | (t1
<< 2) | ((t0
| t1
) << 1) | (t0
& t1
);
1505 static inline int _do_ecmpeq (uint32_t op1
, uint32_t op2
)
1507 return op1
== op2
? 1 : 0;
1510 static inline int _do_ecmpgts (int32_t op1
, int32_t op2
)
1512 return op1
> op2
? 1 : 0;
1515 static inline int _do_ecmpgtu (uint32_t op1
, uint32_t op2
)
1517 return op1
> op2
? 1 : 0;
1520 static inline int _do_ecmplts (int32_t op1
, int32_t op2
)
1522 return op1
< op2
? 1 : 0;
1525 static inline int _do_ecmpltu (uint32_t op1
, uint32_t op2
)
1527 return op1
< op2
? 1 : 0;
1541 /* Single precision floating-point conversions from/to integer */
1542 static inline uint32_t _do_efscfsi (int32_t val
)
1549 u
.f
= int32_to_float32(val
, &env
->spe_status
);
1554 static inline uint32_t _do_efscfui (uint32_t val
)
1561 u
.f
= uint32_to_float32(val
, &env
->spe_status
);
1566 static inline int32_t _do_efsctsi (uint32_t val
)
1574 /* NaN are not treated the same way IEEE 754 does */
1575 if (unlikely(isnan(u
.f
)))
1578 return float32_to_int32(u
.f
, &env
->spe_status
);
1581 static inline uint32_t _do_efsctui (uint32_t val
)
1589 /* NaN are not treated the same way IEEE 754 does */
1590 if (unlikely(isnan(u
.f
)))
1593 return float32_to_uint32(u
.f
, &env
->spe_status
);
1596 static inline int32_t _do_efsctsiz (uint32_t val
)
1604 /* NaN are not treated the same way IEEE 754 does */
1605 if (unlikely(isnan(u
.f
)))
1608 return float32_to_int32_round_to_zero(u
.f
, &env
->spe_status
);
1611 static inline uint32_t _do_efsctuiz (uint32_t val
)
1619 /* NaN are not treated the same way IEEE 754 does */
1620 if (unlikely(isnan(u
.f
)))
1623 return float32_to_uint32_round_to_zero(u
.f
, &env
->spe_status
);
1626 void do_efscfsi (void)
1628 T0_64
= _do_efscfsi(T0_64
);
1631 void do_efscfui (void)
1633 T0_64
= _do_efscfui(T0_64
);
1636 void do_efsctsi (void)
1638 T0_64
= _do_efsctsi(T0_64
);
1641 void do_efsctui (void)
1643 T0_64
= _do_efsctui(T0_64
);
1646 void do_efsctsiz (void)
1648 T0_64
= _do_efsctsiz(T0_64
);
1651 void do_efsctuiz (void)
1653 T0_64
= _do_efsctuiz(T0_64
);
1656 /* Single precision floating-point conversion to/from fractional */
1657 static inline uint32_t _do_efscfsf (uint32_t val
)
1665 u
.f
= int32_to_float32(val
, &env
->spe_status
);
1666 tmp
= int64_to_float32(1ULL << 32, &env
->spe_status
);
1667 u
.f
= float32_div(u
.f
, tmp
, &env
->spe_status
);
1672 static inline uint32_t _do_efscfuf (uint32_t val
)
1680 u
.f
= uint32_to_float32(val
, &env
->spe_status
);
1681 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1682 u
.f
= float32_div(u
.f
, tmp
, &env
->spe_status
);
1687 static inline int32_t _do_efsctsf (uint32_t val
)
1696 /* NaN are not treated the same way IEEE 754 does */
1697 if (unlikely(isnan(u
.f
)))
1699 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1700 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
1702 return float32_to_int32(u
.f
, &env
->spe_status
);
1705 static inline uint32_t _do_efsctuf (uint32_t val
)
1714 /* NaN are not treated the same way IEEE 754 does */
1715 if (unlikely(isnan(u
.f
)))
1717 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1718 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
1720 return float32_to_uint32(u
.f
, &env
->spe_status
);
1723 static inline int32_t _do_efsctsfz (uint32_t val
)
1732 /* NaN are not treated the same way IEEE 754 does */
1733 if (unlikely(isnan(u
.f
)))
1735 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1736 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
1738 return float32_to_int32_round_to_zero(u
.f
, &env
->spe_status
);
1741 static inline uint32_t _do_efsctufz (uint32_t val
)
1750 /* NaN are not treated the same way IEEE 754 does */
1751 if (unlikely(isnan(u
.f
)))
1753 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1754 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
1756 return float32_to_uint32_round_to_zero(u
.f
, &env
->spe_status
);
1759 void do_efscfsf (void)
1761 T0_64
= _do_efscfsf(T0_64
);
1764 void do_efscfuf (void)
1766 T0_64
= _do_efscfuf(T0_64
);
1769 void do_efsctsf (void)
1771 T0_64
= _do_efsctsf(T0_64
);
1774 void do_efsctuf (void)
1776 T0_64
= _do_efsctuf(T0_64
);
1779 void do_efsctsfz (void)
1781 T0_64
= _do_efsctsfz(T0_64
);
1784 void do_efsctufz (void)
1786 T0_64
= _do_efsctufz(T0_64
);
1789 /* Double precision floating point helpers */
1790 static inline int _do_efdcmplt (uint64_t op1
, uint64_t op2
)
1792 /* XXX: TODO: test special values (NaN, infinites, ...) */
1793 return _do_efdtstlt(op1
, op2
);
1796 static inline int _do_efdcmpgt (uint64_t op1
, uint64_t op2
)
1798 /* XXX: TODO: test special values (NaN, infinites, ...) */
1799 return _do_efdtstgt(op1
, op2
);
1802 static inline int _do_efdcmpeq (uint64_t op1
, uint64_t op2
)
1804 /* XXX: TODO: test special values (NaN, infinites, ...) */
1805 return _do_efdtsteq(op1
, op2
);
1808 void do_efdcmplt (void)
1810 T0
= _do_efdcmplt(T0_64
, T1_64
);
1813 void do_efdcmpgt (void)
1815 T0
= _do_efdcmpgt(T0_64
, T1_64
);
1818 void do_efdcmpeq (void)
1820 T0
= _do_efdcmpeq(T0_64
, T1_64
);
1823 /* Double precision floating-point conversion to/from integer */
1824 static inline uint64_t _do_efdcfsi (int64_t val
)
1831 u
.f
= int64_to_float64(val
, &env
->spe_status
);
1836 static inline uint64_t _do_efdcfui (uint64_t val
)
1843 u
.f
= uint64_to_float64(val
, &env
->spe_status
);
1848 static inline int64_t _do_efdctsi (uint64_t val
)
1856 /* NaN are not treated the same way IEEE 754 does */
1857 if (unlikely(isnan(u
.f
)))
1860 return float64_to_int64(u
.f
, &env
->spe_status
);
1863 static inline uint64_t _do_efdctui (uint64_t val
)
1871 /* NaN are not treated the same way IEEE 754 does */
1872 if (unlikely(isnan(u
.f
)))
1875 return float64_to_uint64(u
.f
, &env
->spe_status
);
1878 static inline int64_t _do_efdctsiz (uint64_t val
)
1886 /* NaN are not treated the same way IEEE 754 does */
1887 if (unlikely(isnan(u
.f
)))
1890 return float64_to_int64_round_to_zero(u
.f
, &env
->spe_status
);
1893 static inline uint64_t _do_efdctuiz (uint64_t val
)
1901 /* NaN are not treated the same way IEEE 754 does */
1902 if (unlikely(isnan(u
.f
)))
1905 return float64_to_uint64_round_to_zero(u
.f
, &env
->spe_status
);
1908 void do_efdcfsi (void)
1910 T0_64
= _do_efdcfsi(T0_64
);
1913 void do_efdcfui (void)
1915 T0_64
= _do_efdcfui(T0_64
);
1918 void do_efdctsi (void)
1920 T0_64
= _do_efdctsi(T0_64
);
1923 void do_efdctui (void)
1925 T0_64
= _do_efdctui(T0_64
);
1928 void do_efdctsiz (void)
1930 T0_64
= _do_efdctsiz(T0_64
);
1933 void do_efdctuiz (void)
1935 T0_64
= _do_efdctuiz(T0_64
);
1938 /* Double precision floating-point conversion to/from fractional */
1939 static inline uint64_t _do_efdcfsf (int64_t val
)
1947 u
.f
= int32_to_float64(val
, &env
->spe_status
);
1948 tmp
= int64_to_float64(1ULL << 32, &env
->spe_status
);
1949 u
.f
= float64_div(u
.f
, tmp
, &env
->spe_status
);
1954 static inline uint64_t _do_efdcfuf (uint64_t val
)
1962 u
.f
= uint32_to_float64(val
, &env
->spe_status
);
1963 tmp
= int64_to_float64(1ULL << 32, &env
->spe_status
);
1964 u
.f
= float64_div(u
.f
, tmp
, &env
->spe_status
);
1969 static inline int64_t _do_efdctsf (uint64_t val
)
1978 /* NaN are not treated the same way IEEE 754 does */
1979 if (unlikely(isnan(u
.f
)))
1981 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
1982 u
.f
= float64_mul(u
.f
, tmp
, &env
->spe_status
);
1984 return float64_to_int32(u
.f
, &env
->spe_status
);
1987 static inline uint64_t _do_efdctuf (uint64_t val
)
1996 /* NaN are not treated the same way IEEE 754 does */
1997 if (unlikely(isnan(u
.f
)))
1999 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2000 u
.f
= float64_mul(u
.f
, tmp
, &env
->spe_status
);
2002 return float64_to_uint32(u
.f
, &env
->spe_status
);
2005 static inline int64_t _do_efdctsfz (uint64_t val
)
2014 /* NaN are not treated the same way IEEE 754 does */
2015 if (unlikely(isnan(u
.f
)))
2017 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2018 u
.f
= float64_mul(u
.f
, tmp
, &env
->spe_status
);
2020 return float64_to_int32_round_to_zero(u
.f
, &env
->spe_status
);
2023 static inline uint64_t _do_efdctufz (uint64_t val
)
2032 /* NaN are not treated the same way IEEE 754 does */
2033 if (unlikely(isnan(u
.f
)))
2035 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2036 u
.f
= float64_mul(u
.f
, tmp
, &env
->spe_status
);
2038 return float64_to_uint32_round_to_zero(u
.f
, &env
->spe_status
);
2041 void do_efdcfsf (void)
2043 T0_64
= _do_efdcfsf(T0_64
);
2046 void do_efdcfuf (void)
2048 T0_64
= _do_efdcfuf(T0_64
);
2051 void do_efdctsf (void)
2053 T0_64
= _do_efdctsf(T0_64
);
2056 void do_efdctuf (void)
2058 T0_64
= _do_efdctuf(T0_64
);
2061 void do_efdctsfz (void)
2063 T0_64
= _do_efdctsfz(T0_64
);
2066 void do_efdctufz (void)
2068 T0_64
= _do_efdctufz(T0_64
);
2071 /* Floating point conversion between single and double precision */
2072 static inline uint32_t _do_efscfd (uint64_t val
)
2084 u2
.f
= float64_to_float32(u1
.f
, &env
->spe_status
);
2089 static inline uint64_t _do_efdcfs (uint32_t val
)
2101 u2
.f
= float32_to_float64(u1
.f
, &env
->spe_status
);
2106 void do_efscfd (void)
2108 T0_64
= _do_efscfd(T0_64
);
2111 void do_efdcfs (void)
2113 T0_64
= _do_efdcfs(T0_64
);
2116 /* Single precision fixed-point vector arithmetic */
2132 /* Single-precision floating-point comparisons */
2133 static inline int _do_efscmplt (uint32_t op1
, uint32_t op2
)
2135 /* XXX: TODO: test special values (NaN, infinites, ...) */
2136 return _do_efststlt(op1
, op2
);
2139 static inline int _do_efscmpgt (uint32_t op1
, uint32_t op2
)
2141 /* XXX: TODO: test special values (NaN, infinites, ...) */
2142 return _do_efststgt(op1
, op2
);
2145 static inline int _do_efscmpeq (uint32_t op1
, uint32_t op2
)
2147 /* XXX: TODO: test special values (NaN, infinites, ...) */
2148 return _do_efststeq(op1
, op2
);
2151 void do_efscmplt (void)
2153 T0
= _do_efscmplt(T0_64
, T1_64
);
2156 void do_efscmpgt (void)
2158 T0
= _do_efscmpgt(T0_64
, T1_64
);
2161 void do_efscmpeq (void)
2163 T0
= _do_efscmpeq(T0_64
, T1_64
);
2166 /* Single-precision floating-point vector comparisons */
2168 DO_SPE_CMP(fscmplt
);
2170 DO_SPE_CMP(fscmpgt
);
2172 DO_SPE_CMP(fscmpeq
);
2174 DO_SPE_CMP(fststlt
);
2176 DO_SPE_CMP(fststgt
);
2178 DO_SPE_CMP(fststeq
);
2180 /* Single-precision floating-point vector conversions */
2194 DO_SPE_OP1(fsctsiz
);
2196 DO_SPE_OP1(fsctuiz
);
2201 #endif /* defined(TARGET_PPCEMB) */
2203 /*****************************************************************************/
2204 /* Softmmu support */
2205 #if !defined (CONFIG_USER_ONLY)
2207 #define MMUSUFFIX _mmu
2208 #define GETPC() (__builtin_return_address(0))
2211 #include "softmmu_template.h"
2214 #include "softmmu_template.h"
2217 #include "softmmu_template.h"
2220 #include "softmmu_template.h"
2222 /* try to fill the TLB and return an exception if error. If retaddr is
2223 NULL, it means that the function was called in C code (i.e. not
2224 from generated code or from helper.c) */
2225 /* XXX: fix it to restore all registers */
2226 void tlb_fill (target_ulong addr
, int is_write
, int is_user
, void *retaddr
)
2228 TranslationBlock
*tb
;
2229 CPUState
*saved_env
;
2230 target_phys_addr_t pc
;
2233 /* XXX: hack to restore env in all cases, even if not called from
2236 env
= cpu_single_env
;
2237 ret
= cpu_ppc_handle_mmu_fault(env
, addr
, is_write
, is_user
, 1);
2238 if (unlikely(ret
!= 0)) {
2239 if (likely(retaddr
)) {
2240 /* now we have a real cpu fault */
2241 pc
= (target_phys_addr_t
)retaddr
;
2242 tb
= tb_find_pc(pc
);
2244 /* the PC is inside the translated code. It means that we have
2245 a virtual CPU fault */
2246 cpu_restore_state(tb
, env
, pc
, NULL
);
2249 do_raise_exception_err(env
->exception_index
, env
->error_code
);
2254 /* TLB invalidation helpers */
2255 void do_tlbia (void)
2257 ppc_tlb_invalidate_all(env
);
2260 void do_tlbie (void)
2263 #if !defined(FLUSH_ALL_TLBS)
2264 if (unlikely(PPC_MMU(env
) == PPC_FLAGS_MMU_SOFT_6xx
)) {
2265 ppc6xx_tlb_invalidate_virt(env
, T0
& TARGET_PAGE_MASK
, 0);
2266 if (env
->id_tlbs
== 1)
2267 ppc6xx_tlb_invalidate_virt(env
, T0
& TARGET_PAGE_MASK
, 1);
2268 } else if (unlikely(PPC_MMU(env
) == PPC_FLAGS_MMU_SOFT_4xx
)) {
2271 ppcbooke_tlb_invalidate_virt(env
, T0
& TARGET_PAGE_MASK
,
2272 env
->spr
[SPR_BOOKE_PID
]);
2275 /* tlbie invalidate TLBs for all segments */
2276 T0
&= TARGET_PAGE_MASK
;
2277 T0
&= ~((target_ulong
)-1 << 28);
2278 /* XXX: this case should be optimized,
2279 * giving a mask to tlb_flush_page
2281 tlb_flush_page(env
, T0
| (0x0 << 28));
2282 tlb_flush_page(env
, T0
| (0x1 << 28));
2283 tlb_flush_page(env
, T0
| (0x2 << 28));
2284 tlb_flush_page(env
, T0
| (0x3 << 28));
2285 tlb_flush_page(env
, T0
| (0x4 << 28));
2286 tlb_flush_page(env
, T0
| (0x5 << 28));
2287 tlb_flush_page(env
, T0
| (0x6 << 28));
2288 tlb_flush_page(env
, T0
| (0x7 << 28));
2289 tlb_flush_page(env
, T0
| (0x8 << 28));
2290 tlb_flush_page(env
, T0
| (0x9 << 28));
2291 tlb_flush_page(env
, T0
| (0xA << 28));
2292 tlb_flush_page(env
, T0
| (0xB << 28));
2293 tlb_flush_page(env
, T0
| (0xC << 28));
2294 tlb_flush_page(env
, T0
| (0xD << 28));
2295 tlb_flush_page(env
, T0
| (0xE << 28));
2296 tlb_flush_page(env
, T0
| (0xF << 28));
2303 #if defined(TARGET_PPC64)
2304 void do_tlbie_64 (void)
2307 #if !defined(FLUSH_ALL_TLBS)
2308 if (unlikely(PPC_MMU(env
) == PPC_FLAGS_MMU_SOFT_6xx
)) {
2309 ppc6xx_tlb_invalidate_virt(env
, T0
& TARGET_PAGE_MASK
, 0);
2310 if (env
->id_tlbs
== 1)
2311 ppc6xx_tlb_invalidate_virt(env
, T0
& TARGET_PAGE_MASK
, 1);
2312 } else if (unlikely(PPC_MMU(env
) == PPC_FLAGS_MMU_SOFT_4xx
)) {
2315 ppcbooke_tlb_invalidate_virt(env
, T0
& TARGET_PAGE_MASK
,
2316 env
->spr
[SPR_BOOKE_PID
]);
2319 /* tlbie invalidate TLBs for all segments
2320 * As we have 2^36 segments, invalidate all qemu TLBs
2323 T0
&= TARGET_PAGE_MASK
;
2324 T0
&= ~((target_ulong
)-1 << 28);
2325 /* XXX: this case should be optimized,
2326 * giving a mask to tlb_flush_page
2328 tlb_flush_page(env
, T0
| (0x0 << 28));
2329 tlb_flush_page(env
, T0
| (0x1 << 28));
2330 tlb_flush_page(env
, T0
| (0x2 << 28));
2331 tlb_flush_page(env
, T0
| (0x3 << 28));
2332 tlb_flush_page(env
, T0
| (0x4 << 28));
2333 tlb_flush_page(env
, T0
| (0x5 << 28));
2334 tlb_flush_page(env
, T0
| (0x6 << 28));
2335 tlb_flush_page(env
, T0
| (0x7 << 28));
2336 tlb_flush_page(env
, T0
| (0x8 << 28));
2337 tlb_flush_page(env
, T0
| (0x9 << 28));
2338 tlb_flush_page(env
, T0
| (0xA << 28));
2339 tlb_flush_page(env
, T0
| (0xB << 28));
2340 tlb_flush_page(env
, T0
| (0xC << 28));
2341 tlb_flush_page(env
, T0
| (0xD << 28));
2342 tlb_flush_page(env
, T0
| (0xE << 28));
2343 tlb_flush_page(env
, T0
| (0xF << 28));
2354 #if defined(TARGET_PPC64)
2355 void do_slbia (void)
2361 void do_slbie (void)
2368 /* Software driven TLBs management */
2369 /* PowerPC 602/603 software TLB load instructions helpers */
2370 void do_load_6xx_tlb (int is_code
)
2372 target_ulong RPN
, CMP
, EPN
;
2375 RPN
= env
->spr
[SPR_RPA
];
2377 CMP
= env
->spr
[SPR_ICMP
];
2378 EPN
= env
->spr
[SPR_IMISS
];
2380 CMP
= env
->spr
[SPR_DCMP
];
2381 EPN
= env
->spr
[SPR_DMISS
];
2383 way
= (env
->spr
[SPR_SRR1
] >> 17) & 1;
2384 #if defined (DEBUG_SOFTWARE_TLB)
2385 if (loglevel
!= 0) {
2386 fprintf(logfile
, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2387 __func__
, (unsigned long)T0
, (unsigned long)EPN
,
2388 (unsigned long)CMP
, (unsigned long)RPN
, way
);
2391 /* Store this TLB */
2392 ppc6xx_tlb_store(env
, (uint32_t)(T0
& TARGET_PAGE_MASK
),
2393 way
, is_code
, CMP
, RPN
);
2396 static target_ulong
booke_tlb_to_page_size (int size
)
2398 return 1024 << (2 * size
);
2401 static int booke_page_size_to_tlb (target_ulong page_size
)
2405 switch (page_size
) {
2439 #if defined (TARGET_PPC64)
2440 case 0x000100000000ULL
:
2443 case 0x000400000000ULL
:
2446 case 0x001000000000ULL
:
2449 case 0x004000000000ULL
:
2452 case 0x010000000000ULL
:
2464 /* Helpers for 4xx TLB management */
2465 void do_4xx_tlbre_lo (void)
2471 tlb
= &env
->tlb
[T0
].tlbe
;
2473 if (tlb
->prot
& PAGE_VALID
)
2475 size
= booke_page_size_to_tlb(tlb
->size
);
2476 if (size
< 0 || size
> 0x7)
2479 env
->spr
[SPR_40x_PID
] = tlb
->PID
;
2482 void do_4xx_tlbre_hi (void)
2487 tlb
= &env
->tlb
[T0
].tlbe
;
2489 if (tlb
->prot
& PAGE_EXEC
)
2491 if (tlb
->prot
& PAGE_WRITE
)
2495 void do_4xx_tlbsx (void)
2497 T0
= ppcemb_tlb_search(env
, T0
, env
->spr
[SPR_40x_PID
]);
2500 void do_4xx_tlbsx_ (void)
2504 T0
= ppcemb_tlb_search(env
, T0
, env
->spr
[SPR_40x_PID
]);
2510 void do_4xx_tlbwe_hi (void)
2513 target_ulong page
, end
;
2515 #if defined (DEBUG_SOFTWARE_TLB)
2516 if (loglevel
!= 0) {
2517 fprintf(logfile
, "%s T0 " REGX
" T1 " REGX
"\n", __func__
, T0
, T1
);
2521 tlb
= &env
->tlb
[T0
].tlbe
;
2522 /* Invalidate previous TLB (if it's valid) */
2523 if (tlb
->prot
& PAGE_VALID
) {
2524 end
= tlb
->EPN
+ tlb
->size
;
2525 #if defined (DEBUG_SOFTWARE_TLB)
2526 if (loglevel
!= 0) {
2527 fprintf(logfile
, "%s: invalidate old TLB %d start " ADDRX
2528 " end " ADDRX
"\n", __func__
, (int)T0
, tlb
->EPN
, end
);
2531 for (page
= tlb
->EPN
; page
< end
; page
+= TARGET_PAGE_SIZE
)
2532 tlb_flush_page(env
, page
);
2534 tlb
->size
= booke_tlb_to_page_size((T1
>> 7) & 0x7);
2535 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2536 * If this ever occurs, one should use the ppcemb target instead
2537 * of the ppc or ppc64 one
2539 if ((T1
& 0x40) && tlb
->size
< TARGET_PAGE_SIZE
) {
2540 cpu_abort(env
, "TLB size %u < %u are not supported (%d)\n",
2541 tlb
->size
, TARGET_PAGE_SIZE
, (int)((T1
>> 7) & 0x7));
2543 tlb
->EPN
= (T1
& 0xFFFFFC00) & ~(tlb
->size
- 1);
2545 tlb
->prot
|= PAGE_VALID
;
2547 tlb
->prot
&= ~PAGE_VALID
;
2549 /* XXX: TO BE FIXED */
2550 cpu_abort(env
, "Little-endian TLB entries are not supported by now\n");
2552 tlb
->PID
= env
->spr
[SPR_40x_PID
]; /* PID */
2553 tlb
->attr
= T1
& 0xFF;
2554 #if defined (DEBUG_SOFTWARE_TLB)
2555 if (loglevel
!= 0) {
2556 fprintf(logfile
, "%s: set up TLB %d RPN " PADDRX
" EPN " ADDRX
2557 " size " ADDRX
" prot %c%c%c%c PID %d\n", __func__
,
2558 (int)T0
, tlb
->RPN
, tlb
->EPN
, tlb
->size
,
2559 tlb
->prot
& PAGE_READ
? 'r' : '-',
2560 tlb
->prot
& PAGE_WRITE
? 'w' : '-',
2561 tlb
->prot
& PAGE_EXEC
? 'x' : '-',
2562 tlb
->prot
& PAGE_VALID
? 'v' : '-', (int)tlb
->PID
);
2565 /* Invalidate new TLB (if valid) */
2566 if (tlb
->prot
& PAGE_VALID
) {
2567 end
= tlb
->EPN
+ tlb
->size
;
2568 #if defined (DEBUG_SOFTWARE_TLB)
2569 if (loglevel
!= 0) {
2570 fprintf(logfile
, "%s: invalidate TLB %d start " ADDRX
2571 " end " ADDRX
"\n", __func__
, (int)T0
, tlb
->EPN
, end
);
2574 for (page
= tlb
->EPN
; page
< end
; page
+= TARGET_PAGE_SIZE
)
2575 tlb_flush_page(env
, page
);
2579 void do_4xx_tlbwe_lo (void)
2583 #if defined (DEBUG_SOFTWARE_TLB)
2584 if (loglevel
!= 0) {
2585 fprintf(logfile
, "%s T0 " REGX
" T1 " REGX
"\n", __func__
, T0
, T1
);
2589 tlb
= &env
->tlb
[T0
].tlbe
;
2590 tlb
->RPN
= T1
& 0xFFFFFC00;
2591 tlb
->prot
= PAGE_READ
;
2593 tlb
->prot
|= PAGE_EXEC
;
2595 tlb
->prot
|= PAGE_WRITE
;
2596 #if defined (DEBUG_SOFTWARE_TLB)
2597 if (loglevel
!= 0) {
2598 fprintf(logfile
, "%s: set up TLB %d RPN " PADDRX
" EPN " ADDRX
2599 " size " ADDRX
" prot %c%c%c%c PID %d\n", __func__
,
2600 (int)T0
, tlb
->RPN
, tlb
->EPN
, tlb
->size
,
2601 tlb
->prot
& PAGE_READ
? 'r' : '-',
2602 tlb
->prot
& PAGE_WRITE
? 'w' : '-',
2603 tlb
->prot
& PAGE_EXEC
? 'x' : '-',
2604 tlb
->prot
& PAGE_VALID
? 'v' : '-', (int)tlb
->PID
);
2609 /* BookE TLB management */
2610 void do_booke_tlbwe0 (void)
2613 target_ulong EPN
, size
;
2616 #if defined (DEBUG_SOFTWARE_TLB)
2617 if (loglevel
!= 0) {
2618 fprintf(logfile
, "%s T0 " REGX
" T1 " REGX
"\n", __func__
, T0
, T1
);
2623 tlb
= &env
->tlb
[T0
].tlbe
;
2624 EPN
= T1
& 0xFFFFFC00;
2625 if ((tlb
->prot
& PAGE_VALID
) && EPN
!= tlb
->EPN
)
2628 size
= booke_tlb_to_page_size((T1
>> 4) & 0xF);
2629 if ((tlb
->prot
& PAGE_VALID
) && tlb
->size
< size
)
2633 tlb
->attr
|= (T1
>> 8) & 1;
2635 tlb
->prot
|= PAGE_VALID
;
2637 if (tlb
->prot
& PAGE_VALID
) {
2638 tlb
->prot
&= ~PAGE_VALID
;
2642 tlb
->PID
= env
->spr
[SPR_BOOKE_PID
];
2647 void do_booke_tlbwe1 (void)
2650 target_phys_addr_t RPN
;
2652 #if defined (DEBUG_SOFTWARE_TLB)
2653 if (loglevel
!= 0) {
2654 fprintf(logfile
, "%s T0 " REGX
" T1 " REGX
"\n", __func__
, T0
, T1
);
2658 tlb
= &env
->tlb
[T0
].tlbe
;
2659 RPN
= T1
& 0xFFFFFC0F;
2660 if ((tlb
->prot
& PAGE_VALID
) && tlb
->RPN
!= RPN
)
2665 void do_booke_tlbwe2 (void)
2669 #if defined (DEBUG_SOFTWARE_TLB)
2670 if (loglevel
!= 0) {
2671 fprintf(logfile
, "%s T0 " REGX
" T1 " REGX
"\n", __func__
, T0
, T1
);
2675 tlb
= &env
->tlb
[T0
].tlbe
;
2676 tlb
->attr
= (tlb
->attr
& 0x1) | (T1
& 0x0000FF00);
2677 tlb
->prot
= tlb
->prot
& PAGE_VALID
;
2679 tlb
->prot
|= PAGE_READ
<< 4;
2681 tlb
->prot
|= PAGE_WRITE
<< 4;
2683 tlb
->prot
|= PAGE_EXEC
<< 4;
2685 tlb
->prot
|= PAGE_READ
;
2687 tlb
->prot
|= PAGE_WRITE
;
2689 tlb
->prot
|= PAGE_EXEC
;
2692 void do_booke_tlbsx (void)
2694 T0
= ppcemb_tlb_search(env
, T0
, env
->spr
[SPR_440_MMUCR
]);
2697 void do_booke_tlbsx_ (void)
2701 T0
= ppcemb_tlb_search(env
, T0
, env
->spr
[SPR_440_MMUCR
]);
2707 void do_booke_tlbre0 (void)
2713 tlb
= &env
->tlb
[T0
].tlbe
;
2715 size
= booke_page_size_to_tlb(tlb
->size
);
2716 if (size
< 0 || size
> 0xF)
2719 if (tlb
->attr
& 0x1)
2721 if (tlb
->prot
& PAGE_VALID
)
2723 env
->spr
[SPR_BOOKE_PID
] = tlb
->PID
;
2726 void do_booke_tlbre1 (void)
2731 tlb
= &env
->tlb
[T0
].tlbe
;
2735 void do_booke_tlbre2 (void)
2740 tlb
= &env
->tlb
[T0
].tlbe
;
2741 T0
= tlb
->attr
& ~0x1;
2742 if (tlb
->prot
& (PAGE_READ
<< 4))
2744 if (tlb
->prot
& (PAGE_WRITE
<< 4))
2746 if (tlb
->prot
& (PAGE_EXEC
<< 4))
2748 if (tlb
->prot
& PAGE_READ
)
2750 if (tlb
->prot
& PAGE_WRITE
)
2752 if (tlb
->prot
& PAGE_EXEC
)
2755 #endif /* !CONFIG_USER_ONLY */