]>
git.proxmox.com Git - qemu.git/blob - target-ppc/op_helper.c
2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include "op_helper.h"
24 #define MEMSUFFIX _raw
25 #include "op_helper.h"
26 #include "op_helper_mem.h"
27 #if !defined(CONFIG_USER_ONLY)
28 #define MEMSUFFIX _user
29 #include "op_helper.h"
30 #include "op_helper_mem.h"
31 #define MEMSUFFIX _kernel
32 #include "op_helper.h"
33 #include "op_helper_mem.h"
34 #if defined(TARGET_PPC64H)
35 #define MEMSUFFIX _hypv
36 #include "op_helper.h"
37 #include "op_helper_mem.h"
42 //#define DEBUG_EXCEPTIONS
43 //#define DEBUG_SOFTWARE_TLB
45 /*****************************************************************************/
46 /* Exceptions processing helpers */
48 void do_raise_exception_err (uint32_t exception
, int error_code
)
51 printf("Raise exception %3x code : %d\n", exception
, error_code
);
54 case POWERPC_EXCP_PROGRAM
:
55 if (error_code
== POWERPC_EXCP_FP
&& msr_fe0
== 0 && msr_fe1
== 0)
61 env
->exception_index
= exception
;
62 env
->error_code
= error_code
;
66 void do_raise_exception (uint32_t exception
)
68 do_raise_exception_err(exception
, 0);
71 void cpu_dump_EA (target_ulong EA
);
72 void do_print_mem_EA (target_ulong EA
)
77 /*****************************************************************************/
78 /* Registers load and stores */
79 void do_load_cr (void)
81 T0
= (env
->crf
[0] << 28) |
91 void do_store_cr (uint32_t mask
)
95 for (i
= 0, sh
= 7; i
< 8; i
++, sh
--) {
97 env
->crf
[i
] = (T0
>> (sh
* 4)) & 0xFUL
;
101 void do_load_xer (void)
103 T0
= (xer_so
<< XER_SO
) |
107 (xer_cmp
<< XER_CMP
);
110 void do_store_xer (void)
112 xer_so
= (T0
>> XER_SO
) & 0x01;
113 xer_ov
= (T0
>> XER_OV
) & 0x01;
114 xer_ca
= (T0
>> XER_CA
) & 0x01;
115 xer_cmp
= (T0
>> XER_CMP
) & 0xFF;
116 xer_bc
= (T0
>> XER_BC
) & 0x7F;
119 #if defined(TARGET_PPC64)
120 void do_store_pri (int prio
)
122 env
->spr
[SPR_PPR
] &= ~0x001C000000000000ULL
;
123 env
->spr
[SPR_PPR
] |= ((uint64_t)prio
& 0x7) << 50;
127 void do_load_fpscr (void)
129 /* The 32 MSB of the target fpr are undefined.
140 #if defined(WORDS_BIGENDIAN)
149 for (i
= 0; i
< 8; i
++)
150 u
.s
.u
[WORD1
] |= env
->fpscr
[i
] << (4 * i
);
154 void do_store_fpscr (uint32_t mask
)
157 * We use only the 32 LSB of the incoming fpr
169 env
->fpscr
[0] = (env
->fpscr
[0] & 0x9) | ((u
.s
.u
[WORD1
] >> 28) & ~0x9);
170 for (i
= 1; i
< 7; i
++) {
171 if (mask
& (1 << (7 - i
)))
172 env
->fpscr
[i
] = (u
.s
.u
[WORD1
] >> (4 * (7 - i
))) & 0xF;
174 /* TODO: update FEX & VX */
175 /* Set rounding mode */
176 switch (env
->fpscr
[0] & 0x3) {
178 /* Best approximation (round to nearest) */
179 rnd_type
= float_round_nearest_even
;
182 /* Smaller magnitude (round toward zero) */
183 rnd_type
= float_round_to_zero
;
186 /* Round toward +infinite */
187 rnd_type
= float_round_up
;
191 /* Round toward -infinite */
192 rnd_type
= float_round_down
;
195 set_float_rounding_mode(rnd_type
, &env
->fp_status
);
198 target_ulong
ppc_load_dump_spr (int sprn
)
201 fprintf(logfile
, "Read SPR %d %03x => " ADDRX
"\n",
202 sprn
, sprn
, env
->spr
[sprn
]);
205 return env
->spr
[sprn
];
208 void ppc_store_dump_spr (int sprn
, target_ulong val
)
211 fprintf(logfile
, "Write SPR %d %03x => " ADDRX
" <= " ADDRX
"\n",
212 sprn
, sprn
, env
->spr
[sprn
], val
);
214 env
->spr
[sprn
] = val
;
217 /*****************************************************************************/
218 /* Fixed point operations helpers */
219 #if defined(TARGET_PPC64)
220 static void add128 (uint64_t *plow
, uint64_t *phigh
, uint64_t a
, uint64_t b
)
229 static void neg128 (uint64_t *plow
, uint64_t *phigh
)
233 add128(plow
, phigh
, 1, 0);
236 static void mul64 (uint64_t *plow
, uint64_t *phigh
, uint64_t a
, uint64_t b
)
238 uint32_t a0
, a1
, b0
, b1
;
247 v
= (uint64_t)a0
* (uint64_t)b0
;
251 v
= (uint64_t)a0
* (uint64_t)b1
;
252 add128(plow
, phigh
, v
<< 32, v
>> 32);
254 v
= (uint64_t)a1
* (uint64_t)b0
;
255 add128(plow
, phigh
, v
<< 32, v
>> 32);
257 v
= (uint64_t)a1
* (uint64_t)b1
;
259 #if defined(DEBUG_MULDIV)
260 printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
261 a
, b
, *phigh
, *plow
);
265 void do_mul64 (uint64_t *plow
, uint64_t *phigh
)
267 mul64(plow
, phigh
, T0
, T1
);
270 static void imul64 (uint64_t *plow
, uint64_t *phigh
, int64_t a
, int64_t b
)
280 mul64(plow
, phigh
, a
, b
);
286 void do_imul64 (uint64_t *plow
, uint64_t *phigh
)
288 imul64(plow
, phigh
, T0
, T1
);
296 if (likely(!((uint32_t)T0
< (uint32_t)T2
||
297 (xer_ca
== 1 && (uint32_t)T0
== (uint32_t)T2
)))) {
304 #if defined(TARGET_PPC64)
305 void do_adde_64 (void)
309 if (likely(!((uint64_t)T0
< (uint64_t)T2
||
310 (xer_ca
== 1 && (uint64_t)T0
== (uint64_t)T2
)))) {
318 void do_addmeo (void)
322 if (likely(!((uint32_t)T1
&
323 ((uint32_t)T1
^ (uint32_t)T0
) & (1UL << 31)))) {
333 #if defined(TARGET_PPC64)
334 void do_addmeo_64 (void)
338 if (likely(!((uint64_t)T1
&
339 ((uint64_t)T1
^ (uint64_t)T0
) & (1ULL << 63)))) {
352 if (likely(!(((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== -1) ||
353 (int32_t)T1
== 0))) {
355 T0
= (int32_t)T0
/ (int32_t)T1
;
359 T0
= (-1) * ((uint32_t)T0
>> 31);
363 #if defined(TARGET_PPC64)
366 if (likely(!(((int64_t)T0
== INT64_MIN
&& (int64_t)T1
== -1ULL) ||
367 (int64_t)T1
== 0))) {
369 T0
= (int64_t)T0
/ (int64_t)T1
;
373 T0
= (-1ULL) * ((uint64_t)T0
>> 63);
378 void do_divwuo (void)
380 if (likely((uint32_t)T1
!= 0)) {
382 T0
= (uint32_t)T0
/ (uint32_t)T1
;
390 #if defined(TARGET_PPC64)
391 void do_divduo (void)
393 if (likely((uint64_t)T1
!= 0)) {
395 T0
= (uint64_t)T0
/ (uint64_t)T1
;
404 void do_mullwo (void)
406 int64_t res
= (int64_t)T0
* (int64_t)T1
;
408 if (likely((int32_t)res
== res
)) {
417 #if defined(TARGET_PPC64)
418 void do_mulldo (void)
424 if (likely(th
== 0)) {
436 if (likely((int32_t)T0
!= INT32_MIN
)) {
445 #if defined(TARGET_PPC64)
446 void do_nego_64 (void)
448 if (likely((int64_t)T0
!= INT64_MIN
)) {
460 T0
= T1
+ ~T0
+ xer_ca
;
461 if (likely((uint32_t)T0
>= (uint32_t)T1
&&
462 (xer_ca
== 0 || (uint32_t)T0
!= (uint32_t)T1
))) {
469 #if defined(TARGET_PPC64)
470 void do_subfe_64 (void)
472 T0
= T1
+ ~T0
+ xer_ca
;
473 if (likely((uint64_t)T0
>= (uint64_t)T1
&&
474 (xer_ca
== 0 || (uint64_t)T0
!= (uint64_t)T1
))) {
482 void do_subfmeo (void)
485 T0
= ~T0
+ xer_ca
- 1;
486 if (likely(!((uint32_t)~T1
& ((uint32_t)~T1
^ (uint32_t)T0
) &
493 if (likely((uint32_t)T1
!= UINT32_MAX
))
497 #if defined(TARGET_PPC64)
498 void do_subfmeo_64 (void)
501 T0
= ~T0
+ xer_ca
- 1;
502 if (likely(!((uint64_t)~T1
& ((uint64_t)~T1
^ (uint64_t)T0
) &
509 if (likely((uint64_t)T1
!= UINT64_MAX
))
514 void do_subfzeo (void)
518 if (likely(!(((uint32_t)~T1
^ UINT32_MAX
) &
519 ((uint32_t)(~T1
) ^ (uint32_t)T0
) & (1UL << 31)))) {
525 if (likely((uint32_t)T0
>= (uint32_t)~T1
)) {
532 #if defined(TARGET_PPC64)
533 void do_subfzeo_64 (void)
537 if (likely(!(((uint64_t)~T1
^ UINT64_MAX
) &
538 ((uint64_t)(~T1
) ^ (uint64_t)T0
) & (1ULL << 63)))) {
544 if (likely((uint64_t)T0
>= (uint64_t)~T1
)) {
552 /* shift right arithmetic helper */
557 if (likely(!(T1
& 0x20UL
))) {
558 if (likely((uint32_t)T1
!= 0)) {
559 ret
= (int32_t)T0
>> (T1
& 0x1fUL
);
560 if (likely(ret
>= 0 || ((int32_t)T0
& ((1 << T1
) - 1)) == 0)) {
570 ret
= (-1) * ((uint32_t)T0
>> 31);
571 if (likely(ret
>= 0 || ((uint32_t)T0
& ~0x80000000UL
) == 0)) {
580 #if defined(TARGET_PPC64)
585 if (likely(!(T1
& 0x40UL
))) {
586 if (likely((uint64_t)T1
!= 0)) {
587 ret
= (int64_t)T0
>> (T1
& 0x3FUL
);
588 if (likely(ret
>= 0 || ((int64_t)T0
& ((1 << T1
) - 1)) == 0)) {
598 ret
= (-1) * ((uint64_t)T0
>> 63);
599 if (likely(ret
>= 0 || ((uint64_t)T0
& ~0x8000000000000000ULL
) == 0)) {
609 static always_inline
int popcnt (uint32_t val
)
613 for (i
= 0; val
!= 0;)
614 val
= val
^ (val
- 1);
619 void do_popcntb (void)
625 for (i
= 0; i
< 32; i
+= 8)
626 ret
|= popcnt((T0
>> i
) & 0xFF) << i
;
630 #if defined(TARGET_PPC64)
631 void do_popcntb_64 (void)
637 for (i
= 0; i
< 64; i
+= 8)
638 ret
|= popcnt((T0
>> i
) & 0xFF) << i
;
643 /*****************************************************************************/
644 /* Floating point operations helpers */
652 p
.i
= float64_to_int32(FT0
, &env
->fp_status
);
653 #if USE_PRECISE_EMULATION
654 /* XXX: higher bits are not supposed to be significant.
655 * to make tests easier, return the same as a real PowerPC 750 (aka G3)
657 p
.i
|= 0xFFF80000ULL
<< 32;
662 void do_fctiwz (void)
669 p
.i
= float64_to_int32_round_to_zero(FT0
, &env
->fp_status
);
670 #if USE_PRECISE_EMULATION
671 /* XXX: higher bits are not supposed to be significant.
672 * to make tests easier, return the same as a real PowerPC 750 (aka G3)
674 p
.i
|= 0xFFF80000ULL
<< 32;
679 #if defined(TARGET_PPC64)
688 FT0
= int64_to_float64(p
.i
, &env
->fp_status
);
698 p
.i
= float64_to_int64(FT0
, &env
->fp_status
);
702 void do_fctidz (void)
709 p
.i
= float64_to_int64_round_to_zero(FT0
, &env
->fp_status
);
715 static always_inline
void do_fri (int rounding_mode
)
719 curmode
= env
->fp_status
.float_rounding_mode
;
720 set_float_rounding_mode(rounding_mode
, &env
->fp_status
);
721 FT0
= float64_round_to_int(FT0
, &env
->fp_status
);
722 set_float_rounding_mode(curmode
, &env
->fp_status
);
727 do_fri(float_round_nearest_even
);
732 do_fri(float_round_to_zero
);
737 do_fri(float_round_up
);
742 do_fri(float_round_down
);
745 #if USE_PRECISE_EMULATION
749 float128 ft0_128
, ft1_128
;
751 ft0_128
= float64_to_float128(FT0
, &env
->fp_status
);
752 ft1_128
= float64_to_float128(FT1
, &env
->fp_status
);
753 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
754 ft1_128
= float64_to_float128(FT2
, &env
->fp_status
);
755 ft0_128
= float128_add(ft0_128
, ft1_128
, &env
->fp_status
);
756 FT0
= float128_to_float64(ft0_128
, &env
->fp_status
);
758 /* This is OK on x86 hosts */
759 FT0
= (FT0
* FT1
) + FT2
;
766 float128 ft0_128
, ft1_128
;
768 ft0_128
= float64_to_float128(FT0
, &env
->fp_status
);
769 ft1_128
= float64_to_float128(FT1
, &env
->fp_status
);
770 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
771 ft1_128
= float64_to_float128(FT2
, &env
->fp_status
);
772 ft0_128
= float128_sub(ft0_128
, ft1_128
, &env
->fp_status
);
773 FT0
= float128_to_float64(ft0_128
, &env
->fp_status
);
775 /* This is OK on x86 hosts */
776 FT0
= (FT0
* FT1
) - FT2
;
779 #endif /* USE_PRECISE_EMULATION */
781 void do_fnmadd (void)
783 #if USE_PRECISE_EMULATION
785 float128 ft0_128
, ft1_128
;
787 ft0_128
= float64_to_float128(FT0
, &env
->fp_status
);
788 ft1_128
= float64_to_float128(FT1
, &env
->fp_status
);
789 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
790 ft1_128
= float64_to_float128(FT2
, &env
->fp_status
);
791 ft0_128
= float128_add(ft0_128
, ft1_128
, &env
->fp_status
);
792 FT0
= float128_to_float64(ft0_128
, &env
->fp_status
);
794 /* This is OK on x86 hosts */
795 FT0
= (FT0
* FT1
) + FT2
;
798 FT0
= float64_mul(FT0
, FT1
, &env
->fp_status
);
799 FT0
= float64_add(FT0
, FT2
, &env
->fp_status
);
801 if (likely(!isnan(FT0
)))
802 FT0
= float64_chs(FT0
);
805 void do_fnmsub (void)
807 #if USE_PRECISE_EMULATION
809 float128 ft0_128
, ft1_128
;
811 ft0_128
= float64_to_float128(FT0
, &env
->fp_status
);
812 ft1_128
= float64_to_float128(FT1
, &env
->fp_status
);
813 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
814 ft1_128
= float64_to_float128(FT2
, &env
->fp_status
);
815 ft0_128
= float128_sub(ft0_128
, ft1_128
, &env
->fp_status
);
816 FT0
= float128_to_float64(ft0_128
, &env
->fp_status
);
818 /* This is OK on x86 hosts */
819 FT0
= (FT0
* FT1
) - FT2
;
822 FT0
= float64_mul(FT0
, FT1
, &env
->fp_status
);
823 FT0
= float64_sub(FT0
, FT2
, &env
->fp_status
);
825 if (likely(!isnan(FT0
)))
826 FT0
= float64_chs(FT0
);
831 FT0
= float64_sqrt(FT0
, &env
->fp_status
);
841 if (likely(isnormal(FT0
))) {
842 FT0
= float64_div(1.0, FT0
, &env
->fp_status
);
845 if (p
.i
== 0x8000000000000000ULL
) {
846 p
.i
= 0xFFF0000000000000ULL
;
847 } else if (p
.i
== 0x0000000000000000ULL
) {
848 p
.i
= 0x7FF0000000000000ULL
;
849 } else if (isnan(FT0
)) {
850 p
.i
= 0x7FF8000000000000ULL
;
851 } else if (FT0
< 0.0) {
852 p
.i
= 0x8000000000000000ULL
;
854 p
.i
= 0x0000000000000000ULL
;
867 if (likely(isnormal(FT0
))) {
868 #if USE_PRECISE_EMULATION
869 FT0
= float64_div(1.0, FT0
, &env
->fp_status
);
870 FT0
= float64_to_float32(FT0
, &env
->fp_status
);
872 FT0
= float32_div(1.0, FT0
, &env
->fp_status
);
876 if (p
.i
== 0x8000000000000000ULL
) {
877 p
.i
= 0xFFF0000000000000ULL
;
878 } else if (p
.i
== 0x0000000000000000ULL
) {
879 p
.i
= 0x7FF0000000000000ULL
;
880 } else if (isnan(FT0
)) {
881 p
.i
= 0x7FF8000000000000ULL
;
882 } else if (FT0
< 0.0) {
883 p
.i
= 0x8000000000000000ULL
;
885 p
.i
= 0x0000000000000000ULL
;
891 void do_frsqrte (void)
898 if (likely(isnormal(FT0
) && FT0
> 0.0)) {
899 FT0
= float64_sqrt(FT0
, &env
->fp_status
);
900 FT0
= float32_div(1.0, FT0
, &env
->fp_status
);
903 if (p
.i
== 0x8000000000000000ULL
) {
904 p
.i
= 0xFFF0000000000000ULL
;
905 } else if (p
.i
== 0x0000000000000000ULL
) {
906 p
.i
= 0x7FF0000000000000ULL
;
907 } else if (isnan(FT0
)) {
908 if (!(p
.i
& 0x0008000000000000ULL
))
909 p
.i
|= 0x000FFFFFFFFFFFFFULL
;
910 } else if (FT0
< 0) {
911 p
.i
= 0x7FF8000000000000ULL
;
913 p
.i
= 0x0000000000000000ULL
;
929 if (likely(!isnan(FT0
) && !isnan(FT1
))) {
930 if (float64_lt(FT0
, FT1
, &env
->fp_status
)) {
932 } else if (!float64_le(FT0
, FT1
, &env
->fp_status
)) {
939 env
->fpscr
[4] |= 0x1;
940 env
->fpscr
[6] |= 0x1;
947 env
->fpscr
[4] &= ~0x1;
948 if (likely(!isnan(FT0
) && !isnan(FT1
))) {
949 if (float64_lt(FT0
, FT1
, &env
->fp_status
)) {
951 } else if (!float64_le(FT0
, FT1
, &env
->fp_status
)) {
958 env
->fpscr
[4] |= 0x1;
959 if (!float64_is_signaling_nan(FT0
) || !float64_is_signaling_nan(FT1
)) {
961 env
->fpscr
[6] |= 0x1;
962 if (!(env
->fpscr
[1] & 0x8))
963 env
->fpscr
[4] |= 0x8;
965 env
->fpscr
[4] |= 0x8;
971 #if !defined (CONFIG_USER_ONLY)
972 void cpu_dump_rfi (target_ulong RA
, target_ulong msr
);
975 #if defined(TARGET_PPC64)
976 if (env
->spr
[SPR_SRR1
] & (1ULL << MSR_SF
)) {
977 env
->nip
= (uint64_t)(env
->spr
[SPR_SRR0
] & ~0x00000003);
978 do_store_msr(env
, (uint64_t)(env
->spr
[SPR_SRR1
] & ~0xFFFF0000UL
));
980 env
->nip
= (uint32_t)(env
->spr
[SPR_SRR0
] & ~0x00000003);
981 ppc_store_msr_32(env
, (uint32_t)(env
->spr
[SPR_SRR1
] & ~0xFFFF0000UL
));
984 env
->nip
= (uint32_t)(env
->spr
[SPR_SRR0
] & ~0x00000003);
985 do_store_msr(env
, (uint32_t)(env
->spr
[SPR_SRR1
] & ~0xFFFF0000UL
));
987 #if defined (DEBUG_OP)
988 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
990 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
993 #if defined(TARGET_PPC64)
996 if (env
->spr
[SPR_SRR1
] & (1ULL << MSR_SF
)) {
997 env
->nip
= (uint64_t)(env
->spr
[SPR_SRR0
] & ~0x00000003);
998 do_store_msr(env
, (uint64_t)(env
->spr
[SPR_SRR1
] & ~0xFFFF0000UL
));
1000 env
->nip
= (uint32_t)(env
->spr
[SPR_SRR0
] & ~0x00000003);
1001 do_store_msr(env
, (uint32_t)(env
->spr
[SPR_SRR1
] & ~0xFFFF0000UL
));
1003 #if defined (DEBUG_OP)
1004 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
1006 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1009 #if defined(TARGET_PPC64H)
1010 void do_hrfid (void)
1012 if (env
->spr
[SPR_HSRR1
] & (1ULL << MSR_SF
)) {
1013 env
->nip
= (uint64_t)(env
->spr
[SPR_HSRR0
] & ~0x00000003);
1014 do_store_msr(env
, (uint64_t)(env
->spr
[SPR_HSRR1
] & ~0xFFFF0000UL
));
1016 env
->nip
= (uint32_t)(env
->spr
[SPR_HSRR0
] & ~0x00000003);
1017 do_store_msr(env
, (uint32_t)(env
->spr
[SPR_HSRR1
] & ~0xFFFF0000UL
));
1019 #if defined (DEBUG_OP)
1020 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
1022 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1027 void do_tw (int flags
)
1029 if (!likely(!(((int32_t)T0
< (int32_t)T1
&& (flags
& 0x10)) ||
1030 ((int32_t)T0
> (int32_t)T1
&& (flags
& 0x08)) ||
1031 ((int32_t)T0
== (int32_t)T1
&& (flags
& 0x04)) ||
1032 ((uint32_t)T0
< (uint32_t)T1
&& (flags
& 0x02)) ||
1033 ((uint32_t)T0
> (uint32_t)T1
&& (flags
& 0x01))))) {
1034 do_raise_exception_err(POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
1038 #if defined(TARGET_PPC64)
1039 void do_td (int flags
)
1041 if (!likely(!(((int64_t)T0
< (int64_t)T1
&& (flags
& 0x10)) ||
1042 ((int64_t)T0
> (int64_t)T1
&& (flags
& 0x08)) ||
1043 ((int64_t)T0
== (int64_t)T1
&& (flags
& 0x04)) ||
1044 ((uint64_t)T0
< (uint64_t)T1
&& (flags
& 0x02)) ||
1045 ((uint64_t)T0
> (uint64_t)T1
&& (flags
& 0x01)))))
1046 do_raise_exception_err(POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
1050 /*****************************************************************************/
1051 /* PowerPC 601 specific instructions (POWER bridge) */
1052 void do_POWER_abso (void)
1054 if ((uint32_t)T0
== INT32_MIN
) {
1064 void do_POWER_clcs (void)
1068 /* Instruction cache line size */
1069 T0
= env
->icache_line_size
;
1072 /* Data cache line size */
1073 T0
= env
->dcache_line_size
;
1076 /* Minimum cache line size */
1077 T0
= env
->icache_line_size
< env
->dcache_line_size
?
1078 env
->icache_line_size
: env
->dcache_line_size
;
1081 /* Maximum cache line size */
1082 T0
= env
->icache_line_size
> env
->dcache_line_size
?
1083 env
->icache_line_size
: env
->dcache_line_size
;
1091 void do_POWER_div (void)
1095 if (((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== -1) || (int32_t)T1
== 0) {
1096 T0
= (long)((-1) * (T0
>> 31));
1097 env
->spr
[SPR_MQ
] = 0;
1099 tmp
= ((uint64_t)T0
<< 32) | env
->spr
[SPR_MQ
];
1100 env
->spr
[SPR_MQ
] = tmp
% T1
;
1101 T0
= tmp
/ (int32_t)T1
;
1105 void do_POWER_divo (void)
1109 if (((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== -1) || (int32_t)T1
== 0) {
1110 T0
= (long)((-1) * (T0
>> 31));
1111 env
->spr
[SPR_MQ
] = 0;
1115 tmp
= ((uint64_t)T0
<< 32) | env
->spr
[SPR_MQ
];
1116 env
->spr
[SPR_MQ
] = tmp
% T1
;
1118 if (tmp
> (int64_t)INT32_MAX
|| tmp
< (int64_t)INT32_MIN
) {
1128 void do_POWER_divs (void)
1130 if (((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== -1) || (int32_t)T1
== 0) {
1131 T0
= (long)((-1) * (T0
>> 31));
1132 env
->spr
[SPR_MQ
] = 0;
1134 env
->spr
[SPR_MQ
] = T0
% T1
;
1135 T0
= (int32_t)T0
/ (int32_t)T1
;
1139 void do_POWER_divso (void)
1141 if (((int32_t)T0
== INT32_MIN
&& (int32_t)T1
== -1) || (int32_t)T1
== 0) {
1142 T0
= (long)((-1) * (T0
>> 31));
1143 env
->spr
[SPR_MQ
] = 0;
1147 T0
= (int32_t)T0
/ (int32_t)T1
;
1148 env
->spr
[SPR_MQ
] = (int32_t)T0
% (int32_t)T1
;
1153 void do_POWER_dozo (void)
1155 if ((int32_t)T1
> (int32_t)T0
) {
1158 if (((uint32_t)(~T2
) ^ (uint32_t)T1
^ UINT32_MAX
) &
1159 ((uint32_t)(~T2
) ^ (uint32_t)T0
) & (1UL << 31)) {
1171 void do_POWER_maskg (void)
1175 if ((uint32_t)T0
== (uint32_t)(T1
+ 1)) {
1178 ret
= (((uint32_t)(-1)) >> ((uint32_t)T0
)) ^
1179 (((uint32_t)(-1) >> ((uint32_t)T1
)) >> 1);
1180 if ((uint32_t)T0
> (uint32_t)T1
)
1186 void do_POWER_mulo (void)
1190 tmp
= (uint64_t)T0
* (uint64_t)T1
;
1191 env
->spr
[SPR_MQ
] = tmp
>> 32;
1193 if (tmp
>> 32 != ((uint64_t)T0
>> 16) * ((uint64_t)T1
>> 16)) {
1201 #if !defined (CONFIG_USER_ONLY)
1202 void do_POWER_rac (void)
1207 /* We don't have to generate many instances of this instruction,
1208 * as rac is supervisor only.
1210 if (get_physical_address(env
, &ctx
, T0
, 0, ACCESS_INT
, 1) == 0)
1215 void do_POWER_rfsvc (void)
1217 env
->nip
= env
->lr
& ~0x00000003UL
;
1218 T0
= env
->ctr
& 0x0000FFFFUL
;
1219 do_store_msr(env
, T0
);
1220 #if defined (DEBUG_OP)
1221 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
1223 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1226 /* PowerPC 601 BAT management helper */
1227 void do_store_601_batu (int nr
)
1229 do_store_ibatu(env
, nr
, (uint32_t)T0
);
1230 env
->DBAT
[0][nr
] = env
->IBAT
[0][nr
];
1231 env
->DBAT
[1][nr
] = env
->IBAT
[1][nr
];
1235 /*****************************************************************************/
1236 /* 602 specific instructions */
1237 /* mfrom is the most crazy instruction ever seen, imho ! */
1238 /* Real implementation uses a ROM table. Do the same */
1239 #define USE_MFROM_ROM_TABLE
1240 void do_op_602_mfrom (void)
1242 if (likely(T0
< 602)) {
1243 #if defined(USE_MFROM_ROM_TABLE)
1244 #include "mfrom_table.c"
1245 T0
= mfrom_ROM_table
[T0
];
1248 /* Extremly decomposed:
1250 * T0 = 256 * log10(10 + 1.0) + 0.5
1253 d
= float64_div(d
, 256, &env
->fp_status
);
1255 d
= exp10(d
); // XXX: use float emulation function
1256 d
= float64_add(d
, 1.0, &env
->fp_status
);
1257 d
= log10(d
); // XXX: use float emulation function
1258 d
= float64_mul(d
, 256, &env
->fp_status
);
1259 d
= float64_add(d
, 0.5, &env
->fp_status
);
1260 T0
= float64_round_to_int(d
, &env
->fp_status
);
1267 /*****************************************************************************/
1268 /* Embedded PowerPC specific helpers */
1269 void do_405_check_ov (void)
1271 if (likely((((uint32_t)T1
^ (uint32_t)T2
) >> 31) ||
1272 !(((uint32_t)T0
^ (uint32_t)T2
) >> 31))) {
1280 void do_405_check_sat (void)
1282 if (!likely((((uint32_t)T1
^ (uint32_t)T2
) >> 31) ||
1283 !(((uint32_t)T0
^ (uint32_t)T2
) >> 31))) {
1284 /* Saturate result */
1293 /* XXX: to be improved to check access rights when in user-mode */
1294 void do_load_dcr (void)
1298 if (unlikely(env
->dcr_env
== NULL
)) {
1299 if (loglevel
!= 0) {
1300 fprintf(logfile
, "No DCR environment\n");
1302 do_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1303 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_INVAL
);
1304 } else if (unlikely(ppc_dcr_read(env
->dcr_env
, T0
, &val
) != 0)) {
1305 if (loglevel
!= 0) {
1306 fprintf(logfile
, "DCR read error %d %03x\n", (int)T0
, (int)T0
);
1308 do_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1309 POWERPC_EXCP_INVAL
| POWERPC_EXCP_PRIV_REG
);
1315 void do_store_dcr (void)
1317 if (unlikely(env
->dcr_env
== NULL
)) {
1318 if (loglevel
!= 0) {
1319 fprintf(logfile
, "No DCR environment\n");
1321 do_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1322 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_INVAL
);
1323 } else if (unlikely(ppc_dcr_write(env
->dcr_env
, T0
, T1
) != 0)) {
1324 if (loglevel
!= 0) {
1325 fprintf(logfile
, "DCR write error %d %03x\n", (int)T0
, (int)T0
);
1327 do_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1328 POWERPC_EXCP_INVAL
| POWERPC_EXCP_PRIV_REG
);
1332 #if !defined(CONFIG_USER_ONLY)
1333 void do_40x_rfci (void)
1335 env
->nip
= env
->spr
[SPR_40x_SRR2
];
1336 do_store_msr(env
, env
->spr
[SPR_40x_SRR3
] & ~0xFFFF0000);
1337 #if defined (DEBUG_OP)
1338 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
1340 env
->interrupt_request
= CPU_INTERRUPT_EXITTB
;
1345 #if defined(TARGET_PPC64)
1346 if (env
->spr
[SPR_BOOKE_CSRR1
] & (1 << MSR_CM
)) {
1347 env
->nip
= (uint64_t)env
->spr
[SPR_BOOKE_CSRR0
];
1351 env
->nip
= (uint32_t)env
->spr
[SPR_BOOKE_CSRR0
];
1353 do_store_msr(env
, (uint32_t)env
->spr
[SPR_BOOKE_CSRR1
] & ~0x3FFF0000);
1354 #if defined (DEBUG_OP)
1355 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
1357 env
->interrupt_request
= CPU_INTERRUPT_EXITTB
;
1362 #if defined(TARGET_PPC64)
1363 if (env
->spr
[SPR_BOOKE_DSRR1
] & (1 << MSR_CM
)) {
1364 env
->nip
= (uint64_t)env
->spr
[SPR_BOOKE_DSRR0
];
1368 env
->nip
= (uint32_t)env
->spr
[SPR_BOOKE_DSRR0
];
1370 do_store_msr(env
, (uint32_t)env
->spr
[SPR_BOOKE_DSRR1
] & ~0x3FFF0000);
1371 #if defined (DEBUG_OP)
1372 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
1374 env
->interrupt_request
= CPU_INTERRUPT_EXITTB
;
1377 void do_rfmci (void)
1379 #if defined(TARGET_PPC64)
1380 if (env
->spr
[SPR_BOOKE_MCSRR1
] & (1 << MSR_CM
)) {
1381 env
->nip
= (uint64_t)env
->spr
[SPR_BOOKE_MCSRR0
];
1385 env
->nip
= (uint32_t)env
->spr
[SPR_BOOKE_MCSRR0
];
1387 do_store_msr(env
, (uint32_t)env
->spr
[SPR_BOOKE_MCSRR1
] & ~0x3FFF0000);
1388 #if defined (DEBUG_OP)
1389 cpu_dump_rfi(env
->nip
, do_load_msr(env
));
1391 env
->interrupt_request
= CPU_INTERRUPT_EXITTB
;
1394 void do_load_403_pb (int num
)
1399 void do_store_403_pb (int num
)
1401 if (likely(env
->pb
[num
] != T0
)) {
1403 /* Should be optimized */
1410 void do_440_dlmzb (void)
1416 for (mask
= 0xFF000000; mask
!= 0; mask
= mask
>> 8) {
1417 if ((T0
& mask
) == 0)
1421 for (mask
= 0xFF000000; mask
!= 0; mask
= mask
>> 8) {
1422 if ((T1
& mask
) == 0)
1430 #if defined(TARGET_PPCEMB)
1431 /* SPE extension helpers */
1432 /* Use a table to make this quicker */
1433 static uint8_t hbrev
[16] = {
1434 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1435 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1438 static always_inline
uint8_t byte_reverse (uint8_t val
)
1440 return hbrev
[val
>> 4] | (hbrev
[val
& 0xF] << 4);
1443 static always_inline
uint32_t word_reverse (uint32_t val
)
1445 return byte_reverse(val
>> 24) | (byte_reverse(val
>> 16) << 8) |
1446 (byte_reverse(val
>> 8) << 16) | (byte_reverse(val
) << 24);
1449 #define MASKBITS 16 // Random value - to be fixed
1450 void do_brinc (void)
1452 uint32_t a
, b
, d
, mask
;
1454 mask
= (uint32_t)(-1UL) >> MASKBITS
;
1457 d
= word_reverse(1 + word_reverse(a
| ~mask
));
1458 T0_64
= (T0_64
& ~mask
) | (d
& mask
);
1461 #define DO_SPE_OP2(name) \
1462 void do_ev##name (void) \
1464 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1465 (uint64_t)_do_e##name(T0_64, T1_64); \
1468 #define DO_SPE_OP1(name) \
1469 void do_ev##name (void) \
1471 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1472 (uint64_t)_do_e##name(T0_64); \
1475 /* Fixed-point vector arithmetic */
1476 static always_inline
uint32_t _do_eabs (uint32_t val
)
1478 if (val
!= 0x80000000)
1484 static always_inline
uint32_t _do_eaddw (uint32_t op1
, uint32_t op2
)
1489 static always_inline
int _do_ecntlsw (uint32_t val
)
1491 if (val
& 0x80000000)
1492 return _do_cntlzw(~val
);
1494 return _do_cntlzw(val
);
1497 static always_inline
int _do_ecntlzw (uint32_t val
)
1499 return _do_cntlzw(val
);
1502 static always_inline
uint32_t _do_eneg (uint32_t val
)
1504 if (val
!= 0x80000000)
1510 static always_inline
uint32_t _do_erlw (uint32_t op1
, uint32_t op2
)
1512 return rotl32(op1
, op2
);
1515 static always_inline
uint32_t _do_erndw (uint32_t val
)
1517 return (val
+ 0x000080000000) & 0xFFFF0000;
1520 static always_inline
uint32_t _do_eslw (uint32_t op1
, uint32_t op2
)
1522 /* No error here: 6 bits are used */
1523 return op1
<< (op2
& 0x3F);
1526 static always_inline
int32_t _do_esrws (int32_t op1
, uint32_t op2
)
1528 /* No error here: 6 bits are used */
1529 return op1
>> (op2
& 0x3F);
1532 static always_inline
uint32_t _do_esrwu (uint32_t op1
, uint32_t op2
)
1534 /* No error here: 6 bits are used */
1535 return op1
>> (op2
& 0x3F);
1538 static always_inline
uint32_t _do_esubfw (uint32_t op1
, uint32_t op2
)
1566 /* evsel is a little bit more complicated... */
1567 static always_inline
uint32_t _do_esel (uint32_t op1
, uint32_t op2
, int n
)
1575 void do_evsel (void)
1577 T0_64
= ((uint64_t)_do_esel(T0_64
>> 32, T1_64
>> 32, T0
>> 3) << 32) |
1578 (uint64_t)_do_esel(T0_64
, T1_64
, (T0
>> 2) & 1);
1581 /* Fixed-point vector comparisons */
1582 #define DO_SPE_CMP(name) \
1583 void do_ev##name (void) \
1585 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
1586 T1_64 >> 32) << 32, \
1587 _do_e##name(T0_64, T1_64)); \
1590 static always_inline
uint32_t _do_evcmp_merge (int t0
, int t1
)
1592 return (t0
<< 3) | (t1
<< 2) | ((t0
| t1
) << 1) | (t0
& t1
);
1594 static always_inline
int _do_ecmpeq (uint32_t op1
, uint32_t op2
)
1596 return op1
== op2
? 1 : 0;
1599 static always_inline
int _do_ecmpgts (int32_t op1
, int32_t op2
)
1601 return op1
> op2
? 1 : 0;
1604 static always_inline
int _do_ecmpgtu (uint32_t op1
, uint32_t op2
)
1606 return op1
> op2
? 1 : 0;
1609 static always_inline
int _do_ecmplts (int32_t op1
, int32_t op2
)
1611 return op1
< op2
? 1 : 0;
1614 static always_inline
int _do_ecmpltu (uint32_t op1
, uint32_t op2
)
1616 return op1
< op2
? 1 : 0;
1630 /* Single precision floating-point conversions from/to integer */
1631 static always_inline
uint32_t _do_efscfsi (int32_t val
)
1638 u
.f
= int32_to_float32(val
, &env
->spe_status
);
1643 static always_inline
uint32_t _do_efscfui (uint32_t val
)
1650 u
.f
= uint32_to_float32(val
, &env
->spe_status
);
1655 static always_inline
int32_t _do_efsctsi (uint32_t val
)
1663 /* NaN are not treated the same way IEEE 754 does */
1664 if (unlikely(isnan(u
.f
)))
1667 return float32_to_int32(u
.f
, &env
->spe_status
);
1670 static always_inline
uint32_t _do_efsctui (uint32_t val
)
1678 /* NaN are not treated the same way IEEE 754 does */
1679 if (unlikely(isnan(u
.f
)))
1682 return float32_to_uint32(u
.f
, &env
->spe_status
);
1685 static always_inline
int32_t _do_efsctsiz (uint32_t val
)
1693 /* NaN are not treated the same way IEEE 754 does */
1694 if (unlikely(isnan(u
.f
)))
1697 return float32_to_int32_round_to_zero(u
.f
, &env
->spe_status
);
1700 static always_inline
uint32_t _do_efsctuiz (uint32_t val
)
1708 /* NaN are not treated the same way IEEE 754 does */
1709 if (unlikely(isnan(u
.f
)))
1712 return float32_to_uint32_round_to_zero(u
.f
, &env
->spe_status
);
1715 void do_efscfsi (void)
1717 T0_64
= _do_efscfsi(T0_64
);
1720 void do_efscfui (void)
1722 T0_64
= _do_efscfui(T0_64
);
1725 void do_efsctsi (void)
1727 T0_64
= _do_efsctsi(T0_64
);
1730 void do_efsctui (void)
1732 T0_64
= _do_efsctui(T0_64
);
1735 void do_efsctsiz (void)
1737 T0_64
= _do_efsctsiz(T0_64
);
1740 void do_efsctuiz (void)
1742 T0_64
= _do_efsctuiz(T0_64
);
1745 /* Single precision floating-point conversion to/from fractional */
1746 static always_inline
uint32_t _do_efscfsf (uint32_t val
)
1754 u
.f
= int32_to_float32(val
, &env
->spe_status
);
1755 tmp
= int64_to_float32(1ULL << 32, &env
->spe_status
);
1756 u
.f
= float32_div(u
.f
, tmp
, &env
->spe_status
);
1761 static always_inline
uint32_t _do_efscfuf (uint32_t val
)
1769 u
.f
= uint32_to_float32(val
, &env
->spe_status
);
1770 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1771 u
.f
= float32_div(u
.f
, tmp
, &env
->spe_status
);
1776 static always_inline
int32_t _do_efsctsf (uint32_t val
)
1785 /* NaN are not treated the same way IEEE 754 does */
1786 if (unlikely(isnan(u
.f
)))
1788 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1789 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
1791 return float32_to_int32(u
.f
, &env
->spe_status
);
1794 static always_inline
uint32_t _do_efsctuf (uint32_t val
)
1803 /* NaN are not treated the same way IEEE 754 does */
1804 if (unlikely(isnan(u
.f
)))
1806 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1807 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
1809 return float32_to_uint32(u
.f
, &env
->spe_status
);
1812 static always_inline
int32_t _do_efsctsfz (uint32_t val
)
1821 /* NaN are not treated the same way IEEE 754 does */
1822 if (unlikely(isnan(u
.f
)))
1824 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1825 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
1827 return float32_to_int32_round_to_zero(u
.f
, &env
->spe_status
);
1830 static always_inline
uint32_t _do_efsctufz (uint32_t val
)
1839 /* NaN are not treated the same way IEEE 754 does */
1840 if (unlikely(isnan(u
.f
)))
1842 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
1843 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
1845 return float32_to_uint32_round_to_zero(u
.f
, &env
->spe_status
);
1848 void do_efscfsf (void)
1850 T0_64
= _do_efscfsf(T0_64
);
1853 void do_efscfuf (void)
1855 T0_64
= _do_efscfuf(T0_64
);
1858 void do_efsctsf (void)
1860 T0_64
= _do_efsctsf(T0_64
);
1863 void do_efsctuf (void)
1865 T0_64
= _do_efsctuf(T0_64
);
1868 void do_efsctsfz (void)
1870 T0_64
= _do_efsctsfz(T0_64
);
1873 void do_efsctufz (void)
1875 T0_64
= _do_efsctufz(T0_64
);
1878 /* Double precision floating point helpers */
1879 static always_inline
int _do_efdcmplt (uint64_t op1
, uint64_t op2
)
1881 /* XXX: TODO: test special values (NaN, infinites, ...) */
1882 return _do_efdtstlt(op1
, op2
);
1885 static always_inline
int _do_efdcmpgt (uint64_t op1
, uint64_t op2
)
1887 /* XXX: TODO: test special values (NaN, infinites, ...) */
1888 return _do_efdtstgt(op1
, op2
);
1891 static always_inline
int _do_efdcmpeq (uint64_t op1
, uint64_t op2
)
1893 /* XXX: TODO: test special values (NaN, infinites, ...) */
1894 return _do_efdtsteq(op1
, op2
);
1897 void do_efdcmplt (void)
1899 T0
= _do_efdcmplt(T0_64
, T1_64
);
1902 void do_efdcmpgt (void)
1904 T0
= _do_efdcmpgt(T0_64
, T1_64
);
1907 void do_efdcmpeq (void)
1909 T0
= _do_efdcmpeq(T0_64
, T1_64
);
1912 /* Double precision floating-point conversion to/from integer */
1913 static always_inline
uint64_t _do_efdcfsi (int64_t val
)
1920 u
.f
= int64_to_float64(val
, &env
->spe_status
);
1925 static always_inline
uint64_t _do_efdcfui (uint64_t val
)
1932 u
.f
= uint64_to_float64(val
, &env
->spe_status
);
1937 static always_inline
int64_t _do_efdctsi (uint64_t val
)
1945 /* NaN are not treated the same way IEEE 754 does */
1946 if (unlikely(isnan(u
.f
)))
1949 return float64_to_int64(u
.f
, &env
->spe_status
);
1952 static always_inline
uint64_t _do_efdctui (uint64_t val
)
1960 /* NaN are not treated the same way IEEE 754 does */
1961 if (unlikely(isnan(u
.f
)))
1964 return float64_to_uint64(u
.f
, &env
->spe_status
);
1967 static always_inline
int64_t _do_efdctsiz (uint64_t val
)
1975 /* NaN are not treated the same way IEEE 754 does */
1976 if (unlikely(isnan(u
.f
)))
1979 return float64_to_int64_round_to_zero(u
.f
, &env
->spe_status
);
1982 static always_inline
uint64_t _do_efdctuiz (uint64_t val
)
1990 /* NaN are not treated the same way IEEE 754 does */
1991 if (unlikely(isnan(u
.f
)))
1994 return float64_to_uint64_round_to_zero(u
.f
, &env
->spe_status
);
1997 void do_efdcfsi (void)
1999 T0_64
= _do_efdcfsi(T0_64
);
2002 void do_efdcfui (void)
2004 T0_64
= _do_efdcfui(T0_64
);
2007 void do_efdctsi (void)
2009 T0_64
= _do_efdctsi(T0_64
);
2012 void do_efdctui (void)
2014 T0_64
= _do_efdctui(T0_64
);
2017 void do_efdctsiz (void)
2019 T0_64
= _do_efdctsiz(T0_64
);
2022 void do_efdctuiz (void)
2024 T0_64
= _do_efdctuiz(T0_64
);
2027 /* Double precision floating-point conversion to/from fractional */
2028 static always_inline
uint64_t _do_efdcfsf (int64_t val
)
2036 u
.f
= int32_to_float64(val
, &env
->spe_status
);
2037 tmp
= int64_to_float64(1ULL << 32, &env
->spe_status
);
2038 u
.f
= float64_div(u
.f
, tmp
, &env
->spe_status
);
2043 static always_inline
uint64_t _do_efdcfuf (uint64_t val
)
2051 u
.f
= uint32_to_float64(val
, &env
->spe_status
);
2052 tmp
= int64_to_float64(1ULL << 32, &env
->spe_status
);
2053 u
.f
= float64_div(u
.f
, tmp
, &env
->spe_status
);
2058 static always_inline
int64_t _do_efdctsf (uint64_t val
)
2067 /* NaN are not treated the same way IEEE 754 does */
2068 if (unlikely(isnan(u
.f
)))
2070 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2071 u
.f
= float64_mul(u
.f
, tmp
, &env
->spe_status
);
2073 return float64_to_int32(u
.f
, &env
->spe_status
);
2076 static always_inline
uint64_t _do_efdctuf (uint64_t val
)
2085 /* NaN are not treated the same way IEEE 754 does */
2086 if (unlikely(isnan(u
.f
)))
2088 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2089 u
.f
= float64_mul(u
.f
, tmp
, &env
->spe_status
);
2091 return float64_to_uint32(u
.f
, &env
->spe_status
);
2094 static always_inline
int64_t _do_efdctsfz (uint64_t val
)
2103 /* NaN are not treated the same way IEEE 754 does */
2104 if (unlikely(isnan(u
.f
)))
2106 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2107 u
.f
= float64_mul(u
.f
, tmp
, &env
->spe_status
);
2109 return float64_to_int32_round_to_zero(u
.f
, &env
->spe_status
);
2112 static always_inline
uint64_t _do_efdctufz (uint64_t val
)
2121 /* NaN are not treated the same way IEEE 754 does */
2122 if (unlikely(isnan(u
.f
)))
2124 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2125 u
.f
= float64_mul(u
.f
, tmp
, &env
->spe_status
);
2127 return float64_to_uint32_round_to_zero(u
.f
, &env
->spe_status
);
2130 void do_efdcfsf (void)
2132 T0_64
= _do_efdcfsf(T0_64
);
2135 void do_efdcfuf (void)
2137 T0_64
= _do_efdcfuf(T0_64
);
2140 void do_efdctsf (void)
2142 T0_64
= _do_efdctsf(T0_64
);
2145 void do_efdctuf (void)
2147 T0_64
= _do_efdctuf(T0_64
);
2150 void do_efdctsfz (void)
2152 T0_64
= _do_efdctsfz(T0_64
);
2155 void do_efdctufz (void)
2157 T0_64
= _do_efdctufz(T0_64
);
2160 /* Floating point conversion between single and double precision */
2161 static always_inline
uint32_t _do_efscfd (uint64_t val
)
2173 u2
.f
= float64_to_float32(u1
.f
, &env
->spe_status
);
2178 static always_inline
uint64_t _do_efdcfs (uint32_t val
)
2190 u2
.f
= float32_to_float64(u1
.f
, &env
->spe_status
);
2195 void do_efscfd (void)
2197 T0_64
= _do_efscfd(T0_64
);
2200 void do_efdcfs (void)
2202 T0_64
= _do_efdcfs(T0_64
);
2205 /* Single precision fixed-point vector arithmetic */
2221 /* Single-precision floating-point comparisons */
2222 static always_inline
int _do_efscmplt (uint32_t op1
, uint32_t op2
)
2224 /* XXX: TODO: test special values (NaN, infinites, ...) */
2225 return _do_efststlt(op1
, op2
);
2228 static always_inline
int _do_efscmpgt (uint32_t op1
, uint32_t op2
)
2230 /* XXX: TODO: test special values (NaN, infinites, ...) */
2231 return _do_efststgt(op1
, op2
);
2234 static always_inline
int _do_efscmpeq (uint32_t op1
, uint32_t op2
)
2236 /* XXX: TODO: test special values (NaN, infinites, ...) */
2237 return _do_efststeq(op1
, op2
);
2240 void do_efscmplt (void)
2242 T0
= _do_efscmplt(T0_64
, T1_64
);
2245 void do_efscmpgt (void)
2247 T0
= _do_efscmpgt(T0_64
, T1_64
);
2250 void do_efscmpeq (void)
2252 T0
= _do_efscmpeq(T0_64
, T1_64
);
2255 /* Single-precision floating-point vector comparisons */
2257 DO_SPE_CMP(fscmplt
);
2259 DO_SPE_CMP(fscmpgt
);
2261 DO_SPE_CMP(fscmpeq
);
2263 DO_SPE_CMP(fststlt
);
2265 DO_SPE_CMP(fststgt
);
2267 DO_SPE_CMP(fststeq
);
2269 /* Single-precision floating-point vector conversions */
2283 DO_SPE_OP1(fsctsiz
);
2285 DO_SPE_OP1(fsctuiz
);
2290 #endif /* defined(TARGET_PPCEMB) */
2292 /*****************************************************************************/
2293 /* Softmmu support */
2294 #if !defined (CONFIG_USER_ONLY)
2296 #define MMUSUFFIX _mmu
2297 #define GETPC() (__builtin_return_address(0))
2300 #include "softmmu_template.h"
2303 #include "softmmu_template.h"
2306 #include "softmmu_template.h"
2309 #include "softmmu_template.h"
2311 /* try to fill the TLB and return an exception if error. If retaddr is
2312 NULL, it means that the function was called in C code (i.e. not
2313 from generated code or from helper.c) */
2314 /* XXX: fix it to restore all registers */
2315 void tlb_fill (target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
2317 TranslationBlock
*tb
;
2318 CPUState
*saved_env
;
2319 target_phys_addr_t pc
;
2322 /* XXX: hack to restore env in all cases, even if not called from
2325 env
= cpu_single_env
;
2326 ret
= cpu_ppc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
2327 if (unlikely(ret
!= 0)) {
2328 if (likely(retaddr
)) {
2329 /* now we have a real cpu fault */
2330 pc
= (target_phys_addr_t
)(unsigned long)retaddr
;
2331 tb
= tb_find_pc(pc
);
2333 /* the PC is inside the translated code. It means that we have
2334 a virtual CPU fault */
2335 cpu_restore_state(tb
, env
, pc
, NULL
);
2338 do_raise_exception_err(env
->exception_index
, env
->error_code
);
2343 /* Software driven TLBs management */
2344 /* PowerPC 602/603 software TLB load instructions helpers */
2345 void do_load_6xx_tlb (int is_code
)
2347 target_ulong RPN
, CMP
, EPN
;
2350 RPN
= env
->spr
[SPR_RPA
];
2352 CMP
= env
->spr
[SPR_ICMP
];
2353 EPN
= env
->spr
[SPR_IMISS
];
2355 CMP
= env
->spr
[SPR_DCMP
];
2356 EPN
= env
->spr
[SPR_DMISS
];
2358 way
= (env
->spr
[SPR_SRR1
] >> 17) & 1;
2359 #if defined (DEBUG_SOFTWARE_TLB)
2360 if (loglevel
!= 0) {
2361 fprintf(logfile
, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2362 __func__
, (unsigned long)T0
, (unsigned long)EPN
,
2363 (unsigned long)CMP
, (unsigned long)RPN
, way
);
2366 /* Store this TLB */
2367 ppc6xx_tlb_store(env
, (uint32_t)(T0
& TARGET_PAGE_MASK
),
2368 way
, is_code
, CMP
, RPN
);
2371 void do_load_74xx_tlb (int is_code
)
2373 target_ulong RPN
, CMP
, EPN
;
2376 RPN
= env
->spr
[SPR_PTELO
];
2377 CMP
= env
->spr
[SPR_PTEHI
];
2378 EPN
= env
->spr
[SPR_TLBMISS
] & ~0x3;
2379 way
= env
->spr
[SPR_TLBMISS
] & 0x3;
2380 #if defined (DEBUG_SOFTWARE_TLB)
2381 if (loglevel
!= 0) {
2382 fprintf(logfile
, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
2383 __func__
, (unsigned long)T0
, (unsigned long)EPN
,
2384 (unsigned long)CMP
, (unsigned long)RPN
, way
);
2387 /* Store this TLB */
2388 ppc6xx_tlb_store(env
, (uint32_t)(T0
& TARGET_PAGE_MASK
),
2389 way
, is_code
, CMP
, RPN
);
2392 static target_ulong
booke_tlb_to_page_size (int size
)
2394 return 1024 << (2 * size
);
2397 static int booke_page_size_to_tlb (target_ulong page_size
)
2401 switch (page_size
) {
2435 #if defined (TARGET_PPC64)
2436 case 0x000100000000ULL
:
2439 case 0x000400000000ULL
:
2442 case 0x001000000000ULL
:
2445 case 0x004000000000ULL
:
2448 case 0x010000000000ULL
:
2460 /* Helpers for 4xx TLB management */
2461 void do_4xx_tlbre_lo (void)
2467 tlb
= &env
->tlb
[T0
].tlbe
;
2469 if (tlb
->prot
& PAGE_VALID
)
2471 size
= booke_page_size_to_tlb(tlb
->size
);
2472 if (size
< 0 || size
> 0x7)
2475 env
->spr
[SPR_40x_PID
] = tlb
->PID
;
2478 void do_4xx_tlbre_hi (void)
2483 tlb
= &env
->tlb
[T0
].tlbe
;
2485 if (tlb
->prot
& PAGE_EXEC
)
2487 if (tlb
->prot
& PAGE_WRITE
)
2491 void do_4xx_tlbwe_hi (void)
2494 target_ulong page
, end
;
2496 #if defined (DEBUG_SOFTWARE_TLB)
2497 if (loglevel
!= 0) {
2498 fprintf(logfile
, "%s T0 " REGX
" T1 " REGX
"\n", __func__
, T0
, T1
);
2502 tlb
= &env
->tlb
[T0
].tlbe
;
2503 /* Invalidate previous TLB (if it's valid) */
2504 if (tlb
->prot
& PAGE_VALID
) {
2505 end
= tlb
->EPN
+ tlb
->size
;
2506 #if defined (DEBUG_SOFTWARE_TLB)
2507 if (loglevel
!= 0) {
2508 fprintf(logfile
, "%s: invalidate old TLB %d start " ADDRX
2509 " end " ADDRX
"\n", __func__
, (int)T0
, tlb
->EPN
, end
);
2512 for (page
= tlb
->EPN
; page
< end
; page
+= TARGET_PAGE_SIZE
)
2513 tlb_flush_page(env
, page
);
2515 tlb
->size
= booke_tlb_to_page_size((T1
>> 7) & 0x7);
2516 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2517 * If this ever occurs, one should use the ppcemb target instead
2518 * of the ppc or ppc64 one
2520 if ((T1
& 0x40) && tlb
->size
< TARGET_PAGE_SIZE
) {
2521 cpu_abort(env
, "TLB size " TARGET_FMT_lu
" < %u "
2522 "are not supported (%d)\n",
2523 tlb
->size
, TARGET_PAGE_SIZE
, (int)((T1
>> 7) & 0x7));
2525 tlb
->EPN
= T1
& ~(tlb
->size
- 1);
2527 tlb
->prot
|= PAGE_VALID
;
2529 tlb
->prot
&= ~PAGE_VALID
;
2531 /* XXX: TO BE FIXED */
2532 cpu_abort(env
, "Little-endian TLB entries are not supported by now\n");
2534 tlb
->PID
= env
->spr
[SPR_40x_PID
]; /* PID */
2535 tlb
->attr
= T1
& 0xFF;
2536 #if defined (DEBUG_SOFTWARE_TLB)
2537 if (loglevel
!= 0) {
2538 fprintf(logfile
, "%s: set up TLB %d RPN " PADDRX
" EPN " ADDRX
2539 " size " ADDRX
" prot %c%c%c%c PID %d\n", __func__
,
2540 (int)T0
, tlb
->RPN
, tlb
->EPN
, tlb
->size
,
2541 tlb
->prot
& PAGE_READ
? 'r' : '-',
2542 tlb
->prot
& PAGE_WRITE
? 'w' : '-',
2543 tlb
->prot
& PAGE_EXEC
? 'x' : '-',
2544 tlb
->prot
& PAGE_VALID
? 'v' : '-', (int)tlb
->PID
);
2547 /* Invalidate new TLB (if valid) */
2548 if (tlb
->prot
& PAGE_VALID
) {
2549 end
= tlb
->EPN
+ tlb
->size
;
2550 #if defined (DEBUG_SOFTWARE_TLB)
2551 if (loglevel
!= 0) {
2552 fprintf(logfile
, "%s: invalidate TLB %d start " ADDRX
2553 " end " ADDRX
"\n", __func__
, (int)T0
, tlb
->EPN
, end
);
2556 for (page
= tlb
->EPN
; page
< end
; page
+= TARGET_PAGE_SIZE
)
2557 tlb_flush_page(env
, page
);
2561 void do_4xx_tlbwe_lo (void)
2565 #if defined (DEBUG_SOFTWARE_TLB)
2566 if (loglevel
!= 0) {
2567 fprintf(logfile
, "%s T0 " REGX
" T1 " REGX
"\n", __func__
, T0
, T1
);
2571 tlb
= &env
->tlb
[T0
].tlbe
;
2572 tlb
->RPN
= T1
& 0xFFFFFC00;
2573 tlb
->prot
= PAGE_READ
;
2575 tlb
->prot
|= PAGE_EXEC
;
2577 tlb
->prot
|= PAGE_WRITE
;
2578 #if defined (DEBUG_SOFTWARE_TLB)
2579 if (loglevel
!= 0) {
2580 fprintf(logfile
, "%s: set up TLB %d RPN " PADDRX
" EPN " ADDRX
2581 " size " ADDRX
" prot %c%c%c%c PID %d\n", __func__
,
2582 (int)T0
, tlb
->RPN
, tlb
->EPN
, tlb
->size
,
2583 tlb
->prot
& PAGE_READ
? 'r' : '-',
2584 tlb
->prot
& PAGE_WRITE
? 'w' : '-',
2585 tlb
->prot
& PAGE_EXEC
? 'x' : '-',
2586 tlb
->prot
& PAGE_VALID
? 'v' : '-', (int)tlb
->PID
);
2591 /* PowerPC 440 TLB management */
2592 void do_440_tlbwe (int word
)
2595 target_ulong EPN
, RPN
, size
;
2598 #if defined (DEBUG_SOFTWARE_TLB)
2599 if (loglevel
!= 0) {
2600 fprintf(logfile
, "%s word %d T0 " REGX
" T1 " REGX
"\n",
2601 __func__
, word
, T0
, T1
);
2606 tlb
= &env
->tlb
[T0
].tlbe
;
2609 /* Just here to please gcc */
2611 EPN
= T1
& 0xFFFFFC00;
2612 if ((tlb
->prot
& PAGE_VALID
) && EPN
!= tlb
->EPN
)
2615 size
= booke_tlb_to_page_size((T1
>> 4) & 0xF);
2616 if ((tlb
->prot
& PAGE_VALID
) && tlb
->size
< size
)
2620 tlb
->attr
|= (T1
>> 8) & 1;
2622 tlb
->prot
|= PAGE_VALID
;
2624 if (tlb
->prot
& PAGE_VALID
) {
2625 tlb
->prot
&= ~PAGE_VALID
;
2629 tlb
->PID
= env
->spr
[SPR_440_MMUCR
] & 0x000000FF;
2634 RPN
= T1
& 0xFFFFFC0F;
2635 if ((tlb
->prot
& PAGE_VALID
) && tlb
->RPN
!= RPN
)
2640 tlb
->attr
= (tlb
->attr
& 0x1) | (T1
& 0x0000FF00);
2641 tlb
->prot
= tlb
->prot
& PAGE_VALID
;
2643 tlb
->prot
|= PAGE_READ
<< 4;
2645 tlb
->prot
|= PAGE_WRITE
<< 4;
2647 tlb
->prot
|= PAGE_EXEC
<< 4;
2649 tlb
->prot
|= PAGE_READ
;
2651 tlb
->prot
|= PAGE_WRITE
;
2653 tlb
->prot
|= PAGE_EXEC
;
2658 void do_440_tlbre (int word
)
2664 tlb
= &env
->tlb
[T0
].tlbe
;
2667 /* Just here to please gcc */
2670 size
= booke_page_size_to_tlb(tlb
->size
);
2671 if (size
< 0 || size
> 0xF)
2674 if (tlb
->attr
& 0x1)
2676 if (tlb
->prot
& PAGE_VALID
)
2678 env
->spr
[SPR_440_MMUCR
] &= ~0x000000FF;
2679 env
->spr
[SPR_440_MMUCR
] |= tlb
->PID
;
2685 T0
= tlb
->attr
& ~0x1;
2686 if (tlb
->prot
& (PAGE_READ
<< 4))
2688 if (tlb
->prot
& (PAGE_WRITE
<< 4))
2690 if (tlb
->prot
& (PAGE_EXEC
<< 4))
2692 if (tlb
->prot
& PAGE_READ
)
2694 if (tlb
->prot
& PAGE_WRITE
)
2696 if (tlb
->prot
& PAGE_EXEC
)
2701 #endif /* !CONFIG_USER_ONLY */