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target-ppc: fix compilation with CONFIG_SOFTFLOAT
[qemu.git] / target-ppc / op_helper.c
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "exec.h"
21 #include "host-utils.h"
22 #include "helper.h"
23
24 #include "helper_regs.h"
25
26 //#define DEBUG_OP
27 //#define DEBUG_EXCEPTIONS
28 //#define DEBUG_SOFTWARE_TLB
29
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
32
33 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
34 {
35 #if 0
36 printf("Raise exception %3x code : %d\n", exception, error_code);
37 #endif
38 env->exception_index = exception;
39 env->error_code = error_code;
40 cpu_loop_exit();
41 }
42
43 void helper_raise_exception (uint32_t exception)
44 {
45 helper_raise_exception_err(exception, 0);
46 }
47
48 /*****************************************************************************/
49 /* Registers load and stores */
50 target_ulong helper_load_cr (void)
51 {
52 return (env->crf[0] << 28) |
53 (env->crf[1] << 24) |
54 (env->crf[2] << 20) |
55 (env->crf[3] << 16) |
56 (env->crf[4] << 12) |
57 (env->crf[5] << 8) |
58 (env->crf[6] << 4) |
59 (env->crf[7] << 0);
60 }
61
62 void helper_store_cr (target_ulong val, uint32_t mask)
63 {
64 int i, sh;
65
66 for (i = 0, sh = 7; i < 8; i++, sh--) {
67 if (mask & (1 << sh))
68 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
69 }
70 }
71
72 /*****************************************************************************/
73 /* SPR accesses */
74 void helper_load_dump_spr (uint32_t sprn)
75 {
76 if (loglevel != 0) {
77 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
78 sprn, sprn, env->spr[sprn]);
79 }
80 }
81
82 void helper_store_dump_spr (uint32_t sprn)
83 {
84 if (loglevel != 0) {
85 fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
86 sprn, sprn, env->spr[sprn]);
87 }
88 }
89
90 target_ulong helper_load_tbl (void)
91 {
92 return cpu_ppc_load_tbl(env);
93 }
94
95 target_ulong helper_load_tbu (void)
96 {
97 return cpu_ppc_load_tbu(env);
98 }
99
100 target_ulong helper_load_atbl (void)
101 {
102 return cpu_ppc_load_atbl(env);
103 }
104
105 target_ulong helper_load_atbu (void)
106 {
107 return cpu_ppc_load_atbu(env);
108 }
109
110 target_ulong helper_load_601_rtcl (void)
111 {
112 return cpu_ppc601_load_rtcl(env);
113 }
114
115 target_ulong helper_load_601_rtcu (void)
116 {
117 return cpu_ppc601_load_rtcu(env);
118 }
119
120 #if !defined(CONFIG_USER_ONLY)
121 #if defined (TARGET_PPC64)
122 void helper_store_asr (target_ulong val)
123 {
124 ppc_store_asr(env, val);
125 }
126 #endif
127
128 void helper_store_sdr1 (target_ulong val)
129 {
130 ppc_store_sdr1(env, val);
131 }
132
133 void helper_store_tbl (target_ulong val)
134 {
135 cpu_ppc_store_tbl(env, val);
136 }
137
138 void helper_store_tbu (target_ulong val)
139 {
140 cpu_ppc_store_tbu(env, val);
141 }
142
143 void helper_store_atbl (target_ulong val)
144 {
145 cpu_ppc_store_atbl(env, val);
146 }
147
148 void helper_store_atbu (target_ulong val)
149 {
150 cpu_ppc_store_atbu(env, val);
151 }
152
153 void helper_store_601_rtcl (target_ulong val)
154 {
155 cpu_ppc601_store_rtcl(env, val);
156 }
157
158 void helper_store_601_rtcu (target_ulong val)
159 {
160 cpu_ppc601_store_rtcu(env, val);
161 }
162
163 target_ulong helper_load_decr (void)
164 {
165 return cpu_ppc_load_decr(env);
166 }
167
168 void helper_store_decr (target_ulong val)
169 {
170 cpu_ppc_store_decr(env, val);
171 }
172
173 void helper_store_hid0_601 (target_ulong val)
174 {
175 target_ulong hid0;
176
177 hid0 = env->spr[SPR_HID0];
178 if ((val ^ hid0) & 0x00000008) {
179 /* Change current endianness */
180 env->hflags &= ~(1 << MSR_LE);
181 env->hflags_nmsr &= ~(1 << MSR_LE);
182 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
183 env->hflags |= env->hflags_nmsr;
184 if (loglevel != 0) {
185 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
186 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
187 }
188 }
189 env->spr[SPR_HID0] = (uint32_t)val;
190 }
191
192 void helper_store_403_pbr (uint32_t num, target_ulong value)
193 {
194 if (likely(env->pb[num] != value)) {
195 env->pb[num] = value;
196 /* Should be optimized */
197 tlb_flush(env, 1);
198 }
199 }
200
201 target_ulong helper_load_40x_pit (void)
202 {
203 return load_40x_pit(env);
204 }
205
206 void helper_store_40x_pit (target_ulong val)
207 {
208 store_40x_pit(env, val);
209 }
210
211 void helper_store_40x_dbcr0 (target_ulong val)
212 {
213 store_40x_dbcr0(env, val);
214 }
215
216 void helper_store_40x_sler (target_ulong val)
217 {
218 store_40x_sler(env, val);
219 }
220
221 void helper_store_booke_tcr (target_ulong val)
222 {
223 store_booke_tcr(env, val);
224 }
225
226 void helper_store_booke_tsr (target_ulong val)
227 {
228 store_booke_tsr(env, val);
229 }
230
231 void helper_store_ibatu (uint32_t nr, target_ulong val)
232 {
233 ppc_store_ibatu(env, nr, val);
234 }
235
236 void helper_store_ibatl (uint32_t nr, target_ulong val)
237 {
238 ppc_store_ibatl(env, nr, val);
239 }
240
241 void helper_store_dbatu (uint32_t nr, target_ulong val)
242 {
243 ppc_store_dbatu(env, nr, val);
244 }
245
246 void helper_store_dbatl (uint32_t nr, target_ulong val)
247 {
248 ppc_store_dbatl(env, nr, val);
249 }
250
251 void helper_store_601_batl (uint32_t nr, target_ulong val)
252 {
253 ppc_store_ibatl_601(env, nr, val);
254 }
255
256 void helper_store_601_batu (uint32_t nr, target_ulong val)
257 {
258 ppc_store_ibatu_601(env, nr, val);
259 }
260 #endif
261
262 /*****************************************************************************/
263 /* Memory load and stores */
264
265 static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
266 {
267 #if defined(TARGET_PPC64)
268 if (!msr_sf)
269 return (uint32_t)(addr + arg);
270 else
271 #endif
272 return addr + arg;
273 }
274
275 void helper_lmw (target_ulong addr, uint32_t reg)
276 {
277 for (; reg < 32; reg++) {
278 if (msr_le)
279 env->gpr[reg] = bswap32(ldl(addr));
280 else
281 env->gpr[reg] = ldl(addr);
282 addr = addr_add(addr, 4);
283 }
284 }
285
286 void helper_stmw (target_ulong addr, uint32_t reg)
287 {
288 for (; reg < 32; reg++) {
289 if (msr_le)
290 stl(addr, bswap32((uint32_t)env->gpr[reg]));
291 else
292 stl(addr, (uint32_t)env->gpr[reg]);
293 addr = addr_add(addr, 4);
294 }
295 }
296
297 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
298 {
299 int sh;
300 for (; nb > 3; nb -= 4) {
301 env->gpr[reg] = ldl(addr);
302 reg = (reg + 1) % 32;
303 addr = addr_add(addr, 4);
304 }
305 if (unlikely(nb > 0)) {
306 env->gpr[reg] = 0;
307 for (sh = 24; nb > 0; nb--, sh -= 8) {
308 env->gpr[reg] |= ldub(addr) << sh;
309 addr = addr_add(addr, 1);
310 }
311 }
312 }
313 /* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
317 */
318 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
319 {
320 if (likely(xer_bc != 0)) {
321 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
322 (reg < rb && (reg + xer_bc) > rb))) {
323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
324 POWERPC_EXCP_INVAL |
325 POWERPC_EXCP_INVAL_LSWX);
326 } else {
327 helper_lsw(addr, xer_bc, reg);
328 }
329 }
330 }
331
332 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
333 {
334 int sh;
335 for (; nb > 3; nb -= 4) {
336 stl(addr, env->gpr[reg]);
337 reg = (reg + 1) % 32;
338 addr = addr_add(addr, 4);
339 }
340 if (unlikely(nb > 0)) {
341 for (sh = 24; nb > 0; nb--, sh -= 8)
342 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
343 addr = addr_add(addr, 1);
344 }
345 }
346
347 static void do_dcbz(target_ulong addr, int dcache_line_size)
348 {
349 addr &= ~(dcache_line_size - 1);
350 int i;
351 for (i = 0 ; i < dcache_line_size ; i += 4) {
352 stl(addr + i , 0);
353 }
354 if (env->reserve == addr)
355 env->reserve = (target_ulong)-1ULL;
356 }
357
358 void helper_dcbz(target_ulong addr)
359 {
360 do_dcbz(addr, env->dcache_line_size);
361 }
362
363 void helper_dcbz_970(target_ulong addr)
364 {
365 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
366 do_dcbz(addr, 32);
367 else
368 do_dcbz(addr, env->dcache_line_size);
369 }
370
371 void helper_icbi(target_ulong addr)
372 {
373 uint32_t tmp;
374
375 addr &= ~(env->dcache_line_size - 1);
376 /* Invalidate one cache line :
377 * PowerPC specification says this is to be treated like a load
378 * (not a fetch) by the MMU. To be sure it will be so,
379 * do the load "by hand".
380 */
381 tmp = ldl(addr);
382 tb_invalidate_page_range(addr, addr + env->icache_line_size);
383 }
384
385 // XXX: to be tested
386 target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
387 {
388 int i, c, d;
389 d = 24;
390 for (i = 0; i < xer_bc; i++) {
391 c = ldub(addr);
392 addr = addr_add(addr, 1);
393 /* ra (if not 0) and rb are never modified */
394 if (likely(reg != rb && (ra == 0 || reg != ra))) {
395 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
396 }
397 if (unlikely(c == xer_cmp))
398 break;
399 if (likely(d != 0)) {
400 d -= 8;
401 } else {
402 d = 24;
403 reg++;
404 reg = reg & 0x1F;
405 }
406 }
407 return i;
408 }
409
410 /*****************************************************************************/
411 /* Fixed point operations helpers */
412 #if defined(TARGET_PPC64)
413
414 /* multiply high word */
415 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
416 {
417 uint64_t tl, th;
418
419 muls64(&tl, &th, arg1, arg2);
420 return th;
421 }
422
423 /* multiply high word unsigned */
424 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
425 {
426 uint64_t tl, th;
427
428 mulu64(&tl, &th, arg1, arg2);
429 return th;
430 }
431
432 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
433 {
434 int64_t th;
435 uint64_t tl;
436
437 muls64(&tl, (uint64_t *)&th, arg1, arg2);
438 /* If th != 0 && th != -1, then we had an overflow */
439 if (likely((uint64_t)(th + 1) <= 1)) {
440 env->xer &= ~(1 << XER_OV);
441 } else {
442 env->xer |= (1 << XER_OV) | (1 << XER_SO);
443 }
444 return (int64_t)tl;
445 }
446 #endif
447
448 target_ulong helper_cntlzw (target_ulong t)
449 {
450 return clz32(t);
451 }
452
453 #if defined(TARGET_PPC64)
454 target_ulong helper_cntlzd (target_ulong t)
455 {
456 return clz64(t);
457 }
458 #endif
459
460 /* shift right arithmetic helper */
461 target_ulong helper_sraw (target_ulong value, target_ulong shift)
462 {
463 int32_t ret;
464
465 if (likely(!(shift & 0x20))) {
466 if (likely((uint32_t)shift != 0)) {
467 shift &= 0x1f;
468 ret = (int32_t)value >> shift;
469 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
470 env->xer &= ~(1 << XER_CA);
471 } else {
472 env->xer |= (1 << XER_CA);
473 }
474 } else {
475 ret = (int32_t)value;
476 env->xer &= ~(1 << XER_CA);
477 }
478 } else {
479 ret = (int32_t)value >> 31;
480 if (ret) {
481 env->xer |= (1 << XER_CA);
482 } else {
483 env->xer &= ~(1 << XER_CA);
484 }
485 }
486 return (target_long)ret;
487 }
488
489 #if defined(TARGET_PPC64)
490 target_ulong helper_srad (target_ulong value, target_ulong shift)
491 {
492 int64_t ret;
493
494 if (likely(!(shift & 0x40))) {
495 if (likely((uint64_t)shift != 0)) {
496 shift &= 0x3f;
497 ret = (int64_t)value >> shift;
498 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
499 env->xer &= ~(1 << XER_CA);
500 } else {
501 env->xer |= (1 << XER_CA);
502 }
503 } else {
504 ret = (int64_t)value;
505 env->xer &= ~(1 << XER_CA);
506 }
507 } else {
508 ret = (int64_t)value >> 63;
509 if (ret) {
510 env->xer |= (1 << XER_CA);
511 } else {
512 env->xer &= ~(1 << XER_CA);
513 }
514 }
515 return ret;
516 }
517 #endif
518
519 target_ulong helper_popcntb (target_ulong val)
520 {
521 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
522 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
523 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
524 return val;
525 }
526
527 #if defined(TARGET_PPC64)
528 target_ulong helper_popcntb_64 (target_ulong val)
529 {
530 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
531 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
532 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
533 return val;
534 }
535 #endif
536
537 /*****************************************************************************/
538 /* Floating point operations helpers */
539 uint64_t helper_float32_to_float64(uint32_t arg)
540 {
541 CPU_FloatU f;
542 CPU_DoubleU d;
543 f.l = arg;
544 d.d = float32_to_float64(f.f, &env->fp_status);
545 return d.ll;
546 }
547
548 uint32_t helper_float64_to_float32(uint64_t arg)
549 {
550 CPU_FloatU f;
551 CPU_DoubleU d;
552 d.ll = arg;
553 f.f = float64_to_float32(d.d, &env->fp_status);
554 return f.l;
555 }
556
557 static always_inline int fpisneg (float64 d)
558 {
559 CPU_DoubleU u;
560
561 u.d = d;
562
563 return u.ll >> 63 != 0;
564 }
565
566 static always_inline int isden (float64 d)
567 {
568 CPU_DoubleU u;
569
570 u.d = d;
571
572 return ((u.ll >> 52) & 0x7FF) == 0;
573 }
574
575 static always_inline int iszero (float64 d)
576 {
577 CPU_DoubleU u;
578
579 u.d = d;
580
581 return (u.ll & ~0x8000000000000000ULL) == 0;
582 }
583
584 static always_inline int isinfinity (float64 d)
585 {
586 CPU_DoubleU u;
587
588 u.d = d;
589
590 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
591 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
592 }
593
594 #ifdef CONFIG_SOFTFLOAT
595 static always_inline int isfinite (float64 d)
596 {
597 CPU_DoubleU u;
598
599 u.d = d;
600
601 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
602 }
603
604 static always_inline int isnormal (float64 d)
605 {
606 CPU_DoubleU u;
607
608 u.d = d;
609
610 uint32_t exp = (u.ll >> 52) & 0x7FF;
611 return ((0 < exp) && (exp < 0x7FF));
612 }
613 #endif
614
615 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
616 {
617 CPU_DoubleU farg;
618 int isneg;
619 int ret;
620 farg.ll = arg;
621 isneg = fpisneg(farg.d);
622 if (unlikely(float64_is_nan(farg.d))) {
623 if (float64_is_signaling_nan(farg.d)) {
624 /* Signaling NaN: flags are undefined */
625 ret = 0x00;
626 } else {
627 /* Quiet NaN */
628 ret = 0x11;
629 }
630 } else if (unlikely(isinfinity(farg.d))) {
631 /* +/- infinity */
632 if (isneg)
633 ret = 0x09;
634 else
635 ret = 0x05;
636 } else {
637 if (iszero(farg.d)) {
638 /* +/- zero */
639 if (isneg)
640 ret = 0x12;
641 else
642 ret = 0x02;
643 } else {
644 if (isden(farg.d)) {
645 /* Denormalized numbers */
646 ret = 0x10;
647 } else {
648 /* Normalized numbers */
649 ret = 0x00;
650 }
651 if (isneg) {
652 ret |= 0x08;
653 } else {
654 ret |= 0x04;
655 }
656 }
657 }
658 if (set_fprf) {
659 /* We update FPSCR_FPRF */
660 env->fpscr &= ~(0x1F << FPSCR_FPRF);
661 env->fpscr |= ret << FPSCR_FPRF;
662 }
663 /* We just need fpcc to update Rc1 */
664 return ret & 0xF;
665 }
666
667 /* Floating-point invalid operations exception */
668 static always_inline uint64_t fload_invalid_op_excp (int op)
669 {
670 uint64_t ret = 0;
671 int ve;
672
673 ve = fpscr_ve;
674 if (op & POWERPC_EXCP_FP_VXSNAN) {
675 /* Operation on signaling NaN */
676 env->fpscr |= 1 << FPSCR_VXSNAN;
677 }
678 if (op & POWERPC_EXCP_FP_VXSOFT) {
679 /* Software-defined condition */
680 env->fpscr |= 1 << FPSCR_VXSOFT;
681 }
682 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
683 case POWERPC_EXCP_FP_VXISI:
684 /* Magnitude subtraction of infinities */
685 env->fpscr |= 1 << FPSCR_VXISI;
686 goto update_arith;
687 case POWERPC_EXCP_FP_VXIDI:
688 /* Division of infinity by infinity */
689 env->fpscr |= 1 << FPSCR_VXIDI;
690 goto update_arith;
691 case POWERPC_EXCP_FP_VXZDZ:
692 /* Division of zero by zero */
693 env->fpscr |= 1 << FPSCR_VXZDZ;
694 goto update_arith;
695 case POWERPC_EXCP_FP_VXIMZ:
696 /* Multiplication of zero by infinity */
697 env->fpscr |= 1 << FPSCR_VXIMZ;
698 goto update_arith;
699 case POWERPC_EXCP_FP_VXVC:
700 /* Ordered comparison of NaN */
701 env->fpscr |= 1 << FPSCR_VXVC;
702 env->fpscr &= ~(0xF << FPSCR_FPCC);
703 env->fpscr |= 0x11 << FPSCR_FPCC;
704 /* We must update the target FPR before raising the exception */
705 if (ve != 0) {
706 env->exception_index = POWERPC_EXCP_PROGRAM;
707 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
708 /* Update the floating-point enabled exception summary */
709 env->fpscr |= 1 << FPSCR_FEX;
710 /* Exception is differed */
711 ve = 0;
712 }
713 break;
714 case POWERPC_EXCP_FP_VXSQRT:
715 /* Square root of a negative number */
716 env->fpscr |= 1 << FPSCR_VXSQRT;
717 update_arith:
718 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
719 if (ve == 0) {
720 /* Set the result to quiet NaN */
721 ret = UINT64_MAX;
722 env->fpscr &= ~(0xF << FPSCR_FPCC);
723 env->fpscr |= 0x11 << FPSCR_FPCC;
724 }
725 break;
726 case POWERPC_EXCP_FP_VXCVI:
727 /* Invalid conversion */
728 env->fpscr |= 1 << FPSCR_VXCVI;
729 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
730 if (ve == 0) {
731 /* Set the result to quiet NaN */
732 ret = UINT64_MAX;
733 env->fpscr &= ~(0xF << FPSCR_FPCC);
734 env->fpscr |= 0x11 << FPSCR_FPCC;
735 }
736 break;
737 }
738 /* Update the floating-point invalid operation summary */
739 env->fpscr |= 1 << FPSCR_VX;
740 /* Update the floating-point exception summary */
741 env->fpscr |= 1 << FPSCR_FX;
742 if (ve != 0) {
743 /* Update the floating-point enabled exception summary */
744 env->fpscr |= 1 << FPSCR_FEX;
745 if (msr_fe0 != 0 || msr_fe1 != 0)
746 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
747 }
748 return ret;
749 }
750
751 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
752 {
753 env->fpscr |= 1 << FPSCR_ZX;
754 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
755 /* Update the floating-point exception summary */
756 env->fpscr |= 1 << FPSCR_FX;
757 if (fpscr_ze != 0) {
758 /* Update the floating-point enabled exception summary */
759 env->fpscr |= 1 << FPSCR_FEX;
760 if (msr_fe0 != 0 || msr_fe1 != 0) {
761 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
762 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
763 }
764 } else {
765 /* Set the result to infinity */
766 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
767 arg1 |= 0x7FFULL << 52;
768 }
769 return arg1;
770 }
771
772 static always_inline void float_overflow_excp (void)
773 {
774 env->fpscr |= 1 << FPSCR_OX;
775 /* Update the floating-point exception summary */
776 env->fpscr |= 1 << FPSCR_FX;
777 if (fpscr_oe != 0) {
778 /* XXX: should adjust the result */
779 /* Update the floating-point enabled exception summary */
780 env->fpscr |= 1 << FPSCR_FEX;
781 /* We must update the target FPR before raising the exception */
782 env->exception_index = POWERPC_EXCP_PROGRAM;
783 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
784 } else {
785 env->fpscr |= 1 << FPSCR_XX;
786 env->fpscr |= 1 << FPSCR_FI;
787 }
788 }
789
790 static always_inline void float_underflow_excp (void)
791 {
792 env->fpscr |= 1 << FPSCR_UX;
793 /* Update the floating-point exception summary */
794 env->fpscr |= 1 << FPSCR_FX;
795 if (fpscr_ue != 0) {
796 /* XXX: should adjust the result */
797 /* Update the floating-point enabled exception summary */
798 env->fpscr |= 1 << FPSCR_FEX;
799 /* We must update the target FPR before raising the exception */
800 env->exception_index = POWERPC_EXCP_PROGRAM;
801 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
802 }
803 }
804
805 static always_inline void float_inexact_excp (void)
806 {
807 env->fpscr |= 1 << FPSCR_XX;
808 /* Update the floating-point exception summary */
809 env->fpscr |= 1 << FPSCR_FX;
810 if (fpscr_xe != 0) {
811 /* Update the floating-point enabled exception summary */
812 env->fpscr |= 1 << FPSCR_FEX;
813 /* We must update the target FPR before raising the exception */
814 env->exception_index = POWERPC_EXCP_PROGRAM;
815 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
816 }
817 }
818
819 static always_inline void fpscr_set_rounding_mode (void)
820 {
821 int rnd_type;
822
823 /* Set rounding mode */
824 switch (fpscr_rn) {
825 case 0:
826 /* Best approximation (round to nearest) */
827 rnd_type = float_round_nearest_even;
828 break;
829 case 1:
830 /* Smaller magnitude (round toward zero) */
831 rnd_type = float_round_to_zero;
832 break;
833 case 2:
834 /* Round toward +infinite */
835 rnd_type = float_round_up;
836 break;
837 default:
838 case 3:
839 /* Round toward -infinite */
840 rnd_type = float_round_down;
841 break;
842 }
843 set_float_rounding_mode(rnd_type, &env->fp_status);
844 }
845
846 void helper_fpscr_setbit (uint32_t bit)
847 {
848 int prev;
849
850 prev = (env->fpscr >> bit) & 1;
851 env->fpscr |= 1 << bit;
852 if (prev == 0) {
853 switch (bit) {
854 case FPSCR_VX:
855 env->fpscr |= 1 << FPSCR_FX;
856 if (fpscr_ve)
857 goto raise_ve;
858 case FPSCR_OX:
859 env->fpscr |= 1 << FPSCR_FX;
860 if (fpscr_oe)
861 goto raise_oe;
862 break;
863 case FPSCR_UX:
864 env->fpscr |= 1 << FPSCR_FX;
865 if (fpscr_ue)
866 goto raise_ue;
867 break;
868 case FPSCR_ZX:
869 env->fpscr |= 1 << FPSCR_FX;
870 if (fpscr_ze)
871 goto raise_ze;
872 break;
873 case FPSCR_XX:
874 env->fpscr |= 1 << FPSCR_FX;
875 if (fpscr_xe)
876 goto raise_xe;
877 break;
878 case FPSCR_VXSNAN:
879 case FPSCR_VXISI:
880 case FPSCR_VXIDI:
881 case FPSCR_VXZDZ:
882 case FPSCR_VXIMZ:
883 case FPSCR_VXVC:
884 case FPSCR_VXSOFT:
885 case FPSCR_VXSQRT:
886 case FPSCR_VXCVI:
887 env->fpscr |= 1 << FPSCR_VX;
888 env->fpscr |= 1 << FPSCR_FX;
889 if (fpscr_ve != 0)
890 goto raise_ve;
891 break;
892 case FPSCR_VE:
893 if (fpscr_vx != 0) {
894 raise_ve:
895 env->error_code = POWERPC_EXCP_FP;
896 if (fpscr_vxsnan)
897 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
898 if (fpscr_vxisi)
899 env->error_code |= POWERPC_EXCP_FP_VXISI;
900 if (fpscr_vxidi)
901 env->error_code |= POWERPC_EXCP_FP_VXIDI;
902 if (fpscr_vxzdz)
903 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
904 if (fpscr_vximz)
905 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
906 if (fpscr_vxvc)
907 env->error_code |= POWERPC_EXCP_FP_VXVC;
908 if (fpscr_vxsoft)
909 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
910 if (fpscr_vxsqrt)
911 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
912 if (fpscr_vxcvi)
913 env->error_code |= POWERPC_EXCP_FP_VXCVI;
914 goto raise_excp;
915 }
916 break;
917 case FPSCR_OE:
918 if (fpscr_ox != 0) {
919 raise_oe:
920 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
921 goto raise_excp;
922 }
923 break;
924 case FPSCR_UE:
925 if (fpscr_ux != 0) {
926 raise_ue:
927 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
928 goto raise_excp;
929 }
930 break;
931 case FPSCR_ZE:
932 if (fpscr_zx != 0) {
933 raise_ze:
934 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
935 goto raise_excp;
936 }
937 break;
938 case FPSCR_XE:
939 if (fpscr_xx != 0) {
940 raise_xe:
941 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
942 goto raise_excp;
943 }
944 break;
945 case FPSCR_RN1:
946 case FPSCR_RN:
947 fpscr_set_rounding_mode();
948 break;
949 default:
950 break;
951 raise_excp:
952 /* Update the floating-point enabled exception summary */
953 env->fpscr |= 1 << FPSCR_FEX;
954 /* We have to update Rc1 before raising the exception */
955 env->exception_index = POWERPC_EXCP_PROGRAM;
956 break;
957 }
958 }
959 }
960
961 void helper_store_fpscr (uint64_t arg, uint32_t mask)
962 {
963 /*
964 * We use only the 32 LSB of the incoming fpr
965 */
966 uint32_t prev, new;
967 int i;
968
969 prev = env->fpscr;
970 new = (uint32_t)arg;
971 new &= ~0x90000000;
972 new |= prev & 0x90000000;
973 for (i = 0; i < 7; i++) {
974 if (mask & (1 << i)) {
975 env->fpscr &= ~(0xF << (4 * i));
976 env->fpscr |= new & (0xF << (4 * i));
977 }
978 }
979 /* Update VX and FEX */
980 if (fpscr_ix != 0)
981 env->fpscr |= 1 << FPSCR_VX;
982 else
983 env->fpscr &= ~(1 << FPSCR_VX);
984 if ((fpscr_ex & fpscr_eex) != 0) {
985 env->fpscr |= 1 << FPSCR_FEX;
986 env->exception_index = POWERPC_EXCP_PROGRAM;
987 /* XXX: we should compute it properly */
988 env->error_code = POWERPC_EXCP_FP;
989 }
990 else
991 env->fpscr &= ~(1 << FPSCR_FEX);
992 fpscr_set_rounding_mode();
993 }
994
995 void helper_float_check_status (void)
996 {
997 #ifdef CONFIG_SOFTFLOAT
998 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
999 (env->error_code & POWERPC_EXCP_FP)) {
1000 /* Differred floating-point exception after target FPR update */
1001 if (msr_fe0 != 0 || msr_fe1 != 0)
1002 helper_raise_exception_err(env->exception_index, env->error_code);
1003 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
1004 float_overflow_excp();
1005 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
1006 float_underflow_excp();
1007 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
1008 float_inexact_excp();
1009 }
1010 #else
1011 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
1012 (env->error_code & POWERPC_EXCP_FP)) {
1013 /* Differred floating-point exception after target FPR update */
1014 if (msr_fe0 != 0 || msr_fe1 != 0)
1015 helper_raise_exception_err(env->exception_index, env->error_code);
1016 }
1017 #endif
1018 }
1019
1020 #ifdef CONFIG_SOFTFLOAT
1021 void helper_reset_fpstatus (void)
1022 {
1023 env->fp_status.float_exception_flags = 0;
1024 }
1025 #endif
1026
1027 /* fadd - fadd. */
1028 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
1029 {
1030 CPU_DoubleU farg1, farg2;
1031
1032 farg1.ll = arg1;
1033 farg2.ll = arg2;
1034 #if USE_PRECISE_EMULATION
1035 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1036 float64_is_signaling_nan(farg2.d))) {
1037 /* sNaN addition */
1038 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1039 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1040 fpisneg(farg1.d) == fpisneg(farg2.d))) {
1041 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1042 } else {
1043 /* Magnitude subtraction of infinities */
1044 farg1.ll == fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1045 }
1046 #else
1047 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1048 #endif
1049 return farg1.ll;
1050 }
1051
1052 /* fsub - fsub. */
1053 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
1054 {
1055 CPU_DoubleU farg1, farg2;
1056
1057 farg1.ll = arg1;
1058 farg2.ll = arg2;
1059 #if USE_PRECISE_EMULATION
1060 {
1061 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1062 float64_is_signaling_nan(farg2.d))) {
1063 /* sNaN subtraction */
1064 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1065 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1066 fpisneg(farg1.d) != fpisneg(farg2.d))) {
1067 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1068 } else {
1069 /* Magnitude subtraction of infinities */
1070 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1071 }
1072 }
1073 #else
1074 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1075 #endif
1076 return farg1.ll;
1077 }
1078
1079 /* fmul - fmul. */
1080 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
1081 {
1082 CPU_DoubleU farg1, farg2;
1083
1084 farg1.ll = arg1;
1085 farg2.ll = arg2;
1086 #if USE_PRECISE_EMULATION
1087 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1088 float64_is_signaling_nan(farg2.d))) {
1089 /* sNaN multiplication */
1090 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1091 } else if (unlikely((isinfinity(farg1.d) && iszero(farg2.d)) ||
1092 (iszero(farg1.d) && isinfinity(farg2.d)))) {
1093 /* Multiplication of zero by infinity */
1094 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1095 } else {
1096 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1097 }
1098 }
1099 #else
1100 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1101 #endif
1102 return farg1.ll;
1103 }
1104
1105 /* fdiv - fdiv. */
1106 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
1107 {
1108 CPU_DoubleU farg1, farg2;
1109
1110 farg1.ll = arg1;
1111 farg2.ll = arg2;
1112 #if USE_PRECISE_EMULATION
1113 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1114 float64_is_signaling_nan(farg2.d))) {
1115 /* sNaN division */
1116 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1117 } else if (unlikely(isinfinity(farg1.d) && isinfinity(farg2.d))) {
1118 /* Division of infinity by infinity */
1119 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
1120 } else if (unlikely(iszero(farg2.d))) {
1121 if (iszero(farg1.d)) {
1122 /* Division of zero by zero */
1123 farg1.ll fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
1124 } else {
1125 /* Division by zero */
1126 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
1127 }
1128 } else {
1129 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1130 }
1131 #else
1132 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1133 #endif
1134 return farg1.ll;
1135 }
1136
1137 /* fabs */
1138 uint64_t helper_fabs (uint64_t arg)
1139 {
1140 CPU_DoubleU farg;
1141
1142 farg.ll = arg;
1143 farg.d = float64_abs(farg.d);
1144 return farg.ll;
1145 }
1146
1147 /* fnabs */
1148 uint64_t helper_fnabs (uint64_t arg)
1149 {
1150 CPU_DoubleU farg;
1151
1152 farg.ll = arg;
1153 farg.d = float64_abs(farg.d);
1154 farg.d = float64_chs(farg.d);
1155 return farg.ll;
1156 }
1157
1158 /* fneg */
1159 uint64_t helper_fneg (uint64_t arg)
1160 {
1161 CPU_DoubleU farg;
1162
1163 farg.ll = arg;
1164 farg.d = float64_chs(farg.d);
1165 return farg.ll;
1166 }
1167
1168 /* fctiw - fctiw. */
1169 uint64_t helper_fctiw (uint64_t arg)
1170 {
1171 CPU_DoubleU farg;
1172 farg.ll = arg;
1173
1174 if (unlikely(float64_is_signaling_nan(farg.d))) {
1175 /* sNaN conversion */
1176 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1177 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1178 /* qNan / infinity conversion */
1179 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1180 } else {
1181 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1182 #if USE_PRECISE_EMULATION
1183 /* XXX: higher bits are not supposed to be significant.
1184 * to make tests easier, return the same as a real PowerPC 750
1185 */
1186 farg.ll |= 0xFFF80000ULL << 32;
1187 #endif
1188 }
1189 return farg.ll;
1190 }
1191
1192 /* fctiwz - fctiwz. */
1193 uint64_t helper_fctiwz (uint64_t arg)
1194 {
1195 CPU_DoubleU farg;
1196 farg.ll = arg;
1197
1198 if (unlikely(float64_is_signaling_nan(farg.d))) {
1199 /* sNaN conversion */
1200 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1201 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1202 /* qNan / infinity conversion */
1203 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1204 } else {
1205 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1206 #if USE_PRECISE_EMULATION
1207 /* XXX: higher bits are not supposed to be significant.
1208 * to make tests easier, return the same as a real PowerPC 750
1209 */
1210 farg.ll |= 0xFFF80000ULL << 32;
1211 #endif
1212 }
1213 return farg.ll;
1214 }
1215
1216 #if defined(TARGET_PPC64)
1217 /* fcfid - fcfid. */
1218 uint64_t helper_fcfid (uint64_t arg)
1219 {
1220 CPU_DoubleU farg;
1221 farg.d = int64_to_float64(arg, &env->fp_status);
1222 return farg.ll;
1223 }
1224
1225 /* fctid - fctid. */
1226 uint64_t helper_fctid (uint64_t arg)
1227 {
1228 CPU_DoubleU farg;
1229 farg.ll = arg;
1230
1231 if (unlikely(float64_is_signaling_nan(farg.d))) {
1232 /* sNaN conversion */
1233 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1234 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1235 /* qNan / infinity conversion */
1236 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1237 } else {
1238 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1239 }
1240 return farg.ll;
1241 }
1242
1243 /* fctidz - fctidz. */
1244 uint64_t helper_fctidz (uint64_t arg)
1245 {
1246 CPU_DoubleU farg;
1247 farg.ll = arg;
1248
1249 if (unlikely(float64_is_signaling_nan(farg.d))) {
1250 /* sNaN conversion */
1251 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1252 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1253 /* qNan / infinity conversion */
1254 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1255 } else {
1256 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1257 }
1258 return farg.ll;
1259 }
1260
1261 #endif
1262
1263 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1264 {
1265 CPU_DoubleU farg;
1266 farg.ll = arg;
1267
1268 if (unlikely(float64_is_signaling_nan(farg.d))) {
1269 /* sNaN round */
1270 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1271 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1272 /* qNan / infinity round */
1273 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1274 } else {
1275 set_float_rounding_mode(rounding_mode, &env->fp_status);
1276 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1277 /* Restore rounding mode from FPSCR */
1278 fpscr_set_rounding_mode();
1279 }
1280 return farg.ll;
1281 }
1282
1283 uint64_t helper_frin (uint64_t arg)
1284 {
1285 return do_fri(arg, float_round_nearest_even);
1286 }
1287
1288 uint64_t helper_friz (uint64_t arg)
1289 {
1290 return do_fri(arg, float_round_to_zero);
1291 }
1292
1293 uint64_t helper_frip (uint64_t arg)
1294 {
1295 return do_fri(arg, float_round_up);
1296 }
1297
1298 uint64_t helper_frim (uint64_t arg)
1299 {
1300 return do_fri(arg, float_round_down);
1301 }
1302
1303 /* fmadd - fmadd. */
1304 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1305 {
1306 CPU_DoubleU farg1, farg2, farg3;
1307
1308 farg1.ll = arg1;
1309 farg2.ll = arg2;
1310 farg3.ll = arg3;
1311 #if USE_PRECISE_EMULATION
1312 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1313 float64_is_signaling_nan(farg2.d) ||
1314 float64_is_signaling_nan(farg3.d))) {
1315 /* sNaN operation */
1316 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1317 } else {
1318 #ifdef FLOAT128
1319 /* This is the way the PowerPC specification defines it */
1320 float128 ft0_128, ft1_128;
1321
1322 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1323 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1324 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1325 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1326 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1327 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1328 #else
1329 /* This is OK on x86 hosts */
1330 farg1.d = (farg1.d * farg2.d) + farg3.d;
1331 #endif
1332 }
1333 #else
1334 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1335 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1336 #endif
1337 return farg1.ll;
1338 }
1339
1340 /* fmsub - fmsub. */
1341 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1342 {
1343 CPU_DoubleU farg1, farg2, farg3;
1344
1345 farg1.ll = arg1;
1346 farg2.ll = arg2;
1347 farg3.ll = arg3;
1348 #if USE_PRECISE_EMULATION
1349 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1350 float64_is_signaling_nan(farg2.d) ||
1351 float64_is_signaling_nan(farg3.d))) {
1352 /* sNaN operation */
1353 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1354 } else {
1355 #ifdef FLOAT128
1356 /* This is the way the PowerPC specification defines it */
1357 float128 ft0_128, ft1_128;
1358
1359 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1360 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1361 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1362 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1363 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1364 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1365 #else
1366 /* This is OK on x86 hosts */
1367 farg1.d = (farg1.d * farg2.d) - farg3.d;
1368 #endif
1369 }
1370 #else
1371 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1372 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1373 #endif
1374 return farg1.ll;
1375 }
1376
1377 /* fnmadd - fnmadd. */
1378 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1379 {
1380 CPU_DoubleU farg1, farg2, farg3;
1381
1382 farg1.ll = arg1;
1383 farg2.ll = arg2;
1384 farg3.ll = arg3;
1385
1386 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1387 float64_is_signaling_nan(farg2.d) ||
1388 float64_is_signaling_nan(farg3.d))) {
1389 /* sNaN operation */
1390 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1391 } else {
1392 #if USE_PRECISE_EMULATION
1393 #ifdef FLOAT128
1394 /* This is the way the PowerPC specification defines it */
1395 float128 ft0_128, ft1_128;
1396
1397 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1398 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1399 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1400 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1401 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1402 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
1403 #else
1404 /* This is OK on x86 hosts */
1405 farg1.d = (farg1.d * farg2.d) + farg3.d;
1406 #endif
1407 #else
1408 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1409 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1410 #endif
1411 if (likely(!float64_is_nan(farg1.d)))
1412 farg1.d = float64_chs(farg1.d);
1413 }
1414 return farg1.ll;
1415 }
1416
1417 /* fnmsub - fnmsub. */
1418 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1419 {
1420 CPU_DoubleU farg1, farg2, farg3;
1421
1422 farg1.ll = arg1;
1423 farg2.ll = arg2;
1424 farg3.ll = arg3;
1425
1426 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1427 float64_is_signaling_nan(farg2.d) ||
1428 float64_is_signaling_nan(farg3.d))) {
1429 /* sNaN operation */
1430 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1431 } else {
1432 #if USE_PRECISE_EMULATION
1433 #ifdef FLOAT128
1434 /* This is the way the PowerPC specification defines it */
1435 float128 ft0_128, ft1_128;
1436
1437 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1438 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1439 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1440 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1441 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1442 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1443 #else
1444 /* This is OK on x86 hosts */
1445 farg1.d = (farg1.d * farg2.d) - farg3.d;
1446 #endif
1447 #else
1448 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1449 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1450 #endif
1451 if (likely(!float64_is_nan(farg1.d)))
1452 farg1.d = float64_chs(farg1.d);
1453 }
1454 return farg1.ll;
1455 }
1456
1457 /* frsp - frsp. */
1458 uint64_t helper_frsp (uint64_t arg)
1459 {
1460 CPU_DoubleU farg;
1461 farg.ll = arg;
1462
1463 #if USE_PRECISE_EMULATION
1464 if (unlikely(float64_is_signaling_nan(farg.d))) {
1465 /* sNaN square root */
1466 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1467 } else {
1468 fard.d = float64_to_float32(farg.d, &env->fp_status);
1469 }
1470 #else
1471 farg.d = float64_to_float32(farg.d, &env->fp_status);
1472 #endif
1473 return farg.ll;
1474 }
1475
1476 /* fsqrt - fsqrt. */
1477 uint64_t helper_fsqrt (uint64_t arg)
1478 {
1479 CPU_DoubleU farg;
1480 farg.ll = arg;
1481
1482 if (unlikely(float64_is_signaling_nan(farg.d))) {
1483 /* sNaN square root */
1484 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1485 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1486 /* Square root of a negative nonzero number */
1487 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1488 } else {
1489 farg.d = float64_sqrt(farg.d, &env->fp_status);
1490 }
1491 return farg.ll;
1492 }
1493
1494 /* fre - fre. */
1495 uint64_t helper_fre (uint64_t arg)
1496 {
1497 CPU_DoubleU farg;
1498 farg.ll = arg;
1499
1500 if (unlikely(float64_is_signaling_nan(farg.d))) {
1501 /* sNaN reciprocal */
1502 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1503 } else if (unlikely(iszero(farg.d))) {
1504 /* Zero reciprocal */
1505 farg.ll = float_zero_divide_excp(1.0, farg.d);
1506 } else if (likely(isnormal(farg.d))) {
1507 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1508 } else {
1509 if (farg.ll == 0x8000000000000000ULL) {
1510 farg.ll = 0xFFF0000000000000ULL;
1511 } else if (farg.ll == 0x0000000000000000ULL) {
1512 farg.ll = 0x7FF0000000000000ULL;
1513 } else if (float64_is_nan(farg.d)) {
1514 farg.ll = 0x7FF8000000000000ULL;
1515 } else if (fpisneg(farg.d)) {
1516 farg.ll = 0x8000000000000000ULL;
1517 } else {
1518 farg.ll = 0x0000000000000000ULL;
1519 }
1520 }
1521 return farg.d;
1522 }
1523
1524 /* fres - fres. */
1525 uint64_t helper_fres (uint64_t arg)
1526 {
1527 CPU_DoubleU farg;
1528 farg.ll = arg;
1529
1530 if (unlikely(float64_is_signaling_nan(farg.d))) {
1531 /* sNaN reciprocal */
1532 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1533 } else if (unlikely(iszero(farg.d))) {
1534 /* Zero reciprocal */
1535 farg.ll = float_zero_divide_excp(1.0, farg.d);
1536 } else if (likely(isnormal(farg.d))) {
1537 #if USE_PRECISE_EMULATION
1538 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1539 farg.d = float64_to_float32(farg.d, &env->fp_status);
1540 #else
1541 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1542 #endif
1543 } else {
1544 if (farg.ll == 0x8000000000000000ULL) {
1545 farg.ll = 0xFFF0000000000000ULL;
1546 } else if (farg.ll == 0x0000000000000000ULL) {
1547 farg.ll = 0x7FF0000000000000ULL;
1548 } else if (float64_is_nan(farg.d)) {
1549 farg.ll = 0x7FF8000000000000ULL;
1550 } else if (fpisneg(farg.d)) {
1551 farg.ll = 0x8000000000000000ULL;
1552 } else {
1553 farg.ll = 0x0000000000000000ULL;
1554 }
1555 }
1556 return farg.ll;
1557 }
1558
1559 /* frsqrte - frsqrte. */
1560 uint64_t helper_frsqrte (uint64_t arg)
1561 {
1562 CPU_DoubleU farg;
1563 farg.ll = arg;
1564
1565 if (unlikely(float64_is_signaling_nan(farg.d))) {
1566 /* sNaN reciprocal square root */
1567 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1568 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1569 /* Reciprocal square root of a negative nonzero number */
1570 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1571 } else if (likely(isnormal(farg.d))) {
1572 farg.d = float64_sqrt(farg.d, &env->fp_status);
1573 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1574 } else {
1575 if (farg.ll == 0x8000000000000000ULL) {
1576 farg.ll = 0xFFF0000000000000ULL;
1577 } else if (farg.ll == 0x0000000000000000ULL) {
1578 farg.ll = 0x7FF0000000000000ULL;
1579 } else if (float64_is_nan(farg.d)) {
1580 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1581 } else if (fpisneg(farg.d)) {
1582 farg.ll = 0x7FF8000000000000ULL;
1583 } else {
1584 farg.ll = 0x0000000000000000ULL;
1585 }
1586 }
1587 return farg.ll;
1588 }
1589
1590 /* fsel - fsel. */
1591 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1592 {
1593 CPU_DoubleU farg1, farg2, farg3;
1594
1595 farg1.ll = arg1;
1596 farg2.ll = arg2;
1597 farg3.ll = arg3;
1598
1599 if (!fpisneg(farg1.d) || iszero(farg1.d))
1600 return farg2.ll;
1601 else
1602 return farg2.ll;
1603 }
1604
1605 uint32_t helper_fcmpu (uint64_t arg1, uint64_t arg2)
1606 {
1607 CPU_DoubleU farg1, farg2;
1608 uint32_t ret = 0;
1609 farg1.ll = arg1;
1610 farg2.ll = arg2;
1611
1612 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1613 float64_is_signaling_nan(farg2.d))) {
1614 /* sNaN comparison */
1615 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1616 } else {
1617 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1618 ret = 0x08UL;
1619 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1620 ret = 0x04UL;
1621 } else {
1622 ret = 0x02UL;
1623 }
1624 }
1625 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1626 env->fpscr |= ret << FPSCR_FPRF;
1627 return ret;
1628 }
1629
1630 uint32_t helper_fcmpo (uint64_t arg1, uint64_t arg2)
1631 {
1632 CPU_DoubleU farg1, farg2;
1633 uint32_t ret = 0;
1634 farg1.ll = arg1;
1635 farg2.ll = arg2;
1636
1637 if (unlikely(float64_is_nan(farg1.d) ||
1638 float64_is_nan(farg2.d))) {
1639 if (float64_is_signaling_nan(farg1.d) ||
1640 float64_is_signaling_nan(farg2.d)) {
1641 /* sNaN comparison */
1642 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1643 POWERPC_EXCP_FP_VXVC);
1644 } else {
1645 /* qNaN comparison */
1646 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1647 }
1648 } else {
1649 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1650 ret = 0x08UL;
1651 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1652 ret = 0x04UL;
1653 } else {
1654 ret = 0x02UL;
1655 }
1656 }
1657 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1658 env->fpscr |= ret << FPSCR_FPRF;
1659 return ret;
1660 }
1661
1662 #if !defined (CONFIG_USER_ONLY)
1663 void helper_store_msr (target_ulong val)
1664 {
1665 val = hreg_store_msr(env, val, 0);
1666 if (val != 0) {
1667 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1668 helper_raise_exception(val);
1669 }
1670 }
1671
1672 static always_inline void do_rfi (target_ulong nip, target_ulong msr,
1673 target_ulong msrm, int keep_msrh)
1674 {
1675 #if defined(TARGET_PPC64)
1676 if (msr & (1ULL << MSR_SF)) {
1677 nip = (uint64_t)nip;
1678 msr &= (uint64_t)msrm;
1679 } else {
1680 nip = (uint32_t)nip;
1681 msr = (uint32_t)(msr & msrm);
1682 if (keep_msrh)
1683 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1684 }
1685 #else
1686 nip = (uint32_t)nip;
1687 msr &= (uint32_t)msrm;
1688 #endif
1689 /* XXX: beware: this is false if VLE is supported */
1690 env->nip = nip & ~((target_ulong)0x00000003);
1691 hreg_store_msr(env, msr, 1);
1692 #if defined (DEBUG_OP)
1693 cpu_dump_rfi(env->nip, env->msr);
1694 #endif
1695 /* No need to raise an exception here,
1696 * as rfi is always the last insn of a TB
1697 */
1698 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1699 }
1700
1701 void helper_rfi (void)
1702 {
1703 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1704 ~((target_ulong)0xFFFF0000), 1);
1705 }
1706
1707 #if defined(TARGET_PPC64)
1708 void helper_rfid (void)
1709 {
1710 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1711 ~((target_ulong)0xFFFF0000), 0);
1712 }
1713
1714 void helper_hrfid (void)
1715 {
1716 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1717 ~((target_ulong)0xFFFF0000), 0);
1718 }
1719 #endif
1720 #endif
1721
1722 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1723 {
1724 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1725 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1726 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1727 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1728 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1729 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1730 }
1731 }
1732
1733 #if defined(TARGET_PPC64)
1734 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1735 {
1736 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1737 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1738 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1739 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1740 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1741 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1742 }
1743 #endif
1744
1745 /*****************************************************************************/
1746 /* PowerPC 601 specific instructions (POWER bridge) */
1747
1748 target_ulong helper_clcs (uint32_t arg)
1749 {
1750 switch (arg) {
1751 case 0x0CUL:
1752 /* Instruction cache line size */
1753 return env->icache_line_size;
1754 break;
1755 case 0x0DUL:
1756 /* Data cache line size */
1757 return env->dcache_line_size;
1758 break;
1759 case 0x0EUL:
1760 /* Minimum cache line size */
1761 return (env->icache_line_size < env->dcache_line_size) ?
1762 env->icache_line_size : env->dcache_line_size;
1763 break;
1764 case 0x0FUL:
1765 /* Maximum cache line size */
1766 return (env->icache_line_size > env->dcache_line_size) ?
1767 env->icache_line_size : env->dcache_line_size;
1768 break;
1769 default:
1770 /* Undefined */
1771 return 0;
1772 break;
1773 }
1774 }
1775
1776 target_ulong helper_div (target_ulong arg1, target_ulong arg2)
1777 {
1778 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1779
1780 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1781 (int32_t)arg2 == 0) {
1782 env->spr[SPR_MQ] = 0;
1783 return INT32_MIN;
1784 } else {
1785 env->spr[SPR_MQ] = tmp % arg2;
1786 return tmp / (int32_t)arg2;
1787 }
1788 }
1789
1790 target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
1791 {
1792 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1793
1794 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1795 (int32_t)arg2 == 0) {
1796 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1797 env->spr[SPR_MQ] = 0;
1798 return INT32_MIN;
1799 } else {
1800 env->spr[SPR_MQ] = tmp % arg2;
1801 tmp /= (int32_t)arg2;
1802 if ((int32_t)tmp != tmp) {
1803 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1804 } else {
1805 env->xer &= ~(1 << XER_OV);
1806 }
1807 return tmp;
1808 }
1809 }
1810
1811 target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
1812 {
1813 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1814 (int32_t)arg2 == 0) {
1815 env->spr[SPR_MQ] = 0;
1816 return INT32_MIN;
1817 } else {
1818 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1819 return (int32_t)arg1 / (int32_t)arg2;
1820 }
1821 }
1822
1823 target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
1824 {
1825 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1826 (int32_t)arg2 == 0) {
1827 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1828 env->spr[SPR_MQ] = 0;
1829 return INT32_MIN;
1830 } else {
1831 env->xer &= ~(1 << XER_OV);
1832 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1833 return (int32_t)arg1 / (int32_t)arg2;
1834 }
1835 }
1836
1837 #if !defined (CONFIG_USER_ONLY)
1838 target_ulong helper_rac (target_ulong addr)
1839 {
1840 mmu_ctx_t ctx;
1841 int nb_BATs;
1842 target_ulong ret = 0;
1843
1844 /* We don't have to generate many instances of this instruction,
1845 * as rac is supervisor only.
1846 */
1847 /* XXX: FIX THIS: Pretend we have no BAT */
1848 nb_BATs = env->nb_BATs;
1849 env->nb_BATs = 0;
1850 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1851 ret = ctx.raddr;
1852 env->nb_BATs = nb_BATs;
1853 return ret;
1854 }
1855
1856 void helper_rfsvc (void)
1857 {
1858 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1859 }
1860 #endif
1861
1862 /*****************************************************************************/
1863 /* 602 specific instructions */
1864 /* mfrom is the most crazy instruction ever seen, imho ! */
1865 /* Real implementation uses a ROM table. Do the same */
1866 #if !defined (CONFIG_USER_ONLY)
1867 #define USE_MFROM_ROM_TABLE
1868 target_ulong helper_602_mfrom (target_ulong arg)
1869 {
1870 if (likely(arg < 602)) {
1871 #if defined(USE_MFROM_ROM_TABLE)
1872 #include "mfrom_table.c"
1873 return mfrom_ROM_table[arg];
1874 #else
1875 double d;
1876 /* Extremly decomposed:
1877 * -arg / 256
1878 * return 256 * log10(10 + 1.0) + 0.5
1879 */
1880 d = arg;
1881 d = float64_div(d, 256, &env->fp_status);
1882 d = float64_chs(d);
1883 d = exp10(d); // XXX: use float emulation function
1884 d = float64_add(d, 1.0, &env->fp_status);
1885 d = log10(d); // XXX: use float emulation function
1886 d = float64_mul(d, 256, &env->fp_status);
1887 d = float64_add(d, 0.5, &env->fp_status);
1888 return float64_round_to_int(d, &env->fp_status);
1889 #endif
1890 } else {
1891 return 0;
1892 }
1893 }
1894 #endif
1895
1896 /*****************************************************************************/
1897 /* Embedded PowerPC specific helpers */
1898
1899 /* XXX: to be improved to check access rights when in user-mode */
1900 target_ulong helper_load_dcr (target_ulong dcrn)
1901 {
1902 target_ulong val = 0;
1903
1904 if (unlikely(env->dcr_env == NULL)) {
1905 if (loglevel != 0) {
1906 fprintf(logfile, "No DCR environment\n");
1907 }
1908 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1909 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1910 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
1911 if (loglevel != 0) {
1912 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
1913 }
1914 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1915 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1916 }
1917 return val;
1918 }
1919
1920 void helper_store_dcr (target_ulong dcrn, target_ulong val)
1921 {
1922 if (unlikely(env->dcr_env == NULL)) {
1923 if (loglevel != 0) {
1924 fprintf(logfile, "No DCR environment\n");
1925 }
1926 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1927 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1928 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
1929 if (loglevel != 0) {
1930 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
1931 }
1932 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1933 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1934 }
1935 }
1936
1937 #if !defined(CONFIG_USER_ONLY)
1938 void helper_40x_rfci (void)
1939 {
1940 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1941 ~((target_ulong)0xFFFF0000), 0);
1942 }
1943
1944 void helper_rfci (void)
1945 {
1946 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1947 ~((target_ulong)0x3FFF0000), 0);
1948 }
1949
1950 void helper_rfdi (void)
1951 {
1952 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1953 ~((target_ulong)0x3FFF0000), 0);
1954 }
1955
1956 void helper_rfmci (void)
1957 {
1958 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1959 ~((target_ulong)0x3FFF0000), 0);
1960 }
1961 #endif
1962
1963 /* 440 specific */
1964 target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
1965 {
1966 target_ulong mask;
1967 int i;
1968
1969 i = 1;
1970 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1971 if ((high & mask) == 0) {
1972 if (update_Rc) {
1973 env->crf[0] = 0x4;
1974 }
1975 goto done;
1976 }
1977 i++;
1978 }
1979 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1980 if ((low & mask) == 0) {
1981 if (update_Rc) {
1982 env->crf[0] = 0x8;
1983 }
1984 goto done;
1985 }
1986 i++;
1987 }
1988 if (update_Rc) {
1989 env->crf[0] = 0x2;
1990 }
1991 done:
1992 env->xer = (env->xer & ~0x7F) | i;
1993 if (update_Rc) {
1994 env->crf[0] |= xer_so;
1995 }
1996 return i;
1997 }
1998
1999 /*****************************************************************************/
2000 /* SPE extension helpers */
2001 /* Use a table to make this quicker */
2002 static uint8_t hbrev[16] = {
2003 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2004 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2005 };
2006
2007 static always_inline uint8_t byte_reverse (uint8_t val)
2008 {
2009 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
2010 }
2011
2012 static always_inline uint32_t word_reverse (uint32_t val)
2013 {
2014 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
2015 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
2016 }
2017
2018 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
2019 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
2020 {
2021 uint32_t a, b, d, mask;
2022
2023 mask = UINT32_MAX >> (32 - MASKBITS);
2024 a = arg1 & mask;
2025 b = arg2 & mask;
2026 d = word_reverse(1 + word_reverse(a | ~b));
2027 return (arg1 & ~mask) | (d & b);
2028 }
2029
2030 uint32_t helper_cntlsw32 (uint32_t val)
2031 {
2032 if (val & 0x80000000)
2033 return clz32(~val);
2034 else
2035 return clz32(val);
2036 }
2037
2038 uint32_t helper_cntlzw32 (uint32_t val)
2039 {
2040 return clz32(val);
2041 }
2042
2043 /* Single-precision floating-point conversions */
2044 static always_inline uint32_t efscfsi (uint32_t val)
2045 {
2046 CPU_FloatU u;
2047
2048 u.f = int32_to_float32(val, &env->spe_status);
2049
2050 return u.l;
2051 }
2052
2053 static always_inline uint32_t efscfui (uint32_t val)
2054 {
2055 CPU_FloatU u;
2056
2057 u.f = uint32_to_float32(val, &env->spe_status);
2058
2059 return u.l;
2060 }
2061
2062 static always_inline int32_t efsctsi (uint32_t val)
2063 {
2064 CPU_FloatU u;
2065
2066 u.l = val;
2067 /* NaN are not treated the same way IEEE 754 does */
2068 if (unlikely(float32_is_nan(u.f)))
2069 return 0;
2070
2071 return float32_to_int32(u.f, &env->spe_status);
2072 }
2073
2074 static always_inline uint32_t efsctui (uint32_t val)
2075 {
2076 CPU_FloatU u;
2077
2078 u.l = val;
2079 /* NaN are not treated the same way IEEE 754 does */
2080 if (unlikely(float32_is_nan(u.f)))
2081 return 0;
2082
2083 return float32_to_uint32(u.f, &env->spe_status);
2084 }
2085
2086 static always_inline uint32_t efsctsiz (uint32_t val)
2087 {
2088 CPU_FloatU u;
2089
2090 u.l = val;
2091 /* NaN are not treated the same way IEEE 754 does */
2092 if (unlikely(float32_is_nan(u.f)))
2093 return 0;
2094
2095 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2096 }
2097
2098 static always_inline uint32_t efsctuiz (uint32_t val)
2099 {
2100 CPU_FloatU u;
2101
2102 u.l = val;
2103 /* NaN are not treated the same way IEEE 754 does */
2104 if (unlikely(float32_is_nan(u.f)))
2105 return 0;
2106
2107 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2108 }
2109
2110 static always_inline uint32_t efscfsf (uint32_t val)
2111 {
2112 CPU_FloatU u;
2113 float32 tmp;
2114
2115 u.f = int32_to_float32(val, &env->spe_status);
2116 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2117 u.f = float32_div(u.f, tmp, &env->spe_status);
2118
2119 return u.l;
2120 }
2121
2122 static always_inline uint32_t efscfuf (uint32_t val)
2123 {
2124 CPU_FloatU u;
2125 float32 tmp;
2126
2127 u.f = uint32_to_float32(val, &env->spe_status);
2128 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2129 u.f = float32_div(u.f, tmp, &env->spe_status);
2130
2131 return u.l;
2132 }
2133
2134 static always_inline uint32_t efsctsf (uint32_t val)
2135 {
2136 CPU_FloatU u;
2137 float32 tmp;
2138
2139 u.l = val;
2140 /* NaN are not treated the same way IEEE 754 does */
2141 if (unlikely(float32_is_nan(u.f)))
2142 return 0;
2143 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2144 u.f = float32_mul(u.f, tmp, &env->spe_status);
2145
2146 return float32_to_int32(u.f, &env->spe_status);
2147 }
2148
2149 static always_inline uint32_t efsctuf (uint32_t val)
2150 {
2151 CPU_FloatU u;
2152 float32 tmp;
2153
2154 u.l = val;
2155 /* NaN are not treated the same way IEEE 754 does */
2156 if (unlikely(float32_is_nan(u.f)))
2157 return 0;
2158 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2159 u.f = float32_mul(u.f, tmp, &env->spe_status);
2160
2161 return float32_to_uint32(u.f, &env->spe_status);
2162 }
2163
2164 #define HELPER_SPE_SINGLE_CONV(name) \
2165 uint32_t helper_e##name (uint32_t val) \
2166 { \
2167 return e##name(val); \
2168 }
2169 /* efscfsi */
2170 HELPER_SPE_SINGLE_CONV(fscfsi);
2171 /* efscfui */
2172 HELPER_SPE_SINGLE_CONV(fscfui);
2173 /* efscfuf */
2174 HELPER_SPE_SINGLE_CONV(fscfuf);
2175 /* efscfsf */
2176 HELPER_SPE_SINGLE_CONV(fscfsf);
2177 /* efsctsi */
2178 HELPER_SPE_SINGLE_CONV(fsctsi);
2179 /* efsctui */
2180 HELPER_SPE_SINGLE_CONV(fsctui);
2181 /* efsctsiz */
2182 HELPER_SPE_SINGLE_CONV(fsctsiz);
2183 /* efsctuiz */
2184 HELPER_SPE_SINGLE_CONV(fsctuiz);
2185 /* efsctsf */
2186 HELPER_SPE_SINGLE_CONV(fsctsf);
2187 /* efsctuf */
2188 HELPER_SPE_SINGLE_CONV(fsctuf);
2189
2190 #define HELPER_SPE_VECTOR_CONV(name) \
2191 uint64_t helper_ev##name (uint64_t val) \
2192 { \
2193 return ((uint64_t)e##name(val >> 32) << 32) | \
2194 (uint64_t)e##name(val); \
2195 }
2196 /* evfscfsi */
2197 HELPER_SPE_VECTOR_CONV(fscfsi);
2198 /* evfscfui */
2199 HELPER_SPE_VECTOR_CONV(fscfui);
2200 /* evfscfuf */
2201 HELPER_SPE_VECTOR_CONV(fscfuf);
2202 /* evfscfsf */
2203 HELPER_SPE_VECTOR_CONV(fscfsf);
2204 /* evfsctsi */
2205 HELPER_SPE_VECTOR_CONV(fsctsi);
2206 /* evfsctui */
2207 HELPER_SPE_VECTOR_CONV(fsctui);
2208 /* evfsctsiz */
2209 HELPER_SPE_VECTOR_CONV(fsctsiz);
2210 /* evfsctuiz */
2211 HELPER_SPE_VECTOR_CONV(fsctuiz);
2212 /* evfsctsf */
2213 HELPER_SPE_VECTOR_CONV(fsctsf);
2214 /* evfsctuf */
2215 HELPER_SPE_VECTOR_CONV(fsctuf);
2216
2217 /* Single-precision floating-point arithmetic */
2218 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2219 {
2220 CPU_FloatU u1, u2;
2221 u1.l = op1;
2222 u2.l = op2;
2223 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2224 return u1.l;
2225 }
2226
2227 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2228 {
2229 CPU_FloatU u1, u2;
2230 u1.l = op1;
2231 u2.l = op2;
2232 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2233 return u1.l;
2234 }
2235
2236 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
2237 {
2238 CPU_FloatU u1, u2;
2239 u1.l = op1;
2240 u2.l = op2;
2241 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2242 return u1.l;
2243 }
2244
2245 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
2246 {
2247 CPU_FloatU u1, u2;
2248 u1.l = op1;
2249 u2.l = op2;
2250 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2251 return u1.l;
2252 }
2253
2254 #define HELPER_SPE_SINGLE_ARITH(name) \
2255 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2256 { \
2257 return e##name(op1, op2); \
2258 }
2259 /* efsadd */
2260 HELPER_SPE_SINGLE_ARITH(fsadd);
2261 /* efssub */
2262 HELPER_SPE_SINGLE_ARITH(fssub);
2263 /* efsmul */
2264 HELPER_SPE_SINGLE_ARITH(fsmul);
2265 /* efsdiv */
2266 HELPER_SPE_SINGLE_ARITH(fsdiv);
2267
2268 #define HELPER_SPE_VECTOR_ARITH(name) \
2269 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2270 { \
2271 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2272 (uint64_t)e##name(op1, op2); \
2273 }
2274 /* evfsadd */
2275 HELPER_SPE_VECTOR_ARITH(fsadd);
2276 /* evfssub */
2277 HELPER_SPE_VECTOR_ARITH(fssub);
2278 /* evfsmul */
2279 HELPER_SPE_VECTOR_ARITH(fsmul);
2280 /* evfsdiv */
2281 HELPER_SPE_VECTOR_ARITH(fsdiv);
2282
2283 /* Single-precision floating-point comparisons */
2284 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
2285 {
2286 CPU_FloatU u1, u2;
2287 u1.l = op1;
2288 u2.l = op2;
2289 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2290 }
2291
2292 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
2293 {
2294 CPU_FloatU u1, u2;
2295 u1.l = op1;
2296 u2.l = op2;
2297 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
2298 }
2299
2300 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
2301 {
2302 CPU_FloatU u1, u2;
2303 u1.l = op1;
2304 u2.l = op2;
2305 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2306 }
2307
2308 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
2309 {
2310 /* XXX: TODO: test special values (NaN, infinites, ...) */
2311 return efststlt(op1, op2);
2312 }
2313
2314 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
2315 {
2316 /* XXX: TODO: test special values (NaN, infinites, ...) */
2317 return efststgt(op1, op2);
2318 }
2319
2320 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
2321 {
2322 /* XXX: TODO: test special values (NaN, infinites, ...) */
2323 return efststeq(op1, op2);
2324 }
2325
2326 #define HELPER_SINGLE_SPE_CMP(name) \
2327 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2328 { \
2329 return e##name(op1, op2) << 2; \
2330 }
2331 /* efststlt */
2332 HELPER_SINGLE_SPE_CMP(fststlt);
2333 /* efststgt */
2334 HELPER_SINGLE_SPE_CMP(fststgt);
2335 /* efststeq */
2336 HELPER_SINGLE_SPE_CMP(fststeq);
2337 /* efscmplt */
2338 HELPER_SINGLE_SPE_CMP(fscmplt);
2339 /* efscmpgt */
2340 HELPER_SINGLE_SPE_CMP(fscmpgt);
2341 /* efscmpeq */
2342 HELPER_SINGLE_SPE_CMP(fscmpeq);
2343
2344 static always_inline uint32_t evcmp_merge (int t0, int t1)
2345 {
2346 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2347 }
2348
2349 #define HELPER_VECTOR_SPE_CMP(name) \
2350 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2351 { \
2352 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2353 }
2354 /* evfststlt */
2355 HELPER_VECTOR_SPE_CMP(fststlt);
2356 /* evfststgt */
2357 HELPER_VECTOR_SPE_CMP(fststgt);
2358 /* evfststeq */
2359 HELPER_VECTOR_SPE_CMP(fststeq);
2360 /* evfscmplt */
2361 HELPER_VECTOR_SPE_CMP(fscmplt);
2362 /* evfscmpgt */
2363 HELPER_VECTOR_SPE_CMP(fscmpgt);
2364 /* evfscmpeq */
2365 HELPER_VECTOR_SPE_CMP(fscmpeq);
2366
2367 /* Double-precision floating-point conversion */
2368 uint64_t helper_efdcfsi (uint32_t val)
2369 {
2370 CPU_DoubleU u;
2371
2372 u.d = int32_to_float64(val, &env->spe_status);
2373
2374 return u.ll;
2375 }
2376
2377 uint64_t helper_efdcfsid (uint64_t val)
2378 {
2379 CPU_DoubleU u;
2380
2381 u.d = int64_to_float64(val, &env->spe_status);
2382
2383 return u.ll;
2384 }
2385
2386 uint64_t helper_efdcfui (uint32_t val)
2387 {
2388 CPU_DoubleU u;
2389
2390 u.d = uint32_to_float64(val, &env->spe_status);
2391
2392 return u.ll;
2393 }
2394
2395 uint64_t helper_efdcfuid (uint64_t val)
2396 {
2397 CPU_DoubleU u;
2398
2399 u.d = uint64_to_float64(val, &env->spe_status);
2400
2401 return u.ll;
2402 }
2403
2404 uint32_t helper_efdctsi (uint64_t val)
2405 {
2406 CPU_DoubleU u;
2407
2408 u.ll = val;
2409 /* NaN are not treated the same way IEEE 754 does */
2410 if (unlikely(float64_is_nan(u.d)))
2411 return 0;
2412
2413 return float64_to_int32(u.d, &env->spe_status);
2414 }
2415
2416 uint32_t helper_efdctui (uint64_t val)
2417 {
2418 CPU_DoubleU u;
2419
2420 u.ll = val;
2421 /* NaN are not treated the same way IEEE 754 does */
2422 if (unlikely(float64_is_nan(u.d)))
2423 return 0;
2424
2425 return float64_to_uint32(u.d, &env->spe_status);
2426 }
2427
2428 uint32_t helper_efdctsiz (uint64_t val)
2429 {
2430 CPU_DoubleU u;
2431
2432 u.ll = val;
2433 /* NaN are not treated the same way IEEE 754 does */
2434 if (unlikely(float64_is_nan(u.d)))
2435 return 0;
2436
2437 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2438 }
2439
2440 uint64_t helper_efdctsidz (uint64_t val)
2441 {
2442 CPU_DoubleU u;
2443
2444 u.ll = val;
2445 /* NaN are not treated the same way IEEE 754 does */
2446 if (unlikely(float64_is_nan(u.d)))
2447 return 0;
2448
2449 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2450 }
2451
2452 uint32_t helper_efdctuiz (uint64_t val)
2453 {
2454 CPU_DoubleU u;
2455
2456 u.ll = val;
2457 /* NaN are not treated the same way IEEE 754 does */
2458 if (unlikely(float64_is_nan(u.d)))
2459 return 0;
2460
2461 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2462 }
2463
2464 uint64_t helper_efdctuidz (uint64_t val)
2465 {
2466 CPU_DoubleU u;
2467
2468 u.ll = val;
2469 /* NaN are not treated the same way IEEE 754 does */
2470 if (unlikely(float64_is_nan(u.d)))
2471 return 0;
2472
2473 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2474 }
2475
2476 uint64_t helper_efdcfsf (uint32_t val)
2477 {
2478 CPU_DoubleU u;
2479 float64 tmp;
2480
2481 u.d = int32_to_float64(val, &env->spe_status);
2482 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2483 u.d = float64_div(u.d, tmp, &env->spe_status);
2484
2485 return u.ll;
2486 }
2487
2488 uint64_t helper_efdcfuf (uint32_t val)
2489 {
2490 CPU_DoubleU u;
2491 float64 tmp;
2492
2493 u.d = uint32_to_float64(val, &env->spe_status);
2494 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2495 u.d = float64_div(u.d, tmp, &env->spe_status);
2496
2497 return u.ll;
2498 }
2499
2500 uint32_t helper_efdctsf (uint64_t val)
2501 {
2502 CPU_DoubleU u;
2503 float64 tmp;
2504
2505 u.ll = val;
2506 /* NaN are not treated the same way IEEE 754 does */
2507 if (unlikely(float64_is_nan(u.d)))
2508 return 0;
2509 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2510 u.d = float64_mul(u.d, tmp, &env->spe_status);
2511
2512 return float64_to_int32(u.d, &env->spe_status);
2513 }
2514
2515 uint32_t helper_efdctuf (uint64_t val)
2516 {
2517 CPU_DoubleU u;
2518 float64 tmp;
2519
2520 u.ll = val;
2521 /* NaN are not treated the same way IEEE 754 does */
2522 if (unlikely(float64_is_nan(u.d)))
2523 return 0;
2524 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2525 u.d = float64_mul(u.d, tmp, &env->spe_status);
2526
2527 return float64_to_uint32(u.d, &env->spe_status);
2528 }
2529
2530 uint32_t helper_efscfd (uint64_t val)
2531 {
2532 CPU_DoubleU u1;
2533 CPU_FloatU u2;
2534
2535 u1.ll = val;
2536 u2.f = float64_to_float32(u1.d, &env->spe_status);
2537
2538 return u2.l;
2539 }
2540
2541 uint64_t helper_efdcfs (uint32_t val)
2542 {
2543 CPU_DoubleU u2;
2544 CPU_FloatU u1;
2545
2546 u1.l = val;
2547 u2.d = float32_to_float64(u1.f, &env->spe_status);
2548
2549 return u2.ll;
2550 }
2551
2552 /* Double precision fixed-point arithmetic */
2553 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
2554 {
2555 CPU_DoubleU u1, u2;
2556 u1.ll = op1;
2557 u2.ll = op2;
2558 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2559 return u1.ll;
2560 }
2561
2562 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
2563 {
2564 CPU_DoubleU u1, u2;
2565 u1.ll = op1;
2566 u2.ll = op2;
2567 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2568 return u1.ll;
2569 }
2570
2571 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2572 {
2573 CPU_DoubleU u1, u2;
2574 u1.ll = op1;
2575 u2.ll = op2;
2576 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2577 return u1.ll;
2578 }
2579
2580 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2581 {
2582 CPU_DoubleU u1, u2;
2583 u1.ll = op1;
2584 u2.ll = op2;
2585 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2586 return u1.ll;
2587 }
2588
2589 /* Double precision floating point helpers */
2590 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2591 {
2592 CPU_DoubleU u1, u2;
2593 u1.ll = op1;
2594 u2.ll = op2;
2595 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2596 }
2597
2598 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2599 {
2600 CPU_DoubleU u1, u2;
2601 u1.ll = op1;
2602 u2.ll = op2;
2603 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2604 }
2605
2606 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2607 {
2608 CPU_DoubleU u1, u2;
2609 u1.ll = op1;
2610 u2.ll = op2;
2611 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2612 }
2613
2614 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
2615 {
2616 /* XXX: TODO: test special values (NaN, infinites, ...) */
2617 return helper_efdtstlt(op1, op2);
2618 }
2619
2620 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2621 {
2622 /* XXX: TODO: test special values (NaN, infinites, ...) */
2623 return helper_efdtstgt(op1, op2);
2624 }
2625
2626 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2627 {
2628 /* XXX: TODO: test special values (NaN, infinites, ...) */
2629 return helper_efdtsteq(op1, op2);
2630 }
2631
2632 /*****************************************************************************/
2633 /* Softmmu support */
2634 #if !defined (CONFIG_USER_ONLY)
2635
2636 #define MMUSUFFIX _mmu
2637
2638 #define SHIFT 0
2639 #include "softmmu_template.h"
2640
2641 #define SHIFT 1
2642 #include "softmmu_template.h"
2643
2644 #define SHIFT 2
2645 #include "softmmu_template.h"
2646
2647 #define SHIFT 3
2648 #include "softmmu_template.h"
2649
2650 /* try to fill the TLB and return an exception if error. If retaddr is
2651 NULL, it means that the function was called in C code (i.e. not
2652 from generated code or from helper.c) */
2653 /* XXX: fix it to restore all registers */
2654 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2655 {
2656 TranslationBlock *tb;
2657 CPUState *saved_env;
2658 unsigned long pc;
2659 int ret;
2660
2661 /* XXX: hack to restore env in all cases, even if not called from
2662 generated code */
2663 saved_env = env;
2664 env = cpu_single_env;
2665 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2666 if (unlikely(ret != 0)) {
2667 if (likely(retaddr)) {
2668 /* now we have a real cpu fault */
2669 pc = (unsigned long)retaddr;
2670 tb = tb_find_pc(pc);
2671 if (likely(tb)) {
2672 /* the PC is inside the translated code. It means that we have
2673 a virtual CPU fault */
2674 cpu_restore_state(tb, env, pc, NULL);
2675 }
2676 }
2677 helper_raise_exception_err(env->exception_index, env->error_code);
2678 }
2679 env = saved_env;
2680 }
2681
2682 /* Segment registers load and store */
2683 target_ulong helper_load_sr (target_ulong sr_num)
2684 {
2685 return env->sr[sr_num];
2686 }
2687
2688 void helper_store_sr (target_ulong sr_num, target_ulong val)
2689 {
2690 ppc_store_sr(env, sr_num, val);
2691 }
2692
2693 /* SLB management */
2694 #if defined(TARGET_PPC64)
2695 target_ulong helper_load_slb (target_ulong slb_nr)
2696 {
2697 return ppc_load_slb(env, slb_nr);
2698 }
2699
2700 void helper_store_slb (target_ulong slb_nr, target_ulong rs)
2701 {
2702 ppc_store_slb(env, slb_nr, rs);
2703 }
2704
2705 void helper_slbia (void)
2706 {
2707 ppc_slb_invalidate_all(env);
2708 }
2709
2710 void helper_slbie (target_ulong addr)
2711 {
2712 ppc_slb_invalidate_one(env, addr);
2713 }
2714
2715 #endif /* defined(TARGET_PPC64) */
2716
2717 /* TLB management */
2718 void helper_tlbia (void)
2719 {
2720 ppc_tlb_invalidate_all(env);
2721 }
2722
2723 void helper_tlbie (target_ulong addr)
2724 {
2725 ppc_tlb_invalidate_one(env, addr);
2726 }
2727
2728 /* Software driven TLBs management */
2729 /* PowerPC 602/603 software TLB load instructions helpers */
2730 static void do_6xx_tlb (target_ulong new_EPN, int is_code)
2731 {
2732 target_ulong RPN, CMP, EPN;
2733 int way;
2734
2735 RPN = env->spr[SPR_RPA];
2736 if (is_code) {
2737 CMP = env->spr[SPR_ICMP];
2738 EPN = env->spr[SPR_IMISS];
2739 } else {
2740 CMP = env->spr[SPR_DCMP];
2741 EPN = env->spr[SPR_DMISS];
2742 }
2743 way = (env->spr[SPR_SRR1] >> 17) & 1;
2744 #if defined (DEBUG_SOFTWARE_TLB)
2745 if (loglevel != 0) {
2746 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2747 " PTE1 " ADDRX " way %d\n",
2748 __func__, new_EPN, EPN, CMP, RPN, way);
2749 }
2750 #endif
2751 /* Store this TLB */
2752 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2753 way, is_code, CMP, RPN);
2754 }
2755
2756 void helper_6xx_tlbd (target_ulong EPN)
2757 {
2758 do_6xx_tlb(EPN, 0);
2759 }
2760
2761 void helper_6xx_tlbi (target_ulong EPN)
2762 {
2763 do_6xx_tlb(EPN, 1);
2764 }
2765
2766 /* PowerPC 74xx software TLB load instructions helpers */
2767 static void do_74xx_tlb (target_ulong new_EPN, int is_code)
2768 {
2769 target_ulong RPN, CMP, EPN;
2770 int way;
2771
2772 RPN = env->spr[SPR_PTELO];
2773 CMP = env->spr[SPR_PTEHI];
2774 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2775 way = env->spr[SPR_TLBMISS] & 0x3;
2776 #if defined (DEBUG_SOFTWARE_TLB)
2777 if (loglevel != 0) {
2778 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2779 " PTE1 " ADDRX " way %d\n",
2780 __func__, new_EPN, EPN, CMP, RPN, way);
2781 }
2782 #endif
2783 /* Store this TLB */
2784 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2785 way, is_code, CMP, RPN);
2786 }
2787
2788 void helper_74xx_tlbd (target_ulong EPN)
2789 {
2790 do_74xx_tlb(EPN, 0);
2791 }
2792
2793 void helper_74xx_tlbi (target_ulong EPN)
2794 {
2795 do_74xx_tlb(EPN, 1);
2796 }
2797
2798 static always_inline target_ulong booke_tlb_to_page_size (int size)
2799 {
2800 return 1024 << (2 * size);
2801 }
2802
2803 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2804 {
2805 int size;
2806
2807 switch (page_size) {
2808 case 0x00000400UL:
2809 size = 0x0;
2810 break;
2811 case 0x00001000UL:
2812 size = 0x1;
2813 break;
2814 case 0x00004000UL:
2815 size = 0x2;
2816 break;
2817 case 0x00010000UL:
2818 size = 0x3;
2819 break;
2820 case 0x00040000UL:
2821 size = 0x4;
2822 break;
2823 case 0x00100000UL:
2824 size = 0x5;
2825 break;
2826 case 0x00400000UL:
2827 size = 0x6;
2828 break;
2829 case 0x01000000UL:
2830 size = 0x7;
2831 break;
2832 case 0x04000000UL:
2833 size = 0x8;
2834 break;
2835 case 0x10000000UL:
2836 size = 0x9;
2837 break;
2838 case 0x40000000UL:
2839 size = 0xA;
2840 break;
2841 #if defined (TARGET_PPC64)
2842 case 0x000100000000ULL:
2843 size = 0xB;
2844 break;
2845 case 0x000400000000ULL:
2846 size = 0xC;
2847 break;
2848 case 0x001000000000ULL:
2849 size = 0xD;
2850 break;
2851 case 0x004000000000ULL:
2852 size = 0xE;
2853 break;
2854 case 0x010000000000ULL:
2855 size = 0xF;
2856 break;
2857 #endif
2858 default:
2859 size = -1;
2860 break;
2861 }
2862
2863 return size;
2864 }
2865
2866 /* Helpers for 4xx TLB management */
2867 target_ulong helper_4xx_tlbre_lo (target_ulong entry)
2868 {
2869 ppcemb_tlb_t *tlb;
2870 target_ulong ret;
2871 int size;
2872
2873 entry &= 0x3F;
2874 tlb = &env->tlb[entry].tlbe;
2875 ret = tlb->EPN;
2876 if (tlb->prot & PAGE_VALID)
2877 ret |= 0x400;
2878 size = booke_page_size_to_tlb(tlb->size);
2879 if (size < 0 || size > 0x7)
2880 size = 1;
2881 ret |= size << 7;
2882 env->spr[SPR_40x_PID] = tlb->PID;
2883 return ret;
2884 }
2885
2886 target_ulong helper_4xx_tlbre_hi (target_ulong entry)
2887 {
2888 ppcemb_tlb_t *tlb;
2889 target_ulong ret;
2890
2891 entry &= 0x3F;
2892 tlb = &env->tlb[entry].tlbe;
2893 ret = tlb->RPN;
2894 if (tlb->prot & PAGE_EXEC)
2895 ret |= 0x200;
2896 if (tlb->prot & PAGE_WRITE)
2897 ret |= 0x100;
2898 return ret;
2899 }
2900
2901 void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
2902 {
2903 ppcemb_tlb_t *tlb;
2904 target_ulong page, end;
2905
2906 #if defined (DEBUG_SOFTWARE_TLB)
2907 if (loglevel != 0) {
2908 fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
2909 }
2910 #endif
2911 entry &= 0x3F;
2912 tlb = &env->tlb[entry].tlbe;
2913 /* Invalidate previous TLB (if it's valid) */
2914 if (tlb->prot & PAGE_VALID) {
2915 end = tlb->EPN + tlb->size;
2916 #if defined (DEBUG_SOFTWARE_TLB)
2917 if (loglevel != 0) {
2918 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2919 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2920 }
2921 #endif
2922 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2923 tlb_flush_page(env, page);
2924 }
2925 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
2926 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2927 * If this ever occurs, one should use the ppcemb target instead
2928 * of the ppc or ppc64 one
2929 */
2930 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2931 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2932 "are not supported (%d)\n",
2933 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
2934 }
2935 tlb->EPN = val & ~(tlb->size - 1);
2936 if (val & 0x40)
2937 tlb->prot |= PAGE_VALID;
2938 else
2939 tlb->prot &= ~PAGE_VALID;
2940 if (val & 0x20) {
2941 /* XXX: TO BE FIXED */
2942 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2943 }
2944 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2945 tlb->attr = val & 0xFF;
2946 #if defined (DEBUG_SOFTWARE_TLB)
2947 if (loglevel != 0) {
2948 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2949 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2950 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2951 tlb->prot & PAGE_READ ? 'r' : '-',
2952 tlb->prot & PAGE_WRITE ? 'w' : '-',
2953 tlb->prot & PAGE_EXEC ? 'x' : '-',
2954 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2955 }
2956 #endif
2957 /* Invalidate new TLB (if valid) */
2958 if (tlb->prot & PAGE_VALID) {
2959 end = tlb->EPN + tlb->size;
2960 #if defined (DEBUG_SOFTWARE_TLB)
2961 if (loglevel != 0) {
2962 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2963 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2964 }
2965 #endif
2966 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2967 tlb_flush_page(env, page);
2968 }
2969 }
2970
2971 void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
2972 {
2973 ppcemb_tlb_t *tlb;
2974
2975 #if defined (DEBUG_SOFTWARE_TLB)
2976 if (loglevel != 0) {
2977 fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
2978 }
2979 #endif
2980 entry &= 0x3F;
2981 tlb = &env->tlb[entry].tlbe;
2982 tlb->RPN = val & 0xFFFFFC00;
2983 tlb->prot = PAGE_READ;
2984 if (val & 0x200)
2985 tlb->prot |= PAGE_EXEC;
2986 if (val & 0x100)
2987 tlb->prot |= PAGE_WRITE;
2988 #if defined (DEBUG_SOFTWARE_TLB)
2989 if (loglevel != 0) {
2990 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2991 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2992 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2993 tlb->prot & PAGE_READ ? 'r' : '-',
2994 tlb->prot & PAGE_WRITE ? 'w' : '-',
2995 tlb->prot & PAGE_EXEC ? 'x' : '-',
2996 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2997 }
2998 #endif
2999 }
3000
3001 target_ulong helper_4xx_tlbsx (target_ulong address)
3002 {
3003 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
3004 }
3005
3006 /* PowerPC 440 TLB management */
3007 void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
3008 {
3009 ppcemb_tlb_t *tlb;
3010 target_ulong EPN, RPN, size;
3011 int do_flush_tlbs;
3012
3013 #if defined (DEBUG_SOFTWARE_TLB)
3014 if (loglevel != 0) {
3015 fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
3016 __func__, word, (int)entry, value);
3017 }
3018 #endif
3019 do_flush_tlbs = 0;
3020 entry &= 0x3F;
3021 tlb = &env->tlb[entry].tlbe;
3022 switch (word) {
3023 default:
3024 /* Just here to please gcc */
3025 case 0:
3026 EPN = value & 0xFFFFFC00;
3027 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
3028 do_flush_tlbs = 1;
3029 tlb->EPN = EPN;
3030 size = booke_tlb_to_page_size((value >> 4) & 0xF);
3031 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3032 do_flush_tlbs = 1;
3033 tlb->size = size;
3034 tlb->attr &= ~0x1;
3035 tlb->attr |= (value >> 8) & 1;
3036 if (value & 0x200) {
3037 tlb->prot |= PAGE_VALID;
3038 } else {
3039 if (tlb->prot & PAGE_VALID) {
3040 tlb->prot &= ~PAGE_VALID;
3041 do_flush_tlbs = 1;
3042 }
3043 }
3044 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3045 if (do_flush_tlbs)
3046 tlb_flush(env, 1);
3047 break;
3048 case 1:
3049 RPN = value & 0xFFFFFC0F;
3050 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3051 tlb_flush(env, 1);
3052 tlb->RPN = RPN;
3053 break;
3054 case 2:
3055 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
3056 tlb->prot = tlb->prot & PAGE_VALID;
3057 if (value & 0x1)
3058 tlb->prot |= PAGE_READ << 4;
3059 if (value & 0x2)
3060 tlb->prot |= PAGE_WRITE << 4;
3061 if (value & 0x4)
3062 tlb->prot |= PAGE_EXEC << 4;
3063 if (value & 0x8)
3064 tlb->prot |= PAGE_READ;
3065 if (value & 0x10)
3066 tlb->prot |= PAGE_WRITE;
3067 if (value & 0x20)
3068 tlb->prot |= PAGE_EXEC;
3069 break;
3070 }
3071 }
3072
3073 target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
3074 {
3075 ppcemb_tlb_t *tlb;
3076 target_ulong ret;
3077 int size;
3078
3079 entry &= 0x3F;
3080 tlb = &env->tlb[entry].tlbe;
3081 switch (word) {
3082 default:
3083 /* Just here to please gcc */
3084 case 0:
3085 ret = tlb->EPN;
3086 size = booke_page_size_to_tlb(tlb->size);
3087 if (size < 0 || size > 0xF)
3088 size = 1;
3089 ret |= size << 4;
3090 if (tlb->attr & 0x1)
3091 ret |= 0x100;
3092 if (tlb->prot & PAGE_VALID)
3093 ret |= 0x200;
3094 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3095 env->spr[SPR_440_MMUCR] |= tlb->PID;
3096 break;
3097 case 1:
3098 ret = tlb->RPN;
3099 break;
3100 case 2:
3101 ret = tlb->attr & ~0x1;
3102 if (tlb->prot & (PAGE_READ << 4))
3103 ret |= 0x1;
3104 if (tlb->prot & (PAGE_WRITE << 4))
3105 ret |= 0x2;
3106 if (tlb->prot & (PAGE_EXEC << 4))
3107 ret |= 0x4;
3108 if (tlb->prot & PAGE_READ)
3109 ret |= 0x8;
3110 if (tlb->prot & PAGE_WRITE)
3111 ret |= 0x10;
3112 if (tlb->prot & PAGE_EXEC)
3113 ret |= 0x20;
3114 break;
3115 }
3116 return ret;
3117 }
3118
3119 target_ulong helper_440_tlbsx (target_ulong address)
3120 {
3121 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
3122 }
3123
3124 #endif /* !CONFIG_USER_ONLY */
Qemu copy for testing