2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 /* Include definitions for instructions classes and implementations flags */
31 //#define DO_SINGLE_STEP
32 //#define PPC_DEBUG_DISAS
33 //#define DEBUG_MEMORY_ACCESSES
34 //#define DO_PPC_STATISTICS
35 //#define OPTIMIZE_FPRF_UPDATE
37 /*****************************************************************************/
38 /* Code translation helpers */
39 #if defined(USE_DIRECT_JUMP)
42 #define TBPARAM(x) (long)(x)
46 #define DEF(s, n, copy_size) INDEX_op_ ## s,
52 static uint16_t *gen_opc_ptr
;
53 static uint32_t *gen_opparam_ptr
;
54 #if defined(OPTIMIZE_FPRF_UPDATE)
55 static uint16_t *gen_fprf_buf
[OPC_BUF_SIZE
];
56 static uint16_t **gen_fprf_ptr
;
61 static always_inline
void gen_set_T0 (target_ulong val
)
63 #if defined(TARGET_PPC64)
65 gen_op_set_T0_64(val
>> 32, val
);
71 static always_inline
void gen_set_T1 (target_ulong val
)
73 #if defined(TARGET_PPC64)
75 gen_op_set_T1_64(val
>> 32, val
);
81 #define GEN8(func, NAME) \
82 static GenOpFunc *NAME ## _table [8] = { \
83 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
84 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
86 static always_inline void func (int n) \
88 NAME ## _table[n](); \
91 #define GEN16(func, NAME) \
92 static GenOpFunc *NAME ## _table [16] = { \
93 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
94 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
95 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
96 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
98 static always_inline void func (int n) \
100 NAME ## _table[n](); \
103 #define GEN32(func, NAME) \
104 static GenOpFunc *NAME ## _table [32] = { \
105 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
106 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
107 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
108 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
109 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
110 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
111 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
112 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
114 static always_inline void func (int n) \
116 NAME ## _table[n](); \
119 /* Condition register moves */
120 GEN8(gen_op_load_crf_T0
, gen_op_load_crf_T0_crf
);
121 GEN8(gen_op_load_crf_T1
, gen_op_load_crf_T1_crf
);
122 GEN8(gen_op_store_T0_crf
, gen_op_store_T0_crf_crf
);
124 GEN8(gen_op_store_T1_crf
, gen_op_store_T1_crf_crf
);
127 /* General purpose registers moves */
128 GEN32(gen_op_load_gpr_T0
, gen_op_load_gpr_T0_gpr
);
129 GEN32(gen_op_load_gpr_T1
, gen_op_load_gpr_T1_gpr
);
130 GEN32(gen_op_load_gpr_T2
, gen_op_load_gpr_T2_gpr
);
132 GEN32(gen_op_store_T0_gpr
, gen_op_store_T0_gpr_gpr
);
133 GEN32(gen_op_store_T1_gpr
, gen_op_store_T1_gpr_gpr
);
135 GEN32(gen_op_store_T2_gpr
, gen_op_store_T2_gpr_gpr
);
138 /* floating point registers moves */
139 GEN32(gen_op_load_fpr_FT0
, gen_op_load_fpr_FT0_fpr
);
140 GEN32(gen_op_load_fpr_FT1
, gen_op_load_fpr_FT1_fpr
);
141 GEN32(gen_op_load_fpr_FT2
, gen_op_load_fpr_FT2_fpr
);
142 GEN32(gen_op_store_FT0_fpr
, gen_op_store_FT0_fpr_fpr
);
143 GEN32(gen_op_store_FT1_fpr
, gen_op_store_FT1_fpr_fpr
);
145 GEN32(gen_op_store_FT2_fpr
, gen_op_store_FT2_fpr_fpr
);
148 /* internal defines */
149 typedef struct DisasContext
{
150 struct TranslationBlock
*tb
;
154 /* Routine used to access memory */
156 /* Translation flags */
157 #if !defined(CONFIG_USER_ONLY)
160 #if defined(TARGET_PPC64)
166 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
167 int singlestep_enabled
;
168 int dcache_line_size
;
171 struct opc_handler_t
{
174 /* instruction type */
177 void (*handler
)(DisasContext
*ctx
);
178 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
179 const unsigned char *oname
;
181 #if defined(DO_PPC_STATISTICS)
186 static always_inline
void gen_set_Rc0 (DisasContext
*ctx
)
188 #if defined(TARGET_PPC64)
197 static always_inline
void gen_reset_fpstatus (void)
199 #ifdef CONFIG_SOFTFLOAT
200 gen_op_reset_fpstatus();
204 static always_inline
void gen_compute_fprf (int set_fprf
, int set_rc
)
207 /* This case might be optimized later */
208 #if defined(OPTIMIZE_FPRF_UPDATE)
209 *gen_fprf_ptr
++ = gen_opc_ptr
;
211 gen_op_compute_fprf(1);
212 if (unlikely(set_rc
))
213 gen_op_store_T0_crf(1);
214 gen_op_float_check_status();
215 } else if (unlikely(set_rc
)) {
216 /* We always need to compute fpcc */
217 gen_op_compute_fprf(0);
218 gen_op_store_T0_crf(1);
220 gen_op_float_check_status();
224 static always_inline
void gen_optimize_fprf (void)
226 #if defined(OPTIMIZE_FPRF_UPDATE)
229 for (ptr
= gen_fprf_buf
; ptr
!= (gen_fprf_ptr
- 1); ptr
++)
230 *ptr
= INDEX_op_nop1
;
231 gen_fprf_ptr
= gen_fprf_buf
;
235 static always_inline
void gen_update_nip (DisasContext
*ctx
, target_ulong nip
)
237 #if defined(TARGET_PPC64)
239 gen_op_update_nip_64(nip
>> 32, nip
);
242 gen_op_update_nip(nip
);
245 #define GEN_EXCP(ctx, excp, error) \
247 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
248 gen_update_nip(ctx, (ctx)->nip); \
250 gen_op_raise_exception_err((excp), (error)); \
251 ctx->exception = (excp); \
254 #define GEN_EXCP_INVAL(ctx) \
255 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
256 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
258 #define GEN_EXCP_PRIVOPC(ctx) \
259 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
260 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
262 #define GEN_EXCP_PRIVREG(ctx) \
263 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
264 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
266 #define GEN_EXCP_NO_FP(ctx) \
267 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
269 #define GEN_EXCP_NO_AP(ctx) \
270 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
272 #define GEN_EXCP_NO_VR(ctx) \
273 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
275 /* Stop translation */
276 static always_inline
void GEN_STOP (DisasContext
*ctx
)
278 gen_update_nip(ctx
, ctx
->nip
);
279 ctx
->exception
= POWERPC_EXCP_STOP
;
282 /* No need to update nip here, as execution flow will change */
283 static always_inline
void GEN_SYNC (DisasContext
*ctx
)
285 ctx
->exception
= POWERPC_EXCP_SYNC
;
288 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
289 static void gen_##name (DisasContext *ctx); \
290 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
291 static void gen_##name (DisasContext *ctx)
293 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
294 static void gen_##name (DisasContext *ctx); \
295 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
296 static void gen_##name (DisasContext *ctx)
298 typedef struct opcode_t
{
299 unsigned char opc1
, opc2
, opc3
;
300 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
301 unsigned char pad
[5];
303 unsigned char pad
[1];
305 opc_handler_t handler
;
306 const unsigned char *oname
;
309 /*****************************************************************************/
310 /*** Instruction decoding ***/
311 #define EXTRACT_HELPER(name, shift, nb) \
312 static always_inline uint32_t name (uint32_t opcode) \
314 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
317 #define EXTRACT_SHELPER(name, shift, nb) \
318 static always_inline int32_t name (uint32_t opcode) \
320 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
324 EXTRACT_HELPER(opc1
, 26, 6);
326 EXTRACT_HELPER(opc2
, 1, 5);
328 EXTRACT_HELPER(opc3
, 6, 5);
329 /* Update Cr0 flags */
330 EXTRACT_HELPER(Rc
, 0, 1);
332 EXTRACT_HELPER(rD
, 21, 5);
334 EXTRACT_HELPER(rS
, 21, 5);
336 EXTRACT_HELPER(rA
, 16, 5);
338 EXTRACT_HELPER(rB
, 11, 5);
340 EXTRACT_HELPER(rC
, 6, 5);
342 EXTRACT_HELPER(crfD
, 23, 3);
343 EXTRACT_HELPER(crfS
, 18, 3);
344 EXTRACT_HELPER(crbD
, 21, 5);
345 EXTRACT_HELPER(crbA
, 16, 5);
346 EXTRACT_HELPER(crbB
, 11, 5);
348 EXTRACT_HELPER(_SPR
, 11, 10);
349 static always_inline
uint32_t SPR (uint32_t opcode
)
351 uint32_t sprn
= _SPR(opcode
);
353 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
355 /*** Get constants ***/
356 EXTRACT_HELPER(IMM
, 12, 8);
357 /* 16 bits signed immediate value */
358 EXTRACT_SHELPER(SIMM
, 0, 16);
359 /* 16 bits unsigned immediate value */
360 EXTRACT_HELPER(UIMM
, 0, 16);
362 EXTRACT_HELPER(NB
, 11, 5);
364 EXTRACT_HELPER(SH
, 11, 5);
366 EXTRACT_HELPER(MB
, 6, 5);
368 EXTRACT_HELPER(ME
, 1, 5);
370 EXTRACT_HELPER(TO
, 21, 5);
372 EXTRACT_HELPER(CRM
, 12, 8);
373 EXTRACT_HELPER(FM
, 17, 8);
374 EXTRACT_HELPER(SR
, 16, 4);
375 EXTRACT_HELPER(FPIMM
, 20, 4);
377 /*** Jump target decoding ***/
379 EXTRACT_SHELPER(d
, 0, 16);
380 /* Immediate address */
381 static always_inline target_ulong
LI (uint32_t opcode
)
383 return (opcode
>> 0) & 0x03FFFFFC;
386 static always_inline
uint32_t BD (uint32_t opcode
)
388 return (opcode
>> 0) & 0xFFFC;
391 EXTRACT_HELPER(BO
, 21, 5);
392 EXTRACT_HELPER(BI
, 16, 5);
393 /* Absolute/relative address */
394 EXTRACT_HELPER(AA
, 1, 1);
396 EXTRACT_HELPER(LK
, 0, 1);
398 /* Create a mask between <start> and <end> bits */
399 static always_inline target_ulong
MASK (uint32_t start
, uint32_t end
)
403 #if defined(TARGET_PPC64)
404 if (likely(start
== 0)) {
405 ret
= UINT64_MAX
<< (63 - end
);
406 } else if (likely(end
== 63)) {
407 ret
= UINT64_MAX
>> start
;
410 if (likely(start
== 0)) {
411 ret
= UINT32_MAX
<< (31 - end
);
412 } else if (likely(end
== 31)) {
413 ret
= UINT32_MAX
>> start
;
417 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
418 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
419 if (unlikely(start
> end
))
426 /*****************************************************************************/
427 /* PowerPC Instructions types definitions */
429 PPC_NONE
= 0x0000000000000000ULL
,
430 /* PowerPC base instructions set */
431 PPC_INSNS_BASE
= 0x0000000000000001ULL
,
432 /* integer operations instructions */
433 #define PPC_INTEGER PPC_INSNS_BASE
434 /* flow control instructions */
435 #define PPC_FLOW PPC_INSNS_BASE
436 /* virtual memory instructions */
437 #define PPC_MEM PPC_INSNS_BASE
438 /* ld/st with reservation instructions */
439 #define PPC_RES PPC_INSNS_BASE
440 /* spr/msr access instructions */
441 #define PPC_MISC PPC_INSNS_BASE
442 /* Deprecated instruction sets */
443 /* Original POWER instruction set */
444 PPC_POWER
= 0x0000000000000001ULL
,
445 /* POWER2 instruction set extension */
446 PPC_POWER2
= 0x0000000000000002ULL
,
447 /* Power RTC support */
448 PPC_POWER_RTC
= 0x0000000000000004ULL
,
449 /* Power-to-PowerPC bridge (601) */
450 PPC_POWER_BR
= 0x0000000000000008ULL
,
451 /* 64 bits PowerPC instruction set */
452 PPC_64B
= 0x0000000000000010ULL
,
453 /* New 64 bits extensions (PowerPC 2.0x) */
454 PPC_64BX
= 0x0000000000000020ULL
,
455 /* 64 bits hypervisor extensions */
456 PPC_64H
= 0x0000000000000040ULL
,
457 /* New wait instruction (PowerPC 2.0x) */
458 PPC_WAIT
= 0x0000000000000080ULL
,
459 /* Time base mftb instruction */
460 PPC_MFTB
= 0x0000000000000100ULL
,
462 /* Fixed-point unit extensions */
463 /* PowerPC 602 specific */
464 PPC_602_SPEC
= 0x0000000000000200ULL
,
465 /* PowerPC 2.03 specification extensions */
466 PPC_203
= 0x0000000000000400ULL
,
468 /* Floating-point unit extensions */
469 /* Optional floating point instructions */
470 PPC_FLOAT
= 0x0000000000010000ULL
,
471 /* New floating-point extensions (PowerPC 2.0x) */
472 PPC_FLOAT_EXT
= 0x0000000000020000ULL
,
473 PPC_FLOAT_FSQRT
= 0x0000000000040000ULL
,
474 PPC_FLOAT_FRES
= 0x0000000000080000ULL
,
475 PPC_FLOAT_FRSQRTE
= 0x0000000000100000ULL
,
476 PPC_FLOAT_FRSQRTES
= 0x0000000000200000ULL
,
477 PPC_FLOAT_FSEL
= 0x0000000000400000ULL
,
478 PPC_FLOAT_STFIWX
= 0x0000000000800000ULL
,
480 /* Vector/SIMD extensions */
481 /* Altivec support */
482 PPC_ALTIVEC
= 0x0000000001000000ULL
,
483 /* e500 vector instructions */
484 PPC_E500_VECTOR
= 0x0000000002000000ULL
,
485 /* PowerPC 2.03 SPE extension */
486 PPC_SPE
= 0x0000000004000000ULL
,
487 /* PowerPC 2.03 SPE floating-point extension */
488 PPC_SPEFPU
= 0x0000000008000000ULL
,
490 /* Optional memory control instructions */
491 PPC_MEM_TLBIA
= 0x0000000010000000ULL
,
492 PPC_MEM_TLBIE
= 0x0000000020000000ULL
,
493 PPC_MEM_TLBSYNC
= 0x0000000040000000ULL
,
494 /* sync instruction */
495 PPC_MEM_SYNC
= 0x0000000080000000ULL
,
496 /* eieio instruction */
497 PPC_MEM_EIEIO
= 0x0000000100000000ULL
,
499 /* Cache control instructions */
500 PPC_CACHE
= 0x0000001000000000ULL
,
501 /* icbi instruction */
502 PPC_CACHE_ICBI
= 0x0000002000000000ULL
,
503 /* dcbz instruction with fixed cache line size */
504 PPC_CACHE_DCBZ
= 0x0000004000000000ULL
,
505 /* dcbz instruction with tunable cache line size */
506 PPC_CACHE_DCBZT
= 0x0000008000000000ULL
,
507 /* dcba instruction */
508 PPC_CACHE_DCBA
= 0x0000010000000000ULL
,
510 /* MMU related extensions */
511 /* external control instructions */
512 PPC_EXTERN
= 0x0000100000000000ULL
,
513 /* segment register access instructions */
514 PPC_SEGMENT
= 0x0000200000000000ULL
,
515 /* PowerPC 6xx TLB management instructions */
516 PPC_6xx_TLB
= 0x0000400000000000ULL
,
517 /* PowerPC 74xx TLB management instructions */
518 PPC_74xx_TLB
= 0x0000800000000000ULL
,
519 /* PowerPC 40x TLB management instructions */
520 PPC_40x_TLB
= 0x0001000000000000ULL
,
521 /* segment register access instructions for PowerPC 64 "bridge" */
522 PPC_SEGMENT_64B
= 0x0002000000000000ULL
,
524 PPC_SLBI
= 0x0004000000000000ULL
,
526 /* Embedded PowerPC dedicated instructions */
527 PPC_EMB_COMMON
= 0x0010000000000000ULL
,
528 /* PowerPC 40x exception model */
529 PPC_40x_EXCP
= 0x0020000000000000ULL
,
530 /* PowerPC 405 Mac instructions */
531 PPC_405_MAC
= 0x0040000000000000ULL
,
532 /* PowerPC 440 specific instructions */
533 PPC_440_SPEC
= 0x0080000000000000ULL
,
534 /* BookE (embedded) PowerPC specification */
535 PPC_BOOKE
= 0x0100000000000000ULL
,
536 /* More BookE (embedded) instructions... */
537 PPC_BOOKE_EXT
= 0x0200000000000000ULL
,
538 /* PowerPC 4xx dedicated instructions */
539 PPC_4xx_COMMON
= 0x0400000000000000ULL
,
540 /* PowerPC 40x ibct instructions */
541 PPC_40x_ICBT
= 0x0800000000000000ULL
,
542 /* rfmci is not implemented in all BookE PowerPC */
543 PPC_RFMCI
= 0x1000000000000000ULL
,
544 /* user-mode DCR access, implemented in PowerPC 460 */
545 PPC_DCRUX
= 0x2000000000000000ULL
,
548 /*****************************************************************************/
549 /* PowerPC instructions table */
550 #if HOST_LONG_BITS == 64
555 #if defined(__APPLE__)
556 #define OPCODES_SECTION \
557 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
559 #define OPCODES_SECTION \
560 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
563 #if defined(DO_PPC_STATISTICS)
564 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
565 OPCODES_SECTION opcode_t opc_##name = { \
573 .handler = &gen_##name, \
574 .oname = stringify(name), \
576 .oname = stringify(name), \
578 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
579 OPCODES_SECTION opcode_t opc_##name = { \
587 .handler = &gen_##name, \
593 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
594 OPCODES_SECTION opcode_t opc_##name = { \
602 .handler = &gen_##name, \
604 .oname = stringify(name), \
606 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
607 OPCODES_SECTION opcode_t opc_##name = { \
615 .handler = &gen_##name, \
621 #define GEN_OPCODE_MARK(name) \
622 OPCODES_SECTION opcode_t opc_##name = { \
628 .inval = 0x00000000, \
632 .oname = stringify(name), \
635 /* Start opcode list */
636 GEN_OPCODE_MARK(start
);
638 /* Invalid instruction */
639 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
)
644 static opc_handler_t invalid_handler
= {
647 .handler
= gen_invalid
,
650 /*** Integer arithmetic ***/
651 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
652 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
654 gen_op_load_gpr_T0(rA(ctx->opcode)); \
655 gen_op_load_gpr_T1(rB(ctx->opcode)); \
657 gen_op_store_T0_gpr(rD(ctx->opcode)); \
658 if (unlikely(Rc(ctx->opcode) != 0)) \
662 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
663 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
665 gen_op_load_gpr_T0(rA(ctx->opcode)); \
666 gen_op_load_gpr_T1(rB(ctx->opcode)); \
668 gen_op_store_T0_gpr(rD(ctx->opcode)); \
669 if (unlikely(Rc(ctx->opcode) != 0)) \
673 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
674 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
676 gen_op_load_gpr_T0(rA(ctx->opcode)); \
678 gen_op_store_T0_gpr(rD(ctx->opcode)); \
679 if (unlikely(Rc(ctx->opcode) != 0)) \
682 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
683 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
685 gen_op_load_gpr_T0(rA(ctx->opcode)); \
687 gen_op_store_T0_gpr(rD(ctx->opcode)); \
688 if (unlikely(Rc(ctx->opcode) != 0)) \
692 /* Two operands arithmetic functions */
693 #define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
694 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
695 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
697 /* Two operands arithmetic functions with no overflow allowed */
698 #define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
699 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
701 /* One operand arithmetic functions */
702 #define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
703 __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
704 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
706 #if defined(TARGET_PPC64)
707 #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
708 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
710 gen_op_load_gpr_T0(rA(ctx->opcode)); \
711 gen_op_load_gpr_T1(rB(ctx->opcode)); \
713 gen_op_##name##_64(); \
716 gen_op_store_T0_gpr(rD(ctx->opcode)); \
717 if (unlikely(Rc(ctx->opcode) != 0)) \
721 #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
722 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
724 gen_op_load_gpr_T0(rA(ctx->opcode)); \
725 gen_op_load_gpr_T1(rB(ctx->opcode)); \
727 gen_op_##name##_64(); \
730 gen_op_store_T0_gpr(rD(ctx->opcode)); \
731 if (unlikely(Rc(ctx->opcode) != 0)) \
735 #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
736 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
738 gen_op_load_gpr_T0(rA(ctx->opcode)); \
740 gen_op_##name##_64(); \
743 gen_op_store_T0_gpr(rD(ctx->opcode)); \
744 if (unlikely(Rc(ctx->opcode) != 0)) \
747 #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
748 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
750 gen_op_load_gpr_T0(rA(ctx->opcode)); \
752 gen_op_##name##_64(); \
755 gen_op_store_T0_gpr(rD(ctx->opcode)); \
756 if (unlikely(Rc(ctx->opcode) != 0)) \
760 /* Two operands arithmetic functions */
761 #define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
762 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
763 __GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
765 /* Two operands arithmetic functions with no overflow allowed */
766 #define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
767 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
769 /* One operand arithmetic functions */
770 #define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
771 __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
772 __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
774 #define GEN_INT_ARITH2_64 GEN_INT_ARITH2
775 #define GEN_INT_ARITHN_64 GEN_INT_ARITHN
776 #define GEN_INT_ARITH1_64 GEN_INT_ARITH1
779 /* add add. addo addo. */
780 static always_inline
void gen_op_addo (void)
786 #if defined(TARGET_PPC64)
787 #define gen_op_add_64 gen_op_add
788 static always_inline
void gen_op_addo_64 (void)
792 gen_op_check_addo_64();
795 GEN_INT_ARITH2_64 (add
, 0x1F, 0x0A, 0x08, PPC_INTEGER
);
796 /* addc addc. addco addco. */
797 static always_inline
void gen_op_addc (void)
803 static always_inline
void gen_op_addco (void)
810 #if defined(TARGET_PPC64)
811 static always_inline
void gen_op_addc_64 (void)
815 gen_op_check_addc_64();
817 static always_inline
void gen_op_addco_64 (void)
821 gen_op_check_addc_64();
822 gen_op_check_addo_64();
825 GEN_INT_ARITH2_64 (addc
, 0x1F, 0x0A, 0x00, PPC_INTEGER
);
826 /* adde adde. addeo addeo. */
827 static always_inline
void gen_op_addeo (void)
833 #if defined(TARGET_PPC64)
834 static always_inline
void gen_op_addeo_64 (void)
838 gen_op_check_addo_64();
841 GEN_INT_ARITH2_64 (adde
, 0x1F, 0x0A, 0x04, PPC_INTEGER
);
842 /* addme addme. addmeo addmeo. */
843 static always_inline
void gen_op_addme (void)
848 #if defined(TARGET_PPC64)
849 static always_inline
void gen_op_addme_64 (void)
855 GEN_INT_ARITH1_64 (addme
, 0x1F, 0x0A, 0x07, PPC_INTEGER
);
856 /* addze addze. addzeo addzeo. */
857 static always_inline
void gen_op_addze (void)
863 static always_inline
void gen_op_addzeo (void)
870 #if defined(TARGET_PPC64)
871 static always_inline
void gen_op_addze_64 (void)
875 gen_op_check_addc_64();
877 static always_inline
void gen_op_addzeo_64 (void)
881 gen_op_check_addc_64();
882 gen_op_check_addo_64();
885 GEN_INT_ARITH1_64 (addze
, 0x1F, 0x0A, 0x06, PPC_INTEGER
);
886 /* divw divw. divwo divwo. */
887 GEN_INT_ARITH2 (divw
, 0x1F, 0x0B, 0x0F, PPC_INTEGER
);
888 /* divwu divwu. divwuo divwuo. */
889 GEN_INT_ARITH2 (divwu
, 0x1F, 0x0B, 0x0E, PPC_INTEGER
);
891 GEN_INT_ARITHN (mulhw
, 0x1F, 0x0B, 0x02, PPC_INTEGER
);
893 GEN_INT_ARITHN (mulhwu
, 0x1F, 0x0B, 0x00, PPC_INTEGER
);
894 /* mullw mullw. mullwo mullwo. */
895 GEN_INT_ARITH2 (mullw
, 0x1F, 0x0B, 0x07, PPC_INTEGER
);
896 /* neg neg. nego nego. */
897 GEN_INT_ARITH1_64 (neg
, 0x1F, 0x08, 0x03, PPC_INTEGER
);
898 /* subf subf. subfo subfo. */
899 static always_inline
void gen_op_subfo (void)
901 gen_op_moven_T2_T0();
905 #if defined(TARGET_PPC64)
906 #define gen_op_subf_64 gen_op_subf
907 static always_inline
void gen_op_subfo_64 (void)
909 gen_op_moven_T2_T0();
911 gen_op_check_addo_64();
914 GEN_INT_ARITH2_64 (subf
, 0x1F, 0x08, 0x01, PPC_INTEGER
);
915 /* subfc subfc. subfco subfco. */
916 static always_inline
void gen_op_subfc (void)
919 gen_op_check_subfc();
921 static always_inline
void gen_op_subfco (void)
923 gen_op_moven_T2_T0();
925 gen_op_check_subfc();
928 #if defined(TARGET_PPC64)
929 static always_inline
void gen_op_subfc_64 (void)
932 gen_op_check_subfc_64();
934 static always_inline
void gen_op_subfco_64 (void)
936 gen_op_moven_T2_T0();
938 gen_op_check_subfc_64();
939 gen_op_check_addo_64();
942 GEN_INT_ARITH2_64 (subfc
, 0x1F, 0x08, 0x00, PPC_INTEGER
);
943 /* subfe subfe. subfeo subfeo. */
944 static always_inline
void gen_op_subfeo (void)
946 gen_op_moven_T2_T0();
950 #if defined(TARGET_PPC64)
951 #define gen_op_subfe_64 gen_op_subfe
952 static always_inline
void gen_op_subfeo_64 (void)
954 gen_op_moven_T2_T0();
956 gen_op_check_addo_64();
959 GEN_INT_ARITH2_64 (subfe
, 0x1F, 0x08, 0x04, PPC_INTEGER
);
960 /* subfme subfme. subfmeo subfmeo. */
961 GEN_INT_ARITH1_64 (subfme
, 0x1F, 0x08, 0x07, PPC_INTEGER
);
962 /* subfze subfze. subfzeo subfzeo. */
963 GEN_INT_ARITH1_64 (subfze
, 0x1F, 0x08, 0x06, PPC_INTEGER
);
965 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
967 target_long simm
= SIMM(ctx
->opcode
);
969 if (rA(ctx
->opcode
) == 0) {
973 gen_op_load_gpr_T0(rA(ctx
->opcode
));
974 if (likely(simm
!= 0))
977 gen_op_store_T0_gpr(rD(ctx
->opcode
));
980 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
982 target_long simm
= SIMM(ctx
->opcode
);
984 gen_op_load_gpr_T0(rA(ctx
->opcode
));
985 if (likely(simm
!= 0)) {
988 #if defined(TARGET_PPC64)
990 gen_op_check_addc_64();
995 gen_op_clear_xer_ca();
997 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1000 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1002 target_long simm
= SIMM(ctx
->opcode
);
1004 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1005 if (likely(simm
!= 0)) {
1006 gen_op_move_T2_T0();
1008 #if defined(TARGET_PPC64)
1010 gen_op_check_addc_64();
1013 gen_op_check_addc();
1015 gen_op_clear_xer_ca();
1017 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1021 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1023 target_long simm
= SIMM(ctx
->opcode
);
1025 if (rA(ctx
->opcode
) == 0) {
1027 gen_set_T0(simm
<< 16);
1029 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1030 if (likely(simm
!= 0))
1031 gen_op_addi(simm
<< 16);
1033 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1036 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1038 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1039 gen_op_mulli(SIMM(ctx
->opcode
));
1040 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1043 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1045 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1046 #if defined(TARGET_PPC64)
1048 gen_op_subfic_64(SIMM(ctx
->opcode
));
1051 gen_op_subfic(SIMM(ctx
->opcode
));
1052 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1055 #if defined(TARGET_PPC64)
1057 GEN_INT_ARITHN (mulhd
, 0x1F, 0x09, 0x02, PPC_64B
);
1058 /* mulhdu mulhdu. */
1059 GEN_INT_ARITHN (mulhdu
, 0x1F, 0x09, 0x00, PPC_64B
);
1060 /* mulld mulld. mulldo mulldo. */
1061 GEN_INT_ARITH2 (mulld
, 0x1F, 0x09, 0x07, PPC_64B
);
1062 /* divd divd. divdo divdo. */
1063 GEN_INT_ARITH2 (divd
, 0x1F, 0x09, 0x0F, PPC_64B
);
1064 /* divdu divdu. divduo divduo. */
1065 GEN_INT_ARITH2 (divdu
, 0x1F, 0x09, 0x0E, PPC_64B
);
1068 /*** Integer comparison ***/
1069 #if defined(TARGET_PPC64)
1070 #define GEN_CMP(name, opc, type) \
1071 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1073 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1074 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1075 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
1076 gen_op_##name##_64(); \
1079 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1082 #define GEN_CMP(name, opc, type) \
1083 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1085 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1086 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1088 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1093 GEN_CMP(cmp
, 0x00, PPC_INTEGER
);
1095 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
1097 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1098 #if defined(TARGET_PPC64)
1099 if (ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000))
1100 gen_op_cmpi_64(SIMM(ctx
->opcode
));
1103 gen_op_cmpi(SIMM(ctx
->opcode
));
1104 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1107 GEN_CMP(cmpl
, 0x01, PPC_INTEGER
);
1109 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
1111 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1112 #if defined(TARGET_PPC64)
1113 if (ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000))
1114 gen_op_cmpli_64(UIMM(ctx
->opcode
));
1117 gen_op_cmpli(UIMM(ctx
->opcode
));
1118 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1121 /* isel (PowerPC 2.03 specification) */
1122 GEN_HANDLER(isel
, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203
)
1124 uint32_t bi
= rC(ctx
->opcode
);
1127 if (rA(ctx
->opcode
) == 0) {
1130 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1132 gen_op_load_gpr_T2(rB(ctx
->opcode
));
1133 mask
= 1 << (3 - (bi
& 0x03));
1134 gen_op_load_crf_T0(bi
>> 2);
1135 gen_op_test_true(mask
);
1137 gen_op_store_T0_gpr(rD(ctx
->opcode
));
1140 /*** Integer logical ***/
1141 #define __GEN_LOGICAL2(name, opc2, opc3, type) \
1142 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
1144 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1145 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1147 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1148 if (unlikely(Rc(ctx->opcode) != 0)) \
1151 #define GEN_LOGICAL2(name, opc, type) \
1152 __GEN_LOGICAL2(name, 0x1C, opc, type)
1154 #define GEN_LOGICAL1(name, opc, type) \
1155 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1157 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1159 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1160 if (unlikely(Rc(ctx->opcode) != 0)) \
1165 GEN_LOGICAL2(and, 0x00, PPC_INTEGER
);
1167 GEN_LOGICAL2(andc
, 0x01, PPC_INTEGER
);
1169 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1171 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1172 gen_op_andi_T0(UIMM(ctx
->opcode
));
1173 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1177 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1179 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1180 gen_op_andi_T0(UIMM(ctx
->opcode
) << 16);
1181 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1186 GEN_LOGICAL1(cntlzw
, 0x00, PPC_INTEGER
);
1188 GEN_LOGICAL2(eqv
, 0x08, PPC_INTEGER
);
1189 /* extsb & extsb. */
1190 GEN_LOGICAL1(extsb
, 0x1D, PPC_INTEGER
);
1191 /* extsh & extsh. */
1192 GEN_LOGICAL1(extsh
, 0x1C, PPC_INTEGER
);
1194 GEN_LOGICAL2(nand
, 0x0E, PPC_INTEGER
);
1196 GEN_LOGICAL2(nor
, 0x03, PPC_INTEGER
);
1199 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
)
1203 rs
= rS(ctx
->opcode
);
1204 ra
= rA(ctx
->opcode
);
1205 rb
= rB(ctx
->opcode
);
1206 /* Optimisation for mr. ri case */
1207 if (rs
!= ra
|| rs
!= rb
) {
1208 gen_op_load_gpr_T0(rs
);
1210 gen_op_load_gpr_T1(rb
);
1213 gen_op_store_T0_gpr(ra
);
1214 if (unlikely(Rc(ctx
->opcode
) != 0))
1216 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1217 gen_op_load_gpr_T0(rs
);
1219 #if defined(TARGET_PPC64)
1223 /* Set process priority to low */
1224 gen_op_store_pri(2);
1227 /* Set process priority to medium-low */
1228 gen_op_store_pri(3);
1231 /* Set process priority to normal */
1232 gen_op_store_pri(4);
1234 #if !defined(CONFIG_USER_ONLY)
1236 if (ctx
->supervisor
> 0) {
1237 /* Set process priority to very low */
1238 gen_op_store_pri(1);
1242 if (ctx
->supervisor
> 0) {
1243 /* Set process priority to medium-hight */
1244 gen_op_store_pri(5);
1248 if (ctx
->supervisor
> 0) {
1249 /* Set process priority to high */
1250 gen_op_store_pri(6);
1254 if (ctx
->supervisor
> 1) {
1255 /* Set process priority to very high */
1256 gen_op_store_pri(7);
1269 GEN_LOGICAL2(orc
, 0x0C, PPC_INTEGER
);
1271 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
)
1273 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1274 /* Optimisation for "set to zero" case */
1275 if (rS(ctx
->opcode
) != rB(ctx
->opcode
)) {
1276 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1281 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1282 if (unlikely(Rc(ctx
->opcode
) != 0))
1286 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1288 target_ulong uimm
= UIMM(ctx
->opcode
);
1290 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1292 /* XXX: should handle special NOPs for POWER series */
1295 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1296 if (likely(uimm
!= 0))
1298 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1301 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1303 target_ulong uimm
= UIMM(ctx
->opcode
);
1305 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1309 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1310 if (likely(uimm
!= 0))
1311 gen_op_ori(uimm
<< 16);
1312 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1315 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1317 target_ulong uimm
= UIMM(ctx
->opcode
);
1319 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1323 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1324 if (likely(uimm
!= 0))
1326 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1330 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1332 target_ulong uimm
= UIMM(ctx
->opcode
);
1334 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1338 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1339 if (likely(uimm
!= 0))
1340 gen_op_xori(uimm
<< 16);
1341 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1344 /* popcntb : PowerPC 2.03 specification */
1345 GEN_HANDLER(popcntb
, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203
)
1347 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1348 #if defined(TARGET_PPC64)
1350 gen_op_popcntb_64();
1354 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1357 #if defined(TARGET_PPC64)
1358 /* extsw & extsw. */
1359 GEN_LOGICAL1(extsw
, 0x1E, PPC_64B
);
1361 GEN_LOGICAL1(cntlzd
, 0x01, PPC_64B
);
1364 /*** Integer rotate ***/
1365 /* rlwimi & rlwimi. */
1366 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1369 uint32_t mb
, me
, sh
;
1371 mb
= MB(ctx
->opcode
);
1372 me
= ME(ctx
->opcode
);
1373 sh
= SH(ctx
->opcode
);
1374 if (likely(sh
== 0)) {
1375 if (likely(mb
== 0 && me
== 31)) {
1376 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1378 } else if (likely(mb
== 31 && me
== 0)) {
1379 gen_op_load_gpr_T0(rA(ctx
->opcode
));
1382 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1383 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1386 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1387 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1388 gen_op_rotli32_T0(SH(ctx
->opcode
));
1390 #if defined(TARGET_PPC64)
1394 mask
= MASK(mb
, me
);
1395 gen_op_andi_T0(mask
);
1396 gen_op_andi_T1(~mask
);
1399 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1400 if (unlikely(Rc(ctx
->opcode
) != 0))
1403 /* rlwinm & rlwinm. */
1404 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1406 uint32_t mb
, me
, sh
;
1408 sh
= SH(ctx
->opcode
);
1409 mb
= MB(ctx
->opcode
);
1410 me
= ME(ctx
->opcode
);
1411 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1412 if (likely(sh
== 0)) {
1415 if (likely(mb
== 0)) {
1416 if (likely(me
== 31)) {
1417 gen_op_rotli32_T0(sh
);
1419 } else if (likely(me
== (31 - sh
))) {
1423 } else if (likely(me
== 31)) {
1424 if (likely(sh
== (32 - mb
))) {
1429 gen_op_rotli32_T0(sh
);
1431 #if defined(TARGET_PPC64)
1435 gen_op_andi_T0(MASK(mb
, me
));
1437 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1438 if (unlikely(Rc(ctx
->opcode
) != 0))
1441 /* rlwnm & rlwnm. */
1442 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1446 mb
= MB(ctx
->opcode
);
1447 me
= ME(ctx
->opcode
);
1448 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1449 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1450 gen_op_rotl32_T0_T1();
1451 if (unlikely(mb
!= 0 || me
!= 31)) {
1452 #if defined(TARGET_PPC64)
1456 gen_op_andi_T0(MASK(mb
, me
));
1458 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1459 if (unlikely(Rc(ctx
->opcode
) != 0))
1463 #if defined(TARGET_PPC64)
1464 #define GEN_PPC64_R2(name, opc1, opc2) \
1465 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1467 gen_##name(ctx, 0); \
1469 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1472 gen_##name(ctx, 1); \
1474 #define GEN_PPC64_R4(name, opc1, opc2) \
1475 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1477 gen_##name(ctx, 0, 0); \
1479 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1482 gen_##name(ctx, 0, 1); \
1484 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1487 gen_##name(ctx, 1, 0); \
1489 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1492 gen_##name(ctx, 1, 1); \
1495 static always_inline
void gen_andi_T0_64 (DisasContext
*ctx
, uint64_t mask
)
1498 gen_op_andi_T0_64(mask
>> 32, mask
& 0xFFFFFFFF);
1500 gen_op_andi_T0(mask
);
1503 static always_inline
void gen_andi_T1_64 (DisasContext
*ctx
, uint64_t mask
)
1506 gen_op_andi_T1_64(mask
>> 32, mask
& 0xFFFFFFFF);
1508 gen_op_andi_T1(mask
);
1511 static always_inline
void gen_rldinm (DisasContext
*ctx
, uint32_t mb
,
1512 uint32_t me
, uint32_t sh
)
1514 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1515 if (likely(sh
== 0)) {
1518 if (likely(mb
== 0)) {
1519 if (likely(me
== 63)) {
1520 gen_op_rotli64_T0(sh
);
1522 } else if (likely(me
== (63 - sh
))) {
1526 } else if (likely(me
== 63)) {
1527 if (likely(sh
== (64 - mb
))) {
1528 gen_op_srli_T0_64(mb
);
1532 gen_op_rotli64_T0(sh
);
1534 gen_andi_T0_64(ctx
, MASK(mb
, me
));
1536 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1537 if (unlikely(Rc(ctx
->opcode
) != 0))
1540 /* rldicl - rldicl. */
1541 static always_inline
void gen_rldicl (DisasContext
*ctx
, int mbn
, int shn
)
1545 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1546 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1547 gen_rldinm(ctx
, mb
, 63, sh
);
1549 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1550 /* rldicr - rldicr. */
1551 static always_inline
void gen_rldicr (DisasContext
*ctx
, int men
, int shn
)
1555 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1556 me
= MB(ctx
->opcode
) | (men
<< 5);
1557 gen_rldinm(ctx
, 0, me
, sh
);
1559 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1560 /* rldic - rldic. */
1561 static always_inline
void gen_rldic (DisasContext
*ctx
, int mbn
, int shn
)
1565 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1566 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1567 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1569 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1571 static always_inline
void gen_rldnm (DisasContext
*ctx
, uint32_t mb
,
1574 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1575 gen_op_load_gpr_T1(rB(ctx
->opcode
));
1576 gen_op_rotl64_T0_T1();
1577 if (unlikely(mb
!= 0 || me
!= 63)) {
1578 gen_andi_T0_64(ctx
, MASK(mb
, me
));
1580 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1581 if (unlikely(Rc(ctx
->opcode
) != 0))
1585 /* rldcl - rldcl. */
1586 static always_inline
void gen_rldcl (DisasContext
*ctx
, int mbn
)
1590 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1591 gen_rldnm(ctx
, mb
, 63);
1593 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1594 /* rldcr - rldcr. */
1595 static always_inline
void gen_rldcr (DisasContext
*ctx
, int men
)
1599 me
= MB(ctx
->opcode
) | (men
<< 5);
1600 gen_rldnm(ctx
, 0, me
);
1602 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1603 /* rldimi - rldimi. */
1604 static always_inline
void gen_rldimi (DisasContext
*ctx
, int mbn
, int shn
)
1607 uint32_t sh
, mb
, me
;
1609 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1610 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1612 if (likely(sh
== 0)) {
1613 if (likely(mb
== 0)) {
1614 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1617 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1618 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1621 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1622 gen_op_load_gpr_T1(rA(ctx
->opcode
));
1623 gen_op_rotli64_T0(sh
);
1625 mask
= MASK(mb
, me
);
1626 gen_andi_T0_64(ctx
, mask
);
1627 gen_andi_T1_64(ctx
, ~mask
);
1630 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1631 if (unlikely(Rc(ctx
->opcode
) != 0))
1634 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1637 /*** Integer shift ***/
1639 __GEN_LOGICAL2(slw
, 0x18, 0x00, PPC_INTEGER
);
1641 __GEN_LOGICAL2(sraw
, 0x18, 0x18, PPC_INTEGER
);
1642 /* srawi & srawi. */
1643 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
)
1646 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1647 if (SH(ctx
->opcode
) != 0) {
1648 gen_op_move_T1_T0();
1649 mb
= 32 - SH(ctx
->opcode
);
1651 #if defined(TARGET_PPC64)
1655 gen_op_srawi(SH(ctx
->opcode
), MASK(mb
, me
));
1657 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1658 if (unlikely(Rc(ctx
->opcode
) != 0))
1662 __GEN_LOGICAL2(srw
, 0x18, 0x10, PPC_INTEGER
);
1664 #if defined(TARGET_PPC64)
1666 __GEN_LOGICAL2(sld
, 0x1B, 0x00, PPC_64B
);
1668 __GEN_LOGICAL2(srad
, 0x1A, 0x18, PPC_64B
);
1669 /* sradi & sradi. */
1670 static always_inline
void gen_sradi (DisasContext
*ctx
, int n
)
1675 gen_op_load_gpr_T0(rS(ctx
->opcode
));
1676 sh
= SH(ctx
->opcode
) + (n
<< 5);
1678 gen_op_move_T1_T0();
1679 mb
= 64 - SH(ctx
->opcode
);
1681 mask
= MASK(mb
, me
);
1682 gen_op_sradi(sh
, mask
>> 32, mask
);
1684 gen_op_store_T0_gpr(rA(ctx
->opcode
));
1685 if (unlikely(Rc(ctx
->opcode
) != 0))
1688 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
)
1692 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
)
1697 __GEN_LOGICAL2(srd
, 0x1B, 0x10, PPC_64B
);
1700 /*** Floating-Point arithmetic ***/
1701 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1702 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
1704 if (unlikely(!ctx->fpu_enabled)) { \
1705 GEN_EXCP_NO_FP(ctx); \
1708 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1709 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1710 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
1711 gen_reset_fpstatus(); \
1716 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1717 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1720 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1721 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1722 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1724 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1725 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1727 if (unlikely(!ctx->fpu_enabled)) { \
1728 GEN_EXCP_NO_FP(ctx); \
1731 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1732 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
1733 gen_reset_fpstatus(); \
1738 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1739 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1741 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1742 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1743 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1745 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1746 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1748 if (unlikely(!ctx->fpu_enabled)) { \
1749 GEN_EXCP_NO_FP(ctx); \
1752 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1753 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1754 gen_reset_fpstatus(); \
1759 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1760 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1762 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1763 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1764 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1766 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1767 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
1769 if (unlikely(!ctx->fpu_enabled)) { \
1770 GEN_EXCP_NO_FP(ctx); \
1773 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1774 gen_reset_fpstatus(); \
1776 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1777 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1780 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1781 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
1783 if (unlikely(!ctx->fpu_enabled)) { \
1784 GEN_EXCP_NO_FP(ctx); \
1787 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1788 gen_reset_fpstatus(); \
1790 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1791 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1795 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
1797 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
1799 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
1802 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
1805 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
1808 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
1811 static always_inline
void gen_op_frsqrtes (void)
1816 GEN_FLOAT_BS(rsqrtes
, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES
);
1819 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
1821 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
1824 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
)
1826 if (unlikely(!ctx
->fpu_enabled
)) {
1827 GEN_EXCP_NO_FP(ctx
);
1830 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1831 gen_reset_fpstatus();
1833 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1834 gen_compute_fprf(1, Rc(ctx
->opcode
) != 0);
1837 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
)
1839 if (unlikely(!ctx
->fpu_enabled
)) {
1840 GEN_EXCP_NO_FP(ctx
);
1843 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1844 gen_reset_fpstatus();
1847 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1848 gen_compute_fprf(1, Rc(ctx
->opcode
) != 0);
1851 /*** Floating-Point multiply-and-add ***/
1852 /* fmadd - fmadds */
1853 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
1854 /* fmsub - fmsubs */
1855 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
1856 /* fnmadd - fnmadds */
1857 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
1858 /* fnmsub - fnmsubs */
1859 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
1861 /*** Floating-Point round & convert ***/
1863 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
1865 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
1867 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
1868 #if defined(TARGET_PPC64)
1870 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
);
1872 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
);
1874 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
);
1878 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
1880 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
1882 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
1884 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
1886 /*** Floating-Point compare ***/
1888 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
)
1890 if (unlikely(!ctx
->fpu_enabled
)) {
1891 GEN_EXCP_NO_FP(ctx
);
1894 gen_op_load_fpr_FT0(rA(ctx
->opcode
));
1895 gen_op_load_fpr_FT1(rB(ctx
->opcode
));
1896 gen_reset_fpstatus();
1898 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1899 gen_op_float_check_status();
1903 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
)
1905 if (unlikely(!ctx
->fpu_enabled
)) {
1906 GEN_EXCP_NO_FP(ctx
);
1909 gen_op_load_fpr_FT0(rA(ctx
->opcode
));
1910 gen_op_load_fpr_FT1(rB(ctx
->opcode
));
1911 gen_reset_fpstatus();
1913 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1914 gen_op_float_check_status();
1917 /*** Floating-point move ***/
1919 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1920 GEN_FLOAT_B(abs
, 0x08, 0x08, 0, PPC_FLOAT
);
1923 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
1924 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
)
1926 if (unlikely(!ctx
->fpu_enabled
)) {
1927 GEN_EXCP_NO_FP(ctx
);
1930 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
1931 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1932 gen_compute_fprf(0, Rc(ctx
->opcode
) != 0);
1936 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1937 GEN_FLOAT_B(nabs
, 0x08, 0x04, 0, PPC_FLOAT
);
1939 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1940 GEN_FLOAT_B(neg
, 0x08, 0x01, 0, PPC_FLOAT
);
1942 /*** Floating-Point status & ctrl register ***/
1944 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
)
1948 if (unlikely(!ctx
->fpu_enabled
)) {
1949 GEN_EXCP_NO_FP(ctx
);
1952 gen_optimize_fprf();
1953 bfa
= 4 * (7 - crfS(ctx
->opcode
));
1954 gen_op_load_fpscr_T0(bfa
);
1955 gen_op_store_T0_crf(crfD(ctx
->opcode
));
1956 gen_op_fpscr_resetbit(~(0xF << bfa
));
1960 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
)
1962 if (unlikely(!ctx
->fpu_enabled
)) {
1963 GEN_EXCP_NO_FP(ctx
);
1966 gen_optimize_fprf();
1967 gen_reset_fpstatus();
1968 gen_op_load_fpscr_FT0();
1969 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
1970 gen_compute_fprf(0, Rc(ctx
->opcode
) != 0);
1974 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
)
1978 if (unlikely(!ctx
->fpu_enabled
)) {
1979 GEN_EXCP_NO_FP(ctx
);
1982 crb
= 32 - (crbD(ctx
->opcode
) >> 2);
1983 gen_optimize_fprf();
1984 gen_reset_fpstatus();
1985 if (likely(crb
!= 30 && crb
!= 29))
1986 gen_op_fpscr_resetbit(~(1 << crb
));
1987 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1994 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
)
1998 if (unlikely(!ctx
->fpu_enabled
)) {
1999 GEN_EXCP_NO_FP(ctx
);
2002 crb
= 32 - (crbD(ctx
->opcode
) >> 2);
2003 gen_optimize_fprf();
2004 gen_reset_fpstatus();
2005 /* XXX: we pretend we can only do IEEE floating-point computations */
2006 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
))
2007 gen_op_fpscr_setbit(crb
);
2008 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2012 /* We can raise a differed exception */
2013 gen_op_float_check_status();
2017 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT
)
2019 if (unlikely(!ctx
->fpu_enabled
)) {
2020 GEN_EXCP_NO_FP(ctx
);
2023 gen_optimize_fprf();
2024 gen_op_load_fpr_FT0(rB(ctx
->opcode
));
2025 gen_reset_fpstatus();
2026 gen_op_store_fpscr(FM(ctx
->opcode
));
2027 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2031 /* We can raise a differed exception */
2032 gen_op_float_check_status();
2036 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT
)
2040 if (unlikely(!ctx
->fpu_enabled
)) {
2041 GEN_EXCP_NO_FP(ctx
);
2044 bf
= crbD(ctx
->opcode
) >> 2;
2046 gen_optimize_fprf();
2047 gen_op_set_FT0(FPIMM(ctx
->opcode
) << (4 * sh
));
2048 gen_reset_fpstatus();
2049 gen_op_store_fpscr(1 << sh
);
2050 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2054 /* We can raise a differed exception */
2055 gen_op_float_check_status();
2058 /*** Addressing modes ***/
2059 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2060 static always_inline
void gen_addr_imm_index (DisasContext
*ctx
,
2063 target_long simm
= SIMM(ctx
->opcode
);
2066 if (rA(ctx
->opcode
) == 0) {
2069 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2070 if (likely(simm
!= 0))
2073 #ifdef DEBUG_MEMORY_ACCESSES
2074 gen_op_print_mem_EA();
2078 static always_inline
void gen_addr_reg_index (DisasContext
*ctx
)
2080 if (rA(ctx
->opcode
) == 0) {
2081 gen_op_load_gpr_T0(rB(ctx
->opcode
));
2083 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2084 gen_op_load_gpr_T1(rB(ctx
->opcode
));
2087 #ifdef DEBUG_MEMORY_ACCESSES
2088 gen_op_print_mem_EA();
2092 static always_inline
void gen_addr_register (DisasContext
*ctx
)
2094 if (rA(ctx
->opcode
) == 0) {
2097 gen_op_load_gpr_T0(rA(ctx
->opcode
));
2099 #ifdef DEBUG_MEMORY_ACCESSES
2100 gen_op_print_mem_EA();
2104 #if defined(TARGET_PPC64)
2105 #define _GEN_MEM_FUNCS(name, mode) \
2106 &gen_op_##name##_##mode, \
2107 &gen_op_##name##_le_##mode, \
2108 &gen_op_##name##_64_##mode, \
2109 &gen_op_##name##_le_64_##mode
2111 #define _GEN_MEM_FUNCS(name, mode) \
2112 &gen_op_##name##_##mode, \
2113 &gen_op_##name##_le_##mode
2115 #if defined(CONFIG_USER_ONLY)
2116 #if defined(TARGET_PPC64)
2117 #define NB_MEM_FUNCS 4
2119 #define NB_MEM_FUNCS 2
2121 #define GEN_MEM_FUNCS(name) \
2122 _GEN_MEM_FUNCS(name, raw)
2124 #if defined(TARGET_PPC64)
2125 #define NB_MEM_FUNCS 12
2127 #define NB_MEM_FUNCS 6
2129 #define GEN_MEM_FUNCS(name) \
2130 _GEN_MEM_FUNCS(name, user), \
2131 _GEN_MEM_FUNCS(name, kernel), \
2132 _GEN_MEM_FUNCS(name, hypv)
2135 /*** Integer load ***/
2136 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
2137 /* Byte access routine are endian safe */
2138 #define gen_op_lbz_le_raw gen_op_lbz_raw
2139 #define gen_op_lbz_le_user gen_op_lbz_user
2140 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
2141 #define gen_op_lbz_le_hypv gen_op_lbz_hypv
2142 #define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2143 #define gen_op_lbz_le_64_user gen_op_lbz_64_user
2144 #define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2145 #define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2146 #define gen_op_stb_le_raw gen_op_stb_raw
2147 #define gen_op_stb_le_user gen_op_stb_user
2148 #define gen_op_stb_le_kernel gen_op_stb_kernel
2149 #define gen_op_stb_le_hypv gen_op_stb_hypv
2150 #define gen_op_stb_le_64_raw gen_op_stb_64_raw
2151 #define gen_op_stb_le_64_user gen_op_stb_64_user
2152 #define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2153 #define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
2154 #define OP_LD_TABLE(width) \
2155 static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2156 GEN_MEM_FUNCS(l##width), \
2158 #define OP_ST_TABLE(width) \
2159 static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2160 GEN_MEM_FUNCS(st##width), \
2163 #define GEN_LD(width, opc, type) \
2164 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2166 gen_addr_imm_index(ctx, 0); \
2167 op_ldst(l##width); \
2168 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2171 #define GEN_LDU(width, opc, type) \
2172 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2174 if (unlikely(rA(ctx->opcode) == 0 || \
2175 rA(ctx->opcode) == rD(ctx->opcode))) { \
2176 GEN_EXCP_INVAL(ctx); \
2179 if (type == PPC_64B) \
2180 gen_addr_imm_index(ctx, 0x03); \
2182 gen_addr_imm_index(ctx, 0); \
2183 op_ldst(l##width); \
2184 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2185 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2188 #define GEN_LDUX(width, opc2, opc3, type) \
2189 GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2191 if (unlikely(rA(ctx->opcode) == 0 || \
2192 rA(ctx->opcode) == rD(ctx->opcode))) { \
2193 GEN_EXCP_INVAL(ctx); \
2196 gen_addr_reg_index(ctx); \
2197 op_ldst(l##width); \
2198 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2199 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2202 #define GEN_LDX(width, opc2, opc3, type) \
2203 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2205 gen_addr_reg_index(ctx); \
2206 op_ldst(l##width); \
2207 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2210 #define GEN_LDS(width, op, type) \
2211 OP_LD_TABLE(width); \
2212 GEN_LD(width, op | 0x20, type); \
2213 GEN_LDU(width, op | 0x21, type); \
2214 GEN_LDUX(width, 0x17, op | 0x01, type); \
2215 GEN_LDX(width, 0x17, op | 0x00, type)
2217 /* lbz lbzu lbzux lbzx */
2218 GEN_LDS(bz
, 0x02, PPC_INTEGER
);
2219 /* lha lhau lhaux lhax */
2220 GEN_LDS(ha
, 0x0A, PPC_INTEGER
);
2221 /* lhz lhzu lhzux lhzx */
2222 GEN_LDS(hz
, 0x08, PPC_INTEGER
);
2223 /* lwz lwzu lwzux lwzx */
2224 GEN_LDS(wz
, 0x00, PPC_INTEGER
);
2225 #if defined(TARGET_PPC64)
2229 GEN_LDUX(wa
, 0x15, 0x0B, PPC_64B
);
2231 GEN_LDX(wa
, 0x15, 0x0A, PPC_64B
);
2233 GEN_LDUX(d
, 0x15, 0x01, PPC_64B
);
2235 GEN_LDX(d
, 0x15, 0x00, PPC_64B
);
2236 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
)
2238 if (Rc(ctx
->opcode
)) {
2239 if (unlikely(rA(ctx
->opcode
) == 0 ||
2240 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2241 GEN_EXCP_INVAL(ctx
);
2245 gen_addr_imm_index(ctx
, 0x03);
2246 if (ctx
->opcode
& 0x02) {
2247 /* lwa (lwau is undefined) */
2253 gen_op_store_T1_gpr(rD(ctx
->opcode
));
2254 if (Rc(ctx
->opcode
))
2255 gen_op_store_T0_gpr(rA(ctx
->opcode
));
2258 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
)
2260 #if defined(CONFIG_USER_ONLY)
2261 GEN_EXCP_PRIVOPC(ctx
);
2265 /* Restore CPU state */
2266 if (unlikely(ctx
->supervisor
== 0)) {
2267 GEN_EXCP_PRIVOPC(ctx
);
2270 ra
= rA(ctx
->opcode
);
2271 rd
= rD(ctx
->opcode
);
2272 if (unlikely((rd
& 1) || rd
== ra
)) {
2273 GEN_EXCP_INVAL(ctx
);
2276 if (unlikely(ctx
->mem_idx
& 1)) {
2277 /* Little-endian mode is not handled */
2278 GEN_EXCP(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2281 gen_addr_imm_index(ctx
, 0x0F);
2283 gen_op_store_T1_gpr(rd
);
2286 gen_op_store_T1_gpr(rd
+ 1);
2291 /*** Integer store ***/
2292 #define GEN_ST(width, opc, type) \
2293 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2295 gen_addr_imm_index(ctx, 0); \
2296 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2297 op_ldst(st##width); \
2300 #define GEN_STU(width, opc, type) \
2301 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2303 if (unlikely(rA(ctx->opcode) == 0)) { \
2304 GEN_EXCP_INVAL(ctx); \
2307 if (type == PPC_64B) \
2308 gen_addr_imm_index(ctx, 0x03); \
2310 gen_addr_imm_index(ctx, 0); \
2311 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2312 op_ldst(st##width); \
2313 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2316 #define GEN_STUX(width, opc2, opc3, type) \
2317 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2319 if (unlikely(rA(ctx->opcode) == 0)) { \
2320 GEN_EXCP_INVAL(ctx); \
2323 gen_addr_reg_index(ctx); \
2324 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2325 op_ldst(st##width); \
2326 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2329 #define GEN_STX(width, opc2, opc3, type) \
2330 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2332 gen_addr_reg_index(ctx); \
2333 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2334 op_ldst(st##width); \
2337 #define GEN_STS(width, op, type) \
2338 OP_ST_TABLE(width); \
2339 GEN_ST(width, op | 0x20, type); \
2340 GEN_STU(width, op | 0x21, type); \
2341 GEN_STUX(width, 0x17, op | 0x01, type); \
2342 GEN_STX(width, 0x17, op | 0x00, type)
2344 /* stb stbu stbux stbx */
2345 GEN_STS(b
, 0x06, PPC_INTEGER
);
2346 /* sth sthu sthux sthx */
2347 GEN_STS(h
, 0x0C, PPC_INTEGER
);
2348 /* stw stwu stwux stwx */
2349 GEN_STS(w
, 0x04, PPC_INTEGER
);
2350 #if defined(TARGET_PPC64)
2352 GEN_STUX(d
, 0x15, 0x05, PPC_64B
);
2353 GEN_STX(d
, 0x15, 0x04, PPC_64B
);
2354 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
)
2358 rs
= rS(ctx
->opcode
);
2359 if ((ctx
->opcode
& 0x3) == 0x2) {
2360 #if defined(CONFIG_USER_ONLY)
2361 GEN_EXCP_PRIVOPC(ctx
);
2364 if (unlikely(ctx
->supervisor
== 0)) {
2365 GEN_EXCP_PRIVOPC(ctx
);
2368 if (unlikely(rs
& 1)) {
2369 GEN_EXCP_INVAL(ctx
);
2372 if (unlikely(ctx
->mem_idx
& 1)) {
2373 /* Little-endian mode is not handled */
2374 GEN_EXCP(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2377 gen_addr_imm_index(ctx
, 0x03);
2378 gen_op_load_gpr_T1(rs
);
2381 gen_op_load_gpr_T1(rs
+ 1);
2386 if (Rc(ctx
->opcode
)) {
2387 if (unlikely(rA(ctx
->opcode
) == 0)) {
2388 GEN_EXCP_INVAL(ctx
);
2392 gen_addr_imm_index(ctx
, 0x03);
2393 gen_op_load_gpr_T1(rs
);
2395 if (Rc(ctx
->opcode
))
2396 gen_op_store_T0_gpr(rA(ctx
->opcode
));
2400 /*** Integer load and store with byte reverse ***/
2403 GEN_LDX(hbr
, 0x16, 0x18, PPC_INTEGER
);
2406 GEN_LDX(wbr
, 0x16, 0x10, PPC_INTEGER
);
2409 GEN_STX(hbr
, 0x16, 0x1C, PPC_INTEGER
);
2412 GEN_STX(wbr
, 0x16, 0x14, PPC_INTEGER
);
2414 /*** Integer load and store multiple ***/
2415 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2416 static GenOpFunc1
*gen_op_lmw
[NB_MEM_FUNCS
] = {
2419 static GenOpFunc1
*gen_op_stmw
[NB_MEM_FUNCS
] = {
2420 GEN_MEM_FUNCS(stmw
),
2424 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
2426 /* NIP cannot be restored if the memory exception comes from an helper */
2427 gen_update_nip(ctx
, ctx
->nip
- 4);
2428 gen_addr_imm_index(ctx
, 0);
2429 op_ldstm(lmw
, rD(ctx
->opcode
));
2433 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
2435 /* NIP cannot be restored if the memory exception comes from an helper */
2436 gen_update_nip(ctx
, ctx
->nip
- 4);
2437 gen_addr_imm_index(ctx
, 0);
2438 op_ldstm(stmw
, rS(ctx
->opcode
));
2441 /*** Integer load and store strings ***/
2442 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2443 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2444 static GenOpFunc1
*gen_op_lswi
[NB_MEM_FUNCS
] = {
2445 GEN_MEM_FUNCS(lswi
),
2447 static GenOpFunc3
*gen_op_lswx
[NB_MEM_FUNCS
] = {
2448 GEN_MEM_FUNCS(lswx
),
2450 static GenOpFunc1
*gen_op_stsw
[NB_MEM_FUNCS
] = {
2451 GEN_MEM_FUNCS(stsw
),
2455 /* PowerPC32 specification says we must generate an exception if
2456 * rA is in the range of registers to be loaded.
2457 * In an other hand, IBM says this is valid, but rA won't be loaded.
2458 * For now, I'll follow the spec...
2460 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER
)
2462 int nb
= NB(ctx
->opcode
);
2463 int start
= rD(ctx
->opcode
);
2464 int ra
= rA(ctx
->opcode
);
2470 if (unlikely(((start
+ nr
) > 32 &&
2471 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
2472 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
2473 GEN_EXCP(ctx
, POWERPC_EXCP_PROGRAM
,
2474 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_LSWX
);
2477 /* NIP cannot be restored if the memory exception comes from an helper */
2478 gen_update_nip(ctx
, ctx
->nip
- 4);
2479 gen_addr_register(ctx
);
2481 op_ldsts(lswi
, start
);
2485 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER
)
2487 int ra
= rA(ctx
->opcode
);
2488 int rb
= rB(ctx
->opcode
);
2490 /* NIP cannot be restored if the memory exception comes from an helper */
2491 gen_update_nip(ctx
, ctx
->nip
- 4);
2492 gen_addr_reg_index(ctx
);
2496 gen_op_load_xer_bc();
2497 op_ldstsx(lswx
, rD(ctx
->opcode
), ra
, rb
);
2501 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER
)
2503 int nb
= NB(ctx
->opcode
);
2505 /* NIP cannot be restored if the memory exception comes from an helper */
2506 gen_update_nip(ctx
, ctx
->nip
- 4);
2507 gen_addr_register(ctx
);
2511 op_ldsts(stsw
, rS(ctx
->opcode
));
2515 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER
)
2517 /* NIP cannot be restored if the memory exception comes from an helper */
2518 gen_update_nip(ctx
, ctx
->nip
- 4);
2519 gen_addr_reg_index(ctx
);
2520 gen_op_load_xer_bc();
2521 op_ldsts(stsw
, rS(ctx
->opcode
));
2524 /*** Memory synchronisation ***/
2526 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
)
2531 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
)
2536 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2537 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2538 static GenOpFunc
*gen_op_lwarx
[NB_MEM_FUNCS
] = {
2539 GEN_MEM_FUNCS(lwarx
),
2541 static GenOpFunc
*gen_op_stwcx
[NB_MEM_FUNCS
] = {
2542 GEN_MEM_FUNCS(stwcx
),
2546 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES
)
2548 /* NIP cannot be restored if the memory exception comes from an helper */
2549 gen_update_nip(ctx
, ctx
->nip
- 4);
2550 gen_addr_reg_index(ctx
);
2552 gen_op_store_T1_gpr(rD(ctx
->opcode
));
2556 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
)
2558 /* NIP cannot be restored if the memory exception comes from an helper */
2559 gen_update_nip(ctx
, ctx
->nip
- 4);
2560 gen_addr_reg_index(ctx
);
2561 gen_op_load_gpr_T1(rS(ctx
->opcode
));
2565 #if defined(TARGET_PPC64)
2566 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2567 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2568 static GenOpFunc
*gen_op_ldarx
[NB_MEM_FUNCS
] = {
2569 GEN_MEM_FUNCS(ldarx
),
2571 static GenOpFunc
*gen_op_stdcx
[NB_MEM_FUNCS
] = {
2572 GEN_MEM_FUNCS(stdcx
),
2576 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B
)
2578 /* NIP cannot be restored if the memory exception comes from an helper */
2579 gen_update_nip(ctx
, ctx
->nip
- 4);
2580 gen_addr_reg_index(ctx
);
2582 gen_op_store_T1_gpr(rD(ctx
->opcode
));
2586 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
)
2588 /* NIP cannot be restored if the memory exception comes from an helper */
2589 gen_update_nip(ctx
, ctx
->nip
- 4);
2590 gen_addr_reg_index(ctx
);
2591 gen_op_load_gpr_T1(rS(ctx
->opcode
));
2594 #endif /* defined(TARGET_PPC64) */
2597 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
)
2602 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
)
2604 /* Stop translation, as the CPU is supposed to sleep from now */
2606 GEN_EXCP(ctx
, EXCP_HLT
, 1);
2609 /*** Floating-point load ***/
2610 #define GEN_LDF(width, opc, type) \
2611 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2613 if (unlikely(!ctx->fpu_enabled)) { \
2614 GEN_EXCP_NO_FP(ctx); \
2617 gen_addr_imm_index(ctx, 0); \
2618 op_ldst(l##width); \
2619 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2622 #define GEN_LDUF(width, opc, type) \
2623 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2625 if (unlikely(!ctx->fpu_enabled)) { \
2626 GEN_EXCP_NO_FP(ctx); \
2629 if (unlikely(rA(ctx->opcode) == 0)) { \
2630 GEN_EXCP_INVAL(ctx); \
2633 gen_addr_imm_index(ctx, 0); \
2634 op_ldst(l##width); \
2635 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2636 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2639 #define GEN_LDUXF(width, opc, type) \
2640 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2642 if (unlikely(!ctx->fpu_enabled)) { \
2643 GEN_EXCP_NO_FP(ctx); \
2646 if (unlikely(rA(ctx->opcode) == 0)) { \
2647 GEN_EXCP_INVAL(ctx); \
2650 gen_addr_reg_index(ctx); \
2651 op_ldst(l##width); \
2652 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2653 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2656 #define GEN_LDXF(width, opc2, opc3, type) \
2657 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2659 if (unlikely(!ctx->fpu_enabled)) { \
2660 GEN_EXCP_NO_FP(ctx); \
2663 gen_addr_reg_index(ctx); \
2664 op_ldst(l##width); \
2665 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2668 #define GEN_LDFS(width, op, type) \
2669 OP_LD_TABLE(width); \
2670 GEN_LDF(width, op | 0x20, type); \
2671 GEN_LDUF(width, op | 0x21, type); \
2672 GEN_LDUXF(width, op | 0x01, type); \
2673 GEN_LDXF(width, 0x17, op | 0x00, type)
2675 /* lfd lfdu lfdux lfdx */
2676 GEN_LDFS(fd
, 0x12, PPC_FLOAT
);
2677 /* lfs lfsu lfsux lfsx */
2678 GEN_LDFS(fs
, 0x10, PPC_FLOAT
);
2680 /*** Floating-point store ***/
2681 #define GEN_STF(width, opc, type) \
2682 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2684 if (unlikely(!ctx->fpu_enabled)) { \
2685 GEN_EXCP_NO_FP(ctx); \
2688 gen_addr_imm_index(ctx, 0); \
2689 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2690 op_ldst(st##width); \
2693 #define GEN_STUF(width, opc, type) \
2694 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2696 if (unlikely(!ctx->fpu_enabled)) { \
2697 GEN_EXCP_NO_FP(ctx); \
2700 if (unlikely(rA(ctx->opcode) == 0)) { \
2701 GEN_EXCP_INVAL(ctx); \
2704 gen_addr_imm_index(ctx, 0); \
2705 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2706 op_ldst(st##width); \
2707 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2710 #define GEN_STUXF(width, opc, type) \
2711 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2713 if (unlikely(!ctx->fpu_enabled)) { \
2714 GEN_EXCP_NO_FP(ctx); \
2717 if (unlikely(rA(ctx->opcode) == 0)) { \
2718 GEN_EXCP_INVAL(ctx); \
2721 gen_addr_reg_index(ctx); \
2722 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2723 op_ldst(st##width); \
2724 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2727 #define GEN_STXF(width, opc2, opc3, type) \
2728 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2730 if (unlikely(!ctx->fpu_enabled)) { \
2731 GEN_EXCP_NO_FP(ctx); \
2734 gen_addr_reg_index(ctx); \
2735 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2736 op_ldst(st##width); \
2739 #define GEN_STFS(width, op, type) \
2740 OP_ST_TABLE(width); \
2741 GEN_STF(width, op | 0x20, type); \
2742 GEN_STUF(width, op | 0x21, type); \
2743 GEN_STUXF(width, op | 0x01, type); \
2744 GEN_STXF(width, 0x17, op | 0x00, type)
2746 /* stfd stfdu stfdux stfdx */
2747 GEN_STFS(fd
, 0x16, PPC_FLOAT
);
2748 /* stfs stfsu stfsux stfsx */
2749 GEN_STFS(fs
, 0x14, PPC_FLOAT
);
2754 GEN_STXF(fiwx
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
2757 static always_inline
void gen_goto_tb (DisasContext
*ctx
, int n
,
2760 TranslationBlock
*tb
;
2762 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
2764 gen_op_goto_tb0(TBPARAM(tb
));
2766 gen_op_goto_tb1(TBPARAM(tb
));
2768 #if defined(TARGET_PPC64)
2774 gen_op_set_T0((long)tb
+ n
);
2775 if (ctx
->singlestep_enabled
)
2780 #if defined(TARGET_PPC64)
2787 if (ctx
->singlestep_enabled
)
2793 static always_inline
void gen_setlr (DisasContext
*ctx
, target_ulong nip
)
2795 #if defined(TARGET_PPC64)
2796 if (ctx
->sf_mode
!= 0 && (nip
>> 32))
2797 gen_op_setlr_64(ctx
->nip
>> 32, ctx
->nip
);
2800 gen_op_setlr(ctx
->nip
);
2804 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
2806 target_ulong li
, target
;
2808 /* sign extend LI */
2809 #if defined(TARGET_PPC64)
2811 li
= ((int64_t)LI(ctx
->opcode
) << 38) >> 38;
2814 li
= ((int32_t)LI(ctx
->opcode
) << 6) >> 6;
2815 if (likely(AA(ctx
->opcode
) == 0))
2816 target
= ctx
->nip
+ li
- 4;
2819 #if defined(TARGET_PPC64)
2821 target
= (uint32_t)target
;
2823 if (LK(ctx
->opcode
))
2824 gen_setlr(ctx
, ctx
->nip
);
2825 gen_goto_tb(ctx
, 0, target
);
2826 ctx
->exception
= POWERPC_EXCP_BRANCH
;
2833 static always_inline
void gen_bcond (DisasContext
*ctx
, int type
)
2835 target_ulong target
= 0;
2837 uint32_t bo
= BO(ctx
->opcode
);
2838 uint32_t bi
= BI(ctx
->opcode
);
2841 if ((bo
& 0x4) == 0)
2845 li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
2846 if (likely(AA(ctx
->opcode
) == 0)) {
2847 target
= ctx
->nip
+ li
- 4;
2851 #if defined(TARGET_PPC64)
2853 target
= (uint32_t)target
;
2857 gen_op_movl_T1_ctr();
2861 gen_op_movl_T1_lr();
2864 if (LK(ctx
->opcode
))
2865 gen_setlr(ctx
, ctx
->nip
);
2867 /* No CR condition */
2870 #if defined(TARGET_PPC64)
2872 gen_op_test_ctr_64();
2878 #if defined(TARGET_PPC64)
2880 gen_op_test_ctrz_64();
2888 if (type
== BCOND_IM
) {
2889 gen_goto_tb(ctx
, 0, target
);
2892 #if defined(TARGET_PPC64)
2904 mask
= 1 << (3 - (bi
& 0x03));
2905 gen_op_load_crf_T0(bi
>> 2);
2909 #if defined(TARGET_PPC64)
2911 gen_op_test_ctr_true_64(mask
);
2914 gen_op_test_ctr_true(mask
);
2917 #if defined(TARGET_PPC64)
2919 gen_op_test_ctrz_true_64(mask
);
2922 gen_op_test_ctrz_true(mask
);
2927 gen_op_test_true(mask
);
2933 #if defined(TARGET_PPC64)
2935 gen_op_test_ctr_false_64(mask
);
2938 gen_op_test_ctr_false(mask
);
2941 #if defined(TARGET_PPC64)
2943 gen_op_test_ctrz_false_64(mask
);
2946 gen_op_test_ctrz_false(mask
);
2951 gen_op_test_false(mask
);
2956 if (type
== BCOND_IM
) {
2957 int l1
= gen_new_label();
2959 gen_goto_tb(ctx
, 0, target
);
2961 gen_goto_tb(ctx
, 1, ctx
->nip
);
2963 #if defined(TARGET_PPC64)
2965 gen_op_btest_T1_64(ctx
->nip
>> 32, ctx
->nip
);
2968 gen_op_btest_T1(ctx
->nip
);
2971 if (ctx
->singlestep_enabled
)
2976 ctx
->exception
= POWERPC_EXCP_BRANCH
;
2979 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
2981 gen_bcond(ctx
, BCOND_IM
);
2984 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
)
2986 gen_bcond(ctx
, BCOND_CTR
);
2989 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
)
2991 gen_bcond(ctx
, BCOND_LR
);
2994 /*** Condition register logical ***/
2995 #define GEN_CRLOGIC(op, opc) \
2996 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3000 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
3001 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3003 gen_op_srli_T0(sh); \
3005 gen_op_sli_T0(-sh); \
3006 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
3007 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3009 gen_op_srli_T1(sh); \
3011 gen_op_sli_T1(-sh); \
3013 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3014 gen_op_andi_T0(bitmask); \
3015 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
3016 gen_op_andi_T1(~bitmask); \
3018 gen_op_store_T0_crf(crbD(ctx->opcode) >> 2); \
3022 GEN_CRLOGIC(and, 0x08);
3024 GEN_CRLOGIC(andc
, 0x04);
3026 GEN_CRLOGIC(eqv
, 0x09);
3028 GEN_CRLOGIC(nand
, 0x07);
3030 GEN_CRLOGIC(nor
, 0x01);
3032 GEN_CRLOGIC(or, 0x0E);
3034 GEN_CRLOGIC(orc
, 0x0D);
3036 GEN_CRLOGIC(xor, 0x06);
3038 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
)
3040 gen_op_load_crf_T0(crfS(ctx
->opcode
));
3041 gen_op_store_T0_crf(crfD(ctx
->opcode
));
3044 /*** System linkage ***/
3045 /* rfi (supervisor only) */
3046 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
)
3048 #if defined(CONFIG_USER_ONLY)
3049 GEN_EXCP_PRIVOPC(ctx
);
3051 /* Restore CPU state */
3052 if (unlikely(!ctx
->supervisor
)) {
3053 GEN_EXCP_PRIVOPC(ctx
);
3061 #if defined(TARGET_PPC64)
3062 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
)
3064 #if defined(CONFIG_USER_ONLY)
3065 GEN_EXCP_PRIVOPC(ctx
);
3067 /* Restore CPU state */
3068 if (unlikely(!ctx
->supervisor
)) {
3069 GEN_EXCP_PRIVOPC(ctx
);
3077 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B
)
3079 #if defined(CONFIG_USER_ONLY)
3080 GEN_EXCP_PRIVOPC(ctx
);
3082 /* Restore CPU state */
3083 if (unlikely(ctx
->supervisor
<= 1)) {
3084 GEN_EXCP_PRIVOPC(ctx
);
3094 #if defined(CONFIG_USER_ONLY)
3095 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3097 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3099 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
)
3103 lev
= (ctx
->opcode
>> 5) & 0x7F;
3104 GEN_EXCP(ctx
, POWERPC_SYSCALL
, lev
);
3109 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
)
3111 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3112 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3113 /* Update the nip since this might generate a trap exception */
3114 gen_update_nip(ctx
, ctx
->nip
);
3115 gen_op_tw(TO(ctx
->opcode
));
3119 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3121 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3122 gen_set_T1(SIMM(ctx
->opcode
));
3123 /* Update the nip since this might generate a trap exception */
3124 gen_update_nip(ctx
, ctx
->nip
);
3125 gen_op_tw(TO(ctx
->opcode
));
3128 #if defined(TARGET_PPC64)
3130 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
)
3132 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3133 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3134 /* Update the nip since this might generate a trap exception */
3135 gen_update_nip(ctx
, ctx
->nip
);
3136 gen_op_td(TO(ctx
->opcode
));
3140 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
)
3142 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3143 gen_set_T1(SIMM(ctx
->opcode
));
3144 /* Update the nip since this might generate a trap exception */
3145 gen_update_nip(ctx
, ctx
->nip
);
3146 gen_op_td(TO(ctx
->opcode
));
3150 /*** Processor control ***/
3152 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
)
3154 gen_op_load_xer_cr();
3155 gen_op_store_T0_crf(crfD(ctx
->opcode
));
3156 gen_op_clear_xer_ov();
3157 gen_op_clear_xer_ca();
3161 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
)
3165 if (likely(ctx
->opcode
& 0x00100000)) {
3166 crm
= CRM(ctx
->opcode
);
3167 if (likely((crm
^ (crm
- 1)) == 0)) {
3169 gen_op_load_cro(7 - crn
);
3174 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3178 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
)
3180 #if defined(CONFIG_USER_ONLY)
3181 GEN_EXCP_PRIVREG(ctx
);
3183 if (unlikely(!ctx
->supervisor
)) {
3184 GEN_EXCP_PRIVREG(ctx
);
3188 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3193 #define SPR_NOACCESS ((void *)(-1UL))
3195 static void spr_noaccess (void *opaque
, int sprn
)
3197 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3198 printf("ERROR: try to access SPR %d !\n", sprn
);
3200 #define SPR_NOACCESS (&spr_noaccess)
3204 static always_inline
void gen_op_mfspr (DisasContext
*ctx
)
3206 void (*read_cb
)(void *opaque
, int sprn
);
3207 uint32_t sprn
= SPR(ctx
->opcode
);
3209 #if !defined(CONFIG_USER_ONLY)
3210 if (ctx
->supervisor
== 2)
3211 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3212 else if (ctx
->supervisor
)
3213 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3216 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3217 if (likely(read_cb
!= NULL
)) {
3218 if (likely(read_cb
!= SPR_NOACCESS
)) {
3219 (*read_cb
)(ctx
, sprn
);
3220 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3222 /* Privilege exception */
3223 /* This is a hack to avoid warnings when running Linux:
3224 * this OS breaks the PowerPC virtualisation model,
3225 * allowing userland application to read the PVR
3227 if (sprn
!= SPR_PVR
) {
3228 if (loglevel
!= 0) {
3229 fprintf(logfile
, "Trying to read privileged spr %d %03x at"
3230 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3232 printf("Trying to read privileged spr %d %03x at " ADDRX
"\n",
3233 sprn
, sprn
, ctx
->nip
);
3235 GEN_EXCP_PRIVREG(ctx
);
3239 if (loglevel
!= 0) {
3240 fprintf(logfile
, "Trying to read invalid spr %d %03x at "
3241 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3243 printf("Trying to read invalid spr %d %03x at " ADDRX
"\n",
3244 sprn
, sprn
, ctx
->nip
);
3245 GEN_EXCP(ctx
, POWERPC_EXCP_PROGRAM
,
3246 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_SPR
);
3250 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
)
3256 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
)
3262 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
)
3266 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3267 crm
= CRM(ctx
->opcode
);
3268 if (likely((ctx
->opcode
& 0x00100000) || (crm
^ (crm
- 1)) == 0)) {
3270 gen_op_srli_T0(crn
* 4);
3271 gen_op_andi_T0(0xF);
3272 gen_op_store_cro(7 - crn
);
3274 gen_op_store_cr(crm
);
3279 #if defined(TARGET_PPC64)
3280 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
)
3282 #if defined(CONFIG_USER_ONLY)
3283 GEN_EXCP_PRIVREG(ctx
);
3285 if (unlikely(!ctx
->supervisor
)) {
3286 GEN_EXCP_PRIVREG(ctx
);
3289 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3290 if (ctx
->opcode
& 0x00010000) {
3291 /* Special form that does not need any synchronisation */
3292 gen_op_update_riee();
3294 /* XXX: we need to update nip before the store
3295 * if we enter power saving mode, we will exit the loop
3296 * directly from ppc_store_msr
3298 gen_update_nip(ctx
, ctx
->nip
);
3300 /* Must stop the translation as machine state (may have) changed */
3301 /* Note that mtmsr is not always defined as context-synchronizing */
3302 ctx
->exception
= POWERPC_EXCP_STOP
;
3308 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
)
3310 #if defined(CONFIG_USER_ONLY)
3311 GEN_EXCP_PRIVREG(ctx
);
3313 if (unlikely(!ctx
->supervisor
)) {
3314 GEN_EXCP_PRIVREG(ctx
);
3317 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3318 if (ctx
->opcode
& 0x00010000) {
3319 /* Special form that does not need any synchronisation */
3320 gen_op_update_riee();
3322 /* XXX: we need to update nip before the store
3323 * if we enter power saving mode, we will exit the loop
3324 * directly from ppc_store_msr
3326 gen_update_nip(ctx
, ctx
->nip
);
3327 #if defined(TARGET_PPC64)
3329 gen_op_store_msr_32();
3333 /* Must stop the translation as machine state (may have) changed */
3334 /* Note that mtmsrd is not always defined as context-synchronizing */
3335 ctx
->exception
= POWERPC_EXCP_STOP
;
3341 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
)
3343 void (*write_cb
)(void *opaque
, int sprn
);
3344 uint32_t sprn
= SPR(ctx
->opcode
);
3346 #if !defined(CONFIG_USER_ONLY)
3347 if (ctx
->supervisor
== 2)
3348 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
3349 else if (ctx
->supervisor
)
3350 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
3353 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
3354 if (likely(write_cb
!= NULL
)) {
3355 if (likely(write_cb
!= SPR_NOACCESS
)) {
3356 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3357 (*write_cb
)(ctx
, sprn
);
3359 /* Privilege exception */
3360 if (loglevel
!= 0) {
3361 fprintf(logfile
, "Trying to write privileged spr %d %03x at "
3362 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3364 printf("Trying to write privileged spr %d %03x at " ADDRX
"\n",
3365 sprn
, sprn
, ctx
->nip
);
3366 GEN_EXCP_PRIVREG(ctx
);
3370 if (loglevel
!= 0) {
3371 fprintf(logfile
, "Trying to write invalid spr %d %03x at "
3372 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3374 printf("Trying to write invalid spr %d %03x at " ADDRX
"\n",
3375 sprn
, sprn
, ctx
->nip
);
3376 GEN_EXCP(ctx
, POWERPC_EXCP_PROGRAM
,
3377 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_SPR
);
3381 /*** Cache management ***/
3383 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
)
3385 /* XXX: specification says this is treated as a load by the MMU */
3386 gen_addr_reg_index(ctx
);
3390 /* dcbi (Supervisor only) */
3391 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
)
3393 #if defined(CONFIG_USER_ONLY)
3394 GEN_EXCP_PRIVOPC(ctx
);
3396 if (unlikely(!ctx
->supervisor
)) {
3397 GEN_EXCP_PRIVOPC(ctx
);
3400 gen_addr_reg_index(ctx
);
3401 /* XXX: specification says this should be treated as a store by the MMU */
3408 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
)
3410 /* XXX: specification say this is treated as a load by the MMU */
3411 gen_addr_reg_index(ctx
);
3416 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE
)
3418 /* interpreted as no-op */
3419 /* XXX: specification say this is treated as a load by the MMU
3420 * but does not generate any exception
3425 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE
)
3427 /* interpreted as no-op */
3428 /* XXX: specification say this is treated as a load by the MMU
3429 * but does not generate any exception
3434 #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3435 static GenOpFunc
*gen_op_dcbz
[4][NB_MEM_FUNCS
] = {
3436 /* 32 bytes cache line size */
3438 #define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3439 #define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3440 #define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3441 #define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3442 #define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3443 #define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3444 #define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3445 #define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3446 GEN_MEM_FUNCS(dcbz_l32
),
3448 /* 64 bytes cache line size */
3450 #define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3451 #define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3452 #define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3453 #define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3454 #define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3455 #define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3456 #define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3457 #define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3458 GEN_MEM_FUNCS(dcbz_l64
),
3460 /* 128 bytes cache line size */
3462 #define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3463 #define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3464 #define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3465 #define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3466 #define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3467 #define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3468 #define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3469 #define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3470 GEN_MEM_FUNCS(dcbz_l128
),
3472 /* tunable cache line size */
3474 #define gen_op_dcbz_le_raw gen_op_dcbz_raw
3475 #define gen_op_dcbz_le_user gen_op_dcbz_user
3476 #define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3477 #define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3478 #define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3479 #define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3480 #define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3481 #define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3482 GEN_MEM_FUNCS(dcbz
),
3486 static always_inline
void handler_dcbz (DisasContext
*ctx
,
3487 int dcache_line_size
)
3491 switch (dcache_line_size
) {
3508 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ
)
3510 gen_addr_reg_index(ctx
);
3511 handler_dcbz(ctx
, ctx
->dcache_line_size
);
3512 gen_op_check_reservation();
3515 GEN_HANDLER2(dcbz_970
, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT
)
3517 gen_addr_reg_index(ctx
);
3518 if (ctx
->opcode
& 0x00200000)
3519 handler_dcbz(ctx
, ctx
->dcache_line_size
);
3521 handler_dcbz(ctx
, -1);
3522 gen_op_check_reservation();
3526 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3527 #define gen_op_icbi_le_raw gen_op_icbi_raw
3528 #define gen_op_icbi_le_user gen_op_icbi_user
3529 #define gen_op_icbi_le_kernel gen_op_icbi_kernel
3530 #define gen_op_icbi_le_hypv gen_op_icbi_hypv
3531 #define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
3532 #define gen_op_icbi_le_64_user gen_op_icbi_64_user
3533 #define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3534 #define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
3535 static GenOpFunc
*gen_op_icbi
[NB_MEM_FUNCS
] = {
3536 GEN_MEM_FUNCS(icbi
),
3539 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
)
3541 /* NIP cannot be restored if the memory exception comes from an helper */
3542 gen_update_nip(ctx
, ctx
->nip
- 4);
3543 gen_addr_reg_index(ctx
);
3549 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
)
3551 /* interpreted as no-op */
3552 /* XXX: specification say this is treated as a store by the MMU
3553 * but does not generate any exception
3557 /*** Segment register manipulation ***/
3558 /* Supervisor only: */
3560 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
)
3562 #if defined(CONFIG_USER_ONLY)
3563 GEN_EXCP_PRIVREG(ctx
);
3565 if (unlikely(!ctx
->supervisor
)) {
3566 GEN_EXCP_PRIVREG(ctx
);
3569 gen_op_set_T1(SR(ctx
->opcode
));
3571 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3576 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
)
3578 #if defined(CONFIG_USER_ONLY)
3579 GEN_EXCP_PRIVREG(ctx
);
3581 if (unlikely(!ctx
->supervisor
)) {
3582 GEN_EXCP_PRIVREG(ctx
);
3585 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3588 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3593 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
)
3595 #if defined(CONFIG_USER_ONLY)
3596 GEN_EXCP_PRIVREG(ctx
);
3598 if (unlikely(!ctx
->supervisor
)) {
3599 GEN_EXCP_PRIVREG(ctx
);
3602 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3603 gen_op_set_T1(SR(ctx
->opcode
));
3609 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
)
3611 #if defined(CONFIG_USER_ONLY)
3612 GEN_EXCP_PRIVREG(ctx
);
3614 if (unlikely(!ctx
->supervisor
)) {
3615 GEN_EXCP_PRIVREG(ctx
);
3618 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3619 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3625 #if defined(TARGET_PPC64)
3626 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3628 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
)
3630 #if defined(CONFIG_USER_ONLY)
3631 GEN_EXCP_PRIVREG(ctx
);
3633 if (unlikely(!ctx
->supervisor
)) {
3634 GEN_EXCP_PRIVREG(ctx
);
3637 gen_op_set_T1(SR(ctx
->opcode
));
3639 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3644 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
3647 #if defined(CONFIG_USER_ONLY)
3648 GEN_EXCP_PRIVREG(ctx
);
3650 if (unlikely(!ctx
->supervisor
)) {
3651 GEN_EXCP_PRIVREG(ctx
);
3654 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3657 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3662 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
)
3664 #if defined(CONFIG_USER_ONLY)
3665 GEN_EXCP_PRIVREG(ctx
);
3667 if (unlikely(!ctx
->supervisor
)) {
3668 GEN_EXCP_PRIVREG(ctx
);
3671 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3672 gen_op_set_T1(SR(ctx
->opcode
));
3678 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
3681 #if defined(CONFIG_USER_ONLY)
3682 GEN_EXCP_PRIVREG(ctx
);
3684 if (unlikely(!ctx
->supervisor
)) {
3685 GEN_EXCP_PRIVREG(ctx
);
3688 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3689 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3694 #endif /* defined(TARGET_PPC64) */
3696 /*** Lookaside buffer management ***/
3697 /* Optional & supervisor only: */
3699 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
)
3701 #if defined(CONFIG_USER_ONLY)
3702 GEN_EXCP_PRIVOPC(ctx
);
3704 if (unlikely(!ctx
->supervisor
)) {
3706 fprintf(logfile
, "%s: ! supervisor\n", __func__
);
3707 GEN_EXCP_PRIVOPC(ctx
);
3715 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
)
3717 #if defined(CONFIG_USER_ONLY)
3718 GEN_EXCP_PRIVOPC(ctx
);
3720 if (unlikely(!ctx
->supervisor
)) {
3721 GEN_EXCP_PRIVOPC(ctx
);
3724 gen_op_load_gpr_T0(rB(ctx
->opcode
));
3725 #if defined(TARGET_PPC64)
3735 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
)
3737 #if defined(CONFIG_USER_ONLY)
3738 GEN_EXCP_PRIVOPC(ctx
);
3740 if (unlikely(!ctx
->supervisor
)) {
3741 GEN_EXCP_PRIVOPC(ctx
);
3744 /* This has no effect: it should ensure that all previous
3745 * tlbie have completed
3751 #if defined(TARGET_PPC64)
3753 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
)
3755 #if defined(CONFIG_USER_ONLY)
3756 GEN_EXCP_PRIVOPC(ctx
);
3758 if (unlikely(!ctx
->supervisor
)) {
3760 fprintf(logfile
, "%s: ! supervisor\n", __func__
);
3761 GEN_EXCP_PRIVOPC(ctx
);
3769 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
)
3771 #if defined(CONFIG_USER_ONLY)
3772 GEN_EXCP_PRIVOPC(ctx
);
3774 if (unlikely(!ctx
->supervisor
)) {
3775 GEN_EXCP_PRIVOPC(ctx
);
3778 gen_op_load_gpr_T0(rB(ctx
->opcode
));
3784 /*** External control ***/
3786 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
3787 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
3788 static GenOpFunc
*gen_op_eciwx
[NB_MEM_FUNCS
] = {
3789 GEN_MEM_FUNCS(eciwx
),
3791 static GenOpFunc
*gen_op_ecowx
[NB_MEM_FUNCS
] = {
3792 GEN_MEM_FUNCS(ecowx
),
3796 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
)
3798 /* Should check EAR[E] & alignment ! */
3799 gen_addr_reg_index(ctx
);
3801 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3805 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
)
3807 /* Should check EAR[E] & alignment ! */
3808 gen_addr_reg_index(ctx
);
3809 gen_op_load_gpr_T1(rS(ctx
->opcode
));
3813 /* PowerPC 601 specific instructions */
3815 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
)
3817 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3819 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3820 if (unlikely(Rc(ctx
->opcode
) != 0))
3825 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
)
3827 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3828 gen_op_POWER_abso();
3829 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3830 if (unlikely(Rc(ctx
->opcode
) != 0))
3835 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
)
3837 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3838 gen_op_POWER_clcs();
3839 /* Rc=1 sets CR0 to an undefined state */
3840 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3844 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
)
3846 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3847 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3849 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3850 if (unlikely(Rc(ctx
->opcode
) != 0))
3855 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
)
3857 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3858 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3859 gen_op_POWER_divo();
3860 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3861 if (unlikely(Rc(ctx
->opcode
) != 0))
3866 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
)
3868 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3869 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3870 gen_op_POWER_divs();
3871 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3872 if (unlikely(Rc(ctx
->opcode
) != 0))
3876 /* divso - divso. */
3877 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
)
3879 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3880 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3881 gen_op_POWER_divso();
3882 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3883 if (unlikely(Rc(ctx
->opcode
) != 0))
3888 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
)
3890 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3891 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3893 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3894 if (unlikely(Rc(ctx
->opcode
) != 0))
3899 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
)
3901 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3902 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3903 gen_op_POWER_dozo();
3904 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3905 if (unlikely(Rc(ctx
->opcode
) != 0))
3910 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
)
3912 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3913 gen_op_set_T1(SIMM(ctx
->opcode
));
3915 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3918 /* As lscbx load from memory byte after byte, it's always endian safe.
3919 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
3921 #define op_POWER_lscbx(start, ra, rb) \
3922 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
3923 #define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
3924 #define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
3925 #define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
3926 #define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
3927 #define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
3928 #define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
3929 #define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
3930 #define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
3931 #define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
3932 #define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
3933 #define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
3934 #define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
3935 static GenOpFunc3
*gen_op_POWER_lscbx
[NB_MEM_FUNCS
] = {
3936 GEN_MEM_FUNCS(POWER_lscbx
),
3939 /* lscbx - lscbx. */
3940 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
)
3942 int ra
= rA(ctx
->opcode
);
3943 int rb
= rB(ctx
->opcode
);
3945 gen_addr_reg_index(ctx
);
3949 /* NIP cannot be restored if the memory exception comes from an helper */
3950 gen_update_nip(ctx
, ctx
->nip
- 4);
3951 gen_op_load_xer_bc();
3952 gen_op_load_xer_cmp();
3953 op_POWER_lscbx(rD(ctx
->opcode
), ra
, rb
);
3954 gen_op_store_xer_bc();
3955 if (unlikely(Rc(ctx
->opcode
) != 0))
3959 /* maskg - maskg. */
3960 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
)
3962 gen_op_load_gpr_T0(rS(ctx
->opcode
));
3963 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3964 gen_op_POWER_maskg();
3965 gen_op_store_T0_gpr(rA(ctx
->opcode
));
3966 if (unlikely(Rc(ctx
->opcode
) != 0))
3970 /* maskir - maskir. */
3971 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
)
3973 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3974 gen_op_load_gpr_T1(rS(ctx
->opcode
));
3975 gen_op_load_gpr_T2(rB(ctx
->opcode
));
3976 gen_op_POWER_maskir();
3977 gen_op_store_T0_gpr(rA(ctx
->opcode
));
3978 if (unlikely(Rc(ctx
->opcode
) != 0))
3983 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
)
3985 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3986 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3988 gen_op_store_T0_gpr(rD(ctx
->opcode
));
3989 if (unlikely(Rc(ctx
->opcode
) != 0))
3994 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
)
3996 gen_op_load_gpr_T0(rA(ctx
->opcode
));
3997 gen_op_load_gpr_T1(rB(ctx
->opcode
));
3998 gen_op_POWER_mulo();
3999 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4000 if (unlikely(Rc(ctx
->opcode
) != 0))
4005 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
)
4007 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4008 gen_op_POWER_nabs();
4009 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4010 if (unlikely(Rc(ctx
->opcode
) != 0))
4014 /* nabso - nabso. */
4015 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
)
4017 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4018 gen_op_POWER_nabso();
4019 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4020 if (unlikely(Rc(ctx
->opcode
) != 0))
4025 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
)
4029 mb
= MB(ctx
->opcode
);
4030 me
= ME(ctx
->opcode
);
4031 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4032 gen_op_load_gpr_T1(rA(ctx
->opcode
));
4033 gen_op_load_gpr_T2(rB(ctx
->opcode
));
4034 gen_op_POWER_rlmi(MASK(mb
, me
), ~MASK(mb
, me
));
4035 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4036 if (unlikely(Rc(ctx
->opcode
) != 0))
4041 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
)
4043 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4044 gen_op_load_gpr_T1(rA(ctx
->opcode
));
4045 gen_op_load_gpr_T2(rB(ctx
->opcode
));
4046 gen_op_POWER_rrib();
4047 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4048 if (unlikely(Rc(ctx
->opcode
) != 0))
4053 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
)
4055 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4056 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4058 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4059 if (unlikely(Rc(ctx
->opcode
) != 0))
4064 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
)
4066 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4067 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4068 gen_op_POWER_sleq();
4069 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4070 if (unlikely(Rc(ctx
->opcode
) != 0))
4075 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
)
4077 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4078 gen_op_set_T1(SH(ctx
->opcode
));
4080 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4081 if (unlikely(Rc(ctx
->opcode
) != 0))
4085 /* slliq - slliq. */
4086 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
)
4088 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4089 gen_op_set_T1(SH(ctx
->opcode
));
4090 gen_op_POWER_sleq();
4091 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4092 if (unlikely(Rc(ctx
->opcode
) != 0))
4097 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
)
4099 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4100 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4101 gen_op_POWER_sllq();
4102 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4103 if (unlikely(Rc(ctx
->opcode
) != 0))
4108 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
)
4110 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4111 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4113 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4114 if (unlikely(Rc(ctx
->opcode
) != 0))
4118 /* sraiq - sraiq. */
4119 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
)
4121 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4122 gen_op_set_T1(SH(ctx
->opcode
));
4123 gen_op_POWER_sraq();
4124 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4125 if (unlikely(Rc(ctx
->opcode
) != 0))
4130 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
)
4132 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4133 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4134 gen_op_POWER_sraq();
4135 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4136 if (unlikely(Rc(ctx
->opcode
) != 0))
4141 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
)
4143 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4144 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4146 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4147 if (unlikely(Rc(ctx
->opcode
) != 0))
4152 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
)
4154 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4155 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4156 gen_op_POWER_srea();
4157 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4158 if (unlikely(Rc(ctx
->opcode
) != 0))
4163 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
)
4165 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4166 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4167 gen_op_POWER_sreq();
4168 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4169 if (unlikely(Rc(ctx
->opcode
) != 0))
4174 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
)
4176 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4177 gen_op_set_T1(SH(ctx
->opcode
));
4179 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4180 if (unlikely(Rc(ctx
->opcode
) != 0))
4185 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
)
4187 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4188 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4189 gen_op_set_T1(SH(ctx
->opcode
));
4190 gen_op_POWER_srlq();
4191 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4192 if (unlikely(Rc(ctx
->opcode
) != 0))
4197 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
)
4199 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4200 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4201 gen_op_POWER_srlq();
4202 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4203 if (unlikely(Rc(ctx
->opcode
) != 0))
4208 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
)
4210 gen_op_load_gpr_T0(rS(ctx
->opcode
));
4211 gen_op_load_gpr_T1(rB(ctx
->opcode
));
4213 gen_op_store_T0_gpr(rA(ctx
->opcode
));
4214 if (unlikely(Rc(ctx
->opcode
) != 0))
4218 /* PowerPC 602 specific instructions */
4220 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
)
4223 GEN_EXCP_INVAL(ctx
);
4227 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
)
4230 GEN_EXCP_INVAL(ctx
);
4234 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
)
4236 #if defined(CONFIG_USER_ONLY)
4237 GEN_EXCP_PRIVOPC(ctx
);
4239 if (unlikely(!ctx
->supervisor
)) {
4240 GEN_EXCP_PRIVOPC(ctx
);
4243 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4245 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4249 /* 602 - 603 - G2 TLB management */
4251 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
)
4253 #if defined(CONFIG_USER_ONLY)
4254 GEN_EXCP_PRIVOPC(ctx
);
4256 if (unlikely(!ctx
->supervisor
)) {
4257 GEN_EXCP_PRIVOPC(ctx
);
4260 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4266 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
)
4268 #if defined(CONFIG_USER_ONLY)
4269 GEN_EXCP_PRIVOPC(ctx
);
4271 if (unlikely(!ctx
->supervisor
)) {
4272 GEN_EXCP_PRIVOPC(ctx
);
4275 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4280 /* 74xx TLB management */
4282 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
)
4284 #if defined(CONFIG_USER_ONLY)
4285 GEN_EXCP_PRIVOPC(ctx
);
4287 if (unlikely(!ctx
->supervisor
)) {
4288 GEN_EXCP_PRIVOPC(ctx
);
4291 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4292 gen_op_74xx_tlbld();
4297 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
)
4299 #if defined(CONFIG_USER_ONLY)
4300 GEN_EXCP_PRIVOPC(ctx
);
4302 if (unlikely(!ctx
->supervisor
)) {
4303 GEN_EXCP_PRIVOPC(ctx
);
4306 gen_op_load_gpr_T0(rB(ctx
->opcode
));
4307 gen_op_74xx_tlbli();
4311 /* POWER instructions not in PowerPC 601 */
4313 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
)
4315 /* Cache line flush: implemented as no-op */
4319 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
)
4321 /* Cache line invalidate: privileged and treated as no-op */
4322 #if defined(CONFIG_USER_ONLY)
4323 GEN_EXCP_PRIVOPC(ctx
);
4325 if (unlikely(!ctx
->supervisor
)) {
4326 GEN_EXCP_PRIVOPC(ctx
);
4333 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
)
4335 /* Data cache line store: treated as no-op */
4338 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
)
4340 #if defined(CONFIG_USER_ONLY)
4341 GEN_EXCP_PRIVOPC(ctx
);
4343 if (unlikely(!ctx
->supervisor
)) {
4344 GEN_EXCP_PRIVOPC(ctx
);
4347 int ra
= rA(ctx
->opcode
);
4348 int rd
= rD(ctx
->opcode
);
4350 gen_addr_reg_index(ctx
);
4351 gen_op_POWER_mfsri();
4352 gen_op_store_T0_gpr(rd
);
4353 if (ra
!= 0 && ra
!= rd
)
4354 gen_op_store_T1_gpr(ra
);
4358 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
)
4360 #if defined(CONFIG_USER_ONLY)
4361 GEN_EXCP_PRIVOPC(ctx
);
4363 if (unlikely(!ctx
->supervisor
)) {
4364 GEN_EXCP_PRIVOPC(ctx
);
4367 gen_addr_reg_index(ctx
);
4369 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4373 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
)
4375 #if defined(CONFIG_USER_ONLY)
4376 GEN_EXCP_PRIVOPC(ctx
);
4378 if (unlikely(!ctx
->supervisor
)) {
4379 GEN_EXCP_PRIVOPC(ctx
);
4382 gen_op_POWER_rfsvc();
4387 /* svc is not implemented for now */
4389 /* POWER2 specific instructions */
4390 /* Quad manipulation (load/store two floats at a time) */
4391 /* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
4392 #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4393 #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4394 #define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4395 #define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4396 #define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4397 #define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4398 #define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4399 #define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4400 #define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4401 #define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4402 #define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4403 #define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4404 #define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4405 #define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4406 #define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4407 #define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4408 #define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4409 #define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4410 static GenOpFunc
*gen_op_POWER2_lfq
[NB_MEM_FUNCS
] = {
4411 GEN_MEM_FUNCS(POWER2_lfq
),
4413 static GenOpFunc
*gen_op_POWER2_stfq
[NB_MEM_FUNCS
] = {
4414 GEN_MEM_FUNCS(POWER2_stfq
),
4418 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4420 /* NIP cannot be restored if the memory exception comes from an helper */
4421 gen_update_nip(ctx
, ctx
->nip
- 4);
4422 gen_addr_imm_index(ctx
, 0);
4424 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4425 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4429 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4431 int ra
= rA(ctx
->opcode
);
4433 /* NIP cannot be restored if the memory exception comes from an helper */
4434 gen_update_nip(ctx
, ctx
->nip
- 4);
4435 gen_addr_imm_index(ctx
, 0);
4437 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4438 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4440 gen_op_store_T0_gpr(ra
);
4444 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
)
4446 int ra
= rA(ctx
->opcode
);
4448 /* NIP cannot be restored if the memory exception comes from an helper */
4449 gen_update_nip(ctx
, ctx
->nip
- 4);
4450 gen_addr_reg_index(ctx
);
4452 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4453 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4455 gen_op_store_T0_gpr(ra
);
4459 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
)
4461 /* NIP cannot be restored if the memory exception comes from an helper */
4462 gen_update_nip(ctx
, ctx
->nip
- 4);
4463 gen_addr_reg_index(ctx
);
4465 gen_op_store_FT0_fpr(rD(ctx
->opcode
));
4466 gen_op_store_FT1_fpr(rD(ctx
->opcode
) + 1);
4470 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4472 /* NIP cannot be restored if the memory exception comes from an helper */
4473 gen_update_nip(ctx
, ctx
->nip
- 4);
4474 gen_addr_imm_index(ctx
, 0);
4475 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4476 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4481 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
4483 int ra
= rA(ctx
->opcode
);
4485 /* NIP cannot be restored if the memory exception comes from an helper */
4486 gen_update_nip(ctx
, ctx
->nip
- 4);
4487 gen_addr_imm_index(ctx
, 0);
4488 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4489 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4492 gen_op_store_T0_gpr(ra
);
4496 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
)
4498 int ra
= rA(ctx
->opcode
);
4500 /* NIP cannot be restored if the memory exception comes from an helper */
4501 gen_update_nip(ctx
, ctx
->nip
- 4);
4502 gen_addr_reg_index(ctx
);
4503 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4504 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4507 gen_op_store_T0_gpr(ra
);
4511 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
)
4513 /* NIP cannot be restored if the memory exception comes from an helper */
4514 gen_update_nip(ctx
, ctx
->nip
- 4);
4515 gen_addr_reg_index(ctx
);
4516 gen_op_load_fpr_FT0(rS(ctx
->opcode
));
4517 gen_op_load_fpr_FT1(rS(ctx
->opcode
) + 1);
4521 /* BookE specific instructions */
4522 /* XXX: not implemented on 440 ? */
4523 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT
)
4526 GEN_EXCP_INVAL(ctx
);
4529 /* XXX: not implemented on 440 ? */
4530 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT
)
4532 #if defined(CONFIG_USER_ONLY)
4533 GEN_EXCP_PRIVOPC(ctx
);
4535 if (unlikely(!ctx
->supervisor
)) {
4536 GEN_EXCP_PRIVOPC(ctx
);
4539 gen_addr_reg_index(ctx
);
4540 /* Use the same micro-ops as for tlbie */
4541 #if defined(TARGET_PPC64)
4550 /* All 405 MAC instructions are translated here */
4551 static always_inline
void gen_405_mulladd_insn (DisasContext
*ctx
,
4553 int ra
, int rb
, int rt
, int Rc
)
4555 gen_op_load_gpr_T0(ra
);
4556 gen_op_load_gpr_T1(rb
);
4557 switch (opc3
& 0x0D) {
4559 /* macchw - macchw. - macchwo - macchwo. */
4560 /* macchws - macchws. - macchwso - macchwso. */
4561 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4562 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4563 /* mulchw - mulchw. */
4564 gen_op_405_mulchw();
4567 /* macchwu - macchwu. - macchwuo - macchwuo. */
4568 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4569 /* mulchwu - mulchwu. */
4570 gen_op_405_mulchwu();
4573 /* machhw - machhw. - machhwo - machhwo. */
4574 /* machhws - machhws. - machhwso - machhwso. */
4575 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4576 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4577 /* mulhhw - mulhhw. */
4578 gen_op_405_mulhhw();
4581 /* machhwu - machhwu. - machhwuo - machhwuo. */
4582 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4583 /* mulhhwu - mulhhwu. */
4584 gen_op_405_mulhhwu();
4587 /* maclhw - maclhw. - maclhwo - maclhwo. */
4588 /* maclhws - maclhws. - maclhwso - maclhwso. */
4589 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4590 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4591 /* mullhw - mullhw. */
4592 gen_op_405_mullhw();
4595 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4596 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4597 /* mullhwu - mullhwu. */
4598 gen_op_405_mullhwu();
4602 /* nmultiply-and-accumulate (0x0E) */
4606 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4607 gen_op_load_gpr_T2(rt
);
4608 gen_op_move_T1_T0();
4609 gen_op_405_add_T0_T2();
4612 /* Check overflow */
4614 gen_op_check_addo();
4616 gen_op_405_check_ovu();
4621 gen_op_405_check_sat();
4623 gen_op_405_check_satu();
4625 gen_op_store_T0_gpr(rt
);
4626 if (unlikely(Rc
) != 0) {
4632 #define GEN_MAC_HANDLER(name, opc2, opc3) \
4633 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
4635 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4636 rD(ctx->opcode), Rc(ctx->opcode)); \
4639 /* macchw - macchw. */
4640 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
4641 /* macchwo - macchwo. */
4642 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
4643 /* macchws - macchws. */
4644 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
4645 /* macchwso - macchwso. */
4646 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
4647 /* macchwsu - macchwsu. */
4648 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
4649 /* macchwsuo - macchwsuo. */
4650 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
4651 /* macchwu - macchwu. */
4652 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
4653 /* macchwuo - macchwuo. */
4654 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
4655 /* machhw - machhw. */
4656 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
4657 /* machhwo - machhwo. */
4658 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
4659 /* machhws - machhws. */
4660 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
4661 /* machhwso - machhwso. */
4662 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
4663 /* machhwsu - machhwsu. */
4664 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
4665 /* machhwsuo - machhwsuo. */
4666 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
4667 /* machhwu - machhwu. */
4668 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
4669 /* machhwuo - machhwuo. */
4670 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
4671 /* maclhw - maclhw. */
4672 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
4673 /* maclhwo - maclhwo. */
4674 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
4675 /* maclhws - maclhws. */
4676 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
4677 /* maclhwso - maclhwso. */
4678 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
4679 /* maclhwu - maclhwu. */
4680 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
4681 /* maclhwuo - maclhwuo. */
4682 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
4683 /* maclhwsu - maclhwsu. */
4684 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
4685 /* maclhwsuo - maclhwsuo. */
4686 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
4687 /* nmacchw - nmacchw. */
4688 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
4689 /* nmacchwo - nmacchwo. */
4690 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
4691 /* nmacchws - nmacchws. */
4692 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
4693 /* nmacchwso - nmacchwso. */
4694 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
4695 /* nmachhw - nmachhw. */
4696 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
4697 /* nmachhwo - nmachhwo. */
4698 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
4699 /* nmachhws - nmachhws. */
4700 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
4701 /* nmachhwso - nmachhwso. */
4702 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
4703 /* nmaclhw - nmaclhw. */
4704 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
4705 /* nmaclhwo - nmaclhwo. */
4706 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
4707 /* nmaclhws - nmaclhws. */
4708 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
4709 /* nmaclhwso - nmaclhwso. */
4710 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
4712 /* mulchw - mulchw. */
4713 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
4714 /* mulchwu - mulchwu. */
4715 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
4716 /* mulhhw - mulhhw. */
4717 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
4718 /* mulhhwu - mulhhwu. */
4719 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
4720 /* mullhw - mullhw. */
4721 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
4722 /* mullhwu - mullhwu. */
4723 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
4726 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON
)
4728 #if defined(CONFIG_USER_ONLY)
4729 GEN_EXCP_PRIVREG(ctx
);
4731 uint32_t dcrn
= SPR(ctx
->opcode
);
4733 if (unlikely(!ctx
->supervisor
)) {
4734 GEN_EXCP_PRIVREG(ctx
);
4737 gen_op_set_T0(dcrn
);
4739 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4744 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON
)
4746 #if defined(CONFIG_USER_ONLY)
4747 GEN_EXCP_PRIVREG(ctx
);
4749 uint32_t dcrn
= SPR(ctx
->opcode
);
4751 if (unlikely(!ctx
->supervisor
)) {
4752 GEN_EXCP_PRIVREG(ctx
);
4755 gen_op_set_T0(dcrn
);
4756 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4762 /* XXX: not implemented on 440 ? */
4763 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT
)
4765 #if defined(CONFIG_USER_ONLY)
4766 GEN_EXCP_PRIVREG(ctx
);
4768 if (unlikely(!ctx
->supervisor
)) {
4769 GEN_EXCP_PRIVREG(ctx
);
4772 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4774 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4775 /* Note: Rc update flag set leads to undefined state of Rc0 */
4780 /* XXX: not implemented on 440 ? */
4781 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT
)
4783 #if defined(CONFIG_USER_ONLY)
4784 GEN_EXCP_PRIVREG(ctx
);
4786 if (unlikely(!ctx
->supervisor
)) {
4787 GEN_EXCP_PRIVREG(ctx
);
4790 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4791 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4793 /* Note: Rc update flag set leads to undefined state of Rc0 */
4797 /* mfdcrux (PPC 460) : user-mode access to DCR */
4798 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
)
4800 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4802 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4803 /* Note: Rc update flag set leads to undefined state of Rc0 */
4806 /* mtdcrux (PPC 460) : user-mode access to DCR */
4807 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
)
4809 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4810 gen_op_load_gpr_T1(rS(ctx
->opcode
));
4812 /* Note: Rc update flag set leads to undefined state of Rc0 */
4816 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
)
4818 #if defined(CONFIG_USER_ONLY)
4819 GEN_EXCP_PRIVOPC(ctx
);
4821 if (unlikely(!ctx
->supervisor
)) {
4822 GEN_EXCP_PRIVOPC(ctx
);
4825 /* interpreted as no-op */
4830 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
)
4832 #if defined(CONFIG_USER_ONLY)
4833 GEN_EXCP_PRIVOPC(ctx
);
4835 if (unlikely(!ctx
->supervisor
)) {
4836 GEN_EXCP_PRIVOPC(ctx
);
4839 gen_addr_reg_index(ctx
);
4841 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4846 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
)
4848 /* interpreted as no-op */
4849 /* XXX: specification say this is treated as a load by the MMU
4850 * but does not generate any exception
4855 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
)
4857 #if defined(CONFIG_USER_ONLY)
4858 GEN_EXCP_PRIVOPC(ctx
);
4860 if (unlikely(!ctx
->supervisor
)) {
4861 GEN_EXCP_PRIVOPC(ctx
);
4864 /* interpreted as no-op */
4869 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
)
4871 #if defined(CONFIG_USER_ONLY)
4872 GEN_EXCP_PRIVOPC(ctx
);
4874 if (unlikely(!ctx
->supervisor
)) {
4875 GEN_EXCP_PRIVOPC(ctx
);
4878 /* interpreted as no-op */
4882 /* rfci (supervisor only) */
4883 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
)
4885 #if defined(CONFIG_USER_ONLY)
4886 GEN_EXCP_PRIVOPC(ctx
);
4888 if (unlikely(!ctx
->supervisor
)) {
4889 GEN_EXCP_PRIVOPC(ctx
);
4892 /* Restore CPU state */
4898 GEN_HANDLER(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
)
4900 #if defined(CONFIG_USER_ONLY)
4901 GEN_EXCP_PRIVOPC(ctx
);
4903 if (unlikely(!ctx
->supervisor
)) {
4904 GEN_EXCP_PRIVOPC(ctx
);
4907 /* Restore CPU state */
4913 /* BookE specific */
4914 /* XXX: not implemented on 440 ? */
4915 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT
)
4917 #if defined(CONFIG_USER_ONLY)
4918 GEN_EXCP_PRIVOPC(ctx
);
4920 if (unlikely(!ctx
->supervisor
)) {
4921 GEN_EXCP_PRIVOPC(ctx
);
4924 /* Restore CPU state */
4930 /* XXX: not implemented on 440 ? */
4931 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
)
4933 #if defined(CONFIG_USER_ONLY)
4934 GEN_EXCP_PRIVOPC(ctx
);
4936 if (unlikely(!ctx
->supervisor
)) {
4937 GEN_EXCP_PRIVOPC(ctx
);
4940 /* Restore CPU state */
4946 /* TLB management - PowerPC 405 implementation */
4948 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
)
4950 #if defined(CONFIG_USER_ONLY)
4951 GEN_EXCP_PRIVOPC(ctx
);
4953 if (unlikely(!ctx
->supervisor
)) {
4954 GEN_EXCP_PRIVOPC(ctx
);
4957 switch (rB(ctx
->opcode
)) {
4959 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4960 gen_op_4xx_tlbre_hi();
4961 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4964 gen_op_load_gpr_T0(rA(ctx
->opcode
));
4965 gen_op_4xx_tlbre_lo();
4966 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4969 GEN_EXCP_INVAL(ctx
);
4975 /* tlbsx - tlbsx. */
4976 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
)
4978 #if defined(CONFIG_USER_ONLY)
4979 GEN_EXCP_PRIVOPC(ctx
);
4981 if (unlikely(!ctx
->supervisor
)) {
4982 GEN_EXCP_PRIVOPC(ctx
);
4985 gen_addr_reg_index(ctx
);
4987 if (Rc(ctx
->opcode
))
4988 gen_op_4xx_tlbsx_check();
4989 gen_op_store_T0_gpr(rD(ctx
->opcode
));
4994 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
)
4996 #if defined(CONFIG_USER_ONLY)
4997 GEN_EXCP_PRIVOPC(ctx
);
4999 if (unlikely(!ctx
->supervisor
)) {
5000 GEN_EXCP_PRIVOPC(ctx
);
5003 switch (rB(ctx
->opcode
)) {
5005 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5006 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5007 gen_op_4xx_tlbwe_hi();
5010 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5011 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5012 gen_op_4xx_tlbwe_lo();
5015 GEN_EXCP_INVAL(ctx
);
5021 /* TLB management - PowerPC 440 implementation */
5023 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
)
5025 #if defined(CONFIG_USER_ONLY)
5026 GEN_EXCP_PRIVOPC(ctx
);
5028 if (unlikely(!ctx
->supervisor
)) {
5029 GEN_EXCP_PRIVOPC(ctx
);
5032 switch (rB(ctx
->opcode
)) {
5036 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5037 gen_op_440_tlbre(rB(ctx
->opcode
));
5038 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5041 GEN_EXCP_INVAL(ctx
);
5047 /* tlbsx - tlbsx. */
5048 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
)
5050 #if defined(CONFIG_USER_ONLY)
5051 GEN_EXCP_PRIVOPC(ctx
);
5053 if (unlikely(!ctx
->supervisor
)) {
5054 GEN_EXCP_PRIVOPC(ctx
);
5057 gen_addr_reg_index(ctx
);
5059 if (Rc(ctx
->opcode
))
5060 gen_op_4xx_tlbsx_check();
5061 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5066 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
)
5068 #if defined(CONFIG_USER_ONLY)
5069 GEN_EXCP_PRIVOPC(ctx
);
5071 if (unlikely(!ctx
->supervisor
)) {
5072 GEN_EXCP_PRIVOPC(ctx
);
5075 switch (rB(ctx
->opcode
)) {
5079 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5080 gen_op_load_gpr_T1(rS(ctx
->opcode
));
5081 gen_op_440_tlbwe(rB(ctx
->opcode
));
5084 GEN_EXCP_INVAL(ctx
);
5091 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON
)
5093 #if defined(CONFIG_USER_ONLY)
5094 GEN_EXCP_PRIVOPC(ctx
);
5096 if (unlikely(!ctx
->supervisor
)) {
5097 GEN_EXCP_PRIVOPC(ctx
);
5100 gen_op_load_gpr_T0(rD(ctx
->opcode
));
5102 /* Stop translation to have a chance to raise an exception
5103 * if we just set msr_ee to 1
5110 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON
)
5112 #if defined(CONFIG_USER_ONLY)
5113 GEN_EXCP_PRIVOPC(ctx
);
5115 if (unlikely(!ctx
->supervisor
)) {
5116 GEN_EXCP_PRIVOPC(ctx
);
5119 gen_op_set_T0(ctx
->opcode
& 0x00010000);
5121 /* Stop translation to have a chance to raise an exception
5122 * if we just set msr_ee to 1
5128 /* PowerPC 440 specific instructions */
5130 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
)
5132 gen_op_load_gpr_T0(rS(ctx
->opcode
));
5133 gen_op_load_gpr_T1(rB(ctx
->opcode
));
5135 gen_op_store_T0_gpr(rA(ctx
->opcode
));
5136 gen_op_store_xer_bc();
5137 if (Rc(ctx
->opcode
)) {
5138 gen_op_440_dlmzb_update_Rc();
5139 gen_op_store_T0_crf(0);
5143 /* mbar replaces eieio on 440 */
5144 GEN_HANDLER(mbar
, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE
)
5146 /* interpreted as no-op */
5149 /* msync replaces sync on 440 */
5150 GEN_HANDLER(msync
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
)
5152 /* interpreted as no-op */
5156 GEN_HANDLER2(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE
)
5158 /* interpreted as no-op */
5159 /* XXX: specification say this is treated as a load by the MMU
5160 * but does not generate any exception
5164 /*** Altivec vector extension ***/
5165 /* Altivec registers moves */
5166 GEN32(gen_op_load_avr_A0
, gen_op_load_avr_A0_avr
);
5167 GEN32(gen_op_load_avr_A1
, gen_op_load_avr_A1_avr
);
5168 GEN32(gen_op_load_avr_A2
, gen_op_load_avr_A2_avr
);
5170 GEN32(gen_op_store_A0_avr
, gen_op_store_A0_avr_avr
);
5171 GEN32(gen_op_store_A1_avr
, gen_op_store_A1_avr_avr
);
5173 GEN32(gen_op_store_A2_avr
, gen_op_store_A2_avr_avr
);
5176 #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5177 #define OP_VR_LD_TABLE(name) \
5178 static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5179 GEN_MEM_FUNCS(vr_l##name), \
5181 #define OP_VR_ST_TABLE(name) \
5182 static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5183 GEN_MEM_FUNCS(vr_st##name), \
5186 #define GEN_VR_LDX(name, opc2, opc3) \
5187 GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5189 if (unlikely(!ctx->altivec_enabled)) { \
5190 GEN_EXCP_NO_VR(ctx); \
5193 gen_addr_reg_index(ctx); \
5194 op_vr_ldst(vr_l##name); \
5195 gen_op_store_A0_avr(rD(ctx->opcode)); \
5198 #define GEN_VR_STX(name, opc2, opc3) \
5199 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5201 if (unlikely(!ctx->altivec_enabled)) { \
5202 GEN_EXCP_NO_VR(ctx); \
5205 gen_addr_reg_index(ctx); \
5206 gen_op_load_avr_A0(rS(ctx->opcode)); \
5207 op_vr_ldst(vr_st##name); \
5211 GEN_VR_LDX(vx
, 0x07, 0x03);
5212 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5213 #define gen_op_vr_lvxl gen_op_vr_lvx
5214 GEN_VR_LDX(vxl
, 0x07, 0x0B);
5217 GEN_VR_STX(vx
, 0x07, 0x07);
5218 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5219 #define gen_op_vr_stvxl gen_op_vr_stvx
5220 GEN_VR_STX(vxl
, 0x07, 0x0F);
5222 /*** SPE extension ***/
5223 /* Register moves */
5224 #if !defined(TARGET_PPC64)
5226 GEN32(gen_op_load_gpr64_T0
, gen_op_load_gpr64_T0_gpr
);
5227 GEN32(gen_op_load_gpr64_T1
, gen_op_load_gpr64_T1_gpr
);
5229 GEN32(gen_op_load_gpr64_T2
, gen_op_load_gpr64_T2_gpr
);
5232 GEN32(gen_op_store_T0_gpr64
, gen_op_store_T0_gpr64_gpr
);
5233 GEN32(gen_op_store_T1_gpr64
, gen_op_store_T1_gpr64_gpr
);
5235 GEN32(gen_op_store_T2_gpr64
, gen_op_store_T2_gpr64_gpr
);
5238 #else /* !defined(TARGET_PPC64) */
5240 /* No specific load/store functions: GPRs are already 64 bits */
5241 #define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
5242 #define gen_op_load_gpr64_T1 gen_op_load_gpr_T1
5244 #define gen_op_load_gpr64_T2 gen_op_load_gpr_T2
5247 #define gen_op_store_T0_gpr64 gen_op_store_T0_gpr
5248 #define gen_op_store_T1_gpr64 gen_op_store_T1_gpr
5250 #define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
5253 #endif /* !defined(TARGET_PPC64) */
5255 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5256 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5258 if (Rc(ctx->opcode)) \
5264 /* Handler for undefined SPE opcodes */
5265 static always_inline
void gen_speundef (DisasContext
*ctx
)
5267 GEN_EXCP_INVAL(ctx
);
5270 /* SPE load and stores */
5271 static always_inline
void gen_addr_spe_imm_index (DisasContext
*ctx
, int sh
)
5273 target_long simm
= rB(ctx
->opcode
);
5275 if (rA(ctx
->opcode
) == 0) {
5276 gen_set_T0(simm
<< sh
);
5278 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5279 if (likely(simm
!= 0))
5280 gen_op_addi(simm
<< sh
);
5284 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5285 #define OP_SPE_LD_TABLE(name) \
5286 static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5287 GEN_MEM_FUNCS(spe_l##name), \
5289 #define OP_SPE_ST_TABLE(name) \
5290 static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5291 GEN_MEM_FUNCS(spe_st##name), \
5294 #define GEN_SPE_LD(name, sh) \
5295 static always_inline void gen_evl##name (DisasContext *ctx) \
5297 if (unlikely(!ctx->spe_enabled)) { \
5298 GEN_EXCP_NO_AP(ctx); \
5301 gen_addr_spe_imm_index(ctx, sh); \
5302 op_spe_ldst(spe_l##name); \
5303 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5306 #define GEN_SPE_LDX(name) \
5307 static always_inline void gen_evl##name##x (DisasContext *ctx) \
5309 if (unlikely(!ctx->spe_enabled)) { \
5310 GEN_EXCP_NO_AP(ctx); \
5313 gen_addr_reg_index(ctx); \
5314 op_spe_ldst(spe_l##name); \
5315 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5318 #define GEN_SPEOP_LD(name, sh) \
5319 OP_SPE_LD_TABLE(name); \
5320 GEN_SPE_LD(name, sh); \
5323 #define GEN_SPE_ST(name, sh) \
5324 static always_inline void gen_evst##name (DisasContext *ctx) \
5326 if (unlikely(!ctx->spe_enabled)) { \
5327 GEN_EXCP_NO_AP(ctx); \
5330 gen_addr_spe_imm_index(ctx, sh); \
5331 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5332 op_spe_ldst(spe_st##name); \
5335 #define GEN_SPE_STX(name) \
5336 static always_inline void gen_evst##name##x (DisasContext *ctx) \
5338 if (unlikely(!ctx->spe_enabled)) { \
5339 GEN_EXCP_NO_AP(ctx); \
5342 gen_addr_reg_index(ctx); \
5343 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5344 op_spe_ldst(spe_st##name); \
5347 #define GEN_SPEOP_ST(name, sh) \
5348 OP_SPE_ST_TABLE(name); \
5349 GEN_SPE_ST(name, sh); \
5352 #define GEN_SPEOP_LDST(name, sh) \
5353 GEN_SPEOP_LD(name, sh); \
5354 GEN_SPEOP_ST(name, sh)
5356 /* SPE arithmetic and logic */
5357 #define GEN_SPEOP_ARITH2(name) \
5358 static always_inline void gen_##name (DisasContext *ctx) \
5360 if (unlikely(!ctx->spe_enabled)) { \
5361 GEN_EXCP_NO_AP(ctx); \
5364 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5365 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5367 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5370 #define GEN_SPEOP_ARITH1(name) \
5371 static always_inline void gen_##name (DisasContext *ctx) \
5373 if (unlikely(!ctx->spe_enabled)) { \
5374 GEN_EXCP_NO_AP(ctx); \
5377 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5379 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5382 #define GEN_SPEOP_COMP(name) \
5383 static always_inline void gen_##name (DisasContext *ctx) \
5385 if (unlikely(!ctx->spe_enabled)) { \
5386 GEN_EXCP_NO_AP(ctx); \
5389 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5390 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5392 gen_op_store_T0_crf(crfD(ctx->opcode)); \
5396 GEN_SPEOP_ARITH2(evand
);
5397 GEN_SPEOP_ARITH2(evandc
);
5398 GEN_SPEOP_ARITH2(evxor
);
5399 GEN_SPEOP_ARITH2(evor
);
5400 GEN_SPEOP_ARITH2(evnor
);
5401 GEN_SPEOP_ARITH2(eveqv
);
5402 GEN_SPEOP_ARITH2(evorc
);
5403 GEN_SPEOP_ARITH2(evnand
);
5404 GEN_SPEOP_ARITH2(evsrwu
);
5405 GEN_SPEOP_ARITH2(evsrws
);
5406 GEN_SPEOP_ARITH2(evslw
);
5407 GEN_SPEOP_ARITH2(evrlw
);
5408 GEN_SPEOP_ARITH2(evmergehi
);
5409 GEN_SPEOP_ARITH2(evmergelo
);
5410 GEN_SPEOP_ARITH2(evmergehilo
);
5411 GEN_SPEOP_ARITH2(evmergelohi
);
5414 GEN_SPEOP_ARITH2(evaddw
);
5415 GEN_SPEOP_ARITH2(evsubfw
);
5416 GEN_SPEOP_ARITH1(evabs
);
5417 GEN_SPEOP_ARITH1(evneg
);
5418 GEN_SPEOP_ARITH1(evextsb
);
5419 GEN_SPEOP_ARITH1(evextsh
);
5420 GEN_SPEOP_ARITH1(evrndw
);
5421 GEN_SPEOP_ARITH1(evcntlzw
);
5422 GEN_SPEOP_ARITH1(evcntlsw
);
5423 static always_inline
void gen_brinc (DisasContext
*ctx
)
5425 /* Note: brinc is usable even if SPE is disabled */
5426 gen_op_load_gpr_T0(rA(ctx
->opcode
));
5427 gen_op_load_gpr_T1(rB(ctx
->opcode
));
5429 gen_op_store_T0_gpr(rD(ctx
->opcode
));
5432 #define GEN_SPEOP_ARITH_IMM2(name) \
5433 static always_inline void gen_##name##i (DisasContext *ctx) \
5435 if (unlikely(!ctx->spe_enabled)) { \
5436 GEN_EXCP_NO_AP(ctx); \
5439 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5440 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5442 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5445 #define GEN_SPEOP_LOGIC_IMM2(name) \
5446 static always_inline void gen_##name##i (DisasContext *ctx) \
5448 if (unlikely(!ctx->spe_enabled)) { \
5449 GEN_EXCP_NO_AP(ctx); \
5452 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5453 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5455 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5458 GEN_SPEOP_ARITH_IMM2(evaddw
);
5459 #define gen_evaddiw gen_evaddwi
5460 GEN_SPEOP_ARITH_IMM2(evsubfw
);
5461 #define gen_evsubifw gen_evsubfwi
5462 GEN_SPEOP_LOGIC_IMM2(evslw
);
5463 GEN_SPEOP_LOGIC_IMM2(evsrwu
);
5464 #define gen_evsrwis gen_evsrwsi
5465 GEN_SPEOP_LOGIC_IMM2(evsrws
);
5466 #define gen_evsrwiu gen_evsrwui
5467 GEN_SPEOP_LOGIC_IMM2(evrlw
);
5469 static always_inline
void gen_evsplati (DisasContext
*ctx
)
5471 int32_t imm
= (int32_t)(rA(ctx
->opcode
) << 27) >> 27;
5473 gen_op_splatwi_T0_64(imm
);
5474 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
5477 static always_inline
void gen_evsplatfi (DisasContext
*ctx
)
5479 uint32_t imm
= rA(ctx
->opcode
) << 27;
5481 gen_op_splatwi_T0_64(imm
);
5482 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
5486 GEN_SPEOP_COMP(evcmpgtu
);
5487 GEN_SPEOP_COMP(evcmpgts
);
5488 GEN_SPEOP_COMP(evcmpltu
);
5489 GEN_SPEOP_COMP(evcmplts
);
5490 GEN_SPEOP_COMP(evcmpeq
);
5492 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, PPC_SPE
); ////
5493 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, PPC_SPE
);
5494 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, PPC_SPE
); ////
5495 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, PPC_SPE
);
5496 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, PPC_SPE
); ////
5497 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, PPC_SPE
); ////
5498 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, PPC_SPE
); ////
5499 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x00000000, PPC_SPE
); //
5500 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0x00000000, PPC_SPE
); ////
5501 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, PPC_SPE
); ////
5502 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, PPC_SPE
); ////
5503 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, PPC_SPE
); ////
5504 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0x00000000, PPC_SPE
); ////
5505 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, PPC_SPE
); ////
5506 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, PPC_SPE
); ////
5507 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, PPC_SPE
);
5508 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, PPC_SPE
); ////
5509 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, PPC_SPE
);
5510 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, PPC_SPE
); //
5511 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, PPC_SPE
);
5512 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, PPC_SPE
); ////
5513 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, PPC_SPE
); ////
5514 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, PPC_SPE
); ////
5515 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, PPC_SPE
); ////
5516 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, PPC_SPE
); ////
5518 static always_inline
void gen_evsel (DisasContext
*ctx
)
5520 if (unlikely(!ctx
->spe_enabled
)) {
5521 GEN_EXCP_NO_AP(ctx
);
5524 gen_op_load_crf_T0(ctx
->opcode
& 0x7);
5525 gen_op_load_gpr64_T0(rA(ctx
->opcode
));
5526 gen_op_load_gpr64_T1(rB(ctx
->opcode
));
5528 gen_op_store_T0_gpr64(rD(ctx
->opcode
));
5531 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
)
5535 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
)
5539 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
)
5543 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
)
5548 /* Load and stores */
5549 #if defined(TARGET_PPC64)
5550 /* In that case, we already have 64 bits load & stores
5551 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
5553 #define gen_op_spe_ldd_raw gen_op_ld_raw
5554 #define gen_op_spe_ldd_user gen_op_ld_user
5555 #define gen_op_spe_ldd_kernel gen_op_ld_kernel
5556 #define gen_op_spe_ldd_hypv gen_op_ld_hypv
5557 #define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
5558 #define gen_op_spe_ldd_64_user gen_op_ld_64_user
5559 #define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
5560 #define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
5561 #define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
5562 #define gen_op_spe_ldd_le_user gen_op_ld_le_user
5563 #define gen_op_spe_ldd_le_kernel gen_op_ld_le_kernel
5564 #define gen_op_spe_ldd_le_hypv gen_op_ld_le_hypv
5565 #define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
5566 #define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
5567 #define gen_op_spe_ldd_le_64_kernel gen_op_ld_le_64_kernel
5568 #define gen_op_spe_ldd_le_64_hypv gen_op_ld_le_64_hypv
5569 #define gen_op_spe_stdd_raw gen_op_std_raw
5570 #define gen_op_spe_stdd_user gen_op_std_user
5571 #define gen_op_spe_stdd_kernel gen_op_std_kernel
5572 #define gen_op_spe_stdd_hypv gen_op_std_hypv
5573 #define gen_op_spe_stdd_64_raw gen_op_std_64_raw
5574 #define gen_op_spe_stdd_64_user gen_op_std_64_user
5575 #define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
5576 #define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
5577 #define gen_op_spe_stdd_le_raw gen_op_std_le_raw
5578 #define gen_op_spe_stdd_le_user gen_op_std_le_user
5579 #define gen_op_spe_stdd_le_kernel gen_op_std_le_kernel
5580 #define gen_op_spe_stdd_le_hypv gen_op_std_le_hypv
5581 #define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
5582 #define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
5583 #define gen_op_spe_stdd_le_64_kernel gen_op_std_le_64_kernel
5584 #define gen_op_spe_stdd_le_64_hypv gen_op_std_le_64_hypv
5585 #endif /* defined(TARGET_PPC64) */
5586 GEN_SPEOP_LDST(dd
, 3);
5587 GEN_SPEOP_LDST(dw
, 3);
5588 GEN_SPEOP_LDST(dh
, 3);
5589 GEN_SPEOP_LDST(whe
, 2);
5590 GEN_SPEOP_LD(whou
, 2);
5591 GEN_SPEOP_LD(whos
, 2);
5592 GEN_SPEOP_ST(who
, 2);
5594 #if defined(TARGET_PPC64)
5595 /* In that case, spe_stwwo is equivalent to stw */
5596 #define gen_op_spe_stwwo_raw gen_op_stw_raw
5597 #define gen_op_spe_stwwo_user gen_op_stw_user
5598 #define gen_op_spe_stwwo_kernel gen_op_stw_kernel
5599 #define gen_op_spe_stwwo_hypv gen_op_stw_hypv
5600 #define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
5601 #define gen_op_spe_stwwo_le_user gen_op_stw_le_user
5602 #define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
5603 #define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
5604 #define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
5605 #define gen_op_spe_stwwo_64_user gen_op_stw_64_user
5606 #define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
5607 #define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
5608 #define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
5609 #define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
5610 #define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
5611 #define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
5613 #define _GEN_OP_SPE_STWWE(suffix) \
5614 static always_inline void gen_op_spe_stwwe_##suffix (void) \
5616 gen_op_srli32_T1_64(); \
5617 gen_op_spe_stwwo_##suffix(); \
5619 #define _GEN_OP_SPE_STWWE_LE(suffix) \
5620 static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
5622 gen_op_srli32_T1_64(); \
5623 gen_op_spe_stwwo_le_##suffix(); \
5625 #if defined(TARGET_PPC64)
5626 #define GEN_OP_SPE_STWWE(suffix) \
5627 _GEN_OP_SPE_STWWE(suffix); \
5628 _GEN_OP_SPE_STWWE_LE(suffix); \
5629 static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
5631 gen_op_srli32_T1_64(); \
5632 gen_op_spe_stwwo_64_##suffix(); \
5634 static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
5636 gen_op_srli32_T1_64(); \
5637 gen_op_spe_stwwo_le_64_##suffix(); \
5640 #define GEN_OP_SPE_STWWE(suffix) \
5641 _GEN_OP_SPE_STWWE(suffix); \
5642 _GEN_OP_SPE_STWWE_LE(suffix)
5644 #if defined(CONFIG_USER_ONLY)
5645 GEN_OP_SPE_STWWE(raw
);
5646 #else /* defined(CONFIG_USER_ONLY) */
5647 GEN_OP_SPE_STWWE(user
);
5648 GEN_OP_SPE_STWWE(kernel
);
5649 GEN_OP_SPE_STWWE(hypv
);
5650 #endif /* defined(CONFIG_USER_ONLY) */
5651 GEN_SPEOP_ST(wwe
, 2);
5652 GEN_SPEOP_ST(wwo
, 2);
5654 #define GEN_SPE_LDSPLAT(name, op, suffix) \
5655 static always_inline void gen_op_spe_l##name##_##suffix (void) \
5657 gen_op_##op##_##suffix(); \
5658 gen_op_splatw_T1_64(); \
5661 #define GEN_OP_SPE_LHE(suffix) \
5662 static always_inline void gen_op_spe_lhe_##suffix (void) \
5664 gen_op_spe_lh_##suffix(); \
5665 gen_op_sli16_T1_64(); \
5668 #define GEN_OP_SPE_LHX(suffix) \
5669 static always_inline void gen_op_spe_lhx_##suffix (void) \
5671 gen_op_spe_lh_##suffix(); \
5672 gen_op_extsh_T1_64(); \
5675 #if defined(CONFIG_USER_ONLY)
5676 GEN_OP_SPE_LHE(raw
);
5677 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, raw
);
5678 GEN_OP_SPE_LHE(le_raw
);
5679 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_raw
);
5680 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, raw
);
5681 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_raw
);
5682 GEN_OP_SPE_LHX(raw
);
5683 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, raw
);
5684 GEN_OP_SPE_LHX(le_raw
);
5685 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_raw
);
5686 #if defined(TARGET_PPC64)
5687 GEN_OP_SPE_LHE(64_raw
);
5688 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_raw
);
5689 GEN_OP_SPE_LHE(le_64_raw
);
5690 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_raw
);
5691 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_raw
);
5692 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_raw
);
5693 GEN_OP_SPE_LHX(64_raw
);
5694 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_raw
);
5695 GEN_OP_SPE_LHX(le_64_raw
);
5696 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_raw
);
5699 GEN_OP_SPE_LHE(user
);
5700 GEN_OP_SPE_LHE(kernel
);
5701 GEN_OP_SPE_LHE(hypv
);
5702 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, user
);
5703 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, kernel
);
5704 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, hypv
);
5705 GEN_OP_SPE_LHE(le_user
);
5706 GEN_OP_SPE_LHE(le_kernel
);
5707 GEN_OP_SPE_LHE(le_hypv
);
5708 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_user
);
5709 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_kernel
);
5710 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_hypv
);
5711 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, user
);
5712 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, kernel
);
5713 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, hypv
);
5714 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_user
);
5715 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_kernel
);
5716 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_hypv
);
5717 GEN_OP_SPE_LHX(user
);
5718 GEN_OP_SPE_LHX(kernel
);
5719 GEN_OP_SPE_LHX(hypv
);
5720 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, user
);
5721 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, kernel
);
5722 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, hypv
);
5723 GEN_OP_SPE_LHX(le_user
);
5724 GEN_OP_SPE_LHX(le_kernel
);
5725 GEN_OP_SPE_LHX(le_hypv
);
5726 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_user
);
5727 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_kernel
);
5728 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_hypv
);
5729 #if defined(TARGET_PPC64)
5730 GEN_OP_SPE_LHE(64_user
);
5731 GEN_OP_SPE_LHE(64_kernel
);
5732 GEN_OP_SPE_LHE(64_hypv
);
5733 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_user
);
5734 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_kernel
);
5735 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, 64_hypv
);
5736 GEN_OP_SPE_LHE(le_64_user
);
5737 GEN_OP_SPE_LHE(le_64_kernel
);
5738 GEN_OP_SPE_LHE(le_64_hypv
);
5739 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_user
);
5740 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_kernel
);
5741 GEN_SPE_LDSPLAT(hhesplat
, spe_lhe
, le_64_hypv
);
5742 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_user
);
5743 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_kernel
);
5744 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, 64_hypv
);
5745 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_user
);
5746 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_kernel
);
5747 GEN_SPE_LDSPLAT(hhousplat
, spe_lh
, le_64_hypv
);
5748 GEN_OP_SPE_LHX(64_user
);
5749 GEN_OP_SPE_LHX(64_kernel
);
5750 GEN_OP_SPE_LHX(64_hypv
);
5751 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_user
);
5752 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_kernel
);
5753 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, 64_hypv
);
5754 GEN_OP_SPE_LHX(le_64_user
);
5755 GEN_OP_SPE_LHX(le_64_kernel
);
5756 GEN_OP_SPE_LHX(le_64_hypv
);
5757 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_user
);
5758 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_kernel
);
5759 GEN_SPE_LDSPLAT(hhossplat
, spe_lhx
, le_64_hypv
);
5762 GEN_SPEOP_LD(hhesplat
, 1);
5763 GEN_SPEOP_LD(hhousplat
, 1);
5764 GEN_SPEOP_LD(hhossplat
, 1);
5765 GEN_SPEOP_LD(wwsplat
, 2);
5766 GEN_SPEOP_LD(whsplat
, 2);
5768 GEN_SPE(evlddx
, evldd
, 0x00, 0x0C, 0x00000000, PPC_SPE
); //
5769 GEN_SPE(evldwx
, evldw
, 0x01, 0x0C, 0x00000000, PPC_SPE
); //
5770 GEN_SPE(evldhx
, evldh
, 0x02, 0x0C, 0x00000000, PPC_SPE
); //
5771 GEN_SPE(evlhhesplatx
, evlhhesplat
, 0x04, 0x0C, 0x00000000, PPC_SPE
); //
5772 GEN_SPE(evlhhousplatx
, evlhhousplat
, 0x06, 0x0C, 0x00000000, PPC_SPE
); //
5773 GEN_SPE(evlhhossplatx
, evlhhossplat
, 0x07, 0x0C, 0x00000000, PPC_SPE
); //
5774 GEN_SPE(evlwhex
, evlwhe
, 0x08, 0x0C, 0x00000000, PPC_SPE
); //
5775 GEN_SPE(evlwhoux
, evlwhou
, 0x0A, 0x0C, 0x00000000, PPC_SPE
); //
5776 GEN_SPE(evlwhosx
, evlwhos
, 0x0B, 0x0C, 0x00000000, PPC_SPE
); //
5777 GEN_SPE(evlwwsplatx
, evlwwsplat
, 0x0C, 0x0C, 0x00000000, PPC_SPE
); //
5778 GEN_SPE(evlwhsplatx
, evlwhsplat
, 0x0E, 0x0C, 0x00000000, PPC_SPE
); //
5779 GEN_SPE(evstddx
, evstdd
, 0x10, 0x0C, 0x00000000, PPC_SPE
); //
5780 GEN_SPE(evstdwx
, evstdw
, 0x11, 0x0C, 0x00000000, PPC_SPE
); //
5781 GEN_SPE(evstdhx
, evstdh
, 0x12, 0x0C, 0x00000000, PPC_SPE
); //
5782 GEN_SPE(evstwhex
, evstwhe
, 0x18, 0x0C, 0x00000000, PPC_SPE
); //
5783 GEN_SPE(evstwhox
, evstwho
, 0x1A, 0x0C, 0x00000000, PPC_SPE
); //
5784 GEN_SPE(evstwwex
, evstwwe
, 0x1C, 0x0C, 0x00000000, PPC_SPE
); //
5785 GEN_SPE(evstwwox
, evstwwo
, 0x1E, 0x0C, 0x00000000, PPC_SPE
); //
5787 /* Multiply and add - TODO */
5789 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0x00000000, PPC_SPE
);
5790 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0x00000000, PPC_SPE
);
5791 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, PPC_SPE
);
5792 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0x00000000, PPC_SPE
);
5793 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, PPC_SPE
);
5794 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0x00000000, PPC_SPE
);
5795 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0x00000000, PPC_SPE
);
5796 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0x00000000, PPC_SPE
);
5797 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, PPC_SPE
);
5798 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0x00000000, PPC_SPE
);
5799 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, PPC_SPE
);
5800 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0x00000000, PPC_SPE
);
5802 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0x00000000, PPC_SPE
);
5803 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, PPC_SPE
);
5804 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, PPC_SPE
);
5805 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0x00000000, PPC_SPE
);
5806 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0x00000000, PPC_SPE
);
5807 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, PPC_SPE
);
5808 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0x00000000, PPC_SPE
);
5809 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0x00000000, PPC_SPE
);
5810 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, PPC_SPE
);
5811 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, PPC_SPE
);
5812 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0x00000000, PPC_SPE
);
5813 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0x00000000, PPC_SPE
);
5814 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, PPC_SPE
);
5815 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0x00000000, PPC_SPE
);
5817 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, PPC_SPE
);
5818 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, PPC_SPE
);
5819 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, PPC_SPE
);
5820 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, PPC_SPE
);
5821 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, PPC_SPE
);
5822 GEN_SPE(evmra
, speundef
, 0x07, 0x13, 0x0000F800, PPC_SPE
);
5824 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, PPC_SPE
);
5825 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0x00000000, PPC_SPE
);
5826 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, PPC_SPE
);
5827 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0x00000000, PPC_SPE
);
5828 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, PPC_SPE
);
5829 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0x00000000, PPC_SPE
);
5830 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, PPC_SPE
);
5831 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0x00000000, PPC_SPE
);
5832 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, PPC_SPE
);
5833 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0x00000000, PPC_SPE
);
5834 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, PPC_SPE
);
5835 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0x00000000, PPC_SPE
);
5837 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, PPC_SPE
);
5838 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, PPC_SPE
);
5839 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0x00000000, PPC_SPE
);
5840 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, PPC_SPE
);
5841 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0x00000000, PPC_SPE
);
5843 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, PPC_SPE
);
5844 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0x00000000, PPC_SPE
);
5845 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, PPC_SPE
);
5846 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0x00000000, PPC_SPE
);
5847 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, PPC_SPE
);
5848 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0x00000000, PPC_SPE
);
5849 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, PPC_SPE
);
5850 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0x00000000, PPC_SPE
);
5851 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, PPC_SPE
);
5852 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0x00000000, PPC_SPE
);
5853 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, PPC_SPE
);
5854 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0x00000000, PPC_SPE
);
5856 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, PPC_SPE
);
5857 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, PPC_SPE
);
5858 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0x00000000, PPC_SPE
);
5859 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, PPC_SPE
);
5860 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0x00000000, PPC_SPE
);
5863 /*** SPE floating-point extension ***/
5864 #define GEN_SPEFPUOP_CONV(name) \
5865 static always_inline void gen_##name (DisasContext *ctx) \
5867 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5869 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5872 /* Single precision floating-point vectors operations */
5874 GEN_SPEOP_ARITH2(evfsadd
);
5875 GEN_SPEOP_ARITH2(evfssub
);
5876 GEN_SPEOP_ARITH2(evfsmul
);
5877 GEN_SPEOP_ARITH2(evfsdiv
);
5878 GEN_SPEOP_ARITH1(evfsabs
);
5879 GEN_SPEOP_ARITH1(evfsnabs
);
5880 GEN_SPEOP_ARITH1(evfsneg
);
5882 GEN_SPEFPUOP_CONV(evfscfui
);
5883 GEN_SPEFPUOP_CONV(evfscfsi
);
5884 GEN_SPEFPUOP_CONV(evfscfuf
);
5885 GEN_SPEFPUOP_CONV(evfscfsf
);
5886 GEN_SPEFPUOP_CONV(evfsctui
);
5887 GEN_SPEFPUOP_CONV(evfsctsi
);
5888 GEN_SPEFPUOP_CONV(evfsctuf
);
5889 GEN_SPEFPUOP_CONV(evfsctsf
);
5890 GEN_SPEFPUOP_CONV(evfsctuiz
);
5891 GEN_SPEFPUOP_CONV(evfsctsiz
);
5893 GEN_SPEOP_COMP(evfscmpgt
);
5894 GEN_SPEOP_COMP(evfscmplt
);
5895 GEN_SPEOP_COMP(evfscmpeq
);
5896 GEN_SPEOP_COMP(evfststgt
);
5897 GEN_SPEOP_COMP(evfststlt
);
5898 GEN_SPEOP_COMP(evfststeq
);
5900 /* Opcodes definitions */
5901 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, PPC_SPEFPU
); //
5902 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU
); //
5903 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU
); //
5904 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, PPC_SPEFPU
); //
5905 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, PPC_SPEFPU
); //
5906 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, PPC_SPEFPU
); //
5907 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, PPC_SPEFPU
); //
5908 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, PPC_SPEFPU
); //
5909 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU
); //
5910 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU
); //
5911 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU
); //
5912 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU
); //
5913 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU
); //
5914 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU
); //
5916 /* Single precision floating-point operations */
5918 GEN_SPEOP_ARITH2(efsadd
);
5919 GEN_SPEOP_ARITH2(efssub
);
5920 GEN_SPEOP_ARITH2(efsmul
);
5921 GEN_SPEOP_ARITH2(efsdiv
);
5922 GEN_SPEOP_ARITH1(efsabs
);
5923 GEN_SPEOP_ARITH1(efsnabs
);
5924 GEN_SPEOP_ARITH1(efsneg
);
5926 GEN_SPEFPUOP_CONV(efscfui
);
5927 GEN_SPEFPUOP_CONV(efscfsi
);
5928 GEN_SPEFPUOP_CONV(efscfuf
);
5929 GEN_SPEFPUOP_CONV(efscfsf
);
5930 GEN_SPEFPUOP_CONV(efsctui
);
5931 GEN_SPEFPUOP_CONV(efsctsi
);
5932 GEN_SPEFPUOP_CONV(efsctuf
);
5933 GEN_SPEFPUOP_CONV(efsctsf
);
5934 GEN_SPEFPUOP_CONV(efsctuiz
);
5935 GEN_SPEFPUOP_CONV(efsctsiz
);
5936 GEN_SPEFPUOP_CONV(efscfd
);
5938 GEN_SPEOP_COMP(efscmpgt
);
5939 GEN_SPEOP_COMP(efscmplt
);
5940 GEN_SPEOP_COMP(efscmpeq
);
5941 GEN_SPEOP_COMP(efststgt
);
5942 GEN_SPEOP_COMP(efststlt
);
5943 GEN_SPEOP_COMP(efststeq
);
5945 /* Opcodes definitions */
5946 GEN_SPE(efsadd
, efssub
, 0x00, 0x0A, 0x00000000, PPC_SPEFPU
); //
5947 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU
); //
5948 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU
); //
5949 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, PPC_SPEFPU
); //
5950 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, PPC_SPEFPU
); //
5951 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, PPC_SPEFPU
); //
5952 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, PPC_SPEFPU
); //
5953 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, PPC_SPEFPU
); //
5954 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU
); //
5955 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU
); //
5956 GEN_SPE(efsctuiz
, efsctsiz
, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU
); //
5957 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU
); //
5958 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU
); //
5960 /* Double precision floating-point operations */
5962 GEN_SPEOP_ARITH2(efdadd
);
5963 GEN_SPEOP_ARITH2(efdsub
);
5964 GEN_SPEOP_ARITH2(efdmul
);
5965 GEN_SPEOP_ARITH2(efddiv
);
5966 GEN_SPEOP_ARITH1(efdabs
);
5967 GEN_SPEOP_ARITH1(efdnabs
);
5968 GEN_SPEOP_ARITH1(efdneg
);
5971 GEN_SPEFPUOP_CONV(efdcfui
);
5972 GEN_SPEFPUOP_CONV(efdcfsi
);
5973 GEN_SPEFPUOP_CONV(efdcfuf
);
5974 GEN_SPEFPUOP_CONV(efdcfsf
);
5975 GEN_SPEFPUOP_CONV(efdctui
);
5976 GEN_SPEFPUOP_CONV(efdctsi
);
5977 GEN_SPEFPUOP_CONV(efdctuf
);
5978 GEN_SPEFPUOP_CONV(efdctsf
);
5979 GEN_SPEFPUOP_CONV(efdctuiz
);
5980 GEN_SPEFPUOP_CONV(efdctsiz
);
5981 GEN_SPEFPUOP_CONV(efdcfs
);
5982 GEN_SPEFPUOP_CONV(efdcfuid
);
5983 GEN_SPEFPUOP_CONV(efdcfsid
);
5984 GEN_SPEFPUOP_CONV(efdctuidz
);
5985 GEN_SPEFPUOP_CONV(efdctsidz
);
5987 GEN_SPEOP_COMP(efdcmpgt
);
5988 GEN_SPEOP_COMP(efdcmplt
);
5989 GEN_SPEOP_COMP(efdcmpeq
);
5990 GEN_SPEOP_COMP(efdtstgt
);
5991 GEN_SPEOP_COMP(efdtstlt
);
5992 GEN_SPEOP_COMP(efdtsteq
);
5994 /* Opcodes definitions */
5995 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, PPC_SPEFPU
); //
5996 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, PPC_SPEFPU
); //
5997 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU
); //
5998 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU
); //
5999 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, PPC_SPEFPU
); //
6000 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, PPC_SPEFPU
); //
6001 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, PPC_SPEFPU
); //
6002 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, PPC_SPEFPU
); //
6003 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, PPC_SPEFPU
); //
6004 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, PPC_SPEFPU
); //
6005 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU
); //
6006 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU
); //
6007 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU
); //
6008 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU
); //
6009 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU
); //
6010 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU
); //
6012 /* End opcode list */
6013 GEN_OPCODE_MARK(end
);
6015 #include "translate_init.c"
6016 #include "helper_regs.h"
6018 /*****************************************************************************/
6019 /* Misc PowerPC helpers */
6020 void cpu_dump_state (CPUState
*env
, FILE *f
,
6021 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6024 #if defined(TARGET_PPC64) || 1
6036 cpu_fprintf(f
, "NIP " ADDRX
" LR " ADDRX
" CTR " ADDRX
" XER %08x\n",
6037 env
->nip
, env
->lr
, env
->ctr
, hreg_load_xer(env
));
6038 cpu_fprintf(f
, "MSR " REGX FILL
" HID0 " REGX FILL
" HF " REGX FILL
6040 env
->msr
, env
->hflags
, env
->spr
[SPR_HID0
], env
->mmu_idx
);
6041 #if !defined(NO_TIMER_DUMP)
6042 cpu_fprintf(f
, "TB %08x %08x "
6043 #if !defined(CONFIG_USER_ONLY)
6047 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
6048 #if !defined(CONFIG_USER_ONLY)
6049 , cpu_ppc_load_decr(env
)
6053 for (i
= 0; i
< 32; i
++) {
6054 if ((i
& (RGPL
- 1)) == 0)
6055 cpu_fprintf(f
, "GPR%02d", i
);
6056 cpu_fprintf(f
, " " REGX
, (target_ulong
)env
->gpr
[i
]);
6057 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
6058 cpu_fprintf(f
, "\n");
6060 cpu_fprintf(f
, "CR ");
6061 for (i
= 0; i
< 8; i
++)
6062 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
6063 cpu_fprintf(f
, " [");
6064 for (i
= 0; i
< 8; i
++) {
6066 if (env
->crf
[i
] & 0x08)
6068 else if (env
->crf
[i
] & 0x04)
6070 else if (env
->crf
[i
] & 0x02)
6072 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
6074 cpu_fprintf(f
, " ] " FILL
"RES " REGX
"\n", env
->reserve
);
6075 for (i
= 0; i
< 32; i
++) {
6076 if ((i
& (RFPL
- 1)) == 0)
6077 cpu_fprintf(f
, "FPR%02d", i
);
6078 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
6079 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
6080 cpu_fprintf(f
, "\n");
6082 #if !defined(CONFIG_USER_ONLY)
6083 cpu_fprintf(f
, "SRR0 " REGX
" SRR1 " REGX
" SDR1 " REGX
"\n",
6084 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
], env
->sdr1
);
6092 void cpu_dump_statistics (CPUState
*env
, FILE*f
,
6093 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6096 #if defined(DO_PPC_STATISTICS)
6097 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
6101 for (op1
= 0; op1
< 64; op1
++) {
6103 if (is_indirect_opcode(handler
)) {
6104 t2
= ind_table(handler
);
6105 for (op2
= 0; op2
< 32; op2
++) {
6107 if (is_indirect_opcode(handler
)) {
6108 t3
= ind_table(handler
);
6109 for (op3
= 0; op3
< 32; op3
++) {
6111 if (handler
->count
== 0)
6113 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
6115 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
6117 handler
->count
, handler
->count
);
6120 if (handler
->count
== 0)
6122 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
6124 op1
, op2
, op1
, op2
, handler
->oname
,
6125 handler
->count
, handler
->count
);
6129 if (handler
->count
== 0)
6131 cpu_fprintf(f
, "%02x (%02x ) %16s: %016llx %lld\n",
6132 op1
, op1
, handler
->oname
,
6133 handler
->count
, handler
->count
);
6139 /*****************************************************************************/
6140 static always_inline
int gen_intermediate_code_internal (CPUState
*env
,
6141 TranslationBlock
*tb
,
6144 DisasContext ctx
, *ctxp
= &ctx
;
6145 opc_handler_t
**table
, *handler
;
6146 target_ulong pc_start
;
6147 uint16_t *gen_opc_end
;
6148 int supervisor
, little_endian
;
6149 int single_step
, branch_step
;
6153 gen_opc_ptr
= gen_opc_buf
;
6154 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
6155 gen_opparam_ptr
= gen_opparam_buf
;
6156 #if defined(OPTIMIZE_FPRF_UPDATE)
6157 gen_fprf_ptr
= gen_fprf_buf
;
6162 ctx
.exception
= POWERPC_EXCP_NONE
;
6163 ctx
.spr_cb
= env
->spr_cb
;
6164 supervisor
= env
->mmu_idx
;
6165 #if !defined(CONFIG_USER_ONLY)
6166 ctx
.supervisor
= supervisor
;
6168 little_endian
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
6169 #if defined(TARGET_PPC64)
6170 ctx
.sf_mode
= msr_sf
;
6171 ctx
.mem_idx
= (supervisor
<< 2) | (msr_sf
<< 1) | little_endian
;
6173 ctx
.mem_idx
= (supervisor
<< 1) | little_endian
;
6175 ctx
.dcache_line_size
= env
->dcache_line_size
;
6176 ctx
.fpu_enabled
= msr_fp
;
6177 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
6178 ctx
.spe_enabled
= msr_spe
;
6180 ctx
.spe_enabled
= 0;
6181 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
6182 ctx
.altivec_enabled
= msr_vr
;
6184 ctx
.altivec_enabled
= 0;
6185 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
6189 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
6193 ctx
.singlestep_enabled
= env
->singlestep_enabled
|| single_step
== 1;
6194 #if defined (DO_SINGLE_STEP) && 0
6195 /* Single step trace mode */
6198 /* Set env in case of segfault during code fetch */
6199 while (ctx
.exception
== POWERPC_EXCP_NONE
&& gen_opc_ptr
< gen_opc_end
) {
6200 if (unlikely(env
->nb_breakpoints
> 0)) {
6201 for (j
= 0; j
< env
->nb_breakpoints
; j
++) {
6202 if (env
->breakpoints
[j
] == ctx
.nip
) {
6203 gen_update_nip(&ctx
, ctx
.nip
);
6209 if (unlikely(search_pc
)) {
6210 j
= gen_opc_ptr
- gen_opc_buf
;
6214 gen_opc_instr_start
[lj
++] = 0;
6215 gen_opc_pc
[lj
] = ctx
.nip
;
6216 gen_opc_instr_start
[lj
] = 1;
6219 #if defined PPC_DEBUG_DISAS
6220 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6221 fprintf(logfile
, "----------------\n");
6222 fprintf(logfile
, "nip=" ADDRX
" super=%d ir=%d\n",
6223 ctx
.nip
, supervisor
, (int)msr_ir
);
6226 if (unlikely(little_endian
)) {
6227 ctx
.opcode
= bswap32(ldl_code(ctx
.nip
));
6229 ctx
.opcode
= ldl_code(ctx
.nip
);
6231 #if defined PPC_DEBUG_DISAS
6232 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6233 fprintf(logfile
, "translate opcode %08x (%02x %02x %02x) (%s)\n",
6234 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
6235 opc3(ctx
.opcode
), little_endian
? "little" : "big");
6239 table
= env
->opcodes
;
6240 handler
= table
[opc1(ctx
.opcode
)];
6241 if (is_indirect_opcode(handler
)) {
6242 table
= ind_table(handler
);
6243 handler
= table
[opc2(ctx
.opcode
)];
6244 if (is_indirect_opcode(handler
)) {
6245 table
= ind_table(handler
);
6246 handler
= table
[opc3(ctx
.opcode
)];
6249 /* Is opcode *REALLY* valid ? */
6250 if (unlikely(handler
->handler
== &gen_invalid
)) {
6251 if (loglevel
!= 0) {
6252 fprintf(logfile
, "invalid/unsupported opcode: "
6253 "%02x - %02x - %02x (%08x) 0x" ADDRX
" %d\n",
6254 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
6255 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
6257 printf("invalid/unsupported opcode: "
6258 "%02x - %02x - %02x (%08x) 0x" ADDRX
" %d\n",
6259 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
6260 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
6263 if (unlikely((ctx
.opcode
& handler
->inval
) != 0)) {
6264 if (loglevel
!= 0) {
6265 fprintf(logfile
, "invalid bits: %08x for opcode: "
6266 "%02x - %02x - %02x (%08x) 0x" ADDRX
"\n",
6267 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
6268 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
6269 ctx
.opcode
, ctx
.nip
- 4);
6271 printf("invalid bits: %08x for opcode: "
6272 "%02x - %02x - %02x (%08x) 0x" ADDRX
"\n",
6273 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
6274 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
6275 ctx
.opcode
, ctx
.nip
- 4);
6277 GEN_EXCP_INVAL(ctxp
);
6281 (*(handler
->handler
))(&ctx
);
6282 #if defined(DO_PPC_STATISTICS)
6285 /* Check trace mode exceptions */
6286 if (unlikely(branch_step
!= 0 &&
6287 ctx
.exception
== POWERPC_EXCP_BRANCH
)) {
6288 GEN_EXCP(ctxp
, POWERPC_EXCP_TRACE
, 0);
6289 } else if (unlikely(single_step
!= 0 &&
6290 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00 ||
6291 (ctx
.nip
& 0xFC) != 0x04) &&
6292 ctx
.exception
!= POWERPC_SYSCALL
&&
6293 ctx
.exception
!= POWERPC_EXCP_TRAP
)) {
6294 GEN_EXCP(ctxp
, POWERPC_EXCP_TRACE
, 0);
6295 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
6296 (env
->singlestep_enabled
))) {
6297 /* if we reach a page boundary or are single stepping, stop
6302 #if defined (DO_SINGLE_STEP)
6306 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
6307 gen_goto_tb(&ctx
, 0, ctx
.nip
);
6308 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
6310 /* Generate the return instruction */
6313 *gen_opc_ptr
= INDEX_op_end
;
6314 if (unlikely(search_pc
)) {
6315 j
= gen_opc_ptr
- gen_opc_buf
;
6318 gen_opc_instr_start
[lj
++] = 0;
6320 tb
->size
= ctx
.nip
- pc_start
;
6322 #if defined(DEBUG_DISAS)
6323 if (loglevel
& CPU_LOG_TB_CPU
) {
6324 fprintf(logfile
, "---------------- excp: %04x\n", ctx
.exception
);
6325 cpu_dump_state(env
, logfile
, fprintf
, 0);
6327 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6329 flags
= env
->bfd_mach
;
6330 flags
|= little_endian
<< 16;
6331 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
6332 target_disas(logfile
, pc_start
, ctx
.nip
- pc_start
, flags
);
6333 fprintf(logfile
, "\n");
6335 if (loglevel
& CPU_LOG_TB_OP
) {
6336 fprintf(logfile
, "OP:\n");
6337 dump_ops(gen_opc_buf
, gen_opparam_buf
);
6338 fprintf(logfile
, "\n");
6344 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
6346 return gen_intermediate_code_internal(env
, tb
, 0);
6349 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
6351 return gen_intermediate_code_internal(env
, tb
, 1);