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1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "disas.h"
28 #include "tcg-op.h"
29 #include "qemu-common.h"
30 #include "host-utils.h"
31
32 #include "helper.h"
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_ptr cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 #if !defined(TARGET_PPC64)
56 + 10*4 + 22*5 /* SPE GPRh */
57 #endif
58 + 10*4 + 22*5 /* FPR */
59 + 2*(10*6 + 22*7) /* AVRh, AVRl */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 #if !defined(TARGET_PPC64)
63 static TCGv cpu_gprh[32];
64 #endif
65 static TCGv_i64 cpu_fpr[32];
66 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
67 static TCGv_i32 cpu_crf[8];
68 static TCGv cpu_nip;
69 static TCGv cpu_msr;
70 static TCGv cpu_ctr;
71 static TCGv cpu_lr;
72 #if defined(TARGET_PPC64)
73 static TCGv cpu_cfar;
74 #endif
75 static TCGv cpu_xer;
76 static TCGv cpu_reserve;
77 static TCGv_i32 cpu_fpscr;
78 static TCGv_i32 cpu_access_type;
79
80 #include "gen-icount.h"
81
82 void ppc_translate_init(void)
83 {
84 int i;
85 char* p;
86 size_t cpu_reg_names_size;
87 static int done_init = 0;
88
89 if (done_init)
90 return;
91
92 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
93
94 p = cpu_reg_names;
95 cpu_reg_names_size = sizeof(cpu_reg_names);
96
97 for (i = 0; i < 8; i++) {
98 snprintf(p, cpu_reg_names_size, "crf%d", i);
99 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
100 offsetof(CPUState, crf[i]), p);
101 p += 5;
102 cpu_reg_names_size -= 5;
103 }
104
105 for (i = 0; i < 32; i++) {
106 snprintf(p, cpu_reg_names_size, "r%d", i);
107 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
108 offsetof(CPUState, gpr[i]), p);
109 p += (i < 10) ? 3 : 4;
110 cpu_reg_names_size -= (i < 10) ? 3 : 4;
111 #if !defined(TARGET_PPC64)
112 snprintf(p, cpu_reg_names_size, "r%dH", i);
113 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
114 offsetof(CPUState, gprh[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117 #endif
118
119 snprintf(p, cpu_reg_names_size, "fp%d", i);
120 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUState, fpr[i]), p);
122 p += (i < 10) ? 4 : 5;
123 cpu_reg_names_size -= (i < 10) ? 4 : 5;
124
125 snprintf(p, cpu_reg_names_size, "avr%dH", i);
126 #ifdef HOST_WORDS_BIGENDIAN
127 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
128 offsetof(CPUState, avr[i].u64[0]), p);
129 #else
130 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
131 offsetof(CPUState, avr[i].u64[1]), p);
132 #endif
133 p += (i < 10) ? 6 : 7;
134 cpu_reg_names_size -= (i < 10) ? 6 : 7;
135
136 snprintf(p, cpu_reg_names_size, "avr%dL", i);
137 #ifdef HOST_WORDS_BIGENDIAN
138 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
139 offsetof(CPUState, avr[i].u64[1]), p);
140 #else
141 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
142 offsetof(CPUState, avr[i].u64[0]), p);
143 #endif
144 p += (i < 10) ? 6 : 7;
145 cpu_reg_names_size -= (i < 10) ? 6 : 7;
146 }
147
148 cpu_nip = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUState, nip), "nip");
150
151 cpu_msr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUState, msr), "msr");
153
154 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
155 offsetof(CPUState, ctr), "ctr");
156
157 cpu_lr = tcg_global_mem_new(TCG_AREG0,
158 offsetof(CPUState, lr), "lr");
159
160 #if defined(TARGET_PPC64)
161 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUState, cfar), "cfar");
163 #endif
164
165 cpu_xer = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUState, xer), "xer");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
173 offsetof(CPUState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 struct opc_handler_t {
208 /* invalid bits */
209 uint32_t inval;
210 /* instruction type */
211 uint64_t type;
212 /* extended instruction type */
213 uint64_t type2;
214 /* handler */
215 void (*handler)(DisasContext *ctx);
216 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
217 const char *oname;
218 #endif
219 #if defined(DO_PPC_STATISTICS)
220 uint64_t count;
221 #endif
222 };
223
224 static inline void gen_reset_fpstatus(void)
225 {
226 gen_helper_reset_fpstatus();
227 }
228
229 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
230 {
231 TCGv_i32 t0 = tcg_temp_new_i32();
232
233 if (set_fprf != 0) {
234 /* This case might be optimized later */
235 tcg_gen_movi_i32(t0, 1);
236 gen_helper_compute_fprf(t0, arg, t0);
237 if (unlikely(set_rc)) {
238 tcg_gen_mov_i32(cpu_crf[1], t0);
239 }
240 gen_helper_float_check_status();
241 } else if (unlikely(set_rc)) {
242 /* We always need to compute fpcc */
243 tcg_gen_movi_i32(t0, 0);
244 gen_helper_compute_fprf(t0, arg, t0);
245 tcg_gen_mov_i32(cpu_crf[1], t0);
246 }
247
248 tcg_temp_free_i32(t0);
249 }
250
251 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
252 {
253 if (ctx->access_type != access_type) {
254 tcg_gen_movi_i32(cpu_access_type, access_type);
255 ctx->access_type = access_type;
256 }
257 }
258
259 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
260 {
261 #if defined(TARGET_PPC64)
262 if (ctx->sf_mode)
263 tcg_gen_movi_tl(cpu_nip, nip);
264 else
265 #endif
266 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
267 }
268
269 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
270 {
271 TCGv_i32 t0, t1;
272 if (ctx->exception == POWERPC_EXCP_NONE) {
273 gen_update_nip(ctx, ctx->nip);
274 }
275 t0 = tcg_const_i32(excp);
276 t1 = tcg_const_i32(error);
277 gen_helper_raise_exception_err(t0, t1);
278 tcg_temp_free_i32(t0);
279 tcg_temp_free_i32(t1);
280 ctx->exception = (excp);
281 }
282
283 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
284 {
285 TCGv_i32 t0;
286 if (ctx->exception == POWERPC_EXCP_NONE) {
287 gen_update_nip(ctx, ctx->nip);
288 }
289 t0 = tcg_const_i32(excp);
290 gen_helper_raise_exception(t0);
291 tcg_temp_free_i32(t0);
292 ctx->exception = (excp);
293 }
294
295 static inline void gen_debug_exception(DisasContext *ctx)
296 {
297 TCGv_i32 t0;
298
299 if (ctx->exception != POWERPC_EXCP_BRANCH)
300 gen_update_nip(ctx, ctx->nip);
301 t0 = tcg_const_i32(EXCP_DEBUG);
302 gen_helper_raise_exception(t0);
303 tcg_temp_free_i32(t0);
304 }
305
306 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
307 {
308 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
309 }
310
311 /* Stop translation */
312 static inline void gen_stop_exception(DisasContext *ctx)
313 {
314 gen_update_nip(ctx, ctx->nip);
315 ctx->exception = POWERPC_EXCP_STOP;
316 }
317
318 /* No need to update nip here, as execution flow will change */
319 static inline void gen_sync_exception(DisasContext *ctx)
320 {
321 ctx->exception = POWERPC_EXCP_SYNC;
322 }
323
324 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
325 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
326
327 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
328 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
329
330 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
331 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
332
333 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
334 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
335
336 typedef struct opcode_t {
337 unsigned char opc1, opc2, opc3;
338 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
339 unsigned char pad[5];
340 #else
341 unsigned char pad[1];
342 #endif
343 opc_handler_t handler;
344 const char *oname;
345 } opcode_t;
346
347 /*****************************************************************************/
348 /*** Instruction decoding ***/
349 #define EXTRACT_HELPER(name, shift, nb) \
350 static inline uint32_t name(uint32_t opcode) \
351 { \
352 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
353 }
354
355 #define EXTRACT_SHELPER(name, shift, nb) \
356 static inline int32_t name(uint32_t opcode) \
357 { \
358 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
359 }
360
361 /* Opcode part 1 */
362 EXTRACT_HELPER(opc1, 26, 6);
363 /* Opcode part 2 */
364 EXTRACT_HELPER(opc2, 1, 5);
365 /* Opcode part 3 */
366 EXTRACT_HELPER(opc3, 6, 5);
367 /* Update Cr0 flags */
368 EXTRACT_HELPER(Rc, 0, 1);
369 /* Destination */
370 EXTRACT_HELPER(rD, 21, 5);
371 /* Source */
372 EXTRACT_HELPER(rS, 21, 5);
373 /* First operand */
374 EXTRACT_HELPER(rA, 16, 5);
375 /* Second operand */
376 EXTRACT_HELPER(rB, 11, 5);
377 /* Third operand */
378 EXTRACT_HELPER(rC, 6, 5);
379 /*** Get CRn ***/
380 EXTRACT_HELPER(crfD, 23, 3);
381 EXTRACT_HELPER(crfS, 18, 3);
382 EXTRACT_HELPER(crbD, 21, 5);
383 EXTRACT_HELPER(crbA, 16, 5);
384 EXTRACT_HELPER(crbB, 11, 5);
385 /* SPR / TBL */
386 EXTRACT_HELPER(_SPR, 11, 10);
387 static inline uint32_t SPR(uint32_t opcode)
388 {
389 uint32_t sprn = _SPR(opcode);
390
391 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
392 }
393 /*** Get constants ***/
394 EXTRACT_HELPER(IMM, 12, 8);
395 /* 16 bits signed immediate value */
396 EXTRACT_SHELPER(SIMM, 0, 16);
397 /* 16 bits unsigned immediate value */
398 EXTRACT_HELPER(UIMM, 0, 16);
399 /* 5 bits signed immediate value */
400 EXTRACT_HELPER(SIMM5, 16, 5);
401 /* 5 bits signed immediate value */
402 EXTRACT_HELPER(UIMM5, 16, 5);
403 /* Bit count */
404 EXTRACT_HELPER(NB, 11, 5);
405 /* Shift count */
406 EXTRACT_HELPER(SH, 11, 5);
407 /* Vector shift count */
408 EXTRACT_HELPER(VSH, 6, 4);
409 /* Mask start */
410 EXTRACT_HELPER(MB, 6, 5);
411 /* Mask end */
412 EXTRACT_HELPER(ME, 1, 5);
413 /* Trap operand */
414 EXTRACT_HELPER(TO, 21, 5);
415
416 EXTRACT_HELPER(CRM, 12, 8);
417 EXTRACT_HELPER(FM, 17, 8);
418 EXTRACT_HELPER(SR, 16, 4);
419 EXTRACT_HELPER(FPIMM, 12, 4);
420
421 /*** Jump target decoding ***/
422 /* Displacement */
423 EXTRACT_SHELPER(d, 0, 16);
424 /* Immediate address */
425 static inline target_ulong LI(uint32_t opcode)
426 {
427 return (opcode >> 0) & 0x03FFFFFC;
428 }
429
430 static inline uint32_t BD(uint32_t opcode)
431 {
432 return (opcode >> 0) & 0xFFFC;
433 }
434
435 EXTRACT_HELPER(BO, 21, 5);
436 EXTRACT_HELPER(BI, 16, 5);
437 /* Absolute/relative address */
438 EXTRACT_HELPER(AA, 1, 1);
439 /* Link */
440 EXTRACT_HELPER(LK, 0, 1);
441
442 /* Create a mask between <start> and <end> bits */
443 static inline target_ulong MASK(uint32_t start, uint32_t end)
444 {
445 target_ulong ret;
446
447 #if defined(TARGET_PPC64)
448 if (likely(start == 0)) {
449 ret = UINT64_MAX << (63 - end);
450 } else if (likely(end == 63)) {
451 ret = UINT64_MAX >> start;
452 }
453 #else
454 if (likely(start == 0)) {
455 ret = UINT32_MAX << (31 - end);
456 } else if (likely(end == 31)) {
457 ret = UINT32_MAX >> start;
458 }
459 #endif
460 else {
461 ret = (((target_ulong)(-1ULL)) >> (start)) ^
462 (((target_ulong)(-1ULL) >> (end)) >> 1);
463 if (unlikely(start > end))
464 return ~ret;
465 }
466
467 return ret;
468 }
469
470 /*****************************************************************************/
471 /* PowerPC instructions table */
472
473 #if defined(DO_PPC_STATISTICS)
474 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
475 { \
476 .opc1 = op1, \
477 .opc2 = op2, \
478 .opc3 = op3, \
479 .pad = { 0, }, \
480 .handler = { \
481 .inval = invl, \
482 .type = _typ, \
483 .type2 = _typ2, \
484 .handler = &gen_##name, \
485 .oname = stringify(name), \
486 }, \
487 .oname = stringify(name), \
488 }
489 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
490 { \
491 .opc1 = op1, \
492 .opc2 = op2, \
493 .opc3 = op3, \
494 .pad = { 0, }, \
495 .handler = { \
496 .inval = invl, \
497 .type = _typ, \
498 .type2 = _typ2, \
499 .handler = &gen_##name, \
500 .oname = onam, \
501 }, \
502 .oname = onam, \
503 }
504 #else
505 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
506 { \
507 .opc1 = op1, \
508 .opc2 = op2, \
509 .opc3 = op3, \
510 .pad = { 0, }, \
511 .handler = { \
512 .inval = invl, \
513 .type = _typ, \
514 .type2 = _typ2, \
515 .handler = &gen_##name, \
516 }, \
517 .oname = stringify(name), \
518 }
519 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
520 { \
521 .opc1 = op1, \
522 .opc2 = op2, \
523 .opc3 = op3, \
524 .pad = { 0, }, \
525 .handler = { \
526 .inval = invl, \
527 .type = _typ, \
528 .type2 = _typ2, \
529 .handler = &gen_##name, \
530 }, \
531 .oname = onam, \
532 }
533 #endif
534
535 /* SPR load/store helpers */
536 static inline void gen_load_spr(TCGv t, int reg)
537 {
538 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
539 }
540
541 static inline void gen_store_spr(int reg, TCGv t)
542 {
543 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
544 }
545
546 /* Invalid instruction */
547 static void gen_invalid(DisasContext *ctx)
548 {
549 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
550 }
551
552 static opc_handler_t invalid_handler = {
553 .inval = 0xFFFFFFFF,
554 .type = PPC_NONE,
555 .type2 = PPC_NONE,
556 .handler = gen_invalid,
557 };
558
559 /*** Integer comparison ***/
560
561 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
562 {
563 int l1, l2, l3;
564
565 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
566 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
567 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
568
569 l1 = gen_new_label();
570 l2 = gen_new_label();
571 l3 = gen_new_label();
572 if (s) {
573 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
574 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
575 } else {
576 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
577 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
578 }
579 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
580 tcg_gen_br(l3);
581 gen_set_label(l1);
582 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
583 tcg_gen_br(l3);
584 gen_set_label(l2);
585 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
586 gen_set_label(l3);
587 }
588
589 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
590 {
591 TCGv t0 = tcg_const_local_tl(arg1);
592 gen_op_cmp(arg0, t0, s, crf);
593 tcg_temp_free(t0);
594 }
595
596 #if defined(TARGET_PPC64)
597 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
598 {
599 TCGv t0, t1;
600 t0 = tcg_temp_local_new();
601 t1 = tcg_temp_local_new();
602 if (s) {
603 tcg_gen_ext32s_tl(t0, arg0);
604 tcg_gen_ext32s_tl(t1, arg1);
605 } else {
606 tcg_gen_ext32u_tl(t0, arg0);
607 tcg_gen_ext32u_tl(t1, arg1);
608 }
609 gen_op_cmp(t0, t1, s, crf);
610 tcg_temp_free(t1);
611 tcg_temp_free(t0);
612 }
613
614 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
615 {
616 TCGv t0 = tcg_const_local_tl(arg1);
617 gen_op_cmp32(arg0, t0, s, crf);
618 tcg_temp_free(t0);
619 }
620 #endif
621
622 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
623 {
624 #if defined(TARGET_PPC64)
625 if (!(ctx->sf_mode))
626 gen_op_cmpi32(reg, 0, 1, 0);
627 else
628 #endif
629 gen_op_cmpi(reg, 0, 1, 0);
630 }
631
632 /* cmp */
633 static void gen_cmp(DisasContext *ctx)
634 {
635 #if defined(TARGET_PPC64)
636 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
637 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
638 1, crfD(ctx->opcode));
639 else
640 #endif
641 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
642 1, crfD(ctx->opcode));
643 }
644
645 /* cmpi */
646 static void gen_cmpi(DisasContext *ctx)
647 {
648 #if defined(TARGET_PPC64)
649 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
650 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
651 1, crfD(ctx->opcode));
652 else
653 #endif
654 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
655 1, crfD(ctx->opcode));
656 }
657
658 /* cmpl */
659 static void gen_cmpl(DisasContext *ctx)
660 {
661 #if defined(TARGET_PPC64)
662 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
663 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
664 0, crfD(ctx->opcode));
665 else
666 #endif
667 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
668 0, crfD(ctx->opcode));
669 }
670
671 /* cmpli */
672 static void gen_cmpli(DisasContext *ctx)
673 {
674 #if defined(TARGET_PPC64)
675 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
676 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
677 0, crfD(ctx->opcode));
678 else
679 #endif
680 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
681 0, crfD(ctx->opcode));
682 }
683
684 /* isel (PowerPC 2.03 specification) */
685 static void gen_isel(DisasContext *ctx)
686 {
687 int l1, l2;
688 uint32_t bi = rC(ctx->opcode);
689 uint32_t mask;
690 TCGv_i32 t0;
691
692 l1 = gen_new_label();
693 l2 = gen_new_label();
694
695 mask = 1 << (3 - (bi & 0x03));
696 t0 = tcg_temp_new_i32();
697 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
698 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
699 if (rA(ctx->opcode) == 0)
700 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
701 else
702 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
703 tcg_gen_br(l2);
704 gen_set_label(l1);
705 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
706 gen_set_label(l2);
707 tcg_temp_free_i32(t0);
708 }
709
710 /*** Integer arithmetic ***/
711
712 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
713 TCGv arg1, TCGv arg2, int sub)
714 {
715 int l1;
716 TCGv t0;
717
718 l1 = gen_new_label();
719 /* Start with XER OV disabled, the most likely case */
720 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
721 t0 = tcg_temp_local_new();
722 tcg_gen_xor_tl(t0, arg0, arg1);
723 #if defined(TARGET_PPC64)
724 if (!ctx->sf_mode)
725 tcg_gen_ext32s_tl(t0, t0);
726 #endif
727 if (sub)
728 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
729 else
730 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
731 tcg_gen_xor_tl(t0, arg1, arg2);
732 #if defined(TARGET_PPC64)
733 if (!ctx->sf_mode)
734 tcg_gen_ext32s_tl(t0, t0);
735 #endif
736 if (sub)
737 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
738 else
739 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
740 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
741 gen_set_label(l1);
742 tcg_temp_free(t0);
743 }
744
745 static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
746 TCGv arg2, int sub)
747 {
748 int l1 = gen_new_label();
749
750 #if defined(TARGET_PPC64)
751 if (!(ctx->sf_mode)) {
752 TCGv t0, t1;
753 t0 = tcg_temp_new();
754 t1 = tcg_temp_new();
755
756 tcg_gen_ext32u_tl(t0, arg1);
757 tcg_gen_ext32u_tl(t1, arg2);
758 if (sub) {
759 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
760 } else {
761 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
762 }
763 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
764 gen_set_label(l1);
765 tcg_temp_free(t0);
766 tcg_temp_free(t1);
767 } else
768 #endif
769 {
770 if (sub) {
771 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
772 } else {
773 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
774 }
775 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
776 gen_set_label(l1);
777 }
778 }
779
780 /* Common add function */
781 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
782 TCGv arg2, int add_ca, int compute_ca,
783 int compute_ov)
784 {
785 TCGv t0, t1;
786
787 if ((!compute_ca && !compute_ov) ||
788 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
789 t0 = ret;
790 } else {
791 t0 = tcg_temp_local_new();
792 }
793
794 if (add_ca) {
795 t1 = tcg_temp_local_new();
796 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
797 tcg_gen_shri_tl(t1, t1, XER_CA);
798 } else {
799 TCGV_UNUSED(t1);
800 }
801
802 if (compute_ca && compute_ov) {
803 /* Start with XER CA and OV disabled, the most likely case */
804 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
805 } else if (compute_ca) {
806 /* Start with XER CA disabled, the most likely case */
807 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
808 } else if (compute_ov) {
809 /* Start with XER OV disabled, the most likely case */
810 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
811 }
812
813 tcg_gen_add_tl(t0, arg1, arg2);
814
815 if (compute_ca) {
816 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
817 }
818 if (add_ca) {
819 tcg_gen_add_tl(t0, t0, t1);
820 gen_op_arith_compute_ca(ctx, t0, t1, 0);
821 tcg_temp_free(t1);
822 }
823 if (compute_ov) {
824 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
825 }
826
827 if (unlikely(Rc(ctx->opcode) != 0))
828 gen_set_Rc0(ctx, t0);
829
830 if (!TCGV_EQUAL(t0, ret)) {
831 tcg_gen_mov_tl(ret, t0);
832 tcg_temp_free(t0);
833 }
834 }
835 /* Add functions with two operands */
836 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
837 static void glue(gen_, name)(DisasContext *ctx) \
838 { \
839 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
840 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
841 add_ca, compute_ca, compute_ov); \
842 }
843 /* Add functions with one operand and one immediate */
844 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
845 add_ca, compute_ca, compute_ov) \
846 static void glue(gen_, name)(DisasContext *ctx) \
847 { \
848 TCGv t0 = tcg_const_local_tl(const_val); \
849 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
850 cpu_gpr[rA(ctx->opcode)], t0, \
851 add_ca, compute_ca, compute_ov); \
852 tcg_temp_free(t0); \
853 }
854
855 /* add add. addo addo. */
856 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
857 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
858 /* addc addc. addco addco. */
859 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
860 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
861 /* adde adde. addeo addeo. */
862 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
863 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
864 /* addme addme. addmeo addmeo. */
865 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
866 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
867 /* addze addze. addzeo addzeo.*/
868 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
869 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
870 /* addi */
871 static void gen_addi(DisasContext *ctx)
872 {
873 target_long simm = SIMM(ctx->opcode);
874
875 if (rA(ctx->opcode) == 0) {
876 /* li case */
877 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
878 } else {
879 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
880 }
881 }
882 /* addic addic.*/
883 static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
884 int compute_Rc0)
885 {
886 target_long simm = SIMM(ctx->opcode);
887
888 /* Start with XER CA and OV disabled, the most likely case */
889 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
890
891 if (likely(simm != 0)) {
892 TCGv t0 = tcg_temp_local_new();
893 tcg_gen_addi_tl(t0, arg1, simm);
894 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
895 tcg_gen_mov_tl(ret, t0);
896 tcg_temp_free(t0);
897 } else {
898 tcg_gen_mov_tl(ret, arg1);
899 }
900 if (compute_Rc0) {
901 gen_set_Rc0(ctx, ret);
902 }
903 }
904
905 static void gen_addic(DisasContext *ctx)
906 {
907 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
908 }
909
910 static void gen_addic_(DisasContext *ctx)
911 {
912 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
913 }
914
915 /* addis */
916 static void gen_addis(DisasContext *ctx)
917 {
918 target_long simm = SIMM(ctx->opcode);
919
920 if (rA(ctx->opcode) == 0) {
921 /* lis case */
922 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
923 } else {
924 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
925 }
926 }
927
928 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
929 TCGv arg2, int sign, int compute_ov)
930 {
931 int l1 = gen_new_label();
932 int l2 = gen_new_label();
933 TCGv_i32 t0 = tcg_temp_local_new_i32();
934 TCGv_i32 t1 = tcg_temp_local_new_i32();
935
936 tcg_gen_trunc_tl_i32(t0, arg1);
937 tcg_gen_trunc_tl_i32(t1, arg2);
938 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
939 if (sign) {
940 int l3 = gen_new_label();
941 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
942 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
943 gen_set_label(l3);
944 tcg_gen_div_i32(t0, t0, t1);
945 } else {
946 tcg_gen_divu_i32(t0, t0, t1);
947 }
948 if (compute_ov) {
949 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
950 }
951 tcg_gen_br(l2);
952 gen_set_label(l1);
953 if (sign) {
954 tcg_gen_sari_i32(t0, t0, 31);
955 } else {
956 tcg_gen_movi_i32(t0, 0);
957 }
958 if (compute_ov) {
959 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
960 }
961 gen_set_label(l2);
962 tcg_gen_extu_i32_tl(ret, t0);
963 tcg_temp_free_i32(t0);
964 tcg_temp_free_i32(t1);
965 if (unlikely(Rc(ctx->opcode) != 0))
966 gen_set_Rc0(ctx, ret);
967 }
968 /* Div functions */
969 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
970 static void glue(gen_, name)(DisasContext *ctx) \
971 { \
972 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
973 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
974 sign, compute_ov); \
975 }
976 /* divwu divwu. divwuo divwuo. */
977 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
978 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
979 /* divw divw. divwo divwo. */
980 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
981 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
982 #if defined(TARGET_PPC64)
983 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
984 TCGv arg2, int sign, int compute_ov)
985 {
986 int l1 = gen_new_label();
987 int l2 = gen_new_label();
988
989 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
990 if (sign) {
991 int l3 = gen_new_label();
992 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
993 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
994 gen_set_label(l3);
995 tcg_gen_div_i64(ret, arg1, arg2);
996 } else {
997 tcg_gen_divu_i64(ret, arg1, arg2);
998 }
999 if (compute_ov) {
1000 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1001 }
1002 tcg_gen_br(l2);
1003 gen_set_label(l1);
1004 if (sign) {
1005 tcg_gen_sari_i64(ret, arg1, 63);
1006 } else {
1007 tcg_gen_movi_i64(ret, 0);
1008 }
1009 if (compute_ov) {
1010 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1011 }
1012 gen_set_label(l2);
1013 if (unlikely(Rc(ctx->opcode) != 0))
1014 gen_set_Rc0(ctx, ret);
1015 }
1016 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1017 static void glue(gen_, name)(DisasContext *ctx) \
1018 { \
1019 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1020 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1021 sign, compute_ov); \
1022 }
1023 /* divwu divwu. divwuo divwuo. */
1024 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1025 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1026 /* divw divw. divwo divwo. */
1027 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1028 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1029 #endif
1030
1031 /* mulhw mulhw. */
1032 static void gen_mulhw(DisasContext *ctx)
1033 {
1034 TCGv_i64 t0, t1;
1035
1036 t0 = tcg_temp_new_i64();
1037 t1 = tcg_temp_new_i64();
1038 #if defined(TARGET_PPC64)
1039 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1040 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1041 tcg_gen_mul_i64(t0, t0, t1);
1042 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1043 #else
1044 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1045 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1046 tcg_gen_mul_i64(t0, t0, t1);
1047 tcg_gen_shri_i64(t0, t0, 32);
1048 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1049 #endif
1050 tcg_temp_free_i64(t0);
1051 tcg_temp_free_i64(t1);
1052 if (unlikely(Rc(ctx->opcode) != 0))
1053 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1054 }
1055
1056 /* mulhwu mulhwu. */
1057 static void gen_mulhwu(DisasContext *ctx)
1058 {
1059 TCGv_i64 t0, t1;
1060
1061 t0 = tcg_temp_new_i64();
1062 t1 = tcg_temp_new_i64();
1063 #if defined(TARGET_PPC64)
1064 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1065 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1066 tcg_gen_mul_i64(t0, t0, t1);
1067 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1068 #else
1069 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1070 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1071 tcg_gen_mul_i64(t0, t0, t1);
1072 tcg_gen_shri_i64(t0, t0, 32);
1073 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1074 #endif
1075 tcg_temp_free_i64(t0);
1076 tcg_temp_free_i64(t1);
1077 if (unlikely(Rc(ctx->opcode) != 0))
1078 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1079 }
1080
1081 /* mullw mullw. */
1082 static void gen_mullw(DisasContext *ctx)
1083 {
1084 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1085 cpu_gpr[rB(ctx->opcode)]);
1086 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1087 if (unlikely(Rc(ctx->opcode) != 0))
1088 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1089 }
1090
1091 /* mullwo mullwo. */
1092 static void gen_mullwo(DisasContext *ctx)
1093 {
1094 int l1;
1095 TCGv_i64 t0, t1;
1096
1097 t0 = tcg_temp_new_i64();
1098 t1 = tcg_temp_new_i64();
1099 l1 = gen_new_label();
1100 /* Start with XER OV disabled, the most likely case */
1101 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1102 #if defined(TARGET_PPC64)
1103 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1104 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1105 #else
1106 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1107 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1108 #endif
1109 tcg_gen_mul_i64(t0, t0, t1);
1110 #if defined(TARGET_PPC64)
1111 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1112 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1113 #else
1114 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1115 tcg_gen_ext32s_i64(t1, t0);
1116 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1117 #endif
1118 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1119 gen_set_label(l1);
1120 tcg_temp_free_i64(t0);
1121 tcg_temp_free_i64(t1);
1122 if (unlikely(Rc(ctx->opcode) != 0))
1123 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1124 }
1125
1126 /* mulli */
1127 static void gen_mulli(DisasContext *ctx)
1128 {
1129 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1130 SIMM(ctx->opcode));
1131 }
1132 #if defined(TARGET_PPC64)
1133 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1134 static void glue(gen_, name)(DisasContext *ctx) \
1135 { \
1136 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1137 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1138 if (unlikely(Rc(ctx->opcode) != 0)) \
1139 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1140 }
1141 /* mulhd mulhd. */
1142 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1143 /* mulhdu mulhdu. */
1144 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1145
1146 /* mulld mulld. */
1147 static void gen_mulld(DisasContext *ctx)
1148 {
1149 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1150 cpu_gpr[rB(ctx->opcode)]);
1151 if (unlikely(Rc(ctx->opcode) != 0))
1152 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1153 }
1154 /* mulldo mulldo. */
1155 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1156 #endif
1157
1158 /* neg neg. nego nego. */
1159 static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1160 int ov_check)
1161 {
1162 int l1 = gen_new_label();
1163 int l2 = gen_new_label();
1164 TCGv t0 = tcg_temp_local_new();
1165 #if defined(TARGET_PPC64)
1166 if (ctx->sf_mode) {
1167 tcg_gen_mov_tl(t0, arg1);
1168 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1169 } else
1170 #endif
1171 {
1172 tcg_gen_ext32s_tl(t0, arg1);
1173 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1174 }
1175 tcg_gen_neg_tl(ret, arg1);
1176 if (ov_check) {
1177 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1178 }
1179 tcg_gen_br(l2);
1180 gen_set_label(l1);
1181 tcg_gen_mov_tl(ret, t0);
1182 if (ov_check) {
1183 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1184 }
1185 gen_set_label(l2);
1186 tcg_temp_free(t0);
1187 if (unlikely(Rc(ctx->opcode) != 0))
1188 gen_set_Rc0(ctx, ret);
1189 }
1190
1191 static void gen_neg(DisasContext *ctx)
1192 {
1193 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1194 }
1195
1196 static void gen_nego(DisasContext *ctx)
1197 {
1198 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1199 }
1200
1201 /* Common subf function */
1202 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1203 TCGv arg2, int add_ca, int compute_ca,
1204 int compute_ov)
1205 {
1206 TCGv t0, t1;
1207
1208 if ((!compute_ca && !compute_ov) ||
1209 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1210 t0 = ret;
1211 } else {
1212 t0 = tcg_temp_local_new();
1213 }
1214
1215 if (add_ca) {
1216 t1 = tcg_temp_local_new();
1217 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1218 tcg_gen_shri_tl(t1, t1, XER_CA);
1219 } else {
1220 TCGV_UNUSED(t1);
1221 }
1222
1223 if (compute_ca && compute_ov) {
1224 /* Start with XER CA and OV disabled, the most likely case */
1225 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1226 } else if (compute_ca) {
1227 /* Start with XER CA disabled, the most likely case */
1228 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1229 } else if (compute_ov) {
1230 /* Start with XER OV disabled, the most likely case */
1231 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1232 }
1233
1234 if (add_ca) {
1235 tcg_gen_not_tl(t0, arg1);
1236 tcg_gen_add_tl(t0, t0, arg2);
1237 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1238 tcg_gen_add_tl(t0, t0, t1);
1239 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1240 tcg_temp_free(t1);
1241 } else {
1242 tcg_gen_sub_tl(t0, arg2, arg1);
1243 if (compute_ca) {
1244 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1245 }
1246 }
1247 if (compute_ov) {
1248 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1249 }
1250
1251 if (unlikely(Rc(ctx->opcode) != 0))
1252 gen_set_Rc0(ctx, t0);
1253
1254 if (!TCGV_EQUAL(t0, ret)) {
1255 tcg_gen_mov_tl(ret, t0);
1256 tcg_temp_free(t0);
1257 }
1258 }
1259 /* Sub functions with Two operands functions */
1260 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1261 static void glue(gen_, name)(DisasContext *ctx) \
1262 { \
1263 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1264 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1265 add_ca, compute_ca, compute_ov); \
1266 }
1267 /* Sub functions with one operand and one immediate */
1268 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1269 add_ca, compute_ca, compute_ov) \
1270 static void glue(gen_, name)(DisasContext *ctx) \
1271 { \
1272 TCGv t0 = tcg_const_local_tl(const_val); \
1273 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1274 cpu_gpr[rA(ctx->opcode)], t0, \
1275 add_ca, compute_ca, compute_ov); \
1276 tcg_temp_free(t0); \
1277 }
1278 /* subf subf. subfo subfo. */
1279 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1280 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1281 /* subfc subfc. subfco subfco. */
1282 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1283 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1284 /* subfe subfe. subfeo subfo. */
1285 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1286 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1287 /* subfme subfme. subfmeo subfmeo. */
1288 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1289 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1290 /* subfze subfze. subfzeo subfzeo.*/
1291 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1292 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1293
1294 /* subfic */
1295 static void gen_subfic(DisasContext *ctx)
1296 {
1297 /* Start with XER CA and OV disabled, the most likely case */
1298 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1299 TCGv t0 = tcg_temp_local_new();
1300 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1301 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1302 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1303 tcg_temp_free(t1);
1304 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1305 tcg_temp_free(t0);
1306 }
1307
1308 /*** Integer logical ***/
1309 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1310 static void glue(gen_, name)(DisasContext *ctx) \
1311 { \
1312 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1313 cpu_gpr[rB(ctx->opcode)]); \
1314 if (unlikely(Rc(ctx->opcode) != 0)) \
1315 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1316 }
1317
1318 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1319 static void glue(gen_, name)(DisasContext *ctx) \
1320 { \
1321 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1322 if (unlikely(Rc(ctx->opcode) != 0)) \
1323 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1324 }
1325
1326 /* and & and. */
1327 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1328 /* andc & andc. */
1329 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1330
1331 /* andi. */
1332 static void gen_andi_(DisasContext *ctx)
1333 {
1334 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1335 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1336 }
1337
1338 /* andis. */
1339 static void gen_andis_(DisasContext *ctx)
1340 {
1341 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1342 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1343 }
1344
1345 /* cntlzw */
1346 static void gen_cntlzw(DisasContext *ctx)
1347 {
1348 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1349 if (unlikely(Rc(ctx->opcode) != 0))
1350 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1351 }
1352 /* eqv & eqv. */
1353 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1354 /* extsb & extsb. */
1355 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1356 /* extsh & extsh. */
1357 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1358 /* nand & nand. */
1359 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1360 /* nor & nor. */
1361 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1362
1363 /* or & or. */
1364 static void gen_or(DisasContext *ctx)
1365 {
1366 int rs, ra, rb;
1367
1368 rs = rS(ctx->opcode);
1369 ra = rA(ctx->opcode);
1370 rb = rB(ctx->opcode);
1371 /* Optimisation for mr. ri case */
1372 if (rs != ra || rs != rb) {
1373 if (rs != rb)
1374 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1375 else
1376 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1377 if (unlikely(Rc(ctx->opcode) != 0))
1378 gen_set_Rc0(ctx, cpu_gpr[ra]);
1379 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1380 gen_set_Rc0(ctx, cpu_gpr[rs]);
1381 #if defined(TARGET_PPC64)
1382 } else {
1383 int prio = 0;
1384
1385 switch (rs) {
1386 case 1:
1387 /* Set process priority to low */
1388 prio = 2;
1389 break;
1390 case 6:
1391 /* Set process priority to medium-low */
1392 prio = 3;
1393 break;
1394 case 2:
1395 /* Set process priority to normal */
1396 prio = 4;
1397 break;
1398 #if !defined(CONFIG_USER_ONLY)
1399 case 31:
1400 if (ctx->mem_idx > 0) {
1401 /* Set process priority to very low */
1402 prio = 1;
1403 }
1404 break;
1405 case 5:
1406 if (ctx->mem_idx > 0) {
1407 /* Set process priority to medium-hight */
1408 prio = 5;
1409 }
1410 break;
1411 case 3:
1412 if (ctx->mem_idx > 0) {
1413 /* Set process priority to high */
1414 prio = 6;
1415 }
1416 break;
1417 case 7:
1418 if (ctx->mem_idx > 1) {
1419 /* Set process priority to very high */
1420 prio = 7;
1421 }
1422 break;
1423 #endif
1424 default:
1425 /* nop */
1426 break;
1427 }
1428 if (prio) {
1429 TCGv t0 = tcg_temp_new();
1430 gen_load_spr(t0, SPR_PPR);
1431 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1432 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1433 gen_store_spr(SPR_PPR, t0);
1434 tcg_temp_free(t0);
1435 }
1436 #endif
1437 }
1438 }
1439 /* orc & orc. */
1440 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1441
1442 /* xor & xor. */
1443 static void gen_xor(DisasContext *ctx)
1444 {
1445 /* Optimisation for "set to zero" case */
1446 if (rS(ctx->opcode) != rB(ctx->opcode))
1447 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1448 else
1449 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1450 if (unlikely(Rc(ctx->opcode) != 0))
1451 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1452 }
1453
1454 /* ori */
1455 static void gen_ori(DisasContext *ctx)
1456 {
1457 target_ulong uimm = UIMM(ctx->opcode);
1458
1459 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1460 /* NOP */
1461 /* XXX: should handle special NOPs for POWER series */
1462 return;
1463 }
1464 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1465 }
1466
1467 /* oris */
1468 static void gen_oris(DisasContext *ctx)
1469 {
1470 target_ulong uimm = UIMM(ctx->opcode);
1471
1472 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1473 /* NOP */
1474 return;
1475 }
1476 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1477 }
1478
1479 /* xori */
1480 static void gen_xori(DisasContext *ctx)
1481 {
1482 target_ulong uimm = UIMM(ctx->opcode);
1483
1484 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1485 /* NOP */
1486 return;
1487 }
1488 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1489 }
1490
1491 /* xoris */
1492 static void gen_xoris(DisasContext *ctx)
1493 {
1494 target_ulong uimm = UIMM(ctx->opcode);
1495
1496 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1497 /* NOP */
1498 return;
1499 }
1500 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1501 }
1502
1503 /* popcntb : PowerPC 2.03 specification */
1504 static void gen_popcntb(DisasContext *ctx)
1505 {
1506 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1507 }
1508
1509 static void gen_popcntw(DisasContext *ctx)
1510 {
1511 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1512 }
1513
1514 #if defined(TARGET_PPC64)
1515 /* popcntd: PowerPC 2.06 specification */
1516 static void gen_popcntd(DisasContext *ctx)
1517 {
1518 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1519 }
1520 #endif
1521
1522 #if defined(TARGET_PPC64)
1523 /* extsw & extsw. */
1524 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1525
1526 /* cntlzd */
1527 static void gen_cntlzd(DisasContext *ctx)
1528 {
1529 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1530 if (unlikely(Rc(ctx->opcode) != 0))
1531 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1532 }
1533 #endif
1534
1535 /*** Integer rotate ***/
1536
1537 /* rlwimi & rlwimi. */
1538 static void gen_rlwimi(DisasContext *ctx)
1539 {
1540 uint32_t mb, me, sh;
1541
1542 mb = MB(ctx->opcode);
1543 me = ME(ctx->opcode);
1544 sh = SH(ctx->opcode);
1545 if (likely(sh == 0 && mb == 0 && me == 31)) {
1546 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1547 } else {
1548 target_ulong mask;
1549 TCGv t1;
1550 TCGv t0 = tcg_temp_new();
1551 #if defined(TARGET_PPC64)
1552 TCGv_i32 t2 = tcg_temp_new_i32();
1553 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1554 tcg_gen_rotli_i32(t2, t2, sh);
1555 tcg_gen_extu_i32_i64(t0, t2);
1556 tcg_temp_free_i32(t2);
1557 #else
1558 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1559 #endif
1560 #if defined(TARGET_PPC64)
1561 mb += 32;
1562 me += 32;
1563 #endif
1564 mask = MASK(mb, me);
1565 t1 = tcg_temp_new();
1566 tcg_gen_andi_tl(t0, t0, mask);
1567 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1568 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1569 tcg_temp_free(t0);
1570 tcg_temp_free(t1);
1571 }
1572 if (unlikely(Rc(ctx->opcode) != 0))
1573 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1574 }
1575
1576 /* rlwinm & rlwinm. */
1577 static void gen_rlwinm(DisasContext *ctx)
1578 {
1579 uint32_t mb, me, sh;
1580
1581 sh = SH(ctx->opcode);
1582 mb = MB(ctx->opcode);
1583 me = ME(ctx->opcode);
1584
1585 if (likely(mb == 0 && me == (31 - sh))) {
1586 if (likely(sh == 0)) {
1587 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1588 } else {
1589 TCGv t0 = tcg_temp_new();
1590 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1591 tcg_gen_shli_tl(t0, t0, sh);
1592 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1593 tcg_temp_free(t0);
1594 }
1595 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1596 TCGv t0 = tcg_temp_new();
1597 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1598 tcg_gen_shri_tl(t0, t0, mb);
1599 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1600 tcg_temp_free(t0);
1601 } else {
1602 TCGv t0 = tcg_temp_new();
1603 #if defined(TARGET_PPC64)
1604 TCGv_i32 t1 = tcg_temp_new_i32();
1605 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1606 tcg_gen_rotli_i32(t1, t1, sh);
1607 tcg_gen_extu_i32_i64(t0, t1);
1608 tcg_temp_free_i32(t1);
1609 #else
1610 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1611 #endif
1612 #if defined(TARGET_PPC64)
1613 mb += 32;
1614 me += 32;
1615 #endif
1616 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1617 tcg_temp_free(t0);
1618 }
1619 if (unlikely(Rc(ctx->opcode) != 0))
1620 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1621 }
1622
1623 /* rlwnm & rlwnm. */
1624 static void gen_rlwnm(DisasContext *ctx)
1625 {
1626 uint32_t mb, me;
1627 TCGv t0;
1628 #if defined(TARGET_PPC64)
1629 TCGv_i32 t1, t2;
1630 #endif
1631
1632 mb = MB(ctx->opcode);
1633 me = ME(ctx->opcode);
1634 t0 = tcg_temp_new();
1635 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1636 #if defined(TARGET_PPC64)
1637 t1 = tcg_temp_new_i32();
1638 t2 = tcg_temp_new_i32();
1639 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1640 tcg_gen_trunc_i64_i32(t2, t0);
1641 tcg_gen_rotl_i32(t1, t1, t2);
1642 tcg_gen_extu_i32_i64(t0, t1);
1643 tcg_temp_free_i32(t1);
1644 tcg_temp_free_i32(t2);
1645 #else
1646 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1647 #endif
1648 if (unlikely(mb != 0 || me != 31)) {
1649 #if defined(TARGET_PPC64)
1650 mb += 32;
1651 me += 32;
1652 #endif
1653 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1654 } else {
1655 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1656 }
1657 tcg_temp_free(t0);
1658 if (unlikely(Rc(ctx->opcode) != 0))
1659 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1660 }
1661
1662 #if defined(TARGET_PPC64)
1663 #define GEN_PPC64_R2(name, opc1, opc2) \
1664 static void glue(gen_, name##0)(DisasContext *ctx) \
1665 { \
1666 gen_##name(ctx, 0); \
1667 } \
1668 \
1669 static void glue(gen_, name##1)(DisasContext *ctx) \
1670 { \
1671 gen_##name(ctx, 1); \
1672 }
1673 #define GEN_PPC64_R4(name, opc1, opc2) \
1674 static void glue(gen_, name##0)(DisasContext *ctx) \
1675 { \
1676 gen_##name(ctx, 0, 0); \
1677 } \
1678 \
1679 static void glue(gen_, name##1)(DisasContext *ctx) \
1680 { \
1681 gen_##name(ctx, 0, 1); \
1682 } \
1683 \
1684 static void glue(gen_, name##2)(DisasContext *ctx) \
1685 { \
1686 gen_##name(ctx, 1, 0); \
1687 } \
1688 \
1689 static void glue(gen_, name##3)(DisasContext *ctx) \
1690 { \
1691 gen_##name(ctx, 1, 1); \
1692 }
1693
1694 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1695 uint32_t sh)
1696 {
1697 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1698 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1699 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1700 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1701 } else {
1702 TCGv t0 = tcg_temp_new();
1703 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1704 if (likely(mb == 0 && me == 63)) {
1705 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1706 } else {
1707 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1708 }
1709 tcg_temp_free(t0);
1710 }
1711 if (unlikely(Rc(ctx->opcode) != 0))
1712 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1713 }
1714 /* rldicl - rldicl. */
1715 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1716 {
1717 uint32_t sh, mb;
1718
1719 sh = SH(ctx->opcode) | (shn << 5);
1720 mb = MB(ctx->opcode) | (mbn << 5);
1721 gen_rldinm(ctx, mb, 63, sh);
1722 }
1723 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1724 /* rldicr - rldicr. */
1725 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1726 {
1727 uint32_t sh, me;
1728
1729 sh = SH(ctx->opcode) | (shn << 5);
1730 me = MB(ctx->opcode) | (men << 5);
1731 gen_rldinm(ctx, 0, me, sh);
1732 }
1733 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1734 /* rldic - rldic. */
1735 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1736 {
1737 uint32_t sh, mb;
1738
1739 sh = SH(ctx->opcode) | (shn << 5);
1740 mb = MB(ctx->opcode) | (mbn << 5);
1741 gen_rldinm(ctx, mb, 63 - sh, sh);
1742 }
1743 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1744
1745 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1746 {
1747 TCGv t0;
1748
1749 mb = MB(ctx->opcode);
1750 me = ME(ctx->opcode);
1751 t0 = tcg_temp_new();
1752 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1753 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1754 if (unlikely(mb != 0 || me != 63)) {
1755 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1756 } else {
1757 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1758 }
1759 tcg_temp_free(t0);
1760 if (unlikely(Rc(ctx->opcode) != 0))
1761 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1762 }
1763
1764 /* rldcl - rldcl. */
1765 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1766 {
1767 uint32_t mb;
1768
1769 mb = MB(ctx->opcode) | (mbn << 5);
1770 gen_rldnm(ctx, mb, 63);
1771 }
1772 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1773 /* rldcr - rldcr. */
1774 static inline void gen_rldcr(DisasContext *ctx, int men)
1775 {
1776 uint32_t me;
1777
1778 me = MB(ctx->opcode) | (men << 5);
1779 gen_rldnm(ctx, 0, me);
1780 }
1781 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1782 /* rldimi - rldimi. */
1783 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1784 {
1785 uint32_t sh, mb, me;
1786
1787 sh = SH(ctx->opcode) | (shn << 5);
1788 mb = MB(ctx->opcode) | (mbn << 5);
1789 me = 63 - sh;
1790 if (unlikely(sh == 0 && mb == 0)) {
1791 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1792 } else {
1793 TCGv t0, t1;
1794 target_ulong mask;
1795
1796 t0 = tcg_temp_new();
1797 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1798 t1 = tcg_temp_new();
1799 mask = MASK(mb, me);
1800 tcg_gen_andi_tl(t0, t0, mask);
1801 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1802 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1803 tcg_temp_free(t0);
1804 tcg_temp_free(t1);
1805 }
1806 if (unlikely(Rc(ctx->opcode) != 0))
1807 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1808 }
1809 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1810 #endif
1811
1812 /*** Integer shift ***/
1813
1814 /* slw & slw. */
1815 static void gen_slw(DisasContext *ctx)
1816 {
1817 TCGv t0, t1;
1818
1819 t0 = tcg_temp_new();
1820 /* AND rS with a mask that is 0 when rB >= 0x20 */
1821 #if defined(TARGET_PPC64)
1822 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1823 tcg_gen_sari_tl(t0, t0, 0x3f);
1824 #else
1825 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1826 tcg_gen_sari_tl(t0, t0, 0x1f);
1827 #endif
1828 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1829 t1 = tcg_temp_new();
1830 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1831 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1832 tcg_temp_free(t1);
1833 tcg_temp_free(t0);
1834 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1835 if (unlikely(Rc(ctx->opcode) != 0))
1836 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1837 }
1838
1839 /* sraw & sraw. */
1840 static void gen_sraw(DisasContext *ctx)
1841 {
1842 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1843 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1844 if (unlikely(Rc(ctx->opcode) != 0))
1845 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1846 }
1847
1848 /* srawi & srawi. */
1849 static void gen_srawi(DisasContext *ctx)
1850 {
1851 int sh = SH(ctx->opcode);
1852 if (sh != 0) {
1853 int l1, l2;
1854 TCGv t0;
1855 l1 = gen_new_label();
1856 l2 = gen_new_label();
1857 t0 = tcg_temp_local_new();
1858 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1859 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1860 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1861 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1862 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1863 tcg_gen_br(l2);
1864 gen_set_label(l1);
1865 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1866 gen_set_label(l2);
1867 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1868 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1869 tcg_temp_free(t0);
1870 } else {
1871 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1872 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1873 }
1874 if (unlikely(Rc(ctx->opcode) != 0))
1875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1876 }
1877
1878 /* srw & srw. */
1879 static void gen_srw(DisasContext *ctx)
1880 {
1881 TCGv t0, t1;
1882
1883 t0 = tcg_temp_new();
1884 /* AND rS with a mask that is 0 when rB >= 0x20 */
1885 #if defined(TARGET_PPC64)
1886 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1887 tcg_gen_sari_tl(t0, t0, 0x3f);
1888 #else
1889 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1890 tcg_gen_sari_tl(t0, t0, 0x1f);
1891 #endif
1892 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1893 tcg_gen_ext32u_tl(t0, t0);
1894 t1 = tcg_temp_new();
1895 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1896 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1897 tcg_temp_free(t1);
1898 tcg_temp_free(t0);
1899 if (unlikely(Rc(ctx->opcode) != 0))
1900 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1901 }
1902
1903 #if defined(TARGET_PPC64)
1904 /* sld & sld. */
1905 static void gen_sld(DisasContext *ctx)
1906 {
1907 TCGv t0, t1;
1908
1909 t0 = tcg_temp_new();
1910 /* AND rS with a mask that is 0 when rB >= 0x40 */
1911 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1912 tcg_gen_sari_tl(t0, t0, 0x3f);
1913 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1914 t1 = tcg_temp_new();
1915 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1916 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1917 tcg_temp_free(t1);
1918 tcg_temp_free(t0);
1919 if (unlikely(Rc(ctx->opcode) != 0))
1920 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1921 }
1922
1923 /* srad & srad. */
1924 static void gen_srad(DisasContext *ctx)
1925 {
1926 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
1927 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1928 if (unlikely(Rc(ctx->opcode) != 0))
1929 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1930 }
1931 /* sradi & sradi. */
1932 static inline void gen_sradi(DisasContext *ctx, int n)
1933 {
1934 int sh = SH(ctx->opcode) + (n << 5);
1935 if (sh != 0) {
1936 int l1, l2;
1937 TCGv t0;
1938 l1 = gen_new_label();
1939 l2 = gen_new_label();
1940 t0 = tcg_temp_local_new();
1941 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1942 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1943 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1944 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1945 tcg_gen_br(l2);
1946 gen_set_label(l1);
1947 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1948 gen_set_label(l2);
1949 tcg_temp_free(t0);
1950 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1951 } else {
1952 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1953 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1954 }
1955 if (unlikely(Rc(ctx->opcode) != 0))
1956 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1957 }
1958
1959 static void gen_sradi0(DisasContext *ctx)
1960 {
1961 gen_sradi(ctx, 0);
1962 }
1963
1964 static void gen_sradi1(DisasContext *ctx)
1965 {
1966 gen_sradi(ctx, 1);
1967 }
1968
1969 /* srd & srd. */
1970 static void gen_srd(DisasContext *ctx)
1971 {
1972 TCGv t0, t1;
1973
1974 t0 = tcg_temp_new();
1975 /* AND rS with a mask that is 0 when rB >= 0x40 */
1976 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1977 tcg_gen_sari_tl(t0, t0, 0x3f);
1978 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1979 t1 = tcg_temp_new();
1980 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1981 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1982 tcg_temp_free(t1);
1983 tcg_temp_free(t0);
1984 if (unlikely(Rc(ctx->opcode) != 0))
1985 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1986 }
1987 #endif
1988
1989 /*** Floating-Point arithmetic ***/
1990 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1991 static void gen_f##name(DisasContext *ctx) \
1992 { \
1993 if (unlikely(!ctx->fpu_enabled)) { \
1994 gen_exception(ctx, POWERPC_EXCP_FPU); \
1995 return; \
1996 } \
1997 /* NIP cannot be restored if the memory exception comes from an helper */ \
1998 gen_update_nip(ctx, ctx->nip - 4); \
1999 gen_reset_fpstatus(); \
2000 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2001 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2002 if (isfloat) { \
2003 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2004 } \
2005 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2006 Rc(ctx->opcode) != 0); \
2007 }
2008
2009 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2010 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2011 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2012
2013 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2014 static void gen_f##name(DisasContext *ctx) \
2015 { \
2016 if (unlikely(!ctx->fpu_enabled)) { \
2017 gen_exception(ctx, POWERPC_EXCP_FPU); \
2018 return; \
2019 } \
2020 /* NIP cannot be restored if the memory exception comes from an helper */ \
2021 gen_update_nip(ctx, ctx->nip - 4); \
2022 gen_reset_fpstatus(); \
2023 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2024 cpu_fpr[rB(ctx->opcode)]); \
2025 if (isfloat) { \
2026 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2027 } \
2028 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2029 set_fprf, Rc(ctx->opcode) != 0); \
2030 }
2031 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2032 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2033 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2034
2035 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2036 static void gen_f##name(DisasContext *ctx) \
2037 { \
2038 if (unlikely(!ctx->fpu_enabled)) { \
2039 gen_exception(ctx, POWERPC_EXCP_FPU); \
2040 return; \
2041 } \
2042 /* NIP cannot be restored if the memory exception comes from an helper */ \
2043 gen_update_nip(ctx, ctx->nip - 4); \
2044 gen_reset_fpstatus(); \
2045 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2046 cpu_fpr[rC(ctx->opcode)]); \
2047 if (isfloat) { \
2048 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2049 } \
2050 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2051 set_fprf, Rc(ctx->opcode) != 0); \
2052 }
2053 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2054 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2055 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2056
2057 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2058 static void gen_f##name(DisasContext *ctx) \
2059 { \
2060 if (unlikely(!ctx->fpu_enabled)) { \
2061 gen_exception(ctx, POWERPC_EXCP_FPU); \
2062 return; \
2063 } \
2064 /* NIP cannot be restored if the memory exception comes from an helper */ \
2065 gen_update_nip(ctx, ctx->nip - 4); \
2066 gen_reset_fpstatus(); \
2067 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2068 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2069 set_fprf, Rc(ctx->opcode) != 0); \
2070 }
2071
2072 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2073 static void gen_f##name(DisasContext *ctx) \
2074 { \
2075 if (unlikely(!ctx->fpu_enabled)) { \
2076 gen_exception(ctx, POWERPC_EXCP_FPU); \
2077 return; \
2078 } \
2079 /* NIP cannot be restored if the memory exception comes from an helper */ \
2080 gen_update_nip(ctx, ctx->nip - 4); \
2081 gen_reset_fpstatus(); \
2082 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2083 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2084 set_fprf, Rc(ctx->opcode) != 0); \
2085 }
2086
2087 /* fadd - fadds */
2088 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2089 /* fdiv - fdivs */
2090 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2091 /* fmul - fmuls */
2092 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2093
2094 /* fre */
2095 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2096
2097 /* fres */
2098 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2099
2100 /* frsqrte */
2101 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2102
2103 /* frsqrtes */
2104 static void gen_frsqrtes(DisasContext *ctx)
2105 {
2106 if (unlikely(!ctx->fpu_enabled)) {
2107 gen_exception(ctx, POWERPC_EXCP_FPU);
2108 return;
2109 }
2110 /* NIP cannot be restored if the memory exception comes from an helper */
2111 gen_update_nip(ctx, ctx->nip - 4);
2112 gen_reset_fpstatus();
2113 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2114 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2115 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2116 }
2117
2118 /* fsel */
2119 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2120 /* fsub - fsubs */
2121 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2122 /* Optional: */
2123
2124 /* fsqrt */
2125 static void gen_fsqrt(DisasContext *ctx)
2126 {
2127 if (unlikely(!ctx->fpu_enabled)) {
2128 gen_exception(ctx, POWERPC_EXCP_FPU);
2129 return;
2130 }
2131 /* NIP cannot be restored if the memory exception comes from an helper */
2132 gen_update_nip(ctx, ctx->nip - 4);
2133 gen_reset_fpstatus();
2134 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2135 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2136 }
2137
2138 static void gen_fsqrts(DisasContext *ctx)
2139 {
2140 if (unlikely(!ctx->fpu_enabled)) {
2141 gen_exception(ctx, POWERPC_EXCP_FPU);
2142 return;
2143 }
2144 /* NIP cannot be restored if the memory exception comes from an helper */
2145 gen_update_nip(ctx, ctx->nip - 4);
2146 gen_reset_fpstatus();
2147 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2148 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2149 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2150 }
2151
2152 /*** Floating-Point multiply-and-add ***/
2153 /* fmadd - fmadds */
2154 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2155 /* fmsub - fmsubs */
2156 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2157 /* fnmadd - fnmadds */
2158 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2159 /* fnmsub - fnmsubs */
2160 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2161
2162 /*** Floating-Point round & convert ***/
2163 /* fctiw */
2164 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2165 /* fctiwz */
2166 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2167 /* frsp */
2168 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2169 #if defined(TARGET_PPC64)
2170 /* fcfid */
2171 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2172 /* fctid */
2173 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2174 /* fctidz */
2175 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2176 #endif
2177
2178 /* frin */
2179 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2180 /* friz */
2181 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2182 /* frip */
2183 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2184 /* frim */
2185 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2186
2187 /*** Floating-Point compare ***/
2188
2189 /* fcmpo */
2190 static void gen_fcmpo(DisasContext *ctx)
2191 {
2192 TCGv_i32 crf;
2193 if (unlikely(!ctx->fpu_enabled)) {
2194 gen_exception(ctx, POWERPC_EXCP_FPU);
2195 return;
2196 }
2197 /* NIP cannot be restored if the memory exception comes from an helper */
2198 gen_update_nip(ctx, ctx->nip - 4);
2199 gen_reset_fpstatus();
2200 crf = tcg_const_i32(crfD(ctx->opcode));
2201 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2202 tcg_temp_free_i32(crf);
2203 gen_helper_float_check_status();
2204 }
2205
2206 /* fcmpu */
2207 static void gen_fcmpu(DisasContext *ctx)
2208 {
2209 TCGv_i32 crf;
2210 if (unlikely(!ctx->fpu_enabled)) {
2211 gen_exception(ctx, POWERPC_EXCP_FPU);
2212 return;
2213 }
2214 /* NIP cannot be restored if the memory exception comes from an helper */
2215 gen_update_nip(ctx, ctx->nip - 4);
2216 gen_reset_fpstatus();
2217 crf = tcg_const_i32(crfD(ctx->opcode));
2218 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2219 tcg_temp_free_i32(crf);
2220 gen_helper_float_check_status();
2221 }
2222
2223 /*** Floating-point move ***/
2224 /* fabs */
2225 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2226 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2227
2228 /* fmr - fmr. */
2229 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2230 static void gen_fmr(DisasContext *ctx)
2231 {
2232 if (unlikely(!ctx->fpu_enabled)) {
2233 gen_exception(ctx, POWERPC_EXCP_FPU);
2234 return;
2235 }
2236 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2237 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2238 }
2239
2240 /* fnabs */
2241 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2242 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2243 /* fneg */
2244 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2245 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2246
2247 /*** Floating-Point status & ctrl register ***/
2248
2249 /* mcrfs */
2250 static void gen_mcrfs(DisasContext *ctx)
2251 {
2252 int bfa;
2253
2254 if (unlikely(!ctx->fpu_enabled)) {
2255 gen_exception(ctx, POWERPC_EXCP_FPU);
2256 return;
2257 }
2258 bfa = 4 * (7 - crfS(ctx->opcode));
2259 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2260 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2261 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2262 }
2263
2264 /* mffs */
2265 static void gen_mffs(DisasContext *ctx)
2266 {
2267 if (unlikely(!ctx->fpu_enabled)) {
2268 gen_exception(ctx, POWERPC_EXCP_FPU);
2269 return;
2270 }
2271 gen_reset_fpstatus();
2272 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2273 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2274 }
2275
2276 /* mtfsb0 */
2277 static void gen_mtfsb0(DisasContext *ctx)
2278 {
2279 uint8_t crb;
2280
2281 if (unlikely(!ctx->fpu_enabled)) {
2282 gen_exception(ctx, POWERPC_EXCP_FPU);
2283 return;
2284 }
2285 crb = 31 - crbD(ctx->opcode);
2286 gen_reset_fpstatus();
2287 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2288 TCGv_i32 t0;
2289 /* NIP cannot be restored if the memory exception comes from an helper */
2290 gen_update_nip(ctx, ctx->nip - 4);
2291 t0 = tcg_const_i32(crb);
2292 gen_helper_fpscr_clrbit(t0);
2293 tcg_temp_free_i32(t0);
2294 }
2295 if (unlikely(Rc(ctx->opcode) != 0)) {
2296 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2297 }
2298 }
2299
2300 /* mtfsb1 */
2301 static void gen_mtfsb1(DisasContext *ctx)
2302 {
2303 uint8_t crb;
2304
2305 if (unlikely(!ctx->fpu_enabled)) {
2306 gen_exception(ctx, POWERPC_EXCP_FPU);
2307 return;
2308 }
2309 crb = 31 - crbD(ctx->opcode);
2310 gen_reset_fpstatus();
2311 /* XXX: we pretend we can only do IEEE floating-point computations */
2312 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2313 TCGv_i32 t0;
2314 /* NIP cannot be restored if the memory exception comes from an helper */
2315 gen_update_nip(ctx, ctx->nip - 4);
2316 t0 = tcg_const_i32(crb);
2317 gen_helper_fpscr_setbit(t0);
2318 tcg_temp_free_i32(t0);
2319 }
2320 if (unlikely(Rc(ctx->opcode) != 0)) {
2321 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2322 }
2323 /* We can raise a differed exception */
2324 gen_helper_float_check_status();
2325 }
2326
2327 /* mtfsf */
2328 static void gen_mtfsf(DisasContext *ctx)
2329 {
2330 TCGv_i32 t0;
2331 int L = ctx->opcode & 0x02000000;
2332
2333 if (unlikely(!ctx->fpu_enabled)) {
2334 gen_exception(ctx, POWERPC_EXCP_FPU);
2335 return;
2336 }
2337 /* NIP cannot be restored if the memory exception comes from an helper */
2338 gen_update_nip(ctx, ctx->nip - 4);
2339 gen_reset_fpstatus();
2340 if (L)
2341 t0 = tcg_const_i32(0xff);
2342 else
2343 t0 = tcg_const_i32(FM(ctx->opcode));
2344 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2345 tcg_temp_free_i32(t0);
2346 if (unlikely(Rc(ctx->opcode) != 0)) {
2347 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2348 }
2349 /* We can raise a differed exception */
2350 gen_helper_float_check_status();
2351 }
2352
2353 /* mtfsfi */
2354 static void gen_mtfsfi(DisasContext *ctx)
2355 {
2356 int bf, sh;
2357 TCGv_i64 t0;
2358 TCGv_i32 t1;
2359
2360 if (unlikely(!ctx->fpu_enabled)) {
2361 gen_exception(ctx, POWERPC_EXCP_FPU);
2362 return;
2363 }
2364 bf = crbD(ctx->opcode) >> 2;
2365 sh = 7 - bf;
2366 /* NIP cannot be restored if the memory exception comes from an helper */
2367 gen_update_nip(ctx, ctx->nip - 4);
2368 gen_reset_fpstatus();
2369 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2370 t1 = tcg_const_i32(1 << sh);
2371 gen_helper_store_fpscr(t0, t1);
2372 tcg_temp_free_i64(t0);
2373 tcg_temp_free_i32(t1);
2374 if (unlikely(Rc(ctx->opcode) != 0)) {
2375 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2376 }
2377 /* We can raise a differed exception */
2378 gen_helper_float_check_status();
2379 }
2380
2381 /*** Addressing modes ***/
2382 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2383 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2384 target_long maskl)
2385 {
2386 target_long simm = SIMM(ctx->opcode);
2387
2388 simm &= ~maskl;
2389 if (rA(ctx->opcode) == 0) {
2390 #if defined(TARGET_PPC64)
2391 if (!ctx->sf_mode) {
2392 tcg_gen_movi_tl(EA, (uint32_t)simm);
2393 } else
2394 #endif
2395 tcg_gen_movi_tl(EA, simm);
2396 } else if (likely(simm != 0)) {
2397 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2398 #if defined(TARGET_PPC64)
2399 if (!ctx->sf_mode) {
2400 tcg_gen_ext32u_tl(EA, EA);
2401 }
2402 #endif
2403 } else {
2404 #if defined(TARGET_PPC64)
2405 if (!ctx->sf_mode) {
2406 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2407 } else
2408 #endif
2409 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2410 }
2411 }
2412
2413 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2414 {
2415 if (rA(ctx->opcode) == 0) {
2416 #if defined(TARGET_PPC64)
2417 if (!ctx->sf_mode) {
2418 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2419 } else
2420 #endif
2421 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2422 } else {
2423 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2424 #if defined(TARGET_PPC64)
2425 if (!ctx->sf_mode) {
2426 tcg_gen_ext32u_tl(EA, EA);
2427 }
2428 #endif
2429 }
2430 }
2431
2432 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2433 {
2434 if (rA(ctx->opcode) == 0) {
2435 tcg_gen_movi_tl(EA, 0);
2436 } else {
2437 #if defined(TARGET_PPC64)
2438 if (!ctx->sf_mode) {
2439 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2440 } else
2441 #endif
2442 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2443 }
2444 }
2445
2446 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2447 target_long val)
2448 {
2449 tcg_gen_addi_tl(ret, arg1, val);
2450 #if defined(TARGET_PPC64)
2451 if (!ctx->sf_mode) {
2452 tcg_gen_ext32u_tl(ret, ret);
2453 }
2454 #endif
2455 }
2456
2457 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2458 {
2459 int l1 = gen_new_label();
2460 TCGv t0 = tcg_temp_new();
2461 TCGv_i32 t1, t2;
2462 /* NIP cannot be restored if the memory exception comes from an helper */
2463 gen_update_nip(ctx, ctx->nip - 4);
2464 tcg_gen_andi_tl(t0, EA, mask);
2465 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2466 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2467 t2 = tcg_const_i32(0);
2468 gen_helper_raise_exception_err(t1, t2);
2469 tcg_temp_free_i32(t1);
2470 tcg_temp_free_i32(t2);
2471 gen_set_label(l1);
2472 tcg_temp_free(t0);
2473 }
2474
2475 /*** Integer load ***/
2476 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2477 {
2478 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2479 }
2480
2481 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2482 {
2483 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2484 }
2485
2486 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2487 {
2488 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2489 if (unlikely(ctx->le_mode)) {
2490 tcg_gen_bswap16_tl(arg1, arg1);
2491 }
2492 }
2493
2494 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2495 {
2496 if (unlikely(ctx->le_mode)) {
2497 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2498 tcg_gen_bswap16_tl(arg1, arg1);
2499 tcg_gen_ext16s_tl(arg1, arg1);
2500 } else {
2501 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2502 }
2503 }
2504
2505 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2506 {
2507 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2508 if (unlikely(ctx->le_mode)) {
2509 tcg_gen_bswap32_tl(arg1, arg1);
2510 }
2511 }
2512
2513 #if defined(TARGET_PPC64)
2514 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2515 {
2516 if (unlikely(ctx->le_mode)) {
2517 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2518 tcg_gen_bswap32_tl(arg1, arg1);
2519 tcg_gen_ext32s_tl(arg1, arg1);
2520 } else
2521 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2522 }
2523 #endif
2524
2525 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2526 {
2527 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2528 if (unlikely(ctx->le_mode)) {
2529 tcg_gen_bswap64_i64(arg1, arg1);
2530 }
2531 }
2532
2533 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2534 {
2535 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2536 }
2537
2538 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2539 {
2540 if (unlikely(ctx->le_mode)) {
2541 TCGv t0 = tcg_temp_new();
2542 tcg_gen_ext16u_tl(t0, arg1);
2543 tcg_gen_bswap16_tl(t0, t0);
2544 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2545 tcg_temp_free(t0);
2546 } else {
2547 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2548 }
2549 }
2550
2551 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2552 {
2553 if (unlikely(ctx->le_mode)) {
2554 TCGv t0 = tcg_temp_new();
2555 tcg_gen_ext32u_tl(t0, arg1);
2556 tcg_gen_bswap32_tl(t0, t0);
2557 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2558 tcg_temp_free(t0);
2559 } else {
2560 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2561 }
2562 }
2563
2564 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2565 {
2566 if (unlikely(ctx->le_mode)) {
2567 TCGv_i64 t0 = tcg_temp_new_i64();
2568 tcg_gen_bswap64_i64(t0, arg1);
2569 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2570 tcg_temp_free_i64(t0);
2571 } else
2572 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2573 }
2574
2575 #define GEN_LD(name, ldop, opc, type) \
2576 static void glue(gen_, name)(DisasContext *ctx) \
2577 { \
2578 TCGv EA; \
2579 gen_set_access_type(ctx, ACCESS_INT); \
2580 EA = tcg_temp_new(); \
2581 gen_addr_imm_index(ctx, EA, 0); \
2582 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2583 tcg_temp_free(EA); \
2584 }
2585
2586 #define GEN_LDU(name, ldop, opc, type) \
2587 static void glue(gen_, name##u)(DisasContext *ctx) \
2588 { \
2589 TCGv EA; \
2590 if (unlikely(rA(ctx->opcode) == 0 || \
2591 rA(ctx->opcode) == rD(ctx->opcode))) { \
2592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2593 return; \
2594 } \
2595 gen_set_access_type(ctx, ACCESS_INT); \
2596 EA = tcg_temp_new(); \
2597 if (type == PPC_64B) \
2598 gen_addr_imm_index(ctx, EA, 0x03); \
2599 else \
2600 gen_addr_imm_index(ctx, EA, 0); \
2601 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2602 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2603 tcg_temp_free(EA); \
2604 }
2605
2606 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2607 static void glue(gen_, name##ux)(DisasContext *ctx) \
2608 { \
2609 TCGv EA; \
2610 if (unlikely(rA(ctx->opcode) == 0 || \
2611 rA(ctx->opcode) == rD(ctx->opcode))) { \
2612 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2613 return; \
2614 } \
2615 gen_set_access_type(ctx, ACCESS_INT); \
2616 EA = tcg_temp_new(); \
2617 gen_addr_reg_index(ctx, EA); \
2618 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2619 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2620 tcg_temp_free(EA); \
2621 }
2622
2623 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2624 static void glue(gen_, name##x)(DisasContext *ctx) \
2625 { \
2626 TCGv EA; \
2627 gen_set_access_type(ctx, ACCESS_INT); \
2628 EA = tcg_temp_new(); \
2629 gen_addr_reg_index(ctx, EA); \
2630 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2631 tcg_temp_free(EA); \
2632 }
2633
2634 #define GEN_LDS(name, ldop, op, type) \
2635 GEN_LD(name, ldop, op | 0x20, type); \
2636 GEN_LDU(name, ldop, op | 0x21, type); \
2637 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2638 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2639
2640 /* lbz lbzu lbzux lbzx */
2641 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2642 /* lha lhau lhaux lhax */
2643 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2644 /* lhz lhzu lhzux lhzx */
2645 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2646 /* lwz lwzu lwzux lwzx */
2647 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2648 #if defined(TARGET_PPC64)
2649 /* lwaux */
2650 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2651 /* lwax */
2652 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2653 /* ldux */
2654 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2655 /* ldx */
2656 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2657
2658 static void gen_ld(DisasContext *ctx)
2659 {
2660 TCGv EA;
2661 if (Rc(ctx->opcode)) {
2662 if (unlikely(rA(ctx->opcode) == 0 ||
2663 rA(ctx->opcode) == rD(ctx->opcode))) {
2664 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2665 return;
2666 }
2667 }
2668 gen_set_access_type(ctx, ACCESS_INT);
2669 EA = tcg_temp_new();
2670 gen_addr_imm_index(ctx, EA, 0x03);
2671 if (ctx->opcode & 0x02) {
2672 /* lwa (lwau is undefined) */
2673 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2674 } else {
2675 /* ld - ldu */
2676 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2677 }
2678 if (Rc(ctx->opcode))
2679 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2680 tcg_temp_free(EA);
2681 }
2682
2683 /* lq */
2684 static void gen_lq(DisasContext *ctx)
2685 {
2686 #if defined(CONFIG_USER_ONLY)
2687 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2688 #else
2689 int ra, rd;
2690 TCGv EA;
2691
2692 /* Restore CPU state */
2693 if (unlikely(ctx->mem_idx == 0)) {
2694 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2695 return;
2696 }
2697 ra = rA(ctx->opcode);
2698 rd = rD(ctx->opcode);
2699 if (unlikely((rd & 1) || rd == ra)) {
2700 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2701 return;
2702 }
2703 if (unlikely(ctx->le_mode)) {
2704 /* Little-endian mode is not handled */
2705 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2706 return;
2707 }
2708 gen_set_access_type(ctx, ACCESS_INT);
2709 EA = tcg_temp_new();
2710 gen_addr_imm_index(ctx, EA, 0x0F);
2711 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2712 gen_addr_add(ctx, EA, EA, 8);
2713 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2714 tcg_temp_free(EA);
2715 #endif
2716 }
2717 #endif
2718
2719 /*** Integer store ***/
2720 #define GEN_ST(name, stop, opc, type) \
2721 static void glue(gen_, name)(DisasContext *ctx) \
2722 { \
2723 TCGv EA; \
2724 gen_set_access_type(ctx, ACCESS_INT); \
2725 EA = tcg_temp_new(); \
2726 gen_addr_imm_index(ctx, EA, 0); \
2727 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2728 tcg_temp_free(EA); \
2729 }
2730
2731 #define GEN_STU(name, stop, opc, type) \
2732 static void glue(gen_, stop##u)(DisasContext *ctx) \
2733 { \
2734 TCGv EA; \
2735 if (unlikely(rA(ctx->opcode) == 0)) { \
2736 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2737 return; \
2738 } \
2739 gen_set_access_type(ctx, ACCESS_INT); \
2740 EA = tcg_temp_new(); \
2741 if (type == PPC_64B) \
2742 gen_addr_imm_index(ctx, EA, 0x03); \
2743 else \
2744 gen_addr_imm_index(ctx, EA, 0); \
2745 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2746 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2747 tcg_temp_free(EA); \
2748 }
2749
2750 #define GEN_STUX(name, stop, opc2, opc3, type) \
2751 static void glue(gen_, name##ux)(DisasContext *ctx) \
2752 { \
2753 TCGv EA; \
2754 if (unlikely(rA(ctx->opcode) == 0)) { \
2755 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2756 return; \
2757 } \
2758 gen_set_access_type(ctx, ACCESS_INT); \
2759 EA = tcg_temp_new(); \
2760 gen_addr_reg_index(ctx, EA); \
2761 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2762 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2763 tcg_temp_free(EA); \
2764 }
2765
2766 #define GEN_STX(name, stop, opc2, opc3, type) \
2767 static void glue(gen_, name##x)(DisasContext *ctx) \
2768 { \
2769 TCGv EA; \
2770 gen_set_access_type(ctx, ACCESS_INT); \
2771 EA = tcg_temp_new(); \
2772 gen_addr_reg_index(ctx, EA); \
2773 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2774 tcg_temp_free(EA); \
2775 }
2776
2777 #define GEN_STS(name, stop, op, type) \
2778 GEN_ST(name, stop, op | 0x20, type); \
2779 GEN_STU(name, stop, op | 0x21, type); \
2780 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2781 GEN_STX(name, stop, 0x17, op | 0x00, type)
2782
2783 /* stb stbu stbux stbx */
2784 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2785 /* sth sthu sthux sthx */
2786 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2787 /* stw stwu stwux stwx */
2788 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2789 #if defined(TARGET_PPC64)
2790 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2791 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2792
2793 static void gen_std(DisasContext *ctx)
2794 {
2795 int rs;
2796 TCGv EA;
2797
2798 rs = rS(ctx->opcode);
2799 if ((ctx->opcode & 0x3) == 0x2) {
2800 #if defined(CONFIG_USER_ONLY)
2801 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2802 #else
2803 /* stq */
2804 if (unlikely(ctx->mem_idx == 0)) {
2805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2806 return;
2807 }
2808 if (unlikely(rs & 1)) {
2809 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2810 return;
2811 }
2812 if (unlikely(ctx->le_mode)) {
2813 /* Little-endian mode is not handled */
2814 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2815 return;
2816 }
2817 gen_set_access_type(ctx, ACCESS_INT);
2818 EA = tcg_temp_new();
2819 gen_addr_imm_index(ctx, EA, 0x03);
2820 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2821 gen_addr_add(ctx, EA, EA, 8);
2822 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2823 tcg_temp_free(EA);
2824 #endif
2825 } else {
2826 /* std / stdu */
2827 if (Rc(ctx->opcode)) {
2828 if (unlikely(rA(ctx->opcode) == 0)) {
2829 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2830 return;
2831 }
2832 }
2833 gen_set_access_type(ctx, ACCESS_INT);
2834 EA = tcg_temp_new();
2835 gen_addr_imm_index(ctx, EA, 0x03);
2836 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2837 if (Rc(ctx->opcode))
2838 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2839 tcg_temp_free(EA);
2840 }
2841 }
2842 #endif
2843 /*** Integer load and store with byte reverse ***/
2844 /* lhbrx */
2845 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2846 {
2847 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2848 if (likely(!ctx->le_mode)) {
2849 tcg_gen_bswap16_tl(arg1, arg1);
2850 }
2851 }
2852 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2853
2854 /* lwbrx */
2855 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2856 {
2857 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2858 if (likely(!ctx->le_mode)) {
2859 tcg_gen_bswap32_tl(arg1, arg1);
2860 }
2861 }
2862 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2863
2864 /* sthbrx */
2865 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2866 {
2867 if (likely(!ctx->le_mode)) {
2868 TCGv t0 = tcg_temp_new();
2869 tcg_gen_ext16u_tl(t0, arg1);
2870 tcg_gen_bswap16_tl(t0, t0);
2871 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2872 tcg_temp_free(t0);
2873 } else {
2874 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2875 }
2876 }
2877 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2878
2879 /* stwbrx */
2880 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2881 {
2882 if (likely(!ctx->le_mode)) {
2883 TCGv t0 = tcg_temp_new();
2884 tcg_gen_ext32u_tl(t0, arg1);
2885 tcg_gen_bswap32_tl(t0, t0);
2886 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2887 tcg_temp_free(t0);
2888 } else {
2889 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2890 }
2891 }
2892 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2893
2894 /*** Integer load and store multiple ***/
2895
2896 /* lmw */
2897 static void gen_lmw(DisasContext *ctx)
2898 {
2899 TCGv t0;
2900 TCGv_i32 t1;
2901 gen_set_access_type(ctx, ACCESS_INT);
2902 /* NIP cannot be restored if the memory exception comes from an helper */
2903 gen_update_nip(ctx, ctx->nip - 4);
2904 t0 = tcg_temp_new();
2905 t1 = tcg_const_i32(rD(ctx->opcode));
2906 gen_addr_imm_index(ctx, t0, 0);
2907 gen_helper_lmw(t0, t1);
2908 tcg_temp_free(t0);
2909 tcg_temp_free_i32(t1);
2910 }
2911
2912 /* stmw */
2913 static void gen_stmw(DisasContext *ctx)
2914 {
2915 TCGv t0;
2916 TCGv_i32 t1;
2917 gen_set_access_type(ctx, ACCESS_INT);
2918 /* NIP cannot be restored if the memory exception comes from an helper */
2919 gen_update_nip(ctx, ctx->nip - 4);
2920 t0 = tcg_temp_new();
2921 t1 = tcg_const_i32(rS(ctx->opcode));
2922 gen_addr_imm_index(ctx, t0, 0);
2923 gen_helper_stmw(t0, t1);
2924 tcg_temp_free(t0);
2925 tcg_temp_free_i32(t1);
2926 }
2927
2928 /*** Integer load and store strings ***/
2929
2930 /* lswi */
2931 /* PowerPC32 specification says we must generate an exception if
2932 * rA is in the range of registers to be loaded.
2933 * In an other hand, IBM says this is valid, but rA won't be loaded.
2934 * For now, I'll follow the spec...
2935 */
2936 static void gen_lswi(DisasContext *ctx)
2937 {
2938 TCGv t0;
2939 TCGv_i32 t1, t2;
2940 int nb = NB(ctx->opcode);
2941 int start = rD(ctx->opcode);
2942 int ra = rA(ctx->opcode);
2943 int nr;
2944
2945 if (nb == 0)
2946 nb = 32;
2947 nr = nb / 4;
2948 if (unlikely(((start + nr) > 32 &&
2949 start <= ra && (start + nr - 32) > ra) ||
2950 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2951 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2952 return;
2953 }
2954 gen_set_access_type(ctx, ACCESS_INT);
2955 /* NIP cannot be restored if the memory exception comes from an helper */
2956 gen_update_nip(ctx, ctx->nip - 4);
2957 t0 = tcg_temp_new();
2958 gen_addr_register(ctx, t0);
2959 t1 = tcg_const_i32(nb);
2960 t2 = tcg_const_i32(start);
2961 gen_helper_lsw(t0, t1, t2);
2962 tcg_temp_free(t0);
2963 tcg_temp_free_i32(t1);
2964 tcg_temp_free_i32(t2);
2965 }
2966
2967 /* lswx */
2968 static void gen_lswx(DisasContext *ctx)
2969 {
2970 TCGv t0;
2971 TCGv_i32 t1, t2, t3;
2972 gen_set_access_type(ctx, ACCESS_INT);
2973 /* NIP cannot be restored if the memory exception comes from an helper */
2974 gen_update_nip(ctx, ctx->nip - 4);
2975 t0 = tcg_temp_new();
2976 gen_addr_reg_index(ctx, t0);
2977 t1 = tcg_const_i32(rD(ctx->opcode));
2978 t2 = tcg_const_i32(rA(ctx->opcode));
2979 t3 = tcg_const_i32(rB(ctx->opcode));
2980 gen_helper_lswx(t0, t1, t2, t3);
2981 tcg_temp_free(t0);
2982 tcg_temp_free_i32(t1);
2983 tcg_temp_free_i32(t2);
2984 tcg_temp_free_i32(t3);
2985 }
2986
2987 /* stswi */
2988 static void gen_stswi(DisasContext *ctx)
2989 {
2990 TCGv t0;
2991 TCGv_i32 t1, t2;
2992 int nb = NB(ctx->opcode);
2993 gen_set_access_type(ctx, ACCESS_INT);
2994 /* NIP cannot be restored if the memory exception comes from an helper */
2995 gen_update_nip(ctx, ctx->nip - 4);
2996 t0 = tcg_temp_new();
2997 gen_addr_register(ctx, t0);
2998 if (nb == 0)
2999 nb = 32;
3000 t1 = tcg_const_i32(nb);
3001 t2 = tcg_const_i32(rS(ctx->opcode));
3002 gen_helper_stsw(t0, t1, t2);
3003 tcg_temp_free(t0);
3004 tcg_temp_free_i32(t1);
3005 tcg_temp_free_i32(t2);
3006 }
3007
3008 /* stswx */
3009 static void gen_stswx(DisasContext *ctx)
3010 {
3011 TCGv t0;
3012 TCGv_i32 t1, t2;
3013 gen_set_access_type(ctx, ACCESS_INT);
3014 /* NIP cannot be restored if the memory exception comes from an helper */
3015 gen_update_nip(ctx, ctx->nip - 4);
3016 t0 = tcg_temp_new();
3017 gen_addr_reg_index(ctx, t0);
3018 t1 = tcg_temp_new_i32();
3019 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3020 tcg_gen_andi_i32(t1, t1, 0x7F);
3021 t2 = tcg_const_i32(rS(ctx->opcode));
3022 gen_helper_stsw(t0, t1, t2);
3023 tcg_temp_free(t0);
3024 tcg_temp_free_i32(t1);
3025 tcg_temp_free_i32(t2);
3026 }
3027
3028 /*** Memory synchronisation ***/
3029 /* eieio */
3030 static void gen_eieio(DisasContext *ctx)
3031 {
3032 }
3033
3034 /* isync */
3035 static void gen_isync(DisasContext *ctx)
3036 {
3037 gen_stop_exception(ctx);
3038 }
3039
3040 /* lwarx */
3041 static void gen_lwarx(DisasContext *ctx)
3042 {
3043 TCGv t0;
3044 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3045 gen_set_access_type(ctx, ACCESS_RES);
3046 t0 = tcg_temp_local_new();
3047 gen_addr_reg_index(ctx, t0);
3048 gen_check_align(ctx, t0, 0x03);
3049 gen_qemu_ld32u(ctx, gpr, t0);
3050 tcg_gen_mov_tl(cpu_reserve, t0);
3051 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
3052 tcg_temp_free(t0);
3053 }
3054
3055 #if defined(CONFIG_USER_ONLY)
3056 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3057 int reg, int size)
3058 {
3059 TCGv t0 = tcg_temp_new();
3060 uint32_t save_exception = ctx->exception;
3061
3062 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea));
3063 tcg_gen_movi_tl(t0, (size << 5) | reg);
3064 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info));
3065 tcg_temp_free(t0);
3066 gen_update_nip(ctx, ctx->nip-4);
3067 ctx->exception = POWERPC_EXCP_BRANCH;
3068 gen_exception(ctx, POWERPC_EXCP_STCX);
3069 ctx->exception = save_exception;
3070 }
3071 #endif
3072
3073 /* stwcx. */
3074 static void gen_stwcx_(DisasContext *ctx)
3075 {
3076 TCGv t0;
3077 gen_set_access_type(ctx, ACCESS_RES);
3078 t0 = tcg_temp_local_new();
3079 gen_addr_reg_index(ctx, t0);
3080 gen_check_align(ctx, t0, 0x03);
3081 #if defined(CONFIG_USER_ONLY)
3082 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3083 #else
3084 {
3085 int l1;
3086
3087 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3088 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3089 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3090 l1 = gen_new_label();
3091 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3092 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3093 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3094 gen_set_label(l1);
3095 tcg_gen_movi_tl(cpu_reserve, -1);
3096 }
3097 #endif
3098 tcg_temp_free(t0);
3099 }
3100
3101 #if defined(TARGET_PPC64)
3102 /* ldarx */
3103 static void gen_ldarx(DisasContext *ctx)
3104 {
3105 TCGv t0;
3106 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3107 gen_set_access_type(ctx, ACCESS_RES);
3108 t0 = tcg_temp_local_new();
3109 gen_addr_reg_index(ctx, t0);
3110 gen_check_align(ctx, t0, 0x07);
3111 gen_qemu_ld64(ctx, gpr, t0);
3112 tcg_gen_mov_tl(cpu_reserve, t0);
3113 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
3114 tcg_temp_free(t0);
3115 }
3116
3117 /* stdcx. */
3118 static void gen_stdcx_(DisasContext *ctx)
3119 {
3120 TCGv t0;
3121 gen_set_access_type(ctx, ACCESS_RES);
3122 t0 = tcg_temp_local_new();
3123 gen_addr_reg_index(ctx, t0);
3124 gen_check_align(ctx, t0, 0x07);
3125 #if defined(CONFIG_USER_ONLY)
3126 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3127 #else
3128 {
3129 int l1;
3130 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3131 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3132 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3133 l1 = gen_new_label();
3134 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3135 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3136 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3137 gen_set_label(l1);
3138 tcg_gen_movi_tl(cpu_reserve, -1);
3139 }
3140 #endif
3141 tcg_temp_free(t0);
3142 }
3143 #endif /* defined(TARGET_PPC64) */
3144
3145 /* sync */
3146 static void gen_sync(DisasContext *ctx)
3147 {
3148 }
3149
3150 /* wait */
3151 static void gen_wait(DisasContext *ctx)
3152 {
3153 TCGv_i32 t0 = tcg_temp_new_i32();
3154 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3155 tcg_temp_free_i32(t0);
3156 /* Stop translation, as the CPU is supposed to sleep from now */
3157 gen_exception_err(ctx, EXCP_HLT, 1);
3158 }
3159
3160 /*** Floating-point load ***/
3161 #define GEN_LDF(name, ldop, opc, type) \
3162 static void glue(gen_, name)(DisasContext *ctx) \
3163 { \
3164 TCGv EA; \
3165 if (unlikely(!ctx->fpu_enabled)) { \
3166 gen_exception(ctx, POWERPC_EXCP_FPU); \
3167 return; \
3168 } \
3169 gen_set_access_type(ctx, ACCESS_FLOAT); \
3170 EA = tcg_temp_new(); \
3171 gen_addr_imm_index(ctx, EA, 0); \
3172 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3173 tcg_temp_free(EA); \
3174 }
3175
3176 #define GEN_LDUF(name, ldop, opc, type) \
3177 static void glue(gen_, name##u)(DisasContext *ctx) \
3178 { \
3179 TCGv EA; \
3180 if (unlikely(!ctx->fpu_enabled)) { \
3181 gen_exception(ctx, POWERPC_EXCP_FPU); \
3182 return; \
3183 } \
3184 if (unlikely(rA(ctx->opcode) == 0)) { \
3185 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3186 return; \
3187 } \
3188 gen_set_access_type(ctx, ACCESS_FLOAT); \
3189 EA = tcg_temp_new(); \
3190 gen_addr_imm_index(ctx, EA, 0); \
3191 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3192 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3193 tcg_temp_free(EA); \
3194 }
3195
3196 #define GEN_LDUXF(name, ldop, opc, type) \
3197 static void glue(gen_, name##ux)(DisasContext *ctx) \
3198 { \
3199 TCGv EA; \
3200 if (unlikely(!ctx->fpu_enabled)) { \
3201 gen_exception(ctx, POWERPC_EXCP_FPU); \
3202 return; \
3203 } \
3204 if (unlikely(rA(ctx->opcode) == 0)) { \
3205 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3206 return; \
3207 } \
3208 gen_set_access_type(ctx, ACCESS_FLOAT); \
3209 EA = tcg_temp_new(); \
3210 gen_addr_reg_index(ctx, EA); \
3211 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3212 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3213 tcg_temp_free(EA); \
3214 }
3215
3216 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3217 static void glue(gen_, name##x)(DisasContext *ctx) \
3218 { \
3219 TCGv EA; \
3220 if (unlikely(!ctx->fpu_enabled)) { \
3221 gen_exception(ctx, POWERPC_EXCP_FPU); \
3222 return; \
3223 } \
3224 gen_set_access_type(ctx, ACCESS_FLOAT); \
3225 EA = tcg_temp_new(); \
3226 gen_addr_reg_index(ctx, EA); \
3227 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3228 tcg_temp_free(EA); \
3229 }
3230
3231 #define GEN_LDFS(name, ldop, op, type) \
3232 GEN_LDF(name, ldop, op | 0x20, type); \
3233 GEN_LDUF(name, ldop, op | 0x21, type); \
3234 GEN_LDUXF(name, ldop, op | 0x01, type); \
3235 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3236
3237 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3238 {
3239 TCGv t0 = tcg_temp_new();
3240 TCGv_i32 t1 = tcg_temp_new_i32();
3241 gen_qemu_ld32u(ctx, t0, arg2);
3242 tcg_gen_trunc_tl_i32(t1, t0);
3243 tcg_temp_free(t0);
3244 gen_helper_float32_to_float64(arg1, t1);
3245 tcg_temp_free_i32(t1);
3246 }
3247
3248 /* lfd lfdu lfdux lfdx */
3249 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3250 /* lfs lfsu lfsux lfsx */
3251 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3252
3253 /*** Floating-point store ***/
3254 #define GEN_STF(name, stop, opc, type) \
3255 static void glue(gen_, name)(DisasContext *ctx) \
3256 { \
3257 TCGv EA; \
3258 if (unlikely(!ctx->fpu_enabled)) { \
3259 gen_exception(ctx, POWERPC_EXCP_FPU); \
3260 return; \
3261 } \
3262 gen_set_access_type(ctx, ACCESS_FLOAT); \
3263 EA = tcg_temp_new(); \
3264 gen_addr_imm_index(ctx, EA, 0); \
3265 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3266 tcg_temp_free(EA); \
3267 }
3268
3269 #define GEN_STUF(name, stop, opc, type) \
3270 static void glue(gen_, name##u)(DisasContext *ctx) \
3271 { \
3272 TCGv EA; \
3273 if (unlikely(!ctx->fpu_enabled)) { \
3274 gen_exception(ctx, POWERPC_EXCP_FPU); \
3275 return; \
3276 } \
3277 if (unlikely(rA(ctx->opcode) == 0)) { \
3278 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3279 return; \
3280 } \
3281 gen_set_access_type(ctx, ACCESS_FLOAT); \
3282 EA = tcg_temp_new(); \
3283 gen_addr_imm_index(ctx, EA, 0); \
3284 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3285 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3286 tcg_temp_free(EA); \
3287 }
3288
3289 #define GEN_STUXF(name, stop, opc, type) \
3290 static void glue(gen_, name##ux)(DisasContext *ctx) \
3291 { \
3292 TCGv EA; \
3293 if (unlikely(!ctx->fpu_enabled)) { \
3294 gen_exception(ctx, POWERPC_EXCP_FPU); \
3295 return; \
3296 } \
3297 if (unlikely(rA(ctx->opcode) == 0)) { \
3298 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3299 return; \
3300 } \
3301 gen_set_access_type(ctx, ACCESS_FLOAT); \
3302 EA = tcg_temp_new(); \
3303 gen_addr_reg_index(ctx, EA); \
3304 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3305 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3306 tcg_temp_free(EA); \
3307 }
3308
3309 #define GEN_STXF(name, stop, opc2, opc3, type) \
3310 static void glue(gen_, name##x)(DisasContext *ctx) \
3311 { \
3312 TCGv EA; \
3313 if (unlikely(!ctx->fpu_enabled)) { \
3314 gen_exception(ctx, POWERPC_EXCP_FPU); \
3315 return; \
3316 } \
3317 gen_set_access_type(ctx, ACCESS_FLOAT); \
3318 EA = tcg_temp_new(); \
3319 gen_addr_reg_index(ctx, EA); \
3320 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3321 tcg_temp_free(EA); \
3322 }
3323
3324 #define GEN_STFS(name, stop, op, type) \
3325 GEN_STF(name, stop, op | 0x20, type); \
3326 GEN_STUF(name, stop, op | 0x21, type); \
3327 GEN_STUXF(name, stop, op | 0x01, type); \
3328 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3329
3330 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3331 {
3332 TCGv_i32 t0 = tcg_temp_new_i32();
3333 TCGv t1 = tcg_temp_new();
3334 gen_helper_float64_to_float32(t0, arg1);
3335 tcg_gen_extu_i32_tl(t1, t0);
3336 tcg_temp_free_i32(t0);
3337 gen_qemu_st32(ctx, t1, arg2);
3338 tcg_temp_free(t1);
3339 }
3340
3341 /* stfd stfdu stfdux stfdx */
3342 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3343 /* stfs stfsu stfsux stfsx */
3344 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3345
3346 /* Optional: */
3347 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3348 {
3349 TCGv t0 = tcg_temp_new();
3350 tcg_gen_trunc_i64_tl(t0, arg1),
3351 gen_qemu_st32(ctx, t0, arg2);
3352 tcg_temp_free(t0);
3353 }
3354 /* stfiwx */
3355 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3356
3357 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3358 {
3359 #if defined(TARGET_PPC64)
3360 if (ctx->has_cfar)
3361 tcg_gen_movi_tl(cpu_cfar, nip);
3362 #endif
3363 }
3364
3365 /*** Branch ***/
3366 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3367 {
3368 TranslationBlock *tb;
3369 tb = ctx->tb;
3370 #if defined(TARGET_PPC64)
3371 if (!ctx->sf_mode)
3372 dest = (uint32_t) dest;
3373 #endif
3374 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3375 likely(!ctx->singlestep_enabled)) {
3376 tcg_gen_goto_tb(n);
3377 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3378 tcg_gen_exit_tb((tcg_target_long)tb + n);
3379 } else {
3380 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3381 if (unlikely(ctx->singlestep_enabled)) {
3382 if ((ctx->singlestep_enabled &
3383 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3384 ctx->exception == POWERPC_EXCP_BRANCH) {
3385 target_ulong tmp = ctx->nip;
3386 ctx->nip = dest;
3387 gen_exception(ctx, POWERPC_EXCP_TRACE);
3388 ctx->nip = tmp;
3389 }
3390 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3391 gen_debug_exception(ctx);
3392 }
3393 }
3394 tcg_gen_exit_tb(0);
3395 }
3396 }
3397
3398 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3399 {
3400 #if defined(TARGET_PPC64)
3401 if (ctx->sf_mode == 0)
3402 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3403 else
3404 #endif
3405 tcg_gen_movi_tl(cpu_lr, nip);
3406 }
3407
3408 /* b ba bl bla */
3409 static void gen_b(DisasContext *ctx)
3410 {
3411 target_ulong li, target;
3412
3413 ctx->exception = POWERPC_EXCP_BRANCH;
3414 /* sign extend LI */
3415 #if defined(TARGET_PPC64)
3416 if (ctx->sf_mode)
3417 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3418 else
3419 #endif
3420 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3421 if (likely(AA(ctx->opcode) == 0))
3422 target = ctx->nip + li - 4;
3423 else
3424 target = li;
3425 if (LK(ctx->opcode))
3426 gen_setlr(ctx, ctx->nip);
3427 gen_update_cfar(ctx, ctx->nip);
3428 gen_goto_tb(ctx, 0, target);
3429 }
3430
3431 #define BCOND_IM 0
3432 #define BCOND_LR 1
3433 #define BCOND_CTR 2
3434
3435 static inline void gen_bcond(DisasContext *ctx, int type)
3436 {
3437 uint32_t bo = BO(ctx->opcode);
3438 int l1;
3439 TCGv target;
3440
3441 ctx->exception = POWERPC_EXCP_BRANCH;
3442 if (type == BCOND_LR || type == BCOND_CTR) {
3443 target = tcg_temp_local_new();
3444 if (type == BCOND_CTR)
3445 tcg_gen_mov_tl(target, cpu_ctr);
3446 else
3447 tcg_gen_mov_tl(target, cpu_lr);
3448 } else {
3449 TCGV_UNUSED(target);
3450 }
3451 if (LK(ctx->opcode))
3452 gen_setlr(ctx, ctx->nip);
3453 l1 = gen_new_label();
3454 if ((bo & 0x4) == 0) {
3455 /* Decrement and test CTR */
3456 TCGv temp = tcg_temp_new();
3457 if (unlikely(type == BCOND_CTR)) {
3458 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3459 return;
3460 }
3461 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3462 #if defined(TARGET_PPC64)
3463 if (!ctx->sf_mode)
3464 tcg_gen_ext32u_tl(temp, cpu_ctr);
3465 else
3466 #endif
3467 tcg_gen_mov_tl(temp, cpu_ctr);
3468 if (bo & 0x2) {
3469 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3470 } else {
3471 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3472 }
3473 tcg_temp_free(temp);
3474 }
3475 if ((bo & 0x10) == 0) {
3476 /* Test CR */
3477 uint32_t bi = BI(ctx->opcode);
3478 uint32_t mask = 1 << (3 - (bi & 0x03));
3479 TCGv_i32 temp = tcg_temp_new_i32();
3480
3481 if (bo & 0x8) {
3482 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3483 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3484 } else {
3485 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3486 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3487 }
3488 tcg_temp_free_i32(temp);
3489 }
3490 gen_update_cfar(ctx, ctx->nip);
3491 if (type == BCOND_IM) {
3492 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3493 if (likely(AA(ctx->opcode) == 0)) {
3494 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3495 } else {
3496 gen_goto_tb(ctx, 0, li);
3497 }
3498 gen_set_label(l1);
3499 gen_goto_tb(ctx, 1, ctx->nip);
3500 } else {
3501 #if defined(TARGET_PPC64)
3502 if (!(ctx->sf_mode))
3503 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3504 else
3505 #endif
3506 tcg_gen_andi_tl(cpu_nip, target, ~3);
3507 tcg_gen_exit_tb(0);
3508 gen_set_label(l1);
3509 #if defined(TARGET_PPC64)
3510 if (!(ctx->sf_mode))
3511 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3512 else
3513 #endif
3514 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3515 tcg_gen_exit_tb(0);
3516 }
3517 }
3518
3519 static void gen_bc(DisasContext *ctx)
3520 {
3521 gen_bcond(ctx, BCOND_IM);
3522 }
3523
3524 static void gen_bcctr(DisasContext *ctx)
3525 {
3526 gen_bcond(ctx, BCOND_CTR);
3527 }
3528
3529 static void gen_bclr(DisasContext *ctx)
3530 {
3531 gen_bcond(ctx, BCOND_LR);
3532 }
3533
3534 /*** Condition register logical ***/
3535 #define GEN_CRLOGIC(name, tcg_op, opc) \
3536 static void glue(gen_, name)(DisasContext *ctx) \
3537 { \
3538 uint8_t bitmask; \
3539 int sh; \
3540 TCGv_i32 t0, t1; \
3541 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3542 t0 = tcg_temp_new_i32(); \
3543 if (sh > 0) \
3544 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3545 else if (sh < 0) \
3546 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3547 else \
3548 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3549 t1 = tcg_temp_new_i32(); \
3550 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3551 if (sh > 0) \
3552 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3553 else if (sh < 0) \
3554 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3555 else \
3556 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3557 tcg_op(t0, t0, t1); \
3558 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3559 tcg_gen_andi_i32(t0, t0, bitmask); \
3560 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3561 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3562 tcg_temp_free_i32(t0); \
3563 tcg_temp_free_i32(t1); \
3564 }
3565
3566 /* crand */
3567 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3568 /* crandc */
3569 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3570 /* creqv */
3571 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3572 /* crnand */
3573 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3574 /* crnor */
3575 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3576 /* cror */
3577 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3578 /* crorc */
3579 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3580 /* crxor */
3581 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3582
3583 /* mcrf */
3584 static void gen_mcrf(DisasContext *ctx)
3585 {
3586 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3587 }
3588
3589 /*** System linkage ***/
3590
3591 /* rfi (mem_idx only) */
3592 static void gen_rfi(DisasContext *ctx)
3593 {
3594 #if defined(CONFIG_USER_ONLY)
3595 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3596 #else
3597 /* Restore CPU state */
3598 if (unlikely(!ctx->mem_idx)) {
3599 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3600 return;
3601 }
3602 gen_update_cfar(ctx, ctx->nip);
3603 gen_helper_rfi();
3604 gen_sync_exception(ctx);
3605 #endif
3606 }
3607
3608 #if defined(TARGET_PPC64)
3609 static void gen_rfid(DisasContext *ctx)
3610 {
3611 #if defined(CONFIG_USER_ONLY)
3612 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3613 #else
3614 /* Restore CPU state */
3615 if (unlikely(!ctx->mem_idx)) {
3616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3617 return;
3618 }
3619 gen_update_cfar(ctx, ctx->nip);
3620 gen_helper_rfid();
3621 gen_sync_exception(ctx);
3622 #endif
3623 }
3624
3625 static void gen_hrfid(DisasContext *ctx)
3626 {
3627 #if defined(CONFIG_USER_ONLY)
3628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3629 #else
3630 /* Restore CPU state */
3631 if (unlikely(ctx->mem_idx <= 1)) {
3632 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3633 return;
3634 }
3635 gen_helper_hrfid();
3636 gen_sync_exception(ctx);
3637 #endif
3638 }
3639 #endif
3640
3641 /* sc */
3642 #if defined(CONFIG_USER_ONLY)
3643 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3644 #else
3645 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3646 #endif
3647 static void gen_sc(DisasContext *ctx)
3648 {
3649 uint32_t lev;
3650
3651 lev = (ctx->opcode >> 5) & 0x7F;
3652 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3653 }
3654
3655 /*** Trap ***/
3656
3657 /* tw */
3658 static void gen_tw(DisasContext *ctx)
3659 {
3660 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3661 /* Update the nip since this might generate a trap exception */
3662 gen_update_nip(ctx, ctx->nip);
3663 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3664 tcg_temp_free_i32(t0);
3665 }
3666
3667 /* twi */
3668 static void gen_twi(DisasContext *ctx)
3669 {
3670 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3671 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3672 /* Update the nip since this might generate a trap exception */
3673 gen_update_nip(ctx, ctx->nip);
3674 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3675 tcg_temp_free(t0);
3676 tcg_temp_free_i32(t1);
3677 }
3678
3679 #if defined(TARGET_PPC64)
3680 /* td */
3681 static void gen_td(DisasContext *ctx)
3682 {
3683 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3684 /* Update the nip since this might generate a trap exception */
3685 gen_update_nip(ctx, ctx->nip);
3686 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3687 tcg_temp_free_i32(t0);
3688 }
3689
3690 /* tdi */
3691 static void gen_tdi(DisasContext *ctx)
3692 {
3693 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3694 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3695 /* Update the nip since this might generate a trap exception */
3696 gen_update_nip(ctx, ctx->nip);
3697 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3698 tcg_temp_free(t0);
3699 tcg_temp_free_i32(t1);
3700 }
3701 #endif
3702
3703 /*** Processor control ***/
3704
3705 /* mcrxr */
3706 static void gen_mcrxr(DisasContext *ctx)
3707 {
3708 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3709 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3710 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3711 }
3712
3713 /* mfcr mfocrf */
3714 static void gen_mfcr(DisasContext *ctx)
3715 {
3716 uint32_t crm, crn;
3717
3718 if (likely(ctx->opcode & 0x00100000)) {
3719 crm = CRM(ctx->opcode);
3720 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3721 crn = ctz32 (crm);
3722 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3723 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3724 cpu_gpr[rD(ctx->opcode)], crn * 4);
3725 }
3726 } else {
3727 TCGv_i32 t0 = tcg_temp_new_i32();
3728 tcg_gen_mov_i32(t0, cpu_crf[0]);
3729 tcg_gen_shli_i32(t0, t0, 4);
3730 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3731 tcg_gen_shli_i32(t0, t0, 4);
3732 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3733 tcg_gen_shli_i32(t0, t0, 4);
3734 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3735 tcg_gen_shli_i32(t0, t0, 4);
3736 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3737 tcg_gen_shli_i32(t0, t0, 4);
3738 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3739 tcg_gen_shli_i32(t0, t0, 4);
3740 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3741 tcg_gen_shli_i32(t0, t0, 4);
3742 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3743 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3744 tcg_temp_free_i32(t0);
3745 }
3746 }
3747
3748 /* mfmsr */
3749 static void gen_mfmsr(DisasContext *ctx)
3750 {
3751 #if defined(CONFIG_USER_ONLY)
3752 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3753 #else
3754 if (unlikely(!ctx->mem_idx)) {
3755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3756 return;
3757 }
3758 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3759 #endif
3760 }
3761
3762 static void spr_noaccess(void *opaque, int gprn, int sprn)
3763 {
3764 #if 0
3765 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3766 printf("ERROR: try to access SPR %d !\n", sprn);
3767 #endif
3768 }
3769 #define SPR_NOACCESS (&spr_noaccess)
3770
3771 /* mfspr */
3772 static inline void gen_op_mfspr(DisasContext *ctx)
3773 {
3774 void (*read_cb)(void *opaque, int gprn, int sprn);
3775 uint32_t sprn = SPR(ctx->opcode);
3776
3777 #if !defined(CONFIG_USER_ONLY)
3778 if (ctx->mem_idx == 2)
3779 read_cb = ctx->spr_cb[sprn].hea_read;
3780 else if (ctx->mem_idx)
3781 read_cb = ctx->spr_cb[sprn].oea_read;
3782 else
3783 #endif
3784 read_cb = ctx->spr_cb[sprn].uea_read;
3785 if (likely(read_cb != NULL)) {
3786 if (likely(read_cb != SPR_NOACCESS)) {
3787 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3788 } else {
3789 /* Privilege exception */
3790 /* This is a hack to avoid warnings when running Linux:
3791 * this OS breaks the PowerPC virtualisation model,
3792 * allowing userland application to read the PVR
3793 */
3794 if (sprn != SPR_PVR) {
3795 qemu_log("Trying to read privileged spr %d %03x at "
3796 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3797 printf("Trying to read privileged spr %d %03x at "
3798 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3799 }
3800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3801 }
3802 } else {
3803 /* Not defined */
3804 qemu_log("Trying to read invalid spr %d %03x at "
3805 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3806 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3807 sprn, sprn, ctx->nip);
3808 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3809 }
3810 }
3811
3812 static void gen_mfspr(DisasContext *ctx)
3813 {
3814 gen_op_mfspr(ctx);
3815 }
3816
3817 /* mftb */
3818 static void gen_mftb(DisasContext *ctx)
3819 {
3820 gen_op_mfspr(ctx);
3821 }
3822
3823 /* mtcrf mtocrf*/
3824 static void gen_mtcrf(DisasContext *ctx)
3825 {
3826 uint32_t crm, crn;
3827
3828 crm = CRM(ctx->opcode);
3829 if (likely((ctx->opcode & 0x00100000))) {
3830 if (crm && ((crm & (crm - 1)) == 0)) {
3831 TCGv_i32 temp = tcg_temp_new_i32();
3832 crn = ctz32 (crm);
3833 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3834 tcg_gen_shri_i32(temp, temp, crn * 4);
3835 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3836 tcg_temp_free_i32(temp);
3837 }
3838 } else {
3839 TCGv_i32 temp = tcg_temp_new_i32();
3840 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3841 for (crn = 0 ; crn < 8 ; crn++) {
3842 if (crm & (1 << crn)) {
3843 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3844 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3845 }
3846 }
3847 tcg_temp_free_i32(temp);
3848 }
3849 }
3850
3851 /* mtmsr */
3852 #if defined(TARGET_PPC64)
3853 static void gen_mtmsrd(DisasContext *ctx)
3854 {
3855 #if defined(CONFIG_USER_ONLY)
3856 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3857 #else
3858 if (unlikely(!ctx->mem_idx)) {
3859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3860 return;
3861 }
3862 if (ctx->opcode & 0x00010000) {
3863 /* Special form that does not need any synchronisation */
3864 TCGv t0 = tcg_temp_new();
3865 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3866 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3867 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3868 tcg_temp_free(t0);
3869 } else {
3870 /* XXX: we need to update nip before the store
3871 * if we enter power saving mode, we will exit the loop
3872 * directly from ppc_store_msr
3873 */
3874 gen_update_nip(ctx, ctx->nip);
3875 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3876 /* Must stop the translation as machine state (may have) changed */
3877 /* Note that mtmsr is not always defined as context-synchronizing */
3878 gen_stop_exception(ctx);
3879 }
3880 #endif
3881 }
3882 #endif
3883
3884 static void gen_mtmsr(DisasContext *ctx)
3885 {
3886 #if defined(CONFIG_USER_ONLY)
3887 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3888 #else
3889 if (unlikely(!ctx->mem_idx)) {
3890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3891 return;
3892 }
3893 if (ctx->opcode & 0x00010000) {
3894 /* Special form that does not need any synchronisation */
3895 TCGv t0 = tcg_temp_new();
3896 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3897 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3898 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3899 tcg_temp_free(t0);
3900 } else {
3901 TCGv msr = tcg_temp_new();
3902
3903 /* XXX: we need to update nip before the store
3904 * if we enter power saving mode, we will exit the loop
3905 * directly from ppc_store_msr
3906 */
3907 gen_update_nip(ctx, ctx->nip);
3908 #if defined(TARGET_PPC64)
3909 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3910 #else
3911 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3912 #endif
3913 gen_helper_store_msr(msr);
3914 /* Must stop the translation as machine state (may have) changed */
3915 /* Note that mtmsr is not always defined as context-synchronizing */
3916 gen_stop_exception(ctx);
3917 }
3918 #endif
3919 }
3920
3921 /* mtspr */
3922 static void gen_mtspr(DisasContext *ctx)
3923 {
3924 void (*write_cb)(void *opaque, int sprn, int gprn);
3925 uint32_t sprn = SPR(ctx->opcode);
3926
3927 #if !defined(CONFIG_USER_ONLY)
3928 if (ctx->mem_idx == 2)
3929 write_cb = ctx->spr_cb[sprn].hea_write;
3930 else if (ctx->mem_idx)
3931 write_cb = ctx->spr_cb[sprn].oea_write;
3932 else
3933 #endif
3934 write_cb = ctx->spr_cb[sprn].uea_write;
3935 if (likely(write_cb != NULL)) {
3936 if (likely(write_cb != SPR_NOACCESS)) {
3937 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3938 } else {
3939 /* Privilege exception */
3940 qemu_log("Trying to write privileged spr %d %03x at "
3941 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3942 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3943 "\n", sprn, sprn, ctx->nip);
3944 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3945 }
3946 } else {
3947 /* Not defined */
3948 qemu_log("Trying to write invalid spr %d %03x at "
3949 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3950 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3951 sprn, sprn, ctx->nip);
3952 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3953 }
3954 }
3955
3956 /*** Cache management ***/
3957
3958 /* dcbf */
3959 static void gen_dcbf(DisasContext *ctx)
3960 {
3961 /* XXX: specification says this is treated as a load by the MMU */
3962 TCGv t0;
3963 gen_set_access_type(ctx, ACCESS_CACHE);
3964 t0 = tcg_temp_new();
3965 gen_addr_reg_index(ctx, t0);
3966 gen_qemu_ld8u(ctx, t0, t0);
3967 tcg_temp_free(t0);
3968 }
3969
3970 /* dcbi (Supervisor only) */
3971 static void gen_dcbi(DisasContext *ctx)
3972 {
3973 #if defined(CONFIG_USER_ONLY)
3974 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3975 #else
3976 TCGv EA, val;
3977 if (unlikely(!ctx->mem_idx)) {
3978 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3979 return;
3980 }
3981 EA = tcg_temp_new();
3982 gen_set_access_type(ctx, ACCESS_CACHE);
3983 gen_addr_reg_index(ctx, EA);
3984 val = tcg_temp_new();
3985 /* XXX: specification says this should be treated as a store by the MMU */
3986 gen_qemu_ld8u(ctx, val, EA);
3987 gen_qemu_st8(ctx, val, EA);
3988 tcg_temp_free(val);
3989 tcg_temp_free(EA);
3990 #endif
3991 }
3992
3993 /* dcdst */
3994 static void gen_dcbst(DisasContext *ctx)
3995 {
3996 /* XXX: specification say this is treated as a load by the MMU */
3997 TCGv t0;
3998 gen_set_access_type(ctx, ACCESS_CACHE);
3999 t0 = tcg_temp_new();
4000 gen_addr_reg_index(ctx, t0);
4001 gen_qemu_ld8u(ctx, t0, t0);
4002 tcg_temp_free(t0);
4003 }
4004
4005 /* dcbt */
4006 static void gen_dcbt(DisasContext *ctx)
4007 {
4008 /* interpreted as no-op */
4009 /* XXX: specification say this is treated as a load by the MMU
4010 * but does not generate any exception
4011 */
4012 }
4013
4014 /* dcbtst */
4015 static void gen_dcbtst(DisasContext *ctx)
4016 {
4017 /* interpreted as no-op */
4018 /* XXX: specification say this is treated as a load by the MMU
4019 * but does not generate any exception
4020 */
4021 }
4022
4023 /* dcbz */
4024 static void gen_dcbz(DisasContext *ctx)
4025 {
4026 TCGv t0;
4027 gen_set_access_type(ctx, ACCESS_CACHE);
4028 /* NIP cannot be restored if the memory exception comes from an helper */
4029 gen_update_nip(ctx, ctx->nip - 4);
4030 t0 = tcg_temp_new();
4031 gen_addr_reg_index(ctx, t0);
4032 gen_helper_dcbz(t0);
4033 tcg_temp_free(t0);
4034 }
4035
4036 static void gen_dcbz_970(DisasContext *ctx)
4037 {
4038 TCGv t0;
4039 gen_set_access_type(ctx, ACCESS_CACHE);
4040 /* NIP cannot be restored if the memory exception comes from an helper */
4041 gen_update_nip(ctx, ctx->nip - 4);
4042 t0 = tcg_temp_new();
4043 gen_addr_reg_index(ctx, t0);
4044 if (ctx->opcode & 0x00200000)
4045 gen_helper_dcbz(t0);
4046 else
4047 gen_helper_dcbz_970(t0);
4048 tcg_temp_free(t0);
4049 }
4050
4051 /* dst / dstt */
4052 static void gen_dst(DisasContext *ctx)
4053 {
4054 if (rA(ctx->opcode) == 0) {
4055 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4056 } else {
4057 /* interpreted as no-op */
4058 }
4059 }
4060
4061 /* dstst /dststt */
4062 static void gen_dstst(DisasContext *ctx)
4063 {
4064 if (rA(ctx->opcode) == 0) {
4065 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4066 } else {
4067 /* interpreted as no-op */
4068 }
4069
4070 }
4071
4072 /* dss / dssall */
4073 static void gen_dss(DisasContext *ctx)
4074 {
4075 /* interpreted as no-op */
4076 }
4077
4078 /* icbi */
4079 static void gen_icbi(DisasContext *ctx)
4080 {
4081 TCGv t0;
4082 gen_set_access_type(ctx, ACCESS_CACHE);
4083 /* NIP cannot be restored if the memory exception comes from an helper */
4084 gen_update_nip(ctx, ctx->nip - 4);
4085 t0 = tcg_temp_new();
4086 gen_addr_reg_index(ctx, t0);
4087 gen_helper_icbi(t0);
4088 tcg_temp_free(t0);
4089 }
4090
4091 /* Optional: */
4092 /* dcba */
4093 static void gen_dcba(DisasContext *ctx)
4094 {
4095 /* interpreted as no-op */
4096 /* XXX: specification say this is treated as a store by the MMU
4097 * but does not generate any exception
4098 */
4099 }
4100
4101 /*** Segment register manipulation ***/
4102 /* Supervisor only: */
4103
4104 /* mfsr */
4105 static void gen_mfsr(DisasContext *ctx)
4106 {
4107 #if defined(CONFIG_USER_ONLY)
4108 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4109 #else
4110 TCGv t0;
4111 if (unlikely(!ctx->mem_idx)) {
4112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4113 return;
4114 }
4115 t0 = tcg_const_tl(SR(ctx->opcode));
4116 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4117 tcg_temp_free(t0);
4118 #endif
4119 }
4120
4121 /* mfsrin */
4122 static void gen_mfsrin(DisasContext *ctx)
4123 {
4124 #if defined(CONFIG_USER_ONLY)
4125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4126 #else
4127 TCGv t0;
4128 if (unlikely(!ctx->mem_idx)) {
4129 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4130 return;
4131 }
4132 t0 = tcg_temp_new();
4133 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4134 tcg_gen_andi_tl(t0, t0, 0xF);
4135 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4136 tcg_temp_free(t0);
4137 #endif
4138 }
4139
4140 /* mtsr */
4141 static void gen_mtsr(DisasContext *ctx)
4142 {
4143 #if defined(CONFIG_USER_ONLY)
4144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4145 #else
4146 TCGv t0;
4147 if (unlikely(!ctx->mem_idx)) {
4148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4149 return;
4150 }
4151 t0 = tcg_const_tl(SR(ctx->opcode));
4152 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4153 tcg_temp_free(t0);
4154 #endif
4155 }
4156
4157 /* mtsrin */
4158 static void gen_mtsrin(DisasContext *ctx)
4159 {
4160 #if defined(CONFIG_USER_ONLY)
4161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4162 #else
4163 TCGv t0;
4164 if (unlikely(!ctx->mem_idx)) {
4165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4166 return;
4167 }
4168 t0 = tcg_temp_new();
4169 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4170 tcg_gen_andi_tl(t0, t0, 0xF);
4171 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4172 tcg_temp_free(t0);
4173 #endif
4174 }
4175
4176 #if defined(TARGET_PPC64)
4177 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4178
4179 /* mfsr */
4180 static void gen_mfsr_64b(DisasContext *ctx)
4181 {
4182 #if defined(CONFIG_USER_ONLY)
4183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4184 #else
4185 TCGv t0;
4186 if (unlikely(!ctx->mem_idx)) {
4187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4188 return;
4189 }
4190 t0 = tcg_const_tl(SR(ctx->opcode));
4191 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4192 tcg_temp_free(t0);
4193 #endif
4194 }
4195
4196 /* mfsrin */
4197 static void gen_mfsrin_64b(DisasContext *ctx)
4198 {
4199 #if defined(CONFIG_USER_ONLY)
4200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4201 #else
4202 TCGv t0;
4203 if (unlikely(!ctx->mem_idx)) {
4204 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4205 return;
4206 }
4207 t0 = tcg_temp_new();
4208 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4209 tcg_gen_andi_tl(t0, t0, 0xF);
4210 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4211 tcg_temp_free(t0);
4212 #endif
4213 }
4214
4215 /* mtsr */
4216 static void gen_mtsr_64b(DisasContext *ctx)
4217 {
4218 #if defined(CONFIG_USER_ONLY)
4219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4220 #else
4221 TCGv t0;
4222 if (unlikely(!ctx->mem_idx)) {
4223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4224 return;
4225 }
4226 t0 = tcg_const_tl(SR(ctx->opcode));
4227 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4228 tcg_temp_free(t0);
4229 #endif
4230 }
4231
4232 /* mtsrin */
4233 static void gen_mtsrin_64b(DisasContext *ctx)
4234 {
4235 #if defined(CONFIG_USER_ONLY)
4236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4237 #else
4238 TCGv t0;
4239 if (unlikely(!ctx->mem_idx)) {
4240 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4241 return;
4242 }
4243 t0 = tcg_temp_new();
4244 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4245 tcg_gen_andi_tl(t0, t0, 0xF);
4246 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4247 tcg_temp_free(t0);
4248 #endif
4249 }
4250
4251 /* slbmte */
4252 static void gen_slbmte(DisasContext *ctx)
4253 {
4254 #if defined(CONFIG_USER_ONLY)
4255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4256 #else
4257 if (unlikely(!ctx->mem_idx)) {
4258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4259 return;
4260 }
4261 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4262 #endif
4263 }
4264
4265 static void gen_slbmfee(DisasContext *ctx)
4266 {
4267 #if defined(CONFIG_USER_ONLY)
4268 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4269 #else
4270 if (unlikely(!ctx->mem_idx)) {
4271 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4272 return;
4273 }
4274 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)],
4275 cpu_gpr[rB(ctx->opcode)]);
4276 #endif
4277 }
4278
4279 static void gen_slbmfev(DisasContext *ctx)
4280 {
4281 #if defined(CONFIG_USER_ONLY)
4282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4283 #else
4284 if (unlikely(!ctx->mem_idx)) {
4285 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4286 return;
4287 }
4288 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)],
4289 cpu_gpr[rB(ctx->opcode)]);
4290 #endif
4291 }
4292 #endif /* defined(TARGET_PPC64) */
4293
4294 /*** Lookaside buffer management ***/
4295 /* Optional & mem_idx only: */
4296
4297 /* tlbia */
4298 static void gen_tlbia(DisasContext *ctx)
4299 {
4300 #if defined(CONFIG_USER_ONLY)
4301 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4302 #else
4303 if (unlikely(!ctx->mem_idx)) {
4304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4305 return;
4306 }
4307 gen_helper_tlbia();
4308 #endif
4309 }
4310
4311 /* tlbiel */
4312 static void gen_tlbiel(DisasContext *ctx)
4313 {
4314 #if defined(CONFIG_USER_ONLY)
4315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4316 #else
4317 if (unlikely(!ctx->mem_idx)) {
4318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4319 return;
4320 }
4321 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4322 #endif
4323 }
4324
4325 /* tlbie */
4326 static void gen_tlbie(DisasContext *ctx)
4327 {
4328 #if defined(CONFIG_USER_ONLY)
4329 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4330 #else
4331 if (unlikely(!ctx->mem_idx)) {
4332 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4333 return;
4334 }
4335 #if defined(TARGET_PPC64)
4336 if (!ctx->sf_mode) {
4337 TCGv t0 = tcg_temp_new();
4338 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4339 gen_helper_tlbie(t0);
4340 tcg_temp_free(t0);
4341 } else
4342 #endif
4343 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4344 #endif
4345 }
4346
4347 /* tlbsync */
4348 static void gen_tlbsync(DisasContext *ctx)
4349 {
4350 #if defined(CONFIG_USER_ONLY)
4351 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4352 #else
4353 if (unlikely(!ctx->mem_idx)) {
4354 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4355 return;
4356 }
4357 /* This has no effect: it should ensure that all previous
4358 * tlbie have completed
4359 */
4360 gen_stop_exception(ctx);
4361 #endif
4362 }
4363
4364 #if defined(TARGET_PPC64)
4365 /* slbia */
4366 static void gen_slbia(DisasContext *ctx)
4367 {
4368 #if defined(CONFIG_USER_ONLY)
4369 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4370 #else
4371 if (unlikely(!ctx->mem_idx)) {
4372 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4373 return;
4374 }
4375 gen_helper_slbia();
4376 #endif
4377 }
4378
4379 /* slbie */
4380 static void gen_slbie(DisasContext *ctx)
4381 {
4382 #if defined(CONFIG_USER_ONLY)
4383 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4384 #else
4385 if (unlikely(!ctx->mem_idx)) {
4386 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4387 return;
4388 }
4389 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4390 #endif
4391 }
4392 #endif
4393
4394 /*** External control ***/
4395 /* Optional: */
4396
4397 /* eciwx */
4398 static void gen_eciwx(DisasContext *ctx)
4399 {
4400 TCGv t0;
4401 /* Should check EAR[E] ! */
4402 gen_set_access_type(ctx, ACCESS_EXT);
4403 t0 = tcg_temp_new();
4404 gen_addr_reg_index(ctx, t0);
4405 gen_check_align(ctx, t0, 0x03);
4406 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4407 tcg_temp_free(t0);
4408 }
4409
4410 /* ecowx */
4411 static void gen_ecowx(DisasContext *ctx)
4412 {
4413 TCGv t0;
4414 /* Should check EAR[E] ! */
4415 gen_set_access_type(ctx, ACCESS_EXT);
4416 t0 = tcg_temp_new();
4417 gen_addr_reg_index(ctx, t0);
4418 gen_check_align(ctx, t0, 0x03);
4419 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4420 tcg_temp_free(t0);
4421 }
4422
4423 /* PowerPC 601 specific instructions */
4424
4425 /* abs - abs. */
4426 static void gen_abs(DisasContext *ctx)
4427 {
4428 int l1 = gen_new_label();
4429 int l2 = gen_new_label();
4430 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4431 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4432 tcg_gen_br(l2);
4433 gen_set_label(l1);
4434 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4435 gen_set_label(l2);
4436 if (unlikely(Rc(ctx->opcode) != 0))
4437 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4438 }
4439
4440 /* abso - abso. */
4441 static void gen_abso(DisasContext *ctx)
4442 {
4443 int l1 = gen_new_label();
4444 int l2 = gen_new_label();
4445 int l3 = gen_new_label();
4446 /* Start with XER OV disabled, the most likely case */
4447 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4448 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4449 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4450 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4451 tcg_gen_br(l2);
4452 gen_set_label(l1);
4453 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4454 tcg_gen_br(l3);
4455 gen_set_label(l2);
4456 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4457 gen_set_label(l3);
4458 if (unlikely(Rc(ctx->opcode) != 0))
4459 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4460 }
4461
4462 /* clcs */
4463 static void gen_clcs(DisasContext *ctx)
4464 {
4465 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4466 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4467 tcg_temp_free_i32(t0);
4468 /* Rc=1 sets CR0 to an undefined state */
4469 }
4470
4471 /* div - div. */
4472 static void gen_div(DisasContext *ctx)
4473 {
4474 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4475 if (unlikely(Rc(ctx->opcode) != 0))
4476 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4477 }
4478
4479 /* divo - divo. */
4480 static void gen_divo(DisasContext *ctx)
4481 {
4482 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4483 if (unlikely(Rc(ctx->opcode) != 0))
4484 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4485 }
4486
4487 /* divs - divs. */
4488 static void gen_divs(DisasContext *ctx)
4489 {
4490 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4491 if (unlikely(Rc(ctx->opcode) != 0))
4492 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4493 }
4494
4495 /* divso - divso. */
4496 static void gen_divso(DisasContext *ctx)
4497 {
4498 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4499 if (unlikely(Rc(ctx->opcode) != 0))
4500 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4501 }
4502
4503 /* doz - doz. */
4504 static void gen_doz(DisasContext *ctx)
4505 {
4506 int l1 = gen_new_label();
4507 int l2 = gen_new_label();
4508 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4509 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4510 tcg_gen_br(l2);
4511 gen_set_label(l1);
4512 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4513 gen_set_label(l2);
4514 if (unlikely(Rc(ctx->opcode) != 0))
4515 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4516 }
4517
4518 /* dozo - dozo. */
4519 static void gen_dozo(DisasContext *ctx)
4520 {
4521 int l1 = gen_new_label();
4522 int l2 = gen_new_label();
4523 TCGv t0 = tcg_temp_new();
4524 TCGv t1 = tcg_temp_new();
4525 TCGv t2 = tcg_temp_new();
4526 /* Start with XER OV disabled, the most likely case */
4527 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4528 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4529 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4530 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4531 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4532 tcg_gen_andc_tl(t1, t1, t2);
4533 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4534 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4535 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4536 tcg_gen_br(l2);
4537 gen_set_label(l1);
4538 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4539 gen_set_label(l2);
4540 tcg_temp_free(t0);
4541 tcg_temp_free(t1);
4542 tcg_temp_free(t2);
4543 if (unlikely(Rc(ctx->opcode) != 0))
4544 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4545 }
4546
4547 /* dozi */
4548 static void gen_dozi(DisasContext *ctx)
4549 {
4550 target_long simm = SIMM(ctx->opcode);
4551 int l1 = gen_new_label();
4552 int l2 = gen_new_label();
4553 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4554 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4555 tcg_gen_br(l2);
4556 gen_set_label(l1);
4557 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4558 gen_set_label(l2);
4559 if (unlikely(Rc(ctx->opcode) != 0))
4560 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4561 }
4562
4563 /* lscbx - lscbx. */
4564 static void gen_lscbx(DisasContext *ctx)
4565 {
4566 TCGv t0 = tcg_temp_new();
4567 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4568 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4569 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4570
4571 gen_addr_reg_index(ctx, t0);
4572 /* NIP cannot be restored if the memory exception comes from an helper */
4573 gen_update_nip(ctx, ctx->nip - 4);
4574 gen_helper_lscbx(t0, t0, t1, t2, t3);
4575 tcg_temp_free_i32(t1);
4576 tcg_temp_free_i32(t2);
4577 tcg_temp_free_i32(t3);
4578 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4579 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4580 if (unlikely(Rc(ctx->opcode) != 0))
4581 gen_set_Rc0(ctx, t0);
4582 tcg_temp_free(t0);
4583 }
4584
4585 /* maskg - maskg. */
4586 static void gen_maskg(DisasContext *ctx)
4587 {
4588 int l1 = gen_new_label();
4589 TCGv t0 = tcg_temp_new();
4590 TCGv t1 = tcg_temp_new();
4591 TCGv t2 = tcg_temp_new();
4592 TCGv t3 = tcg_temp_new();
4593 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4594 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4595 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4596 tcg_gen_addi_tl(t2, t0, 1);
4597 tcg_gen_shr_tl(t2, t3, t2);
4598 tcg_gen_shr_tl(t3, t3, t1);
4599 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4600 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4601 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4602 gen_set_label(l1);
4603 tcg_temp_free(t0);
4604 tcg_temp_free(t1);
4605 tcg_temp_free(t2);
4606 tcg_temp_free(t3);
4607 if (unlikely(Rc(ctx->opcode) != 0))
4608 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4609 }
4610
4611 /* maskir - maskir. */
4612 static void gen_maskir(DisasContext *ctx)
4613 {
4614 TCGv t0 = tcg_temp_new();
4615 TCGv t1 = tcg_temp_new();
4616 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4617 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4618 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4619 tcg_temp_free(t0);
4620 tcg_temp_free(t1);
4621 if (unlikely(Rc(ctx->opcode) != 0))
4622 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4623 }
4624
4625 /* mul - mul. */
4626 static void gen_mul(DisasContext *ctx)
4627 {
4628 TCGv_i64 t0 = tcg_temp_new_i64();
4629 TCGv_i64 t1 = tcg_temp_new_i64();
4630 TCGv t2 = tcg_temp_new();
4631 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4632 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4633 tcg_gen_mul_i64(t0, t0, t1);
4634 tcg_gen_trunc_i64_tl(t2, t0);
4635 gen_store_spr(SPR_MQ, t2);
4636 tcg_gen_shri_i64(t1, t0, 32);
4637 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4638 tcg_temp_free_i64(t0);
4639 tcg_temp_free_i64(t1);
4640 tcg_temp_free(t2);
4641 if (unlikely(Rc(ctx->opcode) != 0))
4642 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4643 }
4644
4645 /* mulo - mulo. */
4646 static void gen_mulo(DisasContext *ctx)
4647 {
4648 int l1 = gen_new_label();
4649 TCGv_i64 t0 = tcg_temp_new_i64();
4650 TCGv_i64 t1 = tcg_temp_new_i64();
4651 TCGv t2 = tcg_temp_new();
4652 /* Start with XER OV disabled, the most likely case */
4653 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4654 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4655 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4656 tcg_gen_mul_i64(t0, t0, t1);
4657 tcg_gen_trunc_i64_tl(t2, t0);
4658 gen_store_spr(SPR_MQ, t2);
4659 tcg_gen_shri_i64(t1, t0, 32);
4660 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4661 tcg_gen_ext32s_i64(t1, t0);
4662 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4663 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4664 gen_set_label(l1);
4665 tcg_temp_free_i64(t0);
4666 tcg_temp_free_i64(t1);
4667 tcg_temp_free(t2);
4668 if (unlikely(Rc(ctx->opcode) != 0))
4669 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4670 }
4671
4672 /* nabs - nabs. */
4673 static void gen_nabs(DisasContext *ctx)
4674 {
4675 int l1 = gen_new_label();
4676 int l2 = gen_new_label();
4677 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4678 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4679 tcg_gen_br(l2);
4680 gen_set_label(l1);
4681 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4682 gen_set_label(l2);
4683 if (unlikely(Rc(ctx->opcode) != 0))
4684 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4685 }
4686
4687 /* nabso - nabso. */
4688 static void gen_nabso(DisasContext *ctx)
4689 {
4690 int l1 = gen_new_label();
4691 int l2 = gen_new_label();
4692 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4693 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4694 tcg_gen_br(l2);
4695 gen_set_label(l1);
4696 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4697 gen_set_label(l2);
4698 /* nabs never overflows */
4699 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4700 if (unlikely(Rc(ctx->opcode) != 0))
4701 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4702 }
4703
4704 /* rlmi - rlmi. */
4705 static void gen_rlmi(DisasContext *ctx)
4706 {
4707 uint32_t mb = MB(ctx->opcode);
4708 uint32_t me = ME(ctx->opcode);
4709 TCGv t0 = tcg_temp_new();
4710 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4711 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4712 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4713 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4714 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4715 tcg_temp_free(t0);
4716 if (unlikely(Rc(ctx->opcode) != 0))
4717 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4718 }
4719
4720 /* rrib - rrib. */
4721 static void gen_rrib(DisasContext *ctx)
4722 {
4723 TCGv t0 = tcg_temp_new();
4724 TCGv t1 = tcg_temp_new();
4725 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4726 tcg_gen_movi_tl(t1, 0x80000000);
4727 tcg_gen_shr_tl(t1, t1, t0);
4728 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4729 tcg_gen_and_tl(t0, t0, t1);
4730 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4731 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4732 tcg_temp_free(t0);
4733 tcg_temp_free(t1);
4734 if (unlikely(Rc(ctx->opcode) != 0))
4735 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4736 }
4737
4738 /* sle - sle. */
4739 static void gen_sle(DisasContext *ctx)
4740 {
4741 TCGv t0 = tcg_temp_new();
4742 TCGv t1 = tcg_temp_new();
4743 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4744 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4745 tcg_gen_subfi_tl(t1, 32, t1);
4746 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4747 tcg_gen_or_tl(t1, t0, t1);
4748 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4749 gen_store_spr(SPR_MQ, t1);
4750 tcg_temp_free(t0);
4751 tcg_temp_free(t1);
4752 if (unlikely(Rc(ctx->opcode) != 0))
4753 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4754 }
4755
4756 /* sleq - sleq. */
4757 static void gen_sleq(DisasContext *ctx)
4758 {
4759 TCGv t0 = tcg_temp_new();
4760 TCGv t1 = tcg_temp_new();
4761 TCGv t2 = tcg_temp_new();
4762 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4763 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4764 tcg_gen_shl_tl(t2, t2, t0);
4765 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4766 gen_load_spr(t1, SPR_MQ);
4767 gen_store_spr(SPR_MQ, t0);
4768 tcg_gen_and_tl(t0, t0, t2);
4769 tcg_gen_andc_tl(t1, t1, t2);
4770 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4771 tcg_temp_free(t0);
4772 tcg_temp_free(t1);
4773 tcg_temp_free(t2);
4774 if (unlikely(Rc(ctx->opcode) != 0))
4775 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4776 }
4777
4778 /* sliq - sliq. */
4779 static void gen_sliq(DisasContext *ctx)
4780 {
4781 int sh = SH(ctx->opcode);
4782 TCGv t0 = tcg_temp_new();
4783 TCGv t1 = tcg_temp_new();
4784 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4785 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4786 tcg_gen_or_tl(t1, t0, t1);
4787 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4788 gen_store_spr(SPR_MQ, t1);
4789 tcg_temp_free(t0);
4790 tcg_temp_free(t1);
4791 if (unlikely(Rc(ctx->opcode) != 0))
4792 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4793 }
4794
4795 /* slliq - slliq. */
4796 static void gen_slliq(DisasContext *ctx)
4797 {
4798 int sh = SH(ctx->opcode);
4799 TCGv t0 = tcg_temp_new();
4800 TCGv t1 = tcg_temp_new();
4801 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4802 gen_load_spr(t1, SPR_MQ);
4803 gen_store_spr(SPR_MQ, t0);
4804 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4805 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4806 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4807 tcg_temp_free(t0);
4808 tcg_temp_free(t1);
4809 if (unlikely(Rc(ctx->opcode) != 0))
4810 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4811 }
4812
4813 /* sllq - sllq. */
4814 static void gen_sllq(DisasContext *ctx)
4815 {
4816 int l1 = gen_new_label();
4817 int l2 = gen_new_label();
4818 TCGv t0 = tcg_temp_local_new();
4819 TCGv t1 = tcg_temp_local_new();
4820 TCGv t2 = tcg_temp_local_new();
4821 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4822 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4823 tcg_gen_shl_tl(t1, t1, t2);
4824 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4825 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4826 gen_load_spr(t0, SPR_MQ);
4827 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4828 tcg_gen_br(l2);
4829 gen_set_label(l1);
4830 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4831 gen_load_spr(t2, SPR_MQ);
4832 tcg_gen_andc_tl(t1, t2, t1);
4833 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4834 gen_set_label(l2);
4835 tcg_temp_free(t0);
4836 tcg_temp_free(t1);
4837 tcg_temp_free(t2);
4838 if (unlikely(Rc(ctx->opcode) != 0))
4839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4840 }
4841
4842 /* slq - slq. */
4843 static void gen_slq(DisasContext *ctx)
4844 {
4845 int l1 = gen_new_label();
4846 TCGv t0 = tcg_temp_new();
4847 TCGv t1 = tcg_temp_new();
4848 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4849 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4850 tcg_gen_subfi_tl(t1, 32, t1);
4851 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4852 tcg_gen_or_tl(t1, t0, t1);
4853 gen_store_spr(SPR_MQ, t1);
4854 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4855 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4856 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4857 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4858 gen_set_label(l1);
4859 tcg_temp_free(t0);
4860 tcg_temp_free(t1);
4861 if (unlikely(Rc(ctx->opcode) != 0))
4862 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4863 }
4864
4865 /* sraiq - sraiq. */
4866 static void gen_sraiq(DisasContext *ctx)
4867 {
4868 int sh = SH(ctx->opcode);
4869 int l1 = gen_new_label();
4870 TCGv t0 = tcg_temp_new();
4871 TCGv t1 = tcg_temp_new();
4872 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4873 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4874 tcg_gen_or_tl(t0, t0, t1);
4875 gen_store_spr(SPR_MQ, t0);
4876 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4877 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4878 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4879 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4880 gen_set_label(l1);
4881 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4882 tcg_temp_free(t0);
4883 tcg_temp_free(t1);
4884 if (unlikely(Rc(ctx->opcode) != 0))
4885 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4886 }
4887
4888 /* sraq - sraq. */
4889 static void gen_sraq(DisasContext *ctx)
4890 {
4891 int l1 = gen_new_label();
4892 int l2 = gen_new_label();
4893 TCGv t0 = tcg_temp_new();
4894 TCGv t1 = tcg_temp_local_new();
4895 TCGv t2 = tcg_temp_local_new();
4896 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4897 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4898 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4899 tcg_gen_subfi_tl(t2, 32, t2);
4900 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4901 tcg_gen_or_tl(t0, t0, t2);
4902 gen_store_spr(SPR_MQ, t0);
4903 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4904 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4905 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4906 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4907 gen_set_label(l1);
4908 tcg_temp_free(t0);
4909 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4910 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4911 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4912 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4913 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4914 gen_set_label(l2);
4915 tcg_temp_free(t1);
4916 tcg_temp_free(t2);
4917 if (unlikely(Rc(ctx->opcode) != 0))
4918 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4919 }
4920
4921 /* sre - sre. */
4922 static void gen_sre(DisasContext *ctx)
4923 {
4924 TCGv t0 = tcg_temp_new();
4925 TCGv t1 = tcg_temp_new();
4926 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4927 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4928 tcg_gen_subfi_tl(t1, 32, t1);
4929 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4930 tcg_gen_or_tl(t1, t0, t1);
4931 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4932 gen_store_spr(SPR_MQ, t1);
4933 tcg_temp_free(t0);
4934 tcg_temp_free(t1);
4935 if (unlikely(Rc(ctx->opcode) != 0))
4936 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4937 }
4938
4939 /* srea - srea. */
4940 static void gen_srea(DisasContext *ctx)
4941 {
4942 TCGv t0 = tcg_temp_new();
4943 TCGv t1 = tcg_temp_new();
4944 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4945 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4946 gen_store_spr(SPR_MQ, t0);
4947 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4948 tcg_temp_free(t0);
4949 tcg_temp_free(t1);
4950 if (unlikely(Rc(ctx->opcode) != 0))
4951 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4952 }
4953
4954 /* sreq */
4955 static void gen_sreq(DisasContext *ctx)
4956 {
4957 TCGv t0 = tcg_temp_new();
4958 TCGv t1 = tcg_temp_new();
4959 TCGv t2 = tcg_temp_new();
4960 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4961 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4962 tcg_gen_shr_tl(t1, t1, t0);
4963 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4964 gen_load_spr(t2, SPR_MQ);
4965 gen_store_spr(SPR_MQ, t0);
4966 tcg_gen_and_tl(t0, t0, t1);
4967 tcg_gen_andc_tl(t2, t2, t1);
4968 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4969 tcg_temp_free(t0);
4970 tcg_temp_free(t1);
4971 tcg_temp_free(t2);
4972 if (unlikely(Rc(ctx->opcode) != 0))
4973 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4974 }
4975
4976 /* sriq */
4977 static void gen_sriq(DisasContext *ctx)
4978 {
4979 int sh = SH(ctx->opcode);
4980 TCGv t0 = tcg_temp_new();
4981 TCGv t1 = tcg_temp_new();
4982 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4983 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4984 tcg_gen_or_tl(t1, t0, t1);
4985 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4986 gen_store_spr(SPR_MQ, t1);
4987 tcg_temp_free(t0);
4988 tcg_temp_free(t1);
4989 if (unlikely(Rc(ctx->opcode) != 0))
4990 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4991 }
4992
4993 /* srliq */
4994 static void gen_srliq(DisasContext *ctx)
4995 {
4996 int sh = SH(ctx->opcode);
4997 TCGv t0 = tcg_temp_new();
4998 TCGv t1 = tcg_temp_new();
4999 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5000 gen_load_spr(t1, SPR_MQ);
5001 gen_store_spr(SPR_MQ, t0);
5002 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5003 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5004 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5005 tcg_temp_free(t0);
5006 tcg_temp_free(t1);
5007 if (unlikely(Rc(ctx->opcode) != 0))
5008 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5009 }
5010
5011 /* srlq */
5012 static void gen_srlq(DisasContext *ctx)
5013 {
5014 int l1 = gen_new_label();
5015 int l2 = gen_new_label();
5016 TCGv t0 = tcg_temp_local_new();
5017 TCGv t1 = tcg_temp_local_new();
5018 TCGv t2 = tcg_temp_local_new();
5019 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5020 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5021 tcg_gen_shr_tl(t2, t1, t2);
5022 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5023 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5024 gen_load_spr(t0, SPR_MQ);
5025 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5026 tcg_gen_br(l2);
5027 gen_set_label(l1);
5028 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5029 tcg_gen_and_tl(t0, t0, t2);
5030 gen_load_spr(t1, SPR_MQ);
5031 tcg_gen_andc_tl(t1, t1, t2);
5032 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5033 gen_set_label(l2);
5034 tcg_temp_free(t0);
5035 tcg_temp_free(t1);
5036 tcg_temp_free(t2);
5037 if (unlikely(Rc(ctx->opcode) != 0))
5038 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5039 }
5040
5041 /* srq */
5042 static void gen_srq(DisasContext *ctx)
5043 {
5044 int l1 = gen_new_label();
5045 TCGv t0 = tcg_temp_new();
5046 TCGv t1 = tcg_temp_new();
5047 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5048 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5049 tcg_gen_subfi_tl(t1, 32, t1);
5050 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5051 tcg_gen_or_tl(t1, t0, t1);
5052 gen_store_spr(SPR_MQ, t1);
5053 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5054 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5055 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5056 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5057 gen_set_label(l1);
5058 tcg_temp_free(t0);
5059 tcg_temp_free(t1);
5060 if (unlikely(Rc(ctx->opcode) != 0))
5061 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5062 }
5063
5064 /* PowerPC 602 specific instructions */
5065
5066 /* dsa */
5067 static void gen_dsa(DisasContext *ctx)
5068 {
5069 /* XXX: TODO */
5070 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5071 }
5072
5073 /* esa */
5074 static void gen_esa(DisasContext *ctx)
5075 {
5076 /* XXX: TODO */
5077 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5078 }
5079
5080 /* mfrom */
5081 static void gen_mfrom(DisasContext *ctx)
5082 {
5083 #if defined(CONFIG_USER_ONLY)
5084 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5085 #else
5086 if (unlikely(!ctx->mem_idx)) {
5087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5088 return;
5089 }
5090 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5091 #endif
5092 }
5093
5094 /* 602 - 603 - G2 TLB management */
5095
5096 /* tlbld */
5097 static void gen_tlbld_6xx(DisasContext *ctx)
5098 {
5099 #if defined(CONFIG_USER_ONLY)
5100 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5101 #else
5102 if (unlikely(!ctx->mem_idx)) {
5103 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5104 return;
5105 }
5106 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5107 #endif
5108 }
5109
5110 /* tlbli */
5111 static void gen_tlbli_6xx(DisasContext *ctx)
5112 {
5113 #if defined(CONFIG_USER_ONLY)
5114 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5115 #else
5116 if (unlikely(!ctx->mem_idx)) {
5117 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5118 return;
5119 }
5120 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5121 #endif
5122 }
5123
5124 /* 74xx TLB management */
5125
5126 /* tlbld */
5127 static void gen_tlbld_74xx(DisasContext *ctx)
5128 {
5129 #if defined(CONFIG_USER_ONLY)
5130 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5131 #else
5132 if (unlikely(!ctx->mem_idx)) {
5133 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5134 return;
5135 }
5136 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5137 #endif
5138 }
5139
5140 /* tlbli */
5141 static void gen_tlbli_74xx(DisasContext *ctx)
5142 {
5143 #if defined(CONFIG_USER_ONLY)
5144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5145 #else
5146 if (unlikely(!ctx->mem_idx)) {
5147 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5148 return;
5149 }
5150 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5151 #endif
5152 }
5153
5154 /* POWER instructions not in PowerPC 601 */
5155
5156 /* clf */
5157 static void gen_clf(DisasContext *ctx)
5158 {
5159 /* Cache line flush: implemented as no-op */
5160 }
5161
5162 /* cli */
5163 static void gen_cli(DisasContext *ctx)
5164 {
5165 /* Cache line invalidate: privileged and treated as no-op */
5166 #if defined(CONFIG_USER_ONLY)
5167 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5168 #else
5169 if (unlikely(!ctx->mem_idx)) {
5170 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5171 return;
5172 }
5173 #endif
5174 }
5175
5176 /* dclst */
5177 static void gen_dclst(DisasContext *ctx)
5178 {
5179 /* Data cache line store: treated as no-op */
5180 }
5181
5182 static void gen_mfsri(DisasContext *ctx)
5183 {
5184 #if defined(CONFIG_USER_ONLY)
5185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5186 #else
5187 int ra = rA(ctx->opcode);
5188 int rd = rD(ctx->opcode);
5189 TCGv t0;
5190 if (unlikely(!ctx->mem_idx)) {
5191 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5192 return;
5193 }
5194 t0 = tcg_temp_new();
5195 gen_addr_reg_index(ctx, t0);
5196 tcg_gen_shri_tl(t0, t0, 28);
5197 tcg_gen_andi_tl(t0, t0, 0xF);
5198 gen_helper_load_sr(cpu_gpr[rd], t0);
5199 tcg_temp_free(t0);
5200 if (ra != 0 && ra != rd)
5201 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5202 #endif
5203 }
5204
5205 static void gen_rac(DisasContext *ctx)
5206 {
5207 #if defined(CONFIG_USER_ONLY)
5208 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5209 #else
5210 TCGv t0;
5211 if (unlikely(!ctx->mem_idx)) {
5212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5213 return;
5214 }
5215 t0 = tcg_temp_new();
5216 gen_addr_reg_index(ctx, t0);
5217 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5218 tcg_temp_free(t0);
5219 #endif
5220 }
5221
5222 static void gen_rfsvc(DisasContext *ctx)
5223 {
5224 #if defined(CONFIG_USER_ONLY)
5225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5226 #else
5227 if (unlikely(!ctx->mem_idx)) {
5228 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5229 return;
5230 }
5231 gen_helper_rfsvc();
5232 gen_sync_exception(ctx);
5233 #endif
5234 }
5235
5236 /* svc is not implemented for now */
5237
5238 /* POWER2 specific instructions */
5239 /* Quad manipulation (load/store two floats at a time) */
5240
5241 /* lfq */
5242 static void gen_lfq(DisasContext *ctx)
5243 {
5244 int rd = rD(ctx->opcode);
5245 TCGv t0;
5246 gen_set_access_type(ctx, ACCESS_FLOAT);
5247 t0 = tcg_temp_new();
5248 gen_addr_imm_index(ctx, t0, 0);
5249 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5250 gen_addr_add(ctx, t0, t0, 8);
5251 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5252 tcg_temp_free(t0);
5253 }
5254
5255 /* lfqu */
5256 static void gen_lfqu(DisasContext *ctx)
5257 {
5258 int ra = rA(ctx->opcode);
5259 int rd = rD(ctx->opcode);
5260 TCGv t0, t1;
5261 gen_set_access_type(ctx, ACCESS_FLOAT);
5262 t0 = tcg_temp_new();
5263 t1 = tcg_temp_new();
5264 gen_addr_imm_index(ctx, t0, 0);
5265 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5266 gen_addr_add(ctx, t1, t0, 8);
5267 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5268 if (ra != 0)
5269 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5270 tcg_temp_free(t0);
5271 tcg_temp_free(t1);
5272 }
5273
5274 /* lfqux */
5275 static void gen_lfqux(DisasContext *ctx)
5276 {
5277 int ra = rA(ctx->opcode);
5278 int rd = rD(ctx->opcode);
5279 gen_set_access_type(ctx, ACCESS_FLOAT);
5280 TCGv t0, t1;
5281 t0 = tcg_temp_new();
5282 gen_addr_reg_index(ctx, t0);
5283 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5284 t1 = tcg_temp_new();
5285 gen_addr_add(ctx, t1, t0, 8);
5286 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5287 tcg_temp_free(t1);
5288 if (ra != 0)
5289 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5290 tcg_temp_free(t0);
5291 }
5292
5293 /* lfqx */
5294 static void gen_lfqx(DisasContext *ctx)
5295 {
5296 int rd = rD(ctx->opcode);
5297 TCGv t0;
5298 gen_set_access_type(ctx, ACCESS_FLOAT);
5299 t0 = tcg_temp_new();
5300 gen_addr_reg_index(ctx, t0);
5301 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5302 gen_addr_add(ctx, t0, t0, 8);
5303 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5304 tcg_temp_free(t0);
5305 }
5306
5307 /* stfq */
5308 static void gen_stfq(DisasContext *ctx)
5309 {
5310 int rd = rD(ctx->opcode);
5311 TCGv t0;
5312 gen_set_access_type(ctx, ACCESS_FLOAT);
5313 t0 = tcg_temp_new();
5314 gen_addr_imm_index(ctx, t0, 0);
5315 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5316 gen_addr_add(ctx, t0, t0, 8);
5317 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5318 tcg_temp_free(t0);
5319 }
5320
5321 /* stfqu */
5322 static void gen_stfqu(DisasContext *ctx)
5323 {
5324 int ra = rA(ctx->opcode);
5325 int rd = rD(ctx->opcode);
5326 TCGv t0, t1;
5327 gen_set_access_type(ctx, ACCESS_FLOAT);
5328 t0 = tcg_temp_new();
5329 gen_addr_imm_index(ctx, t0, 0);
5330 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5331 t1 = tcg_temp_new();
5332 gen_addr_add(ctx, t1, t0, 8);
5333 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5334 tcg_temp_free(t1);
5335 if (ra != 0)
5336 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5337 tcg_temp_free(t0);
5338 }
5339
5340 /* stfqux */
5341 static void gen_stfqux(DisasContext *ctx)
5342 {
5343 int ra = rA(ctx->opcode);
5344 int rd = rD(ctx->opcode);
5345 TCGv t0, t1;
5346 gen_set_access_type(ctx, ACCESS_FLOAT);
5347 t0 = tcg_temp_new();
5348 gen_addr_reg_index(ctx, t0);
5349 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5350 t1 = tcg_temp_new();
5351 gen_addr_add(ctx, t1, t0, 8);
5352 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5353 tcg_temp_free(t1);
5354 if (ra != 0)
5355 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5356 tcg_temp_free(t0);
5357 }
5358
5359 /* stfqx */
5360 static void gen_stfqx(DisasContext *ctx)
5361 {
5362 int rd = rD(ctx->opcode);
5363 TCGv t0;
5364 gen_set_access_type(ctx, ACCESS_FLOAT);
5365 t0 = tcg_temp_new();
5366 gen_addr_reg_index(ctx, t0);
5367 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5368 gen_addr_add(ctx, t0, t0, 8);
5369 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5370 tcg_temp_free(t0);
5371 }
5372
5373 /* BookE specific instructions */
5374
5375 /* XXX: not implemented on 440 ? */
5376 static void gen_mfapidi(DisasContext *ctx)
5377 {
5378 /* XXX: TODO */
5379 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5380 }
5381
5382 /* XXX: not implemented on 440 ? */
5383 static void gen_tlbiva(DisasContext *ctx)
5384 {
5385 #if defined(CONFIG_USER_ONLY)
5386 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5387 #else
5388 TCGv t0;
5389 if (unlikely(!ctx->mem_idx)) {
5390 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5391 return;
5392 }
5393 t0 = tcg_temp_new();
5394 gen_addr_reg_index(ctx, t0);
5395 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5396 tcg_temp_free(t0);
5397 #endif
5398 }
5399
5400 /* All 405 MAC instructions are translated here */
5401 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5402 int ra, int rb, int rt, int Rc)
5403 {
5404 TCGv t0, t1;
5405
5406 t0 = tcg_temp_local_new();
5407 t1 = tcg_temp_local_new();
5408
5409 switch (opc3 & 0x0D) {
5410 case 0x05:
5411 /* macchw - macchw. - macchwo - macchwo. */
5412 /* macchws - macchws. - macchwso - macchwso. */
5413 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5414 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5415 /* mulchw - mulchw. */
5416 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5417 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5418 tcg_gen_ext16s_tl(t1, t1);
5419 break;
5420 case 0x04:
5421 /* macchwu - macchwu. - macchwuo - macchwuo. */
5422 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5423 /* mulchwu - mulchwu. */
5424 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5425 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5426 tcg_gen_ext16u_tl(t1, t1);
5427 break;
5428 case 0x01:
5429 /* machhw - machhw. - machhwo - machhwo. */
5430 /* machhws - machhws. - machhwso - machhwso. */
5431 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5432 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5433 /* mulhhw - mulhhw. */
5434 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5435 tcg_gen_ext16s_tl(t0, t0);
5436 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5437 tcg_gen_ext16s_tl(t1, t1);
5438 break;
5439 case 0x00:
5440 /* machhwu - machhwu. - machhwuo - machhwuo. */
5441 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5442 /* mulhhwu - mulhhwu. */
5443 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5444 tcg_gen_ext16u_tl(t0, t0);
5445 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5446 tcg_gen_ext16u_tl(t1, t1);
5447 break;
5448 case 0x0D:
5449 /* maclhw - maclhw. - maclhwo - maclhwo. */
5450 /* maclhws - maclhws. - maclhwso - maclhwso. */
5451 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5452 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5453 /* mullhw - mullhw. */
5454 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5455 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5456 break;
5457 case 0x0C:
5458 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5459 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5460 /* mullhwu - mullhwu. */
5461 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5462 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5463 break;
5464 }
5465 if (opc2 & 0x04) {
5466 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5467 tcg_gen_mul_tl(t1, t0, t1);
5468 if (opc2 & 0x02) {
5469 /* nmultiply-and-accumulate (0x0E) */
5470 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5471 } else {
5472 /* multiply-and-accumulate (0x0C) */
5473 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5474 }
5475
5476 if (opc3 & 0x12) {
5477 /* Check overflow and/or saturate */
5478 int l1 = gen_new_label();
5479
5480 if (opc3 & 0x10) {
5481 /* Start with XER OV disabled, the most likely case */
5482 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5483 }
5484 if (opc3 & 0x01) {
5485 /* Signed */
5486 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5487 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5488 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5489 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5490 if (opc3 & 0x02) {
5491 /* Saturate */
5492 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5493 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5494 }
5495 } else {
5496 /* Unsigned */
5497 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5498 if (opc3 & 0x02) {
5499 /* Saturate */
5500 tcg_gen_movi_tl(t0, UINT32_MAX);
5501 }
5502 }
5503 if (opc3 & 0x10) {
5504 /* Check overflow */
5505 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5506 }
5507 gen_set_label(l1);
5508 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5509 }
5510 } else {
5511 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5512 }
5513 tcg_temp_free(t0);
5514 tcg_temp_free(t1);
5515 if (unlikely(Rc) != 0) {
5516 /* Update Rc0 */
5517 gen_set_Rc0(ctx, cpu_gpr[rt]);
5518 }
5519 }
5520
5521 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5522 static void glue(gen_, name)(DisasContext *ctx) \
5523 { \
5524 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5525 rD(ctx->opcode), Rc(ctx->opcode)); \
5526 }
5527
5528 /* macchw - macchw. */
5529 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5530 /* macchwo - macchwo. */
5531 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5532 /* macchws - macchws. */
5533 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5534 /* macchwso - macchwso. */
5535 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5536 /* macchwsu - macchwsu. */
5537 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5538 /* macchwsuo - macchwsuo. */
5539 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5540 /* macchwu - macchwu. */
5541 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5542 /* macchwuo - macchwuo. */
5543 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5544 /* machhw - machhw. */
5545 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5546 /* machhwo - machhwo. */
5547 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5548 /* machhws - machhws. */
5549 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5550 /* machhwso - machhwso. */
5551 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5552 /* machhwsu - machhwsu. */
5553 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5554 /* machhwsuo - machhwsuo. */
5555 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5556 /* machhwu - machhwu. */
5557 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5558 /* machhwuo - machhwuo. */
5559 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5560 /* maclhw - maclhw. */
5561 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5562 /* maclhwo - maclhwo. */
5563 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5564 /* maclhws - maclhws. */
5565 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5566 /* maclhwso - maclhwso. */
5567 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5568 /* maclhwu - maclhwu. */
5569 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5570 /* maclhwuo - maclhwuo. */
5571 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5572 /* maclhwsu - maclhwsu. */
5573 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5574 /* maclhwsuo - maclhwsuo. */
5575 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5576 /* nmacchw - nmacchw. */
5577 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5578 /* nmacchwo - nmacchwo. */
5579 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5580 /* nmacchws - nmacchws. */
5581 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5582 /* nmacchwso - nmacchwso. */
5583 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5584 /* nmachhw - nmachhw. */
5585 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5586 /* nmachhwo - nmachhwo. */
5587 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5588 /* nmachhws - nmachhws. */
5589 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5590 /* nmachhwso - nmachhwso. */
5591 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5592 /* nmaclhw - nmaclhw. */
5593 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5594 /* nmaclhwo - nmaclhwo. */
5595 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5596 /* nmaclhws - nmaclhws. */
5597 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5598 /* nmaclhwso - nmaclhwso. */
5599 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5600
5601 /* mulchw - mulchw. */
5602 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5603 /* mulchwu - mulchwu. */
5604 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5605 /* mulhhw - mulhhw. */
5606 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5607 /* mulhhwu - mulhhwu. */
5608 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5609 /* mullhw - mullhw. */
5610 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5611 /* mullhwu - mullhwu. */
5612 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5613
5614 /* mfdcr */
5615 static void gen_mfdcr(DisasContext *ctx)
5616 {
5617 #if defined(CONFIG_USER_ONLY)
5618 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5619 #else
5620 TCGv dcrn;
5621 if (unlikely(!ctx->mem_idx)) {
5622 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5623 return;
5624 }
5625 /* NIP cannot be restored if the memory exception comes from an helper */
5626 gen_update_nip(ctx, ctx->nip - 4);
5627 dcrn = tcg_const_tl(SPR(ctx->opcode));
5628 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5629 tcg_temp_free(dcrn);
5630 #endif
5631 }
5632
5633 /* mtdcr */
5634 static void gen_mtdcr(DisasContext *ctx)
5635 {
5636 #if defined(CONFIG_USER_ONLY)
5637 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5638 #else
5639 TCGv dcrn;
5640 if (unlikely(!ctx->mem_idx)) {
5641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5642 return;
5643 }
5644 /* NIP cannot be restored if the memory exception comes from an helper */
5645 gen_update_nip(ctx, ctx->nip - 4);
5646 dcrn = tcg_const_tl(SPR(ctx->opcode));
5647 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5648 tcg_temp_free(dcrn);
5649 #endif
5650 }
5651
5652 /* mfdcrx */
5653 /* XXX: not implemented on 440 ? */
5654 static void gen_mfdcrx(DisasContext *ctx)
5655 {
5656 #if defined(CONFIG_USER_ONLY)
5657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5658 #else
5659 if (unlikely(!ctx->mem_idx)) {
5660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5661 return;
5662 }
5663 /* NIP cannot be restored if the memory exception comes from an helper */
5664 gen_update_nip(ctx, ctx->nip - 4);
5665 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5666 /* Note: Rc update flag set leads to undefined state of Rc0 */
5667 #endif
5668 }
5669
5670 /* mtdcrx */
5671 /* XXX: not implemented on 440 ? */
5672 static void gen_mtdcrx(DisasContext *ctx)
5673 {
5674 #if defined(CONFIG_USER_ONLY)
5675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5676 #else
5677 if (unlikely(!ctx->mem_idx)) {
5678 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5679 return;
5680 }
5681 /* NIP cannot be restored if the memory exception comes from an helper */
5682 gen_update_nip(ctx, ctx->nip - 4);
5683 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5684 /* Note: Rc update flag set leads to undefined state of Rc0 */
5685 #endif
5686 }
5687
5688 /* mfdcrux (PPC 460) : user-mode access to DCR */
5689 static void gen_mfdcrux(DisasContext *ctx)
5690 {
5691 /* NIP cannot be restored if the memory exception comes from an helper */
5692 gen_update_nip(ctx, ctx->nip - 4);
5693 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5694 /* Note: Rc update flag set leads to undefined state of Rc0 */
5695 }
5696
5697 /* mtdcrux (PPC 460) : user-mode access to DCR */
5698 static void gen_mtdcrux(DisasContext *ctx)
5699 {
5700 /* NIP cannot be restored if the memory exception comes from an helper */
5701 gen_update_nip(ctx, ctx->nip - 4);
5702 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5703 /* Note: Rc update flag set leads to undefined state of Rc0 */
5704 }
5705
5706 /* dccci */
5707 static void gen_dccci(DisasContext *ctx)
5708 {
5709 #if defined(CONFIG_USER_ONLY)
5710 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5711 #else
5712 if (unlikely(!ctx->mem_idx)) {
5713 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5714 return;
5715 }
5716 /* interpreted as no-op */
5717 #endif
5718 }
5719
5720 /* dcread */
5721 static void gen_dcread(DisasContext *ctx)
5722 {
5723 #if defined(CONFIG_USER_ONLY)
5724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5725 #else
5726 TCGv EA, val;
5727 if (unlikely(!ctx->mem_idx)) {
5728 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5729 return;
5730 }
5731 gen_set_access_type(ctx, ACCESS_CACHE);
5732 EA = tcg_temp_new();
5733 gen_addr_reg_index(ctx, EA);
5734 val = tcg_temp_new();
5735 gen_qemu_ld32u(ctx, val, EA);
5736 tcg_temp_free(val);
5737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5738 tcg_temp_free(EA);
5739 #endif
5740 }
5741
5742 /* icbt */
5743 static void gen_icbt_40x(DisasContext *ctx)
5744 {
5745 /* interpreted as no-op */
5746 /* XXX: specification say this is treated as a load by the MMU
5747 * but does not generate any exception
5748 */
5749 }
5750
5751 /* iccci */
5752 static void gen_iccci(DisasContext *ctx)
5753 {
5754 #if defined(CONFIG_USER_ONLY)
5755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5756 #else
5757 if (unlikely(!ctx->mem_idx)) {
5758 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5759 return;
5760 }
5761 /* interpreted as no-op */
5762 #endif
5763 }
5764
5765 /* icread */
5766 static void gen_icread(DisasContext *ctx)
5767 {
5768 #if defined(CONFIG_USER_ONLY)
5769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5770 #else
5771 if (unlikely(!ctx->mem_idx)) {
5772 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5773 return;
5774 }
5775 /* interpreted as no-op */
5776 #endif
5777 }
5778
5779 /* rfci (mem_idx only) */
5780 static void gen_rfci_40x(DisasContext *ctx)
5781 {
5782 #if defined(CONFIG_USER_ONLY)
5783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5784 #else
5785 if (unlikely(!ctx->mem_idx)) {
5786 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5787 return;
5788 }
5789 /* Restore CPU state */
5790 gen_helper_40x_rfci();
5791 gen_sync_exception(ctx);
5792 #endif
5793 }
5794
5795 static void gen_rfci(DisasContext *ctx)
5796 {
5797 #if defined(CONFIG_USER_ONLY)
5798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5799 #else
5800 if (unlikely(!ctx->mem_idx)) {
5801 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5802 return;
5803 }
5804 /* Restore CPU state */
5805 gen_helper_rfci();
5806 gen_sync_exception(ctx);
5807 #endif
5808 }
5809
5810 /* BookE specific */
5811
5812 /* XXX: not implemented on 440 ? */
5813 static void gen_rfdi(DisasContext *ctx)
5814 {
5815 #if defined(CONFIG_USER_ONLY)
5816 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5817 #else
5818 if (unlikely(!ctx->mem_idx)) {
5819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5820 return;
5821 }
5822 /* Restore CPU state */
5823 gen_helper_rfdi();
5824 gen_sync_exception(ctx);
5825 #endif
5826 }
5827
5828 /* XXX: not implemented on 440 ? */
5829 static void gen_rfmci(DisasContext *ctx)
5830 {
5831 #if defined(CONFIG_USER_ONLY)
5832 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5833 #else
5834 if (unlikely(!ctx->mem_idx)) {
5835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5836 return;
5837 }
5838 /* Restore CPU state */
5839 gen_helper_rfmci();
5840 gen_sync_exception(ctx);
5841 #endif
5842 }
5843
5844 /* TLB management - PowerPC 405 implementation */
5845
5846 /* tlbre */
5847 static void gen_tlbre_40x(DisasContext *ctx)
5848 {
5849 #if defined(CONFIG_USER_ONLY)
5850 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5851 #else
5852 if (unlikely(!ctx->mem_idx)) {
5853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5854 return;
5855 }
5856 switch (rB(ctx->opcode)) {
5857 case 0:
5858 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5859 break;
5860 case 1:
5861 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5862 break;
5863 default:
5864 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5865 break;
5866 }
5867 #endif
5868 }
5869
5870 /* tlbsx - tlbsx. */
5871 static void gen_tlbsx_40x(DisasContext *ctx)
5872 {
5873 #if defined(CONFIG_USER_ONLY)
5874 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5875 #else
5876 TCGv t0;
5877 if (unlikely(!ctx->mem_idx)) {
5878 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5879 return;
5880 }
5881 t0 = tcg_temp_new();
5882 gen_addr_reg_index(ctx, t0);
5883 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5884 tcg_temp_free(t0);
5885 if (Rc(ctx->opcode)) {
5886 int l1 = gen_new_label();
5887 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5888 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5889 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5890 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5891 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5892 gen_set_label(l1);
5893 }
5894 #endif
5895 }
5896
5897 /* tlbwe */
5898 static void gen_tlbwe_40x(DisasContext *ctx)
5899 {
5900 #if defined(CONFIG_USER_ONLY)
5901 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5902 #else
5903 if (unlikely(!ctx->mem_idx)) {
5904 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5905 return;
5906 }
5907 switch (rB(ctx->opcode)) {
5908 case 0:
5909 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5910 break;
5911 case 1:
5912 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5913 break;
5914 default:
5915 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5916 break;
5917 }
5918 #endif
5919 }
5920
5921 /* TLB management - PowerPC 440 implementation */
5922
5923 /* tlbre */
5924 static void gen_tlbre_440(DisasContext *ctx)
5925 {
5926 #if defined(CONFIG_USER_ONLY)
5927 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5928 #else
5929 if (unlikely(!ctx->mem_idx)) {
5930 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5931 return;
5932 }
5933 switch (rB(ctx->opcode)) {
5934 case 0:
5935 case 1:
5936 case 2:
5937 {
5938 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5939 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], t0, cpu_gpr[rA(ctx->opcode)]);
5940 tcg_temp_free_i32(t0);
5941 }
5942 break;
5943 default:
5944 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5945 break;
5946 }
5947 #endif
5948 }
5949
5950 /* tlbsx - tlbsx. */
5951 static void gen_tlbsx_440(DisasContext *ctx)
5952 {
5953 #if defined(CONFIG_USER_ONLY)
5954 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5955 #else
5956 TCGv t0;
5957 if (unlikely(!ctx->mem_idx)) {
5958 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5959 return;
5960 }
5961 t0 = tcg_temp_new();
5962 gen_addr_reg_index(ctx, t0);
5963 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5964 tcg_temp_free(t0);
5965 if (Rc(ctx->opcode)) {
5966 int l1 = gen_new_label();
5967 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5968 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5969 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5970 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5971 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5972 gen_set_label(l1);
5973 }
5974 #endif
5975 }
5976
5977 /* tlbwe */
5978 static void gen_tlbwe_440(DisasContext *ctx)
5979 {
5980 #if defined(CONFIG_USER_ONLY)
5981 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5982 #else
5983 if (unlikely(!ctx->mem_idx)) {
5984 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5985 return;
5986 }
5987 switch (rB(ctx->opcode)) {
5988 case 0:
5989 case 1:
5990 case 2:
5991 {
5992 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5993 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5994 tcg_temp_free_i32(t0);
5995 }
5996 break;
5997 default:
5998 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5999 break;
6000 }
6001 #endif
6002 }
6003
6004 /* TLB management - PowerPC BookE 2.06 implementation */
6005
6006 /* tlbre */
6007 static void gen_tlbre_booke206(DisasContext *ctx)
6008 {
6009 #if defined(CONFIG_USER_ONLY)
6010 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6011 #else
6012 if (unlikely(!ctx->mem_idx)) {
6013 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6014 return;
6015 }
6016
6017 gen_helper_booke206_tlbre();
6018 #endif
6019 }
6020
6021 /* tlbsx - tlbsx. */
6022 static void gen_tlbsx_booke206(DisasContext *ctx)
6023 {
6024 #if defined(CONFIG_USER_ONLY)
6025 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6026 #else
6027 TCGv t0;
6028 if (unlikely(!ctx->mem_idx)) {
6029 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6030 return;
6031 }
6032
6033 if (rA(ctx->opcode)) {
6034 t0 = tcg_temp_new();
6035 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6036 } else {
6037 t0 = tcg_const_tl(0);
6038 }
6039
6040 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6041 gen_helper_booke206_tlbsx(t0);
6042 #endif
6043 }
6044
6045 /* tlbwe */
6046 static void gen_tlbwe_booke206(DisasContext *ctx)
6047 {
6048 #if defined(CONFIG_USER_ONLY)
6049 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6050 #else
6051 if (unlikely(!ctx->mem_idx)) {
6052 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6053 return;
6054 }
6055 gen_helper_booke206_tlbwe();
6056 #endif
6057 }
6058
6059 static void gen_tlbivax_booke206(DisasContext *ctx)
6060 {
6061 #if defined(CONFIG_USER_ONLY)
6062 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6063 #else
6064 TCGv t0;
6065 if (unlikely(!ctx->mem_idx)) {
6066 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6067 return;
6068 }
6069
6070 t0 = tcg_temp_new();
6071 gen_addr_reg_index(ctx, t0);
6072
6073 gen_helper_booke206_tlbivax(t0);
6074 #endif
6075 }
6076
6077
6078 /* wrtee */
6079 static void gen_wrtee(DisasContext *ctx)
6080 {
6081 #if defined(CONFIG_USER_ONLY)
6082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6083 #else
6084 TCGv t0;
6085 if (unlikely(!ctx->mem_idx)) {
6086 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6087 return;
6088 }
6089 t0 = tcg_temp_new();
6090 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6091 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6092 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6093 tcg_temp_free(t0);
6094 /* Stop translation to have a chance to raise an exception
6095 * if we just set msr_ee to 1
6096 */
6097 gen_stop_exception(ctx);
6098 #endif
6099 }
6100
6101 /* wrteei */
6102 static void gen_wrteei(DisasContext *ctx)
6103 {
6104 #if defined(CONFIG_USER_ONLY)
6105 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6106 #else
6107 if (unlikely(!ctx->mem_idx)) {
6108 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6109 return;
6110 }
6111 if (ctx->opcode & 0x00008000) {
6112 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6113 /* Stop translation to have a chance to raise an exception */
6114 gen_stop_exception(ctx);
6115 } else {
6116 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6117 }
6118 #endif
6119 }
6120
6121 /* PowerPC 440 specific instructions */
6122
6123 /* dlmzb */
6124 static void gen_dlmzb(DisasContext *ctx)
6125 {
6126 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6127 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6128 cpu_gpr[rB(ctx->opcode)], t0);
6129 tcg_temp_free_i32(t0);
6130 }
6131
6132 /* mbar replaces eieio on 440 */
6133 static void gen_mbar(DisasContext *ctx)
6134 {
6135 /* interpreted as no-op */
6136 }
6137
6138 /* msync replaces sync on 440 */
6139 static void gen_msync(DisasContext *ctx)
6140 {
6141 /* interpreted as no-op */
6142 }
6143
6144 /* icbt */
6145 static void gen_icbt_440(DisasContext *ctx)
6146 {
6147 /* interpreted as no-op */
6148 /* XXX: specification say this is treated as a load by the MMU
6149 * but does not generate any exception
6150 */
6151 }
6152
6153 /*** Altivec vector extension ***/
6154 /* Altivec registers moves */
6155
6156 static inline TCGv_ptr gen_avr_ptr(int reg)
6157 {
6158 TCGv_ptr r = tcg_temp_new_ptr();
6159 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6160 return r;
6161 }
6162
6163 #define GEN_VR_LDX(name, opc2, opc3) \
6164 static void glue(gen_, name)(DisasContext *ctx) \
6165 { \
6166 TCGv EA; \
6167 if (unlikely(!ctx->altivec_enabled)) { \
6168 gen_exception(ctx, POWERPC_EXCP_VPU); \
6169 return; \
6170 } \
6171 gen_set_access_type(ctx, ACCESS_INT); \
6172 EA = tcg_temp_new(); \
6173 gen_addr_reg_index(ctx, EA); \
6174 tcg_gen_andi_tl(EA, EA, ~0xf); \
6175 if (ctx->le_mode) { \
6176 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6177 tcg_gen_addi_tl(EA, EA, 8); \
6178 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6179 } else { \
6180 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6181 tcg_gen_addi_tl(EA, EA, 8); \
6182 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6183 } \
6184 tcg_temp_free(EA); \
6185 }
6186
6187 #define GEN_VR_STX(name, opc2, opc3) \
6188 static void gen_st##name(DisasContext *ctx) \
6189 { \
6190 TCGv EA; \
6191 if (unlikely(!ctx->altivec_enabled)) { \
6192 gen_exception(ctx, POWERPC_EXCP_VPU); \
6193 return; \
6194 } \
6195 gen_set_access_type(ctx, ACCESS_INT); \
6196 EA = tcg_temp_new(); \
6197 gen_addr_reg_index(ctx, EA); \
6198 tcg_gen_andi_tl(EA, EA, ~0xf); \
6199 if (ctx->le_mode) { \
6200 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6201 tcg_gen_addi_tl(EA, EA, 8); \
6202 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6203 } else { \
6204 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6205 tcg_gen_addi_tl(EA, EA, 8); \
6206 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6207 } \
6208 tcg_temp_free(EA); \
6209 }
6210
6211 #define GEN_VR_LVE(name, opc2, opc3) \
6212 static void gen_lve##name(DisasContext *ctx) \
6213 { \
6214 TCGv EA; \
6215 TCGv_ptr rs; \
6216 if (unlikely(!ctx->altivec_enabled)) { \
6217 gen_exception(ctx, POWERPC_EXCP_VPU); \
6218 return; \
6219 } \
6220 gen_set_access_type(ctx, ACCESS_INT); \
6221 EA = tcg_temp_new(); \
6222 gen_addr_reg_index(ctx, EA); \
6223 rs = gen_avr_ptr(rS(ctx->opcode)); \
6224 gen_helper_lve##name (rs, EA); \
6225 tcg_temp_free(EA); \
6226 tcg_temp_free_ptr(rs); \
6227 }
6228
6229 #define GEN_VR_STVE(name, opc2, opc3) \
6230 static void gen_stve##name(DisasContext *ctx) \
6231 { \
6232 TCGv EA; \
6233 TCGv_ptr rs; \
6234 if (unlikely(!ctx->altivec_enabled)) { \
6235 gen_exception(ctx, POWERPC_EXCP_VPU); \
6236 return; \
6237 } \
6238 gen_set_access_type(ctx, ACCESS_INT); \
6239 EA = tcg_temp_new(); \
6240 gen_addr_reg_index(ctx, EA); \
6241 rs = gen_avr_ptr(rS(ctx->opcode)); \
6242 gen_helper_stve##name (rs, EA); \
6243 tcg_temp_free(EA); \
6244 tcg_temp_free_ptr(rs); \
6245 }
6246
6247 GEN_VR_LDX(lvx, 0x07, 0x03);
6248 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6249 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6250
6251 GEN_VR_LVE(bx, 0x07, 0x00);
6252 GEN_VR_LVE(hx, 0x07, 0x01);
6253 GEN_VR_LVE(wx, 0x07, 0x02);
6254
6255 GEN_VR_STX(svx, 0x07, 0x07);
6256 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6257 GEN_VR_STX(svxl, 0x07, 0x0F);
6258
6259 GEN_VR_STVE(bx, 0x07, 0x04);
6260 GEN_VR_STVE(hx, 0x07, 0x05);
6261 GEN_VR_STVE(wx, 0x07, 0x06);
6262
6263 static void gen_lvsl(DisasContext *ctx)
6264 {
6265 TCGv_ptr rd;
6266 TCGv EA;
6267 if (unlikely(!ctx->altivec_enabled)) {
6268 gen_exception(ctx, POWERPC_EXCP_VPU);
6269 return;
6270 }
6271 EA = tcg_temp_new();
6272 gen_addr_reg_index(ctx, EA);
6273 rd = gen_avr_ptr(rD(ctx->opcode));
6274 gen_helper_lvsl(rd, EA);
6275 tcg_temp_free(EA);
6276 tcg_temp_free_ptr(rd);
6277 }
6278
6279 static void gen_lvsr(DisasContext *ctx)
6280 {
6281 TCGv_ptr rd;
6282 TCGv EA;
6283 if (unlikely(!ctx->altivec_enabled)) {
6284 gen_exception(ctx, POWERPC_EXCP_VPU);
6285 return;
6286 }
6287 EA = tcg_temp_new();
6288 gen_addr_reg_index(ctx, EA);
6289 rd = gen_avr_ptr(rD(ctx->opcode));
6290 gen_helper_lvsr(rd, EA);
6291 tcg_temp_free(EA);
6292 tcg_temp_free_ptr(rd);
6293 }
6294
6295 static void gen_mfvscr(DisasContext *ctx)
6296 {
6297 TCGv_i32 t;
6298 if (unlikely(!ctx->altivec_enabled)) {
6299 gen_exception(ctx, POWERPC_EXCP_VPU);
6300 return;
6301 }
6302 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6303 t = tcg_temp_new_i32();
6304 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6305 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6306 tcg_temp_free_i32(t);
6307 }
6308
6309 static void gen_mtvscr(DisasContext *ctx)
6310 {
6311 TCGv_ptr p;
6312 if (unlikely(!ctx->altivec_enabled)) {
6313 gen_exception(ctx, POWERPC_EXCP_VPU);
6314 return;
6315 }
6316 p = gen_avr_ptr(rD(ctx->opcode));
6317 gen_helper_mtvscr(p);
6318 tcg_temp_free_ptr(p);
6319 }
6320
6321 /* Logical operations */
6322 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6323 static void glue(gen_, name)(DisasContext *ctx) \
6324 { \
6325 if (unlikely(!ctx->altivec_enabled)) { \
6326 gen_exception(ctx, POWERPC_EXCP_VPU); \
6327 return; \
6328 } \
6329 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6330 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6331 }
6332
6333 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6334 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6335 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6336 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6337 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6338
6339 #define GEN_VXFORM(name, opc2, opc3) \
6340 static void glue(gen_, name)(DisasContext *ctx) \
6341 { \
6342 TCGv_ptr ra, rb, rd; \
6343 if (unlikely(!ctx->altivec_enabled)) { \
6344 gen_exception(ctx, POWERPC_EXCP_VPU); \
6345 return; \
6346 } \
6347 ra = gen_avr_ptr(rA(ctx->opcode)); \
6348 rb = gen_avr_ptr(rB(ctx->opcode)); \
6349 rd = gen_avr_ptr(rD(ctx->opcode)); \
6350 gen_helper_##name (rd, ra, rb); \
6351 tcg_temp_free_ptr(ra); \
6352 tcg_temp_free_ptr(rb); \
6353 tcg_temp_free_ptr(rd); \
6354 }
6355
6356 GEN_VXFORM(vaddubm, 0, 0);
6357 GEN_VXFORM(vadduhm, 0, 1);
6358 GEN_VXFORM(vadduwm, 0, 2);
6359 GEN_VXFORM(vsububm, 0, 16);
6360 GEN_VXFORM(vsubuhm, 0, 17);
6361 GEN_VXFORM(vsubuwm, 0, 18);
6362 GEN_VXFORM(vmaxub, 1, 0);
6363 GEN_VXFORM(vmaxuh, 1, 1);
6364 GEN_VXFORM(vmaxuw, 1, 2);
6365 GEN_VXFORM(vmaxsb, 1, 4);
6366 GEN_VXFORM(vmaxsh, 1, 5);
6367 GEN_VXFORM(vmaxsw, 1, 6);
6368 GEN_VXFORM(vminub, 1, 8);
6369 GEN_VXFORM(vminuh, 1, 9);
6370 GEN_VXFORM(vminuw, 1, 10);
6371 GEN_VXFORM(vminsb, 1, 12);
6372 GEN_VXFORM(vminsh, 1, 13);
6373 GEN_VXFORM(vminsw, 1, 14);
6374 GEN_VXFORM(vavgub, 1, 16);
6375 GEN_VXFORM(vavguh, 1, 17);
6376 GEN_VXFORM(vavguw, 1, 18);
6377 GEN_VXFORM(vavgsb, 1, 20);
6378 GEN_VXFORM(vavgsh, 1, 21);
6379 GEN_VXFORM(vavgsw, 1, 22);
6380 GEN_VXFORM(vmrghb, 6, 0);
6381 GEN_VXFORM(vmrghh, 6, 1);
6382 GEN_VXFORM(vmrghw, 6, 2);
6383 GEN_VXFORM(vmrglb, 6, 4);
6384 GEN_VXFORM(vmrglh, 6, 5);
6385 GEN_VXFORM(vmrglw, 6, 6);
6386 GEN_VXFORM(vmuloub, 4, 0);
6387 GEN_VXFORM(vmulouh, 4, 1);
6388 GEN_VXFORM(vmulosb, 4, 4);
6389 GEN_VXFORM(vmulosh, 4, 5);
6390 GEN_VXFORM(vmuleub, 4, 8);
6391 GEN_VXFORM(vmuleuh, 4, 9);
6392 GEN_VXFORM(vmulesb, 4, 12);
6393 GEN_VXFORM(vmulesh, 4, 13);
6394 GEN_VXFORM(vslb, 2, 4);
6395 GEN_VXFORM(vslh, 2, 5);
6396 GEN_VXFORM(vslw, 2, 6);
6397 GEN_VXFORM(vsrb, 2, 8);
6398 GEN_VXFORM(vsrh, 2, 9);
6399 GEN_VXFORM(vsrw, 2, 10);
6400 GEN_VXFORM(vsrab, 2, 12);
6401 GEN_VXFORM(vsrah, 2, 13);
6402 GEN_VXFORM(vsraw, 2, 14);
6403 GEN_VXFORM(vslo, 6, 16);
6404 GEN_VXFORM(vsro, 6, 17);
6405 GEN_VXFORM(vaddcuw, 0, 6);
6406 GEN_VXFORM(vsubcuw, 0, 22);
6407 GEN_VXFORM(vaddubs, 0, 8);
6408 GEN_VXFORM(vadduhs, 0, 9);
6409 GEN_VXFORM(vadduws, 0, 10);
6410 GEN_VXFORM(vaddsbs, 0, 12);
6411 GEN_VXFORM(vaddshs, 0, 13);
6412 GEN_VXFORM(vaddsws, 0, 14);
6413 GEN_VXFORM(vsububs, 0, 24);
6414 GEN_VXFORM(vsubuhs, 0, 25);
6415 GEN_VXFORM(vsubuws, 0, 26);
6416 GEN_VXFORM(vsubsbs, 0, 28);
6417 GEN_VXFORM(vsubshs, 0, 29);
6418 GEN_VXFORM(vsubsws, 0, 30);
6419 GEN_VXFORM(vrlb, 2, 0);
6420 GEN_VXFORM(vrlh, 2, 1);
6421 GEN_VXFORM(vrlw, 2, 2);
6422 GEN_VXFORM(vsl, 2, 7);
6423 GEN_VXFORM(vsr, 2, 11);
6424 GEN_VXFORM(vpkuhum, 7, 0);
6425 GEN_VXFORM(vpkuwum, 7, 1);
6426 GEN_VXFORM(vpkuhus, 7, 2);
6427 GEN_VXFORM(vpkuwus, 7, 3);
6428 GEN_VXFORM(vpkshus, 7, 4);
6429 GEN_VXFORM(vpkswus, 7, 5);
6430 GEN_VXFORM(vpkshss, 7, 6);
6431 GEN_VXFORM(vpkswss, 7, 7);
6432 GEN_VXFORM(vpkpx, 7, 12);
6433 GEN_VXFORM(vsum4ubs, 4, 24);
6434 GEN_VXFORM(vsum4sbs, 4, 28);
6435 GEN_VXFORM(vsum4shs, 4, 25);
6436 GEN_VXFORM(vsum2sws, 4, 26);
6437 GEN_VXFORM(vsumsws, 4, 30);
6438 GEN_VXFORM(vaddfp, 5, 0);
6439 GEN_VXFORM(vsubfp, 5, 1);
6440 GEN_VXFORM(vmaxfp, 5, 16);
6441 GEN_VXFORM(vminfp, 5, 17);
6442
6443 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6444 static void glue(gen_, name)(DisasContext *ctx) \
6445 { \
6446 TCGv_ptr ra, rb, rd; \
6447 if (unlikely(!ctx->altivec_enabled)) { \
6448 gen_exception(ctx, POWERPC_EXCP_VPU); \
6449 return; \
6450 } \
6451 ra = gen_avr_ptr(rA(ctx->opcode)); \
6452 rb = gen_avr_ptr(rB(ctx->opcode)); \
6453 rd = gen_avr_ptr(rD(ctx->opcode)); \
6454 gen_helper_##opname (rd, ra, rb); \
6455 tcg_temp_free_ptr(ra); \
6456 tcg_temp_free_ptr(rb); \
6457 tcg_temp_free_ptr(rd); \
6458 }
6459
6460 #define GEN_VXRFORM(name, opc2, opc3) \
6461 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6462 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6463
6464 GEN_VXRFORM(vcmpequb, 3, 0)
6465 GEN_VXRFORM(vcmpequh, 3, 1)
6466 GEN_VXRFORM(vcmpequw, 3, 2)
6467 GEN_VXRFORM(vcmpgtsb, 3, 12)
6468 GEN_VXRFORM(vcmpgtsh, 3, 13)
6469 GEN_VXRFORM(vcmpgtsw, 3, 14)
6470 GEN_VXRFORM(vcmpgtub, 3, 8)
6471 GEN_VXRFORM(vcmpgtuh, 3, 9)
6472 GEN_VXRFORM(vcmpgtuw, 3, 10)
6473 GEN_VXRFORM(vcmpeqfp, 3, 3)
6474 GEN_VXRFORM(vcmpgefp, 3, 7)
6475 GEN_VXRFORM(vcmpgtfp, 3, 11)
6476 GEN_VXRFORM(vcmpbfp, 3, 15)
6477
6478 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6479 static void glue(gen_, name)(DisasContext *ctx) \
6480 { \
6481 TCGv_ptr rd; \
6482 TCGv_i32 simm; \
6483 if (unlikely(!ctx->altivec_enabled)) { \
6484 gen_exception(ctx, POWERPC_EXCP_VPU); \
6485 return; \
6486 } \
6487 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6488 rd = gen_avr_ptr(rD(ctx->opcode)); \
6489 gen_helper_##name (rd, simm); \
6490 tcg_temp_free_i32(simm); \
6491 tcg_temp_free_ptr(rd); \
6492 }
6493
6494 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6495 GEN_VXFORM_SIMM(vspltish, 6, 13);
6496 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6497
6498 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6499 static void glue(gen_, name)(DisasContext *ctx) \
6500 { \
6501 TCGv_ptr rb, rd; \
6502 if (unlikely(!ctx->altivec_enabled)) { \
6503 gen_exception(ctx, POWERPC_EXCP_VPU); \
6504 return; \
6505 } \
6506 rb = gen_avr_ptr(rB(ctx->opcode)); \
6507 rd = gen_avr_ptr(rD(ctx->opcode)); \
6508 gen_helper_##name (rd, rb); \
6509 tcg_temp_free_ptr(rb); \
6510 tcg_temp_free_ptr(rd); \
6511 }
6512
6513 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6514 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6515 GEN_VXFORM_NOA(vupklsb, 7, 10);
6516 GEN_VXFORM_NOA(vupklsh, 7, 11);
6517 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6518 GEN_VXFORM_NOA(vupklpx, 7, 15);
6519 GEN_VXFORM_NOA(vrefp, 5, 4);
6520 GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
6521 GEN_VXFORM_NOA(vexptefp, 5, 6);
6522 GEN_VXFORM_NOA(vlogefp, 5, 7);
6523 GEN_VXFORM_NOA(vrfim, 5, 8);
6524 GEN_VXFORM_NOA(vrfin, 5, 9);
6525 GEN_VXFORM_NOA(vrfip, 5, 10);
6526 GEN_VXFORM_NOA(vrfiz, 5, 11);
6527
6528 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6529 static void glue(gen_, name)(DisasContext *ctx) \
6530 { \
6531 TCGv_ptr rd; \
6532 TCGv_i32 simm; \
6533 if (unlikely(!ctx->altivec_enabled)) { \
6534 gen_exception(ctx, POWERPC_EXCP_VPU); \
6535 return; \
6536 } \
6537 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6538 rd = gen_avr_ptr(rD(ctx->opcode)); \
6539 gen_helper_##name (rd, simm); \
6540 tcg_temp_free_i32(simm); \
6541 tcg_temp_free_ptr(rd); \
6542 }
6543
6544 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6545 static void glue(gen_, name)(DisasContext *ctx) \
6546 { \
6547 TCGv_ptr rb, rd; \
6548 TCGv_i32 uimm; \
6549 if (unlikely(!ctx->altivec_enabled)) { \
6550 gen_exception(ctx, POWERPC_EXCP_VPU); \
6551 return; \
6552 } \
6553 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6554 rb = gen_avr_ptr(rB(ctx->opcode)); \
6555 rd = gen_avr_ptr(rD(ctx->opcode)); \
6556 gen_helper_##name (rd, rb, uimm); \
6557 tcg_temp_free_i32(uimm); \
6558 tcg_temp_free_ptr(rb); \
6559 tcg_temp_free_ptr(rd); \
6560 }
6561
6562 GEN_VXFORM_UIMM(vspltb, 6, 8);
6563 GEN_VXFORM_UIMM(vsplth, 6, 9);
6564 GEN_VXFORM_UIMM(vspltw, 6, 10);
6565 GEN_VXFORM_UIMM(vcfux, 5, 12);
6566 GEN_VXFORM_UIMM(vcfsx, 5, 13);
6567 GEN_VXFORM_UIMM(vctuxs, 5, 14);
6568 GEN_VXFORM_UIMM(vctsxs, 5, 15);
6569
6570 static void gen_vsldoi(DisasContext *ctx)
6571 {
6572 TCGv_ptr ra, rb, rd;
6573 TCGv_i32 sh;
6574 if (unlikely(!ctx->altivec_enabled)) {
6575 gen_exception(ctx, POWERPC_EXCP_VPU);
6576 return;
6577 }
6578 ra = gen_avr_ptr(rA(ctx->opcode));
6579 rb = gen_avr_ptr(rB(ctx->opcode));
6580 rd = gen_avr_ptr(rD(ctx->opcode));
6581 sh = tcg_const_i32(VSH(ctx->opcode));
6582 gen_helper_vsldoi (rd, ra, rb, sh);
6583 tcg_temp_free_ptr(ra);
6584 tcg_temp_free_ptr(rb);
6585 tcg_temp_free_ptr(rd);
6586 tcg_temp_free_i32(sh);
6587 }
6588
6589 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6590 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6591 { \
6592 TCGv_ptr ra, rb, rc, rd; \
6593 if (unlikely(!ctx->altivec_enabled)) { \
6594 gen_exception(ctx, POWERPC_EXCP_VPU); \
6595 return; \
6596 } \
6597 ra = gen_avr_ptr(rA(ctx->opcode)); \
6598 rb = gen_avr_ptr(rB(ctx->opcode)); \
6599 rc = gen_avr_ptr(rC(ctx->opcode)); \
6600 rd = gen_avr_ptr(rD(ctx->opcode)); \
6601 if (Rc(ctx->opcode)) { \
6602 gen_helper_##name1 (rd, ra, rb, rc); \
6603 } else { \
6604 gen_helper_##name0 (rd, ra, rb, rc); \
6605 } \
6606 tcg_temp_free_ptr(ra); \
6607 tcg_temp_free_ptr(rb); \
6608 tcg_temp_free_ptr(rc); \
6609 tcg_temp_free_ptr(rd); \
6610 }
6611
6612 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6613
6614 static void gen_vmladduhm(DisasContext *ctx)
6615 {
6616 TCGv_ptr ra, rb, rc, rd;
6617 if (unlikely(!ctx->altivec_enabled)) {
6618 gen_exception(ctx, POWERPC_EXCP_VPU);
6619 return;
6620 }
6621 ra = gen_avr_ptr(rA(ctx->opcode));
6622 rb = gen_avr_ptr(rB(ctx->opcode));
6623 rc = gen_avr_ptr(rC(ctx->opcode));
6624 rd = gen_avr_ptr(rD(ctx->opcode));
6625 gen_helper_vmladduhm(rd, ra, rb, rc);
6626 tcg_temp_free_ptr(ra);
6627 tcg_temp_free_ptr(rb);
6628 tcg_temp_free_ptr(rc);
6629 tcg_temp_free_ptr(rd);
6630 }
6631
6632 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6633 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6634 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6635 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6636 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6637
6638 /*** SPE extension ***/
6639 /* Register moves */
6640
6641
6642 static inline void gen_evmra(DisasContext *ctx)
6643 {
6644
6645 if (unlikely(!ctx->spe_enabled)) {
6646 gen_exception(ctx, POWERPC_EXCP_SPEU);
6647 return;
6648 }
6649
6650 #if defined(TARGET_PPC64)
6651 /* rD := rA */
6652 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6653
6654 /* spe_acc := rA */
6655 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6656 cpu_env,
6657 offsetof(CPUState, spe_acc));
6658 #else
6659 TCGv_i64 tmp = tcg_temp_new_i64();
6660
6661 /* tmp := rA_lo + rA_hi << 32 */
6662 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6663
6664 /* spe_acc := tmp */
6665 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
6666 tcg_temp_free_i64(tmp);
6667
6668 /* rD := rA */
6669 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6670 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6671 #endif
6672 }
6673
6674 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6675 {
6676 #if defined(TARGET_PPC64)
6677 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6678 #else
6679 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6680 #endif
6681 }
6682
6683 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6684 {
6685 #if defined(TARGET_PPC64)
6686 tcg_gen_mov_i64(cpu_gpr[reg], t);
6687 #else
6688 TCGv_i64 tmp = tcg_temp_new_i64();
6689 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6690 tcg_gen_shri_i64(tmp, t, 32);
6691 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6692 tcg_temp_free_i64(tmp);
6693 #endif
6694 }
6695
6696 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6697 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6698 { \
6699 if (Rc(ctx->opcode)) \
6700 gen_##name1(ctx); \
6701 else \
6702 gen_##name0(ctx); \
6703 }
6704
6705 /* Handler for undefined SPE opcodes */
6706 static inline void gen_speundef(DisasContext *ctx)
6707 {
6708 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6709 }
6710
6711 /* SPE logic */
6712 #if defined(TARGET_PPC64)
6713 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6714 static inline void gen_##name(DisasContext *ctx) \
6715 { \
6716 if (unlikely(!ctx->spe_enabled)) { \
6717 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6718 return; \
6719 } \
6720 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6721 cpu_gpr[rB(ctx->opcode)]); \
6722 }
6723 #else
6724 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6725 static inline void gen_##name(DisasContext *ctx) \
6726 { \
6727 if (unlikely(!ctx->spe_enabled)) { \
6728 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6729 return; \
6730 } \
6731 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6732 cpu_gpr[rB(ctx->opcode)]); \
6733 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6734 cpu_gprh[rB(ctx->opcode)]); \
6735 }
6736 #endif
6737
6738 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6739 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6740 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6741 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6742 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6743 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6744 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6745 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6746
6747 /* SPE logic immediate */
6748 #if defined(TARGET_PPC64)
6749 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6750 static inline void gen_##name(DisasContext *ctx) \
6751 { \
6752 if (unlikely(!ctx->spe_enabled)) { \
6753 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6754 return; \
6755 } \
6756 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6757 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6758 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6759 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6760 tcg_opi(t0, t0, rB(ctx->opcode)); \
6761 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6762 tcg_gen_trunc_i64_i32(t1, t2); \
6763 tcg_temp_free_i64(t2); \
6764 tcg_opi(t1, t1, rB(ctx->opcode)); \
6765 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6766 tcg_temp_free_i32(t0); \
6767 tcg_temp_free_i32(t1); \
6768 }
6769 #else
6770 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6771 static inline void gen_##name(DisasContext *ctx) \
6772 { \
6773 if (unlikely(!ctx->spe_enabled)) { \
6774 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6775 return; \
6776 } \
6777 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6778 rB(ctx->opcode)); \
6779 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6780 rB(ctx->opcode)); \
6781 }
6782 #endif
6783 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6784 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6785 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6786 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6787
6788 /* SPE arithmetic */
6789 #if defined(TARGET_PPC64)
6790 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6791 static inline void gen_##name(DisasContext *ctx) \
6792 { \
6793 if (unlikely(!ctx->spe_enabled)) { \
6794 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6795 return; \
6796 } \
6797 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6798 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6799 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6800 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6801 tcg_op(t0, t0); \
6802 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6803 tcg_gen_trunc_i64_i32(t1, t2); \
6804 tcg_temp_free_i64(t2); \
6805 tcg_op(t1, t1); \
6806 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6807 tcg_temp_free_i32(t0); \
6808 tcg_temp_free_i32(t1); \
6809 }
6810 #else
6811 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6812 static inline void gen_##name(DisasContext *ctx) \
6813 { \
6814 if (unlikely(!ctx->spe_enabled)) { \
6815 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6816 return; \
6817 } \
6818 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6819 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6820 }
6821 #endif
6822
6823 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6824 {
6825 int l1 = gen_new_label();
6826 int l2 = gen_new_label();
6827
6828 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6829 tcg_gen_neg_i32(ret, arg1);
6830 tcg_gen_br(l2);
6831 gen_set_label(l1);
6832 tcg_gen_mov_i32(ret, arg1);
6833 gen_set_label(l2);
6834 }
6835 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6836 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6837 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6838 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6839 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6840 {
6841 tcg_gen_addi_i32(ret, arg1, 0x8000);
6842 tcg_gen_ext16u_i32(ret, ret);
6843 }
6844 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6845 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6846 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6847
6848 #if defined(TARGET_PPC64)
6849 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6850 static inline void gen_##name(DisasContext *ctx) \
6851 { \
6852 if (unlikely(!ctx->spe_enabled)) { \
6853 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6854 return; \
6855 } \
6856 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6857 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6858 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6859 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6860 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6861 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6862 tcg_op(t0, t0, t2); \
6863 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6864 tcg_gen_trunc_i64_i32(t1, t3); \
6865 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6866 tcg_gen_trunc_i64_i32(t2, t3); \
6867 tcg_temp_free_i64(t3); \
6868 tcg_op(t1, t1, t2); \
6869 tcg_temp_free_i32(t2); \
6870 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6871 tcg_temp_free_i32(t0); \
6872 tcg_temp_free_i32(t1); \
6873 }
6874 #else
6875 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6876 static inline void gen_##name(DisasContext *ctx) \
6877 { \
6878 if (unlikely(!ctx->spe_enabled)) { \
6879 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6880 return; \
6881 } \
6882 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6883 cpu_gpr[rB(ctx->opcode)]); \
6884 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6885 cpu_gprh[rB(ctx->opcode)]); \
6886 }
6887 #endif
6888
6889 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6890 {
6891 TCGv_i32 t0;
6892 int l1, l2;
6893
6894 l1 = gen_new_label();
6895 l2 = gen_new_label();
6896 t0 = tcg_temp_local_new_i32();
6897 /* No error here: 6 bits are used */
6898 tcg_gen_andi_i32(t0, arg2, 0x3F);
6899 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6900 tcg_gen_shr_i32(ret, arg1, t0);
6901 tcg_gen_br(l2);
6902 gen_set_label(l1);
6903 tcg_gen_movi_i32(ret, 0);
6904 gen_set_label(l2);
6905 tcg_temp_free_i32(t0);
6906 }
6907 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6908 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6909 {
6910 TCGv_i32 t0;
6911 int l1, l2;
6912
6913 l1 = gen_new_label();
6914 l2 = gen_new_label();
6915 t0 = tcg_temp_local_new_i32();
6916 /* No error here: 6 bits are used */
6917 tcg_gen_andi_i32(t0, arg2, 0x3F);
6918 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6919 tcg_gen_sar_i32(ret, arg1, t0);
6920 tcg_gen_br(l2);
6921 gen_set_label(l1);
6922 tcg_gen_movi_i32(ret, 0);
6923 gen_set_label(l2);
6924 tcg_temp_free_i32(t0);
6925 }
6926 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6927 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6928 {
6929 TCGv_i32 t0;
6930 int l1, l2;
6931
6932 l1 = gen_new_label();
6933 l2 = gen_new_label();
6934 t0 = tcg_temp_local_new_i32();
6935 /* No error here: 6 bits are used */
6936 tcg_gen_andi_i32(t0, arg2, 0x3F);
6937 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6938 tcg_gen_shl_i32(ret, arg1, t0);
6939 tcg_gen_br(l2);
6940 gen_set_label(l1);
6941 tcg_gen_movi_i32(ret, 0);
6942 gen_set_label(l2);
6943 tcg_temp_free_i32(t0);
6944 }
6945 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6946 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6947 {
6948 TCGv_i32 t0 = tcg_temp_new_i32();
6949 tcg_gen_andi_i32(t0, arg2, 0x1F);
6950 tcg_gen_rotl_i32(ret, arg1, t0);
6951 tcg_temp_free_i32(t0);
6952 }
6953 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6954 static inline void gen_evmergehi(DisasContext *ctx)
6955 {
6956 if (unlikely(!ctx->spe_enabled)) {
6957 gen_exception(ctx, POWERPC_EXCP_SPEU);
6958 return;
6959 }
6960 #if defined(TARGET_PPC64)
6961 TCGv t0 = tcg_temp_new();
6962 TCGv t1 = tcg_temp_new();
6963 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6964 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6965 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6966 tcg_temp_free(t0);
6967 tcg_temp_free(t1);
6968 #else
6969 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6970 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6971 #endif
6972 }
6973 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6974 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6975 {
6976 tcg_gen_sub_i32(ret, arg2, arg1);
6977 }
6978 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6979
6980 /* SPE arithmetic immediate */
6981 #if defined(TARGET_PPC64)
6982 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6983 static inline void gen_##name(DisasContext *ctx) \
6984 { \
6985 if (unlikely(!ctx->spe_enabled)) { \
6986 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6987 return; \
6988 } \
6989 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6990 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6991 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6992 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6993 tcg_op(t0, t0, rA(ctx->opcode)); \
6994 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6995 tcg_gen_trunc_i64_i32(t1, t2); \
6996 tcg_temp_free_i64(t2); \
6997 tcg_op(t1, t1, rA(ctx->opcode)); \
6998 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6999 tcg_temp_free_i32(t0); \
7000 tcg_temp_free_i32(t1); \
7001 }
7002 #else
7003 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7004 static inline void gen_##name(DisasContext *ctx) \
7005 { \
7006 if (unlikely(!ctx->spe_enabled)) { \
7007 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7008 return; \
7009 } \
7010 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7011 rA(ctx->opcode)); \
7012 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7013 rA(ctx->opcode)); \
7014 }
7015 #endif
7016 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7017 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7018
7019 /* SPE comparison */
7020 #if defined(TARGET_PPC64)
7021 #define GEN_SPEOP_COMP(name, tcg_cond) \
7022 static inline void gen_##name(DisasContext *ctx) \
7023 { \
7024 if (unlikely(!ctx->spe_enabled)) { \
7025 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7026 return; \
7027 } \
7028 int l1 = gen_new_label(); \
7029 int l2 = gen_new_label(); \
7030 int l3 = gen_new_label(); \
7031 int l4 = gen_new_label(); \
7032 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7033 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7034 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7035 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7036 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7037 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7038 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7039 tcg_gen_br(l2); \
7040 gen_set_label(l1); \
7041 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7042 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7043 gen_set_label(l2); \
7044 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7045 tcg_gen_trunc_i64_i32(t0, t2); \
7046 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7047 tcg_gen_trunc_i64_i32(t1, t2); \
7048 tcg_temp_free_i64(t2); \
7049 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7050 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7051 ~(CRF_CH | CRF_CH_AND_CL)); \
7052 tcg_gen_br(l4); \
7053 gen_set_label(l3); \
7054 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7055 CRF_CH | CRF_CH_OR_CL); \
7056 gen_set_label(l4); \
7057 tcg_temp_free_i32(t0); \
7058 tcg_temp_free_i32(t1); \
7059 }
7060 #else
7061 #define GEN_SPEOP_COMP(name, tcg_cond) \
7062 static inline void gen_##name(DisasContext *ctx) \
7063 { \
7064 if (unlikely(!ctx->spe_enabled)) { \
7065 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7066 return; \
7067 } \
7068 int l1 = gen_new_label(); \
7069 int l2 = gen_new_label(); \
7070 int l3 = gen_new_label(); \
7071 int l4 = gen_new_label(); \
7072 \
7073 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7074 cpu_gpr[rB(ctx->opcode)], l1); \
7075 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7076 tcg_gen_br(l2); \
7077 gen_set_label(l1); \
7078 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7079 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7080 gen_set_label(l2); \
7081 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7082 cpu_gprh[rB(ctx->opcode)], l3); \
7083 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7084 ~(CRF_CH | CRF_CH_AND_CL)); \
7085 tcg_gen_br(l4); \
7086 gen_set_label(l3); \
7087 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7088 CRF_CH | CRF_CH_OR_CL); \
7089 gen_set_label(l4); \
7090 }
7091 #endif
7092 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7093 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7094 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7095 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7096 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7097
7098 /* SPE misc */
7099 static inline void gen_brinc(DisasContext *ctx)
7100 {
7101 /* Note: brinc is usable even if SPE is disabled */
7102 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7103 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7104 }
7105 static inline void gen_evmergelo(DisasContext *ctx)
7106 {
7107 if (unlikely(!ctx->spe_enabled)) {
7108 gen_exception(ctx, POWERPC_EXCP_SPEU);
7109 return;
7110 }
7111 #if defined(TARGET_PPC64)
7112 TCGv t0 = tcg_temp_new();
7113 TCGv t1 = tcg_temp_new();
7114 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7115 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7116 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7117 tcg_temp_free(t0);
7118 tcg_temp_free(t1);
7119 #else
7120 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7121 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7122 #endif
7123 }
7124 static inline void gen_evmergehilo(DisasContext *ctx)
7125 {
7126 if (unlikely(!ctx->spe_enabled)) {
7127 gen_exception(ctx, POWERPC_EXCP_SPEU);
7128 return;
7129 }
7130 #if defined(TARGET_PPC64)
7131 TCGv t0 = tcg_temp_new();
7132 TCGv t1 = tcg_temp_new();
7133 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7134 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7135 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7136 tcg_temp_free(t0);
7137 tcg_temp_free(t1);
7138 #else
7139 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7140 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7141 #endif
7142 }
7143 static inline void gen_evmergelohi(DisasContext *ctx)
7144 {
7145 if (unlikely(!ctx->spe_enabled)) {
7146 gen_exception(ctx, POWERPC_EXCP_SPEU);
7147 return;
7148 }
7149 #if defined(TARGET_PPC64)
7150 TCGv t0 = tcg_temp_new();
7151 TCGv t1 = tcg_temp_new();
7152 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7153 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7154 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7155 tcg_temp_free(t0);
7156 tcg_temp_free(t1);
7157 #else
7158 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7159 TCGv_i32 tmp = tcg_temp_new_i32();
7160 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7161 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7162 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7163 tcg_temp_free_i32(tmp);
7164 } else {
7165 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7166 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7167 }
7168 #endif
7169 }
7170 static inline void gen_evsplati(DisasContext *ctx)
7171 {
7172 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7173
7174 #if defined(TARGET_PPC64)
7175 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7176 #else
7177 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7178 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7179 #endif
7180 }
7181 static inline void gen_evsplatfi(DisasContext *ctx)
7182 {
7183 uint64_t imm = rA(ctx->opcode) << 27;
7184
7185 #if defined(TARGET_PPC64)
7186 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7187 #else
7188 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7189 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7190 #endif
7191 }
7192
7193 static inline void gen_evsel(DisasContext *ctx)
7194 {
7195 int l1 = gen_new_label();
7196 int l2 = gen_new_label();
7197 int l3 = gen_new_label();
7198 int l4 = gen_new_label();
7199 TCGv_i32 t0 = tcg_temp_local_new_i32();
7200 #if defined(TARGET_PPC64)
7201 TCGv t1 = tcg_temp_local_new();
7202 TCGv t2 = tcg_temp_local_new();
7203 #endif
7204 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7205 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7206 #if defined(TARGET_PPC64)
7207 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7208 #else
7209 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7210 #endif
7211 tcg_gen_br(l2);
7212 gen_set_label(l1);
7213 #if defined(TARGET_PPC64)
7214 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7215 #else
7216 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7217 #endif
7218 gen_set_label(l2);
7219 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7220 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7221 #if defined(TARGET_PPC64)
7222 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7223 #else
7224 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7225 #endif
7226 tcg_gen_br(l4);
7227 gen_set_label(l3);
7228 #if defined(TARGET_PPC64)
7229 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7230 #else
7231 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7232 #endif
7233 gen_set_label(l4);
7234 tcg_temp_free_i32(t0);
7235 #if defined(TARGET_PPC64)
7236 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7237 tcg_temp_free(t1);
7238 tcg_temp_free(t2);
7239 #endif
7240 }
7241
7242 static void gen_evsel0(DisasContext *ctx)
7243 {
7244 gen_evsel(ctx);
7245 }
7246
7247 static void gen_evsel1(DisasContext *ctx)
7248 {
7249 gen_evsel(ctx);
7250 }
7251
7252 static void gen_evsel2(DisasContext *ctx)
7253 {
7254 gen_evsel(ctx);
7255 }
7256
7257 static void gen_evsel3(DisasContext *ctx)
7258 {
7259 gen_evsel(ctx);
7260 }
7261
7262 /* Multiply */
7263
7264 static inline void gen_evmwumi(DisasContext *ctx)
7265 {
7266 TCGv_i64 t0, t1;
7267
7268 if (unlikely(!ctx->spe_enabled)) {
7269 gen_exception(ctx, POWERPC_EXCP_SPEU);
7270 return;
7271 }
7272
7273 t0 = tcg_temp_new_i64();
7274 t1 = tcg_temp_new_i64();
7275
7276 /* t0 := rA; t1 := rB */
7277 #if defined(TARGET_PPC64)
7278 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7279 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7280 #else
7281 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7282 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7283 #endif
7284
7285 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7286
7287 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7288
7289 tcg_temp_free_i64(t0);
7290 tcg_temp_free_i64(t1);
7291 }
7292
7293 static inline void gen_evmwumia(DisasContext *ctx)
7294 {
7295 TCGv_i64 tmp;
7296
7297 if (unlikely(!ctx->spe_enabled)) {
7298 gen_exception(ctx, POWERPC_EXCP_SPEU);
7299 return;
7300 }
7301
7302 gen_evmwumi(ctx); /* rD := rA * rB */
7303
7304 tmp = tcg_temp_new_i64();
7305
7306 /* acc := rD */
7307 gen_load_gpr64(tmp, rD(ctx->opcode));
7308 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
7309 tcg_temp_free_i64(tmp);
7310 }
7311
7312 static inline void gen_evmwumiaa(DisasContext *ctx)
7313 {
7314 TCGv_i64 acc;
7315 TCGv_i64 tmp;
7316
7317 if (unlikely(!ctx->spe_enabled)) {
7318 gen_exception(ctx, POWERPC_EXCP_SPEU);
7319 return;
7320 }
7321
7322 gen_evmwumi(ctx); /* rD := rA * rB */
7323
7324 acc = tcg_temp_new_i64();
7325 tmp = tcg_temp_new_i64();
7326
7327 /* tmp := rD */
7328 gen_load_gpr64(tmp, rD(ctx->opcode));
7329
7330 /* Load acc */
7331 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7332
7333 /* acc := tmp + acc */
7334 tcg_gen_add_i64(acc, acc, tmp);
7335
7336 /* Store acc */
7337 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7338
7339 /* rD := acc */
7340 gen_store_gpr64(rD(ctx->opcode), acc);
7341
7342 tcg_temp_free_i64(acc);
7343 tcg_temp_free_i64(tmp);
7344 }
7345
7346 static inline void gen_evmwsmi(DisasContext *ctx)
7347 {
7348 TCGv_i64 t0, t1;
7349
7350 if (unlikely(!ctx->spe_enabled)) {
7351 gen_exception(ctx, POWERPC_EXCP_SPEU);
7352 return;
7353 }
7354
7355 t0 = tcg_temp_new_i64();
7356 t1 = tcg_temp_new_i64();
7357
7358 /* t0 := rA; t1 := rB */
7359 #if defined(TARGET_PPC64)
7360 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7361 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7362 #else
7363 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7364 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7365 #endif
7366
7367 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7368
7369 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7370
7371 tcg_temp_free_i64(t0);
7372 tcg_temp_free_i64(t1);
7373 }
7374
7375 static inline void gen_evmwsmia(DisasContext *ctx)
7376 {
7377 TCGv_i64 tmp;
7378
7379 gen_evmwsmi(ctx); /* rD := rA * rB */
7380
7381 tmp = tcg_temp_new_i64();
7382
7383 /* acc := rD */
7384 gen_load_gpr64(tmp, rD(ctx->opcode));
7385 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
7386
7387 tcg_temp_free_i64(tmp);
7388 }
7389
7390 static inline void gen_evmwsmiaa(DisasContext *ctx)
7391 {
7392 TCGv_i64 acc = tcg_temp_new_i64();
7393 TCGv_i64 tmp = tcg_temp_new_i64();
7394
7395 gen_evmwsmi(ctx); /* rD := rA * rB */
7396
7397 acc = tcg_temp_new_i64();
7398 tmp = tcg_temp_new_i64();
7399
7400 /* tmp := rD */
7401 gen_load_gpr64(tmp, rD(ctx->opcode));
7402
7403 /* Load acc */
7404 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7405
7406 /* acc := tmp + acc */
7407 tcg_gen_add_i64(acc, acc, tmp);
7408
7409 /* Store acc */
7410 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7411
7412 /* rD := acc */
7413 gen_store_gpr64(rD(ctx->opcode), acc);
7414
7415 tcg_temp_free_i64(acc);
7416 tcg_temp_free_i64(tmp);
7417 }
7418
7419 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7420 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7421 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7422 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7423 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7424 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7425 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7426 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7427 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, PPC_SPE);
7428 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7429 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7430 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7431 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7432 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7433 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7434 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7435 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7436 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7437 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7438 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7439 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7440 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7441 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7442 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7443 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7444 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7445 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7446 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7447 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7448
7449 /* SPE load and stores */
7450 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7451 {
7452 target_ulong uimm = rB(ctx->opcode);
7453
7454 if (rA(ctx->opcode) == 0) {
7455 tcg_gen_movi_tl(EA, uimm << sh);
7456 } else {
7457 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7458 #if defined(TARGET_PPC64)
7459 if (!ctx->sf_mode) {
7460 tcg_gen_ext32u_tl(EA, EA);
7461 }
7462 #endif
7463 }
7464 }
7465
7466 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7467 {
7468 #if defined(TARGET_PPC64)
7469 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7470 #else
7471 TCGv_i64 t0 = tcg_temp_new_i64();
7472 gen_qemu_ld64(ctx, t0, addr);
7473 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7474 tcg_gen_shri_i64(t0, t0, 32);
7475 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7476 tcg_temp_free_i64(t0);
7477 #endif
7478 }
7479
7480 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7481 {
7482 #if defined(TARGET_PPC64)
7483 TCGv t0 = tcg_temp_new();
7484 gen_qemu_ld32u(ctx, t0, addr);
7485 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7486 gen_addr_add(ctx, addr, addr, 4);
7487 gen_qemu_ld32u(ctx, t0, addr);
7488 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7489 tcg_temp_free(t0);
7490 #else
7491 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7492 gen_addr_add(ctx, addr, addr, 4);
7493 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7494 #endif
7495 }
7496
7497 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7498 {
7499 TCGv t0 = tcg_temp_new();
7500 #if defined(TARGET_PPC64)
7501 gen_qemu_ld16u(ctx, t0, addr);
7502 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7503 gen_addr_add(ctx, addr, addr, 2);
7504 gen_qemu_ld16u(ctx, t0, addr);
7505 tcg_gen_shli_tl(t0, t0, 32);
7506 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7507 gen_addr_add(ctx, addr, addr, 2);
7508 gen_qemu_ld16u(ctx, t0, addr);
7509 tcg_gen_shli_tl(t0, t0, 16);
7510 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7511 gen_addr_add(ctx, addr, addr, 2);
7512 gen_qemu_ld16u(ctx, t0, addr);
7513 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7514 #else
7515 gen_qemu_ld16u(ctx, t0, addr);
7516 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7517 gen_addr_add(ctx, addr, addr, 2);
7518 gen_qemu_ld16u(ctx, t0, addr);
7519 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7520 gen_addr_add(ctx, addr, addr, 2);
7521 gen_qemu_ld16u(ctx, t0, addr);
7522 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7523 gen_addr_add(ctx, addr, addr, 2);
7524 gen_qemu_ld16u(ctx, t0, addr);
7525 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7526 #endif
7527 tcg_temp_free(t0);
7528 }
7529
7530 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7531 {
7532 TCGv t0 = tcg_temp_new();
7533 gen_qemu_ld16u(ctx, t0, addr);
7534 #if defined(TARGET_PPC64)
7535 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7536 tcg_gen_shli_tl(t0, t0, 16);
7537 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7538 #else
7539 tcg_gen_shli_tl(t0, t0, 16);
7540 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7541 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7542 #endif
7543 tcg_temp_free(t0);
7544 }
7545
7546 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7547 {
7548 TCGv t0 = tcg_temp_new();
7549 gen_qemu_ld16u(ctx, t0, addr);
7550 #if defined(TARGET_PPC64)
7551 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7552 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7553 #else
7554 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7555 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7556 #endif
7557 tcg_temp_free(t0);
7558 }
7559
7560 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7561 {
7562 TCGv t0 = tcg_temp_new();
7563 gen_qemu_ld16s(ctx, t0, addr);
7564 #if defined(TARGET_PPC64)
7565 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7566 tcg_gen_ext32u_tl(t0, t0);
7567 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7568 #else
7569 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7570 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7571 #endif
7572 tcg_temp_free(t0);
7573 }
7574
7575 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7576 {
7577 TCGv t0 = tcg_temp_new();
7578 #if defined(TARGET_PPC64)
7579 gen_qemu_ld16u(ctx, t0, addr);
7580 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7581 gen_addr_add(ctx, addr, addr, 2);
7582 gen_qemu_ld16u(ctx, t0, addr);
7583 tcg_gen_shli_tl(t0, t0, 16);
7584 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7585 #else
7586 gen_qemu_ld16u(ctx, t0, addr);
7587 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7588 gen_addr_add(ctx, addr, addr, 2);
7589 gen_qemu_ld16u(ctx, t0, addr);
7590 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7591 #endif
7592 tcg_temp_free(t0);
7593 }
7594
7595 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7596 {
7597 #if defined(TARGET_PPC64)
7598 TCGv t0 = tcg_temp_new();
7599 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7600 gen_addr_add(ctx, addr, addr, 2);
7601 gen_qemu_ld16u(ctx, t0, addr);
7602 tcg_gen_shli_tl(t0, t0, 32);
7603 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7604 tcg_temp_free(t0);
7605 #else
7606 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7607 gen_addr_add(ctx, addr, addr, 2);
7608 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7609 #endif
7610 }
7611
7612 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7613 {
7614 #if defined(TARGET_PPC64)
7615 TCGv t0 = tcg_temp_new();
7616 gen_qemu_ld16s(ctx, t0, addr);
7617 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7618 gen_addr_add(ctx, addr, addr, 2);
7619 gen_qemu_ld16s(ctx, t0, addr);
7620 tcg_gen_shli_tl(t0, t0, 32);
7621 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7622 tcg_temp_free(t0);
7623 #else
7624 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7625 gen_addr_add(ctx, addr, addr, 2);
7626 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7627 #endif
7628 }
7629
7630 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7631 {
7632 TCGv t0 = tcg_temp_new();
7633 gen_qemu_ld32u(ctx, t0, addr);
7634 #if defined(TARGET_PPC64)
7635 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7636 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7637 #else
7638 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7639 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7640 #endif
7641 tcg_temp_free(t0);
7642 }
7643
7644 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7645 {
7646 TCGv t0 = tcg_temp_new();
7647 #if defined(TARGET_PPC64)
7648 gen_qemu_ld16u(ctx, t0, addr);
7649 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7650 tcg_gen_shli_tl(t0, t0, 32);
7651 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7652 gen_addr_add(ctx, addr, addr, 2);
7653 gen_qemu_ld16u(ctx, t0, addr);
7654 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7655 tcg_gen_shli_tl(t0, t0, 16);
7656 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7657 #else
7658 gen_qemu_ld16u(ctx, t0, addr);
7659 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7660 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7661 gen_addr_add(ctx, addr, addr, 2);
7662 gen_qemu_ld16u(ctx, t0, addr);
7663 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7664 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7665 #endif
7666 tcg_temp_free(t0);
7667 }
7668
7669 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7670 {
7671 #if defined(TARGET_PPC64)
7672 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7673 #else
7674 TCGv_i64 t0 = tcg_temp_new_i64();
7675 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7676 gen_qemu_st64(ctx, t0, addr);
7677 tcg_temp_free_i64(t0);
7678 #endif
7679 }
7680
7681 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7682 {
7683 #if defined(TARGET_PPC64)
7684 TCGv t0 = tcg_temp_new();
7685 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7686 gen_qemu_st32(ctx, t0, addr);
7687 tcg_temp_free(t0);
7688 #else
7689 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7690 #endif
7691 gen_addr_add(ctx, addr, addr, 4);
7692 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7693 }
7694
7695 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7696 {
7697 TCGv t0 = tcg_temp_new();
7698 #if defined(TARGET_PPC64)
7699 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7700 #else
7701 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7702 #endif
7703 gen_qemu_st16(ctx, t0, addr);
7704 gen_addr_add(ctx, addr, addr, 2);
7705 #if defined(TARGET_PPC64)
7706 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7707 gen_qemu_st16(ctx, t0, addr);
7708 #else
7709 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7710 #endif
7711 gen_addr_add(ctx, addr, addr, 2);
7712 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7713 gen_qemu_st16(ctx, t0, addr);
7714 tcg_temp_free(t0);
7715 gen_addr_add(ctx, addr, addr, 2);
7716 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7717 }
7718
7719 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7720 {
7721 TCGv t0 = tcg_temp_new();
7722 #if defined(TARGET_PPC64)
7723 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7724 #else
7725 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7726 #endif
7727 gen_qemu_st16(ctx, t0, addr);
7728 gen_addr_add(ctx, addr, addr, 2);
7729 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7730 gen_qemu_st16(ctx, t0, addr);
7731 tcg_temp_free(t0);
7732 }
7733
7734 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7735 {
7736 #if defined(TARGET_PPC64)
7737 TCGv t0 = tcg_temp_new();
7738 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7739 gen_qemu_st16(ctx, t0, addr);
7740 tcg_temp_free(t0);
7741 #else
7742 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7743 #endif
7744 gen_addr_add(ctx, addr, addr, 2);
7745 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7746 }
7747
7748 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7749 {
7750 #if defined(TARGET_PPC64)
7751 TCGv t0 = tcg_temp_new();
7752 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7753 gen_qemu_st32(ctx, t0, addr);
7754 tcg_temp_free(t0);
7755 #else
7756 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7757 #endif
7758 }
7759
7760 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7761 {
7762 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7763 }
7764
7765 #define GEN_SPEOP_LDST(name, opc2, sh) \
7766 static void glue(gen_, name)(DisasContext *ctx) \
7767 { \
7768 TCGv t0; \
7769 if (unlikely(!ctx->spe_enabled)) { \
7770 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7771 return; \
7772 } \
7773 gen_set_access_type(ctx, ACCESS_INT); \
7774 t0 = tcg_temp_new(); \
7775 if (Rc(ctx->opcode)) { \
7776 gen_addr_spe_imm_index(ctx, t0, sh); \
7777 } else { \
7778 gen_addr_reg_index(ctx, t0); \
7779 } \
7780 gen_op_##name(ctx, t0); \
7781 tcg_temp_free(t0); \
7782 }
7783
7784 GEN_SPEOP_LDST(evldd, 0x00, 3);
7785 GEN_SPEOP_LDST(evldw, 0x01, 3);
7786 GEN_SPEOP_LDST(evldh, 0x02, 3);
7787 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7788 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7789 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7790 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7791 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7792 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7793 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7794 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7795
7796 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7797 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7798 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7799 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7800 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7801 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7802 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7803
7804 /* Multiply and add - TODO */
7805 #if 0
7806 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7807 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7808 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7809 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7810 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7811 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7812 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7813 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7814 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7815 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7816 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7817 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7818
7819 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7820 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7821 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7822 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7823 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7824 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7825 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7826 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7827 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7828 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7829 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7830 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7831
7832 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7833 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7834 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7835 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7836 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7837
7838 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7839 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7840 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7841 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7842 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7843 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7844 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7845 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7846 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7847 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7848 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7849 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7850
7851 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7852 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7853 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7854 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7855
7856 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7857 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7858 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7859 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7860 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7861 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7862 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7863 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7864 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7865 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7866 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7867 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7868
7869 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7870 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7871 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7872 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7873 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7874 #endif
7875
7876 /*** SPE floating-point extension ***/
7877 #if defined(TARGET_PPC64)
7878 #define GEN_SPEFPUOP_CONV_32_32(name) \
7879 static inline void gen_##name(DisasContext *ctx) \
7880 { \
7881 TCGv_i32 t0; \
7882 TCGv t1; \
7883 t0 = tcg_temp_new_i32(); \
7884 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7885 gen_helper_##name(t0, t0); \
7886 t1 = tcg_temp_new(); \
7887 tcg_gen_extu_i32_tl(t1, t0); \
7888 tcg_temp_free_i32(t0); \
7889 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7890 0xFFFFFFFF00000000ULL); \
7891 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7892 tcg_temp_free(t1); \
7893 }
7894 #define GEN_SPEFPUOP_CONV_32_64(name) \
7895 static inline void gen_##name(DisasContext *ctx) \
7896 { \
7897 TCGv_i32 t0; \
7898 TCGv t1; \
7899 t0 = tcg_temp_new_i32(); \
7900 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7901 t1 = tcg_temp_new(); \
7902 tcg_gen_extu_i32_tl(t1, t0); \
7903 tcg_temp_free_i32(t0); \
7904 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7905 0xFFFFFFFF00000000ULL); \
7906 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7907 tcg_temp_free(t1); \
7908 }
7909 #define GEN_SPEFPUOP_CONV_64_32(name) \
7910 static inline void gen_##name(DisasContext *ctx) \
7911 { \
7912 TCGv_i32 t0 = tcg_temp_new_i32(); \
7913 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7914 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7915 tcg_temp_free_i32(t0); \
7916 }
7917 #define GEN_SPEFPUOP_CONV_64_64(name) \
7918 static inline void gen_##name(DisasContext *ctx) \
7919 { \
7920 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7921 }
7922 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7923 static inline void gen_##name(DisasContext *ctx) \
7924 { \
7925 TCGv_i32 t0, t1; \
7926 TCGv_i64 t2; \
7927 if (unlikely(!ctx->spe_enabled)) { \
7928 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7929 return; \
7930 } \
7931 t0 = tcg_temp_new_i32(); \
7932 t1 = tcg_temp_new_i32(); \
7933 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7934 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7935 gen_helper_##name(t0, t0, t1); \
7936 tcg_temp_free_i32(t1); \
7937 t2 = tcg_temp_new(); \
7938 tcg_gen_extu_i32_tl(t2, t0); \
7939 tcg_temp_free_i32(t0); \
7940 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7941 0xFFFFFFFF00000000ULL); \
7942 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7943 tcg_temp_free(t2); \
7944 }
7945 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7946 static inline void gen_##name(DisasContext *ctx) \
7947 { \
7948 if (unlikely(!ctx->spe_enabled)) { \
7949 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7950 return; \
7951 } \
7952 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7953 cpu_gpr[rB(ctx->opcode)]); \
7954 }
7955 #define GEN_SPEFPUOP_COMP_32(name) \
7956 static inline void gen_##name(DisasContext *ctx) \
7957 { \
7958 TCGv_i32 t0, t1; \
7959 if (unlikely(!ctx->spe_enabled)) { \
7960 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7961 return; \
7962 } \
7963 t0 = tcg_temp_new_i32(); \
7964 t1 = tcg_temp_new_i32(); \
7965 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7966 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7967 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7968 tcg_temp_free_i32(t0); \
7969 tcg_temp_free_i32(t1); \
7970 }
7971 #define GEN_SPEFPUOP_COMP_64(name) \
7972 static inline void gen_##name(DisasContext *ctx) \
7973 { \
7974 if (unlikely(!ctx->spe_enabled)) { \
7975 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7976 return; \
7977 } \
7978 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7979 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7980 }
7981 #else
7982 #define GEN_SPEFPUOP_CONV_32_32(name) \
7983 static inline void gen_##name(DisasContext *ctx) \
7984 { \
7985 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7986 }
7987 #define GEN_SPEFPUOP_CONV_32_64(name) \
7988 static inline void gen_##name(DisasContext *ctx) \
7989 { \
7990 TCGv_i64 t0 = tcg_temp_new_i64(); \
7991 gen_load_gpr64(t0, rB(ctx->opcode)); \
7992 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7993 tcg_temp_free_i64(t0); \
7994 }
7995 #define GEN_SPEFPUOP_CONV_64_32(name) \
7996 static inline void gen_##name(DisasContext *ctx) \
7997 { \
7998 TCGv_i64 t0 = tcg_temp_new_i64(); \
7999 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
8000 gen_store_gpr64(rD(ctx->opcode), t0); \
8001 tcg_temp_free_i64(t0); \
8002 }
8003 #define GEN_SPEFPUOP_CONV_64_64(name) \
8004 static inline void gen_##name(DisasContext *ctx) \
8005 { \
8006 TCGv_i64 t0 = tcg_temp_new_i64(); \
8007 gen_load_gpr64(t0, rB(ctx->opcode)); \
8008 gen_helper_##name(t0, t0); \
8009 gen_store_gpr64(rD(ctx->opcode), t0); \
8010 tcg_temp_free_i64(t0); \
8011 }
8012 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8013 static inline void gen_##name(DisasContext *ctx) \
8014 { \
8015 if (unlikely(!ctx->spe_enabled)) { \
8016 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8017 return; \
8018 } \
8019 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
8020 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8021 }
8022 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8023 static inline void gen_##name(DisasContext *ctx) \
8024 { \
8025 TCGv_i64 t0, t1; \
8026 if (unlikely(!ctx->spe_enabled)) { \
8027 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8028 return; \
8029 } \
8030 t0 = tcg_temp_new_i64(); \
8031 t1 = tcg_temp_new_i64(); \
8032 gen_load_gpr64(t0, rA(ctx->opcode)); \
8033 gen_load_gpr64(t1, rB(ctx->opcode)); \
8034 gen_helper_##name(t0, t0, t1); \
8035 gen_store_gpr64(rD(ctx->opcode), t0); \
8036 tcg_temp_free_i64(t0); \
8037 tcg_temp_free_i64(t1); \
8038 }
8039 #define GEN_SPEFPUOP_COMP_32(name) \
8040 static inline void gen_##name(DisasContext *ctx) \
8041 { \
8042 if (unlikely(!ctx->spe_enabled)) { \
8043 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8044 return; \
8045 } \
8046 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8047 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8048 }
8049 #define GEN_SPEFPUOP_COMP_64(name) \
8050 static inline void gen_##name(DisasContext *ctx) \
8051 { \
8052 TCGv_i64 t0, t1; \
8053 if (unlikely(!ctx->spe_enabled)) { \
8054 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8055 return; \
8056 } \
8057 t0 = tcg_temp_new_i64(); \
8058 t1 = tcg_temp_new_i64(); \
8059 gen_load_gpr64(t0, rA(ctx->opcode)); \
8060 gen_load_gpr64(t1, rB(ctx->opcode)); \
8061 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
8062 tcg_temp_free_i64(t0); \
8063 tcg_temp_free_i64(t1); \
8064 }
8065 #endif
8066
8067 /* Single precision floating-point vectors operations */
8068 /* Arithmetic */
8069 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8070 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8071 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8072 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8073 static inline void gen_evfsabs(DisasContext *ctx)
8074 {
8075 if (unlikely(!ctx->spe_enabled)) {
8076 gen_exception(ctx, POWERPC_EXCP_SPEU);
8077 return;
8078 }
8079 #if defined(TARGET_PPC64)
8080 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8081 #else
8082 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8083 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8084 #endif
8085 }
8086 static inline void gen_evfsnabs(DisasContext *ctx)
8087 {
8088 if (unlikely(!ctx->spe_enabled)) {
8089 gen_exception(ctx, POWERPC_EXCP_SPEU);
8090 return;
8091 }
8092 #if defined(TARGET_PPC64)
8093 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8094 #else
8095 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8096 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8097 #endif
8098 }
8099 static inline void gen_evfsneg(DisasContext *ctx)
8100 {
8101 if (unlikely(!ctx->spe_enabled)) {
8102 gen_exception(ctx, POWERPC_EXCP_SPEU);
8103 return;
8104 }
8105 #if defined(TARGET_PPC64)
8106 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8107 #else
8108 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8109 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8110 #endif
8111 }
8112
8113 /* Conversion */
8114 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8115 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8116 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8117 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8118 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8119 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8120 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8121 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8122 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8123 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8124
8125 /* Comparison */
8126 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8127 GEN_SPEFPUOP_COMP_64(evfscmplt);
8128 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8129 GEN_SPEFPUOP_COMP_64(evfststgt);
8130 GEN_SPEFPUOP_COMP_64(evfststlt);
8131 GEN_SPEFPUOP_COMP_64(evfststeq);
8132
8133 /* Opcodes definitions */
8134 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
8135 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
8136 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
8137 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
8138 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
8139 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
8140 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
8141 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
8142 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
8143 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
8144 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
8145 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
8146 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
8147 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
8148
8149 /* Single precision floating-point operations */
8150 /* Arithmetic */
8151 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8152 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8153 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8154 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8155 static inline void gen_efsabs(DisasContext *ctx)
8156 {
8157 if (unlikely(!ctx->spe_enabled)) {
8158 gen_exception(ctx, POWERPC_EXCP_SPEU);
8159 return;
8160 }
8161 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8162 }
8163 static inline void gen_efsnabs(DisasContext *ctx)
8164 {
8165 if (unlikely(!ctx->spe_enabled)) {
8166 gen_exception(ctx, POWERPC_EXCP_SPEU);
8167 return;
8168 }
8169 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8170 }
8171 static inline void gen_efsneg(DisasContext *ctx)
8172 {
8173 if (unlikely(!ctx->spe_enabled)) {
8174 gen_exception(ctx, POWERPC_EXCP_SPEU);
8175 return;
8176 }
8177 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8178 }
8179
8180 /* Conversion */
8181 GEN_SPEFPUOP_CONV_32_32(efscfui);
8182 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8183 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8184 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8185 GEN_SPEFPUOP_CONV_32_32(efsctui);
8186 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8187 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8188 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8189 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8190 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8191 GEN_SPEFPUOP_CONV_32_64(efscfd);
8192
8193 /* Comparison */
8194 GEN_SPEFPUOP_COMP_32(efscmpgt);
8195 GEN_SPEFPUOP_COMP_32(efscmplt);
8196 GEN_SPEFPUOP_COMP_32(efscmpeq);
8197 GEN_SPEFPUOP_COMP_32(efststgt);
8198 GEN_SPEFPUOP_COMP_32(efststlt);
8199 GEN_SPEFPUOP_COMP_32(efststeq);
8200
8201 /* Opcodes definitions */
8202 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
8203 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
8204 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
8205 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
8206 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8207 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8208 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8209 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8210 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8211 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8212 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8213 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8214 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8215 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8216
8217 /* Double precision floating-point operations */
8218 /* Arithmetic */
8219 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8220 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8221 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8222 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8223 static inline void gen_efdabs(DisasContext *ctx)
8224 {
8225 if (unlikely(!ctx->spe_enabled)) {
8226 gen_exception(ctx, POWERPC_EXCP_SPEU);
8227 return;
8228 }
8229 #if defined(TARGET_PPC64)
8230 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8231 #else
8232 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8233 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8234 #endif
8235 }
8236 static inline void gen_efdnabs(DisasContext *ctx)
8237 {
8238 if (unlikely(!ctx->spe_enabled)) {
8239 gen_exception(ctx, POWERPC_EXCP_SPEU);
8240 return;
8241 }
8242 #if defined(TARGET_PPC64)
8243 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8244 #else
8245 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8246 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8247 #endif
8248 }
8249 static inline void gen_efdneg(DisasContext *ctx)
8250 {
8251 if (unlikely(!ctx->spe_enabled)) {
8252 gen_exception(ctx, POWERPC_EXCP_SPEU);
8253 return;
8254 }
8255 #if defined(TARGET_PPC64)
8256 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8257 #else
8258 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8259 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8260 #endif
8261 }
8262
8263 /* Conversion */
8264 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8265 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8266 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8267 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8268 GEN_SPEFPUOP_CONV_32_64(efdctui);
8269 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8270 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8271 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8272 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8273 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8274 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8275 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8276 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8277 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8278 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8279
8280 /* Comparison */
8281 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8282 GEN_SPEFPUOP_COMP_64(efdcmplt);
8283 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8284 GEN_SPEFPUOP_COMP_64(efdtstgt);
8285 GEN_SPEFPUOP_COMP_64(efdtstlt);
8286 GEN_SPEFPUOP_COMP_64(efdtsteq);
8287
8288 /* Opcodes definitions */
8289 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8290 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8291 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8292 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8293 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8294 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8295 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8296 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8297 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8298 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8299 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8300 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8301 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8302 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8303 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8304 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8305
8306 static opcode_t opcodes[] = {
8307 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8308 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8309 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8310 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8311 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8312 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8313 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8314 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8315 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8316 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8317 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8318 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8319 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8320 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8321 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8322 #if defined(TARGET_PPC64)
8323 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8324 #endif
8325 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8326 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8327 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8328 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8329 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8330 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8331 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8332 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8333 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8334 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8335 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8336 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8337 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8338 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8339 #if defined(TARGET_PPC64)
8340 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8341 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8342 #endif
8343 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8344 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8345 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8346 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8347 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8348 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8349 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8350 #if defined(TARGET_PPC64)
8351 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8352 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8353 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8354 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8355 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8356 #endif
8357 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8358 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8359 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8360 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8361 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8362 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8363 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8364 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8365 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8366 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8367 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8368 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8369 #if defined(TARGET_PPC64)
8370 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8371 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8372 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8373 #endif
8374 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8375 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8376 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8377 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8378 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8379 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8380 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8381 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8382 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8383 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8384 #if defined(TARGET_PPC64)
8385 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8386 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8387 #endif
8388 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8389 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8390 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8391 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8392 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8393 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8394 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8395 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8396 #if defined(TARGET_PPC64)
8397 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8398 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8399 #endif
8400 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8401 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8402 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8403 #if defined(TARGET_PPC64)
8404 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8405 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8406 #endif
8407 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8408 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8409 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8410 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8411 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8412 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8413 #if defined(TARGET_PPC64)
8414 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8415 #endif
8416 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8417 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8418 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8419 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8420 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8421 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8422 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8423 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ),
8424 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT),
8425 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8426 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8427 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8428 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8429 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8430 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8431 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8432 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8433 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8434 #if defined(TARGET_PPC64)
8435 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8436 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8437 PPC_SEGMENT_64B),
8438 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8439 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8440 PPC_SEGMENT_64B),
8441 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8442 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8443 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8444 #endif
8445 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8446 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8447 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8448 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8449 #if defined(TARGET_PPC64)
8450 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8451 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8452 #endif
8453 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8454 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8455 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8456 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8457 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8458 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8459 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8460 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8461 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8462 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8463 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8464 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8465 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8466 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8467 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8468 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8469 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8470 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8471 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8472 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8473 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8474 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8475 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8476 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8477 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8478 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8479 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8480 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8481 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8482 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8483 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8484 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8485 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8486 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8487 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8488 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8489 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8490 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8491 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8492 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8493 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8494 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8495 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8496 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8497 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8498 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8499 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8500 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8501 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8502 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8503 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8504 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8505 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8506 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8507 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8508 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8509 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8510 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8511 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8512 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8513 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8514 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8515 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8516 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8517 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8518 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8519 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8520 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8521 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8522 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8523 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8524 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8525 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8526 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8527 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8528 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8529 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8530 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8531 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8532 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8533 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8534 PPC_NONE, PPC2_BOOKE206),
8535 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8536 PPC_NONE, PPC2_BOOKE206),
8537 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8538 PPC_NONE, PPC2_BOOKE206),
8539 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8540 PPC_NONE, PPC2_BOOKE206),
8541 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8542 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8543 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8544 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8545 PPC_BOOKE, PPC2_BOOKE206),
8546 GEN_HANDLER_E(msync, 0x1F, 0x16, 0x12, 0x03FFF801,
8547 PPC_BOOKE, PPC2_BOOKE206),
8548 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8549 PPC_BOOKE, PPC2_BOOKE206),
8550 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8551 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8552 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8553 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8554 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8555 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8556 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8557 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8558 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8559 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8560
8561 #undef GEN_INT_ARITH_ADD
8562 #undef GEN_INT_ARITH_ADD_CONST
8563 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8564 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8565 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8566 add_ca, compute_ca, compute_ov) \
8567 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8568 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8569 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8570 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8571 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8572 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8573 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8574 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8575 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8576 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8577 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8578
8579 #undef GEN_INT_ARITH_DIVW
8580 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8581 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8582 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8583 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8584 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8585 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8586
8587 #if defined(TARGET_PPC64)
8588 #undef GEN_INT_ARITH_DIVD
8589 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8590 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8591 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8592 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8593 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8594 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8595
8596 #undef GEN_INT_ARITH_MUL_HELPER
8597 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8598 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8599 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8600 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8601 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8602 #endif
8603
8604 #undef GEN_INT_ARITH_SUBF
8605 #undef GEN_INT_ARITH_SUBF_CONST
8606 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8607 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8608 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8609 add_ca, compute_ca, compute_ov) \
8610 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8611 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8612 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8613 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8614 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8615 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8616 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8617 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8618 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8619 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8620 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8621
8622 #undef GEN_LOGICAL1
8623 #undef GEN_LOGICAL2
8624 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8625 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8626 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8627 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8628 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8629 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8630 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8631 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8632 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8633 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8634 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8635 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8636 #if defined(TARGET_PPC64)
8637 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8638 #endif
8639
8640 #if defined(TARGET_PPC64)
8641 #undef GEN_PPC64_R2
8642 #undef GEN_PPC64_R4
8643 #define GEN_PPC64_R2(name, opc1, opc2) \
8644 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8645 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8646 PPC_64B)
8647 #define GEN_PPC64_R4(name, opc1, opc2) \
8648 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8649 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8650 PPC_64B), \
8651 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8652 PPC_64B), \
8653 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8654 PPC_64B)
8655 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8656 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8657 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8658 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8659 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8660 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8661 #endif
8662
8663 #undef _GEN_FLOAT_ACB
8664 #undef GEN_FLOAT_ACB
8665 #undef _GEN_FLOAT_AB
8666 #undef GEN_FLOAT_AB
8667 #undef _GEN_FLOAT_AC
8668 #undef GEN_FLOAT_AC
8669 #undef GEN_FLOAT_B
8670 #undef GEN_FLOAT_BS
8671 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8672 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8673 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8674 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8675 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8676 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8677 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8678 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8679 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8680 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8681 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8682 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8683 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8684 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8685 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8686 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8687 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8688 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8689 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8690
8691 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8692 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8693 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8694 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8695 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8696 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8697 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8698 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8699 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8700 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8701 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8702 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8703 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8704 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8705 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8706 #if defined(TARGET_PPC64)
8707 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8708 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8709 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8710 #endif
8711 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8712 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8713 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8714 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8715 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8716 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8717 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8718
8719 #undef GEN_LD
8720 #undef GEN_LDU
8721 #undef GEN_LDUX
8722 #undef GEN_LDX
8723 #undef GEN_LDS
8724 #define GEN_LD(name, ldop, opc, type) \
8725 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8726 #define GEN_LDU(name, ldop, opc, type) \
8727 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8728 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8729 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8730 #define GEN_LDX(name, ldop, opc2, opc3, type) \
8731 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8732 #define GEN_LDS(name, ldop, op, type) \
8733 GEN_LD(name, ldop, op | 0x20, type) \
8734 GEN_LDU(name, ldop, op | 0x21, type) \
8735 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8736 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8737
8738 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8739 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8740 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8741 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8742 #if defined(TARGET_PPC64)
8743 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8744 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8745 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8746 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8747 #endif
8748 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8749 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8750
8751 #undef GEN_ST
8752 #undef GEN_STU
8753 #undef GEN_STUX
8754 #undef GEN_STX
8755 #undef GEN_STS
8756 #define GEN_ST(name, stop, opc, type) \
8757 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8758 #define GEN_STU(name, stop, opc, type) \
8759 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8760 #define GEN_STUX(name, stop, opc2, opc3, type) \
8761 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8762 #define GEN_STX(name, stop, opc2, opc3, type) \
8763 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8764 #define GEN_STS(name, stop, op, type) \
8765 GEN_ST(name, stop, op | 0x20, type) \
8766 GEN_STU(name, stop, op | 0x21, type) \
8767 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8768 GEN_STX(name, stop, 0x17, op | 0x00, type)
8769
8770 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8771 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8772 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8773 #if defined(TARGET_PPC64)
8774 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8775 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8776 #endif
8777 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8778 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8779
8780 #undef GEN_LDF
8781 #undef GEN_LDUF
8782 #undef GEN_LDUXF
8783 #undef GEN_LDXF
8784 #undef GEN_LDFS
8785 #define GEN_LDF(name, ldop, opc, type) \
8786 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8787 #define GEN_LDUF(name, ldop, opc, type) \
8788 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8789 #define GEN_LDUXF(name, ldop, opc, type) \
8790 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8791 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8792 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8793 #define GEN_LDFS(name, ldop, op, type) \
8794 GEN_LDF(name, ldop, op | 0x20, type) \
8795 GEN_LDUF(name, ldop, op | 0x21, type) \
8796 GEN_LDUXF(name, ldop, op | 0x01, type) \
8797 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8798
8799 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8800 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8801
8802 #undef GEN_STF
8803 #undef GEN_STUF
8804 #undef GEN_STUXF
8805 #undef GEN_STXF
8806 #undef GEN_STFS
8807 #define GEN_STF(name, stop, opc, type) \
8808 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8809 #define GEN_STUF(name, stop, opc, type) \
8810 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8811 #define GEN_STUXF(name, stop, opc, type) \
8812 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8813 #define GEN_STXF(name, stop, opc2, opc3, type) \
8814 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8815 #define GEN_STFS(name, stop, op, type) \
8816 GEN_STF(name, stop, op | 0x20, type) \
8817 GEN_STUF(name, stop, op | 0x21, type) \
8818 GEN_STUXF(name, stop, op | 0x01, type) \
8819 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8820
8821 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8822 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8823 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8824
8825 #undef GEN_CRLOGIC
8826 #define GEN_CRLOGIC(name, tcg_op, opc) \
8827 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8828 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8829 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8830 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8831 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8832 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8833 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8834 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8835 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8836
8837 #undef GEN_MAC_HANDLER
8838 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8839 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8840 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8841 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8842 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8843 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8844 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8845 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8846 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8847 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8848 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8849 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8850 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8851 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8852 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8853 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8854 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8855 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8856 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8857 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8858 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8859 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8860 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8861 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8862 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8863 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8864 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8865 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8866 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8867 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8868 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8869 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8870 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8871 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
8872 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
8873 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
8874 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
8875 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
8876 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
8877 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
8878 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
8879 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
8880 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
8881 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
8882
8883 #undef GEN_VR_LDX
8884 #undef GEN_VR_STX
8885 #undef GEN_VR_LVE
8886 #undef GEN_VR_STVE
8887 #define GEN_VR_LDX(name, opc2, opc3) \
8888 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8889 #define GEN_VR_STX(name, opc2, opc3) \
8890 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8891 #define GEN_VR_LVE(name, opc2, opc3) \
8892 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8893 #define GEN_VR_STVE(name, opc2, opc3) \
8894 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8895 GEN_VR_LDX(lvx, 0x07, 0x03),
8896 GEN_VR_LDX(lvxl, 0x07, 0x0B),
8897 GEN_VR_LVE(bx, 0x07, 0x00),
8898 GEN_VR_LVE(hx, 0x07, 0x01),
8899 GEN_VR_LVE(wx, 0x07, 0x02),
8900 GEN_VR_STX(svx, 0x07, 0x07),
8901 GEN_VR_STX(svxl, 0x07, 0x0F),
8902 GEN_VR_STVE(bx, 0x07, 0x04),
8903 GEN_VR_STVE(hx, 0x07, 0x05),
8904 GEN_VR_STVE(wx, 0x07, 0x06),
8905
8906 #undef GEN_VX_LOGICAL
8907 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
8908 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8909 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
8910 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
8911 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
8912 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
8913 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
8914
8915 #undef GEN_VXFORM
8916 #define GEN_VXFORM(name, opc2, opc3) \
8917 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8918 GEN_VXFORM(vaddubm, 0, 0),
8919 GEN_VXFORM(vadduhm, 0, 1),
8920 GEN_VXFORM(vadduwm, 0, 2),
8921 GEN_VXFORM(vsububm, 0, 16),
8922 GEN_VXFORM(vsubuhm, 0, 17),
8923 GEN_VXFORM(vsubuwm, 0, 18),
8924 GEN_VXFORM(vmaxub, 1, 0),
8925 GEN_VXFORM(vmaxuh, 1, 1),
8926 GEN_VXFORM(vmaxuw, 1, 2),
8927 GEN_VXFORM(vmaxsb, 1, 4),
8928 GEN_VXFORM(vmaxsh, 1, 5),
8929 GEN_VXFORM(vmaxsw, 1, 6),
8930 GEN_VXFORM(vminub, 1, 8),
8931 GEN_VXFORM(vminuh, 1, 9),
8932 GEN_VXFORM(vminuw, 1, 10),
8933 GEN_VXFORM(vminsb, 1, 12),
8934 GEN_VXFORM(vminsh, 1, 13),
8935 GEN_VXFORM(vminsw, 1, 14),
8936 GEN_VXFORM(vavgub, 1, 16),
8937 GEN_VXFORM(vavguh, 1, 17),
8938 GEN_VXFORM(vavguw, 1, 18),
8939 GEN_VXFORM(vavgsb, 1, 20),
8940 GEN_VXFORM(vavgsh, 1, 21),
8941 GEN_VXFORM(vavgsw, 1, 22),
8942 GEN_VXFORM(vmrghb, 6, 0),
8943 GEN_VXFORM(vmrghh, 6, 1),
8944 GEN_VXFORM(vmrghw, 6, 2),
8945 GEN_VXFORM(vmrglb, 6, 4),
8946 GEN_VXFORM(vmrglh, 6, 5),
8947 GEN_VXFORM(vmrglw, 6, 6),
8948 GEN_VXFORM(vmuloub, 4, 0),
8949 GEN_VXFORM(vmulouh, 4, 1),
8950 GEN_VXFORM(vmulosb, 4, 4),
8951 GEN_VXFORM(vmulosh, 4, 5),
8952 GEN_VXFORM(vmuleub, 4, 8),
8953 GEN_VXFORM(vmuleuh, 4, 9),
8954 GEN_VXFORM(vmulesb, 4, 12),
8955 GEN_VXFORM(vmulesh, 4, 13),
8956 GEN_VXFORM(vslb, 2, 4),
8957 GEN_VXFORM(vslh, 2, 5),
8958 GEN_VXFORM(vslw, 2, 6),
8959 GEN_VXFORM(vsrb, 2, 8),
8960 GEN_VXFORM(vsrh, 2, 9),
8961 GEN_VXFORM(vsrw, 2, 10),
8962 GEN_VXFORM(vsrab, 2, 12),
8963 GEN_VXFORM(vsrah, 2, 13),
8964 GEN_VXFORM(vsraw, 2, 14),
8965 GEN_VXFORM(vslo, 6, 16),
8966 GEN_VXFORM(vsro, 6, 17),
8967 GEN_VXFORM(vaddcuw, 0, 6),
8968 GEN_VXFORM(vsubcuw, 0, 22),
8969 GEN_VXFORM(vaddubs, 0, 8),
8970 GEN_VXFORM(vadduhs, 0, 9),
8971 GEN_VXFORM(vadduws, 0, 10),
8972 GEN_VXFORM(vaddsbs, 0, 12),
8973 GEN_VXFORM(vaddshs, 0, 13),
8974 GEN_VXFORM(vaddsws, 0, 14),
8975 GEN_VXFORM(vsububs, 0, 24),
8976 GEN_VXFORM(vsubuhs, 0, 25),
8977 GEN_VXFORM(vsubuws, 0, 26),
8978 GEN_VXFORM(vsubsbs, 0, 28),
8979 GEN_VXFORM(vsubshs, 0, 29),
8980 GEN_VXFORM(vsubsws, 0, 30),
8981 GEN_VXFORM(vrlb, 2, 0),
8982 GEN_VXFORM(vrlh, 2, 1),
8983 GEN_VXFORM(vrlw, 2, 2),
8984 GEN_VXFORM(vsl, 2, 7),
8985 GEN_VXFORM(vsr, 2, 11),
8986 GEN_VXFORM(vpkuhum, 7, 0),
8987 GEN_VXFORM(vpkuwum, 7, 1),
8988 GEN_VXFORM(vpkuhus, 7, 2),
8989 GEN_VXFORM(vpkuwus, 7, 3),
8990 GEN_VXFORM(vpkshus, 7, 4),
8991 GEN_VXFORM(vpkswus, 7, 5),
8992 GEN_VXFORM(vpkshss, 7, 6),
8993 GEN_VXFORM(vpkswss, 7, 7),
8994 GEN_VXFORM(vpkpx, 7, 12),
8995 GEN_VXFORM(vsum4ubs, 4, 24),
8996 GEN_VXFORM(vsum4sbs, 4, 28),
8997 GEN_VXFORM(vsum4shs, 4, 25),
8998 GEN_VXFORM(vsum2sws, 4, 26),
8999 GEN_VXFORM(vsumsws, 4, 30),
9000 GEN_VXFORM(vaddfp, 5, 0),
9001 GEN_VXFORM(vsubfp, 5, 1),
9002 GEN_VXFORM(vmaxfp, 5, 16),
9003 GEN_VXFORM(vminfp, 5, 17),
9004
9005 #undef GEN_VXRFORM1
9006 #undef GEN_VXRFORM
9007 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9008 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9009 #define GEN_VXRFORM(name, opc2, opc3) \
9010 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9011 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9012 GEN_VXRFORM(vcmpequb, 3, 0)
9013 GEN_VXRFORM(vcmpequh, 3, 1)
9014 GEN_VXRFORM(vcmpequw, 3, 2)
9015 GEN_VXRFORM(vcmpgtsb, 3, 12)
9016 GEN_VXRFORM(vcmpgtsh, 3, 13)
9017 GEN_VXRFORM(vcmpgtsw, 3, 14)
9018 GEN_VXRFORM(vcmpgtub, 3, 8)
9019 GEN_VXRFORM(vcmpgtuh, 3, 9)
9020 GEN_VXRFORM(vcmpgtuw, 3, 10)
9021 GEN_VXRFORM(vcmpeqfp, 3, 3)
9022 GEN_VXRFORM(vcmpgefp, 3, 7)
9023 GEN_VXRFORM(vcmpgtfp, 3, 11)
9024 GEN_VXRFORM(vcmpbfp, 3, 15)
9025
9026 #undef GEN_VXFORM_SIMM
9027 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9028 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9029 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9030 GEN_VXFORM_SIMM(vspltish, 6, 13),
9031 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9032
9033 #undef GEN_VXFORM_NOA
9034 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9035 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9036 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9037 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9038 GEN_VXFORM_NOA(vupklsb, 7, 10),
9039 GEN_VXFORM_NOA(vupklsh, 7, 11),
9040 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9041 GEN_VXFORM_NOA(vupklpx, 7, 15),
9042 GEN_VXFORM_NOA(vrefp, 5, 4),
9043 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9044 GEN_VXFORM_NOA(vexptefp, 5, 6),
9045 GEN_VXFORM_NOA(vlogefp, 5, 7),
9046 GEN_VXFORM_NOA(vrfim, 5, 8),
9047 GEN_VXFORM_NOA(vrfin, 5, 9),
9048 GEN_VXFORM_NOA(vrfip, 5, 10),
9049 GEN_VXFORM_NOA(vrfiz, 5, 11),
9050
9051 #undef GEN_VXFORM_UIMM
9052 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9053 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9054 GEN_VXFORM_UIMM(vspltb, 6, 8),
9055 GEN_VXFORM_UIMM(vsplth, 6, 9),
9056 GEN_VXFORM_UIMM(vspltw, 6, 10),
9057 GEN_VXFORM_UIMM(vcfux, 5, 12),
9058 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9059 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9060 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9061
9062 #undef GEN_VAFORM_PAIRED
9063 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9064 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9065 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9066 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9067 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9068 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9069 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9070 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9071
9072 #undef GEN_SPE
9073 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
9074 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type)
9075 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE),
9076 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE),
9077 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE),
9078 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE),
9079 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE),
9080 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE),
9081 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE),
9082 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE),
9083 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, PPC_SPE),
9084 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE),
9085 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE),
9086 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE),
9087 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE),
9088 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE),
9089 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE),
9090 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE),
9091 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE),
9092 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE),
9093 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE),
9094 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE),
9095 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE),
9096 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE),
9097 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE),
9098 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE),
9099 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE),
9100 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE),
9101 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE),
9102 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE),
9103 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE),
9104
9105 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE),
9106 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE),
9107 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE),
9108 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE),
9109 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE),
9110 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE),
9111 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE),
9112 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE),
9113 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE),
9114 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE),
9115 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE),
9116 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE),
9117 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE),
9118 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE),
9119
9120 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE),
9121 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE),
9122 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE),
9123 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE),
9124 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE),
9125 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE),
9126 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE),
9127 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE),
9128 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE),
9129 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE),
9130 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE),
9131 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE),
9132 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE),
9133 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE),
9134
9135 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE),
9136 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9137 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE),
9138 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE),
9139 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE),
9140 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9141 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
9142 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
9143 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9144 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9145 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9146 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9147 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9148 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9149 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
9150 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
9151
9152 #undef GEN_SPEOP_LDST
9153 #define GEN_SPEOP_LDST(name, opc2, sh) \
9154 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9155 GEN_SPEOP_LDST(evldd, 0x00, 3),
9156 GEN_SPEOP_LDST(evldw, 0x01, 3),
9157 GEN_SPEOP_LDST(evldh, 0x02, 3),
9158 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9159 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9160 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9161 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9162 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9163 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9164 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9165 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9166
9167 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9168 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9169 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9170 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9171 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9172 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9173 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9174 };
9175
9176 #include "translate_init.c"
9177 #include "helper_regs.h"
9178
9179 /*****************************************************************************/
9180 /* Misc PowerPC helpers */
9181 void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
9182 int flags)
9183 {
9184 #define RGPL 4
9185 #define RFPL 4
9186
9187 int i;
9188
9189 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9190 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9191 env->nip, env->lr, env->ctr, env->xer);
9192 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9193 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9194 env->hflags, env->mmu_idx);
9195 #if !defined(NO_TIMER_DUMP)
9196 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9197 #if !defined(CONFIG_USER_ONLY)
9198 " DECR %08" PRIu32
9199 #endif
9200 "\n",
9201 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9202 #if !defined(CONFIG_USER_ONLY)
9203 , cpu_ppc_load_decr(env)
9204 #endif
9205 );
9206 #endif
9207 for (i = 0; i < 32; i++) {
9208 if ((i & (RGPL - 1)) == 0)
9209 cpu_fprintf(f, "GPR%02d", i);
9210 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9211 if ((i & (RGPL - 1)) == (RGPL - 1))
9212 cpu_fprintf(f, "\n");
9213 }
9214 cpu_fprintf(f, "CR ");
9215 for (i = 0; i < 8; i++)
9216 cpu_fprintf(f, "%01x", env->crf[i]);
9217 cpu_fprintf(f, " [");
9218 for (i = 0; i < 8; i++) {
9219 char a = '-';
9220 if (env->crf[i] & 0x08)
9221 a = 'L';
9222 else if (env->crf[i] & 0x04)
9223 a = 'G';
9224 else if (env->crf[i] & 0x02)
9225 a = 'E';
9226 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9227 }
9228 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9229 env->reserve_addr);
9230 for (i = 0; i < 32; i++) {
9231 if ((i & (RFPL - 1)) == 0)
9232 cpu_fprintf(f, "FPR%02d", i);
9233 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9234 if ((i & (RFPL - 1)) == (RFPL - 1))
9235 cpu_fprintf(f, "\n");
9236 }
9237 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
9238 #if !defined(CONFIG_USER_ONLY)
9239 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9240 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9241 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9242 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9243
9244 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9245 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9246 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9247 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9248
9249 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9250 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9251 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9252 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9253
9254 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9255 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9256 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9257 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9258 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9259
9260 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9261 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9262 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9263 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9264
9265 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9266 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9267 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9268 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9269
9270 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9271 " EPR " TARGET_FMT_lx "\n",
9272 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9273 env->spr[SPR_BOOKE_EPR]);
9274
9275 /* FSL-specific */
9276 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9277 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9278 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9279 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9280
9281 /*
9282 * IVORs are left out as they are large and do not change often --
9283 * they can be read with "p $ivor0", "p $ivor1", etc.
9284 */
9285 }
9286
9287 #if defined(TARGET_PPC64)
9288 if (env->flags & POWERPC_FLAG_CFAR) {
9289 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9290 }
9291 #endif
9292
9293 switch (env->mmu_model) {
9294 case POWERPC_MMU_32B:
9295 case POWERPC_MMU_601:
9296 case POWERPC_MMU_SOFT_6xx:
9297 case POWERPC_MMU_SOFT_74xx:
9298 #if defined(TARGET_PPC64)
9299 case POWERPC_MMU_620:
9300 case POWERPC_MMU_64B:
9301 #endif
9302 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9303 break;
9304 case POWERPC_MMU_BOOKE206:
9305 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9306 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9307 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9308 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9309
9310 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9311 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9312 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9313 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9314
9315 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9316 " TLB1CFG " TARGET_FMT_lx "\n",
9317 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9318 env->spr[SPR_BOOKE_TLB1CFG]);
9319 break;
9320 default:
9321 break;
9322 }
9323 #endif
9324
9325 #undef RGPL
9326 #undef RFPL
9327 }
9328
9329 void cpu_dump_statistics (CPUState *env, FILE*f, fprintf_function cpu_fprintf,
9330 int flags)
9331 {
9332 #if defined(DO_PPC_STATISTICS)
9333 opc_handler_t **t1, **t2, **t3, *handler;
9334 int op1, op2, op3;
9335
9336 t1 = env->opcodes;
9337 for (op1 = 0; op1 < 64; op1++) {
9338 handler = t1[op1];
9339 if (is_indirect_opcode(handler)) {
9340 t2 = ind_table(handler);
9341 for (op2 = 0; op2 < 32; op2++) {
9342 handler = t2[op2];
9343 if (is_indirect_opcode(handler)) {
9344 t3 = ind_table(handler);
9345 for (op3 = 0; op3 < 32; op3++) {
9346 handler = t3[op3];
9347 if (handler->count == 0)
9348 continue;
9349 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9350 "%016" PRIx64 " %" PRId64 "\n",
9351 op1, op2, op3, op1, (op3 << 5) | op2,
9352 handler->oname,
9353 handler->count, handler->count);
9354 }
9355 } else {
9356 if (handler->count == 0)
9357 continue;
9358 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9359 "%016" PRIx64 " %" PRId64 "\n",
9360 op1, op2, op1, op2, handler->oname,
9361 handler->count, handler->count);
9362 }
9363 }
9364 } else {
9365 if (handler->count == 0)
9366 continue;
9367 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9368 " %" PRId64 "\n",
9369 op1, op1, handler->oname,
9370 handler->count, handler->count);
9371 }
9372 }
9373 #endif
9374 }
9375
9376 /*****************************************************************************/
9377 static inline void gen_intermediate_code_internal(CPUState *env,
9378 TranslationBlock *tb,
9379 int search_pc)
9380 {
9381 DisasContext ctx, *ctxp = &ctx;
9382 opc_handler_t **table, *handler;
9383 target_ulong pc_start;
9384 uint16_t *gen_opc_end;
9385 CPUBreakpoint *bp;
9386 int j, lj = -1;
9387 int num_insns;
9388 int max_insns;
9389
9390 pc_start = tb->pc;
9391 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9392 ctx.nip = pc_start;
9393 ctx.tb = tb;
9394 ctx.exception = POWERPC_EXCP_NONE;
9395 ctx.spr_cb = env->spr_cb;
9396 ctx.mem_idx = env->mmu_idx;
9397 ctx.access_type = -1;
9398 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9399 #if defined(TARGET_PPC64)
9400 ctx.sf_mode = msr_sf;
9401 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9402 #endif
9403 ctx.fpu_enabled = msr_fp;
9404 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9405 ctx.spe_enabled = msr_spe;
9406 else
9407 ctx.spe_enabled = 0;
9408 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9409 ctx.altivec_enabled = msr_vr;
9410 else
9411 ctx.altivec_enabled = 0;
9412 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9413 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9414 else
9415 ctx.singlestep_enabled = 0;
9416 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9417 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9418 if (unlikely(env->singlestep_enabled))
9419 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9420 #if defined (DO_SINGLE_STEP) && 0
9421 /* Single step trace mode */
9422 msr_se = 1;
9423 #endif
9424 num_insns = 0;
9425 max_insns = tb->cflags & CF_COUNT_MASK;
9426 if (max_insns == 0)
9427 max_insns = CF_COUNT_MASK;
9428
9429 gen_icount_start();
9430 /* Set env in case of segfault during code fetch */
9431 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
9432 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9433 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9434 if (bp->pc == ctx.nip) {
9435 gen_debug_exception(ctxp);
9436 break;
9437 }
9438 }
9439 }
9440 if (unlikely(search_pc)) {
9441 j = gen_opc_ptr - gen_opc_buf;
9442 if (lj < j) {
9443 lj++;
9444 while (lj < j)
9445 gen_opc_instr_start[lj++] = 0;
9446 }
9447 gen_opc_pc[lj] = ctx.nip;
9448 gen_opc_instr_start[lj] = 1;
9449 gen_opc_icount[lj] = num_insns;
9450 }
9451 LOG_DISAS("----------------\n");
9452 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9453 ctx.nip, ctx.mem_idx, (int)msr_ir);
9454 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9455 gen_io_start();
9456 if (unlikely(ctx.le_mode)) {
9457 ctx.opcode = bswap32(ldl_code(ctx.nip));
9458 } else {
9459 ctx.opcode = ldl_code(ctx.nip);
9460 }
9461 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9462 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9463 opc3(ctx.opcode), little_endian ? "little" : "big");
9464 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
9465 tcg_gen_debug_insn_start(ctx.nip);
9466 ctx.nip += 4;
9467 table = env->opcodes;
9468 num_insns++;
9469 handler = table[opc1(ctx.opcode)];
9470 if (is_indirect_opcode(handler)) {
9471 table = ind_table(handler);
9472 handler = table[opc2(ctx.opcode)];
9473 if (is_indirect_opcode(handler)) {
9474 table = ind_table(handler);
9475 handler = table[opc3(ctx.opcode)];
9476 }
9477 }
9478 /* Is opcode *REALLY* valid ? */
9479 if (unlikely(handler->handler == &gen_invalid)) {
9480 if (qemu_log_enabled()) {
9481 qemu_log("invalid/unsupported opcode: "
9482 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9483 opc1(ctx.opcode), opc2(ctx.opcode),
9484 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9485 }
9486 } else {
9487 if (unlikely((ctx.opcode & handler->inval) != 0)) {
9488 if (qemu_log_enabled()) {
9489 qemu_log("invalid bits: %08x for opcode: "
9490 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9491 ctx.opcode & handler->inval, opc1(ctx.opcode),
9492 opc2(ctx.opcode), opc3(ctx.opcode),
9493 ctx.opcode, ctx.nip - 4);
9494 }
9495 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9496 break;
9497 }
9498 }
9499 (*(handler->handler))(&ctx);
9500 #if defined(DO_PPC_STATISTICS)
9501 handler->count++;
9502 #endif
9503 /* Check trace mode exceptions */
9504 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9505 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9506 ctx.exception != POWERPC_SYSCALL &&
9507 ctx.exception != POWERPC_EXCP_TRAP &&
9508 ctx.exception != POWERPC_EXCP_BRANCH)) {
9509 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9510 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9511 (env->singlestep_enabled) ||
9512 singlestep ||
9513 num_insns >= max_insns)) {
9514 /* if we reach a page boundary or are single stepping, stop
9515 * generation
9516 */
9517 break;
9518 }
9519 }
9520 if (tb->cflags & CF_LAST_IO)
9521 gen_io_end();
9522 if (ctx.exception == POWERPC_EXCP_NONE) {
9523 gen_goto_tb(&ctx, 0, ctx.nip);
9524 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9525 if (unlikely(env->singlestep_enabled)) {
9526 gen_debug_exception(ctxp);
9527 }
9528 /* Generate the return instruction */
9529 tcg_gen_exit_tb(0);
9530 }
9531 gen_icount_end(tb, num_insns);
9532 *gen_opc_ptr = INDEX_op_end;
9533 if (unlikely(search_pc)) {
9534 j = gen_opc_ptr - gen_opc_buf;
9535 lj++;
9536 while (lj <= j)
9537 gen_opc_instr_start[lj++] = 0;
9538 } else {
9539 tb->size = ctx.nip - pc_start;
9540 tb->icount = num_insns;
9541 }
9542 #if defined(DEBUG_DISAS)
9543 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9544 int flags;
9545 flags = env->bfd_mach;
9546 flags |= ctx.le_mode << 16;
9547 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9548 log_target_disas(pc_start, ctx.nip - pc_start, flags);
9549 qemu_log("\n");
9550 }
9551 #endif
9552 }
9553
9554 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
9555 {
9556 gen_intermediate_code_internal(env, tb, 0);
9557 }
9558
9559 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
9560 {
9561 gen_intermediate_code_internal(env, tb, 1);
9562 }
9563
9564 void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
9565 {
9566 env->nip = gen_opc_pc[pc_pos];
9567 }
Qemu copy for testing