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Fix PowerPC FPSCR update and floating-point exception generation
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29
30 /* Include definitions for instructions classes and implementations flags */
31 //#define DO_SINGLE_STEP
32 //#define PPC_DEBUG_DISAS
33 //#define DEBUG_MEMORY_ACCESSES
34 //#define DO_PPC_STATISTICS
35 //#define OPTIMIZE_FPRF_UPDATE
36
37 /*****************************************************************************/
38 /* Code translation helpers */
39 #if defined(USE_DIRECT_JUMP)
40 #define TBPARAM(x)
41 #else
42 #define TBPARAM(x) (long)(x)
43 #endif
44
45 enum {
46 #define DEF(s, n, copy_size) INDEX_op_ ## s,
47 #include "opc.h"
48 #undef DEF
49 NB_OPS,
50 };
51
52 static uint16_t *gen_opc_ptr;
53 static uint32_t *gen_opparam_ptr;
54 #if defined(OPTIMIZE_FPRF_UPDATE)
55 static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
56 static uint16_t **gen_fprf_ptr;
57 #endif
58
59 #include "gen-op.h"
60
61 static always_inline void gen_set_T0 (target_ulong val)
62 {
63 #if defined(TARGET_PPC64)
64 if (val >> 32)
65 gen_op_set_T0_64(val >> 32, val);
66 else
67 #endif
68 gen_op_set_T0(val);
69 }
70
71 static always_inline void gen_set_T1 (target_ulong val)
72 {
73 #if defined(TARGET_PPC64)
74 if (val >> 32)
75 gen_op_set_T1_64(val >> 32, val);
76 else
77 #endif
78 gen_op_set_T1(val);
79 }
80
81 #define GEN8(func, NAME) \
82 static GenOpFunc *NAME ## _table [8] = { \
83 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
84 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
85 }; \
86 static always_inline void func (int n) \
87 { \
88 NAME ## _table[n](); \
89 }
90
91 #define GEN16(func, NAME) \
92 static GenOpFunc *NAME ## _table [16] = { \
93 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
94 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
95 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
96 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
97 }; \
98 static always_inline void func (int n) \
99 { \
100 NAME ## _table[n](); \
101 }
102
103 #define GEN32(func, NAME) \
104 static GenOpFunc *NAME ## _table [32] = { \
105 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
106 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
107 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
108 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
109 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
110 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
111 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
112 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
113 }; \
114 static always_inline void func (int n) \
115 { \
116 NAME ## _table[n](); \
117 }
118
119 /* Condition register moves */
120 GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
121 GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
122 GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
123 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
124
125 /* General purpose registers moves */
126 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
127 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
128 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
129
130 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
131 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
132 #if 0 // unused
133 GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
134 #endif
135
136 /* floating point registers moves */
137 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
138 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
139 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
140 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
141 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
142 #if 0 // unused
143 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
144 #endif
145
146 /* internal defines */
147 typedef struct DisasContext {
148 struct TranslationBlock *tb;
149 target_ulong nip;
150 uint32_t opcode;
151 uint32_t exception;
152 /* Routine used to access memory */
153 int mem_idx;
154 /* Translation flags */
155 #if !defined(CONFIG_USER_ONLY)
156 int supervisor;
157 #endif
158 #if defined(TARGET_PPC64)
159 int sf_mode;
160 #endif
161 int fpu_enabled;
162 int altivec_enabled;
163 #if defined(TARGET_PPCEMB)
164 int spe_enabled;
165 #endif
166 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
167 int singlestep_enabled;
168 int dcache_line_size;
169 } DisasContext;
170
171 struct opc_handler_t {
172 /* invalid bits */
173 uint32_t inval;
174 /* instruction type */
175 uint64_t type;
176 /* handler */
177 void (*handler)(DisasContext *ctx);
178 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
179 const unsigned char *oname;
180 #endif
181 #if defined(DO_PPC_STATISTICS)
182 uint64_t count;
183 #endif
184 };
185
186 static always_inline void gen_set_Rc0 (DisasContext *ctx)
187 {
188 #if defined(TARGET_PPC64)
189 if (ctx->sf_mode)
190 gen_op_cmpi_64(0);
191 else
192 #endif
193 gen_op_cmpi(0);
194 gen_op_set_Rc0();
195 }
196
197 static always_inline void gen_reset_fpstatus (void)
198 {
199 #ifdef CONFIG_SOFTFLOAT
200 gen_op_reset_fpstatus();
201 #endif
202 }
203
204 static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
205 {
206 if (set_fprf != 0) {
207 /* This case might be optimized later */
208 #if defined(OPTIMIZE_FPRF_UPDATE)
209 *gen_fprf_ptr++ = gen_opc_ptr;
210 #endif
211 gen_op_compute_fprf(1);
212 if (unlikely(set_rc))
213 gen_op_store_T0_crf(1);
214 gen_op_float_check_status();
215 } else if (unlikely(set_rc)) {
216 /* We always need to compute fpcc */
217 gen_op_compute_fprf(0);
218 gen_op_store_T0_crf(1);
219 if (set_fprf)
220 gen_op_float_check_status();
221 }
222 }
223
224 static always_inline void gen_optimize_fprf (void)
225 {
226 #if defined(OPTIMIZE_FPRF_UPDATE)
227 uint16_t **ptr;
228
229 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
230 *ptr = INDEX_op_nop1;
231 gen_fprf_ptr = gen_fprf_buf;
232 #endif
233 }
234
235 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
236 {
237 #if defined(TARGET_PPC64)
238 if (ctx->sf_mode)
239 gen_op_update_nip_64(nip >> 32, nip);
240 else
241 #endif
242 gen_op_update_nip(nip);
243 }
244
245 #define GEN_EXCP(ctx, excp, error) \
246 do { \
247 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
248 gen_update_nip(ctx, (ctx)->nip); \
249 } \
250 gen_op_raise_exception_err((excp), (error)); \
251 ctx->exception = (excp); \
252 } while (0)
253
254 #define GEN_EXCP_INVAL(ctx) \
255 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
256 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
257
258 #define GEN_EXCP_PRIVOPC(ctx) \
259 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
260 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
261
262 #define GEN_EXCP_PRIVREG(ctx) \
263 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
264 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
265
266 #define GEN_EXCP_NO_FP(ctx) \
267 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
268
269 #define GEN_EXCP_NO_AP(ctx) \
270 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
271
272 #define GEN_EXCP_NO_VR(ctx) \
273 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
274
275 /* Stop translation */
276 static always_inline void GEN_STOP (DisasContext *ctx)
277 {
278 gen_update_nip(ctx, ctx->nip);
279 ctx->exception = POWERPC_EXCP_STOP;
280 }
281
282 /* No need to update nip here, as execution flow will change */
283 static always_inline void GEN_SYNC (DisasContext *ctx)
284 {
285 ctx->exception = POWERPC_EXCP_SYNC;
286 }
287
288 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
289 static void gen_##name (DisasContext *ctx); \
290 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
291 static void gen_##name (DisasContext *ctx)
292
293 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
294 static void gen_##name (DisasContext *ctx); \
295 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
296 static void gen_##name (DisasContext *ctx)
297
298
299 typedef struct opcode_t {
300 unsigned char opc1, opc2, opc3;
301 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
302 unsigned char pad[5];
303 #else
304 unsigned char pad[1];
305 #endif
306 opc_handler_t handler;
307 const unsigned char *oname;
308 } opcode_t;
309
310 /*****************************************************************************/
311 /*** Instruction decoding ***/
312 #define EXTRACT_HELPER(name, shift, nb) \
313 static always_inline uint32_t name (uint32_t opcode) \
314 { \
315 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
316 }
317
318 #define EXTRACT_SHELPER(name, shift, nb) \
319 static always_inline int32_t name (uint32_t opcode) \
320 { \
321 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
322 }
323
324 /* Opcode part 1 */
325 EXTRACT_HELPER(opc1, 26, 6);
326 /* Opcode part 2 */
327 EXTRACT_HELPER(opc2, 1, 5);
328 /* Opcode part 3 */
329 EXTRACT_HELPER(opc3, 6, 5);
330 /* Update Cr0 flags */
331 EXTRACT_HELPER(Rc, 0, 1);
332 /* Destination */
333 EXTRACT_HELPER(rD, 21, 5);
334 /* Source */
335 EXTRACT_HELPER(rS, 21, 5);
336 /* First operand */
337 EXTRACT_HELPER(rA, 16, 5);
338 /* Second operand */
339 EXTRACT_HELPER(rB, 11, 5);
340 /* Third operand */
341 EXTRACT_HELPER(rC, 6, 5);
342 /*** Get CRn ***/
343 EXTRACT_HELPER(crfD, 23, 3);
344 EXTRACT_HELPER(crfS, 18, 3);
345 EXTRACT_HELPER(crbD, 21, 5);
346 EXTRACT_HELPER(crbA, 16, 5);
347 EXTRACT_HELPER(crbB, 11, 5);
348 /* SPR / TBL */
349 EXTRACT_HELPER(_SPR, 11, 10);
350 static always_inline uint32_t SPR (uint32_t opcode)
351 {
352 uint32_t sprn = _SPR(opcode);
353
354 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
355 }
356 /*** Get constants ***/
357 EXTRACT_HELPER(IMM, 12, 8);
358 /* 16 bits signed immediate value */
359 EXTRACT_SHELPER(SIMM, 0, 16);
360 /* 16 bits unsigned immediate value */
361 EXTRACT_HELPER(UIMM, 0, 16);
362 /* Bit count */
363 EXTRACT_HELPER(NB, 11, 5);
364 /* Shift count */
365 EXTRACT_HELPER(SH, 11, 5);
366 /* Mask start */
367 EXTRACT_HELPER(MB, 6, 5);
368 /* Mask end */
369 EXTRACT_HELPER(ME, 1, 5);
370 /* Trap operand */
371 EXTRACT_HELPER(TO, 21, 5);
372
373 EXTRACT_HELPER(CRM, 12, 8);
374 EXTRACT_HELPER(FM, 17, 8);
375 EXTRACT_HELPER(SR, 16, 4);
376 EXTRACT_HELPER(FPIMM, 20, 4);
377
378 /*** Jump target decoding ***/
379 /* Displacement */
380 EXTRACT_SHELPER(d, 0, 16);
381 /* Immediate address */
382 static always_inline target_ulong LI (uint32_t opcode)
383 {
384 return (opcode >> 0) & 0x03FFFFFC;
385 }
386
387 static always_inline uint32_t BD (uint32_t opcode)
388 {
389 return (opcode >> 0) & 0xFFFC;
390 }
391
392 EXTRACT_HELPER(BO, 21, 5);
393 EXTRACT_HELPER(BI, 16, 5);
394 /* Absolute/relative address */
395 EXTRACT_HELPER(AA, 1, 1);
396 /* Link */
397 EXTRACT_HELPER(LK, 0, 1);
398
399 /* Create a mask between <start> and <end> bits */
400 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
401 {
402 target_ulong ret;
403
404 #if defined(TARGET_PPC64)
405 if (likely(start == 0)) {
406 ret = (uint64_t)(-1ULL) << (63 - end);
407 } else if (likely(end == 63)) {
408 ret = (uint64_t)(-1ULL) >> start;
409 }
410 #else
411 if (likely(start == 0)) {
412 ret = (uint32_t)(-1ULL) << (31 - end);
413 } else if (likely(end == 31)) {
414 ret = (uint32_t)(-1ULL) >> start;
415 }
416 #endif
417 else {
418 ret = (((target_ulong)(-1ULL)) >> (start)) ^
419 (((target_ulong)(-1ULL) >> (end)) >> 1);
420 if (unlikely(start > end))
421 return ~ret;
422 }
423
424 return ret;
425 }
426
427 /*****************************************************************************/
428 /* PowerPC Instructions types definitions */
429 enum {
430 PPC_NONE = 0x0000000000000000ULL,
431 /* PowerPC base instructions set */
432 PPC_INSNS_BASE = 0x0000000000000001ULL,
433 /* integer operations instructions */
434 #define PPC_INTEGER PPC_INSNS_BASE
435 /* flow control instructions */
436 #define PPC_FLOW PPC_INSNS_BASE
437 /* virtual memory instructions */
438 #define PPC_MEM PPC_INSNS_BASE
439 /* ld/st with reservation instructions */
440 #define PPC_RES PPC_INSNS_BASE
441 /* cache control instructions */
442 #define PPC_CACHE PPC_INSNS_BASE
443 /* spr/msr access instructions */
444 #define PPC_MISC PPC_INSNS_BASE
445 /* Optional floating point instructions */
446 PPC_FLOAT = 0x0000000000000002ULL,
447 PPC_FLOAT_FSQRT = 0x0000000000000004ULL,
448 PPC_FLOAT_FRES = 0x0000000000000008ULL,
449 PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL,
450 PPC_FLOAT_FSEL = 0x0000000000000020ULL,
451 PPC_FLOAT_STFIWX = 0x0000000000000040ULL,
452 /* external control instructions */
453 PPC_EXTERN = 0x0000000000000080ULL,
454 /* segment register access instructions */
455 PPC_SEGMENT = 0x0000000000000100ULL,
456 /* Optional cache control instruction */
457 PPC_CACHE_DCBA = 0x0000000000000200ULL,
458 /* Optional memory control instructions */
459 PPC_MEM_TLBIA = 0x0000000000000400ULL,
460 PPC_MEM_TLBIE = 0x0000000000000800ULL,
461 PPC_MEM_TLBSYNC = 0x0000000000001000ULL,
462 /* eieio & sync */
463 PPC_MEM_SYNC = 0x0000000000002000ULL,
464 /* PowerPC 6xx TLB management instructions */
465 PPC_6xx_TLB = 0x0000000000004000ULL,
466 /* Altivec support */
467 PPC_ALTIVEC = 0x0000000000008000ULL,
468 /* Time base mftb instruction */
469 PPC_MFTB = 0x0000000000010000ULL,
470 /* Embedded PowerPC dedicated instructions */
471 PPC_EMB_COMMON = 0x0000000000020000ULL,
472 /* PowerPC 40x exception model */
473 PPC_40x_EXCP = 0x0000000000040000ULL,
474 /* PowerPC 40x TLB management instructions */
475 PPC_40x_TLB = 0x0000000000080000ULL,
476 /* PowerPC 405 Mac instructions */
477 PPC_405_MAC = 0x0000000000100000ULL,
478 /* PowerPC 440 specific instructions */
479 PPC_440_SPEC = 0x0000000000200000ULL,
480 /* Power-to-PowerPC bridge (601) */
481 PPC_POWER_BR = 0x0000000000400000ULL,
482 /* PowerPC 602 specific */
483 PPC_602_SPEC = 0x0000000000800000ULL,
484 /* Deprecated instructions */
485 /* Original POWER instruction set */
486 PPC_POWER = 0x0000000001000000ULL,
487 /* POWER2 instruction set extension */
488 PPC_POWER2 = 0x0000000002000000ULL,
489 /* Power RTC support */
490 PPC_POWER_RTC = 0x0000000004000000ULL,
491 /* 64 bits PowerPC instruction set */
492 PPC_64B = 0x0000000008000000ULL,
493 /* 64 bits hypervisor extensions */
494 PPC_64H = 0x0000000010000000ULL,
495 /* segment register access instructions for PowerPC 64 "bridge" */
496 PPC_SEGMENT_64B = 0x0000000020000000ULL,
497 /* BookE (embedded) PowerPC specification */
498 PPC_BOOKE = 0x0000000040000000ULL,
499 /* eieio */
500 PPC_MEM_EIEIO = 0x0000000080000000ULL,
501 /* e500 vector instructions */
502 PPC_E500_VECTOR = 0x0000000100000000ULL,
503 /* PowerPC 4xx dedicated instructions */
504 PPC_4xx_COMMON = 0x0000000200000000ULL,
505 /* PowerPC 2.03 specification extensions */
506 PPC_203 = 0x0000000400000000ULL,
507 /* PowerPC 2.03 SPE extension */
508 PPC_SPE = 0x0000000800000000ULL,
509 /* PowerPC 2.03 SPE floating-point extension */
510 PPC_SPEFPU = 0x0000001000000000ULL,
511 /* SLB management */
512 PPC_SLBI = 0x0000002000000000ULL,
513 /* PowerPC 40x ibct instructions */
514 PPC_40x_ICBT = 0x0000004000000000ULL,
515 /* PowerPC 74xx TLB management instructions */
516 PPC_74xx_TLB = 0x0000008000000000ULL,
517 /* More BookE (embedded) instructions... */
518 PPC_BOOKE_EXT = 0x0000010000000000ULL,
519 /* rfmci is not implemented in all BookE PowerPC */
520 PPC_RFMCI = 0x0000020000000000ULL,
521 /* user-mode DCR access, implemented in PowerPC 460 */
522 PPC_DCRUX = 0x0000040000000000ULL,
523 /* New floating-point extensions (PowerPC 2.0x) */
524 PPC_FLOAT_EXT = 0x0000080000000000ULL,
525 /* New wait instruction (PowerPC 2.0x) */
526 PPC_WAIT = 0x0000100000000000ULL,
527 /* New 64 bits extensions (PowerPC 2.0x) */
528 PPC_64BX = 0x0000200000000000ULL,
529 /* dcbz instruction with fixed cache line size */
530 PPC_CACHE_DCBZ = 0x0000400000000000ULL,
531 /* dcbz instruction with tunable cache line size */
532 PPC_CACHE_DCBZT = 0x0000800000000000ULL,
533 /* frsqrtes extension */
534 PPC_FLOAT_FRSQRTES = 0x0001000000000000ULL,
535 };
536
537 /*****************************************************************************/
538 /* PowerPC instructions table */
539 #if HOST_LONG_BITS == 64
540 #define OPC_ALIGN 8
541 #else
542 #define OPC_ALIGN 4
543 #endif
544 #if defined(__APPLE__)
545 #define OPCODES_SECTION \
546 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
547 #else
548 #define OPCODES_SECTION \
549 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
550 #endif
551
552 #if defined(DO_PPC_STATISTICS)
553 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
554 OPCODES_SECTION opcode_t opc_##name = { \
555 .opc1 = op1, \
556 .opc2 = op2, \
557 .opc3 = op3, \
558 .pad = { 0, }, \
559 .handler = { \
560 .inval = invl, \
561 .type = _typ, \
562 .handler = &gen_##name, \
563 .oname = stringify(name), \
564 }, \
565 .oname = stringify(name), \
566 }
567 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
568 OPCODES_SECTION opcode_t opc_##name = { \
569 .opc1 = op1, \
570 .opc2 = op2, \
571 .opc3 = op3, \
572 .pad = { 0, }, \
573 .handler = { \
574 .inval = invl, \
575 .type = _typ, \
576 .handler = &gen_##name, \
577 .oname = onam, \
578 }, \
579 .oname = onam, \
580 }
581 #else
582 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
583 OPCODES_SECTION opcode_t opc_##name = { \
584 .opc1 = op1, \
585 .opc2 = op2, \
586 .opc3 = op3, \
587 .pad = { 0, }, \
588 .handler = { \
589 .inval = invl, \
590 .type = _typ, \
591 .handler = &gen_##name, \
592 }, \
593 .oname = stringify(name), \
594 }
595 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
596 OPCODES_SECTION opcode_t opc_##name = { \
597 .opc1 = op1, \
598 .opc2 = op2, \
599 .opc3 = op3, \
600 .pad = { 0, }, \
601 .handler = { \
602 .inval = invl, \
603 .type = _typ, \
604 .handler = &gen_##name, \
605 }, \
606 .oname = onam, \
607 }
608 #endif
609
610 #define GEN_OPCODE_MARK(name) \
611 OPCODES_SECTION opcode_t opc_##name = { \
612 .opc1 = 0xFF, \
613 .opc2 = 0xFF, \
614 .opc3 = 0xFF, \
615 .pad = { 0, }, \
616 .handler = { \
617 .inval = 0x00000000, \
618 .type = 0x00, \
619 .handler = NULL, \
620 }, \
621 .oname = stringify(name), \
622 }
623
624 /* Start opcode list */
625 GEN_OPCODE_MARK(start);
626
627 /* Invalid instruction */
628 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
629 {
630 GEN_EXCP_INVAL(ctx);
631 }
632
633 static opc_handler_t invalid_handler = {
634 .inval = 0xFFFFFFFF,
635 .type = PPC_NONE,
636 .handler = gen_invalid,
637 };
638
639 /*** Integer arithmetic ***/
640 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
641 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
642 { \
643 gen_op_load_gpr_T0(rA(ctx->opcode)); \
644 gen_op_load_gpr_T1(rB(ctx->opcode)); \
645 gen_op_##name(); \
646 gen_op_store_T0_gpr(rD(ctx->opcode)); \
647 if (unlikely(Rc(ctx->opcode) != 0)) \
648 gen_set_Rc0(ctx); \
649 }
650
651 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
652 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
653 { \
654 gen_op_load_gpr_T0(rA(ctx->opcode)); \
655 gen_op_load_gpr_T1(rB(ctx->opcode)); \
656 gen_op_##name(); \
657 gen_op_store_T0_gpr(rD(ctx->opcode)); \
658 if (unlikely(Rc(ctx->opcode) != 0)) \
659 gen_set_Rc0(ctx); \
660 }
661
662 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
663 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
664 { \
665 gen_op_load_gpr_T0(rA(ctx->opcode)); \
666 gen_op_##name(); \
667 gen_op_store_T0_gpr(rD(ctx->opcode)); \
668 if (unlikely(Rc(ctx->opcode) != 0)) \
669 gen_set_Rc0(ctx); \
670 }
671 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
672 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
673 { \
674 gen_op_load_gpr_T0(rA(ctx->opcode)); \
675 gen_op_##name(); \
676 gen_op_store_T0_gpr(rD(ctx->opcode)); \
677 if (unlikely(Rc(ctx->opcode) != 0)) \
678 gen_set_Rc0(ctx); \
679 }
680
681 /* Two operands arithmetic functions */
682 #define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
683 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
684 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
685
686 /* Two operands arithmetic functions with no overflow allowed */
687 #define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
688 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
689
690 /* One operand arithmetic functions */
691 #define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
692 __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
693 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
694
695 #if defined(TARGET_PPC64)
696 #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
697 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
698 { \
699 gen_op_load_gpr_T0(rA(ctx->opcode)); \
700 gen_op_load_gpr_T1(rB(ctx->opcode)); \
701 if (ctx->sf_mode) \
702 gen_op_##name##_64(); \
703 else \
704 gen_op_##name(); \
705 gen_op_store_T0_gpr(rD(ctx->opcode)); \
706 if (unlikely(Rc(ctx->opcode) != 0)) \
707 gen_set_Rc0(ctx); \
708 }
709
710 #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
711 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
712 { \
713 gen_op_load_gpr_T0(rA(ctx->opcode)); \
714 gen_op_load_gpr_T1(rB(ctx->opcode)); \
715 if (ctx->sf_mode) \
716 gen_op_##name##_64(); \
717 else \
718 gen_op_##name(); \
719 gen_op_store_T0_gpr(rD(ctx->opcode)); \
720 if (unlikely(Rc(ctx->opcode) != 0)) \
721 gen_set_Rc0(ctx); \
722 }
723
724 #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
725 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
726 { \
727 gen_op_load_gpr_T0(rA(ctx->opcode)); \
728 if (ctx->sf_mode) \
729 gen_op_##name##_64(); \
730 else \
731 gen_op_##name(); \
732 gen_op_store_T0_gpr(rD(ctx->opcode)); \
733 if (unlikely(Rc(ctx->opcode) != 0)) \
734 gen_set_Rc0(ctx); \
735 }
736 #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
737 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
738 { \
739 gen_op_load_gpr_T0(rA(ctx->opcode)); \
740 if (ctx->sf_mode) \
741 gen_op_##name##_64(); \
742 else \
743 gen_op_##name(); \
744 gen_op_store_T0_gpr(rD(ctx->opcode)); \
745 if (unlikely(Rc(ctx->opcode) != 0)) \
746 gen_set_Rc0(ctx); \
747 }
748
749 /* Two operands arithmetic functions */
750 #define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
751 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
752 __GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
753
754 /* Two operands arithmetic functions with no overflow allowed */
755 #define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
756 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
757
758 /* One operand arithmetic functions */
759 #define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
760 __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
761 __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
762 #else
763 #define GEN_INT_ARITH2_64 GEN_INT_ARITH2
764 #define GEN_INT_ARITHN_64 GEN_INT_ARITHN
765 #define GEN_INT_ARITH1_64 GEN_INT_ARITH1
766 #endif
767
768 /* add add. addo addo. */
769 static always_inline void gen_op_addo (void)
770 {
771 gen_op_move_T2_T0();
772 gen_op_add();
773 gen_op_check_addo();
774 }
775 #if defined(TARGET_PPC64)
776 #define gen_op_add_64 gen_op_add
777 static always_inline void gen_op_addo_64 (void)
778 {
779 gen_op_move_T2_T0();
780 gen_op_add();
781 gen_op_check_addo_64();
782 }
783 #endif
784 GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
785 /* addc addc. addco addco. */
786 static always_inline void gen_op_addc (void)
787 {
788 gen_op_move_T2_T0();
789 gen_op_add();
790 gen_op_check_addc();
791 }
792 static always_inline void gen_op_addco (void)
793 {
794 gen_op_move_T2_T0();
795 gen_op_add();
796 gen_op_check_addc();
797 gen_op_check_addo();
798 }
799 #if defined(TARGET_PPC64)
800 static always_inline void gen_op_addc_64 (void)
801 {
802 gen_op_move_T2_T0();
803 gen_op_add();
804 gen_op_check_addc_64();
805 }
806 static always_inline void gen_op_addco_64 (void)
807 {
808 gen_op_move_T2_T0();
809 gen_op_add();
810 gen_op_check_addc_64();
811 gen_op_check_addo_64();
812 }
813 #endif
814 GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
815 /* adde adde. addeo addeo. */
816 static always_inline void gen_op_addeo (void)
817 {
818 gen_op_move_T2_T0();
819 gen_op_adde();
820 gen_op_check_addo();
821 }
822 #if defined(TARGET_PPC64)
823 static always_inline void gen_op_addeo_64 (void)
824 {
825 gen_op_move_T2_T0();
826 gen_op_adde_64();
827 gen_op_check_addo_64();
828 }
829 #endif
830 GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
831 /* addme addme. addmeo addmeo. */
832 static always_inline void gen_op_addme (void)
833 {
834 gen_op_move_T1_T0();
835 gen_op_add_me();
836 }
837 #if defined(TARGET_PPC64)
838 static always_inline void gen_op_addme_64 (void)
839 {
840 gen_op_move_T1_T0();
841 gen_op_add_me_64();
842 }
843 #endif
844 GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
845 /* addze addze. addzeo addzeo. */
846 static always_inline void gen_op_addze (void)
847 {
848 gen_op_move_T2_T0();
849 gen_op_add_ze();
850 gen_op_check_addc();
851 }
852 static always_inline void gen_op_addzeo (void)
853 {
854 gen_op_move_T2_T0();
855 gen_op_add_ze();
856 gen_op_check_addc();
857 gen_op_check_addo();
858 }
859 #if defined(TARGET_PPC64)
860 static always_inline void gen_op_addze_64 (void)
861 {
862 gen_op_move_T2_T0();
863 gen_op_add_ze();
864 gen_op_check_addc_64();
865 }
866 static always_inline void gen_op_addzeo_64 (void)
867 {
868 gen_op_move_T2_T0();
869 gen_op_add_ze();
870 gen_op_check_addc_64();
871 gen_op_check_addo_64();
872 }
873 #endif
874 GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
875 /* divw divw. divwo divwo. */
876 GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
877 /* divwu divwu. divwuo divwuo. */
878 GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
879 /* mulhw mulhw. */
880 GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
881 /* mulhwu mulhwu. */
882 GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
883 /* mullw mullw. mullwo mullwo. */
884 GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
885 /* neg neg. nego nego. */
886 GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
887 /* subf subf. subfo subfo. */
888 static always_inline void gen_op_subfo (void)
889 {
890 gen_op_move_T2_T0();
891 gen_op_subf();
892 gen_op_check_subfo();
893 }
894 #if defined(TARGET_PPC64)
895 #define gen_op_subf_64 gen_op_subf
896 static always_inline void gen_op_subfo_64 (void)
897 {
898 gen_op_move_T2_T0();
899 gen_op_subf();
900 gen_op_check_subfo_64();
901 }
902 #endif
903 GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
904 /* subfc subfc. subfco subfco. */
905 static always_inline void gen_op_subfc (void)
906 {
907 gen_op_subf();
908 gen_op_check_subfc();
909 }
910 static always_inline void gen_op_subfco (void)
911 {
912 gen_op_move_T2_T0();
913 gen_op_subf();
914 gen_op_check_subfc();
915 gen_op_check_subfo();
916 }
917 #if defined(TARGET_PPC64)
918 static always_inline void gen_op_subfc_64 (void)
919 {
920 gen_op_subf();
921 gen_op_check_subfc_64();
922 }
923 static always_inline void gen_op_subfco_64 (void)
924 {
925 gen_op_move_T2_T0();
926 gen_op_subf();
927 gen_op_check_subfc_64();
928 gen_op_check_subfo_64();
929 }
930 #endif
931 GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
932 /* subfe subfe. subfeo subfeo. */
933 static always_inline void gen_op_subfeo (void)
934 {
935 gen_op_move_T2_T0();
936 gen_op_subfe();
937 gen_op_check_subfo();
938 }
939 #if defined(TARGET_PPC64)
940 #define gen_op_subfe_64 gen_op_subfe
941 static always_inline void gen_op_subfeo_64 (void)
942 {
943 gen_op_move_T2_T0();
944 gen_op_subfe_64();
945 gen_op_check_subfo_64();
946 }
947 #endif
948 GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
949 /* subfme subfme. subfmeo subfmeo. */
950 GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
951 /* subfze subfze. subfzeo subfzeo. */
952 GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
953 /* addi */
954 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
955 {
956 target_long simm = SIMM(ctx->opcode);
957
958 if (rA(ctx->opcode) == 0) {
959 /* li case */
960 gen_set_T0(simm);
961 } else {
962 gen_op_load_gpr_T0(rA(ctx->opcode));
963 if (likely(simm != 0))
964 gen_op_addi(simm);
965 }
966 gen_op_store_T0_gpr(rD(ctx->opcode));
967 }
968 /* addic */
969 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
970 {
971 target_long simm = SIMM(ctx->opcode);
972
973 gen_op_load_gpr_T0(rA(ctx->opcode));
974 if (likely(simm != 0)) {
975 gen_op_move_T2_T0();
976 gen_op_addi(simm);
977 #if defined(TARGET_PPC64)
978 if (ctx->sf_mode)
979 gen_op_check_addc_64();
980 else
981 #endif
982 gen_op_check_addc();
983 } else {
984 gen_op_clear_xer_ca();
985 }
986 gen_op_store_T0_gpr(rD(ctx->opcode));
987 }
988 /* addic. */
989 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
990 {
991 target_long simm = SIMM(ctx->opcode);
992
993 gen_op_load_gpr_T0(rA(ctx->opcode));
994 if (likely(simm != 0)) {
995 gen_op_move_T2_T0();
996 gen_op_addi(simm);
997 #if defined(TARGET_PPC64)
998 if (ctx->sf_mode)
999 gen_op_check_addc_64();
1000 else
1001 #endif
1002 gen_op_check_addc();
1003 } else {
1004 gen_op_clear_xer_ca();
1005 }
1006 gen_op_store_T0_gpr(rD(ctx->opcode));
1007 gen_set_Rc0(ctx);
1008 }
1009 /* addis */
1010 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1011 {
1012 target_long simm = SIMM(ctx->opcode);
1013
1014 if (rA(ctx->opcode) == 0) {
1015 /* lis case */
1016 gen_set_T0(simm << 16);
1017 } else {
1018 gen_op_load_gpr_T0(rA(ctx->opcode));
1019 if (likely(simm != 0))
1020 gen_op_addi(simm << 16);
1021 }
1022 gen_op_store_T0_gpr(rD(ctx->opcode));
1023 }
1024 /* mulli */
1025 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1026 {
1027 gen_op_load_gpr_T0(rA(ctx->opcode));
1028 gen_op_mulli(SIMM(ctx->opcode));
1029 gen_op_store_T0_gpr(rD(ctx->opcode));
1030 }
1031 /* subfic */
1032 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1033 {
1034 gen_op_load_gpr_T0(rA(ctx->opcode));
1035 #if defined(TARGET_PPC64)
1036 if (ctx->sf_mode)
1037 gen_op_subfic_64(SIMM(ctx->opcode));
1038 else
1039 #endif
1040 gen_op_subfic(SIMM(ctx->opcode));
1041 gen_op_store_T0_gpr(rD(ctx->opcode));
1042 }
1043
1044 #if defined(TARGET_PPC64)
1045 /* mulhd mulhd. */
1046 GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
1047 /* mulhdu mulhdu. */
1048 GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
1049 /* mulld mulld. mulldo mulldo. */
1050 GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
1051 /* divd divd. divdo divdo. */
1052 GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
1053 /* divdu divdu. divduo divduo. */
1054 GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
1055 #endif
1056
1057 /*** Integer comparison ***/
1058 #if defined(TARGET_PPC64)
1059 #define GEN_CMP(name, opc, type) \
1060 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1061 { \
1062 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1063 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1064 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
1065 gen_op_##name##_64(); \
1066 else \
1067 gen_op_##name(); \
1068 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1069 }
1070 #else
1071 #define GEN_CMP(name, opc, type) \
1072 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1073 { \
1074 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1075 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1076 gen_op_##name(); \
1077 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1078 }
1079 #endif
1080
1081 /* cmp */
1082 GEN_CMP(cmp, 0x00, PPC_INTEGER);
1083 /* cmpi */
1084 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1085 {
1086 gen_op_load_gpr_T0(rA(ctx->opcode));
1087 #if defined(TARGET_PPC64)
1088 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1089 gen_op_cmpi_64(SIMM(ctx->opcode));
1090 else
1091 #endif
1092 gen_op_cmpi(SIMM(ctx->opcode));
1093 gen_op_store_T0_crf(crfD(ctx->opcode));
1094 }
1095 /* cmpl */
1096 GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1097 /* cmpli */
1098 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1099 {
1100 gen_op_load_gpr_T0(rA(ctx->opcode));
1101 #if defined(TARGET_PPC64)
1102 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1103 gen_op_cmpli_64(UIMM(ctx->opcode));
1104 else
1105 #endif
1106 gen_op_cmpli(UIMM(ctx->opcode));
1107 gen_op_store_T0_crf(crfD(ctx->opcode));
1108 }
1109
1110 /* isel (PowerPC 2.03 specification) */
1111 GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
1112 {
1113 uint32_t bi = rC(ctx->opcode);
1114 uint32_t mask;
1115
1116 if (rA(ctx->opcode) == 0) {
1117 gen_set_T0(0);
1118 } else {
1119 gen_op_load_gpr_T1(rA(ctx->opcode));
1120 }
1121 gen_op_load_gpr_T2(rB(ctx->opcode));
1122 mask = 1 << (3 - (bi & 0x03));
1123 gen_op_load_crf_T0(bi >> 2);
1124 gen_op_test_true(mask);
1125 gen_op_isel();
1126 gen_op_store_T0_gpr(rD(ctx->opcode));
1127 }
1128
1129 /*** Integer logical ***/
1130 #define __GEN_LOGICAL2(name, opc2, opc3, type) \
1131 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
1132 { \
1133 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1134 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1135 gen_op_##name(); \
1136 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1137 if (unlikely(Rc(ctx->opcode) != 0)) \
1138 gen_set_Rc0(ctx); \
1139 }
1140 #define GEN_LOGICAL2(name, opc, type) \
1141 __GEN_LOGICAL2(name, 0x1C, opc, type)
1142
1143 #define GEN_LOGICAL1(name, opc, type) \
1144 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1145 { \
1146 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1147 gen_op_##name(); \
1148 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1149 if (unlikely(Rc(ctx->opcode) != 0)) \
1150 gen_set_Rc0(ctx); \
1151 }
1152
1153 /* and & and. */
1154 GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
1155 /* andc & andc. */
1156 GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1157 /* andi. */
1158 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1159 {
1160 gen_op_load_gpr_T0(rS(ctx->opcode));
1161 gen_op_andi_T0(UIMM(ctx->opcode));
1162 gen_op_store_T0_gpr(rA(ctx->opcode));
1163 gen_set_Rc0(ctx);
1164 }
1165 /* andis. */
1166 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1167 {
1168 gen_op_load_gpr_T0(rS(ctx->opcode));
1169 gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1170 gen_op_store_T0_gpr(rA(ctx->opcode));
1171 gen_set_Rc0(ctx);
1172 }
1173
1174 /* cntlzw */
1175 GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
1176 /* eqv & eqv. */
1177 GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
1178 /* extsb & extsb. */
1179 GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
1180 /* extsh & extsh. */
1181 GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
1182 /* nand & nand. */
1183 GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
1184 /* nor & nor. */
1185 GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
1186
1187 /* or & or. */
1188 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1189 {
1190 int rs, ra, rb;
1191
1192 rs = rS(ctx->opcode);
1193 ra = rA(ctx->opcode);
1194 rb = rB(ctx->opcode);
1195 /* Optimisation for mr. ri case */
1196 if (rs != ra || rs != rb) {
1197 gen_op_load_gpr_T0(rs);
1198 if (rs != rb) {
1199 gen_op_load_gpr_T1(rb);
1200 gen_op_or();
1201 }
1202 gen_op_store_T0_gpr(ra);
1203 if (unlikely(Rc(ctx->opcode) != 0))
1204 gen_set_Rc0(ctx);
1205 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1206 gen_op_load_gpr_T0(rs);
1207 gen_set_Rc0(ctx);
1208 #if defined(TARGET_PPC64)
1209 } else {
1210 switch (rs) {
1211 case 1:
1212 /* Set process priority to low */
1213 gen_op_store_pri(2);
1214 break;
1215 case 6:
1216 /* Set process priority to medium-low */
1217 gen_op_store_pri(3);
1218 break;
1219 case 2:
1220 /* Set process priority to normal */
1221 gen_op_store_pri(4);
1222 break;
1223 #if !defined(CONFIG_USER_ONLY)
1224 case 31:
1225 if (ctx->supervisor > 0) {
1226 /* Set process priority to very low */
1227 gen_op_store_pri(1);
1228 }
1229 break;
1230 case 5:
1231 if (ctx->supervisor > 0) {
1232 /* Set process priority to medium-hight */
1233 gen_op_store_pri(5);
1234 }
1235 break;
1236 case 3:
1237 if (ctx->supervisor > 0) {
1238 /* Set process priority to high */
1239 gen_op_store_pri(6);
1240 }
1241 break;
1242 #if defined(TARGET_PPC64H)
1243 case 7:
1244 if (ctx->supervisor > 1) {
1245 /* Set process priority to very high */
1246 gen_op_store_pri(7);
1247 }
1248 break;
1249 #endif
1250 #endif
1251 default:
1252 /* nop */
1253 break;
1254 }
1255 #endif
1256 }
1257 }
1258
1259 /* orc & orc. */
1260 GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1261 /* xor & xor. */
1262 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1263 {
1264 gen_op_load_gpr_T0(rS(ctx->opcode));
1265 /* Optimisation for "set to zero" case */
1266 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1267 gen_op_load_gpr_T1(rB(ctx->opcode));
1268 gen_op_xor();
1269 } else {
1270 gen_op_reset_T0();
1271 }
1272 gen_op_store_T0_gpr(rA(ctx->opcode));
1273 if (unlikely(Rc(ctx->opcode) != 0))
1274 gen_set_Rc0(ctx);
1275 }
1276 /* ori */
1277 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1278 {
1279 target_ulong uimm = UIMM(ctx->opcode);
1280
1281 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1282 /* NOP */
1283 /* XXX: should handle special NOPs for POWER series */
1284 return;
1285 }
1286 gen_op_load_gpr_T0(rS(ctx->opcode));
1287 if (likely(uimm != 0))
1288 gen_op_ori(uimm);
1289 gen_op_store_T0_gpr(rA(ctx->opcode));
1290 }
1291 /* oris */
1292 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1293 {
1294 target_ulong uimm = UIMM(ctx->opcode);
1295
1296 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1297 /* NOP */
1298 return;
1299 }
1300 gen_op_load_gpr_T0(rS(ctx->opcode));
1301 if (likely(uimm != 0))
1302 gen_op_ori(uimm << 16);
1303 gen_op_store_T0_gpr(rA(ctx->opcode));
1304 }
1305 /* xori */
1306 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1307 {
1308 target_ulong uimm = UIMM(ctx->opcode);
1309
1310 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1311 /* NOP */
1312 return;
1313 }
1314 gen_op_load_gpr_T0(rS(ctx->opcode));
1315 if (likely(uimm != 0))
1316 gen_op_xori(uimm);
1317 gen_op_store_T0_gpr(rA(ctx->opcode));
1318 }
1319
1320 /* xoris */
1321 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1322 {
1323 target_ulong uimm = UIMM(ctx->opcode);
1324
1325 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1326 /* NOP */
1327 return;
1328 }
1329 gen_op_load_gpr_T0(rS(ctx->opcode));
1330 if (likely(uimm != 0))
1331 gen_op_xori(uimm << 16);
1332 gen_op_store_T0_gpr(rA(ctx->opcode));
1333 }
1334
1335 /* popcntb : PowerPC 2.03 specification */
1336 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
1337 {
1338 gen_op_load_gpr_T0(rS(ctx->opcode));
1339 #if defined(TARGET_PPC64)
1340 if (ctx->sf_mode)
1341 gen_op_popcntb_64();
1342 else
1343 #endif
1344 gen_op_popcntb();
1345 gen_op_store_T0_gpr(rA(ctx->opcode));
1346 }
1347
1348 #if defined(TARGET_PPC64)
1349 /* extsw & extsw. */
1350 GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1351 /* cntlzd */
1352 GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1353 #endif
1354
1355 /*** Integer rotate ***/
1356 /* rlwimi & rlwimi. */
1357 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1358 {
1359 target_ulong mask;
1360 uint32_t mb, me, sh;
1361
1362 mb = MB(ctx->opcode);
1363 me = ME(ctx->opcode);
1364 sh = SH(ctx->opcode);
1365 if (likely(sh == 0)) {
1366 if (likely(mb == 0 && me == 31)) {
1367 gen_op_load_gpr_T0(rS(ctx->opcode));
1368 goto do_store;
1369 } else if (likely(mb == 31 && me == 0)) {
1370 gen_op_load_gpr_T0(rA(ctx->opcode));
1371 goto do_store;
1372 }
1373 gen_op_load_gpr_T0(rS(ctx->opcode));
1374 gen_op_load_gpr_T1(rA(ctx->opcode));
1375 goto do_mask;
1376 }
1377 gen_op_load_gpr_T0(rS(ctx->opcode));
1378 gen_op_load_gpr_T1(rA(ctx->opcode));
1379 gen_op_rotli32_T0(SH(ctx->opcode));
1380 do_mask:
1381 #if defined(TARGET_PPC64)
1382 mb += 32;
1383 me += 32;
1384 #endif
1385 mask = MASK(mb, me);
1386 gen_op_andi_T0(mask);
1387 gen_op_andi_T1(~mask);
1388 gen_op_or();
1389 do_store:
1390 gen_op_store_T0_gpr(rA(ctx->opcode));
1391 if (unlikely(Rc(ctx->opcode) != 0))
1392 gen_set_Rc0(ctx);
1393 }
1394 /* rlwinm & rlwinm. */
1395 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1396 {
1397 uint32_t mb, me, sh;
1398
1399 sh = SH(ctx->opcode);
1400 mb = MB(ctx->opcode);
1401 me = ME(ctx->opcode);
1402 gen_op_load_gpr_T0(rS(ctx->opcode));
1403 if (likely(sh == 0)) {
1404 goto do_mask;
1405 }
1406 if (likely(mb == 0)) {
1407 if (likely(me == 31)) {
1408 gen_op_rotli32_T0(sh);
1409 goto do_store;
1410 } else if (likely(me == (31 - sh))) {
1411 gen_op_sli_T0(sh);
1412 goto do_store;
1413 }
1414 } else if (likely(me == 31)) {
1415 if (likely(sh == (32 - mb))) {
1416 gen_op_srli_T0(mb);
1417 goto do_store;
1418 }
1419 }
1420 gen_op_rotli32_T0(sh);
1421 do_mask:
1422 #if defined(TARGET_PPC64)
1423 mb += 32;
1424 me += 32;
1425 #endif
1426 gen_op_andi_T0(MASK(mb, me));
1427 do_store:
1428 gen_op_store_T0_gpr(rA(ctx->opcode));
1429 if (unlikely(Rc(ctx->opcode) != 0))
1430 gen_set_Rc0(ctx);
1431 }
1432 /* rlwnm & rlwnm. */
1433 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1434 {
1435 uint32_t mb, me;
1436
1437 mb = MB(ctx->opcode);
1438 me = ME(ctx->opcode);
1439 gen_op_load_gpr_T0(rS(ctx->opcode));
1440 gen_op_load_gpr_T1(rB(ctx->opcode));
1441 gen_op_rotl32_T0_T1();
1442 if (unlikely(mb != 0 || me != 31)) {
1443 #if defined(TARGET_PPC64)
1444 mb += 32;
1445 me += 32;
1446 #endif
1447 gen_op_andi_T0(MASK(mb, me));
1448 }
1449 gen_op_store_T0_gpr(rA(ctx->opcode));
1450 if (unlikely(Rc(ctx->opcode) != 0))
1451 gen_set_Rc0(ctx);
1452 }
1453
1454 #if defined(TARGET_PPC64)
1455 #define GEN_PPC64_R2(name, opc1, opc2) \
1456 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1457 { \
1458 gen_##name(ctx, 0); \
1459 } \
1460 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1461 PPC_64B) \
1462 { \
1463 gen_##name(ctx, 1); \
1464 }
1465 #define GEN_PPC64_R4(name, opc1, opc2) \
1466 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1467 { \
1468 gen_##name(ctx, 0, 0); \
1469 } \
1470 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1471 PPC_64B) \
1472 { \
1473 gen_##name(ctx, 0, 1); \
1474 } \
1475 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1476 PPC_64B) \
1477 { \
1478 gen_##name(ctx, 1, 0); \
1479 } \
1480 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1481 PPC_64B) \
1482 { \
1483 gen_##name(ctx, 1, 1); \
1484 }
1485
1486 static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1487 {
1488 if (mask >> 32)
1489 gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1490 else
1491 gen_op_andi_T0(mask);
1492 }
1493
1494 static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1495 {
1496 if (mask >> 32)
1497 gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1498 else
1499 gen_op_andi_T1(mask);
1500 }
1501
1502 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1503 uint32_t me, uint32_t sh)
1504 {
1505 gen_op_load_gpr_T0(rS(ctx->opcode));
1506 if (likely(sh == 0)) {
1507 goto do_mask;
1508 }
1509 if (likely(mb == 0)) {
1510 if (likely(me == 63)) {
1511 gen_op_rotli64_T0(sh);
1512 goto do_store;
1513 } else if (likely(me == (63 - sh))) {
1514 gen_op_sli_T0(sh);
1515 goto do_store;
1516 }
1517 } else if (likely(me == 63)) {
1518 if (likely(sh == (64 - mb))) {
1519 gen_op_srli_T0_64(mb);
1520 goto do_store;
1521 }
1522 }
1523 gen_op_rotli64_T0(sh);
1524 do_mask:
1525 gen_andi_T0_64(ctx, MASK(mb, me));
1526 do_store:
1527 gen_op_store_T0_gpr(rA(ctx->opcode));
1528 if (unlikely(Rc(ctx->opcode) != 0))
1529 gen_set_Rc0(ctx);
1530 }
1531 /* rldicl - rldicl. */
1532 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1533 {
1534 uint32_t sh, mb;
1535
1536 sh = SH(ctx->opcode) | (shn << 5);
1537 mb = MB(ctx->opcode) | (mbn << 5);
1538 gen_rldinm(ctx, mb, 63, sh);
1539 }
1540 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1541 /* rldicr - rldicr. */
1542 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1543 {
1544 uint32_t sh, me;
1545
1546 sh = SH(ctx->opcode) | (shn << 5);
1547 me = MB(ctx->opcode) | (men << 5);
1548 gen_rldinm(ctx, 0, me, sh);
1549 }
1550 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1551 /* rldic - rldic. */
1552 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1553 {
1554 uint32_t sh, mb;
1555
1556 sh = SH(ctx->opcode) | (shn << 5);
1557 mb = MB(ctx->opcode) | (mbn << 5);
1558 gen_rldinm(ctx, mb, 63 - sh, sh);
1559 }
1560 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1561
1562 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1563 uint32_t me)
1564 {
1565 gen_op_load_gpr_T0(rS(ctx->opcode));
1566 gen_op_load_gpr_T1(rB(ctx->opcode));
1567 gen_op_rotl64_T0_T1();
1568 if (unlikely(mb != 0 || me != 63)) {
1569 gen_andi_T0_64(ctx, MASK(mb, me));
1570 }
1571 gen_op_store_T0_gpr(rA(ctx->opcode));
1572 if (unlikely(Rc(ctx->opcode) != 0))
1573 gen_set_Rc0(ctx);
1574 }
1575
1576 /* rldcl - rldcl. */
1577 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1578 {
1579 uint32_t mb;
1580
1581 mb = MB(ctx->opcode) | (mbn << 5);
1582 gen_rldnm(ctx, mb, 63);
1583 }
1584 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1585 /* rldcr - rldcr. */
1586 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1587 {
1588 uint32_t me;
1589
1590 me = MB(ctx->opcode) | (men << 5);
1591 gen_rldnm(ctx, 0, me);
1592 }
1593 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1594 /* rldimi - rldimi. */
1595 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1596 {
1597 uint64_t mask;
1598 uint32_t sh, mb;
1599
1600 sh = SH(ctx->opcode) | (shn << 5);
1601 mb = MB(ctx->opcode) | (mbn << 5);
1602 if (likely(sh == 0)) {
1603 if (likely(mb == 0)) {
1604 gen_op_load_gpr_T0(rS(ctx->opcode));
1605 goto do_store;
1606 } else if (likely(mb == 63)) {
1607 gen_op_load_gpr_T0(rA(ctx->opcode));
1608 goto do_store;
1609 }
1610 gen_op_load_gpr_T0(rS(ctx->opcode));
1611 gen_op_load_gpr_T1(rA(ctx->opcode));
1612 goto do_mask;
1613 }
1614 gen_op_load_gpr_T0(rS(ctx->opcode));
1615 gen_op_load_gpr_T1(rA(ctx->opcode));
1616 gen_op_rotli64_T0(sh);
1617 do_mask:
1618 mask = MASK(mb, 63 - sh);
1619 gen_andi_T0_64(ctx, mask);
1620 gen_andi_T1_64(ctx, ~mask);
1621 gen_op_or();
1622 do_store:
1623 gen_op_store_T0_gpr(rA(ctx->opcode));
1624 if (unlikely(Rc(ctx->opcode) != 0))
1625 gen_set_Rc0(ctx);
1626 }
1627 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1628 #endif
1629
1630 /*** Integer shift ***/
1631 /* slw & slw. */
1632 __GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
1633 /* sraw & sraw. */
1634 __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1635 /* srawi & srawi. */
1636 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1637 {
1638 int mb, me;
1639 gen_op_load_gpr_T0(rS(ctx->opcode));
1640 if (SH(ctx->opcode) != 0) {
1641 gen_op_move_T1_T0();
1642 mb = 32 - SH(ctx->opcode);
1643 me = 31;
1644 #if defined(TARGET_PPC64)
1645 mb += 32;
1646 me += 32;
1647 #endif
1648 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1649 }
1650 gen_op_store_T0_gpr(rA(ctx->opcode));
1651 if (unlikely(Rc(ctx->opcode) != 0))
1652 gen_set_Rc0(ctx);
1653 }
1654 /* srw & srw. */
1655 __GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1656
1657 #if defined(TARGET_PPC64)
1658 /* sld & sld. */
1659 __GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1660 /* srad & srad. */
1661 __GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1662 /* sradi & sradi. */
1663 static always_inline void gen_sradi (DisasContext *ctx, int n)
1664 {
1665 uint64_t mask;
1666 int sh, mb, me;
1667
1668 gen_op_load_gpr_T0(rS(ctx->opcode));
1669 sh = SH(ctx->opcode) + (n << 5);
1670 if (sh != 0) {
1671 gen_op_move_T1_T0();
1672 mb = 64 - SH(ctx->opcode);
1673 me = 63;
1674 mask = MASK(mb, me);
1675 gen_op_sradi(sh, mask >> 32, mask);
1676 }
1677 gen_op_store_T0_gpr(rA(ctx->opcode));
1678 if (unlikely(Rc(ctx->opcode) != 0))
1679 gen_set_Rc0(ctx);
1680 }
1681 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1682 {
1683 gen_sradi(ctx, 0);
1684 }
1685 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
1686 {
1687 gen_sradi(ctx, 1);
1688 }
1689 /* srd & srd. */
1690 __GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1691 #endif
1692
1693 /*** Floating-Point arithmetic ***/
1694 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1695 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
1696 { \
1697 if (unlikely(!ctx->fpu_enabled)) { \
1698 GEN_EXCP_NO_FP(ctx); \
1699 return; \
1700 } \
1701 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1702 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1703 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
1704 gen_reset_fpstatus(); \
1705 gen_op_f##op(); \
1706 if (isfloat) { \
1707 gen_op_frsp(); \
1708 } \
1709 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1710 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1711 }
1712
1713 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1714 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1715 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1716
1717 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1718 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1719 { \
1720 if (unlikely(!ctx->fpu_enabled)) { \
1721 GEN_EXCP_NO_FP(ctx); \
1722 return; \
1723 } \
1724 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1725 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
1726 gen_reset_fpstatus(); \
1727 gen_op_f##op(); \
1728 if (isfloat) { \
1729 gen_op_frsp(); \
1730 } \
1731 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1732 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1733 }
1734 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1735 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1736 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1737
1738 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1739 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1740 { \
1741 if (unlikely(!ctx->fpu_enabled)) { \
1742 GEN_EXCP_NO_FP(ctx); \
1743 return; \
1744 } \
1745 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1746 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1747 gen_reset_fpstatus(); \
1748 gen_op_f##op(); \
1749 if (isfloat) { \
1750 gen_op_frsp(); \
1751 } \
1752 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1753 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1754 }
1755 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1756 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1757 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1758
1759 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1760 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
1761 { \
1762 if (unlikely(!ctx->fpu_enabled)) { \
1763 GEN_EXCP_NO_FP(ctx); \
1764 return; \
1765 } \
1766 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1767 gen_reset_fpstatus(); \
1768 gen_op_f##name(); \
1769 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1770 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1771 }
1772
1773 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1774 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
1775 { \
1776 if (unlikely(!ctx->fpu_enabled)) { \
1777 GEN_EXCP_NO_FP(ctx); \
1778 return; \
1779 } \
1780 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1781 gen_reset_fpstatus(); \
1782 gen_op_f##name(); \
1783 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1784 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1785 }
1786
1787 /* fadd - fadds */
1788 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
1789 /* fdiv - fdivs */
1790 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
1791 /* fmul - fmuls */
1792 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
1793
1794 /* fre */
1795 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
1796
1797 /* fres */
1798 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
1799
1800 /* frsqrte */
1801 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1802
1803 /* frsqrtes */
1804 static always_inline void gen_op_frsqrtes (void)
1805 {
1806 gen_op_frsqrte();
1807 gen_op_frsp();
1808 }
1809 GEN_FLOAT_BS(rsqrtes, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTES);
1810
1811 /* fsel */
1812 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
1813 /* fsub - fsubs */
1814 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
1815 /* Optional: */
1816 /* fsqrt */
1817 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1818 {
1819 if (unlikely(!ctx->fpu_enabled)) {
1820 GEN_EXCP_NO_FP(ctx);
1821 return;
1822 }
1823 gen_op_load_fpr_FT0(rB(ctx->opcode));
1824 gen_reset_fpstatus();
1825 gen_op_fsqrt();
1826 gen_op_store_FT0_fpr(rD(ctx->opcode));
1827 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1828 }
1829
1830 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1831 {
1832 if (unlikely(!ctx->fpu_enabled)) {
1833 GEN_EXCP_NO_FP(ctx);
1834 return;
1835 }
1836 gen_op_load_fpr_FT0(rB(ctx->opcode));
1837 gen_reset_fpstatus();
1838 gen_op_fsqrt();
1839 gen_op_frsp();
1840 gen_op_store_FT0_fpr(rD(ctx->opcode));
1841 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1842 }
1843
1844 /*** Floating-Point multiply-and-add ***/
1845 /* fmadd - fmadds */
1846 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
1847 /* fmsub - fmsubs */
1848 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
1849 /* fnmadd - fnmadds */
1850 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
1851 /* fnmsub - fnmsubs */
1852 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
1853
1854 /*** Floating-Point round & convert ***/
1855 /* fctiw */
1856 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
1857 /* fctiwz */
1858 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
1859 /* frsp */
1860 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
1861 #if defined(TARGET_PPC64)
1862 /* fcfid */
1863 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
1864 /* fctid */
1865 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
1866 /* fctidz */
1867 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
1868 #endif
1869
1870 /* frin */
1871 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
1872 /* friz */
1873 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
1874 /* frip */
1875 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
1876 /* frim */
1877 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
1878
1879 /*** Floating-Point compare ***/
1880 /* fcmpo */
1881 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1882 {
1883 if (unlikely(!ctx->fpu_enabled)) {
1884 GEN_EXCP_NO_FP(ctx);
1885 return;
1886 }
1887 gen_op_load_fpr_FT0(rA(ctx->opcode));
1888 gen_op_load_fpr_FT1(rB(ctx->opcode));
1889 gen_reset_fpstatus();
1890 gen_op_fcmpo();
1891 gen_op_store_T0_crf(crfD(ctx->opcode));
1892 gen_op_float_check_status();
1893 }
1894
1895 /* fcmpu */
1896 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1897 {
1898 if (unlikely(!ctx->fpu_enabled)) {
1899 GEN_EXCP_NO_FP(ctx);
1900 return;
1901 }
1902 gen_op_load_fpr_FT0(rA(ctx->opcode));
1903 gen_op_load_fpr_FT1(rB(ctx->opcode));
1904 gen_reset_fpstatus();
1905 gen_op_fcmpu();
1906 gen_op_store_T0_crf(crfD(ctx->opcode));
1907 gen_op_float_check_status();
1908 }
1909
1910 /*** Floating-point move ***/
1911 /* fabs */
1912 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1913 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
1914
1915 /* fmr - fmr. */
1916 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
1917 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1918 {
1919 if (unlikely(!ctx->fpu_enabled)) {
1920 GEN_EXCP_NO_FP(ctx);
1921 return;
1922 }
1923 gen_op_load_fpr_FT0(rB(ctx->opcode));
1924 gen_op_store_FT0_fpr(rD(ctx->opcode));
1925 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1926 }
1927
1928 /* fnabs */
1929 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1930 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
1931 /* fneg */
1932 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1933 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
1934
1935 /*** Floating-Point status & ctrl register ***/
1936 /* mcrfs */
1937 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1938 {
1939 int bfa;
1940
1941 if (unlikely(!ctx->fpu_enabled)) {
1942 GEN_EXCP_NO_FP(ctx);
1943 return;
1944 }
1945 gen_optimize_fprf();
1946 bfa = 4 * (7 - crfS(ctx->opcode));
1947 gen_op_load_fpscr_T0(bfa);
1948 gen_op_store_T0_crf(crfD(ctx->opcode));
1949 gen_op_fpscr_resetbit(~(0xF << bfa));
1950 }
1951
1952 /* mffs */
1953 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1954 {
1955 if (unlikely(!ctx->fpu_enabled)) {
1956 GEN_EXCP_NO_FP(ctx);
1957 return;
1958 }
1959 gen_optimize_fprf();
1960 gen_reset_fpstatus();
1961 gen_op_load_fpscr_FT0();
1962 gen_op_store_FT0_fpr(rD(ctx->opcode));
1963 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1964 }
1965
1966 /* mtfsb0 */
1967 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1968 {
1969 uint8_t crb;
1970
1971 if (unlikely(!ctx->fpu_enabled)) {
1972 GEN_EXCP_NO_FP(ctx);
1973 return;
1974 }
1975 crb = 32 - (crbD(ctx->opcode) >> 2);
1976 gen_optimize_fprf();
1977 gen_reset_fpstatus();
1978 if (likely(crb != 30 && crb != 29))
1979 gen_op_fpscr_resetbit(~(1 << crb));
1980 if (unlikely(Rc(ctx->opcode) != 0)) {
1981 gen_op_load_fpcc();
1982 gen_op_set_Rc0();
1983 }
1984 }
1985
1986 /* mtfsb1 */
1987 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1988 {
1989 uint8_t crb;
1990
1991 if (unlikely(!ctx->fpu_enabled)) {
1992 GEN_EXCP_NO_FP(ctx);
1993 return;
1994 }
1995 crb = 32 - (crbD(ctx->opcode) >> 2);
1996 gen_optimize_fprf();
1997 gen_reset_fpstatus();
1998 /* XXX: we pretend we can only do IEEE floating-point computations */
1999 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2000 gen_op_fpscr_setbit(crb);
2001 if (unlikely(Rc(ctx->opcode) != 0)) {
2002 gen_op_load_fpcc();
2003 gen_op_set_Rc0();
2004 }
2005 /* We can raise a differed exception */
2006 gen_op_float_check_status();
2007 }
2008
2009 /* mtfsf */
2010 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2011 {
2012 if (unlikely(!ctx->fpu_enabled)) {
2013 GEN_EXCP_NO_FP(ctx);
2014 return;
2015 }
2016 gen_optimize_fprf();
2017 gen_op_load_fpr_FT0(rB(ctx->opcode));
2018 gen_reset_fpstatus();
2019 gen_op_store_fpscr(FM(ctx->opcode));
2020 if (unlikely(Rc(ctx->opcode) != 0)) {
2021 gen_op_load_fpcc();
2022 gen_op_set_Rc0();
2023 }
2024 /* We can raise a differed exception */
2025 gen_op_float_check_status();
2026 }
2027
2028 /* mtfsfi */
2029 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2030 {
2031 int bf, sh;
2032
2033 if (unlikely(!ctx->fpu_enabled)) {
2034 GEN_EXCP_NO_FP(ctx);
2035 return;
2036 }
2037 bf = crbD(ctx->opcode) >> 2;
2038 sh = 7 - bf;
2039 gen_optimize_fprf();
2040 gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
2041 gen_reset_fpstatus();
2042 gen_op_store_fpscr(1 << sh);
2043 if (unlikely(Rc(ctx->opcode) != 0)) {
2044 gen_op_load_fpcc();
2045 gen_op_set_Rc0();
2046 }
2047 /* We can raise a differed exception */
2048 gen_op_float_check_status();
2049 }
2050
2051 /*** Addressing modes ***/
2052 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2053 static always_inline void gen_addr_imm_index (DisasContext *ctx,
2054 target_long maskl)
2055 {
2056 target_long simm = SIMM(ctx->opcode);
2057
2058 simm &= ~maskl;
2059 if (rA(ctx->opcode) == 0) {
2060 gen_set_T0(simm);
2061 } else {
2062 gen_op_load_gpr_T0(rA(ctx->opcode));
2063 if (likely(simm != 0))
2064 gen_op_addi(simm);
2065 }
2066 #ifdef DEBUG_MEMORY_ACCESSES
2067 gen_op_print_mem_EA();
2068 #endif
2069 }
2070
2071 static always_inline void gen_addr_reg_index (DisasContext *ctx)
2072 {
2073 if (rA(ctx->opcode) == 0) {
2074 gen_op_load_gpr_T0(rB(ctx->opcode));
2075 } else {
2076 gen_op_load_gpr_T0(rA(ctx->opcode));
2077 gen_op_load_gpr_T1(rB(ctx->opcode));
2078 gen_op_add();
2079 }
2080 #ifdef DEBUG_MEMORY_ACCESSES
2081 gen_op_print_mem_EA();
2082 #endif
2083 }
2084
2085 static always_inline void gen_addr_register (DisasContext *ctx)
2086 {
2087 if (rA(ctx->opcode) == 0) {
2088 gen_op_reset_T0();
2089 } else {
2090 gen_op_load_gpr_T0(rA(ctx->opcode));
2091 }
2092 #ifdef DEBUG_MEMORY_ACCESSES
2093 gen_op_print_mem_EA();
2094 #endif
2095 }
2096
2097 /*** Integer load ***/
2098 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
2099 #if defined(CONFIG_USER_ONLY)
2100 #if defined(TARGET_PPC64)
2101 /* User mode only - 64 bits */
2102 #define OP_LD_TABLE(width) \
2103 static GenOpFunc *gen_op_l##width[] = { \
2104 &gen_op_l##width##_raw, \
2105 &gen_op_l##width##_le_raw, \
2106 &gen_op_l##width##_64_raw, \
2107 &gen_op_l##width##_le_64_raw, \
2108 };
2109 #define OP_ST_TABLE(width) \
2110 static GenOpFunc *gen_op_st##width[] = { \
2111 &gen_op_st##width##_raw, \
2112 &gen_op_st##width##_le_raw, \
2113 &gen_op_st##width##_64_raw, \
2114 &gen_op_st##width##_le_64_raw, \
2115 };
2116 /* Byte access routine are endian safe */
2117 #define gen_op_stb_le_64_raw gen_op_stb_64_raw
2118 #define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2119 #else
2120 /* User mode only - 32 bits */
2121 #define OP_LD_TABLE(width) \
2122 static GenOpFunc *gen_op_l##width[] = { \
2123 &gen_op_l##width##_raw, \
2124 &gen_op_l##width##_le_raw, \
2125 };
2126 #define OP_ST_TABLE(width) \
2127 static GenOpFunc *gen_op_st##width[] = { \
2128 &gen_op_st##width##_raw, \
2129 &gen_op_st##width##_le_raw, \
2130 };
2131 #endif
2132 /* Byte access routine are endian safe */
2133 #define gen_op_stb_le_raw gen_op_stb_raw
2134 #define gen_op_lbz_le_raw gen_op_lbz_raw
2135 #else
2136 #if defined(TARGET_PPC64)
2137 #if defined(TARGET_PPC64H)
2138 /* Full system - 64 bits with hypervisor mode */
2139 #define OP_LD_TABLE(width) \
2140 static GenOpFunc *gen_op_l##width[] = { \
2141 &gen_op_l##width##_user, \
2142 &gen_op_l##width##_le_user, \
2143 &gen_op_l##width##_64_user, \
2144 &gen_op_l##width##_le_64_user, \
2145 &gen_op_l##width##_kernel, \
2146 &gen_op_l##width##_le_kernel, \
2147 &gen_op_l##width##_64_kernel, \
2148 &gen_op_l##width##_le_64_kernel, \
2149 &gen_op_l##width##_hypv, \
2150 &gen_op_l##width##_le_hypv, \
2151 &gen_op_l##width##_64_hypv, \
2152 &gen_op_l##width##_le_64_hypv, \
2153 };
2154 #define OP_ST_TABLE(width) \
2155 static GenOpFunc *gen_op_st##width[] = { \
2156 &gen_op_st##width##_user, \
2157 &gen_op_st##width##_le_user, \
2158 &gen_op_st##width##_64_user, \
2159 &gen_op_st##width##_le_64_user, \
2160 &gen_op_st##width##_kernel, \
2161 &gen_op_st##width##_le_kernel, \
2162 &gen_op_st##width##_64_kernel, \
2163 &gen_op_st##width##_le_64_kernel, \
2164 &gen_op_st##width##_hypv, \
2165 &gen_op_st##width##_le_hypv, \
2166 &gen_op_st##width##_64_hypv, \
2167 &gen_op_st##width##_le_64_hypv, \
2168 };
2169 /* Byte access routine are endian safe */
2170 #define gen_op_stb_le_hypv gen_op_stb_64_hypv
2171 #define gen_op_lbz_le_hypv gen_op_lbz_64_hypv
2172 #define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
2173 #define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2174 #else
2175 /* Full system - 64 bits */
2176 #define OP_LD_TABLE(width) \
2177 static GenOpFunc *gen_op_l##width[] = { \
2178 &gen_op_l##width##_user, \
2179 &gen_op_l##width##_le_user, \
2180 &gen_op_l##width##_64_user, \
2181 &gen_op_l##width##_le_64_user, \
2182 &gen_op_l##width##_kernel, \
2183 &gen_op_l##width##_le_kernel, \
2184 &gen_op_l##width##_64_kernel, \
2185 &gen_op_l##width##_le_64_kernel, \
2186 };
2187 #define OP_ST_TABLE(width) \
2188 static GenOpFunc *gen_op_st##width[] = { \
2189 &gen_op_st##width##_user, \
2190 &gen_op_st##width##_le_user, \
2191 &gen_op_st##width##_64_user, \
2192 &gen_op_st##width##_le_64_user, \
2193 &gen_op_st##width##_kernel, \
2194 &gen_op_st##width##_le_kernel, \
2195 &gen_op_st##width##_64_kernel, \
2196 &gen_op_st##width##_le_64_kernel, \
2197 };
2198 #endif
2199 /* Byte access routine are endian safe */
2200 #define gen_op_stb_le_64_user gen_op_stb_64_user
2201 #define gen_op_lbz_le_64_user gen_op_lbz_64_user
2202 #define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2203 #define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2204 #else
2205 /* Full system - 32 bits */
2206 #define OP_LD_TABLE(width) \
2207 static GenOpFunc *gen_op_l##width[] = { \
2208 &gen_op_l##width##_user, \
2209 &gen_op_l##width##_le_user, \
2210 &gen_op_l##width##_kernel, \
2211 &gen_op_l##width##_le_kernel, \
2212 };
2213 #define OP_ST_TABLE(width) \
2214 static GenOpFunc *gen_op_st##width[] = { \
2215 &gen_op_st##width##_user, \
2216 &gen_op_st##width##_le_user, \
2217 &gen_op_st##width##_kernel, \
2218 &gen_op_st##width##_le_kernel, \
2219 };
2220 #endif
2221 /* Byte access routine are endian safe */
2222 #define gen_op_stb_le_user gen_op_stb_user
2223 #define gen_op_lbz_le_user gen_op_lbz_user
2224 #define gen_op_stb_le_kernel gen_op_stb_kernel
2225 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
2226 #endif
2227
2228 #define GEN_LD(width, opc, type) \
2229 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2230 { \
2231 gen_addr_imm_index(ctx, 0); \
2232 op_ldst(l##width); \
2233 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2234 }
2235
2236 #define GEN_LDU(width, opc, type) \
2237 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2238 { \
2239 if (unlikely(rA(ctx->opcode) == 0 || \
2240 rA(ctx->opcode) == rD(ctx->opcode))) { \
2241 GEN_EXCP_INVAL(ctx); \
2242 return; \
2243 } \
2244 if (type == PPC_64B) \
2245 gen_addr_imm_index(ctx, 0x03); \
2246 else \
2247 gen_addr_imm_index(ctx, 0); \
2248 op_ldst(l##width); \
2249 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2250 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2251 }
2252
2253 #define GEN_LDUX(width, opc2, opc3, type) \
2254 GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2255 { \
2256 if (unlikely(rA(ctx->opcode) == 0 || \
2257 rA(ctx->opcode) == rD(ctx->opcode))) { \
2258 GEN_EXCP_INVAL(ctx); \
2259 return; \
2260 } \
2261 gen_addr_reg_index(ctx); \
2262 op_ldst(l##width); \
2263 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2264 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2265 }
2266
2267 #define GEN_LDX(width, opc2, opc3, type) \
2268 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2269 { \
2270 gen_addr_reg_index(ctx); \
2271 op_ldst(l##width); \
2272 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2273 }
2274
2275 #define GEN_LDS(width, op, type) \
2276 OP_LD_TABLE(width); \
2277 GEN_LD(width, op | 0x20, type); \
2278 GEN_LDU(width, op | 0x21, type); \
2279 GEN_LDUX(width, 0x17, op | 0x01, type); \
2280 GEN_LDX(width, 0x17, op | 0x00, type)
2281
2282 /* lbz lbzu lbzux lbzx */
2283 GEN_LDS(bz, 0x02, PPC_INTEGER);
2284 /* lha lhau lhaux lhax */
2285 GEN_LDS(ha, 0x0A, PPC_INTEGER);
2286 /* lhz lhzu lhzux lhzx */
2287 GEN_LDS(hz, 0x08, PPC_INTEGER);
2288 /* lwz lwzu lwzux lwzx */
2289 GEN_LDS(wz, 0x00, PPC_INTEGER);
2290 #if defined(TARGET_PPC64)
2291 OP_LD_TABLE(wa);
2292 OP_LD_TABLE(d);
2293 /* lwaux */
2294 GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2295 /* lwax */
2296 GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2297 /* ldux */
2298 GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2299 /* ldx */
2300 GEN_LDX(d, 0x15, 0x00, PPC_64B);
2301 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2302 {
2303 if (Rc(ctx->opcode)) {
2304 if (unlikely(rA(ctx->opcode) == 0 ||
2305 rA(ctx->opcode) == rD(ctx->opcode))) {
2306 GEN_EXCP_INVAL(ctx);
2307 return;
2308 }
2309 }
2310 gen_addr_imm_index(ctx, 0x03);
2311 if (ctx->opcode & 0x02) {
2312 /* lwa (lwau is undefined) */
2313 op_ldst(lwa);
2314 } else {
2315 /* ld - ldu */
2316 op_ldst(ld);
2317 }
2318 gen_op_store_T1_gpr(rD(ctx->opcode));
2319 if (Rc(ctx->opcode))
2320 gen_op_store_T0_gpr(rA(ctx->opcode));
2321 }
2322 /* lq */
2323 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2324 {
2325 #if defined(CONFIG_USER_ONLY)
2326 GEN_EXCP_PRIVOPC(ctx);
2327 #else
2328 int ra, rd;
2329
2330 /* Restore CPU state */
2331 if (unlikely(ctx->supervisor == 0)) {
2332 GEN_EXCP_PRIVOPC(ctx);
2333 return;
2334 }
2335 ra = rA(ctx->opcode);
2336 rd = rD(ctx->opcode);
2337 if (unlikely((rd & 1) || rd == ra)) {
2338 GEN_EXCP_INVAL(ctx);
2339 return;
2340 }
2341 if (unlikely(ctx->mem_idx & 1)) {
2342 /* Little-endian mode is not handled */
2343 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2344 return;
2345 }
2346 gen_addr_imm_index(ctx, 0x0F);
2347 op_ldst(ld);
2348 gen_op_store_T1_gpr(rd);
2349 gen_op_addi(8);
2350 op_ldst(ld);
2351 gen_op_store_T1_gpr(rd + 1);
2352 #endif
2353 }
2354 #endif
2355
2356 /*** Integer store ***/
2357 #define GEN_ST(width, opc, type) \
2358 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2359 { \
2360 gen_addr_imm_index(ctx, 0); \
2361 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2362 op_ldst(st##width); \
2363 }
2364
2365 #define GEN_STU(width, opc, type) \
2366 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2367 { \
2368 if (unlikely(rA(ctx->opcode) == 0)) { \
2369 GEN_EXCP_INVAL(ctx); \
2370 return; \
2371 } \
2372 if (type == PPC_64B) \
2373 gen_addr_imm_index(ctx, 0x03); \
2374 else \
2375 gen_addr_imm_index(ctx, 0); \
2376 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2377 op_ldst(st##width); \
2378 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2379 }
2380
2381 #define GEN_STUX(width, opc2, opc3, type) \
2382 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2383 { \
2384 if (unlikely(rA(ctx->opcode) == 0)) { \
2385 GEN_EXCP_INVAL(ctx); \
2386 return; \
2387 } \
2388 gen_addr_reg_index(ctx); \
2389 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2390 op_ldst(st##width); \
2391 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2392 }
2393
2394 #define GEN_STX(width, opc2, opc3, type) \
2395 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2396 { \
2397 gen_addr_reg_index(ctx); \
2398 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2399 op_ldst(st##width); \
2400 }
2401
2402 #define GEN_STS(width, op, type) \
2403 OP_ST_TABLE(width); \
2404 GEN_ST(width, op | 0x20, type); \
2405 GEN_STU(width, op | 0x21, type); \
2406 GEN_STUX(width, 0x17, op | 0x01, type); \
2407 GEN_STX(width, 0x17, op | 0x00, type)
2408
2409 /* stb stbu stbux stbx */
2410 GEN_STS(b, 0x06, PPC_INTEGER);
2411 /* sth sthu sthux sthx */
2412 GEN_STS(h, 0x0C, PPC_INTEGER);
2413 /* stw stwu stwux stwx */
2414 GEN_STS(w, 0x04, PPC_INTEGER);
2415 #if defined(TARGET_PPC64)
2416 OP_ST_TABLE(d);
2417 GEN_STUX(d, 0x15, 0x05, PPC_64B);
2418 GEN_STX(d, 0x15, 0x04, PPC_64B);
2419 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2420 {
2421 int rs;
2422
2423 rs = rS(ctx->opcode);
2424 if ((ctx->opcode & 0x3) == 0x2) {
2425 #if defined(CONFIG_USER_ONLY)
2426 GEN_EXCP_PRIVOPC(ctx);
2427 #else
2428 /* stq */
2429 if (unlikely(ctx->supervisor == 0)) {
2430 GEN_EXCP_PRIVOPC(ctx);
2431 return;
2432 }
2433 if (unlikely(rs & 1)) {
2434 GEN_EXCP_INVAL(ctx);
2435 return;
2436 }
2437 if (unlikely(ctx->mem_idx & 1)) {
2438 /* Little-endian mode is not handled */
2439 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2440 return;
2441 }
2442 gen_addr_imm_index(ctx, 0x03);
2443 gen_op_load_gpr_T1(rs);
2444 op_ldst(std);
2445 gen_op_addi(8);
2446 gen_op_load_gpr_T1(rs + 1);
2447 op_ldst(std);
2448 #endif
2449 } else {
2450 /* std / stdu */
2451 if (Rc(ctx->opcode)) {
2452 if (unlikely(rA(ctx->opcode) == 0)) {
2453 GEN_EXCP_INVAL(ctx);
2454 return;
2455 }
2456 }
2457 gen_addr_imm_index(ctx, 0x03);
2458 gen_op_load_gpr_T1(rs);
2459 op_ldst(std);
2460 if (Rc(ctx->opcode))
2461 gen_op_store_T0_gpr(rA(ctx->opcode));
2462 }
2463 }
2464 #endif
2465 /*** Integer load and store with byte reverse ***/
2466 /* lhbrx */
2467 OP_LD_TABLE(hbr);
2468 GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
2469 /* lwbrx */
2470 OP_LD_TABLE(wbr);
2471 GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
2472 /* sthbrx */
2473 OP_ST_TABLE(hbr);
2474 GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
2475 /* stwbrx */
2476 OP_ST_TABLE(wbr);
2477 GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
2478
2479 /*** Integer load and store multiple ***/
2480 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2481 #if defined(CONFIG_USER_ONLY)
2482 /* User-mode only */
2483 static GenOpFunc1 *gen_op_lmw[] = {
2484 &gen_op_lmw_raw,
2485 &gen_op_lmw_le_raw,
2486 #if defined(TARGET_PPC64)
2487 &gen_op_lmw_64_raw,
2488 &gen_op_lmw_le_64_raw,
2489 #endif
2490 };
2491 static GenOpFunc1 *gen_op_stmw[] = {
2492 &gen_op_stmw_raw,
2493 &gen_op_stmw_le_raw,
2494 #if defined(TARGET_PPC64)
2495 &gen_op_stmw_64_raw,
2496 &gen_op_stmw_le_64_raw,
2497 #endif
2498 };
2499 #else
2500 #if defined(TARGET_PPC64)
2501 /* Full system - 64 bits mode */
2502 static GenOpFunc1 *gen_op_lmw[] = {
2503 &gen_op_lmw_user,
2504 &gen_op_lmw_le_user,
2505 &gen_op_lmw_64_user,
2506 &gen_op_lmw_le_64_user,
2507 &gen_op_lmw_kernel,
2508 &gen_op_lmw_le_kernel,
2509 &gen_op_lmw_64_kernel,
2510 &gen_op_lmw_le_64_kernel,
2511 #if defined(TARGET_PPC64H)
2512 &gen_op_lmw_hypv,
2513 &gen_op_lmw_le_hypv,
2514 &gen_op_lmw_64_hypv,
2515 &gen_op_lmw_le_64_hypv,
2516 #endif
2517 };
2518 static GenOpFunc1 *gen_op_stmw[] = {
2519 &gen_op_stmw_user,
2520 &gen_op_stmw_le_user,
2521 &gen_op_stmw_64_user,
2522 &gen_op_stmw_le_64_user,
2523 &gen_op_stmw_kernel,
2524 &gen_op_stmw_le_kernel,
2525 &gen_op_stmw_64_kernel,
2526 &gen_op_stmw_le_64_kernel,
2527 #if defined(TARGET_PPC64H)
2528 &gen_op_stmw_hypv,
2529 &gen_op_stmw_le_hypv,
2530 &gen_op_stmw_64_hypv,
2531 &gen_op_stmw_le_64_hypv,
2532 #endif
2533 };
2534 #else
2535 /* Full system - 32 bits mode */
2536 static GenOpFunc1 *gen_op_lmw[] = {
2537 &gen_op_lmw_user,
2538 &gen_op_lmw_le_user,
2539 &gen_op_lmw_kernel,
2540 &gen_op_lmw_le_kernel,
2541 };
2542 static GenOpFunc1 *gen_op_stmw[] = {
2543 &gen_op_stmw_user,
2544 &gen_op_stmw_le_user,
2545 &gen_op_stmw_kernel,
2546 &gen_op_stmw_le_kernel,
2547 };
2548 #endif
2549 #endif
2550
2551 /* lmw */
2552 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2553 {
2554 /* NIP cannot be restored if the memory exception comes from an helper */
2555 gen_update_nip(ctx, ctx->nip - 4);
2556 gen_addr_imm_index(ctx, 0);
2557 op_ldstm(lmw, rD(ctx->opcode));
2558 }
2559
2560 /* stmw */
2561 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2562 {
2563 /* NIP cannot be restored if the memory exception comes from an helper */
2564 gen_update_nip(ctx, ctx->nip - 4);
2565 gen_addr_imm_index(ctx, 0);
2566 op_ldstm(stmw, rS(ctx->opcode));
2567 }
2568
2569 /*** Integer load and store strings ***/
2570 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2571 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2572 #if defined(CONFIG_USER_ONLY)
2573 /* User-mode only */
2574 static GenOpFunc1 *gen_op_lswi[] = {
2575 &gen_op_lswi_raw,
2576 &gen_op_lswi_le_raw,
2577 #if defined(TARGET_PPC64)
2578 &gen_op_lswi_64_raw,
2579 &gen_op_lswi_le_64_raw,
2580 #endif
2581 };
2582 static GenOpFunc3 *gen_op_lswx[] = {
2583 &gen_op_lswx_raw,
2584 &gen_op_lswx_le_raw,
2585 #if defined(TARGET_PPC64)
2586 &gen_op_lswx_64_raw,
2587 &gen_op_lswx_le_64_raw,
2588 #endif
2589 };
2590 static GenOpFunc1 *gen_op_stsw[] = {
2591 &gen_op_stsw_raw,
2592 &gen_op_stsw_le_raw,
2593 #if defined(TARGET_PPC64)
2594 &gen_op_stsw_64_raw,
2595 &gen_op_stsw_le_64_raw,
2596 #endif
2597 };
2598 #else
2599 #if defined(TARGET_PPC64)
2600 /* Full system - 64 bits mode */
2601 static GenOpFunc1 *gen_op_lswi[] = {
2602 &gen_op_lswi_user,
2603 &gen_op_lswi_le_user,
2604 &gen_op_lswi_64_user,
2605 &gen_op_lswi_le_64_user,
2606 &gen_op_lswi_kernel,
2607 &gen_op_lswi_le_kernel,
2608 &gen_op_lswi_64_kernel,
2609 &gen_op_lswi_le_64_kernel,
2610 #if defined(TARGET_PPC64H)
2611 &gen_op_lswi_hypv,
2612 &gen_op_lswi_le_hypv,
2613 &gen_op_lswi_64_hypv,
2614 &gen_op_lswi_le_64_hypv,
2615 #endif
2616 };
2617 static GenOpFunc3 *gen_op_lswx[] = {
2618 &gen_op_lswx_user,
2619 &gen_op_lswx_le_user,
2620 &gen_op_lswx_64_user,
2621 &gen_op_lswx_le_64_user,
2622 &gen_op_lswx_kernel,
2623 &gen_op_lswx_le_kernel,
2624 &gen_op_lswx_64_kernel,
2625 &gen_op_lswx_le_64_kernel,
2626 #if defined(TARGET_PPC64H)
2627 &gen_op_lswx_hypv,
2628 &gen_op_lswx_le_hypv,
2629 &gen_op_lswx_64_hypv,
2630 &gen_op_lswx_le_64_hypv,
2631 #endif
2632 };
2633 static GenOpFunc1 *gen_op_stsw[] = {
2634 &gen_op_stsw_user,
2635 &gen_op_stsw_le_user,
2636 &gen_op_stsw_64_user,
2637 &gen_op_stsw_le_64_user,
2638 &gen_op_stsw_kernel,
2639 &gen_op_stsw_le_kernel,
2640 &gen_op_stsw_64_kernel,
2641 &gen_op_stsw_le_64_kernel,
2642 #if defined(TARGET_PPC64H)
2643 &gen_op_stsw_hypv,
2644 &gen_op_stsw_le_hypv,
2645 &gen_op_stsw_64_hypv,
2646 &gen_op_stsw_le_64_hypv,
2647 #endif
2648 };
2649 #else
2650 /* Full system - 32 bits mode */
2651 static GenOpFunc1 *gen_op_lswi[] = {
2652 &gen_op_lswi_user,
2653 &gen_op_lswi_le_user,
2654 &gen_op_lswi_kernel,
2655 &gen_op_lswi_le_kernel,
2656 };
2657 static GenOpFunc3 *gen_op_lswx[] = {
2658 &gen_op_lswx_user,
2659 &gen_op_lswx_le_user,
2660 &gen_op_lswx_kernel,
2661 &gen_op_lswx_le_kernel,
2662 };
2663 static GenOpFunc1 *gen_op_stsw[] = {
2664 &gen_op_stsw_user,
2665 &gen_op_stsw_le_user,
2666 &gen_op_stsw_kernel,
2667 &gen_op_stsw_le_kernel,
2668 };
2669 #endif
2670 #endif
2671
2672 /* lswi */
2673 /* PowerPC32 specification says we must generate an exception if
2674 * rA is in the range of registers to be loaded.
2675 * In an other hand, IBM says this is valid, but rA won't be loaded.
2676 * For now, I'll follow the spec...
2677 */
2678 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
2679 {
2680 int nb = NB(ctx->opcode);
2681 int start = rD(ctx->opcode);
2682 int ra = rA(ctx->opcode);
2683 int nr;
2684
2685 if (nb == 0)
2686 nb = 32;
2687 nr = nb / 4;
2688 if (unlikely(((start + nr) > 32 &&
2689 start <= ra && (start + nr - 32) > ra) ||
2690 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2691 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2692 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
2693 return;
2694 }
2695 /* NIP cannot be restored if the memory exception comes from an helper */
2696 gen_update_nip(ctx, ctx->nip - 4);
2697 gen_addr_register(ctx);
2698 gen_op_set_T1(nb);
2699 op_ldsts(lswi, start);
2700 }
2701
2702 /* lswx */
2703 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
2704 {
2705 int ra = rA(ctx->opcode);
2706 int rb = rB(ctx->opcode);
2707
2708 /* NIP cannot be restored if the memory exception comes from an helper */
2709 gen_update_nip(ctx, ctx->nip - 4);
2710 gen_addr_reg_index(ctx);
2711 if (ra == 0) {
2712 ra = rb;
2713 }
2714 gen_op_load_xer_bc();
2715 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
2716 }
2717
2718 /* stswi */
2719 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
2720 {
2721 int nb = NB(ctx->opcode);
2722
2723 /* NIP cannot be restored if the memory exception comes from an helper */
2724 gen_update_nip(ctx, ctx->nip - 4);
2725 gen_addr_register(ctx);
2726 if (nb == 0)
2727 nb = 32;
2728 gen_op_set_T1(nb);
2729 op_ldsts(stsw, rS(ctx->opcode));
2730 }
2731
2732 /* stswx */
2733 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
2734 {
2735 /* NIP cannot be restored if the memory exception comes from an helper */
2736 gen_update_nip(ctx, ctx->nip - 4);
2737 gen_addr_reg_index(ctx);
2738 gen_op_load_xer_bc();
2739 op_ldsts(stsw, rS(ctx->opcode));
2740 }
2741
2742 /*** Memory synchronisation ***/
2743 /* eieio */
2744 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
2745 {
2746 }
2747
2748 /* isync */
2749 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
2750 {
2751 GEN_STOP(ctx);
2752 }
2753
2754 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2755 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2756 #if defined(CONFIG_USER_ONLY)
2757 /* User-mode only */
2758 static GenOpFunc *gen_op_lwarx[] = {
2759 &gen_op_lwarx_raw,
2760 &gen_op_lwarx_le_raw,
2761 #if defined(TARGET_PPC64)
2762 &gen_op_lwarx_64_raw,
2763 &gen_op_lwarx_le_64_raw,
2764 #endif
2765 };
2766 static GenOpFunc *gen_op_stwcx[] = {
2767 &gen_op_stwcx_raw,
2768 &gen_op_stwcx_le_raw,
2769 #if defined(TARGET_PPC64)
2770 &gen_op_stwcx_64_raw,
2771 &gen_op_stwcx_le_64_raw,
2772 #endif
2773 };
2774 #else
2775 #if defined(TARGET_PPC64)
2776 /* Full system - 64 bits mode */
2777 static GenOpFunc *gen_op_lwarx[] = {
2778 &gen_op_lwarx_user,
2779 &gen_op_lwarx_le_user,
2780 &gen_op_lwarx_64_user,
2781 &gen_op_lwarx_le_64_user,
2782 &gen_op_lwarx_kernel,
2783 &gen_op_lwarx_le_kernel,
2784 &gen_op_lwarx_64_kernel,
2785 &gen_op_lwarx_le_64_kernel,
2786 #if defined(TARGET_PPC64H)
2787 &gen_op_lwarx_hypv,
2788 &gen_op_lwarx_le_hypv,
2789 &gen_op_lwarx_64_hypv,
2790 &gen_op_lwarx_le_64_hypv,
2791 #endif
2792 };
2793 static GenOpFunc *gen_op_stwcx[] = {
2794 &gen_op_stwcx_user,
2795 &gen_op_stwcx_le_user,
2796 &gen_op_stwcx_64_user,
2797 &gen_op_stwcx_le_64_user,
2798 &gen_op_stwcx_kernel,
2799 &gen_op_stwcx_le_kernel,
2800 &gen_op_stwcx_64_kernel,
2801 &gen_op_stwcx_le_64_kernel,
2802 #if defined(TARGET_PPC64H)
2803 &gen_op_stwcx_hypv,
2804 &gen_op_stwcx_le_hypv,
2805 &gen_op_stwcx_64_hypv,
2806 &gen_op_stwcx_le_64_hypv,
2807 #endif
2808 };
2809 #else
2810 /* Full system - 32 bits mode */
2811 static GenOpFunc *gen_op_lwarx[] = {
2812 &gen_op_lwarx_user,
2813 &gen_op_lwarx_le_user,
2814 &gen_op_lwarx_kernel,
2815 &gen_op_lwarx_le_kernel,
2816 };
2817 static GenOpFunc *gen_op_stwcx[] = {
2818 &gen_op_stwcx_user,
2819 &gen_op_stwcx_le_user,
2820 &gen_op_stwcx_kernel,
2821 &gen_op_stwcx_le_kernel,
2822 };
2823 #endif
2824 #endif
2825
2826 /* lwarx */
2827 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
2828 {
2829 /* NIP cannot be restored if the memory exception comes from an helper */
2830 gen_update_nip(ctx, ctx->nip - 4);
2831 gen_addr_reg_index(ctx);
2832 op_lwarx();
2833 gen_op_store_T1_gpr(rD(ctx->opcode));
2834 }
2835
2836 /* stwcx. */
2837 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2838 {
2839 /* NIP cannot be restored if the memory exception comes from an helper */
2840 gen_update_nip(ctx, ctx->nip - 4);
2841 gen_addr_reg_index(ctx);
2842 gen_op_load_gpr_T1(rS(ctx->opcode));
2843 op_stwcx();
2844 }
2845
2846 #if defined(TARGET_PPC64)
2847 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2848 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2849 #if defined(CONFIG_USER_ONLY)
2850 /* User-mode only */
2851 static GenOpFunc *gen_op_ldarx[] = {
2852 &gen_op_ldarx_raw,
2853 &gen_op_ldarx_le_raw,
2854 &gen_op_ldarx_64_raw,
2855 &gen_op_ldarx_le_64_raw,
2856 };
2857 static GenOpFunc *gen_op_stdcx[] = {
2858 &gen_op_stdcx_raw,
2859 &gen_op_stdcx_le_raw,
2860 &gen_op_stdcx_64_raw,
2861 &gen_op_stdcx_le_64_raw,
2862 };
2863 #else
2864 /* Full system */
2865 static GenOpFunc *gen_op_ldarx[] = {
2866 &gen_op_ldarx_user,
2867 &gen_op_ldarx_le_user,
2868 &gen_op_ldarx_64_user,
2869 &gen_op_ldarx_le_64_user,
2870 &gen_op_ldarx_kernel,
2871 &gen_op_ldarx_le_kernel,
2872 &gen_op_ldarx_64_kernel,
2873 &gen_op_ldarx_le_64_kernel,
2874 #if defined(TARGET_PPC64H)
2875 &gen_op_ldarx_hypv,
2876 &gen_op_ldarx_le_hypv,
2877 &gen_op_ldarx_64_hypv,
2878 &gen_op_ldarx_le_64_hypv,
2879 #endif
2880 };
2881 static GenOpFunc *gen_op_stdcx[] = {
2882 &gen_op_stdcx_user,
2883 &gen_op_stdcx_le_user,
2884 &gen_op_stdcx_64_user,
2885 &gen_op_stdcx_le_64_user,
2886 &gen_op_stdcx_kernel,
2887 &gen_op_stdcx_le_kernel,
2888 &gen_op_stdcx_64_kernel,
2889 &gen_op_stdcx_le_64_kernel,
2890 #if defined(TARGET_PPC64H)
2891 &gen_op_stdcx_hypv,
2892 &gen_op_stdcx_le_hypv,
2893 &gen_op_stdcx_64_hypv,
2894 &gen_op_stdcx_le_64_hypv,
2895 #endif
2896 };
2897 #endif
2898
2899 /* ldarx */
2900 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2901 {
2902 /* NIP cannot be restored if the memory exception comes from an helper */
2903 gen_update_nip(ctx, ctx->nip - 4);
2904 gen_addr_reg_index(ctx);
2905 op_ldarx();
2906 gen_op_store_T1_gpr(rD(ctx->opcode));
2907 }
2908
2909 /* stdcx. */
2910 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2911 {
2912 /* NIP cannot be restored if the memory exception comes from an helper */
2913 gen_update_nip(ctx, ctx->nip - 4);
2914 gen_addr_reg_index(ctx);
2915 gen_op_load_gpr_T1(rS(ctx->opcode));
2916 op_stdcx();
2917 }
2918 #endif /* defined(TARGET_PPC64) */
2919
2920 /* sync */
2921 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
2922 {
2923 }
2924
2925 /* wait */
2926 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2927 {
2928 /* Stop translation, as the CPU is supposed to sleep from now */
2929 gen_op_wait();
2930 GEN_EXCP(ctx, EXCP_HLT, 1);
2931 }
2932
2933 /*** Floating-point load ***/
2934 #define GEN_LDF(width, opc, type) \
2935 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2936 { \
2937 if (unlikely(!ctx->fpu_enabled)) { \
2938 GEN_EXCP_NO_FP(ctx); \
2939 return; \
2940 } \
2941 gen_addr_imm_index(ctx, 0); \
2942 op_ldst(l##width); \
2943 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2944 }
2945
2946 #define GEN_LDUF(width, opc, type) \
2947 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2948 { \
2949 if (unlikely(!ctx->fpu_enabled)) { \
2950 GEN_EXCP_NO_FP(ctx); \
2951 return; \
2952 } \
2953 if (unlikely(rA(ctx->opcode) == 0)) { \
2954 GEN_EXCP_INVAL(ctx); \
2955 return; \
2956 } \
2957 gen_addr_imm_index(ctx, 0); \
2958 op_ldst(l##width); \
2959 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2960 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2961 }
2962
2963 #define GEN_LDUXF(width, opc, type) \
2964 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2965 { \
2966 if (unlikely(!ctx->fpu_enabled)) { \
2967 GEN_EXCP_NO_FP(ctx); \
2968 return; \
2969 } \
2970 if (unlikely(rA(ctx->opcode) == 0)) { \
2971 GEN_EXCP_INVAL(ctx); \
2972 return; \
2973 } \
2974 gen_addr_reg_index(ctx); \
2975 op_ldst(l##width); \
2976 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2977 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2978 }
2979
2980 #define GEN_LDXF(width, opc2, opc3, type) \
2981 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2982 { \
2983 if (unlikely(!ctx->fpu_enabled)) { \
2984 GEN_EXCP_NO_FP(ctx); \
2985 return; \
2986 } \
2987 gen_addr_reg_index(ctx); \
2988 op_ldst(l##width); \
2989 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2990 }
2991
2992 #define GEN_LDFS(width, op, type) \
2993 OP_LD_TABLE(width); \
2994 GEN_LDF(width, op | 0x20, type); \
2995 GEN_LDUF(width, op | 0x21, type); \
2996 GEN_LDUXF(width, op | 0x01, type); \
2997 GEN_LDXF(width, 0x17, op | 0x00, type)
2998
2999 /* lfd lfdu lfdux lfdx */
3000 GEN_LDFS(fd, 0x12, PPC_FLOAT);
3001 /* lfs lfsu lfsux lfsx */
3002 GEN_LDFS(fs, 0x10, PPC_FLOAT);
3003
3004 /*** Floating-point store ***/
3005 #define GEN_STF(width, opc, type) \
3006 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
3007 { \
3008 if (unlikely(!ctx->fpu_enabled)) { \
3009 GEN_EXCP_NO_FP(ctx); \
3010 return; \
3011 } \
3012 gen_addr_imm_index(ctx, 0); \
3013 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3014 op_ldst(st##width); \
3015 }
3016
3017 #define GEN_STUF(width, opc, type) \
3018 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3019 { \
3020 if (unlikely(!ctx->fpu_enabled)) { \
3021 GEN_EXCP_NO_FP(ctx); \
3022 return; \
3023 } \
3024 if (unlikely(rA(ctx->opcode) == 0)) { \
3025 GEN_EXCP_INVAL(ctx); \
3026 return; \
3027 } \
3028 gen_addr_imm_index(ctx, 0); \
3029 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3030 op_ldst(st##width); \
3031 gen_op_store_T0_gpr(rA(ctx->opcode)); \
3032 }
3033
3034 #define GEN_STUXF(width, opc, type) \
3035 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3036 { \
3037 if (unlikely(!ctx->fpu_enabled)) { \
3038 GEN_EXCP_NO_FP(ctx); \
3039 return; \
3040 } \
3041 if (unlikely(rA(ctx->opcode) == 0)) { \
3042 GEN_EXCP_INVAL(ctx); \
3043 return; \
3044 } \
3045 gen_addr_reg_index(ctx); \
3046 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3047 op_ldst(st##width); \
3048 gen_op_store_T0_gpr(rA(ctx->opcode)); \
3049 }
3050
3051 #define GEN_STXF(width, opc2, opc3, type) \
3052 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
3053 { \
3054 if (unlikely(!ctx->fpu_enabled)) { \
3055 GEN_EXCP_NO_FP(ctx); \
3056 return; \
3057 } \
3058 gen_addr_reg_index(ctx); \
3059 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3060 op_ldst(st##width); \
3061 }
3062
3063 #define GEN_STFS(width, op, type) \
3064 OP_ST_TABLE(width); \
3065 GEN_STF(width, op | 0x20, type); \
3066 GEN_STUF(width, op | 0x21, type); \
3067 GEN_STUXF(width, op | 0x01, type); \
3068 GEN_STXF(width, 0x17, op | 0x00, type)
3069
3070 /* stfd stfdu stfdux stfdx */
3071 GEN_STFS(fd, 0x16, PPC_FLOAT);
3072 /* stfs stfsu stfsux stfsx */
3073 GEN_STFS(fs, 0x14, PPC_FLOAT);
3074
3075 /* Optional: */
3076 /* stfiwx */
3077 OP_ST_TABLE(fiwx);
3078 GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3079
3080 /*** Branch ***/
3081 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3082 target_ulong dest)
3083 {
3084 TranslationBlock *tb;
3085 tb = ctx->tb;
3086 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3087 if (n == 0)
3088 gen_op_goto_tb0(TBPARAM(tb));
3089 else
3090 gen_op_goto_tb1(TBPARAM(tb));
3091 gen_set_T1(dest);
3092 #if defined(TARGET_PPC64)
3093 if (ctx->sf_mode)
3094 gen_op_b_T1_64();
3095 else
3096 #endif
3097 gen_op_b_T1();
3098 gen_op_set_T0((long)tb + n);
3099 if (ctx->singlestep_enabled)
3100 gen_op_debug();
3101 gen_op_exit_tb();
3102 } else {
3103 gen_set_T1(dest);
3104 #if defined(TARGET_PPC64)
3105 if (ctx->sf_mode)
3106 gen_op_b_T1_64();
3107 else
3108 #endif
3109 gen_op_b_T1();
3110 gen_op_reset_T0();
3111 if (ctx->singlestep_enabled)
3112 gen_op_debug();
3113 gen_op_exit_tb();
3114 }
3115 }
3116
3117 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3118 {
3119 #if defined(TARGET_PPC64)
3120 if (ctx->sf_mode != 0 && (nip >> 32))
3121 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
3122 else
3123 #endif
3124 gen_op_setlr(ctx->nip);
3125 }
3126
3127 /* b ba bl bla */
3128 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3129 {
3130 target_ulong li, target;
3131
3132 /* sign extend LI */
3133 #if defined(TARGET_PPC64)
3134 if (ctx->sf_mode)
3135 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3136 else
3137 #endif
3138 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3139 if (likely(AA(ctx->opcode) == 0))
3140 target = ctx->nip + li - 4;
3141 else
3142 target = li;
3143 #if defined(TARGET_PPC64)
3144 if (!ctx->sf_mode)
3145 target = (uint32_t)target;
3146 #endif
3147 if (LK(ctx->opcode))
3148 gen_setlr(ctx, ctx->nip);
3149 gen_goto_tb(ctx, 0, target);
3150 ctx->exception = POWERPC_EXCP_BRANCH;
3151 }
3152
3153 #define BCOND_IM 0
3154 #define BCOND_LR 1
3155 #define BCOND_CTR 2
3156
3157 static always_inline void gen_bcond (DisasContext *ctx, int type)
3158 {
3159 target_ulong target = 0;
3160 target_ulong li;
3161 uint32_t bo = BO(ctx->opcode);
3162 uint32_t bi = BI(ctx->opcode);
3163 uint32_t mask;
3164
3165 if ((bo & 0x4) == 0)
3166 gen_op_dec_ctr();
3167 switch(type) {
3168 case BCOND_IM:
3169 li = (target_long)((int16_t)(BD(ctx->opcode)));
3170 if (likely(AA(ctx->opcode) == 0)) {
3171 target = ctx->nip + li - 4;
3172 } else {
3173 target = li;
3174 }
3175 #if defined(TARGET_PPC64)
3176 if (!ctx->sf_mode)
3177 target = (uint32_t)target;
3178 #endif
3179 break;
3180 case BCOND_CTR:
3181 gen_op_movl_T1_ctr();
3182 break;
3183 default:
3184 case BCOND_LR:
3185 gen_op_movl_T1_lr();
3186 break;
3187 }
3188 if (LK(ctx->opcode))
3189 gen_setlr(ctx, ctx->nip);
3190 if (bo & 0x10) {
3191 /* No CR condition */
3192 switch (bo & 0x6) {
3193 case 0:
3194 #if defined(TARGET_PPC64)
3195 if (ctx->sf_mode)
3196 gen_op_test_ctr_64();
3197 else
3198 #endif
3199 gen_op_test_ctr();
3200 break;
3201 case 2:
3202 #if defined(TARGET_PPC64)
3203 if (ctx->sf_mode)
3204 gen_op_test_ctrz_64();
3205 else
3206 #endif
3207 gen_op_test_ctrz();
3208 break;
3209 default:
3210 case 4:
3211 case 6:
3212 if (type == BCOND_IM) {
3213 gen_goto_tb(ctx, 0, target);
3214 goto out;
3215 } else {
3216 #if defined(TARGET_PPC64)
3217 if (ctx->sf_mode)
3218 gen_op_b_T1_64();
3219 else
3220 #endif
3221 gen_op_b_T1();
3222 gen_op_reset_T0();
3223 goto no_test;
3224 }
3225 break;
3226 }
3227 } else {
3228 mask = 1 << (3 - (bi & 0x03));
3229 gen_op_load_crf_T0(bi >> 2);
3230 if (bo & 0x8) {
3231 switch (bo & 0x6) {
3232 case 0:
3233 #if defined(TARGET_PPC64)
3234 if (ctx->sf_mode)
3235 gen_op_test_ctr_true_64(mask);
3236 else
3237 #endif
3238 gen_op_test_ctr_true(mask);
3239 break;
3240 case 2:
3241 #if defined(TARGET_PPC64)
3242 if (ctx->sf_mode)
3243 gen_op_test_ctrz_true_64(mask);
3244 else
3245 #endif
3246 gen_op_test_ctrz_true(mask);
3247 break;
3248 default:
3249 case 4:
3250 case 6:
3251 gen_op_test_true(mask);
3252 break;
3253 }
3254 } else {
3255 switch (bo & 0x6) {
3256 case 0:
3257 #if defined(TARGET_PPC64)
3258 if (ctx->sf_mode)
3259 gen_op_test_ctr_false_64(mask);
3260 else
3261 #endif
3262 gen_op_test_ctr_false(mask);
3263 break;
3264 case 2:
3265 #if defined(TARGET_PPC64)
3266 if (ctx->sf_mode)
3267 gen_op_test_ctrz_false_64(mask);
3268 else
3269 #endif
3270 gen_op_test_ctrz_false(mask);
3271 break;
3272 default:
3273 case 4:
3274 case 6:
3275 gen_op_test_false(mask);
3276 break;
3277 }
3278 }
3279 }
3280 if (type == BCOND_IM) {
3281 int l1 = gen_new_label();
3282 gen_op_jz_T0(l1);
3283 gen_goto_tb(ctx, 0, target);
3284 gen_set_label(l1);
3285 gen_goto_tb(ctx, 1, ctx->nip);
3286 } else {
3287 #if defined(TARGET_PPC64)
3288 if (ctx->sf_mode)
3289 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3290 else
3291 #endif
3292 gen_op_btest_T1(ctx->nip);
3293 gen_op_reset_T0();
3294 no_test:
3295 if (ctx->singlestep_enabled)
3296 gen_op_debug();
3297 gen_op_exit_tb();
3298 }
3299 out:
3300 ctx->exception = POWERPC_EXCP_BRANCH;
3301 }
3302
3303 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3304 {
3305 gen_bcond(ctx, BCOND_IM);
3306 }
3307
3308 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3309 {
3310 gen_bcond(ctx, BCOND_CTR);
3311 }
3312
3313 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3314 {
3315 gen_bcond(ctx, BCOND_LR);
3316 }
3317
3318 /*** Condition register logical ***/
3319 #define GEN_CRLOGIC(op, opc) \
3320 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3321 { \
3322 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
3323 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
3324 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
3325 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
3326 gen_op_##op(); \
3327 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
3328 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
3329 3 - (crbD(ctx->opcode) & 0x03)); \
3330 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
3331 }
3332
3333 /* crand */
3334 GEN_CRLOGIC(and, 0x08);
3335 /* crandc */
3336 GEN_CRLOGIC(andc, 0x04);
3337 /* creqv */
3338 GEN_CRLOGIC(eqv, 0x09);
3339 /* crnand */
3340 GEN_CRLOGIC(nand, 0x07);
3341 /* crnor */
3342 GEN_CRLOGIC(nor, 0x01);
3343 /* cror */
3344 GEN_CRLOGIC(or, 0x0E);
3345 /* crorc */
3346 GEN_CRLOGIC(orc, 0x0D);
3347 /* crxor */
3348 GEN_CRLOGIC(xor, 0x06);
3349 /* mcrf */
3350 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3351 {
3352 gen_op_load_crf_T0(crfS(ctx->opcode));
3353 gen_op_store_T0_crf(crfD(ctx->opcode));
3354 }
3355
3356 /*** System linkage ***/
3357 /* rfi (supervisor only) */
3358 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3359 {
3360 #if defined(CONFIG_USER_ONLY)
3361 GEN_EXCP_PRIVOPC(ctx);
3362 #else
3363 /* Restore CPU state */
3364 if (unlikely(!ctx->supervisor)) {
3365 GEN_EXCP_PRIVOPC(ctx);
3366 return;
3367 }
3368 gen_op_rfi();
3369 GEN_SYNC(ctx);
3370 #endif
3371 }
3372
3373 #if defined(TARGET_PPC64)
3374 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3375 {
3376 #if defined(CONFIG_USER_ONLY)
3377 GEN_EXCP_PRIVOPC(ctx);
3378 #else
3379 /* Restore CPU state */
3380 if (unlikely(!ctx->supervisor)) {
3381 GEN_EXCP_PRIVOPC(ctx);
3382 return;
3383 }
3384 gen_op_rfid();
3385 GEN_SYNC(ctx);
3386 #endif
3387 }
3388 #endif
3389
3390 #if defined(TARGET_PPC64H)
3391 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B)
3392 {
3393 #if defined(CONFIG_USER_ONLY)
3394 GEN_EXCP_PRIVOPC(ctx);
3395 #else
3396 /* Restore CPU state */
3397 if (unlikely(ctx->supervisor <= 1)) {
3398 GEN_EXCP_PRIVOPC(ctx);
3399 return;
3400 }
3401 gen_op_hrfid();
3402 GEN_SYNC(ctx);
3403 #endif
3404 }
3405 #endif
3406
3407 /* sc */
3408 #if defined(CONFIG_USER_ONLY)
3409 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3410 #else
3411 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3412 #endif
3413 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3414 {
3415 uint32_t lev;
3416
3417 lev = (ctx->opcode >> 5) & 0x7F;
3418 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3419 }
3420
3421 /*** Trap ***/
3422 /* tw */
3423 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3424 {
3425 gen_op_load_gpr_T0(rA(ctx->opcode));
3426 gen_op_load_gpr_T1(rB(ctx->opcode));
3427 /* Update the nip since this might generate a trap exception */
3428 gen_update_nip(ctx, ctx->nip);
3429 gen_op_tw(TO(ctx->opcode));
3430 }
3431
3432 /* twi */
3433 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3434 {
3435 gen_op_load_gpr_T0(rA(ctx->opcode));
3436 gen_set_T1(SIMM(ctx->opcode));
3437 /* Update the nip since this might generate a trap exception */
3438 gen_update_nip(ctx, ctx->nip);
3439 gen_op_tw(TO(ctx->opcode));
3440 }
3441
3442 #if defined(TARGET_PPC64)
3443 /* td */
3444 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3445 {
3446 gen_op_load_gpr_T0(rA(ctx->opcode));
3447 gen_op_load_gpr_T1(rB(ctx->opcode));
3448 /* Update the nip since this might generate a trap exception */
3449 gen_update_nip(ctx, ctx->nip);
3450 gen_op_td(TO(ctx->opcode));
3451 }
3452
3453 /* tdi */
3454 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3455 {
3456 gen_op_load_gpr_T0(rA(ctx->opcode));
3457 gen_set_T1(SIMM(ctx->opcode));
3458 /* Update the nip since this might generate a trap exception */
3459 gen_update_nip(ctx, ctx->nip);
3460 gen_op_td(TO(ctx->opcode));
3461 }
3462 #endif
3463
3464 /*** Processor control ***/
3465 /* mcrxr */
3466 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3467 {
3468 gen_op_load_xer_cr();
3469 gen_op_store_T0_crf(crfD(ctx->opcode));
3470 gen_op_clear_xer_ov();
3471 gen_op_clear_xer_ca();
3472 }
3473
3474 /* mfcr */
3475 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3476 {
3477 uint32_t crm, crn;
3478
3479 if (likely(ctx->opcode & 0x00100000)) {
3480 crm = CRM(ctx->opcode);
3481 if (likely((crm ^ (crm - 1)) == 0)) {
3482 crn = ffs(crm);
3483 gen_op_load_cro(7 - crn);
3484 }
3485 } else {
3486 gen_op_load_cr();
3487 }
3488 gen_op_store_T0_gpr(rD(ctx->opcode));
3489 }
3490
3491 /* mfmsr */
3492 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3493 {
3494 #if defined(CONFIG_USER_ONLY)
3495 GEN_EXCP_PRIVREG(ctx);
3496 #else
3497 if (unlikely(!ctx->supervisor)) {
3498 GEN_EXCP_PRIVREG(ctx);
3499 return;
3500 }
3501 gen_op_load_msr();
3502 gen_op_store_T0_gpr(rD(ctx->opcode));
3503 #endif
3504 }
3505
3506 #if 0
3507 #define SPR_NOACCESS ((void *)(-1))
3508 #else
3509 static void spr_noaccess (void *opaque, int sprn)
3510 {
3511 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3512 printf("ERROR: try to access SPR %d !\n", sprn);
3513 }
3514 #define SPR_NOACCESS (&spr_noaccess)
3515 #endif
3516
3517 /* mfspr */
3518 static always_inline void gen_op_mfspr (DisasContext *ctx)
3519 {
3520 void (*read_cb)(void *opaque, int sprn);
3521 uint32_t sprn = SPR(ctx->opcode);
3522
3523 #if !defined(CONFIG_USER_ONLY)
3524 #if defined(TARGET_PPC64H)
3525 if (ctx->supervisor == 2)
3526 read_cb = ctx->spr_cb[sprn].hea_read;
3527 else
3528 #endif
3529 if (ctx->supervisor)
3530 read_cb = ctx->spr_cb[sprn].oea_read;
3531 else
3532 #endif
3533 read_cb = ctx->spr_cb[sprn].uea_read;
3534 if (likely(read_cb != NULL)) {
3535 if (likely(read_cb != SPR_NOACCESS)) {
3536 (*read_cb)(ctx, sprn);
3537 gen_op_store_T0_gpr(rD(ctx->opcode));
3538 } else {
3539 /* Privilege exception */
3540 if (loglevel != 0) {
3541 fprintf(logfile, "Trying to read privileged spr %d %03x\n",
3542 sprn, sprn);
3543 }
3544 printf("Trying to read privileged spr %d %03x\n", sprn, sprn);
3545 GEN_EXCP_PRIVREG(ctx);
3546 }
3547 } else {
3548 /* Not defined */
3549 if (loglevel != 0) {
3550 fprintf(logfile, "Trying to read invalid spr %d %03x\n",
3551 sprn, sprn);
3552 }
3553 printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
3554 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3555 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3556 }
3557 }
3558
3559 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3560 {
3561 gen_op_mfspr(ctx);
3562 }
3563
3564 /* mftb */
3565 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3566 {
3567 gen_op_mfspr(ctx);
3568 }
3569
3570 /* mtcrf */
3571 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3572 {
3573 uint32_t crm, crn;
3574
3575 gen_op_load_gpr_T0(rS(ctx->opcode));
3576 crm = CRM(ctx->opcode);
3577 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3578 crn = ffs(crm);
3579 gen_op_srli_T0(crn * 4);
3580 gen_op_andi_T0(0xF);
3581 gen_op_store_cro(7 - crn);
3582 } else {
3583 gen_op_store_cr(crm);
3584 }
3585 }
3586
3587 /* mtmsr */
3588 #if defined(TARGET_PPC64)
3589 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3590 {
3591 #if defined(CONFIG_USER_ONLY)
3592 GEN_EXCP_PRIVREG(ctx);
3593 #else
3594 if (unlikely(!ctx->supervisor)) {
3595 GEN_EXCP_PRIVREG(ctx);
3596 return;
3597 }
3598 gen_op_load_gpr_T0(rS(ctx->opcode));
3599 if (ctx->opcode & 0x00010000) {
3600 /* Special form that does not need any synchronisation */
3601 gen_op_update_riee();
3602 } else {
3603 /* XXX: we need to update nip before the store
3604 * if we enter power saving mode, we will exit the loop
3605 * directly from ppc_store_msr
3606 */
3607 gen_update_nip(ctx, ctx->nip);
3608 gen_op_store_msr();
3609 /* Must stop the translation as machine state (may have) changed */
3610 /* Note that mtmsr is not always defined as context-synchronizing */
3611 ctx->exception = POWERPC_EXCP_STOP;
3612 }
3613 #endif
3614 }
3615 #endif
3616
3617 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3618 {
3619 #if defined(CONFIG_USER_ONLY)
3620 GEN_EXCP_PRIVREG(ctx);
3621 #else
3622 if (unlikely(!ctx->supervisor)) {
3623 GEN_EXCP_PRIVREG(ctx);
3624 return;
3625 }
3626 gen_op_load_gpr_T0(rS(ctx->opcode));
3627 if (ctx->opcode & 0x00010000) {
3628 /* Special form that does not need any synchronisation */
3629 gen_op_update_riee();
3630 } else {
3631 /* XXX: we need to update nip before the store
3632 * if we enter power saving mode, we will exit the loop
3633 * directly from ppc_store_msr
3634 */
3635 gen_update_nip(ctx, ctx->nip);
3636 #if defined(TARGET_PPC64)
3637 if (!ctx->sf_mode)
3638 gen_op_store_msr_32();
3639 else
3640 #endif
3641 gen_op_store_msr();
3642 /* Must stop the translation as machine state (may have) changed */
3643 /* Note that mtmsrd is not always defined as context-synchronizing */
3644 ctx->exception = POWERPC_EXCP_STOP;
3645 }
3646 #endif
3647 }
3648
3649 /* mtspr */
3650 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3651 {
3652 void (*write_cb)(void *opaque, int sprn);
3653 uint32_t sprn = SPR(ctx->opcode);
3654
3655 #if !defined(CONFIG_USER_ONLY)
3656 #if defined(TARGET_PPC64H)
3657 if (ctx->supervisor == 2)
3658 write_cb = ctx->spr_cb[sprn].hea_write;
3659 else
3660 #endif
3661 if (ctx->supervisor)
3662 write_cb = ctx->spr_cb[sprn].oea_write;
3663 else
3664 #endif
3665 write_cb = ctx->spr_cb[sprn].uea_write;
3666 if (likely(write_cb != NULL)) {
3667 if (likely(write_cb != SPR_NOACCESS)) {
3668 gen_op_load_gpr_T0(rS(ctx->opcode));
3669 (*write_cb)(ctx, sprn);
3670 } else {
3671 /* Privilege exception */
3672 if (loglevel != 0) {
3673 fprintf(logfile, "Trying to write privileged spr %d %03x\n",
3674 sprn, sprn);
3675 }
3676 printf("Trying to write privileged spr %d %03x\n", sprn, sprn);
3677 GEN_EXCP_PRIVREG(ctx);
3678 }
3679 } else {
3680 /* Not defined */
3681 if (loglevel != 0) {
3682 fprintf(logfile, "Trying to write invalid spr %d %03x\n",
3683 sprn, sprn);
3684 }
3685 printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
3686 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3687 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3688 }
3689 }
3690
3691 /*** Cache management ***/
3692 /* dcbf */
3693 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
3694 {
3695 /* XXX: specification says this is treated as a load by the MMU */
3696 gen_addr_reg_index(ctx);
3697 op_ldst(lbz);
3698 }
3699
3700 /* dcbi (Supervisor only) */
3701 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
3702 {
3703 #if defined(CONFIG_USER_ONLY)
3704 GEN_EXCP_PRIVOPC(ctx);
3705 #else
3706 if (unlikely(!ctx->supervisor)) {
3707 GEN_EXCP_PRIVOPC(ctx);
3708 return;
3709 }
3710 gen_addr_reg_index(ctx);
3711 /* XXX: specification says this should be treated as a store by the MMU */
3712 op_ldst(lbz);
3713 op_ldst(stb);
3714 #endif
3715 }
3716
3717 /* dcdst */
3718 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
3719 {
3720 /* XXX: specification say this is treated as a load by the MMU */
3721 gen_addr_reg_index(ctx);
3722 op_ldst(lbz);
3723 }
3724
3725 /* dcbt */
3726 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
3727 {
3728 /* interpreted as no-op */
3729 /* XXX: specification say this is treated as a load by the MMU
3730 * but does not generate any exception
3731 */
3732 }
3733
3734 /* dcbtst */
3735 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
3736 {
3737 /* interpreted as no-op */
3738 /* XXX: specification say this is treated as a load by the MMU
3739 * but does not generate any exception
3740 */
3741 }
3742
3743 /* dcbz */
3744 #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3745 #if defined(CONFIG_USER_ONLY)
3746 /* User-mode only */
3747 static GenOpFunc *gen_op_dcbz[4][4] = {
3748 {
3749 &gen_op_dcbz_l32_raw,
3750 &gen_op_dcbz_l32_raw,
3751 #if defined(TARGET_PPC64)
3752 &gen_op_dcbz_l32_64_raw,
3753 &gen_op_dcbz_l32_64_raw,
3754 #endif
3755 },
3756 {
3757 &gen_op_dcbz_l64_raw,
3758 &gen_op_dcbz_l64_raw,
3759 #if defined(TARGET_PPC64)
3760 &gen_op_dcbz_l64_64_raw,
3761 &gen_op_dcbz_l64_64_raw,
3762 #endif
3763 },
3764 {
3765 &gen_op_dcbz_l128_raw,
3766 &gen_op_dcbz_l128_raw,
3767 #if defined(TARGET_PPC64)
3768 &gen_op_dcbz_l128_64_raw,
3769 &gen_op_dcbz_l128_64_raw,
3770 #endif
3771 },
3772 {
3773 &gen_op_dcbz_raw,
3774 &gen_op_dcbz_raw,
3775 #if defined(TARGET_PPC64)
3776 &gen_op_dcbz_64_raw,
3777 &gen_op_dcbz_64_raw,
3778 #endif
3779 },
3780 };
3781 #else
3782 #if defined(TARGET_PPC64)
3783 /* Full system - 64 bits mode */
3784 static GenOpFunc *gen_op_dcbz[4][12] = {
3785 {
3786 &gen_op_dcbz_l32_user,
3787 &gen_op_dcbz_l32_user,
3788 &gen_op_dcbz_l32_64_user,
3789 &gen_op_dcbz_l32_64_user,
3790 &gen_op_dcbz_l32_kernel,
3791 &gen_op_dcbz_l32_kernel,
3792 &gen_op_dcbz_l32_64_kernel,
3793 &gen_op_dcbz_l32_64_kernel,
3794 #if defined(TARGET_PPC64H)
3795 &gen_op_dcbz_l32_hypv,
3796 &gen_op_dcbz_l32_hypv,
3797 &gen_op_dcbz_l32_64_hypv,
3798 &gen_op_dcbz_l32_64_hypv,
3799 #endif
3800 },
3801 {
3802 &gen_op_dcbz_l64_user,
3803 &gen_op_dcbz_l64_user,
3804 &gen_op_dcbz_l64_64_user,
3805 &gen_op_dcbz_l64_64_user,
3806 &gen_op_dcbz_l64_kernel,
3807 &gen_op_dcbz_l64_kernel,
3808 &gen_op_dcbz_l64_64_kernel,
3809 &gen_op_dcbz_l64_64_kernel,
3810 #if defined(TARGET_PPC64H)
3811 &gen_op_dcbz_l64_hypv,
3812 &gen_op_dcbz_l64_hypv,
3813 &gen_op_dcbz_l64_64_hypv,
3814 &gen_op_dcbz_l64_64_hypv,
3815 #endif
3816 },
3817 {
3818 &gen_op_dcbz_l128_user,
3819 &gen_op_dcbz_l128_user,
3820 &gen_op_dcbz_l128_64_user,
3821 &gen_op_dcbz_l128_64_user,
3822 &gen_op_dcbz_l128_kernel,
3823 &gen_op_dcbz_l128_kernel,
3824 &gen_op_dcbz_l128_64_kernel,
3825 &gen_op_dcbz_l128_64_kernel,
3826 #if defined(TARGET_PPC64H)
3827 &gen_op_dcbz_l128_hypv,
3828 &gen_op_dcbz_l128_hypv,
3829 &gen_op_dcbz_l128_64_hypv,
3830 &gen_op_dcbz_l128_64_hypv,
3831 #endif
3832 },
3833 {
3834 &gen_op_dcbz_user,
3835 &gen_op_dcbz_user,
3836 &gen_op_dcbz_64_user,
3837 &gen_op_dcbz_64_user,
3838 &gen_op_dcbz_kernel,
3839 &gen_op_dcbz_kernel,
3840 &gen_op_dcbz_64_kernel,
3841 &gen_op_dcbz_64_kernel,
3842 #if defined(TARGET_PPC64H)
3843 &gen_op_dcbz_hypv,
3844 &gen_op_dcbz_hypv,
3845 &gen_op_dcbz_64_hypv,
3846 &gen_op_dcbz_64_hypv,
3847 #endif
3848 },
3849 };
3850 #else
3851 /* Full system - 32 bits mode */
3852 static GenOpFunc *gen_op_dcbz[4][4] = {
3853 {
3854 &gen_op_dcbz_l32_user,
3855 &gen_op_dcbz_l32_user,
3856 &gen_op_dcbz_l32_kernel,
3857 &gen_op_dcbz_l32_kernel,
3858 },
3859 {
3860 &gen_op_dcbz_l64_user,
3861 &gen_op_dcbz_l64_user,
3862 &gen_op_dcbz_l64_kernel,
3863 &gen_op_dcbz_l64_kernel,
3864 },
3865 {
3866 &gen_op_dcbz_l128_user,
3867 &gen_op_dcbz_l128_user,
3868 &gen_op_dcbz_l128_kernel,
3869 &gen_op_dcbz_l128_kernel,
3870 },
3871 {
3872 &gen_op_dcbz_user,
3873 &gen_op_dcbz_user,
3874 &gen_op_dcbz_kernel,
3875 &gen_op_dcbz_kernel,
3876 },
3877 };
3878 #endif
3879 #endif
3880
3881 static always_inline void handler_dcbz (DisasContext *ctx,
3882 int dcache_line_size)
3883 {
3884 int n;
3885
3886 switch (dcache_line_size) {
3887 case 32:
3888 n = 0;
3889 break;
3890 case 64:
3891 n = 1;
3892 break;
3893 case 128:
3894 n = 2;
3895 break;
3896 default:
3897 n = 3;
3898 break;
3899 }
3900 op_dcbz(n);
3901 }
3902
3903 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
3904 {
3905 gen_addr_reg_index(ctx);
3906 handler_dcbz(ctx, ctx->dcache_line_size);
3907 gen_op_check_reservation();
3908 }
3909
3910 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
3911 {
3912 gen_addr_reg_index(ctx);
3913 if (ctx->opcode & 0x00200000)
3914 handler_dcbz(ctx, ctx->dcache_line_size);
3915 else
3916 handler_dcbz(ctx, -1);
3917 gen_op_check_reservation();
3918 }
3919
3920 /* icbi */
3921 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3922 #if defined(CONFIG_USER_ONLY)
3923 /* User-mode only */
3924 static GenOpFunc *gen_op_icbi[] = {
3925 &gen_op_icbi_raw,
3926 &gen_op_icbi_raw,
3927 #if defined(TARGET_PPC64)
3928 &gen_op_icbi_64_raw,
3929 &gen_op_icbi_64_raw,
3930 #endif
3931 };
3932 #else
3933 /* Full system - 64 bits mode */
3934 #if defined(TARGET_PPC64)
3935 static GenOpFunc *gen_op_icbi[] = {
3936 &gen_op_icbi_user,
3937 &gen_op_icbi_user,
3938 &gen_op_icbi_64_user,
3939 &gen_op_icbi_64_user,
3940 &gen_op_icbi_kernel,
3941 &gen_op_icbi_kernel,
3942 &gen_op_icbi_64_kernel,
3943 &gen_op_icbi_64_kernel,
3944 #if defined(TARGET_PPC64H)
3945 &gen_op_icbi_hypv,
3946 &gen_op_icbi_hypv,
3947 &gen_op_icbi_64_hypv,
3948 &gen_op_icbi_64_hypv,
3949 #endif
3950 };
3951 #else
3952 /* Full system - 32 bits mode */
3953 static GenOpFunc *gen_op_icbi[] = {
3954 &gen_op_icbi_user,
3955 &gen_op_icbi_user,
3956 &gen_op_icbi_kernel,
3957 &gen_op_icbi_kernel,
3958 };
3959 #endif
3960 #endif
3961
3962 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
3963 {
3964 /* NIP cannot be restored if the memory exception comes from an helper */
3965 gen_update_nip(ctx, ctx->nip - 4);
3966 gen_addr_reg_index(ctx);
3967 op_icbi();
3968 }
3969
3970 /* Optional: */
3971 /* dcba */
3972 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
3973 {
3974 /* interpreted as no-op */
3975 /* XXX: specification say this is treated as a store by the MMU
3976 * but does not generate any exception
3977 */
3978 }
3979
3980 /*** Segment register manipulation ***/
3981 /* Supervisor only: */
3982 /* mfsr */
3983 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3984 {
3985 #if defined(CONFIG_USER_ONLY)
3986 GEN_EXCP_PRIVREG(ctx);
3987 #else
3988 if (unlikely(!ctx->supervisor)) {
3989 GEN_EXCP_PRIVREG(ctx);
3990 return;
3991 }
3992 gen_op_set_T1(SR(ctx->opcode));
3993 gen_op_load_sr();
3994 gen_op_store_T0_gpr(rD(ctx->opcode));
3995 #endif
3996 }
3997
3998 /* mfsrin */
3999 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4000 {
4001 #if defined(CONFIG_USER_ONLY)
4002 GEN_EXCP_PRIVREG(ctx);
4003 #else
4004 if (unlikely(!ctx->supervisor)) {
4005 GEN_EXCP_PRIVREG(ctx);
4006 return;
4007 }
4008 gen_op_load_gpr_T1(rB(ctx->opcode));
4009 gen_op_srli_T1(28);
4010 gen_op_load_sr();
4011 gen_op_store_T0_gpr(rD(ctx->opcode));
4012 #endif
4013 }
4014
4015 /* mtsr */
4016 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4017 {
4018 #if defined(CONFIG_USER_ONLY)
4019 GEN_EXCP_PRIVREG(ctx);
4020 #else
4021 if (unlikely(!ctx->supervisor)) {
4022 GEN_EXCP_PRIVREG(ctx);
4023 return;
4024 }
4025 gen_op_load_gpr_T0(rS(ctx->opcode));
4026 gen_op_set_T1(SR(ctx->opcode));
4027 gen_op_store_sr();
4028 #endif
4029 }
4030
4031 /* mtsrin */
4032 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4033 {
4034 #if defined(CONFIG_USER_ONLY)
4035 GEN_EXCP_PRIVREG(ctx);
4036 #else
4037 if (unlikely(!ctx->supervisor)) {
4038 GEN_EXCP_PRIVREG(ctx);
4039 return;
4040 }
4041 gen_op_load_gpr_T0(rS(ctx->opcode));
4042 gen_op_load_gpr_T1(rB(ctx->opcode));
4043 gen_op_srli_T1(28);
4044 gen_op_store_sr();
4045 #endif
4046 }
4047
4048 #if defined(TARGET_PPC64)
4049 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4050 /* mfsr */
4051 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4052 {
4053 #if defined(CONFIG_USER_ONLY)
4054 GEN_EXCP_PRIVREG(ctx);
4055 #else
4056 if (unlikely(!ctx->supervisor)) {
4057 GEN_EXCP_PRIVREG(ctx);
4058 return;
4059 }
4060 gen_op_set_T1(SR(ctx->opcode));
4061 gen_op_load_slb();
4062 gen_op_store_T0_gpr(rD(ctx->opcode));
4063 #endif
4064 }
4065
4066 /* mfsrin */
4067 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4068 PPC_SEGMENT_64B)
4069 {
4070 #if defined(CONFIG_USER_ONLY)
4071 GEN_EXCP_PRIVREG(ctx);
4072 #else
4073 if (unlikely(!ctx->supervisor)) {
4074 GEN_EXCP_PRIVREG(ctx);
4075 return;
4076 }
4077 gen_op_load_gpr_T1(rB(ctx->opcode));
4078 gen_op_srli_T1(28);
4079 gen_op_load_slb();
4080 gen_op_store_T0_gpr(rD(ctx->opcode));
4081 #endif
4082 }
4083
4084 /* mtsr */
4085 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4086 {
4087 #if defined(CONFIG_USER_ONLY)
4088 GEN_EXCP_PRIVREG(ctx);
4089 #else
4090 if (unlikely(!ctx->supervisor)) {
4091 GEN_EXCP_PRIVREG(ctx);
4092 return;
4093 }
4094 gen_op_load_gpr_T0(rS(ctx->opcode));
4095 gen_op_set_T1(SR(ctx->opcode));
4096 gen_op_store_slb();
4097 #endif
4098 }
4099
4100 /* mtsrin */
4101 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4102 PPC_SEGMENT_64B)
4103 {
4104 #if defined(CONFIG_USER_ONLY)
4105 GEN_EXCP_PRIVREG(ctx);
4106 #else
4107 if (unlikely(!ctx->supervisor)) {
4108 GEN_EXCP_PRIVREG(ctx);
4109 return;
4110 }
4111 gen_op_load_gpr_T0(rS(ctx->opcode));
4112 gen_op_load_gpr_T1(rB(ctx->opcode));
4113 gen_op_srli_T1(28);
4114 gen_op_store_slb();
4115 #endif
4116 }
4117 #endif /* defined(TARGET_PPC64) */
4118
4119 /*** Lookaside buffer management ***/
4120 /* Optional & supervisor only: */
4121 /* tlbia */
4122 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4123 {
4124 #if defined(CONFIG_USER_ONLY)
4125 GEN_EXCP_PRIVOPC(ctx);
4126 #else
4127 if (unlikely(!ctx->supervisor)) {
4128 if (loglevel != 0)
4129 fprintf(logfile, "%s: ! supervisor\n", __func__);
4130 GEN_EXCP_PRIVOPC(ctx);
4131 return;
4132 }
4133 gen_op_tlbia();
4134 #endif
4135 }
4136
4137 /* tlbie */
4138 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4139 {
4140 #if defined(CONFIG_USER_ONLY)
4141 GEN_EXCP_PRIVOPC(ctx);
4142 #else
4143 if (unlikely(!ctx->supervisor)) {
4144 GEN_EXCP_PRIVOPC(ctx);
4145 return;
4146 }
4147 gen_op_load_gpr_T0(rB(ctx->opcode));
4148 #if defined(TARGET_PPC64)
4149 if (ctx->sf_mode)
4150 gen_op_tlbie_64();
4151 else
4152 #endif
4153 gen_op_tlbie();
4154 #endif
4155 }
4156
4157 /* tlbsync */
4158 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4159 {
4160 #if defined(CONFIG_USER_ONLY)
4161 GEN_EXCP_PRIVOPC(ctx);
4162 #else
4163 if (unlikely(!ctx->supervisor)) {
4164 GEN_EXCP_PRIVOPC(ctx);
4165 return;
4166 }
4167 /* This has no effect: it should ensure that all previous
4168 * tlbie have completed
4169 */
4170 GEN_STOP(ctx);
4171 #endif
4172 }
4173
4174 #if defined(TARGET_PPC64)
4175 /* slbia */
4176 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4177 {
4178 #if defined(CONFIG_USER_ONLY)
4179 GEN_EXCP_PRIVOPC(ctx);
4180 #else
4181 if (unlikely(!ctx->supervisor)) {
4182 if (loglevel != 0)
4183 fprintf(logfile, "%s: ! supervisor\n", __func__);
4184 GEN_EXCP_PRIVOPC(ctx);
4185 return;
4186 }
4187 gen_op_slbia();
4188 #endif
4189 }
4190
4191 /* slbie */
4192 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4193 {
4194 #if defined(CONFIG_USER_ONLY)
4195 GEN_EXCP_PRIVOPC(ctx);
4196 #else
4197 if (unlikely(!ctx->supervisor)) {
4198 GEN_EXCP_PRIVOPC(ctx);
4199 return;
4200 }
4201 gen_op_load_gpr_T0(rB(ctx->opcode));
4202 gen_op_slbie();
4203 #endif
4204 }
4205 #endif
4206
4207 /*** External control ***/
4208 /* Optional: */
4209 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4210 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
4211 #if defined(CONFIG_USER_ONLY)
4212 /* User-mode only */
4213 static GenOpFunc *gen_op_eciwx[] = {
4214 &gen_op_eciwx_raw,
4215 &gen_op_eciwx_le_raw,
4216 #if defined(TARGET_PPC64)
4217 &gen_op_eciwx_64_raw,
4218 &gen_op_eciwx_le_64_raw,
4219 #endif
4220 };
4221 static GenOpFunc *gen_op_ecowx[] = {
4222 &gen_op_ecowx_raw,
4223 &gen_op_ecowx_le_raw,
4224 #if defined(TARGET_PPC64)
4225 &gen_op_ecowx_64_raw,
4226 &gen_op_ecowx_le_64_raw,
4227 #endif
4228 };
4229 #else
4230 #if defined(TARGET_PPC64)
4231 /* Full system - 64 bits mode */
4232 static GenOpFunc *gen_op_eciwx[] = {
4233 &gen_op_eciwx_user,
4234 &gen_op_eciwx_le_user,
4235 &gen_op_eciwx_64_user,
4236 &gen_op_eciwx_le_64_user,
4237 &gen_op_eciwx_kernel,
4238 &gen_op_eciwx_le_kernel,
4239 &gen_op_eciwx_64_kernel,
4240 &gen_op_eciwx_le_64_kernel,
4241 #if defined(TARGET_PPC64H)
4242 &gen_op_eciwx_hypv,
4243 &gen_op_eciwx_le_hypv,
4244 &gen_op_eciwx_64_hypv,
4245 &gen_op_eciwx_le_64_hypv,
4246 #endif
4247 };
4248 static GenOpFunc *gen_op_ecowx[] = {
4249 &gen_op_ecowx_user,
4250 &gen_op_ecowx_le_user,
4251 &gen_op_ecowx_64_user,
4252 &gen_op_ecowx_le_64_user,
4253 &gen_op_ecowx_kernel,
4254 &gen_op_ecowx_le_kernel,
4255 &gen_op_ecowx_64_kernel,
4256 &gen_op_ecowx_le_64_kernel,
4257 #if defined(TARGET_PPC64H)
4258 &gen_op_ecowx_hypv,
4259 &gen_op_ecowx_le_hypv,
4260 &gen_op_ecowx_64_hypv,
4261 &gen_op_ecowx_le_64_hypv,
4262 #endif
4263 };
4264 #else
4265 /* Full system - 32 bits mode */
4266 static GenOpFunc *gen_op_eciwx[] = {
4267 &gen_op_eciwx_user,
4268 &gen_op_eciwx_le_user,
4269 &gen_op_eciwx_kernel,
4270 &gen_op_eciwx_le_kernel,
4271 };
4272 static GenOpFunc *gen_op_ecowx[] = {
4273 &gen_op_ecowx_user,
4274 &gen_op_ecowx_le_user,
4275 &gen_op_ecowx_kernel,
4276 &gen_op_ecowx_le_kernel,
4277 };
4278 #endif
4279 #endif
4280
4281 /* eciwx */
4282 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4283 {
4284 /* Should check EAR[E] & alignment ! */
4285 gen_addr_reg_index(ctx);
4286 op_eciwx();
4287 gen_op_store_T0_gpr(rD(ctx->opcode));
4288 }
4289
4290 /* ecowx */
4291 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4292 {
4293 /* Should check EAR[E] & alignment ! */
4294 gen_addr_reg_index(ctx);
4295 gen_op_load_gpr_T1(rS(ctx->opcode));
4296 op_ecowx();
4297 }
4298
4299 /* PowerPC 601 specific instructions */
4300 /* abs - abs. */
4301 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4302 {
4303 gen_op_load_gpr_T0(rA(ctx->opcode));
4304 gen_op_POWER_abs();
4305 gen_op_store_T0_gpr(rD(ctx->opcode));
4306 if (unlikely(Rc(ctx->opcode) != 0))
4307 gen_set_Rc0(ctx);
4308 }
4309
4310 /* abso - abso. */
4311 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4312 {
4313 gen_op_load_gpr_T0(rA(ctx->opcode));
4314 gen_op_POWER_abso();
4315 gen_op_store_T0_gpr(rD(ctx->opcode));
4316 if (unlikely(Rc(ctx->opcode) != 0))
4317 gen_set_Rc0(ctx);
4318 }
4319
4320 /* clcs */
4321 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4322 {
4323 gen_op_load_gpr_T0(rA(ctx->opcode));
4324 gen_op_POWER_clcs();
4325 /* Rc=1 sets CR0 to an undefined state */
4326 gen_op_store_T0_gpr(rD(ctx->opcode));
4327 }
4328
4329 /* div - div. */
4330 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4331 {
4332 gen_op_load_gpr_T0(rA(ctx->opcode));
4333 gen_op_load_gpr_T1(rB(ctx->opcode));
4334 gen_op_POWER_div();
4335 gen_op_store_T0_gpr(rD(ctx->opcode));
4336 if (unlikely(Rc(ctx->opcode) != 0))
4337 gen_set_Rc0(ctx);
4338 }
4339
4340 /* divo - divo. */
4341 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4342 {
4343 gen_op_load_gpr_T0(rA(ctx->opcode));
4344 gen_op_load_gpr_T1(rB(ctx->opcode));
4345 gen_op_POWER_divo();
4346 gen_op_store_T0_gpr(rD(ctx->opcode));
4347 if (unlikely(Rc(ctx->opcode) != 0))
4348 gen_set_Rc0(ctx);
4349 }
4350
4351 /* divs - divs. */
4352 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4353 {
4354 gen_op_load_gpr_T0(rA(ctx->opcode));
4355 gen_op_load_gpr_T1(rB(ctx->opcode));
4356 gen_op_POWER_divs();
4357 gen_op_store_T0_gpr(rD(ctx->opcode));
4358 if (unlikely(Rc(ctx->opcode) != 0))
4359 gen_set_Rc0(ctx);
4360 }
4361
4362 /* divso - divso. */
4363 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4364 {
4365 gen_op_load_gpr_T0(rA(ctx->opcode));
4366 gen_op_load_gpr_T1(rB(ctx->opcode));
4367 gen_op_POWER_divso();
4368 gen_op_store_T0_gpr(rD(ctx->opcode));
4369 if (unlikely(Rc(ctx->opcode) != 0))
4370 gen_set_Rc0(ctx);
4371 }
4372
4373 /* doz - doz. */
4374 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4375 {
4376 gen_op_load_gpr_T0(rA(ctx->opcode));
4377 gen_op_load_gpr_T1(rB(ctx->opcode));
4378 gen_op_POWER_doz();
4379 gen_op_store_T0_gpr(rD(ctx->opcode));
4380 if (unlikely(Rc(ctx->opcode) != 0))
4381 gen_set_Rc0(ctx);
4382 }
4383
4384 /* dozo - dozo. */
4385 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4386 {
4387 gen_op_load_gpr_T0(rA(ctx->opcode));
4388 gen_op_load_gpr_T1(rB(ctx->opcode));
4389 gen_op_POWER_dozo();
4390 gen_op_store_T0_gpr(rD(ctx->opcode));
4391 if (unlikely(Rc(ctx->opcode) != 0))
4392 gen_set_Rc0(ctx);
4393 }
4394
4395 /* dozi */
4396 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4397 {
4398 gen_op_load_gpr_T0(rA(ctx->opcode));
4399 gen_op_set_T1(SIMM(ctx->opcode));
4400 gen_op_POWER_doz();
4401 gen_op_store_T0_gpr(rD(ctx->opcode));
4402 }
4403
4404 /* As lscbx load from memory byte after byte, it's always endian safe */
4405 #define op_POWER_lscbx(start, ra, rb) \
4406 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4407 #if defined(CONFIG_USER_ONLY)
4408 static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4409 &gen_op_POWER_lscbx_raw,
4410 &gen_op_POWER_lscbx_raw,
4411 };
4412 #else
4413 static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4414 &gen_op_POWER_lscbx_user,
4415 &gen_op_POWER_lscbx_user,
4416 &gen_op_POWER_lscbx_kernel,
4417 &gen_op_POWER_lscbx_kernel,
4418 };
4419 #endif
4420
4421 /* lscbx - lscbx. */
4422 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4423 {
4424 int ra = rA(ctx->opcode);
4425 int rb = rB(ctx->opcode);
4426
4427 gen_addr_reg_index(ctx);
4428 if (ra == 0) {
4429 ra = rb;
4430 }
4431 /* NIP cannot be restored if the memory exception comes from an helper */
4432 gen_update_nip(ctx, ctx->nip - 4);
4433 gen_op_load_xer_bc();
4434 gen_op_load_xer_cmp();
4435 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4436 gen_op_store_xer_bc();
4437 if (unlikely(Rc(ctx->opcode) != 0))
4438 gen_set_Rc0(ctx);
4439 }
4440
4441 /* maskg - maskg. */
4442 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4443 {
4444 gen_op_load_gpr_T0(rS(ctx->opcode));
4445 gen_op_load_gpr_T1(rB(ctx->opcode));
4446 gen_op_POWER_maskg();
4447 gen_op_store_T0_gpr(rA(ctx->opcode));
4448 if (unlikely(Rc(ctx->opcode) != 0))
4449 gen_set_Rc0(ctx);
4450 }
4451
4452 /* maskir - maskir. */
4453 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4454 {
4455 gen_op_load_gpr_T0(rA(ctx->opcode));
4456 gen_op_load_gpr_T1(rS(ctx->opcode));
4457 gen_op_load_gpr_T2(rB(ctx->opcode));
4458 gen_op_POWER_maskir();
4459 gen_op_store_T0_gpr(rA(ctx->opcode));
4460 if (unlikely(Rc(ctx->opcode) != 0))
4461 gen_set_Rc0(ctx);
4462 }
4463
4464 /* mul - mul. */
4465 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4466 {
4467 gen_op_load_gpr_T0(rA(ctx->opcode));
4468 gen_op_load_gpr_T1(rB(ctx->opcode));
4469 gen_op_POWER_mul();
4470 gen_op_store_T0_gpr(rD(ctx->opcode));
4471 if (unlikely(Rc(ctx->opcode) != 0))
4472 gen_set_Rc0(ctx);
4473 }
4474
4475 /* mulo - mulo. */
4476 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4477 {
4478 gen_op_load_gpr_T0(rA(ctx->opcode));
4479 gen_op_load_gpr_T1(rB(ctx->opcode));
4480 gen_op_POWER_mulo();
4481 gen_op_store_T0_gpr(rD(ctx->opcode));
4482 if (unlikely(Rc(ctx->opcode) != 0))
4483 gen_set_Rc0(ctx);
4484 }
4485
4486 /* nabs - nabs. */
4487 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4488 {
4489 gen_op_load_gpr_T0(rA(ctx->opcode));
4490 gen_op_POWER_nabs();
4491 gen_op_store_T0_gpr(rD(ctx->opcode));
4492 if (unlikely(Rc(ctx->opcode) != 0))
4493 gen_set_Rc0(ctx);
4494 }
4495
4496 /* nabso - nabso. */
4497 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4498 {
4499 gen_op_load_gpr_T0(rA(ctx->opcode));
4500 gen_op_POWER_nabso();
4501 gen_op_store_T0_gpr(rD(ctx->opcode));
4502 if (unlikely(Rc(ctx->opcode) != 0))
4503 gen_set_Rc0(ctx);
4504 }
4505
4506 /* rlmi - rlmi. */
4507 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4508 {
4509 uint32_t mb, me;
4510
4511 mb = MB(ctx->opcode);
4512 me = ME(ctx->opcode);
4513 gen_op_load_gpr_T0(rS(ctx->opcode));
4514 gen_op_load_gpr_T1(rA(ctx->opcode));
4515 gen_op_load_gpr_T2(rB(ctx->opcode));
4516 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4517 gen_op_store_T0_gpr(rA(ctx->opcode));
4518 if (unlikely(Rc(ctx->opcode) != 0))
4519 gen_set_Rc0(ctx);
4520 }
4521
4522 /* rrib - rrib. */
4523 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4524 {
4525 gen_op_load_gpr_T0(rS(ctx->opcode));
4526 gen_op_load_gpr_T1(rA(ctx->opcode));
4527 gen_op_load_gpr_T2(rB(ctx->opcode));
4528 gen_op_POWER_rrib();
4529 gen_op_store_T0_gpr(rA(ctx->opcode));
4530 if (unlikely(Rc(ctx->opcode) != 0))
4531 gen_set_Rc0(ctx);
4532 }
4533
4534 /* sle - sle. */
4535 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4536 {
4537 gen_op_load_gpr_T0(rS(ctx->opcode));
4538 gen_op_load_gpr_T1(rB(ctx->opcode));
4539 gen_op_POWER_sle();
4540 gen_op_store_T0_gpr(rA(ctx->opcode));
4541 if (unlikely(Rc(ctx->opcode) != 0))
4542 gen_set_Rc0(ctx);
4543 }
4544
4545 /* sleq - sleq. */
4546 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4547 {
4548 gen_op_load_gpr_T0(rS(ctx->opcode));
4549 gen_op_load_gpr_T1(rB(ctx->opcode));
4550 gen_op_POWER_sleq();
4551 gen_op_store_T0_gpr(rA(ctx->opcode));
4552 if (unlikely(Rc(ctx->opcode) != 0))
4553 gen_set_Rc0(ctx);
4554 }
4555
4556 /* sliq - sliq. */
4557 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4558 {
4559 gen_op_load_gpr_T0(rS(ctx->opcode));
4560 gen_op_set_T1(SH(ctx->opcode));
4561 gen_op_POWER_sle();
4562 gen_op_store_T0_gpr(rA(ctx->opcode));
4563 if (unlikely(Rc(ctx->opcode) != 0))
4564 gen_set_Rc0(ctx);
4565 }
4566
4567 /* slliq - slliq. */
4568 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4569 {
4570 gen_op_load_gpr_T0(rS(ctx->opcode));
4571 gen_op_set_T1(SH(ctx->opcode));
4572 gen_op_POWER_sleq();
4573 gen_op_store_T0_gpr(rA(ctx->opcode));
4574 if (unlikely(Rc(ctx->opcode) != 0))
4575 gen_set_Rc0(ctx);
4576 }
4577
4578 /* sllq - sllq. */
4579 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4580 {
4581 gen_op_load_gpr_T0(rS(ctx->opcode));
4582 gen_op_load_gpr_T1(rB(ctx->opcode));
4583 gen_op_POWER_sllq();
4584 gen_op_store_T0_gpr(rA(ctx->opcode));
4585 if (unlikely(Rc(ctx->opcode) != 0))
4586 gen_set_Rc0(ctx);
4587 }
4588
4589 /* slq - slq. */
4590 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4591 {
4592 gen_op_load_gpr_T0(rS(ctx->opcode));
4593 gen_op_load_gpr_T1(rB(ctx->opcode));
4594 gen_op_POWER_slq();
4595 gen_op_store_T0_gpr(rA(ctx->opcode));
4596 if (unlikely(Rc(ctx->opcode) != 0))
4597 gen_set_Rc0(ctx);
4598 }
4599
4600 /* sraiq - sraiq. */
4601 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4602 {
4603 gen_op_load_gpr_T0(rS(ctx->opcode));
4604 gen_op_set_T1(SH(ctx->opcode));
4605 gen_op_POWER_sraq();
4606 gen_op_store_T0_gpr(rA(ctx->opcode));
4607 if (unlikely(Rc(ctx->opcode) != 0))
4608 gen_set_Rc0(ctx);
4609 }
4610
4611 /* sraq - sraq. */
4612 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4613 {
4614 gen_op_load_gpr_T0(rS(ctx->opcode));
4615 gen_op_load_gpr_T1(rB(ctx->opcode));
4616 gen_op_POWER_sraq();
4617 gen_op_store_T0_gpr(rA(ctx->opcode));
4618 if (unlikely(Rc(ctx->opcode) != 0))
4619 gen_set_Rc0(ctx);
4620 }
4621
4622 /* sre - sre. */
4623 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4624 {
4625 gen_op_load_gpr_T0(rS(ctx->opcode));
4626 gen_op_load_gpr_T1(rB(ctx->opcode));
4627 gen_op_POWER_sre();
4628 gen_op_store_T0_gpr(rA(ctx->opcode));
4629 if (unlikely(Rc(ctx->opcode) != 0))
4630 gen_set_Rc0(ctx);
4631 }
4632
4633 /* srea - srea. */
4634 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4635 {
4636 gen_op_load_gpr_T0(rS(ctx->opcode));
4637 gen_op_load_gpr_T1(rB(ctx->opcode));
4638 gen_op_POWER_srea();
4639 gen_op_store_T0_gpr(rA(ctx->opcode));
4640 if (unlikely(Rc(ctx->opcode) != 0))
4641 gen_set_Rc0(ctx);
4642 }
4643
4644 /* sreq */
4645 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4646 {
4647 gen_op_load_gpr_T0(rS(ctx->opcode));
4648 gen_op_load_gpr_T1(rB(ctx->opcode));
4649 gen_op_POWER_sreq();
4650 gen_op_store_T0_gpr(rA(ctx->opcode));
4651 if (unlikely(Rc(ctx->opcode) != 0))
4652 gen_set_Rc0(ctx);
4653 }
4654
4655 /* sriq */
4656 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4657 {
4658 gen_op_load_gpr_T0(rS(ctx->opcode));
4659 gen_op_set_T1(SH(ctx->opcode));
4660 gen_op_POWER_srq();
4661 gen_op_store_T0_gpr(rA(ctx->opcode));
4662 if (unlikely(Rc(ctx->opcode) != 0))
4663 gen_set_Rc0(ctx);
4664 }
4665
4666 /* srliq */
4667 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4668 {
4669 gen_op_load_gpr_T0(rS(ctx->opcode));
4670 gen_op_load_gpr_T1(rB(ctx->opcode));
4671 gen_op_set_T1(SH(ctx->opcode));
4672 gen_op_POWER_srlq();
4673 gen_op_store_T0_gpr(rA(ctx->opcode));
4674 if (unlikely(Rc(ctx->opcode) != 0))
4675 gen_set_Rc0(ctx);
4676 }
4677
4678 /* srlq */
4679 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4680 {
4681 gen_op_load_gpr_T0(rS(ctx->opcode));
4682 gen_op_load_gpr_T1(rB(ctx->opcode));
4683 gen_op_POWER_srlq();
4684 gen_op_store_T0_gpr(rA(ctx->opcode));
4685 if (unlikely(Rc(ctx->opcode) != 0))
4686 gen_set_Rc0(ctx);
4687 }
4688
4689 /* srq */
4690 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4691 {
4692 gen_op_load_gpr_T0(rS(ctx->opcode));
4693 gen_op_load_gpr_T1(rB(ctx->opcode));
4694 gen_op_POWER_srq();
4695 gen_op_store_T0_gpr(rA(ctx->opcode));
4696 if (unlikely(Rc(ctx->opcode) != 0))
4697 gen_set_Rc0(ctx);
4698 }
4699
4700 /* PowerPC 602 specific instructions */
4701 /* dsa */
4702 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4703 {
4704 /* XXX: TODO */
4705 GEN_EXCP_INVAL(ctx);
4706 }
4707
4708 /* esa */
4709 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4710 {
4711 /* XXX: TODO */
4712 GEN_EXCP_INVAL(ctx);
4713 }
4714
4715 /* mfrom */
4716 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4717 {
4718 #if defined(CONFIG_USER_ONLY)
4719 GEN_EXCP_PRIVOPC(ctx);
4720 #else
4721 if (unlikely(!ctx->supervisor)) {
4722 GEN_EXCP_PRIVOPC(ctx);
4723 return;
4724 }
4725 gen_op_load_gpr_T0(rA(ctx->opcode));
4726 gen_op_602_mfrom();
4727 gen_op_store_T0_gpr(rD(ctx->opcode));
4728 #endif
4729 }
4730
4731 /* 602 - 603 - G2 TLB management */
4732 /* tlbld */
4733 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4734 {
4735 #if defined(CONFIG_USER_ONLY)
4736 GEN_EXCP_PRIVOPC(ctx);
4737 #else
4738 if (unlikely(!ctx->supervisor)) {
4739 GEN_EXCP_PRIVOPC(ctx);
4740 return;
4741 }
4742 gen_op_load_gpr_T0(rB(ctx->opcode));
4743 gen_op_6xx_tlbld();
4744 #endif
4745 }
4746
4747 /* tlbli */
4748 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4749 {
4750 #if defined(CONFIG_USER_ONLY)
4751 GEN_EXCP_PRIVOPC(ctx);
4752 #else
4753 if (unlikely(!ctx->supervisor)) {
4754 GEN_EXCP_PRIVOPC(ctx);
4755 return;
4756 }
4757 gen_op_load_gpr_T0(rB(ctx->opcode));
4758 gen_op_6xx_tlbli();
4759 #endif
4760 }
4761
4762 /* 74xx TLB management */
4763 /* tlbld */
4764 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4765 {
4766 #if defined(CONFIG_USER_ONLY)
4767 GEN_EXCP_PRIVOPC(ctx);
4768 #else
4769 if (unlikely(!ctx->supervisor)) {
4770 GEN_EXCP_PRIVOPC(ctx);
4771 return;
4772 }
4773 gen_op_load_gpr_T0(rB(ctx->opcode));
4774 gen_op_74xx_tlbld();
4775 #endif
4776 }
4777
4778 /* tlbli */
4779 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4780 {
4781 #if defined(CONFIG_USER_ONLY)
4782 GEN_EXCP_PRIVOPC(ctx);
4783 #else
4784 if (unlikely(!ctx->supervisor)) {
4785 GEN_EXCP_PRIVOPC(ctx);
4786 return;
4787 }
4788 gen_op_load_gpr_T0(rB(ctx->opcode));
4789 gen_op_74xx_tlbli();
4790 #endif
4791 }
4792
4793 /* POWER instructions not in PowerPC 601 */
4794 /* clf */
4795 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4796 {
4797 /* Cache line flush: implemented as no-op */
4798 }
4799
4800 /* cli */
4801 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4802 {
4803 /* Cache line invalidate: privileged and treated as no-op */
4804 #if defined(CONFIG_USER_ONLY)
4805 GEN_EXCP_PRIVOPC(ctx);
4806 #else
4807 if (unlikely(!ctx->supervisor)) {
4808 GEN_EXCP_PRIVOPC(ctx);
4809 return;
4810 }
4811 #endif
4812 }
4813
4814 /* dclst */
4815 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4816 {
4817 /* Data cache line store: treated as no-op */
4818 }
4819
4820 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4821 {
4822 #if defined(CONFIG_USER_ONLY)
4823 GEN_EXCP_PRIVOPC(ctx);
4824 #else
4825 if (unlikely(!ctx->supervisor)) {
4826 GEN_EXCP_PRIVOPC(ctx);
4827 return;
4828 }
4829 int ra = rA(ctx->opcode);
4830 int rd = rD(ctx->opcode);
4831
4832 gen_addr_reg_index(ctx);
4833 gen_op_POWER_mfsri();
4834 gen_op_store_T0_gpr(rd);
4835 if (ra != 0 && ra != rd)
4836 gen_op_store_T1_gpr(ra);
4837 #endif
4838 }
4839
4840 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4841 {
4842 #if defined(CONFIG_USER_ONLY)
4843 GEN_EXCP_PRIVOPC(ctx);
4844 #else
4845 if (unlikely(!ctx->supervisor)) {
4846 GEN_EXCP_PRIVOPC(ctx);
4847 return;
4848 }
4849 gen_addr_reg_index(ctx);
4850 gen_op_POWER_rac();
4851 gen_op_store_T0_gpr(rD(ctx->opcode));
4852 #endif
4853 }
4854
4855 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4856 {
4857 #if defined(CONFIG_USER_ONLY)
4858 GEN_EXCP_PRIVOPC(ctx);
4859 #else
4860 if (unlikely(!ctx->supervisor)) {
4861 GEN_EXCP_PRIVOPC(ctx);
4862 return;
4863 }
4864 gen_op_POWER_rfsvc();
4865 GEN_SYNC(ctx);
4866 #endif
4867 }
4868
4869 /* svc is not implemented for now */
4870
4871 /* POWER2 specific instructions */
4872 /* Quad manipulation (load/store two floats at a time) */
4873 #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4874 #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4875 #if defined(CONFIG_USER_ONLY)
4876 static GenOpFunc *gen_op_POWER2_lfq[] = {
4877 &gen_op_POWER2_lfq_le_raw,
4878 &gen_op_POWER2_lfq_raw,
4879 };
4880 static GenOpFunc *gen_op_POWER2_stfq[] = {
4881 &gen_op_POWER2_stfq_le_raw,
4882 &gen_op_POWER2_stfq_raw,
4883 };
4884 #else
4885 static GenOpFunc *gen_op_POWER2_lfq[] = {
4886 &gen_op_POWER2_lfq_le_user,
4887 &gen_op_POWER2_lfq_user,
4888 &gen_op_POWER2_lfq_le_kernel,
4889 &gen_op_POWER2_lfq_kernel,
4890 };
4891 static GenOpFunc *gen_op_POWER2_stfq[] = {
4892 &gen_op_POWER2_stfq_le_user,
4893 &gen_op_POWER2_stfq_user,
4894 &gen_op_POWER2_stfq_le_kernel,
4895 &gen_op_POWER2_stfq_kernel,
4896 };
4897 #endif
4898
4899 /* lfq */
4900 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4901 {
4902 /* NIP cannot be restored if the memory exception comes from an helper */
4903 gen_update_nip(ctx, ctx->nip - 4);
4904 gen_addr_imm_index(ctx, 0);
4905 op_POWER2_lfq();
4906 gen_op_store_FT0_fpr(rD(ctx->opcode));
4907 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4908 }
4909
4910 /* lfqu */
4911 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4912 {
4913 int ra = rA(ctx->opcode);
4914
4915 /* NIP cannot be restored if the memory exception comes from an helper */
4916 gen_update_nip(ctx, ctx->nip - 4);
4917 gen_addr_imm_index(ctx, 0);
4918 op_POWER2_lfq();
4919 gen_op_store_FT0_fpr(rD(ctx->opcode));
4920 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4921 if (ra != 0)
4922 gen_op_store_T0_gpr(ra);
4923 }
4924
4925 /* lfqux */
4926 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4927 {
4928 int ra = rA(ctx->opcode);
4929
4930 /* NIP cannot be restored if the memory exception comes from an helper */
4931 gen_update_nip(ctx, ctx->nip - 4);
4932 gen_addr_reg_index(ctx);
4933 op_POWER2_lfq();
4934 gen_op_store_FT0_fpr(rD(ctx->opcode));
4935 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4936 if (ra != 0)
4937 gen_op_store_T0_gpr(ra);
4938 }
4939
4940 /* lfqx */
4941 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4942 {
4943 /* NIP cannot be restored if the memory exception comes from an helper */
4944 gen_update_nip(ctx, ctx->nip - 4);
4945 gen_addr_reg_index(ctx);
4946 op_POWER2_lfq();
4947 gen_op_store_FT0_fpr(rD(ctx->opcode));
4948 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4949 }
4950
4951 /* stfq */
4952 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4953 {
4954 /* NIP cannot be restored if the memory exception comes from an helper */
4955 gen_update_nip(ctx, ctx->nip - 4);
4956 gen_addr_imm_index(ctx, 0);
4957 gen_op_load_fpr_FT0(rS(ctx->opcode));
4958 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4959 op_POWER2_stfq();
4960 }
4961
4962 /* stfqu */
4963 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4964 {
4965 int ra = rA(ctx->opcode);
4966
4967 /* NIP cannot be restored if the memory exception comes from an helper */
4968 gen_update_nip(ctx, ctx->nip - 4);
4969 gen_addr_imm_index(ctx, 0);
4970 gen_op_load_fpr_FT0(rS(ctx->opcode));
4971 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4972 op_POWER2_stfq();
4973 if (ra != 0)
4974 gen_op_store_T0_gpr(ra);
4975 }
4976
4977 /* stfqux */
4978 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4979 {
4980 int ra = rA(ctx->opcode);
4981
4982 /* NIP cannot be restored if the memory exception comes from an helper */
4983 gen_update_nip(ctx, ctx->nip - 4);
4984 gen_addr_reg_index(ctx);
4985 gen_op_load_fpr_FT0(rS(ctx->opcode));
4986 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4987 op_POWER2_stfq();
4988 if (ra != 0)
4989 gen_op_store_T0_gpr(ra);
4990 }
4991
4992 /* stfqx */
4993 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4994 {
4995 /* NIP cannot be restored if the memory exception comes from an helper */
4996 gen_update_nip(ctx, ctx->nip - 4);
4997 gen_addr_reg_index(ctx);
4998 gen_op_load_fpr_FT0(rS(ctx->opcode));
4999 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5000 op_POWER2_stfq();
5001 }
5002
5003 /* BookE specific instructions */
5004 /* XXX: not implemented on 440 ? */
5005 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
5006 {
5007 /* XXX: TODO */
5008 GEN_EXCP_INVAL(ctx);
5009 }
5010
5011 /* XXX: not implemented on 440 ? */
5012 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
5013 {
5014 #if defined(CONFIG_USER_ONLY)
5015 GEN_EXCP_PRIVOPC(ctx);
5016 #else
5017 if (unlikely(!ctx->supervisor)) {
5018 GEN_EXCP_PRIVOPC(ctx);
5019 return;
5020 }
5021 gen_addr_reg_index(ctx);
5022 /* Use the same micro-ops as for tlbie */
5023 #if defined(TARGET_PPC64)
5024 if (ctx->sf_mode)
5025 gen_op_tlbie_64();
5026 else
5027 #endif
5028 gen_op_tlbie();
5029 #endif
5030 }
5031
5032 /* All 405 MAC instructions are translated here */
5033 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5034 int opc2, int opc3,
5035 int ra, int rb, int rt, int Rc)
5036 {
5037 gen_op_load_gpr_T0(ra);
5038 gen_op_load_gpr_T1(rb);
5039 switch (opc3 & 0x0D) {
5040 case 0x05:
5041 /* macchw - macchw. - macchwo - macchwo. */
5042 /* macchws - macchws. - macchwso - macchwso. */
5043 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5044 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5045 /* mulchw - mulchw. */
5046 gen_op_405_mulchw();
5047 break;
5048 case 0x04:
5049 /* macchwu - macchwu. - macchwuo - macchwuo. */
5050 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5051 /* mulchwu - mulchwu. */
5052 gen_op_405_mulchwu();
5053 break;
5054 case 0x01:
5055 /* machhw - machhw. - machhwo - machhwo. */
5056 /* machhws - machhws. - machhwso - machhwso. */
5057 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5058 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5059 /* mulhhw - mulhhw. */
5060 gen_op_405_mulhhw();
5061 break;
5062 case 0x00:
5063 /* machhwu - machhwu. - machhwuo - machhwuo. */
5064 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5065 /* mulhhwu - mulhhwu. */
5066 gen_op_405_mulhhwu();
5067 break;
5068 case 0x0D:
5069 /* maclhw - maclhw. - maclhwo - maclhwo. */
5070 /* maclhws - maclhws. - maclhwso - maclhwso. */
5071 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5072 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5073 /* mullhw - mullhw. */
5074 gen_op_405_mullhw();
5075 break;
5076 case 0x0C:
5077 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5078 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5079 /* mullhwu - mullhwu. */
5080 gen_op_405_mullhwu();
5081 break;
5082 }
5083 if (opc2 & 0x02) {
5084 /* nmultiply-and-accumulate (0x0E) */
5085 gen_op_neg();
5086 }
5087 if (opc2 & 0x04) {
5088 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
5089 gen_op_load_gpr_T2(rt);
5090 gen_op_move_T1_T0();
5091 gen_op_405_add_T0_T2();
5092 }
5093 if (opc3 & 0x10) {
5094 /* Check overflow */
5095 if (opc3 & 0x01)
5096 gen_op_405_check_ov();
5097 else
5098 gen_op_405_check_ovu();
5099 }
5100 if (opc3 & 0x02) {
5101 /* Saturate */
5102 if (opc3 & 0x01)
5103 gen_op_405_check_sat();
5104 else
5105 gen_op_405_check_satu();
5106 }
5107 gen_op_store_T0_gpr(rt);
5108 if (unlikely(Rc) != 0) {
5109 /* Update Rc0 */
5110 gen_set_Rc0(ctx);
5111 }
5112 }
5113
5114 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5115 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5116 { \
5117 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5118 rD(ctx->opcode), Rc(ctx->opcode)); \
5119 }
5120
5121 /* macchw - macchw. */
5122 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5123 /* macchwo - macchwo. */
5124 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5125 /* macchws - macchws. */
5126 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5127 /* macchwso - macchwso. */
5128 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5129 /* macchwsu - macchwsu. */
5130 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5131 /* macchwsuo - macchwsuo. */
5132 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5133 /* macchwu - macchwu. */
5134 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5135 /* macchwuo - macchwuo. */
5136 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5137 /* machhw - machhw. */
5138 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5139 /* machhwo - machhwo. */
5140 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5141 /* machhws - machhws. */
5142 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5143 /* machhwso - machhwso. */
5144 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5145 /* machhwsu - machhwsu. */
5146 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5147 /* machhwsuo - machhwsuo. */
5148 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5149 /* machhwu - machhwu. */
5150 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5151 /* machhwuo - machhwuo. */
5152 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5153 /* maclhw - maclhw. */
5154 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5155 /* maclhwo - maclhwo. */
5156 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5157 /* maclhws - maclhws. */
5158 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5159 /* maclhwso - maclhwso. */
5160 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5161 /* maclhwu - maclhwu. */
5162 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5163 /* maclhwuo - maclhwuo. */
5164 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5165 /* maclhwsu - maclhwsu. */
5166 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5167 /* maclhwsuo - maclhwsuo. */
5168 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5169 /* nmacchw - nmacchw. */
5170 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5171 /* nmacchwo - nmacchwo. */
5172 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5173 /* nmacchws - nmacchws. */
5174 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5175 /* nmacchwso - nmacchwso. */
5176 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5177 /* nmachhw - nmachhw. */
5178 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5179 /* nmachhwo - nmachhwo. */
5180 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5181 /* nmachhws - nmachhws. */
5182 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5183 /* nmachhwso - nmachhwso. */
5184 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5185 /* nmaclhw - nmaclhw. */
5186 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5187 /* nmaclhwo - nmaclhwo. */
5188 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5189 /* nmaclhws - nmaclhws. */
5190 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5191 /* nmaclhwso - nmaclhwso. */
5192 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5193
5194 /* mulchw - mulchw. */
5195 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5196 /* mulchwu - mulchwu. */
5197 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5198 /* mulhhw - mulhhw. */
5199 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5200 /* mulhhwu - mulhhwu. */
5201 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5202 /* mullhw - mullhw. */
5203 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5204 /* mullhwu - mullhwu. */
5205 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5206
5207 /* mfdcr */
5208 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
5209 {
5210 #if defined(CONFIG_USER_ONLY)
5211 GEN_EXCP_PRIVREG(ctx);
5212 #else
5213 uint32_t dcrn = SPR(ctx->opcode);
5214
5215 if (unlikely(!ctx->supervisor)) {
5216 GEN_EXCP_PRIVREG(ctx);
5217 return;
5218 }
5219 gen_op_set_T0(dcrn);
5220 gen_op_load_dcr();
5221 gen_op_store_T0_gpr(rD(ctx->opcode));
5222 #endif
5223 }
5224
5225 /* mtdcr */
5226 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
5227 {
5228 #if defined(CONFIG_USER_ONLY)
5229 GEN_EXCP_PRIVREG(ctx);
5230 #else
5231 uint32_t dcrn = SPR(ctx->opcode);
5232
5233 if (unlikely(!ctx->supervisor)) {
5234 GEN_EXCP_PRIVREG(ctx);
5235 return;
5236 }
5237 gen_op_set_T0(dcrn);
5238 gen_op_load_gpr_T1(rS(ctx->opcode));
5239 gen_op_store_dcr();
5240 #endif
5241 }
5242
5243 /* mfdcrx */
5244 /* XXX: not implemented on 440 ? */
5245 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
5246 {
5247 #if defined(CONFIG_USER_ONLY)
5248 GEN_EXCP_PRIVREG(ctx);
5249 #else
5250 if (unlikely(!ctx->supervisor)) {
5251 GEN_EXCP_PRIVREG(ctx);
5252 return;
5253 }
5254 gen_op_load_gpr_T0(rA(ctx->opcode));
5255 gen_op_load_dcr();
5256 gen_op_store_T0_gpr(rD(ctx->opcode));
5257 /* Note: Rc update flag set leads to undefined state of Rc0 */
5258 #endif
5259 }
5260
5261 /* mtdcrx */
5262 /* XXX: not implemented on 440 ? */
5263 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
5264 {
5265 #if defined(CONFIG_USER_ONLY)
5266 GEN_EXCP_PRIVREG(ctx);
5267 #else
5268 if (unlikely(!ctx->supervisor)) {
5269 GEN_EXCP_PRIVREG(ctx);
5270 return;
5271 }
5272 gen_op_load_gpr_T0(rA(ctx->opcode));
5273 gen_op_load_gpr_T1(rS(ctx->opcode));
5274 gen_op_store_dcr();
5275 /* Note: Rc update flag set leads to undefined state of Rc0 */
5276 #endif
5277 }
5278
5279 /* mfdcrux (PPC 460) : user-mode access to DCR */
5280 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5281 {
5282 gen_op_load_gpr_T0(rA(ctx->opcode));
5283 gen_op_load_dcr();
5284 gen_op_store_T0_gpr(rD(ctx->opcode));
5285 /* Note: Rc update flag set leads to undefined state of Rc0 */
5286 }
5287
5288 /* mtdcrux (PPC 460) : user-mode access to DCR */
5289 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5290 {
5291 gen_op_load_gpr_T0(rA(ctx->opcode));
5292 gen_op_load_gpr_T1(rS(ctx->opcode));
5293 gen_op_store_dcr();
5294 /* Note: Rc update flag set leads to undefined state of Rc0 */
5295 }
5296
5297 /* dccci */
5298 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5299 {
5300 #if defined(CONFIG_USER_ONLY)
5301 GEN_EXCP_PRIVOPC(ctx);
5302 #else
5303 if (unlikely(!ctx->supervisor)) {
5304 GEN_EXCP_PRIVOPC(ctx);
5305 return;
5306 }
5307 /* interpreted as no-op */
5308 #endif
5309 }
5310
5311 /* dcread */
5312 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5313 {
5314 #if defined(CONFIG_USER_ONLY)
5315 GEN_EXCP_PRIVOPC(ctx);
5316 #else
5317 if (unlikely(!ctx->supervisor)) {
5318 GEN_EXCP_PRIVOPC(ctx);
5319 return;
5320 }
5321 gen_addr_reg_index(ctx);
5322 op_ldst(lwz);
5323 gen_op_store_T0_gpr(rD(ctx->opcode));
5324 #endif
5325 }
5326
5327 /* icbt */
5328 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5329 {
5330 /* interpreted as no-op */
5331 /* XXX: specification say this is treated as a load by the MMU
5332 * but does not generate any exception
5333 */
5334 }
5335
5336 /* iccci */
5337 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5338 {
5339 #if defined(CONFIG_USER_ONLY)
5340 GEN_EXCP_PRIVOPC(ctx);
5341 #else
5342 if (unlikely(!ctx->supervisor)) {
5343 GEN_EXCP_PRIVOPC(ctx);
5344 return;
5345 }
5346 /* interpreted as no-op */
5347 #endif
5348 }
5349
5350 /* icread */
5351 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5352 {
5353 #if defined(CONFIG_USER_ONLY)
5354 GEN_EXCP_PRIVOPC(ctx);
5355 #else
5356 if (unlikely(!ctx->supervisor)) {
5357 GEN_EXCP_PRIVOPC(ctx);
5358 return;
5359 }
5360 /* interpreted as no-op */
5361 #endif
5362 }
5363
5364 /* rfci (supervisor only) */
5365 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5366 {
5367 #if defined(CONFIG_USER_ONLY)
5368 GEN_EXCP_PRIVOPC(ctx);
5369 #else
5370 if (unlikely(!ctx->supervisor)) {
5371 GEN_EXCP_PRIVOPC(ctx);
5372 return;
5373 }
5374 /* Restore CPU state */
5375 gen_op_40x_rfci();
5376 GEN_SYNC(ctx);
5377 #endif
5378 }
5379
5380 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5381 {
5382 #if defined(CONFIG_USER_ONLY)
5383 GEN_EXCP_PRIVOPC(ctx);
5384 #else
5385 if (unlikely(!ctx->supervisor)) {
5386 GEN_EXCP_PRIVOPC(ctx);
5387 return;
5388 }
5389 /* Restore CPU state */
5390 gen_op_rfci();
5391 GEN_SYNC(ctx);
5392 #endif
5393 }
5394
5395 /* BookE specific */
5396 /* XXX: not implemented on 440 ? */
5397 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
5398 {
5399 #if defined(CONFIG_USER_ONLY)
5400 GEN_EXCP_PRIVOPC(ctx);
5401 #else
5402 if (unlikely(!ctx->supervisor)) {
5403 GEN_EXCP_PRIVOPC(ctx);
5404 return;
5405 }
5406 /* Restore CPU state */
5407 gen_op_rfdi();
5408 GEN_SYNC(ctx);
5409 #endif
5410 }
5411
5412 /* XXX: not implemented on 440 ? */
5413 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5414 {
5415 #if defined(CONFIG_USER_ONLY)
5416 GEN_EXCP_PRIVOPC(ctx);
5417 #else
5418 if (unlikely(!ctx->supervisor)) {
5419 GEN_EXCP_PRIVOPC(ctx);
5420 return;
5421 }
5422 /* Restore CPU state */
5423 gen_op_rfmci();
5424 GEN_SYNC(ctx);
5425 #endif
5426 }
5427
5428 /* TLB management - PowerPC 405 implementation */
5429 /* tlbre */
5430 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5431 {
5432 #if defined(CONFIG_USER_ONLY)
5433 GEN_EXCP_PRIVOPC(ctx);
5434 #else
5435 if (unlikely(!ctx->supervisor)) {
5436 GEN_EXCP_PRIVOPC(ctx);
5437 return;
5438 }
5439 switch (rB(ctx->opcode)) {
5440 case 0:
5441 gen_op_load_gpr_T0(rA(ctx->opcode));
5442 gen_op_4xx_tlbre_hi();
5443 gen_op_store_T0_gpr(rD(ctx->opcode));
5444 break;
5445 case 1:
5446 gen_op_load_gpr_T0(rA(ctx->opcode));
5447 gen_op_4xx_tlbre_lo();
5448 gen_op_store_T0_gpr(rD(ctx->opcode));
5449 break;
5450 default:
5451 GEN_EXCP_INVAL(ctx);
5452 break;
5453 }
5454 #endif
5455 }
5456
5457 /* tlbsx - tlbsx. */
5458 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5459 {
5460 #if defined(CONFIG_USER_ONLY)
5461 GEN_EXCP_PRIVOPC(ctx);
5462 #else
5463 if (unlikely(!ctx->supervisor)) {
5464 GEN_EXCP_PRIVOPC(ctx);
5465 return;
5466 }
5467 gen_addr_reg_index(ctx);
5468 gen_op_4xx_tlbsx();
5469 if (Rc(ctx->opcode))
5470 gen_op_4xx_tlbsx_check();
5471 gen_op_store_T0_gpr(rD(ctx->opcode));
5472 #endif
5473 }
5474
5475 /* tlbwe */
5476 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5477 {
5478 #if defined(CONFIG_USER_ONLY)
5479 GEN_EXCP_PRIVOPC(ctx);
5480 #else
5481 if (unlikely(!ctx->supervisor)) {
5482 GEN_EXCP_PRIVOPC(ctx);
5483 return;
5484 }
5485 switch (rB(ctx->opcode)) {
5486 case 0:
5487 gen_op_load_gpr_T0(rA(ctx->opcode));
5488 gen_op_load_gpr_T1(rS(ctx->opcode));
5489 gen_op_4xx_tlbwe_hi();
5490 break;
5491 case 1:
5492 gen_op_load_gpr_T0(rA(ctx->opcode));
5493 gen_op_load_gpr_T1(rS(ctx->opcode));
5494 gen_op_4xx_tlbwe_lo();
5495 break;
5496 default:
5497 GEN_EXCP_INVAL(ctx);
5498 break;
5499 }
5500 #endif
5501 }
5502
5503 /* TLB management - PowerPC 440 implementation */
5504 /* tlbre */
5505 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5506 {
5507 #if defined(CONFIG_USER_ONLY)
5508 GEN_EXCP_PRIVOPC(ctx);
5509 #else
5510 if (unlikely(!ctx->supervisor)) {
5511 GEN_EXCP_PRIVOPC(ctx);
5512 return;
5513 }
5514 switch (rB(ctx->opcode)) {
5515 case 0:
5516 case 1:
5517 case 2:
5518 gen_op_load_gpr_T0(rA(ctx->opcode));
5519 gen_op_440_tlbre(rB(ctx->opcode));
5520 gen_op_store_T0_gpr(rD(ctx->opcode));
5521 break;
5522 default:
5523 GEN_EXCP_INVAL(ctx);
5524 break;
5525 }
5526 #endif
5527 }
5528
5529 /* tlbsx - tlbsx. */
5530 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5531 {
5532 #if defined(CONFIG_USER_ONLY)
5533 GEN_EXCP_PRIVOPC(ctx);
5534 #else
5535 if (unlikely(!ctx->supervisor)) {
5536 GEN_EXCP_PRIVOPC(ctx);
5537 return;
5538 }
5539 gen_addr_reg_index(ctx);
5540 gen_op_440_tlbsx();
5541 if (Rc(ctx->opcode))
5542 gen_op_4xx_tlbsx_check();
5543 gen_op_store_T0_gpr(rD(ctx->opcode));
5544 #endif
5545 }
5546
5547 /* tlbwe */
5548 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5549 {
5550 #if defined(CONFIG_USER_ONLY)
5551 GEN_EXCP_PRIVOPC(ctx);
5552 #else
5553 if (unlikely(!ctx->supervisor)) {
5554 GEN_EXCP_PRIVOPC(ctx);
5555 return;
5556 }
5557 switch (rB(ctx->opcode)) {
5558 case 0:
5559 case 1:
5560 case 2:
5561 gen_op_load_gpr_T0(rA(ctx->opcode));
5562 gen_op_load_gpr_T1(rS(ctx->opcode));
5563 gen_op_440_tlbwe(rB(ctx->opcode));
5564 break;
5565 default:
5566 GEN_EXCP_INVAL(ctx);
5567 break;
5568 }
5569 #endif
5570 }
5571
5572 /* wrtee */
5573 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON)
5574 {
5575 #if defined(CONFIG_USER_ONLY)
5576 GEN_EXCP_PRIVOPC(ctx);
5577 #else
5578 if (unlikely(!ctx->supervisor)) {
5579 GEN_EXCP_PRIVOPC(ctx);
5580 return;
5581 }
5582 gen_op_load_gpr_T0(rD(ctx->opcode));
5583 gen_op_wrte();
5584 /* Stop translation to have a chance to raise an exception
5585 * if we just set msr_ee to 1
5586 */
5587 GEN_STOP(ctx);
5588 #endif
5589 }
5590
5591 /* wrteei */
5592 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON)
5593 {
5594 #if defined(CONFIG_USER_ONLY)
5595 GEN_EXCP_PRIVOPC(ctx);
5596 #else
5597 if (unlikely(!ctx->supervisor)) {
5598 GEN_EXCP_PRIVOPC(ctx);
5599 return;
5600 }
5601 gen_op_set_T0(ctx->opcode & 0x00010000);
5602 gen_op_wrte();
5603 /* Stop translation to have a chance to raise an exception
5604 * if we just set msr_ee to 1
5605 */
5606 GEN_STOP(ctx);
5607 #endif
5608 }
5609
5610 /* PowerPC 440 specific instructions */
5611 /* dlmzb */
5612 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5613 {
5614 gen_op_load_gpr_T0(rS(ctx->opcode));
5615 gen_op_load_gpr_T1(rB(ctx->opcode));
5616 gen_op_440_dlmzb();
5617 gen_op_store_T0_gpr(rA(ctx->opcode));
5618 gen_op_store_xer_bc();
5619 if (Rc(ctx->opcode)) {
5620 gen_op_440_dlmzb_update_Rc();
5621 gen_op_store_T0_crf(0);
5622 }
5623 }
5624
5625 /* mbar replaces eieio on 440 */
5626 GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5627 {
5628 /* interpreted as no-op */
5629 }
5630
5631 /* msync replaces sync on 440 */
5632 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
5633 {
5634 /* interpreted as no-op */
5635 }
5636
5637 /* icbt */
5638 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
5639 {
5640 /* interpreted as no-op */
5641 /* XXX: specification say this is treated as a load by the MMU
5642 * but does not generate any exception
5643 */
5644 }
5645
5646 /*** Altivec vector extension ***/
5647 /* Altivec registers moves */
5648 GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr);
5649 GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr);
5650 GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr);
5651
5652 GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr);
5653 GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr);
5654 #if 0 // unused
5655 GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr);
5656 #endif
5657
5658 #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5659 #if defined(CONFIG_USER_ONLY)
5660 #if defined(TARGET_PPC64)
5661 /* User-mode only - 64 bits mode */
5662 #define OP_VR_LD_TABLE(name) \
5663 static GenOpFunc *gen_op_vr_l##name[] = { \
5664 &gen_op_vr_l##name##_raw, \
5665 &gen_op_vr_l##name##_le_raw, \
5666 &gen_op_vr_l##name##_64_raw, \
5667 &gen_op_vr_l##name##_le_64_raw, \
5668 };
5669 #define OP_VR_ST_TABLE(name) \
5670 static GenOpFunc *gen_op_vr_st##name[] = { \
5671 &gen_op_vr_st##name##_raw, \
5672 &gen_op_vr_st##name##_le_raw, \
5673 &gen_op_vr_st##name##_64_raw, \
5674 &gen_op_vr_st##name##_le_64_raw, \
5675 };
5676 #else /* defined(TARGET_PPC64) */
5677 /* User-mode only - 32 bits mode */
5678 #define OP_VR_LD_TABLE(name) \
5679 static GenOpFunc *gen_op_vr_l##name[] = { \
5680 &gen_op_vr_l##name##_raw, \
5681 &gen_op_vr_l##name##_le_raw, \
5682 };
5683 #define OP_VR_ST_TABLE(name) \
5684 static GenOpFunc *gen_op_vr_st##name[] = { \
5685 &gen_op_vr_st##name##_raw, \
5686 &gen_op_vr_st##name##_le_raw, \
5687 };
5688 #endif /* defined(TARGET_PPC64) */
5689 #else /* defined(CONFIG_USER_ONLY) */
5690 #if defined(TARGET_PPC64H)
5691 /* Full system with hypervisor mode */
5692 #define OP_VR_LD_TABLE(name) \
5693 static GenOpFunc *gen_op_vr_l##name[] = { \
5694 &gen_op_vr_l##name##_user, \
5695 &gen_op_vr_l##name##_le_user, \
5696 &gen_op_vr_l##name##_64_user, \
5697 &gen_op_vr_l##name##_le_64_user, \
5698 &gen_op_vr_l##name##_kernel, \
5699 &gen_op_vr_l##name##_le_kernel, \
5700 &gen_op_vr_l##name##_64_kernel, \
5701 &gen_op_vr_l##name##_le_64_kernel, \
5702 &gen_op_vr_l##name##_hypv, \
5703 &gen_op_vr_l##name##_le_hypv, \
5704 &gen_op_vr_l##name##_64_hypv, \
5705 &gen_op_vr_l##name##_le_64_hypv, \
5706 };
5707 #define OP_VR_ST_TABLE(name) \
5708 static GenOpFunc *gen_op_vr_st##name[] = { \
5709 &gen_op_vr_st##name##_user, \
5710 &gen_op_vr_st##name##_le_user, \
5711 &gen_op_vr_st##name##_64_user, \
5712 &gen_op_vr_st##name##_le_64_user, \
5713 &gen_op_vr_st##name##_kernel, \
5714 &gen_op_vr_st##name##_le_kernel, \
5715 &gen_op_vr_st##name##_64_kernel, \
5716 &gen_op_vr_st##name##_le_64_kernel, \
5717 &gen_op_vr_st##name##_hypv, \
5718 &gen_op_vr_st##name##_le_hypv, \
5719 &gen_op_vr_st##name##_64_hypv, \
5720 &gen_op_vr_st##name##_le_64_hypv, \
5721 };
5722 #elif defined(TARGET_PPC64)
5723 /* Full system - 64 bits mode */
5724 #define OP_VR_LD_TABLE(name) \
5725 static GenOpFunc *gen_op_vr_l##name[] = { \
5726 &gen_op_vr_l##name##_user, \
5727 &gen_op_vr_l##name##_le_user, \
5728 &gen_op_vr_l##name##_64_user, \
5729 &gen_op_vr_l##name##_le_64_user, \
5730 &gen_op_vr_l##name##_kernel, \
5731 &gen_op_vr_l##name##_le_kernel, \
5732 &gen_op_vr_l##name##_64_kernel, \
5733 &gen_op_vr_l##name##_le_64_kernel, \
5734 };
5735 #define OP_VR_ST_TABLE(name) \
5736 static GenOpFunc *gen_op_vr_st##name[] = { \
5737 &gen_op_vr_st##name##_user, \
5738 &gen_op_vr_st##name##_le_user, \
5739 &gen_op_vr_st##name##_64_user, \
5740 &gen_op_vr_st##name##_le_64_user, \
5741 &gen_op_vr_st##name##_kernel, \
5742 &gen_op_vr_st##name##_le_kernel, \
5743 &gen_op_vr_st##name##_64_kernel, \
5744 &gen_op_vr_st##name##_le_64_kernel, \
5745 };
5746 #else /* defined(TARGET_PPC64) */
5747 /* Full system - 32 bits mode */
5748 #define OP_VR_LD_TABLE(name) \
5749 static GenOpFunc *gen_op_vr_l##name[] = { \
5750 &gen_op_vr_l##name##_user, \
5751 &gen_op_vr_l##name##_le_user, \
5752 &gen_op_vr_l##name##_kernel, \
5753 &gen_op_vr_l##name##_le_kernel, \
5754 };
5755 #define OP_VR_ST_TABLE(name) \
5756 static GenOpFunc *gen_op_vr_st##name[] = { \
5757 &gen_op_vr_st##name##_user, \
5758 &gen_op_vr_st##name##_le_user, \
5759 &gen_op_vr_st##name##_kernel, \
5760 &gen_op_vr_st##name##_le_kernel, \
5761 };
5762 #endif /* defined(TARGET_PPC64) */
5763 #endif /* defined(CONFIG_USER_ONLY) */
5764
5765 #define GEN_VR_LDX(name, opc2, opc3) \
5766 GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5767 { \
5768 if (unlikely(!ctx->altivec_enabled)) { \
5769 GEN_EXCP_NO_VR(ctx); \
5770 return; \
5771 } \
5772 gen_addr_reg_index(ctx); \
5773 op_vr_ldst(vr_l##name); \
5774 gen_op_store_A0_avr(rD(ctx->opcode)); \
5775 }
5776
5777 #define GEN_VR_STX(name, opc2, opc3) \
5778 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5779 { \
5780 if (unlikely(!ctx->altivec_enabled)) { \
5781 GEN_EXCP_NO_VR(ctx); \
5782 return; \
5783 } \
5784 gen_addr_reg_index(ctx); \
5785 gen_op_load_avr_A0(rS(ctx->opcode)); \
5786 op_vr_ldst(vr_st##name); \
5787 }
5788
5789 OP_VR_LD_TABLE(vx);
5790 GEN_VR_LDX(vx, 0x07, 0x03);
5791 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5792 #define gen_op_vr_lvxl gen_op_vr_lvx
5793 GEN_VR_LDX(vxl, 0x07, 0x0B);
5794
5795 OP_VR_ST_TABLE(vx);
5796 GEN_VR_STX(vx, 0x07, 0x07);
5797 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5798 #define gen_op_vr_stvxl gen_op_vr_stvx
5799 GEN_VR_STX(vxl, 0x07, 0x0F);
5800
5801 #if defined(TARGET_PPCEMB)
5802 /*** SPE extension ***/
5803
5804 /* Register moves */
5805 GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5806 GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
5807 #if 0 // unused
5808 GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
5809 #endif
5810
5811 GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
5812 GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5813 #if 0 // unused
5814 GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5815 #endif
5816
5817 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5818 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5819 { \
5820 if (Rc(ctx->opcode)) \
5821 gen_##name1(ctx); \
5822 else \
5823 gen_##name0(ctx); \
5824 }
5825
5826 /* Handler for undefined SPE opcodes */
5827 static always_inline void gen_speundef (DisasContext *ctx)
5828 {
5829 GEN_EXCP_INVAL(ctx);
5830 }
5831
5832 /* SPE load and stores */
5833 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
5834 {
5835 target_long simm = rB(ctx->opcode);
5836
5837 if (rA(ctx->opcode) == 0) {
5838 gen_set_T0(simm << sh);
5839 } else {
5840 gen_op_load_gpr_T0(rA(ctx->opcode));
5841 if (likely(simm != 0))
5842 gen_op_addi(simm << sh);
5843 }
5844 }
5845
5846 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5847 #if defined(CONFIG_USER_ONLY)
5848 #if defined(TARGET_PPC64)
5849 /* User-mode only - 64 bits mode */
5850 #define OP_SPE_LD_TABLE(name) \
5851 static GenOpFunc *gen_op_spe_l##name[] = { \
5852 &gen_op_spe_l##name##_raw, \
5853 &gen_op_spe_l##name##_le_raw, \
5854 &gen_op_spe_l##name##_64_raw, \
5855 &gen_op_spe_l##name##_le_64_raw, \
5856 };
5857 #define OP_SPE_ST_TABLE(name) \
5858 static GenOpFunc *gen_op_spe_st##name[] = { \
5859 &gen_op_spe_st##name##_raw, \
5860 &gen_op_spe_st##name##_le_raw, \
5861 &gen_op_spe_st##name##_64_raw, \
5862 &gen_op_spe_st##name##_le_64_raw, \
5863 };
5864 #else /* defined(TARGET_PPC64) */
5865 /* User-mode only - 32 bits mode */
5866 #define OP_SPE_LD_TABLE(name) \
5867 static GenOpFunc *gen_op_spe_l##name[] = { \
5868 &gen_op_spe_l##name##_raw, \
5869 &gen_op_spe_l##name##_le_raw, \
5870 };
5871 #define OP_SPE_ST_TABLE(name) \
5872 static GenOpFunc *gen_op_spe_st##name[] = { \
5873 &gen_op_spe_st##name##_raw, \
5874 &gen_op_spe_st##name##_le_raw, \
5875 };
5876 #endif /* defined(TARGET_PPC64) */
5877 #else /* defined(CONFIG_USER_ONLY) */
5878 #if defined(TARGET_PPC64H)
5879 /* Full system with hypervisor mode */
5880 #define OP_SPE_LD_TABLE(name) \
5881 static GenOpFunc *gen_op_spe_l##name[] = { \
5882 &gen_op_spe_l##name##_user, \
5883 &gen_op_spe_l##name##_le_user, \
5884 &gen_op_spe_l##name##_64_user, \
5885 &gen_op_spe_l##name##_le_64_user, \
5886 &gen_op_spe_l##name##_kernel, \
5887 &gen_op_spe_l##name##_le_kernel, \
5888 &gen_op_spe_l##name##_64_kernel, \
5889 &gen_op_spe_l##name##_le_64_kernel, \
5890 &gen_op_spe_l##name##_hypv, \
5891 &gen_op_spe_l##name##_le_hypv, \
5892 &gen_op_spe_l##name##_64_hypv, \
5893 &gen_op_spe_l##name##_le_64_hypv, \
5894 };
5895 #define OP_SPE_ST_TABLE(name) \
5896 static GenOpFunc *gen_op_spe_st##name[] = { \
5897 &gen_op_spe_st##name##_user, \
5898 &gen_op_spe_st##name##_le_user, \
5899 &gen_op_spe_st##name##_64_user, \
5900 &gen_op_spe_st##name##_le_64_user, \
5901 &gen_op_spe_st##name##_kernel, \
5902 &gen_op_spe_st##name##_le_kernel, \
5903 &gen_op_spe_st##name##_64_kernel, \
5904 &gen_op_spe_st##name##_le_64_kernel, \
5905 &gen_op_spe_st##name##_hypv, \
5906 &gen_op_spe_st##name##_le_hypv, \
5907 &gen_op_spe_st##name##_64_hypv, \
5908 &gen_op_spe_st##name##_le_64_hypv, \
5909 };
5910 #elif defined(TARGET_PPC64)
5911 /* Full system - 64 bits mode */
5912 #define OP_SPE_LD_TABLE(name) \
5913 static GenOpFunc *gen_op_spe_l##name[] = { \
5914 &gen_op_spe_l##name##_user, \
5915 &gen_op_spe_l##name##_le_user, \
5916 &gen_op_spe_l##name##_64_user, \
5917 &gen_op_spe_l##name##_le_64_user, \
5918 &gen_op_spe_l##name##_kernel, \
5919 &gen_op_spe_l##name##_le_kernel, \
5920 &gen_op_spe_l##name##_64_kernel, \
5921 &gen_op_spe_l##name##_le_64_kernel, \
5922 };
5923 #define OP_SPE_ST_TABLE(name) \
5924 static GenOpFunc *gen_op_spe_st##name[] = { \
5925 &gen_op_spe_st##name##_user, \
5926 &gen_op_spe_st##name##_le_user, \
5927 &gen_op_spe_st##name##_64_user, \
5928 &gen_op_spe_st##name##_le_64_user, \
5929 &gen_op_spe_st##name##_kernel, \
5930 &gen_op_spe_st##name##_le_kernel, \
5931 &gen_op_spe_st##name##_64_kernel, \
5932 &gen_op_spe_st##name##_le_64_kernel, \
5933 };
5934 #else /* defined(TARGET_PPC64) */
5935 /* Full system - 32 bits mode */
5936 #define OP_SPE_LD_TABLE(name) \
5937 static GenOpFunc *gen_op_spe_l##name[] = { \
5938 &gen_op_spe_l##name##_user, \
5939 &gen_op_spe_l##name##_le_user, \
5940 &gen_op_spe_l##name##_kernel, \
5941 &gen_op_spe_l##name##_le_kernel, \
5942 };
5943 #define OP_SPE_ST_TABLE(name) \
5944 static GenOpFunc *gen_op_spe_st##name[] = { \
5945 &gen_op_spe_st##name##_user, \
5946 &gen_op_spe_st##name##_le_user, \
5947 &gen_op_spe_st##name##_kernel, \
5948 &gen_op_spe_st##name##_le_kernel, \
5949 };
5950 #endif /* defined(TARGET_PPC64) */
5951 #endif /* defined(CONFIG_USER_ONLY) */
5952
5953 #define GEN_SPE_LD(name, sh) \
5954 static always_inline void gen_evl##name (DisasContext *ctx) \
5955 { \
5956 if (unlikely(!ctx->spe_enabled)) { \
5957 GEN_EXCP_NO_AP(ctx); \
5958 return; \
5959 } \
5960 gen_addr_spe_imm_index(ctx, sh); \
5961 op_spe_ldst(spe_l##name); \
5962 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5963 }
5964
5965 #define GEN_SPE_LDX(name) \
5966 static always_inline void gen_evl##name##x (DisasContext *ctx) \
5967 { \
5968 if (unlikely(!ctx->spe_enabled)) { \
5969 GEN_EXCP_NO_AP(ctx); \
5970 return; \
5971 } \
5972 gen_addr_reg_index(ctx); \
5973 op_spe_ldst(spe_l##name); \
5974 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5975 }
5976
5977 #define GEN_SPEOP_LD(name, sh) \
5978 OP_SPE_LD_TABLE(name); \
5979 GEN_SPE_LD(name, sh); \
5980 GEN_SPE_LDX(name)
5981
5982 #define GEN_SPE_ST(name, sh) \
5983 static always_inline void gen_evst##name (DisasContext *ctx) \
5984 { \
5985 if (unlikely(!ctx->spe_enabled)) { \
5986 GEN_EXCP_NO_AP(ctx); \
5987 return; \
5988 } \
5989 gen_addr_spe_imm_index(ctx, sh); \
5990 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5991 op_spe_ldst(spe_st##name); \
5992 }
5993
5994 #define GEN_SPE_STX(name) \
5995 static always_inline void gen_evst##name##x (DisasContext *ctx) \
5996 { \
5997 if (unlikely(!ctx->spe_enabled)) { \
5998 GEN_EXCP_NO_AP(ctx); \
5999 return; \
6000 } \
6001 gen_addr_reg_index(ctx); \
6002 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
6003 op_spe_ldst(spe_st##name); \
6004 }
6005
6006 #define GEN_SPEOP_ST(name, sh) \
6007 OP_SPE_ST_TABLE(name); \
6008 GEN_SPE_ST(name, sh); \
6009 GEN_SPE_STX(name)
6010
6011 #define GEN_SPEOP_LDST(name, sh) \
6012 GEN_SPEOP_LD(name, sh); \
6013 GEN_SPEOP_ST(name, sh)
6014
6015 /* SPE arithmetic and logic */
6016 #define GEN_SPEOP_ARITH2(name) \
6017 static always_inline void gen_##name (DisasContext *ctx) \
6018 { \
6019 if (unlikely(!ctx->spe_enabled)) { \
6020 GEN_EXCP_NO_AP(ctx); \
6021 return; \
6022 } \
6023 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6024 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
6025 gen_op_##name(); \
6026 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6027 }
6028
6029 #define GEN_SPEOP_ARITH1(name) \
6030 static always_inline void gen_##name (DisasContext *ctx) \
6031 { \
6032 if (unlikely(!ctx->spe_enabled)) { \
6033 GEN_EXCP_NO_AP(ctx); \
6034 return; \
6035 } \
6036 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6037 gen_op_##name(); \
6038 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6039 }
6040
6041 #define GEN_SPEOP_COMP(name) \
6042 static always_inline void gen_##name (DisasContext *ctx) \
6043 { \
6044 if (unlikely(!ctx->spe_enabled)) { \
6045 GEN_EXCP_NO_AP(ctx); \
6046 return; \
6047 } \
6048 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6049 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
6050 gen_op_##name(); \
6051 gen_op_store_T0_crf(crfD(ctx->opcode)); \
6052 }
6053
6054 /* Logical */
6055 GEN_SPEOP_ARITH2(evand);
6056 GEN_SPEOP_ARITH2(evandc);
6057 GEN_SPEOP_ARITH2(evxor);
6058 GEN_SPEOP_ARITH2(evor);
6059 GEN_SPEOP_ARITH2(evnor);
6060 GEN_SPEOP_ARITH2(eveqv);
6061 GEN_SPEOP_ARITH2(evorc);
6062 GEN_SPEOP_ARITH2(evnand);
6063 GEN_SPEOP_ARITH2(evsrwu);
6064 GEN_SPEOP_ARITH2(evsrws);
6065 GEN_SPEOP_ARITH2(evslw);
6066 GEN_SPEOP_ARITH2(evrlw);
6067 GEN_SPEOP_ARITH2(evmergehi);
6068 GEN_SPEOP_ARITH2(evmergelo);
6069 GEN_SPEOP_ARITH2(evmergehilo);
6070 GEN_SPEOP_ARITH2(evmergelohi);
6071
6072 /* Arithmetic */
6073 GEN_SPEOP_ARITH2(evaddw);
6074 GEN_SPEOP_ARITH2(evsubfw);
6075 GEN_SPEOP_ARITH1(evabs);
6076 GEN_SPEOP_ARITH1(evneg);
6077 GEN_SPEOP_ARITH1(evextsb);
6078 GEN_SPEOP_ARITH1(evextsh);
6079 GEN_SPEOP_ARITH1(evrndw);
6080 GEN_SPEOP_ARITH1(evcntlzw);
6081 GEN_SPEOP_ARITH1(evcntlsw);
6082 static always_inline void gen_brinc (DisasContext *ctx)
6083 {
6084 /* Note: brinc is usable even if SPE is disabled */
6085 gen_op_load_gpr64_T0(rA(ctx->opcode));
6086 gen_op_load_gpr64_T1(rB(ctx->opcode));
6087 gen_op_brinc();
6088 gen_op_store_T0_gpr64(rD(ctx->opcode));
6089 }
6090
6091 #define GEN_SPEOP_ARITH_IMM2(name) \
6092 static always_inline void gen_##name##i (DisasContext *ctx) \
6093 { \
6094 if (unlikely(!ctx->spe_enabled)) { \
6095 GEN_EXCP_NO_AP(ctx); \
6096 return; \
6097 } \
6098 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6099 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
6100 gen_op_##name(); \
6101 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6102 }
6103
6104 #define GEN_SPEOP_LOGIC_IMM2(name) \
6105 static always_inline void gen_##name##i (DisasContext *ctx) \
6106 { \
6107 if (unlikely(!ctx->spe_enabled)) { \
6108 GEN_EXCP_NO_AP(ctx); \
6109 return; \
6110 } \
6111 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6112 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
6113 gen_op_##name(); \
6114 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6115 }
6116
6117 GEN_SPEOP_ARITH_IMM2(evaddw);
6118 #define gen_evaddiw gen_evaddwi
6119 GEN_SPEOP_ARITH_IMM2(evsubfw);
6120 #define gen_evsubifw gen_evsubfwi
6121 GEN_SPEOP_LOGIC_IMM2(evslw);
6122 GEN_SPEOP_LOGIC_IMM2(evsrwu);
6123 #define gen_evsrwis gen_evsrwsi
6124 GEN_SPEOP_LOGIC_IMM2(evsrws);
6125 #define gen_evsrwiu gen_evsrwui
6126 GEN_SPEOP_LOGIC_IMM2(evrlw);
6127
6128 static always_inline void gen_evsplati (DisasContext *ctx)
6129 {
6130 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
6131
6132 gen_op_splatwi_T0_64(imm);
6133 gen_op_store_T0_gpr64(rD(ctx->opcode));
6134 }
6135
6136 static always_inline void gen_evsplatfi (DisasContext *ctx)
6137 {
6138 uint32_t imm = rA(ctx->opcode) << 27;
6139
6140 gen_op_splatwi_T0_64(imm);
6141 gen_op_store_T0_gpr64(rD(ctx->opcode));
6142 }
6143
6144 /* Comparison */
6145 GEN_SPEOP_COMP(evcmpgtu);
6146 GEN_SPEOP_COMP(evcmpgts);
6147 GEN_SPEOP_COMP(evcmpltu);
6148 GEN_SPEOP_COMP(evcmplts);
6149 GEN_SPEOP_COMP(evcmpeq);
6150
6151 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6152 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6153 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6154 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6155 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6156 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6157 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6158 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6159 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6160 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6161 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6162 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6163 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6164 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6165 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6166 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6167 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6168 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6169 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6170 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6171 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6172 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6173 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6174 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6175 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6176
6177 static always_inline void gen_evsel (DisasContext *ctx)
6178 {
6179 if (unlikely(!ctx->spe_enabled)) {
6180 GEN_EXCP_NO_AP(ctx);
6181 return;
6182 }
6183 gen_op_load_crf_T0(ctx->opcode & 0x7);
6184 gen_op_load_gpr64_T0(rA(ctx->opcode));
6185 gen_op_load_gpr64_T1(rB(ctx->opcode));
6186 gen_op_evsel();
6187 gen_op_store_T0_gpr64(rD(ctx->opcode));
6188 }
6189
6190 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6191 {
6192 gen_evsel(ctx);
6193 }
6194 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6195 {
6196 gen_evsel(ctx);
6197 }
6198 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6199 {
6200 gen_evsel(ctx);
6201 }
6202 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6203 {
6204 gen_evsel(ctx);
6205 }
6206
6207 /* Load and stores */
6208 #if defined(TARGET_PPC64)
6209 /* In that case, we already have 64 bits load & stores
6210 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
6211 */
6212 #if defined(CONFIG_USER_ONLY)
6213 #define gen_op_spe_ldd_raw gen_op_ld_raw
6214 #define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
6215 #define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
6216 #define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
6217 #define gen_op_spe_stdd_raw gen_op_ld_raw
6218 #define gen_op_spe_stdd_64_raw gen_op_std_64_raw
6219 #define gen_op_spe_stdd_le_raw gen_op_std_le_raw
6220 #define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
6221 #else /* defined(CONFIG_USER_ONLY) */
6222 #define gen_op_spe_ldd_kernel gen_op_ld_kernel
6223 #define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
6224 #define gen_op_spe_ldd_le_kernel gen_op_ld_kernel
6225 #define gen_op_spe_ldd_le_64_kernel gen_op_ld_64_kernel
6226 #define gen_op_spe_ldd_user gen_op_ld_user
6227 #define gen_op_spe_ldd_64_user gen_op_ld_64_user
6228 #define gen_op_spe_ldd_le_user gen_op_ld_le_user
6229 #define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
6230 #define gen_op_spe_stdd_kernel gen_op_std_kernel
6231 #define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
6232 #define gen_op_spe_stdd_le_kernel gen_op_std_kernel
6233 #define gen_op_spe_stdd_le_64_kernel gen_op_std_64_kernel
6234 #define gen_op_spe_stdd_user gen_op_std_user
6235 #define gen_op_spe_stdd_64_user gen_op_std_64_user
6236 #define gen_op_spe_stdd_le_user gen_op_std_le_user
6237 #define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
6238 #endif /* defined(CONFIG_USER_ONLY) */
6239 #endif /* defined(TARGET_PPC64) */
6240 GEN_SPEOP_LDST(dd, 3);
6241 GEN_SPEOP_LDST(dw, 3);
6242 GEN_SPEOP_LDST(dh, 3);
6243 GEN_SPEOP_LDST(whe, 2);
6244 GEN_SPEOP_LD(whou, 2);
6245 GEN_SPEOP_LD(whos, 2);
6246 GEN_SPEOP_ST(who, 2);
6247
6248 #if defined(TARGET_PPC64)
6249 /* In that case, spe_stwwo is equivalent to stw */
6250 #if defined(CONFIG_USER_ONLY)
6251 #define gen_op_spe_stwwo_raw gen_op_stw_raw
6252 #define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
6253 #define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
6254 #define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
6255 #else
6256 #define gen_op_spe_stwwo_user gen_op_stw_user
6257 #define gen_op_spe_stwwo_le_user gen_op_stw_le_user
6258 #define gen_op_spe_stwwo_64_user gen_op_stw_64_user
6259 #define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
6260 #define gen_op_spe_stwwo_kernel gen_op_stw_kernel
6261 #define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
6262 #define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
6263 #define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
6264 #endif
6265 #endif
6266 #define _GEN_OP_SPE_STWWE(suffix) \
6267 static always_inline void gen_op_spe_stwwe_##suffix (void) \
6268 { \
6269 gen_op_srli32_T1_64(); \
6270 gen_op_spe_stwwo_##suffix(); \
6271 }
6272 #define _GEN_OP_SPE_STWWE_LE(suffix) \
6273 static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
6274 { \
6275 gen_op_srli32_T1_64(); \
6276 gen_op_spe_stwwo_le_##suffix(); \
6277 }
6278 #if defined(TARGET_PPC64)
6279 #define GEN_OP_SPE_STWWE(suffix) \
6280 _GEN_OP_SPE_STWWE(suffix); \
6281 _GEN_OP_SPE_STWWE_LE(suffix); \
6282 static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
6283 { \
6284 gen_op_srli32_T1_64(); \
6285 gen_op_spe_stwwo_64_##suffix(); \
6286 } \
6287 static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
6288 { \
6289 gen_op_srli32_T1_64(); \
6290 gen_op_spe_stwwo_le_64_##suffix(); \
6291 }
6292 #else
6293 #define GEN_OP_SPE_STWWE(suffix) \
6294 _GEN_OP_SPE_STWWE(suffix); \
6295 _GEN_OP_SPE_STWWE_LE(suffix)
6296 #endif
6297 #if defined(CONFIG_USER_ONLY)
6298 GEN_OP_SPE_STWWE(raw);
6299 #else /* defined(CONFIG_USER_ONLY) */
6300 GEN_OP_SPE_STWWE(kernel);
6301 GEN_OP_SPE_STWWE(user);
6302 #endif /* defined(CONFIG_USER_ONLY) */
6303 GEN_SPEOP_ST(wwe, 2);
6304 GEN_SPEOP_ST(wwo, 2);
6305
6306 #define GEN_SPE_LDSPLAT(name, op, suffix) \
6307 static always_inline void gen_op_spe_l##name##_##suffix (void) \
6308 { \
6309 gen_op_##op##_##suffix(); \
6310 gen_op_splatw_T1_64(); \
6311 }
6312
6313 #define GEN_OP_SPE_LHE(suffix) \
6314 static always_inline void gen_op_spe_lhe_##suffix (void) \
6315 { \
6316 gen_op_spe_lh_##suffix(); \
6317 gen_op_sli16_T1_64(); \
6318 }
6319
6320 #define GEN_OP_SPE_LHX(suffix) \
6321 static always_inline void gen_op_spe_lhx_##suffix (void) \
6322 { \
6323 gen_op_spe_lh_##suffix(); \
6324 gen_op_extsh_T1_64(); \
6325 }
6326
6327 #if defined(CONFIG_USER_ONLY)
6328 GEN_OP_SPE_LHE(raw);
6329 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6330 GEN_OP_SPE_LHE(le_raw);
6331 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6332 GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6333 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6334 GEN_OP_SPE_LHX(raw);
6335 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6336 GEN_OP_SPE_LHX(le_raw);
6337 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6338 #if defined(TARGET_PPC64)
6339 GEN_OP_SPE_LHE(64_raw);
6340 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6341 GEN_OP_SPE_LHE(le_64_raw);
6342 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6343 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6344 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6345 GEN_OP_SPE_LHX(64_raw);
6346 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6347 GEN_OP_SPE_LHX(le_64_raw);
6348 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6349 #endif
6350 #else
6351 GEN_OP_SPE_LHE(kernel);
6352 GEN_OP_SPE_LHE(user);
6353 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6354 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
6355 GEN_OP_SPE_LHE(le_kernel);
6356 GEN_OP_SPE_LHE(le_user);
6357 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6358 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
6359 GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6360 GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
6361 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6362 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
6363 GEN_OP_SPE_LHX(kernel);
6364 GEN_OP_SPE_LHX(user);
6365 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6366 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
6367 GEN_OP_SPE_LHX(le_kernel);
6368 GEN_OP_SPE_LHX(le_user);
6369 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6370 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
6371 #if defined(TARGET_PPC64)
6372 GEN_OP_SPE_LHE(64_kernel);
6373 GEN_OP_SPE_LHE(64_user);
6374 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6375 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
6376 GEN_OP_SPE_LHE(le_64_kernel);
6377 GEN_OP_SPE_LHE(le_64_user);
6378 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6379 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
6380 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6381 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
6382 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6383 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
6384 GEN_OP_SPE_LHX(64_kernel);
6385 GEN_OP_SPE_LHX(64_user);
6386 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6387 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
6388 GEN_OP_SPE_LHX(le_64_kernel);
6389 GEN_OP_SPE_LHX(le_64_user);
6390 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6391 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
6392 #endif
6393 #endif
6394 GEN_SPEOP_LD(hhesplat, 1);
6395 GEN_SPEOP_LD(hhousplat, 1);
6396 GEN_SPEOP_LD(hhossplat, 1);
6397 GEN_SPEOP_LD(wwsplat, 2);
6398 GEN_SPEOP_LD(whsplat, 2);
6399
6400 GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6401 GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6402 GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6403 GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6404 GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6405 GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6406 GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6407 GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6408 GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6409 GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6410 GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6411 GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6412 GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6413 GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6414 GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6415 GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6416 GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6417 GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6418
6419 /* Multiply and add - TODO */
6420 #if 0
6421 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6422 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6423 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6424 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6425 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6426 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6427 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6428 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6429 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6430 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6431 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6432 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6433
6434 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6435 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6436 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6437 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6438 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6439 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6440 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6441 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6442 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6443 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6444 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6445 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6446 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6447 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6448
6449 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6450 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6451 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6452 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6453 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6454 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6455
6456 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6457 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6458 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6459 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6460 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6461 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6462 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6463 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6464 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6465 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6466 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6467 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6468
6469 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6470 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6471 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6472 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6473 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6474
6475 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6476 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6477 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6478 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6479 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6480 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6481 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6482 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6483 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6484 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6485 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6486 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6487
6488 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6489 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6490 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6491 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6492 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6493 #endif
6494
6495 /*** SPE floating-point extension ***/
6496 #define GEN_SPEFPUOP_CONV(name) \
6497 static always_inline void gen_##name (DisasContext *ctx) \
6498 { \
6499 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6500 gen_op_##name(); \
6501 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6502 }
6503
6504 /* Single precision floating-point vectors operations */
6505 /* Arithmetic */
6506 GEN_SPEOP_ARITH2(evfsadd);
6507 GEN_SPEOP_ARITH2(evfssub);
6508 GEN_SPEOP_ARITH2(evfsmul);
6509 GEN_SPEOP_ARITH2(evfsdiv);
6510 GEN_SPEOP_ARITH1(evfsabs);
6511 GEN_SPEOP_ARITH1(evfsnabs);
6512 GEN_SPEOP_ARITH1(evfsneg);
6513 /* Conversion */
6514 GEN_SPEFPUOP_CONV(evfscfui);
6515 GEN_SPEFPUOP_CONV(evfscfsi);
6516 GEN_SPEFPUOP_CONV(evfscfuf);
6517 GEN_SPEFPUOP_CONV(evfscfsf);
6518 GEN_SPEFPUOP_CONV(evfsctui);
6519 GEN_SPEFPUOP_CONV(evfsctsi);
6520 GEN_SPEFPUOP_CONV(evfsctuf);
6521 GEN_SPEFPUOP_CONV(evfsctsf);
6522 GEN_SPEFPUOP_CONV(evfsctuiz);
6523 GEN_SPEFPUOP_CONV(evfsctsiz);
6524 /* Comparison */
6525 GEN_SPEOP_COMP(evfscmpgt);
6526 GEN_SPEOP_COMP(evfscmplt);
6527 GEN_SPEOP_COMP(evfscmpeq);
6528 GEN_SPEOP_COMP(evfststgt);
6529 GEN_SPEOP_COMP(evfststlt);
6530 GEN_SPEOP_COMP(evfststeq);
6531
6532 /* Opcodes definitions */
6533 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6534 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6535 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6536 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6537 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6538 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6539 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6540 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6541 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6542 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6543 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6544 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6545 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6546 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6547
6548 /* Single precision floating-point operations */
6549 /* Arithmetic */
6550 GEN_SPEOP_ARITH2(efsadd);
6551 GEN_SPEOP_ARITH2(efssub);
6552 GEN_SPEOP_ARITH2(efsmul);
6553 GEN_SPEOP_ARITH2(efsdiv);
6554 GEN_SPEOP_ARITH1(efsabs);
6555 GEN_SPEOP_ARITH1(efsnabs);
6556 GEN_SPEOP_ARITH1(efsneg);
6557 /* Conversion */
6558 GEN_SPEFPUOP_CONV(efscfui);
6559 GEN_SPEFPUOP_CONV(efscfsi);
6560 GEN_SPEFPUOP_CONV(efscfuf);
6561 GEN_SPEFPUOP_CONV(efscfsf);
6562 GEN_SPEFPUOP_CONV(efsctui);
6563 GEN_SPEFPUOP_CONV(efsctsi);
6564 GEN_SPEFPUOP_CONV(efsctuf);
6565 GEN_SPEFPUOP_CONV(efsctsf);
6566 GEN_SPEFPUOP_CONV(efsctuiz);
6567 GEN_SPEFPUOP_CONV(efsctsiz);
6568 GEN_SPEFPUOP_CONV(efscfd);
6569 /* Comparison */
6570 GEN_SPEOP_COMP(efscmpgt);
6571 GEN_SPEOP_COMP(efscmplt);
6572 GEN_SPEOP_COMP(efscmpeq);
6573 GEN_SPEOP_COMP(efststgt);
6574 GEN_SPEOP_COMP(efststlt);
6575 GEN_SPEOP_COMP(efststeq);
6576
6577 /* Opcodes definitions */
6578 GEN_SPE(efsadd, efssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6579 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6580 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6581 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6582 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6583 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6584 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6585 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6586 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6587 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
6588 GEN_SPE(efsctuiz, efsctsiz, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6589 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6590 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6591
6592 /* Double precision floating-point operations */
6593 /* Arithmetic */
6594 GEN_SPEOP_ARITH2(efdadd);
6595 GEN_SPEOP_ARITH2(efdsub);
6596 GEN_SPEOP_ARITH2(efdmul);
6597 GEN_SPEOP_ARITH2(efddiv);
6598 GEN_SPEOP_ARITH1(efdabs);
6599 GEN_SPEOP_ARITH1(efdnabs);
6600 GEN_SPEOP_ARITH1(efdneg);
6601 /* Conversion */
6602
6603 GEN_SPEFPUOP_CONV(efdcfui);
6604 GEN_SPEFPUOP_CONV(efdcfsi);
6605 GEN_SPEFPUOP_CONV(efdcfuf);
6606 GEN_SPEFPUOP_CONV(efdcfsf);
6607 GEN_SPEFPUOP_CONV(efdctui);
6608 GEN_SPEFPUOP_CONV(efdctsi);
6609 GEN_SPEFPUOP_CONV(efdctuf);
6610 GEN_SPEFPUOP_CONV(efdctsf);
6611 GEN_SPEFPUOP_CONV(efdctuiz);
6612 GEN_SPEFPUOP_CONV(efdctsiz);
6613 GEN_SPEFPUOP_CONV(efdcfs);
6614 GEN_SPEFPUOP_CONV(efdcfuid);
6615 GEN_SPEFPUOP_CONV(efdcfsid);
6616 GEN_SPEFPUOP_CONV(efdctuidz);
6617 GEN_SPEFPUOP_CONV(efdctsidz);
6618 /* Comparison */
6619 GEN_SPEOP_COMP(efdcmpgt);
6620 GEN_SPEOP_COMP(efdcmplt);
6621 GEN_SPEOP_COMP(efdcmpeq);
6622 GEN_SPEOP_COMP(efdtstgt);
6623 GEN_SPEOP_COMP(efdtstlt);
6624 GEN_SPEOP_COMP(efdtsteq);
6625
6626 /* Opcodes definitions */
6627 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6628 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6629 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6630 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6631 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6632 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6633 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6634 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6635 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6636 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6637 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6638 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6639 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6640 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6641 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6642 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
6643 #endif
6644
6645 /* End opcode list */
6646 GEN_OPCODE_MARK(end);
6647
6648 #include "translate_init.c"
6649 #include "helper_regs.h"
6650
6651 /*****************************************************************************/
6652 /* Misc PowerPC helpers */
6653 void cpu_dump_state (CPUState *env, FILE *f,
6654 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6655 int flags)
6656 {
6657 #if defined(TARGET_PPC64) || 1
6658 #define FILL ""
6659 #define RGPL 4
6660 #define RFPL 4
6661 #else
6662 #define FILL " "
6663 #define RGPL 8
6664 #define RFPL 4
6665 #endif
6666
6667 int i;
6668
6669 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " idx %d\n",
6670 env->nip, env->lr, env->ctr, env->mmu_idx);
6671 cpu_fprintf(f, "MSR " REGX FILL " XER %08x "
6672 #if !defined(NO_TIMER_DUMP)
6673 "TB %08x %08x "
6674 #if !defined(CONFIG_USER_ONLY)
6675 "DECR %08x"
6676 #endif
6677 #endif
6678 "\n",
6679 env->msr, hreg_load_xer(env)
6680 #if !defined(NO_TIMER_DUMP)
6681 , cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6682 #if !defined(CONFIG_USER_ONLY)
6683 , cpu_ppc_load_decr(env)
6684 #endif
6685 #endif
6686 );
6687 for (i = 0; i < 32; i++) {
6688 if ((i & (RGPL - 1)) == 0)
6689 cpu_fprintf(f, "GPR%02d", i);
6690 cpu_fprintf(f, " " REGX, (target_ulong)env->gpr[i]);
6691 if ((i & (RGPL - 1)) == (RGPL - 1))
6692 cpu_fprintf(f, "\n");
6693 }
6694 cpu_fprintf(f, "CR ");
6695 for (i = 0; i < 8; i++)
6696 cpu_fprintf(f, "%01x", env->crf[i]);
6697 cpu_fprintf(f, " [");
6698 for (i = 0; i < 8; i++) {
6699 char a = '-';
6700 if (env->crf[i] & 0x08)
6701 a = 'L';
6702 else if (env->crf[i] & 0x04)
6703 a = 'G';
6704 else if (env->crf[i] & 0x02)
6705 a = 'E';
6706 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6707 }
6708 cpu_fprintf(f, " ] " FILL "RES " REGX "\n", env->reserve);
6709 for (i = 0; i < 32; i++) {
6710 if ((i & (RFPL - 1)) == 0)
6711 cpu_fprintf(f, "FPR%02d", i);
6712 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6713 if ((i & (RFPL - 1)) == (RFPL - 1))
6714 cpu_fprintf(f, "\n");
6715 }
6716 #if !defined(CONFIG_USER_ONLY)
6717 cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " " FILL FILL FILL
6718 "SDR1 " REGX "\n",
6719 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
6720 #endif
6721
6722 #undef RGPL
6723 #undef RFPL
6724 #undef FILL
6725 }
6726
6727 void cpu_dump_statistics (CPUState *env, FILE*f,
6728 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6729 int flags)
6730 {
6731 #if defined(DO_PPC_STATISTICS)
6732 opc_handler_t **t1, **t2, **t3, *handler;
6733 int op1, op2, op3;
6734
6735 t1 = env->opcodes;
6736 for (op1 = 0; op1 < 64; op1++) {
6737 handler = t1[op1];
6738 if (is_indirect_opcode(handler)) {
6739 t2 = ind_table(handler);
6740 for (op2 = 0; op2 < 32; op2++) {
6741 handler = t2[op2];
6742 if (is_indirect_opcode(handler)) {
6743 t3 = ind_table(handler);
6744 for (op3 = 0; op3 < 32; op3++) {
6745 handler = t3[op3];
6746 if (handler->count == 0)
6747 continue;
6748 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6749 "%016llx %lld\n",
6750 op1, op2, op3, op1, (op3 << 5) | op2,
6751 handler->oname,
6752 handler->count, handler->count);
6753 }
6754 } else {
6755 if (handler->count == 0)
6756 continue;
6757 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6758 "%016llx %lld\n",
6759 op1, op2, op1, op2, handler->oname,
6760 handler->count, handler->count);
6761 }
6762 }
6763 } else {
6764 if (handler->count == 0)
6765 continue;
6766 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6767 op1, op1, handler->oname,
6768 handler->count, handler->count);
6769 }
6770 }
6771 #endif
6772 }
6773
6774 /*****************************************************************************/
6775 static always_inline int gen_intermediate_code_internal (CPUState *env,
6776 TranslationBlock *tb,
6777 int search_pc)
6778 {
6779 DisasContext ctx, *ctxp = &ctx;
6780 opc_handler_t **table, *handler;
6781 target_ulong pc_start;
6782 uint16_t *gen_opc_end;
6783 int supervisor;
6784 int single_step, branch_step;
6785 int j, lj = -1;
6786
6787 pc_start = tb->pc;
6788 gen_opc_ptr = gen_opc_buf;
6789 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6790 gen_opparam_ptr = gen_opparam_buf;
6791 #if defined(OPTIMIZE_FPRF_UPDATE)
6792 gen_fprf_ptr = gen_fprf_buf;
6793 #endif
6794 nb_gen_labels = 0;
6795 ctx.nip = pc_start;
6796 ctx.tb = tb;
6797 ctx.exception = POWERPC_EXCP_NONE;
6798 ctx.spr_cb = env->spr_cb;
6799 supervisor = env->mmu_idx;
6800 #if !defined(CONFIG_USER_ONLY)
6801 ctx.supervisor = supervisor;
6802 #endif
6803 #if defined(TARGET_PPC64)
6804 ctx.sf_mode = msr_sf;
6805 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | msr_le;
6806 #else
6807 ctx.mem_idx = (supervisor << 1) | msr_le;
6808 #endif
6809 ctx.dcache_line_size = env->dcache_line_size;
6810 ctx.fpu_enabled = msr_fp;
6811 #if defined(TARGET_PPCEMB)
6812 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6813 ctx.spe_enabled = msr_spe;
6814 else
6815 ctx.spe_enabled = 0;
6816 #endif
6817 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6818 ctx.altivec_enabled = msr_vr;
6819 else
6820 ctx.altivec_enabled = 0;
6821 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6822 single_step = 1;
6823 else
6824 single_step = 0;
6825 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6826 branch_step = 1;
6827 else
6828 branch_step = 0;
6829 ctx.singlestep_enabled = env->singlestep_enabled || single_step == 1;
6830 #if defined (DO_SINGLE_STEP) && 0
6831 /* Single step trace mode */
6832 msr_se = 1;
6833 #endif
6834 /* Set env in case of segfault during code fetch */
6835 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
6836 if (unlikely(env->nb_breakpoints > 0)) {
6837 for (j = 0; j < env->nb_breakpoints; j++) {
6838 if (env->breakpoints[j] == ctx.nip) {
6839 gen_update_nip(&ctx, ctx.nip);
6840 gen_op_debug();
6841 break;
6842 }
6843 }
6844 }
6845 if (unlikely(search_pc)) {
6846 j = gen_opc_ptr - gen_opc_buf;
6847 if (lj < j) {
6848 lj++;
6849 while (lj < j)
6850 gen_opc_instr_start[lj++] = 0;
6851 gen_opc_pc[lj] = ctx.nip;
6852 gen_opc_instr_start[lj] = 1;
6853 }
6854 }
6855 #if defined PPC_DEBUG_DISAS
6856 if (loglevel & CPU_LOG_TB_IN_ASM) {
6857 fprintf(logfile, "----------------\n");
6858 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
6859 ctx.nip, supervisor, (int)msr_ir);
6860 }
6861 #endif
6862 ctx.opcode = ldl_code(ctx.nip);
6863 if (msr_le) {
6864 ctx.opcode = ((ctx.opcode & 0xFF000000) >> 24) |
6865 ((ctx.opcode & 0x00FF0000) >> 8) |
6866 ((ctx.opcode & 0x0000FF00) << 8) |
6867 ((ctx.opcode & 0x000000FF) << 24);
6868 }
6869 #if defined PPC_DEBUG_DISAS
6870 if (loglevel & CPU_LOG_TB_IN_ASM) {
6871 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
6872 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
6873 opc3(ctx.opcode), msr_le ? "little" : "big");
6874 }
6875 #endif
6876 ctx.nip += 4;
6877 table = env->opcodes;
6878 handler = table[opc1(ctx.opcode)];
6879 if (is_indirect_opcode(handler)) {
6880 table = ind_table(handler);
6881 handler = table[opc2(ctx.opcode)];
6882 if (is_indirect_opcode(handler)) {
6883 table = ind_table(handler);
6884 handler = table[opc3(ctx.opcode)];
6885 }
6886 }
6887 /* Is opcode *REALLY* valid ? */
6888 if (unlikely(handler->handler == &gen_invalid)) {
6889 if (loglevel != 0) {
6890 fprintf(logfile, "invalid/unsupported opcode: "
6891 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
6892 opc1(ctx.opcode), opc2(ctx.opcode),
6893 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6894 } else {
6895 printf("invalid/unsupported opcode: "
6896 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
6897 opc1(ctx.opcode), opc2(ctx.opcode),
6898 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6899 }
6900 } else {
6901 if (unlikely((ctx.opcode & handler->inval) != 0)) {
6902 if (loglevel != 0) {
6903 fprintf(logfile, "invalid bits: %08x for opcode: "
6904 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
6905 ctx.opcode & handler->inval, opc1(ctx.opcode),
6906 opc2(ctx.opcode), opc3(ctx.opcode),
6907 ctx.opcode, ctx.nip - 4);
6908 } else {
6909 printf("invalid bits: %08x for opcode: "
6910 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
6911 ctx.opcode & handler->inval, opc1(ctx.opcode),
6912 opc2(ctx.opcode), opc3(ctx.opcode),
6913 ctx.opcode, ctx.nip - 4);
6914 }
6915 GEN_EXCP_INVAL(ctxp);
6916 break;
6917 }
6918 }
6919 (*(handler->handler))(&ctx);
6920 #if defined(DO_PPC_STATISTICS)
6921 handler->count++;
6922 #endif
6923 /* Check trace mode exceptions */
6924 if (unlikely(branch_step != 0 &&
6925 ctx.exception == POWERPC_EXCP_BRANCH)) {
6926 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6927 } else if (unlikely(single_step != 0 &&
6928 (ctx.nip <= 0x100 || ctx.nip > 0xF00 ||
6929 (ctx.nip & 0xFC) != 0x04) &&
6930 ctx.exception != POWERPC_SYSCALL &&
6931 ctx.exception != POWERPC_EXCP_TRAP)) {
6932 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6933 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
6934 (env->singlestep_enabled))) {
6935 /* if we reach a page boundary or are single stepping, stop
6936 * generation
6937 */
6938 break;
6939 }
6940 #if defined (DO_SINGLE_STEP)
6941 break;
6942 #endif
6943 }
6944 if (ctx.exception == POWERPC_EXCP_NONE) {
6945 gen_goto_tb(&ctx, 0, ctx.nip);
6946 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
6947 gen_op_reset_T0();
6948 /* Generate the return instruction */
6949 gen_op_exit_tb();
6950 }
6951 *gen_opc_ptr = INDEX_op_end;
6952 if (unlikely(search_pc)) {
6953 j = gen_opc_ptr - gen_opc_buf;
6954 lj++;
6955 while (lj <= j)
6956 gen_opc_instr_start[lj++] = 0;
6957 } else {
6958 tb->size = ctx.nip - pc_start;
6959 }
6960 #if defined(DEBUG_DISAS)
6961 if (loglevel & CPU_LOG_TB_CPU) {
6962 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
6963 cpu_dump_state(env, logfile, fprintf, 0);
6964 }
6965 if (loglevel & CPU_LOG_TB_IN_ASM) {
6966 int flags;
6967 flags = env->bfd_mach;
6968 flags |= msr_le << 16;
6969 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
6970 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
6971 fprintf(logfile, "\n");
6972 }
6973 if (loglevel & CPU_LOG_TB_OP) {
6974 fprintf(logfile, "OP:\n");
6975 dump_ops(gen_opc_buf, gen_opparam_buf);
6976 fprintf(logfile, "\n");
6977 }
6978 #endif
6979 return 0;
6980 }
6981
6982 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
6983 {
6984 return gen_intermediate_code_internal(env, tb, 0);
6985 }
6986
6987 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
6988 {
6989 return gen_intermediate_code_internal(env, tb, 1);
6990 }
Qemu copy for testing