2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include "qemu-common.h"
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
40 /* Include definitions for instructions classes and implementations flags */
41 //#define DO_SINGLE_STEP
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
45 /*****************************************************************************/
46 /* Code translation helpers */
48 /* global register indexes */
49 static TCGv_ptr cpu_env
;
50 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
51 #if !defined(TARGET_PPC64)
52 + 10*4 + 22*5 /* SPE GPRh */
54 + 10*4 + 22*5 /* FPR */
55 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 static TCGv cpu_gpr
[32];
58 #if !defined(TARGET_PPC64)
59 static TCGv cpu_gprh
[32];
61 static TCGv_i64 cpu_fpr
[32];
62 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
63 static TCGv_i32 cpu_crf
[8];
69 static TCGv cpu_reserve
;
70 static TCGv_i32 cpu_fpscr
;
71 static TCGv_i32 cpu_access_type
;
73 #include "gen-icount.h"
75 void ppc_translate_init(void)
79 static int done_init
= 0;
84 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
88 for (i
= 0; i
< 8; i
++) {
89 sprintf(p
, "crf%d", i
);
90 cpu_crf
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
91 offsetof(CPUState
, crf
[i
]), p
);
95 for (i
= 0; i
< 32; i
++) {
97 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
98 offsetof(CPUState
, gpr
[i
]), p
);
99 p
+= (i
< 10) ? 3 : 4;
100 #if !defined(TARGET_PPC64)
101 sprintf(p
, "r%dH", i
);
102 cpu_gprh
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
103 offsetof(CPUState
, gprh
[i
]), p
);
104 p
+= (i
< 10) ? 4 : 5;
107 sprintf(p
, "fp%d", i
);
108 cpu_fpr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
109 offsetof(CPUState
, fpr
[i
]), p
);
110 p
+= (i
< 10) ? 4 : 5;
112 sprintf(p
, "avr%dH", i
);
113 #ifdef WORDS_BIGENDIAN
114 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
115 offsetof(CPUState
, avr
[i
].u64
[0]), p
);
117 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
118 offsetof(CPUState
, avr
[i
].u64
[1]), p
);
120 p
+= (i
< 10) ? 6 : 7;
122 sprintf(p
, "avr%dL", i
);
123 #ifdef WORDS_BIGENDIAN
124 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
125 offsetof(CPUState
, avr
[i
].u64
[1]), p
);
127 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
128 offsetof(CPUState
, avr
[i
].u64
[0]), p
);
130 p
+= (i
< 10) ? 6 : 7;
133 cpu_nip
= tcg_global_mem_new(TCG_AREG0
,
134 offsetof(CPUState
, nip
), "nip");
136 cpu_msr
= tcg_global_mem_new(TCG_AREG0
,
137 offsetof(CPUState
, msr
), "msr");
139 cpu_ctr
= tcg_global_mem_new(TCG_AREG0
,
140 offsetof(CPUState
, ctr
), "ctr");
142 cpu_lr
= tcg_global_mem_new(TCG_AREG0
,
143 offsetof(CPUState
, lr
), "lr");
145 cpu_xer
= tcg_global_mem_new(TCG_AREG0
,
146 offsetof(CPUState
, xer
), "xer");
148 cpu_reserve
= tcg_global_mem_new(TCG_AREG0
,
149 offsetof(CPUState
, reserve
), "reserve");
151 cpu_fpscr
= tcg_global_mem_new_i32(TCG_AREG0
,
152 offsetof(CPUState
, fpscr
), "fpscr");
154 cpu_access_type
= tcg_global_mem_new_i32(TCG_AREG0
,
155 offsetof(CPUState
, access_type
), "access_type");
157 /* register helpers */
164 /* internal defines */
165 typedef struct DisasContext
{
166 struct TranslationBlock
*tb
;
170 /* Routine used to access memory */
173 /* Translation flags */
175 #if defined(TARGET_PPC64)
181 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
182 int singlestep_enabled
;
185 struct opc_handler_t
{
188 /* instruction type */
191 void (*handler
)(DisasContext
*ctx
);
192 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
195 #if defined(DO_PPC_STATISTICS)
200 static always_inline
void gen_reset_fpstatus (void)
202 #ifdef CONFIG_SOFTFLOAT
203 gen_helper_reset_fpstatus();
207 static always_inline
void gen_compute_fprf (TCGv_i64 arg
, int set_fprf
, int set_rc
)
209 TCGv_i32 t0
= tcg_temp_new_i32();
212 /* This case might be optimized later */
213 tcg_gen_movi_i32(t0
, 1);
214 gen_helper_compute_fprf(t0
, arg
, t0
);
215 if (unlikely(set_rc
)) {
216 tcg_gen_mov_i32(cpu_crf
[1], t0
);
218 gen_helper_float_check_status();
219 } else if (unlikely(set_rc
)) {
220 /* We always need to compute fpcc */
221 tcg_gen_movi_i32(t0
, 0);
222 gen_helper_compute_fprf(t0
, arg
, t0
);
223 tcg_gen_mov_i32(cpu_crf
[1], t0
);
226 tcg_temp_free_i32(t0
);
229 static always_inline
void gen_set_access_type (DisasContext
*ctx
, int access_type
)
231 if (ctx
->access_type
!= access_type
) {
232 tcg_gen_movi_i32(cpu_access_type
, access_type
);
233 ctx
->access_type
= access_type
;
237 static always_inline
void gen_update_nip (DisasContext
*ctx
, target_ulong nip
)
239 #if defined(TARGET_PPC64)
241 tcg_gen_movi_tl(cpu_nip
, nip
);
244 tcg_gen_movi_tl(cpu_nip
, (uint32_t)nip
);
247 static always_inline
void gen_exception_err (DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
250 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
251 gen_update_nip(ctx
, ctx
->nip
);
253 t0
= tcg_const_i32(excp
);
254 t1
= tcg_const_i32(error
);
255 gen_helper_raise_exception_err(t0
, t1
);
256 tcg_temp_free_i32(t0
);
257 tcg_temp_free_i32(t1
);
258 ctx
->exception
= (excp
);
261 static always_inline
void gen_exception (DisasContext
*ctx
, uint32_t excp
)
264 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
265 gen_update_nip(ctx
, ctx
->nip
);
267 t0
= tcg_const_i32(excp
);
268 gen_helper_raise_exception(t0
);
269 tcg_temp_free_i32(t0
);
270 ctx
->exception
= (excp
);
273 static always_inline
void gen_debug_exception (DisasContext
*ctx
)
276 gen_update_nip(ctx
, ctx
->nip
);
277 t0
= tcg_const_i32(EXCP_DEBUG
);
278 gen_helper_raise_exception(t0
);
279 tcg_temp_free_i32(t0
);
282 static always_inline
void gen_inval_exception (DisasContext
*ctx
, uint32_t error
)
284 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_INVAL
| error
);
287 /* Stop translation */
288 static always_inline
void gen_stop_exception (DisasContext
*ctx
)
290 gen_update_nip(ctx
, ctx
->nip
);
291 ctx
->exception
= POWERPC_EXCP_STOP
;
294 /* No need to update nip here, as execution flow will change */
295 static always_inline
void gen_sync_exception (DisasContext
*ctx
)
297 ctx
->exception
= POWERPC_EXCP_SYNC
;
300 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
301 static void gen_##name (DisasContext *ctx); \
302 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
303 static void gen_##name (DisasContext *ctx)
305 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
306 static void gen_##name (DisasContext *ctx); \
307 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
308 static void gen_##name (DisasContext *ctx)
310 typedef struct opcode_t
{
311 unsigned char opc1
, opc2
, opc3
;
312 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
313 unsigned char pad
[5];
315 unsigned char pad
[1];
317 opc_handler_t handler
;
321 /*****************************************************************************/
322 /*** Instruction decoding ***/
323 #define EXTRACT_HELPER(name, shift, nb) \
324 static always_inline uint32_t name (uint32_t opcode) \
326 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
329 #define EXTRACT_SHELPER(name, shift, nb) \
330 static always_inline int32_t name (uint32_t opcode) \
332 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
336 EXTRACT_HELPER(opc1
, 26, 6);
338 EXTRACT_HELPER(opc2
, 1, 5);
340 EXTRACT_HELPER(opc3
, 6, 5);
341 /* Update Cr0 flags */
342 EXTRACT_HELPER(Rc
, 0, 1);
344 EXTRACT_HELPER(rD
, 21, 5);
346 EXTRACT_HELPER(rS
, 21, 5);
348 EXTRACT_HELPER(rA
, 16, 5);
350 EXTRACT_HELPER(rB
, 11, 5);
352 EXTRACT_HELPER(rC
, 6, 5);
354 EXTRACT_HELPER(crfD
, 23, 3);
355 EXTRACT_HELPER(crfS
, 18, 3);
356 EXTRACT_HELPER(crbD
, 21, 5);
357 EXTRACT_HELPER(crbA
, 16, 5);
358 EXTRACT_HELPER(crbB
, 11, 5);
360 EXTRACT_HELPER(_SPR
, 11, 10);
361 static always_inline
uint32_t SPR (uint32_t opcode
)
363 uint32_t sprn
= _SPR(opcode
);
365 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
367 /*** Get constants ***/
368 EXTRACT_HELPER(IMM
, 12, 8);
369 /* 16 bits signed immediate value */
370 EXTRACT_SHELPER(SIMM
, 0, 16);
371 /* 16 bits unsigned immediate value */
372 EXTRACT_HELPER(UIMM
, 0, 16);
374 EXTRACT_HELPER(NB
, 11, 5);
376 EXTRACT_HELPER(SH
, 11, 5);
378 EXTRACT_HELPER(MB
, 6, 5);
380 EXTRACT_HELPER(ME
, 1, 5);
382 EXTRACT_HELPER(TO
, 21, 5);
384 EXTRACT_HELPER(CRM
, 12, 8);
385 EXTRACT_HELPER(FM
, 17, 8);
386 EXTRACT_HELPER(SR
, 16, 4);
387 EXTRACT_HELPER(FPIMM
, 12, 4);
389 /*** Jump target decoding ***/
391 EXTRACT_SHELPER(d
, 0, 16);
392 /* Immediate address */
393 static always_inline target_ulong
LI (uint32_t opcode
)
395 return (opcode
>> 0) & 0x03FFFFFC;
398 static always_inline
uint32_t BD (uint32_t opcode
)
400 return (opcode
>> 0) & 0xFFFC;
403 EXTRACT_HELPER(BO
, 21, 5);
404 EXTRACT_HELPER(BI
, 16, 5);
405 /* Absolute/relative address */
406 EXTRACT_HELPER(AA
, 1, 1);
408 EXTRACT_HELPER(LK
, 0, 1);
410 /* Create a mask between <start> and <end> bits */
411 static always_inline target_ulong
MASK (uint32_t start
, uint32_t end
)
415 #if defined(TARGET_PPC64)
416 if (likely(start
== 0)) {
417 ret
= UINT64_MAX
<< (63 - end
);
418 } else if (likely(end
== 63)) {
419 ret
= UINT64_MAX
>> start
;
422 if (likely(start
== 0)) {
423 ret
= UINT32_MAX
<< (31 - end
);
424 } else if (likely(end
== 31)) {
425 ret
= UINT32_MAX
>> start
;
429 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
430 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
431 if (unlikely(start
> end
))
438 /*****************************************************************************/
439 /* PowerPC Instructions types definitions */
441 PPC_NONE
= 0x0000000000000000ULL
,
442 /* PowerPC base instructions set */
443 PPC_INSNS_BASE
= 0x0000000000000001ULL
,
444 /* integer operations instructions */
445 #define PPC_INTEGER PPC_INSNS_BASE
446 /* flow control instructions */
447 #define PPC_FLOW PPC_INSNS_BASE
448 /* virtual memory instructions */
449 #define PPC_MEM PPC_INSNS_BASE
450 /* ld/st with reservation instructions */
451 #define PPC_RES PPC_INSNS_BASE
452 /* spr/msr access instructions */
453 #define PPC_MISC PPC_INSNS_BASE
454 /* Deprecated instruction sets */
455 /* Original POWER instruction set */
456 PPC_POWER
= 0x0000000000000002ULL
,
457 /* POWER2 instruction set extension */
458 PPC_POWER2
= 0x0000000000000004ULL
,
459 /* Power RTC support */
460 PPC_POWER_RTC
= 0x0000000000000008ULL
,
461 /* Power-to-PowerPC bridge (601) */
462 PPC_POWER_BR
= 0x0000000000000010ULL
,
463 /* 64 bits PowerPC instruction set */
464 PPC_64B
= 0x0000000000000020ULL
,
465 /* New 64 bits extensions (PowerPC 2.0x) */
466 PPC_64BX
= 0x0000000000000040ULL
,
467 /* 64 bits hypervisor extensions */
468 PPC_64H
= 0x0000000000000080ULL
,
469 /* New wait instruction (PowerPC 2.0x) */
470 PPC_WAIT
= 0x0000000000000100ULL
,
471 /* Time base mftb instruction */
472 PPC_MFTB
= 0x0000000000000200ULL
,
474 /* Fixed-point unit extensions */
475 /* PowerPC 602 specific */
476 PPC_602_SPEC
= 0x0000000000000400ULL
,
477 /* isel instruction */
478 PPC_ISEL
= 0x0000000000000800ULL
,
479 /* popcntb instruction */
480 PPC_POPCNTB
= 0x0000000000001000ULL
,
481 /* string load / store */
482 PPC_STRING
= 0x0000000000002000ULL
,
484 /* Floating-point unit extensions */
485 /* Optional floating point instructions */
486 PPC_FLOAT
= 0x0000000000010000ULL
,
487 /* New floating-point extensions (PowerPC 2.0x) */
488 PPC_FLOAT_EXT
= 0x0000000000020000ULL
,
489 PPC_FLOAT_FSQRT
= 0x0000000000040000ULL
,
490 PPC_FLOAT_FRES
= 0x0000000000080000ULL
,
491 PPC_FLOAT_FRSQRTE
= 0x0000000000100000ULL
,
492 PPC_FLOAT_FRSQRTES
= 0x0000000000200000ULL
,
493 PPC_FLOAT_FSEL
= 0x0000000000400000ULL
,
494 PPC_FLOAT_STFIWX
= 0x0000000000800000ULL
,
496 /* Vector/SIMD extensions */
497 /* Altivec support */
498 PPC_ALTIVEC
= 0x0000000001000000ULL
,
499 /* PowerPC 2.03 SPE extension */
500 PPC_SPE
= 0x0000000002000000ULL
,
501 /* PowerPC 2.03 SPE floating-point extension */
502 PPC_SPEFPU
= 0x0000000004000000ULL
,
504 /* Optional memory control instructions */
505 PPC_MEM_TLBIA
= 0x0000000010000000ULL
,
506 PPC_MEM_TLBIE
= 0x0000000020000000ULL
,
507 PPC_MEM_TLBSYNC
= 0x0000000040000000ULL
,
508 /* sync instruction */
509 PPC_MEM_SYNC
= 0x0000000080000000ULL
,
510 /* eieio instruction */
511 PPC_MEM_EIEIO
= 0x0000000100000000ULL
,
513 /* Cache control instructions */
514 PPC_CACHE
= 0x0000000200000000ULL
,
515 /* icbi instruction */
516 PPC_CACHE_ICBI
= 0x0000000400000000ULL
,
517 /* dcbz instruction with fixed cache line size */
518 PPC_CACHE_DCBZ
= 0x0000000800000000ULL
,
519 /* dcbz instruction with tunable cache line size */
520 PPC_CACHE_DCBZT
= 0x0000001000000000ULL
,
521 /* dcba instruction */
522 PPC_CACHE_DCBA
= 0x0000002000000000ULL
,
523 /* Freescale cache locking instructions */
524 PPC_CACHE_LOCK
= 0x0000004000000000ULL
,
526 /* MMU related extensions */
527 /* external control instructions */
528 PPC_EXTERN
= 0x0000010000000000ULL
,
529 /* segment register access instructions */
530 PPC_SEGMENT
= 0x0000020000000000ULL
,
531 /* PowerPC 6xx TLB management instructions */
532 PPC_6xx_TLB
= 0x0000040000000000ULL
,
533 /* PowerPC 74xx TLB management instructions */
534 PPC_74xx_TLB
= 0x0000080000000000ULL
,
535 /* PowerPC 40x TLB management instructions */
536 PPC_40x_TLB
= 0x0000100000000000ULL
,
537 /* segment register access instructions for PowerPC 64 "bridge" */
538 PPC_SEGMENT_64B
= 0x0000200000000000ULL
,
540 PPC_SLBI
= 0x0000400000000000ULL
,
542 /* Embedded PowerPC dedicated instructions */
543 PPC_WRTEE
= 0x0001000000000000ULL
,
544 /* PowerPC 40x exception model */
545 PPC_40x_EXCP
= 0x0002000000000000ULL
,
546 /* PowerPC 405 Mac instructions */
547 PPC_405_MAC
= 0x0004000000000000ULL
,
548 /* PowerPC 440 specific instructions */
549 PPC_440_SPEC
= 0x0008000000000000ULL
,
550 /* BookE (embedded) PowerPC specification */
551 PPC_BOOKE
= 0x0010000000000000ULL
,
552 /* mfapidi instruction */
553 PPC_MFAPIDI
= 0x0020000000000000ULL
,
554 /* tlbiva instruction */
555 PPC_TLBIVA
= 0x0040000000000000ULL
,
556 /* tlbivax instruction */
557 PPC_TLBIVAX
= 0x0080000000000000ULL
,
558 /* PowerPC 4xx dedicated instructions */
559 PPC_4xx_COMMON
= 0x0100000000000000ULL
,
560 /* PowerPC 40x ibct instructions */
561 PPC_40x_ICBT
= 0x0200000000000000ULL
,
562 /* rfmci is not implemented in all BookE PowerPC */
563 PPC_RFMCI
= 0x0400000000000000ULL
,
564 /* rfdi instruction */
565 PPC_RFDI
= 0x0800000000000000ULL
,
567 PPC_DCR
= 0x1000000000000000ULL
,
568 /* DCR extended accesse */
569 PPC_DCRX
= 0x2000000000000000ULL
,
570 /* user-mode DCR access, implemented in PowerPC 460 */
571 PPC_DCRUX
= 0x4000000000000000ULL
,
574 /*****************************************************************************/
575 /* PowerPC instructions table */
576 #if HOST_LONG_BITS == 64
581 #if defined(__APPLE__)
582 #define OPCODES_SECTION \
583 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
585 #define OPCODES_SECTION \
586 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
589 #if defined(DO_PPC_STATISTICS)
590 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
591 OPCODES_SECTION opcode_t opc_##name = { \
599 .handler = &gen_##name, \
600 .oname = stringify(name), \
602 .oname = stringify(name), \
604 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
605 OPCODES_SECTION opcode_t opc_##name = { \
613 .handler = &gen_##name, \
619 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
620 OPCODES_SECTION opcode_t opc_##name = { \
628 .handler = &gen_##name, \
630 .oname = stringify(name), \
632 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
633 OPCODES_SECTION opcode_t opc_##name = { \
641 .handler = &gen_##name, \
647 #define GEN_OPCODE_MARK(name) \
648 OPCODES_SECTION opcode_t opc_##name = { \
654 .inval = 0x00000000, \
658 .oname = stringify(name), \
661 /* SPR load/store helpers */
662 static always_inline
void gen_load_spr(TCGv t
, int reg
)
664 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUState
, spr
[reg
]));
667 static always_inline
void gen_store_spr(int reg
, TCGv t
)
669 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUState
, spr
[reg
]));
672 /* Start opcode list */
673 GEN_OPCODE_MARK(start
);
675 /* Invalid instruction */
676 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
)
678 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
681 static opc_handler_t invalid_handler
= {
684 .handler
= gen_invalid
,
687 /*** Integer comparison ***/
689 static always_inline
void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
693 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_xer
);
694 tcg_gen_shri_i32(cpu_crf
[crf
], cpu_crf
[crf
], XER_SO
);
695 tcg_gen_andi_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1);
697 l1
= gen_new_label();
698 l2
= gen_new_label();
699 l3
= gen_new_label();
701 tcg_gen_brcond_tl(TCG_COND_LT
, arg0
, arg1
, l1
);
702 tcg_gen_brcond_tl(TCG_COND_GT
, arg0
, arg1
, l2
);
704 tcg_gen_brcond_tl(TCG_COND_LTU
, arg0
, arg1
, l1
);
705 tcg_gen_brcond_tl(TCG_COND_GTU
, arg0
, arg1
, l2
);
707 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_EQ
);
710 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_LT
);
713 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_GT
);
717 static always_inline
void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
719 TCGv t0
= tcg_const_local_tl(arg1
);
720 gen_op_cmp(arg0
, t0
, s
, crf
);
724 #if defined(TARGET_PPC64)
725 static always_inline
void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
728 t0
= tcg_temp_local_new();
729 t1
= tcg_temp_local_new();
731 tcg_gen_ext32s_tl(t0
, arg0
);
732 tcg_gen_ext32s_tl(t1
, arg1
);
734 tcg_gen_ext32u_tl(t0
, arg0
);
735 tcg_gen_ext32u_tl(t1
, arg1
);
737 gen_op_cmp(t0
, t1
, s
, crf
);
742 static always_inline
void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
744 TCGv t0
= tcg_const_local_tl(arg1
);
745 gen_op_cmp32(arg0
, t0
, s
, crf
);
750 static always_inline
void gen_set_Rc0 (DisasContext
*ctx
, TCGv reg
)
752 #if defined(TARGET_PPC64)
754 gen_op_cmpi32(reg
, 0, 1, 0);
757 gen_op_cmpi(reg
, 0, 1, 0);
761 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
)
763 #if defined(TARGET_PPC64)
764 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
765 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
766 1, crfD(ctx
->opcode
));
769 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
770 1, crfD(ctx
->opcode
));
774 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
776 #if defined(TARGET_PPC64)
777 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
778 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
779 1, crfD(ctx
->opcode
));
782 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
783 1, crfD(ctx
->opcode
));
787 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
)
789 #if defined(TARGET_PPC64)
790 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
791 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
792 0, crfD(ctx
->opcode
));
795 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
796 0, crfD(ctx
->opcode
));
800 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
)
802 #if defined(TARGET_PPC64)
803 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
804 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
805 0, crfD(ctx
->opcode
));
808 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
809 0, crfD(ctx
->opcode
));
812 /* isel (PowerPC 2.03 specification) */
813 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
)
816 uint32_t bi
= rC(ctx
->opcode
);
820 l1
= gen_new_label();
821 l2
= gen_new_label();
823 mask
= 1 << (3 - (bi
& 0x03));
824 t0
= tcg_temp_new_i32();
825 tcg_gen_andi_i32(t0
, cpu_crf
[bi
>> 2], mask
);
826 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
827 if (rA(ctx
->opcode
) == 0)
828 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
830 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
833 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
835 tcg_temp_free_i32(t0
);
838 /*** Integer arithmetic ***/
840 static always_inline
void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
, TCGv arg1
, TCGv arg2
, int sub
)
845 l1
= gen_new_label();
846 /* Start with XER OV disabled, the most likely case */
847 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
848 t0
= tcg_temp_local_new();
849 tcg_gen_xor_tl(t0
, arg0
, arg1
);
850 #if defined(TARGET_PPC64)
852 tcg_gen_ext32s_tl(t0
, t0
);
855 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0, l1
);
857 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
858 tcg_gen_xor_tl(t0
, arg1
, arg2
);
859 #if defined(TARGET_PPC64)
861 tcg_gen_ext32s_tl(t0
, t0
);
864 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
866 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0, l1
);
867 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
872 static always_inline
void gen_op_arith_compute_ca(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
, int sub
)
874 int l1
= gen_new_label();
876 #if defined(TARGET_PPC64)
877 if (!(ctx
->sf_mode
)) {
882 tcg_gen_ext32u_tl(t0
, arg1
);
883 tcg_gen_ext32u_tl(t1
, arg2
);
885 tcg_gen_brcond_tl(TCG_COND_GTU
, t0
, t1
, l1
);
887 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
889 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
897 tcg_gen_brcond_tl(TCG_COND_GTU
, arg1
, arg2
, l1
);
899 tcg_gen_brcond_tl(TCG_COND_GEU
, arg1
, arg2
, l1
);
901 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
906 /* Common add function */
907 static always_inline
void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
, TCGv arg2
,
908 int add_ca
, int compute_ca
, int compute_ov
)
912 if ((!compute_ca
&& !compute_ov
) ||
913 (!TCGV_EQUAL(ret
,arg1
) && !TCGV_EQUAL(ret
, arg2
))) {
916 t0
= tcg_temp_local_new();
920 t1
= tcg_temp_local_new();
921 tcg_gen_andi_tl(t1
, cpu_xer
, (1 << XER_CA
));
922 tcg_gen_shri_tl(t1
, t1
, XER_CA
);
925 if (compute_ca
&& compute_ov
) {
926 /* Start with XER CA and OV disabled, the most likely case */
927 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~((1 << XER_CA
) | (1 << XER_OV
)));
928 } else if (compute_ca
) {
929 /* Start with XER CA disabled, the most likely case */
930 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
931 } else if (compute_ov
) {
932 /* Start with XER OV disabled, the most likely case */
933 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
936 tcg_gen_add_tl(t0
, arg1
, arg2
);
939 gen_op_arith_compute_ca(ctx
, t0
, arg1
, 0);
942 tcg_gen_add_tl(t0
, t0
, t1
);
943 gen_op_arith_compute_ca(ctx
, t0
, t1
, 0);
947 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
950 if (unlikely(Rc(ctx
->opcode
) != 0))
951 gen_set_Rc0(ctx
, t0
);
953 if (!TCGV_EQUAL(t0
, ret
)) {
954 tcg_gen_mov_tl(ret
, t0
);
958 /* Add functions with two operands */
959 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
960 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
962 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
963 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
964 add_ca, compute_ca, compute_ov); \
966 /* Add functions with one operand and one immediate */
967 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
968 add_ca, compute_ca, compute_ov) \
969 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
971 TCGv t0 = tcg_const_local_tl(const_val); \
972 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
973 cpu_gpr[rA(ctx->opcode)], t0, \
974 add_ca, compute_ca, compute_ov); \
978 /* add add. addo addo. */
979 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
980 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
981 /* addc addc. addco addco. */
982 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
983 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
984 /* adde adde. addeo addeo. */
985 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
986 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
987 /* addme addme. addmeo addmeo. */
988 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
989 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
990 /* addze addze. addzeo addzeo.*/
991 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
992 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
994 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
996 target_long simm
= SIMM(ctx
->opcode
);
998 if (rA(ctx
->opcode
) == 0) {
1000 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
1002 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], simm
);
1006 static always_inline
void gen_op_addic (DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1009 target_long simm
= SIMM(ctx
->opcode
);
1011 /* Start with XER CA and OV disabled, the most likely case */
1012 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1014 if (likely(simm
!= 0)) {
1015 TCGv t0
= tcg_temp_local_new();
1016 tcg_gen_addi_tl(t0
, arg1
, simm
);
1017 gen_op_arith_compute_ca(ctx
, t0
, arg1
, 0);
1018 tcg_gen_mov_tl(ret
, t0
);
1021 tcg_gen_mov_tl(ret
, arg1
);
1024 gen_set_Rc0(ctx
, ret
);
1027 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1029 gen_op_addic(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0);
1031 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1033 gen_op_addic(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 1);
1036 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1038 target_long simm
= SIMM(ctx
->opcode
);
1040 if (rA(ctx
->opcode
) == 0) {
1042 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
1044 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
1048 static always_inline
void gen_op_arith_divw (DisasContext
*ctx
, TCGv ret
, TCGv arg1
, TCGv arg2
,
1049 int sign
, int compute_ov
)
1051 int l1
= gen_new_label();
1052 int l2
= gen_new_label();
1053 TCGv_i32 t0
= tcg_temp_local_new_i32();
1054 TCGv_i32 t1
= tcg_temp_local_new_i32();
1056 tcg_gen_trunc_tl_i32(t0
, arg1
);
1057 tcg_gen_trunc_tl_i32(t1
, arg2
);
1058 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
1060 int l3
= gen_new_label();
1061 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
1062 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
1064 tcg_gen_div_i32(t0
, t0
, t1
);
1066 tcg_gen_divu_i32(t0
, t0
, t1
);
1069 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1074 tcg_gen_sari_i32(t0
, t0
, 31);
1076 tcg_gen_movi_i32(t0
, 0);
1079 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1082 tcg_gen_extu_i32_tl(ret
, t0
);
1083 tcg_temp_free_i32(t0
);
1084 tcg_temp_free_i32(t1
);
1085 if (unlikely(Rc(ctx
->opcode
) != 0))
1086 gen_set_Rc0(ctx
, ret
);
1089 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1090 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1092 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1093 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1094 sign, compute_ov); \
1096 /* divwu divwu. divwuo divwuo. */
1097 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1098 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1099 /* divw divw. divwo divwo. */
1100 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1101 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1102 #if defined(TARGET_PPC64)
1103 static always_inline
void gen_op_arith_divd (DisasContext
*ctx
, TCGv ret
, TCGv arg1
, TCGv arg2
,
1104 int sign
, int compute_ov
)
1106 int l1
= gen_new_label();
1107 int l2
= gen_new_label();
1109 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
1111 int l3
= gen_new_label();
1112 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
1113 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
1115 tcg_gen_div_i64(ret
, arg1
, arg2
);
1117 tcg_gen_divu_i64(ret
, arg1
, arg2
);
1120 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1125 tcg_gen_sari_i64(ret
, arg1
, 63);
1127 tcg_gen_movi_i64(ret
, 0);
1130 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1133 if (unlikely(Rc(ctx
->opcode
) != 0))
1134 gen_set_Rc0(ctx
, ret
);
1136 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1137 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1139 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1140 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1141 sign, compute_ov); \
1143 /* divwu divwu. divwuo divwuo. */
1144 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1145 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1146 /* divw divw. divwo divwo. */
1147 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1148 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1152 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
)
1156 t0
= tcg_temp_new_i64();
1157 t1
= tcg_temp_new_i64();
1158 #if defined(TARGET_PPC64)
1159 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1160 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1161 tcg_gen_mul_i64(t0
, t0
, t1
);
1162 tcg_gen_shri_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
1164 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1165 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1166 tcg_gen_mul_i64(t0
, t0
, t1
);
1167 tcg_gen_shri_i64(t0
, t0
, 32);
1168 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1170 tcg_temp_free_i64(t0
);
1171 tcg_temp_free_i64(t1
);
1172 if (unlikely(Rc(ctx
->opcode
) != 0))
1173 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1175 /* mulhwu mulhwu. */
1176 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
)
1180 t0
= tcg_temp_new_i64();
1181 t1
= tcg_temp_new_i64();
1182 #if defined(TARGET_PPC64)
1183 tcg_gen_ext32u_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1184 tcg_gen_ext32u_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1185 tcg_gen_mul_i64(t0
, t0
, t1
);
1186 tcg_gen_shri_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
1188 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1189 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1190 tcg_gen_mul_i64(t0
, t0
, t1
);
1191 tcg_gen_shri_i64(t0
, t0
, 32);
1192 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1194 tcg_temp_free_i64(t0
);
1195 tcg_temp_free_i64(t1
);
1196 if (unlikely(Rc(ctx
->opcode
) != 0))
1197 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1200 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
)
1202 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1203 cpu_gpr
[rB(ctx
->opcode
)]);
1204 tcg_gen_ext32s_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)]);
1205 if (unlikely(Rc(ctx
->opcode
) != 0))
1206 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1208 /* mullwo mullwo. */
1209 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
)
1214 t0
= tcg_temp_new_i64();
1215 t1
= tcg_temp_new_i64();
1216 l1
= gen_new_label();
1217 /* Start with XER OV disabled, the most likely case */
1218 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1219 #if defined(TARGET_PPC64)
1220 tcg_gen_ext32s_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1221 tcg_gen_ext32s_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1223 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1224 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1226 tcg_gen_mul_i64(t0
, t0
, t1
);
1227 #if defined(TARGET_PPC64)
1228 tcg_gen_ext32s_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1229 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, cpu_gpr
[rD(ctx
->opcode
)], l1
);
1231 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1232 tcg_gen_ext32s_i64(t1
, t0
);
1233 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
1235 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1237 tcg_temp_free_i64(t0
);
1238 tcg_temp_free_i64(t1
);
1239 if (unlikely(Rc(ctx
->opcode
) != 0))
1240 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1243 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1245 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1248 #if defined(TARGET_PPC64)
1249 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1250 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1252 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1253 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1254 if (unlikely(Rc(ctx->opcode) != 0)) \
1255 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1258 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00);
1259 /* mulhdu mulhdu. */
1260 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02);
1262 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
)
1264 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1265 cpu_gpr
[rB(ctx
->opcode
)]);
1266 if (unlikely(Rc(ctx
->opcode
) != 0))
1267 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1269 /* mulldo mulldo. */
1270 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17);
1273 /* neg neg. nego nego. */
1274 static always_inline
void gen_op_arith_neg (DisasContext
*ctx
, TCGv ret
, TCGv arg1
, int ov_check
)
1276 int l1
= gen_new_label();
1277 int l2
= gen_new_label();
1278 TCGv t0
= tcg_temp_local_new();
1279 #if defined(TARGET_PPC64)
1281 tcg_gen_mov_tl(t0
, arg1
);
1282 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, INT64_MIN
, l1
);
1286 tcg_gen_ext32s_tl(t0
, arg1
);
1287 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
1289 tcg_gen_neg_tl(ret
, arg1
);
1291 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1295 tcg_gen_mov_tl(ret
, t0
);
1297 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1301 if (unlikely(Rc(ctx
->opcode
) != 0))
1302 gen_set_Rc0(ctx
, ret
);
1304 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
)
1306 gen_op_arith_neg(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0);
1308 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
)
1310 gen_op_arith_neg(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 1);
1313 /* Common subf function */
1314 static always_inline
void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
, TCGv arg2
,
1315 int add_ca
, int compute_ca
, int compute_ov
)
1319 if ((!compute_ca
&& !compute_ov
) ||
1320 (!TCGV_EQUAL(ret
, arg1
) && !TCGV_EQUAL(ret
, arg2
))) {
1323 t0
= tcg_temp_local_new();
1327 t1
= tcg_temp_local_new();
1328 tcg_gen_andi_tl(t1
, cpu_xer
, (1 << XER_CA
));
1329 tcg_gen_shri_tl(t1
, t1
, XER_CA
);
1332 if (compute_ca
&& compute_ov
) {
1333 /* Start with XER CA and OV disabled, the most likely case */
1334 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~((1 << XER_CA
) | (1 << XER_OV
)));
1335 } else if (compute_ca
) {
1336 /* Start with XER CA disabled, the most likely case */
1337 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1338 } else if (compute_ov
) {
1339 /* Start with XER OV disabled, the most likely case */
1340 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1344 tcg_gen_not_tl(t0
, arg1
);
1345 tcg_gen_add_tl(t0
, t0
, arg2
);
1346 gen_op_arith_compute_ca(ctx
, t0
, arg2
, 0);
1347 tcg_gen_add_tl(t0
, t0
, t1
);
1348 gen_op_arith_compute_ca(ctx
, t0
, t1
, 0);
1351 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1353 gen_op_arith_compute_ca(ctx
, t0
, arg2
, 1);
1357 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1360 if (unlikely(Rc(ctx
->opcode
) != 0))
1361 gen_set_Rc0(ctx
, t0
);
1363 if (!TCGV_EQUAL(t0
, ret
)) {
1364 tcg_gen_mov_tl(ret
, t0
);
1368 /* Sub functions with Two operands functions */
1369 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1370 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1372 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1373 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1374 add_ca, compute_ca, compute_ov); \
1376 /* Sub functions with one operand and one immediate */
1377 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1378 add_ca, compute_ca, compute_ov) \
1379 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1381 TCGv t0 = tcg_const_local_tl(const_val); \
1382 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1383 cpu_gpr[rA(ctx->opcode)], t0, \
1384 add_ca, compute_ca, compute_ov); \
1385 tcg_temp_free(t0); \
1387 /* subf subf. subfo subfo. */
1388 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1389 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1390 /* subfc subfc. subfco subfco. */
1391 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1392 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1393 /* subfe subfe. subfeo subfo. */
1394 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1395 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1396 /* subfme subfme. subfmeo subfmeo. */
1397 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1398 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1399 /* subfze subfze. subfzeo subfzeo.*/
1400 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1401 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1403 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1405 /* Start with XER CA and OV disabled, the most likely case */
1406 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1407 TCGv t0
= tcg_temp_local_new();
1408 TCGv t1
= tcg_const_local_tl(SIMM(ctx
->opcode
));
1409 tcg_gen_sub_tl(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)]);
1410 gen_op_arith_compute_ca(ctx
, t0
, t1
, 1);
1412 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1416 /*** Integer logical ***/
1417 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1418 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1420 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1421 cpu_gpr[rB(ctx->opcode)]); \
1422 if (unlikely(Rc(ctx->opcode) != 0)) \
1423 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1426 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1427 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1429 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1430 if (unlikely(Rc(ctx->opcode) != 0)) \
1431 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1435 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1437 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1439 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1441 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1442 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1445 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1447 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1448 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1451 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
)
1453 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1454 if (unlikely(Rc(ctx
->opcode
) != 0))
1455 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1458 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1459 /* extsb & extsb. */
1460 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1461 /* extsh & extsh. */
1462 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1464 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1466 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1468 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
)
1472 rs
= rS(ctx
->opcode
);
1473 ra
= rA(ctx
->opcode
);
1474 rb
= rB(ctx
->opcode
);
1475 /* Optimisation for mr. ri case */
1476 if (rs
!= ra
|| rs
!= rb
) {
1478 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1480 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1481 if (unlikely(Rc(ctx
->opcode
) != 0))
1482 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1483 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1484 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1485 #if defined(TARGET_PPC64)
1491 /* Set process priority to low */
1495 /* Set process priority to medium-low */
1499 /* Set process priority to normal */
1502 #if !defined(CONFIG_USER_ONLY)
1504 if (ctx
->mem_idx
> 0) {
1505 /* Set process priority to very low */
1510 if (ctx
->mem_idx
> 0) {
1511 /* Set process priority to medium-hight */
1516 if (ctx
->mem_idx
> 0) {
1517 /* Set process priority to high */
1522 if (ctx
->mem_idx
> 1) {
1523 /* Set process priority to very high */
1533 TCGv t0
= tcg_temp_new();
1534 gen_load_spr(t0
, SPR_PPR
);
1535 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1536 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1537 gen_store_spr(SPR_PPR
, t0
);
1544 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1546 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
)
1548 /* Optimisation for "set to zero" case */
1549 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1550 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1552 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1553 if (unlikely(Rc(ctx
->opcode
) != 0))
1554 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1557 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1559 target_ulong uimm
= UIMM(ctx
->opcode
);
1561 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1563 /* XXX: should handle special NOPs for POWER series */
1566 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1569 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1571 target_ulong uimm
= UIMM(ctx
->opcode
);
1573 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1577 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1580 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1582 target_ulong uimm
= UIMM(ctx
->opcode
);
1584 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1588 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1591 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1593 target_ulong uimm
= UIMM(ctx
->opcode
);
1595 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1599 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1601 /* popcntb : PowerPC 2.03 specification */
1602 GEN_HANDLER(popcntb
, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB
)
1604 #if defined(TARGET_PPC64)
1606 gen_helper_popcntb_64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1609 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1612 #if defined(TARGET_PPC64)
1613 /* extsw & extsw. */
1614 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1616 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
)
1618 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1619 if (unlikely(Rc(ctx
->opcode
) != 0))
1620 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1624 /*** Integer rotate ***/
1625 /* rlwimi & rlwimi. */
1626 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1628 uint32_t mb
, me
, sh
;
1630 mb
= MB(ctx
->opcode
);
1631 me
= ME(ctx
->opcode
);
1632 sh
= SH(ctx
->opcode
);
1633 if (likely(sh
== 0 && mb
== 0 && me
== 31)) {
1634 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1638 TCGv t0
= tcg_temp_new();
1639 #if defined(TARGET_PPC64)
1640 TCGv_i32 t2
= tcg_temp_new_i32();
1641 tcg_gen_trunc_i64_i32(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
1642 tcg_gen_rotli_i32(t2
, t2
, sh
);
1643 tcg_gen_extu_i32_i64(t0
, t2
);
1644 tcg_temp_free_i32(t2
);
1646 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1648 #if defined(TARGET_PPC64)
1652 mask
= MASK(mb
, me
);
1653 t1
= tcg_temp_new();
1654 tcg_gen_andi_tl(t0
, t0
, mask
);
1655 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1656 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1660 if (unlikely(Rc(ctx
->opcode
) != 0))
1661 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1663 /* rlwinm & rlwinm. */
1664 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1666 uint32_t mb
, me
, sh
;
1668 sh
= SH(ctx
->opcode
);
1669 mb
= MB(ctx
->opcode
);
1670 me
= ME(ctx
->opcode
);
1672 if (likely(mb
== 0 && me
== (31 - sh
))) {
1673 if (likely(sh
== 0)) {
1674 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1676 TCGv t0
= tcg_temp_new();
1677 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1678 tcg_gen_shli_tl(t0
, t0
, sh
);
1679 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1682 } else if (likely(sh
!= 0 && me
== 31 && sh
== (32 - mb
))) {
1683 TCGv t0
= tcg_temp_new();
1684 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1685 tcg_gen_shri_tl(t0
, t0
, mb
);
1686 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1689 TCGv t0
= tcg_temp_new();
1690 #if defined(TARGET_PPC64)
1691 TCGv_i32 t1
= tcg_temp_new_i32();
1692 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1693 tcg_gen_rotli_i32(t1
, t1
, sh
);
1694 tcg_gen_extu_i32_i64(t0
, t1
);
1695 tcg_temp_free_i32(t1
);
1697 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1699 #if defined(TARGET_PPC64)
1703 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1706 if (unlikely(Rc(ctx
->opcode
) != 0))
1707 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1709 /* rlwnm & rlwnm. */
1710 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1714 #if defined(TARGET_PPC64)
1718 mb
= MB(ctx
->opcode
);
1719 me
= ME(ctx
->opcode
);
1720 t0
= tcg_temp_new();
1721 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1722 #if defined(TARGET_PPC64)
1723 t1
= tcg_temp_new_i32();
1724 t2
= tcg_temp_new_i32();
1725 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1726 tcg_gen_trunc_i64_i32(t2
, t0
);
1727 tcg_gen_rotl_i32(t1
, t1
, t2
);
1728 tcg_gen_extu_i32_i64(t0
, t1
);
1729 tcg_temp_free_i32(t1
);
1730 tcg_temp_free_i32(t2
);
1732 tcg_gen_rotl_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1734 if (unlikely(mb
!= 0 || me
!= 31)) {
1735 #if defined(TARGET_PPC64)
1739 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1741 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1744 if (unlikely(Rc(ctx
->opcode
) != 0))
1745 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1748 #if defined(TARGET_PPC64)
1749 #define GEN_PPC64_R2(name, opc1, opc2) \
1750 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1752 gen_##name(ctx, 0); \
1754 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1757 gen_##name(ctx, 1); \
1759 #define GEN_PPC64_R4(name, opc1, opc2) \
1760 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1762 gen_##name(ctx, 0, 0); \
1764 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1767 gen_##name(ctx, 0, 1); \
1769 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1772 gen_##name(ctx, 1, 0); \
1774 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1777 gen_##name(ctx, 1, 1); \
1780 static always_inline
void gen_rldinm (DisasContext
*ctx
, uint32_t mb
,
1781 uint32_t me
, uint32_t sh
)
1783 if (likely(sh
!= 0 && mb
== 0 && me
== (63 - sh
))) {
1784 tcg_gen_shli_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
1785 } else if (likely(sh
!= 0 && me
== 63 && sh
== (64 - mb
))) {
1786 tcg_gen_shri_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], mb
);
1788 TCGv t0
= tcg_temp_new();
1789 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1790 if (likely(mb
== 0 && me
== 63)) {
1791 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1793 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1797 if (unlikely(Rc(ctx
->opcode
) != 0))
1798 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1800 /* rldicl - rldicl. */
1801 static always_inline
void gen_rldicl (DisasContext
*ctx
, int mbn
, int shn
)
1805 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1806 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1807 gen_rldinm(ctx
, mb
, 63, sh
);
1809 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1810 /* rldicr - rldicr. */
1811 static always_inline
void gen_rldicr (DisasContext
*ctx
, int men
, int shn
)
1815 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1816 me
= MB(ctx
->opcode
) | (men
<< 5);
1817 gen_rldinm(ctx
, 0, me
, sh
);
1819 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1820 /* rldic - rldic. */
1821 static always_inline
void gen_rldic (DisasContext
*ctx
, int mbn
, int shn
)
1825 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1826 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1827 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1829 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1831 static always_inline
void gen_rldnm (DisasContext
*ctx
, uint32_t mb
,
1836 mb
= MB(ctx
->opcode
);
1837 me
= ME(ctx
->opcode
);
1838 t0
= tcg_temp_new();
1839 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1840 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1841 if (unlikely(mb
!= 0 || me
!= 63)) {
1842 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1844 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1847 if (unlikely(Rc(ctx
->opcode
) != 0))
1848 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1851 /* rldcl - rldcl. */
1852 static always_inline
void gen_rldcl (DisasContext
*ctx
, int mbn
)
1856 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1857 gen_rldnm(ctx
, mb
, 63);
1859 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1860 /* rldcr - rldcr. */
1861 static always_inline
void gen_rldcr (DisasContext
*ctx
, int men
)
1865 me
= MB(ctx
->opcode
) | (men
<< 5);
1866 gen_rldnm(ctx
, 0, me
);
1868 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1869 /* rldimi - rldimi. */
1870 static always_inline
void gen_rldimi (DisasContext
*ctx
, int mbn
, int shn
)
1872 uint32_t sh
, mb
, me
;
1874 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1875 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1877 if (unlikely(sh
== 0 && mb
== 0)) {
1878 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1883 t0
= tcg_temp_new();
1884 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1885 t1
= tcg_temp_new();
1886 mask
= MASK(mb
, me
);
1887 tcg_gen_andi_tl(t0
, t0
, mask
);
1888 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1889 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1893 if (unlikely(Rc(ctx
->opcode
) != 0))
1894 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1896 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1899 /*** Integer shift ***/
1901 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
)
1905 l1
= gen_new_label();
1906 l2
= gen_new_label();
1908 t0
= tcg_temp_local_new();
1909 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1910 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0x20, l1
);
1911 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1914 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t0
);
1915 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1918 if (unlikely(Rc(ctx
->opcode
) != 0))
1919 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1922 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
)
1924 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)],
1925 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1926 if (unlikely(Rc(ctx
->opcode
) != 0))
1927 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1929 /* srawi & srawi. */
1930 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
)
1932 int sh
= SH(ctx
->opcode
);
1936 l1
= gen_new_label();
1937 l2
= gen_new_label();
1938 t0
= tcg_temp_local_new();
1939 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1940 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
1941 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1ULL << sh
) - 1);
1942 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1943 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
1946 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1948 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1949 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, sh
);
1952 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1953 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1955 if (unlikely(Rc(ctx
->opcode
) != 0))
1956 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1959 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
)
1963 l1
= gen_new_label();
1964 l2
= gen_new_label();
1966 t0
= tcg_temp_local_new();
1967 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1968 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0x20, l1
);
1969 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1972 t1
= tcg_temp_new();
1973 tcg_gen_ext32u_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1974 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
, t0
);
1978 if (unlikely(Rc(ctx
->opcode
) != 0))
1979 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1981 #if defined(TARGET_PPC64)
1983 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
)
1987 l1
= gen_new_label();
1988 l2
= gen_new_label();
1990 t0
= tcg_temp_local_new();
1991 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x7f);
1992 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0x40, l1
);
1993 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1996 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t0
);
1999 if (unlikely(Rc(ctx
->opcode
) != 0))
2000 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2003 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
)
2005 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)],
2006 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2007 if (unlikely(Rc(ctx
->opcode
) != 0))
2008 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2010 /* sradi & sradi. */
2011 static always_inline
void gen_sradi (DisasContext
*ctx
, int n
)
2013 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2017 l1
= gen_new_label();
2018 l2
= gen_new_label();
2019 t0
= tcg_temp_local_new();
2020 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
2021 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1ULL << sh
) - 1);
2022 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2023 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
2026 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
2029 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
2031 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
2032 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
2034 if (unlikely(Rc(ctx
->opcode
) != 0))
2035 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2037 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
)
2041 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
)
2046 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
)
2050 l1
= gen_new_label();
2051 l2
= gen_new_label();
2053 t0
= tcg_temp_local_new();
2054 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x7f);
2055 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0x40, l1
);
2056 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
2059 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t0
);
2062 if (unlikely(Rc(ctx
->opcode
) != 0))
2063 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2067 /*** Floating-Point arithmetic ***/
2068 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2069 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2071 if (unlikely(!ctx->fpu_enabled)) { \
2072 gen_exception(ctx, POWERPC_EXCP_FPU); \
2075 gen_reset_fpstatus(); \
2076 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2077 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2079 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2081 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2082 Rc(ctx->opcode) != 0); \
2085 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2086 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2087 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2089 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2090 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2092 if (unlikely(!ctx->fpu_enabled)) { \
2093 gen_exception(ctx, POWERPC_EXCP_FPU); \
2096 gen_reset_fpstatus(); \
2097 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2098 cpu_fpr[rB(ctx->opcode)]); \
2100 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2102 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2103 set_fprf, Rc(ctx->opcode) != 0); \
2105 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2106 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2107 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2109 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2110 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2112 if (unlikely(!ctx->fpu_enabled)) { \
2113 gen_exception(ctx, POWERPC_EXCP_FPU); \
2116 gen_reset_fpstatus(); \
2117 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2118 cpu_fpr[rC(ctx->opcode)]); \
2120 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2122 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2123 set_fprf, Rc(ctx->opcode) != 0); \
2125 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2126 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2127 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2129 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2130 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2132 if (unlikely(!ctx->fpu_enabled)) { \
2133 gen_exception(ctx, POWERPC_EXCP_FPU); \
2136 gen_reset_fpstatus(); \
2137 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2138 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2139 set_fprf, Rc(ctx->opcode) != 0); \
2142 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2143 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2145 if (unlikely(!ctx->fpu_enabled)) { \
2146 gen_exception(ctx, POWERPC_EXCP_FPU); \
2149 gen_reset_fpstatus(); \
2150 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2151 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2152 set_fprf, Rc(ctx->opcode) != 0); \
2156 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
2158 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
2160 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
2163 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
2166 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
2169 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
2172 GEN_HANDLER(frsqrtes
, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES
)
2174 if (unlikely(!ctx
->fpu_enabled
)) {
2175 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2178 gen_reset_fpstatus();
2179 gen_helper_frsqrte(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2180 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rD(ctx
->opcode
)]);
2181 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2185 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
2187 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
2190 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
)
2192 if (unlikely(!ctx
->fpu_enabled
)) {
2193 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2196 gen_reset_fpstatus();
2197 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2198 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2201 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
)
2203 if (unlikely(!ctx
->fpu_enabled
)) {
2204 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2207 gen_reset_fpstatus();
2208 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2209 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rD(ctx
->opcode
)]);
2210 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2213 /*** Floating-Point multiply-and-add ***/
2214 /* fmadd - fmadds */
2215 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
2216 /* fmsub - fmsubs */
2217 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
2218 /* fnmadd - fnmadds */
2219 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
2220 /* fnmsub - fnmsubs */
2221 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
2223 /*** Floating-Point round & convert ***/
2225 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
2227 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
2229 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
2230 #if defined(TARGET_PPC64)
2232 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
);
2234 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
);
2236 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
);
2240 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
2242 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
2244 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
2246 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
2248 /*** Floating-Point compare ***/
2250 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
)
2253 if (unlikely(!ctx
->fpu_enabled
)) {
2254 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2257 gen_reset_fpstatus();
2258 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2259 gen_helper_fcmpo(cpu_fpr
[rA(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)], crf
);
2261 gen_helper_float_check_status();
2265 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
)
2268 if (unlikely(!ctx
->fpu_enabled
)) {
2269 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2272 gen_reset_fpstatus();
2273 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2274 gen_helper_fcmpu(cpu_fpr
[rA(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)], crf
);
2276 gen_helper_float_check_status();
2279 /*** Floating-point move ***/
2281 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2282 GEN_FLOAT_B(abs
, 0x08, 0x08, 0, PPC_FLOAT
);
2285 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2286 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
)
2288 if (unlikely(!ctx
->fpu_enabled
)) {
2289 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2292 tcg_gen_mov_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2293 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2297 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2298 GEN_FLOAT_B(nabs
, 0x08, 0x04, 0, PPC_FLOAT
);
2300 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2301 GEN_FLOAT_B(neg
, 0x08, 0x01, 0, PPC_FLOAT
);
2303 /*** Floating-Point status & ctrl register ***/
2305 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
)
2309 if (unlikely(!ctx
->fpu_enabled
)) {
2310 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2313 bfa
= 4 * (7 - crfS(ctx
->opcode
));
2314 tcg_gen_shri_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_fpscr
, bfa
);
2315 tcg_gen_andi_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], 0xf);
2316 tcg_gen_andi_i32(cpu_fpscr
, cpu_fpscr
, ~(0xF << bfa
));
2320 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
)
2322 if (unlikely(!ctx
->fpu_enabled
)) {
2323 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2326 gen_reset_fpstatus();
2327 tcg_gen_extu_i32_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpscr
);
2328 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2332 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
)
2336 if (unlikely(!ctx
->fpu_enabled
)) {
2337 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2340 crb
= 31 - crbD(ctx
->opcode
);
2341 gen_reset_fpstatus();
2342 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
)) {
2343 TCGv_i32 t0
= tcg_const_i32(crb
);
2344 gen_helper_fpscr_clrbit(t0
);
2345 tcg_temp_free_i32(t0
);
2347 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2348 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2353 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
)
2357 if (unlikely(!ctx
->fpu_enabled
)) {
2358 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2361 crb
= 31 - crbD(ctx
->opcode
);
2362 gen_reset_fpstatus();
2363 /* XXX: we pretend we can only do IEEE floating-point computations */
2364 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
)) {
2365 TCGv_i32 t0
= tcg_const_i32(crb
);
2366 gen_helper_fpscr_setbit(t0
);
2367 tcg_temp_free_i32(t0
);
2369 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2370 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2372 /* We can raise a differed exception */
2373 gen_helper_float_check_status();
2377 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT
)
2381 if (unlikely(!ctx
->fpu_enabled
)) {
2382 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2385 gen_reset_fpstatus();
2386 t0
= tcg_const_i32(FM(ctx
->opcode
));
2387 gen_helper_store_fpscr(cpu_fpr
[rB(ctx
->opcode
)], t0
);
2388 tcg_temp_free_i32(t0
);
2389 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2390 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2392 /* We can raise a differed exception */
2393 gen_helper_float_check_status();
2397 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT
)
2403 if (unlikely(!ctx
->fpu_enabled
)) {
2404 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2407 bf
= crbD(ctx
->opcode
) >> 2;
2409 gen_reset_fpstatus();
2410 t0
= tcg_const_i64(FPIMM(ctx
->opcode
) << (4 * sh
));
2411 t1
= tcg_const_i32(1 << sh
);
2412 gen_helper_store_fpscr(t0
, t1
);
2413 tcg_temp_free_i64(t0
);
2414 tcg_temp_free_i32(t1
);
2415 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2416 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2418 /* We can raise a differed exception */
2419 gen_helper_float_check_status();
2422 /*** Addressing modes ***/
2423 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2424 static always_inline
void gen_addr_imm_index (DisasContext
*ctx
, TCGv EA
, target_long maskl
)
2426 target_long simm
= SIMM(ctx
->opcode
);
2429 if (rA(ctx
->opcode
) == 0) {
2430 #if defined(TARGET_PPC64)
2431 if (!ctx
->sf_mode
) {
2432 tcg_gen_movi_tl(EA
, (uint32_t)simm
);
2435 tcg_gen_movi_tl(EA
, simm
);
2436 } else if (likely(simm
!= 0)) {
2437 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2438 #if defined(TARGET_PPC64)
2439 if (!ctx
->sf_mode
) {
2440 tcg_gen_ext32u_tl(EA
, EA
);
2444 #if defined(TARGET_PPC64)
2445 if (!ctx
->sf_mode
) {
2446 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2449 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2453 static always_inline
void gen_addr_reg_index (DisasContext
*ctx
, TCGv EA
)
2455 if (rA(ctx
->opcode
) == 0) {
2456 #if defined(TARGET_PPC64)
2457 if (!ctx
->sf_mode
) {
2458 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2461 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2463 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2464 #if defined(TARGET_PPC64)
2465 if (!ctx
->sf_mode
) {
2466 tcg_gen_ext32u_tl(EA
, EA
);
2472 static always_inline
void gen_addr_register (DisasContext
*ctx
, TCGv EA
)
2474 if (rA(ctx
->opcode
) == 0) {
2475 tcg_gen_movi_tl(EA
, 0);
2477 #if defined(TARGET_PPC64)
2478 if (!ctx
->sf_mode
) {
2479 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2482 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2486 static always_inline
void gen_addr_add (DisasContext
*ctx
, TCGv ret
, TCGv arg1
, target_long val
)
2488 tcg_gen_addi_tl(ret
, arg1
, val
);
2489 #if defined(TARGET_PPC64)
2490 if (!ctx
->sf_mode
) {
2491 tcg_gen_ext32u_tl(ret
, ret
);
2496 static always_inline
void gen_check_align (DisasContext
*ctx
, TCGv EA
, int mask
)
2498 int l1
= gen_new_label();
2499 TCGv t0
= tcg_temp_new();
2501 /* NIP cannot be restored if the memory exception comes from an helper */
2502 gen_update_nip(ctx
, ctx
->nip
- 4);
2503 tcg_gen_andi_tl(t0
, EA
, mask
);
2504 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2505 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2506 t2
= tcg_const_i32(0);
2507 gen_helper_raise_exception_err(t1
, t2
);
2508 tcg_temp_free_i32(t1
);
2509 tcg_temp_free_i32(t2
);
2514 /*** Integer load ***/
2515 static always_inline
void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2517 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2520 static always_inline
void gen_qemu_ld8s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2522 tcg_gen_qemu_ld8s(arg1
, arg2
, ctx
->mem_idx
);
2525 static always_inline
void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2527 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2528 if (unlikely(ctx
->le_mode
)) {
2529 #if defined(TARGET_PPC64)
2530 TCGv_i32 t0
= tcg_temp_new_i32();
2531 tcg_gen_trunc_tl_i32(t0
, arg1
);
2532 tcg_gen_bswap16_i32(t0
, t0
);
2533 tcg_gen_extu_i32_tl(arg1
, t0
);
2534 tcg_temp_free_i32(t0
);
2536 tcg_gen_bswap16_i32(arg1
, arg1
);
2541 static always_inline
void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2543 if (unlikely(ctx
->le_mode
)) {
2544 #if defined(TARGET_PPC64)
2546 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2547 t0
= tcg_temp_new_i32();
2548 tcg_gen_trunc_tl_i32(t0
, arg1
);
2549 tcg_gen_bswap16_i32(t0
, t0
);
2550 tcg_gen_extu_i32_tl(arg1
, t0
);
2551 tcg_gen_ext16s_tl(arg1
, arg1
);
2552 tcg_temp_free_i32(t0
);
2554 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2555 tcg_gen_bswap16_i32(arg1
, arg1
);
2556 tcg_gen_ext16s_i32(arg1
, arg1
);
2559 tcg_gen_qemu_ld16s(arg1
, arg2
, ctx
->mem_idx
);
2563 static always_inline
void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2565 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2566 if (unlikely(ctx
->le_mode
)) {
2567 #if defined(TARGET_PPC64)
2568 TCGv_i32 t0
= tcg_temp_new_i32();
2569 tcg_gen_trunc_tl_i32(t0
, arg1
);
2570 tcg_gen_bswap_i32(t0
, t0
);
2571 tcg_gen_extu_i32_tl(arg1
, t0
);
2572 tcg_temp_free_i32(t0
);
2574 tcg_gen_bswap_i32(arg1
, arg1
);
2579 #if defined(TARGET_PPC64)
2580 static always_inline
void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2582 if (unlikely(ctx
->mem_idx
)) {
2584 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2585 t0
= tcg_temp_new_i32();
2586 tcg_gen_trunc_tl_i32(t0
, arg1
);
2587 tcg_gen_bswap_i32(t0
, t0
);
2588 tcg_gen_ext_i32_tl(arg1
, t0
);
2589 tcg_temp_free_i32(t0
);
2591 tcg_gen_qemu_ld32s(arg1
, arg2
, ctx
->mem_idx
);
2595 static always_inline
void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2597 tcg_gen_qemu_ld64(arg1
, arg2
, ctx
->mem_idx
);
2598 if (unlikely(ctx
->le_mode
)) {
2599 tcg_gen_bswap_i64(arg1
, arg1
);
2603 static always_inline
void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2605 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2608 static always_inline
void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2610 if (unlikely(ctx
->le_mode
)) {
2611 #if defined(TARGET_PPC64)
2614 t0
= tcg_temp_new_i32();
2615 tcg_gen_trunc_tl_i32(t0
, arg1
);
2616 tcg_gen_ext16u_i32(t0
, t0
);
2617 tcg_gen_bswap16_i32(t0
, t0
);
2618 t1
= tcg_temp_new();
2619 tcg_gen_extu_i32_tl(t1
, t0
);
2620 tcg_temp_free_i32(t0
);
2621 tcg_gen_qemu_st16(t1
, arg2
, ctx
->mem_idx
);
2624 TCGv t0
= tcg_temp_new();
2625 tcg_gen_ext16u_tl(t0
, arg1
);
2626 tcg_gen_bswap16_i32(t0
, t0
);
2627 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2631 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
2635 static always_inline
void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2637 if (unlikely(ctx
->le_mode
)) {
2638 #if defined(TARGET_PPC64)
2641 t0
= tcg_temp_new_i32();
2642 tcg_gen_trunc_tl_i32(t0
, arg1
);
2643 tcg_gen_bswap_i32(t0
, t0
);
2644 t1
= tcg_temp_new();
2645 tcg_gen_extu_i32_tl(t1
, t0
);
2646 tcg_temp_free_i32(t0
);
2647 tcg_gen_qemu_st32(t1
, arg2
, ctx
->mem_idx
);
2650 TCGv t0
= tcg_temp_new_i32();
2651 tcg_gen_bswap_i32(t0
, arg1
);
2652 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
2656 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
2660 static always_inline
void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2662 if (unlikely(ctx
->le_mode
)) {
2663 TCGv_i64 t0
= tcg_temp_new_i64();
2664 tcg_gen_bswap_i64(t0
, arg1
);
2665 tcg_gen_qemu_st64(t0
, arg2
, ctx
->mem_idx
);
2666 tcg_temp_free_i64(t0
);
2668 tcg_gen_qemu_st64(arg1
, arg2
, ctx
->mem_idx
);
2671 #define GEN_LD(name, ldop, opc, type) \
2672 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2675 gen_set_access_type(ctx, ACCESS_INT); \
2676 EA = tcg_temp_new(); \
2677 gen_addr_imm_index(ctx, EA, 0); \
2678 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2679 tcg_temp_free(EA); \
2682 #define GEN_LDU(name, ldop, opc, type) \
2683 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2686 if (unlikely(rA(ctx->opcode) == 0 || \
2687 rA(ctx->opcode) == rD(ctx->opcode))) { \
2688 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2691 gen_set_access_type(ctx, ACCESS_INT); \
2692 EA = tcg_temp_new(); \
2693 if (type == PPC_64B) \
2694 gen_addr_imm_index(ctx, EA, 0x03); \
2696 gen_addr_imm_index(ctx, EA, 0); \
2697 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2698 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2699 tcg_temp_free(EA); \
2702 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2703 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2706 if (unlikely(rA(ctx->opcode) == 0 || \
2707 rA(ctx->opcode) == rD(ctx->opcode))) { \
2708 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2711 gen_set_access_type(ctx, ACCESS_INT); \
2712 EA = tcg_temp_new(); \
2713 gen_addr_reg_index(ctx, EA); \
2714 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2715 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2716 tcg_temp_free(EA); \
2719 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2720 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2723 gen_set_access_type(ctx, ACCESS_INT); \
2724 EA = tcg_temp_new(); \
2725 gen_addr_reg_index(ctx, EA); \
2726 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2727 tcg_temp_free(EA); \
2730 #define GEN_LDS(name, ldop, op, type) \
2731 GEN_LD(name, ldop, op | 0x20, type); \
2732 GEN_LDU(name, ldop, op | 0x21, type); \
2733 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2734 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2736 /* lbz lbzu lbzux lbzx */
2737 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2738 /* lha lhau lhaux lhax */
2739 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2740 /* lhz lhzu lhzux lhzx */
2741 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2742 /* lwz lwzu lwzux lwzx */
2743 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2744 #if defined(TARGET_PPC64)
2746 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2748 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2750 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2752 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2753 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
)
2756 if (Rc(ctx
->opcode
)) {
2757 if (unlikely(rA(ctx
->opcode
) == 0 ||
2758 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2759 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2763 gen_set_access_type(ctx
, ACCESS_INT
);
2764 EA
= tcg_temp_new();
2765 gen_addr_imm_index(ctx
, EA
, 0x03);
2766 if (ctx
->opcode
& 0x02) {
2767 /* lwa (lwau is undefined) */
2768 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2771 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2773 if (Rc(ctx
->opcode
))
2774 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2778 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
)
2780 #if defined(CONFIG_USER_ONLY)
2781 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2786 /* Restore CPU state */
2787 if (unlikely(ctx
->mem_idx
== 0)) {
2788 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2791 ra
= rA(ctx
->opcode
);
2792 rd
= rD(ctx
->opcode
);
2793 if (unlikely((rd
& 1) || rd
== ra
)) {
2794 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2797 if (unlikely(ctx
->le_mode
)) {
2798 /* Little-endian mode is not handled */
2799 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2802 gen_set_access_type(ctx
, ACCESS_INT
);
2803 EA
= tcg_temp_new();
2804 gen_addr_imm_index(ctx
, EA
, 0x0F);
2805 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2806 gen_addr_add(ctx
, EA
, EA
, 8);
2807 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2813 /*** Integer store ***/
2814 #define GEN_ST(name, stop, opc, type) \
2815 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2818 gen_set_access_type(ctx, ACCESS_INT); \
2819 EA = tcg_temp_new(); \
2820 gen_addr_imm_index(ctx, EA, 0); \
2821 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2822 tcg_temp_free(EA); \
2825 #define GEN_STU(name, stop, opc, type) \
2826 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2829 if (unlikely(rA(ctx->opcode) == 0)) { \
2830 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2833 gen_set_access_type(ctx, ACCESS_INT); \
2834 EA = tcg_temp_new(); \
2835 if (type == PPC_64B) \
2836 gen_addr_imm_index(ctx, EA, 0x03); \
2838 gen_addr_imm_index(ctx, EA, 0); \
2839 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2840 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2841 tcg_temp_free(EA); \
2844 #define GEN_STUX(name, stop, opc2, opc3, type) \
2845 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2848 if (unlikely(rA(ctx->opcode) == 0)) { \
2849 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2852 gen_set_access_type(ctx, ACCESS_INT); \
2853 EA = tcg_temp_new(); \
2854 gen_addr_reg_index(ctx, EA); \
2855 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2856 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2857 tcg_temp_free(EA); \
2860 #define GEN_STX(name, stop, opc2, opc3, type) \
2861 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2864 gen_set_access_type(ctx, ACCESS_INT); \
2865 EA = tcg_temp_new(); \
2866 gen_addr_reg_index(ctx, EA); \
2867 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2868 tcg_temp_free(EA); \
2871 #define GEN_STS(name, stop, op, type) \
2872 GEN_ST(name, stop, op | 0x20, type); \
2873 GEN_STU(name, stop, op | 0x21, type); \
2874 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2875 GEN_STX(name, stop, 0x17, op | 0x00, type)
2877 /* stb stbu stbux stbx */
2878 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2879 /* sth sthu sthux sthx */
2880 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2881 /* stw stwu stwux stwx */
2882 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2883 #if defined(TARGET_PPC64)
2884 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
2885 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
2886 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
)
2891 rs
= rS(ctx
->opcode
);
2892 if ((ctx
->opcode
& 0x3) == 0x2) {
2893 #if defined(CONFIG_USER_ONLY)
2894 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2897 if (unlikely(ctx
->mem_idx
== 0)) {
2898 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2901 if (unlikely(rs
& 1)) {
2902 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2905 if (unlikely(ctx
->le_mode
)) {
2906 /* Little-endian mode is not handled */
2907 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2910 gen_set_access_type(ctx
, ACCESS_INT
);
2911 EA
= tcg_temp_new();
2912 gen_addr_imm_index(ctx
, EA
, 0x03);
2913 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2914 gen_addr_add(ctx
, EA
, EA
, 8);
2915 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
2920 if (Rc(ctx
->opcode
)) {
2921 if (unlikely(rA(ctx
->opcode
) == 0)) {
2922 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2926 gen_set_access_type(ctx
, ACCESS_INT
);
2927 EA
= tcg_temp_new();
2928 gen_addr_imm_index(ctx
, EA
, 0x03);
2929 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2930 if (Rc(ctx
->opcode
))
2931 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2936 /*** Integer load and store with byte reverse ***/
2938 static void always_inline
gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2940 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2941 if (likely(!ctx
->le_mode
)) {
2942 #if defined(TARGET_PPC64)
2943 TCGv_i32 t0
= tcg_temp_new_i32();
2944 tcg_gen_trunc_tl_i32(t0
, arg1
);
2945 tcg_gen_bswap16_i32(t0
, t0
);
2946 tcg_gen_extu_i32_tl(arg1
, t0
);
2947 tcg_temp_free_i32(t0
);
2949 tcg_gen_bswap16_i32(arg1
, arg1
);
2953 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2956 static void always_inline
gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2958 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2959 if (likely(!ctx
->le_mode
)) {
2960 #if defined(TARGET_PPC64)
2961 TCGv_i32 t0
= tcg_temp_new_i32();
2962 tcg_gen_trunc_tl_i32(t0
, arg1
);
2963 tcg_gen_bswap_i32(t0
, t0
);
2964 tcg_gen_extu_i32_tl(arg1
, t0
);
2965 tcg_temp_free_i32(t0
);
2967 tcg_gen_bswap_i32(arg1
, arg1
);
2971 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2974 static void always_inline
gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2976 if (likely(!ctx
->le_mode
)) {
2977 #if defined(TARGET_PPC64)
2980 t0
= tcg_temp_new_i32();
2981 tcg_gen_trunc_tl_i32(t0
, arg1
);
2982 tcg_gen_ext16u_i32(t0
, t0
);
2983 tcg_gen_bswap16_i32(t0
, t0
);
2984 t1
= tcg_temp_new();
2985 tcg_gen_extu_i32_tl(t1
, t0
);
2986 tcg_temp_free_i32(t0
);
2987 tcg_gen_qemu_st16(t1
, arg2
, ctx
->mem_idx
);
2990 TCGv t0
= tcg_temp_new();
2991 tcg_gen_ext16u_tl(t0
, arg1
);
2992 tcg_gen_bswap16_i32(t0
, t0
);
2993 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2997 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
3000 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
3003 static void always_inline
gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3005 if (likely(!ctx
->le_mode
)) {
3006 #if defined(TARGET_PPC64)
3009 t0
= tcg_temp_new_i32();
3010 tcg_gen_trunc_tl_i32(t0
, arg1
);
3011 tcg_gen_bswap_i32(t0
, t0
);
3012 t1
= tcg_temp_new();
3013 tcg_gen_extu_i32_tl(t1
, t0
);
3014 tcg_temp_free_i32(t0
);
3015 tcg_gen_qemu_st32(t1
, arg2
, ctx
->mem_idx
);
3018 TCGv t0
= tcg_temp_new_i32();
3019 tcg_gen_bswap_i32(t0
, arg1
);
3020 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
3024 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
3027 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
3029 /*** Integer load and store multiple ***/
3031 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
3035 gen_set_access_type(ctx
, ACCESS_INT
);
3036 /* NIP cannot be restored if the memory exception comes from an helper */
3037 gen_update_nip(ctx
, ctx
->nip
- 4);
3038 t0
= tcg_temp_new();
3039 t1
= tcg_const_i32(rD(ctx
->opcode
));
3040 gen_addr_imm_index(ctx
, t0
, 0);
3041 gen_helper_lmw(t0
, t1
);
3043 tcg_temp_free_i32(t1
);
3047 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
3051 gen_set_access_type(ctx
, ACCESS_INT
);
3052 /* NIP cannot be restored if the memory exception comes from an helper */
3053 gen_update_nip(ctx
, ctx
->nip
- 4);
3054 t0
= tcg_temp_new();
3055 t1
= tcg_const_i32(rS(ctx
->opcode
));
3056 gen_addr_imm_index(ctx
, t0
, 0);
3057 gen_helper_stmw(t0
, t1
);
3059 tcg_temp_free_i32(t1
);
3062 /*** Integer load and store strings ***/
3064 /* PowerPC32 specification says we must generate an exception if
3065 * rA is in the range of registers to be loaded.
3066 * In an other hand, IBM says this is valid, but rA won't be loaded.
3067 * For now, I'll follow the spec...
3069 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
)
3073 int nb
= NB(ctx
->opcode
);
3074 int start
= rD(ctx
->opcode
);
3075 int ra
= rA(ctx
->opcode
);
3081 if (unlikely(((start
+ nr
) > 32 &&
3082 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
3083 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
3084 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
3087 gen_set_access_type(ctx
, ACCESS_INT
);
3088 /* NIP cannot be restored if the memory exception comes from an helper */
3089 gen_update_nip(ctx
, ctx
->nip
- 4);
3090 t0
= tcg_temp_new();
3091 gen_addr_register(ctx
, t0
);
3092 t1
= tcg_const_i32(nb
);
3093 t2
= tcg_const_i32(start
);
3094 gen_helper_lsw(t0
, t1
, t2
);
3096 tcg_temp_free_i32(t1
);
3097 tcg_temp_free_i32(t2
);
3101 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
)
3104 TCGv_i32 t1
, t2
, t3
;
3105 gen_set_access_type(ctx
, ACCESS_INT
);
3106 /* NIP cannot be restored if the memory exception comes from an helper */
3107 gen_update_nip(ctx
, ctx
->nip
- 4);
3108 t0
= tcg_temp_new();
3109 gen_addr_reg_index(ctx
, t0
);
3110 t1
= tcg_const_i32(rD(ctx
->opcode
));
3111 t2
= tcg_const_i32(rA(ctx
->opcode
));
3112 t3
= tcg_const_i32(rB(ctx
->opcode
));
3113 gen_helper_lswx(t0
, t1
, t2
, t3
);
3115 tcg_temp_free_i32(t1
);
3116 tcg_temp_free_i32(t2
);
3117 tcg_temp_free_i32(t3
);
3121 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
)
3125 int nb
= NB(ctx
->opcode
);
3126 gen_set_access_type(ctx
, ACCESS_INT
);
3127 /* NIP cannot be restored if the memory exception comes from an helper */
3128 gen_update_nip(ctx
, ctx
->nip
- 4);
3129 t0
= tcg_temp_new();
3130 gen_addr_register(ctx
, t0
);
3133 t1
= tcg_const_i32(nb
);
3134 t2
= tcg_const_i32(rS(ctx
->opcode
));
3135 gen_helper_stsw(t0
, t1
, t2
);
3137 tcg_temp_free_i32(t1
);
3138 tcg_temp_free_i32(t2
);
3142 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
)
3146 gen_set_access_type(ctx
, ACCESS_INT
);
3147 /* NIP cannot be restored if the memory exception comes from an helper */
3148 gen_update_nip(ctx
, ctx
->nip
- 4);
3149 t0
= tcg_temp_new();
3150 gen_addr_reg_index(ctx
, t0
);
3151 t1
= tcg_temp_new_i32();
3152 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3153 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3154 t2
= tcg_const_i32(rS(ctx
->opcode
));
3155 gen_helper_stsw(t0
, t1
, t2
);
3157 tcg_temp_free_i32(t1
);
3158 tcg_temp_free_i32(t2
);
3161 /*** Memory synchronisation ***/
3163 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
)
3168 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
)
3170 gen_stop_exception(ctx
);
3174 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES
)
3177 gen_set_access_type(ctx
, ACCESS_RES
);
3178 t0
= tcg_temp_local_new();
3179 gen_addr_reg_index(ctx
, t0
);
3180 gen_check_align(ctx
, t0
, 0x03);
3181 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
3182 tcg_gen_mov_tl(cpu_reserve
, t0
);
3187 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
)
3191 gen_set_access_type(ctx
, ACCESS_RES
);
3192 t0
= tcg_temp_local_new();
3193 gen_addr_reg_index(ctx
, t0
);
3194 gen_check_align(ctx
, t0
, 0x03);
3195 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
3196 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
3197 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
3198 l1
= gen_new_label();
3199 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3200 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3201 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3203 tcg_gen_movi_tl(cpu_reserve
, -1);
3207 #if defined(TARGET_PPC64)
3209 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B
)
3212 gen_set_access_type(ctx
, ACCESS_RES
);
3213 t0
= tcg_temp_local_new();
3214 gen_addr_reg_index(ctx
, t0
);
3215 gen_check_align(ctx
, t0
, 0x07);
3216 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
3217 tcg_gen_mov_tl(cpu_reserve
, t0
);
3222 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
)
3226 gen_set_access_type(ctx
, ACCESS_RES
);
3227 t0
= tcg_temp_local_new();
3228 gen_addr_reg_index(ctx
, t0
);
3229 gen_check_align(ctx
, t0
, 0x07);
3230 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
3231 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
3232 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
3233 l1
= gen_new_label();
3234 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3235 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3236 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3238 tcg_gen_movi_tl(cpu_reserve
, -1);
3241 #endif /* defined(TARGET_PPC64) */
3244 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
)
3249 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
)
3251 TCGv_i32 t0
= tcg_temp_new_i32();
3252 tcg_gen_st_i32(t0
, cpu_env
, offsetof(CPUState
, halted
));
3253 tcg_temp_free_i32(t0
);
3254 /* Stop translation, as the CPU is supposed to sleep from now */
3255 gen_exception_err(ctx
, EXCP_HLT
, 1);
3258 /*** Floating-point load ***/
3259 #define GEN_LDF(name, ldop, opc, type) \
3260 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3263 if (unlikely(!ctx->fpu_enabled)) { \
3264 gen_exception(ctx, POWERPC_EXCP_FPU); \
3267 gen_set_access_type(ctx, ACCESS_FLOAT); \
3268 EA = tcg_temp_new(); \
3269 gen_addr_imm_index(ctx, EA, 0); \
3270 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3271 tcg_temp_free(EA); \
3274 #define GEN_LDUF(name, ldop, opc, type) \
3275 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3278 if (unlikely(!ctx->fpu_enabled)) { \
3279 gen_exception(ctx, POWERPC_EXCP_FPU); \
3282 if (unlikely(rA(ctx->opcode) == 0)) { \
3283 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3286 gen_set_access_type(ctx, ACCESS_FLOAT); \
3287 EA = tcg_temp_new(); \
3288 gen_addr_imm_index(ctx, EA, 0); \
3289 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3290 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3291 tcg_temp_free(EA); \
3294 #define GEN_LDUXF(name, ldop, opc, type) \
3295 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3298 if (unlikely(!ctx->fpu_enabled)) { \
3299 gen_exception(ctx, POWERPC_EXCP_FPU); \
3302 if (unlikely(rA(ctx->opcode) == 0)) { \
3303 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3306 gen_set_access_type(ctx, ACCESS_FLOAT); \
3307 EA = tcg_temp_new(); \
3308 gen_addr_reg_index(ctx, EA); \
3309 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3310 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3311 tcg_temp_free(EA); \
3314 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3315 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3318 if (unlikely(!ctx->fpu_enabled)) { \
3319 gen_exception(ctx, POWERPC_EXCP_FPU); \
3322 gen_set_access_type(ctx, ACCESS_FLOAT); \
3323 EA = tcg_temp_new(); \
3324 gen_addr_reg_index(ctx, EA); \
3325 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3326 tcg_temp_free(EA); \
3329 #define GEN_LDFS(name, ldop, op, type) \
3330 GEN_LDF(name, ldop, op | 0x20, type); \
3331 GEN_LDUF(name, ldop, op | 0x21, type); \
3332 GEN_LDUXF(name, ldop, op | 0x01, type); \
3333 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3335 static always_inline
void gen_qemu_ld32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3337 TCGv t0
= tcg_temp_new();
3338 TCGv_i32 t1
= tcg_temp_new_i32();
3339 gen_qemu_ld32u(ctx
, t0
, arg2
);
3340 tcg_gen_trunc_tl_i32(t1
, t0
);
3342 gen_helper_float32_to_float64(arg1
, t1
);
3343 tcg_temp_free_i32(t1
);
3346 /* lfd lfdu lfdux lfdx */
3347 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
);
3348 /* lfs lfsu lfsux lfsx */
3349 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
);
3351 /*** Floating-point store ***/
3352 #define GEN_STF(name, stop, opc, type) \
3353 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3356 if (unlikely(!ctx->fpu_enabled)) { \
3357 gen_exception(ctx, POWERPC_EXCP_FPU); \
3360 gen_set_access_type(ctx, ACCESS_FLOAT); \
3361 EA = tcg_temp_new(); \
3362 gen_addr_imm_index(ctx, EA, 0); \
3363 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3364 tcg_temp_free(EA); \
3367 #define GEN_STUF(name, stop, opc, type) \
3368 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3371 if (unlikely(!ctx->fpu_enabled)) { \
3372 gen_exception(ctx, POWERPC_EXCP_FPU); \
3375 if (unlikely(rA(ctx->opcode) == 0)) { \
3376 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3379 gen_set_access_type(ctx, ACCESS_FLOAT); \
3380 EA = tcg_temp_new(); \
3381 gen_addr_imm_index(ctx, EA, 0); \
3382 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3383 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3384 tcg_temp_free(EA); \
3387 #define GEN_STUXF(name, stop, opc, type) \
3388 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3391 if (unlikely(!ctx->fpu_enabled)) { \
3392 gen_exception(ctx, POWERPC_EXCP_FPU); \
3395 if (unlikely(rA(ctx->opcode) == 0)) { \
3396 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3399 gen_set_access_type(ctx, ACCESS_FLOAT); \
3400 EA = tcg_temp_new(); \
3401 gen_addr_reg_index(ctx, EA); \
3402 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3403 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3404 tcg_temp_free(EA); \
3407 #define GEN_STXF(name, stop, opc2, opc3, type) \
3408 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3411 if (unlikely(!ctx->fpu_enabled)) { \
3412 gen_exception(ctx, POWERPC_EXCP_FPU); \
3415 gen_set_access_type(ctx, ACCESS_FLOAT); \
3416 EA = tcg_temp_new(); \
3417 gen_addr_reg_index(ctx, EA); \
3418 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3419 tcg_temp_free(EA); \
3422 #define GEN_STFS(name, stop, op, type) \
3423 GEN_STF(name, stop, op | 0x20, type); \
3424 GEN_STUF(name, stop, op | 0x21, type); \
3425 GEN_STUXF(name, stop, op | 0x01, type); \
3426 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3428 static always_inline
void gen_qemu_st32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3430 TCGv_i32 t0
= tcg_temp_new_i32();
3431 TCGv t1
= tcg_temp_new();
3432 gen_helper_float64_to_float32(t0
, arg1
);
3433 tcg_gen_extu_i32_tl(t1
, t0
);
3434 tcg_temp_free_i32(t0
);
3435 gen_qemu_st32(ctx
, t1
, arg2
);
3439 /* stfd stfdu stfdux stfdx */
3440 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
);
3441 /* stfs stfsu stfsux stfsx */
3442 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
);
3445 static always_inline
void gen_qemu_st32fiw(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3447 TCGv t0
= tcg_temp_new();
3448 tcg_gen_trunc_i64_tl(t0
, arg1
),
3449 gen_qemu_st32(ctx
, t0
, arg2
);
3453 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
3456 static always_inline
void gen_goto_tb (DisasContext
*ctx
, int n
,
3459 TranslationBlock
*tb
;
3461 #if defined(TARGET_PPC64)
3463 dest
= (uint32_t) dest
;
3465 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
3466 likely(!ctx
->singlestep_enabled
)) {
3468 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3469 tcg_gen_exit_tb((long)tb
+ n
);
3471 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3472 if (unlikely(ctx
->singlestep_enabled
)) {
3473 if ((ctx
->singlestep_enabled
&
3474 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3475 ctx
->exception
== POWERPC_EXCP_BRANCH
) {
3476 target_ulong tmp
= ctx
->nip
;
3478 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3481 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3482 gen_debug_exception(ctx
);
3489 static always_inline
void gen_setlr (DisasContext
*ctx
, target_ulong nip
)
3491 #if defined(TARGET_PPC64)
3492 if (ctx
->sf_mode
== 0)
3493 tcg_gen_movi_tl(cpu_lr
, (uint32_t)nip
);
3496 tcg_gen_movi_tl(cpu_lr
, nip
);
3500 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3502 target_ulong li
, target
;
3504 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3505 /* sign extend LI */
3506 #if defined(TARGET_PPC64)
3508 li
= ((int64_t)LI(ctx
->opcode
) << 38) >> 38;
3511 li
= ((int32_t)LI(ctx
->opcode
) << 6) >> 6;
3512 if (likely(AA(ctx
->opcode
) == 0))
3513 target
= ctx
->nip
+ li
- 4;
3516 if (LK(ctx
->opcode
))
3517 gen_setlr(ctx
, ctx
->nip
);
3518 gen_goto_tb(ctx
, 0, target
);
3525 static always_inline
void gen_bcond (DisasContext
*ctx
, int type
)
3527 uint32_t bo
= BO(ctx
->opcode
);
3528 int l1
= gen_new_label();
3531 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3532 if (type
== BCOND_LR
|| type
== BCOND_CTR
) {
3533 target
= tcg_temp_local_new();
3534 if (type
== BCOND_CTR
)
3535 tcg_gen_mov_tl(target
, cpu_ctr
);
3537 tcg_gen_mov_tl(target
, cpu_lr
);
3539 if (LK(ctx
->opcode
))
3540 gen_setlr(ctx
, ctx
->nip
);
3541 l1
= gen_new_label();
3542 if ((bo
& 0x4) == 0) {
3543 /* Decrement and test CTR */
3544 TCGv temp
= tcg_temp_new();
3545 if (unlikely(type
== BCOND_CTR
)) {
3546 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3549 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3550 #if defined(TARGET_PPC64)
3552 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3555 tcg_gen_mov_tl(temp
, cpu_ctr
);
3557 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3559 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3561 tcg_temp_free(temp
);
3563 if ((bo
& 0x10) == 0) {
3565 uint32_t bi
= BI(ctx
->opcode
);
3566 uint32_t mask
= 1 << (3 - (bi
& 0x03));
3567 TCGv_i32 temp
= tcg_temp_new_i32();
3570 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3571 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3573 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3574 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3576 tcg_temp_free_i32(temp
);
3578 if (type
== BCOND_IM
) {
3579 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3580 if (likely(AA(ctx
->opcode
) == 0)) {
3581 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3583 gen_goto_tb(ctx
, 0, li
);
3586 gen_goto_tb(ctx
, 1, ctx
->nip
);
3588 #if defined(TARGET_PPC64)
3589 if (!(ctx
->sf_mode
))
3590 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3593 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3596 #if defined(TARGET_PPC64)
3597 if (!(ctx
->sf_mode
))
3598 tcg_gen_movi_tl(cpu_nip
, (uint32_t)ctx
->nip
);
3601 tcg_gen_movi_tl(cpu_nip
, ctx
->nip
);
3606 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3608 gen_bcond(ctx
, BCOND_IM
);
3611 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
)
3613 gen_bcond(ctx
, BCOND_CTR
);
3616 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
)
3618 gen_bcond(ctx
, BCOND_LR
);
3621 /*** Condition register logical ***/
3622 #define GEN_CRLOGIC(name, tcg_op, opc) \
3623 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3628 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3629 t0 = tcg_temp_new_i32(); \
3631 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3633 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3635 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3636 t1 = tcg_temp_new_i32(); \
3637 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3639 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3641 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3643 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3644 tcg_op(t0, t0, t1); \
3645 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3646 tcg_gen_andi_i32(t0, t0, bitmask); \
3647 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3648 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3649 tcg_temp_free_i32(t0); \
3650 tcg_temp_free_i32(t1); \
3654 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3656 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3658 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3660 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3662 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3664 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3666 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3668 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3670 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
)
3672 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3675 /*** System linkage ***/
3676 /* rfi (mem_idx only) */
3677 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
)
3679 #if defined(CONFIG_USER_ONLY)
3680 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3682 /* Restore CPU state */
3683 if (unlikely(!ctx
->mem_idx
)) {
3684 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3688 gen_sync_exception(ctx
);
3692 #if defined(TARGET_PPC64)
3693 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
)
3695 #if defined(CONFIG_USER_ONLY)
3696 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3698 /* Restore CPU state */
3699 if (unlikely(!ctx
->mem_idx
)) {
3700 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3704 gen_sync_exception(ctx
);
3708 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
)
3710 #if defined(CONFIG_USER_ONLY)
3711 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3713 /* Restore CPU state */
3714 if (unlikely(ctx
->mem_idx
<= 1)) {
3715 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3719 gen_sync_exception(ctx
);
3725 #if defined(CONFIG_USER_ONLY)
3726 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3728 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3730 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
)
3734 lev
= (ctx
->opcode
>> 5) & 0x7F;
3735 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3740 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
)
3742 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3743 /* Update the nip since this might generate a trap exception */
3744 gen_update_nip(ctx
, ctx
->nip
);
3745 gen_helper_tw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
3746 tcg_temp_free_i32(t0
);
3750 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
)
3752 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3753 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3754 /* Update the nip since this might generate a trap exception */
3755 gen_update_nip(ctx
, ctx
->nip
);
3756 gen_helper_tw(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3758 tcg_temp_free_i32(t1
);
3761 #if defined(TARGET_PPC64)
3763 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
)
3765 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3766 /* Update the nip since this might generate a trap exception */
3767 gen_update_nip(ctx
, ctx
->nip
);
3768 gen_helper_td(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
3769 tcg_temp_free_i32(t0
);
3773 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
)
3775 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3776 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3777 /* Update the nip since this might generate a trap exception */
3778 gen_update_nip(ctx
, ctx
->nip
);
3779 gen_helper_td(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3781 tcg_temp_free_i32(t1
);
3785 /*** Processor control ***/
3787 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
)
3789 tcg_gen_trunc_tl_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_xer
);
3790 tcg_gen_shri_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], XER_CA
);
3791 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_SO
| 1 << XER_OV
| 1 << XER_CA
));
3795 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
)
3799 if (likely(ctx
->opcode
& 0x00100000)) {
3800 crm
= CRM(ctx
->opcode
);
3801 if (likely((crm
^ (crm
- 1)) == 0)) {
3803 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
3806 gen_helper_load_cr(cpu_gpr
[rD(ctx
->opcode
)]);
3811 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
)
3813 #if defined(CONFIG_USER_ONLY)
3814 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3816 if (unlikely(!ctx
->mem_idx
)) {
3817 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3820 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
3825 #define SPR_NOACCESS ((void *)(-1UL))
3827 static void spr_noaccess (void *opaque
, int sprn
)
3829 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3830 printf("ERROR: try to access SPR %d !\n", sprn
);
3832 #define SPR_NOACCESS (&spr_noaccess)
3836 static always_inline
void gen_op_mfspr (DisasContext
*ctx
)
3838 void (*read_cb
)(void *opaque
, int gprn
, int sprn
);
3839 uint32_t sprn
= SPR(ctx
->opcode
);
3841 #if !defined(CONFIG_USER_ONLY)
3842 if (ctx
->mem_idx
== 2)
3843 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3844 else if (ctx
->mem_idx
)
3845 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3848 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3849 if (likely(read_cb
!= NULL
)) {
3850 if (likely(read_cb
!= SPR_NOACCESS
)) {
3851 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
3853 /* Privilege exception */
3854 /* This is a hack to avoid warnings when running Linux:
3855 * this OS breaks the PowerPC virtualisation model,
3856 * allowing userland application to read the PVR
3858 if (sprn
!= SPR_PVR
) {
3859 if (loglevel
!= 0) {
3860 fprintf(logfile
, "Trying to read privileged spr %d %03x at "
3861 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3863 printf("Trying to read privileged spr %d %03x at " ADDRX
"\n",
3864 sprn
, sprn
, ctx
->nip
);
3866 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3870 if (loglevel
!= 0) {
3871 fprintf(logfile
, "Trying to read invalid spr %d %03x at "
3872 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3874 printf("Trying to read invalid spr %d %03x at " ADDRX
"\n",
3875 sprn
, sprn
, ctx
->nip
);
3876 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3880 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
)
3886 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
)
3892 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
)
3896 crm
= CRM(ctx
->opcode
);
3897 if (likely((ctx
->opcode
& 0x00100000) || (crm
^ (crm
- 1)) == 0)) {
3898 TCGv_i32 temp
= tcg_temp_new_i32();
3900 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3901 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
3902 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
3903 tcg_temp_free_i32(temp
);
3905 TCGv_i32 temp
= tcg_const_i32(crm
);
3906 gen_helper_store_cr(cpu_gpr
[rS(ctx
->opcode
)], temp
);
3907 tcg_temp_free_i32(temp
);
3912 #if defined(TARGET_PPC64)
3913 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
)
3915 #if defined(CONFIG_USER_ONLY)
3916 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3918 if (unlikely(!ctx
->mem_idx
)) {
3919 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3922 if (ctx
->opcode
& 0x00010000) {
3923 /* Special form that does not need any synchronisation */
3924 TCGv t0
= tcg_temp_new();
3925 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3926 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
3927 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3930 /* XXX: we need to update nip before the store
3931 * if we enter power saving mode, we will exit the loop
3932 * directly from ppc_store_msr
3934 gen_update_nip(ctx
, ctx
->nip
);
3935 gen_helper_store_msr(cpu_gpr
[rS(ctx
->opcode
)]);
3936 /* Must stop the translation as machine state (may have) changed */
3937 /* Note that mtmsr is not always defined as context-synchronizing */
3938 gen_stop_exception(ctx
);
3944 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
)
3946 #if defined(CONFIG_USER_ONLY)
3947 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3949 if (unlikely(!ctx
->mem_idx
)) {
3950 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3953 if (ctx
->opcode
& 0x00010000) {
3954 /* Special form that does not need any synchronisation */
3955 TCGv t0
= tcg_temp_new();
3956 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3957 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
3958 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3961 /* XXX: we need to update nip before the store
3962 * if we enter power saving mode, we will exit the loop
3963 * directly from ppc_store_msr
3965 gen_update_nip(ctx
, ctx
->nip
);
3966 #if defined(TARGET_PPC64)
3967 if (!ctx
->sf_mode
) {
3968 TCGv t0
= tcg_temp_new();
3969 TCGv t1
= tcg_temp_new();
3970 tcg_gen_andi_tl(t0
, cpu_msr
, 0xFFFFFFFF00000000ULL
);
3971 tcg_gen_ext32u_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
3972 tcg_gen_or_tl(t0
, t0
, t1
);
3974 gen_helper_store_msr(t0
);
3978 gen_helper_store_msr(cpu_gpr
[rS(ctx
->opcode
)]);
3979 /* Must stop the translation as machine state (may have) changed */
3980 /* Note that mtmsr is not always defined as context-synchronizing */
3981 gen_stop_exception(ctx
);
3987 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
)
3989 void (*write_cb
)(void *opaque
, int sprn
, int gprn
);
3990 uint32_t sprn
= SPR(ctx
->opcode
);
3992 #if !defined(CONFIG_USER_ONLY)
3993 if (ctx
->mem_idx
== 2)
3994 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
3995 else if (ctx
->mem_idx
)
3996 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
3999 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4000 if (likely(write_cb
!= NULL
)) {
4001 if (likely(write_cb
!= SPR_NOACCESS
)) {
4002 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4004 /* Privilege exception */
4005 if (loglevel
!= 0) {
4006 fprintf(logfile
, "Trying to write privileged spr %d %03x at "
4007 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
4009 printf("Trying to write privileged spr %d %03x at " ADDRX
"\n",
4010 sprn
, sprn
, ctx
->nip
);
4011 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4015 if (loglevel
!= 0) {
4016 fprintf(logfile
, "Trying to write invalid spr %d %03x at "
4017 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
4019 printf("Trying to write invalid spr %d %03x at " ADDRX
"\n",
4020 sprn
, sprn
, ctx
->nip
);
4021 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4025 /*** Cache management ***/
4027 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
)
4029 /* XXX: specification says this is treated as a load by the MMU */
4031 gen_set_access_type(ctx
, ACCESS_CACHE
);
4032 t0
= tcg_temp_new();
4033 gen_addr_reg_index(ctx
, t0
);
4034 gen_qemu_ld8u(ctx
, t0
, t0
);
4038 /* dcbi (Supervisor only) */
4039 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
)
4041 #if defined(CONFIG_USER_ONLY)
4042 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4045 if (unlikely(!ctx
->mem_idx
)) {
4046 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4049 EA
= tcg_temp_new();
4050 gen_set_access_type(ctx
, ACCESS_CACHE
);
4051 gen_addr_reg_index(ctx
, EA
);
4052 val
= tcg_temp_new();
4053 /* XXX: specification says this should be treated as a store by the MMU */
4054 gen_qemu_ld8u(ctx
, val
, EA
);
4055 gen_qemu_st8(ctx
, val
, EA
);
4062 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
)
4064 /* XXX: specification say this is treated as a load by the MMU */
4066 gen_set_access_type(ctx
, ACCESS_CACHE
);
4067 t0
= tcg_temp_new();
4068 gen_addr_reg_index(ctx
, t0
);
4069 gen_qemu_ld8u(ctx
, t0
, t0
);
4074 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE
)
4076 /* interpreted as no-op */
4077 /* XXX: specification say this is treated as a load by the MMU
4078 * but does not generate any exception
4083 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE
)
4085 /* interpreted as no-op */
4086 /* XXX: specification say this is treated as a load by the MMU
4087 * but does not generate any exception
4092 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ
)
4095 gen_set_access_type(ctx
, ACCESS_CACHE
);
4096 /* NIP cannot be restored if the memory exception comes from an helper */
4097 gen_update_nip(ctx
, ctx
->nip
- 4);
4098 t0
= tcg_temp_new();
4099 gen_addr_reg_index(ctx
, t0
);
4100 gen_helper_dcbz(t0
);
4104 GEN_HANDLER2(dcbz_970
, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT
)
4107 gen_set_access_type(ctx
, ACCESS_CACHE
);
4108 /* NIP cannot be restored if the memory exception comes from an helper */
4109 gen_update_nip(ctx
, ctx
->nip
- 4);
4110 t0
= tcg_temp_new();
4111 gen_addr_reg_index(ctx
, t0
);
4112 if (ctx
->opcode
& 0x00200000)
4113 gen_helper_dcbz(t0
);
4115 gen_helper_dcbz_970(t0
);
4120 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
)
4123 gen_set_access_type(ctx
, ACCESS_CACHE
);
4124 /* NIP cannot be restored if the memory exception comes from an helper */
4125 gen_update_nip(ctx
, ctx
->nip
- 4);
4126 t0
= tcg_temp_new();
4127 gen_addr_reg_index(ctx
, t0
);
4128 gen_helper_icbi(t0
);
4134 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
)
4136 /* interpreted as no-op */
4137 /* XXX: specification say this is treated as a store by the MMU
4138 * but does not generate any exception
4142 /*** Segment register manipulation ***/
4143 /* Supervisor only: */
4145 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
)
4147 #if defined(CONFIG_USER_ONLY)
4148 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4151 if (unlikely(!ctx
->mem_idx
)) {
4152 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4155 t0
= tcg_const_tl(SR(ctx
->opcode
));
4156 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4162 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
)
4164 #if defined(CONFIG_USER_ONLY)
4165 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4168 if (unlikely(!ctx
->mem_idx
)) {
4169 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4172 t0
= tcg_temp_new();
4173 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4174 tcg_gen_andi_tl(t0
, t0
, 0xF);
4175 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4181 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
)
4183 #if defined(CONFIG_USER_ONLY)
4184 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4187 if (unlikely(!ctx
->mem_idx
)) {
4188 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4191 t0
= tcg_const_tl(SR(ctx
->opcode
));
4192 gen_helper_store_sr(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4198 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
)
4200 #if defined(CONFIG_USER_ONLY)
4201 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4204 if (unlikely(!ctx
->mem_idx
)) {
4205 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4208 t0
= tcg_temp_new();
4209 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4210 tcg_gen_andi_tl(t0
, t0
, 0xF);
4211 gen_helper_store_sr(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4216 #if defined(TARGET_PPC64)
4217 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4219 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
)
4221 #if defined(CONFIG_USER_ONLY)
4222 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4225 if (unlikely(!ctx
->mem_idx
)) {
4226 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4229 t0
= tcg_const_tl(SR(ctx
->opcode
));
4230 gen_helper_load_slb(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4236 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4239 #if defined(CONFIG_USER_ONLY)
4240 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4243 if (unlikely(!ctx
->mem_idx
)) {
4244 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4247 t0
= tcg_temp_new();
4248 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4249 tcg_gen_andi_tl(t0
, t0
, 0xF);
4250 gen_helper_load_slb(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4256 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
)
4258 #if defined(CONFIG_USER_ONLY)
4259 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4262 if (unlikely(!ctx
->mem_idx
)) {
4263 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4266 t0
= tcg_const_tl(SR(ctx
->opcode
));
4267 gen_helper_store_slb(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4273 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4276 #if defined(CONFIG_USER_ONLY)
4277 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4280 if (unlikely(!ctx
->mem_idx
)) {
4281 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4284 t0
= tcg_temp_new();
4285 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4286 tcg_gen_andi_tl(t0
, t0
, 0xF);
4287 gen_helper_store_slb(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4291 #endif /* defined(TARGET_PPC64) */
4293 /*** Lookaside buffer management ***/
4294 /* Optional & mem_idx only: */
4296 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
)
4298 #if defined(CONFIG_USER_ONLY)
4299 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4301 if (unlikely(!ctx
->mem_idx
)) {
4302 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4310 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
)
4312 #if defined(CONFIG_USER_ONLY)
4313 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4315 if (unlikely(!ctx
->mem_idx
)) {
4316 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4319 #if defined(TARGET_PPC64)
4320 if (!ctx
->sf_mode
) {
4321 TCGv t0
= tcg_temp_new();
4322 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4323 gen_helper_tlbie(t0
);
4327 gen_helper_tlbie(cpu_gpr
[rB(ctx
->opcode
)]);
4332 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
)
4334 #if defined(CONFIG_USER_ONLY)
4335 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4337 if (unlikely(!ctx
->mem_idx
)) {
4338 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4341 /* This has no effect: it should ensure that all previous
4342 * tlbie have completed
4344 gen_stop_exception(ctx
);
4348 #if defined(TARGET_PPC64)
4350 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
)
4352 #if defined(CONFIG_USER_ONLY)
4353 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4355 if (unlikely(!ctx
->mem_idx
)) {
4356 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4364 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
)
4366 #if defined(CONFIG_USER_ONLY)
4367 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4369 if (unlikely(!ctx
->mem_idx
)) {
4370 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4373 gen_helper_slbie(cpu_gpr
[rB(ctx
->opcode
)]);
4378 /*** External control ***/
4381 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
)
4384 /* Should check EAR[E] ! */
4385 gen_set_access_type(ctx
, ACCESS_EXT
);
4386 t0
= tcg_temp_new();
4387 gen_addr_reg_index(ctx
, t0
);
4388 gen_check_align(ctx
, t0
, 0x03);
4389 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4394 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
)
4397 /* Should check EAR[E] ! */
4398 gen_set_access_type(ctx
, ACCESS_EXT
);
4399 t0
= tcg_temp_new();
4400 gen_addr_reg_index(ctx
, t0
);
4401 gen_check_align(ctx
, t0
, 0x03);
4402 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4406 /* PowerPC 601 specific instructions */
4408 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
)
4410 int l1
= gen_new_label();
4411 int l2
= gen_new_label();
4412 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4413 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4416 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4418 if (unlikely(Rc(ctx
->opcode
) != 0))
4419 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4423 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
)
4425 int l1
= gen_new_label();
4426 int l2
= gen_new_label();
4427 int l3
= gen_new_label();
4428 /* Start with XER OV disabled, the most likely case */
4429 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4430 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4431 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4432 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4435 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4438 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4440 if (unlikely(Rc(ctx
->opcode
) != 0))
4441 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4445 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
)
4447 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4448 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4449 tcg_temp_free_i32(t0
);
4450 /* Rc=1 sets CR0 to an undefined state */
4454 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
)
4456 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4457 if (unlikely(Rc(ctx
->opcode
) != 0))
4458 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4462 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
)
4464 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4465 if (unlikely(Rc(ctx
->opcode
) != 0))
4466 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4470 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
)
4472 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4473 if (unlikely(Rc(ctx
->opcode
) != 0))
4474 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4477 /* divso - divso. */
4478 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
)
4480 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4481 if (unlikely(Rc(ctx
->opcode
) != 0))
4482 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4486 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
)
4488 int l1
= gen_new_label();
4489 int l2
= gen_new_label();
4490 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4491 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4494 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4496 if (unlikely(Rc(ctx
->opcode
) != 0))
4497 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4501 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
)
4503 int l1
= gen_new_label();
4504 int l2
= gen_new_label();
4505 TCGv t0
= tcg_temp_new();
4506 TCGv t1
= tcg_temp_new();
4507 TCGv t2
= tcg_temp_new();
4508 /* Start with XER OV disabled, the most likely case */
4509 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4510 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4511 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4512 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4513 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
4514 tcg_gen_andc_tl(t1
, t1
, t2
);
4515 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4516 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4517 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4520 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4525 if (unlikely(Rc(ctx
->opcode
) != 0))
4526 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4530 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
)
4532 target_long simm
= SIMM(ctx
->opcode
);
4533 int l1
= gen_new_label();
4534 int l2
= gen_new_label();
4535 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
4536 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
4539 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4541 if (unlikely(Rc(ctx
->opcode
) != 0))
4542 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4545 /* lscbx - lscbx. */
4546 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
)
4548 TCGv t0
= tcg_temp_new();
4549 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
4550 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
4551 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
4553 gen_addr_reg_index(ctx
, t0
);
4554 /* NIP cannot be restored if the memory exception comes from an helper */
4555 gen_update_nip(ctx
, ctx
->nip
- 4);
4556 gen_helper_lscbx(t0
, t0
, t1
, t2
, t3
);
4557 tcg_temp_free_i32(t1
);
4558 tcg_temp_free_i32(t2
);
4559 tcg_temp_free_i32(t3
);
4560 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
4561 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
4562 if (unlikely(Rc(ctx
->opcode
) != 0))
4563 gen_set_Rc0(ctx
, t0
);
4567 /* maskg - maskg. */
4568 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
)
4570 int l1
= gen_new_label();
4571 TCGv t0
= tcg_temp_new();
4572 TCGv t1
= tcg_temp_new();
4573 TCGv t2
= tcg_temp_new();
4574 TCGv t3
= tcg_temp_new();
4575 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
4576 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4577 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
4578 tcg_gen_addi_tl(t2
, t0
, 1);
4579 tcg_gen_shr_tl(t2
, t3
, t2
);
4580 tcg_gen_shr_tl(t3
, t3
, t1
);
4581 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
4582 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4583 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4589 if (unlikely(Rc(ctx
->opcode
) != 0))
4590 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4593 /* maskir - maskir. */
4594 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
)
4596 TCGv t0
= tcg_temp_new();
4597 TCGv t1
= tcg_temp_new();
4598 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4599 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4600 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4603 if (unlikely(Rc(ctx
->opcode
) != 0))
4604 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4608 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
)
4610 TCGv_i64 t0
= tcg_temp_new_i64();
4611 TCGv_i64 t1
= tcg_temp_new_i64();
4612 TCGv t2
= tcg_temp_new();
4613 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4614 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4615 tcg_gen_mul_i64(t0
, t0
, t1
);
4616 tcg_gen_trunc_i64_tl(t2
, t0
);
4617 gen_store_spr(SPR_MQ
, t2
);
4618 tcg_gen_shri_i64(t1
, t0
, 32);
4619 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4620 tcg_temp_free_i64(t0
);
4621 tcg_temp_free_i64(t1
);
4623 if (unlikely(Rc(ctx
->opcode
) != 0))
4624 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4628 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
)
4630 int l1
= gen_new_label();
4631 TCGv_i64 t0
= tcg_temp_new_i64();
4632 TCGv_i64 t1
= tcg_temp_new_i64();
4633 TCGv t2
= tcg_temp_new();
4634 /* Start with XER OV disabled, the most likely case */
4635 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4636 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4637 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4638 tcg_gen_mul_i64(t0
, t0
, t1
);
4639 tcg_gen_trunc_i64_tl(t2
, t0
);
4640 gen_store_spr(SPR_MQ
, t2
);
4641 tcg_gen_shri_i64(t1
, t0
, 32);
4642 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4643 tcg_gen_ext32s_i64(t1
, t0
);
4644 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
4645 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4647 tcg_temp_free_i64(t0
);
4648 tcg_temp_free_i64(t1
);
4650 if (unlikely(Rc(ctx
->opcode
) != 0))
4651 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4655 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
)
4657 int l1
= gen_new_label();
4658 int l2
= gen_new_label();
4659 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4660 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4663 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4665 if (unlikely(Rc(ctx
->opcode
) != 0))
4666 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4669 /* nabso - nabso. */
4670 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
)
4672 int l1
= gen_new_label();
4673 int l2
= gen_new_label();
4674 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4675 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4678 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4680 /* nabs never overflows */
4681 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4682 if (unlikely(Rc(ctx
->opcode
) != 0))
4683 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4687 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
)
4689 uint32_t mb
= MB(ctx
->opcode
);
4690 uint32_t me
= ME(ctx
->opcode
);
4691 TCGv t0
= tcg_temp_new();
4692 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4693 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4694 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
4695 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
4696 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
4698 if (unlikely(Rc(ctx
->opcode
) != 0))
4699 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4703 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
)
4705 TCGv t0
= tcg_temp_new();
4706 TCGv t1
= tcg_temp_new();
4707 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4708 tcg_gen_movi_tl(t1
, 0x80000000);
4709 tcg_gen_shr_tl(t1
, t1
, t0
);
4710 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4711 tcg_gen_and_tl(t0
, t0
, t1
);
4712 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
4713 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4716 if (unlikely(Rc(ctx
->opcode
) != 0))
4717 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4721 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
)
4723 TCGv t0
= tcg_temp_new();
4724 TCGv t1
= tcg_temp_new();
4725 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4726 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4727 tcg_gen_subfi_tl(t1
, 32, t1
);
4728 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4729 tcg_gen_or_tl(t1
, t0
, t1
);
4730 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4731 gen_store_spr(SPR_MQ
, t1
);
4734 if (unlikely(Rc(ctx
->opcode
) != 0))
4735 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4739 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
)
4741 TCGv t0
= tcg_temp_new();
4742 TCGv t1
= tcg_temp_new();
4743 TCGv t2
= tcg_temp_new();
4744 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4745 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
4746 tcg_gen_shl_tl(t2
, t2
, t0
);
4747 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4748 gen_load_spr(t1
, SPR_MQ
);
4749 gen_store_spr(SPR_MQ
, t0
);
4750 tcg_gen_and_tl(t0
, t0
, t2
);
4751 tcg_gen_andc_tl(t1
, t1
, t2
);
4752 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4756 if (unlikely(Rc(ctx
->opcode
) != 0))
4757 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4761 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
)
4763 int sh
= SH(ctx
->opcode
);
4764 TCGv t0
= tcg_temp_new();
4765 TCGv t1
= tcg_temp_new();
4766 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4767 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4768 tcg_gen_or_tl(t1
, t0
, t1
);
4769 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4770 gen_store_spr(SPR_MQ
, t1
);
4773 if (unlikely(Rc(ctx
->opcode
) != 0))
4774 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4777 /* slliq - slliq. */
4778 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
)
4780 int sh
= SH(ctx
->opcode
);
4781 TCGv t0
= tcg_temp_new();
4782 TCGv t1
= tcg_temp_new();
4783 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4784 gen_load_spr(t1
, SPR_MQ
);
4785 gen_store_spr(SPR_MQ
, t0
);
4786 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
4787 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
4788 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4791 if (unlikely(Rc(ctx
->opcode
) != 0))
4792 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4796 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
)
4798 int l1
= gen_new_label();
4799 int l2
= gen_new_label();
4800 TCGv t0
= tcg_temp_local_new();
4801 TCGv t1
= tcg_temp_local_new();
4802 TCGv t2
= tcg_temp_local_new();
4803 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4804 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
4805 tcg_gen_shl_tl(t1
, t1
, t2
);
4806 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4807 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
4808 gen_load_spr(t0
, SPR_MQ
);
4809 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4812 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4813 gen_load_spr(t2
, SPR_MQ
);
4814 tcg_gen_andc_tl(t1
, t2
, t1
);
4815 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4820 if (unlikely(Rc(ctx
->opcode
) != 0))
4821 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4825 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
)
4827 int l1
= gen_new_label();
4828 TCGv t0
= tcg_temp_new();
4829 TCGv t1
= tcg_temp_new();
4830 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4831 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4832 tcg_gen_subfi_tl(t1
, 32, t1
);
4833 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4834 tcg_gen_or_tl(t1
, t0
, t1
);
4835 gen_store_spr(SPR_MQ
, t1
);
4836 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4837 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4838 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4839 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
4843 if (unlikely(Rc(ctx
->opcode
) != 0))
4844 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4847 /* sraiq - sraiq. */
4848 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
)
4850 int sh
= SH(ctx
->opcode
);
4851 int l1
= gen_new_label();
4852 TCGv t0
= tcg_temp_new();
4853 TCGv t1
= tcg_temp_new();
4854 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4855 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4856 tcg_gen_or_tl(t0
, t0
, t1
);
4857 gen_store_spr(SPR_MQ
, t0
);
4858 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
4859 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4860 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
4861 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_CA
));
4863 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
4866 if (unlikely(Rc(ctx
->opcode
) != 0))
4867 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4871 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
)
4873 int l1
= gen_new_label();
4874 int l2
= gen_new_label();
4875 TCGv t0
= tcg_temp_new();
4876 TCGv t1
= tcg_temp_local_new();
4877 TCGv t2
= tcg_temp_local_new();
4878 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4879 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4880 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4881 tcg_gen_subfi_tl(t2
, 32, t2
);
4882 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4883 tcg_gen_or_tl(t0
, t0
, t2
);
4884 gen_store_spr(SPR_MQ
, t0
);
4885 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4886 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
4887 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
4888 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
4891 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
4892 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
4893 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4894 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
4895 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_CA
));
4899 if (unlikely(Rc(ctx
->opcode
) != 0))
4900 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4904 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
)
4906 TCGv t0
= tcg_temp_new();
4907 TCGv t1
= tcg_temp_new();
4908 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4909 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4910 tcg_gen_subfi_tl(t1
, 32, t1
);
4911 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4912 tcg_gen_or_tl(t1
, t0
, t1
);
4913 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4914 gen_store_spr(SPR_MQ
, t1
);
4917 if (unlikely(Rc(ctx
->opcode
) != 0))
4918 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4922 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
)
4924 TCGv t0
= tcg_temp_new();
4925 TCGv t1
= tcg_temp_new();
4926 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4927 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4928 gen_store_spr(SPR_MQ
, t0
);
4929 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
4932 if (unlikely(Rc(ctx
->opcode
) != 0))
4933 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4937 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
)
4939 TCGv t0
= tcg_temp_new();
4940 TCGv t1
= tcg_temp_new();
4941 TCGv t2
= tcg_temp_new();
4942 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4943 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
4944 tcg_gen_shr_tl(t1
, t1
, t0
);
4945 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4946 gen_load_spr(t2
, SPR_MQ
);
4947 gen_store_spr(SPR_MQ
, t0
);
4948 tcg_gen_and_tl(t0
, t0
, t1
);
4949 tcg_gen_andc_tl(t2
, t2
, t1
);
4950 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
4954 if (unlikely(Rc(ctx
->opcode
) != 0))
4955 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4959 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
)
4961 int sh
= SH(ctx
->opcode
);
4962 TCGv t0
= tcg_temp_new();
4963 TCGv t1
= tcg_temp_new();
4964 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4965 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4966 tcg_gen_or_tl(t1
, t0
, t1
);
4967 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4968 gen_store_spr(SPR_MQ
, t1
);
4971 if (unlikely(Rc(ctx
->opcode
) != 0))
4972 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4976 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
)
4978 int sh
= SH(ctx
->opcode
);
4979 TCGv t0
= tcg_temp_new();
4980 TCGv t1
= tcg_temp_new();
4981 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4982 gen_load_spr(t1
, SPR_MQ
);
4983 gen_store_spr(SPR_MQ
, t0
);
4984 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
4985 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
4986 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4989 if (unlikely(Rc(ctx
->opcode
) != 0))
4990 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4994 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
)
4996 int l1
= gen_new_label();
4997 int l2
= gen_new_label();
4998 TCGv t0
= tcg_temp_local_new();
4999 TCGv t1
= tcg_temp_local_new();
5000 TCGv t2
= tcg_temp_local_new();
5001 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5002 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5003 tcg_gen_shr_tl(t2
, t1
, t2
);
5004 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5005 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5006 gen_load_spr(t0
, SPR_MQ
);
5007 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5010 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5011 tcg_gen_and_tl(t0
, t0
, t2
);
5012 gen_load_spr(t1
, SPR_MQ
);
5013 tcg_gen_andc_tl(t1
, t1
, t2
);
5014 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5019 if (unlikely(Rc(ctx
->opcode
) != 0))
5020 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5024 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
)
5026 int l1
= gen_new_label();
5027 TCGv t0
= tcg_temp_new();
5028 TCGv t1
= tcg_temp_new();
5029 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5030 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5031 tcg_gen_subfi_tl(t1
, 32, t1
);
5032 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5033 tcg_gen_or_tl(t1
, t0
, t1
);
5034 gen_store_spr(SPR_MQ
, t1
);
5035 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5036 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5037 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5038 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5042 if (unlikely(Rc(ctx
->opcode
) != 0))
5043 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5046 /* PowerPC 602 specific instructions */
5048 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
)
5051 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5055 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
)
5058 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5062 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
)
5064 #if defined(CONFIG_USER_ONLY)
5065 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5067 if (unlikely(!ctx
->mem_idx
)) {
5068 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5071 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5075 /* 602 - 603 - G2 TLB management */
5077 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
)
5079 #if defined(CONFIG_USER_ONLY)
5080 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5082 if (unlikely(!ctx
->mem_idx
)) {
5083 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5086 gen_helper_6xx_tlbd(cpu_gpr
[rB(ctx
->opcode
)]);
5091 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
)
5093 #if defined(CONFIG_USER_ONLY)
5094 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5096 if (unlikely(!ctx
->mem_idx
)) {
5097 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5100 gen_helper_6xx_tlbi(cpu_gpr
[rB(ctx
->opcode
)]);
5104 /* 74xx TLB management */
5106 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
)
5108 #if defined(CONFIG_USER_ONLY)
5109 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5111 if (unlikely(!ctx
->mem_idx
)) {
5112 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5115 gen_helper_74xx_tlbd(cpu_gpr
[rB(ctx
->opcode
)]);
5120 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
)
5122 #if defined(CONFIG_USER_ONLY)
5123 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5125 if (unlikely(!ctx
->mem_idx
)) {
5126 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5129 gen_helper_74xx_tlbi(cpu_gpr
[rB(ctx
->opcode
)]);
5133 /* POWER instructions not in PowerPC 601 */
5135 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
)
5137 /* Cache line flush: implemented as no-op */
5141 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
)
5143 /* Cache line invalidate: privileged and treated as no-op */
5144 #if defined(CONFIG_USER_ONLY)
5145 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5147 if (unlikely(!ctx
->mem_idx
)) {
5148 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5155 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
)
5157 /* Data cache line store: treated as no-op */
5160 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
)
5162 #if defined(CONFIG_USER_ONLY)
5163 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5165 int ra
= rA(ctx
->opcode
);
5166 int rd
= rD(ctx
->opcode
);
5168 if (unlikely(!ctx
->mem_idx
)) {
5169 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5172 t0
= tcg_temp_new();
5173 gen_addr_reg_index(ctx
, t0
);
5174 tcg_gen_shri_tl(t0
, t0
, 28);
5175 tcg_gen_andi_tl(t0
, t0
, 0xF);
5176 gen_helper_load_sr(cpu_gpr
[rd
], t0
);
5178 if (ra
!= 0 && ra
!= rd
)
5179 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5183 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
)
5185 #if defined(CONFIG_USER_ONLY)
5186 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5189 if (unlikely(!ctx
->mem_idx
)) {
5190 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5193 t0
= tcg_temp_new();
5194 gen_addr_reg_index(ctx
, t0
);
5195 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5200 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
)
5202 #if defined(CONFIG_USER_ONLY)
5203 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5205 if (unlikely(!ctx
->mem_idx
)) {
5206 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5210 gen_sync_exception(ctx
);
5214 /* svc is not implemented for now */
5216 /* POWER2 specific instructions */
5217 /* Quad manipulation (load/store two floats at a time) */
5220 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
5222 int rd
= rD(ctx
->opcode
);
5224 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5225 t0
= tcg_temp_new();
5226 gen_addr_imm_index(ctx
, t0
, 0);
5227 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5228 gen_addr_add(ctx
, t0
, t0
, 8);
5229 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5234 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
5236 int ra
= rA(ctx
->opcode
);
5237 int rd
= rD(ctx
->opcode
);
5239 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5240 t0
= tcg_temp_new();
5241 t1
= tcg_temp_new();
5242 gen_addr_imm_index(ctx
, t0
, 0);
5243 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5244 gen_addr_add(ctx
, t1
, t0
, 8);
5245 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5247 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5253 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
)
5255 int ra
= rA(ctx
->opcode
);
5256 int rd
= rD(ctx
->opcode
);
5257 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5259 t0
= tcg_temp_new();
5260 gen_addr_reg_index(ctx
, t0
);
5261 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5262 t1
= tcg_temp_new();
5263 gen_addr_add(ctx
, t1
, t0
, 8);
5264 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5267 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5272 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
)
5274 int rd
= rD(ctx
->opcode
);
5276 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5277 t0
= tcg_temp_new();
5278 gen_addr_reg_index(ctx
, t0
);
5279 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5280 gen_addr_add(ctx
, t0
, t0
, 8);
5281 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5286 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
5288 int rd
= rD(ctx
->opcode
);
5290 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5291 t0
= tcg_temp_new();
5292 gen_addr_imm_index(ctx
, t0
, 0);
5293 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5294 gen_addr_add(ctx
, t0
, t0
, 8);
5295 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5300 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
)
5302 int ra
= rA(ctx
->opcode
);
5303 int rd
= rD(ctx
->opcode
);
5305 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5306 t0
= tcg_temp_new();
5307 gen_addr_imm_index(ctx
, t0
, 0);
5308 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5309 t1
= tcg_temp_new();
5310 gen_addr_add(ctx
, t1
, t0
, 8);
5311 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5314 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5319 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
)
5321 int ra
= rA(ctx
->opcode
);
5322 int rd
= rD(ctx
->opcode
);
5324 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5325 t0
= tcg_temp_new();
5326 gen_addr_reg_index(ctx
, t0
);
5327 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5328 t1
= tcg_temp_new();
5329 gen_addr_add(ctx
, t1
, t0
, 8);
5330 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5333 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5338 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
)
5340 int rd
= rD(ctx
->opcode
);
5342 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5343 t0
= tcg_temp_new();
5344 gen_addr_reg_index(ctx
, t0
);
5345 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5346 gen_addr_add(ctx
, t0
, t0
, 8);
5347 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5351 /* BookE specific instructions */
5352 /* XXX: not implemented on 440 ? */
5353 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
)
5356 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5359 /* XXX: not implemented on 440 ? */
5360 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
)
5362 #if defined(CONFIG_USER_ONLY)
5363 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5366 if (unlikely(!ctx
->mem_idx
)) {
5367 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5370 t0
= tcg_temp_new();
5371 gen_addr_reg_index(ctx
, t0
);
5372 gen_helper_tlbie(cpu_gpr
[rB(ctx
->opcode
)]);
5377 /* All 405 MAC instructions are translated here */
5378 static always_inline
void gen_405_mulladd_insn (DisasContext
*ctx
,
5380 int ra
, int rb
, int rt
, int Rc
)
5384 t0
= tcg_temp_local_new();
5385 t1
= tcg_temp_local_new();
5387 switch (opc3
& 0x0D) {
5389 /* macchw - macchw. - macchwo - macchwo. */
5390 /* macchws - macchws. - macchwso - macchwso. */
5391 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5392 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5393 /* mulchw - mulchw. */
5394 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5395 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5396 tcg_gen_ext16s_tl(t1
, t1
);
5399 /* macchwu - macchwu. - macchwuo - macchwuo. */
5400 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5401 /* mulchwu - mulchwu. */
5402 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5403 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5404 tcg_gen_ext16u_tl(t1
, t1
);
5407 /* machhw - machhw. - machhwo - machhwo. */
5408 /* machhws - machhws. - machhwso - machhwso. */
5409 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5410 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5411 /* mulhhw - mulhhw. */
5412 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5413 tcg_gen_ext16s_tl(t0
, t0
);
5414 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5415 tcg_gen_ext16s_tl(t1
, t1
);
5418 /* machhwu - machhwu. - machhwuo - machhwuo. */
5419 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5420 /* mulhhwu - mulhhwu. */
5421 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5422 tcg_gen_ext16u_tl(t0
, t0
);
5423 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5424 tcg_gen_ext16u_tl(t1
, t1
);
5427 /* maclhw - maclhw. - maclhwo - maclhwo. */
5428 /* maclhws - maclhws. - maclhwso - maclhwso. */
5429 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5430 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5431 /* mullhw - mullhw. */
5432 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5433 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5436 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5437 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5438 /* mullhwu - mullhwu. */
5439 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5440 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5444 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5445 tcg_gen_mul_tl(t1
, t0
, t1
);
5447 /* nmultiply-and-accumulate (0x0E) */
5448 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5450 /* multiply-and-accumulate (0x0C) */
5451 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5455 /* Check overflow and/or saturate */
5456 int l1
= gen_new_label();
5459 /* Start with XER OV disabled, the most likely case */
5460 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
5464 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5465 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5466 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5467 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5470 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5471 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5475 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5478 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5482 /* Check overflow */
5483 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
5486 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5489 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5493 if (unlikely(Rc
) != 0) {
5495 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5499 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5500 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5502 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5503 rD(ctx->opcode), Rc(ctx->opcode)); \
5506 /* macchw - macchw. */
5507 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5508 /* macchwo - macchwo. */
5509 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5510 /* macchws - macchws. */
5511 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5512 /* macchwso - macchwso. */
5513 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5514 /* macchwsu - macchwsu. */
5515 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5516 /* macchwsuo - macchwsuo. */
5517 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5518 /* macchwu - macchwu. */
5519 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5520 /* macchwuo - macchwuo. */
5521 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5522 /* machhw - machhw. */
5523 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5524 /* machhwo - machhwo. */
5525 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5526 /* machhws - machhws. */
5527 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5528 /* machhwso - machhwso. */
5529 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5530 /* machhwsu - machhwsu. */
5531 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5532 /* machhwsuo - machhwsuo. */
5533 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5534 /* machhwu - machhwu. */
5535 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5536 /* machhwuo - machhwuo. */
5537 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5538 /* maclhw - maclhw. */
5539 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5540 /* maclhwo - maclhwo. */
5541 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5542 /* maclhws - maclhws. */
5543 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5544 /* maclhwso - maclhwso. */
5545 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5546 /* maclhwu - maclhwu. */
5547 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5548 /* maclhwuo - maclhwuo. */
5549 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5550 /* maclhwsu - maclhwsu. */
5551 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5552 /* maclhwsuo - maclhwsuo. */
5553 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5554 /* nmacchw - nmacchw. */
5555 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5556 /* nmacchwo - nmacchwo. */
5557 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5558 /* nmacchws - nmacchws. */
5559 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5560 /* nmacchwso - nmacchwso. */
5561 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5562 /* nmachhw - nmachhw. */
5563 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5564 /* nmachhwo - nmachhwo. */
5565 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5566 /* nmachhws - nmachhws. */
5567 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5568 /* nmachhwso - nmachhwso. */
5569 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5570 /* nmaclhw - nmaclhw. */
5571 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5572 /* nmaclhwo - nmaclhwo. */
5573 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5574 /* nmaclhws - nmaclhws. */
5575 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5576 /* nmaclhwso - nmaclhwso. */
5577 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5579 /* mulchw - mulchw. */
5580 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5581 /* mulchwu - mulchwu. */
5582 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5583 /* mulhhw - mulhhw. */
5584 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5585 /* mulhhwu - mulhhwu. */
5586 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5587 /* mullhw - mullhw. */
5588 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5589 /* mullhwu - mullhwu. */
5590 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5593 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
)
5595 #if defined(CONFIG_USER_ONLY)
5596 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5599 if (unlikely(!ctx
->mem_idx
)) {
5600 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5603 /* NIP cannot be restored if the memory exception comes from an helper */
5604 gen_update_nip(ctx
, ctx
->nip
- 4);
5605 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5606 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], dcrn
);
5607 tcg_temp_free(dcrn
);
5612 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
)
5614 #if defined(CONFIG_USER_ONLY)
5615 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5618 if (unlikely(!ctx
->mem_idx
)) {
5619 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5622 /* NIP cannot be restored if the memory exception comes from an helper */
5623 gen_update_nip(ctx
, ctx
->nip
- 4);
5624 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5625 gen_helper_store_dcr(dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
5626 tcg_temp_free(dcrn
);
5631 /* XXX: not implemented on 440 ? */
5632 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
)
5634 #if defined(CONFIG_USER_ONLY)
5635 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5637 if (unlikely(!ctx
->mem_idx
)) {
5638 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5641 /* NIP cannot be restored if the memory exception comes from an helper */
5642 gen_update_nip(ctx
, ctx
->nip
- 4);
5643 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5644 /* Note: Rc update flag set leads to undefined state of Rc0 */
5649 /* XXX: not implemented on 440 ? */
5650 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
)
5652 #if defined(CONFIG_USER_ONLY)
5653 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5655 if (unlikely(!ctx
->mem_idx
)) {
5656 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5659 /* NIP cannot be restored if the memory exception comes from an helper */
5660 gen_update_nip(ctx
, ctx
->nip
- 4);
5661 gen_helper_store_dcr(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5662 /* Note: Rc update flag set leads to undefined state of Rc0 */
5666 /* mfdcrux (PPC 460) : user-mode access to DCR */
5667 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
)
5669 /* NIP cannot be restored if the memory exception comes from an helper */
5670 gen_update_nip(ctx
, ctx
->nip
- 4);
5671 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5672 /* Note: Rc update flag set leads to undefined state of Rc0 */
5675 /* mtdcrux (PPC 460) : user-mode access to DCR */
5676 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
)
5678 /* NIP cannot be restored if the memory exception comes from an helper */
5679 gen_update_nip(ctx
, ctx
->nip
- 4);
5680 gen_helper_store_dcr(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5681 /* Note: Rc update flag set leads to undefined state of Rc0 */
5685 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
)
5687 #if defined(CONFIG_USER_ONLY)
5688 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5690 if (unlikely(!ctx
->mem_idx
)) {
5691 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5694 /* interpreted as no-op */
5699 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
)
5701 #if defined(CONFIG_USER_ONLY)
5702 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5705 if (unlikely(!ctx
->mem_idx
)) {
5706 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5709 gen_set_access_type(ctx
, ACCESS_CACHE
);
5710 EA
= tcg_temp_new();
5711 gen_addr_reg_index(ctx
, EA
);
5712 val
= tcg_temp_new();
5713 gen_qemu_ld32u(ctx
, val
, EA
);
5715 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
5721 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
)
5723 /* interpreted as no-op */
5724 /* XXX: specification say this is treated as a load by the MMU
5725 * but does not generate any exception
5730 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
)
5732 #if defined(CONFIG_USER_ONLY)
5733 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5735 if (unlikely(!ctx
->mem_idx
)) {
5736 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5739 /* interpreted as no-op */
5744 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
)
5746 #if defined(CONFIG_USER_ONLY)
5747 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5749 if (unlikely(!ctx
->mem_idx
)) {
5750 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5753 /* interpreted as no-op */
5757 /* rfci (mem_idx only) */
5758 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
)
5760 #if defined(CONFIG_USER_ONLY)
5761 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5763 if (unlikely(!ctx
->mem_idx
)) {
5764 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5767 /* Restore CPU state */
5768 gen_helper_40x_rfci();
5769 gen_sync_exception(ctx
);
5773 GEN_HANDLER(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
)
5775 #if defined(CONFIG_USER_ONLY)
5776 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5778 if (unlikely(!ctx
->mem_idx
)) {
5779 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5782 /* Restore CPU state */
5784 gen_sync_exception(ctx
);
5788 /* BookE specific */
5789 /* XXX: not implemented on 440 ? */
5790 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
)
5792 #if defined(CONFIG_USER_ONLY)
5793 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5795 if (unlikely(!ctx
->mem_idx
)) {
5796 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5799 /* Restore CPU state */
5801 gen_sync_exception(ctx
);
5805 /* XXX: not implemented on 440 ? */
5806 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
)
5808 #if defined(CONFIG_USER_ONLY)
5809 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5811 if (unlikely(!ctx
->mem_idx
)) {
5812 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5815 /* Restore CPU state */
5817 gen_sync_exception(ctx
);
5821 /* TLB management - PowerPC 405 implementation */
5823 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
)
5825 #if defined(CONFIG_USER_ONLY)
5826 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5828 if (unlikely(!ctx
->mem_idx
)) {
5829 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5832 switch (rB(ctx
->opcode
)) {
5834 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5837 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5840 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5846 /* tlbsx - tlbsx. */
5847 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
)
5849 #if defined(CONFIG_USER_ONLY)
5850 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5853 if (unlikely(!ctx
->mem_idx
)) {
5854 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5857 t0
= tcg_temp_new();
5858 gen_addr_reg_index(ctx
, t0
);
5859 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5861 if (Rc(ctx
->opcode
)) {
5862 int l1
= gen_new_label();
5863 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
5864 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
5865 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
5866 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5867 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5874 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
)
5876 #if defined(CONFIG_USER_ONLY)
5877 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5879 if (unlikely(!ctx
->mem_idx
)) {
5880 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5883 switch (rB(ctx
->opcode
)) {
5885 gen_helper_4xx_tlbwe_hi(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5888 gen_helper_4xx_tlbwe_lo(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5891 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5897 /* TLB management - PowerPC 440 implementation */
5899 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
)
5901 #if defined(CONFIG_USER_ONLY)
5902 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5904 if (unlikely(!ctx
->mem_idx
)) {
5905 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5908 switch (rB(ctx
->opcode
)) {
5913 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
5914 gen_helper_440_tlbwe(t0
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5915 tcg_temp_free_i32(t0
);
5919 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5925 /* tlbsx - tlbsx. */
5926 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
)
5928 #if defined(CONFIG_USER_ONLY)
5929 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5932 if (unlikely(!ctx
->mem_idx
)) {
5933 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5936 t0
= tcg_temp_new();
5937 gen_addr_reg_index(ctx
, t0
);
5938 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5940 if (Rc(ctx
->opcode
)) {
5941 int l1
= gen_new_label();
5942 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
5943 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
5944 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
5945 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5946 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5953 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
)
5955 #if defined(CONFIG_USER_ONLY)
5956 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5958 if (unlikely(!ctx
->mem_idx
)) {
5959 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5962 switch (rB(ctx
->opcode
)) {
5967 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
5968 gen_helper_440_tlbwe(t0
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5969 tcg_temp_free_i32(t0
);
5973 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5980 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
)
5982 #if defined(CONFIG_USER_ONLY)
5983 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5986 if (unlikely(!ctx
->mem_idx
)) {
5987 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5990 t0
= tcg_temp_new();
5991 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
5992 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
5993 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
5995 /* Stop translation to have a chance to raise an exception
5996 * if we just set msr_ee to 1
5998 gen_stop_exception(ctx
);
6003 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE
)
6005 #if defined(CONFIG_USER_ONLY)
6006 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6008 if (unlikely(!ctx
->mem_idx
)) {
6009 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6012 if (ctx
->opcode
& 0x00010000) {
6013 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6014 /* Stop translation to have a chance to raise an exception */
6015 gen_stop_exception(ctx
);
6017 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6022 /* PowerPC 440 specific instructions */
6024 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
)
6026 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6027 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
6028 cpu_gpr
[rB(ctx
->opcode
)], t0
);
6029 tcg_temp_free_i32(t0
);
6032 /* mbar replaces eieio on 440 */
6033 GEN_HANDLER(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE
)
6035 /* interpreted as no-op */
6038 /* msync replaces sync on 440 */
6039 GEN_HANDLER(msync
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
)
6041 /* interpreted as no-op */
6045 GEN_HANDLER2(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE
)
6047 /* interpreted as no-op */
6048 /* XXX: specification say this is treated as a load by the MMU
6049 * but does not generate any exception
6053 /*** Altivec vector extension ***/
6054 /* Altivec registers moves */
6056 #define GEN_VR_LDX(name, opc2, opc3) \
6057 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6060 if (unlikely(!ctx->altivec_enabled)) { \
6061 gen_exception(ctx, POWERPC_EXCP_VPU); \
6064 gen_set_access_type(ctx, ACCESS_INT); \
6065 EA = tcg_temp_new(); \
6066 gen_addr_reg_index(ctx, EA); \
6067 tcg_gen_andi_tl(EA, EA, ~0xf); \
6068 if (ctx->le_mode) { \
6069 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6070 tcg_gen_addi_tl(EA, EA, 8); \
6071 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6073 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6074 tcg_gen_addi_tl(EA, EA, 8); \
6075 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6077 tcg_temp_free(EA); \
6080 #define GEN_VR_STX(name, opc2, opc3) \
6081 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6084 if (unlikely(!ctx->altivec_enabled)) { \
6085 gen_exception(ctx, POWERPC_EXCP_VPU); \
6088 gen_set_access_type(ctx, ACCESS_INT); \
6089 EA = tcg_temp_new(); \
6090 gen_addr_reg_index(ctx, EA); \
6091 tcg_gen_andi_tl(EA, EA, ~0xf); \
6092 if (ctx->le_mode) { \
6093 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6094 tcg_gen_addi_tl(EA, EA, 8); \
6095 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6097 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6098 tcg_gen_addi_tl(EA, EA, 8); \
6099 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6101 tcg_temp_free(EA); \
6104 GEN_VR_LDX(lvx
, 0x07, 0x03);
6105 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6106 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
6108 GEN_VR_STX(svx
, 0x07, 0x07);
6109 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6110 GEN_VR_STX(svxl
, 0x07, 0x0F);
6112 /*** SPE extension ***/
6113 /* Register moves */
6115 static always_inline
void gen_load_gpr64(TCGv_i64 t
, int reg
) {
6116 #if defined(TARGET_PPC64)
6117 tcg_gen_mov_i64(t
, cpu_gpr
[reg
]);
6119 tcg_gen_concat_i32_i64(t
, cpu_gpr
[reg
], cpu_gprh
[reg
]);
6123 static always_inline
void gen_store_gpr64(int reg
, TCGv_i64 t
) {
6124 #if defined(TARGET_PPC64)
6125 tcg_gen_mov_i64(cpu_gpr
[reg
], t
);
6127 TCGv_i64 tmp
= tcg_temp_new_i64();
6128 tcg_gen_trunc_i64_i32(cpu_gpr
[reg
], t
);
6129 tcg_gen_shri_i64(tmp
, t
, 32);
6130 tcg_gen_trunc_i64_i32(cpu_gprh
[reg
], tmp
);
6131 tcg_temp_free_i64(tmp
);
6135 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6136 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6138 if (Rc(ctx->opcode)) \
6144 /* Handler for undefined SPE opcodes */
6145 static always_inline
void gen_speundef (DisasContext
*ctx
)
6147 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6151 #if defined(TARGET_PPC64)
6152 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6153 static always_inline void gen_##name (DisasContext *ctx) \
6155 if (unlikely(!ctx->spe_enabled)) { \
6156 gen_exception(ctx, POWERPC_EXCP_APU); \
6159 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6160 cpu_gpr[rB(ctx->opcode)]); \
6163 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6164 static always_inline void gen_##name (DisasContext *ctx) \
6166 if (unlikely(!ctx->spe_enabled)) { \
6167 gen_exception(ctx, POWERPC_EXCP_APU); \
6170 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6171 cpu_gpr[rB(ctx->opcode)]); \
6172 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6173 cpu_gprh[rB(ctx->opcode)]); \
6177 GEN_SPEOP_LOGIC2(evand
, tcg_gen_and_tl
);
6178 GEN_SPEOP_LOGIC2(evandc
, tcg_gen_andc_tl
);
6179 GEN_SPEOP_LOGIC2(evxor
, tcg_gen_xor_tl
);
6180 GEN_SPEOP_LOGIC2(evor
, tcg_gen_or_tl
);
6181 GEN_SPEOP_LOGIC2(evnor
, tcg_gen_nor_tl
);
6182 GEN_SPEOP_LOGIC2(eveqv
, tcg_gen_eqv_tl
);
6183 GEN_SPEOP_LOGIC2(evorc
, tcg_gen_orc_tl
);
6184 GEN_SPEOP_LOGIC2(evnand
, tcg_gen_nand_tl
);
6186 /* SPE logic immediate */
6187 #if defined(TARGET_PPC64)
6188 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6189 static always_inline void gen_##name (DisasContext *ctx) \
6191 if (unlikely(!ctx->spe_enabled)) { \
6192 gen_exception(ctx, POWERPC_EXCP_APU); \
6195 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6196 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6197 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6198 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6199 tcg_opi(t0, t0, rB(ctx->opcode)); \
6200 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6201 tcg_gen_trunc_i64_i32(t1, t2); \
6202 tcg_temp_free_i64(t2); \
6203 tcg_opi(t1, t1, rB(ctx->opcode)); \
6204 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6205 tcg_temp_free_i32(t0); \
6206 tcg_temp_free_i32(t1); \
6209 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6210 static always_inline void gen_##name (DisasContext *ctx) \
6212 if (unlikely(!ctx->spe_enabled)) { \
6213 gen_exception(ctx, POWERPC_EXCP_APU); \
6216 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6218 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6222 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi
, tcg_gen_shli_i32
);
6223 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu
, tcg_gen_shri_i32
);
6224 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis
, tcg_gen_sari_i32
);
6225 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi
, tcg_gen_rotli_i32
);
6227 /* SPE arithmetic */
6228 #if defined(TARGET_PPC64)
6229 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6230 static always_inline void gen_##name (DisasContext *ctx) \
6232 if (unlikely(!ctx->spe_enabled)) { \
6233 gen_exception(ctx, POWERPC_EXCP_APU); \
6236 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6237 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6238 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6239 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6241 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6242 tcg_gen_trunc_i64_i32(t1, t2); \
6243 tcg_temp_free_i64(t2); \
6245 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6246 tcg_temp_free_i32(t0); \
6247 tcg_temp_free_i32(t1); \
6250 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6251 static always_inline void gen_##name (DisasContext *ctx) \
6253 if (unlikely(!ctx->spe_enabled)) { \
6254 gen_exception(ctx, POWERPC_EXCP_APU); \
6257 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6258 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6262 static always_inline
void gen_op_evabs (TCGv_i32 ret
, TCGv_i32 arg1
)
6264 int l1
= gen_new_label();
6265 int l2
= gen_new_label();
6267 tcg_gen_brcondi_i32(TCG_COND_GE
, arg1
, 0, l1
);
6268 tcg_gen_neg_i32(ret
, arg1
);
6271 tcg_gen_mov_i32(ret
, arg1
);
6274 GEN_SPEOP_ARITH1(evabs
, gen_op_evabs
);
6275 GEN_SPEOP_ARITH1(evneg
, tcg_gen_neg_i32
);
6276 GEN_SPEOP_ARITH1(evextsb
, tcg_gen_ext8s_i32
);
6277 GEN_SPEOP_ARITH1(evextsh
, tcg_gen_ext16s_i32
);
6278 static always_inline
void gen_op_evrndw (TCGv_i32 ret
, TCGv_i32 arg1
)
6280 tcg_gen_addi_i32(ret
, arg1
, 0x8000);
6281 tcg_gen_ext16u_i32(ret
, ret
);
6283 GEN_SPEOP_ARITH1(evrndw
, gen_op_evrndw
);
6284 GEN_SPEOP_ARITH1(evcntlsw
, gen_helper_cntlsw32
);
6285 GEN_SPEOP_ARITH1(evcntlzw
, gen_helper_cntlzw32
);
6287 #if defined(TARGET_PPC64)
6288 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6289 static always_inline void gen_##name (DisasContext *ctx) \
6291 if (unlikely(!ctx->spe_enabled)) { \
6292 gen_exception(ctx, POWERPC_EXCP_APU); \
6295 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6296 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6297 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6298 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
6299 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6300 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6301 tcg_op(t0, t0, t2); \
6302 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6303 tcg_gen_trunc_i64_i32(t1, t3); \
6304 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6305 tcg_gen_trunc_i64_i32(t2, t3); \
6306 tcg_temp_free_i64(t3); \
6307 tcg_op(t1, t1, t2); \
6308 tcg_temp_free_i32(t2); \
6309 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6310 tcg_temp_free_i32(t0); \
6311 tcg_temp_free_i32(t1); \
6314 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6315 static always_inline void gen_##name (DisasContext *ctx) \
6317 if (unlikely(!ctx->spe_enabled)) { \
6318 gen_exception(ctx, POWERPC_EXCP_APU); \
6321 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6322 cpu_gpr[rB(ctx->opcode)]); \
6323 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6324 cpu_gprh[rB(ctx->opcode)]); \
6328 static always_inline
void gen_op_evsrwu (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
6333 l1
= gen_new_label();
6334 l2
= gen_new_label();
6335 t0
= tcg_temp_local_new_i32();
6336 /* No error here: 6 bits are used */
6337 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
6338 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
6339 tcg_gen_shr_i32(ret
, arg1
, t0
);
6342 tcg_gen_movi_i32(ret
, 0);
6344 tcg_temp_free_i32(t0
);
6346 GEN_SPEOP_ARITH2(evsrwu
, gen_op_evsrwu
);
6347 static always_inline
void gen_op_evsrws (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
6352 l1
= gen_new_label();
6353 l2
= gen_new_label();
6354 t0
= tcg_temp_local_new_i32();
6355 /* No error here: 6 bits are used */
6356 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
6357 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
6358 tcg_gen_sar_i32(ret
, arg1
, t0
);
6361 tcg_gen_movi_i32(ret
, 0);
6363 tcg_temp_free_i32(t0
);
6365 GEN_SPEOP_ARITH2(evsrws
, gen_op_evsrws
);
6366 static always_inline
void gen_op_evslw (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
6371 l1
= gen_new_label();
6372 l2
= gen_new_label();
6373 t0
= tcg_temp_local_new_i32();
6374 /* No error here: 6 bits are used */
6375 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
6376 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
6377 tcg_gen_shl_i32(ret
, arg1
, t0
);
6380 tcg_gen_movi_i32(ret
, 0);
6382 tcg_temp_free_i32(t0
);
6384 GEN_SPEOP_ARITH2(evslw
, gen_op_evslw
);
6385 static always_inline
void gen_op_evrlw (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
6387 TCGv_i32 t0
= tcg_temp_new_i32();
6388 tcg_gen_andi_i32(t0
, arg2
, 0x1F);
6389 tcg_gen_rotl_i32(ret
, arg1
, t0
);
6390 tcg_temp_free_i32(t0
);
6392 GEN_SPEOP_ARITH2(evrlw
, gen_op_evrlw
);
6393 static always_inline
void gen_evmergehi (DisasContext
*ctx
)
6395 if (unlikely(!ctx
->spe_enabled
)) {
6396 gen_exception(ctx
, POWERPC_EXCP_APU
);
6399 #if defined(TARGET_PPC64)
6400 TCGv t0
= tcg_temp_new();
6401 TCGv t1
= tcg_temp_new();
6402 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
6403 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
6404 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
6408 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
6409 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
6412 GEN_SPEOP_ARITH2(evaddw
, tcg_gen_add_i32
);
6413 static always_inline
void gen_op_evsubf (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
6415 tcg_gen_sub_i32(ret
, arg2
, arg1
);
6417 GEN_SPEOP_ARITH2(evsubfw
, gen_op_evsubf
);
6419 /* SPE arithmetic immediate */
6420 #if defined(TARGET_PPC64)
6421 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6422 static always_inline void gen_##name (DisasContext *ctx) \
6424 if (unlikely(!ctx->spe_enabled)) { \
6425 gen_exception(ctx, POWERPC_EXCP_APU); \
6428 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6429 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6430 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6431 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6432 tcg_op(t0, t0, rA(ctx->opcode)); \
6433 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6434 tcg_gen_trunc_i64_i32(t1, t2); \
6435 tcg_temp_free_i64(t2); \
6436 tcg_op(t1, t1, rA(ctx->opcode)); \
6437 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6438 tcg_temp_free_i32(t0); \
6439 tcg_temp_free_i32(t1); \
6442 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6443 static always_inline void gen_##name (DisasContext *ctx) \
6445 if (unlikely(!ctx->spe_enabled)) { \
6446 gen_exception(ctx, POWERPC_EXCP_APU); \
6449 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6451 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6455 GEN_SPEOP_ARITH_IMM2(evaddiw
, tcg_gen_addi_i32
);
6456 GEN_SPEOP_ARITH_IMM2(evsubifw
, tcg_gen_subi_i32
);
6458 /* SPE comparison */
6459 #if defined(TARGET_PPC64)
6460 #define GEN_SPEOP_COMP(name, tcg_cond) \
6461 static always_inline void gen_##name (DisasContext *ctx) \
6463 if (unlikely(!ctx->spe_enabled)) { \
6464 gen_exception(ctx, POWERPC_EXCP_APU); \
6467 int l1 = gen_new_label(); \
6468 int l2 = gen_new_label(); \
6469 int l3 = gen_new_label(); \
6470 int l4 = gen_new_label(); \
6471 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6472 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6473 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6474 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6475 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6476 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6477 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6479 gen_set_label(l1); \
6480 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6481 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6482 gen_set_label(l2); \
6483 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6484 tcg_gen_trunc_i64_i32(t0, t2); \
6485 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6486 tcg_gen_trunc_i64_i32(t1, t2); \
6487 tcg_temp_free_i64(t2); \
6488 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6489 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6490 ~(CRF_CH | CRF_CH_AND_CL)); \
6492 gen_set_label(l3); \
6493 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6494 CRF_CH | CRF_CH_OR_CL); \
6495 gen_set_label(l4); \
6496 tcg_temp_free_i32(t0); \
6497 tcg_temp_free_i32(t1); \
6500 #define GEN_SPEOP_COMP(name, tcg_cond) \
6501 static always_inline void gen_##name (DisasContext *ctx) \
6503 if (unlikely(!ctx->spe_enabled)) { \
6504 gen_exception(ctx, POWERPC_EXCP_APU); \
6507 int l1 = gen_new_label(); \
6508 int l2 = gen_new_label(); \
6509 int l3 = gen_new_label(); \
6510 int l4 = gen_new_label(); \
6512 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6513 cpu_gpr[rB(ctx->opcode)], l1); \
6514 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6516 gen_set_label(l1); \
6517 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6518 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6519 gen_set_label(l2); \
6520 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6521 cpu_gprh[rB(ctx->opcode)], l3); \
6522 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6523 ~(CRF_CH | CRF_CH_AND_CL)); \
6525 gen_set_label(l3); \
6526 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6527 CRF_CH | CRF_CH_OR_CL); \
6528 gen_set_label(l4); \
6531 GEN_SPEOP_COMP(evcmpgtu
, TCG_COND_GTU
);
6532 GEN_SPEOP_COMP(evcmpgts
, TCG_COND_GT
);
6533 GEN_SPEOP_COMP(evcmpltu
, TCG_COND_LTU
);
6534 GEN_SPEOP_COMP(evcmplts
, TCG_COND_LT
);
6535 GEN_SPEOP_COMP(evcmpeq
, TCG_COND_EQ
);
6538 static always_inline
void gen_brinc (DisasContext
*ctx
)
6540 /* Note: brinc is usable even if SPE is disabled */
6541 gen_helper_brinc(cpu_gpr
[rD(ctx
->opcode
)],
6542 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
6544 static always_inline
void gen_evmergelo (DisasContext
*ctx
)
6546 if (unlikely(!ctx
->spe_enabled
)) {
6547 gen_exception(ctx
, POWERPC_EXCP_APU
);
6550 #if defined(TARGET_PPC64)
6551 TCGv t0
= tcg_temp_new();
6552 TCGv t1
= tcg_temp_new();
6553 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x00000000FFFFFFFFLL
);
6554 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
6555 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
6559 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
6560 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6563 static always_inline
void gen_evmergehilo (DisasContext
*ctx
)
6565 if (unlikely(!ctx
->spe_enabled
)) {
6566 gen_exception(ctx
, POWERPC_EXCP_APU
);
6569 #if defined(TARGET_PPC64)
6570 TCGv t0
= tcg_temp_new();
6571 TCGv t1
= tcg_temp_new();
6572 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x00000000FFFFFFFFLL
);
6573 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
6574 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
6578 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
6579 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
6582 static always_inline
void gen_evmergelohi (DisasContext
*ctx
)
6584 if (unlikely(!ctx
->spe_enabled
)) {
6585 gen_exception(ctx
, POWERPC_EXCP_APU
);
6588 #if defined(TARGET_PPC64)
6589 TCGv t0
= tcg_temp_new();
6590 TCGv t1
= tcg_temp_new();
6591 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
6592 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
6593 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
6597 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
6598 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6601 static always_inline
void gen_evsplati (DisasContext
*ctx
)
6603 uint64_t imm
= ((int32_t)(rA(ctx
->opcode
) << 11)) >> 27;
6605 #if defined(TARGET_PPC64)
6606 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
6608 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
6609 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
6612 static always_inline
void gen_evsplatfi (DisasContext
*ctx
)
6614 uint64_t imm
= rA(ctx
->opcode
) << 11;
6616 #if defined(TARGET_PPC64)
6617 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
6619 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
6620 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
6624 static always_inline
void gen_evsel (DisasContext
*ctx
)
6626 int l1
= gen_new_label();
6627 int l2
= gen_new_label();
6628 int l3
= gen_new_label();
6629 int l4
= gen_new_label();
6630 TCGv_i32 t0
= tcg_temp_local_new_i32();
6631 #if defined(TARGET_PPC64)
6632 TCGv t1
= tcg_temp_local_new();
6633 TCGv t2
= tcg_temp_local_new();
6635 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 3);
6636 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
6637 #if defined(TARGET_PPC64)
6638 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
6640 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
6644 #if defined(TARGET_PPC64)
6645 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
6647 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
6650 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 2);
6651 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l3
);
6652 #if defined(TARGET_PPC64)
6653 tcg_gen_andi_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], 0x00000000FFFFFFFFULL
);
6655 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6659 #if defined(TARGET_PPC64)
6660 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x00000000FFFFFFFFULL
);
6662 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
6665 tcg_temp_free_i32(t0
);
6666 #if defined(TARGET_PPC64)
6667 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
, t2
);
6672 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
)
6676 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
)
6680 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
)
6684 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
)
6689 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, PPC_SPE
); ////
6690 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, PPC_SPE
);
6691 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, PPC_SPE
); ////
6692 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, PPC_SPE
);
6693 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, PPC_SPE
); ////
6694 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, PPC_SPE
); ////
6695 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, PPC_SPE
); ////
6696 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x00000000, PPC_SPE
); //
6697 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0x00000000, PPC_SPE
); ////
6698 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, PPC_SPE
); ////
6699 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, PPC_SPE
); ////
6700 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, PPC_SPE
); ////
6701 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0x00000000, PPC_SPE
); ////
6702 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, PPC_SPE
); ////
6703 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, PPC_SPE
); ////
6704 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, PPC_SPE
);
6705 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, PPC_SPE
); ////
6706 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, PPC_SPE
);
6707 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, PPC_SPE
); //
6708 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, PPC_SPE
);
6709 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, PPC_SPE
); ////
6710 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, PPC_SPE
); ////
6711 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, PPC_SPE
); ////
6712 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, PPC_SPE
); ////
6713 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, PPC_SPE
); ////
6715 /* SPE load and stores */
6716 static always_inline
void gen_addr_spe_imm_index (DisasContext
*ctx
, TCGv EA
, int sh
)
6718 target_ulong uimm
= rB(ctx
->opcode
);
6720 if (rA(ctx
->opcode
) == 0) {
6721 tcg_gen_movi_tl(EA
, uimm
<< sh
);
6723 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], uimm
<< sh
);
6724 #if defined(TARGET_PPC64)
6725 if (!ctx
->sf_mode
) {
6726 tcg_gen_ext32u_tl(EA
, EA
);
6732 static always_inline
void gen_op_evldd(DisasContext
*ctx
, TCGv addr
)
6734 #if defined(TARGET_PPC64)
6735 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
6737 TCGv_i64 t0
= tcg_temp_new_i64();
6738 gen_qemu_ld64(ctx
, t0
, addr
);
6739 tcg_gen_trunc_i64_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
6740 tcg_gen_shri_i64(t0
, t0
, 32);
6741 tcg_gen_trunc_i64_i32(cpu_gprh
[rD(ctx
->opcode
)], t0
);
6742 tcg_temp_free_i64(t0
);
6746 static always_inline
void gen_op_evldw(DisasContext
*ctx
, TCGv addr
)
6748 #if defined(TARGET_PPC64)
6749 TCGv t0
= tcg_temp_new();
6750 gen_qemu_ld32u(ctx
, t0
, addr
);
6751 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
6752 gen_addr_add(ctx
, addr
, addr
, 4);
6753 gen_qemu_ld32u(ctx
, t0
, addr
);
6754 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6757 gen_qemu_ld32u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
6758 gen_addr_add(ctx
, addr
, addr
, 4);
6759 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
6763 static always_inline
void gen_op_evldh(DisasContext
*ctx
, TCGv addr
)
6765 TCGv t0
= tcg_temp_new();
6766 #if defined(TARGET_PPC64)
6767 gen_qemu_ld16u(ctx
, t0
, addr
);
6768 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
6769 gen_addr_add(ctx
, addr
, addr
, 2);
6770 gen_qemu_ld16u(ctx
, t0
, addr
);
6771 tcg_gen_shli_tl(t0
, t0
, 32);
6772 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6773 gen_addr_add(ctx
, addr
, addr
, 2);
6774 gen_qemu_ld16u(ctx
, t0
, addr
);
6775 tcg_gen_shli_tl(t0
, t0
, 16);
6776 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6777 gen_addr_add(ctx
, addr
, addr
, 2);
6778 gen_qemu_ld16u(ctx
, t0
, addr
);
6779 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6781 gen_qemu_ld16u(ctx
, t0
, addr
);
6782 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
6783 gen_addr_add(ctx
, addr
, addr
, 2);
6784 gen_qemu_ld16u(ctx
, t0
, addr
);
6785 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
6786 gen_addr_add(ctx
, addr
, addr
, 2);
6787 gen_qemu_ld16u(ctx
, t0
, addr
);
6788 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
6789 gen_addr_add(ctx
, addr
, addr
, 2);
6790 gen_qemu_ld16u(ctx
, t0
, addr
);
6791 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6796 static always_inline
void gen_op_evlhhesplat(DisasContext
*ctx
, TCGv addr
)
6798 TCGv t0
= tcg_temp_new();
6799 gen_qemu_ld16u(ctx
, t0
, addr
);
6800 #if defined(TARGET_PPC64)
6801 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
6802 tcg_gen_shli_tl(t0
, t0
, 16);
6803 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6805 tcg_gen_shli_tl(t0
, t0
, 16);
6806 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
6807 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
6812 static always_inline
void gen_op_evlhhousplat(DisasContext
*ctx
, TCGv addr
)
6814 TCGv t0
= tcg_temp_new();
6815 gen_qemu_ld16u(ctx
, t0
, addr
);
6816 #if defined(TARGET_PPC64)
6817 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
6818 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6820 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
6821 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
6826 static always_inline
void gen_op_evlhhossplat(DisasContext
*ctx
, TCGv addr
)
6828 TCGv t0
= tcg_temp_new();
6829 gen_qemu_ld16s(ctx
, t0
, addr
);
6830 #if defined(TARGET_PPC64)
6831 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
6832 tcg_gen_ext32u_tl(t0
, t0
);
6833 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6835 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
6836 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
6841 static always_inline
void gen_op_evlwhe(DisasContext
*ctx
, TCGv addr
)
6843 TCGv t0
= tcg_temp_new();
6844 #if defined(TARGET_PPC64)
6845 gen_qemu_ld16u(ctx
, t0
, addr
);
6846 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
6847 gen_addr_add(ctx
, addr
, addr
, 2);
6848 gen_qemu_ld16u(ctx
, t0
, addr
);
6849 tcg_gen_shli_tl(t0
, t0
, 16);
6850 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6852 gen_qemu_ld16u(ctx
, t0
, addr
);
6853 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
6854 gen_addr_add(ctx
, addr
, addr
, 2);
6855 gen_qemu_ld16u(ctx
, t0
, addr
);
6856 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
6861 static always_inline
void gen_op_evlwhou(DisasContext
*ctx
, TCGv addr
)
6863 #if defined(TARGET_PPC64)
6864 TCGv t0
= tcg_temp_new();
6865 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
6866 gen_addr_add(ctx
, addr
, addr
, 2);
6867 gen_qemu_ld16u(ctx
, t0
, addr
);
6868 tcg_gen_shli_tl(t0
, t0
, 32);
6869 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6872 gen_qemu_ld16u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
6873 gen_addr_add(ctx
, addr
, addr
, 2);
6874 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
6878 static always_inline
void gen_op_evlwhos(DisasContext
*ctx
, TCGv addr
)
6880 #if defined(TARGET_PPC64)
6881 TCGv t0
= tcg_temp_new();
6882 gen_qemu_ld16s(ctx
, t0
, addr
);
6883 tcg_gen_ext32u_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
6884 gen_addr_add(ctx
, addr
, addr
, 2);
6885 gen_qemu_ld16s(ctx
, t0
, addr
);
6886 tcg_gen_shli_tl(t0
, t0
, 32);
6887 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6890 gen_qemu_ld16s(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
6891 gen_addr_add(ctx
, addr
, addr
, 2);
6892 gen_qemu_ld16s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
6896 static always_inline
void gen_op_evlwwsplat(DisasContext
*ctx
, TCGv addr
)
6898 TCGv t0
= tcg_temp_new();
6899 gen_qemu_ld32u(ctx
, t0
, addr
);
6900 #if defined(TARGET_PPC64)
6901 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
6902 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6904 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
6905 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
6910 static always_inline
void gen_op_evlwhsplat(DisasContext
*ctx
, TCGv addr
)
6912 TCGv t0
= tcg_temp_new();
6913 #if defined(TARGET_PPC64)
6914 gen_qemu_ld16u(ctx
, t0
, addr
);
6915 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
6916 tcg_gen_shli_tl(t0
, t0
, 32);
6917 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6918 gen_addr_add(ctx
, addr
, addr
, 2);
6919 gen_qemu_ld16u(ctx
, t0
, addr
);
6920 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6921 tcg_gen_shli_tl(t0
, t0
, 16);
6922 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
6924 gen_qemu_ld16u(ctx
, t0
, addr
);
6925 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
6926 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
6927 gen_addr_add(ctx
, addr
, addr
, 2);
6928 gen_qemu_ld16u(ctx
, t0
, addr
);
6929 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
6930 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
6935 static always_inline
void gen_op_evstdd(DisasContext
*ctx
, TCGv addr
)
6937 #if defined(TARGET_PPC64)
6938 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
6940 TCGv_i64 t0
= tcg_temp_new_i64();
6941 tcg_gen_concat_i32_i64(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gprh
[rS(ctx
->opcode
)]);
6942 gen_qemu_st64(ctx
, t0
, addr
);
6943 tcg_temp_free_i64(t0
);
6947 static always_inline
void gen_op_evstdw(DisasContext
*ctx
, TCGv addr
)
6949 #if defined(TARGET_PPC64)
6950 TCGv t0
= tcg_temp_new();
6951 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
6952 gen_qemu_st32(ctx
, t0
, addr
);
6955 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
6957 gen_addr_add(ctx
, addr
, addr
, 4);
6958 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
6961 static always_inline
void gen_op_evstdh(DisasContext
*ctx
, TCGv addr
)
6963 TCGv t0
= tcg_temp_new();
6964 #if defined(TARGET_PPC64)
6965 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
6967 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
6969 gen_qemu_st16(ctx
, t0
, addr
);
6970 gen_addr_add(ctx
, addr
, addr
, 2);
6971 #if defined(TARGET_PPC64)
6972 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
6973 gen_qemu_st16(ctx
, t0
, addr
);
6975 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
6977 gen_addr_add(ctx
, addr
, addr
, 2);
6978 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
6979 gen_qemu_st16(ctx
, t0
, addr
);
6981 gen_addr_add(ctx
, addr
, addr
, 2);
6982 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
6985 static always_inline
void gen_op_evstwhe(DisasContext
*ctx
, TCGv addr
)
6987 TCGv t0
= tcg_temp_new();
6988 #if defined(TARGET_PPC64)
6989 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
6991 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
6993 gen_qemu_st16(ctx
, t0
, addr
);
6994 gen_addr_add(ctx
, addr
, addr
, 2);
6995 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
6996 gen_qemu_st16(ctx
, t0
, addr
);
7000 static always_inline
void gen_op_evstwho(DisasContext
*ctx
, TCGv addr
)
7002 #if defined(TARGET_PPC64)
7003 TCGv t0
= tcg_temp_new();
7004 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7005 gen_qemu_st16(ctx
, t0
, addr
);
7008 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7010 gen_addr_add(ctx
, addr
, addr
, 2);
7011 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7014 static always_inline
void gen_op_evstwwe(DisasContext
*ctx
, TCGv addr
)
7016 #if defined(TARGET_PPC64)
7017 TCGv t0
= tcg_temp_new();
7018 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7019 gen_qemu_st32(ctx
, t0
, addr
);
7022 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7026 static always_inline
void gen_op_evstwwo(DisasContext
*ctx
, TCGv addr
)
7028 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7031 #define GEN_SPEOP_LDST(name, opc2, sh) \
7032 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7035 if (unlikely(!ctx->spe_enabled)) { \
7036 gen_exception(ctx, POWERPC_EXCP_APU); \
7039 gen_set_access_type(ctx, ACCESS_INT); \
7040 t0 = tcg_temp_new(); \
7041 if (Rc(ctx->opcode)) { \
7042 gen_addr_spe_imm_index(ctx, t0, sh); \
7044 gen_addr_reg_index(ctx, t0); \
7046 gen_op_##name(ctx, t0); \
7047 tcg_temp_free(t0); \
7050 GEN_SPEOP_LDST(evldd
, 0x00, 3);
7051 GEN_SPEOP_LDST(evldw
, 0x01, 3);
7052 GEN_SPEOP_LDST(evldh
, 0x02, 3);
7053 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1);
7054 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1);
7055 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1);
7056 GEN_SPEOP_LDST(evlwhe
, 0x08, 2);
7057 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2);
7058 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2);
7059 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2);
7060 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2);
7062 GEN_SPEOP_LDST(evstdd
, 0x10, 3);
7063 GEN_SPEOP_LDST(evstdw
, 0x11, 3);
7064 GEN_SPEOP_LDST(evstdh
, 0x12, 3);
7065 GEN_SPEOP_LDST(evstwhe
, 0x18, 2);
7066 GEN_SPEOP_LDST(evstwho
, 0x1A, 2);
7067 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2);
7068 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2);
7070 /* Multiply and add - TODO */
7072 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0x00000000, PPC_SPE
);
7073 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0x00000000, PPC_SPE
);
7074 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, PPC_SPE
);
7075 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0x00000000, PPC_SPE
);
7076 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, PPC_SPE
);
7077 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0x00000000, PPC_SPE
);
7078 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0x00000000, PPC_SPE
);
7079 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0x00000000, PPC_SPE
);
7080 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, PPC_SPE
);
7081 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0x00000000, PPC_SPE
);
7082 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, PPC_SPE
);
7083 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0x00000000, PPC_SPE
);
7085 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0x00000000, PPC_SPE
);
7086 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, PPC_SPE
);
7087 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, PPC_SPE
);
7088 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0x00000000, PPC_SPE
);
7089 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0x00000000, PPC_SPE
);
7090 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, PPC_SPE
);
7091 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0x00000000, PPC_SPE
);
7092 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0x00000000, PPC_SPE
);
7093 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, PPC_SPE
);
7094 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, PPC_SPE
);
7095 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0x00000000, PPC_SPE
);
7096 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0x00000000, PPC_SPE
);
7097 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, PPC_SPE
);
7098 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0x00000000, PPC_SPE
);
7100 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, PPC_SPE
);
7101 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, PPC_SPE
);
7102 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, PPC_SPE
);
7103 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, PPC_SPE
);
7104 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, PPC_SPE
);
7105 GEN_SPE(evmra
, speundef
, 0x07, 0x13, 0x0000F800, PPC_SPE
);
7107 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, PPC_SPE
);
7108 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0x00000000, PPC_SPE
);
7109 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, PPC_SPE
);
7110 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0x00000000, PPC_SPE
);
7111 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, PPC_SPE
);
7112 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0x00000000, PPC_SPE
);
7113 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, PPC_SPE
);
7114 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0x00000000, PPC_SPE
);
7115 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, PPC_SPE
);
7116 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0x00000000, PPC_SPE
);
7117 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, PPC_SPE
);
7118 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0x00000000, PPC_SPE
);
7120 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, PPC_SPE
);
7121 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, PPC_SPE
);
7122 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0x00000000, PPC_SPE
);
7123 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, PPC_SPE
);
7124 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0x00000000, PPC_SPE
);
7126 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, PPC_SPE
);
7127 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0x00000000, PPC_SPE
);
7128 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, PPC_SPE
);
7129 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0x00000000, PPC_SPE
);
7130 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, PPC_SPE
);
7131 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0x00000000, PPC_SPE
);
7132 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, PPC_SPE
);
7133 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0x00000000, PPC_SPE
);
7134 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, PPC_SPE
);
7135 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0x00000000, PPC_SPE
);
7136 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, PPC_SPE
);
7137 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0x00000000, PPC_SPE
);
7139 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, PPC_SPE
);
7140 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, PPC_SPE
);
7141 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0x00000000, PPC_SPE
);
7142 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, PPC_SPE
);
7143 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0x00000000, PPC_SPE
);
7146 /*** SPE floating-point extension ***/
7147 #if defined(TARGET_PPC64)
7148 #define GEN_SPEFPUOP_CONV_32_32(name) \
7149 static always_inline void gen_##name (DisasContext *ctx) \
7153 t0 = tcg_temp_new_i32(); \
7154 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7155 gen_helper_##name(t0, t0); \
7156 t1 = tcg_temp_new(); \
7157 tcg_gen_extu_i32_tl(t1, t0); \
7158 tcg_temp_free_i32(t0); \
7159 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7160 0xFFFFFFFF00000000ULL); \
7161 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7162 tcg_temp_free(t1); \
7164 #define GEN_SPEFPUOP_CONV_32_64(name) \
7165 static always_inline void gen_##name (DisasContext *ctx) \
7169 t0 = tcg_temp_new_i32(); \
7170 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7171 t1 = tcg_temp_new(); \
7172 tcg_gen_extu_i32_tl(t1, t0); \
7173 tcg_temp_free_i32(t0); \
7174 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7175 0xFFFFFFFF00000000ULL); \
7176 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7177 tcg_temp_free(t1); \
7179 #define GEN_SPEFPUOP_CONV_64_32(name) \
7180 static always_inline void gen_##name (DisasContext *ctx) \
7182 TCGv_i32 t0 = tcg_temp_new_i32(); \
7183 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7184 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7185 tcg_temp_free_i32(t0); \
7187 #define GEN_SPEFPUOP_CONV_64_64(name) \
7188 static always_inline void gen_##name (DisasContext *ctx) \
7190 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7192 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7193 static always_inline void gen_##name (DisasContext *ctx) \
7197 if (unlikely(!ctx->spe_enabled)) { \
7198 gen_exception(ctx, POWERPC_EXCP_APU); \
7201 t0 = tcg_temp_new_i32(); \
7202 t1 = tcg_temp_new_i32(); \
7203 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7204 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7205 gen_helper_##name(t0, t0, t1); \
7206 tcg_temp_free_i32(t1); \
7207 t2 = tcg_temp_new(); \
7208 tcg_gen_extu_i32_tl(t2, t0); \
7209 tcg_temp_free_i32(t0); \
7210 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7211 0xFFFFFFFF00000000ULL); \
7212 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7213 tcg_temp_free(t2); \
7215 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7216 static always_inline void gen_##name (DisasContext *ctx) \
7218 if (unlikely(!ctx->spe_enabled)) { \
7219 gen_exception(ctx, POWERPC_EXCP_APU); \
7222 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7223 cpu_gpr[rB(ctx->opcode)]); \
7225 #define GEN_SPEFPUOP_COMP_32(name) \
7226 static always_inline void gen_##name (DisasContext *ctx) \
7229 if (unlikely(!ctx->spe_enabled)) { \
7230 gen_exception(ctx, POWERPC_EXCP_APU); \
7233 t0 = tcg_temp_new_i32(); \
7234 t1 = tcg_temp_new_i32(); \
7235 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7236 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7237 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7238 tcg_temp_free_i32(t0); \
7239 tcg_temp_free_i32(t1); \
7241 #define GEN_SPEFPUOP_COMP_64(name) \
7242 static always_inline void gen_##name (DisasContext *ctx) \
7244 if (unlikely(!ctx->spe_enabled)) { \
7245 gen_exception(ctx, POWERPC_EXCP_APU); \
7248 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7249 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7252 #define GEN_SPEFPUOP_CONV_32_32(name) \
7253 static always_inline void gen_##name (DisasContext *ctx) \
7255 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7257 #define GEN_SPEFPUOP_CONV_32_64(name) \
7258 static always_inline void gen_##name (DisasContext *ctx) \
7260 TCGv_i64 t0 = tcg_temp_new_i64(); \
7261 gen_load_gpr64(t0, rB(ctx->opcode)); \
7262 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7263 tcg_temp_free_i64(t0); \
7265 #define GEN_SPEFPUOP_CONV_64_32(name) \
7266 static always_inline void gen_##name (DisasContext *ctx) \
7268 TCGv_i64 t0 = tcg_temp_new_i64(); \
7269 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7270 gen_store_gpr64(rD(ctx->opcode), t0); \
7271 tcg_temp_free_i64(t0); \
7273 #define GEN_SPEFPUOP_CONV_64_64(name) \
7274 static always_inline void gen_##name (DisasContext *ctx) \
7276 TCGv_i64 t0 = tcg_temp_new_i64(); \
7277 gen_load_gpr64(t0, rB(ctx->opcode)); \
7278 gen_helper_##name(t0, t0); \
7279 gen_store_gpr64(rD(ctx->opcode), t0); \
7280 tcg_temp_free_i64(t0); \
7282 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7283 static always_inline void gen_##name (DisasContext *ctx) \
7285 if (unlikely(!ctx->spe_enabled)) { \
7286 gen_exception(ctx, POWERPC_EXCP_APU); \
7289 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7290 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7292 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7293 static always_inline void gen_##name (DisasContext *ctx) \
7296 if (unlikely(!ctx->spe_enabled)) { \
7297 gen_exception(ctx, POWERPC_EXCP_APU); \
7300 t0 = tcg_temp_new_i64(); \
7301 t1 = tcg_temp_new_i64(); \
7302 gen_load_gpr64(t0, rA(ctx->opcode)); \
7303 gen_load_gpr64(t1, rB(ctx->opcode)); \
7304 gen_helper_##name(t0, t0, t1); \
7305 gen_store_gpr64(rD(ctx->opcode), t0); \
7306 tcg_temp_free_i64(t0); \
7307 tcg_temp_free_i64(t1); \
7309 #define GEN_SPEFPUOP_COMP_32(name) \
7310 static always_inline void gen_##name (DisasContext *ctx) \
7312 if (unlikely(!ctx->spe_enabled)) { \
7313 gen_exception(ctx, POWERPC_EXCP_APU); \
7316 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7317 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7319 #define GEN_SPEFPUOP_COMP_64(name) \
7320 static always_inline void gen_##name (DisasContext *ctx) \
7323 if (unlikely(!ctx->spe_enabled)) { \
7324 gen_exception(ctx, POWERPC_EXCP_APU); \
7327 t0 = tcg_temp_new_i64(); \
7328 t1 = tcg_temp_new_i64(); \
7329 gen_load_gpr64(t0, rA(ctx->opcode)); \
7330 gen_load_gpr64(t1, rB(ctx->opcode)); \
7331 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7332 tcg_temp_free_i64(t0); \
7333 tcg_temp_free_i64(t1); \
7337 /* Single precision floating-point vectors operations */
7339 GEN_SPEFPUOP_ARITH2_64_64(evfsadd
);
7340 GEN_SPEFPUOP_ARITH2_64_64(evfssub
);
7341 GEN_SPEFPUOP_ARITH2_64_64(evfsmul
);
7342 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv
);
7343 static always_inline
void gen_evfsabs (DisasContext
*ctx
)
7345 if (unlikely(!ctx
->spe_enabled
)) {
7346 gen_exception(ctx
, POWERPC_EXCP_APU
);
7349 #if defined(TARGET_PPC64)
7350 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000080000000LL
);
7352 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x80000000);
7353 tcg_gen_andi_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
7356 static always_inline
void gen_evfsnabs (DisasContext
*ctx
)
7358 if (unlikely(!ctx
->spe_enabled
)) {
7359 gen_exception(ctx
, POWERPC_EXCP_APU
);
7362 #if defined(TARGET_PPC64)
7363 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
7365 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
7366 tcg_gen_ori_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
7369 static always_inline
void gen_evfsneg (DisasContext
*ctx
)
7371 if (unlikely(!ctx
->spe_enabled
)) {
7372 gen_exception(ctx
, POWERPC_EXCP_APU
);
7375 #if defined(TARGET_PPC64)
7376 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
7378 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
7379 tcg_gen_xori_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
7384 GEN_SPEFPUOP_CONV_64_64(evfscfui
);
7385 GEN_SPEFPUOP_CONV_64_64(evfscfsi
);
7386 GEN_SPEFPUOP_CONV_64_64(evfscfuf
);
7387 GEN_SPEFPUOP_CONV_64_64(evfscfsf
);
7388 GEN_SPEFPUOP_CONV_64_64(evfsctui
);
7389 GEN_SPEFPUOP_CONV_64_64(evfsctsi
);
7390 GEN_SPEFPUOP_CONV_64_64(evfsctuf
);
7391 GEN_SPEFPUOP_CONV_64_64(evfsctsf
);
7392 GEN_SPEFPUOP_CONV_64_64(evfsctuiz
);
7393 GEN_SPEFPUOP_CONV_64_64(evfsctsiz
);
7396 GEN_SPEFPUOP_COMP_64(evfscmpgt
);
7397 GEN_SPEFPUOP_COMP_64(evfscmplt
);
7398 GEN_SPEFPUOP_COMP_64(evfscmpeq
);
7399 GEN_SPEFPUOP_COMP_64(evfststgt
);
7400 GEN_SPEFPUOP_COMP_64(evfststlt
);
7401 GEN_SPEFPUOP_COMP_64(evfststeq
);
7403 /* Opcodes definitions */
7404 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, PPC_SPEFPU
); //
7405 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU
); //
7406 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU
); //
7407 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, PPC_SPEFPU
); //
7408 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, PPC_SPEFPU
); //
7409 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, PPC_SPEFPU
); //
7410 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, PPC_SPEFPU
); //
7411 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, PPC_SPEFPU
); //
7412 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU
); //
7413 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU
); //
7414 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU
); //
7415 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU
); //
7416 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU
); //
7417 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU
); //
7419 /* Single precision floating-point operations */
7421 GEN_SPEFPUOP_ARITH2_32_32(efsadd
);
7422 GEN_SPEFPUOP_ARITH2_32_32(efssub
);
7423 GEN_SPEFPUOP_ARITH2_32_32(efsmul
);
7424 GEN_SPEFPUOP_ARITH2_32_32(efsdiv
);
7425 static always_inline
void gen_efsabs (DisasContext
*ctx
)
7427 if (unlikely(!ctx
->spe_enabled
)) {
7428 gen_exception(ctx
, POWERPC_EXCP_APU
);
7431 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], (target_long
)~0x80000000LL
);
7433 static always_inline
void gen_efsnabs (DisasContext
*ctx
)
7435 if (unlikely(!ctx
->spe_enabled
)) {
7436 gen_exception(ctx
, POWERPC_EXCP_APU
);
7439 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
7441 static always_inline
void gen_efsneg (DisasContext
*ctx
)
7443 if (unlikely(!ctx
->spe_enabled
)) {
7444 gen_exception(ctx
, POWERPC_EXCP_APU
);
7447 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
7451 GEN_SPEFPUOP_CONV_32_32(efscfui
);
7452 GEN_SPEFPUOP_CONV_32_32(efscfsi
);
7453 GEN_SPEFPUOP_CONV_32_32(efscfuf
);
7454 GEN_SPEFPUOP_CONV_32_32(efscfsf
);
7455 GEN_SPEFPUOP_CONV_32_32(efsctui
);
7456 GEN_SPEFPUOP_CONV_32_32(efsctsi
);
7457 GEN_SPEFPUOP_CONV_32_32(efsctuf
);
7458 GEN_SPEFPUOP_CONV_32_32(efsctsf
);
7459 GEN_SPEFPUOP_CONV_32_32(efsctuiz
);
7460 GEN_SPEFPUOP_CONV_32_32(efsctsiz
);
7461 GEN_SPEFPUOP_CONV_32_64(efscfd
);
7464 GEN_SPEFPUOP_COMP_32(efscmpgt
);
7465 GEN_SPEFPUOP_COMP_32(efscmplt
);
7466 GEN_SPEFPUOP_COMP_32(efscmpeq
);
7467 GEN_SPEFPUOP_COMP_32(efststgt
);
7468 GEN_SPEFPUOP_COMP_32(efststlt
);
7469 GEN_SPEFPUOP_COMP_32(efststeq
);
7471 /* Opcodes definitions */
7472 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, PPC_SPEFPU
); //
7473 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU
); //
7474 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU
); //
7475 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, PPC_SPEFPU
); //
7476 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, PPC_SPEFPU
); //
7477 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, PPC_SPEFPU
); //
7478 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, PPC_SPEFPU
); //
7479 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, PPC_SPEFPU
); //
7480 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU
); //
7481 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU
); //
7482 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU
); //
7483 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU
); //
7484 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU
); //
7485 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU
); //
7487 /* Double precision floating-point operations */
7489 GEN_SPEFPUOP_ARITH2_64_64(efdadd
);
7490 GEN_SPEFPUOP_ARITH2_64_64(efdsub
);
7491 GEN_SPEFPUOP_ARITH2_64_64(efdmul
);
7492 GEN_SPEFPUOP_ARITH2_64_64(efddiv
);
7493 static always_inline
void gen_efdabs (DisasContext
*ctx
)
7495 if (unlikely(!ctx
->spe_enabled
)) {
7496 gen_exception(ctx
, POWERPC_EXCP_APU
);
7499 #if defined(TARGET_PPC64)
7500 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000000000000LL
);
7502 tcg_gen_andi_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
7505 static always_inline
void gen_efdnabs (DisasContext
*ctx
)
7507 if (unlikely(!ctx
->spe_enabled
)) {
7508 gen_exception(ctx
, POWERPC_EXCP_APU
);
7511 #if defined(TARGET_PPC64)
7512 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
7514 tcg_gen_ori_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
7517 static always_inline
void gen_efdneg (DisasContext
*ctx
)
7519 if (unlikely(!ctx
->spe_enabled
)) {
7520 gen_exception(ctx
, POWERPC_EXCP_APU
);
7523 #if defined(TARGET_PPC64)
7524 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
7526 tcg_gen_xori_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
7531 GEN_SPEFPUOP_CONV_64_32(efdcfui
);
7532 GEN_SPEFPUOP_CONV_64_32(efdcfsi
);
7533 GEN_SPEFPUOP_CONV_64_32(efdcfuf
);
7534 GEN_SPEFPUOP_CONV_64_32(efdcfsf
);
7535 GEN_SPEFPUOP_CONV_32_64(efdctui
);
7536 GEN_SPEFPUOP_CONV_32_64(efdctsi
);
7537 GEN_SPEFPUOP_CONV_32_64(efdctuf
);
7538 GEN_SPEFPUOP_CONV_32_64(efdctsf
);
7539 GEN_SPEFPUOP_CONV_32_64(efdctuiz
);
7540 GEN_SPEFPUOP_CONV_32_64(efdctsiz
);
7541 GEN_SPEFPUOP_CONV_64_32(efdcfs
);
7542 GEN_SPEFPUOP_CONV_64_64(efdcfuid
);
7543 GEN_SPEFPUOP_CONV_64_64(efdcfsid
);
7544 GEN_SPEFPUOP_CONV_64_64(efdctuidz
);
7545 GEN_SPEFPUOP_CONV_64_64(efdctsidz
);
7548 GEN_SPEFPUOP_COMP_64(efdcmpgt
);
7549 GEN_SPEFPUOP_COMP_64(efdcmplt
);
7550 GEN_SPEFPUOP_COMP_64(efdcmpeq
);
7551 GEN_SPEFPUOP_COMP_64(efdtstgt
);
7552 GEN_SPEFPUOP_COMP_64(efdtstlt
);
7553 GEN_SPEFPUOP_COMP_64(efdtsteq
);
7555 /* Opcodes definitions */
7556 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, PPC_SPEFPU
); //
7557 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, PPC_SPEFPU
); //
7558 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU
); //
7559 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU
); //
7560 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, PPC_SPEFPU
); //
7561 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, PPC_SPEFPU
); //
7562 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, PPC_SPEFPU
); //
7563 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, PPC_SPEFPU
); //
7564 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, PPC_SPEFPU
); //
7565 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, PPC_SPEFPU
); //
7566 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU
); //
7567 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU
); //
7568 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU
); //
7569 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU
); //
7570 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU
); //
7571 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU
); //
7573 /* End opcode list */
7574 GEN_OPCODE_MARK(end
);
7576 #include "translate_init.c"
7577 #include "helper_regs.h"
7579 /*****************************************************************************/
7580 /* Misc PowerPC helpers */
7581 void cpu_dump_state (CPUState
*env
, FILE *f
,
7582 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
7590 cpu_fprintf(f
, "NIP " ADDRX
" LR " ADDRX
" CTR " ADDRX
" XER %08x\n",
7591 env
->nip
, env
->lr
, env
->ctr
, env
->xer
);
7592 cpu_fprintf(f
, "MSR " ADDRX
" HID0 " ADDRX
" HF " ADDRX
" idx %d\n",
7593 env
->msr
, env
->spr
[SPR_HID0
], env
->hflags
, env
->mmu_idx
);
7594 #if !defined(NO_TIMER_DUMP)
7595 cpu_fprintf(f
, "TB %08x %08x "
7596 #if !defined(CONFIG_USER_ONLY)
7600 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
7601 #if !defined(CONFIG_USER_ONLY)
7602 , cpu_ppc_load_decr(env
)
7606 for (i
= 0; i
< 32; i
++) {
7607 if ((i
& (RGPL
- 1)) == 0)
7608 cpu_fprintf(f
, "GPR%02d", i
);
7609 cpu_fprintf(f
, " " REGX
, ppc_dump_gpr(env
, i
));
7610 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
7611 cpu_fprintf(f
, "\n");
7613 cpu_fprintf(f
, "CR ");
7614 for (i
= 0; i
< 8; i
++)
7615 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
7616 cpu_fprintf(f
, " [");
7617 for (i
= 0; i
< 8; i
++) {
7619 if (env
->crf
[i
] & 0x08)
7621 else if (env
->crf
[i
] & 0x04)
7623 else if (env
->crf
[i
] & 0x02)
7625 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
7627 cpu_fprintf(f
, " ] RES " ADDRX
"\n", env
->reserve
);
7628 for (i
= 0; i
< 32; i
++) {
7629 if ((i
& (RFPL
- 1)) == 0)
7630 cpu_fprintf(f
, "FPR%02d", i
);
7631 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
7632 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
7633 cpu_fprintf(f
, "\n");
7635 cpu_fprintf(f
, "FPSCR %08x\n", env
->fpscr
);
7636 #if !defined(CONFIG_USER_ONLY)
7637 cpu_fprintf(f
, "SRR0 " ADDRX
" SRR1 " ADDRX
" SDR1 " ADDRX
"\n",
7638 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
], env
->sdr1
);
7645 void cpu_dump_statistics (CPUState
*env
, FILE*f
,
7646 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
7649 #if defined(DO_PPC_STATISTICS)
7650 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
7654 for (op1
= 0; op1
< 64; op1
++) {
7656 if (is_indirect_opcode(handler
)) {
7657 t2
= ind_table(handler
);
7658 for (op2
= 0; op2
< 32; op2
++) {
7660 if (is_indirect_opcode(handler
)) {
7661 t3
= ind_table(handler
);
7662 for (op3
= 0; op3
< 32; op3
++) {
7664 if (handler
->count
== 0)
7666 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
7668 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
7670 handler
->count
, handler
->count
);
7673 if (handler
->count
== 0)
7675 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
7677 op1
, op2
, op1
, op2
, handler
->oname
,
7678 handler
->count
, handler
->count
);
7682 if (handler
->count
== 0)
7684 cpu_fprintf(f
, "%02x (%02x ) %16s: %016llx %lld\n",
7685 op1
, op1
, handler
->oname
,
7686 handler
->count
, handler
->count
);
7692 /*****************************************************************************/
7693 static always_inline
void gen_intermediate_code_internal (CPUState
*env
,
7694 TranslationBlock
*tb
,
7697 DisasContext ctx
, *ctxp
= &ctx
;
7698 opc_handler_t
**table
, *handler
;
7699 target_ulong pc_start
;
7700 uint16_t *gen_opc_end
;
7707 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
7710 ctx
.exception
= POWERPC_EXCP_NONE
;
7711 ctx
.spr_cb
= env
->spr_cb
;
7712 ctx
.mem_idx
= env
->mmu_idx
;
7713 ctx
.access_type
= -1;
7714 ctx
.le_mode
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
7715 #if defined(TARGET_PPC64)
7716 ctx
.sf_mode
= msr_sf
;
7718 ctx
.fpu_enabled
= msr_fp
;
7719 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
7720 ctx
.spe_enabled
= msr_spe
;
7722 ctx
.spe_enabled
= 0;
7723 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
7724 ctx
.altivec_enabled
= msr_vr
;
7726 ctx
.altivec_enabled
= 0;
7727 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
7728 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
7730 ctx
.singlestep_enabled
= 0;
7731 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
7732 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
7733 if (unlikely(env
->singlestep_enabled
))
7734 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
7735 #if defined (DO_SINGLE_STEP) && 0
7736 /* Single step trace mode */
7740 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7742 max_insns
= CF_COUNT_MASK
;
7745 /* Set env in case of segfault during code fetch */
7746 while (ctx
.exception
== POWERPC_EXCP_NONE
&& gen_opc_ptr
< gen_opc_end
) {
7747 if (unlikely(!TAILQ_EMPTY(&env
->breakpoints
))) {
7748 TAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
7749 if (bp
->pc
== ctx
.nip
) {
7750 gen_debug_exception(ctxp
);
7755 if (unlikely(search_pc
)) {
7756 j
= gen_opc_ptr
- gen_opc_buf
;
7760 gen_opc_instr_start
[lj
++] = 0;
7761 gen_opc_pc
[lj
] = ctx
.nip
;
7762 gen_opc_instr_start
[lj
] = 1;
7763 gen_opc_icount
[lj
] = num_insns
;
7766 #if defined PPC_DEBUG_DISAS
7767 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
7768 fprintf(logfile
, "----------------\n");
7769 fprintf(logfile
, "nip=" ADDRX
" super=%d ir=%d\n",
7770 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
7773 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7775 if (unlikely(ctx
.le_mode
)) {
7776 ctx
.opcode
= bswap32(ldl_code(ctx
.nip
));
7778 ctx
.opcode
= ldl_code(ctx
.nip
);
7780 #if defined PPC_DEBUG_DISAS
7781 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
7782 fprintf(logfile
, "translate opcode %08x (%02x %02x %02x) (%s)\n",
7783 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
7784 opc3(ctx
.opcode
), little_endian
? "little" : "big");
7788 table
= env
->opcodes
;
7790 handler
= table
[opc1(ctx
.opcode
)];
7791 if (is_indirect_opcode(handler
)) {
7792 table
= ind_table(handler
);
7793 handler
= table
[opc2(ctx
.opcode
)];
7794 if (is_indirect_opcode(handler
)) {
7795 table
= ind_table(handler
);
7796 handler
= table
[opc3(ctx
.opcode
)];
7799 /* Is opcode *REALLY* valid ? */
7800 if (unlikely(handler
->handler
== &gen_invalid
)) {
7801 if (loglevel
!= 0) {
7802 fprintf(logfile
, "invalid/unsupported opcode: "
7803 "%02x - %02x - %02x (%08x) " ADDRX
" %d\n",
7804 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
7805 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
7807 printf("invalid/unsupported opcode: "
7808 "%02x - %02x - %02x (%08x) " ADDRX
" %d\n",
7809 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
7810 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
7813 if (unlikely((ctx
.opcode
& handler
->inval
) != 0)) {
7814 if (loglevel
!= 0) {
7815 fprintf(logfile
, "invalid bits: %08x for opcode: "
7816 "%02x - %02x - %02x (%08x) " ADDRX
"\n",
7817 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
7818 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
7819 ctx
.opcode
, ctx
.nip
- 4);
7821 printf("invalid bits: %08x for opcode: "
7822 "%02x - %02x - %02x (%08x) " ADDRX
"\n",
7823 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
7824 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
7825 ctx
.opcode
, ctx
.nip
- 4);
7827 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
7831 (*(handler
->handler
))(&ctx
);
7832 #if defined(DO_PPC_STATISTICS)
7835 /* Check trace mode exceptions */
7836 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
7837 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
7838 ctx
.exception
!= POWERPC_SYSCALL
&&
7839 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
7840 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
7841 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
7842 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
7843 (env
->singlestep_enabled
) ||
7844 num_insns
>= max_insns
)) {
7845 /* if we reach a page boundary or are single stepping, stop
7850 #if defined (DO_SINGLE_STEP)
7854 if (tb
->cflags
& CF_LAST_IO
)
7856 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
7857 gen_goto_tb(&ctx
, 0, ctx
.nip
);
7858 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
7859 if (unlikely(env
->singlestep_enabled
)) {
7860 gen_debug_exception(ctxp
);
7862 /* Generate the return instruction */
7865 gen_icount_end(tb
, num_insns
);
7866 *gen_opc_ptr
= INDEX_op_end
;
7867 if (unlikely(search_pc
)) {
7868 j
= gen_opc_ptr
- gen_opc_buf
;
7871 gen_opc_instr_start
[lj
++] = 0;
7873 tb
->size
= ctx
.nip
- pc_start
;
7874 tb
->icount
= num_insns
;
7876 #if defined(DEBUG_DISAS)
7877 if (loglevel
& CPU_LOG_TB_CPU
) {
7878 fprintf(logfile
, "---------------- excp: %04x\n", ctx
.exception
);
7879 cpu_dump_state(env
, logfile
, fprintf
, 0);
7881 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
7883 flags
= env
->bfd_mach
;
7884 flags
|= ctx
.le_mode
<< 16;
7885 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
7886 target_disas(logfile
, pc_start
, ctx
.nip
- pc_start
, flags
);
7887 fprintf(logfile
, "\n");
7892 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
7894 gen_intermediate_code_internal(env
, tb
, 0);
7897 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
7899 gen_intermediate_code_internal(env
, tb
, 1);
7902 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
7903 unsigned long searched_pc
, int pc_pos
, void *puc
)
7905 env
->nip
= gen_opc_pc
[pc_pos
];