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1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31
32 /* Include definitions for instructions classes and implementations flags */
33 //#define DO_SINGLE_STEP
34 //#define PPC_DEBUG_DISAS
35 //#define DEBUG_MEMORY_ACCESSES
36 //#define DO_PPC_STATISTICS
37 //#define OPTIMIZE_FPRF_UPDATE
38
39 /*****************************************************************************/
40 /* Code translation helpers */
41
42 #if defined(OPTIMIZE_FPRF_UPDATE)
43 static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
44 static uint16_t **gen_fprf_ptr;
45 #endif
46
47 static always_inline void gen_set_T0 (target_ulong val)
48 {
49 #if defined(TARGET_PPC64)
50 if (val >> 32)
51 gen_op_set_T0_64(val >> 32, val);
52 else
53 #endif
54 gen_op_set_T0(val);
55 }
56
57 static always_inline void gen_set_T1 (target_ulong val)
58 {
59 #if defined(TARGET_PPC64)
60 if (val >> 32)
61 gen_op_set_T1_64(val >> 32, val);
62 else
63 #endif
64 gen_op_set_T1(val);
65 }
66
67 #define GEN8(func, NAME) \
68 static GenOpFunc *NAME ## _table [8] = { \
69 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
70 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
71 }; \
72 static always_inline void func (int n) \
73 { \
74 NAME ## _table[n](); \
75 }
76
77 #define GEN16(func, NAME) \
78 static GenOpFunc *NAME ## _table [16] = { \
79 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
80 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
81 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
82 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
83 }; \
84 static always_inline void func (int n) \
85 { \
86 NAME ## _table[n](); \
87 }
88
89 #define GEN32(func, NAME) \
90 static GenOpFunc *NAME ## _table [32] = { \
91 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
92 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
93 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
94 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
95 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
96 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
97 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
98 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
99 }; \
100 static always_inline void func (int n) \
101 { \
102 NAME ## _table[n](); \
103 }
104
105 /* Condition register moves */
106 GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
107 GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
108 GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
109 #if 0 // Unused
110 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
111 #endif
112
113 /* General purpose registers moves */
114 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
115 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
116 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
117
118 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
119 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
120 #if 0 // unused
121 GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
122 #endif
123
124 /* floating point registers moves */
125 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
126 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
127 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
128 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
129 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
130 #if 0 // unused
131 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
132 #endif
133
134 /* internal defines */
135 typedef struct DisasContext {
136 struct TranslationBlock *tb;
137 target_ulong nip;
138 uint32_t opcode;
139 uint32_t exception;
140 /* Routine used to access memory */
141 int mem_idx;
142 /* Translation flags */
143 #if !defined(CONFIG_USER_ONLY)
144 int supervisor;
145 #endif
146 #if defined(TARGET_PPC64)
147 int sf_mode;
148 #endif
149 int fpu_enabled;
150 int altivec_enabled;
151 int spe_enabled;
152 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
153 int singlestep_enabled;
154 int dcache_line_size;
155 } DisasContext;
156
157 struct opc_handler_t {
158 /* invalid bits */
159 uint32_t inval;
160 /* instruction type */
161 uint64_t type;
162 /* handler */
163 void (*handler)(DisasContext *ctx);
164 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
165 const unsigned char *oname;
166 #endif
167 #if defined(DO_PPC_STATISTICS)
168 uint64_t count;
169 #endif
170 };
171
172 static always_inline void gen_set_Rc0 (DisasContext *ctx)
173 {
174 #if defined(TARGET_PPC64)
175 if (ctx->sf_mode)
176 gen_op_cmpi_64(0);
177 else
178 #endif
179 gen_op_cmpi(0);
180 gen_op_set_Rc0();
181 }
182
183 static always_inline void gen_reset_fpstatus (void)
184 {
185 #ifdef CONFIG_SOFTFLOAT
186 gen_op_reset_fpstatus();
187 #endif
188 }
189
190 static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
191 {
192 if (set_fprf != 0) {
193 /* This case might be optimized later */
194 #if defined(OPTIMIZE_FPRF_UPDATE)
195 *gen_fprf_ptr++ = gen_opc_ptr;
196 #endif
197 gen_op_compute_fprf(1);
198 if (unlikely(set_rc))
199 gen_op_store_T0_crf(1);
200 gen_op_float_check_status();
201 } else if (unlikely(set_rc)) {
202 /* We always need to compute fpcc */
203 gen_op_compute_fprf(0);
204 gen_op_store_T0_crf(1);
205 if (set_fprf)
206 gen_op_float_check_status();
207 }
208 }
209
210 static always_inline void gen_optimize_fprf (void)
211 {
212 #if defined(OPTIMIZE_FPRF_UPDATE)
213 uint16_t **ptr;
214
215 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
216 *ptr = INDEX_op_nop1;
217 gen_fprf_ptr = gen_fprf_buf;
218 #endif
219 }
220
221 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
222 {
223 #if defined(TARGET_PPC64)
224 if (ctx->sf_mode)
225 gen_op_update_nip_64(nip >> 32, nip);
226 else
227 #endif
228 gen_op_update_nip(nip);
229 }
230
231 #define GEN_EXCP(ctx, excp, error) \
232 do { \
233 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
234 gen_update_nip(ctx, (ctx)->nip); \
235 } \
236 gen_op_raise_exception_err((excp), (error)); \
237 ctx->exception = (excp); \
238 } while (0)
239
240 #define GEN_EXCP_INVAL(ctx) \
241 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
242 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
243
244 #define GEN_EXCP_PRIVOPC(ctx) \
245 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
246 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
247
248 #define GEN_EXCP_PRIVREG(ctx) \
249 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
250 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
251
252 #define GEN_EXCP_NO_FP(ctx) \
253 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
254
255 #define GEN_EXCP_NO_AP(ctx) \
256 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
257
258 #define GEN_EXCP_NO_VR(ctx) \
259 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
260
261 /* Stop translation */
262 static always_inline void GEN_STOP (DisasContext *ctx)
263 {
264 gen_update_nip(ctx, ctx->nip);
265 ctx->exception = POWERPC_EXCP_STOP;
266 }
267
268 /* No need to update nip here, as execution flow will change */
269 static always_inline void GEN_SYNC (DisasContext *ctx)
270 {
271 ctx->exception = POWERPC_EXCP_SYNC;
272 }
273
274 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
275 static void gen_##name (DisasContext *ctx); \
276 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
277 static void gen_##name (DisasContext *ctx)
278
279 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
280 static void gen_##name (DisasContext *ctx); \
281 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
282 static void gen_##name (DisasContext *ctx)
283
284 typedef struct opcode_t {
285 unsigned char opc1, opc2, opc3;
286 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
287 unsigned char pad[5];
288 #else
289 unsigned char pad[1];
290 #endif
291 opc_handler_t handler;
292 const unsigned char *oname;
293 } opcode_t;
294
295 /*****************************************************************************/
296 /*** Instruction decoding ***/
297 #define EXTRACT_HELPER(name, shift, nb) \
298 static always_inline uint32_t name (uint32_t opcode) \
299 { \
300 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
301 }
302
303 #define EXTRACT_SHELPER(name, shift, nb) \
304 static always_inline int32_t name (uint32_t opcode) \
305 { \
306 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
307 }
308
309 /* Opcode part 1 */
310 EXTRACT_HELPER(opc1, 26, 6);
311 /* Opcode part 2 */
312 EXTRACT_HELPER(opc2, 1, 5);
313 /* Opcode part 3 */
314 EXTRACT_HELPER(opc3, 6, 5);
315 /* Update Cr0 flags */
316 EXTRACT_HELPER(Rc, 0, 1);
317 /* Destination */
318 EXTRACT_HELPER(rD, 21, 5);
319 /* Source */
320 EXTRACT_HELPER(rS, 21, 5);
321 /* First operand */
322 EXTRACT_HELPER(rA, 16, 5);
323 /* Second operand */
324 EXTRACT_HELPER(rB, 11, 5);
325 /* Third operand */
326 EXTRACT_HELPER(rC, 6, 5);
327 /*** Get CRn ***/
328 EXTRACT_HELPER(crfD, 23, 3);
329 EXTRACT_HELPER(crfS, 18, 3);
330 EXTRACT_HELPER(crbD, 21, 5);
331 EXTRACT_HELPER(crbA, 16, 5);
332 EXTRACT_HELPER(crbB, 11, 5);
333 /* SPR / TBL */
334 EXTRACT_HELPER(_SPR, 11, 10);
335 static always_inline uint32_t SPR (uint32_t opcode)
336 {
337 uint32_t sprn = _SPR(opcode);
338
339 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
340 }
341 /*** Get constants ***/
342 EXTRACT_HELPER(IMM, 12, 8);
343 /* 16 bits signed immediate value */
344 EXTRACT_SHELPER(SIMM, 0, 16);
345 /* 16 bits unsigned immediate value */
346 EXTRACT_HELPER(UIMM, 0, 16);
347 /* Bit count */
348 EXTRACT_HELPER(NB, 11, 5);
349 /* Shift count */
350 EXTRACT_HELPER(SH, 11, 5);
351 /* Mask start */
352 EXTRACT_HELPER(MB, 6, 5);
353 /* Mask end */
354 EXTRACT_HELPER(ME, 1, 5);
355 /* Trap operand */
356 EXTRACT_HELPER(TO, 21, 5);
357
358 EXTRACT_HELPER(CRM, 12, 8);
359 EXTRACT_HELPER(FM, 17, 8);
360 EXTRACT_HELPER(SR, 16, 4);
361 EXTRACT_HELPER(FPIMM, 20, 4);
362
363 /*** Jump target decoding ***/
364 /* Displacement */
365 EXTRACT_SHELPER(d, 0, 16);
366 /* Immediate address */
367 static always_inline target_ulong LI (uint32_t opcode)
368 {
369 return (opcode >> 0) & 0x03FFFFFC;
370 }
371
372 static always_inline uint32_t BD (uint32_t opcode)
373 {
374 return (opcode >> 0) & 0xFFFC;
375 }
376
377 EXTRACT_HELPER(BO, 21, 5);
378 EXTRACT_HELPER(BI, 16, 5);
379 /* Absolute/relative address */
380 EXTRACT_HELPER(AA, 1, 1);
381 /* Link */
382 EXTRACT_HELPER(LK, 0, 1);
383
384 /* Create a mask between <start> and <end> bits */
385 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
386 {
387 target_ulong ret;
388
389 #if defined(TARGET_PPC64)
390 if (likely(start == 0)) {
391 ret = UINT64_MAX << (63 - end);
392 } else if (likely(end == 63)) {
393 ret = UINT64_MAX >> start;
394 }
395 #else
396 if (likely(start == 0)) {
397 ret = UINT32_MAX << (31 - end);
398 } else if (likely(end == 31)) {
399 ret = UINT32_MAX >> start;
400 }
401 #endif
402 else {
403 ret = (((target_ulong)(-1ULL)) >> (start)) ^
404 (((target_ulong)(-1ULL) >> (end)) >> 1);
405 if (unlikely(start > end))
406 return ~ret;
407 }
408
409 return ret;
410 }
411
412 /*****************************************************************************/
413 /* PowerPC Instructions types definitions */
414 enum {
415 PPC_NONE = 0x0000000000000000ULL,
416 /* PowerPC base instructions set */
417 PPC_INSNS_BASE = 0x0000000000000001ULL,
418 /* integer operations instructions */
419 #define PPC_INTEGER PPC_INSNS_BASE
420 /* flow control instructions */
421 #define PPC_FLOW PPC_INSNS_BASE
422 /* virtual memory instructions */
423 #define PPC_MEM PPC_INSNS_BASE
424 /* ld/st with reservation instructions */
425 #define PPC_RES PPC_INSNS_BASE
426 /* spr/msr access instructions */
427 #define PPC_MISC PPC_INSNS_BASE
428 /* Deprecated instruction sets */
429 /* Original POWER instruction set */
430 PPC_POWER = 0x0000000000000002ULL,
431 /* POWER2 instruction set extension */
432 PPC_POWER2 = 0x0000000000000004ULL,
433 /* Power RTC support */
434 PPC_POWER_RTC = 0x0000000000000008ULL,
435 /* Power-to-PowerPC bridge (601) */
436 PPC_POWER_BR = 0x0000000000000010ULL,
437 /* 64 bits PowerPC instruction set */
438 PPC_64B = 0x0000000000000020ULL,
439 /* New 64 bits extensions (PowerPC 2.0x) */
440 PPC_64BX = 0x0000000000000040ULL,
441 /* 64 bits hypervisor extensions */
442 PPC_64H = 0x0000000000000080ULL,
443 /* New wait instruction (PowerPC 2.0x) */
444 PPC_WAIT = 0x0000000000000100ULL,
445 /* Time base mftb instruction */
446 PPC_MFTB = 0x0000000000000200ULL,
447
448 /* Fixed-point unit extensions */
449 /* PowerPC 602 specific */
450 PPC_602_SPEC = 0x0000000000000400ULL,
451 /* isel instruction */
452 PPC_ISEL = 0x0000000000000800ULL,
453 /* popcntb instruction */
454 PPC_POPCNTB = 0x0000000000001000ULL,
455 /* string load / store */
456 PPC_STRING = 0x0000000000002000ULL,
457
458 /* Floating-point unit extensions */
459 /* Optional floating point instructions */
460 PPC_FLOAT = 0x0000000000010000ULL,
461 /* New floating-point extensions (PowerPC 2.0x) */
462 PPC_FLOAT_EXT = 0x0000000000020000ULL,
463 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
464 PPC_FLOAT_FRES = 0x0000000000080000ULL,
465 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
466 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
467 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
468 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
469
470 /* Vector/SIMD extensions */
471 /* Altivec support */
472 PPC_ALTIVEC = 0x0000000001000000ULL,
473 /* PowerPC 2.03 SPE extension */
474 PPC_SPE = 0x0000000002000000ULL,
475 /* PowerPC 2.03 SPE floating-point extension */
476 PPC_SPEFPU = 0x0000000004000000ULL,
477
478 /* Optional memory control instructions */
479 PPC_MEM_TLBIA = 0x0000000010000000ULL,
480 PPC_MEM_TLBIE = 0x0000000020000000ULL,
481 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
482 /* sync instruction */
483 PPC_MEM_SYNC = 0x0000000080000000ULL,
484 /* eieio instruction */
485 PPC_MEM_EIEIO = 0x0000000100000000ULL,
486
487 /* Cache control instructions */
488 PPC_CACHE = 0x0000000200000000ULL,
489 /* icbi instruction */
490 PPC_CACHE_ICBI = 0x0000000400000000ULL,
491 /* dcbz instruction with fixed cache line size */
492 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
493 /* dcbz instruction with tunable cache line size */
494 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
495 /* dcba instruction */
496 PPC_CACHE_DCBA = 0x0000002000000000ULL,
497 /* Freescale cache locking instructions */
498 PPC_CACHE_LOCK = 0x0000004000000000ULL,
499
500 /* MMU related extensions */
501 /* external control instructions */
502 PPC_EXTERN = 0x0000010000000000ULL,
503 /* segment register access instructions */
504 PPC_SEGMENT = 0x0000020000000000ULL,
505 /* PowerPC 6xx TLB management instructions */
506 PPC_6xx_TLB = 0x0000040000000000ULL,
507 /* PowerPC 74xx TLB management instructions */
508 PPC_74xx_TLB = 0x0000080000000000ULL,
509 /* PowerPC 40x TLB management instructions */
510 PPC_40x_TLB = 0x0000100000000000ULL,
511 /* segment register access instructions for PowerPC 64 "bridge" */
512 PPC_SEGMENT_64B = 0x0000200000000000ULL,
513 /* SLB management */
514 PPC_SLBI = 0x0000400000000000ULL,
515
516 /* Embedded PowerPC dedicated instructions */
517 PPC_WRTEE = 0x0001000000000000ULL,
518 /* PowerPC 40x exception model */
519 PPC_40x_EXCP = 0x0002000000000000ULL,
520 /* PowerPC 405 Mac instructions */
521 PPC_405_MAC = 0x0004000000000000ULL,
522 /* PowerPC 440 specific instructions */
523 PPC_440_SPEC = 0x0008000000000000ULL,
524 /* BookE (embedded) PowerPC specification */
525 PPC_BOOKE = 0x0010000000000000ULL,
526 /* mfapidi instruction */
527 PPC_MFAPIDI = 0x0020000000000000ULL,
528 /* tlbiva instruction */
529 PPC_TLBIVA = 0x0040000000000000ULL,
530 /* tlbivax instruction */
531 PPC_TLBIVAX = 0x0080000000000000ULL,
532 /* PowerPC 4xx dedicated instructions */
533 PPC_4xx_COMMON = 0x0100000000000000ULL,
534 /* PowerPC 40x ibct instructions */
535 PPC_40x_ICBT = 0x0200000000000000ULL,
536 /* rfmci is not implemented in all BookE PowerPC */
537 PPC_RFMCI = 0x0400000000000000ULL,
538 /* rfdi instruction */
539 PPC_RFDI = 0x0800000000000000ULL,
540 /* DCR accesses */
541 PPC_DCR = 0x1000000000000000ULL,
542 /* DCR extended accesse */
543 PPC_DCRX = 0x2000000000000000ULL,
544 /* user-mode DCR access, implemented in PowerPC 460 */
545 PPC_DCRUX = 0x4000000000000000ULL,
546 };
547
548 /*****************************************************************************/
549 /* PowerPC instructions table */
550 #if HOST_LONG_BITS == 64
551 #define OPC_ALIGN 8
552 #else
553 #define OPC_ALIGN 4
554 #endif
555 #if defined(__APPLE__)
556 #define OPCODES_SECTION \
557 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
558 #else
559 #define OPCODES_SECTION \
560 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
561 #endif
562
563 #if defined(DO_PPC_STATISTICS)
564 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
565 OPCODES_SECTION opcode_t opc_##name = { \
566 .opc1 = op1, \
567 .opc2 = op2, \
568 .opc3 = op3, \
569 .pad = { 0, }, \
570 .handler = { \
571 .inval = invl, \
572 .type = _typ, \
573 .handler = &gen_##name, \
574 .oname = stringify(name), \
575 }, \
576 .oname = stringify(name), \
577 }
578 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
579 OPCODES_SECTION opcode_t opc_##name = { \
580 .opc1 = op1, \
581 .opc2 = op2, \
582 .opc3 = op3, \
583 .pad = { 0, }, \
584 .handler = { \
585 .inval = invl, \
586 .type = _typ, \
587 .handler = &gen_##name, \
588 .oname = onam, \
589 }, \
590 .oname = onam, \
591 }
592 #else
593 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
594 OPCODES_SECTION opcode_t opc_##name = { \
595 .opc1 = op1, \
596 .opc2 = op2, \
597 .opc3 = op3, \
598 .pad = { 0, }, \
599 .handler = { \
600 .inval = invl, \
601 .type = _typ, \
602 .handler = &gen_##name, \
603 }, \
604 .oname = stringify(name), \
605 }
606 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
607 OPCODES_SECTION opcode_t opc_##name = { \
608 .opc1 = op1, \
609 .opc2 = op2, \
610 .opc3 = op3, \
611 .pad = { 0, }, \
612 .handler = { \
613 .inval = invl, \
614 .type = _typ, \
615 .handler = &gen_##name, \
616 }, \
617 .oname = onam, \
618 }
619 #endif
620
621 #define GEN_OPCODE_MARK(name) \
622 OPCODES_SECTION opcode_t opc_##name = { \
623 .opc1 = 0xFF, \
624 .opc2 = 0xFF, \
625 .opc3 = 0xFF, \
626 .pad = { 0, }, \
627 .handler = { \
628 .inval = 0x00000000, \
629 .type = 0x00, \
630 .handler = NULL, \
631 }, \
632 .oname = stringify(name), \
633 }
634
635 /* Start opcode list */
636 GEN_OPCODE_MARK(start);
637
638 /* Invalid instruction */
639 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
640 {
641 GEN_EXCP_INVAL(ctx);
642 }
643
644 static opc_handler_t invalid_handler = {
645 .inval = 0xFFFFFFFF,
646 .type = PPC_NONE,
647 .handler = gen_invalid,
648 };
649
650 /*** Integer arithmetic ***/
651 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
652 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
653 { \
654 gen_op_load_gpr_T0(rA(ctx->opcode)); \
655 gen_op_load_gpr_T1(rB(ctx->opcode)); \
656 gen_op_##name(); \
657 gen_op_store_T0_gpr(rD(ctx->opcode)); \
658 if (unlikely(Rc(ctx->opcode) != 0)) \
659 gen_set_Rc0(ctx); \
660 }
661
662 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
663 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
664 { \
665 gen_op_load_gpr_T0(rA(ctx->opcode)); \
666 gen_op_load_gpr_T1(rB(ctx->opcode)); \
667 gen_op_##name(); \
668 gen_op_store_T0_gpr(rD(ctx->opcode)); \
669 if (unlikely(Rc(ctx->opcode) != 0)) \
670 gen_set_Rc0(ctx); \
671 }
672
673 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
674 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
675 { \
676 gen_op_load_gpr_T0(rA(ctx->opcode)); \
677 gen_op_##name(); \
678 gen_op_store_T0_gpr(rD(ctx->opcode)); \
679 if (unlikely(Rc(ctx->opcode) != 0)) \
680 gen_set_Rc0(ctx); \
681 }
682 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
683 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
684 { \
685 gen_op_load_gpr_T0(rA(ctx->opcode)); \
686 gen_op_##name(); \
687 gen_op_store_T0_gpr(rD(ctx->opcode)); \
688 if (unlikely(Rc(ctx->opcode) != 0)) \
689 gen_set_Rc0(ctx); \
690 }
691
692 /* Two operands arithmetic functions */
693 #define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
694 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
695 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
696
697 /* Two operands arithmetic functions with no overflow allowed */
698 #define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
699 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
700
701 /* One operand arithmetic functions */
702 #define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
703 __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
704 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
705
706 #if defined(TARGET_PPC64)
707 #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
708 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
709 { \
710 gen_op_load_gpr_T0(rA(ctx->opcode)); \
711 gen_op_load_gpr_T1(rB(ctx->opcode)); \
712 if (ctx->sf_mode) \
713 gen_op_##name##_64(); \
714 else \
715 gen_op_##name(); \
716 gen_op_store_T0_gpr(rD(ctx->opcode)); \
717 if (unlikely(Rc(ctx->opcode) != 0)) \
718 gen_set_Rc0(ctx); \
719 }
720
721 #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
722 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
723 { \
724 gen_op_load_gpr_T0(rA(ctx->opcode)); \
725 gen_op_load_gpr_T1(rB(ctx->opcode)); \
726 if (ctx->sf_mode) \
727 gen_op_##name##_64(); \
728 else \
729 gen_op_##name(); \
730 gen_op_store_T0_gpr(rD(ctx->opcode)); \
731 if (unlikely(Rc(ctx->opcode) != 0)) \
732 gen_set_Rc0(ctx); \
733 }
734
735 #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
736 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
737 { \
738 gen_op_load_gpr_T0(rA(ctx->opcode)); \
739 if (ctx->sf_mode) \
740 gen_op_##name##_64(); \
741 else \
742 gen_op_##name(); \
743 gen_op_store_T0_gpr(rD(ctx->opcode)); \
744 if (unlikely(Rc(ctx->opcode) != 0)) \
745 gen_set_Rc0(ctx); \
746 }
747 #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
748 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
749 { \
750 gen_op_load_gpr_T0(rA(ctx->opcode)); \
751 if (ctx->sf_mode) \
752 gen_op_##name##_64(); \
753 else \
754 gen_op_##name(); \
755 gen_op_store_T0_gpr(rD(ctx->opcode)); \
756 if (unlikely(Rc(ctx->opcode) != 0)) \
757 gen_set_Rc0(ctx); \
758 }
759
760 /* Two operands arithmetic functions */
761 #define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
762 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
763 __GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
764
765 /* Two operands arithmetic functions with no overflow allowed */
766 #define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
767 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
768
769 /* One operand arithmetic functions */
770 #define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
771 __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
772 __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
773 #else
774 #define GEN_INT_ARITH2_64 GEN_INT_ARITH2
775 #define GEN_INT_ARITHN_64 GEN_INT_ARITHN
776 #define GEN_INT_ARITH1_64 GEN_INT_ARITH1
777 #endif
778
779 /* add add. addo addo. */
780 static always_inline void gen_op_addo (void)
781 {
782 gen_op_move_T2_T0();
783 gen_op_add();
784 gen_op_check_addo();
785 }
786 #if defined(TARGET_PPC64)
787 #define gen_op_add_64 gen_op_add
788 static always_inline void gen_op_addo_64 (void)
789 {
790 gen_op_move_T2_T0();
791 gen_op_add();
792 gen_op_check_addo_64();
793 }
794 #endif
795 GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
796 /* addc addc. addco addco. */
797 static always_inline void gen_op_addc (void)
798 {
799 gen_op_move_T2_T0();
800 gen_op_add();
801 gen_op_check_addc();
802 }
803 static always_inline void gen_op_addco (void)
804 {
805 gen_op_move_T2_T0();
806 gen_op_add();
807 gen_op_check_addc();
808 gen_op_check_addo();
809 }
810 #if defined(TARGET_PPC64)
811 static always_inline void gen_op_addc_64 (void)
812 {
813 gen_op_move_T2_T0();
814 gen_op_add();
815 gen_op_check_addc_64();
816 }
817 static always_inline void gen_op_addco_64 (void)
818 {
819 gen_op_move_T2_T0();
820 gen_op_add();
821 gen_op_check_addc_64();
822 gen_op_check_addo_64();
823 }
824 #endif
825 GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
826 /* adde adde. addeo addeo. */
827 static always_inline void gen_op_addeo (void)
828 {
829 gen_op_move_T2_T0();
830 gen_op_adde();
831 gen_op_check_addo();
832 }
833 #if defined(TARGET_PPC64)
834 static always_inline void gen_op_addeo_64 (void)
835 {
836 gen_op_move_T2_T0();
837 gen_op_adde_64();
838 gen_op_check_addo_64();
839 }
840 #endif
841 GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
842 /* addme addme. addmeo addmeo. */
843 static always_inline void gen_op_addme (void)
844 {
845 gen_op_move_T1_T0();
846 gen_op_add_me();
847 }
848 #if defined(TARGET_PPC64)
849 static always_inline void gen_op_addme_64 (void)
850 {
851 gen_op_move_T1_T0();
852 gen_op_add_me_64();
853 }
854 #endif
855 GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
856 /* addze addze. addzeo addzeo. */
857 static always_inline void gen_op_addze (void)
858 {
859 gen_op_move_T2_T0();
860 gen_op_add_ze();
861 gen_op_check_addc();
862 }
863 static always_inline void gen_op_addzeo (void)
864 {
865 gen_op_move_T2_T0();
866 gen_op_add_ze();
867 gen_op_check_addc();
868 gen_op_check_addo();
869 }
870 #if defined(TARGET_PPC64)
871 static always_inline void gen_op_addze_64 (void)
872 {
873 gen_op_move_T2_T0();
874 gen_op_add_ze();
875 gen_op_check_addc_64();
876 }
877 static always_inline void gen_op_addzeo_64 (void)
878 {
879 gen_op_move_T2_T0();
880 gen_op_add_ze();
881 gen_op_check_addc_64();
882 gen_op_check_addo_64();
883 }
884 #endif
885 GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
886 /* divw divw. divwo divwo. */
887 GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
888 /* divwu divwu. divwuo divwuo. */
889 GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
890 /* mulhw mulhw. */
891 GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
892 /* mulhwu mulhwu. */
893 GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
894 /* mullw mullw. mullwo mullwo. */
895 GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
896 /* neg neg. nego nego. */
897 GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
898 /* subf subf. subfo subfo. */
899 static always_inline void gen_op_subfo (void)
900 {
901 gen_op_moven_T2_T0();
902 gen_op_subf();
903 gen_op_check_addo();
904 }
905 #if defined(TARGET_PPC64)
906 #define gen_op_subf_64 gen_op_subf
907 static always_inline void gen_op_subfo_64 (void)
908 {
909 gen_op_moven_T2_T0();
910 gen_op_subf();
911 gen_op_check_addo_64();
912 }
913 #endif
914 GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
915 /* subfc subfc. subfco subfco. */
916 static always_inline void gen_op_subfc (void)
917 {
918 gen_op_subf();
919 gen_op_check_subfc();
920 }
921 static always_inline void gen_op_subfco (void)
922 {
923 gen_op_moven_T2_T0();
924 gen_op_subf();
925 gen_op_check_subfc();
926 gen_op_check_addo();
927 }
928 #if defined(TARGET_PPC64)
929 static always_inline void gen_op_subfc_64 (void)
930 {
931 gen_op_subf();
932 gen_op_check_subfc_64();
933 }
934 static always_inline void gen_op_subfco_64 (void)
935 {
936 gen_op_moven_T2_T0();
937 gen_op_subf();
938 gen_op_check_subfc_64();
939 gen_op_check_addo_64();
940 }
941 #endif
942 GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
943 /* subfe subfe. subfeo subfeo. */
944 static always_inline void gen_op_subfeo (void)
945 {
946 gen_op_moven_T2_T0();
947 gen_op_subfe();
948 gen_op_check_addo();
949 }
950 #if defined(TARGET_PPC64)
951 #define gen_op_subfe_64 gen_op_subfe
952 static always_inline void gen_op_subfeo_64 (void)
953 {
954 gen_op_moven_T2_T0();
955 gen_op_subfe_64();
956 gen_op_check_addo_64();
957 }
958 #endif
959 GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
960 /* subfme subfme. subfmeo subfmeo. */
961 GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
962 /* subfze subfze. subfzeo subfzeo. */
963 GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
964 /* addi */
965 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
966 {
967 target_long simm = SIMM(ctx->opcode);
968
969 if (rA(ctx->opcode) == 0) {
970 /* li case */
971 gen_set_T0(simm);
972 } else {
973 gen_op_load_gpr_T0(rA(ctx->opcode));
974 if (likely(simm != 0))
975 gen_op_addi(simm);
976 }
977 gen_op_store_T0_gpr(rD(ctx->opcode));
978 }
979 /* addic */
980 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
981 {
982 target_long simm = SIMM(ctx->opcode);
983
984 gen_op_load_gpr_T0(rA(ctx->opcode));
985 if (likely(simm != 0)) {
986 gen_op_move_T2_T0();
987 gen_op_addi(simm);
988 #if defined(TARGET_PPC64)
989 if (ctx->sf_mode)
990 gen_op_check_addc_64();
991 else
992 #endif
993 gen_op_check_addc();
994 } else {
995 gen_op_clear_xer_ca();
996 }
997 gen_op_store_T0_gpr(rD(ctx->opcode));
998 }
999 /* addic. */
1000 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1001 {
1002 target_long simm = SIMM(ctx->opcode);
1003
1004 gen_op_load_gpr_T0(rA(ctx->opcode));
1005 if (likely(simm != 0)) {
1006 gen_op_move_T2_T0();
1007 gen_op_addi(simm);
1008 #if defined(TARGET_PPC64)
1009 if (ctx->sf_mode)
1010 gen_op_check_addc_64();
1011 else
1012 #endif
1013 gen_op_check_addc();
1014 } else {
1015 gen_op_clear_xer_ca();
1016 }
1017 gen_op_store_T0_gpr(rD(ctx->opcode));
1018 gen_set_Rc0(ctx);
1019 }
1020 /* addis */
1021 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1022 {
1023 target_long simm = SIMM(ctx->opcode);
1024
1025 if (rA(ctx->opcode) == 0) {
1026 /* lis case */
1027 gen_set_T0(simm << 16);
1028 } else {
1029 gen_op_load_gpr_T0(rA(ctx->opcode));
1030 if (likely(simm != 0))
1031 gen_op_addi(simm << 16);
1032 }
1033 gen_op_store_T0_gpr(rD(ctx->opcode));
1034 }
1035 /* mulli */
1036 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1037 {
1038 gen_op_load_gpr_T0(rA(ctx->opcode));
1039 gen_op_mulli(SIMM(ctx->opcode));
1040 gen_op_store_T0_gpr(rD(ctx->opcode));
1041 }
1042 /* subfic */
1043 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1044 {
1045 gen_op_load_gpr_T0(rA(ctx->opcode));
1046 #if defined(TARGET_PPC64)
1047 if (ctx->sf_mode)
1048 gen_op_subfic_64(SIMM(ctx->opcode));
1049 else
1050 #endif
1051 gen_op_subfic(SIMM(ctx->opcode));
1052 gen_op_store_T0_gpr(rD(ctx->opcode));
1053 }
1054
1055 #if defined(TARGET_PPC64)
1056 /* mulhd mulhd. */
1057 GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
1058 /* mulhdu mulhdu. */
1059 GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
1060 /* mulld mulld. mulldo mulldo. */
1061 GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
1062 /* divd divd. divdo divdo. */
1063 GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
1064 /* divdu divdu. divduo divduo. */
1065 GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
1066 #endif
1067
1068 /*** Integer comparison ***/
1069 #if defined(TARGET_PPC64)
1070 #define GEN_CMP(name, opc, type) \
1071 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1072 { \
1073 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1074 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1075 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
1076 gen_op_##name##_64(); \
1077 else \
1078 gen_op_##name(); \
1079 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1080 }
1081 #else
1082 #define GEN_CMP(name, opc, type) \
1083 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1084 { \
1085 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1086 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1087 gen_op_##name(); \
1088 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1089 }
1090 #endif
1091
1092 /* cmp */
1093 GEN_CMP(cmp, 0x00, PPC_INTEGER);
1094 /* cmpi */
1095 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1096 {
1097 gen_op_load_gpr_T0(rA(ctx->opcode));
1098 #if defined(TARGET_PPC64)
1099 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1100 gen_op_cmpi_64(SIMM(ctx->opcode));
1101 else
1102 #endif
1103 gen_op_cmpi(SIMM(ctx->opcode));
1104 gen_op_store_T0_crf(crfD(ctx->opcode));
1105 }
1106 /* cmpl */
1107 GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1108 /* cmpli */
1109 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1110 {
1111 gen_op_load_gpr_T0(rA(ctx->opcode));
1112 #if defined(TARGET_PPC64)
1113 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1114 gen_op_cmpli_64(UIMM(ctx->opcode));
1115 else
1116 #endif
1117 gen_op_cmpli(UIMM(ctx->opcode));
1118 gen_op_store_T0_crf(crfD(ctx->opcode));
1119 }
1120
1121 /* isel (PowerPC 2.03 specification) */
1122 GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_ISEL)
1123 {
1124 uint32_t bi = rC(ctx->opcode);
1125 uint32_t mask;
1126
1127 if (rA(ctx->opcode) == 0) {
1128 gen_set_T0(0);
1129 } else {
1130 gen_op_load_gpr_T1(rA(ctx->opcode));
1131 }
1132 gen_op_load_gpr_T2(rB(ctx->opcode));
1133 mask = 1 << (3 - (bi & 0x03));
1134 gen_op_load_crf_T0(bi >> 2);
1135 gen_op_test_true(mask);
1136 gen_op_isel();
1137 gen_op_store_T0_gpr(rD(ctx->opcode));
1138 }
1139
1140 /*** Integer logical ***/
1141 #define __GEN_LOGICAL2(name, opc2, opc3, type) \
1142 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
1143 { \
1144 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1145 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1146 gen_op_##name(); \
1147 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1148 if (unlikely(Rc(ctx->opcode) != 0)) \
1149 gen_set_Rc0(ctx); \
1150 }
1151 #define GEN_LOGICAL2(name, opc, type) \
1152 __GEN_LOGICAL2(name, 0x1C, opc, type)
1153
1154 #define GEN_LOGICAL1(name, opc, type) \
1155 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1156 { \
1157 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1158 gen_op_##name(); \
1159 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1160 if (unlikely(Rc(ctx->opcode) != 0)) \
1161 gen_set_Rc0(ctx); \
1162 }
1163
1164 /* and & and. */
1165 GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
1166 /* andc & andc. */
1167 GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1168 /* andi. */
1169 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1170 {
1171 gen_op_load_gpr_T0(rS(ctx->opcode));
1172 gen_op_andi_T0(UIMM(ctx->opcode));
1173 gen_op_store_T0_gpr(rA(ctx->opcode));
1174 gen_set_Rc0(ctx);
1175 }
1176 /* andis. */
1177 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1178 {
1179 gen_op_load_gpr_T0(rS(ctx->opcode));
1180 gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1181 gen_op_store_T0_gpr(rA(ctx->opcode));
1182 gen_set_Rc0(ctx);
1183 }
1184
1185 /* cntlzw */
1186 GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
1187 /* eqv & eqv. */
1188 GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
1189 /* extsb & extsb. */
1190 GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
1191 /* extsh & extsh. */
1192 GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
1193 /* nand & nand. */
1194 GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
1195 /* nor & nor. */
1196 GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
1197
1198 /* or & or. */
1199 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1200 {
1201 int rs, ra, rb;
1202
1203 rs = rS(ctx->opcode);
1204 ra = rA(ctx->opcode);
1205 rb = rB(ctx->opcode);
1206 /* Optimisation for mr. ri case */
1207 if (rs != ra || rs != rb) {
1208 gen_op_load_gpr_T0(rs);
1209 if (rs != rb) {
1210 gen_op_load_gpr_T1(rb);
1211 gen_op_or();
1212 }
1213 gen_op_store_T0_gpr(ra);
1214 if (unlikely(Rc(ctx->opcode) != 0))
1215 gen_set_Rc0(ctx);
1216 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1217 gen_op_load_gpr_T0(rs);
1218 gen_set_Rc0(ctx);
1219 #if defined(TARGET_PPC64)
1220 } else {
1221 switch (rs) {
1222 case 1:
1223 /* Set process priority to low */
1224 gen_op_store_pri(2);
1225 break;
1226 case 6:
1227 /* Set process priority to medium-low */
1228 gen_op_store_pri(3);
1229 break;
1230 case 2:
1231 /* Set process priority to normal */
1232 gen_op_store_pri(4);
1233 break;
1234 #if !defined(CONFIG_USER_ONLY)
1235 case 31:
1236 if (ctx->supervisor > 0) {
1237 /* Set process priority to very low */
1238 gen_op_store_pri(1);
1239 }
1240 break;
1241 case 5:
1242 if (ctx->supervisor > 0) {
1243 /* Set process priority to medium-hight */
1244 gen_op_store_pri(5);
1245 }
1246 break;
1247 case 3:
1248 if (ctx->supervisor > 0) {
1249 /* Set process priority to high */
1250 gen_op_store_pri(6);
1251 }
1252 break;
1253 case 7:
1254 if (ctx->supervisor > 1) {
1255 /* Set process priority to very high */
1256 gen_op_store_pri(7);
1257 }
1258 break;
1259 #endif
1260 default:
1261 /* nop */
1262 break;
1263 }
1264 #endif
1265 }
1266 }
1267
1268 /* orc & orc. */
1269 GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1270 /* xor & xor. */
1271 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1272 {
1273 gen_op_load_gpr_T0(rS(ctx->opcode));
1274 /* Optimisation for "set to zero" case */
1275 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1276 gen_op_load_gpr_T1(rB(ctx->opcode));
1277 gen_op_xor();
1278 } else {
1279 gen_op_reset_T0();
1280 }
1281 gen_op_store_T0_gpr(rA(ctx->opcode));
1282 if (unlikely(Rc(ctx->opcode) != 0))
1283 gen_set_Rc0(ctx);
1284 }
1285 /* ori */
1286 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1287 {
1288 target_ulong uimm = UIMM(ctx->opcode);
1289
1290 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1291 /* NOP */
1292 /* XXX: should handle special NOPs for POWER series */
1293 return;
1294 }
1295 gen_op_load_gpr_T0(rS(ctx->opcode));
1296 if (likely(uimm != 0))
1297 gen_op_ori(uimm);
1298 gen_op_store_T0_gpr(rA(ctx->opcode));
1299 }
1300 /* oris */
1301 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1302 {
1303 target_ulong uimm = UIMM(ctx->opcode);
1304
1305 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1306 /* NOP */
1307 return;
1308 }
1309 gen_op_load_gpr_T0(rS(ctx->opcode));
1310 if (likely(uimm != 0))
1311 gen_op_ori(uimm << 16);
1312 gen_op_store_T0_gpr(rA(ctx->opcode));
1313 }
1314 /* xori */
1315 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1316 {
1317 target_ulong uimm = UIMM(ctx->opcode);
1318
1319 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1320 /* NOP */
1321 return;
1322 }
1323 gen_op_load_gpr_T0(rS(ctx->opcode));
1324 if (likely(uimm != 0))
1325 gen_op_xori(uimm);
1326 gen_op_store_T0_gpr(rA(ctx->opcode));
1327 }
1328
1329 /* xoris */
1330 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1331 {
1332 target_ulong uimm = UIMM(ctx->opcode);
1333
1334 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1335 /* NOP */
1336 return;
1337 }
1338 gen_op_load_gpr_T0(rS(ctx->opcode));
1339 if (likely(uimm != 0))
1340 gen_op_xori(uimm << 16);
1341 gen_op_store_T0_gpr(rA(ctx->opcode));
1342 }
1343
1344 /* popcntb : PowerPC 2.03 specification */
1345 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1346 {
1347 gen_op_load_gpr_T0(rS(ctx->opcode));
1348 #if defined(TARGET_PPC64)
1349 if (ctx->sf_mode)
1350 gen_op_popcntb_64();
1351 else
1352 #endif
1353 gen_op_popcntb();
1354 gen_op_store_T0_gpr(rA(ctx->opcode));
1355 }
1356
1357 #if defined(TARGET_PPC64)
1358 /* extsw & extsw. */
1359 GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1360 /* cntlzd */
1361 GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1362 #endif
1363
1364 /*** Integer rotate ***/
1365 /* rlwimi & rlwimi. */
1366 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1367 {
1368 target_ulong mask;
1369 uint32_t mb, me, sh;
1370
1371 mb = MB(ctx->opcode);
1372 me = ME(ctx->opcode);
1373 sh = SH(ctx->opcode);
1374 if (likely(sh == 0)) {
1375 if (likely(mb == 0 && me == 31)) {
1376 gen_op_load_gpr_T0(rS(ctx->opcode));
1377 goto do_store;
1378 } else if (likely(mb == 31 && me == 0)) {
1379 gen_op_load_gpr_T0(rA(ctx->opcode));
1380 goto do_store;
1381 }
1382 gen_op_load_gpr_T0(rS(ctx->opcode));
1383 gen_op_load_gpr_T1(rA(ctx->opcode));
1384 goto do_mask;
1385 }
1386 gen_op_load_gpr_T0(rS(ctx->opcode));
1387 gen_op_load_gpr_T1(rA(ctx->opcode));
1388 gen_op_rotli32_T0(SH(ctx->opcode));
1389 do_mask:
1390 #if defined(TARGET_PPC64)
1391 mb += 32;
1392 me += 32;
1393 #endif
1394 mask = MASK(mb, me);
1395 gen_op_andi_T0(mask);
1396 gen_op_andi_T1(~mask);
1397 gen_op_or();
1398 do_store:
1399 gen_op_store_T0_gpr(rA(ctx->opcode));
1400 if (unlikely(Rc(ctx->opcode) != 0))
1401 gen_set_Rc0(ctx);
1402 }
1403 /* rlwinm & rlwinm. */
1404 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1405 {
1406 uint32_t mb, me, sh;
1407
1408 sh = SH(ctx->opcode);
1409 mb = MB(ctx->opcode);
1410 me = ME(ctx->opcode);
1411 gen_op_load_gpr_T0(rS(ctx->opcode));
1412 if (likely(sh == 0)) {
1413 goto do_mask;
1414 }
1415 if (likely(mb == 0)) {
1416 if (likely(me == 31)) {
1417 gen_op_rotli32_T0(sh);
1418 goto do_store;
1419 } else if (likely(me == (31 - sh))) {
1420 gen_op_sli_T0(sh);
1421 goto do_store;
1422 }
1423 } else if (likely(me == 31)) {
1424 if (likely(sh == (32 - mb))) {
1425 gen_op_srli_T0(mb);
1426 goto do_store;
1427 }
1428 }
1429 gen_op_rotli32_T0(sh);
1430 do_mask:
1431 #if defined(TARGET_PPC64)
1432 mb += 32;
1433 me += 32;
1434 #endif
1435 gen_op_andi_T0(MASK(mb, me));
1436 do_store:
1437 gen_op_store_T0_gpr(rA(ctx->opcode));
1438 if (unlikely(Rc(ctx->opcode) != 0))
1439 gen_set_Rc0(ctx);
1440 }
1441 /* rlwnm & rlwnm. */
1442 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1443 {
1444 uint32_t mb, me;
1445
1446 mb = MB(ctx->opcode);
1447 me = ME(ctx->opcode);
1448 gen_op_load_gpr_T0(rS(ctx->opcode));
1449 gen_op_load_gpr_T1(rB(ctx->opcode));
1450 gen_op_rotl32_T0_T1();
1451 if (unlikely(mb != 0 || me != 31)) {
1452 #if defined(TARGET_PPC64)
1453 mb += 32;
1454 me += 32;
1455 #endif
1456 gen_op_andi_T0(MASK(mb, me));
1457 }
1458 gen_op_store_T0_gpr(rA(ctx->opcode));
1459 if (unlikely(Rc(ctx->opcode) != 0))
1460 gen_set_Rc0(ctx);
1461 }
1462
1463 #if defined(TARGET_PPC64)
1464 #define GEN_PPC64_R2(name, opc1, opc2) \
1465 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1466 { \
1467 gen_##name(ctx, 0); \
1468 } \
1469 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1470 PPC_64B) \
1471 { \
1472 gen_##name(ctx, 1); \
1473 }
1474 #define GEN_PPC64_R4(name, opc1, opc2) \
1475 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1476 { \
1477 gen_##name(ctx, 0, 0); \
1478 } \
1479 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1480 PPC_64B) \
1481 { \
1482 gen_##name(ctx, 0, 1); \
1483 } \
1484 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1485 PPC_64B) \
1486 { \
1487 gen_##name(ctx, 1, 0); \
1488 } \
1489 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1490 PPC_64B) \
1491 { \
1492 gen_##name(ctx, 1, 1); \
1493 }
1494
1495 static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1496 {
1497 if (mask >> 32)
1498 gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1499 else
1500 gen_op_andi_T0(mask);
1501 }
1502
1503 static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1504 {
1505 if (mask >> 32)
1506 gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1507 else
1508 gen_op_andi_T1(mask);
1509 }
1510
1511 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1512 uint32_t me, uint32_t sh)
1513 {
1514 gen_op_load_gpr_T0(rS(ctx->opcode));
1515 if (likely(sh == 0)) {
1516 goto do_mask;
1517 }
1518 if (likely(mb == 0)) {
1519 if (likely(me == 63)) {
1520 gen_op_rotli64_T0(sh);
1521 goto do_store;
1522 } else if (likely(me == (63 - sh))) {
1523 gen_op_sli_T0(sh);
1524 goto do_store;
1525 }
1526 } else if (likely(me == 63)) {
1527 if (likely(sh == (64 - mb))) {
1528 gen_op_srli_T0_64(mb);
1529 goto do_store;
1530 }
1531 }
1532 gen_op_rotli64_T0(sh);
1533 do_mask:
1534 gen_andi_T0_64(ctx, MASK(mb, me));
1535 do_store:
1536 gen_op_store_T0_gpr(rA(ctx->opcode));
1537 if (unlikely(Rc(ctx->opcode) != 0))
1538 gen_set_Rc0(ctx);
1539 }
1540 /* rldicl - rldicl. */
1541 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1542 {
1543 uint32_t sh, mb;
1544
1545 sh = SH(ctx->opcode) | (shn << 5);
1546 mb = MB(ctx->opcode) | (mbn << 5);
1547 gen_rldinm(ctx, mb, 63, sh);
1548 }
1549 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1550 /* rldicr - rldicr. */
1551 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1552 {
1553 uint32_t sh, me;
1554
1555 sh = SH(ctx->opcode) | (shn << 5);
1556 me = MB(ctx->opcode) | (men << 5);
1557 gen_rldinm(ctx, 0, me, sh);
1558 }
1559 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1560 /* rldic - rldic. */
1561 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1562 {
1563 uint32_t sh, mb;
1564
1565 sh = SH(ctx->opcode) | (shn << 5);
1566 mb = MB(ctx->opcode) | (mbn << 5);
1567 gen_rldinm(ctx, mb, 63 - sh, sh);
1568 }
1569 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1570
1571 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1572 uint32_t me)
1573 {
1574 gen_op_load_gpr_T0(rS(ctx->opcode));
1575 gen_op_load_gpr_T1(rB(ctx->opcode));
1576 gen_op_rotl64_T0_T1();
1577 if (unlikely(mb != 0 || me != 63)) {
1578 gen_andi_T0_64(ctx, MASK(mb, me));
1579 }
1580 gen_op_store_T0_gpr(rA(ctx->opcode));
1581 if (unlikely(Rc(ctx->opcode) != 0))
1582 gen_set_Rc0(ctx);
1583 }
1584
1585 /* rldcl - rldcl. */
1586 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1587 {
1588 uint32_t mb;
1589
1590 mb = MB(ctx->opcode) | (mbn << 5);
1591 gen_rldnm(ctx, mb, 63);
1592 }
1593 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1594 /* rldcr - rldcr. */
1595 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1596 {
1597 uint32_t me;
1598
1599 me = MB(ctx->opcode) | (men << 5);
1600 gen_rldnm(ctx, 0, me);
1601 }
1602 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1603 /* rldimi - rldimi. */
1604 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1605 {
1606 uint64_t mask;
1607 uint32_t sh, mb, me;
1608
1609 sh = SH(ctx->opcode) | (shn << 5);
1610 mb = MB(ctx->opcode) | (mbn << 5);
1611 me = 63 - sh;
1612 if (likely(sh == 0)) {
1613 if (likely(mb == 0)) {
1614 gen_op_load_gpr_T0(rS(ctx->opcode));
1615 goto do_store;
1616 }
1617 gen_op_load_gpr_T0(rS(ctx->opcode));
1618 gen_op_load_gpr_T1(rA(ctx->opcode));
1619 goto do_mask;
1620 }
1621 gen_op_load_gpr_T0(rS(ctx->opcode));
1622 gen_op_load_gpr_T1(rA(ctx->opcode));
1623 gen_op_rotli64_T0(sh);
1624 do_mask:
1625 mask = MASK(mb, me);
1626 gen_andi_T0_64(ctx, mask);
1627 gen_andi_T1_64(ctx, ~mask);
1628 gen_op_or();
1629 do_store:
1630 gen_op_store_T0_gpr(rA(ctx->opcode));
1631 if (unlikely(Rc(ctx->opcode) != 0))
1632 gen_set_Rc0(ctx);
1633 }
1634 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1635 #endif
1636
1637 /*** Integer shift ***/
1638 /* slw & slw. */
1639 __GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
1640 /* sraw & sraw. */
1641 __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1642 /* srawi & srawi. */
1643 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1644 {
1645 int mb, me;
1646 gen_op_load_gpr_T0(rS(ctx->opcode));
1647 if (SH(ctx->opcode) != 0) {
1648 gen_op_move_T1_T0();
1649 mb = 32 - SH(ctx->opcode);
1650 me = 31;
1651 #if defined(TARGET_PPC64)
1652 mb += 32;
1653 me += 32;
1654 #endif
1655 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1656 }
1657 gen_op_store_T0_gpr(rA(ctx->opcode));
1658 if (unlikely(Rc(ctx->opcode) != 0))
1659 gen_set_Rc0(ctx);
1660 }
1661 /* srw & srw. */
1662 __GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1663
1664 #if defined(TARGET_PPC64)
1665 /* sld & sld. */
1666 __GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1667 /* srad & srad. */
1668 __GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1669 /* sradi & sradi. */
1670 static always_inline void gen_sradi (DisasContext *ctx, int n)
1671 {
1672 uint64_t mask;
1673 int sh, mb, me;
1674
1675 gen_op_load_gpr_T0(rS(ctx->opcode));
1676 sh = SH(ctx->opcode) + (n << 5);
1677 if (sh != 0) {
1678 gen_op_move_T1_T0();
1679 mb = 64 - SH(ctx->opcode);
1680 me = 63;
1681 mask = MASK(mb, me);
1682 gen_op_sradi(sh, mask >> 32, mask);
1683 }
1684 gen_op_store_T0_gpr(rA(ctx->opcode));
1685 if (unlikely(Rc(ctx->opcode) != 0))
1686 gen_set_Rc0(ctx);
1687 }
1688 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1689 {
1690 gen_sradi(ctx, 0);
1691 }
1692 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
1693 {
1694 gen_sradi(ctx, 1);
1695 }
1696 /* srd & srd. */
1697 __GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1698 #endif
1699
1700 /*** Floating-Point arithmetic ***/
1701 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1702 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
1703 { \
1704 if (unlikely(!ctx->fpu_enabled)) { \
1705 GEN_EXCP_NO_FP(ctx); \
1706 return; \
1707 } \
1708 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1709 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1710 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
1711 gen_reset_fpstatus(); \
1712 gen_op_f##op(); \
1713 if (isfloat) { \
1714 gen_op_frsp(); \
1715 } \
1716 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1717 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1718 }
1719
1720 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1721 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1722 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1723
1724 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1725 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1726 { \
1727 if (unlikely(!ctx->fpu_enabled)) { \
1728 GEN_EXCP_NO_FP(ctx); \
1729 return; \
1730 } \
1731 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1732 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
1733 gen_reset_fpstatus(); \
1734 gen_op_f##op(); \
1735 if (isfloat) { \
1736 gen_op_frsp(); \
1737 } \
1738 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1739 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1740 }
1741 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1742 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1743 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1744
1745 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1746 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1747 { \
1748 if (unlikely(!ctx->fpu_enabled)) { \
1749 GEN_EXCP_NO_FP(ctx); \
1750 return; \
1751 } \
1752 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1753 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1754 gen_reset_fpstatus(); \
1755 gen_op_f##op(); \
1756 if (isfloat) { \
1757 gen_op_frsp(); \
1758 } \
1759 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1760 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1761 }
1762 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1763 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1764 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1765
1766 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1767 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
1768 { \
1769 if (unlikely(!ctx->fpu_enabled)) { \
1770 GEN_EXCP_NO_FP(ctx); \
1771 return; \
1772 } \
1773 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1774 gen_reset_fpstatus(); \
1775 gen_op_f##name(); \
1776 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1777 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1778 }
1779
1780 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1781 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
1782 { \
1783 if (unlikely(!ctx->fpu_enabled)) { \
1784 GEN_EXCP_NO_FP(ctx); \
1785 return; \
1786 } \
1787 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1788 gen_reset_fpstatus(); \
1789 gen_op_f##name(); \
1790 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1791 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1792 }
1793
1794 /* fadd - fadds */
1795 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
1796 /* fdiv - fdivs */
1797 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
1798 /* fmul - fmuls */
1799 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
1800
1801 /* fre */
1802 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
1803
1804 /* fres */
1805 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
1806
1807 /* frsqrte */
1808 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1809
1810 /* frsqrtes */
1811 static always_inline void gen_op_frsqrtes (void)
1812 {
1813 gen_op_frsqrte();
1814 gen_op_frsp();
1815 }
1816 GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
1817
1818 /* fsel */
1819 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
1820 /* fsub - fsubs */
1821 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
1822 /* Optional: */
1823 /* fsqrt */
1824 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1825 {
1826 if (unlikely(!ctx->fpu_enabled)) {
1827 GEN_EXCP_NO_FP(ctx);
1828 return;
1829 }
1830 gen_op_load_fpr_FT0(rB(ctx->opcode));
1831 gen_reset_fpstatus();
1832 gen_op_fsqrt();
1833 gen_op_store_FT0_fpr(rD(ctx->opcode));
1834 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1835 }
1836
1837 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1838 {
1839 if (unlikely(!ctx->fpu_enabled)) {
1840 GEN_EXCP_NO_FP(ctx);
1841 return;
1842 }
1843 gen_op_load_fpr_FT0(rB(ctx->opcode));
1844 gen_reset_fpstatus();
1845 gen_op_fsqrt();
1846 gen_op_frsp();
1847 gen_op_store_FT0_fpr(rD(ctx->opcode));
1848 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1849 }
1850
1851 /*** Floating-Point multiply-and-add ***/
1852 /* fmadd - fmadds */
1853 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
1854 /* fmsub - fmsubs */
1855 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
1856 /* fnmadd - fnmadds */
1857 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
1858 /* fnmsub - fnmsubs */
1859 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
1860
1861 /*** Floating-Point round & convert ***/
1862 /* fctiw */
1863 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
1864 /* fctiwz */
1865 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
1866 /* frsp */
1867 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
1868 #if defined(TARGET_PPC64)
1869 /* fcfid */
1870 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
1871 /* fctid */
1872 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
1873 /* fctidz */
1874 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
1875 #endif
1876
1877 /* frin */
1878 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
1879 /* friz */
1880 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
1881 /* frip */
1882 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
1883 /* frim */
1884 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
1885
1886 /*** Floating-Point compare ***/
1887 /* fcmpo */
1888 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1889 {
1890 if (unlikely(!ctx->fpu_enabled)) {
1891 GEN_EXCP_NO_FP(ctx);
1892 return;
1893 }
1894 gen_op_load_fpr_FT0(rA(ctx->opcode));
1895 gen_op_load_fpr_FT1(rB(ctx->opcode));
1896 gen_reset_fpstatus();
1897 gen_op_fcmpo();
1898 gen_op_store_T0_crf(crfD(ctx->opcode));
1899 gen_op_float_check_status();
1900 }
1901
1902 /* fcmpu */
1903 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1904 {
1905 if (unlikely(!ctx->fpu_enabled)) {
1906 GEN_EXCP_NO_FP(ctx);
1907 return;
1908 }
1909 gen_op_load_fpr_FT0(rA(ctx->opcode));
1910 gen_op_load_fpr_FT1(rB(ctx->opcode));
1911 gen_reset_fpstatus();
1912 gen_op_fcmpu();
1913 gen_op_store_T0_crf(crfD(ctx->opcode));
1914 gen_op_float_check_status();
1915 }
1916
1917 /*** Floating-point move ***/
1918 /* fabs */
1919 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1920 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
1921
1922 /* fmr - fmr. */
1923 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
1924 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1925 {
1926 if (unlikely(!ctx->fpu_enabled)) {
1927 GEN_EXCP_NO_FP(ctx);
1928 return;
1929 }
1930 gen_op_load_fpr_FT0(rB(ctx->opcode));
1931 gen_op_store_FT0_fpr(rD(ctx->opcode));
1932 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1933 }
1934
1935 /* fnabs */
1936 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1937 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
1938 /* fneg */
1939 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1940 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
1941
1942 /*** Floating-Point status & ctrl register ***/
1943 /* mcrfs */
1944 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1945 {
1946 int bfa;
1947
1948 if (unlikely(!ctx->fpu_enabled)) {
1949 GEN_EXCP_NO_FP(ctx);
1950 return;
1951 }
1952 gen_optimize_fprf();
1953 bfa = 4 * (7 - crfS(ctx->opcode));
1954 gen_op_load_fpscr_T0(bfa);
1955 gen_op_store_T0_crf(crfD(ctx->opcode));
1956 gen_op_fpscr_resetbit(~(0xF << bfa));
1957 }
1958
1959 /* mffs */
1960 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1961 {
1962 if (unlikely(!ctx->fpu_enabled)) {
1963 GEN_EXCP_NO_FP(ctx);
1964 return;
1965 }
1966 gen_optimize_fprf();
1967 gen_reset_fpstatus();
1968 gen_op_load_fpscr_FT0();
1969 gen_op_store_FT0_fpr(rD(ctx->opcode));
1970 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1971 }
1972
1973 /* mtfsb0 */
1974 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1975 {
1976 uint8_t crb;
1977
1978 if (unlikely(!ctx->fpu_enabled)) {
1979 GEN_EXCP_NO_FP(ctx);
1980 return;
1981 }
1982 crb = 32 - (crbD(ctx->opcode) >> 2);
1983 gen_optimize_fprf();
1984 gen_reset_fpstatus();
1985 if (likely(crb != 30 && crb != 29))
1986 gen_op_fpscr_resetbit(~(1 << crb));
1987 if (unlikely(Rc(ctx->opcode) != 0)) {
1988 gen_op_load_fpcc();
1989 gen_op_set_Rc0();
1990 }
1991 }
1992
1993 /* mtfsb1 */
1994 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1995 {
1996 uint8_t crb;
1997
1998 if (unlikely(!ctx->fpu_enabled)) {
1999 GEN_EXCP_NO_FP(ctx);
2000 return;
2001 }
2002 crb = 32 - (crbD(ctx->opcode) >> 2);
2003 gen_optimize_fprf();
2004 gen_reset_fpstatus();
2005 /* XXX: we pretend we can only do IEEE floating-point computations */
2006 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2007 gen_op_fpscr_setbit(crb);
2008 if (unlikely(Rc(ctx->opcode) != 0)) {
2009 gen_op_load_fpcc();
2010 gen_op_set_Rc0();
2011 }
2012 /* We can raise a differed exception */
2013 gen_op_float_check_status();
2014 }
2015
2016 /* mtfsf */
2017 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2018 {
2019 if (unlikely(!ctx->fpu_enabled)) {
2020 GEN_EXCP_NO_FP(ctx);
2021 return;
2022 }
2023 gen_optimize_fprf();
2024 gen_op_load_fpr_FT0(rB(ctx->opcode));
2025 gen_reset_fpstatus();
2026 gen_op_store_fpscr(FM(ctx->opcode));
2027 if (unlikely(Rc(ctx->opcode) != 0)) {
2028 gen_op_load_fpcc();
2029 gen_op_set_Rc0();
2030 }
2031 /* We can raise a differed exception */
2032 gen_op_float_check_status();
2033 }
2034
2035 /* mtfsfi */
2036 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2037 {
2038 int bf, sh;
2039
2040 if (unlikely(!ctx->fpu_enabled)) {
2041 GEN_EXCP_NO_FP(ctx);
2042 return;
2043 }
2044 bf = crbD(ctx->opcode) >> 2;
2045 sh = 7 - bf;
2046 gen_optimize_fprf();
2047 gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
2048 gen_reset_fpstatus();
2049 gen_op_store_fpscr(1 << sh);
2050 if (unlikely(Rc(ctx->opcode) != 0)) {
2051 gen_op_load_fpcc();
2052 gen_op_set_Rc0();
2053 }
2054 /* We can raise a differed exception */
2055 gen_op_float_check_status();
2056 }
2057
2058 /*** Addressing modes ***/
2059 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2060 static always_inline void gen_addr_imm_index (DisasContext *ctx,
2061 target_long maskl)
2062 {
2063 target_long simm = SIMM(ctx->opcode);
2064
2065 simm &= ~maskl;
2066 if (rA(ctx->opcode) == 0) {
2067 gen_set_T0(simm);
2068 } else {
2069 gen_op_load_gpr_T0(rA(ctx->opcode));
2070 if (likely(simm != 0))
2071 gen_op_addi(simm);
2072 }
2073 #ifdef DEBUG_MEMORY_ACCESSES
2074 gen_op_print_mem_EA();
2075 #endif
2076 }
2077
2078 static always_inline void gen_addr_reg_index (DisasContext *ctx)
2079 {
2080 if (rA(ctx->opcode) == 0) {
2081 gen_op_load_gpr_T0(rB(ctx->opcode));
2082 } else {
2083 gen_op_load_gpr_T0(rA(ctx->opcode));
2084 gen_op_load_gpr_T1(rB(ctx->opcode));
2085 gen_op_add();
2086 }
2087 #ifdef DEBUG_MEMORY_ACCESSES
2088 gen_op_print_mem_EA();
2089 #endif
2090 }
2091
2092 static always_inline void gen_addr_register (DisasContext *ctx)
2093 {
2094 if (rA(ctx->opcode) == 0) {
2095 gen_op_reset_T0();
2096 } else {
2097 gen_op_load_gpr_T0(rA(ctx->opcode));
2098 }
2099 #ifdef DEBUG_MEMORY_ACCESSES
2100 gen_op_print_mem_EA();
2101 #endif
2102 }
2103
2104 #if defined(TARGET_PPC64)
2105 #define _GEN_MEM_FUNCS(name, mode) \
2106 &gen_op_##name##_##mode, \
2107 &gen_op_##name##_le_##mode, \
2108 &gen_op_##name##_64_##mode, \
2109 &gen_op_##name##_le_64_##mode
2110 #else
2111 #define _GEN_MEM_FUNCS(name, mode) \
2112 &gen_op_##name##_##mode, \
2113 &gen_op_##name##_le_##mode
2114 #endif
2115 #if defined(CONFIG_USER_ONLY)
2116 #if defined(TARGET_PPC64)
2117 #define NB_MEM_FUNCS 4
2118 #else
2119 #define NB_MEM_FUNCS 2
2120 #endif
2121 #define GEN_MEM_FUNCS(name) \
2122 _GEN_MEM_FUNCS(name, raw)
2123 #else
2124 #if defined(TARGET_PPC64)
2125 #define NB_MEM_FUNCS 12
2126 #else
2127 #define NB_MEM_FUNCS 6
2128 #endif
2129 #define GEN_MEM_FUNCS(name) \
2130 _GEN_MEM_FUNCS(name, user), \
2131 _GEN_MEM_FUNCS(name, kernel), \
2132 _GEN_MEM_FUNCS(name, hypv)
2133 #endif
2134
2135 /*** Integer load ***/
2136 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
2137 /* Byte access routine are endian safe */
2138 #define gen_op_lbz_le_raw gen_op_lbz_raw
2139 #define gen_op_lbz_le_user gen_op_lbz_user
2140 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
2141 #define gen_op_lbz_le_hypv gen_op_lbz_hypv
2142 #define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2143 #define gen_op_lbz_le_64_user gen_op_lbz_64_user
2144 #define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2145 #define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2146 #define gen_op_stb_le_raw gen_op_stb_raw
2147 #define gen_op_stb_le_user gen_op_stb_user
2148 #define gen_op_stb_le_kernel gen_op_stb_kernel
2149 #define gen_op_stb_le_hypv gen_op_stb_hypv
2150 #define gen_op_stb_le_64_raw gen_op_stb_64_raw
2151 #define gen_op_stb_le_64_user gen_op_stb_64_user
2152 #define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2153 #define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
2154 #define OP_LD_TABLE(width) \
2155 static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2156 GEN_MEM_FUNCS(l##width), \
2157 };
2158 #define OP_ST_TABLE(width) \
2159 static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2160 GEN_MEM_FUNCS(st##width), \
2161 };
2162
2163 #define GEN_LD(width, opc, type) \
2164 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2165 { \
2166 gen_addr_imm_index(ctx, 0); \
2167 op_ldst(l##width); \
2168 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2169 }
2170
2171 #define GEN_LDU(width, opc, type) \
2172 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2173 { \
2174 if (unlikely(rA(ctx->opcode) == 0 || \
2175 rA(ctx->opcode) == rD(ctx->opcode))) { \
2176 GEN_EXCP_INVAL(ctx); \
2177 return; \
2178 } \
2179 if (type == PPC_64B) \
2180 gen_addr_imm_index(ctx, 0x03); \
2181 else \
2182 gen_addr_imm_index(ctx, 0); \
2183 op_ldst(l##width); \
2184 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2185 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2186 }
2187
2188 #define GEN_LDUX(width, opc2, opc3, type) \
2189 GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2190 { \
2191 if (unlikely(rA(ctx->opcode) == 0 || \
2192 rA(ctx->opcode) == rD(ctx->opcode))) { \
2193 GEN_EXCP_INVAL(ctx); \
2194 return; \
2195 } \
2196 gen_addr_reg_index(ctx); \
2197 op_ldst(l##width); \
2198 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2199 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2200 }
2201
2202 #define GEN_LDX(width, opc2, opc3, type) \
2203 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2204 { \
2205 gen_addr_reg_index(ctx); \
2206 op_ldst(l##width); \
2207 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2208 }
2209
2210 #define GEN_LDS(width, op, type) \
2211 OP_LD_TABLE(width); \
2212 GEN_LD(width, op | 0x20, type); \
2213 GEN_LDU(width, op | 0x21, type); \
2214 GEN_LDUX(width, 0x17, op | 0x01, type); \
2215 GEN_LDX(width, 0x17, op | 0x00, type)
2216
2217 /* lbz lbzu lbzux lbzx */
2218 GEN_LDS(bz, 0x02, PPC_INTEGER);
2219 /* lha lhau lhaux lhax */
2220 GEN_LDS(ha, 0x0A, PPC_INTEGER);
2221 /* lhz lhzu lhzux lhzx */
2222 GEN_LDS(hz, 0x08, PPC_INTEGER);
2223 /* lwz lwzu lwzux lwzx */
2224 GEN_LDS(wz, 0x00, PPC_INTEGER);
2225 #if defined(TARGET_PPC64)
2226 OP_LD_TABLE(wa);
2227 OP_LD_TABLE(d);
2228 /* lwaux */
2229 GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2230 /* lwax */
2231 GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2232 /* ldux */
2233 GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2234 /* ldx */
2235 GEN_LDX(d, 0x15, 0x00, PPC_64B);
2236 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2237 {
2238 if (Rc(ctx->opcode)) {
2239 if (unlikely(rA(ctx->opcode) == 0 ||
2240 rA(ctx->opcode) == rD(ctx->opcode))) {
2241 GEN_EXCP_INVAL(ctx);
2242 return;
2243 }
2244 }
2245 gen_addr_imm_index(ctx, 0x03);
2246 if (ctx->opcode & 0x02) {
2247 /* lwa (lwau is undefined) */
2248 op_ldst(lwa);
2249 } else {
2250 /* ld - ldu */
2251 op_ldst(ld);
2252 }
2253 gen_op_store_T1_gpr(rD(ctx->opcode));
2254 if (Rc(ctx->opcode))
2255 gen_op_store_T0_gpr(rA(ctx->opcode));
2256 }
2257 /* lq */
2258 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2259 {
2260 #if defined(CONFIG_USER_ONLY)
2261 GEN_EXCP_PRIVOPC(ctx);
2262 #else
2263 int ra, rd;
2264
2265 /* Restore CPU state */
2266 if (unlikely(ctx->supervisor == 0)) {
2267 GEN_EXCP_PRIVOPC(ctx);
2268 return;
2269 }
2270 ra = rA(ctx->opcode);
2271 rd = rD(ctx->opcode);
2272 if (unlikely((rd & 1) || rd == ra)) {
2273 GEN_EXCP_INVAL(ctx);
2274 return;
2275 }
2276 if (unlikely(ctx->mem_idx & 1)) {
2277 /* Little-endian mode is not handled */
2278 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2279 return;
2280 }
2281 gen_addr_imm_index(ctx, 0x0F);
2282 op_ldst(ld);
2283 gen_op_store_T1_gpr(rd);
2284 gen_op_addi(8);
2285 op_ldst(ld);
2286 gen_op_store_T1_gpr(rd + 1);
2287 #endif
2288 }
2289 #endif
2290
2291 /*** Integer store ***/
2292 #define GEN_ST(width, opc, type) \
2293 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2294 { \
2295 gen_addr_imm_index(ctx, 0); \
2296 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2297 op_ldst(st##width); \
2298 }
2299
2300 #define GEN_STU(width, opc, type) \
2301 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2302 { \
2303 if (unlikely(rA(ctx->opcode) == 0)) { \
2304 GEN_EXCP_INVAL(ctx); \
2305 return; \
2306 } \
2307 if (type == PPC_64B) \
2308 gen_addr_imm_index(ctx, 0x03); \
2309 else \
2310 gen_addr_imm_index(ctx, 0); \
2311 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2312 op_ldst(st##width); \
2313 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2314 }
2315
2316 #define GEN_STUX(width, opc2, opc3, type) \
2317 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2318 { \
2319 if (unlikely(rA(ctx->opcode) == 0)) { \
2320 GEN_EXCP_INVAL(ctx); \
2321 return; \
2322 } \
2323 gen_addr_reg_index(ctx); \
2324 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2325 op_ldst(st##width); \
2326 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2327 }
2328
2329 #define GEN_STX(width, opc2, opc3, type) \
2330 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2331 { \
2332 gen_addr_reg_index(ctx); \
2333 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2334 op_ldst(st##width); \
2335 }
2336
2337 #define GEN_STS(width, op, type) \
2338 OP_ST_TABLE(width); \
2339 GEN_ST(width, op | 0x20, type); \
2340 GEN_STU(width, op | 0x21, type); \
2341 GEN_STUX(width, 0x17, op | 0x01, type); \
2342 GEN_STX(width, 0x17, op | 0x00, type)
2343
2344 /* stb stbu stbux stbx */
2345 GEN_STS(b, 0x06, PPC_INTEGER);
2346 /* sth sthu sthux sthx */
2347 GEN_STS(h, 0x0C, PPC_INTEGER);
2348 /* stw stwu stwux stwx */
2349 GEN_STS(w, 0x04, PPC_INTEGER);
2350 #if defined(TARGET_PPC64)
2351 OP_ST_TABLE(d);
2352 GEN_STUX(d, 0x15, 0x05, PPC_64B);
2353 GEN_STX(d, 0x15, 0x04, PPC_64B);
2354 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2355 {
2356 int rs;
2357
2358 rs = rS(ctx->opcode);
2359 if ((ctx->opcode & 0x3) == 0x2) {
2360 #if defined(CONFIG_USER_ONLY)
2361 GEN_EXCP_PRIVOPC(ctx);
2362 #else
2363 /* stq */
2364 if (unlikely(ctx->supervisor == 0)) {
2365 GEN_EXCP_PRIVOPC(ctx);
2366 return;
2367 }
2368 if (unlikely(rs & 1)) {
2369 GEN_EXCP_INVAL(ctx);
2370 return;
2371 }
2372 if (unlikely(ctx->mem_idx & 1)) {
2373 /* Little-endian mode is not handled */
2374 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2375 return;
2376 }
2377 gen_addr_imm_index(ctx, 0x03);
2378 gen_op_load_gpr_T1(rs);
2379 op_ldst(std);
2380 gen_op_addi(8);
2381 gen_op_load_gpr_T1(rs + 1);
2382 op_ldst(std);
2383 #endif
2384 } else {
2385 /* std / stdu */
2386 if (Rc(ctx->opcode)) {
2387 if (unlikely(rA(ctx->opcode) == 0)) {
2388 GEN_EXCP_INVAL(ctx);
2389 return;
2390 }
2391 }
2392 gen_addr_imm_index(ctx, 0x03);
2393 gen_op_load_gpr_T1(rs);
2394 op_ldst(std);
2395 if (Rc(ctx->opcode))
2396 gen_op_store_T0_gpr(rA(ctx->opcode));
2397 }
2398 }
2399 #endif
2400 /*** Integer load and store with byte reverse ***/
2401 /* lhbrx */
2402 OP_LD_TABLE(hbr);
2403 GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
2404 /* lwbrx */
2405 OP_LD_TABLE(wbr);
2406 GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
2407 /* sthbrx */
2408 OP_ST_TABLE(hbr);
2409 GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
2410 /* stwbrx */
2411 OP_ST_TABLE(wbr);
2412 GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
2413
2414 /*** Integer load and store multiple ***/
2415 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2416 static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2417 GEN_MEM_FUNCS(lmw),
2418 };
2419 static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2420 GEN_MEM_FUNCS(stmw),
2421 };
2422
2423 /* lmw */
2424 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2425 {
2426 /* NIP cannot be restored if the memory exception comes from an helper */
2427 gen_update_nip(ctx, ctx->nip - 4);
2428 gen_addr_imm_index(ctx, 0);
2429 op_ldstm(lmw, rD(ctx->opcode));
2430 }
2431
2432 /* stmw */
2433 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2434 {
2435 /* NIP cannot be restored if the memory exception comes from an helper */
2436 gen_update_nip(ctx, ctx->nip - 4);
2437 gen_addr_imm_index(ctx, 0);
2438 op_ldstm(stmw, rS(ctx->opcode));
2439 }
2440
2441 /*** Integer load and store strings ***/
2442 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2443 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2444 /* string load & stores are by definition endian-safe */
2445 #define gen_op_lswi_le_raw gen_op_lswi_raw
2446 #define gen_op_lswi_le_user gen_op_lswi_user
2447 #define gen_op_lswi_le_kernel gen_op_lswi_kernel
2448 #define gen_op_lswi_le_hypv gen_op_lswi_hypv
2449 #define gen_op_lswi_le_64_raw gen_op_lswi_raw
2450 #define gen_op_lswi_le_64_user gen_op_lswi_user
2451 #define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2452 #define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
2453 static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2454 GEN_MEM_FUNCS(lswi),
2455 };
2456 #define gen_op_lswx_le_raw gen_op_lswx_raw
2457 #define gen_op_lswx_le_user gen_op_lswx_user
2458 #define gen_op_lswx_le_kernel gen_op_lswx_kernel
2459 #define gen_op_lswx_le_hypv gen_op_lswx_hypv
2460 #define gen_op_lswx_le_64_raw gen_op_lswx_raw
2461 #define gen_op_lswx_le_64_user gen_op_lswx_user
2462 #define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2463 #define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
2464 static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2465 GEN_MEM_FUNCS(lswx),
2466 };
2467 #define gen_op_stsw_le_raw gen_op_stsw_raw
2468 #define gen_op_stsw_le_user gen_op_stsw_user
2469 #define gen_op_stsw_le_kernel gen_op_stsw_kernel
2470 #define gen_op_stsw_le_hypv gen_op_stsw_hypv
2471 #define gen_op_stsw_le_64_raw gen_op_stsw_raw
2472 #define gen_op_stsw_le_64_user gen_op_stsw_user
2473 #define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
2474 #define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
2475 static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
2476 GEN_MEM_FUNCS(stsw),
2477 };
2478
2479 /* lswi */
2480 /* PowerPC32 specification says we must generate an exception if
2481 * rA is in the range of registers to be loaded.
2482 * In an other hand, IBM says this is valid, but rA won't be loaded.
2483 * For now, I'll follow the spec...
2484 */
2485 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
2486 {
2487 int nb = NB(ctx->opcode);
2488 int start = rD(ctx->opcode);
2489 int ra = rA(ctx->opcode);
2490 int nr;
2491
2492 if (nb == 0)
2493 nb = 32;
2494 nr = nb / 4;
2495 if (unlikely(((start + nr) > 32 &&
2496 start <= ra && (start + nr - 32) > ra) ||
2497 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2498 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2499 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
2500 return;
2501 }
2502 /* NIP cannot be restored if the memory exception comes from an helper */
2503 gen_update_nip(ctx, ctx->nip - 4);
2504 gen_addr_register(ctx);
2505 gen_op_set_T1(nb);
2506 op_ldsts(lswi, start);
2507 }
2508
2509 /* lswx */
2510 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
2511 {
2512 int ra = rA(ctx->opcode);
2513 int rb = rB(ctx->opcode);
2514
2515 /* NIP cannot be restored if the memory exception comes from an helper */
2516 gen_update_nip(ctx, ctx->nip - 4);
2517 gen_addr_reg_index(ctx);
2518 if (ra == 0) {
2519 ra = rb;
2520 }
2521 gen_op_load_xer_bc();
2522 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
2523 }
2524
2525 /* stswi */
2526 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
2527 {
2528 int nb = NB(ctx->opcode);
2529
2530 /* NIP cannot be restored if the memory exception comes from an helper */
2531 gen_update_nip(ctx, ctx->nip - 4);
2532 gen_addr_register(ctx);
2533 if (nb == 0)
2534 nb = 32;
2535 gen_op_set_T1(nb);
2536 op_ldsts(stsw, rS(ctx->opcode));
2537 }
2538
2539 /* stswx */
2540 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
2541 {
2542 /* NIP cannot be restored if the memory exception comes from an helper */
2543 gen_update_nip(ctx, ctx->nip - 4);
2544 gen_addr_reg_index(ctx);
2545 gen_op_load_xer_bc();
2546 op_ldsts(stsw, rS(ctx->opcode));
2547 }
2548
2549 /*** Memory synchronisation ***/
2550 /* eieio */
2551 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
2552 {
2553 }
2554
2555 /* isync */
2556 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
2557 {
2558 GEN_STOP(ctx);
2559 }
2560
2561 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2562 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2563 static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
2564 GEN_MEM_FUNCS(lwarx),
2565 };
2566 static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
2567 GEN_MEM_FUNCS(stwcx),
2568 };
2569
2570 /* lwarx */
2571 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
2572 {
2573 /* NIP cannot be restored if the memory exception comes from an helper */
2574 gen_update_nip(ctx, ctx->nip - 4);
2575 gen_addr_reg_index(ctx);
2576 op_lwarx();
2577 gen_op_store_T1_gpr(rD(ctx->opcode));
2578 }
2579
2580 /* stwcx. */
2581 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2582 {
2583 /* NIP cannot be restored if the memory exception comes from an helper */
2584 gen_update_nip(ctx, ctx->nip - 4);
2585 gen_addr_reg_index(ctx);
2586 gen_op_load_gpr_T1(rS(ctx->opcode));
2587 op_stwcx();
2588 }
2589
2590 #if defined(TARGET_PPC64)
2591 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2592 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2593 static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
2594 GEN_MEM_FUNCS(ldarx),
2595 };
2596 static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
2597 GEN_MEM_FUNCS(stdcx),
2598 };
2599
2600 /* ldarx */
2601 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2602 {
2603 /* NIP cannot be restored if the memory exception comes from an helper */
2604 gen_update_nip(ctx, ctx->nip - 4);
2605 gen_addr_reg_index(ctx);
2606 op_ldarx();
2607 gen_op_store_T1_gpr(rD(ctx->opcode));
2608 }
2609
2610 /* stdcx. */
2611 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2612 {
2613 /* NIP cannot be restored if the memory exception comes from an helper */
2614 gen_update_nip(ctx, ctx->nip - 4);
2615 gen_addr_reg_index(ctx);
2616 gen_op_load_gpr_T1(rS(ctx->opcode));
2617 op_stdcx();
2618 }
2619 #endif /* defined(TARGET_PPC64) */
2620
2621 /* sync */
2622 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
2623 {
2624 }
2625
2626 /* wait */
2627 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2628 {
2629 /* Stop translation, as the CPU is supposed to sleep from now */
2630 gen_op_wait();
2631 GEN_EXCP(ctx, EXCP_HLT, 1);
2632 }
2633
2634 /*** Floating-point load ***/
2635 #define GEN_LDF(width, opc, type) \
2636 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2637 { \
2638 if (unlikely(!ctx->fpu_enabled)) { \
2639 GEN_EXCP_NO_FP(ctx); \
2640 return; \
2641 } \
2642 gen_addr_imm_index(ctx, 0); \
2643 op_ldst(l##width); \
2644 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2645 }
2646
2647 #define GEN_LDUF(width, opc, type) \
2648 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2649 { \
2650 if (unlikely(!ctx->fpu_enabled)) { \
2651 GEN_EXCP_NO_FP(ctx); \
2652 return; \
2653 } \
2654 if (unlikely(rA(ctx->opcode) == 0)) { \
2655 GEN_EXCP_INVAL(ctx); \
2656 return; \
2657 } \
2658 gen_addr_imm_index(ctx, 0); \
2659 op_ldst(l##width); \
2660 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2661 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2662 }
2663
2664 #define GEN_LDUXF(width, opc, type) \
2665 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2666 { \
2667 if (unlikely(!ctx->fpu_enabled)) { \
2668 GEN_EXCP_NO_FP(ctx); \
2669 return; \
2670 } \
2671 if (unlikely(rA(ctx->opcode) == 0)) { \
2672 GEN_EXCP_INVAL(ctx); \
2673 return; \
2674 } \
2675 gen_addr_reg_index(ctx); \
2676 op_ldst(l##width); \
2677 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2678 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2679 }
2680
2681 #define GEN_LDXF(width, opc2, opc3, type) \
2682 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2683 { \
2684 if (unlikely(!ctx->fpu_enabled)) { \
2685 GEN_EXCP_NO_FP(ctx); \
2686 return; \
2687 } \
2688 gen_addr_reg_index(ctx); \
2689 op_ldst(l##width); \
2690 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2691 }
2692
2693 #define GEN_LDFS(width, op, type) \
2694 OP_LD_TABLE(width); \
2695 GEN_LDF(width, op | 0x20, type); \
2696 GEN_LDUF(width, op | 0x21, type); \
2697 GEN_LDUXF(width, op | 0x01, type); \
2698 GEN_LDXF(width, 0x17, op | 0x00, type)
2699
2700 /* lfd lfdu lfdux lfdx */
2701 GEN_LDFS(fd, 0x12, PPC_FLOAT);
2702 /* lfs lfsu lfsux lfsx */
2703 GEN_LDFS(fs, 0x10, PPC_FLOAT);
2704
2705 /*** Floating-point store ***/
2706 #define GEN_STF(width, opc, type) \
2707 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2708 { \
2709 if (unlikely(!ctx->fpu_enabled)) { \
2710 GEN_EXCP_NO_FP(ctx); \
2711 return; \
2712 } \
2713 gen_addr_imm_index(ctx, 0); \
2714 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2715 op_ldst(st##width); \
2716 }
2717
2718 #define GEN_STUF(width, opc, type) \
2719 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2720 { \
2721 if (unlikely(!ctx->fpu_enabled)) { \
2722 GEN_EXCP_NO_FP(ctx); \
2723 return; \
2724 } \
2725 if (unlikely(rA(ctx->opcode) == 0)) { \
2726 GEN_EXCP_INVAL(ctx); \
2727 return; \
2728 } \
2729 gen_addr_imm_index(ctx, 0); \
2730 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2731 op_ldst(st##width); \
2732 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2733 }
2734
2735 #define GEN_STUXF(width, opc, type) \
2736 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2737 { \
2738 if (unlikely(!ctx->fpu_enabled)) { \
2739 GEN_EXCP_NO_FP(ctx); \
2740 return; \
2741 } \
2742 if (unlikely(rA(ctx->opcode) == 0)) { \
2743 GEN_EXCP_INVAL(ctx); \
2744 return; \
2745 } \
2746 gen_addr_reg_index(ctx); \
2747 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2748 op_ldst(st##width); \
2749 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2750 }
2751
2752 #define GEN_STXF(width, opc2, opc3, type) \
2753 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2754 { \
2755 if (unlikely(!ctx->fpu_enabled)) { \
2756 GEN_EXCP_NO_FP(ctx); \
2757 return; \
2758 } \
2759 gen_addr_reg_index(ctx); \
2760 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2761 op_ldst(st##width); \
2762 }
2763
2764 #define GEN_STFS(width, op, type) \
2765 OP_ST_TABLE(width); \
2766 GEN_STF(width, op | 0x20, type); \
2767 GEN_STUF(width, op | 0x21, type); \
2768 GEN_STUXF(width, op | 0x01, type); \
2769 GEN_STXF(width, 0x17, op | 0x00, type)
2770
2771 /* stfd stfdu stfdux stfdx */
2772 GEN_STFS(fd, 0x16, PPC_FLOAT);
2773 /* stfs stfsu stfsux stfsx */
2774 GEN_STFS(fs, 0x14, PPC_FLOAT);
2775
2776 /* Optional: */
2777 /* stfiwx */
2778 OP_ST_TABLE(fiw);
2779 GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
2780
2781 /*** Branch ***/
2782 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2783 target_ulong dest)
2784 {
2785 TranslationBlock *tb;
2786 tb = ctx->tb;
2787 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
2788 !ctx->singlestep_enabled) {
2789 tcg_gen_goto_tb(n);
2790 gen_set_T1(dest);
2791 #if defined(TARGET_PPC64)
2792 if (ctx->sf_mode)
2793 gen_op_b_T1_64();
2794 else
2795 #endif
2796 gen_op_b_T1();
2797 tcg_gen_exit_tb((long)tb + n);
2798 } else {
2799 gen_set_T1(dest);
2800 #if defined(TARGET_PPC64)
2801 if (ctx->sf_mode)
2802 gen_op_b_T1_64();
2803 else
2804 #endif
2805 gen_op_b_T1();
2806 if (ctx->singlestep_enabled)
2807 gen_op_debug();
2808 tcg_gen_exit_tb(0);
2809 }
2810 }
2811
2812 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
2813 {
2814 #if defined(TARGET_PPC64)
2815 if (ctx->sf_mode != 0 && (nip >> 32))
2816 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
2817 else
2818 #endif
2819 gen_op_setlr(ctx->nip);
2820 }
2821
2822 /* b ba bl bla */
2823 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
2824 {
2825 target_ulong li, target;
2826
2827 /* sign extend LI */
2828 #if defined(TARGET_PPC64)
2829 if (ctx->sf_mode)
2830 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
2831 else
2832 #endif
2833 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
2834 if (likely(AA(ctx->opcode) == 0))
2835 target = ctx->nip + li - 4;
2836 else
2837 target = li;
2838 #if defined(TARGET_PPC64)
2839 if (!ctx->sf_mode)
2840 target = (uint32_t)target;
2841 #endif
2842 if (LK(ctx->opcode))
2843 gen_setlr(ctx, ctx->nip);
2844 gen_goto_tb(ctx, 0, target);
2845 ctx->exception = POWERPC_EXCP_BRANCH;
2846 }
2847
2848 #define BCOND_IM 0
2849 #define BCOND_LR 1
2850 #define BCOND_CTR 2
2851
2852 static always_inline void gen_bcond (DisasContext *ctx, int type)
2853 {
2854 target_ulong target = 0;
2855 target_ulong li;
2856 uint32_t bo = BO(ctx->opcode);
2857 uint32_t bi = BI(ctx->opcode);
2858 uint32_t mask;
2859
2860 if ((bo & 0x4) == 0)
2861 gen_op_dec_ctr();
2862 switch(type) {
2863 case BCOND_IM:
2864 li = (target_long)((int16_t)(BD(ctx->opcode)));
2865 if (likely(AA(ctx->opcode) == 0)) {
2866 target = ctx->nip + li - 4;
2867 } else {
2868 target = li;
2869 }
2870 #if defined(TARGET_PPC64)
2871 if (!ctx->sf_mode)
2872 target = (uint32_t)target;
2873 #endif
2874 break;
2875 case BCOND_CTR:
2876 gen_op_movl_T1_ctr();
2877 break;
2878 default:
2879 case BCOND_LR:
2880 gen_op_movl_T1_lr();
2881 break;
2882 }
2883 if (LK(ctx->opcode))
2884 gen_setlr(ctx, ctx->nip);
2885 if (bo & 0x10) {
2886 /* No CR condition */
2887 switch (bo & 0x6) {
2888 case 0:
2889 #if defined(TARGET_PPC64)
2890 if (ctx->sf_mode)
2891 gen_op_test_ctr_64();
2892 else
2893 #endif
2894 gen_op_test_ctr();
2895 break;
2896 case 2:
2897 #if defined(TARGET_PPC64)
2898 if (ctx->sf_mode)
2899 gen_op_test_ctrz_64();
2900 else
2901 #endif
2902 gen_op_test_ctrz();
2903 break;
2904 default:
2905 case 4:
2906 case 6:
2907 if (type == BCOND_IM) {
2908 gen_goto_tb(ctx, 0, target);
2909 goto out;
2910 } else {
2911 #if defined(TARGET_PPC64)
2912 if (ctx->sf_mode)
2913 gen_op_b_T1_64();
2914 else
2915 #endif
2916 gen_op_b_T1();
2917 goto no_test;
2918 }
2919 break;
2920 }
2921 } else {
2922 mask = 1 << (3 - (bi & 0x03));
2923 gen_op_load_crf_T0(bi >> 2);
2924 if (bo & 0x8) {
2925 switch (bo & 0x6) {
2926 case 0:
2927 #if defined(TARGET_PPC64)
2928 if (ctx->sf_mode)
2929 gen_op_test_ctr_true_64(mask);
2930 else
2931 #endif
2932 gen_op_test_ctr_true(mask);
2933 break;
2934 case 2:
2935 #if defined(TARGET_PPC64)
2936 if (ctx->sf_mode)
2937 gen_op_test_ctrz_true_64(mask);
2938 else
2939 #endif
2940 gen_op_test_ctrz_true(mask);
2941 break;
2942 default:
2943 case 4:
2944 case 6:
2945 gen_op_test_true(mask);
2946 break;
2947 }
2948 } else {
2949 switch (bo & 0x6) {
2950 case 0:
2951 #if defined(TARGET_PPC64)
2952 if (ctx->sf_mode)
2953 gen_op_test_ctr_false_64(mask);
2954 else
2955 #endif
2956 gen_op_test_ctr_false(mask);
2957 break;
2958 case 2:
2959 #if defined(TARGET_PPC64)
2960 if (ctx->sf_mode)
2961 gen_op_test_ctrz_false_64(mask);
2962 else
2963 #endif
2964 gen_op_test_ctrz_false(mask);
2965 break;
2966 default:
2967 case 4:
2968 case 6:
2969 gen_op_test_false(mask);
2970 break;
2971 }
2972 }
2973 }
2974 if (type == BCOND_IM) {
2975 int l1 = gen_new_label();
2976 gen_op_jz_T0(l1);
2977 gen_goto_tb(ctx, 0, target);
2978 gen_set_label(l1);
2979 gen_goto_tb(ctx, 1, ctx->nip);
2980 } else {
2981 #if defined(TARGET_PPC64)
2982 if (ctx->sf_mode)
2983 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
2984 else
2985 #endif
2986 gen_op_btest_T1(ctx->nip);
2987 no_test:
2988 if (ctx->singlestep_enabled)
2989 gen_op_debug();
2990 tcg_gen_exit_tb(0);
2991 }
2992 out:
2993 ctx->exception = POWERPC_EXCP_BRANCH;
2994 }
2995
2996 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
2997 {
2998 gen_bcond(ctx, BCOND_IM);
2999 }
3000
3001 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3002 {
3003 gen_bcond(ctx, BCOND_CTR);
3004 }
3005
3006 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3007 {
3008 gen_bcond(ctx, BCOND_LR);
3009 }
3010
3011 /*** Condition register logical ***/
3012 #define GEN_CRLOGIC(op, opc) \
3013 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3014 { \
3015 uint8_t bitmask; \
3016 int sh; \
3017 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
3018 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3019 if (sh > 0) \
3020 gen_op_srli_T0(sh); \
3021 else if (sh < 0) \
3022 gen_op_sli_T0(-sh); \
3023 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
3024 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3025 if (sh > 0) \
3026 gen_op_srli_T1(sh); \
3027 else if (sh < 0) \
3028 gen_op_sli_T1(-sh); \
3029 gen_op_##op(); \
3030 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3031 gen_op_andi_T0(bitmask); \
3032 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
3033 gen_op_andi_T1(~bitmask); \
3034 gen_op_or(); \
3035 gen_op_store_T0_crf(crbD(ctx->opcode) >> 2); \
3036 }
3037
3038 /* crand */
3039 GEN_CRLOGIC(and, 0x08);
3040 /* crandc */
3041 GEN_CRLOGIC(andc, 0x04);
3042 /* creqv */
3043 GEN_CRLOGIC(eqv, 0x09);
3044 /* crnand */
3045 GEN_CRLOGIC(nand, 0x07);
3046 /* crnor */
3047 GEN_CRLOGIC(nor, 0x01);
3048 /* cror */
3049 GEN_CRLOGIC(or, 0x0E);
3050 /* crorc */
3051 GEN_CRLOGIC(orc, 0x0D);
3052 /* crxor */
3053 GEN_CRLOGIC(xor, 0x06);
3054 /* mcrf */
3055 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3056 {
3057 gen_op_load_crf_T0(crfS(ctx->opcode));
3058 gen_op_store_T0_crf(crfD(ctx->opcode));
3059 }
3060
3061 /*** System linkage ***/
3062 /* rfi (supervisor only) */
3063 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3064 {
3065 #if defined(CONFIG_USER_ONLY)
3066 GEN_EXCP_PRIVOPC(ctx);
3067 #else
3068 /* Restore CPU state */
3069 if (unlikely(!ctx->supervisor)) {
3070 GEN_EXCP_PRIVOPC(ctx);
3071 return;
3072 }
3073 gen_op_rfi();
3074 GEN_SYNC(ctx);
3075 #endif
3076 }
3077
3078 #if defined(TARGET_PPC64)
3079 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3080 {
3081 #if defined(CONFIG_USER_ONLY)
3082 GEN_EXCP_PRIVOPC(ctx);
3083 #else
3084 /* Restore CPU state */
3085 if (unlikely(!ctx->supervisor)) {
3086 GEN_EXCP_PRIVOPC(ctx);
3087 return;
3088 }
3089 gen_op_rfid();
3090 GEN_SYNC(ctx);
3091 #endif
3092 }
3093
3094 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3095 {
3096 #if defined(CONFIG_USER_ONLY)
3097 GEN_EXCP_PRIVOPC(ctx);
3098 #else
3099 /* Restore CPU state */
3100 if (unlikely(ctx->supervisor <= 1)) {
3101 GEN_EXCP_PRIVOPC(ctx);
3102 return;
3103 }
3104 gen_op_hrfid();
3105 GEN_SYNC(ctx);
3106 #endif
3107 }
3108 #endif
3109
3110 /* sc */
3111 #if defined(CONFIG_USER_ONLY)
3112 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3113 #else
3114 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3115 #endif
3116 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3117 {
3118 uint32_t lev;
3119
3120 lev = (ctx->opcode >> 5) & 0x7F;
3121 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3122 }
3123
3124 /*** Trap ***/
3125 /* tw */
3126 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3127 {
3128 gen_op_load_gpr_T0(rA(ctx->opcode));
3129 gen_op_load_gpr_T1(rB(ctx->opcode));
3130 /* Update the nip since this might generate a trap exception */
3131 gen_update_nip(ctx, ctx->nip);
3132 gen_op_tw(TO(ctx->opcode));
3133 }
3134
3135 /* twi */
3136 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3137 {
3138 gen_op_load_gpr_T0(rA(ctx->opcode));
3139 gen_set_T1(SIMM(ctx->opcode));
3140 /* Update the nip since this might generate a trap exception */
3141 gen_update_nip(ctx, ctx->nip);
3142 gen_op_tw(TO(ctx->opcode));
3143 }
3144
3145 #if defined(TARGET_PPC64)
3146 /* td */
3147 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3148 {
3149 gen_op_load_gpr_T0(rA(ctx->opcode));
3150 gen_op_load_gpr_T1(rB(ctx->opcode));
3151 /* Update the nip since this might generate a trap exception */
3152 gen_update_nip(ctx, ctx->nip);
3153 gen_op_td(TO(ctx->opcode));
3154 }
3155
3156 /* tdi */
3157 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3158 {
3159 gen_op_load_gpr_T0(rA(ctx->opcode));
3160 gen_set_T1(SIMM(ctx->opcode));
3161 /* Update the nip since this might generate a trap exception */
3162 gen_update_nip(ctx, ctx->nip);
3163 gen_op_td(TO(ctx->opcode));
3164 }
3165 #endif
3166
3167 /*** Processor control ***/
3168 /* mcrxr */
3169 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3170 {
3171 gen_op_load_xer_cr();
3172 gen_op_store_T0_crf(crfD(ctx->opcode));
3173 gen_op_clear_xer_ov();
3174 gen_op_clear_xer_ca();
3175 }
3176
3177 /* mfcr */
3178 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3179 {
3180 uint32_t crm, crn;
3181
3182 if (likely(ctx->opcode & 0x00100000)) {
3183 crm = CRM(ctx->opcode);
3184 if (likely((crm ^ (crm - 1)) == 0)) {
3185 crn = ffs(crm);
3186 gen_op_load_cro(7 - crn);
3187 }
3188 } else {
3189 gen_op_load_cr();
3190 }
3191 gen_op_store_T0_gpr(rD(ctx->opcode));
3192 }
3193
3194 /* mfmsr */
3195 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3196 {
3197 #if defined(CONFIG_USER_ONLY)
3198 GEN_EXCP_PRIVREG(ctx);
3199 #else
3200 if (unlikely(!ctx->supervisor)) {
3201 GEN_EXCP_PRIVREG(ctx);
3202 return;
3203 }
3204 gen_op_load_msr();
3205 gen_op_store_T0_gpr(rD(ctx->opcode));
3206 #endif
3207 }
3208
3209 #if 1
3210 #define SPR_NOACCESS ((void *)(-1UL))
3211 #else
3212 static void spr_noaccess (void *opaque, int sprn)
3213 {
3214 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3215 printf("ERROR: try to access SPR %d !\n", sprn);
3216 }
3217 #define SPR_NOACCESS (&spr_noaccess)
3218 #endif
3219
3220 /* mfspr */
3221 static always_inline void gen_op_mfspr (DisasContext *ctx)
3222 {
3223 void (*read_cb)(void *opaque, int sprn);
3224 uint32_t sprn = SPR(ctx->opcode);
3225
3226 #if !defined(CONFIG_USER_ONLY)
3227 if (ctx->supervisor == 2)
3228 read_cb = ctx->spr_cb[sprn].hea_read;
3229 else if (ctx->supervisor)
3230 read_cb = ctx->spr_cb[sprn].oea_read;
3231 else
3232 #endif
3233 read_cb = ctx->spr_cb[sprn].uea_read;
3234 if (likely(read_cb != NULL)) {
3235 if (likely(read_cb != SPR_NOACCESS)) {
3236 (*read_cb)(ctx, sprn);
3237 gen_op_store_T0_gpr(rD(ctx->opcode));
3238 } else {
3239 /* Privilege exception */
3240 /* This is a hack to avoid warnings when running Linux:
3241 * this OS breaks the PowerPC virtualisation model,
3242 * allowing userland application to read the PVR
3243 */
3244 if (sprn != SPR_PVR) {
3245 if (loglevel != 0) {
3246 fprintf(logfile, "Trying to read privileged spr %d %03x at "
3247 ADDRX "\n", sprn, sprn, ctx->nip);
3248 }
3249 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3250 sprn, sprn, ctx->nip);
3251 }
3252 GEN_EXCP_PRIVREG(ctx);
3253 }
3254 } else {
3255 /* Not defined */
3256 if (loglevel != 0) {
3257 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3258 ADDRX "\n", sprn, sprn, ctx->nip);
3259 }
3260 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3261 sprn, sprn, ctx->nip);
3262 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3263 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3264 }
3265 }
3266
3267 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3268 {
3269 gen_op_mfspr(ctx);
3270 }
3271
3272 /* mftb */
3273 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3274 {
3275 gen_op_mfspr(ctx);
3276 }
3277
3278 /* mtcrf */
3279 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3280 {
3281 uint32_t crm, crn;
3282
3283 gen_op_load_gpr_T0(rS(ctx->opcode));
3284 crm = CRM(ctx->opcode);
3285 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3286 crn = ffs(crm);
3287 gen_op_srli_T0(crn * 4);
3288 gen_op_andi_T0(0xF);
3289 gen_op_store_cro(7 - crn);
3290 } else {
3291 gen_op_store_cr(crm);
3292 }
3293 }
3294
3295 /* mtmsr */
3296 #if defined(TARGET_PPC64)
3297 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3298 {
3299 #if defined(CONFIG_USER_ONLY)
3300 GEN_EXCP_PRIVREG(ctx);
3301 #else
3302 if (unlikely(!ctx->supervisor)) {
3303 GEN_EXCP_PRIVREG(ctx);
3304 return;
3305 }
3306 gen_op_load_gpr_T0(rS(ctx->opcode));
3307 if (ctx->opcode & 0x00010000) {
3308 /* Special form that does not need any synchronisation */
3309 gen_op_update_riee();
3310 } else {
3311 /* XXX: we need to update nip before the store
3312 * if we enter power saving mode, we will exit the loop
3313 * directly from ppc_store_msr
3314 */
3315 gen_update_nip(ctx, ctx->nip);
3316 gen_op_store_msr();
3317 /* Must stop the translation as machine state (may have) changed */
3318 /* Note that mtmsr is not always defined as context-synchronizing */
3319 ctx->exception = POWERPC_EXCP_STOP;
3320 }
3321 #endif
3322 }
3323 #endif
3324
3325 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3326 {
3327 #if defined(CONFIG_USER_ONLY)
3328 GEN_EXCP_PRIVREG(ctx);
3329 #else
3330 if (unlikely(!ctx->supervisor)) {
3331 GEN_EXCP_PRIVREG(ctx);
3332 return;
3333 }
3334 gen_op_load_gpr_T0(rS(ctx->opcode));
3335 if (ctx->opcode & 0x00010000) {
3336 /* Special form that does not need any synchronisation */
3337 gen_op_update_riee();
3338 } else {
3339 /* XXX: we need to update nip before the store
3340 * if we enter power saving mode, we will exit the loop
3341 * directly from ppc_store_msr
3342 */
3343 gen_update_nip(ctx, ctx->nip);
3344 #if defined(TARGET_PPC64)
3345 if (!ctx->sf_mode)
3346 gen_op_store_msr_32();
3347 else
3348 #endif
3349 gen_op_store_msr();
3350 /* Must stop the translation as machine state (may have) changed */
3351 /* Note that mtmsrd is not always defined as context-synchronizing */
3352 ctx->exception = POWERPC_EXCP_STOP;
3353 }
3354 #endif
3355 }
3356
3357 /* mtspr */
3358 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3359 {
3360 void (*write_cb)(void *opaque, int sprn);
3361 uint32_t sprn = SPR(ctx->opcode);
3362
3363 #if !defined(CONFIG_USER_ONLY)
3364 if (ctx->supervisor == 2)
3365 write_cb = ctx->spr_cb[sprn].hea_write;
3366 else if (ctx->supervisor)
3367 write_cb = ctx->spr_cb[sprn].oea_write;
3368 else
3369 #endif
3370 write_cb = ctx->spr_cb[sprn].uea_write;
3371 if (likely(write_cb != NULL)) {
3372 if (likely(write_cb != SPR_NOACCESS)) {
3373 gen_op_load_gpr_T0(rS(ctx->opcode));
3374 (*write_cb)(ctx, sprn);
3375 } else {
3376 /* Privilege exception */
3377 if (loglevel != 0) {
3378 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3379 ADDRX "\n", sprn, sprn, ctx->nip);
3380 }
3381 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3382 sprn, sprn, ctx->nip);
3383 GEN_EXCP_PRIVREG(ctx);
3384 }
3385 } else {
3386 /* Not defined */
3387 if (loglevel != 0) {
3388 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3389 ADDRX "\n", sprn, sprn, ctx->nip);
3390 }
3391 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3392 sprn, sprn, ctx->nip);
3393 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3394 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3395 }
3396 }
3397
3398 /*** Cache management ***/
3399 /* dcbf */
3400 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
3401 {
3402 /* XXX: specification says this is treated as a load by the MMU */
3403 gen_addr_reg_index(ctx);
3404 op_ldst(lbz);
3405 }
3406
3407 /* dcbi (Supervisor only) */
3408 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
3409 {
3410 #if defined(CONFIG_USER_ONLY)
3411 GEN_EXCP_PRIVOPC(ctx);
3412 #else
3413 if (unlikely(!ctx->supervisor)) {
3414 GEN_EXCP_PRIVOPC(ctx);
3415 return;
3416 }
3417 gen_addr_reg_index(ctx);
3418 /* XXX: specification says this should be treated as a store by the MMU */
3419 op_ldst(lbz);
3420 op_ldst(stb);
3421 #endif
3422 }
3423
3424 /* dcdst */
3425 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
3426 {
3427 /* XXX: specification say this is treated as a load by the MMU */
3428 gen_addr_reg_index(ctx);
3429 op_ldst(lbz);
3430 }
3431
3432 /* dcbt */
3433 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
3434 {
3435 /* interpreted as no-op */
3436 /* XXX: specification say this is treated as a load by the MMU
3437 * but does not generate any exception
3438 */
3439 }
3440
3441 /* dcbtst */
3442 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
3443 {
3444 /* interpreted as no-op */
3445 /* XXX: specification say this is treated as a load by the MMU
3446 * but does not generate any exception
3447 */
3448 }
3449
3450 /* dcbz */
3451 #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3452 static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3453 /* 32 bytes cache line size */
3454 {
3455 #define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3456 #define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3457 #define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3458 #define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3459 #define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3460 #define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3461 #define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3462 #define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3463 GEN_MEM_FUNCS(dcbz_l32),
3464 },
3465 /* 64 bytes cache line size */
3466 {
3467 #define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3468 #define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3469 #define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3470 #define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3471 #define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3472 #define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3473 #define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3474 #define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3475 GEN_MEM_FUNCS(dcbz_l64),
3476 },
3477 /* 128 bytes cache line size */
3478 {
3479 #define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3480 #define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3481 #define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3482 #define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3483 #define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3484 #define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3485 #define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3486 #define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3487 GEN_MEM_FUNCS(dcbz_l128),
3488 },
3489 /* tunable cache line size */
3490 {
3491 #define gen_op_dcbz_le_raw gen_op_dcbz_raw
3492 #define gen_op_dcbz_le_user gen_op_dcbz_user
3493 #define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3494 #define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3495 #define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3496 #define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3497 #define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3498 #define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3499 GEN_MEM_FUNCS(dcbz),
3500 },
3501 };
3502
3503 static always_inline void handler_dcbz (DisasContext *ctx,
3504 int dcache_line_size)
3505 {
3506 int n;
3507
3508 switch (dcache_line_size) {
3509 case 32:
3510 n = 0;
3511 break;
3512 case 64:
3513 n = 1;
3514 break;
3515 case 128:
3516 n = 2;
3517 break;
3518 default:
3519 n = 3;
3520 break;
3521 }
3522 op_dcbz(n);
3523 }
3524
3525 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
3526 {
3527 gen_addr_reg_index(ctx);
3528 handler_dcbz(ctx, ctx->dcache_line_size);
3529 gen_op_check_reservation();
3530 }
3531
3532 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
3533 {
3534 gen_addr_reg_index(ctx);
3535 if (ctx->opcode & 0x00200000)
3536 handler_dcbz(ctx, ctx->dcache_line_size);
3537 else
3538 handler_dcbz(ctx, -1);
3539 gen_op_check_reservation();
3540 }
3541
3542 /* icbi */
3543 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3544 #define gen_op_icbi_le_raw gen_op_icbi_raw
3545 #define gen_op_icbi_le_user gen_op_icbi_user
3546 #define gen_op_icbi_le_kernel gen_op_icbi_kernel
3547 #define gen_op_icbi_le_hypv gen_op_icbi_hypv
3548 #define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
3549 #define gen_op_icbi_le_64_user gen_op_icbi_64_user
3550 #define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3551 #define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
3552 static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
3553 GEN_MEM_FUNCS(icbi),
3554 };
3555
3556 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
3557 {
3558 /* NIP cannot be restored if the memory exception comes from an helper */
3559 gen_update_nip(ctx, ctx->nip - 4);
3560 gen_addr_reg_index(ctx);
3561 op_icbi();
3562 }
3563
3564 /* Optional: */
3565 /* dcba */
3566 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
3567 {
3568 /* interpreted as no-op */
3569 /* XXX: specification say this is treated as a store by the MMU
3570 * but does not generate any exception
3571 */
3572 }
3573
3574 /*** Segment register manipulation ***/
3575 /* Supervisor only: */
3576 /* mfsr */
3577 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3578 {
3579 #if defined(CONFIG_USER_ONLY)
3580 GEN_EXCP_PRIVREG(ctx);
3581 #else
3582 if (unlikely(!ctx->supervisor)) {
3583 GEN_EXCP_PRIVREG(ctx);
3584 return;
3585 }
3586 gen_op_set_T1(SR(ctx->opcode));
3587 gen_op_load_sr();
3588 gen_op_store_T0_gpr(rD(ctx->opcode));
3589 #endif
3590 }
3591
3592 /* mfsrin */
3593 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
3594 {
3595 #if defined(CONFIG_USER_ONLY)
3596 GEN_EXCP_PRIVREG(ctx);
3597 #else
3598 if (unlikely(!ctx->supervisor)) {
3599 GEN_EXCP_PRIVREG(ctx);
3600 return;
3601 }
3602 gen_op_load_gpr_T1(rB(ctx->opcode));
3603 gen_op_srli_T1(28);
3604 gen_op_load_sr();
3605 gen_op_store_T0_gpr(rD(ctx->opcode));
3606 #endif
3607 }
3608
3609 /* mtsr */
3610 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
3611 {
3612 #if defined(CONFIG_USER_ONLY)
3613 GEN_EXCP_PRIVREG(ctx);
3614 #else
3615 if (unlikely(!ctx->supervisor)) {
3616 GEN_EXCP_PRIVREG(ctx);
3617 return;
3618 }
3619 gen_op_load_gpr_T0(rS(ctx->opcode));
3620 gen_op_set_T1(SR(ctx->opcode));
3621 gen_op_store_sr();
3622 #endif
3623 }
3624
3625 /* mtsrin */
3626 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
3627 {
3628 #if defined(CONFIG_USER_ONLY)
3629 GEN_EXCP_PRIVREG(ctx);
3630 #else
3631 if (unlikely(!ctx->supervisor)) {
3632 GEN_EXCP_PRIVREG(ctx);
3633 return;
3634 }
3635 gen_op_load_gpr_T0(rS(ctx->opcode));
3636 gen_op_load_gpr_T1(rB(ctx->opcode));
3637 gen_op_srli_T1(28);
3638 gen_op_store_sr();
3639 #endif
3640 }
3641
3642 #if defined(TARGET_PPC64)
3643 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3644 /* mfsr */
3645 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
3646 {
3647 #if defined(CONFIG_USER_ONLY)
3648 GEN_EXCP_PRIVREG(ctx);
3649 #else
3650 if (unlikely(!ctx->supervisor)) {
3651 GEN_EXCP_PRIVREG(ctx);
3652 return;
3653 }
3654 gen_op_set_T1(SR(ctx->opcode));
3655 gen_op_load_slb();
3656 gen_op_store_T0_gpr(rD(ctx->opcode));
3657 #endif
3658 }
3659
3660 /* mfsrin */
3661 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
3662 PPC_SEGMENT_64B)
3663 {
3664 #if defined(CONFIG_USER_ONLY)
3665 GEN_EXCP_PRIVREG(ctx);
3666 #else
3667 if (unlikely(!ctx->supervisor)) {
3668 GEN_EXCP_PRIVREG(ctx);
3669 return;
3670 }
3671 gen_op_load_gpr_T1(rB(ctx->opcode));
3672 gen_op_srli_T1(28);
3673 gen_op_load_slb();
3674 gen_op_store_T0_gpr(rD(ctx->opcode));
3675 #endif
3676 }
3677
3678 /* mtsr */
3679 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
3680 {
3681 #if defined(CONFIG_USER_ONLY)
3682 GEN_EXCP_PRIVREG(ctx);
3683 #else
3684 if (unlikely(!ctx->supervisor)) {
3685 GEN_EXCP_PRIVREG(ctx);
3686 return;
3687 }
3688 gen_op_load_gpr_T0(rS(ctx->opcode));
3689 gen_op_set_T1(SR(ctx->opcode));
3690 gen_op_store_slb();
3691 #endif
3692 }
3693
3694 /* mtsrin */
3695 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
3696 PPC_SEGMENT_64B)
3697 {
3698 #if defined(CONFIG_USER_ONLY)
3699 GEN_EXCP_PRIVREG(ctx);
3700 #else
3701 if (unlikely(!ctx->supervisor)) {
3702 GEN_EXCP_PRIVREG(ctx);
3703 return;
3704 }
3705 gen_op_load_gpr_T0(rS(ctx->opcode));
3706 gen_op_load_gpr_T1(rB(ctx->opcode));
3707 gen_op_srli_T1(28);
3708 gen_op_store_slb();
3709 #endif
3710 }
3711 #endif /* defined(TARGET_PPC64) */
3712
3713 /*** Lookaside buffer management ***/
3714 /* Optional & supervisor only: */
3715 /* tlbia */
3716 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
3717 {
3718 #if defined(CONFIG_USER_ONLY)
3719 GEN_EXCP_PRIVOPC(ctx);
3720 #else
3721 if (unlikely(!ctx->supervisor)) {
3722 GEN_EXCP_PRIVOPC(ctx);
3723 return;
3724 }
3725 gen_op_tlbia();
3726 #endif
3727 }
3728
3729 /* tlbie */
3730 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
3731 {
3732 #if defined(CONFIG_USER_ONLY)
3733 GEN_EXCP_PRIVOPC(ctx);
3734 #else
3735 if (unlikely(!ctx->supervisor)) {
3736 GEN_EXCP_PRIVOPC(ctx);
3737 return;
3738 }
3739 gen_op_load_gpr_T0(rB(ctx->opcode));
3740 #if defined(TARGET_PPC64)
3741 if (ctx->sf_mode)
3742 gen_op_tlbie_64();
3743 else
3744 #endif
3745 gen_op_tlbie();
3746 #endif
3747 }
3748
3749 /* tlbsync */
3750 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
3751 {
3752 #if defined(CONFIG_USER_ONLY)
3753 GEN_EXCP_PRIVOPC(ctx);
3754 #else
3755 if (unlikely(!ctx->supervisor)) {
3756 GEN_EXCP_PRIVOPC(ctx);
3757 return;
3758 }
3759 /* This has no effect: it should ensure that all previous
3760 * tlbie have completed
3761 */
3762 GEN_STOP(ctx);
3763 #endif
3764 }
3765
3766 #if defined(TARGET_PPC64)
3767 /* slbia */
3768 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
3769 {
3770 #if defined(CONFIG_USER_ONLY)
3771 GEN_EXCP_PRIVOPC(ctx);
3772 #else
3773 if (unlikely(!ctx->supervisor)) {
3774 GEN_EXCP_PRIVOPC(ctx);
3775 return;
3776 }
3777 gen_op_slbia();
3778 #endif
3779 }
3780
3781 /* slbie */
3782 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
3783 {
3784 #if defined(CONFIG_USER_ONLY)
3785 GEN_EXCP_PRIVOPC(ctx);
3786 #else
3787 if (unlikely(!ctx->supervisor)) {
3788 GEN_EXCP_PRIVOPC(ctx);
3789 return;
3790 }
3791 gen_op_load_gpr_T0(rB(ctx->opcode));
3792 gen_op_slbie();
3793 #endif
3794 }
3795 #endif
3796
3797 /*** External control ***/
3798 /* Optional: */
3799 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
3800 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
3801 static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
3802 GEN_MEM_FUNCS(eciwx),
3803 };
3804 static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
3805 GEN_MEM_FUNCS(ecowx),
3806 };
3807
3808 /* eciwx */
3809 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
3810 {
3811 /* Should check EAR[E] & alignment ! */
3812 gen_addr_reg_index(ctx);
3813 op_eciwx();
3814 gen_op_store_T0_gpr(rD(ctx->opcode));
3815 }
3816
3817 /* ecowx */
3818 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
3819 {
3820 /* Should check EAR[E] & alignment ! */
3821 gen_addr_reg_index(ctx);
3822 gen_op_load_gpr_T1(rS(ctx->opcode));
3823 op_ecowx();
3824 }
3825
3826 /* PowerPC 601 specific instructions */
3827 /* abs - abs. */
3828 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
3829 {
3830 gen_op_load_gpr_T0(rA(ctx->opcode));
3831 gen_op_POWER_abs();
3832 gen_op_store_T0_gpr(rD(ctx->opcode));
3833 if (unlikely(Rc(ctx->opcode) != 0))
3834 gen_set_Rc0(ctx);
3835 }
3836
3837 /* abso - abso. */
3838 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
3839 {
3840 gen_op_load_gpr_T0(rA(ctx->opcode));
3841 gen_op_POWER_abso();
3842 gen_op_store_T0_gpr(rD(ctx->opcode));
3843 if (unlikely(Rc(ctx->opcode) != 0))
3844 gen_set_Rc0(ctx);
3845 }
3846
3847 /* clcs */
3848 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
3849 {
3850 gen_op_load_gpr_T0(rA(ctx->opcode));
3851 gen_op_POWER_clcs();
3852 /* Rc=1 sets CR0 to an undefined state */
3853 gen_op_store_T0_gpr(rD(ctx->opcode));
3854 }
3855
3856 /* div - div. */
3857 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
3858 {
3859 gen_op_load_gpr_T0(rA(ctx->opcode));
3860 gen_op_load_gpr_T1(rB(ctx->opcode));
3861 gen_op_POWER_div();
3862 gen_op_store_T0_gpr(rD(ctx->opcode));
3863 if (unlikely(Rc(ctx->opcode) != 0))
3864 gen_set_Rc0(ctx);
3865 }
3866
3867 /* divo - divo. */
3868 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
3869 {
3870 gen_op_load_gpr_T0(rA(ctx->opcode));
3871 gen_op_load_gpr_T1(rB(ctx->opcode));
3872 gen_op_POWER_divo();
3873 gen_op_store_T0_gpr(rD(ctx->opcode));
3874 if (unlikely(Rc(ctx->opcode) != 0))
3875 gen_set_Rc0(ctx);
3876 }
3877
3878 /* divs - divs. */
3879 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
3880 {
3881 gen_op_load_gpr_T0(rA(ctx->opcode));
3882 gen_op_load_gpr_T1(rB(ctx->opcode));
3883 gen_op_POWER_divs();
3884 gen_op_store_T0_gpr(rD(ctx->opcode));
3885 if (unlikely(Rc(ctx->opcode) != 0))
3886 gen_set_Rc0(ctx);
3887 }
3888
3889 /* divso - divso. */
3890 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
3891 {
3892 gen_op_load_gpr_T0(rA(ctx->opcode));
3893 gen_op_load_gpr_T1(rB(ctx->opcode));
3894 gen_op_POWER_divso();
3895 gen_op_store_T0_gpr(rD(ctx->opcode));
3896 if (unlikely(Rc(ctx->opcode) != 0))
3897 gen_set_Rc0(ctx);
3898 }
3899
3900 /* doz - doz. */
3901 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
3902 {
3903 gen_op_load_gpr_T0(rA(ctx->opcode));
3904 gen_op_load_gpr_T1(rB(ctx->opcode));
3905 gen_op_POWER_doz();
3906 gen_op_store_T0_gpr(rD(ctx->opcode));
3907 if (unlikely(Rc(ctx->opcode) != 0))
3908 gen_set_Rc0(ctx);
3909 }
3910
3911 /* dozo - dozo. */
3912 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
3913 {
3914 gen_op_load_gpr_T0(rA(ctx->opcode));
3915 gen_op_load_gpr_T1(rB(ctx->opcode));
3916 gen_op_POWER_dozo();
3917 gen_op_store_T0_gpr(rD(ctx->opcode));
3918 if (unlikely(Rc(ctx->opcode) != 0))
3919 gen_set_Rc0(ctx);
3920 }
3921
3922 /* dozi */
3923 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
3924 {
3925 gen_op_load_gpr_T0(rA(ctx->opcode));
3926 gen_op_set_T1(SIMM(ctx->opcode));
3927 gen_op_POWER_doz();
3928 gen_op_store_T0_gpr(rD(ctx->opcode));
3929 }
3930
3931 /* As lscbx load from memory byte after byte, it's always endian safe.
3932 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
3933 */
3934 #define op_POWER_lscbx(start, ra, rb) \
3935 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
3936 #define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
3937 #define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
3938 #define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
3939 #define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
3940 #define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
3941 #define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
3942 #define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
3943 #define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
3944 #define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
3945 #define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
3946 #define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
3947 #define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
3948 static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
3949 GEN_MEM_FUNCS(POWER_lscbx),
3950 };
3951
3952 /* lscbx - lscbx. */
3953 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
3954 {
3955 int ra = rA(ctx->opcode);
3956 int rb = rB(ctx->opcode);
3957
3958 gen_addr_reg_index(ctx);
3959 if (ra == 0) {
3960 ra = rb;
3961 }
3962 /* NIP cannot be restored if the memory exception comes from an helper */
3963 gen_update_nip(ctx, ctx->nip - 4);
3964 gen_op_load_xer_bc();
3965 gen_op_load_xer_cmp();
3966 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3967 gen_op_store_xer_bc();
3968 if (unlikely(Rc(ctx->opcode) != 0))
3969 gen_set_Rc0(ctx);
3970 }
3971
3972 /* maskg - maskg. */
3973 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
3974 {
3975 gen_op_load_gpr_T0(rS(ctx->opcode));
3976 gen_op_load_gpr_T1(rB(ctx->opcode));
3977 gen_op_POWER_maskg();
3978 gen_op_store_T0_gpr(rA(ctx->opcode));
3979 if (unlikely(Rc(ctx->opcode) != 0))
3980 gen_set_Rc0(ctx);
3981 }
3982
3983 /* maskir - maskir. */
3984 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
3985 {
3986 gen_op_load_gpr_T0(rA(ctx->opcode));
3987 gen_op_load_gpr_T1(rS(ctx->opcode));
3988 gen_op_load_gpr_T2(rB(ctx->opcode));
3989 gen_op_POWER_maskir();
3990 gen_op_store_T0_gpr(rA(ctx->opcode));
3991 if (unlikely(Rc(ctx->opcode) != 0))
3992 gen_set_Rc0(ctx);
3993 }
3994
3995 /* mul - mul. */
3996 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
3997 {
3998 gen_op_load_gpr_T0(rA(ctx->opcode));
3999 gen_op_load_gpr_T1(rB(ctx->opcode));
4000 gen_op_POWER_mul();
4001 gen_op_store_T0_gpr(rD(ctx->opcode));
4002 if (unlikely(Rc(ctx->opcode) != 0))
4003 gen_set_Rc0(ctx);
4004 }
4005
4006 /* mulo - mulo. */
4007 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4008 {
4009 gen_op_load_gpr_T0(rA(ctx->opcode));
4010 gen_op_load_gpr_T1(rB(ctx->opcode));
4011 gen_op_POWER_mulo();
4012 gen_op_store_T0_gpr(rD(ctx->opcode));
4013 if (unlikely(Rc(ctx->opcode) != 0))
4014 gen_set_Rc0(ctx);
4015 }
4016
4017 /* nabs - nabs. */
4018 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4019 {
4020 gen_op_load_gpr_T0(rA(ctx->opcode));
4021 gen_op_POWER_nabs();
4022 gen_op_store_T0_gpr(rD(ctx->opcode));
4023 if (unlikely(Rc(ctx->opcode) != 0))
4024 gen_set_Rc0(ctx);
4025 }
4026
4027 /* nabso - nabso. */
4028 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4029 {
4030 gen_op_load_gpr_T0(rA(ctx->opcode));
4031 gen_op_POWER_nabso();
4032 gen_op_store_T0_gpr(rD(ctx->opcode));
4033 if (unlikely(Rc(ctx->opcode) != 0))
4034 gen_set_Rc0(ctx);
4035 }
4036
4037 /* rlmi - rlmi. */
4038 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4039 {
4040 uint32_t mb, me;
4041
4042 mb = MB(ctx->opcode);
4043 me = ME(ctx->opcode);
4044 gen_op_load_gpr_T0(rS(ctx->opcode));
4045 gen_op_load_gpr_T1(rA(ctx->opcode));
4046 gen_op_load_gpr_T2(rB(ctx->opcode));
4047 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4048 gen_op_store_T0_gpr(rA(ctx->opcode));
4049 if (unlikely(Rc(ctx->opcode) != 0))
4050 gen_set_Rc0(ctx);
4051 }
4052
4053 /* rrib - rrib. */
4054 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4055 {
4056 gen_op_load_gpr_T0(rS(ctx->opcode));
4057 gen_op_load_gpr_T1(rA(ctx->opcode));
4058 gen_op_load_gpr_T2(rB(ctx->opcode));
4059 gen_op_POWER_rrib();
4060 gen_op_store_T0_gpr(rA(ctx->opcode));
4061 if (unlikely(Rc(ctx->opcode) != 0))
4062 gen_set_Rc0(ctx);
4063 }
4064
4065 /* sle - sle. */
4066 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4067 {
4068 gen_op_load_gpr_T0(rS(ctx->opcode));
4069 gen_op_load_gpr_T1(rB(ctx->opcode));
4070 gen_op_POWER_sle();
4071 gen_op_store_T0_gpr(rA(ctx->opcode));
4072 if (unlikely(Rc(ctx->opcode) != 0))
4073 gen_set_Rc0(ctx);
4074 }
4075
4076 /* sleq - sleq. */
4077 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4078 {
4079 gen_op_load_gpr_T0(rS(ctx->opcode));
4080 gen_op_load_gpr_T1(rB(ctx->opcode));
4081 gen_op_POWER_sleq();
4082 gen_op_store_T0_gpr(rA(ctx->opcode));
4083 if (unlikely(Rc(ctx->opcode) != 0))
4084 gen_set_Rc0(ctx);
4085 }
4086
4087 /* sliq - sliq. */
4088 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4089 {
4090 gen_op_load_gpr_T0(rS(ctx->opcode));
4091 gen_op_set_T1(SH(ctx->opcode));
4092 gen_op_POWER_sle();
4093 gen_op_store_T0_gpr(rA(ctx->opcode));
4094 if (unlikely(Rc(ctx->opcode) != 0))
4095 gen_set_Rc0(ctx);
4096 }
4097
4098 /* slliq - slliq. */
4099 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4100 {
4101 gen_op_load_gpr_T0(rS(ctx->opcode));
4102 gen_op_set_T1(SH(ctx->opcode));
4103 gen_op_POWER_sleq();
4104 gen_op_store_T0_gpr(rA(ctx->opcode));
4105 if (unlikely(Rc(ctx->opcode) != 0))
4106 gen_set_Rc0(ctx);
4107 }
4108
4109 /* sllq - sllq. */
4110 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4111 {
4112 gen_op_load_gpr_T0(rS(ctx->opcode));
4113 gen_op_load_gpr_T1(rB(ctx->opcode));
4114 gen_op_POWER_sllq();
4115 gen_op_store_T0_gpr(rA(ctx->opcode));
4116 if (unlikely(Rc(ctx->opcode) != 0))
4117 gen_set_Rc0(ctx);
4118 }
4119
4120 /* slq - slq. */
4121 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4122 {
4123 gen_op_load_gpr_T0(rS(ctx->opcode));
4124 gen_op_load_gpr_T1(rB(ctx->opcode));
4125 gen_op_POWER_slq();
4126 gen_op_store_T0_gpr(rA(ctx->opcode));
4127 if (unlikely(Rc(ctx->opcode) != 0))
4128 gen_set_Rc0(ctx);
4129 }
4130
4131 /* sraiq - sraiq. */
4132 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4133 {
4134 gen_op_load_gpr_T0(rS(ctx->opcode));
4135 gen_op_set_T1(SH(ctx->opcode));
4136 gen_op_POWER_sraq();
4137 gen_op_store_T0_gpr(rA(ctx->opcode));
4138 if (unlikely(Rc(ctx->opcode) != 0))
4139 gen_set_Rc0(ctx);
4140 }
4141
4142 /* sraq - sraq. */
4143 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4144 {
4145 gen_op_load_gpr_T0(rS(ctx->opcode));
4146 gen_op_load_gpr_T1(rB(ctx->opcode));
4147 gen_op_POWER_sraq();
4148 gen_op_store_T0_gpr(rA(ctx->opcode));
4149 if (unlikely(Rc(ctx->opcode) != 0))
4150 gen_set_Rc0(ctx);
4151 }
4152
4153 /* sre - sre. */
4154 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4155 {
4156 gen_op_load_gpr_T0(rS(ctx->opcode));
4157 gen_op_load_gpr_T1(rB(ctx->opcode));
4158 gen_op_POWER_sre();
4159 gen_op_store_T0_gpr(rA(ctx->opcode));
4160 if (unlikely(Rc(ctx->opcode) != 0))
4161 gen_set_Rc0(ctx);
4162 }
4163
4164 /* srea - srea. */
4165 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4166 {
4167 gen_op_load_gpr_T0(rS(ctx->opcode));
4168 gen_op_load_gpr_T1(rB(ctx->opcode));
4169 gen_op_POWER_srea();
4170 gen_op_store_T0_gpr(rA(ctx->opcode));
4171 if (unlikely(Rc(ctx->opcode) != 0))
4172 gen_set_Rc0(ctx);
4173 }
4174
4175 /* sreq */
4176 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4177 {
4178 gen_op_load_gpr_T0(rS(ctx->opcode));
4179 gen_op_load_gpr_T1(rB(ctx->opcode));
4180 gen_op_POWER_sreq();
4181 gen_op_store_T0_gpr(rA(ctx->opcode));
4182 if (unlikely(Rc(ctx->opcode) != 0))
4183 gen_set_Rc0(ctx);
4184 }
4185
4186 /* sriq */
4187 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4188 {
4189 gen_op_load_gpr_T0(rS(ctx->opcode));
4190 gen_op_set_T1(SH(ctx->opcode));
4191 gen_op_POWER_srq();
4192 gen_op_store_T0_gpr(rA(ctx->opcode));
4193 if (unlikely(Rc(ctx->opcode) != 0))
4194 gen_set_Rc0(ctx);
4195 }
4196
4197 /* srliq */
4198 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4199 {
4200 gen_op_load_gpr_T0(rS(ctx->opcode));
4201 gen_op_load_gpr_T1(rB(ctx->opcode));
4202 gen_op_set_T1(SH(ctx->opcode));
4203 gen_op_POWER_srlq();
4204 gen_op_store_T0_gpr(rA(ctx->opcode));
4205 if (unlikely(Rc(ctx->opcode) != 0))
4206 gen_set_Rc0(ctx);
4207 }
4208
4209 /* srlq */
4210 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4211 {
4212 gen_op_load_gpr_T0(rS(ctx->opcode));
4213 gen_op_load_gpr_T1(rB(ctx->opcode));
4214 gen_op_POWER_srlq();
4215 gen_op_store_T0_gpr(rA(ctx->opcode));
4216 if (unlikely(Rc(ctx->opcode) != 0))
4217 gen_set_Rc0(ctx);
4218 }
4219
4220 /* srq */
4221 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4222 {
4223 gen_op_load_gpr_T0(rS(ctx->opcode));
4224 gen_op_load_gpr_T1(rB(ctx->opcode));
4225 gen_op_POWER_srq();
4226 gen_op_store_T0_gpr(rA(ctx->opcode));
4227 if (unlikely(Rc(ctx->opcode) != 0))
4228 gen_set_Rc0(ctx);
4229 }
4230
4231 /* PowerPC 602 specific instructions */
4232 /* dsa */
4233 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4234 {
4235 /* XXX: TODO */
4236 GEN_EXCP_INVAL(ctx);
4237 }
4238
4239 /* esa */
4240 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4241 {
4242 /* XXX: TODO */
4243 GEN_EXCP_INVAL(ctx);
4244 }
4245
4246 /* mfrom */
4247 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4248 {
4249 #if defined(CONFIG_USER_ONLY)
4250 GEN_EXCP_PRIVOPC(ctx);
4251 #else
4252 if (unlikely(!ctx->supervisor)) {
4253 GEN_EXCP_PRIVOPC(ctx);
4254 return;
4255 }
4256 gen_op_load_gpr_T0(rA(ctx->opcode));
4257 gen_op_602_mfrom();
4258 gen_op_store_T0_gpr(rD(ctx->opcode));
4259 #endif
4260 }
4261
4262 /* 602 - 603 - G2 TLB management */
4263 /* tlbld */
4264 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4265 {
4266 #if defined(CONFIG_USER_ONLY)
4267 GEN_EXCP_PRIVOPC(ctx);
4268 #else
4269 if (unlikely(!ctx->supervisor)) {
4270 GEN_EXCP_PRIVOPC(ctx);
4271 return;
4272 }
4273 gen_op_load_gpr_T0(rB(ctx->opcode));
4274 gen_op_6xx_tlbld();
4275 #endif
4276 }
4277
4278 /* tlbli */
4279 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4280 {
4281 #if defined(CONFIG_USER_ONLY)
4282 GEN_EXCP_PRIVOPC(ctx);
4283 #else
4284 if (unlikely(!ctx->supervisor)) {
4285 GEN_EXCP_PRIVOPC(ctx);
4286 return;
4287 }
4288 gen_op_load_gpr_T0(rB(ctx->opcode));
4289 gen_op_6xx_tlbli();
4290 #endif
4291 }
4292
4293 /* 74xx TLB management */
4294 /* tlbld */
4295 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4296 {
4297 #if defined(CONFIG_USER_ONLY)
4298 GEN_EXCP_PRIVOPC(ctx);
4299 #else
4300 if (unlikely(!ctx->supervisor)) {
4301 GEN_EXCP_PRIVOPC(ctx);
4302 return;
4303 }
4304 gen_op_load_gpr_T0(rB(ctx->opcode));
4305 gen_op_74xx_tlbld();
4306 #endif
4307 }
4308
4309 /* tlbli */
4310 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4311 {
4312 #if defined(CONFIG_USER_ONLY)
4313 GEN_EXCP_PRIVOPC(ctx);
4314 #else
4315 if (unlikely(!ctx->supervisor)) {
4316 GEN_EXCP_PRIVOPC(ctx);
4317 return;
4318 }
4319 gen_op_load_gpr_T0(rB(ctx->opcode));
4320 gen_op_74xx_tlbli();
4321 #endif
4322 }
4323
4324 /* POWER instructions not in PowerPC 601 */
4325 /* clf */
4326 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4327 {
4328 /* Cache line flush: implemented as no-op */
4329 }
4330
4331 /* cli */
4332 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4333 {
4334 /* Cache line invalidate: privileged and treated as no-op */
4335 #if defined(CONFIG_USER_ONLY)
4336 GEN_EXCP_PRIVOPC(ctx);
4337 #else
4338 if (unlikely(!ctx->supervisor)) {
4339 GEN_EXCP_PRIVOPC(ctx);
4340 return;
4341 }
4342 #endif
4343 }
4344
4345 /* dclst */
4346 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4347 {
4348 /* Data cache line store: treated as no-op */
4349 }
4350
4351 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4352 {
4353 #if defined(CONFIG_USER_ONLY)
4354 GEN_EXCP_PRIVOPC(ctx);
4355 #else
4356 if (unlikely(!ctx->supervisor)) {
4357 GEN_EXCP_PRIVOPC(ctx);
4358 return;
4359 }
4360 int ra = rA(ctx->opcode);
4361 int rd = rD(ctx->opcode);
4362
4363 gen_addr_reg_index(ctx);
4364 gen_op_POWER_mfsri();
4365 gen_op_store_T0_gpr(rd);
4366 if (ra != 0 && ra != rd)
4367 gen_op_store_T1_gpr(ra);
4368 #endif
4369 }
4370
4371 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4372 {
4373 #if defined(CONFIG_USER_ONLY)
4374 GEN_EXCP_PRIVOPC(ctx);
4375 #else
4376 if (unlikely(!ctx->supervisor)) {
4377 GEN_EXCP_PRIVOPC(ctx);
4378 return;
4379 }
4380 gen_addr_reg_index(ctx);
4381 gen_op_POWER_rac();
4382 gen_op_store_T0_gpr(rD(ctx->opcode));
4383 #endif
4384 }
4385
4386 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4387 {
4388 #if defined(CONFIG_USER_ONLY)
4389 GEN_EXCP_PRIVOPC(ctx);
4390 #else
4391 if (unlikely(!ctx->supervisor)) {
4392 GEN_EXCP_PRIVOPC(ctx);
4393 return;
4394 }
4395 gen_op_POWER_rfsvc();
4396 GEN_SYNC(ctx);
4397 #endif
4398 }
4399
4400 /* svc is not implemented for now */
4401
4402 /* POWER2 specific instructions */
4403 /* Quad manipulation (load/store two floats at a time) */
4404 /* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
4405 #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4406 #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4407 #define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4408 #define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4409 #define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4410 #define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4411 #define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4412 #define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4413 #define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4414 #define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4415 #define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4416 #define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4417 #define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4418 #define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4419 #define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4420 #define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4421 #define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4422 #define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4423 static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4424 GEN_MEM_FUNCS(POWER2_lfq),
4425 };
4426 static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4427 GEN_MEM_FUNCS(POWER2_stfq),
4428 };
4429
4430 /* lfq */
4431 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4432 {
4433 /* NIP cannot be restored if the memory exception comes from an helper */
4434 gen_update_nip(ctx, ctx->nip - 4);
4435 gen_addr_imm_index(ctx, 0);
4436 op_POWER2_lfq();
4437 gen_op_store_FT0_fpr(rD(ctx->opcode));
4438 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4439 }
4440
4441 /* lfqu */
4442 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4443 {
4444 int ra = rA(ctx->opcode);
4445
4446 /* NIP cannot be restored if the memory exception comes from an helper */
4447 gen_update_nip(ctx, ctx->nip - 4);
4448 gen_addr_imm_index(ctx, 0);
4449 op_POWER2_lfq();
4450 gen_op_store_FT0_fpr(rD(ctx->opcode));
4451 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4452 if (ra != 0)
4453 gen_op_store_T0_gpr(ra);
4454 }
4455
4456 /* lfqux */
4457 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4458 {
4459 int ra = rA(ctx->opcode);
4460
4461 /* NIP cannot be restored if the memory exception comes from an helper */
4462 gen_update_nip(ctx, ctx->nip - 4);
4463 gen_addr_reg_index(ctx);
4464 op_POWER2_lfq();
4465 gen_op_store_FT0_fpr(rD(ctx->opcode));
4466 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4467 if (ra != 0)
4468 gen_op_store_T0_gpr(ra);
4469 }
4470
4471 /* lfqx */
4472 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4473 {
4474 /* NIP cannot be restored if the memory exception comes from an helper */
4475 gen_update_nip(ctx, ctx->nip - 4);
4476 gen_addr_reg_index(ctx);
4477 op_POWER2_lfq();
4478 gen_op_store_FT0_fpr(rD(ctx->opcode));
4479 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4480 }
4481
4482 /* stfq */
4483 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4484 {
4485 /* NIP cannot be restored if the memory exception comes from an helper */
4486 gen_update_nip(ctx, ctx->nip - 4);
4487 gen_addr_imm_index(ctx, 0);
4488 gen_op_load_fpr_FT0(rS(ctx->opcode));
4489 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4490 op_POWER2_stfq();
4491 }
4492
4493 /* stfqu */
4494 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4495 {
4496 int ra = rA(ctx->opcode);
4497
4498 /* NIP cannot be restored if the memory exception comes from an helper */
4499 gen_update_nip(ctx, ctx->nip - 4);
4500 gen_addr_imm_index(ctx, 0);
4501 gen_op_load_fpr_FT0(rS(ctx->opcode));
4502 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4503 op_POWER2_stfq();
4504 if (ra != 0)
4505 gen_op_store_T0_gpr(ra);
4506 }
4507
4508 /* stfqux */
4509 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4510 {
4511 int ra = rA(ctx->opcode);
4512
4513 /* NIP cannot be restored if the memory exception comes from an helper */
4514 gen_update_nip(ctx, ctx->nip - 4);
4515 gen_addr_reg_index(ctx);
4516 gen_op_load_fpr_FT0(rS(ctx->opcode));
4517 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4518 op_POWER2_stfq();
4519 if (ra != 0)
4520 gen_op_store_T0_gpr(ra);
4521 }
4522
4523 /* stfqx */
4524 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4525 {
4526 /* NIP cannot be restored if the memory exception comes from an helper */
4527 gen_update_nip(ctx, ctx->nip - 4);
4528 gen_addr_reg_index(ctx);
4529 gen_op_load_fpr_FT0(rS(ctx->opcode));
4530 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4531 op_POWER2_stfq();
4532 }
4533
4534 /* BookE specific instructions */
4535 /* XXX: not implemented on 440 ? */
4536 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
4537 {
4538 /* XXX: TODO */
4539 GEN_EXCP_INVAL(ctx);
4540 }
4541
4542 /* XXX: not implemented on 440 ? */
4543 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
4544 {
4545 #if defined(CONFIG_USER_ONLY)
4546 GEN_EXCP_PRIVOPC(ctx);
4547 #else
4548 if (unlikely(!ctx->supervisor)) {
4549 GEN_EXCP_PRIVOPC(ctx);
4550 return;
4551 }
4552 gen_addr_reg_index(ctx);
4553 /* Use the same micro-ops as for tlbie */
4554 #if defined(TARGET_PPC64)
4555 if (ctx->sf_mode)
4556 gen_op_tlbie_64();
4557 else
4558 #endif
4559 gen_op_tlbie();
4560 #endif
4561 }
4562
4563 /* All 405 MAC instructions are translated here */
4564 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4565 int opc2, int opc3,
4566 int ra, int rb, int rt, int Rc)
4567 {
4568 gen_op_load_gpr_T0(ra);
4569 gen_op_load_gpr_T1(rb);
4570 switch (opc3 & 0x0D) {
4571 case 0x05:
4572 /* macchw - macchw. - macchwo - macchwo. */
4573 /* macchws - macchws. - macchwso - macchwso. */
4574 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4575 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4576 /* mulchw - mulchw. */
4577 gen_op_405_mulchw();
4578 break;
4579 case 0x04:
4580 /* macchwu - macchwu. - macchwuo - macchwuo. */
4581 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4582 /* mulchwu - mulchwu. */
4583 gen_op_405_mulchwu();
4584 break;
4585 case 0x01:
4586 /* machhw - machhw. - machhwo - machhwo. */
4587 /* machhws - machhws. - machhwso - machhwso. */
4588 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4589 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4590 /* mulhhw - mulhhw. */
4591 gen_op_405_mulhhw();
4592 break;
4593 case 0x00:
4594 /* machhwu - machhwu. - machhwuo - machhwuo. */
4595 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4596 /* mulhhwu - mulhhwu. */
4597 gen_op_405_mulhhwu();
4598 break;
4599 case 0x0D:
4600 /* maclhw - maclhw. - maclhwo - maclhwo. */
4601 /* maclhws - maclhws. - maclhwso - maclhwso. */
4602 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4603 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4604 /* mullhw - mullhw. */
4605 gen_op_405_mullhw();
4606 break;
4607 case 0x0C:
4608 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4609 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4610 /* mullhwu - mullhwu. */
4611 gen_op_405_mullhwu();
4612 break;
4613 }
4614 if (opc2 & 0x02) {
4615 /* nmultiply-and-accumulate (0x0E) */
4616 gen_op_neg();
4617 }
4618 if (opc2 & 0x04) {
4619 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4620 gen_op_load_gpr_T2(rt);
4621 gen_op_move_T1_T0();
4622 gen_op_405_add_T0_T2();
4623 }
4624 if (opc3 & 0x10) {
4625 /* Check overflow */
4626 if (opc3 & 0x01)
4627 gen_op_check_addo();
4628 else
4629 gen_op_405_check_ovu();
4630 }
4631 if (opc3 & 0x02) {
4632 /* Saturate */
4633 if (opc3 & 0x01)
4634 gen_op_405_check_sat();
4635 else
4636 gen_op_405_check_satu();
4637 }
4638 gen_op_store_T0_gpr(rt);
4639 if (unlikely(Rc) != 0) {
4640 /* Update Rc0 */
4641 gen_set_Rc0(ctx);
4642 }
4643 }
4644
4645 #define GEN_MAC_HANDLER(name, opc2, opc3) \
4646 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
4647 { \
4648 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4649 rD(ctx->opcode), Rc(ctx->opcode)); \
4650 }
4651
4652 /* macchw - macchw. */
4653 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
4654 /* macchwo - macchwo. */
4655 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
4656 /* macchws - macchws. */
4657 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
4658 /* macchwso - macchwso. */
4659 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
4660 /* macchwsu - macchwsu. */
4661 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
4662 /* macchwsuo - macchwsuo. */
4663 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
4664 /* macchwu - macchwu. */
4665 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
4666 /* macchwuo - macchwuo. */
4667 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
4668 /* machhw - machhw. */
4669 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
4670 /* machhwo - machhwo. */
4671 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
4672 /* machhws - machhws. */
4673 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
4674 /* machhwso - machhwso. */
4675 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
4676 /* machhwsu - machhwsu. */
4677 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
4678 /* machhwsuo - machhwsuo. */
4679 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
4680 /* machhwu - machhwu. */
4681 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
4682 /* machhwuo - machhwuo. */
4683 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
4684 /* maclhw - maclhw. */
4685 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
4686 /* maclhwo - maclhwo. */
4687 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
4688 /* maclhws - maclhws. */
4689 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
4690 /* maclhwso - maclhwso. */
4691 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
4692 /* maclhwu - maclhwu. */
4693 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
4694 /* maclhwuo - maclhwuo. */
4695 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
4696 /* maclhwsu - maclhwsu. */
4697 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
4698 /* maclhwsuo - maclhwsuo. */
4699 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
4700 /* nmacchw - nmacchw. */
4701 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
4702 /* nmacchwo - nmacchwo. */
4703 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
4704 /* nmacchws - nmacchws. */
4705 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
4706 /* nmacchwso - nmacchwso. */
4707 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
4708 /* nmachhw - nmachhw. */
4709 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
4710 /* nmachhwo - nmachhwo. */
4711 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
4712 /* nmachhws - nmachhws. */
4713 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
4714 /* nmachhwso - nmachhwso. */
4715 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
4716 /* nmaclhw - nmaclhw. */
4717 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
4718 /* nmaclhwo - nmaclhwo. */
4719 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
4720 /* nmaclhws - nmaclhws. */
4721 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
4722 /* nmaclhwso - nmaclhwso. */
4723 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
4724
4725 /* mulchw - mulchw. */
4726 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
4727 /* mulchwu - mulchwu. */
4728 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
4729 /* mulhhw - mulhhw. */
4730 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
4731 /* mulhhwu - mulhhwu. */
4732 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
4733 /* mullhw - mullhw. */
4734 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
4735 /* mullhwu - mullhwu. */
4736 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
4737
4738 /* mfdcr */
4739 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
4740 {
4741 #if defined(CONFIG_USER_ONLY)
4742 GEN_EXCP_PRIVREG(ctx);
4743 #else
4744 uint32_t dcrn = SPR(ctx->opcode);
4745
4746 if (unlikely(!ctx->supervisor)) {
4747 GEN_EXCP_PRIVREG(ctx);
4748 return;
4749 }
4750 gen_op_set_T0(dcrn);
4751 gen_op_load_dcr();
4752 gen_op_store_T0_gpr(rD(ctx->opcode));
4753 #endif
4754 }
4755
4756 /* mtdcr */
4757 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
4758 {
4759 #if defined(CONFIG_USER_ONLY)
4760 GEN_EXCP_PRIVREG(ctx);
4761 #else
4762 uint32_t dcrn = SPR(ctx->opcode);
4763
4764 if (unlikely(!ctx->supervisor)) {
4765 GEN_EXCP_PRIVREG(ctx);
4766 return;
4767 }
4768 gen_op_set_T0(dcrn);
4769 gen_op_load_gpr_T1(rS(ctx->opcode));
4770 gen_op_store_dcr();
4771 #endif
4772 }
4773
4774 /* mfdcrx */
4775 /* XXX: not implemented on 440 ? */
4776 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
4777 {
4778 #if defined(CONFIG_USER_ONLY)
4779 GEN_EXCP_PRIVREG(ctx);
4780 #else
4781 if (unlikely(!ctx->supervisor)) {
4782 GEN_EXCP_PRIVREG(ctx);
4783 return;
4784 }
4785 gen_op_load_gpr_T0(rA(ctx->opcode));
4786 gen_op_load_dcr();
4787 gen_op_store_T0_gpr(rD(ctx->opcode));
4788 /* Note: Rc update flag set leads to undefined state of Rc0 */
4789 #endif
4790 }
4791
4792 /* mtdcrx */
4793 /* XXX: not implemented on 440 ? */
4794 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
4795 {
4796 #if defined(CONFIG_USER_ONLY)
4797 GEN_EXCP_PRIVREG(ctx);
4798 #else
4799 if (unlikely(!ctx->supervisor)) {
4800 GEN_EXCP_PRIVREG(ctx);
4801 return;
4802 }
4803 gen_op_load_gpr_T0(rA(ctx->opcode));
4804 gen_op_load_gpr_T1(rS(ctx->opcode));
4805 gen_op_store_dcr();
4806 /* Note: Rc update flag set leads to undefined state of Rc0 */
4807 #endif
4808 }
4809
4810 /* mfdcrux (PPC 460) : user-mode access to DCR */
4811 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
4812 {
4813 gen_op_load_gpr_T0(rA(ctx->opcode));
4814 gen_op_load_dcr();
4815 gen_op_store_T0_gpr(rD(ctx->opcode));
4816 /* Note: Rc update flag set leads to undefined state of Rc0 */
4817 }
4818
4819 /* mtdcrux (PPC 460) : user-mode access to DCR */
4820 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
4821 {
4822 gen_op_load_gpr_T0(rA(ctx->opcode));
4823 gen_op_load_gpr_T1(rS(ctx->opcode));
4824 gen_op_store_dcr();
4825 /* Note: Rc update flag set leads to undefined state of Rc0 */
4826 }
4827
4828 /* dccci */
4829 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
4830 {
4831 #if defined(CONFIG_USER_ONLY)
4832 GEN_EXCP_PRIVOPC(ctx);
4833 #else
4834 if (unlikely(!ctx->supervisor)) {
4835 GEN_EXCP_PRIVOPC(ctx);
4836 return;
4837 }
4838 /* interpreted as no-op */
4839 #endif
4840 }
4841
4842 /* dcread */
4843 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
4844 {
4845 #if defined(CONFIG_USER_ONLY)
4846 GEN_EXCP_PRIVOPC(ctx);
4847 #else
4848 if (unlikely(!ctx->supervisor)) {
4849 GEN_EXCP_PRIVOPC(ctx);
4850 return;
4851 }
4852 gen_addr_reg_index(ctx);
4853 op_ldst(lwz);
4854 gen_op_store_T0_gpr(rD(ctx->opcode));
4855 #endif
4856 }
4857
4858 /* icbt */
4859 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
4860 {
4861 /* interpreted as no-op */
4862 /* XXX: specification say this is treated as a load by the MMU
4863 * but does not generate any exception
4864 */
4865 }
4866
4867 /* iccci */
4868 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
4869 {
4870 #if defined(CONFIG_USER_ONLY)
4871 GEN_EXCP_PRIVOPC(ctx);
4872 #else
4873 if (unlikely(!ctx->supervisor)) {
4874 GEN_EXCP_PRIVOPC(ctx);
4875 return;
4876 }
4877 /* interpreted as no-op */
4878 #endif
4879 }
4880
4881 /* icread */
4882 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
4883 {
4884 #if defined(CONFIG_USER_ONLY)
4885 GEN_EXCP_PRIVOPC(ctx);
4886 #else
4887 if (unlikely(!ctx->supervisor)) {
4888 GEN_EXCP_PRIVOPC(ctx);
4889 return;
4890 }
4891 /* interpreted as no-op */
4892 #endif
4893 }
4894
4895 /* rfci (supervisor only) */
4896 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
4897 {
4898 #if defined(CONFIG_USER_ONLY)
4899 GEN_EXCP_PRIVOPC(ctx);
4900 #else
4901 if (unlikely(!ctx->supervisor)) {
4902 GEN_EXCP_PRIVOPC(ctx);
4903 return;
4904 }
4905 /* Restore CPU state */
4906 gen_op_40x_rfci();
4907 GEN_SYNC(ctx);
4908 #endif
4909 }
4910
4911 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
4912 {
4913 #if defined(CONFIG_USER_ONLY)
4914 GEN_EXCP_PRIVOPC(ctx);
4915 #else
4916 if (unlikely(!ctx->supervisor)) {
4917 GEN_EXCP_PRIVOPC(ctx);
4918 return;
4919 }
4920 /* Restore CPU state */
4921 gen_op_rfci();
4922 GEN_SYNC(ctx);
4923 #endif
4924 }
4925
4926 /* BookE specific */
4927 /* XXX: not implemented on 440 ? */
4928 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
4929 {
4930 #if defined(CONFIG_USER_ONLY)
4931 GEN_EXCP_PRIVOPC(ctx);
4932 #else
4933 if (unlikely(!ctx->supervisor)) {
4934 GEN_EXCP_PRIVOPC(ctx);
4935 return;
4936 }
4937 /* Restore CPU state */
4938 gen_op_rfdi();
4939 GEN_SYNC(ctx);
4940 #endif
4941 }
4942
4943 /* XXX: not implemented on 440 ? */
4944 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
4945 {
4946 #if defined(CONFIG_USER_ONLY)
4947 GEN_EXCP_PRIVOPC(ctx);
4948 #else
4949 if (unlikely(!ctx->supervisor)) {
4950 GEN_EXCP_PRIVOPC(ctx);
4951 return;
4952 }
4953 /* Restore CPU state */
4954 gen_op_rfmci();
4955 GEN_SYNC(ctx);
4956 #endif
4957 }
4958
4959 /* TLB management - PowerPC 405 implementation */
4960 /* tlbre */
4961 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
4962 {
4963 #if defined(CONFIG_USER_ONLY)
4964 GEN_EXCP_PRIVOPC(ctx);
4965 #else
4966 if (unlikely(!ctx->supervisor)) {
4967 GEN_EXCP_PRIVOPC(ctx);
4968 return;
4969 }
4970 switch (rB(ctx->opcode)) {
4971 case 0:
4972 gen_op_load_gpr_T0(rA(ctx->opcode));
4973 gen_op_4xx_tlbre_hi();
4974 gen_op_store_T0_gpr(rD(ctx->opcode));
4975 break;
4976 case 1:
4977 gen_op_load_gpr_T0(rA(ctx->opcode));
4978 gen_op_4xx_tlbre_lo();
4979 gen_op_store_T0_gpr(rD(ctx->opcode));
4980 break;
4981 default:
4982 GEN_EXCP_INVAL(ctx);
4983 break;
4984 }
4985 #endif
4986 }
4987
4988 /* tlbsx - tlbsx. */
4989 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
4990 {
4991 #if defined(CONFIG_USER_ONLY)
4992 GEN_EXCP_PRIVOPC(ctx);
4993 #else
4994 if (unlikely(!ctx->supervisor)) {
4995 GEN_EXCP_PRIVOPC(ctx);
4996 return;
4997 }
4998 gen_addr_reg_index(ctx);
4999 gen_op_4xx_tlbsx();
5000 if (Rc(ctx->opcode))
5001 gen_op_4xx_tlbsx_check();
5002 gen_op_store_T0_gpr(rD(ctx->opcode));
5003 #endif
5004 }
5005
5006 /* tlbwe */
5007 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5008 {
5009 #if defined(CONFIG_USER_ONLY)
5010 GEN_EXCP_PRIVOPC(ctx);
5011 #else
5012 if (unlikely(!ctx->supervisor)) {
5013 GEN_EXCP_PRIVOPC(ctx);
5014 return;
5015 }
5016 switch (rB(ctx->opcode)) {
5017 case 0:
5018 gen_op_load_gpr_T0(rA(ctx->opcode));
5019 gen_op_load_gpr_T1(rS(ctx->opcode));
5020 gen_op_4xx_tlbwe_hi();
5021 break;
5022 case 1:
5023 gen_op_load_gpr_T0(rA(ctx->opcode));
5024 gen_op_load_gpr_T1(rS(ctx->opcode));
5025 gen_op_4xx_tlbwe_lo();
5026 break;
5027 default:
5028 GEN_EXCP_INVAL(ctx);
5029 break;
5030 }
5031 #endif
5032 }
5033
5034 /* TLB management - PowerPC 440 implementation */
5035 /* tlbre */
5036 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5037 {
5038 #if defined(CONFIG_USER_ONLY)
5039 GEN_EXCP_PRIVOPC(ctx);
5040 #else
5041 if (unlikely(!ctx->supervisor)) {
5042 GEN_EXCP_PRIVOPC(ctx);
5043 return;
5044 }
5045 switch (rB(ctx->opcode)) {
5046 case 0:
5047 case 1:
5048 case 2:
5049 gen_op_load_gpr_T0(rA(ctx->opcode));
5050 gen_op_440_tlbre(rB(ctx->opcode));
5051 gen_op_store_T0_gpr(rD(ctx->opcode));
5052 break;
5053 default:
5054 GEN_EXCP_INVAL(ctx);
5055 break;
5056 }
5057 #endif
5058 }
5059
5060 /* tlbsx - tlbsx. */
5061 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5062 {
5063 #if defined(CONFIG_USER_ONLY)
5064 GEN_EXCP_PRIVOPC(ctx);
5065 #else
5066 if (unlikely(!ctx->supervisor)) {
5067 GEN_EXCP_PRIVOPC(ctx);
5068 return;
5069 }
5070 gen_addr_reg_index(ctx);
5071 gen_op_440_tlbsx();
5072 if (Rc(ctx->opcode))
5073 gen_op_4xx_tlbsx_check();
5074 gen_op_store_T0_gpr(rD(ctx->opcode));
5075 #endif
5076 }
5077
5078 /* tlbwe */
5079 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5080 {
5081 #if defined(CONFIG_USER_ONLY)
5082 GEN_EXCP_PRIVOPC(ctx);
5083 #else
5084 if (unlikely(!ctx->supervisor)) {
5085 GEN_EXCP_PRIVOPC(ctx);
5086 return;
5087 }
5088 switch (rB(ctx->opcode)) {
5089 case 0:
5090 case 1:
5091 case 2:
5092 gen_op_load_gpr_T0(rA(ctx->opcode));
5093 gen_op_load_gpr_T1(rS(ctx->opcode));
5094 gen_op_440_tlbwe(rB(ctx->opcode));
5095 break;
5096 default:
5097 GEN_EXCP_INVAL(ctx);
5098 break;
5099 }
5100 #endif
5101 }
5102
5103 /* wrtee */
5104 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
5105 {
5106 #if defined(CONFIG_USER_ONLY)
5107 GEN_EXCP_PRIVOPC(ctx);
5108 #else
5109 if (unlikely(!ctx->supervisor)) {
5110 GEN_EXCP_PRIVOPC(ctx);
5111 return;
5112 }
5113 gen_op_load_gpr_T0(rD(ctx->opcode));
5114 gen_op_wrte();
5115 /* Stop translation to have a chance to raise an exception
5116 * if we just set msr_ee to 1
5117 */
5118 GEN_STOP(ctx);
5119 #endif
5120 }
5121
5122 /* wrteei */
5123 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
5124 {
5125 #if defined(CONFIG_USER_ONLY)
5126 GEN_EXCP_PRIVOPC(ctx);
5127 #else
5128 if (unlikely(!ctx->supervisor)) {
5129 GEN_EXCP_PRIVOPC(ctx);
5130 return;
5131 }
5132 gen_op_set_T0(ctx->opcode & 0x00010000);
5133 gen_op_wrte();
5134 /* Stop translation to have a chance to raise an exception
5135 * if we just set msr_ee to 1
5136 */
5137 GEN_STOP(ctx);
5138 #endif
5139 }
5140
5141 /* PowerPC 440 specific instructions */
5142 /* dlmzb */
5143 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5144 {
5145 gen_op_load_gpr_T0(rS(ctx->opcode));
5146 gen_op_load_gpr_T1(rB(ctx->opcode));
5147 gen_op_440_dlmzb();
5148 gen_op_store_T0_gpr(rA(ctx->opcode));
5149 gen_op_store_xer_bc();
5150 if (Rc(ctx->opcode)) {
5151 gen_op_440_dlmzb_update_Rc();
5152 gen_op_store_T0_crf(0);
5153 }
5154 }
5155
5156 /* mbar replaces eieio on 440 */
5157 GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5158 {
5159 /* interpreted as no-op */
5160 }
5161
5162 /* msync replaces sync on 440 */
5163 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
5164 {
5165 /* interpreted as no-op */
5166 }
5167
5168 /* icbt */
5169 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
5170 {
5171 /* interpreted as no-op */
5172 /* XXX: specification say this is treated as a load by the MMU
5173 * but does not generate any exception
5174 */
5175 }
5176
5177 /*** Altivec vector extension ***/
5178 /* Altivec registers moves */
5179 GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr);
5180 GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr);
5181 GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr);
5182
5183 GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr);
5184 GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr);
5185 #if 0 // unused
5186 GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr);
5187 #endif
5188
5189 #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5190 #define OP_VR_LD_TABLE(name) \
5191 static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5192 GEN_MEM_FUNCS(vr_l##name), \
5193 };
5194 #define OP_VR_ST_TABLE(name) \
5195 static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5196 GEN_MEM_FUNCS(vr_st##name), \
5197 };
5198
5199 #define GEN_VR_LDX(name, opc2, opc3) \
5200 GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5201 { \
5202 if (unlikely(!ctx->altivec_enabled)) { \
5203 GEN_EXCP_NO_VR(ctx); \
5204 return; \
5205 } \
5206 gen_addr_reg_index(ctx); \
5207 op_vr_ldst(vr_l##name); \
5208 gen_op_store_A0_avr(rD(ctx->opcode)); \
5209 }
5210
5211 #define GEN_VR_STX(name, opc2, opc3) \
5212 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5213 { \
5214 if (unlikely(!ctx->altivec_enabled)) { \
5215 GEN_EXCP_NO_VR(ctx); \
5216 return; \
5217 } \
5218 gen_addr_reg_index(ctx); \
5219 gen_op_load_avr_A0(rS(ctx->opcode)); \
5220 op_vr_ldst(vr_st##name); \
5221 }
5222
5223 OP_VR_LD_TABLE(vx);
5224 GEN_VR_LDX(vx, 0x07, 0x03);
5225 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5226 #define gen_op_vr_lvxl gen_op_vr_lvx
5227 GEN_VR_LDX(vxl, 0x07, 0x0B);
5228
5229 OP_VR_ST_TABLE(vx);
5230 GEN_VR_STX(vx, 0x07, 0x07);
5231 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5232 #define gen_op_vr_stvxl gen_op_vr_stvx
5233 GEN_VR_STX(vxl, 0x07, 0x0F);
5234
5235 /*** SPE extension ***/
5236 /* Register moves */
5237 #if !defined(TARGET_PPC64)
5238
5239 GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5240 GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
5241 #if 0 // unused
5242 GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
5243 #endif
5244
5245 GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
5246 GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5247 #if 0 // unused
5248 GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5249 #endif
5250
5251 #else /* !defined(TARGET_PPC64) */
5252
5253 /* No specific load/store functions: GPRs are already 64 bits */
5254 #define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
5255 #define gen_op_load_gpr64_T1 gen_op_load_gpr_T1
5256 #if 0 // unused
5257 #define gen_op_load_gpr64_T2 gen_op_load_gpr_T2
5258 #endif
5259
5260 #define gen_op_store_T0_gpr64 gen_op_store_T0_gpr
5261 #define gen_op_store_T1_gpr64 gen_op_store_T1_gpr
5262 #if 0 // unused
5263 #define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
5264 #endif
5265
5266 #endif /* !defined(TARGET_PPC64) */
5267
5268 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5269 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5270 { \
5271 if (Rc(ctx->opcode)) \
5272 gen_##name1(ctx); \
5273 else \
5274 gen_##name0(ctx); \
5275 }
5276
5277 /* Handler for undefined SPE opcodes */
5278 static always_inline void gen_speundef (DisasContext *ctx)
5279 {
5280 GEN_EXCP_INVAL(ctx);
5281 }
5282
5283 /* SPE load and stores */
5284 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
5285 {
5286 target_long simm = rB(ctx->opcode);
5287
5288 if (rA(ctx->opcode) == 0) {
5289 gen_set_T0(simm << sh);
5290 } else {
5291 gen_op_load_gpr_T0(rA(ctx->opcode));
5292 if (likely(simm != 0))
5293 gen_op_addi(simm << sh);
5294 }
5295 }
5296
5297 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5298 #define OP_SPE_LD_TABLE(name) \
5299 static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5300 GEN_MEM_FUNCS(spe_l##name), \
5301 };
5302 #define OP_SPE_ST_TABLE(name) \
5303 static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5304 GEN_MEM_FUNCS(spe_st##name), \
5305 };
5306
5307 #define GEN_SPE_LD(name, sh) \
5308 static always_inline void gen_evl##name (DisasContext *ctx) \
5309 { \
5310 if (unlikely(!ctx->spe_enabled)) { \
5311 GEN_EXCP_NO_AP(ctx); \
5312 return; \
5313 } \
5314 gen_addr_spe_imm_index(ctx, sh); \
5315 op_spe_ldst(spe_l##name); \
5316 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5317 }
5318
5319 #define GEN_SPE_LDX(name) \
5320 static always_inline void gen_evl##name##x (DisasContext *ctx) \
5321 { \
5322 if (unlikely(!ctx->spe_enabled)) { \
5323 GEN_EXCP_NO_AP(ctx); \
5324 return; \
5325 } \
5326 gen_addr_reg_index(ctx); \
5327 op_spe_ldst(spe_l##name); \
5328 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5329 }
5330
5331 #define GEN_SPEOP_LD(name, sh) \
5332 OP_SPE_LD_TABLE(name); \
5333 GEN_SPE_LD(name, sh); \
5334 GEN_SPE_LDX(name)
5335
5336 #define GEN_SPE_ST(name, sh) \
5337 static always_inline void gen_evst##name (DisasContext *ctx) \
5338 { \
5339 if (unlikely(!ctx->spe_enabled)) { \
5340 GEN_EXCP_NO_AP(ctx); \
5341 return; \
5342 } \
5343 gen_addr_spe_imm_index(ctx, sh); \
5344 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5345 op_spe_ldst(spe_st##name); \
5346 }
5347
5348 #define GEN_SPE_STX(name) \
5349 static always_inline void gen_evst##name##x (DisasContext *ctx) \
5350 { \
5351 if (unlikely(!ctx->spe_enabled)) { \
5352 GEN_EXCP_NO_AP(ctx); \
5353 return; \
5354 } \
5355 gen_addr_reg_index(ctx); \
5356 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5357 op_spe_ldst(spe_st##name); \
5358 }
5359
5360 #define GEN_SPEOP_ST(name, sh) \
5361 OP_SPE_ST_TABLE(name); \
5362 GEN_SPE_ST(name, sh); \
5363 GEN_SPE_STX(name)
5364
5365 #define GEN_SPEOP_LDST(name, sh) \
5366 GEN_SPEOP_LD(name, sh); \
5367 GEN_SPEOP_ST(name, sh)
5368
5369 /* SPE arithmetic and logic */
5370 #define GEN_SPEOP_ARITH2(name) \
5371 static always_inline void gen_##name (DisasContext *ctx) \
5372 { \
5373 if (unlikely(!ctx->spe_enabled)) { \
5374 GEN_EXCP_NO_AP(ctx); \
5375 return; \
5376 } \
5377 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5378 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5379 gen_op_##name(); \
5380 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5381 }
5382
5383 #define GEN_SPEOP_ARITH1(name) \
5384 static always_inline void gen_##name (DisasContext *ctx) \
5385 { \
5386 if (unlikely(!ctx->spe_enabled)) { \
5387 GEN_EXCP_NO_AP(ctx); \
5388 return; \
5389 } \
5390 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5391 gen_op_##name(); \
5392 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5393 }
5394
5395 #define GEN_SPEOP_COMP(name) \
5396 static always_inline void gen_##name (DisasContext *ctx) \
5397 { \
5398 if (unlikely(!ctx->spe_enabled)) { \
5399 GEN_EXCP_NO_AP(ctx); \
5400 return; \
5401 } \
5402 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5403 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5404 gen_op_##name(); \
5405 gen_op_store_T0_crf(crfD(ctx->opcode)); \
5406 }
5407
5408 /* Logical */
5409 GEN_SPEOP_ARITH2(evand);
5410 GEN_SPEOP_ARITH2(evandc);
5411 GEN_SPEOP_ARITH2(evxor);
5412 GEN_SPEOP_ARITH2(evor);
5413 GEN_SPEOP_ARITH2(evnor);
5414 GEN_SPEOP_ARITH2(eveqv);
5415 GEN_SPEOP_ARITH2(evorc);
5416 GEN_SPEOP_ARITH2(evnand);
5417 GEN_SPEOP_ARITH2(evsrwu);
5418 GEN_SPEOP_ARITH2(evsrws);
5419 GEN_SPEOP_ARITH2(evslw);
5420 GEN_SPEOP_ARITH2(evrlw);
5421 GEN_SPEOP_ARITH2(evmergehi);
5422 GEN_SPEOP_ARITH2(evmergelo);
5423 GEN_SPEOP_ARITH2(evmergehilo);
5424 GEN_SPEOP_ARITH2(evmergelohi);
5425
5426 /* Arithmetic */
5427 GEN_SPEOP_ARITH2(evaddw);
5428 GEN_SPEOP_ARITH2(evsubfw);
5429 GEN_SPEOP_ARITH1(evabs);
5430 GEN_SPEOP_ARITH1(evneg);
5431 GEN_SPEOP_ARITH1(evextsb);
5432 GEN_SPEOP_ARITH1(evextsh);
5433 GEN_SPEOP_ARITH1(evrndw);
5434 GEN_SPEOP_ARITH1(evcntlzw);
5435 GEN_SPEOP_ARITH1(evcntlsw);
5436 static always_inline void gen_brinc (DisasContext *ctx)
5437 {
5438 /* Note: brinc is usable even if SPE is disabled */
5439 gen_op_load_gpr_T0(rA(ctx->opcode));
5440 gen_op_load_gpr_T1(rB(ctx->opcode));
5441 gen_op_brinc();
5442 gen_op_store_T0_gpr(rD(ctx->opcode));
5443 }
5444
5445 #define GEN_SPEOP_ARITH_IMM2(name) \
5446 static always_inline void gen_##name##i (DisasContext *ctx) \
5447 { \
5448 if (unlikely(!ctx->spe_enabled)) { \
5449 GEN_EXCP_NO_AP(ctx); \
5450 return; \
5451 } \
5452 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5453 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5454 gen_op_##name(); \
5455 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5456 }
5457
5458 #define GEN_SPEOP_LOGIC_IMM2(name) \
5459 static always_inline void gen_##name##i (DisasContext *ctx) \
5460 { \
5461 if (unlikely(!ctx->spe_enabled)) { \
5462 GEN_EXCP_NO_AP(ctx); \
5463 return; \
5464 } \
5465 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5466 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5467 gen_op_##name(); \
5468 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5469 }
5470
5471 GEN_SPEOP_ARITH_IMM2(evaddw);
5472 #define gen_evaddiw gen_evaddwi
5473 GEN_SPEOP_ARITH_IMM2(evsubfw);
5474 #define gen_evsubifw gen_evsubfwi
5475 GEN_SPEOP_LOGIC_IMM2(evslw);
5476 GEN_SPEOP_LOGIC_IMM2(evsrwu);
5477 #define gen_evsrwis gen_evsrwsi
5478 GEN_SPEOP_LOGIC_IMM2(evsrws);
5479 #define gen_evsrwiu gen_evsrwui
5480 GEN_SPEOP_LOGIC_IMM2(evrlw);
5481
5482 static always_inline void gen_evsplati (DisasContext *ctx)
5483 {
5484 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5485
5486 gen_op_splatwi_T0_64(imm);
5487 gen_op_store_T0_gpr64(rD(ctx->opcode));
5488 }
5489
5490 static always_inline void gen_evsplatfi (DisasContext *ctx)
5491 {
5492 uint32_t imm = rA(ctx->opcode) << 27;
5493
5494 gen_op_splatwi_T0_64(imm);
5495 gen_op_store_T0_gpr64(rD(ctx->opcode));
5496 }
5497
5498 /* Comparison */
5499 GEN_SPEOP_COMP(evcmpgtu);
5500 GEN_SPEOP_COMP(evcmpgts);
5501 GEN_SPEOP_COMP(evcmpltu);
5502 GEN_SPEOP_COMP(evcmplts);
5503 GEN_SPEOP_COMP(evcmpeq);
5504
5505 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
5506 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
5507 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
5508 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
5509 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
5510 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
5511 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
5512 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
5513 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
5514 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
5515 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
5516 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
5517 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
5518 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
5519 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
5520 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
5521 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
5522 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
5523 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
5524 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
5525 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
5526 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
5527 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
5528 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
5529 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
5530
5531 static always_inline void gen_evsel (DisasContext *ctx)
5532 {
5533 if (unlikely(!ctx->spe_enabled)) {
5534 GEN_EXCP_NO_AP(ctx);
5535 return;
5536 }
5537 gen_op_load_crf_T0(ctx->opcode & 0x7);
5538 gen_op_load_gpr64_T0(rA(ctx->opcode));
5539 gen_op_load_gpr64_T1(rB(ctx->opcode));
5540 gen_op_evsel();
5541 gen_op_store_T0_gpr64(rD(ctx->opcode));
5542 }
5543
5544 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
5545 {
5546 gen_evsel(ctx);
5547 }
5548 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
5549 {
5550 gen_evsel(ctx);
5551 }
5552 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
5553 {
5554 gen_evsel(ctx);
5555 }
5556 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
5557 {
5558 gen_evsel(ctx);
5559 }
5560
5561 /* Load and stores */
5562 #if defined(TARGET_PPC64)
5563 /* In that case, we already have 64 bits load & stores
5564 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
5565 */
5566 #define gen_op_spe_ldd_raw gen_op_ld_raw
5567 #define gen_op_spe_ldd_user gen_op_ld_user
5568 #define gen_op_spe_ldd_kernel gen_op_ld_kernel
5569 #define gen_op_spe_ldd_hypv gen_op_ld_hypv
5570 #define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
5571 #define gen_op_spe_ldd_64_user gen_op_ld_64_user
5572 #define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
5573 #define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
5574 #define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
5575 #define gen_op_spe_ldd_le_user gen_op_ld_le_user
5576 #define gen_op_spe_ldd_le_kernel gen_op_ld_le_kernel
5577 #define gen_op_spe_ldd_le_hypv gen_op_ld_le_hypv
5578 #define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
5579 #define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
5580 #define gen_op_spe_ldd_le_64_kernel gen_op_ld_le_64_kernel
5581 #define gen_op_spe_ldd_le_64_hypv gen_op_ld_le_64_hypv
5582 #define gen_op_spe_stdd_raw gen_op_std_raw
5583 #define gen_op_spe_stdd_user gen_op_std_user
5584 #define gen_op_spe_stdd_kernel gen_op_std_kernel
5585 #define gen_op_spe_stdd_hypv gen_op_std_hypv
5586 #define gen_op_spe_stdd_64_raw gen_op_std_64_raw
5587 #define gen_op_spe_stdd_64_user gen_op_std_64_user
5588 #define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
5589 #define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
5590 #define gen_op_spe_stdd_le_raw gen_op_std_le_raw
5591 #define gen_op_spe_stdd_le_user gen_op_std_le_user
5592 #define gen_op_spe_stdd_le_kernel gen_op_std_le_kernel
5593 #define gen_op_spe_stdd_le_hypv gen_op_std_le_hypv
5594 #define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
5595 #define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
5596 #define gen_op_spe_stdd_le_64_kernel gen_op_std_le_64_kernel
5597 #define gen_op_spe_stdd_le_64_hypv gen_op_std_le_64_hypv
5598 #endif /* defined(TARGET_PPC64) */
5599 GEN_SPEOP_LDST(dd, 3);
5600 GEN_SPEOP_LDST(dw, 3);
5601 GEN_SPEOP_LDST(dh, 3);
5602 GEN_SPEOP_LDST(whe, 2);
5603 GEN_SPEOP_LD(whou, 2);
5604 GEN_SPEOP_LD(whos, 2);
5605 GEN_SPEOP_ST(who, 2);
5606
5607 #if defined(TARGET_PPC64)
5608 /* In that case, spe_stwwo is equivalent to stw */
5609 #define gen_op_spe_stwwo_raw gen_op_stw_raw
5610 #define gen_op_spe_stwwo_user gen_op_stw_user
5611 #define gen_op_spe_stwwo_kernel gen_op_stw_kernel
5612 #define gen_op_spe_stwwo_hypv gen_op_stw_hypv
5613 #define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
5614 #define gen_op_spe_stwwo_le_user gen_op_stw_le_user
5615 #define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
5616 #define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
5617 #define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
5618 #define gen_op_spe_stwwo_64_user gen_op_stw_64_user
5619 #define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
5620 #define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
5621 #define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
5622 #define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
5623 #define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
5624 #define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
5625 #endif
5626 #define _GEN_OP_SPE_STWWE(suffix) \
5627 static always_inline void gen_op_spe_stwwe_##suffix (void) \
5628 { \
5629 gen_op_srli32_T1_64(); \
5630 gen_op_spe_stwwo_##suffix(); \
5631 }
5632 #define _GEN_OP_SPE_STWWE_LE(suffix) \
5633 static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
5634 { \
5635 gen_op_srli32_T1_64(); \
5636 gen_op_spe_stwwo_le_##suffix(); \
5637 }
5638 #if defined(TARGET_PPC64)
5639 #define GEN_OP_SPE_STWWE(suffix) \
5640 _GEN_OP_SPE_STWWE(suffix); \
5641 _GEN_OP_SPE_STWWE_LE(suffix); \
5642 static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
5643 { \
5644 gen_op_srli32_T1_64(); \
5645 gen_op_spe_stwwo_64_##suffix(); \
5646 } \
5647 static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
5648 { \
5649 gen_op_srli32_T1_64(); \
5650 gen_op_spe_stwwo_le_64_##suffix(); \
5651 }
5652 #else
5653 #define GEN_OP_SPE_STWWE(suffix) \
5654 _GEN_OP_SPE_STWWE(suffix); \
5655 _GEN_OP_SPE_STWWE_LE(suffix)
5656 #endif
5657 #if defined(CONFIG_USER_ONLY)
5658 GEN_OP_SPE_STWWE(raw);
5659 #else /* defined(CONFIG_USER_ONLY) */
5660 GEN_OP_SPE_STWWE(user);
5661 GEN_OP_SPE_STWWE(kernel);
5662 GEN_OP_SPE_STWWE(hypv);
5663 #endif /* defined(CONFIG_USER_ONLY) */
5664 GEN_SPEOP_ST(wwe, 2);
5665 GEN_SPEOP_ST(wwo, 2);
5666
5667 #define GEN_SPE_LDSPLAT(name, op, suffix) \
5668 static always_inline void gen_op_spe_l##name##_##suffix (void) \
5669 { \
5670 gen_op_##op##_##suffix(); \
5671 gen_op_splatw_T1_64(); \
5672 }
5673
5674 #define GEN_OP_SPE_LHE(suffix) \
5675 static always_inline void gen_op_spe_lhe_##suffix (void) \
5676 { \
5677 gen_op_spe_lh_##suffix(); \
5678 gen_op_sli16_T1_64(); \
5679 }
5680
5681 #define GEN_OP_SPE_LHX(suffix) \
5682 static always_inline void gen_op_spe_lhx_##suffix (void) \
5683 { \
5684 gen_op_spe_lh_##suffix(); \
5685 gen_op_extsh_T1_64(); \
5686 }
5687
5688 #if defined(CONFIG_USER_ONLY)
5689 GEN_OP_SPE_LHE(raw);
5690 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
5691 GEN_OP_SPE_LHE(le_raw);
5692 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
5693 GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
5694 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
5695 GEN_OP_SPE_LHX(raw);
5696 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
5697 GEN_OP_SPE_LHX(le_raw);
5698 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
5699 #if defined(TARGET_PPC64)
5700 GEN_OP_SPE_LHE(64_raw);
5701 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
5702 GEN_OP_SPE_LHE(le_64_raw);
5703 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
5704 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
5705 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
5706 GEN_OP_SPE_LHX(64_raw);
5707 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
5708 GEN_OP_SPE_LHX(le_64_raw);
5709 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
5710 #endif
5711 #else
5712 GEN_OP_SPE_LHE(user);
5713 GEN_OP_SPE_LHE(kernel);
5714 GEN_OP_SPE_LHE(hypv);
5715 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
5716 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
5717 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
5718 GEN_OP_SPE_LHE(le_user);
5719 GEN_OP_SPE_LHE(le_kernel);
5720 GEN_OP_SPE_LHE(le_hypv);
5721 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
5722 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
5723 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
5724 GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
5725 GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
5726 GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
5727 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
5728 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
5729 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
5730 GEN_OP_SPE_LHX(user);
5731 GEN_OP_SPE_LHX(kernel);
5732 GEN_OP_SPE_LHX(hypv);
5733 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
5734 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
5735 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
5736 GEN_OP_SPE_LHX(le_user);
5737 GEN_OP_SPE_LHX(le_kernel);
5738 GEN_OP_SPE_LHX(le_hypv);
5739 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
5740 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
5741 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
5742 #if defined(TARGET_PPC64)
5743 GEN_OP_SPE_LHE(64_user);
5744 GEN_OP_SPE_LHE(64_kernel);
5745 GEN_OP_SPE_LHE(64_hypv);
5746 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
5747 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
5748 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
5749 GEN_OP_SPE_LHE(le_64_user);
5750 GEN_OP_SPE_LHE(le_64_kernel);
5751 GEN_OP_SPE_LHE(le_64_hypv);
5752 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
5753 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
5754 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
5755 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
5756 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
5757 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
5758 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
5759 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
5760 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
5761 GEN_OP_SPE_LHX(64_user);
5762 GEN_OP_SPE_LHX(64_kernel);
5763 GEN_OP_SPE_LHX(64_hypv);
5764 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
5765 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
5766 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
5767 GEN_OP_SPE_LHX(le_64_user);
5768 GEN_OP_SPE_LHX(le_64_kernel);
5769 GEN_OP_SPE_LHX(le_64_hypv);
5770 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
5771 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
5772 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
5773 #endif
5774 #endif
5775 GEN_SPEOP_LD(hhesplat, 1);
5776 GEN_SPEOP_LD(hhousplat, 1);
5777 GEN_SPEOP_LD(hhossplat, 1);
5778 GEN_SPEOP_LD(wwsplat, 2);
5779 GEN_SPEOP_LD(whsplat, 2);
5780
5781 GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
5782 GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
5783 GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
5784 GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
5785 GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
5786 GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
5787 GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
5788 GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
5789 GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
5790 GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
5791 GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
5792 GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
5793 GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
5794 GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
5795 GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
5796 GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
5797 GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
5798 GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
5799
5800 /* Multiply and add - TODO */
5801 #if 0
5802 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
5803 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
5804 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
5805 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
5806 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
5807 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
5808 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
5809 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
5810 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
5811 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
5812 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
5813 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
5814
5815 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
5816 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
5817 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
5818 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
5819 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
5820 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
5821 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
5822 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
5823 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
5824 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
5825 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
5826 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
5827 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
5828 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
5829
5830 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
5831 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
5832 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
5833 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
5834 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
5835 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
5836
5837 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
5838 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
5839 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
5840 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
5841 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
5842 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
5843 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
5844 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
5845 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
5846 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
5847 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
5848 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
5849
5850 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
5851 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
5852 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
5853 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
5854 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
5855
5856 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
5857 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
5858 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
5859 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
5860 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
5861 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
5862 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
5863 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
5864 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
5865 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
5866 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
5867 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
5868
5869 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
5870 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
5871 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
5872 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
5873 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
5874 #endif
5875
5876 /*** SPE floating-point extension ***/
5877 #define GEN_SPEFPUOP_CONV(name) \
5878 static always_inline void gen_##name (DisasContext *ctx) \
5879 { \
5880 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5881 gen_op_##name(); \
5882 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5883 }
5884
5885 /* Single precision floating-point vectors operations */
5886 /* Arithmetic */
5887 GEN_SPEOP_ARITH2(evfsadd);
5888 GEN_SPEOP_ARITH2(evfssub);
5889 GEN_SPEOP_ARITH2(evfsmul);
5890 GEN_SPEOP_ARITH2(evfsdiv);
5891 GEN_SPEOP_ARITH1(evfsabs);
5892 GEN_SPEOP_ARITH1(evfsnabs);
5893 GEN_SPEOP_ARITH1(evfsneg);
5894 /* Conversion */
5895 GEN_SPEFPUOP_CONV(evfscfui);
5896 GEN_SPEFPUOP_CONV(evfscfsi);
5897 GEN_SPEFPUOP_CONV(evfscfuf);
5898 GEN_SPEFPUOP_CONV(evfscfsf);
5899 GEN_SPEFPUOP_CONV(evfsctui);
5900 GEN_SPEFPUOP_CONV(evfsctsi);
5901 GEN_SPEFPUOP_CONV(evfsctuf);
5902 GEN_SPEFPUOP_CONV(evfsctsf);
5903 GEN_SPEFPUOP_CONV(evfsctuiz);
5904 GEN_SPEFPUOP_CONV(evfsctsiz);
5905 /* Comparison */
5906 GEN_SPEOP_COMP(evfscmpgt);
5907 GEN_SPEOP_COMP(evfscmplt);
5908 GEN_SPEOP_COMP(evfscmpeq);
5909 GEN_SPEOP_COMP(evfststgt);
5910 GEN_SPEOP_COMP(evfststlt);
5911 GEN_SPEOP_COMP(evfststeq);
5912
5913 /* Opcodes definitions */
5914 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
5915 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
5916 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
5917 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
5918 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
5919 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
5920 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
5921 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
5922 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
5923 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
5924 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
5925 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
5926 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
5927 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
5928
5929 /* Single precision floating-point operations */
5930 /* Arithmetic */
5931 GEN_SPEOP_ARITH2(efsadd);
5932 GEN_SPEOP_ARITH2(efssub);
5933 GEN_SPEOP_ARITH2(efsmul);
5934 GEN_SPEOP_ARITH2(efsdiv);
5935 GEN_SPEOP_ARITH1(efsabs);
5936 GEN_SPEOP_ARITH1(efsnabs);
5937 GEN_SPEOP_ARITH1(efsneg);
5938 /* Conversion */
5939 GEN_SPEFPUOP_CONV(efscfui);
5940 GEN_SPEFPUOP_CONV(efscfsi);
5941 GEN_SPEFPUOP_CONV(efscfuf);
5942 GEN_SPEFPUOP_CONV(efscfsf);
5943 GEN_SPEFPUOP_CONV(efsctui);
5944 GEN_SPEFPUOP_CONV(efsctsi);
5945 GEN_SPEFPUOP_CONV(efsctuf);
5946 GEN_SPEFPUOP_CONV(efsctsf);
5947 GEN_SPEFPUOP_CONV(efsctuiz);
5948 GEN_SPEFPUOP_CONV(efsctsiz);
5949 GEN_SPEFPUOP_CONV(efscfd);
5950 /* Comparison */
5951 GEN_SPEOP_COMP(efscmpgt);
5952 GEN_SPEOP_COMP(efscmplt);
5953 GEN_SPEOP_COMP(efscmpeq);
5954 GEN_SPEOP_COMP(efststgt);
5955 GEN_SPEOP_COMP(efststlt);
5956 GEN_SPEOP_COMP(efststeq);
5957
5958 /* Opcodes definitions */
5959 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
5960 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
5961 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
5962 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
5963 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
5964 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
5965 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
5966 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
5967 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
5968 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
5969 GEN_SPE(efsctuiz, efsctsiz, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
5970 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
5971 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
5972
5973 /* Double precision floating-point operations */
5974 /* Arithmetic */
5975 GEN_SPEOP_ARITH2(efdadd);
5976 GEN_SPEOP_ARITH2(efdsub);
5977 GEN_SPEOP_ARITH2(efdmul);
5978 GEN_SPEOP_ARITH2(efddiv);
5979 GEN_SPEOP_ARITH1(efdabs);
5980 GEN_SPEOP_ARITH1(efdnabs);
5981 GEN_SPEOP_ARITH1(efdneg);
5982 /* Conversion */
5983
5984 GEN_SPEFPUOP_CONV(efdcfui);
5985 GEN_SPEFPUOP_CONV(efdcfsi);
5986 GEN_SPEFPUOP_CONV(efdcfuf);
5987 GEN_SPEFPUOP_CONV(efdcfsf);
5988 GEN_SPEFPUOP_CONV(efdctui);
5989 GEN_SPEFPUOP_CONV(efdctsi);
5990 GEN_SPEFPUOP_CONV(efdctuf);
5991 GEN_SPEFPUOP_CONV(efdctsf);
5992 GEN_SPEFPUOP_CONV(efdctuiz);
5993 GEN_SPEFPUOP_CONV(efdctsiz);
5994 GEN_SPEFPUOP_CONV(efdcfs);
5995 GEN_SPEFPUOP_CONV(efdcfuid);
5996 GEN_SPEFPUOP_CONV(efdcfsid);
5997 GEN_SPEFPUOP_CONV(efdctuidz);
5998 GEN_SPEFPUOP_CONV(efdctsidz);
5999 /* Comparison */
6000 GEN_SPEOP_COMP(efdcmpgt);
6001 GEN_SPEOP_COMP(efdcmplt);
6002 GEN_SPEOP_COMP(efdcmpeq);
6003 GEN_SPEOP_COMP(efdtstgt);
6004 GEN_SPEOP_COMP(efdtstlt);
6005 GEN_SPEOP_COMP(efdtsteq);
6006
6007 /* Opcodes definitions */
6008 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6009 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6010 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6011 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6012 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6013 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6014 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6015 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6016 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6017 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6018 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6019 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6020 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6021 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6022 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6023 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
6024
6025 /* End opcode list */
6026 GEN_OPCODE_MARK(end);
6027
6028 #include "translate_init.c"
6029 #include "helper_regs.h"
6030
6031 /*****************************************************************************/
6032 /* Misc PowerPC helpers */
6033 void cpu_dump_state (CPUState *env, FILE *f,
6034 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6035 int flags)
6036 {
6037 #define RGPL 4
6038 #define RFPL 4
6039
6040 int i;
6041
6042 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
6043 env->nip, env->lr, env->ctr, hreg_load_xer(env));
6044 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6045 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
6046 #if !defined(NO_TIMER_DUMP)
6047 cpu_fprintf(f, "TB %08x %08x "
6048 #if !defined(CONFIG_USER_ONLY)
6049 "DECR %08x"
6050 #endif
6051 "\n",
6052 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6053 #if !defined(CONFIG_USER_ONLY)
6054 , cpu_ppc_load_decr(env)
6055 #endif
6056 );
6057 #endif
6058 for (i = 0; i < 32; i++) {
6059 if ((i & (RGPL - 1)) == 0)
6060 cpu_fprintf(f, "GPR%02d", i);
6061 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
6062 if ((i & (RGPL - 1)) == (RGPL - 1))
6063 cpu_fprintf(f, "\n");
6064 }
6065 cpu_fprintf(f, "CR ");
6066 for (i = 0; i < 8; i++)
6067 cpu_fprintf(f, "%01x", env->crf[i]);
6068 cpu_fprintf(f, " [");
6069 for (i = 0; i < 8; i++) {
6070 char a = '-';
6071 if (env->crf[i] & 0x08)
6072 a = 'L';
6073 else if (env->crf[i] & 0x04)
6074 a = 'G';
6075 else if (env->crf[i] & 0x02)
6076 a = 'E';
6077 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6078 }
6079 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
6080 for (i = 0; i < 32; i++) {
6081 if ((i & (RFPL - 1)) == 0)
6082 cpu_fprintf(f, "FPR%02d", i);
6083 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6084 if ((i & (RFPL - 1)) == (RFPL - 1))
6085 cpu_fprintf(f, "\n");
6086 }
6087 #if !defined(CONFIG_USER_ONLY)
6088 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
6089 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
6090 #endif
6091
6092 #undef RGPL
6093 #undef RFPL
6094 }
6095
6096 void cpu_dump_statistics (CPUState *env, FILE*f,
6097 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6098 int flags)
6099 {
6100 #if defined(DO_PPC_STATISTICS)
6101 opc_handler_t **t1, **t2, **t3, *handler;
6102 int op1, op2, op3;
6103
6104 t1 = env->opcodes;
6105 for (op1 = 0; op1 < 64; op1++) {
6106 handler = t1[op1];
6107 if (is_indirect_opcode(handler)) {
6108 t2 = ind_table(handler);
6109 for (op2 = 0; op2 < 32; op2++) {
6110 handler = t2[op2];
6111 if (is_indirect_opcode(handler)) {
6112 t3 = ind_table(handler);
6113 for (op3 = 0; op3 < 32; op3++) {
6114 handler = t3[op3];
6115 if (handler->count == 0)
6116 continue;
6117 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6118 "%016llx %lld\n",
6119 op1, op2, op3, op1, (op3 << 5) | op2,
6120 handler->oname,
6121 handler->count, handler->count);
6122 }
6123 } else {
6124 if (handler->count == 0)
6125 continue;
6126 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6127 "%016llx %lld\n",
6128 op1, op2, op1, op2, handler->oname,
6129 handler->count, handler->count);
6130 }
6131 }
6132 } else {
6133 if (handler->count == 0)
6134 continue;
6135 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6136 op1, op1, handler->oname,
6137 handler->count, handler->count);
6138 }
6139 }
6140 #endif
6141 }
6142
6143 /*****************************************************************************/
6144 static always_inline int gen_intermediate_code_internal (CPUState *env,
6145 TranslationBlock *tb,
6146 int search_pc)
6147 {
6148 DisasContext ctx, *ctxp = &ctx;
6149 opc_handler_t **table, *handler;
6150 target_ulong pc_start;
6151 uint16_t *gen_opc_end;
6152 int supervisor, little_endian;
6153 int single_step, branch_step;
6154 int j, lj = -1;
6155
6156 pc_start = tb->pc;
6157 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6158 #if defined(OPTIMIZE_FPRF_UPDATE)
6159 gen_fprf_ptr = gen_fprf_buf;
6160 #endif
6161 ctx.nip = pc_start;
6162 ctx.tb = tb;
6163 ctx.exception = POWERPC_EXCP_NONE;
6164 ctx.spr_cb = env->spr_cb;
6165 supervisor = env->mmu_idx;
6166 #if !defined(CONFIG_USER_ONLY)
6167 ctx.supervisor = supervisor;
6168 #endif
6169 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
6170 #if defined(TARGET_PPC64)
6171 ctx.sf_mode = msr_sf;
6172 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
6173 #else
6174 ctx.mem_idx = (supervisor << 1) | little_endian;
6175 #endif
6176 ctx.dcache_line_size = env->dcache_line_size;
6177 ctx.fpu_enabled = msr_fp;
6178 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6179 ctx.spe_enabled = msr_spe;
6180 else
6181 ctx.spe_enabled = 0;
6182 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6183 ctx.altivec_enabled = msr_vr;
6184 else
6185 ctx.altivec_enabled = 0;
6186 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6187 single_step = 1;
6188 else
6189 single_step = 0;
6190 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6191 branch_step = 1;
6192 else
6193 branch_step = 0;
6194 ctx.singlestep_enabled = env->singlestep_enabled || single_step == 1;
6195 #if defined (DO_SINGLE_STEP) && 0
6196 /* Single step trace mode */
6197 msr_se = 1;
6198 #endif
6199 /* Set env in case of segfault during code fetch */
6200 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
6201 if (unlikely(env->nb_breakpoints > 0)) {
6202 for (j = 0; j < env->nb_breakpoints; j++) {
6203 if (env->breakpoints[j] == ctx.nip) {
6204 gen_update_nip(&ctx, ctx.nip);
6205 gen_op_debug();
6206 break;
6207 }
6208 }
6209 }
6210 if (unlikely(search_pc)) {
6211 j = gen_opc_ptr - gen_opc_buf;
6212 if (lj < j) {
6213 lj++;
6214 while (lj < j)
6215 gen_opc_instr_start[lj++] = 0;
6216 gen_opc_pc[lj] = ctx.nip;
6217 gen_opc_instr_start[lj] = 1;
6218 }
6219 }
6220 #if defined PPC_DEBUG_DISAS
6221 if (loglevel & CPU_LOG_TB_IN_ASM) {
6222 fprintf(logfile, "----------------\n");
6223 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
6224 ctx.nip, supervisor, (int)msr_ir);
6225 }
6226 #endif
6227 if (unlikely(little_endian)) {
6228 ctx.opcode = bswap32(ldl_code(ctx.nip));
6229 } else {
6230 ctx.opcode = ldl_code(ctx.nip);
6231 }
6232 #if defined PPC_DEBUG_DISAS
6233 if (loglevel & CPU_LOG_TB_IN_ASM) {
6234 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
6235 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
6236 opc3(ctx.opcode), little_endian ? "little" : "big");
6237 }
6238 #endif
6239 ctx.nip += 4;
6240 table = env->opcodes;
6241 handler = table[opc1(ctx.opcode)];
6242 if (is_indirect_opcode(handler)) {
6243 table = ind_table(handler);
6244 handler = table[opc2(ctx.opcode)];
6245 if (is_indirect_opcode(handler)) {
6246 table = ind_table(handler);
6247 handler = table[opc3(ctx.opcode)];
6248 }
6249 }
6250 /* Is opcode *REALLY* valid ? */
6251 if (unlikely(handler->handler == &gen_invalid)) {
6252 if (loglevel != 0) {
6253 fprintf(logfile, "invalid/unsupported opcode: "
6254 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
6255 opc1(ctx.opcode), opc2(ctx.opcode),
6256 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6257 } else {
6258 printf("invalid/unsupported opcode: "
6259 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
6260 opc1(ctx.opcode), opc2(ctx.opcode),
6261 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6262 }
6263 } else {
6264 if (unlikely((ctx.opcode & handler->inval) != 0)) {
6265 if (loglevel != 0) {
6266 fprintf(logfile, "invalid bits: %08x for opcode: "
6267 "%02x - %02x - %02x (%08x) " ADDRX "\n",
6268 ctx.opcode & handler->inval, opc1(ctx.opcode),
6269 opc2(ctx.opcode), opc3(ctx.opcode),
6270 ctx.opcode, ctx.nip - 4);
6271 } else {
6272 printf("invalid bits: %08x for opcode: "
6273 "%02x - %02x - %02x (%08x) " ADDRX "\n",
6274 ctx.opcode & handler->inval, opc1(ctx.opcode),
6275 opc2(ctx.opcode), opc3(ctx.opcode),
6276 ctx.opcode, ctx.nip - 4);
6277 }
6278 GEN_EXCP_INVAL(ctxp);
6279 break;
6280 }
6281 }
6282 (*(handler->handler))(&ctx);
6283 #if defined(DO_PPC_STATISTICS)
6284 handler->count++;
6285 #endif
6286 /* Check trace mode exceptions */
6287 if (unlikely(branch_step != 0 &&
6288 ctx.exception == POWERPC_EXCP_BRANCH)) {
6289 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6290 } else if (unlikely(single_step != 0 &&
6291 (ctx.nip <= 0x100 || ctx.nip > 0xF00 ||
6292 (ctx.nip & 0xFC) != 0x04) &&
6293 ctx.exception != POWERPC_SYSCALL &&
6294 ctx.exception != POWERPC_EXCP_TRAP)) {
6295 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6296 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
6297 (env->singlestep_enabled))) {
6298 /* if we reach a page boundary or are single stepping, stop
6299 * generation
6300 */
6301 break;
6302 }
6303 #if defined (DO_SINGLE_STEP)
6304 break;
6305 #endif
6306 }
6307 if (ctx.exception == POWERPC_EXCP_NONE) {
6308 gen_goto_tb(&ctx, 0, ctx.nip);
6309 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
6310 /* Generate the return instruction */
6311 tcg_gen_exit_tb(0);
6312 }
6313 *gen_opc_ptr = INDEX_op_end;
6314 if (unlikely(search_pc)) {
6315 j = gen_opc_ptr - gen_opc_buf;
6316 lj++;
6317 while (lj <= j)
6318 gen_opc_instr_start[lj++] = 0;
6319 } else {
6320 tb->size = ctx.nip - pc_start;
6321 }
6322 #if defined(DEBUG_DISAS)
6323 if (loglevel & CPU_LOG_TB_CPU) {
6324 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
6325 cpu_dump_state(env, logfile, fprintf, 0);
6326 }
6327 if (loglevel & CPU_LOG_TB_IN_ASM) {
6328 int flags;
6329 flags = env->bfd_mach;
6330 flags |= little_endian << 16;
6331 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
6332 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
6333 fprintf(logfile, "\n");
6334 }
6335 #endif
6336 return 0;
6337 }
6338
6339 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
6340 {
6341 return gen_intermediate_code_internal(env, tb, 0);
6342 }
6343
6344 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
6345 {
6346 return gen_intermediate_code_internal(env, tb, 1);
6347 }
Qemu copy for testing