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target-ppc: convert SPE FP ops to TCG
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31
32 #include "helper.h"
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define DO_SINGLE_STEP
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44 //#define OPTIMIZE_FPRF_UPDATE
45
46 /*****************************************************************************/
47 /* Code translation helpers */
48
49 /* global register indexes */
50 static TCGv_ptr cpu_env;
51 static char cpu_reg_names[10*3 + 22*4 /* GPR */
52 #if !defined(TARGET_PPC64)
53 + 10*4 + 22*5 /* SPE GPRh */
54 #endif
55 + 10*4 + 22*5 /* FPR */
56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 8*5 /* CRF */];
58 static TCGv cpu_gpr[32];
59 #if !defined(TARGET_PPC64)
60 static TCGv cpu_gprh[32];
61 #endif
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i32 cpu_crf[8];
65 static TCGv cpu_nip;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 static TCGv cpu_xer;
69 static TCGv_i32 cpu_fpscr;
70
71 /* dyngen register indexes */
72 static TCGv cpu_T[3];
73 #if defined(TARGET_PPC64)
74 #define cpu_T64 cpu_T
75 #else
76 static TCGv_i64 cpu_T64[3];
77 #endif
78 static TCGv_i64 cpu_FT[2];
79 static TCGv_i64 cpu_AVRh[3], cpu_AVRl[3];
80
81 #include "gen-icount.h"
82
83 void ppc_translate_init(void)
84 {
85 int i;
86 char* p;
87 static int done_init = 0;
88
89 if (done_init)
90 return;
91
92 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
93 #if TARGET_LONG_BITS > HOST_LONG_BITS
94 cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0");
95 cpu_T[1] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t1), "T1");
96 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
97 #else
98 cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0");
99 cpu_T[1] = tcg_global_reg_new(TCG_AREG2, "T1");
100 #ifdef HOST_I386
101 /* XXX: This is a temporary workaround for i386.
102 * On i386 qemu_st32 runs out of registers.
103 * The proper fix is to remove cpu_T.
104 */
105 cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");
106 #else
107 cpu_T[2] = tcg_global_reg_new(TCG_AREG3, "T2");
108 #endif
109 #endif
110 #if !defined(TARGET_PPC64)
111 cpu_T64[0] = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, t0_64),
112 "T0_64");
113 cpu_T64[1] = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, t1_64),
114 "T1_64");
115 cpu_T64[2] = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, t2_64),
116 "T2_64");
117 #endif
118
119 cpu_FT[0] = tcg_global_mem_new_i64(TCG_AREG0,
120 offsetof(CPUState, ft0), "FT0");
121 cpu_FT[1] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUState, ft1), "FT1");
123
124 cpu_AVRh[0] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUState, avr0.u64[0]), "AVR0H");
126 cpu_AVRl[0] = tcg_global_mem_new_i64(TCG_AREG0,
127 offsetof(CPUState, avr0.u64[1]), "AVR0L");
128 cpu_AVRh[1] = tcg_global_mem_new_i64(TCG_AREG0,
129 offsetof(CPUState, avr1.u64[0]), "AVR1H");
130 cpu_AVRl[1] = tcg_global_mem_new_i64(TCG_AREG0,
131 offsetof(CPUState, avr1.u64[1]), "AVR1L");
132 cpu_AVRh[2] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUState, avr2.u64[0]), "AVR2H");
134 cpu_AVRl[2] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUState, avr2.u64[1]), "AVR2L");
136
137 p = cpu_reg_names;
138
139 for (i = 0; i < 8; i++) {
140 sprintf(p, "crf%d", i);
141 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
142 offsetof(CPUState, crf[i]), p);
143 p += 5;
144 }
145
146 for (i = 0; i < 32; i++) {
147 sprintf(p, "r%d", i);
148 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUState, gpr[i]), p);
150 p += (i < 10) ? 3 : 4;
151 #if !defined(TARGET_PPC64)
152 sprintf(p, "r%dH", i);
153 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
154 offsetof(CPUState, gprh[i]), p);
155 p += (i < 10) ? 4 : 5;
156 #endif
157
158 sprintf(p, "fp%d", i);
159 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
160 offsetof(CPUState, fpr[i]), p);
161 p += (i < 10) ? 4 : 5;
162
163 sprintf(p, "avr%dH", i);
164 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
165 offsetof(CPUState, avr[i].u64[0]), p);
166 p += (i < 10) ? 6 : 7;
167
168 sprintf(p, "avr%dL", i);
169 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
170 offsetof(CPUState, avr[i].u64[1]), p);
171 p += (i < 10) ? 6 : 7;
172 }
173
174 cpu_nip = tcg_global_mem_new(TCG_AREG0,
175 offsetof(CPUState, nip), "nip");
176
177 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
178 offsetof(CPUState, ctr), "ctr");
179
180 cpu_lr = tcg_global_mem_new(TCG_AREG0,
181 offsetof(CPUState, lr), "lr");
182
183 cpu_xer = tcg_global_mem_new(TCG_AREG0,
184 offsetof(CPUState, xer), "xer");
185
186 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
187 offsetof(CPUState, fpscr), "fpscr");
188
189 /* register helpers */
190 #define GEN_HELPER 2
191 #include "helper.h"
192
193 done_init = 1;
194 }
195
196 #if defined(OPTIMIZE_FPRF_UPDATE)
197 static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
198 static uint16_t **gen_fprf_ptr;
199 #endif
200
201 /* internal defines */
202 typedef struct DisasContext {
203 struct TranslationBlock *tb;
204 target_ulong nip;
205 uint32_t opcode;
206 uint32_t exception;
207 /* Routine used to access memory */
208 int mem_idx;
209 /* Translation flags */
210 #if !defined(CONFIG_USER_ONLY)
211 int supervisor;
212 #endif
213 #if defined(TARGET_PPC64)
214 int sf_mode;
215 #endif
216 int fpu_enabled;
217 int altivec_enabled;
218 int spe_enabled;
219 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
220 int singlestep_enabled;
221 int dcache_line_size;
222 } DisasContext;
223
224 struct opc_handler_t {
225 /* invalid bits */
226 uint32_t inval;
227 /* instruction type */
228 uint64_t type;
229 /* handler */
230 void (*handler)(DisasContext *ctx);
231 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
232 const char *oname;
233 #endif
234 #if defined(DO_PPC_STATISTICS)
235 uint64_t count;
236 #endif
237 };
238
239 static always_inline void gen_reset_fpstatus (void)
240 {
241 #ifdef CONFIG_SOFTFLOAT
242 gen_op_reset_fpstatus();
243 #endif
244 }
245
246 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
247 {
248 TCGv_i32 t0 = tcg_temp_new_i32();
249
250 if (set_fprf != 0) {
251 /* This case might be optimized later */
252 #if defined(OPTIMIZE_FPRF_UPDATE)
253 *gen_fprf_ptr++ = gen_opc_ptr;
254 #endif
255 tcg_gen_movi_i32(t0, 1);
256 gen_helper_compute_fprf(t0, arg, t0);
257 if (unlikely(set_rc)) {
258 tcg_gen_mov_i32(cpu_crf[1], t0);
259 }
260 gen_helper_float_check_status();
261 } else if (unlikely(set_rc)) {
262 /* We always need to compute fpcc */
263 tcg_gen_movi_i32(t0, 0);
264 gen_helper_compute_fprf(t0, arg, t0);
265 tcg_gen_mov_i32(cpu_crf[1], t0);
266 if (set_fprf)
267 gen_helper_float_check_status();
268 }
269
270 tcg_temp_free_i32(t0);
271 }
272
273 static always_inline void gen_optimize_fprf (void)
274 {
275 #if defined(OPTIMIZE_FPRF_UPDATE)
276 uint16_t **ptr;
277
278 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
279 *ptr = INDEX_op_nop1;
280 gen_fprf_ptr = gen_fprf_buf;
281 #endif
282 }
283
284 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
285 {
286 #if defined(TARGET_PPC64)
287 if (ctx->sf_mode)
288 tcg_gen_movi_tl(cpu_nip, nip);
289 else
290 #endif
291 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
292 }
293
294 #define GEN_EXCP(ctx, excp, error) \
295 do { \
296 TCGv_i32 t0 = tcg_const_i32(excp); \
297 TCGv_i32 t1 = tcg_const_i32(error); \
298 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
299 gen_update_nip(ctx, (ctx)->nip); \
300 } \
301 gen_helper_raise_exception_err(t0, t1); \
302 tcg_temp_free_i32(t0); \
303 tcg_temp_free_i32(t1); \
304 ctx->exception = (excp); \
305 } while (0)
306
307 #define GEN_EXCP_INVAL(ctx) \
308 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
309 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
310
311 #define GEN_EXCP_PRIVOPC(ctx) \
312 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
313 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
314
315 #define GEN_EXCP_PRIVREG(ctx) \
316 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
317 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
318
319 #define GEN_EXCP_NO_FP(ctx) \
320 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
321
322 #define GEN_EXCP_NO_AP(ctx) \
323 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
324
325 #define GEN_EXCP_NO_VR(ctx) \
326 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
327
328 /* Stop translation */
329 static always_inline void GEN_STOP (DisasContext *ctx)
330 {
331 gen_update_nip(ctx, ctx->nip);
332 ctx->exception = POWERPC_EXCP_STOP;
333 }
334
335 /* No need to update nip here, as execution flow will change */
336 static always_inline void GEN_SYNC (DisasContext *ctx)
337 {
338 ctx->exception = POWERPC_EXCP_SYNC;
339 }
340
341 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
342 static void gen_##name (DisasContext *ctx); \
343 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
344 static void gen_##name (DisasContext *ctx)
345
346 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
347 static void gen_##name (DisasContext *ctx); \
348 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
349 static void gen_##name (DisasContext *ctx)
350
351 typedef struct opcode_t {
352 unsigned char opc1, opc2, opc3;
353 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
354 unsigned char pad[5];
355 #else
356 unsigned char pad[1];
357 #endif
358 opc_handler_t handler;
359 const char *oname;
360 } opcode_t;
361
362 /*****************************************************************************/
363 /*** Instruction decoding ***/
364 #define EXTRACT_HELPER(name, shift, nb) \
365 static always_inline uint32_t name (uint32_t opcode) \
366 { \
367 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
368 }
369
370 #define EXTRACT_SHELPER(name, shift, nb) \
371 static always_inline int32_t name (uint32_t opcode) \
372 { \
373 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
374 }
375
376 /* Opcode part 1 */
377 EXTRACT_HELPER(opc1, 26, 6);
378 /* Opcode part 2 */
379 EXTRACT_HELPER(opc2, 1, 5);
380 /* Opcode part 3 */
381 EXTRACT_HELPER(opc3, 6, 5);
382 /* Update Cr0 flags */
383 EXTRACT_HELPER(Rc, 0, 1);
384 /* Destination */
385 EXTRACT_HELPER(rD, 21, 5);
386 /* Source */
387 EXTRACT_HELPER(rS, 21, 5);
388 /* First operand */
389 EXTRACT_HELPER(rA, 16, 5);
390 /* Second operand */
391 EXTRACT_HELPER(rB, 11, 5);
392 /* Third operand */
393 EXTRACT_HELPER(rC, 6, 5);
394 /*** Get CRn ***/
395 EXTRACT_HELPER(crfD, 23, 3);
396 EXTRACT_HELPER(crfS, 18, 3);
397 EXTRACT_HELPER(crbD, 21, 5);
398 EXTRACT_HELPER(crbA, 16, 5);
399 EXTRACT_HELPER(crbB, 11, 5);
400 /* SPR / TBL */
401 EXTRACT_HELPER(_SPR, 11, 10);
402 static always_inline uint32_t SPR (uint32_t opcode)
403 {
404 uint32_t sprn = _SPR(opcode);
405
406 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
407 }
408 /*** Get constants ***/
409 EXTRACT_HELPER(IMM, 12, 8);
410 /* 16 bits signed immediate value */
411 EXTRACT_SHELPER(SIMM, 0, 16);
412 /* 16 bits unsigned immediate value */
413 EXTRACT_HELPER(UIMM, 0, 16);
414 /* Bit count */
415 EXTRACT_HELPER(NB, 11, 5);
416 /* Shift count */
417 EXTRACT_HELPER(SH, 11, 5);
418 /* Mask start */
419 EXTRACT_HELPER(MB, 6, 5);
420 /* Mask end */
421 EXTRACT_HELPER(ME, 1, 5);
422 /* Trap operand */
423 EXTRACT_HELPER(TO, 21, 5);
424
425 EXTRACT_HELPER(CRM, 12, 8);
426 EXTRACT_HELPER(FM, 17, 8);
427 EXTRACT_HELPER(SR, 16, 4);
428 EXTRACT_HELPER(FPIMM, 12, 4);
429
430 /*** Jump target decoding ***/
431 /* Displacement */
432 EXTRACT_SHELPER(d, 0, 16);
433 /* Immediate address */
434 static always_inline target_ulong LI (uint32_t opcode)
435 {
436 return (opcode >> 0) & 0x03FFFFFC;
437 }
438
439 static always_inline uint32_t BD (uint32_t opcode)
440 {
441 return (opcode >> 0) & 0xFFFC;
442 }
443
444 EXTRACT_HELPER(BO, 21, 5);
445 EXTRACT_HELPER(BI, 16, 5);
446 /* Absolute/relative address */
447 EXTRACT_HELPER(AA, 1, 1);
448 /* Link */
449 EXTRACT_HELPER(LK, 0, 1);
450
451 /* Create a mask between <start> and <end> bits */
452 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
453 {
454 target_ulong ret;
455
456 #if defined(TARGET_PPC64)
457 if (likely(start == 0)) {
458 ret = UINT64_MAX << (63 - end);
459 } else if (likely(end == 63)) {
460 ret = UINT64_MAX >> start;
461 }
462 #else
463 if (likely(start == 0)) {
464 ret = UINT32_MAX << (31 - end);
465 } else if (likely(end == 31)) {
466 ret = UINT32_MAX >> start;
467 }
468 #endif
469 else {
470 ret = (((target_ulong)(-1ULL)) >> (start)) ^
471 (((target_ulong)(-1ULL) >> (end)) >> 1);
472 if (unlikely(start > end))
473 return ~ret;
474 }
475
476 return ret;
477 }
478
479 /*****************************************************************************/
480 /* PowerPC Instructions types definitions */
481 enum {
482 PPC_NONE = 0x0000000000000000ULL,
483 /* PowerPC base instructions set */
484 PPC_INSNS_BASE = 0x0000000000000001ULL,
485 /* integer operations instructions */
486 #define PPC_INTEGER PPC_INSNS_BASE
487 /* flow control instructions */
488 #define PPC_FLOW PPC_INSNS_BASE
489 /* virtual memory instructions */
490 #define PPC_MEM PPC_INSNS_BASE
491 /* ld/st with reservation instructions */
492 #define PPC_RES PPC_INSNS_BASE
493 /* spr/msr access instructions */
494 #define PPC_MISC PPC_INSNS_BASE
495 /* Deprecated instruction sets */
496 /* Original POWER instruction set */
497 PPC_POWER = 0x0000000000000002ULL,
498 /* POWER2 instruction set extension */
499 PPC_POWER2 = 0x0000000000000004ULL,
500 /* Power RTC support */
501 PPC_POWER_RTC = 0x0000000000000008ULL,
502 /* Power-to-PowerPC bridge (601) */
503 PPC_POWER_BR = 0x0000000000000010ULL,
504 /* 64 bits PowerPC instruction set */
505 PPC_64B = 0x0000000000000020ULL,
506 /* New 64 bits extensions (PowerPC 2.0x) */
507 PPC_64BX = 0x0000000000000040ULL,
508 /* 64 bits hypervisor extensions */
509 PPC_64H = 0x0000000000000080ULL,
510 /* New wait instruction (PowerPC 2.0x) */
511 PPC_WAIT = 0x0000000000000100ULL,
512 /* Time base mftb instruction */
513 PPC_MFTB = 0x0000000000000200ULL,
514
515 /* Fixed-point unit extensions */
516 /* PowerPC 602 specific */
517 PPC_602_SPEC = 0x0000000000000400ULL,
518 /* isel instruction */
519 PPC_ISEL = 0x0000000000000800ULL,
520 /* popcntb instruction */
521 PPC_POPCNTB = 0x0000000000001000ULL,
522 /* string load / store */
523 PPC_STRING = 0x0000000000002000ULL,
524
525 /* Floating-point unit extensions */
526 /* Optional floating point instructions */
527 PPC_FLOAT = 0x0000000000010000ULL,
528 /* New floating-point extensions (PowerPC 2.0x) */
529 PPC_FLOAT_EXT = 0x0000000000020000ULL,
530 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
531 PPC_FLOAT_FRES = 0x0000000000080000ULL,
532 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
533 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
534 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
535 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
536
537 /* Vector/SIMD extensions */
538 /* Altivec support */
539 PPC_ALTIVEC = 0x0000000001000000ULL,
540 /* PowerPC 2.03 SPE extension */
541 PPC_SPE = 0x0000000002000000ULL,
542 /* PowerPC 2.03 SPE floating-point extension */
543 PPC_SPEFPU = 0x0000000004000000ULL,
544
545 /* Optional memory control instructions */
546 PPC_MEM_TLBIA = 0x0000000010000000ULL,
547 PPC_MEM_TLBIE = 0x0000000020000000ULL,
548 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
549 /* sync instruction */
550 PPC_MEM_SYNC = 0x0000000080000000ULL,
551 /* eieio instruction */
552 PPC_MEM_EIEIO = 0x0000000100000000ULL,
553
554 /* Cache control instructions */
555 PPC_CACHE = 0x0000000200000000ULL,
556 /* icbi instruction */
557 PPC_CACHE_ICBI = 0x0000000400000000ULL,
558 /* dcbz instruction with fixed cache line size */
559 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
560 /* dcbz instruction with tunable cache line size */
561 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
562 /* dcba instruction */
563 PPC_CACHE_DCBA = 0x0000002000000000ULL,
564 /* Freescale cache locking instructions */
565 PPC_CACHE_LOCK = 0x0000004000000000ULL,
566
567 /* MMU related extensions */
568 /* external control instructions */
569 PPC_EXTERN = 0x0000010000000000ULL,
570 /* segment register access instructions */
571 PPC_SEGMENT = 0x0000020000000000ULL,
572 /* PowerPC 6xx TLB management instructions */
573 PPC_6xx_TLB = 0x0000040000000000ULL,
574 /* PowerPC 74xx TLB management instructions */
575 PPC_74xx_TLB = 0x0000080000000000ULL,
576 /* PowerPC 40x TLB management instructions */
577 PPC_40x_TLB = 0x0000100000000000ULL,
578 /* segment register access instructions for PowerPC 64 "bridge" */
579 PPC_SEGMENT_64B = 0x0000200000000000ULL,
580 /* SLB management */
581 PPC_SLBI = 0x0000400000000000ULL,
582
583 /* Embedded PowerPC dedicated instructions */
584 PPC_WRTEE = 0x0001000000000000ULL,
585 /* PowerPC 40x exception model */
586 PPC_40x_EXCP = 0x0002000000000000ULL,
587 /* PowerPC 405 Mac instructions */
588 PPC_405_MAC = 0x0004000000000000ULL,
589 /* PowerPC 440 specific instructions */
590 PPC_440_SPEC = 0x0008000000000000ULL,
591 /* BookE (embedded) PowerPC specification */
592 PPC_BOOKE = 0x0010000000000000ULL,
593 /* mfapidi instruction */
594 PPC_MFAPIDI = 0x0020000000000000ULL,
595 /* tlbiva instruction */
596 PPC_TLBIVA = 0x0040000000000000ULL,
597 /* tlbivax instruction */
598 PPC_TLBIVAX = 0x0080000000000000ULL,
599 /* PowerPC 4xx dedicated instructions */
600 PPC_4xx_COMMON = 0x0100000000000000ULL,
601 /* PowerPC 40x ibct instructions */
602 PPC_40x_ICBT = 0x0200000000000000ULL,
603 /* rfmci is not implemented in all BookE PowerPC */
604 PPC_RFMCI = 0x0400000000000000ULL,
605 /* rfdi instruction */
606 PPC_RFDI = 0x0800000000000000ULL,
607 /* DCR accesses */
608 PPC_DCR = 0x1000000000000000ULL,
609 /* DCR extended accesse */
610 PPC_DCRX = 0x2000000000000000ULL,
611 /* user-mode DCR access, implemented in PowerPC 460 */
612 PPC_DCRUX = 0x4000000000000000ULL,
613 };
614
615 /*****************************************************************************/
616 /* PowerPC instructions table */
617 #if HOST_LONG_BITS == 64
618 #define OPC_ALIGN 8
619 #else
620 #define OPC_ALIGN 4
621 #endif
622 #if defined(__APPLE__)
623 #define OPCODES_SECTION \
624 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
625 #else
626 #define OPCODES_SECTION \
627 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
628 #endif
629
630 #if defined(DO_PPC_STATISTICS)
631 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
632 OPCODES_SECTION opcode_t opc_##name = { \
633 .opc1 = op1, \
634 .opc2 = op2, \
635 .opc3 = op3, \
636 .pad = { 0, }, \
637 .handler = { \
638 .inval = invl, \
639 .type = _typ, \
640 .handler = &gen_##name, \
641 .oname = stringify(name), \
642 }, \
643 .oname = stringify(name), \
644 }
645 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
646 OPCODES_SECTION opcode_t opc_##name = { \
647 .opc1 = op1, \
648 .opc2 = op2, \
649 .opc3 = op3, \
650 .pad = { 0, }, \
651 .handler = { \
652 .inval = invl, \
653 .type = _typ, \
654 .handler = &gen_##name, \
655 .oname = onam, \
656 }, \
657 .oname = onam, \
658 }
659 #else
660 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
661 OPCODES_SECTION opcode_t opc_##name = { \
662 .opc1 = op1, \
663 .opc2 = op2, \
664 .opc3 = op3, \
665 .pad = { 0, }, \
666 .handler = { \
667 .inval = invl, \
668 .type = _typ, \
669 .handler = &gen_##name, \
670 }, \
671 .oname = stringify(name), \
672 }
673 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
674 OPCODES_SECTION opcode_t opc_##name = { \
675 .opc1 = op1, \
676 .opc2 = op2, \
677 .opc3 = op3, \
678 .pad = { 0, }, \
679 .handler = { \
680 .inval = invl, \
681 .type = _typ, \
682 .handler = &gen_##name, \
683 }, \
684 .oname = onam, \
685 }
686 #endif
687
688 #define GEN_OPCODE_MARK(name) \
689 OPCODES_SECTION opcode_t opc_##name = { \
690 .opc1 = 0xFF, \
691 .opc2 = 0xFF, \
692 .opc3 = 0xFF, \
693 .pad = { 0, }, \
694 .handler = { \
695 .inval = 0x00000000, \
696 .type = 0x00, \
697 .handler = NULL, \
698 }, \
699 .oname = stringify(name), \
700 }
701
702 /* Start opcode list */
703 GEN_OPCODE_MARK(start);
704
705 /* Invalid instruction */
706 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
707 {
708 GEN_EXCP_INVAL(ctx);
709 }
710
711 static opc_handler_t invalid_handler = {
712 .inval = 0xFFFFFFFF,
713 .type = PPC_NONE,
714 .handler = gen_invalid,
715 };
716
717 /*** Integer comparison ***/
718
719 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
720 {
721 int l1, l2, l3;
722
723 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
724 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
725 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
726
727 l1 = gen_new_label();
728 l2 = gen_new_label();
729 l3 = gen_new_label();
730 if (s) {
731 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
732 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
733 } else {
734 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
735 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
736 }
737 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
738 tcg_gen_br(l3);
739 gen_set_label(l1);
740 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
741 tcg_gen_br(l3);
742 gen_set_label(l2);
743 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
744 gen_set_label(l3);
745 }
746
747 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
748 {
749 TCGv t0 = tcg_const_local_tl(arg1);
750 gen_op_cmp(arg0, t0, s, crf);
751 tcg_temp_free(t0);
752 }
753
754 #if defined(TARGET_PPC64)
755 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
756 {
757 TCGv t0, t1;
758 t0 = tcg_temp_local_new();
759 t1 = tcg_temp_local_new();
760 if (s) {
761 tcg_gen_ext32s_tl(t0, arg0);
762 tcg_gen_ext32s_tl(t1, arg1);
763 } else {
764 tcg_gen_ext32u_tl(t0, arg0);
765 tcg_gen_ext32u_tl(t1, arg1);
766 }
767 gen_op_cmp(t0, t1, s, crf);
768 tcg_temp_free(t1);
769 tcg_temp_free(t0);
770 }
771
772 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
773 {
774 TCGv t0 = tcg_const_local_tl(arg1);
775 gen_op_cmp32(arg0, t0, s, crf);
776 tcg_temp_free(t0);
777 }
778 #endif
779
780 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
781 {
782 #if defined(TARGET_PPC64)
783 if (!(ctx->sf_mode))
784 gen_op_cmpi32(reg, 0, 1, 0);
785 else
786 #endif
787 gen_op_cmpi(reg, 0, 1, 0);
788 }
789
790 /* cmp */
791 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
792 {
793 #if defined(TARGET_PPC64)
794 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
795 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
796 1, crfD(ctx->opcode));
797 else
798 #endif
799 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
800 1, crfD(ctx->opcode));
801 }
802
803 /* cmpi */
804 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
805 {
806 #if defined(TARGET_PPC64)
807 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
808 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
809 1, crfD(ctx->opcode));
810 else
811 #endif
812 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
813 1, crfD(ctx->opcode));
814 }
815
816 /* cmpl */
817 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
818 {
819 #if defined(TARGET_PPC64)
820 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
821 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
822 0, crfD(ctx->opcode));
823 else
824 #endif
825 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
826 0, crfD(ctx->opcode));
827 }
828
829 /* cmpli */
830 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
831 {
832 #if defined(TARGET_PPC64)
833 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
834 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
835 0, crfD(ctx->opcode));
836 else
837 #endif
838 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
839 0, crfD(ctx->opcode));
840 }
841
842 /* isel (PowerPC 2.03 specification) */
843 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
844 {
845 int l1, l2;
846 uint32_t bi = rC(ctx->opcode);
847 uint32_t mask;
848 TCGv_i32 t0;
849
850 l1 = gen_new_label();
851 l2 = gen_new_label();
852
853 mask = 1 << (3 - (bi & 0x03));
854 t0 = tcg_temp_new_i32();
855 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
856 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
857 if (rA(ctx->opcode) == 0)
858 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
859 else
860 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
861 tcg_gen_br(l2);
862 gen_set_label(l1);
863 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
864 gen_set_label(l2);
865 tcg_temp_free_i32(t0);
866 }
867
868 /*** Integer arithmetic ***/
869
870 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
871 {
872 int l1;
873 TCGv t0;
874
875 l1 = gen_new_label();
876 /* Start with XER OV disabled, the most likely case */
877 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
878 t0 = tcg_temp_local_new();
879 tcg_gen_xor_tl(t0, arg0, arg1);
880 #if defined(TARGET_PPC64)
881 if (!ctx->sf_mode)
882 tcg_gen_ext32s_tl(t0, t0);
883 #endif
884 if (sub)
885 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
886 else
887 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
888 tcg_gen_xor_tl(t0, arg1, arg2);
889 #if defined(TARGET_PPC64)
890 if (!ctx->sf_mode)
891 tcg_gen_ext32s_tl(t0, t0);
892 #endif
893 if (sub)
894 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
895 else
896 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
897 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
898 gen_set_label(l1);
899 tcg_temp_free(t0);
900 }
901
902 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
903 {
904 int l1 = gen_new_label();
905
906 #if defined(TARGET_PPC64)
907 if (!(ctx->sf_mode)) {
908 TCGv t0, t1;
909 t0 = tcg_temp_new();
910 t1 = tcg_temp_new();
911
912 tcg_gen_ext32u_tl(t0, arg1);
913 tcg_gen_ext32u_tl(t1, arg2);
914 if (sub) {
915 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
916 } else {
917 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
918 }
919 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
920 gen_set_label(l1);
921 tcg_temp_free(t0);
922 tcg_temp_free(t1);
923 } else
924 #endif
925 {
926 if (sub) {
927 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
928 } else {
929 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
930 }
931 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
932 gen_set_label(l1);
933 }
934 }
935
936 /* Common add function */
937 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
938 int add_ca, int compute_ca, int compute_ov)
939 {
940 TCGv t0, t1;
941
942 if ((!compute_ca && !compute_ov) ||
943 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
944 t0 = ret;
945 } else {
946 t0 = tcg_temp_local_new();
947 }
948
949 if (add_ca) {
950 t1 = tcg_temp_local_new();
951 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
952 tcg_gen_shri_tl(t1, t1, XER_CA);
953 }
954
955 if (compute_ca && compute_ov) {
956 /* Start with XER CA and OV disabled, the most likely case */
957 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
958 } else if (compute_ca) {
959 /* Start with XER CA disabled, the most likely case */
960 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
961 } else if (compute_ov) {
962 /* Start with XER OV disabled, the most likely case */
963 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
964 }
965
966 tcg_gen_add_tl(t0, arg1, arg2);
967
968 if (compute_ca) {
969 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
970 }
971 if (add_ca) {
972 tcg_gen_add_tl(t0, t0, t1);
973 gen_op_arith_compute_ca(ctx, t0, t1, 0);
974 tcg_temp_free(t1);
975 }
976 if (compute_ov) {
977 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
978 }
979
980 if (unlikely(Rc(ctx->opcode) != 0))
981 gen_set_Rc0(ctx, t0);
982
983 if (!TCGV_EQUAL(t0, ret)) {
984 tcg_gen_mov_tl(ret, t0);
985 tcg_temp_free(t0);
986 }
987 }
988 /* Add functions with two operands */
989 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
990 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
991 { \
992 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
993 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
994 add_ca, compute_ca, compute_ov); \
995 }
996 /* Add functions with one operand and one immediate */
997 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
998 add_ca, compute_ca, compute_ov) \
999 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
1000 { \
1001 TCGv t0 = tcg_const_local_tl(const_val); \
1002 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1003 cpu_gpr[rA(ctx->opcode)], t0, \
1004 add_ca, compute_ca, compute_ov); \
1005 tcg_temp_free(t0); \
1006 }
1007
1008 /* add add. addo addo. */
1009 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1010 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1011 /* addc addc. addco addco. */
1012 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1013 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1014 /* adde adde. addeo addeo. */
1015 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1016 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1017 /* addme addme. addmeo addmeo. */
1018 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1019 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1020 /* addze addze. addzeo addzeo.*/
1021 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1022 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1023 /* addi */
1024 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1025 {
1026 target_long simm = SIMM(ctx->opcode);
1027
1028 if (rA(ctx->opcode) == 0) {
1029 /* li case */
1030 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1031 } else {
1032 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1033 }
1034 }
1035 /* addic addic.*/
1036 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1037 int compute_Rc0)
1038 {
1039 target_long simm = SIMM(ctx->opcode);
1040
1041 /* Start with XER CA and OV disabled, the most likely case */
1042 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1043
1044 if (likely(simm != 0)) {
1045 TCGv t0 = tcg_temp_local_new();
1046 tcg_gen_addi_tl(t0, arg1, simm);
1047 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1048 tcg_gen_mov_tl(ret, t0);
1049 tcg_temp_free(t0);
1050 } else {
1051 tcg_gen_mov_tl(ret, arg1);
1052 }
1053 if (compute_Rc0) {
1054 gen_set_Rc0(ctx, ret);
1055 }
1056 }
1057 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1058 {
1059 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1060 }
1061 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1062 {
1063 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1064 }
1065 /* addis */
1066 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1067 {
1068 target_long simm = SIMM(ctx->opcode);
1069
1070 if (rA(ctx->opcode) == 0) {
1071 /* lis case */
1072 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1073 } else {
1074 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1075 }
1076 }
1077
1078 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1079 int sign, int compute_ov)
1080 {
1081 int l1 = gen_new_label();
1082 int l2 = gen_new_label();
1083 TCGv_i32 t0 = tcg_temp_local_new_i32();
1084 TCGv_i32 t1 = tcg_temp_local_new_i32();
1085
1086 tcg_gen_trunc_tl_i32(t0, arg1);
1087 tcg_gen_trunc_tl_i32(t1, arg2);
1088 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1089 if (sign) {
1090 int l3 = gen_new_label();
1091 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1092 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1093 gen_set_label(l3);
1094 tcg_gen_div_i32(t0, t0, t1);
1095 } else {
1096 tcg_gen_divu_i32(t0, t0, t1);
1097 }
1098 if (compute_ov) {
1099 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1100 }
1101 tcg_gen_br(l2);
1102 gen_set_label(l1);
1103 if (sign) {
1104 tcg_gen_sari_i32(t0, t0, 31);
1105 } else {
1106 tcg_gen_movi_i32(t0, 0);
1107 }
1108 if (compute_ov) {
1109 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1110 }
1111 gen_set_label(l2);
1112 tcg_gen_extu_i32_tl(ret, t0);
1113 tcg_temp_free_i32(t0);
1114 tcg_temp_free_i32(t1);
1115 if (unlikely(Rc(ctx->opcode) != 0))
1116 gen_set_Rc0(ctx, ret);
1117 }
1118 /* Div functions */
1119 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1120 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1121 { \
1122 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1123 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1124 sign, compute_ov); \
1125 }
1126 /* divwu divwu. divwuo divwuo. */
1127 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1128 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1129 /* divw divw. divwo divwo. */
1130 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1131 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1132 #if defined(TARGET_PPC64)
1133 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1134 int sign, int compute_ov)
1135 {
1136 int l1 = gen_new_label();
1137 int l2 = gen_new_label();
1138
1139 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1140 if (sign) {
1141 int l3 = gen_new_label();
1142 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1143 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1144 gen_set_label(l3);
1145 tcg_gen_div_i64(ret, arg1, arg2);
1146 } else {
1147 tcg_gen_divu_i64(ret, arg1, arg2);
1148 }
1149 if (compute_ov) {
1150 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1151 }
1152 tcg_gen_br(l2);
1153 gen_set_label(l1);
1154 if (sign) {
1155 tcg_gen_sari_i64(ret, arg1, 63);
1156 } else {
1157 tcg_gen_movi_i64(ret, 0);
1158 }
1159 if (compute_ov) {
1160 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1161 }
1162 gen_set_label(l2);
1163 if (unlikely(Rc(ctx->opcode) != 0))
1164 gen_set_Rc0(ctx, ret);
1165 }
1166 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1167 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1168 { \
1169 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1170 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1171 sign, compute_ov); \
1172 }
1173 /* divwu divwu. divwuo divwuo. */
1174 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1175 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1176 /* divw divw. divwo divwo. */
1177 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1178 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1179 #endif
1180
1181 /* mulhw mulhw. */
1182 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1183 {
1184 TCGv_i64 t0, t1;
1185
1186 t0 = tcg_temp_new_i64();
1187 t1 = tcg_temp_new_i64();
1188 #if defined(TARGET_PPC64)
1189 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1190 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1191 tcg_gen_mul_i64(t0, t0, t1);
1192 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1193 #else
1194 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1195 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1196 tcg_gen_mul_i64(t0, t0, t1);
1197 tcg_gen_shri_i64(t0, t0, 32);
1198 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1199 #endif
1200 tcg_temp_free_i64(t0);
1201 tcg_temp_free_i64(t1);
1202 if (unlikely(Rc(ctx->opcode) != 0))
1203 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1204 }
1205 /* mulhwu mulhwu. */
1206 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1207 {
1208 TCGv_i64 t0, t1;
1209
1210 t0 = tcg_temp_new_i64();
1211 t1 = tcg_temp_new_i64();
1212 #if defined(TARGET_PPC64)
1213 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1214 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1215 tcg_gen_mul_i64(t0, t0, t1);
1216 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1217 #else
1218 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1219 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1220 tcg_gen_mul_i64(t0, t0, t1);
1221 tcg_gen_shri_i64(t0, t0, 32);
1222 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1223 #endif
1224 tcg_temp_free_i64(t0);
1225 tcg_temp_free_i64(t1);
1226 if (unlikely(Rc(ctx->opcode) != 0))
1227 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1228 }
1229 /* mullw mullw. */
1230 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1231 {
1232 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1233 cpu_gpr[rB(ctx->opcode)]);
1234 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1235 if (unlikely(Rc(ctx->opcode) != 0))
1236 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1237 }
1238 /* mullwo mullwo. */
1239 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1240 {
1241 int l1;
1242 TCGv_i64 t0, t1;
1243
1244 t0 = tcg_temp_new_i64();
1245 t1 = tcg_temp_new_i64();
1246 l1 = gen_new_label();
1247 /* Start with XER OV disabled, the most likely case */
1248 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1249 #if defined(TARGET_PPC64)
1250 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1251 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1252 #else
1253 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1254 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1255 #endif
1256 tcg_gen_mul_i64(t0, t0, t1);
1257 #if defined(TARGET_PPC64)
1258 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1259 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1260 #else
1261 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1262 tcg_gen_ext32s_i64(t1, t0);
1263 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1264 #endif
1265 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1266 gen_set_label(l1);
1267 tcg_temp_free_i64(t0);
1268 tcg_temp_free_i64(t1);
1269 if (unlikely(Rc(ctx->opcode) != 0))
1270 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1271 }
1272 /* mulli */
1273 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1274 {
1275 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1276 SIMM(ctx->opcode));
1277 }
1278 #if defined(TARGET_PPC64)
1279 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1280 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1281 { \
1282 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1283 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1284 if (unlikely(Rc(ctx->opcode) != 0)) \
1285 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1286 }
1287 /* mulhd mulhd. */
1288 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1289 /* mulhdu mulhdu. */
1290 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1291 /* mulld mulld. */
1292 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1293 {
1294 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1295 cpu_gpr[rB(ctx->opcode)]);
1296 if (unlikely(Rc(ctx->opcode) != 0))
1297 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1298 }
1299 /* mulldo mulldo. */
1300 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1301 #endif
1302
1303 /* neg neg. nego nego. */
1304 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1305 {
1306 int l1 = gen_new_label();
1307 int l2 = gen_new_label();
1308 TCGv t0 = tcg_temp_local_new();
1309 #if defined(TARGET_PPC64)
1310 if (ctx->sf_mode) {
1311 tcg_gen_mov_tl(t0, arg1);
1312 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1313 } else
1314 #endif
1315 {
1316 tcg_gen_ext32s_tl(t0, arg1);
1317 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1318 }
1319 tcg_gen_neg_tl(ret, arg1);
1320 if (ov_check) {
1321 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1322 }
1323 tcg_gen_br(l2);
1324 gen_set_label(l1);
1325 tcg_gen_mov_tl(ret, t0);
1326 if (ov_check) {
1327 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1328 }
1329 gen_set_label(l2);
1330 tcg_temp_free(t0);
1331 if (unlikely(Rc(ctx->opcode) != 0))
1332 gen_set_Rc0(ctx, ret);
1333 }
1334 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1335 {
1336 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1337 }
1338 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1339 {
1340 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1341 }
1342
1343 /* Common subf function */
1344 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1345 int add_ca, int compute_ca, int compute_ov)
1346 {
1347 TCGv t0, t1;
1348
1349 if ((!compute_ca && !compute_ov) ||
1350 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1351 t0 = ret;
1352 } else {
1353 t0 = tcg_temp_local_new();
1354 }
1355
1356 if (add_ca) {
1357 t1 = tcg_temp_local_new();
1358 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1359 tcg_gen_shri_tl(t1, t1, XER_CA);
1360 }
1361
1362 if (compute_ca && compute_ov) {
1363 /* Start with XER CA and OV disabled, the most likely case */
1364 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1365 } else if (compute_ca) {
1366 /* Start with XER CA disabled, the most likely case */
1367 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1368 } else if (compute_ov) {
1369 /* Start with XER OV disabled, the most likely case */
1370 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1371 }
1372
1373 if (add_ca) {
1374 tcg_gen_not_tl(t0, arg1);
1375 tcg_gen_add_tl(t0, t0, arg2);
1376 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1377 tcg_gen_add_tl(t0, t0, t1);
1378 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1379 tcg_temp_free(t1);
1380 } else {
1381 tcg_gen_sub_tl(t0, arg2, arg1);
1382 if (compute_ca) {
1383 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1384 }
1385 }
1386 if (compute_ov) {
1387 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1388 }
1389
1390 if (unlikely(Rc(ctx->opcode) != 0))
1391 gen_set_Rc0(ctx, t0);
1392
1393 if (!TCGV_EQUAL(t0, ret)) {
1394 tcg_gen_mov_tl(ret, t0);
1395 tcg_temp_free(t0);
1396 }
1397 }
1398 /* Sub functions with Two operands functions */
1399 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1400 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1401 { \
1402 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1403 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1404 add_ca, compute_ca, compute_ov); \
1405 }
1406 /* Sub functions with one operand and one immediate */
1407 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1408 add_ca, compute_ca, compute_ov) \
1409 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1410 { \
1411 TCGv t0 = tcg_const_local_tl(const_val); \
1412 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1413 cpu_gpr[rA(ctx->opcode)], t0, \
1414 add_ca, compute_ca, compute_ov); \
1415 tcg_temp_free(t0); \
1416 }
1417 /* subf subf. subfo subfo. */
1418 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1419 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1420 /* subfc subfc. subfco subfco. */
1421 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1422 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1423 /* subfe subfe. subfeo subfo. */
1424 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1425 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1426 /* subfme subfme. subfmeo subfmeo. */
1427 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1428 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1429 /* subfze subfze. subfzeo subfzeo.*/
1430 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1431 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1432 /* subfic */
1433 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1434 {
1435 /* Start with XER CA and OV disabled, the most likely case */
1436 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1437 TCGv t0 = tcg_temp_local_new();
1438 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1439 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1440 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1441 tcg_temp_free(t1);
1442 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1443 tcg_temp_free(t0);
1444 }
1445
1446 /*** Integer logical ***/
1447 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1448 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1449 { \
1450 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1451 cpu_gpr[rB(ctx->opcode)]); \
1452 if (unlikely(Rc(ctx->opcode) != 0)) \
1453 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1454 }
1455
1456 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1457 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1458 { \
1459 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1460 if (unlikely(Rc(ctx->opcode) != 0)) \
1461 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1462 }
1463
1464 /* and & and. */
1465 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1466 /* andc & andc. */
1467 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1468 /* andi. */
1469 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1470 {
1471 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1472 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1473 }
1474 /* andis. */
1475 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1476 {
1477 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1478 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1479 }
1480 /* cntlzw */
1481 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1482 {
1483 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1484 if (unlikely(Rc(ctx->opcode) != 0))
1485 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1486 }
1487 /* eqv & eqv. */
1488 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1489 /* extsb & extsb. */
1490 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1491 /* extsh & extsh. */
1492 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1493 /* nand & nand. */
1494 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1495 /* nor & nor. */
1496 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1497 /* or & or. */
1498 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1499 {
1500 int rs, ra, rb;
1501
1502 rs = rS(ctx->opcode);
1503 ra = rA(ctx->opcode);
1504 rb = rB(ctx->opcode);
1505 /* Optimisation for mr. ri case */
1506 if (rs != ra || rs != rb) {
1507 if (rs != rb)
1508 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1509 else
1510 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1511 if (unlikely(Rc(ctx->opcode) != 0))
1512 gen_set_Rc0(ctx, cpu_gpr[ra]);
1513 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1514 gen_set_Rc0(ctx, cpu_gpr[rs]);
1515 #if defined(TARGET_PPC64)
1516 } else {
1517 int prio = 0;
1518
1519 switch (rs) {
1520 case 1:
1521 /* Set process priority to low */
1522 prio = 2;
1523 break;
1524 case 6:
1525 /* Set process priority to medium-low */
1526 prio = 3;
1527 break;
1528 case 2:
1529 /* Set process priority to normal */
1530 prio = 4;
1531 break;
1532 #if !defined(CONFIG_USER_ONLY)
1533 case 31:
1534 if (ctx->supervisor > 0) {
1535 /* Set process priority to very low */
1536 prio = 1;
1537 }
1538 break;
1539 case 5:
1540 if (ctx->supervisor > 0) {
1541 /* Set process priority to medium-hight */
1542 prio = 5;
1543 }
1544 break;
1545 case 3:
1546 if (ctx->supervisor > 0) {
1547 /* Set process priority to high */
1548 prio = 6;
1549 }
1550 break;
1551 case 7:
1552 if (ctx->supervisor > 1) {
1553 /* Set process priority to very high */
1554 prio = 7;
1555 }
1556 break;
1557 #endif
1558 default:
1559 /* nop */
1560 break;
1561 }
1562 if (prio) {
1563 TCGv t0 = tcg_temp_new();
1564 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1565 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1566 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1567 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1568 tcg_temp_free(t0);
1569 }
1570 #endif
1571 }
1572 }
1573 /* orc & orc. */
1574 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1575 /* xor & xor. */
1576 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1577 {
1578 /* Optimisation for "set to zero" case */
1579 if (rS(ctx->opcode) != rB(ctx->opcode))
1580 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1581 else
1582 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1583 if (unlikely(Rc(ctx->opcode) != 0))
1584 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1585 }
1586 /* ori */
1587 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1588 {
1589 target_ulong uimm = UIMM(ctx->opcode);
1590
1591 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1592 /* NOP */
1593 /* XXX: should handle special NOPs for POWER series */
1594 return;
1595 }
1596 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1597 }
1598 /* oris */
1599 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1600 {
1601 target_ulong uimm = UIMM(ctx->opcode);
1602
1603 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1604 /* NOP */
1605 return;
1606 }
1607 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1608 }
1609 /* xori */
1610 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1611 {
1612 target_ulong uimm = UIMM(ctx->opcode);
1613
1614 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1615 /* NOP */
1616 return;
1617 }
1618 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1619 }
1620 /* xoris */
1621 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1622 {
1623 target_ulong uimm = UIMM(ctx->opcode);
1624
1625 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1626 /* NOP */
1627 return;
1628 }
1629 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1630 }
1631 /* popcntb : PowerPC 2.03 specification */
1632 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1633 {
1634 #if defined(TARGET_PPC64)
1635 if (ctx->sf_mode)
1636 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1637 else
1638 #endif
1639 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1640 }
1641
1642 #if defined(TARGET_PPC64)
1643 /* extsw & extsw. */
1644 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1645 /* cntlzd */
1646 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1647 {
1648 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1649 if (unlikely(Rc(ctx->opcode) != 0))
1650 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1651 }
1652 #endif
1653
1654 /*** Integer rotate ***/
1655 /* rlwimi & rlwimi. */
1656 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1657 {
1658 uint32_t mb, me, sh;
1659
1660 mb = MB(ctx->opcode);
1661 me = ME(ctx->opcode);
1662 sh = SH(ctx->opcode);
1663 if (likely(sh == 0 && mb == 0 && me == 31)) {
1664 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1665 } else {
1666 target_ulong mask;
1667 TCGv t1;
1668 TCGv t0 = tcg_temp_new();
1669 #if defined(TARGET_PPC64)
1670 TCGv_i32 t2 = tcg_temp_new_i32();
1671 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1672 tcg_gen_rotli_i32(t2, t2, sh);
1673 tcg_gen_extu_i32_i64(t0, t2);
1674 tcg_temp_free_i32(t2);
1675 #else
1676 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1677 #endif
1678 #if defined(TARGET_PPC64)
1679 mb += 32;
1680 me += 32;
1681 #endif
1682 mask = MASK(mb, me);
1683 t1 = tcg_temp_new();
1684 tcg_gen_andi_tl(t0, t0, mask);
1685 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1686 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1687 tcg_temp_free(t0);
1688 tcg_temp_free(t1);
1689 }
1690 if (unlikely(Rc(ctx->opcode) != 0))
1691 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1692 }
1693 /* rlwinm & rlwinm. */
1694 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1695 {
1696 uint32_t mb, me, sh;
1697
1698 sh = SH(ctx->opcode);
1699 mb = MB(ctx->opcode);
1700 me = ME(ctx->opcode);
1701
1702 if (likely(mb == 0 && me == (31 - sh))) {
1703 if (likely(sh == 0)) {
1704 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1705 } else {
1706 TCGv t0 = tcg_temp_new();
1707 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1708 tcg_gen_shli_tl(t0, t0, sh);
1709 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1710 tcg_temp_free(t0);
1711 }
1712 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1713 TCGv t0 = tcg_temp_new();
1714 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1715 tcg_gen_shri_tl(t0, t0, mb);
1716 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1717 tcg_temp_free(t0);
1718 } else {
1719 TCGv t0 = tcg_temp_new();
1720 #if defined(TARGET_PPC64)
1721 TCGv_i32 t1 = tcg_temp_new_i32();
1722 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1723 tcg_gen_rotli_i32(t1, t1, sh);
1724 tcg_gen_extu_i32_i64(t0, t1);
1725 tcg_temp_free_i32(t1);
1726 #else
1727 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1728 #endif
1729 #if defined(TARGET_PPC64)
1730 mb += 32;
1731 me += 32;
1732 #endif
1733 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1734 tcg_temp_free(t0);
1735 }
1736 if (unlikely(Rc(ctx->opcode) != 0))
1737 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1738 }
1739 /* rlwnm & rlwnm. */
1740 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1741 {
1742 uint32_t mb, me;
1743 TCGv t0;
1744 #if defined(TARGET_PPC64)
1745 TCGv_i32 t1, t2;
1746 #endif
1747
1748 mb = MB(ctx->opcode);
1749 me = ME(ctx->opcode);
1750 t0 = tcg_temp_new();
1751 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1752 #if defined(TARGET_PPC64)
1753 t1 = tcg_temp_new_i32();
1754 t2 = tcg_temp_new_i32();
1755 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1756 tcg_gen_trunc_i64_i32(t2, t0);
1757 tcg_gen_rotl_i32(t1, t1, t2);
1758 tcg_gen_extu_i32_i64(t0, t1);
1759 tcg_temp_free_i32(t1);
1760 tcg_temp_free_i32(t2);
1761 #else
1762 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1763 #endif
1764 if (unlikely(mb != 0 || me != 31)) {
1765 #if defined(TARGET_PPC64)
1766 mb += 32;
1767 me += 32;
1768 #endif
1769 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1770 } else {
1771 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1772 }
1773 tcg_temp_free(t0);
1774 if (unlikely(Rc(ctx->opcode) != 0))
1775 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1776 }
1777
1778 #if defined(TARGET_PPC64)
1779 #define GEN_PPC64_R2(name, opc1, opc2) \
1780 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1781 { \
1782 gen_##name(ctx, 0); \
1783 } \
1784 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1785 PPC_64B) \
1786 { \
1787 gen_##name(ctx, 1); \
1788 }
1789 #define GEN_PPC64_R4(name, opc1, opc2) \
1790 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1791 { \
1792 gen_##name(ctx, 0, 0); \
1793 } \
1794 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1795 PPC_64B) \
1796 { \
1797 gen_##name(ctx, 0, 1); \
1798 } \
1799 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1800 PPC_64B) \
1801 { \
1802 gen_##name(ctx, 1, 0); \
1803 } \
1804 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1805 PPC_64B) \
1806 { \
1807 gen_##name(ctx, 1, 1); \
1808 }
1809
1810 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1811 uint32_t me, uint32_t sh)
1812 {
1813 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1814 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1815 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1816 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1817 } else {
1818 TCGv t0 = tcg_temp_new();
1819 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1820 if (likely(mb == 0 && me == 63)) {
1821 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1822 } else {
1823 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1824 }
1825 tcg_temp_free(t0);
1826 }
1827 if (unlikely(Rc(ctx->opcode) != 0))
1828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1829 }
1830 /* rldicl - rldicl. */
1831 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1832 {
1833 uint32_t sh, mb;
1834
1835 sh = SH(ctx->opcode) | (shn << 5);
1836 mb = MB(ctx->opcode) | (mbn << 5);
1837 gen_rldinm(ctx, mb, 63, sh);
1838 }
1839 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1840 /* rldicr - rldicr. */
1841 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1842 {
1843 uint32_t sh, me;
1844
1845 sh = SH(ctx->opcode) | (shn << 5);
1846 me = MB(ctx->opcode) | (men << 5);
1847 gen_rldinm(ctx, 0, me, sh);
1848 }
1849 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1850 /* rldic - rldic. */
1851 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1852 {
1853 uint32_t sh, mb;
1854
1855 sh = SH(ctx->opcode) | (shn << 5);
1856 mb = MB(ctx->opcode) | (mbn << 5);
1857 gen_rldinm(ctx, mb, 63 - sh, sh);
1858 }
1859 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1860
1861 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1862 uint32_t me)
1863 {
1864 TCGv t0;
1865
1866 mb = MB(ctx->opcode);
1867 me = ME(ctx->opcode);
1868 t0 = tcg_temp_new();
1869 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1870 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1871 if (unlikely(mb != 0 || me != 63)) {
1872 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1873 } else {
1874 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1875 }
1876 tcg_temp_free(t0);
1877 if (unlikely(Rc(ctx->opcode) != 0))
1878 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1879 }
1880
1881 /* rldcl - rldcl. */
1882 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1883 {
1884 uint32_t mb;
1885
1886 mb = MB(ctx->opcode) | (mbn << 5);
1887 gen_rldnm(ctx, mb, 63);
1888 }
1889 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1890 /* rldcr - rldcr. */
1891 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1892 {
1893 uint32_t me;
1894
1895 me = MB(ctx->opcode) | (men << 5);
1896 gen_rldnm(ctx, 0, me);
1897 }
1898 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1899 /* rldimi - rldimi. */
1900 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1901 {
1902 uint32_t sh, mb, me;
1903
1904 sh = SH(ctx->opcode) | (shn << 5);
1905 mb = MB(ctx->opcode) | (mbn << 5);
1906 me = 63 - sh;
1907 if (unlikely(sh == 0 && mb == 0)) {
1908 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1909 } else {
1910 TCGv t0, t1;
1911 target_ulong mask;
1912
1913 t0 = tcg_temp_new();
1914 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1915 t1 = tcg_temp_new();
1916 mask = MASK(mb, me);
1917 tcg_gen_andi_tl(t0, t0, mask);
1918 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1919 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1920 tcg_temp_free(t0);
1921 tcg_temp_free(t1);
1922 }
1923 if (unlikely(Rc(ctx->opcode) != 0))
1924 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1925 }
1926 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1927 #endif
1928
1929 /*** Integer shift ***/
1930 /* slw & slw. */
1931 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1932 {
1933 TCGv t0;
1934 int l1, l2;
1935 l1 = gen_new_label();
1936 l2 = gen_new_label();
1937
1938 t0 = tcg_temp_local_new();
1939 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1940 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1941 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1942 tcg_gen_br(l2);
1943 gen_set_label(l1);
1944 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1945 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1946 gen_set_label(l2);
1947 tcg_temp_free(t0);
1948 if (unlikely(Rc(ctx->opcode) != 0))
1949 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1950 }
1951 /* sraw & sraw. */
1952 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1953 {
1954 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1955 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1956 if (unlikely(Rc(ctx->opcode) != 0))
1957 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1958 }
1959 /* srawi & srawi. */
1960 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1961 {
1962 int sh = SH(ctx->opcode);
1963 if (sh != 0) {
1964 int l1, l2;
1965 TCGv t0;
1966 l1 = gen_new_label();
1967 l2 = gen_new_label();
1968 t0 = tcg_temp_local_new();
1969 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1970 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1971 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1972 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1973 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1974 tcg_gen_br(l2);
1975 gen_set_label(l1);
1976 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1977 gen_set_label(l2);
1978 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1979 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1980 tcg_temp_free(t0);
1981 } else {
1982 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1983 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1984 }
1985 if (unlikely(Rc(ctx->opcode) != 0))
1986 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1987 }
1988 /* srw & srw. */
1989 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1990 {
1991 TCGv t0, t1;
1992 int l1, l2;
1993 l1 = gen_new_label();
1994 l2 = gen_new_label();
1995
1996 t0 = tcg_temp_local_new();
1997 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1998 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1999 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2000 tcg_gen_br(l2);
2001 gen_set_label(l1);
2002 t1 = tcg_temp_new();
2003 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
2004 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
2005 tcg_temp_free(t1);
2006 gen_set_label(l2);
2007 tcg_temp_free(t0);
2008 if (unlikely(Rc(ctx->opcode) != 0))
2009 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2010 }
2011 #if defined(TARGET_PPC64)
2012 /* sld & sld. */
2013 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2014 {
2015 TCGv t0;
2016 int l1, l2;
2017 l1 = gen_new_label();
2018 l2 = gen_new_label();
2019
2020 t0 = tcg_temp_local_new();
2021 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2022 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2023 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2024 tcg_gen_br(l2);
2025 gen_set_label(l1);
2026 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2027 gen_set_label(l2);
2028 tcg_temp_free(t0);
2029 if (unlikely(Rc(ctx->opcode) != 0))
2030 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2031 }
2032 /* srad & srad. */
2033 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2034 {
2035 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2036 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2037 if (unlikely(Rc(ctx->opcode) != 0))
2038 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2039 }
2040 /* sradi & sradi. */
2041 static always_inline void gen_sradi (DisasContext *ctx, int n)
2042 {
2043 int sh = SH(ctx->opcode) + (n << 5);
2044 if (sh != 0) {
2045 int l1, l2;
2046 TCGv t0;
2047 l1 = gen_new_label();
2048 l2 = gen_new_label();
2049 t0 = tcg_temp_local_new();
2050 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2051 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2052 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2053 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2054 tcg_gen_br(l2);
2055 gen_set_label(l1);
2056 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2057 gen_set_label(l2);
2058 tcg_temp_free(t0);
2059 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2060 } else {
2061 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2062 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2063 }
2064 if (unlikely(Rc(ctx->opcode) != 0))
2065 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2066 }
2067 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2068 {
2069 gen_sradi(ctx, 0);
2070 }
2071 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2072 {
2073 gen_sradi(ctx, 1);
2074 }
2075 /* srd & srd. */
2076 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2077 {
2078 TCGv t0;
2079 int l1, l2;
2080 l1 = gen_new_label();
2081 l2 = gen_new_label();
2082
2083 t0 = tcg_temp_local_new();
2084 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2085 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2086 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2087 tcg_gen_br(l2);
2088 gen_set_label(l1);
2089 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2090 gen_set_label(l2);
2091 tcg_temp_free(t0);
2092 if (unlikely(Rc(ctx->opcode) != 0))
2093 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2094 }
2095 #endif
2096
2097 /*** Floating-Point arithmetic ***/
2098 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2099 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2100 { \
2101 if (unlikely(!ctx->fpu_enabled)) { \
2102 GEN_EXCP_NO_FP(ctx); \
2103 return; \
2104 } \
2105 gen_reset_fpstatus(); \
2106 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2107 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2108 if (isfloat) { \
2109 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2110 } \
2111 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2112 Rc(ctx->opcode) != 0); \
2113 }
2114
2115 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2116 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2117 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2118
2119 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2120 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2121 { \
2122 if (unlikely(!ctx->fpu_enabled)) { \
2123 GEN_EXCP_NO_FP(ctx); \
2124 return; \
2125 } \
2126 gen_reset_fpstatus(); \
2127 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2128 cpu_fpr[rB(ctx->opcode)]); \
2129 if (isfloat) { \
2130 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2131 } \
2132 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2133 set_fprf, Rc(ctx->opcode) != 0); \
2134 }
2135 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2136 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2137 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2138
2139 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2140 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2141 { \
2142 if (unlikely(!ctx->fpu_enabled)) { \
2143 GEN_EXCP_NO_FP(ctx); \
2144 return; \
2145 } \
2146 gen_reset_fpstatus(); \
2147 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2148 cpu_fpr[rC(ctx->opcode)]); \
2149 if (isfloat) { \
2150 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2151 } \
2152 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2153 set_fprf, Rc(ctx->opcode) != 0); \
2154 }
2155 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2156 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2157 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2158
2159 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2160 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2161 { \
2162 if (unlikely(!ctx->fpu_enabled)) { \
2163 GEN_EXCP_NO_FP(ctx); \
2164 return; \
2165 } \
2166 gen_reset_fpstatus(); \
2167 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2168 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2169 set_fprf, Rc(ctx->opcode) != 0); \
2170 }
2171
2172 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2173 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2174 { \
2175 if (unlikely(!ctx->fpu_enabled)) { \
2176 GEN_EXCP_NO_FP(ctx); \
2177 return; \
2178 } \
2179 gen_reset_fpstatus(); \
2180 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2181 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2182 set_fprf, Rc(ctx->opcode) != 0); \
2183 }
2184
2185 /* fadd - fadds */
2186 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2187 /* fdiv - fdivs */
2188 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2189 /* fmul - fmuls */
2190 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2191
2192 /* fre */
2193 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2194
2195 /* fres */
2196 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2197
2198 /* frsqrte */
2199 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2200
2201 /* frsqrtes */
2202 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2203 {
2204 if (unlikely(!ctx->fpu_enabled)) {
2205 GEN_EXCP_NO_FP(ctx);
2206 return;
2207 }
2208 gen_reset_fpstatus();
2209 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2210 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2211 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2212 }
2213
2214 /* fsel */
2215 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2216 /* fsub - fsubs */
2217 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2218 /* Optional: */
2219 /* fsqrt */
2220 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2221 {
2222 if (unlikely(!ctx->fpu_enabled)) {
2223 GEN_EXCP_NO_FP(ctx);
2224 return;
2225 }
2226 gen_reset_fpstatus();
2227 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2228 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2229 }
2230
2231 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2232 {
2233 if (unlikely(!ctx->fpu_enabled)) {
2234 GEN_EXCP_NO_FP(ctx);
2235 return;
2236 }
2237 gen_reset_fpstatus();
2238 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2239 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2240 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2241 }
2242
2243 /*** Floating-Point multiply-and-add ***/
2244 /* fmadd - fmadds */
2245 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2246 /* fmsub - fmsubs */
2247 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2248 /* fnmadd - fnmadds */
2249 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2250 /* fnmsub - fnmsubs */
2251 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2252
2253 /*** Floating-Point round & convert ***/
2254 /* fctiw */
2255 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2256 /* fctiwz */
2257 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2258 /* frsp */
2259 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2260 #if defined(TARGET_PPC64)
2261 /* fcfid */
2262 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2263 /* fctid */
2264 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2265 /* fctidz */
2266 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2267 #endif
2268
2269 /* frin */
2270 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2271 /* friz */
2272 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2273 /* frip */
2274 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2275 /* frim */
2276 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2277
2278 /*** Floating-Point compare ***/
2279 /* fcmpo */
2280 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2281 {
2282 if (unlikely(!ctx->fpu_enabled)) {
2283 GEN_EXCP_NO_FP(ctx);
2284 return;
2285 }
2286 gen_reset_fpstatus();
2287 gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
2288 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2289 gen_helper_float_check_status();
2290 }
2291
2292 /* fcmpu */
2293 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2294 {
2295 if (unlikely(!ctx->fpu_enabled)) {
2296 GEN_EXCP_NO_FP(ctx);
2297 return;
2298 }
2299 gen_reset_fpstatus();
2300 gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
2301 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2302 gen_helper_float_check_status();
2303 }
2304
2305 /*** Floating-point move ***/
2306 /* fabs */
2307 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2308 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2309
2310 /* fmr - fmr. */
2311 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2312 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2313 {
2314 if (unlikely(!ctx->fpu_enabled)) {
2315 GEN_EXCP_NO_FP(ctx);
2316 return;
2317 }
2318 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2319 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2320 }
2321
2322 /* fnabs */
2323 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2324 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2325 /* fneg */
2326 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2327 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2328
2329 /*** Floating-Point status & ctrl register ***/
2330 /* mcrfs */
2331 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2332 {
2333 int bfa;
2334
2335 if (unlikely(!ctx->fpu_enabled)) {
2336 GEN_EXCP_NO_FP(ctx);
2337 return;
2338 }
2339 gen_optimize_fprf();
2340 bfa = 4 * (7 - crfS(ctx->opcode));
2341 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2342 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2343 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2344 }
2345
2346 /* mffs */
2347 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2348 {
2349 if (unlikely(!ctx->fpu_enabled)) {
2350 GEN_EXCP_NO_FP(ctx);
2351 return;
2352 }
2353 gen_optimize_fprf();
2354 gen_reset_fpstatus();
2355 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2356 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2357 }
2358
2359 /* mtfsb0 */
2360 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2361 {
2362 uint8_t crb;
2363
2364 if (unlikely(!ctx->fpu_enabled)) {
2365 GEN_EXCP_NO_FP(ctx);
2366 return;
2367 }
2368 crb = 32 - (crbD(ctx->opcode) >> 2);
2369 gen_optimize_fprf();
2370 gen_reset_fpstatus();
2371 if (likely(crb != 30 && crb != 29))
2372 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
2373 if (unlikely(Rc(ctx->opcode) != 0)) {
2374 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2375 }
2376 }
2377
2378 /* mtfsb1 */
2379 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2380 {
2381 uint8_t crb;
2382
2383 if (unlikely(!ctx->fpu_enabled)) {
2384 GEN_EXCP_NO_FP(ctx);
2385 return;
2386 }
2387 crb = 32 - (crbD(ctx->opcode) >> 2);
2388 gen_optimize_fprf();
2389 gen_reset_fpstatus();
2390 /* XXX: we pretend we can only do IEEE floating-point computations */
2391 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2392 TCGv_i32 t0 = tcg_const_i32(crb);
2393 gen_helper_fpscr_setbit(t0);
2394 tcg_temp_free_i32(t0);
2395 }
2396 if (unlikely(Rc(ctx->opcode) != 0)) {
2397 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2398 }
2399 /* We can raise a differed exception */
2400 gen_helper_float_check_status();
2401 }
2402
2403 /* mtfsf */
2404 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2405 {
2406 TCGv_i32 t0;
2407
2408 if (unlikely(!ctx->fpu_enabled)) {
2409 GEN_EXCP_NO_FP(ctx);
2410 return;
2411 }
2412 gen_optimize_fprf();
2413 gen_reset_fpstatus();
2414 t0 = tcg_const_i32(FM(ctx->opcode));
2415 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2416 tcg_temp_free_i32(t0);
2417 if (unlikely(Rc(ctx->opcode) != 0)) {
2418 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2419 }
2420 /* We can raise a differed exception */
2421 gen_helper_float_check_status();
2422 }
2423
2424 /* mtfsfi */
2425 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2426 {
2427 int bf, sh;
2428 TCGv_i64 t0;
2429 TCGv_i32 t1;
2430
2431 if (unlikely(!ctx->fpu_enabled)) {
2432 GEN_EXCP_NO_FP(ctx);
2433 return;
2434 }
2435 bf = crbD(ctx->opcode) >> 2;
2436 sh = 7 - bf;
2437 gen_optimize_fprf();
2438 gen_reset_fpstatus();
2439 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2440 t1 = tcg_const_i32(1 << sh);
2441 gen_helper_store_fpscr(t0, t1);
2442 tcg_temp_free_i64(t0);
2443 tcg_temp_free_i32(t1);
2444 if (unlikely(Rc(ctx->opcode) != 0)) {
2445 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2446 }
2447 /* We can raise a differed exception */
2448 gen_helper_float_check_status();
2449 }
2450
2451 /*** Addressing modes ***/
2452 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2453 static always_inline void gen_addr_imm_index (TCGv EA,
2454 DisasContext *ctx,
2455 target_long maskl)
2456 {
2457 target_long simm = SIMM(ctx->opcode);
2458
2459 simm &= ~maskl;
2460 if (rA(ctx->opcode) == 0)
2461 tcg_gen_movi_tl(EA, simm);
2462 else if (likely(simm != 0))
2463 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2464 else
2465 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2466 }
2467
2468 static always_inline void gen_addr_reg_index (TCGv EA,
2469 DisasContext *ctx)
2470 {
2471 if (rA(ctx->opcode) == 0)
2472 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2473 else
2474 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2475 }
2476
2477 static always_inline void gen_addr_register (TCGv EA,
2478 DisasContext *ctx)
2479 {
2480 if (rA(ctx->opcode) == 0)
2481 tcg_gen_movi_tl(EA, 0);
2482 else
2483 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2484 }
2485
2486 #if defined(TARGET_PPC64)
2487 #define _GEN_MEM_FUNCS(name, mode) \
2488 &gen_op_##name##_##mode, \
2489 &gen_op_##name##_le_##mode, \
2490 &gen_op_##name##_64_##mode, \
2491 &gen_op_##name##_le_64_##mode
2492 #else
2493 #define _GEN_MEM_FUNCS(name, mode) \
2494 &gen_op_##name##_##mode, \
2495 &gen_op_##name##_le_##mode
2496 #endif
2497 #if defined(CONFIG_USER_ONLY)
2498 #if defined(TARGET_PPC64)
2499 #define NB_MEM_FUNCS 4
2500 #else
2501 #define NB_MEM_FUNCS 2
2502 #endif
2503 #define GEN_MEM_FUNCS(name) \
2504 _GEN_MEM_FUNCS(name, raw)
2505 #else
2506 #if defined(TARGET_PPC64)
2507 #define NB_MEM_FUNCS 12
2508 #else
2509 #define NB_MEM_FUNCS 6
2510 #endif
2511 #define GEN_MEM_FUNCS(name) \
2512 _GEN_MEM_FUNCS(name, user), \
2513 _GEN_MEM_FUNCS(name, kernel), \
2514 _GEN_MEM_FUNCS(name, hypv)
2515 #endif
2516
2517 /*** Integer load ***/
2518 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
2519 #define OP_LD_TABLE(width) \
2520 static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2521 GEN_MEM_FUNCS(l##width), \
2522 };
2523 #define OP_ST_TABLE(width) \
2524 static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2525 GEN_MEM_FUNCS(st##width), \
2526 };
2527
2528
2529 #if defined(TARGET_PPC64)
2530 #define GEN_QEMU_LD_PPC64(width) \
2531 static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2532 { \
2533 if (likely(flags & 2)) \
2534 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2535 else { \
2536 TCGv addr = tcg_temp_new(); \
2537 tcg_gen_ext32u_tl(addr, t1); \
2538 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2539 tcg_temp_free(addr); \
2540 } \
2541 }
2542 GEN_QEMU_LD_PPC64(8u)
2543 GEN_QEMU_LD_PPC64(8s)
2544 GEN_QEMU_LD_PPC64(16u)
2545 GEN_QEMU_LD_PPC64(16s)
2546 GEN_QEMU_LD_PPC64(32u)
2547 GEN_QEMU_LD_PPC64(32s)
2548 GEN_QEMU_LD_PPC64(64)
2549
2550 #define GEN_QEMU_ST_PPC64(width) \
2551 static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2552 { \
2553 if (likely(flags & 2)) \
2554 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2555 else { \
2556 TCGv addr = tcg_temp_new(); \
2557 tcg_gen_ext32u_tl(addr, t1); \
2558 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2559 tcg_temp_free(addr); \
2560 } \
2561 }
2562 GEN_QEMU_ST_PPC64(8)
2563 GEN_QEMU_ST_PPC64(16)
2564 GEN_QEMU_ST_PPC64(32)
2565 GEN_QEMU_ST_PPC64(64)
2566
2567 static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
2568 {
2569 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
2570 }
2571
2572 static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
2573 {
2574 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
2575 }
2576
2577 static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
2578 {
2579 if (unlikely(flags & 1)) {
2580 TCGv_i32 t0;
2581 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2582 t0 = tcg_temp_new_i32();
2583 tcg_gen_trunc_tl_i32(t0, arg0);
2584 tcg_gen_bswap16_i32(t0, t0);
2585 tcg_gen_extu_i32_tl(arg0, t0);
2586 tcg_temp_free_i32(t0);
2587 } else
2588 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2589 }
2590
2591 static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
2592 {
2593 if (unlikely(flags & 1)) {
2594 TCGv_i32 t0;
2595 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2596 t0 = tcg_temp_new_i32();
2597 tcg_gen_trunc_tl_i32(t0, arg0);
2598 tcg_gen_bswap16_i32(t0, t0);
2599 tcg_gen_extu_i32_tl(arg0, t0);
2600 tcg_gen_ext16s_tl(arg0, arg0);
2601 tcg_temp_free_i32(t0);
2602 } else
2603 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
2604 }
2605
2606 static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
2607 {
2608 if (unlikely(flags & 1)) {
2609 TCGv_i32 t0;
2610 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2611 t0 = tcg_temp_new_i32();
2612 tcg_gen_trunc_tl_i32(t0, arg0);
2613 tcg_gen_bswap_i32(t0, t0);
2614 tcg_gen_extu_i32_tl(arg0, t0);
2615 tcg_temp_free_i32(t0);
2616 } else
2617 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2618 }
2619
2620 static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
2621 {
2622 if (unlikely(flags & 1)) {
2623 TCGv_i32 t0;
2624 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2625 t0 = tcg_temp_new_i32();
2626 tcg_gen_trunc_tl_i32(t0, arg0);
2627 tcg_gen_bswap_i32(t0, t0);
2628 tcg_gen_ext_i32_tl(arg0, t0);
2629 tcg_temp_free_i32(t0);
2630 } else
2631 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
2632 }
2633
2634 static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
2635 {
2636 gen_qemu_ld64_ppc64(arg0, arg1, flags);
2637 if (unlikely(flags & 1))
2638 tcg_gen_bswap_i64(arg0, arg0);
2639 }
2640
2641 static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
2642 {
2643 gen_qemu_st8_ppc64(arg0, arg1, flags);
2644 }
2645
2646 static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
2647 {
2648 if (unlikely(flags & 1)) {
2649 TCGv_i32 t0;
2650 TCGv_i64 t1;
2651 t0 = tcg_temp_new_i32();
2652 tcg_gen_trunc_tl_i32(t0, arg0);
2653 tcg_gen_ext16u_i32(t0, t0);
2654 tcg_gen_bswap16_i32(t0, t0);
2655 t1 = tcg_temp_new_i64();
2656 tcg_gen_extu_i32_tl(t1, t0);
2657 tcg_temp_free_i32(t0);
2658 gen_qemu_st16_ppc64(t1, arg1, flags);
2659 tcg_temp_free_i64(t1);
2660 } else
2661 gen_qemu_st16_ppc64(arg0, arg1, flags);
2662 }
2663
2664 static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2665 {
2666 if (unlikely(flags & 1)) {
2667 TCGv_i32 t0;
2668 TCGv_i64 t1;
2669 t0 = tcg_temp_new_i32();
2670 tcg_gen_trunc_tl_i32(t0, arg0);
2671 tcg_gen_bswap_i32(t0, t0);
2672 t1 = tcg_temp_new_i64();
2673 tcg_gen_extu_i32_tl(t1, t0);
2674 tcg_temp_free_i32(t0);
2675 gen_qemu_st32_ppc64(t1, arg1, flags);
2676 tcg_temp_free_i64(t1);
2677 } else
2678 gen_qemu_st32_ppc64(arg0, arg1, flags);
2679 }
2680
2681 static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
2682 {
2683 if (unlikely(flags & 1)) {
2684 TCGv_i64 t0 = tcg_temp_new_i64();
2685 tcg_gen_bswap_i64(t0, arg0);
2686 gen_qemu_st64_ppc64(t0, arg1, flags);
2687 tcg_temp_free_i64(t0);
2688 } else
2689 gen_qemu_st64_ppc64(arg0, arg1, flags);
2690 }
2691
2692
2693 #else /* defined(TARGET_PPC64) */
2694 #define GEN_QEMU_LD_PPC32(width) \
2695 static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
2696 { \
2697 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
2698 }
2699 GEN_QEMU_LD_PPC32(8u)
2700 GEN_QEMU_LD_PPC32(8s)
2701 GEN_QEMU_LD_PPC32(16u)
2702 GEN_QEMU_LD_PPC32(16s)
2703 GEN_QEMU_LD_PPC32(32u)
2704 GEN_QEMU_LD_PPC32(32s)
2705
2706 #define GEN_QEMU_ST_PPC32(width) \
2707 static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
2708 { \
2709 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
2710 }
2711 GEN_QEMU_ST_PPC32(8)
2712 GEN_QEMU_ST_PPC32(16)
2713 GEN_QEMU_ST_PPC32(32)
2714
2715 static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
2716 {
2717 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
2718 }
2719
2720 static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
2721 {
2722 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
2723 }
2724
2725 static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
2726 {
2727 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
2728 if (unlikely(flags & 1))
2729 tcg_gen_bswap16_i32(arg0, arg0);
2730 }
2731
2732 static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
2733 {
2734 if (unlikely(flags & 1)) {
2735 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2736 tcg_gen_bswap16_i32(arg0, arg0);
2737 tcg_gen_ext16s_i32(arg0, arg0);
2738 } else
2739 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
2740 }
2741
2742 static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
2743 {
2744 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
2745 if (unlikely(flags & 1))
2746 tcg_gen_bswap_i32(arg0, arg0);
2747 }
2748
2749 static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
2750 {
2751 gen_qemu_st8_ppc32(arg0, arg1, flags);
2752 }
2753
2754 static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
2755 {
2756 if (unlikely(flags & 1)) {
2757 TCGv_i32 temp = tcg_temp_new_i32();
2758 tcg_gen_ext16u_i32(temp, arg0);
2759 tcg_gen_bswap16_i32(temp, temp);
2760 gen_qemu_st16_ppc32(temp, arg1, flags);
2761 tcg_temp_free_i32(temp);
2762 } else
2763 gen_qemu_st16_ppc32(arg0, arg1, flags);
2764 }
2765
2766 static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2767 {
2768 if (unlikely(flags & 1)) {
2769 TCGv_i32 temp = tcg_temp_new_i32();
2770 tcg_gen_bswap_i32(temp, arg0);
2771 gen_qemu_st32_ppc32(temp, arg1, flags);
2772 tcg_temp_free_i32(temp);
2773 } else
2774 gen_qemu_st32_ppc32(arg0, arg1, flags);
2775 }
2776
2777 #endif
2778
2779 #define GEN_LD(width, opc, type) \
2780 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2781 { \
2782 TCGv EA = tcg_temp_new(); \
2783 gen_addr_imm_index(EA, ctx, 0); \
2784 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2785 tcg_temp_free(EA); \
2786 }
2787
2788 #define GEN_LDU(width, opc, type) \
2789 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2790 { \
2791 TCGv EA; \
2792 if (unlikely(rA(ctx->opcode) == 0 || \
2793 rA(ctx->opcode) == rD(ctx->opcode))) { \
2794 GEN_EXCP_INVAL(ctx); \
2795 return; \
2796 } \
2797 EA = tcg_temp_new(); \
2798 if (type == PPC_64B) \
2799 gen_addr_imm_index(EA, ctx, 0x03); \
2800 else \
2801 gen_addr_imm_index(EA, ctx, 0); \
2802 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2803 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2804 tcg_temp_free(EA); \
2805 }
2806
2807 #define GEN_LDUX(width, opc2, opc3, type) \
2808 GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2809 { \
2810 TCGv EA; \
2811 if (unlikely(rA(ctx->opcode) == 0 || \
2812 rA(ctx->opcode) == rD(ctx->opcode))) { \
2813 GEN_EXCP_INVAL(ctx); \
2814 return; \
2815 } \
2816 EA = tcg_temp_new(); \
2817 gen_addr_reg_index(EA, ctx); \
2818 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2819 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2820 tcg_temp_free(EA); \
2821 }
2822
2823 #define GEN_LDX(width, opc2, opc3, type) \
2824 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2825 { \
2826 TCGv EA = tcg_temp_new(); \
2827 gen_addr_reg_index(EA, ctx); \
2828 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2829 tcg_temp_free(EA); \
2830 }
2831
2832 #define GEN_LDS(width, op, type) \
2833 GEN_LD(width, op | 0x20, type); \
2834 GEN_LDU(width, op | 0x21, type); \
2835 GEN_LDUX(width, 0x17, op | 0x01, type); \
2836 GEN_LDX(width, 0x17, op | 0x00, type)
2837
2838 /* lbz lbzu lbzux lbzx */
2839 GEN_LDS(8u, 0x02, PPC_INTEGER);
2840 /* lha lhau lhaux lhax */
2841 GEN_LDS(16s, 0x0A, PPC_INTEGER);
2842 /* lhz lhzu lhzux lhzx */
2843 GEN_LDS(16u, 0x08, PPC_INTEGER);
2844 /* lwz lwzu lwzux lwzx */
2845 GEN_LDS(32u, 0x00, PPC_INTEGER);
2846 #if defined(TARGET_PPC64)
2847 /* lwaux */
2848 GEN_LDUX(32s, 0x15, 0x0B, PPC_64B);
2849 /* lwax */
2850 GEN_LDX(32s, 0x15, 0x0A, PPC_64B);
2851 /* ldux */
2852 GEN_LDUX(64, 0x15, 0x01, PPC_64B);
2853 /* ldx */
2854 GEN_LDX(64, 0x15, 0x00, PPC_64B);
2855 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2856 {
2857 TCGv EA;
2858 if (Rc(ctx->opcode)) {
2859 if (unlikely(rA(ctx->opcode) == 0 ||
2860 rA(ctx->opcode) == rD(ctx->opcode))) {
2861 GEN_EXCP_INVAL(ctx);
2862 return;
2863 }
2864 }
2865 EA = tcg_temp_new();
2866 gen_addr_imm_index(EA, ctx, 0x03);
2867 if (ctx->opcode & 0x02) {
2868 /* lwa (lwau is undefined) */
2869 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
2870 } else {
2871 /* ld - ldu */
2872 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
2873 }
2874 if (Rc(ctx->opcode))
2875 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2876 tcg_temp_free(EA);
2877 }
2878 /* lq */
2879 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2880 {
2881 #if defined(CONFIG_USER_ONLY)
2882 GEN_EXCP_PRIVOPC(ctx);
2883 #else
2884 int ra, rd;
2885 TCGv EA;
2886
2887 /* Restore CPU state */
2888 if (unlikely(ctx->supervisor == 0)) {
2889 GEN_EXCP_PRIVOPC(ctx);
2890 return;
2891 }
2892 ra = rA(ctx->opcode);
2893 rd = rD(ctx->opcode);
2894 if (unlikely((rd & 1) || rd == ra)) {
2895 GEN_EXCP_INVAL(ctx);
2896 return;
2897 }
2898 if (unlikely(ctx->mem_idx & 1)) {
2899 /* Little-endian mode is not handled */
2900 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2901 return;
2902 }
2903 EA = tcg_temp_new();
2904 gen_addr_imm_index(EA, ctx, 0x0F);
2905 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2906 tcg_gen_addi_tl(EA, EA, 8);
2907 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2908 tcg_temp_free(EA);
2909 #endif
2910 }
2911 #endif
2912
2913 /*** Integer store ***/
2914 #define GEN_ST(width, opc, type) \
2915 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2916 { \
2917 TCGv EA = tcg_temp_new(); \
2918 gen_addr_imm_index(EA, ctx, 0); \
2919 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2920 tcg_temp_free(EA); \
2921 }
2922
2923 #define GEN_STU(width, opc, type) \
2924 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2925 { \
2926 TCGv EA; \
2927 if (unlikely(rA(ctx->opcode) == 0)) { \
2928 GEN_EXCP_INVAL(ctx); \
2929 return; \
2930 } \
2931 EA = tcg_temp_new(); \
2932 if (type == PPC_64B) \
2933 gen_addr_imm_index(EA, ctx, 0x03); \
2934 else \
2935 gen_addr_imm_index(EA, ctx, 0); \
2936 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2937 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2938 tcg_temp_free(EA); \
2939 }
2940
2941 #define GEN_STUX(width, opc2, opc3, type) \
2942 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2943 { \
2944 TCGv EA; \
2945 if (unlikely(rA(ctx->opcode) == 0)) { \
2946 GEN_EXCP_INVAL(ctx); \
2947 return; \
2948 } \
2949 EA = tcg_temp_new(); \
2950 gen_addr_reg_index(EA, ctx); \
2951 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2952 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2953 tcg_temp_free(EA); \
2954 }
2955
2956 #define GEN_STX(width, opc2, opc3, type) \
2957 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2958 { \
2959 TCGv EA = tcg_temp_new(); \
2960 gen_addr_reg_index(EA, ctx); \
2961 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2962 tcg_temp_free(EA); \
2963 }
2964
2965 #define GEN_STS(width, op, type) \
2966 GEN_ST(width, op | 0x20, type); \
2967 GEN_STU(width, op | 0x21, type); \
2968 GEN_STUX(width, 0x17, op | 0x01, type); \
2969 GEN_STX(width, 0x17, op | 0x00, type)
2970
2971 /* stb stbu stbux stbx */
2972 GEN_STS(8, 0x06, PPC_INTEGER);
2973 /* sth sthu sthux sthx */
2974 GEN_STS(16, 0x0C, PPC_INTEGER);
2975 /* stw stwu stwux stwx */
2976 GEN_STS(32, 0x04, PPC_INTEGER);
2977 #if defined(TARGET_PPC64)
2978 GEN_STUX(64, 0x15, 0x05, PPC_64B);
2979 GEN_STX(64, 0x15, 0x04, PPC_64B);
2980 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2981 {
2982 int rs;
2983 TCGv EA;
2984
2985 rs = rS(ctx->opcode);
2986 if ((ctx->opcode & 0x3) == 0x2) {
2987 #if defined(CONFIG_USER_ONLY)
2988 GEN_EXCP_PRIVOPC(ctx);
2989 #else
2990 /* stq */
2991 if (unlikely(ctx->supervisor == 0)) {
2992 GEN_EXCP_PRIVOPC(ctx);
2993 return;
2994 }
2995 if (unlikely(rs & 1)) {
2996 GEN_EXCP_INVAL(ctx);
2997 return;
2998 }
2999 if (unlikely(ctx->mem_idx & 1)) {
3000 /* Little-endian mode is not handled */
3001 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3002 return;
3003 }
3004 EA = tcg_temp_new();
3005 gen_addr_imm_index(EA, ctx, 0x03);
3006 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3007 tcg_gen_addi_tl(EA, EA, 8);
3008 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3009 tcg_temp_free(EA);
3010 #endif
3011 } else {
3012 /* std / stdu */
3013 if (Rc(ctx->opcode)) {
3014 if (unlikely(rA(ctx->opcode) == 0)) {
3015 GEN_EXCP_INVAL(ctx);
3016 return;
3017 }
3018 }
3019 EA = tcg_temp_new();
3020 gen_addr_imm_index(EA, ctx, 0x03);
3021 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3022 if (Rc(ctx->opcode))
3023 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3024 tcg_temp_free(EA);
3025 }
3026 }
3027 #endif
3028 /*** Integer load and store with byte reverse ***/
3029 /* lhbrx */
3030 void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3031 {
3032 TCGv_i32 temp = tcg_temp_new_i32();
3033 gen_qemu_ld16u(t0, t1, flags);
3034 tcg_gen_trunc_tl_i32(temp, t0);
3035 tcg_gen_bswap16_i32(temp, temp);
3036 tcg_gen_extu_i32_tl(t0, temp);
3037 tcg_temp_free_i32(temp);
3038 }
3039 GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER);
3040
3041 /* lwbrx */
3042 void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3043 {
3044 TCGv_i32 temp = tcg_temp_new_i32();
3045 gen_qemu_ld32u(t0, t1, flags);
3046 tcg_gen_trunc_tl_i32(temp, t0);
3047 tcg_gen_bswap_i32(temp, temp);
3048 tcg_gen_extu_i32_tl(t0, temp);
3049 tcg_temp_free_i32(temp);
3050 }
3051 GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER);
3052
3053 /* sthbrx */
3054 void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3055 {
3056 TCGv_i32 temp = tcg_temp_new_i32();
3057 TCGv t2 = tcg_temp_new();
3058 tcg_gen_trunc_tl_i32(temp, t0);
3059 tcg_gen_ext16u_i32(temp, temp);
3060 tcg_gen_bswap16_i32(temp, temp);
3061 tcg_gen_extu_i32_tl(t2, temp);
3062 tcg_temp_free_i32(temp);
3063 gen_qemu_st16(t2, t1, flags);
3064 tcg_temp_free(t2);
3065 }
3066 GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER);
3067
3068 /* stwbrx */
3069 void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3070 {
3071 TCGv_i32 temp = tcg_temp_new_i32();
3072 TCGv t2 = tcg_temp_new();
3073 tcg_gen_trunc_tl_i32(temp, t0);
3074 tcg_gen_bswap_i32(temp, temp);
3075 tcg_gen_extu_i32_tl(t2, temp);
3076 tcg_temp_free_i32(temp);
3077 gen_qemu_st32(t2, t1, flags);
3078 tcg_temp_free(t2);
3079 }
3080 GEN_STX(32r, 0x16, 0x14, PPC_INTEGER);
3081
3082 /*** Integer load and store multiple ***/
3083 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
3084 static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
3085 GEN_MEM_FUNCS(lmw),
3086 };
3087 static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
3088 GEN_MEM_FUNCS(stmw),
3089 };
3090
3091 /* lmw */
3092 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3093 {
3094 /* NIP cannot be restored if the memory exception comes from an helper */
3095 gen_update_nip(ctx, ctx->nip - 4);
3096 gen_addr_imm_index(cpu_T[0], ctx, 0);
3097 op_ldstm(lmw, rD(ctx->opcode));
3098 }
3099
3100 /* stmw */
3101 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3102 {
3103 /* NIP cannot be restored if the memory exception comes from an helper */
3104 gen_update_nip(ctx, ctx->nip - 4);
3105 gen_addr_imm_index(cpu_T[0], ctx, 0);
3106 op_ldstm(stmw, rS(ctx->opcode));
3107 }
3108
3109 /*** Integer load and store strings ***/
3110 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
3111 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
3112 /* string load & stores are by definition endian-safe */
3113 #define gen_op_lswi_le_raw gen_op_lswi_raw
3114 #define gen_op_lswi_le_user gen_op_lswi_user
3115 #define gen_op_lswi_le_kernel gen_op_lswi_kernel
3116 #define gen_op_lswi_le_hypv gen_op_lswi_hypv
3117 #define gen_op_lswi_le_64_raw gen_op_lswi_raw
3118 #define gen_op_lswi_le_64_user gen_op_lswi_user
3119 #define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
3120 #define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
3121 static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
3122 GEN_MEM_FUNCS(lswi),
3123 };
3124 #define gen_op_lswx_le_raw gen_op_lswx_raw
3125 #define gen_op_lswx_le_user gen_op_lswx_user
3126 #define gen_op_lswx_le_kernel gen_op_lswx_kernel
3127 #define gen_op_lswx_le_hypv gen_op_lswx_hypv
3128 #define gen_op_lswx_le_64_raw gen_op_lswx_raw
3129 #define gen_op_lswx_le_64_user gen_op_lswx_user
3130 #define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
3131 #define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
3132 static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
3133 GEN_MEM_FUNCS(lswx),
3134 };
3135 #define gen_op_stsw_le_raw gen_op_stsw_raw
3136 #define gen_op_stsw_le_user gen_op_stsw_user
3137 #define gen_op_stsw_le_kernel gen_op_stsw_kernel
3138 #define gen_op_stsw_le_hypv gen_op_stsw_hypv
3139 #define gen_op_stsw_le_64_raw gen_op_stsw_raw
3140 #define gen_op_stsw_le_64_user gen_op_stsw_user
3141 #define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
3142 #define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
3143 static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
3144 GEN_MEM_FUNCS(stsw),
3145 };
3146
3147 /* lswi */
3148 /* PowerPC32 specification says we must generate an exception if
3149 * rA is in the range of registers to be loaded.
3150 * In an other hand, IBM says this is valid, but rA won't be loaded.
3151 * For now, I'll follow the spec...
3152 */
3153 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3154 {
3155 int nb = NB(ctx->opcode);
3156 int start = rD(ctx->opcode);
3157 int ra = rA(ctx->opcode);
3158 int nr;
3159
3160 if (nb == 0)
3161 nb = 32;
3162 nr = nb / 4;
3163 if (unlikely(((start + nr) > 32 &&
3164 start <= ra && (start + nr - 32) > ra) ||
3165 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3166 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3167 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
3168 return;
3169 }
3170 /* NIP cannot be restored if the memory exception comes from an helper */
3171 gen_update_nip(ctx, ctx->nip - 4);
3172 gen_addr_register(cpu_T[0], ctx);
3173 tcg_gen_movi_tl(cpu_T[1], nb);
3174 op_ldsts(lswi, start);
3175 }
3176
3177 /* lswx */
3178 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3179 {
3180 int ra = rA(ctx->opcode);
3181 int rb = rB(ctx->opcode);
3182
3183 /* NIP cannot be restored if the memory exception comes from an helper */
3184 gen_update_nip(ctx, ctx->nip - 4);
3185 gen_addr_reg_index(cpu_T[0], ctx);
3186 if (ra == 0) {
3187 ra = rb;
3188 }
3189 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
3190 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
3191 }
3192
3193 /* stswi */
3194 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3195 {
3196 int nb = NB(ctx->opcode);
3197
3198 /* NIP cannot be restored if the memory exception comes from an helper */
3199 gen_update_nip(ctx, ctx->nip - 4);
3200 gen_addr_register(cpu_T[0], ctx);
3201 if (nb == 0)
3202 nb = 32;
3203 tcg_gen_movi_tl(cpu_T[1], nb);
3204 op_ldsts(stsw, rS(ctx->opcode));
3205 }
3206
3207 /* stswx */
3208 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3209 {
3210 /* NIP cannot be restored if the memory exception comes from an helper */
3211 gen_update_nip(ctx, ctx->nip - 4);
3212 gen_addr_reg_index(cpu_T[0], ctx);
3213 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
3214 op_ldsts(stsw, rS(ctx->opcode));
3215 }
3216
3217 /*** Memory synchronisation ***/
3218 /* eieio */
3219 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3220 {
3221 }
3222
3223 /* isync */
3224 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3225 {
3226 GEN_STOP(ctx);
3227 }
3228
3229 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
3230 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
3231 static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
3232 GEN_MEM_FUNCS(lwarx),
3233 };
3234 static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
3235 GEN_MEM_FUNCS(stwcx),
3236 };
3237
3238 /* lwarx */
3239 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3240 {
3241 /* NIP cannot be restored if the memory exception comes from an helper */
3242 gen_update_nip(ctx, ctx->nip - 4);
3243 gen_addr_reg_index(cpu_T[0], ctx);
3244 op_lwarx();
3245 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
3246 }
3247
3248 /* stwcx. */
3249 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3250 {
3251 /* NIP cannot be restored if the memory exception comes from an helper */
3252 gen_update_nip(ctx, ctx->nip - 4);
3253 gen_addr_reg_index(cpu_T[0], ctx);
3254 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
3255 op_stwcx();
3256 }
3257
3258 #if defined(TARGET_PPC64)
3259 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
3260 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
3261 static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
3262 GEN_MEM_FUNCS(ldarx),
3263 };
3264 static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
3265 GEN_MEM_FUNCS(stdcx),
3266 };
3267
3268 /* ldarx */
3269 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3270 {
3271 /* NIP cannot be restored if the memory exception comes from an helper */
3272 gen_update_nip(ctx, ctx->nip - 4);
3273 gen_addr_reg_index(cpu_T[0], ctx);
3274 op_ldarx();
3275 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
3276 }
3277
3278 /* stdcx. */
3279 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3280 {
3281 /* NIP cannot be restored if the memory exception comes from an helper */
3282 gen_update_nip(ctx, ctx->nip - 4);
3283 gen_addr_reg_index(cpu_T[0], ctx);
3284 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
3285 op_stdcx();
3286 }
3287 #endif /* defined(TARGET_PPC64) */
3288
3289 /* sync */
3290 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3291 {
3292 }
3293
3294 /* wait */
3295 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3296 {
3297 /* Stop translation, as the CPU is supposed to sleep from now */
3298 gen_op_wait();
3299 GEN_EXCP(ctx, EXCP_HLT, 1);
3300 }
3301
3302 /*** Floating-point load ***/
3303 #define GEN_LDF(width, opc, type) \
3304 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
3305 { \
3306 if (unlikely(!ctx->fpu_enabled)) { \
3307 GEN_EXCP_NO_FP(ctx); \
3308 return; \
3309 } \
3310 gen_addr_imm_index(cpu_T[0], ctx, 0); \
3311 op_ldst(l##width); \
3312 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
3313 }
3314
3315 #define GEN_LDUF(width, opc, type) \
3316 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3317 { \
3318 if (unlikely(!ctx->fpu_enabled)) { \
3319 GEN_EXCP_NO_FP(ctx); \
3320 return; \
3321 } \
3322 if (unlikely(rA(ctx->opcode) == 0)) { \
3323 GEN_EXCP_INVAL(ctx); \
3324 return; \
3325 } \
3326 gen_addr_imm_index(cpu_T[0], ctx, 0); \
3327 op_ldst(l##width); \
3328 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
3329 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
3330 }
3331
3332 #define GEN_LDUXF(width, opc, type) \
3333 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3334 { \
3335 if (unlikely(!ctx->fpu_enabled)) { \
3336 GEN_EXCP_NO_FP(ctx); \
3337 return; \
3338 } \
3339 if (unlikely(rA(ctx->opcode) == 0)) { \
3340 GEN_EXCP_INVAL(ctx); \
3341 return; \
3342 } \
3343 gen_addr_reg_index(cpu_T[0], ctx); \
3344 op_ldst(l##width); \
3345 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
3346 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
3347 }
3348
3349 #define GEN_LDXF(width, opc2, opc3, type) \
3350 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
3351 { \
3352 if (unlikely(!ctx->fpu_enabled)) { \
3353 GEN_EXCP_NO_FP(ctx); \
3354 return; \
3355 } \
3356 gen_addr_reg_index(cpu_T[0], ctx); \
3357 op_ldst(l##width); \
3358 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
3359 }
3360
3361 #define GEN_LDFS(width, op, type) \
3362 OP_LD_TABLE(width); \
3363 GEN_LDF(width, op | 0x20, type); \
3364 GEN_LDUF(width, op | 0x21, type); \
3365 GEN_LDUXF(width, op | 0x01, type); \
3366 GEN_LDXF(width, 0x17, op | 0x00, type)
3367
3368 /* lfd lfdu lfdux lfdx */
3369 GEN_LDFS(fd, 0x12, PPC_FLOAT);
3370 /* lfs lfsu lfsux lfsx */
3371 GEN_LDFS(fs, 0x10, PPC_FLOAT);
3372
3373 /*** Floating-point store ***/
3374 #define GEN_STF(width, opc, type) \
3375 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
3376 { \
3377 if (unlikely(!ctx->fpu_enabled)) { \
3378 GEN_EXCP_NO_FP(ctx); \
3379 return; \
3380 } \
3381 gen_addr_imm_index(cpu_T[0], ctx, 0); \
3382 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
3383 op_ldst(st##width); \
3384 }
3385
3386 #define GEN_STUF(width, opc, type) \
3387 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3388 { \
3389 if (unlikely(!ctx->fpu_enabled)) { \
3390 GEN_EXCP_NO_FP(ctx); \
3391 return; \
3392 } \
3393 if (unlikely(rA(ctx->opcode) == 0)) { \
3394 GEN_EXCP_INVAL(ctx); \
3395 return; \
3396 } \
3397 gen_addr_imm_index(cpu_T[0], ctx, 0); \
3398 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
3399 op_ldst(st##width); \
3400 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
3401 }
3402
3403 #define GEN_STUXF(width, opc, type) \
3404 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3405 { \
3406 if (unlikely(!ctx->fpu_enabled)) { \
3407 GEN_EXCP_NO_FP(ctx); \
3408 return; \
3409 } \
3410 if (unlikely(rA(ctx->opcode) == 0)) { \
3411 GEN_EXCP_INVAL(ctx); \
3412 return; \
3413 } \
3414 gen_addr_reg_index(cpu_T[0], ctx); \
3415 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
3416 op_ldst(st##width); \
3417 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
3418 }
3419
3420 #define GEN_STXF(width, opc2, opc3, type) \
3421 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
3422 { \
3423 if (unlikely(!ctx->fpu_enabled)) { \
3424 GEN_EXCP_NO_FP(ctx); \
3425 return; \
3426 } \
3427 gen_addr_reg_index(cpu_T[0], ctx); \
3428 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
3429 op_ldst(st##width); \
3430 }
3431
3432 #define GEN_STFS(width, op, type) \
3433 OP_ST_TABLE(width); \
3434 GEN_STF(width, op | 0x20, type); \
3435 GEN_STUF(width, op | 0x21, type); \
3436 GEN_STUXF(width, op | 0x01, type); \
3437 GEN_STXF(width, 0x17, op | 0x00, type)
3438
3439 /* stfd stfdu stfdux stfdx */
3440 GEN_STFS(fd, 0x16, PPC_FLOAT);
3441 /* stfs stfsu stfsux stfsx */
3442 GEN_STFS(fs, 0x14, PPC_FLOAT);
3443
3444 /* Optional: */
3445 /* stfiwx */
3446 OP_ST_TABLE(fiw);
3447 GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3448
3449 /*** Branch ***/
3450 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3451 target_ulong dest)
3452 {
3453 TranslationBlock *tb;
3454 tb = ctx->tb;
3455 #if defined(TARGET_PPC64)
3456 if (!ctx->sf_mode)
3457 dest = (uint32_t) dest;
3458 #endif
3459 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3460 likely(!ctx->singlestep_enabled)) {
3461 tcg_gen_goto_tb(n);
3462 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3463 tcg_gen_exit_tb((long)tb + n);
3464 } else {
3465 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3466 if (unlikely(ctx->singlestep_enabled)) {
3467 if ((ctx->singlestep_enabled &
3468 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3469 ctx->exception == POWERPC_EXCP_BRANCH) {
3470 target_ulong tmp = ctx->nip;
3471 ctx->nip = dest;
3472 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3473 ctx->nip = tmp;
3474 }
3475 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3476 gen_update_nip(ctx, dest);
3477 gen_helper_raise_debug();
3478 }
3479 }
3480 tcg_gen_exit_tb(0);
3481 }
3482 }
3483
3484 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3485 {
3486 #if defined(TARGET_PPC64)
3487 if (ctx->sf_mode == 0)
3488 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3489 else
3490 #endif
3491 tcg_gen_movi_tl(cpu_lr, nip);
3492 }
3493
3494 /* b ba bl bla */
3495 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3496 {
3497 target_ulong li, target;
3498
3499 ctx->exception = POWERPC_EXCP_BRANCH;
3500 /* sign extend LI */
3501 #if defined(TARGET_PPC64)
3502 if (ctx->sf_mode)
3503 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3504 else
3505 #endif
3506 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3507 if (likely(AA(ctx->opcode) == 0))
3508 target = ctx->nip + li - 4;
3509 else
3510 target = li;
3511 if (LK(ctx->opcode))
3512 gen_setlr(ctx, ctx->nip);
3513 gen_goto_tb(ctx, 0, target);
3514 }
3515
3516 #define BCOND_IM 0
3517 #define BCOND_LR 1
3518 #define BCOND_CTR 2
3519
3520 static always_inline void gen_bcond (DisasContext *ctx, int type)
3521 {
3522 uint32_t bo = BO(ctx->opcode);
3523 int l1 = gen_new_label();
3524 TCGv target;
3525
3526 ctx->exception = POWERPC_EXCP_BRANCH;
3527 if (type == BCOND_LR || type == BCOND_CTR) {
3528 target = tcg_temp_local_new();
3529 if (type == BCOND_CTR)
3530 tcg_gen_mov_tl(target, cpu_ctr);
3531 else
3532 tcg_gen_mov_tl(target, cpu_lr);
3533 }
3534 if (LK(ctx->opcode))
3535 gen_setlr(ctx, ctx->nip);
3536 l1 = gen_new_label();
3537 if ((bo & 0x4) == 0) {
3538 /* Decrement and test CTR */
3539 TCGv temp = tcg_temp_new();
3540 if (unlikely(type == BCOND_CTR)) {
3541 GEN_EXCP_INVAL(ctx);
3542 return;
3543 }
3544 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3545 #if defined(TARGET_PPC64)
3546 if (!ctx->sf_mode)
3547 tcg_gen_ext32u_tl(temp, cpu_ctr);
3548 else
3549 #endif
3550 tcg_gen_mov_tl(temp, cpu_ctr);
3551 if (bo & 0x2) {
3552 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3553 } else {
3554 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3555 }
3556 tcg_temp_free(temp);
3557 }
3558 if ((bo & 0x10) == 0) {
3559 /* Test CR */
3560 uint32_t bi = BI(ctx->opcode);
3561 uint32_t mask = 1 << (3 - (bi & 0x03));
3562 TCGv_i32 temp = tcg_temp_new_i32();
3563
3564 if (bo & 0x8) {
3565 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3566 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3567 } else {
3568 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3569 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3570 }
3571 tcg_temp_free_i32(temp);
3572 }
3573 if (type == BCOND_IM) {
3574 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3575 if (likely(AA(ctx->opcode) == 0)) {
3576 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3577 } else {
3578 gen_goto_tb(ctx, 0, li);
3579 }
3580 gen_set_label(l1);
3581 gen_goto_tb(ctx, 1, ctx->nip);
3582 } else {
3583 #if defined(TARGET_PPC64)
3584 if (!(ctx->sf_mode))
3585 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3586 else
3587 #endif
3588 tcg_gen_andi_tl(cpu_nip, target, ~3);
3589 tcg_gen_exit_tb(0);
3590 gen_set_label(l1);
3591 #if defined(TARGET_PPC64)
3592 if (!(ctx->sf_mode))
3593 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3594 else
3595 #endif
3596 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3597 tcg_gen_exit_tb(0);
3598 }
3599 }
3600
3601 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3602 {
3603 gen_bcond(ctx, BCOND_IM);
3604 }
3605
3606 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3607 {
3608 gen_bcond(ctx, BCOND_CTR);
3609 }
3610
3611 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3612 {
3613 gen_bcond(ctx, BCOND_LR);
3614 }
3615
3616 /*** Condition register logical ***/
3617 #define GEN_CRLOGIC(name, tcg_op, opc) \
3618 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3619 { \
3620 uint8_t bitmask; \
3621 int sh; \
3622 TCGv_i32 t0, t1; \
3623 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3624 t0 = tcg_temp_new_i32(); \
3625 if (sh > 0) \
3626 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3627 else if (sh < 0) \
3628 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3629 else \
3630 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3631 t1 = tcg_temp_new_i32(); \
3632 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3633 if (sh > 0) \
3634 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3635 else if (sh < 0) \
3636 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3637 else \
3638 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3639 tcg_op(t0, t0, t1); \
3640 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3641 tcg_gen_andi_i32(t0, t0, bitmask); \
3642 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3643 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3644 tcg_temp_free_i32(t0); \
3645 tcg_temp_free_i32(t1); \
3646 }
3647
3648 /* crand */
3649 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3650 /* crandc */
3651 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3652 /* creqv */
3653 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3654 /* crnand */
3655 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3656 /* crnor */
3657 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3658 /* cror */
3659 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3660 /* crorc */
3661 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3662 /* crxor */
3663 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3664 /* mcrf */
3665 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3666 {
3667 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3668 }
3669
3670 /*** System linkage ***/
3671 /* rfi (supervisor only) */
3672 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3673 {
3674 #if defined(CONFIG_USER_ONLY)
3675 GEN_EXCP_PRIVOPC(ctx);
3676 #else
3677 /* Restore CPU state */
3678 if (unlikely(!ctx->supervisor)) {
3679 GEN_EXCP_PRIVOPC(ctx);
3680 return;
3681 }
3682 gen_op_rfi();
3683 GEN_SYNC(ctx);
3684 #endif
3685 }
3686
3687 #if defined(TARGET_PPC64)
3688 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3689 {
3690 #if defined(CONFIG_USER_ONLY)
3691 GEN_EXCP_PRIVOPC(ctx);
3692 #else
3693 /* Restore CPU state */
3694 if (unlikely(!ctx->supervisor)) {
3695 GEN_EXCP_PRIVOPC(ctx);
3696 return;
3697 }
3698 gen_op_rfid();
3699 GEN_SYNC(ctx);
3700 #endif
3701 }
3702
3703 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3704 {
3705 #if defined(CONFIG_USER_ONLY)
3706 GEN_EXCP_PRIVOPC(ctx);
3707 #else
3708 /* Restore CPU state */
3709 if (unlikely(ctx->supervisor <= 1)) {
3710 GEN_EXCP_PRIVOPC(ctx);
3711 return;
3712 }
3713 gen_op_hrfid();
3714 GEN_SYNC(ctx);
3715 #endif
3716 }
3717 #endif
3718
3719 /* sc */
3720 #if defined(CONFIG_USER_ONLY)
3721 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3722 #else
3723 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3724 #endif
3725 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3726 {
3727 uint32_t lev;
3728
3729 lev = (ctx->opcode >> 5) & 0x7F;
3730 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3731 }
3732
3733 /*** Trap ***/
3734 /* tw */
3735 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3736 {
3737 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3738 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3739 /* Update the nip since this might generate a trap exception */
3740 gen_update_nip(ctx, ctx->nip);
3741 gen_op_tw(TO(ctx->opcode));
3742 }
3743
3744 /* twi */
3745 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3746 {
3747 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3748 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3749 /* Update the nip since this might generate a trap exception */
3750 gen_update_nip(ctx, ctx->nip);
3751 gen_op_tw(TO(ctx->opcode));
3752 }
3753
3754 #if defined(TARGET_PPC64)
3755 /* td */
3756 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3757 {
3758 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3759 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3760 /* Update the nip since this might generate a trap exception */
3761 gen_update_nip(ctx, ctx->nip);
3762 gen_op_td(TO(ctx->opcode));
3763 }
3764
3765 /* tdi */
3766 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3767 {
3768 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3769 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3770 /* Update the nip since this might generate a trap exception */
3771 gen_update_nip(ctx, ctx->nip);
3772 gen_op_td(TO(ctx->opcode));
3773 }
3774 #endif
3775
3776 /*** Processor control ***/
3777 /* mcrxr */
3778 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3779 {
3780 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3781 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3782 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3783 }
3784
3785 /* mfcr */
3786 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3787 {
3788 uint32_t crm, crn;
3789
3790 if (likely(ctx->opcode & 0x00100000)) {
3791 crm = CRM(ctx->opcode);
3792 if (likely((crm ^ (crm - 1)) == 0)) {
3793 crn = ffs(crm);
3794 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3795 }
3796 } else {
3797 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
3798 }
3799 }
3800
3801 /* mfmsr */
3802 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3803 {
3804 #if defined(CONFIG_USER_ONLY)
3805 GEN_EXCP_PRIVREG(ctx);
3806 #else
3807 if (unlikely(!ctx->supervisor)) {
3808 GEN_EXCP_PRIVREG(ctx);
3809 return;
3810 }
3811 gen_op_load_msr();
3812 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3813 #endif
3814 }
3815
3816 #if 1
3817 #define SPR_NOACCESS ((void *)(-1UL))
3818 #else
3819 static void spr_noaccess (void *opaque, int sprn)
3820 {
3821 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3822 printf("ERROR: try to access SPR %d !\n", sprn);
3823 }
3824 #define SPR_NOACCESS (&spr_noaccess)
3825 #endif
3826
3827 /* mfspr */
3828 static always_inline void gen_op_mfspr (DisasContext *ctx)
3829 {
3830 void (*read_cb)(void *opaque, int sprn);
3831 uint32_t sprn = SPR(ctx->opcode);
3832
3833 #if !defined(CONFIG_USER_ONLY)
3834 if (ctx->supervisor == 2)
3835 read_cb = ctx->spr_cb[sprn].hea_read;
3836 else if (ctx->supervisor)
3837 read_cb = ctx->spr_cb[sprn].oea_read;
3838 else
3839 #endif
3840 read_cb = ctx->spr_cb[sprn].uea_read;
3841 if (likely(read_cb != NULL)) {
3842 if (likely(read_cb != SPR_NOACCESS)) {
3843 (*read_cb)(ctx, sprn);
3844 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3845 } else {
3846 /* Privilege exception */
3847 /* This is a hack to avoid warnings when running Linux:
3848 * this OS breaks the PowerPC virtualisation model,
3849 * allowing userland application to read the PVR
3850 */
3851 if (sprn != SPR_PVR) {
3852 if (loglevel != 0) {
3853 fprintf(logfile, "Trying to read privileged spr %d %03x at "
3854 ADDRX "\n", sprn, sprn, ctx->nip);
3855 }
3856 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3857 sprn, sprn, ctx->nip);
3858 }
3859 GEN_EXCP_PRIVREG(ctx);
3860 }
3861 } else {
3862 /* Not defined */
3863 if (loglevel != 0) {
3864 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3865 ADDRX "\n", sprn, sprn, ctx->nip);
3866 }
3867 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3868 sprn, sprn, ctx->nip);
3869 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3870 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3871 }
3872 }
3873
3874 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3875 {
3876 gen_op_mfspr(ctx);
3877 }
3878
3879 /* mftb */
3880 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3881 {
3882 gen_op_mfspr(ctx);
3883 }
3884
3885 /* mtcrf */
3886 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3887 {
3888 uint32_t crm, crn;
3889
3890 crm = CRM(ctx->opcode);
3891 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3892 TCGv_i32 temp = tcg_temp_new_i32();
3893 crn = ffs(crm);
3894 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3895 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3896 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3897 tcg_temp_free_i32(temp);
3898 } else {
3899 TCGv_i32 temp = tcg_const_i32(crm);
3900 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3901 tcg_temp_free_i32(temp);
3902 }
3903 }
3904
3905 /* mtmsr */
3906 #if defined(TARGET_PPC64)
3907 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3908 {
3909 #if defined(CONFIG_USER_ONLY)
3910 GEN_EXCP_PRIVREG(ctx);
3911 #else
3912 if (unlikely(!ctx->supervisor)) {
3913 GEN_EXCP_PRIVREG(ctx);
3914 return;
3915 }
3916 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3917 if (ctx->opcode & 0x00010000) {
3918 /* Special form that does not need any synchronisation */
3919 gen_op_update_riee();
3920 } else {
3921 /* XXX: we need to update nip before the store
3922 * if we enter power saving mode, we will exit the loop
3923 * directly from ppc_store_msr
3924 */
3925 gen_update_nip(ctx, ctx->nip);
3926 gen_op_store_msr();
3927 /* Must stop the translation as machine state (may have) changed */
3928 /* Note that mtmsr is not always defined as context-synchronizing */
3929 ctx->exception = POWERPC_EXCP_STOP;
3930 }
3931 #endif
3932 }
3933 #endif
3934
3935 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3936 {
3937 #if defined(CONFIG_USER_ONLY)
3938 GEN_EXCP_PRIVREG(ctx);
3939 #else
3940 if (unlikely(!ctx->supervisor)) {
3941 GEN_EXCP_PRIVREG(ctx);
3942 return;
3943 }
3944 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3945 if (ctx->opcode & 0x00010000) {
3946 /* Special form that does not need any synchronisation */
3947 gen_op_update_riee();
3948 } else {
3949 /* XXX: we need to update nip before the store
3950 * if we enter power saving mode, we will exit the loop
3951 * directly from ppc_store_msr
3952 */
3953 gen_update_nip(ctx, ctx->nip);
3954 #if defined(TARGET_PPC64)
3955 if (!ctx->sf_mode)
3956 gen_op_store_msr_32();
3957 else
3958 #endif
3959 gen_op_store_msr();
3960 /* Must stop the translation as machine state (may have) changed */
3961 /* Note that mtmsrd is not always defined as context-synchronizing */
3962 ctx->exception = POWERPC_EXCP_STOP;
3963 }
3964 #endif
3965 }
3966
3967 /* mtspr */
3968 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3969 {
3970 void (*write_cb)(void *opaque, int sprn);
3971 uint32_t sprn = SPR(ctx->opcode);
3972
3973 #if !defined(CONFIG_USER_ONLY)
3974 if (ctx->supervisor == 2)
3975 write_cb = ctx->spr_cb[sprn].hea_write;
3976 else if (ctx->supervisor)
3977 write_cb = ctx->spr_cb[sprn].oea_write;
3978 else
3979 #endif
3980 write_cb = ctx->spr_cb[sprn].uea_write;
3981 if (likely(write_cb != NULL)) {
3982 if (likely(write_cb != SPR_NOACCESS)) {
3983 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3984 (*write_cb)(ctx, sprn);
3985 } else {
3986 /* Privilege exception */
3987 if (loglevel != 0) {
3988 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3989 ADDRX "\n", sprn, sprn, ctx->nip);
3990 }
3991 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3992 sprn, sprn, ctx->nip);
3993 GEN_EXCP_PRIVREG(ctx);
3994 }
3995 } else {
3996 /* Not defined */
3997 if (loglevel != 0) {
3998 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3999 ADDRX "\n", sprn, sprn, ctx->nip);
4000 }
4001 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4002 sprn, sprn, ctx->nip);
4003 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4004 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
4005 }
4006 }
4007
4008 /*** Cache management ***/
4009 /* dcbf */
4010 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4011 {
4012 /* XXX: specification says this is treated as a load by the MMU */
4013 TCGv t0 = tcg_temp_new();
4014 gen_addr_reg_index(t0, ctx);
4015 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4016 tcg_temp_free(t0);
4017 }
4018
4019 /* dcbi (Supervisor only) */
4020 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4021 {
4022 #if defined(CONFIG_USER_ONLY)
4023 GEN_EXCP_PRIVOPC(ctx);
4024 #else
4025 TCGv EA, val;
4026 if (unlikely(!ctx->supervisor)) {
4027 GEN_EXCP_PRIVOPC(ctx);
4028 return;
4029 }
4030 EA = tcg_temp_new();
4031 gen_addr_reg_index(EA, ctx);
4032 val = tcg_temp_new();
4033 /* XXX: specification says this should be treated as a store by the MMU */
4034 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4035 gen_qemu_st8(val, EA, ctx->mem_idx);
4036 tcg_temp_free(val);
4037 tcg_temp_free(EA);
4038 #endif
4039 }
4040
4041 /* dcdst */
4042 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4043 {
4044 /* XXX: specification say this is treated as a load by the MMU */
4045 TCGv t0 = tcg_temp_new();
4046 gen_addr_reg_index(t0, ctx);
4047 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4048 tcg_temp_free(t0);
4049 }
4050
4051 /* dcbt */
4052 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4053 {
4054 /* interpreted as no-op */
4055 /* XXX: specification say this is treated as a load by the MMU
4056 * but does not generate any exception
4057 */
4058 }
4059
4060 /* dcbtst */
4061 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4062 {
4063 /* interpreted as no-op */
4064 /* XXX: specification say this is treated as a load by the MMU
4065 * but does not generate any exception
4066 */
4067 }
4068
4069 /* dcbz */
4070 #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
4071 static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
4072 /* 32 bytes cache line size */
4073 {
4074 #define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
4075 #define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
4076 #define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
4077 #define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
4078 #define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
4079 #define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
4080 #define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
4081 #define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
4082 GEN_MEM_FUNCS(dcbz_l32),
4083 },
4084 /* 64 bytes cache line size */
4085 {
4086 #define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
4087 #define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
4088 #define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
4089 #define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
4090 #define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
4091 #define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
4092 #define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
4093 #define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
4094 GEN_MEM_FUNCS(dcbz_l64),
4095 },
4096 /* 128 bytes cache line size */
4097 {
4098 #define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
4099 #define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
4100 #define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
4101 #define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
4102 #define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
4103 #define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
4104 #define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
4105 #define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
4106 GEN_MEM_FUNCS(dcbz_l128),
4107 },
4108 /* tunable cache line size */
4109 {
4110 #define gen_op_dcbz_le_raw gen_op_dcbz_raw
4111 #define gen_op_dcbz_le_user gen_op_dcbz_user
4112 #define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
4113 #define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
4114 #define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
4115 #define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
4116 #define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
4117 #define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
4118 GEN_MEM_FUNCS(dcbz),
4119 },
4120 };
4121
4122 static always_inline void handler_dcbz (DisasContext *ctx,
4123 int dcache_line_size)
4124 {
4125 int n;
4126
4127 switch (dcache_line_size) {
4128 case 32:
4129 n = 0;
4130 break;
4131 case 64:
4132 n = 1;
4133 break;
4134 case 128:
4135 n = 2;
4136 break;
4137 default:
4138 n = 3;
4139 break;
4140 }
4141 op_dcbz(n);
4142 }
4143
4144 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4145 {
4146 gen_addr_reg_index(cpu_T[0], ctx);
4147 handler_dcbz(ctx, ctx->dcache_line_size);
4148 gen_op_check_reservation();
4149 }
4150
4151 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4152 {
4153 gen_addr_reg_index(cpu_T[0], ctx);
4154 if (ctx->opcode & 0x00200000)
4155 handler_dcbz(ctx, ctx->dcache_line_size);
4156 else
4157 handler_dcbz(ctx, -1);
4158 gen_op_check_reservation();
4159 }
4160
4161 /* icbi */
4162 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
4163 #define gen_op_icbi_le_raw gen_op_icbi_raw
4164 #define gen_op_icbi_le_user gen_op_icbi_user
4165 #define gen_op_icbi_le_kernel gen_op_icbi_kernel
4166 #define gen_op_icbi_le_hypv gen_op_icbi_hypv
4167 #define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
4168 #define gen_op_icbi_le_64_user gen_op_icbi_64_user
4169 #define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
4170 #define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
4171 static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
4172 GEN_MEM_FUNCS(icbi),
4173 };
4174
4175 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4176 {
4177 /* NIP cannot be restored if the memory exception comes from an helper */
4178 gen_update_nip(ctx, ctx->nip - 4);
4179 gen_addr_reg_index(cpu_T[0], ctx);
4180 op_icbi();
4181 }
4182
4183 /* Optional: */
4184 /* dcba */
4185 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4186 {
4187 /* interpreted as no-op */
4188 /* XXX: specification say this is treated as a store by the MMU
4189 * but does not generate any exception
4190 */
4191 }
4192
4193 /*** Segment register manipulation ***/
4194 /* Supervisor only: */
4195 /* mfsr */
4196 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4197 {
4198 #if defined(CONFIG_USER_ONLY)
4199 GEN_EXCP_PRIVREG(ctx);
4200 #else
4201 if (unlikely(!ctx->supervisor)) {
4202 GEN_EXCP_PRIVREG(ctx);
4203 return;
4204 }
4205 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
4206 gen_op_load_sr();
4207 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4208 #endif
4209 }
4210
4211 /* mfsrin */
4212 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4213 {
4214 #if defined(CONFIG_USER_ONLY)
4215 GEN_EXCP_PRIVREG(ctx);
4216 #else
4217 if (unlikely(!ctx->supervisor)) {
4218 GEN_EXCP_PRIVREG(ctx);
4219 return;
4220 }
4221 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4222 gen_op_srli_T1(28);
4223 gen_op_load_sr();
4224 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4225 #endif
4226 }
4227
4228 /* mtsr */
4229 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4230 {
4231 #if defined(CONFIG_USER_ONLY)
4232 GEN_EXCP_PRIVREG(ctx);
4233 #else
4234 if (unlikely(!ctx->supervisor)) {
4235 GEN_EXCP_PRIVREG(ctx);
4236 return;
4237 }
4238 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4239 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
4240 gen_op_store_sr();
4241 #endif
4242 }
4243
4244 /* mtsrin */
4245 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4246 {
4247 #if defined(CONFIG_USER_ONLY)
4248 GEN_EXCP_PRIVREG(ctx);
4249 #else
4250 if (unlikely(!ctx->supervisor)) {
4251 GEN_EXCP_PRIVREG(ctx);
4252 return;
4253 }
4254 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4255 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4256 gen_op_srli_T1(28);
4257 gen_op_store_sr();
4258 #endif
4259 }
4260
4261 #if defined(TARGET_PPC64)
4262 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4263 /* mfsr */
4264 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4265 {
4266 #if defined(CONFIG_USER_ONLY)
4267 GEN_EXCP_PRIVREG(ctx);
4268 #else
4269 if (unlikely(!ctx->supervisor)) {
4270 GEN_EXCP_PRIVREG(ctx);
4271 return;
4272 }
4273 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
4274 gen_op_load_slb();
4275 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4276 #endif
4277 }
4278
4279 /* mfsrin */
4280 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4281 PPC_SEGMENT_64B)
4282 {
4283 #if defined(CONFIG_USER_ONLY)
4284 GEN_EXCP_PRIVREG(ctx);
4285 #else
4286 if (unlikely(!ctx->supervisor)) {
4287 GEN_EXCP_PRIVREG(ctx);
4288 return;
4289 }
4290 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4291 gen_op_srli_T1(28);
4292 gen_op_load_slb();
4293 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4294 #endif
4295 }
4296
4297 /* mtsr */
4298 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4299 {
4300 #if defined(CONFIG_USER_ONLY)
4301 GEN_EXCP_PRIVREG(ctx);
4302 #else
4303 if (unlikely(!ctx->supervisor)) {
4304 GEN_EXCP_PRIVREG(ctx);
4305 return;
4306 }
4307 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4308 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
4309 gen_op_store_slb();
4310 #endif
4311 }
4312
4313 /* mtsrin */
4314 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4315 PPC_SEGMENT_64B)
4316 {
4317 #if defined(CONFIG_USER_ONLY)
4318 GEN_EXCP_PRIVREG(ctx);
4319 #else
4320 if (unlikely(!ctx->supervisor)) {
4321 GEN_EXCP_PRIVREG(ctx);
4322 return;
4323 }
4324 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4325 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4326 gen_op_srli_T1(28);
4327 gen_op_store_slb();
4328 #endif
4329 }
4330 #endif /* defined(TARGET_PPC64) */
4331
4332 /*** Lookaside buffer management ***/
4333 /* Optional & supervisor only: */
4334 /* tlbia */
4335 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4336 {
4337 #if defined(CONFIG_USER_ONLY)
4338 GEN_EXCP_PRIVOPC(ctx);
4339 #else
4340 if (unlikely(!ctx->supervisor)) {
4341 GEN_EXCP_PRIVOPC(ctx);
4342 return;
4343 }
4344 gen_op_tlbia();
4345 #endif
4346 }
4347
4348 /* tlbie */
4349 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4350 {
4351 #if defined(CONFIG_USER_ONLY)
4352 GEN_EXCP_PRIVOPC(ctx);
4353 #else
4354 if (unlikely(!ctx->supervisor)) {
4355 GEN_EXCP_PRIVOPC(ctx);
4356 return;
4357 }
4358 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4359 #if defined(TARGET_PPC64)
4360 if (ctx->sf_mode)
4361 gen_op_tlbie_64();
4362 else
4363 #endif
4364 gen_op_tlbie();
4365 #endif
4366 }
4367
4368 /* tlbsync */
4369 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4370 {
4371 #if defined(CONFIG_USER_ONLY)
4372 GEN_EXCP_PRIVOPC(ctx);
4373 #else
4374 if (unlikely(!ctx->supervisor)) {
4375 GEN_EXCP_PRIVOPC(ctx);
4376 return;
4377 }
4378 /* This has no effect: it should ensure that all previous
4379 * tlbie have completed
4380 */
4381 GEN_STOP(ctx);
4382 #endif
4383 }
4384
4385 #if defined(TARGET_PPC64)
4386 /* slbia */
4387 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4388 {
4389 #if defined(CONFIG_USER_ONLY)
4390 GEN_EXCP_PRIVOPC(ctx);
4391 #else
4392 if (unlikely(!ctx->supervisor)) {
4393 GEN_EXCP_PRIVOPC(ctx);
4394 return;
4395 }
4396 gen_op_slbia();
4397 #endif
4398 }
4399
4400 /* slbie */
4401 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4402 {
4403 #if defined(CONFIG_USER_ONLY)
4404 GEN_EXCP_PRIVOPC(ctx);
4405 #else
4406 if (unlikely(!ctx->supervisor)) {
4407 GEN_EXCP_PRIVOPC(ctx);
4408 return;
4409 }
4410 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4411 gen_op_slbie();
4412 #endif
4413 }
4414 #endif
4415
4416 /*** External control ***/
4417 /* Optional: */
4418 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4419 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
4420 static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4421 GEN_MEM_FUNCS(eciwx),
4422 };
4423 static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4424 GEN_MEM_FUNCS(ecowx),
4425 };
4426
4427 /* eciwx */
4428 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4429 {
4430 /* Should check EAR[E] & alignment ! */
4431 gen_addr_reg_index(cpu_T[0], ctx);
4432 op_eciwx();
4433 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4434 }
4435
4436 /* ecowx */
4437 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4438 {
4439 /* Should check EAR[E] & alignment ! */
4440 gen_addr_reg_index(cpu_T[0], ctx);
4441 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4442 op_ecowx();
4443 }
4444
4445 /* PowerPC 601 specific instructions */
4446 /* abs - abs. */
4447 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4448 {
4449 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4450 gen_op_POWER_abs();
4451 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4452 if (unlikely(Rc(ctx->opcode) != 0))
4453 gen_set_Rc0(ctx, cpu_T[0]);
4454 }
4455
4456 /* abso - abso. */
4457 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4458 {
4459 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4460 gen_op_POWER_abso();
4461 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4462 if (unlikely(Rc(ctx->opcode) != 0))
4463 gen_set_Rc0(ctx, cpu_T[0]);
4464 }
4465
4466 /* clcs */
4467 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4468 {
4469 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4470 gen_op_POWER_clcs();
4471 /* Rc=1 sets CR0 to an undefined state */
4472 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4473 }
4474
4475 /* div - div. */
4476 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4477 {
4478 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4479 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4480 gen_op_POWER_div();
4481 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4482 if (unlikely(Rc(ctx->opcode) != 0))
4483 gen_set_Rc0(ctx, cpu_T[0]);
4484 }
4485
4486 /* divo - divo. */
4487 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4488 {
4489 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4490 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4491 gen_op_POWER_divo();
4492 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4493 if (unlikely(Rc(ctx->opcode) != 0))
4494 gen_set_Rc0(ctx, cpu_T[0]);
4495 }
4496
4497 /* divs - divs. */
4498 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4499 {
4500 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4501 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4502 gen_op_POWER_divs();
4503 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4504 if (unlikely(Rc(ctx->opcode) != 0))
4505 gen_set_Rc0(ctx, cpu_T[0]);
4506 }
4507
4508 /* divso - divso. */
4509 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4510 {
4511 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4512 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4513 gen_op_POWER_divso();
4514 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4515 if (unlikely(Rc(ctx->opcode) != 0))
4516 gen_set_Rc0(ctx, cpu_T[0]);
4517 }
4518
4519 /* doz - doz. */
4520 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4521 {
4522 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4523 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4524 gen_op_POWER_doz();
4525 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4526 if (unlikely(Rc(ctx->opcode) != 0))
4527 gen_set_Rc0(ctx, cpu_T[0]);
4528 }
4529
4530 /* dozo - dozo. */
4531 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4532 {
4533 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4534 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4535 gen_op_POWER_dozo();
4536 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4537 if (unlikely(Rc(ctx->opcode) != 0))
4538 gen_set_Rc0(ctx, cpu_T[0]);
4539 }
4540
4541 /* dozi */
4542 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4543 {
4544 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4545 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
4546 gen_op_POWER_doz();
4547 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4548 }
4549
4550 /* As lscbx load from memory byte after byte, it's always endian safe.
4551 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4552 */
4553 #define op_POWER_lscbx(start, ra, rb) \
4554 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4555 #define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4556 #define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4557 #define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4558 #define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4559 #define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4560 #define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4561 #define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4562 #define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4563 #define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4564 #define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4565 #define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4566 #define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4567 static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4568 GEN_MEM_FUNCS(POWER_lscbx),
4569 };
4570
4571 /* lscbx - lscbx. */
4572 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4573 {
4574 int ra = rA(ctx->opcode);
4575 int rb = rB(ctx->opcode);
4576
4577 gen_addr_reg_index(cpu_T[0], ctx);
4578 if (ra == 0) {
4579 ra = rb;
4580 }
4581 /* NIP cannot be restored if the memory exception comes from an helper */
4582 gen_update_nip(ctx, ctx->nip - 4);
4583 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4584 tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4585 tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
4586 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4587 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4588 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
4589 if (unlikely(Rc(ctx->opcode) != 0))
4590 gen_set_Rc0(ctx, cpu_T[0]);
4591 }
4592
4593 /* maskg - maskg. */
4594 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4595 {
4596 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4597 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4598 gen_op_POWER_maskg();
4599 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4600 if (unlikely(Rc(ctx->opcode) != 0))
4601 gen_set_Rc0(ctx, cpu_T[0]);
4602 }
4603
4604 /* maskir - maskir. */
4605 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4606 {
4607 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4608 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4609 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4610 gen_op_POWER_maskir();
4611 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4612 if (unlikely(Rc(ctx->opcode) != 0))
4613 gen_set_Rc0(ctx, cpu_T[0]);
4614 }
4615
4616 /* mul - mul. */
4617 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4618 {
4619 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4620 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4621 gen_op_POWER_mul();
4622 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4623 if (unlikely(Rc(ctx->opcode) != 0))
4624 gen_set_Rc0(ctx, cpu_T[0]);
4625 }
4626
4627 /* mulo - mulo. */
4628 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4629 {
4630 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4631 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4632 gen_op_POWER_mulo();
4633 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4634 if (unlikely(Rc(ctx->opcode) != 0))
4635 gen_set_Rc0(ctx, cpu_T[0]);
4636 }
4637
4638 /* nabs - nabs. */
4639 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4640 {
4641 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4642 gen_op_POWER_nabs();
4643 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4644 if (unlikely(Rc(ctx->opcode) != 0))
4645 gen_set_Rc0(ctx, cpu_T[0]);
4646 }
4647
4648 /* nabso - nabso. */
4649 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4650 {
4651 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4652 gen_op_POWER_nabso();
4653 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4654 if (unlikely(Rc(ctx->opcode) != 0))
4655 gen_set_Rc0(ctx, cpu_T[0]);
4656 }
4657
4658 /* rlmi - rlmi. */
4659 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4660 {
4661 uint32_t mb, me;
4662
4663 mb = MB(ctx->opcode);
4664 me = ME(ctx->opcode);
4665 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4666 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4667 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4668 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4669 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4670 if (unlikely(Rc(ctx->opcode) != 0))
4671 gen_set_Rc0(ctx, cpu_T[0]);
4672 }
4673
4674 /* rrib - rrib. */
4675 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4676 {
4677 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4678 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4679 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4680 gen_op_POWER_rrib();
4681 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4682 if (unlikely(Rc(ctx->opcode) != 0))
4683 gen_set_Rc0(ctx, cpu_T[0]);
4684 }
4685
4686 /* sle - sle. */
4687 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4688 {
4689 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4690 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4691 gen_op_POWER_sle();
4692 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4693 if (unlikely(Rc(ctx->opcode) != 0))
4694 gen_set_Rc0(ctx, cpu_T[0]);
4695 }
4696
4697 /* sleq - sleq. */
4698 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4699 {
4700 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4701 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4702 gen_op_POWER_sleq();
4703 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4704 if (unlikely(Rc(ctx->opcode) != 0))
4705 gen_set_Rc0(ctx, cpu_T[0]);
4706 }
4707
4708 /* sliq - sliq. */
4709 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4710 {
4711 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4712 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4713 gen_op_POWER_sle();
4714 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4715 if (unlikely(Rc(ctx->opcode) != 0))
4716 gen_set_Rc0(ctx, cpu_T[0]);
4717 }
4718
4719 /* slliq - slliq. */
4720 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4721 {
4722 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4723 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4724 gen_op_POWER_sleq();
4725 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4726 if (unlikely(Rc(ctx->opcode) != 0))
4727 gen_set_Rc0(ctx, cpu_T[0]);
4728 }
4729
4730 /* sllq - sllq. */
4731 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4732 {
4733 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4734 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4735 gen_op_POWER_sllq();
4736 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4737 if (unlikely(Rc(ctx->opcode) != 0))
4738 gen_set_Rc0(ctx, cpu_T[0]);
4739 }
4740
4741 /* slq - slq. */
4742 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4743 {
4744 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4745 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4746 gen_op_POWER_slq();
4747 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4748 if (unlikely(Rc(ctx->opcode) != 0))
4749 gen_set_Rc0(ctx, cpu_T[0]);
4750 }
4751
4752 /* sraiq - sraiq. */
4753 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4754 {
4755 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4756 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4757 gen_op_POWER_sraq();
4758 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4759 if (unlikely(Rc(ctx->opcode) != 0))
4760 gen_set_Rc0(ctx, cpu_T[0]);
4761 }
4762
4763 /* sraq - sraq. */
4764 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4765 {
4766 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4767 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4768 gen_op_POWER_sraq();
4769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4770 if (unlikely(Rc(ctx->opcode) != 0))
4771 gen_set_Rc0(ctx, cpu_T[0]);
4772 }
4773
4774 /* sre - sre. */
4775 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4776 {
4777 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4778 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4779 gen_op_POWER_sre();
4780 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4781 if (unlikely(Rc(ctx->opcode) != 0))
4782 gen_set_Rc0(ctx, cpu_T[0]);
4783 }
4784
4785 /* srea - srea. */
4786 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4787 {
4788 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4789 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4790 gen_op_POWER_srea();
4791 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4792 if (unlikely(Rc(ctx->opcode) != 0))
4793 gen_set_Rc0(ctx, cpu_T[0]);
4794 }
4795
4796 /* sreq */
4797 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4798 {
4799 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4800 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4801 gen_op_POWER_sreq();
4802 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4803 if (unlikely(Rc(ctx->opcode) != 0))
4804 gen_set_Rc0(ctx, cpu_T[0]);
4805 }
4806
4807 /* sriq */
4808 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4809 {
4810 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4811 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4812 gen_op_POWER_srq();
4813 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4814 if (unlikely(Rc(ctx->opcode) != 0))
4815 gen_set_Rc0(ctx, cpu_T[0]);
4816 }
4817
4818 /* srliq */
4819 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4820 {
4821 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4822 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4823 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4824 gen_op_POWER_srlq();
4825 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4826 if (unlikely(Rc(ctx->opcode) != 0))
4827 gen_set_Rc0(ctx, cpu_T[0]);
4828 }
4829
4830 /* srlq */
4831 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4832 {
4833 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4834 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4835 gen_op_POWER_srlq();
4836 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4837 if (unlikely(Rc(ctx->opcode) != 0))
4838 gen_set_Rc0(ctx, cpu_T[0]);
4839 }
4840
4841 /* srq */
4842 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4843 {
4844 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4845 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4846 gen_op_POWER_srq();
4847 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4848 if (unlikely(Rc(ctx->opcode) != 0))
4849 gen_set_Rc0(ctx, cpu_T[0]);
4850 }
4851
4852 /* PowerPC 602 specific instructions */
4853 /* dsa */
4854 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4855 {
4856 /* XXX: TODO */
4857 GEN_EXCP_INVAL(ctx);
4858 }
4859
4860 /* esa */
4861 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4862 {
4863 /* XXX: TODO */
4864 GEN_EXCP_INVAL(ctx);
4865 }
4866
4867 /* mfrom */
4868 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4869 {
4870 #if defined(CONFIG_USER_ONLY)
4871 GEN_EXCP_PRIVOPC(ctx);
4872 #else
4873 if (unlikely(!ctx->supervisor)) {
4874 GEN_EXCP_PRIVOPC(ctx);
4875 return;
4876 }
4877 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4878 gen_op_602_mfrom();
4879 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4880 #endif
4881 }
4882
4883 /* 602 - 603 - G2 TLB management */
4884 /* tlbld */
4885 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4886 {
4887 #if defined(CONFIG_USER_ONLY)
4888 GEN_EXCP_PRIVOPC(ctx);
4889 #else
4890 if (unlikely(!ctx->supervisor)) {
4891 GEN_EXCP_PRIVOPC(ctx);
4892 return;
4893 }
4894 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4895 gen_op_6xx_tlbld();
4896 #endif
4897 }
4898
4899 /* tlbli */
4900 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4901 {
4902 #if defined(CONFIG_USER_ONLY)
4903 GEN_EXCP_PRIVOPC(ctx);
4904 #else
4905 if (unlikely(!ctx->supervisor)) {
4906 GEN_EXCP_PRIVOPC(ctx);
4907 return;
4908 }
4909 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4910 gen_op_6xx_tlbli();
4911 #endif
4912 }
4913
4914 /* 74xx TLB management */
4915 /* tlbld */
4916 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4917 {
4918 #if defined(CONFIG_USER_ONLY)
4919 GEN_EXCP_PRIVOPC(ctx);
4920 #else
4921 if (unlikely(!ctx->supervisor)) {
4922 GEN_EXCP_PRIVOPC(ctx);
4923 return;
4924 }
4925 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4926 gen_op_74xx_tlbld();
4927 #endif
4928 }
4929
4930 /* tlbli */
4931 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4932 {
4933 #if defined(CONFIG_USER_ONLY)
4934 GEN_EXCP_PRIVOPC(ctx);
4935 #else
4936 if (unlikely(!ctx->supervisor)) {
4937 GEN_EXCP_PRIVOPC(ctx);
4938 return;
4939 }
4940 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4941 gen_op_74xx_tlbli();
4942 #endif
4943 }
4944
4945 /* POWER instructions not in PowerPC 601 */
4946 /* clf */
4947 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4948 {
4949 /* Cache line flush: implemented as no-op */
4950 }
4951
4952 /* cli */
4953 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4954 {
4955 /* Cache line invalidate: privileged and treated as no-op */
4956 #if defined(CONFIG_USER_ONLY)
4957 GEN_EXCP_PRIVOPC(ctx);
4958 #else
4959 if (unlikely(!ctx->supervisor)) {
4960 GEN_EXCP_PRIVOPC(ctx);
4961 return;
4962 }
4963 #endif
4964 }
4965
4966 /* dclst */
4967 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4968 {
4969 /* Data cache line store: treated as no-op */
4970 }
4971
4972 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4973 {
4974 #if defined(CONFIG_USER_ONLY)
4975 GEN_EXCP_PRIVOPC(ctx);
4976 #else
4977 if (unlikely(!ctx->supervisor)) {
4978 GEN_EXCP_PRIVOPC(ctx);
4979 return;
4980 }
4981 int ra = rA(ctx->opcode);
4982 int rd = rD(ctx->opcode);
4983
4984 gen_addr_reg_index(cpu_T[0], ctx);
4985 gen_op_POWER_mfsri();
4986 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
4987 if (ra != 0 && ra != rd)
4988 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
4989 #endif
4990 }
4991
4992 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4993 {
4994 #if defined(CONFIG_USER_ONLY)
4995 GEN_EXCP_PRIVOPC(ctx);
4996 #else
4997 if (unlikely(!ctx->supervisor)) {
4998 GEN_EXCP_PRIVOPC(ctx);
4999 return;
5000 }
5001 gen_addr_reg_index(cpu_T[0], ctx);
5002 gen_op_POWER_rac();
5003 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5004 #endif
5005 }
5006
5007 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5008 {
5009 #if defined(CONFIG_USER_ONLY)
5010 GEN_EXCP_PRIVOPC(ctx);
5011 #else
5012 if (unlikely(!ctx->supervisor)) {
5013 GEN_EXCP_PRIVOPC(ctx);
5014 return;
5015 }
5016 gen_op_POWER_rfsvc();
5017 GEN_SYNC(ctx);
5018 #endif
5019 }
5020
5021 /* svc is not implemented for now */
5022
5023 /* POWER2 specific instructions */
5024 /* Quad manipulation (load/store two floats at a time) */
5025 /* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
5026 #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
5027 #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
5028 #define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
5029 #define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
5030 #define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
5031 #define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
5032 #define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
5033 #define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
5034 #define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
5035 #define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
5036 #define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
5037 #define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
5038 #define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
5039 #define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
5040 #define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
5041 #define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
5042 #define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
5043 #define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
5044 static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
5045 GEN_MEM_FUNCS(POWER2_lfq),
5046 };
5047 static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
5048 GEN_MEM_FUNCS(POWER2_stfq),
5049 };
5050
5051 /* lfq */
5052 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5053 {
5054 /* NIP cannot be restored if the memory exception comes from an helper */
5055 gen_update_nip(ctx, ctx->nip - 4);
5056 gen_addr_imm_index(cpu_T[0], ctx, 0);
5057 op_POWER2_lfq();
5058 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5059 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
5060 }
5061
5062 /* lfqu */
5063 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5064 {
5065 int ra = rA(ctx->opcode);
5066
5067 /* NIP cannot be restored if the memory exception comes from an helper */
5068 gen_update_nip(ctx, ctx->nip - 4);
5069 gen_addr_imm_index(cpu_T[0], ctx, 0);
5070 op_POWER2_lfq();
5071 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5072 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
5073 if (ra != 0)
5074 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
5075 }
5076
5077 /* lfqux */
5078 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5079 {
5080 int ra = rA(ctx->opcode);
5081
5082 /* NIP cannot be restored if the memory exception comes from an helper */
5083 gen_update_nip(ctx, ctx->nip - 4);
5084 gen_addr_reg_index(cpu_T[0], ctx);
5085 op_POWER2_lfq();
5086 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5087 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
5088 if (ra != 0)
5089 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
5090 }
5091
5092 /* lfqx */
5093 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5094 {
5095 /* NIP cannot be restored if the memory exception comes from an helper */
5096 gen_update_nip(ctx, ctx->nip - 4);
5097 gen_addr_reg_index(cpu_T[0], ctx);
5098 op_POWER2_lfq();
5099 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5100 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
5101 }
5102
5103 /* stfq */
5104 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5105 {
5106 /* NIP cannot be restored if the memory exception comes from an helper */
5107 gen_update_nip(ctx, ctx->nip - 4);
5108 gen_addr_imm_index(cpu_T[0], ctx, 0);
5109 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5110 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
5111 op_POWER2_stfq();
5112 }
5113
5114 /* stfqu */
5115 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5116 {
5117 int ra = rA(ctx->opcode);
5118
5119 /* NIP cannot be restored if the memory exception comes from an helper */
5120 gen_update_nip(ctx, ctx->nip - 4);
5121 gen_addr_imm_index(cpu_T[0], ctx, 0);
5122 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5123 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
5124 op_POWER2_stfq();
5125 if (ra != 0)
5126 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
5127 }
5128
5129 /* stfqux */
5130 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5131 {
5132 int ra = rA(ctx->opcode);
5133
5134 /* NIP cannot be restored if the memory exception comes from an helper */
5135 gen_update_nip(ctx, ctx->nip - 4);
5136 gen_addr_reg_index(cpu_T[0], ctx);
5137 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5138 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
5139 op_POWER2_stfq();
5140 if (ra != 0)
5141 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
5142 }
5143
5144 /* stfqx */
5145 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5146 {
5147 /* NIP cannot be restored if the memory exception comes from an helper */
5148 gen_update_nip(ctx, ctx->nip - 4);
5149 gen_addr_reg_index(cpu_T[0], ctx);
5150 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5151 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
5152 op_POWER2_stfq();
5153 }
5154
5155 /* BookE specific instructions */
5156 /* XXX: not implemented on 440 ? */
5157 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5158 {
5159 /* XXX: TODO */
5160 GEN_EXCP_INVAL(ctx);
5161 }
5162
5163 /* XXX: not implemented on 440 ? */
5164 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5165 {
5166 #if defined(CONFIG_USER_ONLY)
5167 GEN_EXCP_PRIVOPC(ctx);
5168 #else
5169 if (unlikely(!ctx->supervisor)) {
5170 GEN_EXCP_PRIVOPC(ctx);
5171 return;
5172 }
5173 gen_addr_reg_index(cpu_T[0], ctx);
5174 /* Use the same micro-ops as for tlbie */
5175 #if defined(TARGET_PPC64)
5176 if (ctx->sf_mode)
5177 gen_op_tlbie_64();
5178 else
5179 #endif
5180 gen_op_tlbie();
5181 #endif
5182 }
5183
5184 /* All 405 MAC instructions are translated here */
5185 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5186 int opc2, int opc3,
5187 int ra, int rb, int rt, int Rc)
5188 {
5189 TCGv t0, t1;
5190
5191 t0 = tcg_temp_local_new();
5192 t1 = tcg_temp_local_new();
5193
5194 switch (opc3 & 0x0D) {
5195 case 0x05:
5196 /* macchw - macchw. - macchwo - macchwo. */
5197 /* macchws - macchws. - macchwso - macchwso. */
5198 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5199 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5200 /* mulchw - mulchw. */
5201 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5202 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5203 tcg_gen_ext16s_tl(t1, t1);
5204 break;
5205 case 0x04:
5206 /* macchwu - macchwu. - macchwuo - macchwuo. */
5207 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5208 /* mulchwu - mulchwu. */
5209 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5210 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5211 tcg_gen_ext16u_tl(t1, t1);
5212 break;
5213 case 0x01:
5214 /* machhw - machhw. - machhwo - machhwo. */
5215 /* machhws - machhws. - machhwso - machhwso. */
5216 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5217 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5218 /* mulhhw - mulhhw. */
5219 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5220 tcg_gen_ext16s_tl(t0, t0);
5221 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5222 tcg_gen_ext16s_tl(t1, t1);
5223 break;
5224 case 0x00:
5225 /* machhwu - machhwu. - machhwuo - machhwuo. */
5226 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5227 /* mulhhwu - mulhhwu. */
5228 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5229 tcg_gen_ext16u_tl(t0, t0);
5230 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5231 tcg_gen_ext16u_tl(t1, t1);
5232 break;
5233 case 0x0D:
5234 /* maclhw - maclhw. - maclhwo - maclhwo. */
5235 /* maclhws - maclhws. - maclhwso - maclhwso. */
5236 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5237 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5238 /* mullhw - mullhw. */
5239 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5240 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5241 break;
5242 case 0x0C:
5243 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5244 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5245 /* mullhwu - mullhwu. */
5246 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5247 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5248 break;
5249 }
5250 if (opc2 & 0x04) {
5251 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5252 tcg_gen_mul_tl(t1, t0, t1);
5253 if (opc2 & 0x02) {
5254 /* nmultiply-and-accumulate (0x0E) */
5255 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5256 } else {
5257 /* multiply-and-accumulate (0x0C) */
5258 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5259 }
5260
5261 if (opc3 & 0x12) {
5262 /* Check overflow and/or saturate */
5263 int l1 = gen_new_label();
5264
5265 if (opc3 & 0x10) {
5266 /* Start with XER OV disabled, the most likely case */
5267 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5268 }
5269 if (opc3 & 0x01) {
5270 /* Signed */
5271 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5272 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5273 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5274 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5275 if (opc3 & 0x02) {
5276 /* Saturate */
5277 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5278 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5279 }
5280 } else {
5281 /* Unsigned */
5282 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5283 if (opc3 & 0x02) {
5284 /* Saturate */
5285 tcg_gen_movi_tl(t0, UINT32_MAX);
5286 }
5287 }
5288 if (opc3 & 0x10) {
5289 /* Check overflow */
5290 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5291 }
5292 gen_set_label(l1);
5293 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5294 }
5295 } else {
5296 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5297 }
5298 tcg_temp_free(t0);
5299 tcg_temp_free(t1);
5300 if (unlikely(Rc) != 0) {
5301 /* Update Rc0 */
5302 gen_set_Rc0(ctx, cpu_gpr[rt]);
5303 }
5304 }
5305
5306 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5307 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5308 { \
5309 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5310 rD(ctx->opcode), Rc(ctx->opcode)); \
5311 }
5312
5313 /* macchw - macchw. */
5314 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5315 /* macchwo - macchwo. */
5316 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5317 /* macchws - macchws. */
5318 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5319 /* macchwso - macchwso. */
5320 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5321 /* macchwsu - macchwsu. */
5322 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5323 /* macchwsuo - macchwsuo. */
5324 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5325 /* macchwu - macchwu. */
5326 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5327 /* macchwuo - macchwuo. */
5328 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5329 /* machhw - machhw. */
5330 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5331 /* machhwo - machhwo. */
5332 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5333 /* machhws - machhws. */
5334 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5335 /* machhwso - machhwso. */
5336 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5337 /* machhwsu - machhwsu. */
5338 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5339 /* machhwsuo - machhwsuo. */
5340 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5341 /* machhwu - machhwu. */
5342 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5343 /* machhwuo - machhwuo. */
5344 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5345 /* maclhw - maclhw. */
5346 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5347 /* maclhwo - maclhwo. */
5348 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5349 /* maclhws - maclhws. */
5350 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5351 /* maclhwso - maclhwso. */
5352 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5353 /* maclhwu - maclhwu. */
5354 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5355 /* maclhwuo - maclhwuo. */
5356 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5357 /* maclhwsu - maclhwsu. */
5358 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5359 /* maclhwsuo - maclhwsuo. */
5360 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5361 /* nmacchw - nmacchw. */
5362 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5363 /* nmacchwo - nmacchwo. */
5364 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5365 /* nmacchws - nmacchws. */
5366 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5367 /* nmacchwso - nmacchwso. */
5368 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5369 /* nmachhw - nmachhw. */
5370 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5371 /* nmachhwo - nmachhwo. */
5372 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5373 /* nmachhws - nmachhws. */
5374 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5375 /* nmachhwso - nmachhwso. */
5376 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5377 /* nmaclhw - nmaclhw. */
5378 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5379 /* nmaclhwo - nmaclhwo. */
5380 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5381 /* nmaclhws - nmaclhws. */
5382 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5383 /* nmaclhwso - nmaclhwso. */
5384 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5385
5386 /* mulchw - mulchw. */
5387 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5388 /* mulchwu - mulchwu. */
5389 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5390 /* mulhhw - mulhhw. */
5391 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5392 /* mulhhwu - mulhhwu. */
5393 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5394 /* mullhw - mullhw. */
5395 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5396 /* mullhwu - mullhwu. */
5397 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5398
5399 /* mfdcr */
5400 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5401 {
5402 #if defined(CONFIG_USER_ONLY)
5403 GEN_EXCP_PRIVREG(ctx);
5404 #else
5405 uint32_t dcrn = SPR(ctx->opcode);
5406
5407 if (unlikely(!ctx->supervisor)) {
5408 GEN_EXCP_PRIVREG(ctx);
5409 return;
5410 }
5411 tcg_gen_movi_tl(cpu_T[0], dcrn);
5412 gen_op_load_dcr();
5413 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5414 #endif
5415 }
5416
5417 /* mtdcr */
5418 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5419 {
5420 #if defined(CONFIG_USER_ONLY)
5421 GEN_EXCP_PRIVREG(ctx);
5422 #else
5423 uint32_t dcrn = SPR(ctx->opcode);
5424
5425 if (unlikely(!ctx->supervisor)) {
5426 GEN_EXCP_PRIVREG(ctx);
5427 return;
5428 }
5429 tcg_gen_movi_tl(cpu_T[0], dcrn);
5430 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5431 gen_op_store_dcr();
5432 #endif
5433 }
5434
5435 /* mfdcrx */
5436 /* XXX: not implemented on 440 ? */
5437 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5438 {
5439 #if defined(CONFIG_USER_ONLY)
5440 GEN_EXCP_PRIVREG(ctx);
5441 #else
5442 if (unlikely(!ctx->supervisor)) {
5443 GEN_EXCP_PRIVREG(ctx);
5444 return;
5445 }
5446 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5447 gen_op_load_dcr();
5448 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5449 /* Note: Rc update flag set leads to undefined state of Rc0 */
5450 #endif
5451 }
5452
5453 /* mtdcrx */
5454 /* XXX: not implemented on 440 ? */
5455 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5456 {
5457 #if defined(CONFIG_USER_ONLY)
5458 GEN_EXCP_PRIVREG(ctx);
5459 #else
5460 if (unlikely(!ctx->supervisor)) {
5461 GEN_EXCP_PRIVREG(ctx);
5462 return;
5463 }
5464 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5465 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5466 gen_op_store_dcr();
5467 /* Note: Rc update flag set leads to undefined state of Rc0 */
5468 #endif
5469 }
5470
5471 /* mfdcrux (PPC 460) : user-mode access to DCR */
5472 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5473 {
5474 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5475 gen_op_load_dcr();
5476 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5477 /* Note: Rc update flag set leads to undefined state of Rc0 */
5478 }
5479
5480 /* mtdcrux (PPC 460) : user-mode access to DCR */
5481 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5482 {
5483 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5484 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5485 gen_op_store_dcr();
5486 /* Note: Rc update flag set leads to undefined state of Rc0 */
5487 }
5488
5489 /* dccci */
5490 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5491 {
5492 #if defined(CONFIG_USER_ONLY)
5493 GEN_EXCP_PRIVOPC(ctx);
5494 #else
5495 if (unlikely(!ctx->supervisor)) {
5496 GEN_EXCP_PRIVOPC(ctx);
5497 return;
5498 }
5499 /* interpreted as no-op */
5500 #endif
5501 }
5502
5503 /* dcread */
5504 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5505 {
5506 #if defined(CONFIG_USER_ONLY)
5507 GEN_EXCP_PRIVOPC(ctx);
5508 #else
5509 TCGv EA, val;
5510 if (unlikely(!ctx->supervisor)) {
5511 GEN_EXCP_PRIVOPC(ctx);
5512 return;
5513 }
5514 EA = tcg_temp_new();
5515 gen_addr_reg_index(EA, ctx);
5516 val = tcg_temp_new();
5517 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5518 tcg_temp_free(val);
5519 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5520 tcg_temp_free(EA);
5521 #endif
5522 }
5523
5524 /* icbt */
5525 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5526 {
5527 /* interpreted as no-op */
5528 /* XXX: specification say this is treated as a load by the MMU
5529 * but does not generate any exception
5530 */
5531 }
5532
5533 /* iccci */
5534 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5535 {
5536 #if defined(CONFIG_USER_ONLY)
5537 GEN_EXCP_PRIVOPC(ctx);
5538 #else
5539 if (unlikely(!ctx->supervisor)) {
5540 GEN_EXCP_PRIVOPC(ctx);
5541 return;
5542 }
5543 /* interpreted as no-op */
5544 #endif
5545 }
5546
5547 /* icread */
5548 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5549 {
5550 #if defined(CONFIG_USER_ONLY)
5551 GEN_EXCP_PRIVOPC(ctx);
5552 #else
5553 if (unlikely(!ctx->supervisor)) {
5554 GEN_EXCP_PRIVOPC(ctx);
5555 return;
5556 }
5557 /* interpreted as no-op */
5558 #endif
5559 }
5560
5561 /* rfci (supervisor only) */
5562 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5563 {
5564 #if defined(CONFIG_USER_ONLY)
5565 GEN_EXCP_PRIVOPC(ctx);
5566 #else
5567 if (unlikely(!ctx->supervisor)) {
5568 GEN_EXCP_PRIVOPC(ctx);
5569 return;
5570 }
5571 /* Restore CPU state */
5572 gen_op_40x_rfci();
5573 GEN_SYNC(ctx);
5574 #endif
5575 }
5576
5577 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5578 {
5579 #if defined(CONFIG_USER_ONLY)
5580 GEN_EXCP_PRIVOPC(ctx);
5581 #else
5582 if (unlikely(!ctx->supervisor)) {
5583 GEN_EXCP_PRIVOPC(ctx);
5584 return;
5585 }
5586 /* Restore CPU state */
5587 gen_op_rfci();
5588 GEN_SYNC(ctx);
5589 #endif
5590 }
5591
5592 /* BookE specific */
5593 /* XXX: not implemented on 440 ? */
5594 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5595 {
5596 #if defined(CONFIG_USER_ONLY)
5597 GEN_EXCP_PRIVOPC(ctx);
5598 #else
5599 if (unlikely(!ctx->supervisor)) {
5600 GEN_EXCP_PRIVOPC(ctx);
5601 return;
5602 }
5603 /* Restore CPU state */
5604 gen_op_rfdi();
5605 GEN_SYNC(ctx);
5606 #endif
5607 }
5608
5609 /* XXX: not implemented on 440 ? */
5610 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5611 {
5612 #if defined(CONFIG_USER_ONLY)
5613 GEN_EXCP_PRIVOPC(ctx);
5614 #else
5615 if (unlikely(!ctx->supervisor)) {
5616 GEN_EXCP_PRIVOPC(ctx);
5617 return;
5618 }
5619 /* Restore CPU state */
5620 gen_op_rfmci();
5621 GEN_SYNC(ctx);
5622 #endif
5623 }
5624
5625 /* TLB management - PowerPC 405 implementation */
5626 /* tlbre */
5627 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5628 {
5629 #if defined(CONFIG_USER_ONLY)
5630 GEN_EXCP_PRIVOPC(ctx);
5631 #else
5632 if (unlikely(!ctx->supervisor)) {
5633 GEN_EXCP_PRIVOPC(ctx);
5634 return;
5635 }
5636 switch (rB(ctx->opcode)) {
5637 case 0:
5638 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5639 gen_op_4xx_tlbre_hi();
5640 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5641 break;
5642 case 1:
5643 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5644 gen_op_4xx_tlbre_lo();
5645 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5646 break;
5647 default:
5648 GEN_EXCP_INVAL(ctx);
5649 break;
5650 }
5651 #endif
5652 }
5653
5654 /* tlbsx - tlbsx. */
5655 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5656 {
5657 #if defined(CONFIG_USER_ONLY)
5658 GEN_EXCP_PRIVOPC(ctx);
5659 #else
5660 if (unlikely(!ctx->supervisor)) {
5661 GEN_EXCP_PRIVOPC(ctx);
5662 return;
5663 }
5664 gen_addr_reg_index(cpu_T[0], ctx);
5665 gen_op_4xx_tlbsx();
5666 if (Rc(ctx->opcode))
5667 gen_op_4xx_tlbsx_check();
5668 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5669 #endif
5670 }
5671
5672 /* tlbwe */
5673 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5674 {
5675 #if defined(CONFIG_USER_ONLY)
5676 GEN_EXCP_PRIVOPC(ctx);
5677 #else
5678 if (unlikely(!ctx->supervisor)) {
5679 GEN_EXCP_PRIVOPC(ctx);
5680 return;
5681 }
5682 switch (rB(ctx->opcode)) {
5683 case 0:
5684 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5685 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5686 gen_op_4xx_tlbwe_hi();
5687 break;
5688 case 1:
5689 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5690 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5691 gen_op_4xx_tlbwe_lo();
5692 break;
5693 default:
5694 GEN_EXCP_INVAL(ctx);
5695 break;
5696 }
5697 #endif
5698 }
5699
5700 /* TLB management - PowerPC 440 implementation */
5701 /* tlbre */
5702 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5703 {
5704 #if defined(CONFIG_USER_ONLY)
5705 GEN_EXCP_PRIVOPC(ctx);
5706 #else
5707 if (unlikely(!ctx->supervisor)) {
5708 GEN_EXCP_PRIVOPC(ctx);
5709 return;
5710 }
5711 switch (rB(ctx->opcode)) {
5712 case 0:
5713 case 1:
5714 case 2:
5715 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5716 gen_op_440_tlbre(rB(ctx->opcode));
5717 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5718 break;
5719 default:
5720 GEN_EXCP_INVAL(ctx);
5721 break;
5722 }
5723 #endif
5724 }
5725
5726 /* tlbsx - tlbsx. */
5727 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5728 {
5729 #if defined(CONFIG_USER_ONLY)
5730 GEN_EXCP_PRIVOPC(ctx);
5731 #else
5732 if (unlikely(!ctx->supervisor)) {
5733 GEN_EXCP_PRIVOPC(ctx);
5734 return;
5735 }
5736 gen_addr_reg_index(cpu_T[0], ctx);
5737 gen_op_440_tlbsx();
5738 if (Rc(ctx->opcode))
5739 gen_op_4xx_tlbsx_check();
5740 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5741 #endif
5742 }
5743
5744 /* tlbwe */
5745 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5746 {
5747 #if defined(CONFIG_USER_ONLY)
5748 GEN_EXCP_PRIVOPC(ctx);
5749 #else
5750 if (unlikely(!ctx->supervisor)) {
5751 GEN_EXCP_PRIVOPC(ctx);
5752 return;
5753 }
5754 switch (rB(ctx->opcode)) {
5755 case 0:
5756 case 1:
5757 case 2:
5758 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5759 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5760 gen_op_440_tlbwe(rB(ctx->opcode));
5761 break;
5762 default:
5763 GEN_EXCP_INVAL(ctx);
5764 break;
5765 }
5766 #endif
5767 }
5768
5769 /* wrtee */
5770 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
5771 {
5772 #if defined(CONFIG_USER_ONLY)
5773 GEN_EXCP_PRIVOPC(ctx);
5774 #else
5775 if (unlikely(!ctx->supervisor)) {
5776 GEN_EXCP_PRIVOPC(ctx);
5777 return;
5778 }
5779 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
5780 gen_op_wrte();
5781 /* Stop translation to have a chance to raise an exception
5782 * if we just set msr_ee to 1
5783 */
5784 GEN_STOP(ctx);
5785 #endif
5786 }
5787
5788 /* wrteei */
5789 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
5790 {
5791 #if defined(CONFIG_USER_ONLY)
5792 GEN_EXCP_PRIVOPC(ctx);
5793 #else
5794 if (unlikely(!ctx->supervisor)) {
5795 GEN_EXCP_PRIVOPC(ctx);
5796 return;
5797 }
5798 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
5799 gen_op_wrte();
5800 /* Stop translation to have a chance to raise an exception
5801 * if we just set msr_ee to 1
5802 */
5803 GEN_STOP(ctx);
5804 #endif
5805 }
5806
5807 /* PowerPC 440 specific instructions */
5808 /* dlmzb */
5809 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5810 {
5811 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5812 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
5813 gen_op_440_dlmzb();
5814 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
5815 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5816 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
5817 if (Rc(ctx->opcode)) {
5818 gen_op_440_dlmzb_update_Rc();
5819 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_T[0]);
5820 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 0xf);
5821 }
5822 }
5823
5824 /* mbar replaces eieio on 440 */
5825 GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5826 {
5827 /* interpreted as no-op */
5828 }
5829
5830 /* msync replaces sync on 440 */
5831 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
5832 {
5833 /* interpreted as no-op */
5834 }
5835
5836 /* icbt */
5837 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
5838 {
5839 /* interpreted as no-op */
5840 /* XXX: specification say this is treated as a load by the MMU
5841 * but does not generate any exception
5842 */
5843 }
5844
5845 /*** Altivec vector extension ***/
5846 /* Altivec registers moves */
5847
5848 static always_inline void gen_load_avr(int t, int reg) {
5849 tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5850 tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5851 }
5852
5853 static always_inline void gen_store_avr(int reg, int t) {
5854 tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5855 tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5856 }
5857
5858 #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5859 #define OP_VR_LD_TABLE(name) \
5860 static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5861 GEN_MEM_FUNCS(vr_l##name), \
5862 };
5863 #define OP_VR_ST_TABLE(name) \
5864 static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5865 GEN_MEM_FUNCS(vr_st##name), \
5866 };
5867
5868 #define GEN_VR_LDX(name, opc2, opc3) \
5869 GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5870 { \
5871 if (unlikely(!ctx->altivec_enabled)) { \
5872 GEN_EXCP_NO_VR(ctx); \
5873 return; \
5874 } \
5875 gen_addr_reg_index(cpu_T[0], ctx); \
5876 op_vr_ldst(vr_l##name); \
5877 gen_store_avr(rD(ctx->opcode), 0); \
5878 }
5879
5880 #define GEN_VR_STX(name, opc2, opc3) \
5881 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5882 { \
5883 if (unlikely(!ctx->altivec_enabled)) { \
5884 GEN_EXCP_NO_VR(ctx); \
5885 return; \
5886 } \
5887 gen_addr_reg_index(cpu_T[0], ctx); \
5888 gen_load_avr(0, rS(ctx->opcode)); \
5889 op_vr_ldst(vr_st##name); \
5890 }
5891
5892 OP_VR_LD_TABLE(vx);
5893 GEN_VR_LDX(vx, 0x07, 0x03);
5894 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5895 #define gen_op_vr_lvxl gen_op_vr_lvx
5896 GEN_VR_LDX(vxl, 0x07, 0x0B);
5897
5898 OP_VR_ST_TABLE(vx);
5899 GEN_VR_STX(vx, 0x07, 0x07);
5900 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5901 #define gen_op_vr_stvxl gen_op_vr_stvx
5902 GEN_VR_STX(vxl, 0x07, 0x0F);
5903
5904 /*** SPE extension ***/
5905 /* Register moves */
5906
5907 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
5908 #if defined(TARGET_PPC64)
5909 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5910 #else
5911 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
5912 #endif
5913 }
5914
5915 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
5916 #if defined(TARGET_PPC64)
5917 tcg_gen_mov_i64(cpu_gpr[reg], t);
5918 #else
5919 TCGv_i64 tmp = tcg_temp_new_i64();
5920 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
5921 tcg_gen_shri_i64(tmp, t, 32);
5922 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5923 tcg_temp_free_i64(tmp);
5924 #endif
5925 }
5926
5927 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5928 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5929 { \
5930 if (Rc(ctx->opcode)) \
5931 gen_##name1(ctx); \
5932 else \
5933 gen_##name0(ctx); \
5934 }
5935
5936 /* Handler for undefined SPE opcodes */
5937 static always_inline void gen_speundef (DisasContext *ctx)
5938 {
5939 GEN_EXCP_INVAL(ctx);
5940 }
5941
5942 /* SPE load and stores */
5943 static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
5944 {
5945 target_long simm = rB(ctx->opcode);
5946
5947 if (rA(ctx->opcode) == 0)
5948 tcg_gen_movi_tl(EA, simm << sh);
5949 else if (likely(simm != 0))
5950 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
5951 else
5952 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
5953 }
5954
5955 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5956 #define OP_SPE_LD_TABLE(name) \
5957 static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5958 GEN_MEM_FUNCS(spe_l##name), \
5959 };
5960 #define OP_SPE_ST_TABLE(name) \
5961 static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5962 GEN_MEM_FUNCS(spe_st##name), \
5963 };
5964
5965 #define GEN_SPE_LD(name, sh) \
5966 static always_inline void gen_evl##name (DisasContext *ctx) \
5967 { \
5968 if (unlikely(!ctx->spe_enabled)) { \
5969 GEN_EXCP_NO_AP(ctx); \
5970 return; \
5971 } \
5972 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
5973 op_spe_ldst(spe_l##name); \
5974 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
5975 }
5976
5977 #define GEN_SPE_LDX(name) \
5978 static always_inline void gen_evl##name##x (DisasContext *ctx) \
5979 { \
5980 if (unlikely(!ctx->spe_enabled)) { \
5981 GEN_EXCP_NO_AP(ctx); \
5982 return; \
5983 } \
5984 gen_addr_reg_index(cpu_T[0], ctx); \
5985 op_spe_ldst(spe_l##name); \
5986 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
5987 }
5988
5989 #define GEN_SPEOP_LD(name, sh) \
5990 OP_SPE_LD_TABLE(name); \
5991 GEN_SPE_LD(name, sh); \
5992 GEN_SPE_LDX(name)
5993
5994 #define GEN_SPE_ST(name, sh) \
5995 static always_inline void gen_evst##name (DisasContext *ctx) \
5996 { \
5997 if (unlikely(!ctx->spe_enabled)) { \
5998 GEN_EXCP_NO_AP(ctx); \
5999 return; \
6000 } \
6001 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
6002 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
6003 op_spe_ldst(spe_st##name); \
6004 }
6005
6006 #define GEN_SPE_STX(name) \
6007 static always_inline void gen_evst##name##x (DisasContext *ctx) \
6008 { \
6009 if (unlikely(!ctx->spe_enabled)) { \
6010 GEN_EXCP_NO_AP(ctx); \
6011 return; \
6012 } \
6013 gen_addr_reg_index(cpu_T[0], ctx); \
6014 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
6015 op_spe_ldst(spe_st##name); \
6016 }
6017
6018 #define GEN_SPEOP_ST(name, sh) \
6019 OP_SPE_ST_TABLE(name); \
6020 GEN_SPE_ST(name, sh); \
6021 GEN_SPE_STX(name)
6022
6023 #define GEN_SPEOP_LDST(name, sh) \
6024 GEN_SPEOP_LD(name, sh); \
6025 GEN_SPEOP_ST(name, sh)
6026
6027 /* SPE logic */
6028 #if defined(TARGET_PPC64)
6029 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6030 static always_inline void gen_##name (DisasContext *ctx) \
6031 { \
6032 if (unlikely(!ctx->spe_enabled)) { \
6033 GEN_EXCP_NO_AP(ctx); \
6034 return; \
6035 } \
6036 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6037 cpu_gpr[rB(ctx->opcode)]); \
6038 }
6039 #else
6040 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6041 static always_inline void gen_##name (DisasContext *ctx) \
6042 { \
6043 if (unlikely(!ctx->spe_enabled)) { \
6044 GEN_EXCP_NO_AP(ctx); \
6045 return; \
6046 } \
6047 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6048 cpu_gpr[rB(ctx->opcode)]); \
6049 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6050 cpu_gprh[rB(ctx->opcode)]); \
6051 }
6052 #endif
6053
6054 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6055 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6056 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6057 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6058 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6059 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6060 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6061 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6062
6063 /* SPE logic immediate */
6064 #if defined(TARGET_PPC64)
6065 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6066 static always_inline void gen_##name (DisasContext *ctx) \
6067 { \
6068 if (unlikely(!ctx->spe_enabled)) { \
6069 GEN_EXCP_NO_AP(ctx); \
6070 return; \
6071 } \
6072 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6073 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6074 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6075 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6076 tcg_opi(t0, t0, rB(ctx->opcode)); \
6077 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6078 tcg_gen_trunc_i64_i32(t1, t2); \
6079 tcg_temp_free_i64(t2); \
6080 tcg_opi(t1, t1, rB(ctx->opcode)); \
6081 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6082 tcg_temp_free_i32(t0); \
6083 tcg_temp_free_i32(t1); \
6084 }
6085 #else
6086 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6087 static always_inline void gen_##name (DisasContext *ctx) \
6088 { \
6089 if (unlikely(!ctx->spe_enabled)) { \
6090 GEN_EXCP_NO_AP(ctx); \
6091 return; \
6092 } \
6093 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6094 rB(ctx->opcode)); \
6095 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6096 rB(ctx->opcode)); \
6097 }
6098 #endif
6099 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6100 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6101 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6102 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6103
6104 /* SPE arithmetic */
6105 #if defined(TARGET_PPC64)
6106 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6107 static always_inline void gen_##name (DisasContext *ctx) \
6108 { \
6109 if (unlikely(!ctx->spe_enabled)) { \
6110 GEN_EXCP_NO_AP(ctx); \
6111 return; \
6112 } \
6113 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6114 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6115 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6116 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6117 tcg_op(t0, t0); \
6118 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6119 tcg_gen_trunc_i64_i32(t1, t2); \
6120 tcg_temp_free_i64(t2); \
6121 tcg_op(t1, t1); \
6122 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6123 tcg_temp_free_i32(t0); \
6124 tcg_temp_free_i32(t1); \
6125 }
6126 #else
6127 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6128 static always_inline void gen_##name (DisasContext *ctx) \
6129 { \
6130 if (unlikely(!ctx->spe_enabled)) { \
6131 GEN_EXCP_NO_AP(ctx); \
6132 return; \
6133 } \
6134 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6135 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6136 }
6137 #endif
6138
6139 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6140 {
6141 int l1 = gen_new_label();
6142 int l2 = gen_new_label();
6143
6144 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6145 tcg_gen_neg_i32(ret, arg1);
6146 tcg_gen_br(l2);
6147 gen_set_label(l1);
6148 tcg_gen_mov_i32(ret, arg1);
6149 gen_set_label(l2);
6150 }
6151 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6152 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6153 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6154 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6155 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6156 {
6157 tcg_gen_addi_i32(ret, arg1, 0x8000);
6158 tcg_gen_ext16u_i32(ret, ret);
6159 }
6160 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6161 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6162 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6163
6164 #if defined(TARGET_PPC64)
6165 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6166 static always_inline void gen_##name (DisasContext *ctx) \
6167 { \
6168 if (unlikely(!ctx->spe_enabled)) { \
6169 GEN_EXCP_NO_AP(ctx); \
6170 return; \
6171 } \
6172 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6173 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6174 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6175 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
6176 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6177 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6178 tcg_op(t0, t0, t2); \
6179 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6180 tcg_gen_trunc_i64_i32(t1, t3); \
6181 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6182 tcg_gen_trunc_i64_i32(t2, t3); \
6183 tcg_temp_free_i64(t3); \
6184 tcg_op(t1, t1, t2); \
6185 tcg_temp_free_i32(t2); \
6186 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6187 tcg_temp_free_i32(t0); \
6188 tcg_temp_free_i32(t1); \
6189 }
6190 #else
6191 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6192 static always_inline void gen_##name (DisasContext *ctx) \
6193 { \
6194 if (unlikely(!ctx->spe_enabled)) { \
6195 GEN_EXCP_NO_AP(ctx); \
6196 return; \
6197 } \
6198 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6199 cpu_gpr[rB(ctx->opcode)]); \
6200 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6201 cpu_gprh[rB(ctx->opcode)]); \
6202 }
6203 #endif
6204
6205 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6206 {
6207 TCGv_i32 t0;
6208 int l1, l2;
6209
6210 l1 = gen_new_label();
6211 l2 = gen_new_label();
6212 t0 = tcg_temp_local_new_i32();
6213 /* No error here: 6 bits are used */
6214 tcg_gen_andi_i32(t0, arg2, 0x3F);
6215 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6216 tcg_gen_shr_i32(ret, arg1, t0);
6217 tcg_gen_br(l2);
6218 gen_set_label(l1);
6219 tcg_gen_movi_i32(ret, 0);
6220 tcg_gen_br(l2);
6221 tcg_temp_free_i32(t0);
6222 }
6223 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6224 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6225 {
6226 TCGv_i32 t0;
6227 int l1, l2;
6228
6229 l1 = gen_new_label();
6230 l2 = gen_new_label();
6231 t0 = tcg_temp_local_new_i32();
6232 /* No error here: 6 bits are used */
6233 tcg_gen_andi_i32(t0, arg2, 0x3F);
6234 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6235 tcg_gen_sar_i32(ret, arg1, t0);
6236 tcg_gen_br(l2);
6237 gen_set_label(l1);
6238 tcg_gen_movi_i32(ret, 0);
6239 tcg_gen_br(l2);
6240 tcg_temp_free_i32(t0);
6241 }
6242 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6243 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6244 {
6245 TCGv_i32 t0;
6246 int l1, l2;
6247
6248 l1 = gen_new_label();
6249 l2 = gen_new_label();
6250 t0 = tcg_temp_local_new_i32();
6251 /* No error here: 6 bits are used */
6252 tcg_gen_andi_i32(t0, arg2, 0x3F);
6253 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6254 tcg_gen_shl_i32(ret, arg1, t0);
6255 tcg_gen_br(l2);
6256 gen_set_label(l1);
6257 tcg_gen_movi_i32(ret, 0);
6258 tcg_gen_br(l2);
6259 tcg_temp_free_i32(t0);
6260 }
6261 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6262 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6263 {
6264 TCGv_i32 t0 = tcg_temp_new_i32();
6265 tcg_gen_andi_i32(t0, arg2, 0x1F);
6266 tcg_gen_rotl_i32(ret, arg1, t0);
6267 tcg_temp_free_i32(t0);
6268 }
6269 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6270 static always_inline void gen_evmergehi (DisasContext *ctx)
6271 {
6272 if (unlikely(!ctx->spe_enabled)) {
6273 GEN_EXCP_NO_AP(ctx);
6274 return;
6275 }
6276 #if defined(TARGET_PPC64)
6277 TCGv t0 = tcg_temp_new();
6278 TCGv t1 = tcg_temp_new();
6279 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6280 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6281 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6282 tcg_temp_free(t0);
6283 tcg_temp_free(t1);
6284 #else
6285 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6286 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6287 #endif
6288 }
6289 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6290 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6291 {
6292 tcg_gen_sub_i32(ret, arg2, arg1);
6293 }
6294 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6295
6296 /* SPE arithmetic immediate */
6297 #if defined(TARGET_PPC64)
6298 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6299 static always_inline void gen_##name (DisasContext *ctx) \
6300 { \
6301 if (unlikely(!ctx->spe_enabled)) { \
6302 GEN_EXCP_NO_AP(ctx); \
6303 return; \
6304 } \
6305 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6306 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6307 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6308 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6309 tcg_op(t0, t0, rA(ctx->opcode)); \
6310 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6311 tcg_gen_trunc_i64_i32(t1, t2); \
6312 tcg_temp_free_i64(t2); \
6313 tcg_op(t1, t1, rA(ctx->opcode)); \
6314 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6315 tcg_temp_free_i32(t0); \
6316 tcg_temp_free_i32(t1); \
6317 }
6318 #else
6319 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6320 static always_inline void gen_##name (DisasContext *ctx) \
6321 { \
6322 if (unlikely(!ctx->spe_enabled)) { \
6323 GEN_EXCP_NO_AP(ctx); \
6324 return; \
6325 } \
6326 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6327 rA(ctx->opcode)); \
6328 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6329 rA(ctx->opcode)); \
6330 }
6331 #endif
6332 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6333 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6334
6335 /* SPE comparison */
6336 #if defined(TARGET_PPC64)
6337 #define GEN_SPEOP_COMP(name, tcg_cond) \
6338 static always_inline void gen_##name (DisasContext *ctx) \
6339 { \
6340 if (unlikely(!ctx->spe_enabled)) { \
6341 GEN_EXCP_NO_AP(ctx); \
6342 return; \
6343 } \
6344 int l1 = gen_new_label(); \
6345 int l2 = gen_new_label(); \
6346 int l3 = gen_new_label(); \
6347 int l4 = gen_new_label(); \
6348 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6349 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6350 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6351 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6352 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6353 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6354 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6355 tcg_gen_br(l2); \
6356 gen_set_label(l1); \
6357 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6358 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6359 gen_set_label(l2); \
6360 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6361 tcg_gen_trunc_i64_i32(t0, t2); \
6362 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6363 tcg_gen_trunc_i64_i32(t1, t2); \
6364 tcg_temp_free_i64(t2); \
6365 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6366 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6367 ~(CRF_CH | CRF_CH_AND_CL)); \
6368 tcg_gen_br(l4); \
6369 gen_set_label(l3); \
6370 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6371 CRF_CH | CRF_CH_OR_CL); \
6372 gen_set_label(l4); \
6373 tcg_temp_free_i32(t0); \
6374 tcg_temp_free_i32(t1); \
6375 }
6376 #else
6377 #define GEN_SPEOP_COMP(name, tcg_cond) \
6378 static always_inline void gen_##name (DisasContext *ctx) \
6379 { \
6380 if (unlikely(!ctx->spe_enabled)) { \
6381 GEN_EXCP_NO_AP(ctx); \
6382 return; \
6383 } \
6384 int l1 = gen_new_label(); \
6385 int l2 = gen_new_label(); \
6386 int l3 = gen_new_label(); \
6387 int l4 = gen_new_label(); \
6388 \
6389 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6390 cpu_gpr[rB(ctx->opcode)], l1); \
6391 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6392 tcg_gen_br(l2); \
6393 gen_set_label(l1); \
6394 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6395 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6396 gen_set_label(l2); \
6397 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6398 cpu_gprh[rB(ctx->opcode)], l3); \
6399 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6400 ~(CRF_CH | CRF_CH_AND_CL)); \
6401 tcg_gen_br(l4); \
6402 gen_set_label(l3); \
6403 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6404 CRF_CH | CRF_CH_OR_CL); \
6405 gen_set_label(l4); \
6406 }
6407 #endif
6408 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6409 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6410 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6411 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6412 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6413
6414 /* SPE misc */
6415 static always_inline void gen_brinc (DisasContext *ctx)
6416 {
6417 /* Note: brinc is usable even if SPE is disabled */
6418 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6419 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6420 }
6421 static always_inline void gen_evmergelo (DisasContext *ctx)
6422 {
6423 if (unlikely(!ctx->spe_enabled)) {
6424 GEN_EXCP_NO_AP(ctx);
6425 return;
6426 }
6427 #if defined(TARGET_PPC64)
6428 TCGv t0 = tcg_temp_new();
6429 TCGv t1 = tcg_temp_new();
6430 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6431 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6432 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6433 tcg_temp_free(t0);
6434 tcg_temp_free(t1);
6435 #else
6436 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6437 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6438 #endif
6439 }
6440 static always_inline void gen_evmergehilo (DisasContext *ctx)
6441 {
6442 if (unlikely(!ctx->spe_enabled)) {
6443 GEN_EXCP_NO_AP(ctx);
6444 return;
6445 }
6446 #if defined(TARGET_PPC64)
6447 TCGv t0 = tcg_temp_new();
6448 TCGv t1 = tcg_temp_new();
6449 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6450 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6451 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6452 tcg_temp_free(t0);
6453 tcg_temp_free(t1);
6454 #else
6455 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6456 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6457 #endif
6458 }
6459 static always_inline void gen_evmergelohi (DisasContext *ctx)
6460 {
6461 if (unlikely(!ctx->spe_enabled)) {
6462 GEN_EXCP_NO_AP(ctx);
6463 return;
6464 }
6465 #if defined(TARGET_PPC64)
6466 TCGv t0 = tcg_temp_new();
6467 TCGv t1 = tcg_temp_new();
6468 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6469 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6470 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6471 tcg_temp_free(t0);
6472 tcg_temp_free(t1);
6473 #else
6474 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6475 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6476 #endif
6477 }
6478 static always_inline void gen_evsplati (DisasContext *ctx)
6479 {
6480 int32_t imm = (int32_t)(rA(ctx->opcode) << 11) >> 27;
6481
6482 #if defined(TARGET_PPC64)
6483 TCGv t0 = tcg_temp_new();
6484 TCGv t1 = tcg_temp_new();
6485 tcg_gen_movi_tl(t0, imm);
6486 tcg_gen_shri_tl(t1, t0, 32);
6487 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6488 tcg_temp_free(t0);
6489 tcg_temp_free(t1);
6490 #else
6491 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6492 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6493 #endif
6494 }
6495 static always_inline void gen_evsplatfi (DisasContext *ctx)
6496 {
6497 uint32_t imm = rA(ctx->opcode) << 11;
6498
6499 #if defined(TARGET_PPC64)
6500 TCGv t0 = tcg_temp_new();
6501 TCGv t1 = tcg_temp_new();
6502 tcg_gen_movi_tl(t0, imm);
6503 tcg_gen_shri_tl(t1, t0, 32);
6504 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6505 tcg_temp_free(t0);
6506 tcg_temp_free(t1);
6507 #else
6508 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6509 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6510 #endif
6511 }
6512
6513 static always_inline void gen_evsel (DisasContext *ctx)
6514 {
6515 int l1 = gen_new_label();
6516 int l2 = gen_new_label();
6517 int l3 = gen_new_label();
6518 int l4 = gen_new_label();
6519 TCGv_i32 t0 = tcg_temp_local_new_i32();
6520 #if defined(TARGET_PPC64)
6521 TCGv t1 = tcg_temp_local_new();
6522 TCGv t2 = tcg_temp_local_new();
6523 #endif
6524 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6525 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6526 #if defined(TARGET_PPC64)
6527 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6528 #else
6529 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6530 #endif
6531 tcg_gen_br(l2);
6532 gen_set_label(l1);
6533 #if defined(TARGET_PPC64)
6534 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6535 #else
6536 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6537 #endif
6538 gen_set_label(l2);
6539 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6540 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6541 #if defined(TARGET_PPC64)
6542 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6543 #else
6544 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6545 #endif
6546 tcg_gen_br(l4);
6547 gen_set_label(l3);
6548 #if defined(TARGET_PPC64)
6549 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6550 #else
6551 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6552 #endif
6553 gen_set_label(l4);
6554 tcg_temp_free_i32(t0);
6555 #if defined(TARGET_PPC64)
6556 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6557 tcg_temp_free(t1);
6558 tcg_temp_free(t2);
6559 #endif
6560 }
6561 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6562 {
6563 gen_evsel(ctx);
6564 }
6565 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6566 {
6567 gen_evsel(ctx);
6568 }
6569 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6570 {
6571 gen_evsel(ctx);
6572 }
6573 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6574 {
6575 gen_evsel(ctx);
6576 }
6577
6578 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6579 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6580 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6581 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6582 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6583 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6584 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6585 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6586 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6587 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6588 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6589 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6590 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6591 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6592 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6593 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6594 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6595 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6596 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6597 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6598 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6599 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6600 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6601 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6602 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6603
6604 /* Load and stores */
6605 GEN_SPEOP_LDST(dd, 3);
6606 GEN_SPEOP_LDST(dw, 3);
6607 GEN_SPEOP_LDST(dh, 3);
6608 GEN_SPEOP_LDST(whe, 2);
6609 GEN_SPEOP_LD(whou, 2);
6610 GEN_SPEOP_LD(whos, 2);
6611 GEN_SPEOP_ST(who, 2);
6612
6613 #define _GEN_OP_SPE_STWWE(suffix) \
6614 static always_inline void gen_op_spe_stwwe_##suffix (void) \
6615 { \
6616 gen_op_srli32_T1_64(); \
6617 gen_op_spe_stwwo_##suffix(); \
6618 }
6619 #define _GEN_OP_SPE_STWWE_LE(suffix) \
6620 static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
6621 { \
6622 gen_op_srli32_T1_64(); \
6623 gen_op_spe_stwwo_le_##suffix(); \
6624 }
6625 #if defined(TARGET_PPC64)
6626 #define GEN_OP_SPE_STWWE(suffix) \
6627 _GEN_OP_SPE_STWWE(suffix); \
6628 _GEN_OP_SPE_STWWE_LE(suffix); \
6629 static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
6630 { \
6631 gen_op_srli32_T1_64(); \
6632 gen_op_spe_stwwo_64_##suffix(); \
6633 } \
6634 static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
6635 { \
6636 gen_op_srli32_T1_64(); \
6637 gen_op_spe_stwwo_le_64_##suffix(); \
6638 }
6639 #else
6640 #define GEN_OP_SPE_STWWE(suffix) \
6641 _GEN_OP_SPE_STWWE(suffix); \
6642 _GEN_OP_SPE_STWWE_LE(suffix)
6643 #endif
6644 #if defined(CONFIG_USER_ONLY)
6645 GEN_OP_SPE_STWWE(raw);
6646 #else /* defined(CONFIG_USER_ONLY) */
6647 GEN_OP_SPE_STWWE(user);
6648 GEN_OP_SPE_STWWE(kernel);
6649 GEN_OP_SPE_STWWE(hypv);
6650 #endif /* defined(CONFIG_USER_ONLY) */
6651 GEN_SPEOP_ST(wwe, 2);
6652 GEN_SPEOP_ST(wwo, 2);
6653
6654 #define GEN_SPE_LDSPLAT(name, op, suffix) \
6655 static always_inline void gen_op_spe_l##name##_##suffix (void) \
6656 { \
6657 gen_op_##op##_##suffix(); \
6658 gen_op_splatw_T1_64(); \
6659 }
6660
6661 #define GEN_OP_SPE_LHE(suffix) \
6662 static always_inline void gen_op_spe_lhe_##suffix (void) \
6663 { \
6664 gen_op_spe_lh_##suffix(); \
6665 gen_op_sli16_T1_64(); \
6666 }
6667
6668 #define GEN_OP_SPE_LHX(suffix) \
6669 static always_inline void gen_op_spe_lhx_##suffix (void) \
6670 { \
6671 gen_op_spe_lh_##suffix(); \
6672 gen_op_extsh_T1_64(); \
6673 }
6674
6675 #if defined(CONFIG_USER_ONLY)
6676 GEN_OP_SPE_LHE(raw);
6677 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6678 GEN_OP_SPE_LHE(le_raw);
6679 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6680 GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6681 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6682 GEN_OP_SPE_LHX(raw);
6683 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6684 GEN_OP_SPE_LHX(le_raw);
6685 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6686 #if defined(TARGET_PPC64)
6687 GEN_OP_SPE_LHE(64_raw);
6688 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6689 GEN_OP_SPE_LHE(le_64_raw);
6690 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6691 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6692 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6693 GEN_OP_SPE_LHX(64_raw);
6694 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6695 GEN_OP_SPE_LHX(le_64_raw);
6696 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6697 #endif
6698 #else
6699 GEN_OP_SPE_LHE(user);
6700 GEN_OP_SPE_LHE(kernel);
6701 GEN_OP_SPE_LHE(hypv);
6702 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
6703 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6704 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
6705 GEN_OP_SPE_LHE(le_user);
6706 GEN_OP_SPE_LHE(le_kernel);
6707 GEN_OP_SPE_LHE(le_hypv);
6708 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
6709 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6710 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
6711 GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
6712 GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6713 GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
6714 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
6715 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6716 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
6717 GEN_OP_SPE_LHX(user);
6718 GEN_OP_SPE_LHX(kernel);
6719 GEN_OP_SPE_LHX(hypv);
6720 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
6721 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6722 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
6723 GEN_OP_SPE_LHX(le_user);
6724 GEN_OP_SPE_LHX(le_kernel);
6725 GEN_OP_SPE_LHX(le_hypv);
6726 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
6727 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6728 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
6729 #if defined(TARGET_PPC64)
6730 GEN_OP_SPE_LHE(64_user);
6731 GEN_OP_SPE_LHE(64_kernel);
6732 GEN_OP_SPE_LHE(64_hypv);
6733 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
6734 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6735 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
6736 GEN_OP_SPE_LHE(le_64_user);
6737 GEN_OP_SPE_LHE(le_64_kernel);
6738 GEN_OP_SPE_LHE(le_64_hypv);
6739 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
6740 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6741 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
6742 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
6743 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6744 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
6745 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
6746 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6747 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
6748 GEN_OP_SPE_LHX(64_user);
6749 GEN_OP_SPE_LHX(64_kernel);
6750 GEN_OP_SPE_LHX(64_hypv);
6751 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
6752 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6753 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
6754 GEN_OP_SPE_LHX(le_64_user);
6755 GEN_OP_SPE_LHX(le_64_kernel);
6756 GEN_OP_SPE_LHX(le_64_hypv);
6757 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
6758 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6759 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
6760 #endif
6761 #endif
6762 GEN_SPEOP_LD(hhesplat, 1);
6763 GEN_SPEOP_LD(hhousplat, 1);
6764 GEN_SPEOP_LD(hhossplat, 1);
6765 GEN_SPEOP_LD(wwsplat, 2);
6766 GEN_SPEOP_LD(whsplat, 2);
6767
6768 GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6769 GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6770 GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6771 GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6772 GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6773 GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6774 GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6775 GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6776 GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6777 GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6778 GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6779 GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6780 GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6781 GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6782 GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6783 GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6784 GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6785 GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6786
6787 /* Multiply and add - TODO */
6788 #if 0
6789 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6790 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6791 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6792 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6793 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6794 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6795 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6796 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6797 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6798 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6799 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6800 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6801
6802 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6803 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6804 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6805 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6806 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6807 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6808 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6809 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6810 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6811 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6812 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6813 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6814 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6815 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6816
6817 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6818 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6819 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6820 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6821 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6822 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6823
6824 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6825 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6826 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6827 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6828 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6829 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6830 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6831 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6832 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6833 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6834 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6835 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6836
6837 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6838 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6839 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6840 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6841 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6842
6843 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6844 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6845 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6846 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6847 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6848 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6849 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6850 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6851 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6852 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6853 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6854 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6855
6856 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6857 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6858 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6859 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6860 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6861 #endif
6862
6863 /*** SPE floating-point extension ***/
6864 #if defined(TARGET_PPC64)
6865 #define GEN_SPEFPUOP_CONV_32_32(name) \
6866 static always_inline void gen_##name (DisasContext *ctx) \
6867 { \
6868 TCGv_i32 t0; \
6869 TCGv t1; \
6870 t0 = tcg_temp_new_i32(); \
6871 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6872 gen_helper_##name(t0, t0); \
6873 t1 = tcg_temp_new(); \
6874 tcg_gen_extu_i32_tl(t1, t0); \
6875 tcg_temp_free_i32(t0); \
6876 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6877 0xFFFFFFFF00000000ULL); \
6878 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
6879 tcg_temp_free(t1); \
6880 }
6881 #define GEN_SPEFPUOP_CONV_32_64(name) \
6882 static always_inline void gen_##name (DisasContext *ctx) \
6883 { \
6884 TCGv_i32 t0; \
6885 TCGv t1; \
6886 t0 = tcg_temp_new_i32(); \
6887 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
6888 t1 = tcg_temp_new(); \
6889 tcg_gen_extu_i32_tl(t1, t0); \
6890 tcg_temp_free_i32(t0); \
6891 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6892 0xFFFFFFFF00000000ULL); \
6893 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
6894 tcg_temp_free(t1); \
6895 }
6896 #define GEN_SPEFPUOP_CONV_64_32(name) \
6897 static always_inline void gen_##name (DisasContext *ctx) \
6898 { \
6899 TCGv_i32 t0 = tcg_temp_new_i32(); \
6900 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6901 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
6902 tcg_temp_free_i32(t0); \
6903 }
6904 #define GEN_SPEFPUOP_CONV_64_64(name) \
6905 static always_inline void gen_##name (DisasContext *ctx) \
6906 { \
6907 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
6908 }
6909 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
6910 static always_inline void gen_##name (DisasContext *ctx) \
6911 { \
6912 TCGv_i32 t0, t1; \
6913 TCGv_i64 t2; \
6914 if (unlikely(!ctx->spe_enabled)) { \
6915 GEN_EXCP_NO_AP(ctx); \
6916 return; \
6917 } \
6918 t0 = tcg_temp_new_i32(); \
6919 t1 = tcg_temp_new_i32(); \
6920 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6921 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6922 gen_helper_##name(t0, t0, t1); \
6923 tcg_temp_free_i32(t1); \
6924 t2 = tcg_temp_new(); \
6925 tcg_gen_extu_i32_tl(t2, t0); \
6926 tcg_temp_free_i32(t0); \
6927 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
6928 0xFFFFFFFF00000000ULL); \
6929 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
6930 tcg_temp_free(t2); \
6931 }
6932 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
6933 static always_inline void gen_##name (DisasContext *ctx) \
6934 { \
6935 if (unlikely(!ctx->spe_enabled)) { \
6936 GEN_EXCP_NO_AP(ctx); \
6937 return; \
6938 } \
6939 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6940 cpu_gpr[rB(ctx->opcode)]); \
6941 }
6942 #define GEN_SPEFPUOP_COMP_32(name) \
6943 static always_inline void gen_##name (DisasContext *ctx) \
6944 { \
6945 TCGv_i32 t0, t1; \
6946 if (unlikely(!ctx->spe_enabled)) { \
6947 GEN_EXCP_NO_AP(ctx); \
6948 return; \
6949 } \
6950 t0 = tcg_temp_new_i32(); \
6951 t1 = tcg_temp_new_i32(); \
6952 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6953 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6954 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
6955 tcg_temp_free_i32(t0); \
6956 tcg_temp_free_i32(t1); \
6957 }
6958 #define GEN_SPEFPUOP_COMP_64(name) \
6959 static always_inline void gen_##name (DisasContext *ctx) \
6960 { \
6961 if (unlikely(!ctx->spe_enabled)) { \
6962 GEN_EXCP_NO_AP(ctx); \
6963 return; \
6964 } \
6965 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
6966 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
6967 }
6968 #else
6969 #define GEN_SPEFPUOP_CONV_32_32(name) \
6970 static always_inline void gen_##name (DisasContext *ctx) \
6971 { \
6972 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
6973 }
6974 #define GEN_SPEFPUOP_CONV_32_64(name) \
6975 static always_inline void gen_##name (DisasContext *ctx) \
6976 { \
6977 TCGv_i64 t0 = tcg_temp_new_i64(); \
6978 gen_load_gpr64(t0, rB(ctx->opcode)); \
6979 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
6980 tcg_temp_free_i64(t0); \
6981 }
6982 #define GEN_SPEFPUOP_CONV_64_32(name) \
6983 static always_inline void gen_##name (DisasContext *ctx) \
6984 { \
6985 TCGv_i64 t0 = tcg_temp_new_i64(); \
6986 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
6987 gen_store_gpr64(rD(ctx->opcode), t0); \
6988 tcg_temp_free_i64(t0); \
6989 }
6990 #define GEN_SPEFPUOP_CONV_64_64(name) \
6991 static always_inline void gen_##name (DisasContext *ctx) \
6992 { \
6993 TCGv_i64 t0 = tcg_temp_new_i64(); \
6994 gen_load_gpr64(t0, rB(ctx->opcode)); \
6995 gen_helper_##name(t0, t0); \
6996 gen_store_gpr64(rD(ctx->opcode), t0); \
6997 tcg_temp_free_i64(t0); \
6998 }
6999 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7000 static always_inline void gen_##name (DisasContext *ctx) \
7001 { \
7002 if (unlikely(!ctx->spe_enabled)) { \
7003 GEN_EXCP_NO_AP(ctx); \
7004 return; \
7005 } \
7006 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7007 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7008 }
7009 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7010 static always_inline void gen_##name (DisasContext *ctx) \
7011 { \
7012 TCGv_i64 t0, t1; \
7013 if (unlikely(!ctx->spe_enabled)) { \
7014 GEN_EXCP_NO_AP(ctx); \
7015 return; \
7016 } \
7017 t0 = tcg_temp_new_i64(); \
7018 t1 = tcg_temp_new_i64(); \
7019 gen_load_gpr64(t0, rA(ctx->opcode)); \
7020 gen_load_gpr64(t1, rB(ctx->opcode)); \
7021 gen_helper_##name(t0, t0, t1); \
7022 gen_store_gpr64(rD(ctx->opcode), t0); \
7023 tcg_temp_free_i64(t0); \
7024 tcg_temp_free_i64(t1); \
7025 }
7026 #define GEN_SPEFPUOP_COMP_32(name) \
7027 static always_inline void gen_##name (DisasContext *ctx) \
7028 { \
7029 if (unlikely(!ctx->spe_enabled)) { \
7030 GEN_EXCP_NO_AP(ctx); \
7031 return; \
7032 } \
7033 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7034 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7035 }
7036 #define GEN_SPEFPUOP_COMP_64(name) \
7037 static always_inline void gen_##name (DisasContext *ctx) \
7038 { \
7039 TCGv_i64 t0, t1; \
7040 if (unlikely(!ctx->spe_enabled)) { \
7041 GEN_EXCP_NO_AP(ctx); \
7042 return; \
7043 } \
7044 t0 = tcg_temp_new_i64(); \
7045 t1 = tcg_temp_new_i64(); \
7046 gen_load_gpr64(t0, rA(ctx->opcode)); \
7047 gen_load_gpr64(t1, rB(ctx->opcode)); \
7048 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7049 tcg_temp_free_i64(t0); \
7050 tcg_temp_free_i64(t1); \
7051 }
7052 #endif
7053
7054 /* Single precision floating-point vectors operations */
7055 /* Arithmetic */
7056 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7057 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7058 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7059 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7060 static always_inline void gen_evfsabs (DisasContext *ctx)
7061 {
7062 if (unlikely(!ctx->spe_enabled)) {
7063 GEN_EXCP_NO_AP(ctx);
7064 return;
7065 }
7066 #if defined(TARGET_PPC64)
7067 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7068 #else
7069 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7070 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7071 #endif
7072 }
7073 static always_inline void gen_evfsnabs (DisasContext *ctx)
7074 {
7075 if (unlikely(!ctx->spe_enabled)) {
7076 GEN_EXCP_NO_AP(ctx);
7077 return;
7078 }
7079 #if defined(TARGET_PPC64)
7080 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7081 #else
7082 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7083 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7084 #endif
7085 }
7086 static always_inline void gen_evfsneg (DisasContext *ctx)
7087 {
7088 if (unlikely(!ctx->spe_enabled)) {
7089 GEN_EXCP_NO_AP(ctx);
7090 return;
7091 }
7092 #if defined(TARGET_PPC64)
7093 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7094 #else
7095 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7096 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7097 #endif
7098 }
7099
7100 /* Conversion */
7101 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7102 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7103 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7104 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7105 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7106 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7107 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7108 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7109 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7110 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7111
7112 /* Comparison */
7113 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7114 GEN_SPEFPUOP_COMP_64(evfscmplt);
7115 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7116 GEN_SPEFPUOP_COMP_64(evfststgt);
7117 GEN_SPEFPUOP_COMP_64(evfststlt);
7118 GEN_SPEFPUOP_COMP_64(evfststeq);
7119
7120 /* Opcodes definitions */
7121 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7122 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7123 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7124 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7125 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7126 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7127 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7128 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7129 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7130 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7131 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7132 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7133 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7134 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7135
7136 /* Single precision floating-point operations */
7137 /* Arithmetic */
7138 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7139 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7140 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7141 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7142 static always_inline void gen_efsabs (DisasContext *ctx)
7143 {
7144 if (unlikely(!ctx->spe_enabled)) {
7145 GEN_EXCP_NO_AP(ctx);
7146 return;
7147 }
7148 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7149 }
7150 static always_inline void gen_efsnabs (DisasContext *ctx)
7151 {
7152 if (unlikely(!ctx->spe_enabled)) {
7153 GEN_EXCP_NO_AP(ctx);
7154 return;
7155 }
7156 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7157 }
7158 static always_inline void gen_efsneg (DisasContext *ctx)
7159 {
7160 if (unlikely(!ctx->spe_enabled)) {
7161 GEN_EXCP_NO_AP(ctx);
7162 return;
7163 }
7164 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7165 }
7166
7167 /* Conversion */
7168 GEN_SPEFPUOP_CONV_32_32(efscfui);
7169 GEN_SPEFPUOP_CONV_32_32(efscfsi);
7170 GEN_SPEFPUOP_CONV_32_32(efscfuf);
7171 GEN_SPEFPUOP_CONV_32_32(efscfsf);
7172 GEN_SPEFPUOP_CONV_32_32(efsctui);
7173 GEN_SPEFPUOP_CONV_32_32(efsctsi);
7174 GEN_SPEFPUOP_CONV_32_32(efsctuf);
7175 GEN_SPEFPUOP_CONV_32_32(efsctsf);
7176 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7177 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7178 GEN_SPEFPUOP_CONV_32_64(efscfd);
7179
7180 /* Comparison */
7181 GEN_SPEFPUOP_COMP_32(efscmpgt);
7182 GEN_SPEFPUOP_COMP_32(efscmplt);
7183 GEN_SPEFPUOP_COMP_32(efscmpeq);
7184 GEN_SPEFPUOP_COMP_32(efststgt);
7185 GEN_SPEFPUOP_COMP_32(efststlt);
7186 GEN_SPEFPUOP_COMP_32(efststeq);
7187
7188 /* Opcodes definitions */
7189 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
7190 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7191 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7192 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7193 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7194 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7195 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7196 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7197 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7198 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
7199 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7200 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
7201 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7202 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7203
7204 /* Double precision floating-point operations */
7205 /* Arithmetic */
7206 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7207 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7208 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7209 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7210 static always_inline void gen_efdabs (DisasContext *ctx)
7211 {
7212 if (unlikely(!ctx->spe_enabled)) {
7213 GEN_EXCP_NO_AP(ctx);
7214 return;
7215 }
7216 #if defined(TARGET_PPC64)
7217 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7218 #else
7219 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7220 #endif
7221 }
7222 static always_inline void gen_efdnabs (DisasContext *ctx)
7223 {
7224 if (unlikely(!ctx->spe_enabled)) {
7225 GEN_EXCP_NO_AP(ctx);
7226 return;
7227 }
7228 #if defined(TARGET_PPC64)
7229 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7230 #else
7231 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7232 #endif
7233 }
7234 static always_inline void gen_efdneg (DisasContext *ctx)
7235 {
7236 if (unlikely(!ctx->spe_enabled)) {
7237 GEN_EXCP_NO_AP(ctx);
7238 return;
7239 }
7240 #if defined(TARGET_PPC64)
7241 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7242 #else
7243 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7244 #endif
7245 }
7246
7247 /* Conversion */
7248 GEN_SPEFPUOP_CONV_64_32(efdcfui);
7249 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7250 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7251 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7252 GEN_SPEFPUOP_CONV_32_64(efdctui);
7253 GEN_SPEFPUOP_CONV_32_64(efdctsi);
7254 GEN_SPEFPUOP_CONV_32_64(efdctuf);
7255 GEN_SPEFPUOP_CONV_32_64(efdctsf);
7256 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7257 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7258 GEN_SPEFPUOP_CONV_64_32(efdcfs);
7259 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7260 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7261 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7262 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
7263
7264 /* Comparison */
7265 GEN_SPEFPUOP_COMP_64(efdcmpgt);
7266 GEN_SPEFPUOP_COMP_64(efdcmplt);
7267 GEN_SPEFPUOP_COMP_64(efdcmpeq);
7268 GEN_SPEFPUOP_COMP_64(efdtstgt);
7269 GEN_SPEFPUOP_COMP_64(efdtstlt);
7270 GEN_SPEFPUOP_COMP_64(efdtsteq);
7271
7272 /* Opcodes definitions */
7273 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7274 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7275 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7276 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7277 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7278 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7279 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7280 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7281 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7282 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7283 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7284 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7285 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7286 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7287 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7288 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
7289
7290 /* End opcode list */
7291 GEN_OPCODE_MARK(end);
7292
7293 #include "translate_init.c"
7294 #include "helper_regs.h"
7295
7296 /*****************************************************************************/
7297 /* Misc PowerPC helpers */
7298 void cpu_dump_state (CPUState *env, FILE *f,
7299 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7300 int flags)
7301 {
7302 #define RGPL 4
7303 #define RFPL 4
7304
7305 int i;
7306
7307 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
7308 env->nip, env->lr, env->ctr, env->xer);
7309 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7310 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
7311 #if !defined(NO_TIMER_DUMP)
7312 cpu_fprintf(f, "TB %08x %08x "
7313 #if !defined(CONFIG_USER_ONLY)
7314 "DECR %08x"
7315 #endif
7316 "\n",
7317 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7318 #if !defined(CONFIG_USER_ONLY)
7319 , cpu_ppc_load_decr(env)
7320 #endif
7321 );
7322 #endif
7323 for (i = 0; i < 32; i++) {
7324 if ((i & (RGPL - 1)) == 0)
7325 cpu_fprintf(f, "GPR%02d", i);
7326 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
7327 if ((i & (RGPL - 1)) == (RGPL - 1))
7328 cpu_fprintf(f, "\n");
7329 }
7330 cpu_fprintf(f, "CR ");
7331 for (i = 0; i < 8; i++)
7332 cpu_fprintf(f, "%01x", env->crf[i]);
7333 cpu_fprintf(f, " [");
7334 for (i = 0; i < 8; i++) {
7335 char a = '-';
7336 if (env->crf[i] & 0x08)
7337 a = 'L';
7338 else if (env->crf[i] & 0x04)
7339 a = 'G';
7340 else if (env->crf[i] & 0x02)
7341 a = 'E';
7342 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7343 }
7344 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
7345 for (i = 0; i < 32; i++) {
7346 if ((i & (RFPL - 1)) == 0)
7347 cpu_fprintf(f, "FPR%02d", i);
7348 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7349 if ((i & (RFPL - 1)) == (RFPL - 1))
7350 cpu_fprintf(f, "\n");
7351 }
7352 #if !defined(CONFIG_USER_ONLY)
7353 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
7354 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
7355 #endif
7356
7357 #undef RGPL
7358 #undef RFPL
7359 }
7360
7361 void cpu_dump_statistics (CPUState *env, FILE*f,
7362 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7363 int flags)
7364 {
7365 #if defined(DO_PPC_STATISTICS)
7366 opc_handler_t **t1, **t2, **t3, *handler;
7367 int op1, op2, op3;
7368
7369 t1 = env->opcodes;
7370 for (op1 = 0; op1 < 64; op1++) {
7371 handler = t1[op1];
7372 if (is_indirect_opcode(handler)) {
7373 t2 = ind_table(handler);
7374 for (op2 = 0; op2 < 32; op2++) {
7375 handler = t2[op2];
7376 if (is_indirect_opcode(handler)) {
7377 t3 = ind_table(handler);
7378 for (op3 = 0; op3 < 32; op3++) {
7379 handler = t3[op3];
7380 if (handler->count == 0)
7381 continue;
7382 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7383 "%016llx %lld\n",
7384 op1, op2, op3, op1, (op3 << 5) | op2,
7385 handler->oname,
7386 handler->count, handler->count);
7387 }
7388 } else {
7389 if (handler->count == 0)
7390 continue;
7391 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7392 "%016llx %lld\n",
7393 op1, op2, op1, op2, handler->oname,
7394 handler->count, handler->count);
7395 }
7396 }
7397 } else {
7398 if (handler->count == 0)
7399 continue;
7400 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7401 op1, op1, handler->oname,
7402 handler->count, handler->count);
7403 }
7404 }
7405 #endif
7406 }
7407
7408 /*****************************************************************************/
7409 static always_inline void gen_intermediate_code_internal (CPUState *env,
7410 TranslationBlock *tb,
7411 int search_pc)
7412 {
7413 DisasContext ctx, *ctxp = &ctx;
7414 opc_handler_t **table, *handler;
7415 target_ulong pc_start;
7416 uint16_t *gen_opc_end;
7417 int supervisor, little_endian;
7418 CPUBreakpoint *bp;
7419 int j, lj = -1;
7420 int num_insns;
7421 int max_insns;
7422
7423 pc_start = tb->pc;
7424 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7425 #if defined(OPTIMIZE_FPRF_UPDATE)
7426 gen_fprf_ptr = gen_fprf_buf;
7427 #endif
7428 ctx.nip = pc_start;
7429 ctx.tb = tb;
7430 ctx.exception = POWERPC_EXCP_NONE;
7431 ctx.spr_cb = env->spr_cb;
7432 supervisor = env->mmu_idx;
7433 #if !defined(CONFIG_USER_ONLY)
7434 ctx.supervisor = supervisor;
7435 #endif
7436 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
7437 #if defined(TARGET_PPC64)
7438 ctx.sf_mode = msr_sf;
7439 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
7440 #else
7441 ctx.mem_idx = (supervisor << 1) | little_endian;
7442 #endif
7443 ctx.dcache_line_size = env->dcache_line_size;
7444 ctx.fpu_enabled = msr_fp;
7445 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7446 ctx.spe_enabled = msr_spe;
7447 else
7448 ctx.spe_enabled = 0;
7449 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7450 ctx.altivec_enabled = msr_vr;
7451 else
7452 ctx.altivec_enabled = 0;
7453 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7454 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7455 else
7456 ctx.singlestep_enabled = 0;
7457 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7458 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7459 if (unlikely(env->singlestep_enabled))
7460 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7461 #if defined (DO_SINGLE_STEP) && 0
7462 /* Single step trace mode */
7463 msr_se = 1;
7464 #endif
7465 num_insns = 0;
7466 max_insns = tb->cflags & CF_COUNT_MASK;
7467 if (max_insns == 0)
7468 max_insns = CF_COUNT_MASK;
7469
7470 gen_icount_start();
7471 /* Set env in case of segfault during code fetch */
7472 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
7473 if (unlikely(env->breakpoints)) {
7474 for (bp = env->breakpoints; bp != NULL; bp = bp->next) {
7475 if (bp->pc == ctx.nip) {
7476 gen_update_nip(&ctx, ctx.nip);
7477 gen_helper_raise_debug();
7478 break;
7479 }
7480 }
7481 }
7482 if (unlikely(search_pc)) {
7483 j = gen_opc_ptr - gen_opc_buf;
7484 if (lj < j) {
7485 lj++;
7486 while (lj < j)
7487 gen_opc_instr_start[lj++] = 0;
7488 gen_opc_pc[lj] = ctx.nip;
7489 gen_opc_instr_start[lj] = 1;
7490 gen_opc_icount[lj] = num_insns;
7491 }
7492 }
7493 #if defined PPC_DEBUG_DISAS
7494 if (loglevel & CPU_LOG_TB_IN_ASM) {
7495 fprintf(logfile, "----------------\n");
7496 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
7497 ctx.nip, supervisor, (int)msr_ir);
7498 }
7499 #endif
7500 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7501 gen_io_start();
7502 if (unlikely(little_endian)) {
7503 ctx.opcode = bswap32(ldl_code(ctx.nip));
7504 } else {
7505 ctx.opcode = ldl_code(ctx.nip);
7506 }
7507 #if defined PPC_DEBUG_DISAS
7508 if (loglevel & CPU_LOG_TB_IN_ASM) {
7509 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
7510 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7511 opc3(ctx.opcode), little_endian ? "little" : "big");
7512 }
7513 #endif
7514 ctx.nip += 4;
7515 table = env->opcodes;
7516 num_insns++;
7517 handler = table[opc1(ctx.opcode)];
7518 if (is_indirect_opcode(handler)) {
7519 table = ind_table(handler);
7520 handler = table[opc2(ctx.opcode)];
7521 if (is_indirect_opcode(handler)) {
7522 table = ind_table(handler);
7523 handler = table[opc3(ctx.opcode)];
7524 }
7525 }
7526 /* Is opcode *REALLY* valid ? */
7527 if (unlikely(handler->handler == &gen_invalid)) {
7528 if (loglevel != 0) {
7529 fprintf(logfile, "invalid/unsupported opcode: "
7530 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
7531 opc1(ctx.opcode), opc2(ctx.opcode),
7532 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
7533 } else {
7534 printf("invalid/unsupported opcode: "
7535 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
7536 opc1(ctx.opcode), opc2(ctx.opcode),
7537 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
7538 }
7539 } else {
7540 if (unlikely((ctx.opcode & handler->inval) != 0)) {
7541 if (loglevel != 0) {
7542 fprintf(logfile, "invalid bits: %08x for opcode: "
7543 "%02x - %02x - %02x (%08x) " ADDRX "\n",
7544 ctx.opcode & handler->inval, opc1(ctx.opcode),
7545 opc2(ctx.opcode), opc3(ctx.opcode),
7546 ctx.opcode, ctx.nip - 4);
7547 } else {
7548 printf("invalid bits: %08x for opcode: "
7549 "%02x - %02x - %02x (%08x) " ADDRX "\n",
7550 ctx.opcode & handler->inval, opc1(ctx.opcode),
7551 opc2(ctx.opcode), opc3(ctx.opcode),
7552 ctx.opcode, ctx.nip - 4);
7553 }
7554 GEN_EXCP_INVAL(ctxp);
7555 break;
7556 }
7557 }
7558 (*(handler->handler))(&ctx);
7559 #if defined(DO_PPC_STATISTICS)
7560 handler->count++;
7561 #endif
7562 /* Check trace mode exceptions */
7563 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7564 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7565 ctx.exception != POWERPC_SYSCALL &&
7566 ctx.exception != POWERPC_EXCP_TRAP &&
7567 ctx.exception != POWERPC_EXCP_BRANCH)) {
7568 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
7569 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7570 (env->singlestep_enabled) ||
7571 num_insns >= max_insns)) {
7572 /* if we reach a page boundary or are single stepping, stop
7573 * generation
7574 */
7575 break;
7576 }
7577 #if defined (DO_SINGLE_STEP)
7578 break;
7579 #endif
7580 }
7581 if (tb->cflags & CF_LAST_IO)
7582 gen_io_end();
7583 if (ctx.exception == POWERPC_EXCP_NONE) {
7584 gen_goto_tb(&ctx, 0, ctx.nip);
7585 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7586 if (unlikely(env->singlestep_enabled)) {
7587 gen_update_nip(&ctx, ctx.nip);
7588 gen_helper_raise_debug();
7589 }
7590 /* Generate the return instruction */
7591 tcg_gen_exit_tb(0);
7592 }
7593 gen_icount_end(tb, num_insns);
7594 *gen_opc_ptr = INDEX_op_end;
7595 if (unlikely(search_pc)) {
7596 j = gen_opc_ptr - gen_opc_buf;
7597 lj++;
7598 while (lj <= j)
7599 gen_opc_instr_start[lj++] = 0;
7600 } else {
7601 tb->size = ctx.nip - pc_start;
7602 tb->icount = num_insns;
7603 }
7604 #if defined(DEBUG_DISAS)
7605 if (loglevel & CPU_LOG_TB_CPU) {
7606 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7607 cpu_dump_state(env, logfile, fprintf, 0);
7608 }
7609 if (loglevel & CPU_LOG_TB_IN_ASM) {
7610 int flags;
7611 flags = env->bfd_mach;
7612 flags |= little_endian << 16;
7613 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
7614 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
7615 fprintf(logfile, "\n");
7616 }
7617 #endif
7618 }
7619
7620 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
7621 {
7622 gen_intermediate_code_internal(env, tb, 0);
7623 }
7624
7625 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
7626 {
7627 gen_intermediate_code_internal(env, tb, 1);
7628 }
7629
7630 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7631 unsigned long searched_pc, int pc_pos, void *puc)
7632 {
7633 int type, c;
7634 /* for PPC, we need to look at the micro operation to get the
7635 * access type */
7636 env->nip = gen_opc_pc[pc_pos];
7637 c = gen_opc_buf[pc_pos];
7638 switch(c) {
7639 #if defined(CONFIG_USER_ONLY)
7640 #define CASE3(op)\
7641 case INDEX_op_ ## op ## _raw
7642 #else
7643 #define CASE3(op)\
7644 case INDEX_op_ ## op ## _user:\
7645 case INDEX_op_ ## op ## _kernel:\
7646 case INDEX_op_ ## op ## _hypv
7647 #endif
7648
7649 CASE3(stfd):
7650 CASE3(stfs):
7651 CASE3(lfd):
7652 CASE3(lfs):
7653 type = ACCESS_FLOAT;
7654 break;
7655 CASE3(lwarx):
7656 type = ACCESS_RES;
7657 break;
7658 CASE3(stwcx):
7659 type = ACCESS_RES;
7660 break;
7661 CASE3(eciwx):
7662 CASE3(ecowx):
7663 type = ACCESS_EXT;
7664 break;
7665 default:
7666 type = ACCESS_INT;
7667 break;
7668 }
7669 env->access_type = type;
7670 }
Qemu copy for testing