]> git.proxmox.com Git - qemu.git/blob - target-ppc/translate.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target-ppc: add exceptions for conditional stores
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24
25 #include "cpu.h"
26 #include "exec-all.h"
27 #include "disas.h"
28 #include "tcg-op.h"
29 #include "qemu-common.h"
30 #include "host-utils.h"
31
32 #include "helper.h"
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_ptr cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 #if !defined(TARGET_PPC64)
56 + 10*4 + 22*5 /* SPE GPRh */
57 #endif
58 + 10*4 + 22*5 /* FPR */
59 + 2*(10*6 + 22*7) /* AVRh, AVRl */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 #if !defined(TARGET_PPC64)
63 static TCGv cpu_gprh[32];
64 #endif
65 static TCGv_i64 cpu_fpr[32];
66 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
67 static TCGv_i32 cpu_crf[8];
68 static TCGv cpu_nip;
69 static TCGv cpu_msr;
70 static TCGv cpu_ctr;
71 static TCGv cpu_lr;
72 static TCGv cpu_xer;
73 static TCGv cpu_reserve;
74 static TCGv_i32 cpu_fpscr;
75 static TCGv_i32 cpu_access_type;
76
77 #include "gen-icount.h"
78
79 void ppc_translate_init(void)
80 {
81 int i;
82 char* p;
83 size_t cpu_reg_names_size;
84 static int done_init = 0;
85
86 if (done_init)
87 return;
88
89 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
90
91 p = cpu_reg_names;
92 cpu_reg_names_size = sizeof(cpu_reg_names);
93
94 for (i = 0; i < 8; i++) {
95 snprintf(p, cpu_reg_names_size, "crf%d", i);
96 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
97 offsetof(CPUState, crf[i]), p);
98 p += 5;
99 cpu_reg_names_size -= 5;
100 }
101
102 for (i = 0; i < 32; i++) {
103 snprintf(p, cpu_reg_names_size, "r%d", i);
104 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
105 offsetof(CPUState, gpr[i]), p);
106 p += (i < 10) ? 3 : 4;
107 cpu_reg_names_size -= (i < 10) ? 3 : 4;
108 #if !defined(TARGET_PPC64)
109 snprintf(p, cpu_reg_names_size, "r%dH", i);
110 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, gprh[i]), p);
112 p += (i < 10) ? 4 : 5;
113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
114 #endif
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
118 offsetof(CPUState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
128 offsetof(CPUState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
139 offsetof(CPUState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 }
144
145 cpu_nip = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUState, nip), "nip");
147
148 cpu_msr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUState, msr), "msr");
150
151 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUState, ctr), "ctr");
153
154 cpu_lr = tcg_global_mem_new(TCG_AREG0,
155 offsetof(CPUState, lr), "lr");
156
157 cpu_xer = tcg_global_mem_new(TCG_AREG0,
158 offsetof(CPUState, xer), "xer");
159
160 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
161 offsetof(CPUState, reserve_addr),
162 "reserve_addr");
163
164 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
165 offsetof(CPUState, fpscr), "fpscr");
166
167 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
168 offsetof(CPUState, access_type), "access_type");
169
170 /* register helpers */
171 #define GEN_HELPER 2
172 #include "helper.h"
173
174 done_init = 1;
175 }
176
177 /* internal defines */
178 typedef struct DisasContext {
179 struct TranslationBlock *tb;
180 target_ulong nip;
181 uint32_t opcode;
182 uint32_t exception;
183 /* Routine used to access memory */
184 int mem_idx;
185 int access_type;
186 /* Translation flags */
187 int le_mode;
188 #if defined(TARGET_PPC64)
189 int sf_mode;
190 #endif
191 int fpu_enabled;
192 int altivec_enabled;
193 int spe_enabled;
194 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
195 int singlestep_enabled;
196 } DisasContext;
197
198 struct opc_handler_t {
199 /* invalid bits */
200 uint32_t inval;
201 /* instruction type */
202 uint64_t type;
203 /* handler */
204 void (*handler)(DisasContext *ctx);
205 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
206 const char *oname;
207 #endif
208 #if defined(DO_PPC_STATISTICS)
209 uint64_t count;
210 #endif
211 };
212
213 static always_inline void gen_reset_fpstatus (void)
214 {
215 #ifdef CONFIG_SOFTFLOAT
216 gen_helper_reset_fpstatus();
217 #endif
218 }
219
220 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
221 {
222 TCGv_i32 t0 = tcg_temp_new_i32();
223
224 if (set_fprf != 0) {
225 /* This case might be optimized later */
226 tcg_gen_movi_i32(t0, 1);
227 gen_helper_compute_fprf(t0, arg, t0);
228 if (unlikely(set_rc)) {
229 tcg_gen_mov_i32(cpu_crf[1], t0);
230 }
231 gen_helper_float_check_status();
232 } else if (unlikely(set_rc)) {
233 /* We always need to compute fpcc */
234 tcg_gen_movi_i32(t0, 0);
235 gen_helper_compute_fprf(t0, arg, t0);
236 tcg_gen_mov_i32(cpu_crf[1], t0);
237 }
238
239 tcg_temp_free_i32(t0);
240 }
241
242 static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
243 {
244 if (ctx->access_type != access_type) {
245 tcg_gen_movi_i32(cpu_access_type, access_type);
246 ctx->access_type = access_type;
247 }
248 }
249
250 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
251 {
252 #if defined(TARGET_PPC64)
253 if (ctx->sf_mode)
254 tcg_gen_movi_tl(cpu_nip, nip);
255 else
256 #endif
257 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
258 }
259
260 static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
261 {
262 TCGv_i32 t0, t1;
263 if (ctx->exception == POWERPC_EXCP_NONE) {
264 gen_update_nip(ctx, ctx->nip);
265 }
266 t0 = tcg_const_i32(excp);
267 t1 = tcg_const_i32(error);
268 gen_helper_raise_exception_err(t0, t1);
269 tcg_temp_free_i32(t0);
270 tcg_temp_free_i32(t1);
271 ctx->exception = (excp);
272 }
273
274 static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
275 {
276 TCGv_i32 t0;
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->nip);
279 }
280 t0 = tcg_const_i32(excp);
281 gen_helper_raise_exception(t0);
282 tcg_temp_free_i32(t0);
283 ctx->exception = (excp);
284 }
285
286 static always_inline void gen_debug_exception (DisasContext *ctx)
287 {
288 TCGv_i32 t0;
289
290 if (ctx->exception != POWERPC_EXCP_BRANCH)
291 gen_update_nip(ctx, ctx->nip);
292 t0 = tcg_const_i32(EXCP_DEBUG);
293 gen_helper_raise_exception(t0);
294 tcg_temp_free_i32(t0);
295 }
296
297 static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
298 {
299 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
300 }
301
302 /* Stop translation */
303 static always_inline void gen_stop_exception (DisasContext *ctx)
304 {
305 gen_update_nip(ctx, ctx->nip);
306 ctx->exception = POWERPC_EXCP_STOP;
307 }
308
309 /* No need to update nip here, as execution flow will change */
310 static always_inline void gen_sync_exception (DisasContext *ctx)
311 {
312 ctx->exception = POWERPC_EXCP_SYNC;
313 }
314
315 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
316 GEN_OPCODE(name, opc1, opc2, opc3, inval, type)
317
318 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
319 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type)
320
321 typedef struct opcode_t {
322 unsigned char opc1, opc2, opc3;
323 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
324 unsigned char pad[5];
325 #else
326 unsigned char pad[1];
327 #endif
328 opc_handler_t handler;
329 const char *oname;
330 } opcode_t;
331
332 /*****************************************************************************/
333 /*** Instruction decoding ***/
334 #define EXTRACT_HELPER(name, shift, nb) \
335 static always_inline uint32_t name (uint32_t opcode) \
336 { \
337 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
338 }
339
340 #define EXTRACT_SHELPER(name, shift, nb) \
341 static always_inline int32_t name (uint32_t opcode) \
342 { \
343 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
344 }
345
346 /* Opcode part 1 */
347 EXTRACT_HELPER(opc1, 26, 6);
348 /* Opcode part 2 */
349 EXTRACT_HELPER(opc2, 1, 5);
350 /* Opcode part 3 */
351 EXTRACT_HELPER(opc3, 6, 5);
352 /* Update Cr0 flags */
353 EXTRACT_HELPER(Rc, 0, 1);
354 /* Destination */
355 EXTRACT_HELPER(rD, 21, 5);
356 /* Source */
357 EXTRACT_HELPER(rS, 21, 5);
358 /* First operand */
359 EXTRACT_HELPER(rA, 16, 5);
360 /* Second operand */
361 EXTRACT_HELPER(rB, 11, 5);
362 /* Third operand */
363 EXTRACT_HELPER(rC, 6, 5);
364 /*** Get CRn ***/
365 EXTRACT_HELPER(crfD, 23, 3);
366 EXTRACT_HELPER(crfS, 18, 3);
367 EXTRACT_HELPER(crbD, 21, 5);
368 EXTRACT_HELPER(crbA, 16, 5);
369 EXTRACT_HELPER(crbB, 11, 5);
370 /* SPR / TBL */
371 EXTRACT_HELPER(_SPR, 11, 10);
372 static always_inline uint32_t SPR (uint32_t opcode)
373 {
374 uint32_t sprn = _SPR(opcode);
375
376 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
377 }
378 /*** Get constants ***/
379 EXTRACT_HELPER(IMM, 12, 8);
380 /* 16 bits signed immediate value */
381 EXTRACT_SHELPER(SIMM, 0, 16);
382 /* 16 bits unsigned immediate value */
383 EXTRACT_HELPER(UIMM, 0, 16);
384 /* 5 bits signed immediate value */
385 EXTRACT_HELPER(SIMM5, 16, 5);
386 /* 5 bits signed immediate value */
387 EXTRACT_HELPER(UIMM5, 16, 5);
388 /* Bit count */
389 EXTRACT_HELPER(NB, 11, 5);
390 /* Shift count */
391 EXTRACT_HELPER(SH, 11, 5);
392 /* Vector shift count */
393 EXTRACT_HELPER(VSH, 6, 4);
394 /* Mask start */
395 EXTRACT_HELPER(MB, 6, 5);
396 /* Mask end */
397 EXTRACT_HELPER(ME, 1, 5);
398 /* Trap operand */
399 EXTRACT_HELPER(TO, 21, 5);
400
401 EXTRACT_HELPER(CRM, 12, 8);
402 EXTRACT_HELPER(FM, 17, 8);
403 EXTRACT_HELPER(SR, 16, 4);
404 EXTRACT_HELPER(FPIMM, 12, 4);
405
406 /*** Jump target decoding ***/
407 /* Displacement */
408 EXTRACT_SHELPER(d, 0, 16);
409 /* Immediate address */
410 static always_inline target_ulong LI (uint32_t opcode)
411 {
412 return (opcode >> 0) & 0x03FFFFFC;
413 }
414
415 static always_inline uint32_t BD (uint32_t opcode)
416 {
417 return (opcode >> 0) & 0xFFFC;
418 }
419
420 EXTRACT_HELPER(BO, 21, 5);
421 EXTRACT_HELPER(BI, 16, 5);
422 /* Absolute/relative address */
423 EXTRACT_HELPER(AA, 1, 1);
424 /* Link */
425 EXTRACT_HELPER(LK, 0, 1);
426
427 /* Create a mask between <start> and <end> bits */
428 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
429 {
430 target_ulong ret;
431
432 #if defined(TARGET_PPC64)
433 if (likely(start == 0)) {
434 ret = UINT64_MAX << (63 - end);
435 } else if (likely(end == 63)) {
436 ret = UINT64_MAX >> start;
437 }
438 #else
439 if (likely(start == 0)) {
440 ret = UINT32_MAX << (31 - end);
441 } else if (likely(end == 31)) {
442 ret = UINT32_MAX >> start;
443 }
444 #endif
445 else {
446 ret = (((target_ulong)(-1ULL)) >> (start)) ^
447 (((target_ulong)(-1ULL) >> (end)) >> 1);
448 if (unlikely(start > end))
449 return ~ret;
450 }
451
452 return ret;
453 }
454
455 /*****************************************************************************/
456 /* PowerPC instructions table */
457
458 #if defined(DO_PPC_STATISTICS)
459 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
460 { \
461 .opc1 = op1, \
462 .opc2 = op2, \
463 .opc3 = op3, \
464 .pad = { 0, }, \
465 .handler = { \
466 .inval = invl, \
467 .type = _typ, \
468 .handler = &gen_##name, \
469 .oname = stringify(name), \
470 }, \
471 .oname = stringify(name), \
472 }
473 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
474 { \
475 .opc1 = op1, \
476 .opc2 = op2, \
477 .opc3 = op3, \
478 .pad = { 0, }, \
479 .handler = { \
480 .inval = invl, \
481 .type = _typ, \
482 .handler = &gen_##name, \
483 .oname = onam, \
484 }, \
485 .oname = onam, \
486 }
487 #else
488 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
489 { \
490 .opc1 = op1, \
491 .opc2 = op2, \
492 .opc3 = op3, \
493 .pad = { 0, }, \
494 .handler = { \
495 .inval = invl, \
496 .type = _typ, \
497 .handler = &gen_##name, \
498 }, \
499 .oname = stringify(name), \
500 }
501 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
502 { \
503 .opc1 = op1, \
504 .opc2 = op2, \
505 .opc3 = op3, \
506 .pad = { 0, }, \
507 .handler = { \
508 .inval = invl, \
509 .type = _typ, \
510 .handler = &gen_##name, \
511 }, \
512 .oname = onam, \
513 }
514 #endif
515
516 /* SPR load/store helpers */
517 static always_inline void gen_load_spr(TCGv t, int reg)
518 {
519 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
520 }
521
522 static always_inline void gen_store_spr(int reg, TCGv t)
523 {
524 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
525 }
526
527 /* Invalid instruction */
528 static void gen_invalid(DisasContext *ctx)
529 {
530 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
531 }
532
533 static opc_handler_t invalid_handler = {
534 .inval = 0xFFFFFFFF,
535 .type = PPC_NONE,
536 .handler = gen_invalid,
537 };
538
539 /*** Integer comparison ***/
540
541 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
542 {
543 int l1, l2, l3;
544
545 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
546 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
547 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
548
549 l1 = gen_new_label();
550 l2 = gen_new_label();
551 l3 = gen_new_label();
552 if (s) {
553 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
554 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
555 } else {
556 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
557 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
558 }
559 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
560 tcg_gen_br(l3);
561 gen_set_label(l1);
562 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
563 tcg_gen_br(l3);
564 gen_set_label(l2);
565 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
566 gen_set_label(l3);
567 }
568
569 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
570 {
571 TCGv t0 = tcg_const_local_tl(arg1);
572 gen_op_cmp(arg0, t0, s, crf);
573 tcg_temp_free(t0);
574 }
575
576 #if defined(TARGET_PPC64)
577 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
578 {
579 TCGv t0, t1;
580 t0 = tcg_temp_local_new();
581 t1 = tcg_temp_local_new();
582 if (s) {
583 tcg_gen_ext32s_tl(t0, arg0);
584 tcg_gen_ext32s_tl(t1, arg1);
585 } else {
586 tcg_gen_ext32u_tl(t0, arg0);
587 tcg_gen_ext32u_tl(t1, arg1);
588 }
589 gen_op_cmp(t0, t1, s, crf);
590 tcg_temp_free(t1);
591 tcg_temp_free(t0);
592 }
593
594 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
595 {
596 TCGv t0 = tcg_const_local_tl(arg1);
597 gen_op_cmp32(arg0, t0, s, crf);
598 tcg_temp_free(t0);
599 }
600 #endif
601
602 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
603 {
604 #if defined(TARGET_PPC64)
605 if (!(ctx->sf_mode))
606 gen_op_cmpi32(reg, 0, 1, 0);
607 else
608 #endif
609 gen_op_cmpi(reg, 0, 1, 0);
610 }
611
612 /* cmp */
613 static void gen_cmp(DisasContext *ctx)
614 {
615 #if defined(TARGET_PPC64)
616 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
617 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
618 1, crfD(ctx->opcode));
619 else
620 #endif
621 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
622 1, crfD(ctx->opcode));
623 }
624
625 /* cmpi */
626 static void gen_cmpi(DisasContext *ctx)
627 {
628 #if defined(TARGET_PPC64)
629 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
630 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
631 1, crfD(ctx->opcode));
632 else
633 #endif
634 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
635 1, crfD(ctx->opcode));
636 }
637
638 /* cmpl */
639 static void gen_cmpl(DisasContext *ctx)
640 {
641 #if defined(TARGET_PPC64)
642 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
643 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
644 0, crfD(ctx->opcode));
645 else
646 #endif
647 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
648 0, crfD(ctx->opcode));
649 }
650
651 /* cmpli */
652 static void gen_cmpli(DisasContext *ctx)
653 {
654 #if defined(TARGET_PPC64)
655 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
656 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
657 0, crfD(ctx->opcode));
658 else
659 #endif
660 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
661 0, crfD(ctx->opcode));
662 }
663
664 /* isel (PowerPC 2.03 specification) */
665 static void gen_isel(DisasContext *ctx)
666 {
667 int l1, l2;
668 uint32_t bi = rC(ctx->opcode);
669 uint32_t mask;
670 TCGv_i32 t0;
671
672 l1 = gen_new_label();
673 l2 = gen_new_label();
674
675 mask = 1 << (3 - (bi & 0x03));
676 t0 = tcg_temp_new_i32();
677 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
678 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
679 if (rA(ctx->opcode) == 0)
680 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
681 else
682 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
683 tcg_gen_br(l2);
684 gen_set_label(l1);
685 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
686 gen_set_label(l2);
687 tcg_temp_free_i32(t0);
688 }
689
690 /*** Integer arithmetic ***/
691
692 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
693 {
694 int l1;
695 TCGv t0;
696
697 l1 = gen_new_label();
698 /* Start with XER OV disabled, the most likely case */
699 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
700 t0 = tcg_temp_local_new();
701 tcg_gen_xor_tl(t0, arg0, arg1);
702 #if defined(TARGET_PPC64)
703 if (!ctx->sf_mode)
704 tcg_gen_ext32s_tl(t0, t0);
705 #endif
706 if (sub)
707 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
708 else
709 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
710 tcg_gen_xor_tl(t0, arg1, arg2);
711 #if defined(TARGET_PPC64)
712 if (!ctx->sf_mode)
713 tcg_gen_ext32s_tl(t0, t0);
714 #endif
715 if (sub)
716 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
717 else
718 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
719 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
720 gen_set_label(l1);
721 tcg_temp_free(t0);
722 }
723
724 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
725 {
726 int l1 = gen_new_label();
727
728 #if defined(TARGET_PPC64)
729 if (!(ctx->sf_mode)) {
730 TCGv t0, t1;
731 t0 = tcg_temp_new();
732 t1 = tcg_temp_new();
733
734 tcg_gen_ext32u_tl(t0, arg1);
735 tcg_gen_ext32u_tl(t1, arg2);
736 if (sub) {
737 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
738 } else {
739 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
740 }
741 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
742 gen_set_label(l1);
743 tcg_temp_free(t0);
744 tcg_temp_free(t1);
745 } else
746 #endif
747 {
748 if (sub) {
749 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
750 } else {
751 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
752 }
753 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
754 gen_set_label(l1);
755 }
756 }
757
758 /* Common add function */
759 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
760 int add_ca, int compute_ca, int compute_ov)
761 {
762 TCGv t0, t1;
763
764 if ((!compute_ca && !compute_ov) ||
765 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
766 t0 = ret;
767 } else {
768 t0 = tcg_temp_local_new();
769 }
770
771 if (add_ca) {
772 t1 = tcg_temp_local_new();
773 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
774 tcg_gen_shri_tl(t1, t1, XER_CA);
775 } else {
776 TCGV_UNUSED(t1);
777 }
778
779 if (compute_ca && compute_ov) {
780 /* Start with XER CA and OV disabled, the most likely case */
781 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
782 } else if (compute_ca) {
783 /* Start with XER CA disabled, the most likely case */
784 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
785 } else if (compute_ov) {
786 /* Start with XER OV disabled, the most likely case */
787 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
788 }
789
790 tcg_gen_add_tl(t0, arg1, arg2);
791
792 if (compute_ca) {
793 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
794 }
795 if (add_ca) {
796 tcg_gen_add_tl(t0, t0, t1);
797 gen_op_arith_compute_ca(ctx, t0, t1, 0);
798 tcg_temp_free(t1);
799 }
800 if (compute_ov) {
801 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
802 }
803
804 if (unlikely(Rc(ctx->opcode) != 0))
805 gen_set_Rc0(ctx, t0);
806
807 if (!TCGV_EQUAL(t0, ret)) {
808 tcg_gen_mov_tl(ret, t0);
809 tcg_temp_free(t0);
810 }
811 }
812 /* Add functions with two operands */
813 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
814 static void glue(gen_, name)(DisasContext *ctx) \
815 { \
816 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
817 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
818 add_ca, compute_ca, compute_ov); \
819 }
820 /* Add functions with one operand and one immediate */
821 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
822 add_ca, compute_ca, compute_ov) \
823 static void glue(gen_, name)(DisasContext *ctx) \
824 { \
825 TCGv t0 = tcg_const_local_tl(const_val); \
826 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
827 cpu_gpr[rA(ctx->opcode)], t0, \
828 add_ca, compute_ca, compute_ov); \
829 tcg_temp_free(t0); \
830 }
831
832 /* add add. addo addo. */
833 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
834 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
835 /* addc addc. addco addco. */
836 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
837 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
838 /* adde adde. addeo addeo. */
839 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
840 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
841 /* addme addme. addmeo addmeo. */
842 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
843 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
844 /* addze addze. addzeo addzeo.*/
845 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
846 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
847 /* addi */
848 static void gen_addi(DisasContext *ctx)
849 {
850 target_long simm = SIMM(ctx->opcode);
851
852 if (rA(ctx->opcode) == 0) {
853 /* li case */
854 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
855 } else {
856 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
857 }
858 }
859 /* addic addic.*/
860 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
861 int compute_Rc0)
862 {
863 target_long simm = SIMM(ctx->opcode);
864
865 /* Start with XER CA and OV disabled, the most likely case */
866 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
867
868 if (likely(simm != 0)) {
869 TCGv t0 = tcg_temp_local_new();
870 tcg_gen_addi_tl(t0, arg1, simm);
871 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
872 tcg_gen_mov_tl(ret, t0);
873 tcg_temp_free(t0);
874 } else {
875 tcg_gen_mov_tl(ret, arg1);
876 }
877 if (compute_Rc0) {
878 gen_set_Rc0(ctx, ret);
879 }
880 }
881
882 static void gen_addic(DisasContext *ctx)
883 {
884 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
885 }
886
887 static void gen_addic_(DisasContext *ctx)
888 {
889 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
890 }
891
892 /* addis */
893 static void gen_addis(DisasContext *ctx)
894 {
895 target_long simm = SIMM(ctx->opcode);
896
897 if (rA(ctx->opcode) == 0) {
898 /* lis case */
899 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
900 } else {
901 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
902 }
903 }
904
905 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
906 int sign, int compute_ov)
907 {
908 int l1 = gen_new_label();
909 int l2 = gen_new_label();
910 TCGv_i32 t0 = tcg_temp_local_new_i32();
911 TCGv_i32 t1 = tcg_temp_local_new_i32();
912
913 tcg_gen_trunc_tl_i32(t0, arg1);
914 tcg_gen_trunc_tl_i32(t1, arg2);
915 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
916 if (sign) {
917 int l3 = gen_new_label();
918 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
919 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
920 gen_set_label(l3);
921 tcg_gen_div_i32(t0, t0, t1);
922 } else {
923 tcg_gen_divu_i32(t0, t0, t1);
924 }
925 if (compute_ov) {
926 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
927 }
928 tcg_gen_br(l2);
929 gen_set_label(l1);
930 if (sign) {
931 tcg_gen_sari_i32(t0, t0, 31);
932 } else {
933 tcg_gen_movi_i32(t0, 0);
934 }
935 if (compute_ov) {
936 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
937 }
938 gen_set_label(l2);
939 tcg_gen_extu_i32_tl(ret, t0);
940 tcg_temp_free_i32(t0);
941 tcg_temp_free_i32(t1);
942 if (unlikely(Rc(ctx->opcode) != 0))
943 gen_set_Rc0(ctx, ret);
944 }
945 /* Div functions */
946 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
947 static void glue(gen_, name)(DisasContext *ctx) \
948 { \
949 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
950 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
951 sign, compute_ov); \
952 }
953 /* divwu divwu. divwuo divwuo. */
954 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
955 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
956 /* divw divw. divwo divwo. */
957 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
958 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
959 #if defined(TARGET_PPC64)
960 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
961 int sign, int compute_ov)
962 {
963 int l1 = gen_new_label();
964 int l2 = gen_new_label();
965
966 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
967 if (sign) {
968 int l3 = gen_new_label();
969 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
970 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
971 gen_set_label(l3);
972 tcg_gen_div_i64(ret, arg1, arg2);
973 } else {
974 tcg_gen_divu_i64(ret, arg1, arg2);
975 }
976 if (compute_ov) {
977 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
978 }
979 tcg_gen_br(l2);
980 gen_set_label(l1);
981 if (sign) {
982 tcg_gen_sari_i64(ret, arg1, 63);
983 } else {
984 tcg_gen_movi_i64(ret, 0);
985 }
986 if (compute_ov) {
987 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
988 }
989 gen_set_label(l2);
990 if (unlikely(Rc(ctx->opcode) != 0))
991 gen_set_Rc0(ctx, ret);
992 }
993 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
994 static void glue(gen_, name)(DisasContext *ctx) \
995 { \
996 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
997 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
998 sign, compute_ov); \
999 }
1000 /* divwu divwu. divwuo divwuo. */
1001 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1002 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1003 /* divw divw. divwo divwo. */
1004 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1005 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1006 #endif
1007
1008 /* mulhw mulhw. */
1009 static void gen_mulhw(DisasContext *ctx)
1010 {
1011 TCGv_i64 t0, t1;
1012
1013 t0 = tcg_temp_new_i64();
1014 t1 = tcg_temp_new_i64();
1015 #if defined(TARGET_PPC64)
1016 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1017 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1018 tcg_gen_mul_i64(t0, t0, t1);
1019 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1020 #else
1021 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1022 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1023 tcg_gen_mul_i64(t0, t0, t1);
1024 tcg_gen_shri_i64(t0, t0, 32);
1025 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1026 #endif
1027 tcg_temp_free_i64(t0);
1028 tcg_temp_free_i64(t1);
1029 if (unlikely(Rc(ctx->opcode) != 0))
1030 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1031 }
1032
1033 /* mulhwu mulhwu. */
1034 static void gen_mulhwu(DisasContext *ctx)
1035 {
1036 TCGv_i64 t0, t1;
1037
1038 t0 = tcg_temp_new_i64();
1039 t1 = tcg_temp_new_i64();
1040 #if defined(TARGET_PPC64)
1041 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1042 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1043 tcg_gen_mul_i64(t0, t0, t1);
1044 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1045 #else
1046 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1047 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1048 tcg_gen_mul_i64(t0, t0, t1);
1049 tcg_gen_shri_i64(t0, t0, 32);
1050 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1051 #endif
1052 tcg_temp_free_i64(t0);
1053 tcg_temp_free_i64(t1);
1054 if (unlikely(Rc(ctx->opcode) != 0))
1055 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1056 }
1057
1058 /* mullw mullw. */
1059 static void gen_mullw(DisasContext *ctx)
1060 {
1061 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1062 cpu_gpr[rB(ctx->opcode)]);
1063 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1064 if (unlikely(Rc(ctx->opcode) != 0))
1065 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1066 }
1067
1068 /* mullwo mullwo. */
1069 static void gen_mullwo(DisasContext *ctx)
1070 {
1071 int l1;
1072 TCGv_i64 t0, t1;
1073
1074 t0 = tcg_temp_new_i64();
1075 t1 = tcg_temp_new_i64();
1076 l1 = gen_new_label();
1077 /* Start with XER OV disabled, the most likely case */
1078 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1079 #if defined(TARGET_PPC64)
1080 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1081 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1082 #else
1083 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1084 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1085 #endif
1086 tcg_gen_mul_i64(t0, t0, t1);
1087 #if defined(TARGET_PPC64)
1088 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1089 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1090 #else
1091 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1092 tcg_gen_ext32s_i64(t1, t0);
1093 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1094 #endif
1095 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1096 gen_set_label(l1);
1097 tcg_temp_free_i64(t0);
1098 tcg_temp_free_i64(t1);
1099 if (unlikely(Rc(ctx->opcode) != 0))
1100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1101 }
1102
1103 /* mulli */
1104 static void gen_mulli(DisasContext *ctx)
1105 {
1106 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1107 SIMM(ctx->opcode));
1108 }
1109 #if defined(TARGET_PPC64)
1110 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1111 static void glue(gen_, name)(DisasContext *ctx) \
1112 { \
1113 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1114 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1115 if (unlikely(Rc(ctx->opcode) != 0)) \
1116 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1117 }
1118 /* mulhd mulhd. */
1119 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1120 /* mulhdu mulhdu. */
1121 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1122
1123 /* mulld mulld. */
1124 static void gen_mulld(DisasContext *ctx)
1125 {
1126 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1127 cpu_gpr[rB(ctx->opcode)]);
1128 if (unlikely(Rc(ctx->opcode) != 0))
1129 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1130 }
1131 /* mulldo mulldo. */
1132 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1133 #endif
1134
1135 /* neg neg. nego nego. */
1136 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1137 {
1138 int l1 = gen_new_label();
1139 int l2 = gen_new_label();
1140 TCGv t0 = tcg_temp_local_new();
1141 #if defined(TARGET_PPC64)
1142 if (ctx->sf_mode) {
1143 tcg_gen_mov_tl(t0, arg1);
1144 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1145 } else
1146 #endif
1147 {
1148 tcg_gen_ext32s_tl(t0, arg1);
1149 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1150 }
1151 tcg_gen_neg_tl(ret, arg1);
1152 if (ov_check) {
1153 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1154 }
1155 tcg_gen_br(l2);
1156 gen_set_label(l1);
1157 tcg_gen_mov_tl(ret, t0);
1158 if (ov_check) {
1159 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1160 }
1161 gen_set_label(l2);
1162 tcg_temp_free(t0);
1163 if (unlikely(Rc(ctx->opcode) != 0))
1164 gen_set_Rc0(ctx, ret);
1165 }
1166
1167 static void gen_neg(DisasContext *ctx)
1168 {
1169 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1170 }
1171
1172 static void gen_nego(DisasContext *ctx)
1173 {
1174 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1175 }
1176
1177 /* Common subf function */
1178 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1179 int add_ca, int compute_ca, int compute_ov)
1180 {
1181 TCGv t0, t1;
1182
1183 if ((!compute_ca && !compute_ov) ||
1184 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1185 t0 = ret;
1186 } else {
1187 t0 = tcg_temp_local_new();
1188 }
1189
1190 if (add_ca) {
1191 t1 = tcg_temp_local_new();
1192 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1193 tcg_gen_shri_tl(t1, t1, XER_CA);
1194 } else {
1195 TCGV_UNUSED(t1);
1196 }
1197
1198 if (compute_ca && compute_ov) {
1199 /* Start with XER CA and OV disabled, the most likely case */
1200 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1201 } else if (compute_ca) {
1202 /* Start with XER CA disabled, the most likely case */
1203 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1204 } else if (compute_ov) {
1205 /* Start with XER OV disabled, the most likely case */
1206 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1207 }
1208
1209 if (add_ca) {
1210 tcg_gen_not_tl(t0, arg1);
1211 tcg_gen_add_tl(t0, t0, arg2);
1212 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1213 tcg_gen_add_tl(t0, t0, t1);
1214 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1215 tcg_temp_free(t1);
1216 } else {
1217 tcg_gen_sub_tl(t0, arg2, arg1);
1218 if (compute_ca) {
1219 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1220 }
1221 }
1222 if (compute_ov) {
1223 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1224 }
1225
1226 if (unlikely(Rc(ctx->opcode) != 0))
1227 gen_set_Rc0(ctx, t0);
1228
1229 if (!TCGV_EQUAL(t0, ret)) {
1230 tcg_gen_mov_tl(ret, t0);
1231 tcg_temp_free(t0);
1232 }
1233 }
1234 /* Sub functions with Two operands functions */
1235 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1236 static void glue(gen_, name)(DisasContext *ctx) \
1237 { \
1238 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1239 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1240 add_ca, compute_ca, compute_ov); \
1241 }
1242 /* Sub functions with one operand and one immediate */
1243 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1244 add_ca, compute_ca, compute_ov) \
1245 static void glue(gen_, name)(DisasContext *ctx) \
1246 { \
1247 TCGv t0 = tcg_const_local_tl(const_val); \
1248 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1249 cpu_gpr[rA(ctx->opcode)], t0, \
1250 add_ca, compute_ca, compute_ov); \
1251 tcg_temp_free(t0); \
1252 }
1253 /* subf subf. subfo subfo. */
1254 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1255 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1256 /* subfc subfc. subfco subfco. */
1257 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1258 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1259 /* subfe subfe. subfeo subfo. */
1260 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1261 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1262 /* subfme subfme. subfmeo subfmeo. */
1263 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1264 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1265 /* subfze subfze. subfzeo subfzeo.*/
1266 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1267 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1268
1269 /* subfic */
1270 static void gen_subfic(DisasContext *ctx)
1271 {
1272 /* Start with XER CA and OV disabled, the most likely case */
1273 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1274 TCGv t0 = tcg_temp_local_new();
1275 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1276 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1277 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1278 tcg_temp_free(t1);
1279 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1280 tcg_temp_free(t0);
1281 }
1282
1283 /*** Integer logical ***/
1284 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1285 static void glue(gen_, name)(DisasContext *ctx) \
1286 { \
1287 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1288 cpu_gpr[rB(ctx->opcode)]); \
1289 if (unlikely(Rc(ctx->opcode) != 0)) \
1290 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1291 }
1292
1293 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1294 static void glue(gen_, name)(DisasContext *ctx) \
1295 { \
1296 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1297 if (unlikely(Rc(ctx->opcode) != 0)) \
1298 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1299 }
1300
1301 /* and & and. */
1302 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1303 /* andc & andc. */
1304 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1305
1306 /* andi. */
1307 static void gen_andi_(DisasContext *ctx)
1308 {
1309 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1310 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1311 }
1312
1313 /* andis. */
1314 static void gen_andis_(DisasContext *ctx)
1315 {
1316 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1317 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1318 }
1319
1320 /* cntlzw */
1321 static void gen_cntlzw(DisasContext *ctx)
1322 {
1323 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1324 if (unlikely(Rc(ctx->opcode) != 0))
1325 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1326 }
1327 /* eqv & eqv. */
1328 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1329 /* extsb & extsb. */
1330 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1331 /* extsh & extsh. */
1332 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1333 /* nand & nand. */
1334 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1335 /* nor & nor. */
1336 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1337
1338 /* or & or. */
1339 static void gen_or(DisasContext *ctx)
1340 {
1341 int rs, ra, rb;
1342
1343 rs = rS(ctx->opcode);
1344 ra = rA(ctx->opcode);
1345 rb = rB(ctx->opcode);
1346 /* Optimisation for mr. ri case */
1347 if (rs != ra || rs != rb) {
1348 if (rs != rb)
1349 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1350 else
1351 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1352 if (unlikely(Rc(ctx->opcode) != 0))
1353 gen_set_Rc0(ctx, cpu_gpr[ra]);
1354 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1355 gen_set_Rc0(ctx, cpu_gpr[rs]);
1356 #if defined(TARGET_PPC64)
1357 } else {
1358 int prio = 0;
1359
1360 switch (rs) {
1361 case 1:
1362 /* Set process priority to low */
1363 prio = 2;
1364 break;
1365 case 6:
1366 /* Set process priority to medium-low */
1367 prio = 3;
1368 break;
1369 case 2:
1370 /* Set process priority to normal */
1371 prio = 4;
1372 break;
1373 #if !defined(CONFIG_USER_ONLY)
1374 case 31:
1375 if (ctx->mem_idx > 0) {
1376 /* Set process priority to very low */
1377 prio = 1;
1378 }
1379 break;
1380 case 5:
1381 if (ctx->mem_idx > 0) {
1382 /* Set process priority to medium-hight */
1383 prio = 5;
1384 }
1385 break;
1386 case 3:
1387 if (ctx->mem_idx > 0) {
1388 /* Set process priority to high */
1389 prio = 6;
1390 }
1391 break;
1392 case 7:
1393 if (ctx->mem_idx > 1) {
1394 /* Set process priority to very high */
1395 prio = 7;
1396 }
1397 break;
1398 #endif
1399 default:
1400 /* nop */
1401 break;
1402 }
1403 if (prio) {
1404 TCGv t0 = tcg_temp_new();
1405 gen_load_spr(t0, SPR_PPR);
1406 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1407 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1408 gen_store_spr(SPR_PPR, t0);
1409 tcg_temp_free(t0);
1410 }
1411 #endif
1412 }
1413 }
1414 /* orc & orc. */
1415 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1416
1417 /* xor & xor. */
1418 static void gen_xor(DisasContext *ctx)
1419 {
1420 /* Optimisation for "set to zero" case */
1421 if (rS(ctx->opcode) != rB(ctx->opcode))
1422 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1423 else
1424 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1425 if (unlikely(Rc(ctx->opcode) != 0))
1426 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1427 }
1428
1429 /* ori */
1430 static void gen_ori(DisasContext *ctx)
1431 {
1432 target_ulong uimm = UIMM(ctx->opcode);
1433
1434 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1435 /* NOP */
1436 /* XXX: should handle special NOPs for POWER series */
1437 return;
1438 }
1439 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1440 }
1441
1442 /* oris */
1443 static void gen_oris(DisasContext *ctx)
1444 {
1445 target_ulong uimm = UIMM(ctx->opcode);
1446
1447 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1448 /* NOP */
1449 return;
1450 }
1451 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1452 }
1453
1454 /* xori */
1455 static void gen_xori(DisasContext *ctx)
1456 {
1457 target_ulong uimm = UIMM(ctx->opcode);
1458
1459 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1460 /* NOP */
1461 return;
1462 }
1463 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1464 }
1465
1466 /* xoris */
1467 static void gen_xoris(DisasContext *ctx)
1468 {
1469 target_ulong uimm = UIMM(ctx->opcode);
1470
1471 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1472 /* NOP */
1473 return;
1474 }
1475 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1476 }
1477
1478 /* popcntb : PowerPC 2.03 specification */
1479 static void gen_popcntb(DisasContext *ctx)
1480 {
1481 #if defined(TARGET_PPC64)
1482 if (ctx->sf_mode)
1483 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1484 else
1485 #endif
1486 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1487 }
1488
1489 #if defined(TARGET_PPC64)
1490 /* extsw & extsw. */
1491 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1492
1493 /* cntlzd */
1494 static void gen_cntlzd(DisasContext *ctx)
1495 {
1496 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1497 if (unlikely(Rc(ctx->opcode) != 0))
1498 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1499 }
1500 #endif
1501
1502 /*** Integer rotate ***/
1503
1504 /* rlwimi & rlwimi. */
1505 static void gen_rlwimi(DisasContext *ctx)
1506 {
1507 uint32_t mb, me, sh;
1508
1509 mb = MB(ctx->opcode);
1510 me = ME(ctx->opcode);
1511 sh = SH(ctx->opcode);
1512 if (likely(sh == 0 && mb == 0 && me == 31)) {
1513 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1514 } else {
1515 target_ulong mask;
1516 TCGv t1;
1517 TCGv t0 = tcg_temp_new();
1518 #if defined(TARGET_PPC64)
1519 TCGv_i32 t2 = tcg_temp_new_i32();
1520 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1521 tcg_gen_rotli_i32(t2, t2, sh);
1522 tcg_gen_extu_i32_i64(t0, t2);
1523 tcg_temp_free_i32(t2);
1524 #else
1525 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1526 #endif
1527 #if defined(TARGET_PPC64)
1528 mb += 32;
1529 me += 32;
1530 #endif
1531 mask = MASK(mb, me);
1532 t1 = tcg_temp_new();
1533 tcg_gen_andi_tl(t0, t0, mask);
1534 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1535 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1536 tcg_temp_free(t0);
1537 tcg_temp_free(t1);
1538 }
1539 if (unlikely(Rc(ctx->opcode) != 0))
1540 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1541 }
1542
1543 /* rlwinm & rlwinm. */
1544 static void gen_rlwinm(DisasContext *ctx)
1545 {
1546 uint32_t mb, me, sh;
1547
1548 sh = SH(ctx->opcode);
1549 mb = MB(ctx->opcode);
1550 me = ME(ctx->opcode);
1551
1552 if (likely(mb == 0 && me == (31 - sh))) {
1553 if (likely(sh == 0)) {
1554 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1555 } else {
1556 TCGv t0 = tcg_temp_new();
1557 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1558 tcg_gen_shli_tl(t0, t0, sh);
1559 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1560 tcg_temp_free(t0);
1561 }
1562 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1563 TCGv t0 = tcg_temp_new();
1564 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1565 tcg_gen_shri_tl(t0, t0, mb);
1566 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1567 tcg_temp_free(t0);
1568 } else {
1569 TCGv t0 = tcg_temp_new();
1570 #if defined(TARGET_PPC64)
1571 TCGv_i32 t1 = tcg_temp_new_i32();
1572 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1573 tcg_gen_rotli_i32(t1, t1, sh);
1574 tcg_gen_extu_i32_i64(t0, t1);
1575 tcg_temp_free_i32(t1);
1576 #else
1577 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1578 #endif
1579 #if defined(TARGET_PPC64)
1580 mb += 32;
1581 me += 32;
1582 #endif
1583 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1584 tcg_temp_free(t0);
1585 }
1586 if (unlikely(Rc(ctx->opcode) != 0))
1587 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1588 }
1589
1590 /* rlwnm & rlwnm. */
1591 static void gen_rlwnm(DisasContext *ctx)
1592 {
1593 uint32_t mb, me;
1594 TCGv t0;
1595 #if defined(TARGET_PPC64)
1596 TCGv_i32 t1, t2;
1597 #endif
1598
1599 mb = MB(ctx->opcode);
1600 me = ME(ctx->opcode);
1601 t0 = tcg_temp_new();
1602 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1603 #if defined(TARGET_PPC64)
1604 t1 = tcg_temp_new_i32();
1605 t2 = tcg_temp_new_i32();
1606 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1607 tcg_gen_trunc_i64_i32(t2, t0);
1608 tcg_gen_rotl_i32(t1, t1, t2);
1609 tcg_gen_extu_i32_i64(t0, t1);
1610 tcg_temp_free_i32(t1);
1611 tcg_temp_free_i32(t2);
1612 #else
1613 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1614 #endif
1615 if (unlikely(mb != 0 || me != 31)) {
1616 #if defined(TARGET_PPC64)
1617 mb += 32;
1618 me += 32;
1619 #endif
1620 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1621 } else {
1622 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1623 }
1624 tcg_temp_free(t0);
1625 if (unlikely(Rc(ctx->opcode) != 0))
1626 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1627 }
1628
1629 #if defined(TARGET_PPC64)
1630 #define GEN_PPC64_R2(name, opc1, opc2) \
1631 static void glue(gen_, name##0)(DisasContext *ctx) \
1632 { \
1633 gen_##name(ctx, 0); \
1634 } \
1635 \
1636 static void glue(gen_, name##1)(DisasContext *ctx) \
1637 { \
1638 gen_##name(ctx, 1); \
1639 }
1640 #define GEN_PPC64_R4(name, opc1, opc2) \
1641 static void glue(gen_, name##0)(DisasContext *ctx) \
1642 { \
1643 gen_##name(ctx, 0, 0); \
1644 } \
1645 \
1646 static void glue(gen_, name##1)(DisasContext *ctx) \
1647 { \
1648 gen_##name(ctx, 0, 1); \
1649 } \
1650 \
1651 static void glue(gen_, name##2)(DisasContext *ctx) \
1652 { \
1653 gen_##name(ctx, 1, 0); \
1654 } \
1655 \
1656 static void glue(gen_, name##3)(DisasContext *ctx) \
1657 { \
1658 gen_##name(ctx, 1, 1); \
1659 }
1660
1661 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1662 uint32_t me, uint32_t sh)
1663 {
1664 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1665 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1666 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1667 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1668 } else {
1669 TCGv t0 = tcg_temp_new();
1670 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1671 if (likely(mb == 0 && me == 63)) {
1672 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1673 } else {
1674 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1675 }
1676 tcg_temp_free(t0);
1677 }
1678 if (unlikely(Rc(ctx->opcode) != 0))
1679 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1680 }
1681 /* rldicl - rldicl. */
1682 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1683 {
1684 uint32_t sh, mb;
1685
1686 sh = SH(ctx->opcode) | (shn << 5);
1687 mb = MB(ctx->opcode) | (mbn << 5);
1688 gen_rldinm(ctx, mb, 63, sh);
1689 }
1690 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1691 /* rldicr - rldicr. */
1692 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1693 {
1694 uint32_t sh, me;
1695
1696 sh = SH(ctx->opcode) | (shn << 5);
1697 me = MB(ctx->opcode) | (men << 5);
1698 gen_rldinm(ctx, 0, me, sh);
1699 }
1700 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1701 /* rldic - rldic. */
1702 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1703 {
1704 uint32_t sh, mb;
1705
1706 sh = SH(ctx->opcode) | (shn << 5);
1707 mb = MB(ctx->opcode) | (mbn << 5);
1708 gen_rldinm(ctx, mb, 63 - sh, sh);
1709 }
1710 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1711
1712 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1713 uint32_t me)
1714 {
1715 TCGv t0;
1716
1717 mb = MB(ctx->opcode);
1718 me = ME(ctx->opcode);
1719 t0 = tcg_temp_new();
1720 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1721 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1722 if (unlikely(mb != 0 || me != 63)) {
1723 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1724 } else {
1725 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1726 }
1727 tcg_temp_free(t0);
1728 if (unlikely(Rc(ctx->opcode) != 0))
1729 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1730 }
1731
1732 /* rldcl - rldcl. */
1733 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1734 {
1735 uint32_t mb;
1736
1737 mb = MB(ctx->opcode) | (mbn << 5);
1738 gen_rldnm(ctx, mb, 63);
1739 }
1740 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1741 /* rldcr - rldcr. */
1742 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1743 {
1744 uint32_t me;
1745
1746 me = MB(ctx->opcode) | (men << 5);
1747 gen_rldnm(ctx, 0, me);
1748 }
1749 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1750 /* rldimi - rldimi. */
1751 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1752 {
1753 uint32_t sh, mb, me;
1754
1755 sh = SH(ctx->opcode) | (shn << 5);
1756 mb = MB(ctx->opcode) | (mbn << 5);
1757 me = 63 - sh;
1758 if (unlikely(sh == 0 && mb == 0)) {
1759 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1760 } else {
1761 TCGv t0, t1;
1762 target_ulong mask;
1763
1764 t0 = tcg_temp_new();
1765 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1766 t1 = tcg_temp_new();
1767 mask = MASK(mb, me);
1768 tcg_gen_andi_tl(t0, t0, mask);
1769 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1770 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1771 tcg_temp_free(t0);
1772 tcg_temp_free(t1);
1773 }
1774 if (unlikely(Rc(ctx->opcode) != 0))
1775 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1776 }
1777 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1778 #endif
1779
1780 /*** Integer shift ***/
1781
1782 /* slw & slw. */
1783 static void gen_slw(DisasContext *ctx)
1784 {
1785 TCGv t0;
1786 int l1, l2;
1787 l1 = gen_new_label();
1788 l2 = gen_new_label();
1789
1790 t0 = tcg_temp_local_new();
1791 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1792 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1793 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1794 tcg_gen_br(l2);
1795 gen_set_label(l1);
1796 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1797 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1798 gen_set_label(l2);
1799 tcg_temp_free(t0);
1800 if (unlikely(Rc(ctx->opcode) != 0))
1801 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1802 }
1803
1804 /* sraw & sraw. */
1805 static void gen_sraw(DisasContext *ctx)
1806 {
1807 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1808 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1809 if (unlikely(Rc(ctx->opcode) != 0))
1810 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1811 }
1812
1813 /* srawi & srawi. */
1814 static void gen_srawi(DisasContext *ctx)
1815 {
1816 int sh = SH(ctx->opcode);
1817 if (sh != 0) {
1818 int l1, l2;
1819 TCGv t0;
1820 l1 = gen_new_label();
1821 l2 = gen_new_label();
1822 t0 = tcg_temp_local_new();
1823 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1824 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1825 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1826 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1827 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1828 tcg_gen_br(l2);
1829 gen_set_label(l1);
1830 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1831 gen_set_label(l2);
1832 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1833 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1834 tcg_temp_free(t0);
1835 } else {
1836 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1837 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1838 }
1839 if (unlikely(Rc(ctx->opcode) != 0))
1840 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1841 }
1842
1843 /* srw & srw. */
1844 static void gen_srw(DisasContext *ctx)
1845 {
1846 TCGv t0, t1;
1847 int l1, l2;
1848 l1 = gen_new_label();
1849 l2 = gen_new_label();
1850
1851 t0 = tcg_temp_local_new();
1852 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1853 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1854 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1855 tcg_gen_br(l2);
1856 gen_set_label(l1);
1857 t1 = tcg_temp_new();
1858 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1859 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1860 tcg_temp_free(t1);
1861 gen_set_label(l2);
1862 tcg_temp_free(t0);
1863 if (unlikely(Rc(ctx->opcode) != 0))
1864 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1865 }
1866
1867 #if defined(TARGET_PPC64)
1868 /* sld & sld. */
1869 static void gen_sld(DisasContext *ctx)
1870 {
1871 TCGv t0;
1872 int l1, l2;
1873 l1 = gen_new_label();
1874 l2 = gen_new_label();
1875
1876 t0 = tcg_temp_local_new();
1877 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
1878 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
1879 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1880 tcg_gen_br(l2);
1881 gen_set_label(l1);
1882 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1883 gen_set_label(l2);
1884 tcg_temp_free(t0);
1885 if (unlikely(Rc(ctx->opcode) != 0))
1886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1887 }
1888
1889 /* srad & srad. */
1890 static void gen_srad(DisasContext *ctx)
1891 {
1892 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
1893 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1894 if (unlikely(Rc(ctx->opcode) != 0))
1895 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1896 }
1897 /* sradi & sradi. */
1898 static always_inline void gen_sradi (DisasContext *ctx, int n)
1899 {
1900 int sh = SH(ctx->opcode) + (n << 5);
1901 if (sh != 0) {
1902 int l1, l2;
1903 TCGv t0;
1904 l1 = gen_new_label();
1905 l2 = gen_new_label();
1906 t0 = tcg_temp_local_new();
1907 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1908 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1909 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1910 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1911 tcg_gen_br(l2);
1912 gen_set_label(l1);
1913 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1914 gen_set_label(l2);
1915 tcg_temp_free(t0);
1916 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1917 } else {
1918 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1919 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1920 }
1921 if (unlikely(Rc(ctx->opcode) != 0))
1922 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1923 }
1924
1925 static void gen_sradi0(DisasContext *ctx)
1926 {
1927 gen_sradi(ctx, 0);
1928 }
1929
1930 static void gen_sradi1(DisasContext *ctx)
1931 {
1932 gen_sradi(ctx, 1);
1933 }
1934
1935 /* srd & srd. */
1936 static void gen_srd(DisasContext *ctx)
1937 {
1938 TCGv t0;
1939 int l1, l2;
1940 l1 = gen_new_label();
1941 l2 = gen_new_label();
1942
1943 t0 = tcg_temp_local_new();
1944 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
1945 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
1946 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1947 tcg_gen_br(l2);
1948 gen_set_label(l1);
1949 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1950 gen_set_label(l2);
1951 tcg_temp_free(t0);
1952 if (unlikely(Rc(ctx->opcode) != 0))
1953 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1954 }
1955 #endif
1956
1957 /*** Floating-Point arithmetic ***/
1958 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1959 static void gen_f##name(DisasContext *ctx) \
1960 { \
1961 if (unlikely(!ctx->fpu_enabled)) { \
1962 gen_exception(ctx, POWERPC_EXCP_FPU); \
1963 return; \
1964 } \
1965 /* NIP cannot be restored if the memory exception comes from an helper */ \
1966 gen_update_nip(ctx, ctx->nip - 4); \
1967 gen_reset_fpstatus(); \
1968 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
1969 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1970 if (isfloat) { \
1971 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
1972 } \
1973 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1974 Rc(ctx->opcode) != 0); \
1975 }
1976
1977 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1978 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1979 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1980
1981 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1982 static void gen_f##name(DisasContext *ctx) \
1983 { \
1984 if (unlikely(!ctx->fpu_enabled)) { \
1985 gen_exception(ctx, POWERPC_EXCP_FPU); \
1986 return; \
1987 } \
1988 /* NIP cannot be restored if the memory exception comes from an helper */ \
1989 gen_update_nip(ctx, ctx->nip - 4); \
1990 gen_reset_fpstatus(); \
1991 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
1992 cpu_fpr[rB(ctx->opcode)]); \
1993 if (isfloat) { \
1994 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
1995 } \
1996 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1997 set_fprf, Rc(ctx->opcode) != 0); \
1998 }
1999 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2000 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2001 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2002
2003 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2004 static void gen_f##name(DisasContext *ctx) \
2005 { \
2006 if (unlikely(!ctx->fpu_enabled)) { \
2007 gen_exception(ctx, POWERPC_EXCP_FPU); \
2008 return; \
2009 } \
2010 /* NIP cannot be restored if the memory exception comes from an helper */ \
2011 gen_update_nip(ctx, ctx->nip - 4); \
2012 gen_reset_fpstatus(); \
2013 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2014 cpu_fpr[rC(ctx->opcode)]); \
2015 if (isfloat) { \
2016 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2017 } \
2018 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2019 set_fprf, Rc(ctx->opcode) != 0); \
2020 }
2021 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2022 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2023 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2024
2025 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2026 static void gen_f##name(DisasContext *ctx) \
2027 { \
2028 if (unlikely(!ctx->fpu_enabled)) { \
2029 gen_exception(ctx, POWERPC_EXCP_FPU); \
2030 return; \
2031 } \
2032 /* NIP cannot be restored if the memory exception comes from an helper */ \
2033 gen_update_nip(ctx, ctx->nip - 4); \
2034 gen_reset_fpstatus(); \
2035 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2036 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2037 set_fprf, Rc(ctx->opcode) != 0); \
2038 }
2039
2040 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2041 static void gen_f##name(DisasContext *ctx) \
2042 { \
2043 if (unlikely(!ctx->fpu_enabled)) { \
2044 gen_exception(ctx, POWERPC_EXCP_FPU); \
2045 return; \
2046 } \
2047 /* NIP cannot be restored if the memory exception comes from an helper */ \
2048 gen_update_nip(ctx, ctx->nip - 4); \
2049 gen_reset_fpstatus(); \
2050 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2051 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2052 set_fprf, Rc(ctx->opcode) != 0); \
2053 }
2054
2055 /* fadd - fadds */
2056 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2057 /* fdiv - fdivs */
2058 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2059 /* fmul - fmuls */
2060 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2061
2062 /* fre */
2063 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2064
2065 /* fres */
2066 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2067
2068 /* frsqrte */
2069 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2070
2071 /* frsqrtes */
2072 static void gen_frsqrtes(DisasContext *ctx)
2073 {
2074 if (unlikely(!ctx->fpu_enabled)) {
2075 gen_exception(ctx, POWERPC_EXCP_FPU);
2076 return;
2077 }
2078 /* NIP cannot be restored if the memory exception comes from an helper */
2079 gen_update_nip(ctx, ctx->nip - 4);
2080 gen_reset_fpstatus();
2081 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2082 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2083 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2084 }
2085
2086 /* fsel */
2087 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2088 /* fsub - fsubs */
2089 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2090 /* Optional: */
2091
2092 /* fsqrt */
2093 static void gen_fsqrt(DisasContext *ctx)
2094 {
2095 if (unlikely(!ctx->fpu_enabled)) {
2096 gen_exception(ctx, POWERPC_EXCP_FPU);
2097 return;
2098 }
2099 /* NIP cannot be restored if the memory exception comes from an helper */
2100 gen_update_nip(ctx, ctx->nip - 4);
2101 gen_reset_fpstatus();
2102 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2103 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2104 }
2105
2106 static void gen_fsqrts(DisasContext *ctx)
2107 {
2108 if (unlikely(!ctx->fpu_enabled)) {
2109 gen_exception(ctx, POWERPC_EXCP_FPU);
2110 return;
2111 }
2112 /* NIP cannot be restored if the memory exception comes from an helper */
2113 gen_update_nip(ctx, ctx->nip - 4);
2114 gen_reset_fpstatus();
2115 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2116 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2117 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2118 }
2119
2120 /*** Floating-Point multiply-and-add ***/
2121 /* fmadd - fmadds */
2122 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2123 /* fmsub - fmsubs */
2124 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2125 /* fnmadd - fnmadds */
2126 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2127 /* fnmsub - fnmsubs */
2128 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2129
2130 /*** Floating-Point round & convert ***/
2131 /* fctiw */
2132 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2133 /* fctiwz */
2134 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2135 /* frsp */
2136 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2137 #if defined(TARGET_PPC64)
2138 /* fcfid */
2139 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2140 /* fctid */
2141 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2142 /* fctidz */
2143 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2144 #endif
2145
2146 /* frin */
2147 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2148 /* friz */
2149 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2150 /* frip */
2151 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2152 /* frim */
2153 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2154
2155 /*** Floating-Point compare ***/
2156
2157 /* fcmpo */
2158 static void gen_fcmpo(DisasContext *ctx)
2159 {
2160 TCGv_i32 crf;
2161 if (unlikely(!ctx->fpu_enabled)) {
2162 gen_exception(ctx, POWERPC_EXCP_FPU);
2163 return;
2164 }
2165 /* NIP cannot be restored if the memory exception comes from an helper */
2166 gen_update_nip(ctx, ctx->nip - 4);
2167 gen_reset_fpstatus();
2168 crf = tcg_const_i32(crfD(ctx->opcode));
2169 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2170 tcg_temp_free_i32(crf);
2171 gen_helper_float_check_status();
2172 }
2173
2174 /* fcmpu */
2175 static void gen_fcmpu(DisasContext *ctx)
2176 {
2177 TCGv_i32 crf;
2178 if (unlikely(!ctx->fpu_enabled)) {
2179 gen_exception(ctx, POWERPC_EXCP_FPU);
2180 return;
2181 }
2182 /* NIP cannot be restored if the memory exception comes from an helper */
2183 gen_update_nip(ctx, ctx->nip - 4);
2184 gen_reset_fpstatus();
2185 crf = tcg_const_i32(crfD(ctx->opcode));
2186 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2187 tcg_temp_free_i32(crf);
2188 gen_helper_float_check_status();
2189 }
2190
2191 /*** Floating-point move ***/
2192 /* fabs */
2193 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2194 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2195
2196 /* fmr - fmr. */
2197 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2198 static void gen_fmr(DisasContext *ctx)
2199 {
2200 if (unlikely(!ctx->fpu_enabled)) {
2201 gen_exception(ctx, POWERPC_EXCP_FPU);
2202 return;
2203 }
2204 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2205 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2206 }
2207
2208 /* fnabs */
2209 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2210 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2211 /* fneg */
2212 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2213 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2214
2215 /*** Floating-Point status & ctrl register ***/
2216
2217 /* mcrfs */
2218 static void gen_mcrfs(DisasContext *ctx)
2219 {
2220 int bfa;
2221
2222 if (unlikely(!ctx->fpu_enabled)) {
2223 gen_exception(ctx, POWERPC_EXCP_FPU);
2224 return;
2225 }
2226 bfa = 4 * (7 - crfS(ctx->opcode));
2227 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2228 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2229 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2230 }
2231
2232 /* mffs */
2233 static void gen_mffs(DisasContext *ctx)
2234 {
2235 if (unlikely(!ctx->fpu_enabled)) {
2236 gen_exception(ctx, POWERPC_EXCP_FPU);
2237 return;
2238 }
2239 gen_reset_fpstatus();
2240 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2241 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2242 }
2243
2244 /* mtfsb0 */
2245 static void gen_mtfsb0(DisasContext *ctx)
2246 {
2247 uint8_t crb;
2248
2249 if (unlikely(!ctx->fpu_enabled)) {
2250 gen_exception(ctx, POWERPC_EXCP_FPU);
2251 return;
2252 }
2253 crb = 31 - crbD(ctx->opcode);
2254 gen_reset_fpstatus();
2255 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2256 TCGv_i32 t0;
2257 /* NIP cannot be restored if the memory exception comes from an helper */
2258 gen_update_nip(ctx, ctx->nip - 4);
2259 t0 = tcg_const_i32(crb);
2260 gen_helper_fpscr_clrbit(t0);
2261 tcg_temp_free_i32(t0);
2262 }
2263 if (unlikely(Rc(ctx->opcode) != 0)) {
2264 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2265 }
2266 }
2267
2268 /* mtfsb1 */
2269 static void gen_mtfsb1(DisasContext *ctx)
2270 {
2271 uint8_t crb;
2272
2273 if (unlikely(!ctx->fpu_enabled)) {
2274 gen_exception(ctx, POWERPC_EXCP_FPU);
2275 return;
2276 }
2277 crb = 31 - crbD(ctx->opcode);
2278 gen_reset_fpstatus();
2279 /* XXX: we pretend we can only do IEEE floating-point computations */
2280 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2281 TCGv_i32 t0;
2282 /* NIP cannot be restored if the memory exception comes from an helper */
2283 gen_update_nip(ctx, ctx->nip - 4);
2284 t0 = tcg_const_i32(crb);
2285 gen_helper_fpscr_setbit(t0);
2286 tcg_temp_free_i32(t0);
2287 }
2288 if (unlikely(Rc(ctx->opcode) != 0)) {
2289 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2290 }
2291 /* We can raise a differed exception */
2292 gen_helper_float_check_status();
2293 }
2294
2295 /* mtfsf */
2296 static void gen_mtfsf(DisasContext *ctx)
2297 {
2298 TCGv_i32 t0;
2299 int L = ctx->opcode & 0x02000000;
2300
2301 if (unlikely(!ctx->fpu_enabled)) {
2302 gen_exception(ctx, POWERPC_EXCP_FPU);
2303 return;
2304 }
2305 /* NIP cannot be restored if the memory exception comes from an helper */
2306 gen_update_nip(ctx, ctx->nip - 4);
2307 gen_reset_fpstatus();
2308 if (L)
2309 t0 = tcg_const_i32(0xff);
2310 else
2311 t0 = tcg_const_i32(FM(ctx->opcode));
2312 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2313 tcg_temp_free_i32(t0);
2314 if (unlikely(Rc(ctx->opcode) != 0)) {
2315 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2316 }
2317 /* We can raise a differed exception */
2318 gen_helper_float_check_status();
2319 }
2320
2321 /* mtfsfi */
2322 static void gen_mtfsfi(DisasContext *ctx)
2323 {
2324 int bf, sh;
2325 TCGv_i64 t0;
2326 TCGv_i32 t1;
2327
2328 if (unlikely(!ctx->fpu_enabled)) {
2329 gen_exception(ctx, POWERPC_EXCP_FPU);
2330 return;
2331 }
2332 bf = crbD(ctx->opcode) >> 2;
2333 sh = 7 - bf;
2334 /* NIP cannot be restored if the memory exception comes from an helper */
2335 gen_update_nip(ctx, ctx->nip - 4);
2336 gen_reset_fpstatus();
2337 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2338 t1 = tcg_const_i32(1 << sh);
2339 gen_helper_store_fpscr(t0, t1);
2340 tcg_temp_free_i64(t0);
2341 tcg_temp_free_i32(t1);
2342 if (unlikely(Rc(ctx->opcode) != 0)) {
2343 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2344 }
2345 /* We can raise a differed exception */
2346 gen_helper_float_check_status();
2347 }
2348
2349 /*** Addressing modes ***/
2350 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2351 static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2352 {
2353 target_long simm = SIMM(ctx->opcode);
2354
2355 simm &= ~maskl;
2356 if (rA(ctx->opcode) == 0) {
2357 #if defined(TARGET_PPC64)
2358 if (!ctx->sf_mode) {
2359 tcg_gen_movi_tl(EA, (uint32_t)simm);
2360 } else
2361 #endif
2362 tcg_gen_movi_tl(EA, simm);
2363 } else if (likely(simm != 0)) {
2364 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2365 #if defined(TARGET_PPC64)
2366 if (!ctx->sf_mode) {
2367 tcg_gen_ext32u_tl(EA, EA);
2368 }
2369 #endif
2370 } else {
2371 #if defined(TARGET_PPC64)
2372 if (!ctx->sf_mode) {
2373 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2374 } else
2375 #endif
2376 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2377 }
2378 }
2379
2380 static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2381 {
2382 if (rA(ctx->opcode) == 0) {
2383 #if defined(TARGET_PPC64)
2384 if (!ctx->sf_mode) {
2385 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2386 } else
2387 #endif
2388 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2389 } else {
2390 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2391 #if defined(TARGET_PPC64)
2392 if (!ctx->sf_mode) {
2393 tcg_gen_ext32u_tl(EA, EA);
2394 }
2395 #endif
2396 }
2397 }
2398
2399 static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2400 {
2401 if (rA(ctx->opcode) == 0) {
2402 tcg_gen_movi_tl(EA, 0);
2403 } else {
2404 #if defined(TARGET_PPC64)
2405 if (!ctx->sf_mode) {
2406 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2407 } else
2408 #endif
2409 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2410 }
2411 }
2412
2413 static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2414 {
2415 tcg_gen_addi_tl(ret, arg1, val);
2416 #if defined(TARGET_PPC64)
2417 if (!ctx->sf_mode) {
2418 tcg_gen_ext32u_tl(ret, ret);
2419 }
2420 #endif
2421 }
2422
2423 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2424 {
2425 int l1 = gen_new_label();
2426 TCGv t0 = tcg_temp_new();
2427 TCGv_i32 t1, t2;
2428 /* NIP cannot be restored if the memory exception comes from an helper */
2429 gen_update_nip(ctx, ctx->nip - 4);
2430 tcg_gen_andi_tl(t0, EA, mask);
2431 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2432 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2433 t2 = tcg_const_i32(0);
2434 gen_helper_raise_exception_err(t1, t2);
2435 tcg_temp_free_i32(t1);
2436 tcg_temp_free_i32(t2);
2437 gen_set_label(l1);
2438 tcg_temp_free(t0);
2439 }
2440
2441 /*** Integer load ***/
2442 static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2443 {
2444 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2445 }
2446
2447 static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2448 {
2449 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2450 }
2451
2452 static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2453 {
2454 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2455 if (unlikely(ctx->le_mode)) {
2456 tcg_gen_bswap16_tl(arg1, arg1);
2457 }
2458 }
2459
2460 static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2461 {
2462 if (unlikely(ctx->le_mode)) {
2463 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2464 tcg_gen_bswap16_tl(arg1, arg1);
2465 tcg_gen_ext16s_tl(arg1, arg1);
2466 } else {
2467 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2468 }
2469 }
2470
2471 static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2472 {
2473 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2474 if (unlikely(ctx->le_mode)) {
2475 tcg_gen_bswap32_tl(arg1, arg1);
2476 }
2477 }
2478
2479 #if defined(TARGET_PPC64)
2480 static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2481 {
2482 if (unlikely(ctx->le_mode)) {
2483 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2484 tcg_gen_bswap32_tl(arg1, arg1);
2485 tcg_gen_ext32s_tl(arg1, arg1);
2486 } else
2487 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2488 }
2489 #endif
2490
2491 static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2492 {
2493 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2494 if (unlikely(ctx->le_mode)) {
2495 tcg_gen_bswap64_i64(arg1, arg1);
2496 }
2497 }
2498
2499 static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2500 {
2501 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2502 }
2503
2504 static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2505 {
2506 if (unlikely(ctx->le_mode)) {
2507 TCGv t0 = tcg_temp_new();
2508 tcg_gen_ext16u_tl(t0, arg1);
2509 tcg_gen_bswap16_tl(t0, t0);
2510 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2511 tcg_temp_free(t0);
2512 } else {
2513 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2514 }
2515 }
2516
2517 static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2518 {
2519 if (unlikely(ctx->le_mode)) {
2520 TCGv t0 = tcg_temp_new();
2521 tcg_gen_ext32u_tl(t0, arg1);
2522 tcg_gen_bswap32_tl(t0, t0);
2523 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2524 tcg_temp_free(t0);
2525 } else {
2526 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2527 }
2528 }
2529
2530 static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2531 {
2532 if (unlikely(ctx->le_mode)) {
2533 TCGv_i64 t0 = tcg_temp_new_i64();
2534 tcg_gen_bswap64_i64(t0, arg1);
2535 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2536 tcg_temp_free_i64(t0);
2537 } else
2538 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2539 }
2540
2541 #define GEN_LD(name, ldop, opc, type) \
2542 static void glue(gen_, name)(DisasContext *ctx) \
2543 { \
2544 TCGv EA; \
2545 gen_set_access_type(ctx, ACCESS_INT); \
2546 EA = tcg_temp_new(); \
2547 gen_addr_imm_index(ctx, EA, 0); \
2548 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2549 tcg_temp_free(EA); \
2550 }
2551
2552 #define GEN_LDU(name, ldop, opc, type) \
2553 static void glue(gen_, name##u)(DisasContext *ctx) \
2554 { \
2555 TCGv EA; \
2556 if (unlikely(rA(ctx->opcode) == 0 || \
2557 rA(ctx->opcode) == rD(ctx->opcode))) { \
2558 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2559 return; \
2560 } \
2561 gen_set_access_type(ctx, ACCESS_INT); \
2562 EA = tcg_temp_new(); \
2563 if (type == PPC_64B) \
2564 gen_addr_imm_index(ctx, EA, 0x03); \
2565 else \
2566 gen_addr_imm_index(ctx, EA, 0); \
2567 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2568 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2569 tcg_temp_free(EA); \
2570 }
2571
2572 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2573 static void glue(gen_, name##ux)(DisasContext *ctx) \
2574 { \
2575 TCGv EA; \
2576 if (unlikely(rA(ctx->opcode) == 0 || \
2577 rA(ctx->opcode) == rD(ctx->opcode))) { \
2578 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2579 return; \
2580 } \
2581 gen_set_access_type(ctx, ACCESS_INT); \
2582 EA = tcg_temp_new(); \
2583 gen_addr_reg_index(ctx, EA); \
2584 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2585 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2586 tcg_temp_free(EA); \
2587 }
2588
2589 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2590 static void glue(gen_, name##x)(DisasContext *ctx) \
2591 { \
2592 TCGv EA; \
2593 gen_set_access_type(ctx, ACCESS_INT); \
2594 EA = tcg_temp_new(); \
2595 gen_addr_reg_index(ctx, EA); \
2596 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2597 tcg_temp_free(EA); \
2598 }
2599
2600 #define GEN_LDS(name, ldop, op, type) \
2601 GEN_LD(name, ldop, op | 0x20, type); \
2602 GEN_LDU(name, ldop, op | 0x21, type); \
2603 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2604 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2605
2606 /* lbz lbzu lbzux lbzx */
2607 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2608 /* lha lhau lhaux lhax */
2609 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2610 /* lhz lhzu lhzux lhzx */
2611 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2612 /* lwz lwzu lwzux lwzx */
2613 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2614 #if defined(TARGET_PPC64)
2615 /* lwaux */
2616 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2617 /* lwax */
2618 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2619 /* ldux */
2620 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2621 /* ldx */
2622 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2623
2624 static void gen_ld(DisasContext *ctx)
2625 {
2626 TCGv EA;
2627 if (Rc(ctx->opcode)) {
2628 if (unlikely(rA(ctx->opcode) == 0 ||
2629 rA(ctx->opcode) == rD(ctx->opcode))) {
2630 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2631 return;
2632 }
2633 }
2634 gen_set_access_type(ctx, ACCESS_INT);
2635 EA = tcg_temp_new();
2636 gen_addr_imm_index(ctx, EA, 0x03);
2637 if (ctx->opcode & 0x02) {
2638 /* lwa (lwau is undefined) */
2639 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2640 } else {
2641 /* ld - ldu */
2642 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2643 }
2644 if (Rc(ctx->opcode))
2645 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2646 tcg_temp_free(EA);
2647 }
2648
2649 /* lq */
2650 static void gen_lq(DisasContext *ctx)
2651 {
2652 #if defined(CONFIG_USER_ONLY)
2653 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2654 #else
2655 int ra, rd;
2656 TCGv EA;
2657
2658 /* Restore CPU state */
2659 if (unlikely(ctx->mem_idx == 0)) {
2660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2661 return;
2662 }
2663 ra = rA(ctx->opcode);
2664 rd = rD(ctx->opcode);
2665 if (unlikely((rd & 1) || rd == ra)) {
2666 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2667 return;
2668 }
2669 if (unlikely(ctx->le_mode)) {
2670 /* Little-endian mode is not handled */
2671 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2672 return;
2673 }
2674 gen_set_access_type(ctx, ACCESS_INT);
2675 EA = tcg_temp_new();
2676 gen_addr_imm_index(ctx, EA, 0x0F);
2677 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2678 gen_addr_add(ctx, EA, EA, 8);
2679 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2680 tcg_temp_free(EA);
2681 #endif
2682 }
2683 #endif
2684
2685 /*** Integer store ***/
2686 #define GEN_ST(name, stop, opc, type) \
2687 static void glue(gen_, name)(DisasContext *ctx) \
2688 { \
2689 TCGv EA; \
2690 gen_set_access_type(ctx, ACCESS_INT); \
2691 EA = tcg_temp_new(); \
2692 gen_addr_imm_index(ctx, EA, 0); \
2693 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2694 tcg_temp_free(EA); \
2695 }
2696
2697 #define GEN_STU(name, stop, opc, type) \
2698 static void glue(gen_, stop##u)(DisasContext *ctx) \
2699 { \
2700 TCGv EA; \
2701 if (unlikely(rA(ctx->opcode) == 0)) { \
2702 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2703 return; \
2704 } \
2705 gen_set_access_type(ctx, ACCESS_INT); \
2706 EA = tcg_temp_new(); \
2707 if (type == PPC_64B) \
2708 gen_addr_imm_index(ctx, EA, 0x03); \
2709 else \
2710 gen_addr_imm_index(ctx, EA, 0); \
2711 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2712 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2713 tcg_temp_free(EA); \
2714 }
2715
2716 #define GEN_STUX(name, stop, opc2, opc3, type) \
2717 static void glue(gen_, name##ux)(DisasContext *ctx) \
2718 { \
2719 TCGv EA; \
2720 if (unlikely(rA(ctx->opcode) == 0)) { \
2721 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2722 return; \
2723 } \
2724 gen_set_access_type(ctx, ACCESS_INT); \
2725 EA = tcg_temp_new(); \
2726 gen_addr_reg_index(ctx, EA); \
2727 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2728 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2729 tcg_temp_free(EA); \
2730 }
2731
2732 #define GEN_STX(name, stop, opc2, opc3, type) \
2733 static void glue(gen_, name##x)(DisasContext *ctx) \
2734 { \
2735 TCGv EA; \
2736 gen_set_access_type(ctx, ACCESS_INT); \
2737 EA = tcg_temp_new(); \
2738 gen_addr_reg_index(ctx, EA); \
2739 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2740 tcg_temp_free(EA); \
2741 }
2742
2743 #define GEN_STS(name, stop, op, type) \
2744 GEN_ST(name, stop, op | 0x20, type); \
2745 GEN_STU(name, stop, op | 0x21, type); \
2746 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2747 GEN_STX(name, stop, 0x17, op | 0x00, type)
2748
2749 /* stb stbu stbux stbx */
2750 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2751 /* sth sthu sthux sthx */
2752 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2753 /* stw stwu stwux stwx */
2754 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2755 #if defined(TARGET_PPC64)
2756 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2757 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2758
2759 static void gen_std(DisasContext *ctx)
2760 {
2761 int rs;
2762 TCGv EA;
2763
2764 rs = rS(ctx->opcode);
2765 if ((ctx->opcode & 0x3) == 0x2) {
2766 #if defined(CONFIG_USER_ONLY)
2767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2768 #else
2769 /* stq */
2770 if (unlikely(ctx->mem_idx == 0)) {
2771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2772 return;
2773 }
2774 if (unlikely(rs & 1)) {
2775 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2776 return;
2777 }
2778 if (unlikely(ctx->le_mode)) {
2779 /* Little-endian mode is not handled */
2780 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2781 return;
2782 }
2783 gen_set_access_type(ctx, ACCESS_INT);
2784 EA = tcg_temp_new();
2785 gen_addr_imm_index(ctx, EA, 0x03);
2786 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2787 gen_addr_add(ctx, EA, EA, 8);
2788 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2789 tcg_temp_free(EA);
2790 #endif
2791 } else {
2792 /* std / stdu */
2793 if (Rc(ctx->opcode)) {
2794 if (unlikely(rA(ctx->opcode) == 0)) {
2795 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2796 return;
2797 }
2798 }
2799 gen_set_access_type(ctx, ACCESS_INT);
2800 EA = tcg_temp_new();
2801 gen_addr_imm_index(ctx, EA, 0x03);
2802 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2803 if (Rc(ctx->opcode))
2804 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2805 tcg_temp_free(EA);
2806 }
2807 }
2808 #endif
2809 /*** Integer load and store with byte reverse ***/
2810 /* lhbrx */
2811 static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2812 {
2813 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2814 if (likely(!ctx->le_mode)) {
2815 tcg_gen_bswap16_tl(arg1, arg1);
2816 }
2817 }
2818 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2819
2820 /* lwbrx */
2821 static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2822 {
2823 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2824 if (likely(!ctx->le_mode)) {
2825 tcg_gen_bswap32_tl(arg1, arg1);
2826 }
2827 }
2828 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2829
2830 /* sthbrx */
2831 static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2832 {
2833 if (likely(!ctx->le_mode)) {
2834 TCGv t0 = tcg_temp_new();
2835 tcg_gen_ext16u_tl(t0, arg1);
2836 tcg_gen_bswap16_tl(t0, t0);
2837 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2838 tcg_temp_free(t0);
2839 } else {
2840 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2841 }
2842 }
2843 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2844
2845 /* stwbrx */
2846 static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2847 {
2848 if (likely(!ctx->le_mode)) {
2849 TCGv t0 = tcg_temp_new();
2850 tcg_gen_ext32u_tl(t0, arg1);
2851 tcg_gen_bswap32_tl(t0, t0);
2852 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2853 tcg_temp_free(t0);
2854 } else {
2855 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2856 }
2857 }
2858 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2859
2860 /*** Integer load and store multiple ***/
2861
2862 /* lmw */
2863 static void gen_lmw(DisasContext *ctx)
2864 {
2865 TCGv t0;
2866 TCGv_i32 t1;
2867 gen_set_access_type(ctx, ACCESS_INT);
2868 /* NIP cannot be restored if the memory exception comes from an helper */
2869 gen_update_nip(ctx, ctx->nip - 4);
2870 t0 = tcg_temp_new();
2871 t1 = tcg_const_i32(rD(ctx->opcode));
2872 gen_addr_imm_index(ctx, t0, 0);
2873 gen_helper_lmw(t0, t1);
2874 tcg_temp_free(t0);
2875 tcg_temp_free_i32(t1);
2876 }
2877
2878 /* stmw */
2879 static void gen_stmw(DisasContext *ctx)
2880 {
2881 TCGv t0;
2882 TCGv_i32 t1;
2883 gen_set_access_type(ctx, ACCESS_INT);
2884 /* NIP cannot be restored if the memory exception comes from an helper */
2885 gen_update_nip(ctx, ctx->nip - 4);
2886 t0 = tcg_temp_new();
2887 t1 = tcg_const_i32(rS(ctx->opcode));
2888 gen_addr_imm_index(ctx, t0, 0);
2889 gen_helper_stmw(t0, t1);
2890 tcg_temp_free(t0);
2891 tcg_temp_free_i32(t1);
2892 }
2893
2894 /*** Integer load and store strings ***/
2895
2896 /* lswi */
2897 /* PowerPC32 specification says we must generate an exception if
2898 * rA is in the range of registers to be loaded.
2899 * In an other hand, IBM says this is valid, but rA won't be loaded.
2900 * For now, I'll follow the spec...
2901 */
2902 static void gen_lswi(DisasContext *ctx)
2903 {
2904 TCGv t0;
2905 TCGv_i32 t1, t2;
2906 int nb = NB(ctx->opcode);
2907 int start = rD(ctx->opcode);
2908 int ra = rA(ctx->opcode);
2909 int nr;
2910
2911 if (nb == 0)
2912 nb = 32;
2913 nr = nb / 4;
2914 if (unlikely(((start + nr) > 32 &&
2915 start <= ra && (start + nr - 32) > ra) ||
2916 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2917 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2918 return;
2919 }
2920 gen_set_access_type(ctx, ACCESS_INT);
2921 /* NIP cannot be restored if the memory exception comes from an helper */
2922 gen_update_nip(ctx, ctx->nip - 4);
2923 t0 = tcg_temp_new();
2924 gen_addr_register(ctx, t0);
2925 t1 = tcg_const_i32(nb);
2926 t2 = tcg_const_i32(start);
2927 gen_helper_lsw(t0, t1, t2);
2928 tcg_temp_free(t0);
2929 tcg_temp_free_i32(t1);
2930 tcg_temp_free_i32(t2);
2931 }
2932
2933 /* lswx */
2934 static void gen_lswx(DisasContext *ctx)
2935 {
2936 TCGv t0;
2937 TCGv_i32 t1, t2, t3;
2938 gen_set_access_type(ctx, ACCESS_INT);
2939 /* NIP cannot be restored if the memory exception comes from an helper */
2940 gen_update_nip(ctx, ctx->nip - 4);
2941 t0 = tcg_temp_new();
2942 gen_addr_reg_index(ctx, t0);
2943 t1 = tcg_const_i32(rD(ctx->opcode));
2944 t2 = tcg_const_i32(rA(ctx->opcode));
2945 t3 = tcg_const_i32(rB(ctx->opcode));
2946 gen_helper_lswx(t0, t1, t2, t3);
2947 tcg_temp_free(t0);
2948 tcg_temp_free_i32(t1);
2949 tcg_temp_free_i32(t2);
2950 tcg_temp_free_i32(t3);
2951 }
2952
2953 /* stswi */
2954 static void gen_stswi(DisasContext *ctx)
2955 {
2956 TCGv t0;
2957 TCGv_i32 t1, t2;
2958 int nb = NB(ctx->opcode);
2959 gen_set_access_type(ctx, ACCESS_INT);
2960 /* NIP cannot be restored if the memory exception comes from an helper */
2961 gen_update_nip(ctx, ctx->nip - 4);
2962 t0 = tcg_temp_new();
2963 gen_addr_register(ctx, t0);
2964 if (nb == 0)
2965 nb = 32;
2966 t1 = tcg_const_i32(nb);
2967 t2 = tcg_const_i32(rS(ctx->opcode));
2968 gen_helper_stsw(t0, t1, t2);
2969 tcg_temp_free(t0);
2970 tcg_temp_free_i32(t1);
2971 tcg_temp_free_i32(t2);
2972 }
2973
2974 /* stswx */
2975 static void gen_stswx(DisasContext *ctx)
2976 {
2977 TCGv t0;
2978 TCGv_i32 t1, t2;
2979 gen_set_access_type(ctx, ACCESS_INT);
2980 /* NIP cannot be restored if the memory exception comes from an helper */
2981 gen_update_nip(ctx, ctx->nip - 4);
2982 t0 = tcg_temp_new();
2983 gen_addr_reg_index(ctx, t0);
2984 t1 = tcg_temp_new_i32();
2985 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2986 tcg_gen_andi_i32(t1, t1, 0x7F);
2987 t2 = tcg_const_i32(rS(ctx->opcode));
2988 gen_helper_stsw(t0, t1, t2);
2989 tcg_temp_free(t0);
2990 tcg_temp_free_i32(t1);
2991 tcg_temp_free_i32(t2);
2992 }
2993
2994 /*** Memory synchronisation ***/
2995 /* eieio */
2996 static void gen_eieio(DisasContext *ctx)
2997 {
2998 }
2999
3000 /* isync */
3001 static void gen_isync(DisasContext *ctx)
3002 {
3003 gen_stop_exception(ctx);
3004 }
3005
3006 /* lwarx */
3007 static void gen_lwarx(DisasContext *ctx)
3008 {
3009 TCGv t0;
3010 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3011 gen_set_access_type(ctx, ACCESS_RES);
3012 t0 = tcg_temp_local_new();
3013 gen_addr_reg_index(ctx, t0);
3014 gen_check_align(ctx, t0, 0x03);
3015 gen_qemu_ld32u(ctx, gpr, t0);
3016 tcg_gen_mov_tl(cpu_reserve, t0);
3017 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
3018 tcg_temp_free(t0);
3019 }
3020
3021 #if defined(CONFIG_USER_ONLY)
3022 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3023 int reg, int size)
3024 {
3025 TCGv t0 = tcg_temp_new();
3026 uint32_t save_exception = ctx->exception;
3027
3028 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea));
3029 tcg_gen_movi_tl(t0, (size << 5) | reg);
3030 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info));
3031 tcg_temp_free(t0);
3032 gen_update_nip(ctx, ctx->nip-4);
3033 ctx->exception = POWERPC_EXCP_BRANCH;
3034 gen_exception(ctx, POWERPC_EXCP_STCX);
3035 ctx->exception = save_exception;
3036 }
3037 #endif
3038
3039 /* stwcx. */
3040 static void gen_stwcx_(DisasContext *ctx)
3041 {
3042 TCGv t0;
3043 gen_set_access_type(ctx, ACCESS_RES);
3044 t0 = tcg_temp_local_new();
3045 gen_addr_reg_index(ctx, t0);
3046 gen_check_align(ctx, t0, 0x03);
3047 #if defined(CONFIG_USER_ONLY)
3048 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3049 #else
3050 {
3051 int l1;
3052
3053 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3054 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3055 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3056 l1 = gen_new_label();
3057 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3058 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3059 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3060 gen_set_label(l1);
3061 tcg_gen_movi_tl(cpu_reserve, -1);
3062 }
3063 #endif
3064 tcg_temp_free(t0);
3065 }
3066
3067 #if defined(TARGET_PPC64)
3068 /* ldarx */
3069 static void gen_ldarx(DisasContext *ctx)
3070 {
3071 TCGv t0;
3072 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3073 gen_set_access_type(ctx, ACCESS_RES);
3074 t0 = tcg_temp_local_new();
3075 gen_addr_reg_index(ctx, t0);
3076 gen_check_align(ctx, t0, 0x07);
3077 gen_qemu_ld64(ctx, gpr, t0);
3078 tcg_gen_mov_tl(cpu_reserve, t0);
3079 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
3080 tcg_temp_free(t0);
3081 }
3082
3083 /* stdcx. */
3084 static void gen_stdcx_(DisasContext *ctx)
3085 {
3086 TCGv t0;
3087 gen_set_access_type(ctx, ACCESS_RES);
3088 t0 = tcg_temp_local_new();
3089 gen_addr_reg_index(ctx, t0);
3090 gen_check_align(ctx, t0, 0x07);
3091 #if defined(CONFIG_USER_ONLY)
3092 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3093 #else
3094 {
3095 int l1;
3096 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3097 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3098 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3099 l1 = gen_new_label();
3100 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3101 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3102 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3103 gen_set_label(l1);
3104 tcg_gen_movi_tl(cpu_reserve, -1);
3105 }
3106 #endif
3107 tcg_temp_free(t0);
3108 }
3109 #endif /* defined(TARGET_PPC64) */
3110
3111 /* sync */
3112 static void gen_sync(DisasContext *ctx)
3113 {
3114 }
3115
3116 /* wait */
3117 static void gen_wait(DisasContext *ctx)
3118 {
3119 TCGv_i32 t0 = tcg_temp_new_i32();
3120 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3121 tcg_temp_free_i32(t0);
3122 /* Stop translation, as the CPU is supposed to sleep from now */
3123 gen_exception_err(ctx, EXCP_HLT, 1);
3124 }
3125
3126 /*** Floating-point load ***/
3127 #define GEN_LDF(name, ldop, opc, type) \
3128 static void glue(gen_, name)(DisasContext *ctx) \
3129 { \
3130 TCGv EA; \
3131 if (unlikely(!ctx->fpu_enabled)) { \
3132 gen_exception(ctx, POWERPC_EXCP_FPU); \
3133 return; \
3134 } \
3135 gen_set_access_type(ctx, ACCESS_FLOAT); \
3136 EA = tcg_temp_new(); \
3137 gen_addr_imm_index(ctx, EA, 0); \
3138 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3139 tcg_temp_free(EA); \
3140 }
3141
3142 #define GEN_LDUF(name, ldop, opc, type) \
3143 static void glue(gen_, name##u)(DisasContext *ctx) \
3144 { \
3145 TCGv EA; \
3146 if (unlikely(!ctx->fpu_enabled)) { \
3147 gen_exception(ctx, POWERPC_EXCP_FPU); \
3148 return; \
3149 } \
3150 if (unlikely(rA(ctx->opcode) == 0)) { \
3151 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3152 return; \
3153 } \
3154 gen_set_access_type(ctx, ACCESS_FLOAT); \
3155 EA = tcg_temp_new(); \
3156 gen_addr_imm_index(ctx, EA, 0); \
3157 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3158 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3159 tcg_temp_free(EA); \
3160 }
3161
3162 #define GEN_LDUXF(name, ldop, opc, type) \
3163 static void glue(gen_, name##ux)(DisasContext *ctx) \
3164 { \
3165 TCGv EA; \
3166 if (unlikely(!ctx->fpu_enabled)) { \
3167 gen_exception(ctx, POWERPC_EXCP_FPU); \
3168 return; \
3169 } \
3170 if (unlikely(rA(ctx->opcode) == 0)) { \
3171 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3172 return; \
3173 } \
3174 gen_set_access_type(ctx, ACCESS_FLOAT); \
3175 EA = tcg_temp_new(); \
3176 gen_addr_reg_index(ctx, EA); \
3177 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3178 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3179 tcg_temp_free(EA); \
3180 }
3181
3182 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3183 static void glue(gen_, name##x)(DisasContext *ctx) \
3184 { \
3185 TCGv EA; \
3186 if (unlikely(!ctx->fpu_enabled)) { \
3187 gen_exception(ctx, POWERPC_EXCP_FPU); \
3188 return; \
3189 } \
3190 gen_set_access_type(ctx, ACCESS_FLOAT); \
3191 EA = tcg_temp_new(); \
3192 gen_addr_reg_index(ctx, EA); \
3193 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3194 tcg_temp_free(EA); \
3195 }
3196
3197 #define GEN_LDFS(name, ldop, op, type) \
3198 GEN_LDF(name, ldop, op | 0x20, type); \
3199 GEN_LDUF(name, ldop, op | 0x21, type); \
3200 GEN_LDUXF(name, ldop, op | 0x01, type); \
3201 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3202
3203 static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3204 {
3205 TCGv t0 = tcg_temp_new();
3206 TCGv_i32 t1 = tcg_temp_new_i32();
3207 gen_qemu_ld32u(ctx, t0, arg2);
3208 tcg_gen_trunc_tl_i32(t1, t0);
3209 tcg_temp_free(t0);
3210 gen_helper_float32_to_float64(arg1, t1);
3211 tcg_temp_free_i32(t1);
3212 }
3213
3214 /* lfd lfdu lfdux lfdx */
3215 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3216 /* lfs lfsu lfsux lfsx */
3217 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3218
3219 /*** Floating-point store ***/
3220 #define GEN_STF(name, stop, opc, type) \
3221 static void glue(gen_, name)(DisasContext *ctx) \
3222 { \
3223 TCGv EA; \
3224 if (unlikely(!ctx->fpu_enabled)) { \
3225 gen_exception(ctx, POWERPC_EXCP_FPU); \
3226 return; \
3227 } \
3228 gen_set_access_type(ctx, ACCESS_FLOAT); \
3229 EA = tcg_temp_new(); \
3230 gen_addr_imm_index(ctx, EA, 0); \
3231 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3232 tcg_temp_free(EA); \
3233 }
3234
3235 #define GEN_STUF(name, stop, opc, type) \
3236 static void glue(gen_, name##u)(DisasContext *ctx) \
3237 { \
3238 TCGv EA; \
3239 if (unlikely(!ctx->fpu_enabled)) { \
3240 gen_exception(ctx, POWERPC_EXCP_FPU); \
3241 return; \
3242 } \
3243 if (unlikely(rA(ctx->opcode) == 0)) { \
3244 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3245 return; \
3246 } \
3247 gen_set_access_type(ctx, ACCESS_FLOAT); \
3248 EA = tcg_temp_new(); \
3249 gen_addr_imm_index(ctx, EA, 0); \
3250 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3251 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3252 tcg_temp_free(EA); \
3253 }
3254
3255 #define GEN_STUXF(name, stop, opc, type) \
3256 static void glue(gen_, name##ux)(DisasContext *ctx) \
3257 { \
3258 TCGv EA; \
3259 if (unlikely(!ctx->fpu_enabled)) { \
3260 gen_exception(ctx, POWERPC_EXCP_FPU); \
3261 return; \
3262 } \
3263 if (unlikely(rA(ctx->opcode) == 0)) { \
3264 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3265 return; \
3266 } \
3267 gen_set_access_type(ctx, ACCESS_FLOAT); \
3268 EA = tcg_temp_new(); \
3269 gen_addr_reg_index(ctx, EA); \
3270 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3271 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3272 tcg_temp_free(EA); \
3273 }
3274
3275 #define GEN_STXF(name, stop, opc2, opc3, type) \
3276 static void glue(gen_, name##x)(DisasContext *ctx) \
3277 { \
3278 TCGv EA; \
3279 if (unlikely(!ctx->fpu_enabled)) { \
3280 gen_exception(ctx, POWERPC_EXCP_FPU); \
3281 return; \
3282 } \
3283 gen_set_access_type(ctx, ACCESS_FLOAT); \
3284 EA = tcg_temp_new(); \
3285 gen_addr_reg_index(ctx, EA); \
3286 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3287 tcg_temp_free(EA); \
3288 }
3289
3290 #define GEN_STFS(name, stop, op, type) \
3291 GEN_STF(name, stop, op | 0x20, type); \
3292 GEN_STUF(name, stop, op | 0x21, type); \
3293 GEN_STUXF(name, stop, op | 0x01, type); \
3294 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3295
3296 static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3297 {
3298 TCGv_i32 t0 = tcg_temp_new_i32();
3299 TCGv t1 = tcg_temp_new();
3300 gen_helper_float64_to_float32(t0, arg1);
3301 tcg_gen_extu_i32_tl(t1, t0);
3302 tcg_temp_free_i32(t0);
3303 gen_qemu_st32(ctx, t1, arg2);
3304 tcg_temp_free(t1);
3305 }
3306
3307 /* stfd stfdu stfdux stfdx */
3308 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3309 /* stfs stfsu stfsux stfsx */
3310 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3311
3312 /* Optional: */
3313 static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3314 {
3315 TCGv t0 = tcg_temp_new();
3316 tcg_gen_trunc_i64_tl(t0, arg1),
3317 gen_qemu_st32(ctx, t0, arg2);
3318 tcg_temp_free(t0);
3319 }
3320 /* stfiwx */
3321 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3322
3323 /*** Branch ***/
3324 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3325 target_ulong dest)
3326 {
3327 TranslationBlock *tb;
3328 tb = ctx->tb;
3329 #if defined(TARGET_PPC64)
3330 if (!ctx->sf_mode)
3331 dest = (uint32_t) dest;
3332 #endif
3333 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3334 likely(!ctx->singlestep_enabled)) {
3335 tcg_gen_goto_tb(n);
3336 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3337 tcg_gen_exit_tb((long)tb + n);
3338 } else {
3339 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3340 if (unlikely(ctx->singlestep_enabled)) {
3341 if ((ctx->singlestep_enabled &
3342 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3343 ctx->exception == POWERPC_EXCP_BRANCH) {
3344 target_ulong tmp = ctx->nip;
3345 ctx->nip = dest;
3346 gen_exception(ctx, POWERPC_EXCP_TRACE);
3347 ctx->nip = tmp;
3348 }
3349 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3350 gen_debug_exception(ctx);
3351 }
3352 }
3353 tcg_gen_exit_tb(0);
3354 }
3355 }
3356
3357 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3358 {
3359 #if defined(TARGET_PPC64)
3360 if (ctx->sf_mode == 0)
3361 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3362 else
3363 #endif
3364 tcg_gen_movi_tl(cpu_lr, nip);
3365 }
3366
3367 /* b ba bl bla */
3368 static void gen_b(DisasContext *ctx)
3369 {
3370 target_ulong li, target;
3371
3372 ctx->exception = POWERPC_EXCP_BRANCH;
3373 /* sign extend LI */
3374 #if defined(TARGET_PPC64)
3375 if (ctx->sf_mode)
3376 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3377 else
3378 #endif
3379 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3380 if (likely(AA(ctx->opcode) == 0))
3381 target = ctx->nip + li - 4;
3382 else
3383 target = li;
3384 if (LK(ctx->opcode))
3385 gen_setlr(ctx, ctx->nip);
3386 gen_goto_tb(ctx, 0, target);
3387 }
3388
3389 #define BCOND_IM 0
3390 #define BCOND_LR 1
3391 #define BCOND_CTR 2
3392
3393 static always_inline void gen_bcond (DisasContext *ctx, int type)
3394 {
3395 uint32_t bo = BO(ctx->opcode);
3396 int l1 = gen_new_label();
3397 TCGv target;
3398
3399 ctx->exception = POWERPC_EXCP_BRANCH;
3400 if (type == BCOND_LR || type == BCOND_CTR) {
3401 target = tcg_temp_local_new();
3402 if (type == BCOND_CTR)
3403 tcg_gen_mov_tl(target, cpu_ctr);
3404 else
3405 tcg_gen_mov_tl(target, cpu_lr);
3406 } else {
3407 TCGV_UNUSED(target);
3408 }
3409 if (LK(ctx->opcode))
3410 gen_setlr(ctx, ctx->nip);
3411 l1 = gen_new_label();
3412 if ((bo & 0x4) == 0) {
3413 /* Decrement and test CTR */
3414 TCGv temp = tcg_temp_new();
3415 if (unlikely(type == BCOND_CTR)) {
3416 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3417 return;
3418 }
3419 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3420 #if defined(TARGET_PPC64)
3421 if (!ctx->sf_mode)
3422 tcg_gen_ext32u_tl(temp, cpu_ctr);
3423 else
3424 #endif
3425 tcg_gen_mov_tl(temp, cpu_ctr);
3426 if (bo & 0x2) {
3427 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3428 } else {
3429 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3430 }
3431 tcg_temp_free(temp);
3432 }
3433 if ((bo & 0x10) == 0) {
3434 /* Test CR */
3435 uint32_t bi = BI(ctx->opcode);
3436 uint32_t mask = 1 << (3 - (bi & 0x03));
3437 TCGv_i32 temp = tcg_temp_new_i32();
3438
3439 if (bo & 0x8) {
3440 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3441 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3442 } else {
3443 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3444 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3445 }
3446 tcg_temp_free_i32(temp);
3447 }
3448 if (type == BCOND_IM) {
3449 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3450 if (likely(AA(ctx->opcode) == 0)) {
3451 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3452 } else {
3453 gen_goto_tb(ctx, 0, li);
3454 }
3455 gen_set_label(l1);
3456 gen_goto_tb(ctx, 1, ctx->nip);
3457 } else {
3458 #if defined(TARGET_PPC64)
3459 if (!(ctx->sf_mode))
3460 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3461 else
3462 #endif
3463 tcg_gen_andi_tl(cpu_nip, target, ~3);
3464 tcg_gen_exit_tb(0);
3465 gen_set_label(l1);
3466 #if defined(TARGET_PPC64)
3467 if (!(ctx->sf_mode))
3468 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3469 else
3470 #endif
3471 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3472 tcg_gen_exit_tb(0);
3473 }
3474 }
3475
3476 static void gen_bc(DisasContext *ctx)
3477 {
3478 gen_bcond(ctx, BCOND_IM);
3479 }
3480
3481 static void gen_bcctr(DisasContext *ctx)
3482 {
3483 gen_bcond(ctx, BCOND_CTR);
3484 }
3485
3486 static void gen_bclr(DisasContext *ctx)
3487 {
3488 gen_bcond(ctx, BCOND_LR);
3489 }
3490
3491 /*** Condition register logical ***/
3492 #define GEN_CRLOGIC(name, tcg_op, opc) \
3493 static void glue(gen_, name)(DisasContext *ctx) \
3494 { \
3495 uint8_t bitmask; \
3496 int sh; \
3497 TCGv_i32 t0, t1; \
3498 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3499 t0 = tcg_temp_new_i32(); \
3500 if (sh > 0) \
3501 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3502 else if (sh < 0) \
3503 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3504 else \
3505 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3506 t1 = tcg_temp_new_i32(); \
3507 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3508 if (sh > 0) \
3509 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3510 else if (sh < 0) \
3511 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3512 else \
3513 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3514 tcg_op(t0, t0, t1); \
3515 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3516 tcg_gen_andi_i32(t0, t0, bitmask); \
3517 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3518 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3519 tcg_temp_free_i32(t0); \
3520 tcg_temp_free_i32(t1); \
3521 }
3522
3523 /* crand */
3524 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3525 /* crandc */
3526 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3527 /* creqv */
3528 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3529 /* crnand */
3530 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3531 /* crnor */
3532 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3533 /* cror */
3534 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3535 /* crorc */
3536 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3537 /* crxor */
3538 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3539
3540 /* mcrf */
3541 static void gen_mcrf(DisasContext *ctx)
3542 {
3543 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3544 }
3545
3546 /*** System linkage ***/
3547
3548 /* rfi (mem_idx only) */
3549 static void gen_rfi(DisasContext *ctx)
3550 {
3551 #if defined(CONFIG_USER_ONLY)
3552 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3553 #else
3554 /* Restore CPU state */
3555 if (unlikely(!ctx->mem_idx)) {
3556 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3557 return;
3558 }
3559 gen_helper_rfi();
3560 gen_sync_exception(ctx);
3561 #endif
3562 }
3563
3564 #if defined(TARGET_PPC64)
3565 static void gen_rfid(DisasContext *ctx)
3566 {
3567 #if defined(CONFIG_USER_ONLY)
3568 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3569 #else
3570 /* Restore CPU state */
3571 if (unlikely(!ctx->mem_idx)) {
3572 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3573 return;
3574 }
3575 gen_helper_rfid();
3576 gen_sync_exception(ctx);
3577 #endif
3578 }
3579
3580 static void gen_hrfid(DisasContext *ctx)
3581 {
3582 #if defined(CONFIG_USER_ONLY)
3583 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3584 #else
3585 /* Restore CPU state */
3586 if (unlikely(ctx->mem_idx <= 1)) {
3587 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3588 return;
3589 }
3590 gen_helper_hrfid();
3591 gen_sync_exception(ctx);
3592 #endif
3593 }
3594 #endif
3595
3596 /* sc */
3597 #if defined(CONFIG_USER_ONLY)
3598 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3599 #else
3600 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3601 #endif
3602 static void gen_sc(DisasContext *ctx)
3603 {
3604 uint32_t lev;
3605
3606 lev = (ctx->opcode >> 5) & 0x7F;
3607 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3608 }
3609
3610 /*** Trap ***/
3611
3612 /* tw */
3613 static void gen_tw(DisasContext *ctx)
3614 {
3615 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3616 /* Update the nip since this might generate a trap exception */
3617 gen_update_nip(ctx, ctx->nip);
3618 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3619 tcg_temp_free_i32(t0);
3620 }
3621
3622 /* twi */
3623 static void gen_twi(DisasContext *ctx)
3624 {
3625 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3626 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3627 /* Update the nip since this might generate a trap exception */
3628 gen_update_nip(ctx, ctx->nip);
3629 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3630 tcg_temp_free(t0);
3631 tcg_temp_free_i32(t1);
3632 }
3633
3634 #if defined(TARGET_PPC64)
3635 /* td */
3636 static void gen_td(DisasContext *ctx)
3637 {
3638 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3639 /* Update the nip since this might generate a trap exception */
3640 gen_update_nip(ctx, ctx->nip);
3641 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3642 tcg_temp_free_i32(t0);
3643 }
3644
3645 /* tdi */
3646 static void gen_tdi(DisasContext *ctx)
3647 {
3648 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3649 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3650 /* Update the nip since this might generate a trap exception */
3651 gen_update_nip(ctx, ctx->nip);
3652 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3653 tcg_temp_free(t0);
3654 tcg_temp_free_i32(t1);
3655 }
3656 #endif
3657
3658 /*** Processor control ***/
3659
3660 /* mcrxr */
3661 static void gen_mcrxr(DisasContext *ctx)
3662 {
3663 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3664 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3665 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3666 }
3667
3668 /* mfcr mfocrf */
3669 static void gen_mfcr(DisasContext *ctx)
3670 {
3671 uint32_t crm, crn;
3672
3673 if (likely(ctx->opcode & 0x00100000)) {
3674 crm = CRM(ctx->opcode);
3675 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3676 crn = ctz32 (crm);
3677 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3678 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3679 cpu_gpr[rD(ctx->opcode)], crn * 4);
3680 }
3681 } else {
3682 TCGv_i32 t0 = tcg_temp_new_i32();
3683 tcg_gen_mov_i32(t0, cpu_crf[0]);
3684 tcg_gen_shli_i32(t0, t0, 4);
3685 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3686 tcg_gen_shli_i32(t0, t0, 4);
3687 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3688 tcg_gen_shli_i32(t0, t0, 4);
3689 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3690 tcg_gen_shli_i32(t0, t0, 4);
3691 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3692 tcg_gen_shli_i32(t0, t0, 4);
3693 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3694 tcg_gen_shli_i32(t0, t0, 4);
3695 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3696 tcg_gen_shli_i32(t0, t0, 4);
3697 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3698 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3699 tcg_temp_free_i32(t0);
3700 }
3701 }
3702
3703 /* mfmsr */
3704 static void gen_mfmsr(DisasContext *ctx)
3705 {
3706 #if defined(CONFIG_USER_ONLY)
3707 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3708 #else
3709 if (unlikely(!ctx->mem_idx)) {
3710 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3711 return;
3712 }
3713 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3714 #endif
3715 }
3716
3717 #if 1
3718 #define SPR_NOACCESS ((void *)(-1UL))
3719 #else
3720 static void spr_noaccess (void *opaque, int sprn)
3721 {
3722 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3723 printf("ERROR: try to access SPR %d !\n", sprn);
3724 }
3725 #define SPR_NOACCESS (&spr_noaccess)
3726 #endif
3727
3728 /* mfspr */
3729 static always_inline void gen_op_mfspr (DisasContext *ctx)
3730 {
3731 void (*read_cb)(void *opaque, int gprn, int sprn);
3732 uint32_t sprn = SPR(ctx->opcode);
3733
3734 #if !defined(CONFIG_USER_ONLY)
3735 if (ctx->mem_idx == 2)
3736 read_cb = ctx->spr_cb[sprn].hea_read;
3737 else if (ctx->mem_idx)
3738 read_cb = ctx->spr_cb[sprn].oea_read;
3739 else
3740 #endif
3741 read_cb = ctx->spr_cb[sprn].uea_read;
3742 if (likely(read_cb != NULL)) {
3743 if (likely(read_cb != SPR_NOACCESS)) {
3744 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3745 } else {
3746 /* Privilege exception */
3747 /* This is a hack to avoid warnings when running Linux:
3748 * this OS breaks the PowerPC virtualisation model,
3749 * allowing userland application to read the PVR
3750 */
3751 if (sprn != SPR_PVR) {
3752 qemu_log("Trying to read privileged spr %d %03x at "
3753 ADDRX "\n", sprn, sprn, ctx->nip);
3754 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3755 sprn, sprn, ctx->nip);
3756 }
3757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3758 }
3759 } else {
3760 /* Not defined */
3761 qemu_log("Trying to read invalid spr %d %03x at "
3762 ADDRX "\n", sprn, sprn, ctx->nip);
3763 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3764 sprn, sprn, ctx->nip);
3765 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3766 }
3767 }
3768
3769 static void gen_mfspr(DisasContext *ctx)
3770 {
3771 gen_op_mfspr(ctx);
3772 }
3773
3774 /* mftb */
3775 static void gen_mftb(DisasContext *ctx)
3776 {
3777 gen_op_mfspr(ctx);
3778 }
3779
3780 /* mtcrf mtocrf*/
3781 static void gen_mtcrf(DisasContext *ctx)
3782 {
3783 uint32_t crm, crn;
3784
3785 crm = CRM(ctx->opcode);
3786 if (likely((ctx->opcode & 0x00100000))) {
3787 if (crm && ((crm & (crm - 1)) == 0)) {
3788 TCGv_i32 temp = tcg_temp_new_i32();
3789 crn = ctz32 (crm);
3790 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3791 tcg_gen_shri_i32(temp, temp, crn * 4);
3792 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3793 tcg_temp_free_i32(temp);
3794 }
3795 } else {
3796 TCGv_i32 temp = tcg_temp_new_i32();
3797 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3798 for (crn = 0 ; crn < 8 ; crn++) {
3799 if (crm & (1 << crn)) {
3800 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3801 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3802 }
3803 }
3804 tcg_temp_free_i32(temp);
3805 }
3806 }
3807
3808 /* mtmsr */
3809 #if defined(TARGET_PPC64)
3810 static void gen_mtmsrd(DisasContext *ctx)
3811 {
3812 #if defined(CONFIG_USER_ONLY)
3813 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3814 #else
3815 if (unlikely(!ctx->mem_idx)) {
3816 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3817 return;
3818 }
3819 if (ctx->opcode & 0x00010000) {
3820 /* Special form that does not need any synchronisation */
3821 TCGv t0 = tcg_temp_new();
3822 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3823 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3824 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3825 tcg_temp_free(t0);
3826 } else {
3827 /* XXX: we need to update nip before the store
3828 * if we enter power saving mode, we will exit the loop
3829 * directly from ppc_store_msr
3830 */
3831 gen_update_nip(ctx, ctx->nip);
3832 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3833 /* Must stop the translation as machine state (may have) changed */
3834 /* Note that mtmsr is not always defined as context-synchronizing */
3835 gen_stop_exception(ctx);
3836 }
3837 #endif
3838 }
3839 #endif
3840
3841 static void gen_mtmsr(DisasContext *ctx)
3842 {
3843 #if defined(CONFIG_USER_ONLY)
3844 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3845 #else
3846 if (unlikely(!ctx->mem_idx)) {
3847 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3848 return;
3849 }
3850 if (ctx->opcode & 0x00010000) {
3851 /* Special form that does not need any synchronisation */
3852 TCGv t0 = tcg_temp_new();
3853 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3854 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3855 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3856 tcg_temp_free(t0);
3857 } else {
3858 /* XXX: we need to update nip before the store
3859 * if we enter power saving mode, we will exit the loop
3860 * directly from ppc_store_msr
3861 */
3862 gen_update_nip(ctx, ctx->nip);
3863 #if defined(TARGET_PPC64)
3864 if (!ctx->sf_mode) {
3865 TCGv t0 = tcg_temp_new();
3866 TCGv t1 = tcg_temp_new();
3867 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
3868 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
3869 tcg_gen_or_tl(t0, t0, t1);
3870 tcg_temp_free(t1);
3871 gen_helper_store_msr(t0);
3872 tcg_temp_free(t0);
3873 } else
3874 #endif
3875 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3876 /* Must stop the translation as machine state (may have) changed */
3877 /* Note that mtmsr is not always defined as context-synchronizing */
3878 gen_stop_exception(ctx);
3879 }
3880 #endif
3881 }
3882
3883 /* mtspr */
3884 static void gen_mtspr(DisasContext *ctx)
3885 {
3886 void (*write_cb)(void *opaque, int sprn, int gprn);
3887 uint32_t sprn = SPR(ctx->opcode);
3888
3889 #if !defined(CONFIG_USER_ONLY)
3890 if (ctx->mem_idx == 2)
3891 write_cb = ctx->spr_cb[sprn].hea_write;
3892 else if (ctx->mem_idx)
3893 write_cb = ctx->spr_cb[sprn].oea_write;
3894 else
3895 #endif
3896 write_cb = ctx->spr_cb[sprn].uea_write;
3897 if (likely(write_cb != NULL)) {
3898 if (likely(write_cb != SPR_NOACCESS)) {
3899 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3900 } else {
3901 /* Privilege exception */
3902 qemu_log("Trying to write privileged spr %d %03x at "
3903 ADDRX "\n", sprn, sprn, ctx->nip);
3904 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3905 sprn, sprn, ctx->nip);
3906 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3907 }
3908 } else {
3909 /* Not defined */
3910 qemu_log("Trying to write invalid spr %d %03x at "
3911 ADDRX "\n", sprn, sprn, ctx->nip);
3912 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3913 sprn, sprn, ctx->nip);
3914 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3915 }
3916 }
3917
3918 /*** Cache management ***/
3919
3920 /* dcbf */
3921 static void gen_dcbf(DisasContext *ctx)
3922 {
3923 /* XXX: specification says this is treated as a load by the MMU */
3924 TCGv t0;
3925 gen_set_access_type(ctx, ACCESS_CACHE);
3926 t0 = tcg_temp_new();
3927 gen_addr_reg_index(ctx, t0);
3928 gen_qemu_ld8u(ctx, t0, t0);
3929 tcg_temp_free(t0);
3930 }
3931
3932 /* dcbi (Supervisor only) */
3933 static void gen_dcbi(DisasContext *ctx)
3934 {
3935 #if defined(CONFIG_USER_ONLY)
3936 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3937 #else
3938 TCGv EA, val;
3939 if (unlikely(!ctx->mem_idx)) {
3940 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3941 return;
3942 }
3943 EA = tcg_temp_new();
3944 gen_set_access_type(ctx, ACCESS_CACHE);
3945 gen_addr_reg_index(ctx, EA);
3946 val = tcg_temp_new();
3947 /* XXX: specification says this should be treated as a store by the MMU */
3948 gen_qemu_ld8u(ctx, val, EA);
3949 gen_qemu_st8(ctx, val, EA);
3950 tcg_temp_free(val);
3951 tcg_temp_free(EA);
3952 #endif
3953 }
3954
3955 /* dcdst */
3956 static void gen_dcbst(DisasContext *ctx)
3957 {
3958 /* XXX: specification say this is treated as a load by the MMU */
3959 TCGv t0;
3960 gen_set_access_type(ctx, ACCESS_CACHE);
3961 t0 = tcg_temp_new();
3962 gen_addr_reg_index(ctx, t0);
3963 gen_qemu_ld8u(ctx, t0, t0);
3964 tcg_temp_free(t0);
3965 }
3966
3967 /* dcbt */
3968 static void gen_dcbt(DisasContext *ctx)
3969 {
3970 /* interpreted as no-op */
3971 /* XXX: specification say this is treated as a load by the MMU
3972 * but does not generate any exception
3973 */
3974 }
3975
3976 /* dcbtst */
3977 static void gen_dcbtst(DisasContext *ctx)
3978 {
3979 /* interpreted as no-op */
3980 /* XXX: specification say this is treated as a load by the MMU
3981 * but does not generate any exception
3982 */
3983 }
3984
3985 /* dcbz */
3986 static void gen_dcbz(DisasContext *ctx)
3987 {
3988 TCGv t0;
3989 gen_set_access_type(ctx, ACCESS_CACHE);
3990 /* NIP cannot be restored if the memory exception comes from an helper */
3991 gen_update_nip(ctx, ctx->nip - 4);
3992 t0 = tcg_temp_new();
3993 gen_addr_reg_index(ctx, t0);
3994 gen_helper_dcbz(t0);
3995 tcg_temp_free(t0);
3996 }
3997
3998 static void gen_dcbz_970(DisasContext *ctx)
3999 {
4000 TCGv t0;
4001 gen_set_access_type(ctx, ACCESS_CACHE);
4002 /* NIP cannot be restored if the memory exception comes from an helper */
4003 gen_update_nip(ctx, ctx->nip - 4);
4004 t0 = tcg_temp_new();
4005 gen_addr_reg_index(ctx, t0);
4006 if (ctx->opcode & 0x00200000)
4007 gen_helper_dcbz(t0);
4008 else
4009 gen_helper_dcbz_970(t0);
4010 tcg_temp_free(t0);
4011 }
4012
4013 /* dst / dstt */
4014 static void gen_dst(DisasContext *ctx)
4015 {
4016 if (rA(ctx->opcode) == 0) {
4017 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4018 } else {
4019 /* interpreted as no-op */
4020 }
4021 }
4022
4023 /* dstst /dststt */
4024 static void gen_dstst(DisasContext *ctx)
4025 {
4026 if (rA(ctx->opcode) == 0) {
4027 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4028 } else {
4029 /* interpreted as no-op */
4030 }
4031
4032 }
4033
4034 /* dss / dssall */
4035 static void gen_dss(DisasContext *ctx)
4036 {
4037 /* interpreted as no-op */
4038 }
4039
4040 /* icbi */
4041 static void gen_icbi(DisasContext *ctx)
4042 {
4043 TCGv t0;
4044 gen_set_access_type(ctx, ACCESS_CACHE);
4045 /* NIP cannot be restored if the memory exception comes from an helper */
4046 gen_update_nip(ctx, ctx->nip - 4);
4047 t0 = tcg_temp_new();
4048 gen_addr_reg_index(ctx, t0);
4049 gen_helper_icbi(t0);
4050 tcg_temp_free(t0);
4051 }
4052
4053 /* Optional: */
4054 /* dcba */
4055 static void gen_dcba(DisasContext *ctx)
4056 {
4057 /* interpreted as no-op */
4058 /* XXX: specification say this is treated as a store by the MMU
4059 * but does not generate any exception
4060 */
4061 }
4062
4063 /*** Segment register manipulation ***/
4064 /* Supervisor only: */
4065
4066 /* mfsr */
4067 static void gen_mfsr(DisasContext *ctx)
4068 {
4069 #if defined(CONFIG_USER_ONLY)
4070 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4071 #else
4072 TCGv t0;
4073 if (unlikely(!ctx->mem_idx)) {
4074 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4075 return;
4076 }
4077 t0 = tcg_const_tl(SR(ctx->opcode));
4078 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4079 tcg_temp_free(t0);
4080 #endif
4081 }
4082
4083 /* mfsrin */
4084 static void gen_mfsrin(DisasContext *ctx)
4085 {
4086 #if defined(CONFIG_USER_ONLY)
4087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4088 #else
4089 TCGv t0;
4090 if (unlikely(!ctx->mem_idx)) {
4091 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4092 return;
4093 }
4094 t0 = tcg_temp_new();
4095 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4096 tcg_gen_andi_tl(t0, t0, 0xF);
4097 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4098 tcg_temp_free(t0);
4099 #endif
4100 }
4101
4102 /* mtsr */
4103 static void gen_mtsr(DisasContext *ctx)
4104 {
4105 #if defined(CONFIG_USER_ONLY)
4106 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4107 #else
4108 TCGv t0;
4109 if (unlikely(!ctx->mem_idx)) {
4110 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4111 return;
4112 }
4113 t0 = tcg_const_tl(SR(ctx->opcode));
4114 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4115 tcg_temp_free(t0);
4116 #endif
4117 }
4118
4119 /* mtsrin */
4120 static void gen_mtsrin(DisasContext *ctx)
4121 {
4122 #if defined(CONFIG_USER_ONLY)
4123 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4124 #else
4125 TCGv t0;
4126 if (unlikely(!ctx->mem_idx)) {
4127 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4128 return;
4129 }
4130 t0 = tcg_temp_new();
4131 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4132 tcg_gen_andi_tl(t0, t0, 0xF);
4133 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4134 tcg_temp_free(t0);
4135 #endif
4136 }
4137
4138 #if defined(TARGET_PPC64)
4139 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4140
4141 /* mfsr */
4142 static void gen_mfsr_64b(DisasContext *ctx)
4143 {
4144 #if defined(CONFIG_USER_ONLY)
4145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4146 #else
4147 TCGv t0;
4148 if (unlikely(!ctx->mem_idx)) {
4149 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4150 return;
4151 }
4152 t0 = tcg_const_tl(SR(ctx->opcode));
4153 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4154 tcg_temp_free(t0);
4155 #endif
4156 }
4157
4158 /* mfsrin */
4159 static void gen_mfsrin_64b(DisasContext *ctx)
4160 {
4161 #if defined(CONFIG_USER_ONLY)
4162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4163 #else
4164 TCGv t0;
4165 if (unlikely(!ctx->mem_idx)) {
4166 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4167 return;
4168 }
4169 t0 = tcg_temp_new();
4170 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4171 tcg_gen_andi_tl(t0, t0, 0xF);
4172 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4173 tcg_temp_free(t0);
4174 #endif
4175 }
4176
4177 /* mtsr */
4178 static void gen_mtsr_64b(DisasContext *ctx)
4179 {
4180 #if defined(CONFIG_USER_ONLY)
4181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4182 #else
4183 TCGv t0;
4184 if (unlikely(!ctx->mem_idx)) {
4185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4186 return;
4187 }
4188 t0 = tcg_const_tl(SR(ctx->opcode));
4189 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4190 tcg_temp_free(t0);
4191 #endif
4192 }
4193
4194 /* mtsrin */
4195 static void gen_mtsrin_64b(DisasContext *ctx)
4196 {
4197 #if defined(CONFIG_USER_ONLY)
4198 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4199 #else
4200 TCGv t0;
4201 if (unlikely(!ctx->mem_idx)) {
4202 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4203 return;
4204 }
4205 t0 = tcg_temp_new();
4206 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4207 tcg_gen_andi_tl(t0, t0, 0xF);
4208 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4209 tcg_temp_free(t0);
4210 #endif
4211 }
4212
4213 /* slbmte */
4214 static void gen_slbmte(DisasContext *ctx)
4215 {
4216 #if defined(CONFIG_USER_ONLY)
4217 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4218 #else
4219 if (unlikely(!ctx->mem_idx)) {
4220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4221 return;
4222 }
4223 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4224 #endif
4225 }
4226
4227 #endif /* defined(TARGET_PPC64) */
4228
4229 /*** Lookaside buffer management ***/
4230 /* Optional & mem_idx only: */
4231
4232 /* tlbia */
4233 static void gen_tlbia(DisasContext *ctx)
4234 {
4235 #if defined(CONFIG_USER_ONLY)
4236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4237 #else
4238 if (unlikely(!ctx->mem_idx)) {
4239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4240 return;
4241 }
4242 gen_helper_tlbia();
4243 #endif
4244 }
4245
4246 /* tlbiel */
4247 static void gen_tlbiel(DisasContext *ctx)
4248 {
4249 #if defined(CONFIG_USER_ONLY)
4250 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4251 #else
4252 if (unlikely(!ctx->mem_idx)) {
4253 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4254 return;
4255 }
4256 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4257 #endif
4258 }
4259
4260 /* tlbie */
4261 static void gen_tlbie(DisasContext *ctx)
4262 {
4263 #if defined(CONFIG_USER_ONLY)
4264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4265 #else
4266 if (unlikely(!ctx->mem_idx)) {
4267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4268 return;
4269 }
4270 #if defined(TARGET_PPC64)
4271 if (!ctx->sf_mode) {
4272 TCGv t0 = tcg_temp_new();
4273 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4274 gen_helper_tlbie(t0);
4275 tcg_temp_free(t0);
4276 } else
4277 #endif
4278 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4279 #endif
4280 }
4281
4282 /* tlbsync */
4283 static void gen_tlbsync(DisasContext *ctx)
4284 {
4285 #if defined(CONFIG_USER_ONLY)
4286 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4287 #else
4288 if (unlikely(!ctx->mem_idx)) {
4289 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4290 return;
4291 }
4292 /* This has no effect: it should ensure that all previous
4293 * tlbie have completed
4294 */
4295 gen_stop_exception(ctx);
4296 #endif
4297 }
4298
4299 #if defined(TARGET_PPC64)
4300 /* slbia */
4301 static void gen_slbia(DisasContext *ctx)
4302 {
4303 #if defined(CONFIG_USER_ONLY)
4304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4305 #else
4306 if (unlikely(!ctx->mem_idx)) {
4307 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4308 return;
4309 }
4310 gen_helper_slbia();
4311 #endif
4312 }
4313
4314 /* slbie */
4315 static void gen_slbie(DisasContext *ctx)
4316 {
4317 #if defined(CONFIG_USER_ONLY)
4318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4319 #else
4320 if (unlikely(!ctx->mem_idx)) {
4321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4322 return;
4323 }
4324 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4325 #endif
4326 }
4327 #endif
4328
4329 /*** External control ***/
4330 /* Optional: */
4331
4332 /* eciwx */
4333 static void gen_eciwx(DisasContext *ctx)
4334 {
4335 TCGv t0;
4336 /* Should check EAR[E] ! */
4337 gen_set_access_type(ctx, ACCESS_EXT);
4338 t0 = tcg_temp_new();
4339 gen_addr_reg_index(ctx, t0);
4340 gen_check_align(ctx, t0, 0x03);
4341 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4342 tcg_temp_free(t0);
4343 }
4344
4345 /* ecowx */
4346 static void gen_ecowx(DisasContext *ctx)
4347 {
4348 TCGv t0;
4349 /* Should check EAR[E] ! */
4350 gen_set_access_type(ctx, ACCESS_EXT);
4351 t0 = tcg_temp_new();
4352 gen_addr_reg_index(ctx, t0);
4353 gen_check_align(ctx, t0, 0x03);
4354 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4355 tcg_temp_free(t0);
4356 }
4357
4358 /* PowerPC 601 specific instructions */
4359
4360 /* abs - abs. */
4361 static void gen_abs(DisasContext *ctx)
4362 {
4363 int l1 = gen_new_label();
4364 int l2 = gen_new_label();
4365 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4366 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4367 tcg_gen_br(l2);
4368 gen_set_label(l1);
4369 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4370 gen_set_label(l2);
4371 if (unlikely(Rc(ctx->opcode) != 0))
4372 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4373 }
4374
4375 /* abso - abso. */
4376 static void gen_abso(DisasContext *ctx)
4377 {
4378 int l1 = gen_new_label();
4379 int l2 = gen_new_label();
4380 int l3 = gen_new_label();
4381 /* Start with XER OV disabled, the most likely case */
4382 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4383 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4384 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4385 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4386 tcg_gen_br(l2);
4387 gen_set_label(l1);
4388 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4389 tcg_gen_br(l3);
4390 gen_set_label(l2);
4391 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4392 gen_set_label(l3);
4393 if (unlikely(Rc(ctx->opcode) != 0))
4394 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4395 }
4396
4397 /* clcs */
4398 static void gen_clcs(DisasContext *ctx)
4399 {
4400 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4401 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4402 tcg_temp_free_i32(t0);
4403 /* Rc=1 sets CR0 to an undefined state */
4404 }
4405
4406 /* div - div. */
4407 static void gen_div(DisasContext *ctx)
4408 {
4409 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4410 if (unlikely(Rc(ctx->opcode) != 0))
4411 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4412 }
4413
4414 /* divo - divo. */
4415 static void gen_divo(DisasContext *ctx)
4416 {
4417 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4418 if (unlikely(Rc(ctx->opcode) != 0))
4419 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4420 }
4421
4422 /* divs - divs. */
4423 static void gen_divs(DisasContext *ctx)
4424 {
4425 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4426 if (unlikely(Rc(ctx->opcode) != 0))
4427 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4428 }
4429
4430 /* divso - divso. */
4431 static void gen_divso(DisasContext *ctx)
4432 {
4433 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4434 if (unlikely(Rc(ctx->opcode) != 0))
4435 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4436 }
4437
4438 /* doz - doz. */
4439 static void gen_doz(DisasContext *ctx)
4440 {
4441 int l1 = gen_new_label();
4442 int l2 = gen_new_label();
4443 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4444 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4445 tcg_gen_br(l2);
4446 gen_set_label(l1);
4447 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4448 gen_set_label(l2);
4449 if (unlikely(Rc(ctx->opcode) != 0))
4450 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4451 }
4452
4453 /* dozo - dozo. */
4454 static void gen_dozo(DisasContext *ctx)
4455 {
4456 int l1 = gen_new_label();
4457 int l2 = gen_new_label();
4458 TCGv t0 = tcg_temp_new();
4459 TCGv t1 = tcg_temp_new();
4460 TCGv t2 = tcg_temp_new();
4461 /* Start with XER OV disabled, the most likely case */
4462 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4463 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4464 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4465 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4466 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4467 tcg_gen_andc_tl(t1, t1, t2);
4468 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4469 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4470 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4471 tcg_gen_br(l2);
4472 gen_set_label(l1);
4473 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4474 gen_set_label(l2);
4475 tcg_temp_free(t0);
4476 tcg_temp_free(t1);
4477 tcg_temp_free(t2);
4478 if (unlikely(Rc(ctx->opcode) != 0))
4479 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4480 }
4481
4482 /* dozi */
4483 static void gen_dozi(DisasContext *ctx)
4484 {
4485 target_long simm = SIMM(ctx->opcode);
4486 int l1 = gen_new_label();
4487 int l2 = gen_new_label();
4488 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4489 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4490 tcg_gen_br(l2);
4491 gen_set_label(l1);
4492 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4493 gen_set_label(l2);
4494 if (unlikely(Rc(ctx->opcode) != 0))
4495 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4496 }
4497
4498 /* lscbx - lscbx. */
4499 static void gen_lscbx(DisasContext *ctx)
4500 {
4501 TCGv t0 = tcg_temp_new();
4502 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4503 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4504 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4505
4506 gen_addr_reg_index(ctx, t0);
4507 /* NIP cannot be restored if the memory exception comes from an helper */
4508 gen_update_nip(ctx, ctx->nip - 4);
4509 gen_helper_lscbx(t0, t0, t1, t2, t3);
4510 tcg_temp_free_i32(t1);
4511 tcg_temp_free_i32(t2);
4512 tcg_temp_free_i32(t3);
4513 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4514 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4515 if (unlikely(Rc(ctx->opcode) != 0))
4516 gen_set_Rc0(ctx, t0);
4517 tcg_temp_free(t0);
4518 }
4519
4520 /* maskg - maskg. */
4521 static void gen_maskg(DisasContext *ctx)
4522 {
4523 int l1 = gen_new_label();
4524 TCGv t0 = tcg_temp_new();
4525 TCGv t1 = tcg_temp_new();
4526 TCGv t2 = tcg_temp_new();
4527 TCGv t3 = tcg_temp_new();
4528 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4529 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4530 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4531 tcg_gen_addi_tl(t2, t0, 1);
4532 tcg_gen_shr_tl(t2, t3, t2);
4533 tcg_gen_shr_tl(t3, t3, t1);
4534 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4535 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4536 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4537 gen_set_label(l1);
4538 tcg_temp_free(t0);
4539 tcg_temp_free(t1);
4540 tcg_temp_free(t2);
4541 tcg_temp_free(t3);
4542 if (unlikely(Rc(ctx->opcode) != 0))
4543 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4544 }
4545
4546 /* maskir - maskir. */
4547 static void gen_maskir(DisasContext *ctx)
4548 {
4549 TCGv t0 = tcg_temp_new();
4550 TCGv t1 = tcg_temp_new();
4551 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4552 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4553 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4554 tcg_temp_free(t0);
4555 tcg_temp_free(t1);
4556 if (unlikely(Rc(ctx->opcode) != 0))
4557 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4558 }
4559
4560 /* mul - mul. */
4561 static void gen_mul(DisasContext *ctx)
4562 {
4563 TCGv_i64 t0 = tcg_temp_new_i64();
4564 TCGv_i64 t1 = tcg_temp_new_i64();
4565 TCGv t2 = tcg_temp_new();
4566 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4567 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4568 tcg_gen_mul_i64(t0, t0, t1);
4569 tcg_gen_trunc_i64_tl(t2, t0);
4570 gen_store_spr(SPR_MQ, t2);
4571 tcg_gen_shri_i64(t1, t0, 32);
4572 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4573 tcg_temp_free_i64(t0);
4574 tcg_temp_free_i64(t1);
4575 tcg_temp_free(t2);
4576 if (unlikely(Rc(ctx->opcode) != 0))
4577 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4578 }
4579
4580 /* mulo - mulo. */
4581 static void gen_mulo(DisasContext *ctx)
4582 {
4583 int l1 = gen_new_label();
4584 TCGv_i64 t0 = tcg_temp_new_i64();
4585 TCGv_i64 t1 = tcg_temp_new_i64();
4586 TCGv t2 = tcg_temp_new();
4587 /* Start with XER OV disabled, the most likely case */
4588 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4589 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4590 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4591 tcg_gen_mul_i64(t0, t0, t1);
4592 tcg_gen_trunc_i64_tl(t2, t0);
4593 gen_store_spr(SPR_MQ, t2);
4594 tcg_gen_shri_i64(t1, t0, 32);
4595 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4596 tcg_gen_ext32s_i64(t1, t0);
4597 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4598 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4599 gen_set_label(l1);
4600 tcg_temp_free_i64(t0);
4601 tcg_temp_free_i64(t1);
4602 tcg_temp_free(t2);
4603 if (unlikely(Rc(ctx->opcode) != 0))
4604 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4605 }
4606
4607 /* nabs - nabs. */
4608 static void gen_nabs(DisasContext *ctx)
4609 {
4610 int l1 = gen_new_label();
4611 int l2 = gen_new_label();
4612 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4613 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4614 tcg_gen_br(l2);
4615 gen_set_label(l1);
4616 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4617 gen_set_label(l2);
4618 if (unlikely(Rc(ctx->opcode) != 0))
4619 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4620 }
4621
4622 /* nabso - nabso. */
4623 static void gen_nabso(DisasContext *ctx)
4624 {
4625 int l1 = gen_new_label();
4626 int l2 = gen_new_label();
4627 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4628 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4629 tcg_gen_br(l2);
4630 gen_set_label(l1);
4631 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4632 gen_set_label(l2);
4633 /* nabs never overflows */
4634 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4635 if (unlikely(Rc(ctx->opcode) != 0))
4636 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4637 }
4638
4639 /* rlmi - rlmi. */
4640 static void gen_rlmi(DisasContext *ctx)
4641 {
4642 uint32_t mb = MB(ctx->opcode);
4643 uint32_t me = ME(ctx->opcode);
4644 TCGv t0 = tcg_temp_new();
4645 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4646 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4647 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4648 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4649 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4650 tcg_temp_free(t0);
4651 if (unlikely(Rc(ctx->opcode) != 0))
4652 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4653 }
4654
4655 /* rrib - rrib. */
4656 static void gen_rrib(DisasContext *ctx)
4657 {
4658 TCGv t0 = tcg_temp_new();
4659 TCGv t1 = tcg_temp_new();
4660 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4661 tcg_gen_movi_tl(t1, 0x80000000);
4662 tcg_gen_shr_tl(t1, t1, t0);
4663 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4664 tcg_gen_and_tl(t0, t0, t1);
4665 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4666 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4667 tcg_temp_free(t0);
4668 tcg_temp_free(t1);
4669 if (unlikely(Rc(ctx->opcode) != 0))
4670 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4671 }
4672
4673 /* sle - sle. */
4674 static void gen_sle(DisasContext *ctx)
4675 {
4676 TCGv t0 = tcg_temp_new();
4677 TCGv t1 = tcg_temp_new();
4678 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4679 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4680 tcg_gen_subfi_tl(t1, 32, t1);
4681 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4682 tcg_gen_or_tl(t1, t0, t1);
4683 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4684 gen_store_spr(SPR_MQ, t1);
4685 tcg_temp_free(t0);
4686 tcg_temp_free(t1);
4687 if (unlikely(Rc(ctx->opcode) != 0))
4688 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4689 }
4690
4691 /* sleq - sleq. */
4692 static void gen_sleq(DisasContext *ctx)
4693 {
4694 TCGv t0 = tcg_temp_new();
4695 TCGv t1 = tcg_temp_new();
4696 TCGv t2 = tcg_temp_new();
4697 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4698 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4699 tcg_gen_shl_tl(t2, t2, t0);
4700 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4701 gen_load_spr(t1, SPR_MQ);
4702 gen_store_spr(SPR_MQ, t0);
4703 tcg_gen_and_tl(t0, t0, t2);
4704 tcg_gen_andc_tl(t1, t1, t2);
4705 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4706 tcg_temp_free(t0);
4707 tcg_temp_free(t1);
4708 tcg_temp_free(t2);
4709 if (unlikely(Rc(ctx->opcode) != 0))
4710 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4711 }
4712
4713 /* sliq - sliq. */
4714 static void gen_sliq(DisasContext *ctx)
4715 {
4716 int sh = SH(ctx->opcode);
4717 TCGv t0 = tcg_temp_new();
4718 TCGv t1 = tcg_temp_new();
4719 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4720 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4721 tcg_gen_or_tl(t1, t0, t1);
4722 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4723 gen_store_spr(SPR_MQ, t1);
4724 tcg_temp_free(t0);
4725 tcg_temp_free(t1);
4726 if (unlikely(Rc(ctx->opcode) != 0))
4727 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4728 }
4729
4730 /* slliq - slliq. */
4731 static void gen_slliq(DisasContext *ctx)
4732 {
4733 int sh = SH(ctx->opcode);
4734 TCGv t0 = tcg_temp_new();
4735 TCGv t1 = tcg_temp_new();
4736 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4737 gen_load_spr(t1, SPR_MQ);
4738 gen_store_spr(SPR_MQ, t0);
4739 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4740 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4741 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4742 tcg_temp_free(t0);
4743 tcg_temp_free(t1);
4744 if (unlikely(Rc(ctx->opcode) != 0))
4745 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4746 }
4747
4748 /* sllq - sllq. */
4749 static void gen_sllq(DisasContext *ctx)
4750 {
4751 int l1 = gen_new_label();
4752 int l2 = gen_new_label();
4753 TCGv t0 = tcg_temp_local_new();
4754 TCGv t1 = tcg_temp_local_new();
4755 TCGv t2 = tcg_temp_local_new();
4756 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4757 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4758 tcg_gen_shl_tl(t1, t1, t2);
4759 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4760 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4761 gen_load_spr(t0, SPR_MQ);
4762 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4763 tcg_gen_br(l2);
4764 gen_set_label(l1);
4765 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4766 gen_load_spr(t2, SPR_MQ);
4767 tcg_gen_andc_tl(t1, t2, t1);
4768 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4769 gen_set_label(l2);
4770 tcg_temp_free(t0);
4771 tcg_temp_free(t1);
4772 tcg_temp_free(t2);
4773 if (unlikely(Rc(ctx->opcode) != 0))
4774 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4775 }
4776
4777 /* slq - slq. */
4778 static void gen_slq(DisasContext *ctx)
4779 {
4780 int l1 = gen_new_label();
4781 TCGv t0 = tcg_temp_new();
4782 TCGv t1 = tcg_temp_new();
4783 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4784 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4785 tcg_gen_subfi_tl(t1, 32, t1);
4786 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4787 tcg_gen_or_tl(t1, t0, t1);
4788 gen_store_spr(SPR_MQ, t1);
4789 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4790 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4791 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4792 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4793 gen_set_label(l1);
4794 tcg_temp_free(t0);
4795 tcg_temp_free(t1);
4796 if (unlikely(Rc(ctx->opcode) != 0))
4797 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4798 }
4799
4800 /* sraiq - sraiq. */
4801 static void gen_sraiq(DisasContext *ctx)
4802 {
4803 int sh = SH(ctx->opcode);
4804 int l1 = gen_new_label();
4805 TCGv t0 = tcg_temp_new();
4806 TCGv t1 = tcg_temp_new();
4807 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4808 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4809 tcg_gen_or_tl(t0, t0, t1);
4810 gen_store_spr(SPR_MQ, t0);
4811 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4812 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4813 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4814 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4815 gen_set_label(l1);
4816 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4817 tcg_temp_free(t0);
4818 tcg_temp_free(t1);
4819 if (unlikely(Rc(ctx->opcode) != 0))
4820 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4821 }
4822
4823 /* sraq - sraq. */
4824 static void gen_sraq(DisasContext *ctx)
4825 {
4826 int l1 = gen_new_label();
4827 int l2 = gen_new_label();
4828 TCGv t0 = tcg_temp_new();
4829 TCGv t1 = tcg_temp_local_new();
4830 TCGv t2 = tcg_temp_local_new();
4831 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4832 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4833 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4834 tcg_gen_subfi_tl(t2, 32, t2);
4835 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4836 tcg_gen_or_tl(t0, t0, t2);
4837 gen_store_spr(SPR_MQ, t0);
4838 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4839 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4840 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4841 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4842 gen_set_label(l1);
4843 tcg_temp_free(t0);
4844 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4845 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4846 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4847 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4848 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4849 gen_set_label(l2);
4850 tcg_temp_free(t1);
4851 tcg_temp_free(t2);
4852 if (unlikely(Rc(ctx->opcode) != 0))
4853 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4854 }
4855
4856 /* sre - sre. */
4857 static void gen_sre(DisasContext *ctx)
4858 {
4859 TCGv t0 = tcg_temp_new();
4860 TCGv t1 = tcg_temp_new();
4861 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4862 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4863 tcg_gen_subfi_tl(t1, 32, t1);
4864 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4865 tcg_gen_or_tl(t1, t0, t1);
4866 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4867 gen_store_spr(SPR_MQ, t1);
4868 tcg_temp_free(t0);
4869 tcg_temp_free(t1);
4870 if (unlikely(Rc(ctx->opcode) != 0))
4871 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4872 }
4873
4874 /* srea - srea. */
4875 static void gen_srea(DisasContext *ctx)
4876 {
4877 TCGv t0 = tcg_temp_new();
4878 TCGv t1 = tcg_temp_new();
4879 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4880 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4881 gen_store_spr(SPR_MQ, t0);
4882 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4883 tcg_temp_free(t0);
4884 tcg_temp_free(t1);
4885 if (unlikely(Rc(ctx->opcode) != 0))
4886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4887 }
4888
4889 /* sreq */
4890 static void gen_sreq(DisasContext *ctx)
4891 {
4892 TCGv t0 = tcg_temp_new();
4893 TCGv t1 = tcg_temp_new();
4894 TCGv t2 = tcg_temp_new();
4895 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4896 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4897 tcg_gen_shr_tl(t1, t1, t0);
4898 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4899 gen_load_spr(t2, SPR_MQ);
4900 gen_store_spr(SPR_MQ, t0);
4901 tcg_gen_and_tl(t0, t0, t1);
4902 tcg_gen_andc_tl(t2, t2, t1);
4903 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4904 tcg_temp_free(t0);
4905 tcg_temp_free(t1);
4906 tcg_temp_free(t2);
4907 if (unlikely(Rc(ctx->opcode) != 0))
4908 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4909 }
4910
4911 /* sriq */
4912 static void gen_sriq(DisasContext *ctx)
4913 {
4914 int sh = SH(ctx->opcode);
4915 TCGv t0 = tcg_temp_new();
4916 TCGv t1 = tcg_temp_new();
4917 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4918 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4919 tcg_gen_or_tl(t1, t0, t1);
4920 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4921 gen_store_spr(SPR_MQ, t1);
4922 tcg_temp_free(t0);
4923 tcg_temp_free(t1);
4924 if (unlikely(Rc(ctx->opcode) != 0))
4925 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4926 }
4927
4928 /* srliq */
4929 static void gen_srliq(DisasContext *ctx)
4930 {
4931 int sh = SH(ctx->opcode);
4932 TCGv t0 = tcg_temp_new();
4933 TCGv t1 = tcg_temp_new();
4934 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4935 gen_load_spr(t1, SPR_MQ);
4936 gen_store_spr(SPR_MQ, t0);
4937 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
4938 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
4939 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4940 tcg_temp_free(t0);
4941 tcg_temp_free(t1);
4942 if (unlikely(Rc(ctx->opcode) != 0))
4943 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4944 }
4945
4946 /* srlq */
4947 static void gen_srlq(DisasContext *ctx)
4948 {
4949 int l1 = gen_new_label();
4950 int l2 = gen_new_label();
4951 TCGv t0 = tcg_temp_local_new();
4952 TCGv t1 = tcg_temp_local_new();
4953 TCGv t2 = tcg_temp_local_new();
4954 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4955 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4956 tcg_gen_shr_tl(t2, t1, t2);
4957 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4958 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4959 gen_load_spr(t0, SPR_MQ);
4960 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4961 tcg_gen_br(l2);
4962 gen_set_label(l1);
4963 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4964 tcg_gen_and_tl(t0, t0, t2);
4965 gen_load_spr(t1, SPR_MQ);
4966 tcg_gen_andc_tl(t1, t1, t2);
4967 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4968 gen_set_label(l2);
4969 tcg_temp_free(t0);
4970 tcg_temp_free(t1);
4971 tcg_temp_free(t2);
4972 if (unlikely(Rc(ctx->opcode) != 0))
4973 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4974 }
4975
4976 /* srq */
4977 static void gen_srq(DisasContext *ctx)
4978 {
4979 int l1 = gen_new_label();
4980 TCGv t0 = tcg_temp_new();
4981 TCGv t1 = tcg_temp_new();
4982 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4983 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4984 tcg_gen_subfi_tl(t1, 32, t1);
4985 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4986 tcg_gen_or_tl(t1, t0, t1);
4987 gen_store_spr(SPR_MQ, t1);
4988 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4989 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4990 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4991 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4992 gen_set_label(l1);
4993 tcg_temp_free(t0);
4994 tcg_temp_free(t1);
4995 if (unlikely(Rc(ctx->opcode) != 0))
4996 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4997 }
4998
4999 /* PowerPC 602 specific instructions */
5000
5001 /* dsa */
5002 static void gen_dsa(DisasContext *ctx)
5003 {
5004 /* XXX: TODO */
5005 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5006 }
5007
5008 /* esa */
5009 static void gen_esa(DisasContext *ctx)
5010 {
5011 /* XXX: TODO */
5012 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5013 }
5014
5015 /* mfrom */
5016 static void gen_mfrom(DisasContext *ctx)
5017 {
5018 #if defined(CONFIG_USER_ONLY)
5019 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5020 #else
5021 if (unlikely(!ctx->mem_idx)) {
5022 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5023 return;
5024 }
5025 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5026 #endif
5027 }
5028
5029 /* 602 - 603 - G2 TLB management */
5030
5031 /* tlbld */
5032 static void gen_tlbld_6xx(DisasContext *ctx)
5033 {
5034 #if defined(CONFIG_USER_ONLY)
5035 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5036 #else
5037 if (unlikely(!ctx->mem_idx)) {
5038 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5039 return;
5040 }
5041 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5042 #endif
5043 }
5044
5045 /* tlbli */
5046 static void gen_tlbli_6xx(DisasContext *ctx)
5047 {
5048 #if defined(CONFIG_USER_ONLY)
5049 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5050 #else
5051 if (unlikely(!ctx->mem_idx)) {
5052 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5053 return;
5054 }
5055 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5056 #endif
5057 }
5058
5059 /* 74xx TLB management */
5060
5061 /* tlbld */
5062 static void gen_tlbld_74xx(DisasContext *ctx)
5063 {
5064 #if defined(CONFIG_USER_ONLY)
5065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5066 #else
5067 if (unlikely(!ctx->mem_idx)) {
5068 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5069 return;
5070 }
5071 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5072 #endif
5073 }
5074
5075 /* tlbli */
5076 static void gen_tlbli_74xx(DisasContext *ctx)
5077 {
5078 #if defined(CONFIG_USER_ONLY)
5079 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5080 #else
5081 if (unlikely(!ctx->mem_idx)) {
5082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5083 return;
5084 }
5085 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5086 #endif
5087 }
5088
5089 /* POWER instructions not in PowerPC 601 */
5090
5091 /* clf */
5092 static void gen_clf(DisasContext *ctx)
5093 {
5094 /* Cache line flush: implemented as no-op */
5095 }
5096
5097 /* cli */
5098 static void gen_cli(DisasContext *ctx)
5099 {
5100 /* Cache line invalidate: privileged and treated as no-op */
5101 #if defined(CONFIG_USER_ONLY)
5102 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5103 #else
5104 if (unlikely(!ctx->mem_idx)) {
5105 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5106 return;
5107 }
5108 #endif
5109 }
5110
5111 /* dclst */
5112 static void gen_dclst(DisasContext *ctx)
5113 {
5114 /* Data cache line store: treated as no-op */
5115 }
5116
5117 static void gen_mfsri(DisasContext *ctx)
5118 {
5119 #if defined(CONFIG_USER_ONLY)
5120 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5121 #else
5122 int ra = rA(ctx->opcode);
5123 int rd = rD(ctx->opcode);
5124 TCGv t0;
5125 if (unlikely(!ctx->mem_idx)) {
5126 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5127 return;
5128 }
5129 t0 = tcg_temp_new();
5130 gen_addr_reg_index(ctx, t0);
5131 tcg_gen_shri_tl(t0, t0, 28);
5132 tcg_gen_andi_tl(t0, t0, 0xF);
5133 gen_helper_load_sr(cpu_gpr[rd], t0);
5134 tcg_temp_free(t0);
5135 if (ra != 0 && ra != rd)
5136 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5137 #endif
5138 }
5139
5140 static void gen_rac(DisasContext *ctx)
5141 {
5142 #if defined(CONFIG_USER_ONLY)
5143 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5144 #else
5145 TCGv t0;
5146 if (unlikely(!ctx->mem_idx)) {
5147 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5148 return;
5149 }
5150 t0 = tcg_temp_new();
5151 gen_addr_reg_index(ctx, t0);
5152 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5153 tcg_temp_free(t0);
5154 #endif
5155 }
5156
5157 static void gen_rfsvc(DisasContext *ctx)
5158 {
5159 #if defined(CONFIG_USER_ONLY)
5160 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5161 #else
5162 if (unlikely(!ctx->mem_idx)) {
5163 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5164 return;
5165 }
5166 gen_helper_rfsvc();
5167 gen_sync_exception(ctx);
5168 #endif
5169 }
5170
5171 /* svc is not implemented for now */
5172
5173 /* POWER2 specific instructions */
5174 /* Quad manipulation (load/store two floats at a time) */
5175
5176 /* lfq */
5177 static void gen_lfq(DisasContext *ctx)
5178 {
5179 int rd = rD(ctx->opcode);
5180 TCGv t0;
5181 gen_set_access_type(ctx, ACCESS_FLOAT);
5182 t0 = tcg_temp_new();
5183 gen_addr_imm_index(ctx, t0, 0);
5184 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5185 gen_addr_add(ctx, t0, t0, 8);
5186 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5187 tcg_temp_free(t0);
5188 }
5189
5190 /* lfqu */
5191 static void gen_lfqu(DisasContext *ctx)
5192 {
5193 int ra = rA(ctx->opcode);
5194 int rd = rD(ctx->opcode);
5195 TCGv t0, t1;
5196 gen_set_access_type(ctx, ACCESS_FLOAT);
5197 t0 = tcg_temp_new();
5198 t1 = tcg_temp_new();
5199 gen_addr_imm_index(ctx, t0, 0);
5200 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5201 gen_addr_add(ctx, t1, t0, 8);
5202 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5203 if (ra != 0)
5204 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5205 tcg_temp_free(t0);
5206 tcg_temp_free(t1);
5207 }
5208
5209 /* lfqux */
5210 static void gen_lfqux(DisasContext *ctx)
5211 {
5212 int ra = rA(ctx->opcode);
5213 int rd = rD(ctx->opcode);
5214 gen_set_access_type(ctx, ACCESS_FLOAT);
5215 TCGv t0, t1;
5216 t0 = tcg_temp_new();
5217 gen_addr_reg_index(ctx, t0);
5218 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5219 t1 = tcg_temp_new();
5220 gen_addr_add(ctx, t1, t0, 8);
5221 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5222 tcg_temp_free(t1);
5223 if (ra != 0)
5224 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5225 tcg_temp_free(t0);
5226 }
5227
5228 /* lfqx */
5229 static void gen_lfqx(DisasContext *ctx)
5230 {
5231 int rd = rD(ctx->opcode);
5232 TCGv t0;
5233 gen_set_access_type(ctx, ACCESS_FLOAT);
5234 t0 = tcg_temp_new();
5235 gen_addr_reg_index(ctx, t0);
5236 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5237 gen_addr_add(ctx, t0, t0, 8);
5238 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5239 tcg_temp_free(t0);
5240 }
5241
5242 /* stfq */
5243 static void gen_stfq(DisasContext *ctx)
5244 {
5245 int rd = rD(ctx->opcode);
5246 TCGv t0;
5247 gen_set_access_type(ctx, ACCESS_FLOAT);
5248 t0 = tcg_temp_new();
5249 gen_addr_imm_index(ctx, t0, 0);
5250 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5251 gen_addr_add(ctx, t0, t0, 8);
5252 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5253 tcg_temp_free(t0);
5254 }
5255
5256 /* stfqu */
5257 static void gen_stfqu(DisasContext *ctx)
5258 {
5259 int ra = rA(ctx->opcode);
5260 int rd = rD(ctx->opcode);
5261 TCGv t0, t1;
5262 gen_set_access_type(ctx, ACCESS_FLOAT);
5263 t0 = tcg_temp_new();
5264 gen_addr_imm_index(ctx, t0, 0);
5265 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5266 t1 = tcg_temp_new();
5267 gen_addr_add(ctx, t1, t0, 8);
5268 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5269 tcg_temp_free(t1);
5270 if (ra != 0)
5271 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5272 tcg_temp_free(t0);
5273 }
5274
5275 /* stfqux */
5276 static void gen_stfqux(DisasContext *ctx)
5277 {
5278 int ra = rA(ctx->opcode);
5279 int rd = rD(ctx->opcode);
5280 TCGv t0, t1;
5281 gen_set_access_type(ctx, ACCESS_FLOAT);
5282 t0 = tcg_temp_new();
5283 gen_addr_reg_index(ctx, t0);
5284 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5285 t1 = tcg_temp_new();
5286 gen_addr_add(ctx, t1, t0, 8);
5287 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5288 tcg_temp_free(t1);
5289 if (ra != 0)
5290 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5291 tcg_temp_free(t0);
5292 }
5293
5294 /* stfqx */
5295 static void gen_stfqx(DisasContext *ctx)
5296 {
5297 int rd = rD(ctx->opcode);
5298 TCGv t0;
5299 gen_set_access_type(ctx, ACCESS_FLOAT);
5300 t0 = tcg_temp_new();
5301 gen_addr_reg_index(ctx, t0);
5302 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5303 gen_addr_add(ctx, t0, t0, 8);
5304 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5305 tcg_temp_free(t0);
5306 }
5307
5308 /* BookE specific instructions */
5309
5310 /* XXX: not implemented on 440 ? */
5311 static void gen_mfapidi(DisasContext *ctx)
5312 {
5313 /* XXX: TODO */
5314 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5315 }
5316
5317 /* XXX: not implemented on 440 ? */
5318 static void gen_tlbiva(DisasContext *ctx)
5319 {
5320 #if defined(CONFIG_USER_ONLY)
5321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5322 #else
5323 TCGv t0;
5324 if (unlikely(!ctx->mem_idx)) {
5325 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5326 return;
5327 }
5328 t0 = tcg_temp_new();
5329 gen_addr_reg_index(ctx, t0);
5330 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5331 tcg_temp_free(t0);
5332 #endif
5333 }
5334
5335 /* All 405 MAC instructions are translated here */
5336 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5337 int opc2, int opc3,
5338 int ra, int rb, int rt, int Rc)
5339 {
5340 TCGv t0, t1;
5341
5342 t0 = tcg_temp_local_new();
5343 t1 = tcg_temp_local_new();
5344
5345 switch (opc3 & 0x0D) {
5346 case 0x05:
5347 /* macchw - macchw. - macchwo - macchwo. */
5348 /* macchws - macchws. - macchwso - macchwso. */
5349 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5350 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5351 /* mulchw - mulchw. */
5352 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5353 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5354 tcg_gen_ext16s_tl(t1, t1);
5355 break;
5356 case 0x04:
5357 /* macchwu - macchwu. - macchwuo - macchwuo. */
5358 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5359 /* mulchwu - mulchwu. */
5360 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5361 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5362 tcg_gen_ext16u_tl(t1, t1);
5363 break;
5364 case 0x01:
5365 /* machhw - machhw. - machhwo - machhwo. */
5366 /* machhws - machhws. - machhwso - machhwso. */
5367 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5368 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5369 /* mulhhw - mulhhw. */
5370 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5371 tcg_gen_ext16s_tl(t0, t0);
5372 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5373 tcg_gen_ext16s_tl(t1, t1);
5374 break;
5375 case 0x00:
5376 /* machhwu - machhwu. - machhwuo - machhwuo. */
5377 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5378 /* mulhhwu - mulhhwu. */
5379 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5380 tcg_gen_ext16u_tl(t0, t0);
5381 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5382 tcg_gen_ext16u_tl(t1, t1);
5383 break;
5384 case 0x0D:
5385 /* maclhw - maclhw. - maclhwo - maclhwo. */
5386 /* maclhws - maclhws. - maclhwso - maclhwso. */
5387 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5388 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5389 /* mullhw - mullhw. */
5390 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5391 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5392 break;
5393 case 0x0C:
5394 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5395 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5396 /* mullhwu - mullhwu. */
5397 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5398 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5399 break;
5400 }
5401 if (opc2 & 0x04) {
5402 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5403 tcg_gen_mul_tl(t1, t0, t1);
5404 if (opc2 & 0x02) {
5405 /* nmultiply-and-accumulate (0x0E) */
5406 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5407 } else {
5408 /* multiply-and-accumulate (0x0C) */
5409 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5410 }
5411
5412 if (opc3 & 0x12) {
5413 /* Check overflow and/or saturate */
5414 int l1 = gen_new_label();
5415
5416 if (opc3 & 0x10) {
5417 /* Start with XER OV disabled, the most likely case */
5418 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5419 }
5420 if (opc3 & 0x01) {
5421 /* Signed */
5422 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5423 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5424 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5425 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5426 if (opc3 & 0x02) {
5427 /* Saturate */
5428 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5429 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5430 }
5431 } else {
5432 /* Unsigned */
5433 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5434 if (opc3 & 0x02) {
5435 /* Saturate */
5436 tcg_gen_movi_tl(t0, UINT32_MAX);
5437 }
5438 }
5439 if (opc3 & 0x10) {
5440 /* Check overflow */
5441 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5442 }
5443 gen_set_label(l1);
5444 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5445 }
5446 } else {
5447 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5448 }
5449 tcg_temp_free(t0);
5450 tcg_temp_free(t1);
5451 if (unlikely(Rc) != 0) {
5452 /* Update Rc0 */
5453 gen_set_Rc0(ctx, cpu_gpr[rt]);
5454 }
5455 }
5456
5457 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5458 static void glue(gen_, name)(DisasContext *ctx) \
5459 { \
5460 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5461 rD(ctx->opcode), Rc(ctx->opcode)); \
5462 }
5463
5464 /* macchw - macchw. */
5465 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5466 /* macchwo - macchwo. */
5467 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5468 /* macchws - macchws. */
5469 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5470 /* macchwso - macchwso. */
5471 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5472 /* macchwsu - macchwsu. */
5473 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5474 /* macchwsuo - macchwsuo. */
5475 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5476 /* macchwu - macchwu. */
5477 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5478 /* macchwuo - macchwuo. */
5479 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5480 /* machhw - machhw. */
5481 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5482 /* machhwo - machhwo. */
5483 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5484 /* machhws - machhws. */
5485 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5486 /* machhwso - machhwso. */
5487 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5488 /* machhwsu - machhwsu. */
5489 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5490 /* machhwsuo - machhwsuo. */
5491 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5492 /* machhwu - machhwu. */
5493 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5494 /* machhwuo - machhwuo. */
5495 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5496 /* maclhw - maclhw. */
5497 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5498 /* maclhwo - maclhwo. */
5499 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5500 /* maclhws - maclhws. */
5501 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5502 /* maclhwso - maclhwso. */
5503 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5504 /* maclhwu - maclhwu. */
5505 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5506 /* maclhwuo - maclhwuo. */
5507 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5508 /* maclhwsu - maclhwsu. */
5509 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5510 /* maclhwsuo - maclhwsuo. */
5511 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5512 /* nmacchw - nmacchw. */
5513 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5514 /* nmacchwo - nmacchwo. */
5515 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5516 /* nmacchws - nmacchws. */
5517 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5518 /* nmacchwso - nmacchwso. */
5519 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5520 /* nmachhw - nmachhw. */
5521 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5522 /* nmachhwo - nmachhwo. */
5523 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5524 /* nmachhws - nmachhws. */
5525 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5526 /* nmachhwso - nmachhwso. */
5527 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5528 /* nmaclhw - nmaclhw. */
5529 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5530 /* nmaclhwo - nmaclhwo. */
5531 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5532 /* nmaclhws - nmaclhws. */
5533 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5534 /* nmaclhwso - nmaclhwso. */
5535 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5536
5537 /* mulchw - mulchw. */
5538 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5539 /* mulchwu - mulchwu. */
5540 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5541 /* mulhhw - mulhhw. */
5542 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5543 /* mulhhwu - mulhhwu. */
5544 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5545 /* mullhw - mullhw. */
5546 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5547 /* mullhwu - mullhwu. */
5548 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5549
5550 /* mfdcr */
5551 static void gen_mfdcr(DisasContext *ctx)
5552 {
5553 #if defined(CONFIG_USER_ONLY)
5554 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5555 #else
5556 TCGv dcrn;
5557 if (unlikely(!ctx->mem_idx)) {
5558 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5559 return;
5560 }
5561 /* NIP cannot be restored if the memory exception comes from an helper */
5562 gen_update_nip(ctx, ctx->nip - 4);
5563 dcrn = tcg_const_tl(SPR(ctx->opcode));
5564 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5565 tcg_temp_free(dcrn);
5566 #endif
5567 }
5568
5569 /* mtdcr */
5570 static void gen_mtdcr(DisasContext *ctx)
5571 {
5572 #if defined(CONFIG_USER_ONLY)
5573 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5574 #else
5575 TCGv dcrn;
5576 if (unlikely(!ctx->mem_idx)) {
5577 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5578 return;
5579 }
5580 /* NIP cannot be restored if the memory exception comes from an helper */
5581 gen_update_nip(ctx, ctx->nip - 4);
5582 dcrn = tcg_const_tl(SPR(ctx->opcode));
5583 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5584 tcg_temp_free(dcrn);
5585 #endif
5586 }
5587
5588 /* mfdcrx */
5589 /* XXX: not implemented on 440 ? */
5590 static void gen_mfdcrx(DisasContext *ctx)
5591 {
5592 #if defined(CONFIG_USER_ONLY)
5593 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5594 #else
5595 if (unlikely(!ctx->mem_idx)) {
5596 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5597 return;
5598 }
5599 /* NIP cannot be restored if the memory exception comes from an helper */
5600 gen_update_nip(ctx, ctx->nip - 4);
5601 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5602 /* Note: Rc update flag set leads to undefined state of Rc0 */
5603 #endif
5604 }
5605
5606 /* mtdcrx */
5607 /* XXX: not implemented on 440 ? */
5608 static void gen_mtdcrx(DisasContext *ctx)
5609 {
5610 #if defined(CONFIG_USER_ONLY)
5611 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5612 #else
5613 if (unlikely(!ctx->mem_idx)) {
5614 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5615 return;
5616 }
5617 /* NIP cannot be restored if the memory exception comes from an helper */
5618 gen_update_nip(ctx, ctx->nip - 4);
5619 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5620 /* Note: Rc update flag set leads to undefined state of Rc0 */
5621 #endif
5622 }
5623
5624 /* mfdcrux (PPC 460) : user-mode access to DCR */
5625 static void gen_mfdcrux(DisasContext *ctx)
5626 {
5627 /* NIP cannot be restored if the memory exception comes from an helper */
5628 gen_update_nip(ctx, ctx->nip - 4);
5629 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5630 /* Note: Rc update flag set leads to undefined state of Rc0 */
5631 }
5632
5633 /* mtdcrux (PPC 460) : user-mode access to DCR */
5634 static void gen_mtdcrux(DisasContext *ctx)
5635 {
5636 /* NIP cannot be restored if the memory exception comes from an helper */
5637 gen_update_nip(ctx, ctx->nip - 4);
5638 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5639 /* Note: Rc update flag set leads to undefined state of Rc0 */
5640 }
5641
5642 /* dccci */
5643 static void gen_dccci(DisasContext *ctx)
5644 {
5645 #if defined(CONFIG_USER_ONLY)
5646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5647 #else
5648 if (unlikely(!ctx->mem_idx)) {
5649 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5650 return;
5651 }
5652 /* interpreted as no-op */
5653 #endif
5654 }
5655
5656 /* dcread */
5657 static void gen_dcread(DisasContext *ctx)
5658 {
5659 #if defined(CONFIG_USER_ONLY)
5660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5661 #else
5662 TCGv EA, val;
5663 if (unlikely(!ctx->mem_idx)) {
5664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5665 return;
5666 }
5667 gen_set_access_type(ctx, ACCESS_CACHE);
5668 EA = tcg_temp_new();
5669 gen_addr_reg_index(ctx, EA);
5670 val = tcg_temp_new();
5671 gen_qemu_ld32u(ctx, val, EA);
5672 tcg_temp_free(val);
5673 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5674 tcg_temp_free(EA);
5675 #endif
5676 }
5677
5678 /* icbt */
5679 static void gen_icbt_40x(DisasContext *ctx)
5680 {
5681 /* interpreted as no-op */
5682 /* XXX: specification say this is treated as a load by the MMU
5683 * but does not generate any exception
5684 */
5685 }
5686
5687 /* iccci */
5688 static void gen_iccci(DisasContext *ctx)
5689 {
5690 #if defined(CONFIG_USER_ONLY)
5691 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5692 #else
5693 if (unlikely(!ctx->mem_idx)) {
5694 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5695 return;
5696 }
5697 /* interpreted as no-op */
5698 #endif
5699 }
5700
5701 /* icread */
5702 static void gen_icread(DisasContext *ctx)
5703 {
5704 #if defined(CONFIG_USER_ONLY)
5705 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5706 #else
5707 if (unlikely(!ctx->mem_idx)) {
5708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5709 return;
5710 }
5711 /* interpreted as no-op */
5712 #endif
5713 }
5714
5715 /* rfci (mem_idx only) */
5716 static void gen_rfci_40x(DisasContext *ctx)
5717 {
5718 #if defined(CONFIG_USER_ONLY)
5719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5720 #else
5721 if (unlikely(!ctx->mem_idx)) {
5722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5723 return;
5724 }
5725 /* Restore CPU state */
5726 gen_helper_40x_rfci();
5727 gen_sync_exception(ctx);
5728 #endif
5729 }
5730
5731 static void gen_rfci(DisasContext *ctx)
5732 {
5733 #if defined(CONFIG_USER_ONLY)
5734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5735 #else
5736 if (unlikely(!ctx->mem_idx)) {
5737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5738 return;
5739 }
5740 /* Restore CPU state */
5741 gen_helper_rfci();
5742 gen_sync_exception(ctx);
5743 #endif
5744 }
5745
5746 /* BookE specific */
5747
5748 /* XXX: not implemented on 440 ? */
5749 static void gen_rfdi(DisasContext *ctx)
5750 {
5751 #if defined(CONFIG_USER_ONLY)
5752 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5753 #else
5754 if (unlikely(!ctx->mem_idx)) {
5755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5756 return;
5757 }
5758 /* Restore CPU state */
5759 gen_helper_rfdi();
5760 gen_sync_exception(ctx);
5761 #endif
5762 }
5763
5764 /* XXX: not implemented on 440 ? */
5765 static void gen_rfmci(DisasContext *ctx)
5766 {
5767 #if defined(CONFIG_USER_ONLY)
5768 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5769 #else
5770 if (unlikely(!ctx->mem_idx)) {
5771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5772 return;
5773 }
5774 /* Restore CPU state */
5775 gen_helper_rfmci();
5776 gen_sync_exception(ctx);
5777 #endif
5778 }
5779
5780 /* TLB management - PowerPC 405 implementation */
5781
5782 /* tlbre */
5783 static void gen_tlbre_40x(DisasContext *ctx)
5784 {
5785 #if defined(CONFIG_USER_ONLY)
5786 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5787 #else
5788 if (unlikely(!ctx->mem_idx)) {
5789 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5790 return;
5791 }
5792 switch (rB(ctx->opcode)) {
5793 case 0:
5794 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5795 break;
5796 case 1:
5797 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5798 break;
5799 default:
5800 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5801 break;
5802 }
5803 #endif
5804 }
5805
5806 /* tlbsx - tlbsx. */
5807 static void gen_tlbsx_40x(DisasContext *ctx)
5808 {
5809 #if defined(CONFIG_USER_ONLY)
5810 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5811 #else
5812 TCGv t0;
5813 if (unlikely(!ctx->mem_idx)) {
5814 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5815 return;
5816 }
5817 t0 = tcg_temp_new();
5818 gen_addr_reg_index(ctx, t0);
5819 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5820 tcg_temp_free(t0);
5821 if (Rc(ctx->opcode)) {
5822 int l1 = gen_new_label();
5823 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5824 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5825 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5826 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5827 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5828 gen_set_label(l1);
5829 }
5830 #endif
5831 }
5832
5833 /* tlbwe */
5834 static void gen_tlbwe_40x(DisasContext *ctx)
5835 {
5836 #if defined(CONFIG_USER_ONLY)
5837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5838 #else
5839 if (unlikely(!ctx->mem_idx)) {
5840 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5841 return;
5842 }
5843 switch (rB(ctx->opcode)) {
5844 case 0:
5845 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5846 break;
5847 case 1:
5848 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5849 break;
5850 default:
5851 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5852 break;
5853 }
5854 #endif
5855 }
5856
5857 /* TLB management - PowerPC 440 implementation */
5858
5859 /* tlbre */
5860 static void gen_tlbre_440(DisasContext *ctx)
5861 {
5862 #if defined(CONFIG_USER_ONLY)
5863 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5864 #else
5865 if (unlikely(!ctx->mem_idx)) {
5866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5867 return;
5868 }
5869 switch (rB(ctx->opcode)) {
5870 case 0:
5871 case 1:
5872 case 2:
5873 {
5874 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5875 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5876 tcg_temp_free_i32(t0);
5877 }
5878 break;
5879 default:
5880 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5881 break;
5882 }
5883 #endif
5884 }
5885
5886 /* tlbsx - tlbsx. */
5887 static void gen_tlbsx_440(DisasContext *ctx)
5888 {
5889 #if defined(CONFIG_USER_ONLY)
5890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5891 #else
5892 TCGv t0;
5893 if (unlikely(!ctx->mem_idx)) {
5894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5895 return;
5896 }
5897 t0 = tcg_temp_new();
5898 gen_addr_reg_index(ctx, t0);
5899 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5900 tcg_temp_free(t0);
5901 if (Rc(ctx->opcode)) {
5902 int l1 = gen_new_label();
5903 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5904 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5905 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5906 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5907 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5908 gen_set_label(l1);
5909 }
5910 #endif
5911 }
5912
5913 /* tlbwe */
5914 static void gen_tlbwe_440(DisasContext *ctx)
5915 {
5916 #if defined(CONFIG_USER_ONLY)
5917 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5918 #else
5919 if (unlikely(!ctx->mem_idx)) {
5920 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5921 return;
5922 }
5923 switch (rB(ctx->opcode)) {
5924 case 0:
5925 case 1:
5926 case 2:
5927 {
5928 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5929 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5930 tcg_temp_free_i32(t0);
5931 }
5932 break;
5933 default:
5934 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5935 break;
5936 }
5937 #endif
5938 }
5939
5940 /* wrtee */
5941 static void gen_wrtee(DisasContext *ctx)
5942 {
5943 #if defined(CONFIG_USER_ONLY)
5944 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5945 #else
5946 TCGv t0;
5947 if (unlikely(!ctx->mem_idx)) {
5948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5949 return;
5950 }
5951 t0 = tcg_temp_new();
5952 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5953 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5954 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5955 tcg_temp_free(t0);
5956 /* Stop translation to have a chance to raise an exception
5957 * if we just set msr_ee to 1
5958 */
5959 gen_stop_exception(ctx);
5960 #endif
5961 }
5962
5963 /* wrteei */
5964 static void gen_wrteei(DisasContext *ctx)
5965 {
5966 #if defined(CONFIG_USER_ONLY)
5967 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5968 #else
5969 if (unlikely(!ctx->mem_idx)) {
5970 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5971 return;
5972 }
5973 if (ctx->opcode & 0x00008000) {
5974 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5975 /* Stop translation to have a chance to raise an exception */
5976 gen_stop_exception(ctx);
5977 } else {
5978 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5979 }
5980 #endif
5981 }
5982
5983 /* PowerPC 440 specific instructions */
5984
5985 /* dlmzb */
5986 static void gen_dlmzb(DisasContext *ctx)
5987 {
5988 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
5989 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
5990 cpu_gpr[rB(ctx->opcode)], t0);
5991 tcg_temp_free_i32(t0);
5992 }
5993
5994 /* mbar replaces eieio on 440 */
5995 static void gen_mbar(DisasContext *ctx)
5996 {
5997 /* interpreted as no-op */
5998 }
5999
6000 /* msync replaces sync on 440 */
6001 static void gen_msync(DisasContext *ctx)
6002 {
6003 /* interpreted as no-op */
6004 }
6005
6006 /* icbt */
6007 static void gen_icbt_440(DisasContext *ctx)
6008 {
6009 /* interpreted as no-op */
6010 /* XXX: specification say this is treated as a load by the MMU
6011 * but does not generate any exception
6012 */
6013 }
6014
6015 /*** Altivec vector extension ***/
6016 /* Altivec registers moves */
6017
6018 static always_inline TCGv_ptr gen_avr_ptr(int reg)
6019 {
6020 TCGv_ptr r = tcg_temp_new_ptr();
6021 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6022 return r;
6023 }
6024
6025 #define GEN_VR_LDX(name, opc2, opc3) \
6026 static void glue(gen_, name)(DisasContext *ctx) \
6027 { \
6028 TCGv EA; \
6029 if (unlikely(!ctx->altivec_enabled)) { \
6030 gen_exception(ctx, POWERPC_EXCP_VPU); \
6031 return; \
6032 } \
6033 gen_set_access_type(ctx, ACCESS_INT); \
6034 EA = tcg_temp_new(); \
6035 gen_addr_reg_index(ctx, EA); \
6036 tcg_gen_andi_tl(EA, EA, ~0xf); \
6037 if (ctx->le_mode) { \
6038 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6039 tcg_gen_addi_tl(EA, EA, 8); \
6040 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6041 } else { \
6042 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6043 tcg_gen_addi_tl(EA, EA, 8); \
6044 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6045 } \
6046 tcg_temp_free(EA); \
6047 }
6048
6049 #define GEN_VR_STX(name, opc2, opc3) \
6050 static void gen_st##name(DisasContext *ctx) \
6051 { \
6052 TCGv EA; \
6053 if (unlikely(!ctx->altivec_enabled)) { \
6054 gen_exception(ctx, POWERPC_EXCP_VPU); \
6055 return; \
6056 } \
6057 gen_set_access_type(ctx, ACCESS_INT); \
6058 EA = tcg_temp_new(); \
6059 gen_addr_reg_index(ctx, EA); \
6060 tcg_gen_andi_tl(EA, EA, ~0xf); \
6061 if (ctx->le_mode) { \
6062 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6063 tcg_gen_addi_tl(EA, EA, 8); \
6064 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6065 } else { \
6066 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6067 tcg_gen_addi_tl(EA, EA, 8); \
6068 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6069 } \
6070 tcg_temp_free(EA); \
6071 }
6072
6073 #define GEN_VR_LVE(name, opc2, opc3) \
6074 static void gen_lve##name(DisasContext *ctx) \
6075 { \
6076 TCGv EA; \
6077 TCGv_ptr rs; \
6078 if (unlikely(!ctx->altivec_enabled)) { \
6079 gen_exception(ctx, POWERPC_EXCP_VPU); \
6080 return; \
6081 } \
6082 gen_set_access_type(ctx, ACCESS_INT); \
6083 EA = tcg_temp_new(); \
6084 gen_addr_reg_index(ctx, EA); \
6085 rs = gen_avr_ptr(rS(ctx->opcode)); \
6086 gen_helper_lve##name (rs, EA); \
6087 tcg_temp_free(EA); \
6088 tcg_temp_free_ptr(rs); \
6089 }
6090
6091 #define GEN_VR_STVE(name, opc2, opc3) \
6092 static void gen_stve##name(DisasContext *ctx) \
6093 { \
6094 TCGv EA; \
6095 TCGv_ptr rs; \
6096 if (unlikely(!ctx->altivec_enabled)) { \
6097 gen_exception(ctx, POWERPC_EXCP_VPU); \
6098 return; \
6099 } \
6100 gen_set_access_type(ctx, ACCESS_INT); \
6101 EA = tcg_temp_new(); \
6102 gen_addr_reg_index(ctx, EA); \
6103 rs = gen_avr_ptr(rS(ctx->opcode)); \
6104 gen_helper_stve##name (rs, EA); \
6105 tcg_temp_free(EA); \
6106 tcg_temp_free_ptr(rs); \
6107 }
6108
6109 GEN_VR_LDX(lvx, 0x07, 0x03);
6110 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6111 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6112
6113 GEN_VR_LVE(bx, 0x07, 0x00);
6114 GEN_VR_LVE(hx, 0x07, 0x01);
6115 GEN_VR_LVE(wx, 0x07, 0x02);
6116
6117 GEN_VR_STX(svx, 0x07, 0x07);
6118 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6119 GEN_VR_STX(svxl, 0x07, 0x0F);
6120
6121 GEN_VR_STVE(bx, 0x07, 0x04);
6122 GEN_VR_STVE(hx, 0x07, 0x05);
6123 GEN_VR_STVE(wx, 0x07, 0x06);
6124
6125 static void gen_lvsl(DisasContext *ctx)
6126 {
6127 TCGv_ptr rd;
6128 TCGv EA;
6129 if (unlikely(!ctx->altivec_enabled)) {
6130 gen_exception(ctx, POWERPC_EXCP_VPU);
6131 return;
6132 }
6133 EA = tcg_temp_new();
6134 gen_addr_reg_index(ctx, EA);
6135 rd = gen_avr_ptr(rD(ctx->opcode));
6136 gen_helper_lvsl(rd, EA);
6137 tcg_temp_free(EA);
6138 tcg_temp_free_ptr(rd);
6139 }
6140
6141 static void gen_lvsr(DisasContext *ctx)
6142 {
6143 TCGv_ptr rd;
6144 TCGv EA;
6145 if (unlikely(!ctx->altivec_enabled)) {
6146 gen_exception(ctx, POWERPC_EXCP_VPU);
6147 return;
6148 }
6149 EA = tcg_temp_new();
6150 gen_addr_reg_index(ctx, EA);
6151 rd = gen_avr_ptr(rD(ctx->opcode));
6152 gen_helper_lvsr(rd, EA);
6153 tcg_temp_free(EA);
6154 tcg_temp_free_ptr(rd);
6155 }
6156
6157 static void gen_mfvscr(DisasContext *ctx)
6158 {
6159 TCGv_i32 t;
6160 if (unlikely(!ctx->altivec_enabled)) {
6161 gen_exception(ctx, POWERPC_EXCP_VPU);
6162 return;
6163 }
6164 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6165 t = tcg_temp_new_i32();
6166 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6167 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6168 tcg_temp_free_i32(t);
6169 }
6170
6171 static void gen_mtvscr(DisasContext *ctx)
6172 {
6173 TCGv_ptr p;
6174 if (unlikely(!ctx->altivec_enabled)) {
6175 gen_exception(ctx, POWERPC_EXCP_VPU);
6176 return;
6177 }
6178 p = gen_avr_ptr(rD(ctx->opcode));
6179 gen_helper_mtvscr(p);
6180 tcg_temp_free_ptr(p);
6181 }
6182
6183 /* Logical operations */
6184 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6185 static void glue(gen_, name)(DisasContext *ctx) \
6186 { \
6187 if (unlikely(!ctx->altivec_enabled)) { \
6188 gen_exception(ctx, POWERPC_EXCP_VPU); \
6189 return; \
6190 } \
6191 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6192 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6193 }
6194
6195 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6196 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6197 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6198 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6199 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6200
6201 #define GEN_VXFORM(name, opc2, opc3) \
6202 static void glue(gen_, name)(DisasContext *ctx) \
6203 { \
6204 TCGv_ptr ra, rb, rd; \
6205 if (unlikely(!ctx->altivec_enabled)) { \
6206 gen_exception(ctx, POWERPC_EXCP_VPU); \
6207 return; \
6208 } \
6209 ra = gen_avr_ptr(rA(ctx->opcode)); \
6210 rb = gen_avr_ptr(rB(ctx->opcode)); \
6211 rd = gen_avr_ptr(rD(ctx->opcode)); \
6212 gen_helper_##name (rd, ra, rb); \
6213 tcg_temp_free_ptr(ra); \
6214 tcg_temp_free_ptr(rb); \
6215 tcg_temp_free_ptr(rd); \
6216 }
6217
6218 GEN_VXFORM(vaddubm, 0, 0);
6219 GEN_VXFORM(vadduhm, 0, 1);
6220 GEN_VXFORM(vadduwm, 0, 2);
6221 GEN_VXFORM(vsububm, 0, 16);
6222 GEN_VXFORM(vsubuhm, 0, 17);
6223 GEN_VXFORM(vsubuwm, 0, 18);
6224 GEN_VXFORM(vmaxub, 1, 0);
6225 GEN_VXFORM(vmaxuh, 1, 1);
6226 GEN_VXFORM(vmaxuw, 1, 2);
6227 GEN_VXFORM(vmaxsb, 1, 4);
6228 GEN_VXFORM(vmaxsh, 1, 5);
6229 GEN_VXFORM(vmaxsw, 1, 6);
6230 GEN_VXFORM(vminub, 1, 8);
6231 GEN_VXFORM(vminuh, 1, 9);
6232 GEN_VXFORM(vminuw, 1, 10);
6233 GEN_VXFORM(vminsb, 1, 12);
6234 GEN_VXFORM(vminsh, 1, 13);
6235 GEN_VXFORM(vminsw, 1, 14);
6236 GEN_VXFORM(vavgub, 1, 16);
6237 GEN_VXFORM(vavguh, 1, 17);
6238 GEN_VXFORM(vavguw, 1, 18);
6239 GEN_VXFORM(vavgsb, 1, 20);
6240 GEN_VXFORM(vavgsh, 1, 21);
6241 GEN_VXFORM(vavgsw, 1, 22);
6242 GEN_VXFORM(vmrghb, 6, 0);
6243 GEN_VXFORM(vmrghh, 6, 1);
6244 GEN_VXFORM(vmrghw, 6, 2);
6245 GEN_VXFORM(vmrglb, 6, 4);
6246 GEN_VXFORM(vmrglh, 6, 5);
6247 GEN_VXFORM(vmrglw, 6, 6);
6248 GEN_VXFORM(vmuloub, 4, 0);
6249 GEN_VXFORM(vmulouh, 4, 1);
6250 GEN_VXFORM(vmulosb, 4, 4);
6251 GEN_VXFORM(vmulosh, 4, 5);
6252 GEN_VXFORM(vmuleub, 4, 8);
6253 GEN_VXFORM(vmuleuh, 4, 9);
6254 GEN_VXFORM(vmulesb, 4, 12);
6255 GEN_VXFORM(vmulesh, 4, 13);
6256 GEN_VXFORM(vslb, 2, 4);
6257 GEN_VXFORM(vslh, 2, 5);
6258 GEN_VXFORM(vslw, 2, 6);
6259 GEN_VXFORM(vsrb, 2, 8);
6260 GEN_VXFORM(vsrh, 2, 9);
6261 GEN_VXFORM(vsrw, 2, 10);
6262 GEN_VXFORM(vsrab, 2, 12);
6263 GEN_VXFORM(vsrah, 2, 13);
6264 GEN_VXFORM(vsraw, 2, 14);
6265 GEN_VXFORM(vslo, 6, 16);
6266 GEN_VXFORM(vsro, 6, 17);
6267 GEN_VXFORM(vaddcuw, 0, 6);
6268 GEN_VXFORM(vsubcuw, 0, 22);
6269 GEN_VXFORM(vaddubs, 0, 8);
6270 GEN_VXFORM(vadduhs, 0, 9);
6271 GEN_VXFORM(vadduws, 0, 10);
6272 GEN_VXFORM(vaddsbs, 0, 12);
6273 GEN_VXFORM(vaddshs, 0, 13);
6274 GEN_VXFORM(vaddsws, 0, 14);
6275 GEN_VXFORM(vsububs, 0, 24);
6276 GEN_VXFORM(vsubuhs, 0, 25);
6277 GEN_VXFORM(vsubuws, 0, 26);
6278 GEN_VXFORM(vsubsbs, 0, 28);
6279 GEN_VXFORM(vsubshs, 0, 29);
6280 GEN_VXFORM(vsubsws, 0, 30);
6281 GEN_VXFORM(vrlb, 2, 0);
6282 GEN_VXFORM(vrlh, 2, 1);
6283 GEN_VXFORM(vrlw, 2, 2);
6284 GEN_VXFORM(vsl, 2, 7);
6285 GEN_VXFORM(vsr, 2, 11);
6286 GEN_VXFORM(vpkuhum, 7, 0);
6287 GEN_VXFORM(vpkuwum, 7, 1);
6288 GEN_VXFORM(vpkuhus, 7, 2);
6289 GEN_VXFORM(vpkuwus, 7, 3);
6290 GEN_VXFORM(vpkshus, 7, 4);
6291 GEN_VXFORM(vpkswus, 7, 5);
6292 GEN_VXFORM(vpkshss, 7, 6);
6293 GEN_VXFORM(vpkswss, 7, 7);
6294 GEN_VXFORM(vpkpx, 7, 12);
6295 GEN_VXFORM(vsum4ubs, 4, 24);
6296 GEN_VXFORM(vsum4sbs, 4, 28);
6297 GEN_VXFORM(vsum4shs, 4, 25);
6298 GEN_VXFORM(vsum2sws, 4, 26);
6299 GEN_VXFORM(vsumsws, 4, 30);
6300 GEN_VXFORM(vaddfp, 5, 0);
6301 GEN_VXFORM(vsubfp, 5, 1);
6302 GEN_VXFORM(vmaxfp, 5, 16);
6303 GEN_VXFORM(vminfp, 5, 17);
6304
6305 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6306 static void glue(gen_, name)(DisasContext *ctx) \
6307 { \
6308 TCGv_ptr ra, rb, rd; \
6309 if (unlikely(!ctx->altivec_enabled)) { \
6310 gen_exception(ctx, POWERPC_EXCP_VPU); \
6311 return; \
6312 } \
6313 ra = gen_avr_ptr(rA(ctx->opcode)); \
6314 rb = gen_avr_ptr(rB(ctx->opcode)); \
6315 rd = gen_avr_ptr(rD(ctx->opcode)); \
6316 gen_helper_##opname (rd, ra, rb); \
6317 tcg_temp_free_ptr(ra); \
6318 tcg_temp_free_ptr(rb); \
6319 tcg_temp_free_ptr(rd); \
6320 }
6321
6322 #define GEN_VXRFORM(name, opc2, opc3) \
6323 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6324 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6325
6326 GEN_VXRFORM(vcmpequb, 3, 0)
6327 GEN_VXRFORM(vcmpequh, 3, 1)
6328 GEN_VXRFORM(vcmpequw, 3, 2)
6329 GEN_VXRFORM(vcmpgtsb, 3, 12)
6330 GEN_VXRFORM(vcmpgtsh, 3, 13)
6331 GEN_VXRFORM(vcmpgtsw, 3, 14)
6332 GEN_VXRFORM(vcmpgtub, 3, 8)
6333 GEN_VXRFORM(vcmpgtuh, 3, 9)
6334 GEN_VXRFORM(vcmpgtuw, 3, 10)
6335 GEN_VXRFORM(vcmpeqfp, 3, 3)
6336 GEN_VXRFORM(vcmpgefp, 3, 7)
6337 GEN_VXRFORM(vcmpgtfp, 3, 11)
6338 GEN_VXRFORM(vcmpbfp, 3, 15)
6339
6340 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6341 static void glue(gen_, name)(DisasContext *ctx) \
6342 { \
6343 TCGv_ptr rd; \
6344 TCGv_i32 simm; \
6345 if (unlikely(!ctx->altivec_enabled)) { \
6346 gen_exception(ctx, POWERPC_EXCP_VPU); \
6347 return; \
6348 } \
6349 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6350 rd = gen_avr_ptr(rD(ctx->opcode)); \
6351 gen_helper_##name (rd, simm); \
6352 tcg_temp_free_i32(simm); \
6353 tcg_temp_free_ptr(rd); \
6354 }
6355
6356 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6357 GEN_VXFORM_SIMM(vspltish, 6, 13);
6358 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6359
6360 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6361 static void glue(gen_, name)(DisasContext *ctx) \
6362 { \
6363 TCGv_ptr rb, rd; \
6364 if (unlikely(!ctx->altivec_enabled)) { \
6365 gen_exception(ctx, POWERPC_EXCP_VPU); \
6366 return; \
6367 } \
6368 rb = gen_avr_ptr(rB(ctx->opcode)); \
6369 rd = gen_avr_ptr(rD(ctx->opcode)); \
6370 gen_helper_##name (rd, rb); \
6371 tcg_temp_free_ptr(rb); \
6372 tcg_temp_free_ptr(rd); \
6373 }
6374
6375 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6376 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6377 GEN_VXFORM_NOA(vupklsb, 7, 10);
6378 GEN_VXFORM_NOA(vupklsh, 7, 11);
6379 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6380 GEN_VXFORM_NOA(vupklpx, 7, 15);
6381 GEN_VXFORM_NOA(vrefp, 5, 4);
6382 GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
6383 GEN_VXFORM_NOA(vlogefp, 5, 7);
6384 GEN_VXFORM_NOA(vrfim, 5, 8);
6385 GEN_VXFORM_NOA(vrfin, 5, 9);
6386 GEN_VXFORM_NOA(vrfip, 5, 10);
6387 GEN_VXFORM_NOA(vrfiz, 5, 11);
6388
6389 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6390 static void glue(gen_, name)(DisasContext *ctx) \
6391 { \
6392 TCGv_ptr rd; \
6393 TCGv_i32 simm; \
6394 if (unlikely(!ctx->altivec_enabled)) { \
6395 gen_exception(ctx, POWERPC_EXCP_VPU); \
6396 return; \
6397 } \
6398 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6399 rd = gen_avr_ptr(rD(ctx->opcode)); \
6400 gen_helper_##name (rd, simm); \
6401 tcg_temp_free_i32(simm); \
6402 tcg_temp_free_ptr(rd); \
6403 }
6404
6405 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6406 static void glue(gen_, name)(DisasContext *ctx) \
6407 { \
6408 TCGv_ptr rb, rd; \
6409 TCGv_i32 uimm; \
6410 if (unlikely(!ctx->altivec_enabled)) { \
6411 gen_exception(ctx, POWERPC_EXCP_VPU); \
6412 return; \
6413 } \
6414 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6415 rb = gen_avr_ptr(rB(ctx->opcode)); \
6416 rd = gen_avr_ptr(rD(ctx->opcode)); \
6417 gen_helper_##name (rd, rb, uimm); \
6418 tcg_temp_free_i32(uimm); \
6419 tcg_temp_free_ptr(rb); \
6420 tcg_temp_free_ptr(rd); \
6421 }
6422
6423 GEN_VXFORM_UIMM(vspltb, 6, 8);
6424 GEN_VXFORM_UIMM(vsplth, 6, 9);
6425 GEN_VXFORM_UIMM(vspltw, 6, 10);
6426 GEN_VXFORM_UIMM(vcfux, 5, 12);
6427 GEN_VXFORM_UIMM(vcfsx, 5, 13);
6428 GEN_VXFORM_UIMM(vctuxs, 5, 14);
6429 GEN_VXFORM_UIMM(vctsxs, 5, 15);
6430
6431 static void gen_vsldoi(DisasContext *ctx)
6432 {
6433 TCGv_ptr ra, rb, rd;
6434 TCGv_i32 sh;
6435 if (unlikely(!ctx->altivec_enabled)) {
6436 gen_exception(ctx, POWERPC_EXCP_VPU);
6437 return;
6438 }
6439 ra = gen_avr_ptr(rA(ctx->opcode));
6440 rb = gen_avr_ptr(rB(ctx->opcode));
6441 rd = gen_avr_ptr(rD(ctx->opcode));
6442 sh = tcg_const_i32(VSH(ctx->opcode));
6443 gen_helper_vsldoi (rd, ra, rb, sh);
6444 tcg_temp_free_ptr(ra);
6445 tcg_temp_free_ptr(rb);
6446 tcg_temp_free_ptr(rd);
6447 tcg_temp_free_i32(sh);
6448 }
6449
6450 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6451 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6452 { \
6453 TCGv_ptr ra, rb, rc, rd; \
6454 if (unlikely(!ctx->altivec_enabled)) { \
6455 gen_exception(ctx, POWERPC_EXCP_VPU); \
6456 return; \
6457 } \
6458 ra = gen_avr_ptr(rA(ctx->opcode)); \
6459 rb = gen_avr_ptr(rB(ctx->opcode)); \
6460 rc = gen_avr_ptr(rC(ctx->opcode)); \
6461 rd = gen_avr_ptr(rD(ctx->opcode)); \
6462 if (Rc(ctx->opcode)) { \
6463 gen_helper_##name1 (rd, ra, rb, rc); \
6464 } else { \
6465 gen_helper_##name0 (rd, ra, rb, rc); \
6466 } \
6467 tcg_temp_free_ptr(ra); \
6468 tcg_temp_free_ptr(rb); \
6469 tcg_temp_free_ptr(rc); \
6470 tcg_temp_free_ptr(rd); \
6471 }
6472
6473 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6474
6475 static void gen_vmladduhm(DisasContext *ctx)
6476 {
6477 TCGv_ptr ra, rb, rc, rd;
6478 if (unlikely(!ctx->altivec_enabled)) {
6479 gen_exception(ctx, POWERPC_EXCP_VPU);
6480 return;
6481 }
6482 ra = gen_avr_ptr(rA(ctx->opcode));
6483 rb = gen_avr_ptr(rB(ctx->opcode));
6484 rc = gen_avr_ptr(rC(ctx->opcode));
6485 rd = gen_avr_ptr(rD(ctx->opcode));
6486 gen_helper_vmladduhm(rd, ra, rb, rc);
6487 tcg_temp_free_ptr(ra);
6488 tcg_temp_free_ptr(rb);
6489 tcg_temp_free_ptr(rc);
6490 tcg_temp_free_ptr(rd);
6491 }
6492
6493 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6494 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6495 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6496 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6497 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6498
6499 /*** SPE extension ***/
6500 /* Register moves */
6501
6502 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
6503 #if defined(TARGET_PPC64)
6504 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6505 #else
6506 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6507 #endif
6508 }
6509
6510 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
6511 #if defined(TARGET_PPC64)
6512 tcg_gen_mov_i64(cpu_gpr[reg], t);
6513 #else
6514 TCGv_i64 tmp = tcg_temp_new_i64();
6515 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6516 tcg_gen_shri_i64(tmp, t, 32);
6517 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6518 tcg_temp_free_i64(tmp);
6519 #endif
6520 }
6521
6522 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6523 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6524 { \
6525 if (Rc(ctx->opcode)) \
6526 gen_##name1(ctx); \
6527 else \
6528 gen_##name0(ctx); \
6529 }
6530
6531 /* Handler for undefined SPE opcodes */
6532 static always_inline void gen_speundef (DisasContext *ctx)
6533 {
6534 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6535 }
6536
6537 /* SPE logic */
6538 #if defined(TARGET_PPC64)
6539 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6540 static always_inline void gen_##name (DisasContext *ctx) \
6541 { \
6542 if (unlikely(!ctx->spe_enabled)) { \
6543 gen_exception(ctx, POWERPC_EXCP_APU); \
6544 return; \
6545 } \
6546 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6547 cpu_gpr[rB(ctx->opcode)]); \
6548 }
6549 #else
6550 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6551 static always_inline void gen_##name (DisasContext *ctx) \
6552 { \
6553 if (unlikely(!ctx->spe_enabled)) { \
6554 gen_exception(ctx, POWERPC_EXCP_APU); \
6555 return; \
6556 } \
6557 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6558 cpu_gpr[rB(ctx->opcode)]); \
6559 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6560 cpu_gprh[rB(ctx->opcode)]); \
6561 }
6562 #endif
6563
6564 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6565 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6566 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6567 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6568 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6569 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6570 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6571 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6572
6573 /* SPE logic immediate */
6574 #if defined(TARGET_PPC64)
6575 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6576 static always_inline void gen_##name (DisasContext *ctx) \
6577 { \
6578 if (unlikely(!ctx->spe_enabled)) { \
6579 gen_exception(ctx, POWERPC_EXCP_APU); \
6580 return; \
6581 } \
6582 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6583 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6584 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6585 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6586 tcg_opi(t0, t0, rB(ctx->opcode)); \
6587 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6588 tcg_gen_trunc_i64_i32(t1, t2); \
6589 tcg_temp_free_i64(t2); \
6590 tcg_opi(t1, t1, rB(ctx->opcode)); \
6591 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6592 tcg_temp_free_i32(t0); \
6593 tcg_temp_free_i32(t1); \
6594 }
6595 #else
6596 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6597 static always_inline void gen_##name (DisasContext *ctx) \
6598 { \
6599 if (unlikely(!ctx->spe_enabled)) { \
6600 gen_exception(ctx, POWERPC_EXCP_APU); \
6601 return; \
6602 } \
6603 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6604 rB(ctx->opcode)); \
6605 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6606 rB(ctx->opcode)); \
6607 }
6608 #endif
6609 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6610 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6611 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6612 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6613
6614 /* SPE arithmetic */
6615 #if defined(TARGET_PPC64)
6616 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6617 static always_inline void gen_##name (DisasContext *ctx) \
6618 { \
6619 if (unlikely(!ctx->spe_enabled)) { \
6620 gen_exception(ctx, POWERPC_EXCP_APU); \
6621 return; \
6622 } \
6623 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6624 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6625 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6626 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6627 tcg_op(t0, t0); \
6628 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6629 tcg_gen_trunc_i64_i32(t1, t2); \
6630 tcg_temp_free_i64(t2); \
6631 tcg_op(t1, t1); \
6632 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6633 tcg_temp_free_i32(t0); \
6634 tcg_temp_free_i32(t1); \
6635 }
6636 #else
6637 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6638 static always_inline void gen_##name (DisasContext *ctx) \
6639 { \
6640 if (unlikely(!ctx->spe_enabled)) { \
6641 gen_exception(ctx, POWERPC_EXCP_APU); \
6642 return; \
6643 } \
6644 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6645 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6646 }
6647 #endif
6648
6649 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6650 {
6651 int l1 = gen_new_label();
6652 int l2 = gen_new_label();
6653
6654 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6655 tcg_gen_neg_i32(ret, arg1);
6656 tcg_gen_br(l2);
6657 gen_set_label(l1);
6658 tcg_gen_mov_i32(ret, arg1);
6659 gen_set_label(l2);
6660 }
6661 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6662 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6663 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6664 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6665 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6666 {
6667 tcg_gen_addi_i32(ret, arg1, 0x8000);
6668 tcg_gen_ext16u_i32(ret, ret);
6669 }
6670 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6671 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6672 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6673
6674 #if defined(TARGET_PPC64)
6675 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6676 static always_inline void gen_##name (DisasContext *ctx) \
6677 { \
6678 if (unlikely(!ctx->spe_enabled)) { \
6679 gen_exception(ctx, POWERPC_EXCP_APU); \
6680 return; \
6681 } \
6682 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6683 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6684 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6685 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6686 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6687 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6688 tcg_op(t0, t0, t2); \
6689 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6690 tcg_gen_trunc_i64_i32(t1, t3); \
6691 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6692 tcg_gen_trunc_i64_i32(t2, t3); \
6693 tcg_temp_free_i64(t3); \
6694 tcg_op(t1, t1, t2); \
6695 tcg_temp_free_i32(t2); \
6696 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6697 tcg_temp_free_i32(t0); \
6698 tcg_temp_free_i32(t1); \
6699 }
6700 #else
6701 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6702 static always_inline void gen_##name (DisasContext *ctx) \
6703 { \
6704 if (unlikely(!ctx->spe_enabled)) { \
6705 gen_exception(ctx, POWERPC_EXCP_APU); \
6706 return; \
6707 } \
6708 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6709 cpu_gpr[rB(ctx->opcode)]); \
6710 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6711 cpu_gprh[rB(ctx->opcode)]); \
6712 }
6713 #endif
6714
6715 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6716 {
6717 TCGv_i32 t0;
6718 int l1, l2;
6719
6720 l1 = gen_new_label();
6721 l2 = gen_new_label();
6722 t0 = tcg_temp_local_new_i32();
6723 /* No error here: 6 bits are used */
6724 tcg_gen_andi_i32(t0, arg2, 0x3F);
6725 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6726 tcg_gen_shr_i32(ret, arg1, t0);
6727 tcg_gen_br(l2);
6728 gen_set_label(l1);
6729 tcg_gen_movi_i32(ret, 0);
6730 tcg_gen_br(l2);
6731 tcg_temp_free_i32(t0);
6732 }
6733 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6734 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6735 {
6736 TCGv_i32 t0;
6737 int l1, l2;
6738
6739 l1 = gen_new_label();
6740 l2 = gen_new_label();
6741 t0 = tcg_temp_local_new_i32();
6742 /* No error here: 6 bits are used */
6743 tcg_gen_andi_i32(t0, arg2, 0x3F);
6744 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6745 tcg_gen_sar_i32(ret, arg1, t0);
6746 tcg_gen_br(l2);
6747 gen_set_label(l1);
6748 tcg_gen_movi_i32(ret, 0);
6749 tcg_gen_br(l2);
6750 tcg_temp_free_i32(t0);
6751 }
6752 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6753 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6754 {
6755 TCGv_i32 t0;
6756 int l1, l2;
6757
6758 l1 = gen_new_label();
6759 l2 = gen_new_label();
6760 t0 = tcg_temp_local_new_i32();
6761 /* No error here: 6 bits are used */
6762 tcg_gen_andi_i32(t0, arg2, 0x3F);
6763 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6764 tcg_gen_shl_i32(ret, arg1, t0);
6765 tcg_gen_br(l2);
6766 gen_set_label(l1);
6767 tcg_gen_movi_i32(ret, 0);
6768 tcg_gen_br(l2);
6769 tcg_temp_free_i32(t0);
6770 }
6771 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6772 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6773 {
6774 TCGv_i32 t0 = tcg_temp_new_i32();
6775 tcg_gen_andi_i32(t0, arg2, 0x1F);
6776 tcg_gen_rotl_i32(ret, arg1, t0);
6777 tcg_temp_free_i32(t0);
6778 }
6779 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6780 static always_inline void gen_evmergehi (DisasContext *ctx)
6781 {
6782 if (unlikely(!ctx->spe_enabled)) {
6783 gen_exception(ctx, POWERPC_EXCP_APU);
6784 return;
6785 }
6786 #if defined(TARGET_PPC64)
6787 TCGv t0 = tcg_temp_new();
6788 TCGv t1 = tcg_temp_new();
6789 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6790 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6791 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6792 tcg_temp_free(t0);
6793 tcg_temp_free(t1);
6794 #else
6795 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6796 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6797 #endif
6798 }
6799 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6800 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6801 {
6802 tcg_gen_sub_i32(ret, arg2, arg1);
6803 }
6804 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6805
6806 /* SPE arithmetic immediate */
6807 #if defined(TARGET_PPC64)
6808 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6809 static always_inline void gen_##name (DisasContext *ctx) \
6810 { \
6811 if (unlikely(!ctx->spe_enabled)) { \
6812 gen_exception(ctx, POWERPC_EXCP_APU); \
6813 return; \
6814 } \
6815 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6816 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6817 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6818 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6819 tcg_op(t0, t0, rA(ctx->opcode)); \
6820 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6821 tcg_gen_trunc_i64_i32(t1, t2); \
6822 tcg_temp_free_i64(t2); \
6823 tcg_op(t1, t1, rA(ctx->opcode)); \
6824 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6825 tcg_temp_free_i32(t0); \
6826 tcg_temp_free_i32(t1); \
6827 }
6828 #else
6829 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6830 static always_inline void gen_##name (DisasContext *ctx) \
6831 { \
6832 if (unlikely(!ctx->spe_enabled)) { \
6833 gen_exception(ctx, POWERPC_EXCP_APU); \
6834 return; \
6835 } \
6836 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6837 rA(ctx->opcode)); \
6838 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6839 rA(ctx->opcode)); \
6840 }
6841 #endif
6842 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6843 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6844
6845 /* SPE comparison */
6846 #if defined(TARGET_PPC64)
6847 #define GEN_SPEOP_COMP(name, tcg_cond) \
6848 static always_inline void gen_##name (DisasContext *ctx) \
6849 { \
6850 if (unlikely(!ctx->spe_enabled)) { \
6851 gen_exception(ctx, POWERPC_EXCP_APU); \
6852 return; \
6853 } \
6854 int l1 = gen_new_label(); \
6855 int l2 = gen_new_label(); \
6856 int l3 = gen_new_label(); \
6857 int l4 = gen_new_label(); \
6858 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6859 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6860 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6861 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6862 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6863 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6864 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6865 tcg_gen_br(l2); \
6866 gen_set_label(l1); \
6867 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6868 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6869 gen_set_label(l2); \
6870 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6871 tcg_gen_trunc_i64_i32(t0, t2); \
6872 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6873 tcg_gen_trunc_i64_i32(t1, t2); \
6874 tcg_temp_free_i64(t2); \
6875 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6876 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6877 ~(CRF_CH | CRF_CH_AND_CL)); \
6878 tcg_gen_br(l4); \
6879 gen_set_label(l3); \
6880 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6881 CRF_CH | CRF_CH_OR_CL); \
6882 gen_set_label(l4); \
6883 tcg_temp_free_i32(t0); \
6884 tcg_temp_free_i32(t1); \
6885 }
6886 #else
6887 #define GEN_SPEOP_COMP(name, tcg_cond) \
6888 static always_inline void gen_##name (DisasContext *ctx) \
6889 { \
6890 if (unlikely(!ctx->spe_enabled)) { \
6891 gen_exception(ctx, POWERPC_EXCP_APU); \
6892 return; \
6893 } \
6894 int l1 = gen_new_label(); \
6895 int l2 = gen_new_label(); \
6896 int l3 = gen_new_label(); \
6897 int l4 = gen_new_label(); \
6898 \
6899 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6900 cpu_gpr[rB(ctx->opcode)], l1); \
6901 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6902 tcg_gen_br(l2); \
6903 gen_set_label(l1); \
6904 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6905 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6906 gen_set_label(l2); \
6907 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6908 cpu_gprh[rB(ctx->opcode)], l3); \
6909 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6910 ~(CRF_CH | CRF_CH_AND_CL)); \
6911 tcg_gen_br(l4); \
6912 gen_set_label(l3); \
6913 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6914 CRF_CH | CRF_CH_OR_CL); \
6915 gen_set_label(l4); \
6916 }
6917 #endif
6918 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6919 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6920 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6921 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6922 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6923
6924 /* SPE misc */
6925 static always_inline void gen_brinc (DisasContext *ctx)
6926 {
6927 /* Note: brinc is usable even if SPE is disabled */
6928 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6929 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6930 }
6931 static always_inline void gen_evmergelo (DisasContext *ctx)
6932 {
6933 if (unlikely(!ctx->spe_enabled)) {
6934 gen_exception(ctx, POWERPC_EXCP_APU);
6935 return;
6936 }
6937 #if defined(TARGET_PPC64)
6938 TCGv t0 = tcg_temp_new();
6939 TCGv t1 = tcg_temp_new();
6940 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6941 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6942 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6943 tcg_temp_free(t0);
6944 tcg_temp_free(t1);
6945 #else
6946 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6947 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6948 #endif
6949 }
6950 static always_inline void gen_evmergehilo (DisasContext *ctx)
6951 {
6952 if (unlikely(!ctx->spe_enabled)) {
6953 gen_exception(ctx, POWERPC_EXCP_APU);
6954 return;
6955 }
6956 #if defined(TARGET_PPC64)
6957 TCGv t0 = tcg_temp_new();
6958 TCGv t1 = tcg_temp_new();
6959 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6960 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6961 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6962 tcg_temp_free(t0);
6963 tcg_temp_free(t1);
6964 #else
6965 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6966 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6967 #endif
6968 }
6969 static always_inline void gen_evmergelohi (DisasContext *ctx)
6970 {
6971 if (unlikely(!ctx->spe_enabled)) {
6972 gen_exception(ctx, POWERPC_EXCP_APU);
6973 return;
6974 }
6975 #if defined(TARGET_PPC64)
6976 TCGv t0 = tcg_temp_new();
6977 TCGv t1 = tcg_temp_new();
6978 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6979 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6980 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6981 tcg_temp_free(t0);
6982 tcg_temp_free(t1);
6983 #else
6984 if (rD(ctx->opcode) == rA(ctx->opcode)) {
6985 TCGv_i32 tmp = tcg_temp_new_i32();
6986 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
6987 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6988 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
6989 tcg_temp_free_i32(tmp);
6990 } else {
6991 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6992 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6993 }
6994 #endif
6995 }
6996 static always_inline void gen_evsplati (DisasContext *ctx)
6997 {
6998 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
6999
7000 #if defined(TARGET_PPC64)
7001 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7002 #else
7003 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7004 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7005 #endif
7006 }
7007 static always_inline void gen_evsplatfi (DisasContext *ctx)
7008 {
7009 uint64_t imm = rA(ctx->opcode) << 11;
7010
7011 #if defined(TARGET_PPC64)
7012 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7013 #else
7014 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7015 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7016 #endif
7017 }
7018
7019 static always_inline void gen_evsel (DisasContext *ctx)
7020 {
7021 int l1 = gen_new_label();
7022 int l2 = gen_new_label();
7023 int l3 = gen_new_label();
7024 int l4 = gen_new_label();
7025 TCGv_i32 t0 = tcg_temp_local_new_i32();
7026 #if defined(TARGET_PPC64)
7027 TCGv t1 = tcg_temp_local_new();
7028 TCGv t2 = tcg_temp_local_new();
7029 #endif
7030 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7031 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7032 #if defined(TARGET_PPC64)
7033 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7034 #else
7035 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7036 #endif
7037 tcg_gen_br(l2);
7038 gen_set_label(l1);
7039 #if defined(TARGET_PPC64)
7040 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7041 #else
7042 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7043 #endif
7044 gen_set_label(l2);
7045 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7046 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7047 #if defined(TARGET_PPC64)
7048 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7049 #else
7050 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7051 #endif
7052 tcg_gen_br(l4);
7053 gen_set_label(l3);
7054 #if defined(TARGET_PPC64)
7055 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7056 #else
7057 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7058 #endif
7059 gen_set_label(l4);
7060 tcg_temp_free_i32(t0);
7061 #if defined(TARGET_PPC64)
7062 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7063 tcg_temp_free(t1);
7064 tcg_temp_free(t2);
7065 #endif
7066 }
7067
7068 static void gen_evsel0(DisasContext *ctx)
7069 {
7070 gen_evsel(ctx);
7071 }
7072
7073 static void gen_evsel1(DisasContext *ctx)
7074 {
7075 gen_evsel(ctx);
7076 }
7077
7078 static void gen_evsel2(DisasContext *ctx)
7079 {
7080 gen_evsel(ctx);
7081 }
7082
7083 static void gen_evsel3(DisasContext *ctx)
7084 {
7085 gen_evsel(ctx);
7086 }
7087
7088 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7089 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7090 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7091 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7092 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7093 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7094 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7095 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7096 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7097 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7098 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7099 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7100 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7101 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7102 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7103 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7104 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7105 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7106 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7107 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7108 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7109 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7110 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7111 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7112 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7113
7114 /* SPE load and stores */
7115 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
7116 {
7117 target_ulong uimm = rB(ctx->opcode);
7118
7119 if (rA(ctx->opcode) == 0) {
7120 tcg_gen_movi_tl(EA, uimm << sh);
7121 } else {
7122 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7123 #if defined(TARGET_PPC64)
7124 if (!ctx->sf_mode) {
7125 tcg_gen_ext32u_tl(EA, EA);
7126 }
7127 #endif
7128 }
7129 }
7130
7131 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7132 {
7133 #if defined(TARGET_PPC64)
7134 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7135 #else
7136 TCGv_i64 t0 = tcg_temp_new_i64();
7137 gen_qemu_ld64(ctx, t0, addr);
7138 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7139 tcg_gen_shri_i64(t0, t0, 32);
7140 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7141 tcg_temp_free_i64(t0);
7142 #endif
7143 }
7144
7145 static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7146 {
7147 #if defined(TARGET_PPC64)
7148 TCGv t0 = tcg_temp_new();
7149 gen_qemu_ld32u(ctx, t0, addr);
7150 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7151 gen_addr_add(ctx, addr, addr, 4);
7152 gen_qemu_ld32u(ctx, t0, addr);
7153 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7154 tcg_temp_free(t0);
7155 #else
7156 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7157 gen_addr_add(ctx, addr, addr, 4);
7158 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7159 #endif
7160 }
7161
7162 static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7163 {
7164 TCGv t0 = tcg_temp_new();
7165 #if defined(TARGET_PPC64)
7166 gen_qemu_ld16u(ctx, t0, addr);
7167 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7168 gen_addr_add(ctx, addr, addr, 2);
7169 gen_qemu_ld16u(ctx, t0, addr);
7170 tcg_gen_shli_tl(t0, t0, 32);
7171 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7172 gen_addr_add(ctx, addr, addr, 2);
7173 gen_qemu_ld16u(ctx, t0, addr);
7174 tcg_gen_shli_tl(t0, t0, 16);
7175 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7176 gen_addr_add(ctx, addr, addr, 2);
7177 gen_qemu_ld16u(ctx, t0, addr);
7178 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7179 #else
7180 gen_qemu_ld16u(ctx, t0, addr);
7181 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7182 gen_addr_add(ctx, addr, addr, 2);
7183 gen_qemu_ld16u(ctx, t0, addr);
7184 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7185 gen_addr_add(ctx, addr, addr, 2);
7186 gen_qemu_ld16u(ctx, t0, addr);
7187 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7188 gen_addr_add(ctx, addr, addr, 2);
7189 gen_qemu_ld16u(ctx, t0, addr);
7190 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7191 #endif
7192 tcg_temp_free(t0);
7193 }
7194
7195 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7196 {
7197 TCGv t0 = tcg_temp_new();
7198 gen_qemu_ld16u(ctx, t0, addr);
7199 #if defined(TARGET_PPC64)
7200 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7201 tcg_gen_shli_tl(t0, t0, 16);
7202 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7203 #else
7204 tcg_gen_shli_tl(t0, t0, 16);
7205 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7206 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7207 #endif
7208 tcg_temp_free(t0);
7209 }
7210
7211 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7212 {
7213 TCGv t0 = tcg_temp_new();
7214 gen_qemu_ld16u(ctx, t0, addr);
7215 #if defined(TARGET_PPC64)
7216 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7217 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7218 #else
7219 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7220 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7221 #endif
7222 tcg_temp_free(t0);
7223 }
7224
7225 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7226 {
7227 TCGv t0 = tcg_temp_new();
7228 gen_qemu_ld16s(ctx, t0, addr);
7229 #if defined(TARGET_PPC64)
7230 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7231 tcg_gen_ext32u_tl(t0, t0);
7232 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7233 #else
7234 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7235 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7236 #endif
7237 tcg_temp_free(t0);
7238 }
7239
7240 static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7241 {
7242 TCGv t0 = tcg_temp_new();
7243 #if defined(TARGET_PPC64)
7244 gen_qemu_ld16u(ctx, t0, addr);
7245 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7246 gen_addr_add(ctx, addr, addr, 2);
7247 gen_qemu_ld16u(ctx, t0, addr);
7248 tcg_gen_shli_tl(t0, t0, 16);
7249 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7250 #else
7251 gen_qemu_ld16u(ctx, t0, addr);
7252 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7253 gen_addr_add(ctx, addr, addr, 2);
7254 gen_qemu_ld16u(ctx, t0, addr);
7255 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7256 #endif
7257 tcg_temp_free(t0);
7258 }
7259
7260 static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7261 {
7262 #if defined(TARGET_PPC64)
7263 TCGv t0 = tcg_temp_new();
7264 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7265 gen_addr_add(ctx, addr, addr, 2);
7266 gen_qemu_ld16u(ctx, t0, addr);
7267 tcg_gen_shli_tl(t0, t0, 32);
7268 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7269 tcg_temp_free(t0);
7270 #else
7271 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7272 gen_addr_add(ctx, addr, addr, 2);
7273 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7274 #endif
7275 }
7276
7277 static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7278 {
7279 #if defined(TARGET_PPC64)
7280 TCGv t0 = tcg_temp_new();
7281 gen_qemu_ld16s(ctx, t0, addr);
7282 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7283 gen_addr_add(ctx, addr, addr, 2);
7284 gen_qemu_ld16s(ctx, t0, addr);
7285 tcg_gen_shli_tl(t0, t0, 32);
7286 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7287 tcg_temp_free(t0);
7288 #else
7289 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7290 gen_addr_add(ctx, addr, addr, 2);
7291 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7292 #endif
7293 }
7294
7295 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7296 {
7297 TCGv t0 = tcg_temp_new();
7298 gen_qemu_ld32u(ctx, t0, addr);
7299 #if defined(TARGET_PPC64)
7300 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7301 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7302 #else
7303 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7304 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7305 #endif
7306 tcg_temp_free(t0);
7307 }
7308
7309 static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7310 {
7311 TCGv t0 = tcg_temp_new();
7312 #if defined(TARGET_PPC64)
7313 gen_qemu_ld16u(ctx, t0, addr);
7314 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7315 tcg_gen_shli_tl(t0, t0, 32);
7316 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7317 gen_addr_add(ctx, addr, addr, 2);
7318 gen_qemu_ld16u(ctx, t0, addr);
7319 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7320 tcg_gen_shli_tl(t0, t0, 16);
7321 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7322 #else
7323 gen_qemu_ld16u(ctx, t0, addr);
7324 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7325 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7326 gen_addr_add(ctx, addr, addr, 2);
7327 gen_qemu_ld16u(ctx, t0, addr);
7328 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7329 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7330 #endif
7331 tcg_temp_free(t0);
7332 }
7333
7334 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7335 {
7336 #if defined(TARGET_PPC64)
7337 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7338 #else
7339 TCGv_i64 t0 = tcg_temp_new_i64();
7340 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7341 gen_qemu_st64(ctx, t0, addr);
7342 tcg_temp_free_i64(t0);
7343 #endif
7344 }
7345
7346 static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7347 {
7348 #if defined(TARGET_PPC64)
7349 TCGv t0 = tcg_temp_new();
7350 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7351 gen_qemu_st32(ctx, t0, addr);
7352 tcg_temp_free(t0);
7353 #else
7354 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7355 #endif
7356 gen_addr_add(ctx, addr, addr, 4);
7357 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7358 }
7359
7360 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7361 {
7362 TCGv t0 = tcg_temp_new();
7363 #if defined(TARGET_PPC64)
7364 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7365 #else
7366 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7367 #endif
7368 gen_qemu_st16(ctx, t0, addr);
7369 gen_addr_add(ctx, addr, addr, 2);
7370 #if defined(TARGET_PPC64)
7371 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7372 gen_qemu_st16(ctx, t0, addr);
7373 #else
7374 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7375 #endif
7376 gen_addr_add(ctx, addr, addr, 2);
7377 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7378 gen_qemu_st16(ctx, t0, addr);
7379 tcg_temp_free(t0);
7380 gen_addr_add(ctx, addr, addr, 2);
7381 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7382 }
7383
7384 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7385 {
7386 TCGv t0 = tcg_temp_new();
7387 #if defined(TARGET_PPC64)
7388 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7389 #else
7390 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7391 #endif
7392 gen_qemu_st16(ctx, t0, addr);
7393 gen_addr_add(ctx, addr, addr, 2);
7394 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7395 gen_qemu_st16(ctx, t0, addr);
7396 tcg_temp_free(t0);
7397 }
7398
7399 static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7400 {
7401 #if defined(TARGET_PPC64)
7402 TCGv t0 = tcg_temp_new();
7403 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7404 gen_qemu_st16(ctx, t0, addr);
7405 tcg_temp_free(t0);
7406 #else
7407 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7408 #endif
7409 gen_addr_add(ctx, addr, addr, 2);
7410 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7411 }
7412
7413 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7414 {
7415 #if defined(TARGET_PPC64)
7416 TCGv t0 = tcg_temp_new();
7417 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7418 gen_qemu_st32(ctx, t0, addr);
7419 tcg_temp_free(t0);
7420 #else
7421 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7422 #endif
7423 }
7424
7425 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7426 {
7427 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7428 }
7429
7430 #define GEN_SPEOP_LDST(name, opc2, sh) \
7431 static void glue(gen_, name)(DisasContext *ctx) \
7432 { \
7433 TCGv t0; \
7434 if (unlikely(!ctx->spe_enabled)) { \
7435 gen_exception(ctx, POWERPC_EXCP_APU); \
7436 return; \
7437 } \
7438 gen_set_access_type(ctx, ACCESS_INT); \
7439 t0 = tcg_temp_new(); \
7440 if (Rc(ctx->opcode)) { \
7441 gen_addr_spe_imm_index(ctx, t0, sh); \
7442 } else { \
7443 gen_addr_reg_index(ctx, t0); \
7444 } \
7445 gen_op_##name(ctx, t0); \
7446 tcg_temp_free(t0); \
7447 }
7448
7449 GEN_SPEOP_LDST(evldd, 0x00, 3);
7450 GEN_SPEOP_LDST(evldw, 0x01, 3);
7451 GEN_SPEOP_LDST(evldh, 0x02, 3);
7452 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7453 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7454 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7455 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7456 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7457 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7458 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7459 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7460
7461 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7462 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7463 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7464 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7465 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7466 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7467 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7468
7469 /* Multiply and add - TODO */
7470 #if 0
7471 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7472 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7473 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7474 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7475 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7476 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7477 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7478 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7479 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7480 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7481 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7482 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7483
7484 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7485 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7486 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7487 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7488 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7489 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7490 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7491 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7492 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7493 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7494 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7495 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7496 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7497 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7498
7499 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7500 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7501 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7502 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7503 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7504 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7505
7506 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7507 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7508 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7509 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7510 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7511 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7512 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7513 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7514 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7515 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7516 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7517 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7518
7519 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7520 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7521 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7522 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7523 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7524
7525 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7526 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7527 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7528 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7529 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7530 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7531 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7532 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7533 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7534 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7535 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7536 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7537
7538 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7539 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7540 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7541 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7542 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7543 #endif
7544
7545 /*** SPE floating-point extension ***/
7546 #if defined(TARGET_PPC64)
7547 #define GEN_SPEFPUOP_CONV_32_32(name) \
7548 static always_inline void gen_##name (DisasContext *ctx) \
7549 { \
7550 TCGv_i32 t0; \
7551 TCGv t1; \
7552 t0 = tcg_temp_new_i32(); \
7553 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7554 gen_helper_##name(t0, t0); \
7555 t1 = tcg_temp_new(); \
7556 tcg_gen_extu_i32_tl(t1, t0); \
7557 tcg_temp_free_i32(t0); \
7558 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7559 0xFFFFFFFF00000000ULL); \
7560 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7561 tcg_temp_free(t1); \
7562 }
7563 #define GEN_SPEFPUOP_CONV_32_64(name) \
7564 static always_inline void gen_##name (DisasContext *ctx) \
7565 { \
7566 TCGv_i32 t0; \
7567 TCGv t1; \
7568 t0 = tcg_temp_new_i32(); \
7569 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7570 t1 = tcg_temp_new(); \
7571 tcg_gen_extu_i32_tl(t1, t0); \
7572 tcg_temp_free_i32(t0); \
7573 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7574 0xFFFFFFFF00000000ULL); \
7575 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7576 tcg_temp_free(t1); \
7577 }
7578 #define GEN_SPEFPUOP_CONV_64_32(name) \
7579 static always_inline void gen_##name (DisasContext *ctx) \
7580 { \
7581 TCGv_i32 t0 = tcg_temp_new_i32(); \
7582 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7583 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7584 tcg_temp_free_i32(t0); \
7585 }
7586 #define GEN_SPEFPUOP_CONV_64_64(name) \
7587 static always_inline void gen_##name (DisasContext *ctx) \
7588 { \
7589 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7590 }
7591 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7592 static always_inline void gen_##name (DisasContext *ctx) \
7593 { \
7594 TCGv_i32 t0, t1; \
7595 TCGv_i64 t2; \
7596 if (unlikely(!ctx->spe_enabled)) { \
7597 gen_exception(ctx, POWERPC_EXCP_APU); \
7598 return; \
7599 } \
7600 t0 = tcg_temp_new_i32(); \
7601 t1 = tcg_temp_new_i32(); \
7602 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7603 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7604 gen_helper_##name(t0, t0, t1); \
7605 tcg_temp_free_i32(t1); \
7606 t2 = tcg_temp_new(); \
7607 tcg_gen_extu_i32_tl(t2, t0); \
7608 tcg_temp_free_i32(t0); \
7609 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7610 0xFFFFFFFF00000000ULL); \
7611 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7612 tcg_temp_free(t2); \
7613 }
7614 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7615 static always_inline void gen_##name (DisasContext *ctx) \
7616 { \
7617 if (unlikely(!ctx->spe_enabled)) { \
7618 gen_exception(ctx, POWERPC_EXCP_APU); \
7619 return; \
7620 } \
7621 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7622 cpu_gpr[rB(ctx->opcode)]); \
7623 }
7624 #define GEN_SPEFPUOP_COMP_32(name) \
7625 static always_inline void gen_##name (DisasContext *ctx) \
7626 { \
7627 TCGv_i32 t0, t1; \
7628 if (unlikely(!ctx->spe_enabled)) { \
7629 gen_exception(ctx, POWERPC_EXCP_APU); \
7630 return; \
7631 } \
7632 t0 = tcg_temp_new_i32(); \
7633 t1 = tcg_temp_new_i32(); \
7634 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7635 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7636 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7637 tcg_temp_free_i32(t0); \
7638 tcg_temp_free_i32(t1); \
7639 }
7640 #define GEN_SPEFPUOP_COMP_64(name) \
7641 static always_inline void gen_##name (DisasContext *ctx) \
7642 { \
7643 if (unlikely(!ctx->spe_enabled)) { \
7644 gen_exception(ctx, POWERPC_EXCP_APU); \
7645 return; \
7646 } \
7647 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7648 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7649 }
7650 #else
7651 #define GEN_SPEFPUOP_CONV_32_32(name) \
7652 static always_inline void gen_##name (DisasContext *ctx) \
7653 { \
7654 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7655 }
7656 #define GEN_SPEFPUOP_CONV_32_64(name) \
7657 static always_inline void gen_##name (DisasContext *ctx) \
7658 { \
7659 TCGv_i64 t0 = tcg_temp_new_i64(); \
7660 gen_load_gpr64(t0, rB(ctx->opcode)); \
7661 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7662 tcg_temp_free_i64(t0); \
7663 }
7664 #define GEN_SPEFPUOP_CONV_64_32(name) \
7665 static always_inline void gen_##name (DisasContext *ctx) \
7666 { \
7667 TCGv_i64 t0 = tcg_temp_new_i64(); \
7668 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7669 gen_store_gpr64(rD(ctx->opcode), t0); \
7670 tcg_temp_free_i64(t0); \
7671 }
7672 #define GEN_SPEFPUOP_CONV_64_64(name) \
7673 static always_inline void gen_##name (DisasContext *ctx) \
7674 { \
7675 TCGv_i64 t0 = tcg_temp_new_i64(); \
7676 gen_load_gpr64(t0, rB(ctx->opcode)); \
7677 gen_helper_##name(t0, t0); \
7678 gen_store_gpr64(rD(ctx->opcode), t0); \
7679 tcg_temp_free_i64(t0); \
7680 }
7681 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7682 static always_inline void gen_##name (DisasContext *ctx) \
7683 { \
7684 if (unlikely(!ctx->spe_enabled)) { \
7685 gen_exception(ctx, POWERPC_EXCP_APU); \
7686 return; \
7687 } \
7688 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7689 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7690 }
7691 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7692 static always_inline void gen_##name (DisasContext *ctx) \
7693 { \
7694 TCGv_i64 t0, t1; \
7695 if (unlikely(!ctx->spe_enabled)) { \
7696 gen_exception(ctx, POWERPC_EXCP_APU); \
7697 return; \
7698 } \
7699 t0 = tcg_temp_new_i64(); \
7700 t1 = tcg_temp_new_i64(); \
7701 gen_load_gpr64(t0, rA(ctx->opcode)); \
7702 gen_load_gpr64(t1, rB(ctx->opcode)); \
7703 gen_helper_##name(t0, t0, t1); \
7704 gen_store_gpr64(rD(ctx->opcode), t0); \
7705 tcg_temp_free_i64(t0); \
7706 tcg_temp_free_i64(t1); \
7707 }
7708 #define GEN_SPEFPUOP_COMP_32(name) \
7709 static always_inline void gen_##name (DisasContext *ctx) \
7710 { \
7711 if (unlikely(!ctx->spe_enabled)) { \
7712 gen_exception(ctx, POWERPC_EXCP_APU); \
7713 return; \
7714 } \
7715 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7716 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7717 }
7718 #define GEN_SPEFPUOP_COMP_64(name) \
7719 static always_inline void gen_##name (DisasContext *ctx) \
7720 { \
7721 TCGv_i64 t0, t1; \
7722 if (unlikely(!ctx->spe_enabled)) { \
7723 gen_exception(ctx, POWERPC_EXCP_APU); \
7724 return; \
7725 } \
7726 t0 = tcg_temp_new_i64(); \
7727 t1 = tcg_temp_new_i64(); \
7728 gen_load_gpr64(t0, rA(ctx->opcode)); \
7729 gen_load_gpr64(t1, rB(ctx->opcode)); \
7730 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7731 tcg_temp_free_i64(t0); \
7732 tcg_temp_free_i64(t1); \
7733 }
7734 #endif
7735
7736 /* Single precision floating-point vectors operations */
7737 /* Arithmetic */
7738 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7739 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7740 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7741 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7742 static always_inline void gen_evfsabs (DisasContext *ctx)
7743 {
7744 if (unlikely(!ctx->spe_enabled)) {
7745 gen_exception(ctx, POWERPC_EXCP_APU);
7746 return;
7747 }
7748 #if defined(TARGET_PPC64)
7749 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7750 #else
7751 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7752 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7753 #endif
7754 }
7755 static always_inline void gen_evfsnabs (DisasContext *ctx)
7756 {
7757 if (unlikely(!ctx->spe_enabled)) {
7758 gen_exception(ctx, POWERPC_EXCP_APU);
7759 return;
7760 }
7761 #if defined(TARGET_PPC64)
7762 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7763 #else
7764 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7765 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7766 #endif
7767 }
7768 static always_inline void gen_evfsneg (DisasContext *ctx)
7769 {
7770 if (unlikely(!ctx->spe_enabled)) {
7771 gen_exception(ctx, POWERPC_EXCP_APU);
7772 return;
7773 }
7774 #if defined(TARGET_PPC64)
7775 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7776 #else
7777 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7778 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7779 #endif
7780 }
7781
7782 /* Conversion */
7783 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7784 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7785 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7786 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7787 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7788 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7789 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7790 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7791 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7792 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7793
7794 /* Comparison */
7795 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7796 GEN_SPEFPUOP_COMP_64(evfscmplt);
7797 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7798 GEN_SPEFPUOP_COMP_64(evfststgt);
7799 GEN_SPEFPUOP_COMP_64(evfststlt);
7800 GEN_SPEFPUOP_COMP_64(evfststeq);
7801
7802 /* Opcodes definitions */
7803 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7804 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7805 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7806 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7807 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7808 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7809 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7810 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7811 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7812 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7813 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7814 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7815 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7816 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7817
7818 /* Single precision floating-point operations */
7819 /* Arithmetic */
7820 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7821 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7822 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7823 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7824 static always_inline void gen_efsabs (DisasContext *ctx)
7825 {
7826 if (unlikely(!ctx->spe_enabled)) {
7827 gen_exception(ctx, POWERPC_EXCP_APU);
7828 return;
7829 }
7830 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7831 }
7832 static always_inline void gen_efsnabs (DisasContext *ctx)
7833 {
7834 if (unlikely(!ctx->spe_enabled)) {
7835 gen_exception(ctx, POWERPC_EXCP_APU);
7836 return;
7837 }
7838 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7839 }
7840 static always_inline void gen_efsneg (DisasContext *ctx)
7841 {
7842 if (unlikely(!ctx->spe_enabled)) {
7843 gen_exception(ctx, POWERPC_EXCP_APU);
7844 return;
7845 }
7846 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7847 }
7848
7849 /* Conversion */
7850 GEN_SPEFPUOP_CONV_32_32(efscfui);
7851 GEN_SPEFPUOP_CONV_32_32(efscfsi);
7852 GEN_SPEFPUOP_CONV_32_32(efscfuf);
7853 GEN_SPEFPUOP_CONV_32_32(efscfsf);
7854 GEN_SPEFPUOP_CONV_32_32(efsctui);
7855 GEN_SPEFPUOP_CONV_32_32(efsctsi);
7856 GEN_SPEFPUOP_CONV_32_32(efsctuf);
7857 GEN_SPEFPUOP_CONV_32_32(efsctsf);
7858 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7859 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7860 GEN_SPEFPUOP_CONV_32_64(efscfd);
7861
7862 /* Comparison */
7863 GEN_SPEFPUOP_COMP_32(efscmpgt);
7864 GEN_SPEFPUOP_COMP_32(efscmplt);
7865 GEN_SPEFPUOP_COMP_32(efscmpeq);
7866 GEN_SPEFPUOP_COMP_32(efststgt);
7867 GEN_SPEFPUOP_COMP_32(efststlt);
7868 GEN_SPEFPUOP_COMP_32(efststeq);
7869
7870 /* Opcodes definitions */
7871 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7872 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7873 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7874 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7875 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7876 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7877 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7878 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7879 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7880 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7881 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7882 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7883 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7884 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7885
7886 /* Double precision floating-point operations */
7887 /* Arithmetic */
7888 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7889 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7890 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7891 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7892 static always_inline void gen_efdabs (DisasContext *ctx)
7893 {
7894 if (unlikely(!ctx->spe_enabled)) {
7895 gen_exception(ctx, POWERPC_EXCP_APU);
7896 return;
7897 }
7898 #if defined(TARGET_PPC64)
7899 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7900 #else
7901 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7902 #endif
7903 }
7904 static always_inline void gen_efdnabs (DisasContext *ctx)
7905 {
7906 if (unlikely(!ctx->spe_enabled)) {
7907 gen_exception(ctx, POWERPC_EXCP_APU);
7908 return;
7909 }
7910 #if defined(TARGET_PPC64)
7911 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7912 #else
7913 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7914 #endif
7915 }
7916 static always_inline void gen_efdneg (DisasContext *ctx)
7917 {
7918 if (unlikely(!ctx->spe_enabled)) {
7919 gen_exception(ctx, POWERPC_EXCP_APU);
7920 return;
7921 }
7922 #if defined(TARGET_PPC64)
7923 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7924 #else
7925 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7926 #endif
7927 }
7928
7929 /* Conversion */
7930 GEN_SPEFPUOP_CONV_64_32(efdcfui);
7931 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7932 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7933 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7934 GEN_SPEFPUOP_CONV_32_64(efdctui);
7935 GEN_SPEFPUOP_CONV_32_64(efdctsi);
7936 GEN_SPEFPUOP_CONV_32_64(efdctuf);
7937 GEN_SPEFPUOP_CONV_32_64(efdctsf);
7938 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7939 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7940 GEN_SPEFPUOP_CONV_64_32(efdcfs);
7941 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7942 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7943 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7944 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
7945
7946 /* Comparison */
7947 GEN_SPEFPUOP_COMP_64(efdcmpgt);
7948 GEN_SPEFPUOP_COMP_64(efdcmplt);
7949 GEN_SPEFPUOP_COMP_64(efdcmpeq);
7950 GEN_SPEFPUOP_COMP_64(efdtstgt);
7951 GEN_SPEFPUOP_COMP_64(efdtstlt);
7952 GEN_SPEFPUOP_COMP_64(efdtsteq);
7953
7954 /* Opcodes definitions */
7955 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
7956 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7957 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
7958 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
7959 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
7960 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7961 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
7962 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
7963 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7964 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7965 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7966 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7967 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7968 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7969 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
7970 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
7971
7972 static opcode_t opcodes[] = {
7973 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
7974 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
7975 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
7976 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
7977 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
7978 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
7979 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7980 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7981 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7982 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7983 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
7984 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
7985 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
7986 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
7987 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7988 #if defined(TARGET_PPC64)
7989 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
7990 #endif
7991 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
7992 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
7993 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7994 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7995 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7996 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
7997 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
7998 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
7999 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8000 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8001 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8002 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8003 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8004 #if defined(TARGET_PPC64)
8005 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8006 #endif
8007 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8008 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8009 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8010 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8011 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8012 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8013 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8014 #if defined(TARGET_PPC64)
8015 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8016 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8017 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8018 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8019 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8020 #endif
8021 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8022 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8023 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8024 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8025 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8026 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8027 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8028 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8029 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8030 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8031 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8032 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8033 #if defined(TARGET_PPC64)
8034 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8035 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8036 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8037 #endif
8038 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8039 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8040 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8041 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8042 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8043 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8044 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8045 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8046 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES),
8047 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8048 #if defined(TARGET_PPC64)
8049 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B),
8050 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8051 #endif
8052 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8053 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8054 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8055 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8056 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8057 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8058 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8059 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8060 #if defined(TARGET_PPC64)
8061 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8062 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8063 #endif
8064 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8065 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8066 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8067 #if defined(TARGET_PPC64)
8068 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8069 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8070 #endif
8071 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8072 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8073 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8074 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8075 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8076 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8077 #if defined(TARGET_PPC64)
8078 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8079 #endif
8080 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8081 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8082 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8083 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8084 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8085 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8086 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8087 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ),
8088 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT),
8089 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8090 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8091 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8092 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8093 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8094 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8095 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8096 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8097 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8098 #if defined(TARGET_PPC64)
8099 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8100 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8101 PPC_SEGMENT_64B),
8102 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8103 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8104 PPC_SEGMENT_64B),
8105 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B),
8106 #endif
8107 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8108 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8109 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8110 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8111 #if defined(TARGET_PPC64)
8112 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8113 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8114 #endif
8115 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8116 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8117 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8118 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8119 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8120 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8121 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8122 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8123 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8124 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8125 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8126 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8127 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8128 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8129 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8130 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8131 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8132 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8133 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8134 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8135 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8136 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8137 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8138 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8139 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8140 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8141 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8142 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8143 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8144 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8145 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8146 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8147 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8148 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8149 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8150 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8151 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8152 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8153 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8154 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8155 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8156 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8157 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8158 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8159 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8160 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8161 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8162 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8163 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8164 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8165 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8166 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8167 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8168 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8169 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8170 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8171 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8172 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8173 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8174 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8175 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8176 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8177 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8178 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8179 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8180 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8181 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8182 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8183 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8184 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8185 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8186 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE),
8187 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8188 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8189 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8190 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8191 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8192 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8193 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8194 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8195 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8196 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8197 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8198 GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE),
8199 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8200 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE),
8201 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8202 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8203 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8204 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8205 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8206 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8207 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8208 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8209 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8210 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8211
8212 #undef GEN_INT_ARITH_ADD
8213 #undef GEN_INT_ARITH_ADD_CONST
8214 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8215 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8216 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8217 add_ca, compute_ca, compute_ov) \
8218 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8219 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8220 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8221 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8222 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8223 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8224 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8225 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8226 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8227 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8228 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8229
8230 #undef GEN_INT_ARITH_DIVW
8231 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8232 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8233 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8234 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8235 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8236 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8237
8238 #if defined(TARGET_PPC64)
8239 #undef GEN_INT_ARITH_DIVD
8240 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8241 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8242 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8243 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8244 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8245 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8246
8247 #undef GEN_INT_ARITH_MUL_HELPER
8248 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8249 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8250 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8251 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8252 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8253 #endif
8254
8255 #undef GEN_INT_ARITH_SUBF
8256 #undef GEN_INT_ARITH_SUBF_CONST
8257 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8258 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8259 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8260 add_ca, compute_ca, compute_ov) \
8261 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8262 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8263 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8264 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8265 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8266 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8267 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8268 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8269 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8270 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8271 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8272
8273 #undef GEN_LOGICAL1
8274 #undef GEN_LOGICAL2
8275 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8276 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8277 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8278 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8279 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8280 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8281 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8282 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8283 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8284 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8285 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8286 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8287 #if defined(TARGET_PPC64)
8288 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8289 #endif
8290
8291 #if defined(TARGET_PPC64)
8292 #undef GEN_PPC64_R2
8293 #undef GEN_PPC64_R4
8294 #define GEN_PPC64_R2(name, opc1, opc2) \
8295 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8296 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8297 PPC_64B)
8298 #define GEN_PPC64_R4(name, opc1, opc2) \
8299 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8300 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8301 PPC_64B), \
8302 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8303 PPC_64B), \
8304 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8305 PPC_64B)
8306 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8307 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8308 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8309 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8310 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8311 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8312 #endif
8313
8314 #undef _GEN_FLOAT_ACB
8315 #undef GEN_FLOAT_ACB
8316 #undef _GEN_FLOAT_AB
8317 #undef GEN_FLOAT_AB
8318 #undef _GEN_FLOAT_AC
8319 #undef GEN_FLOAT_AC
8320 #undef GEN_FLOAT_B
8321 #undef GEN_FLOAT_BS
8322 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8323 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8324 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8325 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8326 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8327 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8328 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8329 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8330 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8331 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8332 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8333 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8334 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8335 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8336 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8337 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8338 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8339 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8340 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8341
8342 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8343 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8344 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8345 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8346 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8347 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8348 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8349 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8350 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8351 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8352 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8353 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8354 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8355 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8356 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8357 #if defined(TARGET_PPC64)
8358 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8359 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8360 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8361 #endif
8362 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8363 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8364 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8365 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8366 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8367 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8368 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8369
8370 #undef GEN_LD
8371 #undef GEN_LDU
8372 #undef GEN_LDUX
8373 #undef GEN_LDX
8374 #undef GEN_LDS
8375 #define GEN_LD(name, ldop, opc, type) \
8376 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8377 #define GEN_LDU(name, ldop, opc, type) \
8378 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8379 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8380 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8381 #define GEN_LDX(name, ldop, opc2, opc3, type) \
8382 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8383 #define GEN_LDS(name, ldop, op, type) \
8384 GEN_LD(name, ldop, op | 0x20, type) \
8385 GEN_LDU(name, ldop, op | 0x21, type) \
8386 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8387 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8388
8389 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8390 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8391 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8392 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8393 #if defined(TARGET_PPC64)
8394 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8395 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8396 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8397 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8398 #endif
8399 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8400 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8401
8402 #undef GEN_ST
8403 #undef GEN_STU
8404 #undef GEN_STUX
8405 #undef GEN_STX
8406 #undef GEN_STS
8407 #define GEN_ST(name, stop, opc, type) \
8408 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8409 #define GEN_STU(name, stop, opc, type) \
8410 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8411 #define GEN_STUX(name, stop, opc2, opc3, type) \
8412 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8413 #define GEN_STX(name, stop, opc2, opc3, type) \
8414 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8415 #define GEN_STS(name, stop, op, type) \
8416 GEN_ST(name, stop, op | 0x20, type) \
8417 GEN_STU(name, stop, op | 0x21, type) \
8418 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8419 GEN_STX(name, stop, 0x17, op | 0x00, type)
8420
8421 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8422 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8423 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8424 #if defined(TARGET_PPC64)
8425 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8426 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8427 #endif
8428 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8429 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8430
8431 #undef GEN_LDF
8432 #undef GEN_LDUF
8433 #undef GEN_LDUXF
8434 #undef GEN_LDXF
8435 #undef GEN_LDFS
8436 #define GEN_LDF(name, ldop, opc, type) \
8437 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8438 #define GEN_LDUF(name, ldop, opc, type) \
8439 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8440 #define GEN_LDUXF(name, ldop, opc, type) \
8441 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8442 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8443 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8444 #define GEN_LDFS(name, ldop, op, type) \
8445 GEN_LDF(name, ldop, op | 0x20, type) \
8446 GEN_LDUF(name, ldop, op | 0x21, type) \
8447 GEN_LDUXF(name, ldop, op | 0x01, type) \
8448 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8449
8450 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8451 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8452
8453 #undef GEN_STF
8454 #undef GEN_STUF
8455 #undef GEN_STUXF
8456 #undef GEN_STXF
8457 #undef GEN_STFS
8458 #define GEN_STF(name, stop, opc, type) \
8459 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8460 #define GEN_STUF(name, stop, opc, type) \
8461 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8462 #define GEN_STUXF(name, stop, opc, type) \
8463 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8464 #define GEN_STXF(name, stop, opc2, opc3, type) \
8465 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8466 #define GEN_STFS(name, stop, op, type) \
8467 GEN_STF(name, stop, op | 0x20, type) \
8468 GEN_STUF(name, stop, op | 0x21, type) \
8469 GEN_STUXF(name, stop, op | 0x01, type) \
8470 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8471
8472 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8473 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8474 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8475
8476 #undef GEN_CRLOGIC
8477 #define GEN_CRLOGIC(name, tcg_op, opc) \
8478 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8479 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8480 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8481 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8482 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8483 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8484 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8485 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8486 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8487
8488 #undef GEN_MAC_HANDLER
8489 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8490 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8491 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8492 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8493 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8494 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8495 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8496 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8497 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8498 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8499 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8500 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8501 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8502 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8503 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8504 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8505 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8506 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8507 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8508 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8509 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8510 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8511 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8512 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8513 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8514 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8515 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8516 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8517 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8518 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8519 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8520 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8521 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8522 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
8523 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
8524 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
8525 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
8526 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
8527 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
8528 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
8529 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
8530 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
8531 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
8532 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
8533
8534 #undef GEN_VR_LDX
8535 #undef GEN_VR_STX
8536 #undef GEN_VR_LVE
8537 #undef GEN_VR_STVE
8538 #define GEN_VR_LDX(name, opc2, opc3) \
8539 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8540 #define GEN_VR_STX(name, opc2, opc3) \
8541 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8542 #define GEN_VR_LVE(name, opc2, opc3) \
8543 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8544 #define GEN_VR_STVE(name, opc2, opc3) \
8545 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8546 GEN_VR_LDX(lvx, 0x07, 0x03),
8547 GEN_VR_LDX(lvxl, 0x07, 0x0B),
8548 GEN_VR_LVE(bx, 0x07, 0x00),
8549 GEN_VR_LVE(hx, 0x07, 0x01),
8550 GEN_VR_LVE(wx, 0x07, 0x02),
8551 GEN_VR_STX(svx, 0x07, 0x07),
8552 GEN_VR_STX(svxl, 0x07, 0x0F),
8553 GEN_VR_STVE(bx, 0x07, 0x04),
8554 GEN_VR_STVE(hx, 0x07, 0x05),
8555 GEN_VR_STVE(wx, 0x07, 0x06),
8556
8557 #undef GEN_VX_LOGICAL
8558 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
8559 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8560 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
8561 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
8562 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
8563 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
8564 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
8565
8566 #undef GEN_VXFORM
8567 #define GEN_VXFORM(name, opc2, opc3) \
8568 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8569 GEN_VXFORM(vaddubm, 0, 0),
8570 GEN_VXFORM(vadduhm, 0, 1),
8571 GEN_VXFORM(vadduwm, 0, 2),
8572 GEN_VXFORM(vsububm, 0, 16),
8573 GEN_VXFORM(vsubuhm, 0, 17),
8574 GEN_VXFORM(vsubuwm, 0, 18),
8575 GEN_VXFORM(vmaxub, 1, 0),
8576 GEN_VXFORM(vmaxuh, 1, 1),
8577 GEN_VXFORM(vmaxuw, 1, 2),
8578 GEN_VXFORM(vmaxsb, 1, 4),
8579 GEN_VXFORM(vmaxsh, 1, 5),
8580 GEN_VXFORM(vmaxsw, 1, 6),
8581 GEN_VXFORM(vminub, 1, 8),
8582 GEN_VXFORM(vminuh, 1, 9),
8583 GEN_VXFORM(vminuw, 1, 10),
8584 GEN_VXFORM(vminsb, 1, 12),
8585 GEN_VXFORM(vminsh, 1, 13),
8586 GEN_VXFORM(vminsw, 1, 14),
8587 GEN_VXFORM(vavgub, 1, 16),
8588 GEN_VXFORM(vavguh, 1, 17),
8589 GEN_VXFORM(vavguw, 1, 18),
8590 GEN_VXFORM(vavgsb, 1, 20),
8591 GEN_VXFORM(vavgsh, 1, 21),
8592 GEN_VXFORM(vavgsw, 1, 22),
8593 GEN_VXFORM(vmrghb, 6, 0),
8594 GEN_VXFORM(vmrghh, 6, 1),
8595 GEN_VXFORM(vmrghw, 6, 2),
8596 GEN_VXFORM(vmrglb, 6, 4),
8597 GEN_VXFORM(vmrglh, 6, 5),
8598 GEN_VXFORM(vmrglw, 6, 6),
8599 GEN_VXFORM(vmuloub, 4, 0),
8600 GEN_VXFORM(vmulouh, 4, 1),
8601 GEN_VXFORM(vmulosb, 4, 4),
8602 GEN_VXFORM(vmulosh, 4, 5),
8603 GEN_VXFORM(vmuleub, 4, 8),
8604 GEN_VXFORM(vmuleuh, 4, 9),
8605 GEN_VXFORM(vmulesb, 4, 12),
8606 GEN_VXFORM(vmulesh, 4, 13),
8607 GEN_VXFORM(vslb, 2, 4),
8608 GEN_VXFORM(vslh, 2, 5),
8609 GEN_VXFORM(vslw, 2, 6),
8610 GEN_VXFORM(vsrb, 2, 8),
8611 GEN_VXFORM(vsrh, 2, 9),
8612 GEN_VXFORM(vsrw, 2, 10),
8613 GEN_VXFORM(vsrab, 2, 12),
8614 GEN_VXFORM(vsrah, 2, 13),
8615 GEN_VXFORM(vsraw, 2, 14),
8616 GEN_VXFORM(vslo, 6, 16),
8617 GEN_VXFORM(vsro, 6, 17),
8618 GEN_VXFORM(vaddcuw, 0, 6),
8619 GEN_VXFORM(vsubcuw, 0, 22),
8620 GEN_VXFORM(vaddubs, 0, 8),
8621 GEN_VXFORM(vadduhs, 0, 9),
8622 GEN_VXFORM(vadduws, 0, 10),
8623 GEN_VXFORM(vaddsbs, 0, 12),
8624 GEN_VXFORM(vaddshs, 0, 13),
8625 GEN_VXFORM(vaddsws, 0, 14),
8626 GEN_VXFORM(vsububs, 0, 24),
8627 GEN_VXFORM(vsubuhs, 0, 25),
8628 GEN_VXFORM(vsubuws, 0, 26),
8629 GEN_VXFORM(vsubsbs, 0, 28),
8630 GEN_VXFORM(vsubshs, 0, 29),
8631 GEN_VXFORM(vsubsws, 0, 30),
8632 GEN_VXFORM(vrlb, 2, 0),
8633 GEN_VXFORM(vrlh, 2, 1),
8634 GEN_VXFORM(vrlw, 2, 2),
8635 GEN_VXFORM(vsl, 2, 7),
8636 GEN_VXFORM(vsr, 2, 11),
8637 GEN_VXFORM(vpkuhum, 7, 0),
8638 GEN_VXFORM(vpkuwum, 7, 1),
8639 GEN_VXFORM(vpkuhus, 7, 2),
8640 GEN_VXFORM(vpkuwus, 7, 3),
8641 GEN_VXFORM(vpkshus, 7, 4),
8642 GEN_VXFORM(vpkswus, 7, 5),
8643 GEN_VXFORM(vpkshss, 7, 6),
8644 GEN_VXFORM(vpkswss, 7, 7),
8645 GEN_VXFORM(vpkpx, 7, 12),
8646 GEN_VXFORM(vsum4ubs, 4, 24),
8647 GEN_VXFORM(vsum4sbs, 4, 28),
8648 GEN_VXFORM(vsum4shs, 4, 25),
8649 GEN_VXFORM(vsum2sws, 4, 26),
8650 GEN_VXFORM(vsumsws, 4, 30),
8651 GEN_VXFORM(vaddfp, 5, 0),
8652 GEN_VXFORM(vsubfp, 5, 1),
8653 GEN_VXFORM(vmaxfp, 5, 16),
8654 GEN_VXFORM(vminfp, 5, 17),
8655
8656 #undef GEN_VXRFORM1
8657 #undef GEN_VXRFORM
8658 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
8659 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
8660 #define GEN_VXRFORM(name, opc2, opc3) \
8661 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
8662 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
8663 GEN_VXRFORM(vcmpequb, 3, 0)
8664 GEN_VXRFORM(vcmpequh, 3, 1)
8665 GEN_VXRFORM(vcmpequw, 3, 2)
8666 GEN_VXRFORM(vcmpgtsb, 3, 12)
8667 GEN_VXRFORM(vcmpgtsh, 3, 13)
8668 GEN_VXRFORM(vcmpgtsw, 3, 14)
8669 GEN_VXRFORM(vcmpgtub, 3, 8)
8670 GEN_VXRFORM(vcmpgtuh, 3, 9)
8671 GEN_VXRFORM(vcmpgtuw, 3, 10)
8672 GEN_VXRFORM(vcmpeqfp, 3, 3)
8673 GEN_VXRFORM(vcmpgefp, 3, 7)
8674 GEN_VXRFORM(vcmpgtfp, 3, 11)
8675 GEN_VXRFORM(vcmpbfp, 3, 15)
8676
8677 #undef GEN_VXFORM_SIMM
8678 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
8679 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8680 GEN_VXFORM_SIMM(vspltisb, 6, 12),
8681 GEN_VXFORM_SIMM(vspltish, 6, 13),
8682 GEN_VXFORM_SIMM(vspltisw, 6, 14),
8683
8684 #undef GEN_VXFORM_NOA
8685 #define GEN_VXFORM_NOA(name, opc2, opc3) \
8686 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
8687 GEN_VXFORM_NOA(vupkhsb, 7, 8),
8688 GEN_VXFORM_NOA(vupkhsh, 7, 9),
8689 GEN_VXFORM_NOA(vupklsb, 7, 10),
8690 GEN_VXFORM_NOA(vupklsh, 7, 11),
8691 GEN_VXFORM_NOA(vupkhpx, 7, 13),
8692 GEN_VXFORM_NOA(vupklpx, 7, 15),
8693 GEN_VXFORM_NOA(vrefp, 5, 4),
8694 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
8695 GEN_VXFORM_NOA(vlogefp, 5, 7),
8696 GEN_VXFORM_NOA(vrfim, 5, 8),
8697 GEN_VXFORM_NOA(vrfin, 5, 9),
8698 GEN_VXFORM_NOA(vrfip, 5, 10),
8699 GEN_VXFORM_NOA(vrfiz, 5, 11),
8700
8701 #undef GEN_VXFORM_UIMM
8702 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
8703 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8704 GEN_VXFORM_UIMM(vspltb, 6, 8),
8705 GEN_VXFORM_UIMM(vsplth, 6, 9),
8706 GEN_VXFORM_UIMM(vspltw, 6, 10),
8707 GEN_VXFORM_UIMM(vcfux, 5, 12),
8708 GEN_VXFORM_UIMM(vcfsx, 5, 13),
8709 GEN_VXFORM_UIMM(vctuxs, 5, 14),
8710 GEN_VXFORM_UIMM(vctsxs, 5, 15),
8711
8712 #undef GEN_VAFORM_PAIRED
8713 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
8714 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
8715 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
8716 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
8717 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
8718 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
8719 GEN_VAFORM_PAIRED(vsel, vperm, 21),
8720 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
8721
8722 #undef GEN_SPE
8723 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
8724 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type)
8725 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE),
8726 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE),
8727 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE),
8728 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE),
8729 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE),
8730 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE),
8731 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE),
8732 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE),
8733 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE),
8734 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE),
8735 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE),
8736 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE),
8737 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE),
8738 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE),
8739 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE),
8740 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE),
8741 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE),
8742 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE),
8743 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE),
8744 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE),
8745 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE),
8746 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE),
8747 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE),
8748 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE),
8749 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE),
8750
8751 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE),
8752 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE),
8753 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE),
8754 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE),
8755 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE),
8756 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE),
8757 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE),
8758 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE),
8759 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE),
8760 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE),
8761 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE),
8762 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE),
8763 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE),
8764 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE),
8765
8766 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE),
8767 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE),
8768 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE),
8769 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE),
8770 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE),
8771 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE),
8772 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE),
8773 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE),
8774 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE),
8775 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE),
8776 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE),
8777 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE),
8778 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE),
8779 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE),
8780
8781 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE),
8782 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8783 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE),
8784 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE),
8785 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE),
8786 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8787 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
8788 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
8789 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8790 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8791 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8792 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8793 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8794 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8795 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
8796 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
8797
8798 #undef GEN_SPEOP_LDST
8799 #define GEN_SPEOP_LDST(name, opc2, sh) \
8800 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
8801 GEN_SPEOP_LDST(evldd, 0x00, 3),
8802 GEN_SPEOP_LDST(evldw, 0x01, 3),
8803 GEN_SPEOP_LDST(evldh, 0x02, 3),
8804 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
8805 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
8806 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
8807 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
8808 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
8809 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
8810 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
8811 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
8812
8813 GEN_SPEOP_LDST(evstdd, 0x10, 3),
8814 GEN_SPEOP_LDST(evstdw, 0x11, 3),
8815 GEN_SPEOP_LDST(evstdh, 0x12, 3),
8816 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
8817 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
8818 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
8819 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
8820 };
8821
8822 #include "translate_init.c"
8823 #include "helper_regs.h"
8824
8825 /*****************************************************************************/
8826 /* Misc PowerPC helpers */
8827 void cpu_dump_state (CPUState *env, FILE *f,
8828 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8829 int flags)
8830 {
8831 #define RGPL 4
8832 #define RFPL 4
8833
8834 int i;
8835
8836 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
8837 env->nip, env->lr, env->ctr, env->xer);
8838 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8839 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
8840 #if !defined(NO_TIMER_DUMP)
8841 cpu_fprintf(f, "TB %08x %08x "
8842 #if !defined(CONFIG_USER_ONLY)
8843 "DECR %08x"
8844 #endif
8845 "\n",
8846 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8847 #if !defined(CONFIG_USER_ONLY)
8848 , cpu_ppc_load_decr(env)
8849 #endif
8850 );
8851 #endif
8852 for (i = 0; i < 32; i++) {
8853 if ((i & (RGPL - 1)) == 0)
8854 cpu_fprintf(f, "GPR%02d", i);
8855 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
8856 if ((i & (RGPL - 1)) == (RGPL - 1))
8857 cpu_fprintf(f, "\n");
8858 }
8859 cpu_fprintf(f, "CR ");
8860 for (i = 0; i < 8; i++)
8861 cpu_fprintf(f, "%01x", env->crf[i]);
8862 cpu_fprintf(f, " [");
8863 for (i = 0; i < 8; i++) {
8864 char a = '-';
8865 if (env->crf[i] & 0x08)
8866 a = 'L';
8867 else if (env->crf[i] & 0x04)
8868 a = 'G';
8869 else if (env->crf[i] & 0x02)
8870 a = 'E';
8871 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8872 }
8873 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve_addr);
8874 for (i = 0; i < 32; i++) {
8875 if ((i & (RFPL - 1)) == 0)
8876 cpu_fprintf(f, "FPR%02d", i);
8877 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
8878 if ((i & (RFPL - 1)) == (RFPL - 1))
8879 cpu_fprintf(f, "\n");
8880 }
8881 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
8882 #if !defined(CONFIG_USER_ONLY)
8883 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
8884 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
8885 #endif
8886
8887 #undef RGPL
8888 #undef RFPL
8889 }
8890
8891 void cpu_dump_statistics (CPUState *env, FILE*f,
8892 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8893 int flags)
8894 {
8895 #if defined(DO_PPC_STATISTICS)
8896 opc_handler_t **t1, **t2, **t3, *handler;
8897 int op1, op2, op3;
8898
8899 t1 = env->opcodes;
8900 for (op1 = 0; op1 < 64; op1++) {
8901 handler = t1[op1];
8902 if (is_indirect_opcode(handler)) {
8903 t2 = ind_table(handler);
8904 for (op2 = 0; op2 < 32; op2++) {
8905 handler = t2[op2];
8906 if (is_indirect_opcode(handler)) {
8907 t3 = ind_table(handler);
8908 for (op3 = 0; op3 < 32; op3++) {
8909 handler = t3[op3];
8910 if (handler->count == 0)
8911 continue;
8912 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8913 "%016llx %lld\n",
8914 op1, op2, op3, op1, (op3 << 5) | op2,
8915 handler->oname,
8916 handler->count, handler->count);
8917 }
8918 } else {
8919 if (handler->count == 0)
8920 continue;
8921 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8922 "%016llx %lld\n",
8923 op1, op2, op1, op2, handler->oname,
8924 handler->count, handler->count);
8925 }
8926 }
8927 } else {
8928 if (handler->count == 0)
8929 continue;
8930 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8931 op1, op1, handler->oname,
8932 handler->count, handler->count);
8933 }
8934 }
8935 #endif
8936 }
8937
8938 /*****************************************************************************/
8939 static always_inline void gen_intermediate_code_internal (CPUState *env,
8940 TranslationBlock *tb,
8941 int search_pc)
8942 {
8943 DisasContext ctx, *ctxp = &ctx;
8944 opc_handler_t **table, *handler;
8945 target_ulong pc_start;
8946 uint16_t *gen_opc_end;
8947 CPUBreakpoint *bp;
8948 int j, lj = -1;
8949 int num_insns;
8950 int max_insns;
8951
8952 pc_start = tb->pc;
8953 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
8954 ctx.nip = pc_start;
8955 ctx.tb = tb;
8956 ctx.exception = POWERPC_EXCP_NONE;
8957 ctx.spr_cb = env->spr_cb;
8958 ctx.mem_idx = env->mmu_idx;
8959 ctx.access_type = -1;
8960 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
8961 #if defined(TARGET_PPC64)
8962 ctx.sf_mode = msr_sf;
8963 #endif
8964 ctx.fpu_enabled = msr_fp;
8965 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
8966 ctx.spe_enabled = msr_spe;
8967 else
8968 ctx.spe_enabled = 0;
8969 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8970 ctx.altivec_enabled = msr_vr;
8971 else
8972 ctx.altivec_enabled = 0;
8973 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8974 ctx.singlestep_enabled = CPU_SINGLE_STEP;
8975 else
8976 ctx.singlestep_enabled = 0;
8977 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8978 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8979 if (unlikely(env->singlestep_enabled))
8980 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
8981 #if defined (DO_SINGLE_STEP) && 0
8982 /* Single step trace mode */
8983 msr_se = 1;
8984 #endif
8985 num_insns = 0;
8986 max_insns = tb->cflags & CF_COUNT_MASK;
8987 if (max_insns == 0)
8988 max_insns = CF_COUNT_MASK;
8989
8990 gen_icount_start();
8991 /* Set env in case of segfault during code fetch */
8992 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
8993 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8994 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
8995 if (bp->pc == ctx.nip) {
8996 gen_debug_exception(ctxp);
8997 break;
8998 }
8999 }
9000 }
9001 if (unlikely(search_pc)) {
9002 j = gen_opc_ptr - gen_opc_buf;
9003 if (lj < j) {
9004 lj++;
9005 while (lj < j)
9006 gen_opc_instr_start[lj++] = 0;
9007 }
9008 gen_opc_pc[lj] = ctx.nip;
9009 gen_opc_instr_start[lj] = 1;
9010 gen_opc_icount[lj] = num_insns;
9011 }
9012 LOG_DISAS("----------------\n");
9013 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
9014 ctx.nip, ctx.mem_idx, (int)msr_ir);
9015 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9016 gen_io_start();
9017 if (unlikely(ctx.le_mode)) {
9018 ctx.opcode = bswap32(ldl_code(ctx.nip));
9019 } else {
9020 ctx.opcode = ldl_code(ctx.nip);
9021 }
9022 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9023 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9024 opc3(ctx.opcode), little_endian ? "little" : "big");
9025 ctx.nip += 4;
9026 table = env->opcodes;
9027 num_insns++;
9028 handler = table[opc1(ctx.opcode)];
9029 if (is_indirect_opcode(handler)) {
9030 table = ind_table(handler);
9031 handler = table[opc2(ctx.opcode)];
9032 if (is_indirect_opcode(handler)) {
9033 table = ind_table(handler);
9034 handler = table[opc3(ctx.opcode)];
9035 }
9036 }
9037 /* Is opcode *REALLY* valid ? */
9038 if (unlikely(handler->handler == &gen_invalid)) {
9039 if (qemu_log_enabled()) {
9040 qemu_log("invalid/unsupported opcode: "
9041 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
9042 opc1(ctx.opcode), opc2(ctx.opcode),
9043 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9044 } else {
9045 printf("invalid/unsupported opcode: "
9046 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
9047 opc1(ctx.opcode), opc2(ctx.opcode),
9048 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9049 }
9050 } else {
9051 if (unlikely((ctx.opcode & handler->inval) != 0)) {
9052 if (qemu_log_enabled()) {
9053 qemu_log("invalid bits: %08x for opcode: "
9054 "%02x - %02x - %02x (%08x) " ADDRX "\n",
9055 ctx.opcode & handler->inval, opc1(ctx.opcode),
9056 opc2(ctx.opcode), opc3(ctx.opcode),
9057 ctx.opcode, ctx.nip - 4);
9058 } else {
9059 printf("invalid bits: %08x for opcode: "
9060 "%02x - %02x - %02x (%08x) " ADDRX "\n",
9061 ctx.opcode & handler->inval, opc1(ctx.opcode),
9062 opc2(ctx.opcode), opc3(ctx.opcode),
9063 ctx.opcode, ctx.nip - 4);
9064 }
9065 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9066 break;
9067 }
9068 }
9069 (*(handler->handler))(&ctx);
9070 #if defined(DO_PPC_STATISTICS)
9071 handler->count++;
9072 #endif
9073 /* Check trace mode exceptions */
9074 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9075 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9076 ctx.exception != POWERPC_SYSCALL &&
9077 ctx.exception != POWERPC_EXCP_TRAP &&
9078 ctx.exception != POWERPC_EXCP_BRANCH)) {
9079 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9080 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9081 (env->singlestep_enabled) ||
9082 singlestep ||
9083 num_insns >= max_insns)) {
9084 /* if we reach a page boundary or are single stepping, stop
9085 * generation
9086 */
9087 break;
9088 }
9089 }
9090 if (tb->cflags & CF_LAST_IO)
9091 gen_io_end();
9092 if (ctx.exception == POWERPC_EXCP_NONE) {
9093 gen_goto_tb(&ctx, 0, ctx.nip);
9094 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9095 if (unlikely(env->singlestep_enabled)) {
9096 gen_debug_exception(ctxp);
9097 }
9098 /* Generate the return instruction */
9099 tcg_gen_exit_tb(0);
9100 }
9101 gen_icount_end(tb, num_insns);
9102 *gen_opc_ptr = INDEX_op_end;
9103 if (unlikely(search_pc)) {
9104 j = gen_opc_ptr - gen_opc_buf;
9105 lj++;
9106 while (lj <= j)
9107 gen_opc_instr_start[lj++] = 0;
9108 } else {
9109 tb->size = ctx.nip - pc_start;
9110 tb->icount = num_insns;
9111 }
9112 #if defined(DEBUG_DISAS)
9113 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
9114 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
9115 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9116 int flags;
9117 flags = env->bfd_mach;
9118 flags |= ctx.le_mode << 16;
9119 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9120 log_target_disas(pc_start, ctx.nip - pc_start, flags);
9121 qemu_log("\n");
9122 }
9123 #endif
9124 }
9125
9126 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
9127 {
9128 gen_intermediate_code_internal(env, tb, 0);
9129 }
9130
9131 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
9132 {
9133 gen_intermediate_code_internal(env, tb, 1);
9134 }
9135
9136 void gen_pc_load(CPUState *env, TranslationBlock *tb,
9137 unsigned long searched_pc, int pc_pos, void *puc)
9138 {
9139 env->nip = gen_opc_pc[pc_pos];
9140 }
Qemu copy for testing