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target-ppc: Use mul*2 in mulh* insns
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161
162 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, reserve_addr),
164 "reserve_addr");
165
166 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, fpscr), "fpscr");
168
169 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
170 offsetof(CPUPPCState, access_type), "access_type");
171
172 /* register helpers */
173 #define GEN_HELPER 2
174 #include "helper.h"
175
176 done_init = 1;
177 }
178
179 /* internal defines */
180 typedef struct DisasContext {
181 struct TranslationBlock *tb;
182 target_ulong nip;
183 uint32_t opcode;
184 uint32_t exception;
185 /* Routine used to access memory */
186 int mem_idx;
187 int access_type;
188 /* Translation flags */
189 int le_mode;
190 #if defined(TARGET_PPC64)
191 int sf_mode;
192 int has_cfar;
193 #endif
194 int fpu_enabled;
195 int altivec_enabled;
196 int spe_enabled;
197 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
198 int singlestep_enabled;
199 } DisasContext;
200
201 struct opc_handler_t {
202 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
203 uint32_t inval1;
204 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
205 uint32_t inval2;
206 /* instruction type */
207 uint64_t type;
208 /* extended instruction type */
209 uint64_t type2;
210 /* handler */
211 void (*handler)(DisasContext *ctx);
212 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
213 const char *oname;
214 #endif
215 #if defined(DO_PPC_STATISTICS)
216 uint64_t count;
217 #endif
218 };
219
220 static inline void gen_reset_fpstatus(void)
221 {
222 gen_helper_reset_fpstatus(cpu_env);
223 }
224
225 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
226 {
227 TCGv_i32 t0 = tcg_temp_new_i32();
228
229 if (set_fprf != 0) {
230 /* This case might be optimized later */
231 tcg_gen_movi_i32(t0, 1);
232 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
233 if (unlikely(set_rc)) {
234 tcg_gen_mov_i32(cpu_crf[1], t0);
235 }
236 gen_helper_float_check_status(cpu_env);
237 } else if (unlikely(set_rc)) {
238 /* We always need to compute fpcc */
239 tcg_gen_movi_i32(t0, 0);
240 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
241 tcg_gen_mov_i32(cpu_crf[1], t0);
242 }
243
244 tcg_temp_free_i32(t0);
245 }
246
247 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
248 {
249 if (ctx->access_type != access_type) {
250 tcg_gen_movi_i32(cpu_access_type, access_type);
251 ctx->access_type = access_type;
252 }
253 }
254
255 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
256 {
257 #if defined(TARGET_PPC64)
258 if (ctx->sf_mode)
259 tcg_gen_movi_tl(cpu_nip, nip);
260 else
261 #endif
262 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
263 }
264
265 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
266 {
267 TCGv_i32 t0, t1;
268 if (ctx->exception == POWERPC_EXCP_NONE) {
269 gen_update_nip(ctx, ctx->nip);
270 }
271 t0 = tcg_const_i32(excp);
272 t1 = tcg_const_i32(error);
273 gen_helper_raise_exception_err(cpu_env, t0, t1);
274 tcg_temp_free_i32(t0);
275 tcg_temp_free_i32(t1);
276 ctx->exception = (excp);
277 }
278
279 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
280 {
281 TCGv_i32 t0;
282 if (ctx->exception == POWERPC_EXCP_NONE) {
283 gen_update_nip(ctx, ctx->nip);
284 }
285 t0 = tcg_const_i32(excp);
286 gen_helper_raise_exception(cpu_env, t0);
287 tcg_temp_free_i32(t0);
288 ctx->exception = (excp);
289 }
290
291 static inline void gen_debug_exception(DisasContext *ctx)
292 {
293 TCGv_i32 t0;
294
295 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
296 (ctx->exception != POWERPC_EXCP_SYNC)) {
297 gen_update_nip(ctx, ctx->nip);
298 }
299 t0 = tcg_const_i32(EXCP_DEBUG);
300 gen_helper_raise_exception(cpu_env, t0);
301 tcg_temp_free_i32(t0);
302 }
303
304 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
305 {
306 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
307 }
308
309 /* Stop translation */
310 static inline void gen_stop_exception(DisasContext *ctx)
311 {
312 gen_update_nip(ctx, ctx->nip);
313 ctx->exception = POWERPC_EXCP_STOP;
314 }
315
316 /* No need to update nip here, as execution flow will change */
317 static inline void gen_sync_exception(DisasContext *ctx)
318 {
319 ctx->exception = POWERPC_EXCP_SYNC;
320 }
321
322 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
323 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
324
325 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
326 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
327
328 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
333
334 typedef struct opcode_t {
335 unsigned char opc1, opc2, opc3;
336 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
337 unsigned char pad[5];
338 #else
339 unsigned char pad[1];
340 #endif
341 opc_handler_t handler;
342 const char *oname;
343 } opcode_t;
344
345 /*****************************************************************************/
346 /*** Instruction decoding ***/
347 #define EXTRACT_HELPER(name, shift, nb) \
348 static inline uint32_t name(uint32_t opcode) \
349 { \
350 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
351 }
352
353 #define EXTRACT_SHELPER(name, shift, nb) \
354 static inline int32_t name(uint32_t opcode) \
355 { \
356 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
357 }
358
359 /* Opcode part 1 */
360 EXTRACT_HELPER(opc1, 26, 6);
361 /* Opcode part 2 */
362 EXTRACT_HELPER(opc2, 1, 5);
363 /* Opcode part 3 */
364 EXTRACT_HELPER(opc3, 6, 5);
365 /* Update Cr0 flags */
366 EXTRACT_HELPER(Rc, 0, 1);
367 /* Destination */
368 EXTRACT_HELPER(rD, 21, 5);
369 /* Source */
370 EXTRACT_HELPER(rS, 21, 5);
371 /* First operand */
372 EXTRACT_HELPER(rA, 16, 5);
373 /* Second operand */
374 EXTRACT_HELPER(rB, 11, 5);
375 /* Third operand */
376 EXTRACT_HELPER(rC, 6, 5);
377 /*** Get CRn ***/
378 EXTRACT_HELPER(crfD, 23, 3);
379 EXTRACT_HELPER(crfS, 18, 3);
380 EXTRACT_HELPER(crbD, 21, 5);
381 EXTRACT_HELPER(crbA, 16, 5);
382 EXTRACT_HELPER(crbB, 11, 5);
383 /* SPR / TBL */
384 EXTRACT_HELPER(_SPR, 11, 10);
385 static inline uint32_t SPR(uint32_t opcode)
386 {
387 uint32_t sprn = _SPR(opcode);
388
389 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
390 }
391 /*** Get constants ***/
392 EXTRACT_HELPER(IMM, 12, 8);
393 /* 16 bits signed immediate value */
394 EXTRACT_SHELPER(SIMM, 0, 16);
395 /* 16 bits unsigned immediate value */
396 EXTRACT_HELPER(UIMM, 0, 16);
397 /* 5 bits signed immediate value */
398 EXTRACT_HELPER(SIMM5, 16, 5);
399 /* 5 bits signed immediate value */
400 EXTRACT_HELPER(UIMM5, 16, 5);
401 /* Bit count */
402 EXTRACT_HELPER(NB, 11, 5);
403 /* Shift count */
404 EXTRACT_HELPER(SH, 11, 5);
405 /* Vector shift count */
406 EXTRACT_HELPER(VSH, 6, 4);
407 /* Mask start */
408 EXTRACT_HELPER(MB, 6, 5);
409 /* Mask end */
410 EXTRACT_HELPER(ME, 1, 5);
411 /* Trap operand */
412 EXTRACT_HELPER(TO, 21, 5);
413
414 EXTRACT_HELPER(CRM, 12, 8);
415 EXTRACT_HELPER(FM, 17, 8);
416 EXTRACT_HELPER(SR, 16, 4);
417 EXTRACT_HELPER(FPIMM, 12, 4);
418
419 /*** Jump target decoding ***/
420 /* Displacement */
421 EXTRACT_SHELPER(d, 0, 16);
422 /* Immediate address */
423 static inline target_ulong LI(uint32_t opcode)
424 {
425 return (opcode >> 0) & 0x03FFFFFC;
426 }
427
428 static inline uint32_t BD(uint32_t opcode)
429 {
430 return (opcode >> 0) & 0xFFFC;
431 }
432
433 EXTRACT_HELPER(BO, 21, 5);
434 EXTRACT_HELPER(BI, 16, 5);
435 /* Absolute/relative address */
436 EXTRACT_HELPER(AA, 1, 1);
437 /* Link */
438 EXTRACT_HELPER(LK, 0, 1);
439
440 /* Create a mask between <start> and <end> bits */
441 static inline target_ulong MASK(uint32_t start, uint32_t end)
442 {
443 target_ulong ret;
444
445 #if defined(TARGET_PPC64)
446 if (likely(start == 0)) {
447 ret = UINT64_MAX << (63 - end);
448 } else if (likely(end == 63)) {
449 ret = UINT64_MAX >> start;
450 }
451 #else
452 if (likely(start == 0)) {
453 ret = UINT32_MAX << (31 - end);
454 } else if (likely(end == 31)) {
455 ret = UINT32_MAX >> start;
456 }
457 #endif
458 else {
459 ret = (((target_ulong)(-1ULL)) >> (start)) ^
460 (((target_ulong)(-1ULL) >> (end)) >> 1);
461 if (unlikely(start > end))
462 return ~ret;
463 }
464
465 return ret;
466 }
467
468 /*****************************************************************************/
469 /* PowerPC instructions table */
470
471 #if defined(DO_PPC_STATISTICS)
472 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
473 { \
474 .opc1 = op1, \
475 .opc2 = op2, \
476 .opc3 = op3, \
477 .pad = { 0, }, \
478 .handler = { \
479 .inval1 = invl, \
480 .type = _typ, \
481 .type2 = _typ2, \
482 .handler = &gen_##name, \
483 .oname = stringify(name), \
484 }, \
485 .oname = stringify(name), \
486 }
487 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
488 { \
489 .opc1 = op1, \
490 .opc2 = op2, \
491 .opc3 = op3, \
492 .pad = { 0, }, \
493 .handler = { \
494 .inval1 = invl1, \
495 .inval2 = invl2, \
496 .type = _typ, \
497 .type2 = _typ2, \
498 .handler = &gen_##name, \
499 .oname = stringify(name), \
500 }, \
501 .oname = stringify(name), \
502 }
503 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
504 { \
505 .opc1 = op1, \
506 .opc2 = op2, \
507 .opc3 = op3, \
508 .pad = { 0, }, \
509 .handler = { \
510 .inval1 = invl, \
511 .type = _typ, \
512 .type2 = _typ2, \
513 .handler = &gen_##name, \
514 .oname = onam, \
515 }, \
516 .oname = onam, \
517 }
518 #else
519 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
520 { \
521 .opc1 = op1, \
522 .opc2 = op2, \
523 .opc3 = op3, \
524 .pad = { 0, }, \
525 .handler = { \
526 .inval1 = invl, \
527 .type = _typ, \
528 .type2 = _typ2, \
529 .handler = &gen_##name, \
530 }, \
531 .oname = stringify(name), \
532 }
533 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
534 { \
535 .opc1 = op1, \
536 .opc2 = op2, \
537 .opc3 = op3, \
538 .pad = { 0, }, \
539 .handler = { \
540 .inval1 = invl1, \
541 .inval2 = invl2, \
542 .type = _typ, \
543 .type2 = _typ2, \
544 .handler = &gen_##name, \
545 }, \
546 .oname = stringify(name), \
547 }
548 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
549 { \
550 .opc1 = op1, \
551 .opc2 = op2, \
552 .opc3 = op3, \
553 .pad = { 0, }, \
554 .handler = { \
555 .inval1 = invl, \
556 .type = _typ, \
557 .type2 = _typ2, \
558 .handler = &gen_##name, \
559 }, \
560 .oname = onam, \
561 }
562 #endif
563
564 /* SPR load/store helpers */
565 static inline void gen_load_spr(TCGv t, int reg)
566 {
567 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
568 }
569
570 static inline void gen_store_spr(int reg, TCGv t)
571 {
572 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
573 }
574
575 /* Invalid instruction */
576 static void gen_invalid(DisasContext *ctx)
577 {
578 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
579 }
580
581 static opc_handler_t invalid_handler = {
582 .inval1 = 0xFFFFFFFF,
583 .inval2 = 0xFFFFFFFF,
584 .type = PPC_NONE,
585 .type2 = PPC_NONE,
586 .handler = gen_invalid,
587 };
588
589 /*** Integer comparison ***/
590
591 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
592 {
593 int l1, l2, l3;
594
595 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
596 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
597 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
598
599 l1 = gen_new_label();
600 l2 = gen_new_label();
601 l3 = gen_new_label();
602 if (s) {
603 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
604 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
605 } else {
606 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
607 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
608 }
609 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
610 tcg_gen_br(l3);
611 gen_set_label(l1);
612 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
613 tcg_gen_br(l3);
614 gen_set_label(l2);
615 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
616 gen_set_label(l3);
617 }
618
619 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
620 {
621 TCGv t0 = tcg_const_local_tl(arg1);
622 gen_op_cmp(arg0, t0, s, crf);
623 tcg_temp_free(t0);
624 }
625
626 #if defined(TARGET_PPC64)
627 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
628 {
629 TCGv t0, t1;
630 t0 = tcg_temp_local_new();
631 t1 = tcg_temp_local_new();
632 if (s) {
633 tcg_gen_ext32s_tl(t0, arg0);
634 tcg_gen_ext32s_tl(t1, arg1);
635 } else {
636 tcg_gen_ext32u_tl(t0, arg0);
637 tcg_gen_ext32u_tl(t1, arg1);
638 }
639 gen_op_cmp(t0, t1, s, crf);
640 tcg_temp_free(t1);
641 tcg_temp_free(t0);
642 }
643
644 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
645 {
646 TCGv t0 = tcg_const_local_tl(arg1);
647 gen_op_cmp32(arg0, t0, s, crf);
648 tcg_temp_free(t0);
649 }
650 #endif
651
652 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
653 {
654 #if defined(TARGET_PPC64)
655 if (!(ctx->sf_mode))
656 gen_op_cmpi32(reg, 0, 1, 0);
657 else
658 #endif
659 gen_op_cmpi(reg, 0, 1, 0);
660 }
661
662 /* cmp */
663 static void gen_cmp(DisasContext *ctx)
664 {
665 #if defined(TARGET_PPC64)
666 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
667 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
668 1, crfD(ctx->opcode));
669 else
670 #endif
671 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 }
674
675 /* cmpi */
676 static void gen_cmpi(DisasContext *ctx)
677 {
678 #if defined(TARGET_PPC64)
679 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
680 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
681 1, crfD(ctx->opcode));
682 else
683 #endif
684 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 }
687
688 /* cmpl */
689 static void gen_cmpl(DisasContext *ctx)
690 {
691 #if defined(TARGET_PPC64)
692 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
693 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
694 0, crfD(ctx->opcode));
695 else
696 #endif
697 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 }
700
701 /* cmpli */
702 static void gen_cmpli(DisasContext *ctx)
703 {
704 #if defined(TARGET_PPC64)
705 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
706 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
707 0, crfD(ctx->opcode));
708 else
709 #endif
710 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712 }
713
714 /* isel (PowerPC 2.03 specification) */
715 static void gen_isel(DisasContext *ctx)
716 {
717 int l1, l2;
718 uint32_t bi = rC(ctx->opcode);
719 uint32_t mask;
720 TCGv_i32 t0;
721
722 l1 = gen_new_label();
723 l2 = gen_new_label();
724
725 mask = 1 << (3 - (bi & 0x03));
726 t0 = tcg_temp_new_i32();
727 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
728 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
729 if (rA(ctx->opcode) == 0)
730 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
731 else
732 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
733 tcg_gen_br(l2);
734 gen_set_label(l1);
735 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
736 gen_set_label(l2);
737 tcg_temp_free_i32(t0);
738 }
739
740 /*** Integer arithmetic ***/
741
742 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
743 TCGv arg1, TCGv arg2, int sub)
744 {
745 int l1;
746 TCGv t0;
747
748 l1 = gen_new_label();
749 /* Start with XER OV disabled, the most likely case */
750 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
751 t0 = tcg_temp_local_new();
752 tcg_gen_xor_tl(t0, arg0, arg1);
753 #if defined(TARGET_PPC64)
754 if (!ctx->sf_mode)
755 tcg_gen_ext32s_tl(t0, t0);
756 #endif
757 if (sub)
758 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
759 else
760 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
761 tcg_gen_xor_tl(t0, arg1, arg2);
762 #if defined(TARGET_PPC64)
763 if (!ctx->sf_mode)
764 tcg_gen_ext32s_tl(t0, t0);
765 #endif
766 if (sub)
767 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
768 else
769 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
770 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
771 gen_set_label(l1);
772 tcg_temp_free(t0);
773 }
774
775 static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
776 TCGv arg2, int sub)
777 {
778 int l1 = gen_new_label();
779
780 #if defined(TARGET_PPC64)
781 if (!(ctx->sf_mode)) {
782 TCGv t0, t1;
783 t0 = tcg_temp_new();
784 t1 = tcg_temp_new();
785
786 tcg_gen_ext32u_tl(t0, arg1);
787 tcg_gen_ext32u_tl(t1, arg2);
788 if (sub) {
789 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
790 } else {
791 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
792 }
793 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
794 gen_set_label(l1);
795 tcg_temp_free(t0);
796 tcg_temp_free(t1);
797 } else
798 #endif
799 {
800 if (sub) {
801 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
802 } else {
803 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
804 }
805 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
806 gen_set_label(l1);
807 }
808 }
809
810 /* Common add function */
811 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
812 TCGv arg2, int add_ca, int compute_ca,
813 int compute_ov)
814 {
815 TCGv t0, t1;
816
817 if ((!compute_ca && !compute_ov) ||
818 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
819 t0 = ret;
820 } else {
821 t0 = tcg_temp_local_new();
822 }
823
824 if (add_ca) {
825 t1 = tcg_temp_local_new();
826 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
827 tcg_gen_shri_tl(t1, t1, XER_CA);
828 } else {
829 TCGV_UNUSED(t1);
830 }
831
832 if (compute_ca && compute_ov) {
833 /* Start with XER CA and OV disabled, the most likely case */
834 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
835 } else if (compute_ca) {
836 /* Start with XER CA disabled, the most likely case */
837 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
838 } else if (compute_ov) {
839 /* Start with XER OV disabled, the most likely case */
840 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
841 }
842
843 tcg_gen_add_tl(t0, arg1, arg2);
844
845 if (compute_ca) {
846 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
847 }
848 if (add_ca) {
849 tcg_gen_add_tl(t0, t0, t1);
850 gen_op_arith_compute_ca(ctx, t0, t1, 0);
851 tcg_temp_free(t1);
852 }
853 if (compute_ov) {
854 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
855 }
856
857 if (unlikely(Rc(ctx->opcode) != 0))
858 gen_set_Rc0(ctx, t0);
859
860 if (!TCGV_EQUAL(t0, ret)) {
861 tcg_gen_mov_tl(ret, t0);
862 tcg_temp_free(t0);
863 }
864 }
865 /* Add functions with two operands */
866 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
867 static void glue(gen_, name)(DisasContext *ctx) \
868 { \
869 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
870 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
871 add_ca, compute_ca, compute_ov); \
872 }
873 /* Add functions with one operand and one immediate */
874 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
875 add_ca, compute_ca, compute_ov) \
876 static void glue(gen_, name)(DisasContext *ctx) \
877 { \
878 TCGv t0 = tcg_const_local_tl(const_val); \
879 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
880 cpu_gpr[rA(ctx->opcode)], t0, \
881 add_ca, compute_ca, compute_ov); \
882 tcg_temp_free(t0); \
883 }
884
885 /* add add. addo addo. */
886 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
887 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
888 /* addc addc. addco addco. */
889 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
890 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
891 /* adde adde. addeo addeo. */
892 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
893 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
894 /* addme addme. addmeo addmeo. */
895 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
896 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
897 /* addze addze. addzeo addzeo.*/
898 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
899 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
900 /* addi */
901 static void gen_addi(DisasContext *ctx)
902 {
903 target_long simm = SIMM(ctx->opcode);
904
905 if (rA(ctx->opcode) == 0) {
906 /* li case */
907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
908 } else {
909 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
910 }
911 }
912 /* addic addic.*/
913 static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
914 int compute_Rc0)
915 {
916 target_long simm = SIMM(ctx->opcode);
917
918 /* Start with XER CA and OV disabled, the most likely case */
919 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
920
921 if (likely(simm != 0)) {
922 TCGv t0 = tcg_temp_local_new();
923 tcg_gen_addi_tl(t0, arg1, simm);
924 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
925 tcg_gen_mov_tl(ret, t0);
926 tcg_temp_free(t0);
927 } else {
928 tcg_gen_mov_tl(ret, arg1);
929 }
930 if (compute_Rc0) {
931 gen_set_Rc0(ctx, ret);
932 }
933 }
934
935 static void gen_addic(DisasContext *ctx)
936 {
937 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
938 }
939
940 static void gen_addic_(DisasContext *ctx)
941 {
942 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
943 }
944
945 /* addis */
946 static void gen_addis(DisasContext *ctx)
947 {
948 target_long simm = SIMM(ctx->opcode);
949
950 if (rA(ctx->opcode) == 0) {
951 /* lis case */
952 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
953 } else {
954 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
955 }
956 }
957
958 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
959 TCGv arg2, int sign, int compute_ov)
960 {
961 int l1 = gen_new_label();
962 int l2 = gen_new_label();
963 TCGv_i32 t0 = tcg_temp_local_new_i32();
964 TCGv_i32 t1 = tcg_temp_local_new_i32();
965
966 tcg_gen_trunc_tl_i32(t0, arg1);
967 tcg_gen_trunc_tl_i32(t1, arg2);
968 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
969 if (sign) {
970 int l3 = gen_new_label();
971 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
972 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
973 gen_set_label(l3);
974 tcg_gen_div_i32(t0, t0, t1);
975 } else {
976 tcg_gen_divu_i32(t0, t0, t1);
977 }
978 if (compute_ov) {
979 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
980 }
981 tcg_gen_br(l2);
982 gen_set_label(l1);
983 if (sign) {
984 tcg_gen_sari_i32(t0, t0, 31);
985 } else {
986 tcg_gen_movi_i32(t0, 0);
987 }
988 if (compute_ov) {
989 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
990 }
991 gen_set_label(l2);
992 tcg_gen_extu_i32_tl(ret, t0);
993 tcg_temp_free_i32(t0);
994 tcg_temp_free_i32(t1);
995 if (unlikely(Rc(ctx->opcode) != 0))
996 gen_set_Rc0(ctx, ret);
997 }
998 /* Div functions */
999 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1000 static void glue(gen_, name)(DisasContext *ctx) \
1001 { \
1002 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1004 sign, compute_ov); \
1005 }
1006 /* divwu divwu. divwuo divwuo. */
1007 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1008 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1009 /* divw divw. divwo divwo. */
1010 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1011 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1012 #if defined(TARGET_PPC64)
1013 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1014 TCGv arg2, int sign, int compute_ov)
1015 {
1016 int l1 = gen_new_label();
1017 int l2 = gen_new_label();
1018
1019 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1020 if (sign) {
1021 int l3 = gen_new_label();
1022 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1023 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1024 gen_set_label(l3);
1025 tcg_gen_div_i64(ret, arg1, arg2);
1026 } else {
1027 tcg_gen_divu_i64(ret, arg1, arg2);
1028 }
1029 if (compute_ov) {
1030 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1031 }
1032 tcg_gen_br(l2);
1033 gen_set_label(l1);
1034 if (sign) {
1035 tcg_gen_sari_i64(ret, arg1, 63);
1036 } else {
1037 tcg_gen_movi_i64(ret, 0);
1038 }
1039 if (compute_ov) {
1040 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1041 }
1042 gen_set_label(l2);
1043 if (unlikely(Rc(ctx->opcode) != 0))
1044 gen_set_Rc0(ctx, ret);
1045 }
1046 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1047 static void glue(gen_, name)(DisasContext *ctx) \
1048 { \
1049 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1050 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1051 sign, compute_ov); \
1052 }
1053 /* divwu divwu. divwuo divwuo. */
1054 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1055 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1056 /* divw divw. divwo divwo. */
1057 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1058 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1059 #endif
1060
1061 /* mulhw mulhw. */
1062 static void gen_mulhw(DisasContext *ctx)
1063 {
1064 TCGv_i32 t0 = tcg_temp_new_i32();
1065 TCGv_i32 t1 = tcg_temp_new_i32();
1066
1067 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1068 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1069 tcg_gen_muls2_i32(t0, t1, t0, t1);
1070 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1071 tcg_temp_free_i32(t0);
1072 tcg_temp_free_i32(t1);
1073 if (unlikely(Rc(ctx->opcode) != 0))
1074 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1075 }
1076
1077 /* mulhwu mulhwu. */
1078 static void gen_mulhwu(DisasContext *ctx)
1079 {
1080 TCGv_i32 t0 = tcg_temp_new_i32();
1081 TCGv_i32 t1 = tcg_temp_new_i32();
1082
1083 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1084 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1085 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1086 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1087 tcg_temp_free_i32(t0);
1088 tcg_temp_free_i32(t1);
1089 if (unlikely(Rc(ctx->opcode) != 0))
1090 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1091 }
1092
1093 /* mullw mullw. */
1094 static void gen_mullw(DisasContext *ctx)
1095 {
1096 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1097 cpu_gpr[rB(ctx->opcode)]);
1098 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1099 if (unlikely(Rc(ctx->opcode) != 0))
1100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1101 }
1102
1103 /* mullwo mullwo. */
1104 static void gen_mullwo(DisasContext *ctx)
1105 {
1106 int l1;
1107 TCGv_i64 t0, t1;
1108
1109 t0 = tcg_temp_new_i64();
1110 t1 = tcg_temp_new_i64();
1111 l1 = gen_new_label();
1112 /* Start with XER OV disabled, the most likely case */
1113 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1114 #if defined(TARGET_PPC64)
1115 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1116 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1117 #else
1118 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1119 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1120 #endif
1121 tcg_gen_mul_i64(t0, t0, t1);
1122 #if defined(TARGET_PPC64)
1123 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1124 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1125 #else
1126 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1127 tcg_gen_ext32s_i64(t1, t0);
1128 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1129 #endif
1130 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1131 gen_set_label(l1);
1132 tcg_temp_free_i64(t0);
1133 tcg_temp_free_i64(t1);
1134 if (unlikely(Rc(ctx->opcode) != 0))
1135 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1136 }
1137
1138 /* mulli */
1139 static void gen_mulli(DisasContext *ctx)
1140 {
1141 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1142 SIMM(ctx->opcode));
1143 }
1144
1145 #if defined(TARGET_PPC64)
1146 /* mulhd mulhd. */
1147 static void gen_mulhd(DisasContext *ctx)
1148 {
1149 TCGv lo = tcg_temp_new();
1150 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1151 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1152 tcg_temp_free(lo);
1153 if (unlikely(Rc(ctx->opcode) != 0)) {
1154 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1155 }
1156 }
1157
1158 /* mulhdu mulhdu. */
1159 static void gen_mulhdu(DisasContext *ctx)
1160 {
1161 TCGv lo = tcg_temp_new();
1162 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1163 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1164 tcg_temp_free(lo);
1165 if (unlikely(Rc(ctx->opcode) != 0)) {
1166 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1167 }
1168 }
1169
1170 /* mulld mulld. */
1171 static void gen_mulld(DisasContext *ctx)
1172 {
1173 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1174 cpu_gpr[rB(ctx->opcode)]);
1175 if (unlikely(Rc(ctx->opcode) != 0))
1176 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1177 }
1178
1179 /* mulldo mulldo. */
1180 static void gen_mulldo(DisasContext *ctx)
1181 {
1182 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1183 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1184 if (unlikely(Rc(ctx->opcode) != 0)) {
1185 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1186 }
1187 }
1188 #endif
1189
1190 /* neg neg. nego nego. */
1191 static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1192 int ov_check)
1193 {
1194 int l1 = gen_new_label();
1195 int l2 = gen_new_label();
1196 TCGv t0 = tcg_temp_local_new();
1197 #if defined(TARGET_PPC64)
1198 if (ctx->sf_mode) {
1199 tcg_gen_mov_tl(t0, arg1);
1200 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1201 } else
1202 #endif
1203 {
1204 tcg_gen_ext32s_tl(t0, arg1);
1205 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1206 }
1207 tcg_gen_neg_tl(ret, arg1);
1208 if (ov_check) {
1209 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1210 }
1211 tcg_gen_br(l2);
1212 gen_set_label(l1);
1213 tcg_gen_mov_tl(ret, t0);
1214 if (ov_check) {
1215 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1216 }
1217 gen_set_label(l2);
1218 tcg_temp_free(t0);
1219 if (unlikely(Rc(ctx->opcode) != 0))
1220 gen_set_Rc0(ctx, ret);
1221 }
1222
1223 static void gen_neg(DisasContext *ctx)
1224 {
1225 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1226 }
1227
1228 static void gen_nego(DisasContext *ctx)
1229 {
1230 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1231 }
1232
1233 /* Common subf function */
1234 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1235 TCGv arg2, int add_ca, int compute_ca,
1236 int compute_ov)
1237 {
1238 TCGv t0, t1;
1239
1240 if ((!compute_ca && !compute_ov) ||
1241 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1242 t0 = ret;
1243 } else {
1244 t0 = tcg_temp_local_new();
1245 }
1246
1247 if (add_ca) {
1248 t1 = tcg_temp_local_new();
1249 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1250 tcg_gen_shri_tl(t1, t1, XER_CA);
1251 } else {
1252 TCGV_UNUSED(t1);
1253 }
1254
1255 if (compute_ca && compute_ov) {
1256 /* Start with XER CA and OV disabled, the most likely case */
1257 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1258 } else if (compute_ca) {
1259 /* Start with XER CA disabled, the most likely case */
1260 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1261 } else if (compute_ov) {
1262 /* Start with XER OV disabled, the most likely case */
1263 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1264 }
1265
1266 if (add_ca) {
1267 tcg_gen_not_tl(t0, arg1);
1268 tcg_gen_add_tl(t0, t0, arg2);
1269 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1270 tcg_gen_add_tl(t0, t0, t1);
1271 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1272 tcg_temp_free(t1);
1273 } else {
1274 tcg_gen_sub_tl(t0, arg2, arg1);
1275 if (compute_ca) {
1276 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1277 }
1278 }
1279 if (compute_ov) {
1280 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1281 }
1282
1283 if (unlikely(Rc(ctx->opcode) != 0))
1284 gen_set_Rc0(ctx, t0);
1285
1286 if (!TCGV_EQUAL(t0, ret)) {
1287 tcg_gen_mov_tl(ret, t0);
1288 tcg_temp_free(t0);
1289 }
1290 }
1291 /* Sub functions with Two operands functions */
1292 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1293 static void glue(gen_, name)(DisasContext *ctx) \
1294 { \
1295 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1296 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1297 add_ca, compute_ca, compute_ov); \
1298 }
1299 /* Sub functions with one operand and one immediate */
1300 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1301 add_ca, compute_ca, compute_ov) \
1302 static void glue(gen_, name)(DisasContext *ctx) \
1303 { \
1304 TCGv t0 = tcg_const_local_tl(const_val); \
1305 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1306 cpu_gpr[rA(ctx->opcode)], t0, \
1307 add_ca, compute_ca, compute_ov); \
1308 tcg_temp_free(t0); \
1309 }
1310 /* subf subf. subfo subfo. */
1311 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1312 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1313 /* subfc subfc. subfco subfco. */
1314 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1315 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1316 /* subfe subfe. subfeo subfo. */
1317 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1318 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1319 /* subfme subfme. subfmeo subfmeo. */
1320 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1321 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1322 /* subfze subfze. subfzeo subfzeo.*/
1323 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1324 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1325
1326 /* subfic */
1327 static void gen_subfic(DisasContext *ctx)
1328 {
1329 /* Start with XER CA and OV disabled, the most likely case */
1330 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1331 TCGv t0 = tcg_temp_local_new();
1332 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1333 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1334 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1335 tcg_temp_free(t1);
1336 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1337 tcg_temp_free(t0);
1338 }
1339
1340 /*** Integer logical ***/
1341 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1342 static void glue(gen_, name)(DisasContext *ctx) \
1343 { \
1344 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1345 cpu_gpr[rB(ctx->opcode)]); \
1346 if (unlikely(Rc(ctx->opcode) != 0)) \
1347 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1348 }
1349
1350 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1351 static void glue(gen_, name)(DisasContext *ctx) \
1352 { \
1353 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1354 if (unlikely(Rc(ctx->opcode) != 0)) \
1355 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1356 }
1357
1358 /* and & and. */
1359 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1360 /* andc & andc. */
1361 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1362
1363 /* andi. */
1364 static void gen_andi_(DisasContext *ctx)
1365 {
1366 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1367 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1368 }
1369
1370 /* andis. */
1371 static void gen_andis_(DisasContext *ctx)
1372 {
1373 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1374 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1375 }
1376
1377 /* cntlzw */
1378 static void gen_cntlzw(DisasContext *ctx)
1379 {
1380 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1381 if (unlikely(Rc(ctx->opcode) != 0))
1382 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1383 }
1384 /* eqv & eqv. */
1385 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1386 /* extsb & extsb. */
1387 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1388 /* extsh & extsh. */
1389 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1390 /* nand & nand. */
1391 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1392 /* nor & nor. */
1393 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1394
1395 /* or & or. */
1396 static void gen_or(DisasContext *ctx)
1397 {
1398 int rs, ra, rb;
1399
1400 rs = rS(ctx->opcode);
1401 ra = rA(ctx->opcode);
1402 rb = rB(ctx->opcode);
1403 /* Optimisation for mr. ri case */
1404 if (rs != ra || rs != rb) {
1405 if (rs != rb)
1406 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1407 else
1408 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1409 if (unlikely(Rc(ctx->opcode) != 0))
1410 gen_set_Rc0(ctx, cpu_gpr[ra]);
1411 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1412 gen_set_Rc0(ctx, cpu_gpr[rs]);
1413 #if defined(TARGET_PPC64)
1414 } else {
1415 int prio = 0;
1416
1417 switch (rs) {
1418 case 1:
1419 /* Set process priority to low */
1420 prio = 2;
1421 break;
1422 case 6:
1423 /* Set process priority to medium-low */
1424 prio = 3;
1425 break;
1426 case 2:
1427 /* Set process priority to normal */
1428 prio = 4;
1429 break;
1430 #if !defined(CONFIG_USER_ONLY)
1431 case 31:
1432 if (ctx->mem_idx > 0) {
1433 /* Set process priority to very low */
1434 prio = 1;
1435 }
1436 break;
1437 case 5:
1438 if (ctx->mem_idx > 0) {
1439 /* Set process priority to medium-hight */
1440 prio = 5;
1441 }
1442 break;
1443 case 3:
1444 if (ctx->mem_idx > 0) {
1445 /* Set process priority to high */
1446 prio = 6;
1447 }
1448 break;
1449 case 7:
1450 if (ctx->mem_idx > 1) {
1451 /* Set process priority to very high */
1452 prio = 7;
1453 }
1454 break;
1455 #endif
1456 default:
1457 /* nop */
1458 break;
1459 }
1460 if (prio) {
1461 TCGv t0 = tcg_temp_new();
1462 gen_load_spr(t0, SPR_PPR);
1463 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1464 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1465 gen_store_spr(SPR_PPR, t0);
1466 tcg_temp_free(t0);
1467 }
1468 #endif
1469 }
1470 }
1471 /* orc & orc. */
1472 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1473
1474 /* xor & xor. */
1475 static void gen_xor(DisasContext *ctx)
1476 {
1477 /* Optimisation for "set to zero" case */
1478 if (rS(ctx->opcode) != rB(ctx->opcode))
1479 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1480 else
1481 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1482 if (unlikely(Rc(ctx->opcode) != 0))
1483 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1484 }
1485
1486 /* ori */
1487 static void gen_ori(DisasContext *ctx)
1488 {
1489 target_ulong uimm = UIMM(ctx->opcode);
1490
1491 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1492 /* NOP */
1493 /* XXX: should handle special NOPs for POWER series */
1494 return;
1495 }
1496 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1497 }
1498
1499 /* oris */
1500 static void gen_oris(DisasContext *ctx)
1501 {
1502 target_ulong uimm = UIMM(ctx->opcode);
1503
1504 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1505 /* NOP */
1506 return;
1507 }
1508 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1509 }
1510
1511 /* xori */
1512 static void gen_xori(DisasContext *ctx)
1513 {
1514 target_ulong uimm = UIMM(ctx->opcode);
1515
1516 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1517 /* NOP */
1518 return;
1519 }
1520 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1521 }
1522
1523 /* xoris */
1524 static void gen_xoris(DisasContext *ctx)
1525 {
1526 target_ulong uimm = UIMM(ctx->opcode);
1527
1528 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1529 /* NOP */
1530 return;
1531 }
1532 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1533 }
1534
1535 /* popcntb : PowerPC 2.03 specification */
1536 static void gen_popcntb(DisasContext *ctx)
1537 {
1538 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1539 }
1540
1541 static void gen_popcntw(DisasContext *ctx)
1542 {
1543 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1544 }
1545
1546 #if defined(TARGET_PPC64)
1547 /* popcntd: PowerPC 2.06 specification */
1548 static void gen_popcntd(DisasContext *ctx)
1549 {
1550 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1551 }
1552 #endif
1553
1554 #if defined(TARGET_PPC64)
1555 /* extsw & extsw. */
1556 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1557
1558 /* cntlzd */
1559 static void gen_cntlzd(DisasContext *ctx)
1560 {
1561 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1562 if (unlikely(Rc(ctx->opcode) != 0))
1563 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1564 }
1565 #endif
1566
1567 /*** Integer rotate ***/
1568
1569 /* rlwimi & rlwimi. */
1570 static void gen_rlwimi(DisasContext *ctx)
1571 {
1572 uint32_t mb, me, sh;
1573
1574 mb = MB(ctx->opcode);
1575 me = ME(ctx->opcode);
1576 sh = SH(ctx->opcode);
1577 if (likely(sh == 0 && mb == 0 && me == 31)) {
1578 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1579 } else {
1580 target_ulong mask;
1581 TCGv t1;
1582 TCGv t0 = tcg_temp_new();
1583 #if defined(TARGET_PPC64)
1584 TCGv_i32 t2 = tcg_temp_new_i32();
1585 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1586 tcg_gen_rotli_i32(t2, t2, sh);
1587 tcg_gen_extu_i32_i64(t0, t2);
1588 tcg_temp_free_i32(t2);
1589 #else
1590 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1591 #endif
1592 #if defined(TARGET_PPC64)
1593 mb += 32;
1594 me += 32;
1595 #endif
1596 mask = MASK(mb, me);
1597 t1 = tcg_temp_new();
1598 tcg_gen_andi_tl(t0, t0, mask);
1599 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1600 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1601 tcg_temp_free(t0);
1602 tcg_temp_free(t1);
1603 }
1604 if (unlikely(Rc(ctx->opcode) != 0))
1605 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1606 }
1607
1608 /* rlwinm & rlwinm. */
1609 static void gen_rlwinm(DisasContext *ctx)
1610 {
1611 uint32_t mb, me, sh;
1612
1613 sh = SH(ctx->opcode);
1614 mb = MB(ctx->opcode);
1615 me = ME(ctx->opcode);
1616
1617 if (likely(mb == 0 && me == (31 - sh))) {
1618 if (likely(sh == 0)) {
1619 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1620 } else {
1621 TCGv t0 = tcg_temp_new();
1622 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1623 tcg_gen_shli_tl(t0, t0, sh);
1624 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1625 tcg_temp_free(t0);
1626 }
1627 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1628 TCGv t0 = tcg_temp_new();
1629 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1630 tcg_gen_shri_tl(t0, t0, mb);
1631 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1632 tcg_temp_free(t0);
1633 } else {
1634 TCGv t0 = tcg_temp_new();
1635 #if defined(TARGET_PPC64)
1636 TCGv_i32 t1 = tcg_temp_new_i32();
1637 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1638 tcg_gen_rotli_i32(t1, t1, sh);
1639 tcg_gen_extu_i32_i64(t0, t1);
1640 tcg_temp_free_i32(t1);
1641 #else
1642 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1643 #endif
1644 #if defined(TARGET_PPC64)
1645 mb += 32;
1646 me += 32;
1647 #endif
1648 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1649 tcg_temp_free(t0);
1650 }
1651 if (unlikely(Rc(ctx->opcode) != 0))
1652 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1653 }
1654
1655 /* rlwnm & rlwnm. */
1656 static void gen_rlwnm(DisasContext *ctx)
1657 {
1658 uint32_t mb, me;
1659 TCGv t0;
1660 #if defined(TARGET_PPC64)
1661 TCGv_i32 t1, t2;
1662 #endif
1663
1664 mb = MB(ctx->opcode);
1665 me = ME(ctx->opcode);
1666 t0 = tcg_temp_new();
1667 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1668 #if defined(TARGET_PPC64)
1669 t1 = tcg_temp_new_i32();
1670 t2 = tcg_temp_new_i32();
1671 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1672 tcg_gen_trunc_i64_i32(t2, t0);
1673 tcg_gen_rotl_i32(t1, t1, t2);
1674 tcg_gen_extu_i32_i64(t0, t1);
1675 tcg_temp_free_i32(t1);
1676 tcg_temp_free_i32(t2);
1677 #else
1678 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1679 #endif
1680 if (unlikely(mb != 0 || me != 31)) {
1681 #if defined(TARGET_PPC64)
1682 mb += 32;
1683 me += 32;
1684 #endif
1685 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1686 } else {
1687 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1688 }
1689 tcg_temp_free(t0);
1690 if (unlikely(Rc(ctx->opcode) != 0))
1691 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1692 }
1693
1694 #if defined(TARGET_PPC64)
1695 #define GEN_PPC64_R2(name, opc1, opc2) \
1696 static void glue(gen_, name##0)(DisasContext *ctx) \
1697 { \
1698 gen_##name(ctx, 0); \
1699 } \
1700 \
1701 static void glue(gen_, name##1)(DisasContext *ctx) \
1702 { \
1703 gen_##name(ctx, 1); \
1704 }
1705 #define GEN_PPC64_R4(name, opc1, opc2) \
1706 static void glue(gen_, name##0)(DisasContext *ctx) \
1707 { \
1708 gen_##name(ctx, 0, 0); \
1709 } \
1710 \
1711 static void glue(gen_, name##1)(DisasContext *ctx) \
1712 { \
1713 gen_##name(ctx, 0, 1); \
1714 } \
1715 \
1716 static void glue(gen_, name##2)(DisasContext *ctx) \
1717 { \
1718 gen_##name(ctx, 1, 0); \
1719 } \
1720 \
1721 static void glue(gen_, name##3)(DisasContext *ctx) \
1722 { \
1723 gen_##name(ctx, 1, 1); \
1724 }
1725
1726 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1727 uint32_t sh)
1728 {
1729 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1730 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1731 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1732 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1733 } else {
1734 TCGv t0 = tcg_temp_new();
1735 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1736 if (likely(mb == 0 && me == 63)) {
1737 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1738 } else {
1739 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1740 }
1741 tcg_temp_free(t0);
1742 }
1743 if (unlikely(Rc(ctx->opcode) != 0))
1744 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1745 }
1746 /* rldicl - rldicl. */
1747 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1748 {
1749 uint32_t sh, mb;
1750
1751 sh = SH(ctx->opcode) | (shn << 5);
1752 mb = MB(ctx->opcode) | (mbn << 5);
1753 gen_rldinm(ctx, mb, 63, sh);
1754 }
1755 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1756 /* rldicr - rldicr. */
1757 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1758 {
1759 uint32_t sh, me;
1760
1761 sh = SH(ctx->opcode) | (shn << 5);
1762 me = MB(ctx->opcode) | (men << 5);
1763 gen_rldinm(ctx, 0, me, sh);
1764 }
1765 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1766 /* rldic - rldic. */
1767 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1768 {
1769 uint32_t sh, mb;
1770
1771 sh = SH(ctx->opcode) | (shn << 5);
1772 mb = MB(ctx->opcode) | (mbn << 5);
1773 gen_rldinm(ctx, mb, 63 - sh, sh);
1774 }
1775 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1776
1777 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1778 {
1779 TCGv t0;
1780
1781 mb = MB(ctx->opcode);
1782 me = ME(ctx->opcode);
1783 t0 = tcg_temp_new();
1784 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1785 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1786 if (unlikely(mb != 0 || me != 63)) {
1787 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1788 } else {
1789 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1790 }
1791 tcg_temp_free(t0);
1792 if (unlikely(Rc(ctx->opcode) != 0))
1793 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1794 }
1795
1796 /* rldcl - rldcl. */
1797 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1798 {
1799 uint32_t mb;
1800
1801 mb = MB(ctx->opcode) | (mbn << 5);
1802 gen_rldnm(ctx, mb, 63);
1803 }
1804 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1805 /* rldcr - rldcr. */
1806 static inline void gen_rldcr(DisasContext *ctx, int men)
1807 {
1808 uint32_t me;
1809
1810 me = MB(ctx->opcode) | (men << 5);
1811 gen_rldnm(ctx, 0, me);
1812 }
1813 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1814 /* rldimi - rldimi. */
1815 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1816 {
1817 uint32_t sh, mb, me;
1818
1819 sh = SH(ctx->opcode) | (shn << 5);
1820 mb = MB(ctx->opcode) | (mbn << 5);
1821 me = 63 - sh;
1822 if (unlikely(sh == 0 && mb == 0)) {
1823 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1824 } else {
1825 TCGv t0, t1;
1826 target_ulong mask;
1827
1828 t0 = tcg_temp_new();
1829 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1830 t1 = tcg_temp_new();
1831 mask = MASK(mb, me);
1832 tcg_gen_andi_tl(t0, t0, mask);
1833 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1834 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1835 tcg_temp_free(t0);
1836 tcg_temp_free(t1);
1837 }
1838 if (unlikely(Rc(ctx->opcode) != 0))
1839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1840 }
1841 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1842 #endif
1843
1844 /*** Integer shift ***/
1845
1846 /* slw & slw. */
1847 static void gen_slw(DisasContext *ctx)
1848 {
1849 TCGv t0, t1;
1850
1851 t0 = tcg_temp_new();
1852 /* AND rS with a mask that is 0 when rB >= 0x20 */
1853 #if defined(TARGET_PPC64)
1854 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1855 tcg_gen_sari_tl(t0, t0, 0x3f);
1856 #else
1857 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1858 tcg_gen_sari_tl(t0, t0, 0x1f);
1859 #endif
1860 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1861 t1 = tcg_temp_new();
1862 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1863 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1864 tcg_temp_free(t1);
1865 tcg_temp_free(t0);
1866 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1867 if (unlikely(Rc(ctx->opcode) != 0))
1868 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1869 }
1870
1871 /* sraw & sraw. */
1872 static void gen_sraw(DisasContext *ctx)
1873 {
1874 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1875 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1876 if (unlikely(Rc(ctx->opcode) != 0))
1877 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1878 }
1879
1880 /* srawi & srawi. */
1881 static void gen_srawi(DisasContext *ctx)
1882 {
1883 int sh = SH(ctx->opcode);
1884 if (sh != 0) {
1885 int l1, l2;
1886 TCGv t0;
1887 l1 = gen_new_label();
1888 l2 = gen_new_label();
1889 t0 = tcg_temp_local_new();
1890 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1891 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1892 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1893 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1894 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1895 tcg_gen_br(l2);
1896 gen_set_label(l1);
1897 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1898 gen_set_label(l2);
1899 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1900 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1901 tcg_temp_free(t0);
1902 } else {
1903 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1904 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1905 }
1906 if (unlikely(Rc(ctx->opcode) != 0))
1907 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1908 }
1909
1910 /* srw & srw. */
1911 static void gen_srw(DisasContext *ctx)
1912 {
1913 TCGv t0, t1;
1914
1915 t0 = tcg_temp_new();
1916 /* AND rS with a mask that is 0 when rB >= 0x20 */
1917 #if defined(TARGET_PPC64)
1918 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1919 tcg_gen_sari_tl(t0, t0, 0x3f);
1920 #else
1921 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1922 tcg_gen_sari_tl(t0, t0, 0x1f);
1923 #endif
1924 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1925 tcg_gen_ext32u_tl(t0, t0);
1926 t1 = tcg_temp_new();
1927 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1928 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1929 tcg_temp_free(t1);
1930 tcg_temp_free(t0);
1931 if (unlikely(Rc(ctx->opcode) != 0))
1932 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1933 }
1934
1935 #if defined(TARGET_PPC64)
1936 /* sld & sld. */
1937 static void gen_sld(DisasContext *ctx)
1938 {
1939 TCGv t0, t1;
1940
1941 t0 = tcg_temp_new();
1942 /* AND rS with a mask that is 0 when rB >= 0x40 */
1943 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1944 tcg_gen_sari_tl(t0, t0, 0x3f);
1945 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1946 t1 = tcg_temp_new();
1947 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1948 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1949 tcg_temp_free(t1);
1950 tcg_temp_free(t0);
1951 if (unlikely(Rc(ctx->opcode) != 0))
1952 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1953 }
1954
1955 /* srad & srad. */
1956 static void gen_srad(DisasContext *ctx)
1957 {
1958 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1959 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1960 if (unlikely(Rc(ctx->opcode) != 0))
1961 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1962 }
1963 /* sradi & sradi. */
1964 static inline void gen_sradi(DisasContext *ctx, int n)
1965 {
1966 int sh = SH(ctx->opcode) + (n << 5);
1967 if (sh != 0) {
1968 int l1, l2;
1969 TCGv t0;
1970 l1 = gen_new_label();
1971 l2 = gen_new_label();
1972 t0 = tcg_temp_local_new();
1973 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1974 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1975 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1976 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1977 tcg_gen_br(l2);
1978 gen_set_label(l1);
1979 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1980 gen_set_label(l2);
1981 tcg_temp_free(t0);
1982 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1983 } else {
1984 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1985 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1986 }
1987 if (unlikely(Rc(ctx->opcode) != 0))
1988 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1989 }
1990
1991 static void gen_sradi0(DisasContext *ctx)
1992 {
1993 gen_sradi(ctx, 0);
1994 }
1995
1996 static void gen_sradi1(DisasContext *ctx)
1997 {
1998 gen_sradi(ctx, 1);
1999 }
2000
2001 /* srd & srd. */
2002 static void gen_srd(DisasContext *ctx)
2003 {
2004 TCGv t0, t1;
2005
2006 t0 = tcg_temp_new();
2007 /* AND rS with a mask that is 0 when rB >= 0x40 */
2008 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2009 tcg_gen_sari_tl(t0, t0, 0x3f);
2010 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2011 t1 = tcg_temp_new();
2012 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2013 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2014 tcg_temp_free(t1);
2015 tcg_temp_free(t0);
2016 if (unlikely(Rc(ctx->opcode) != 0))
2017 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2018 }
2019 #endif
2020
2021 /*** Floating-Point arithmetic ***/
2022 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2023 static void gen_f##name(DisasContext *ctx) \
2024 { \
2025 if (unlikely(!ctx->fpu_enabled)) { \
2026 gen_exception(ctx, POWERPC_EXCP_FPU); \
2027 return; \
2028 } \
2029 /* NIP cannot be restored if the memory exception comes from an helper */ \
2030 gen_update_nip(ctx, ctx->nip - 4); \
2031 gen_reset_fpstatus(); \
2032 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2033 cpu_fpr[rA(ctx->opcode)], \
2034 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2035 if (isfloat) { \
2036 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2037 cpu_fpr[rD(ctx->opcode)]); \
2038 } \
2039 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2040 Rc(ctx->opcode) != 0); \
2041 }
2042
2043 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2044 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2045 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2046
2047 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2048 static void gen_f##name(DisasContext *ctx) \
2049 { \
2050 if (unlikely(!ctx->fpu_enabled)) { \
2051 gen_exception(ctx, POWERPC_EXCP_FPU); \
2052 return; \
2053 } \
2054 /* NIP cannot be restored if the memory exception comes from an helper */ \
2055 gen_update_nip(ctx, ctx->nip - 4); \
2056 gen_reset_fpstatus(); \
2057 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2058 cpu_fpr[rA(ctx->opcode)], \
2059 cpu_fpr[rB(ctx->opcode)]); \
2060 if (isfloat) { \
2061 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2062 cpu_fpr[rD(ctx->opcode)]); \
2063 } \
2064 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2065 set_fprf, Rc(ctx->opcode) != 0); \
2066 }
2067 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2068 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2069 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2070
2071 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2072 static void gen_f##name(DisasContext *ctx) \
2073 { \
2074 if (unlikely(!ctx->fpu_enabled)) { \
2075 gen_exception(ctx, POWERPC_EXCP_FPU); \
2076 return; \
2077 } \
2078 /* NIP cannot be restored if the memory exception comes from an helper */ \
2079 gen_update_nip(ctx, ctx->nip - 4); \
2080 gen_reset_fpstatus(); \
2081 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2082 cpu_fpr[rA(ctx->opcode)], \
2083 cpu_fpr[rC(ctx->opcode)]); \
2084 if (isfloat) { \
2085 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2086 cpu_fpr[rD(ctx->opcode)]); \
2087 } \
2088 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2089 set_fprf, Rc(ctx->opcode) != 0); \
2090 }
2091 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2092 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2093 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2094
2095 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2096 static void gen_f##name(DisasContext *ctx) \
2097 { \
2098 if (unlikely(!ctx->fpu_enabled)) { \
2099 gen_exception(ctx, POWERPC_EXCP_FPU); \
2100 return; \
2101 } \
2102 /* NIP cannot be restored if the memory exception comes from an helper */ \
2103 gen_update_nip(ctx, ctx->nip - 4); \
2104 gen_reset_fpstatus(); \
2105 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2106 cpu_fpr[rB(ctx->opcode)]); \
2107 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2108 set_fprf, Rc(ctx->opcode) != 0); \
2109 }
2110
2111 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2112 static void gen_f##name(DisasContext *ctx) \
2113 { \
2114 if (unlikely(!ctx->fpu_enabled)) { \
2115 gen_exception(ctx, POWERPC_EXCP_FPU); \
2116 return; \
2117 } \
2118 /* NIP cannot be restored if the memory exception comes from an helper */ \
2119 gen_update_nip(ctx, ctx->nip - 4); \
2120 gen_reset_fpstatus(); \
2121 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2122 cpu_fpr[rB(ctx->opcode)]); \
2123 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2124 set_fprf, Rc(ctx->opcode) != 0); \
2125 }
2126
2127 /* fadd - fadds */
2128 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2129 /* fdiv - fdivs */
2130 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2131 /* fmul - fmuls */
2132 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2133
2134 /* fre */
2135 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2136
2137 /* fres */
2138 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2139
2140 /* frsqrte */
2141 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2142
2143 /* frsqrtes */
2144 static void gen_frsqrtes(DisasContext *ctx)
2145 {
2146 if (unlikely(!ctx->fpu_enabled)) {
2147 gen_exception(ctx, POWERPC_EXCP_FPU);
2148 return;
2149 }
2150 /* NIP cannot be restored if the memory exception comes from an helper */
2151 gen_update_nip(ctx, ctx->nip - 4);
2152 gen_reset_fpstatus();
2153 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2154 cpu_fpr[rB(ctx->opcode)]);
2155 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2156 cpu_fpr[rD(ctx->opcode)]);
2157 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2158 }
2159
2160 /* fsel */
2161 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2162 /* fsub - fsubs */
2163 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2164 /* Optional: */
2165
2166 /* fsqrt */
2167 static void gen_fsqrt(DisasContext *ctx)
2168 {
2169 if (unlikely(!ctx->fpu_enabled)) {
2170 gen_exception(ctx, POWERPC_EXCP_FPU);
2171 return;
2172 }
2173 /* NIP cannot be restored if the memory exception comes from an helper */
2174 gen_update_nip(ctx, ctx->nip - 4);
2175 gen_reset_fpstatus();
2176 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2177 cpu_fpr[rB(ctx->opcode)]);
2178 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2179 }
2180
2181 static void gen_fsqrts(DisasContext *ctx)
2182 {
2183 if (unlikely(!ctx->fpu_enabled)) {
2184 gen_exception(ctx, POWERPC_EXCP_FPU);
2185 return;
2186 }
2187 /* NIP cannot be restored if the memory exception comes from an helper */
2188 gen_update_nip(ctx, ctx->nip - 4);
2189 gen_reset_fpstatus();
2190 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2191 cpu_fpr[rB(ctx->opcode)]);
2192 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2193 cpu_fpr[rD(ctx->opcode)]);
2194 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2195 }
2196
2197 /*** Floating-Point multiply-and-add ***/
2198 /* fmadd - fmadds */
2199 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2200 /* fmsub - fmsubs */
2201 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2202 /* fnmadd - fnmadds */
2203 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2204 /* fnmsub - fnmsubs */
2205 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2206
2207 /*** Floating-Point round & convert ***/
2208 /* fctiw */
2209 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2210 /* fctiwz */
2211 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2212 /* frsp */
2213 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2214 #if defined(TARGET_PPC64)
2215 /* fcfid */
2216 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2217 /* fctid */
2218 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2219 /* fctidz */
2220 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2221 #endif
2222
2223 /* frin */
2224 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2225 /* friz */
2226 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2227 /* frip */
2228 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2229 /* frim */
2230 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2231
2232 /*** Floating-Point compare ***/
2233
2234 /* fcmpo */
2235 static void gen_fcmpo(DisasContext *ctx)
2236 {
2237 TCGv_i32 crf;
2238 if (unlikely(!ctx->fpu_enabled)) {
2239 gen_exception(ctx, POWERPC_EXCP_FPU);
2240 return;
2241 }
2242 /* NIP cannot be restored if the memory exception comes from an helper */
2243 gen_update_nip(ctx, ctx->nip - 4);
2244 gen_reset_fpstatus();
2245 crf = tcg_const_i32(crfD(ctx->opcode));
2246 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2247 cpu_fpr[rB(ctx->opcode)], crf);
2248 tcg_temp_free_i32(crf);
2249 gen_helper_float_check_status(cpu_env);
2250 }
2251
2252 /* fcmpu */
2253 static void gen_fcmpu(DisasContext *ctx)
2254 {
2255 TCGv_i32 crf;
2256 if (unlikely(!ctx->fpu_enabled)) {
2257 gen_exception(ctx, POWERPC_EXCP_FPU);
2258 return;
2259 }
2260 /* NIP cannot be restored if the memory exception comes from an helper */
2261 gen_update_nip(ctx, ctx->nip - 4);
2262 gen_reset_fpstatus();
2263 crf = tcg_const_i32(crfD(ctx->opcode));
2264 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2265 cpu_fpr[rB(ctx->opcode)], crf);
2266 tcg_temp_free_i32(crf);
2267 gen_helper_float_check_status(cpu_env);
2268 }
2269
2270 /*** Floating-point move ***/
2271 /* fabs */
2272 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2273 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2274
2275 /* fmr - fmr. */
2276 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2277 static void gen_fmr(DisasContext *ctx)
2278 {
2279 if (unlikely(!ctx->fpu_enabled)) {
2280 gen_exception(ctx, POWERPC_EXCP_FPU);
2281 return;
2282 }
2283 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2284 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2285 }
2286
2287 /* fnabs */
2288 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2289 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2290 /* fneg */
2291 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2292 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2293
2294 /*** Floating-Point status & ctrl register ***/
2295
2296 /* mcrfs */
2297 static void gen_mcrfs(DisasContext *ctx)
2298 {
2299 TCGv tmp = tcg_temp_new();
2300 int bfa;
2301
2302 if (unlikely(!ctx->fpu_enabled)) {
2303 gen_exception(ctx, POWERPC_EXCP_FPU);
2304 return;
2305 }
2306 bfa = 4 * (7 - crfS(ctx->opcode));
2307 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2308 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2309 tcg_temp_free(tmp);
2310 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2311 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2312 }
2313
2314 /* mffs */
2315 static void gen_mffs(DisasContext *ctx)
2316 {
2317 if (unlikely(!ctx->fpu_enabled)) {
2318 gen_exception(ctx, POWERPC_EXCP_FPU);
2319 return;
2320 }
2321 gen_reset_fpstatus();
2322 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2323 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2324 }
2325
2326 /* mtfsb0 */
2327 static void gen_mtfsb0(DisasContext *ctx)
2328 {
2329 uint8_t crb;
2330
2331 if (unlikely(!ctx->fpu_enabled)) {
2332 gen_exception(ctx, POWERPC_EXCP_FPU);
2333 return;
2334 }
2335 crb = 31 - crbD(ctx->opcode);
2336 gen_reset_fpstatus();
2337 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2338 TCGv_i32 t0;
2339 /* NIP cannot be restored if the memory exception comes from an helper */
2340 gen_update_nip(ctx, ctx->nip - 4);
2341 t0 = tcg_const_i32(crb);
2342 gen_helper_fpscr_clrbit(cpu_env, t0);
2343 tcg_temp_free_i32(t0);
2344 }
2345 if (unlikely(Rc(ctx->opcode) != 0)) {
2346 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2347 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2348 }
2349 }
2350
2351 /* mtfsb1 */
2352 static void gen_mtfsb1(DisasContext *ctx)
2353 {
2354 uint8_t crb;
2355
2356 if (unlikely(!ctx->fpu_enabled)) {
2357 gen_exception(ctx, POWERPC_EXCP_FPU);
2358 return;
2359 }
2360 crb = 31 - crbD(ctx->opcode);
2361 gen_reset_fpstatus();
2362 /* XXX: we pretend we can only do IEEE floating-point computations */
2363 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2364 TCGv_i32 t0;
2365 /* NIP cannot be restored if the memory exception comes from an helper */
2366 gen_update_nip(ctx, ctx->nip - 4);
2367 t0 = tcg_const_i32(crb);
2368 gen_helper_fpscr_setbit(cpu_env, t0);
2369 tcg_temp_free_i32(t0);
2370 }
2371 if (unlikely(Rc(ctx->opcode) != 0)) {
2372 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2373 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2374 }
2375 /* We can raise a differed exception */
2376 gen_helper_float_check_status(cpu_env);
2377 }
2378
2379 /* mtfsf */
2380 static void gen_mtfsf(DisasContext *ctx)
2381 {
2382 TCGv_i32 t0;
2383 int L = ctx->opcode & 0x02000000;
2384
2385 if (unlikely(!ctx->fpu_enabled)) {
2386 gen_exception(ctx, POWERPC_EXCP_FPU);
2387 return;
2388 }
2389 /* NIP cannot be restored if the memory exception comes from an helper */
2390 gen_update_nip(ctx, ctx->nip - 4);
2391 gen_reset_fpstatus();
2392 if (L)
2393 t0 = tcg_const_i32(0xff);
2394 else
2395 t0 = tcg_const_i32(FM(ctx->opcode));
2396 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2397 tcg_temp_free_i32(t0);
2398 if (unlikely(Rc(ctx->opcode) != 0)) {
2399 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2400 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2401 }
2402 /* We can raise a differed exception */
2403 gen_helper_float_check_status(cpu_env);
2404 }
2405
2406 /* mtfsfi */
2407 static void gen_mtfsfi(DisasContext *ctx)
2408 {
2409 int bf, sh;
2410 TCGv_i64 t0;
2411 TCGv_i32 t1;
2412
2413 if (unlikely(!ctx->fpu_enabled)) {
2414 gen_exception(ctx, POWERPC_EXCP_FPU);
2415 return;
2416 }
2417 bf = crbD(ctx->opcode) >> 2;
2418 sh = 7 - bf;
2419 /* NIP cannot be restored if the memory exception comes from an helper */
2420 gen_update_nip(ctx, ctx->nip - 4);
2421 gen_reset_fpstatus();
2422 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2423 t1 = tcg_const_i32(1 << sh);
2424 gen_helper_store_fpscr(cpu_env, t0, t1);
2425 tcg_temp_free_i64(t0);
2426 tcg_temp_free_i32(t1);
2427 if (unlikely(Rc(ctx->opcode) != 0)) {
2428 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2429 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2430 }
2431 /* We can raise a differed exception */
2432 gen_helper_float_check_status(cpu_env);
2433 }
2434
2435 /*** Addressing modes ***/
2436 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2437 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2438 target_long maskl)
2439 {
2440 target_long simm = SIMM(ctx->opcode);
2441
2442 simm &= ~maskl;
2443 if (rA(ctx->opcode) == 0) {
2444 #if defined(TARGET_PPC64)
2445 if (!ctx->sf_mode) {
2446 tcg_gen_movi_tl(EA, (uint32_t)simm);
2447 } else
2448 #endif
2449 tcg_gen_movi_tl(EA, simm);
2450 } else if (likely(simm != 0)) {
2451 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2452 #if defined(TARGET_PPC64)
2453 if (!ctx->sf_mode) {
2454 tcg_gen_ext32u_tl(EA, EA);
2455 }
2456 #endif
2457 } else {
2458 #if defined(TARGET_PPC64)
2459 if (!ctx->sf_mode) {
2460 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2461 } else
2462 #endif
2463 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2464 }
2465 }
2466
2467 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2468 {
2469 if (rA(ctx->opcode) == 0) {
2470 #if defined(TARGET_PPC64)
2471 if (!ctx->sf_mode) {
2472 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2473 } else
2474 #endif
2475 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2476 } else {
2477 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2478 #if defined(TARGET_PPC64)
2479 if (!ctx->sf_mode) {
2480 tcg_gen_ext32u_tl(EA, EA);
2481 }
2482 #endif
2483 }
2484 }
2485
2486 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2487 {
2488 if (rA(ctx->opcode) == 0) {
2489 tcg_gen_movi_tl(EA, 0);
2490 } else {
2491 #if defined(TARGET_PPC64)
2492 if (!ctx->sf_mode) {
2493 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2494 } else
2495 #endif
2496 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2497 }
2498 }
2499
2500 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2501 target_long val)
2502 {
2503 tcg_gen_addi_tl(ret, arg1, val);
2504 #if defined(TARGET_PPC64)
2505 if (!ctx->sf_mode) {
2506 tcg_gen_ext32u_tl(ret, ret);
2507 }
2508 #endif
2509 }
2510
2511 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2512 {
2513 int l1 = gen_new_label();
2514 TCGv t0 = tcg_temp_new();
2515 TCGv_i32 t1, t2;
2516 /* NIP cannot be restored if the memory exception comes from an helper */
2517 gen_update_nip(ctx, ctx->nip - 4);
2518 tcg_gen_andi_tl(t0, EA, mask);
2519 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2520 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2521 t2 = tcg_const_i32(0);
2522 gen_helper_raise_exception_err(cpu_env, t1, t2);
2523 tcg_temp_free_i32(t1);
2524 tcg_temp_free_i32(t2);
2525 gen_set_label(l1);
2526 tcg_temp_free(t0);
2527 }
2528
2529 /*** Integer load ***/
2530 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2531 {
2532 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2533 }
2534
2535 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2536 {
2537 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2538 }
2539
2540 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2541 {
2542 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2543 if (unlikely(ctx->le_mode)) {
2544 tcg_gen_bswap16_tl(arg1, arg1);
2545 }
2546 }
2547
2548 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2549 {
2550 if (unlikely(ctx->le_mode)) {
2551 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2552 tcg_gen_bswap16_tl(arg1, arg1);
2553 tcg_gen_ext16s_tl(arg1, arg1);
2554 } else {
2555 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2556 }
2557 }
2558
2559 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2560 {
2561 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2562 if (unlikely(ctx->le_mode)) {
2563 tcg_gen_bswap32_tl(arg1, arg1);
2564 }
2565 }
2566
2567 #if defined(TARGET_PPC64)
2568 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2569 {
2570 if (unlikely(ctx->le_mode)) {
2571 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2572 tcg_gen_bswap32_tl(arg1, arg1);
2573 tcg_gen_ext32s_tl(arg1, arg1);
2574 } else
2575 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2576 }
2577 #endif
2578
2579 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2580 {
2581 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2582 if (unlikely(ctx->le_mode)) {
2583 tcg_gen_bswap64_i64(arg1, arg1);
2584 }
2585 }
2586
2587 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2588 {
2589 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2590 }
2591
2592 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2593 {
2594 if (unlikely(ctx->le_mode)) {
2595 TCGv t0 = tcg_temp_new();
2596 tcg_gen_ext16u_tl(t0, arg1);
2597 tcg_gen_bswap16_tl(t0, t0);
2598 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2599 tcg_temp_free(t0);
2600 } else {
2601 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2602 }
2603 }
2604
2605 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2606 {
2607 if (unlikely(ctx->le_mode)) {
2608 TCGv t0 = tcg_temp_new();
2609 tcg_gen_ext32u_tl(t0, arg1);
2610 tcg_gen_bswap32_tl(t0, t0);
2611 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2612 tcg_temp_free(t0);
2613 } else {
2614 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2615 }
2616 }
2617
2618 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2619 {
2620 if (unlikely(ctx->le_mode)) {
2621 TCGv_i64 t0 = tcg_temp_new_i64();
2622 tcg_gen_bswap64_i64(t0, arg1);
2623 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2624 tcg_temp_free_i64(t0);
2625 } else
2626 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2627 }
2628
2629 #define GEN_LD(name, ldop, opc, type) \
2630 static void glue(gen_, name)(DisasContext *ctx) \
2631 { \
2632 TCGv EA; \
2633 gen_set_access_type(ctx, ACCESS_INT); \
2634 EA = tcg_temp_new(); \
2635 gen_addr_imm_index(ctx, EA, 0); \
2636 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2637 tcg_temp_free(EA); \
2638 }
2639
2640 #define GEN_LDU(name, ldop, opc, type) \
2641 static void glue(gen_, name##u)(DisasContext *ctx) \
2642 { \
2643 TCGv EA; \
2644 if (unlikely(rA(ctx->opcode) == 0 || \
2645 rA(ctx->opcode) == rD(ctx->opcode))) { \
2646 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2647 return; \
2648 } \
2649 gen_set_access_type(ctx, ACCESS_INT); \
2650 EA = tcg_temp_new(); \
2651 if (type == PPC_64B) \
2652 gen_addr_imm_index(ctx, EA, 0x03); \
2653 else \
2654 gen_addr_imm_index(ctx, EA, 0); \
2655 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2656 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2657 tcg_temp_free(EA); \
2658 }
2659
2660 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2661 static void glue(gen_, name##ux)(DisasContext *ctx) \
2662 { \
2663 TCGv EA; \
2664 if (unlikely(rA(ctx->opcode) == 0 || \
2665 rA(ctx->opcode) == rD(ctx->opcode))) { \
2666 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2667 return; \
2668 } \
2669 gen_set_access_type(ctx, ACCESS_INT); \
2670 EA = tcg_temp_new(); \
2671 gen_addr_reg_index(ctx, EA); \
2672 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2673 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2674 tcg_temp_free(EA); \
2675 }
2676
2677 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2678 static void glue(gen_, name##x)(DisasContext *ctx) \
2679 { \
2680 TCGv EA; \
2681 gen_set_access_type(ctx, ACCESS_INT); \
2682 EA = tcg_temp_new(); \
2683 gen_addr_reg_index(ctx, EA); \
2684 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2685 tcg_temp_free(EA); \
2686 }
2687 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2688 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2689
2690 #define GEN_LDS(name, ldop, op, type) \
2691 GEN_LD(name, ldop, op | 0x20, type); \
2692 GEN_LDU(name, ldop, op | 0x21, type); \
2693 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2694 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2695
2696 /* lbz lbzu lbzux lbzx */
2697 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2698 /* lha lhau lhaux lhax */
2699 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2700 /* lhz lhzu lhzux lhzx */
2701 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2702 /* lwz lwzu lwzux lwzx */
2703 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2704 #if defined(TARGET_PPC64)
2705 /* lwaux */
2706 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2707 /* lwax */
2708 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2709 /* ldux */
2710 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2711 /* ldx */
2712 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2713
2714 static void gen_ld(DisasContext *ctx)
2715 {
2716 TCGv EA;
2717 if (Rc(ctx->opcode)) {
2718 if (unlikely(rA(ctx->opcode) == 0 ||
2719 rA(ctx->opcode) == rD(ctx->opcode))) {
2720 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2721 return;
2722 }
2723 }
2724 gen_set_access_type(ctx, ACCESS_INT);
2725 EA = tcg_temp_new();
2726 gen_addr_imm_index(ctx, EA, 0x03);
2727 if (ctx->opcode & 0x02) {
2728 /* lwa (lwau is undefined) */
2729 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2730 } else {
2731 /* ld - ldu */
2732 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2733 }
2734 if (Rc(ctx->opcode))
2735 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2736 tcg_temp_free(EA);
2737 }
2738
2739 /* lq */
2740 static void gen_lq(DisasContext *ctx)
2741 {
2742 #if defined(CONFIG_USER_ONLY)
2743 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2744 #else
2745 int ra, rd;
2746 TCGv EA;
2747
2748 /* Restore CPU state */
2749 if (unlikely(ctx->mem_idx == 0)) {
2750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2751 return;
2752 }
2753 ra = rA(ctx->opcode);
2754 rd = rD(ctx->opcode);
2755 if (unlikely((rd & 1) || rd == ra)) {
2756 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2757 return;
2758 }
2759 if (unlikely(ctx->le_mode)) {
2760 /* Little-endian mode is not handled */
2761 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2762 return;
2763 }
2764 gen_set_access_type(ctx, ACCESS_INT);
2765 EA = tcg_temp_new();
2766 gen_addr_imm_index(ctx, EA, 0x0F);
2767 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2768 gen_addr_add(ctx, EA, EA, 8);
2769 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2770 tcg_temp_free(EA);
2771 #endif
2772 }
2773 #endif
2774
2775 /*** Integer store ***/
2776 #define GEN_ST(name, stop, opc, type) \
2777 static void glue(gen_, name)(DisasContext *ctx) \
2778 { \
2779 TCGv EA; \
2780 gen_set_access_type(ctx, ACCESS_INT); \
2781 EA = tcg_temp_new(); \
2782 gen_addr_imm_index(ctx, EA, 0); \
2783 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2784 tcg_temp_free(EA); \
2785 }
2786
2787 #define GEN_STU(name, stop, opc, type) \
2788 static void glue(gen_, stop##u)(DisasContext *ctx) \
2789 { \
2790 TCGv EA; \
2791 if (unlikely(rA(ctx->opcode) == 0)) { \
2792 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2793 return; \
2794 } \
2795 gen_set_access_type(ctx, ACCESS_INT); \
2796 EA = tcg_temp_new(); \
2797 if (type == PPC_64B) \
2798 gen_addr_imm_index(ctx, EA, 0x03); \
2799 else \
2800 gen_addr_imm_index(ctx, EA, 0); \
2801 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2802 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2803 tcg_temp_free(EA); \
2804 }
2805
2806 #define GEN_STUX(name, stop, opc2, opc3, type) \
2807 static void glue(gen_, name##ux)(DisasContext *ctx) \
2808 { \
2809 TCGv EA; \
2810 if (unlikely(rA(ctx->opcode) == 0)) { \
2811 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2812 return; \
2813 } \
2814 gen_set_access_type(ctx, ACCESS_INT); \
2815 EA = tcg_temp_new(); \
2816 gen_addr_reg_index(ctx, EA); \
2817 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2818 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2819 tcg_temp_free(EA); \
2820 }
2821
2822 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2823 static void glue(gen_, name##x)(DisasContext *ctx) \
2824 { \
2825 TCGv EA; \
2826 gen_set_access_type(ctx, ACCESS_INT); \
2827 EA = tcg_temp_new(); \
2828 gen_addr_reg_index(ctx, EA); \
2829 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2830 tcg_temp_free(EA); \
2831 }
2832 #define GEN_STX(name, stop, opc2, opc3, type) \
2833 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2834
2835 #define GEN_STS(name, stop, op, type) \
2836 GEN_ST(name, stop, op | 0x20, type); \
2837 GEN_STU(name, stop, op | 0x21, type); \
2838 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2839 GEN_STX(name, stop, 0x17, op | 0x00, type)
2840
2841 /* stb stbu stbux stbx */
2842 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2843 /* sth sthu sthux sthx */
2844 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2845 /* stw stwu stwux stwx */
2846 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2847 #if defined(TARGET_PPC64)
2848 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2849 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2850
2851 static void gen_std(DisasContext *ctx)
2852 {
2853 int rs;
2854 TCGv EA;
2855
2856 rs = rS(ctx->opcode);
2857 if ((ctx->opcode & 0x3) == 0x2) {
2858 #if defined(CONFIG_USER_ONLY)
2859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2860 #else
2861 /* stq */
2862 if (unlikely(ctx->mem_idx == 0)) {
2863 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2864 return;
2865 }
2866 if (unlikely(rs & 1)) {
2867 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2868 return;
2869 }
2870 if (unlikely(ctx->le_mode)) {
2871 /* Little-endian mode is not handled */
2872 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2873 return;
2874 }
2875 gen_set_access_type(ctx, ACCESS_INT);
2876 EA = tcg_temp_new();
2877 gen_addr_imm_index(ctx, EA, 0x03);
2878 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2879 gen_addr_add(ctx, EA, EA, 8);
2880 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2881 tcg_temp_free(EA);
2882 #endif
2883 } else {
2884 /* std / stdu */
2885 if (Rc(ctx->opcode)) {
2886 if (unlikely(rA(ctx->opcode) == 0)) {
2887 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2888 return;
2889 }
2890 }
2891 gen_set_access_type(ctx, ACCESS_INT);
2892 EA = tcg_temp_new();
2893 gen_addr_imm_index(ctx, EA, 0x03);
2894 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2895 if (Rc(ctx->opcode))
2896 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2897 tcg_temp_free(EA);
2898 }
2899 }
2900 #endif
2901 /*** Integer load and store with byte reverse ***/
2902 /* lhbrx */
2903 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2904 {
2905 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2906 if (likely(!ctx->le_mode)) {
2907 tcg_gen_bswap16_tl(arg1, arg1);
2908 }
2909 }
2910 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2911
2912 /* lwbrx */
2913 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2914 {
2915 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2916 if (likely(!ctx->le_mode)) {
2917 tcg_gen_bswap32_tl(arg1, arg1);
2918 }
2919 }
2920 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2921
2922 #if defined(TARGET_PPC64)
2923 /* ldbrx */
2924 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2925 {
2926 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2927 if (likely(!ctx->le_mode)) {
2928 tcg_gen_bswap64_tl(arg1, arg1);
2929 }
2930 }
2931 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2932 #endif /* TARGET_PPC64 */
2933
2934 /* sthbrx */
2935 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2936 {
2937 if (likely(!ctx->le_mode)) {
2938 TCGv t0 = tcg_temp_new();
2939 tcg_gen_ext16u_tl(t0, arg1);
2940 tcg_gen_bswap16_tl(t0, t0);
2941 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2942 tcg_temp_free(t0);
2943 } else {
2944 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2945 }
2946 }
2947 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2948
2949 /* stwbrx */
2950 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2951 {
2952 if (likely(!ctx->le_mode)) {
2953 TCGv t0 = tcg_temp_new();
2954 tcg_gen_ext32u_tl(t0, arg1);
2955 tcg_gen_bswap32_tl(t0, t0);
2956 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2957 tcg_temp_free(t0);
2958 } else {
2959 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2960 }
2961 }
2962 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2963
2964 #if defined(TARGET_PPC64)
2965 /* stdbrx */
2966 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2967 {
2968 if (likely(!ctx->le_mode)) {
2969 TCGv t0 = tcg_temp_new();
2970 tcg_gen_bswap64_tl(t0, arg1);
2971 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2972 tcg_temp_free(t0);
2973 } else {
2974 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2975 }
2976 }
2977 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2978 #endif /* TARGET_PPC64 */
2979
2980 /*** Integer load and store multiple ***/
2981
2982 /* lmw */
2983 static void gen_lmw(DisasContext *ctx)
2984 {
2985 TCGv t0;
2986 TCGv_i32 t1;
2987 gen_set_access_type(ctx, ACCESS_INT);
2988 /* NIP cannot be restored if the memory exception comes from an helper */
2989 gen_update_nip(ctx, ctx->nip - 4);
2990 t0 = tcg_temp_new();
2991 t1 = tcg_const_i32(rD(ctx->opcode));
2992 gen_addr_imm_index(ctx, t0, 0);
2993 gen_helper_lmw(cpu_env, t0, t1);
2994 tcg_temp_free(t0);
2995 tcg_temp_free_i32(t1);
2996 }
2997
2998 /* stmw */
2999 static void gen_stmw(DisasContext *ctx)
3000 {
3001 TCGv t0;
3002 TCGv_i32 t1;
3003 gen_set_access_type(ctx, ACCESS_INT);
3004 /* NIP cannot be restored if the memory exception comes from an helper */
3005 gen_update_nip(ctx, ctx->nip - 4);
3006 t0 = tcg_temp_new();
3007 t1 = tcg_const_i32(rS(ctx->opcode));
3008 gen_addr_imm_index(ctx, t0, 0);
3009 gen_helper_stmw(cpu_env, t0, t1);
3010 tcg_temp_free(t0);
3011 tcg_temp_free_i32(t1);
3012 }
3013
3014 /*** Integer load and store strings ***/
3015
3016 /* lswi */
3017 /* PowerPC32 specification says we must generate an exception if
3018 * rA is in the range of registers to be loaded.
3019 * In an other hand, IBM says this is valid, but rA won't be loaded.
3020 * For now, I'll follow the spec...
3021 */
3022 static void gen_lswi(DisasContext *ctx)
3023 {
3024 TCGv t0;
3025 TCGv_i32 t1, t2;
3026 int nb = NB(ctx->opcode);
3027 int start = rD(ctx->opcode);
3028 int ra = rA(ctx->opcode);
3029 int nr;
3030
3031 if (nb == 0)
3032 nb = 32;
3033 nr = nb / 4;
3034 if (unlikely(((start + nr) > 32 &&
3035 start <= ra && (start + nr - 32) > ra) ||
3036 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3037 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3038 return;
3039 }
3040 gen_set_access_type(ctx, ACCESS_INT);
3041 /* NIP cannot be restored if the memory exception comes from an helper */
3042 gen_update_nip(ctx, ctx->nip - 4);
3043 t0 = tcg_temp_new();
3044 gen_addr_register(ctx, t0);
3045 t1 = tcg_const_i32(nb);
3046 t2 = tcg_const_i32(start);
3047 gen_helper_lsw(cpu_env, t0, t1, t2);
3048 tcg_temp_free(t0);
3049 tcg_temp_free_i32(t1);
3050 tcg_temp_free_i32(t2);
3051 }
3052
3053 /* lswx */
3054 static void gen_lswx(DisasContext *ctx)
3055 {
3056 TCGv t0;
3057 TCGv_i32 t1, t2, t3;
3058 gen_set_access_type(ctx, ACCESS_INT);
3059 /* NIP cannot be restored if the memory exception comes from an helper */
3060 gen_update_nip(ctx, ctx->nip - 4);
3061 t0 = tcg_temp_new();
3062 gen_addr_reg_index(ctx, t0);
3063 t1 = tcg_const_i32(rD(ctx->opcode));
3064 t2 = tcg_const_i32(rA(ctx->opcode));
3065 t3 = tcg_const_i32(rB(ctx->opcode));
3066 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3067 tcg_temp_free(t0);
3068 tcg_temp_free_i32(t1);
3069 tcg_temp_free_i32(t2);
3070 tcg_temp_free_i32(t3);
3071 }
3072
3073 /* stswi */
3074 static void gen_stswi(DisasContext *ctx)
3075 {
3076 TCGv t0;
3077 TCGv_i32 t1, t2;
3078 int nb = NB(ctx->opcode);
3079 gen_set_access_type(ctx, ACCESS_INT);
3080 /* NIP cannot be restored if the memory exception comes from an helper */
3081 gen_update_nip(ctx, ctx->nip - 4);
3082 t0 = tcg_temp_new();
3083 gen_addr_register(ctx, t0);
3084 if (nb == 0)
3085 nb = 32;
3086 t1 = tcg_const_i32(nb);
3087 t2 = tcg_const_i32(rS(ctx->opcode));
3088 gen_helper_stsw(cpu_env, t0, t1, t2);
3089 tcg_temp_free(t0);
3090 tcg_temp_free_i32(t1);
3091 tcg_temp_free_i32(t2);
3092 }
3093
3094 /* stswx */
3095 static void gen_stswx(DisasContext *ctx)
3096 {
3097 TCGv t0;
3098 TCGv_i32 t1, t2;
3099 gen_set_access_type(ctx, ACCESS_INT);
3100 /* NIP cannot be restored if the memory exception comes from an helper */
3101 gen_update_nip(ctx, ctx->nip - 4);
3102 t0 = tcg_temp_new();
3103 gen_addr_reg_index(ctx, t0);
3104 t1 = tcg_temp_new_i32();
3105 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3106 tcg_gen_andi_i32(t1, t1, 0x7F);
3107 t2 = tcg_const_i32(rS(ctx->opcode));
3108 gen_helper_stsw(cpu_env, t0, t1, t2);
3109 tcg_temp_free(t0);
3110 tcg_temp_free_i32(t1);
3111 tcg_temp_free_i32(t2);
3112 }
3113
3114 /*** Memory synchronisation ***/
3115 /* eieio */
3116 static void gen_eieio(DisasContext *ctx)
3117 {
3118 }
3119
3120 /* isync */
3121 static void gen_isync(DisasContext *ctx)
3122 {
3123 gen_stop_exception(ctx);
3124 }
3125
3126 /* lwarx */
3127 static void gen_lwarx(DisasContext *ctx)
3128 {
3129 TCGv t0;
3130 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3131 gen_set_access_type(ctx, ACCESS_RES);
3132 t0 = tcg_temp_local_new();
3133 gen_addr_reg_index(ctx, t0);
3134 gen_check_align(ctx, t0, 0x03);
3135 gen_qemu_ld32u(ctx, gpr, t0);
3136 tcg_gen_mov_tl(cpu_reserve, t0);
3137 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3138 tcg_temp_free(t0);
3139 }
3140
3141 #if defined(CONFIG_USER_ONLY)
3142 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3143 int reg, int size)
3144 {
3145 TCGv t0 = tcg_temp_new();
3146 uint32_t save_exception = ctx->exception;
3147
3148 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3149 tcg_gen_movi_tl(t0, (size << 5) | reg);
3150 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3151 tcg_temp_free(t0);
3152 gen_update_nip(ctx, ctx->nip-4);
3153 ctx->exception = POWERPC_EXCP_BRANCH;
3154 gen_exception(ctx, POWERPC_EXCP_STCX);
3155 ctx->exception = save_exception;
3156 }
3157 #endif
3158
3159 /* stwcx. */
3160 static void gen_stwcx_(DisasContext *ctx)
3161 {
3162 TCGv t0;
3163 gen_set_access_type(ctx, ACCESS_RES);
3164 t0 = tcg_temp_local_new();
3165 gen_addr_reg_index(ctx, t0);
3166 gen_check_align(ctx, t0, 0x03);
3167 #if defined(CONFIG_USER_ONLY)
3168 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3169 #else
3170 {
3171 int l1;
3172
3173 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3174 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3175 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3176 l1 = gen_new_label();
3177 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3178 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3179 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3180 gen_set_label(l1);
3181 tcg_gen_movi_tl(cpu_reserve, -1);
3182 }
3183 #endif
3184 tcg_temp_free(t0);
3185 }
3186
3187 #if defined(TARGET_PPC64)
3188 /* ldarx */
3189 static void gen_ldarx(DisasContext *ctx)
3190 {
3191 TCGv t0;
3192 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3193 gen_set_access_type(ctx, ACCESS_RES);
3194 t0 = tcg_temp_local_new();
3195 gen_addr_reg_index(ctx, t0);
3196 gen_check_align(ctx, t0, 0x07);
3197 gen_qemu_ld64(ctx, gpr, t0);
3198 tcg_gen_mov_tl(cpu_reserve, t0);
3199 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3200 tcg_temp_free(t0);
3201 }
3202
3203 /* stdcx. */
3204 static void gen_stdcx_(DisasContext *ctx)
3205 {
3206 TCGv t0;
3207 gen_set_access_type(ctx, ACCESS_RES);
3208 t0 = tcg_temp_local_new();
3209 gen_addr_reg_index(ctx, t0);
3210 gen_check_align(ctx, t0, 0x07);
3211 #if defined(CONFIG_USER_ONLY)
3212 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3213 #else
3214 {
3215 int l1;
3216 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3217 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3218 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3219 l1 = gen_new_label();
3220 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3221 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3222 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3223 gen_set_label(l1);
3224 tcg_gen_movi_tl(cpu_reserve, -1);
3225 }
3226 #endif
3227 tcg_temp_free(t0);
3228 }
3229 #endif /* defined(TARGET_PPC64) */
3230
3231 /* sync */
3232 static void gen_sync(DisasContext *ctx)
3233 {
3234 }
3235
3236 /* wait */
3237 static void gen_wait(DisasContext *ctx)
3238 {
3239 TCGv_i32 t0 = tcg_temp_new_i32();
3240 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
3241 tcg_temp_free_i32(t0);
3242 /* Stop translation, as the CPU is supposed to sleep from now */
3243 gen_exception_err(ctx, EXCP_HLT, 1);
3244 }
3245
3246 /*** Floating-point load ***/
3247 #define GEN_LDF(name, ldop, opc, type) \
3248 static void glue(gen_, name)(DisasContext *ctx) \
3249 { \
3250 TCGv EA; \
3251 if (unlikely(!ctx->fpu_enabled)) { \
3252 gen_exception(ctx, POWERPC_EXCP_FPU); \
3253 return; \
3254 } \
3255 gen_set_access_type(ctx, ACCESS_FLOAT); \
3256 EA = tcg_temp_new(); \
3257 gen_addr_imm_index(ctx, EA, 0); \
3258 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3259 tcg_temp_free(EA); \
3260 }
3261
3262 #define GEN_LDUF(name, ldop, opc, type) \
3263 static void glue(gen_, name##u)(DisasContext *ctx) \
3264 { \
3265 TCGv EA; \
3266 if (unlikely(!ctx->fpu_enabled)) { \
3267 gen_exception(ctx, POWERPC_EXCP_FPU); \
3268 return; \
3269 } \
3270 if (unlikely(rA(ctx->opcode) == 0)) { \
3271 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3272 return; \
3273 } \
3274 gen_set_access_type(ctx, ACCESS_FLOAT); \
3275 EA = tcg_temp_new(); \
3276 gen_addr_imm_index(ctx, EA, 0); \
3277 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3278 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3279 tcg_temp_free(EA); \
3280 }
3281
3282 #define GEN_LDUXF(name, ldop, opc, type) \
3283 static void glue(gen_, name##ux)(DisasContext *ctx) \
3284 { \
3285 TCGv EA; \
3286 if (unlikely(!ctx->fpu_enabled)) { \
3287 gen_exception(ctx, POWERPC_EXCP_FPU); \
3288 return; \
3289 } \
3290 if (unlikely(rA(ctx->opcode) == 0)) { \
3291 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3292 return; \
3293 } \
3294 gen_set_access_type(ctx, ACCESS_FLOAT); \
3295 EA = tcg_temp_new(); \
3296 gen_addr_reg_index(ctx, EA); \
3297 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3298 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3299 tcg_temp_free(EA); \
3300 }
3301
3302 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3303 static void glue(gen_, name##x)(DisasContext *ctx) \
3304 { \
3305 TCGv EA; \
3306 if (unlikely(!ctx->fpu_enabled)) { \
3307 gen_exception(ctx, POWERPC_EXCP_FPU); \
3308 return; \
3309 } \
3310 gen_set_access_type(ctx, ACCESS_FLOAT); \
3311 EA = tcg_temp_new(); \
3312 gen_addr_reg_index(ctx, EA); \
3313 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3314 tcg_temp_free(EA); \
3315 }
3316
3317 #define GEN_LDFS(name, ldop, op, type) \
3318 GEN_LDF(name, ldop, op | 0x20, type); \
3319 GEN_LDUF(name, ldop, op | 0x21, type); \
3320 GEN_LDUXF(name, ldop, op | 0x01, type); \
3321 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3322
3323 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3324 {
3325 TCGv t0 = tcg_temp_new();
3326 TCGv_i32 t1 = tcg_temp_new_i32();
3327 gen_qemu_ld32u(ctx, t0, arg2);
3328 tcg_gen_trunc_tl_i32(t1, t0);
3329 tcg_temp_free(t0);
3330 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3331 tcg_temp_free_i32(t1);
3332 }
3333
3334 /* lfd lfdu lfdux lfdx */
3335 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3336 /* lfs lfsu lfsux lfsx */
3337 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3338
3339 /*** Floating-point store ***/
3340 #define GEN_STF(name, stop, opc, type) \
3341 static void glue(gen_, name)(DisasContext *ctx) \
3342 { \
3343 TCGv EA; \
3344 if (unlikely(!ctx->fpu_enabled)) { \
3345 gen_exception(ctx, POWERPC_EXCP_FPU); \
3346 return; \
3347 } \
3348 gen_set_access_type(ctx, ACCESS_FLOAT); \
3349 EA = tcg_temp_new(); \
3350 gen_addr_imm_index(ctx, EA, 0); \
3351 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3352 tcg_temp_free(EA); \
3353 }
3354
3355 #define GEN_STUF(name, stop, opc, type) \
3356 static void glue(gen_, name##u)(DisasContext *ctx) \
3357 { \
3358 TCGv EA; \
3359 if (unlikely(!ctx->fpu_enabled)) { \
3360 gen_exception(ctx, POWERPC_EXCP_FPU); \
3361 return; \
3362 } \
3363 if (unlikely(rA(ctx->opcode) == 0)) { \
3364 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3365 return; \
3366 } \
3367 gen_set_access_type(ctx, ACCESS_FLOAT); \
3368 EA = tcg_temp_new(); \
3369 gen_addr_imm_index(ctx, EA, 0); \
3370 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3371 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3372 tcg_temp_free(EA); \
3373 }
3374
3375 #define GEN_STUXF(name, stop, opc, type) \
3376 static void glue(gen_, name##ux)(DisasContext *ctx) \
3377 { \
3378 TCGv EA; \
3379 if (unlikely(!ctx->fpu_enabled)) { \
3380 gen_exception(ctx, POWERPC_EXCP_FPU); \
3381 return; \
3382 } \
3383 if (unlikely(rA(ctx->opcode) == 0)) { \
3384 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3385 return; \
3386 } \
3387 gen_set_access_type(ctx, ACCESS_FLOAT); \
3388 EA = tcg_temp_new(); \
3389 gen_addr_reg_index(ctx, EA); \
3390 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3391 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3392 tcg_temp_free(EA); \
3393 }
3394
3395 #define GEN_STXF(name, stop, opc2, opc3, type) \
3396 static void glue(gen_, name##x)(DisasContext *ctx) \
3397 { \
3398 TCGv EA; \
3399 if (unlikely(!ctx->fpu_enabled)) { \
3400 gen_exception(ctx, POWERPC_EXCP_FPU); \
3401 return; \
3402 } \
3403 gen_set_access_type(ctx, ACCESS_FLOAT); \
3404 EA = tcg_temp_new(); \
3405 gen_addr_reg_index(ctx, EA); \
3406 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3407 tcg_temp_free(EA); \
3408 }
3409
3410 #define GEN_STFS(name, stop, op, type) \
3411 GEN_STF(name, stop, op | 0x20, type); \
3412 GEN_STUF(name, stop, op | 0x21, type); \
3413 GEN_STUXF(name, stop, op | 0x01, type); \
3414 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3415
3416 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3417 {
3418 TCGv_i32 t0 = tcg_temp_new_i32();
3419 TCGv t1 = tcg_temp_new();
3420 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3421 tcg_gen_extu_i32_tl(t1, t0);
3422 tcg_temp_free_i32(t0);
3423 gen_qemu_st32(ctx, t1, arg2);
3424 tcg_temp_free(t1);
3425 }
3426
3427 /* stfd stfdu stfdux stfdx */
3428 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3429 /* stfs stfsu stfsux stfsx */
3430 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3431
3432 /* Optional: */
3433 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3434 {
3435 TCGv t0 = tcg_temp_new();
3436 tcg_gen_trunc_i64_tl(t0, arg1),
3437 gen_qemu_st32(ctx, t0, arg2);
3438 tcg_temp_free(t0);
3439 }
3440 /* stfiwx */
3441 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3442
3443 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3444 {
3445 #if defined(TARGET_PPC64)
3446 if (ctx->has_cfar)
3447 tcg_gen_movi_tl(cpu_cfar, nip);
3448 #endif
3449 }
3450
3451 /*** Branch ***/
3452 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3453 {
3454 TranslationBlock *tb;
3455 tb = ctx->tb;
3456 #if defined(TARGET_PPC64)
3457 if (!ctx->sf_mode)
3458 dest = (uint32_t) dest;
3459 #endif
3460 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3461 likely(!ctx->singlestep_enabled)) {
3462 tcg_gen_goto_tb(n);
3463 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3464 tcg_gen_exit_tb((tcg_target_long)tb + n);
3465 } else {
3466 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3467 if (unlikely(ctx->singlestep_enabled)) {
3468 if ((ctx->singlestep_enabled &
3469 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3470 (ctx->exception == POWERPC_EXCP_BRANCH ||
3471 ctx->exception == POWERPC_EXCP_TRACE)) {
3472 target_ulong tmp = ctx->nip;
3473 ctx->nip = dest;
3474 gen_exception(ctx, POWERPC_EXCP_TRACE);
3475 ctx->nip = tmp;
3476 }
3477 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3478 gen_debug_exception(ctx);
3479 }
3480 }
3481 tcg_gen_exit_tb(0);
3482 }
3483 }
3484
3485 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3486 {
3487 #if defined(TARGET_PPC64)
3488 if (ctx->sf_mode == 0)
3489 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3490 else
3491 #endif
3492 tcg_gen_movi_tl(cpu_lr, nip);
3493 }
3494
3495 /* b ba bl bla */
3496 static void gen_b(DisasContext *ctx)
3497 {
3498 target_ulong li, target;
3499
3500 ctx->exception = POWERPC_EXCP_BRANCH;
3501 /* sign extend LI */
3502 #if defined(TARGET_PPC64)
3503 if (ctx->sf_mode)
3504 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3505 else
3506 #endif
3507 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3508 if (likely(AA(ctx->opcode) == 0))
3509 target = ctx->nip + li - 4;
3510 else
3511 target = li;
3512 if (LK(ctx->opcode))
3513 gen_setlr(ctx, ctx->nip);
3514 gen_update_cfar(ctx, ctx->nip);
3515 gen_goto_tb(ctx, 0, target);
3516 }
3517
3518 #define BCOND_IM 0
3519 #define BCOND_LR 1
3520 #define BCOND_CTR 2
3521
3522 static inline void gen_bcond(DisasContext *ctx, int type)
3523 {
3524 uint32_t bo = BO(ctx->opcode);
3525 int l1;
3526 TCGv target;
3527
3528 ctx->exception = POWERPC_EXCP_BRANCH;
3529 if (type == BCOND_LR || type == BCOND_CTR) {
3530 target = tcg_temp_local_new();
3531 if (type == BCOND_CTR)
3532 tcg_gen_mov_tl(target, cpu_ctr);
3533 else
3534 tcg_gen_mov_tl(target, cpu_lr);
3535 } else {
3536 TCGV_UNUSED(target);
3537 }
3538 if (LK(ctx->opcode))
3539 gen_setlr(ctx, ctx->nip);
3540 l1 = gen_new_label();
3541 if ((bo & 0x4) == 0) {
3542 /* Decrement and test CTR */
3543 TCGv temp = tcg_temp_new();
3544 if (unlikely(type == BCOND_CTR)) {
3545 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3546 return;
3547 }
3548 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3549 #if defined(TARGET_PPC64)
3550 if (!ctx->sf_mode)
3551 tcg_gen_ext32u_tl(temp, cpu_ctr);
3552 else
3553 #endif
3554 tcg_gen_mov_tl(temp, cpu_ctr);
3555 if (bo & 0x2) {
3556 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3557 } else {
3558 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3559 }
3560 tcg_temp_free(temp);
3561 }
3562 if ((bo & 0x10) == 0) {
3563 /* Test CR */
3564 uint32_t bi = BI(ctx->opcode);
3565 uint32_t mask = 1 << (3 - (bi & 0x03));
3566 TCGv_i32 temp = tcg_temp_new_i32();
3567
3568 if (bo & 0x8) {
3569 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3570 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3571 } else {
3572 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3573 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3574 }
3575 tcg_temp_free_i32(temp);
3576 }
3577 gen_update_cfar(ctx, ctx->nip);
3578 if (type == BCOND_IM) {
3579 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3580 if (likely(AA(ctx->opcode) == 0)) {
3581 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3582 } else {
3583 gen_goto_tb(ctx, 0, li);
3584 }
3585 gen_set_label(l1);
3586 gen_goto_tb(ctx, 1, ctx->nip);
3587 } else {
3588 #if defined(TARGET_PPC64)
3589 if (!(ctx->sf_mode))
3590 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3591 else
3592 #endif
3593 tcg_gen_andi_tl(cpu_nip, target, ~3);
3594 tcg_gen_exit_tb(0);
3595 gen_set_label(l1);
3596 #if defined(TARGET_PPC64)
3597 if (!(ctx->sf_mode))
3598 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3599 else
3600 #endif
3601 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3602 tcg_gen_exit_tb(0);
3603 }
3604 }
3605
3606 static void gen_bc(DisasContext *ctx)
3607 {
3608 gen_bcond(ctx, BCOND_IM);
3609 }
3610
3611 static void gen_bcctr(DisasContext *ctx)
3612 {
3613 gen_bcond(ctx, BCOND_CTR);
3614 }
3615
3616 static void gen_bclr(DisasContext *ctx)
3617 {
3618 gen_bcond(ctx, BCOND_LR);
3619 }
3620
3621 /*** Condition register logical ***/
3622 #define GEN_CRLOGIC(name, tcg_op, opc) \
3623 static void glue(gen_, name)(DisasContext *ctx) \
3624 { \
3625 uint8_t bitmask; \
3626 int sh; \
3627 TCGv_i32 t0, t1; \
3628 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3629 t0 = tcg_temp_new_i32(); \
3630 if (sh > 0) \
3631 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3632 else if (sh < 0) \
3633 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3634 else \
3635 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3636 t1 = tcg_temp_new_i32(); \
3637 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3638 if (sh > 0) \
3639 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3640 else if (sh < 0) \
3641 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3642 else \
3643 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3644 tcg_op(t0, t0, t1); \
3645 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3646 tcg_gen_andi_i32(t0, t0, bitmask); \
3647 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3648 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3649 tcg_temp_free_i32(t0); \
3650 tcg_temp_free_i32(t1); \
3651 }
3652
3653 /* crand */
3654 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3655 /* crandc */
3656 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3657 /* creqv */
3658 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3659 /* crnand */
3660 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3661 /* crnor */
3662 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3663 /* cror */
3664 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3665 /* crorc */
3666 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3667 /* crxor */
3668 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3669
3670 /* mcrf */
3671 static void gen_mcrf(DisasContext *ctx)
3672 {
3673 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3674 }
3675
3676 /*** System linkage ***/
3677
3678 /* rfi (mem_idx only) */
3679 static void gen_rfi(DisasContext *ctx)
3680 {
3681 #if defined(CONFIG_USER_ONLY)
3682 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3683 #else
3684 /* Restore CPU state */
3685 if (unlikely(!ctx->mem_idx)) {
3686 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3687 return;
3688 }
3689 gen_update_cfar(ctx, ctx->nip);
3690 gen_helper_rfi(cpu_env);
3691 gen_sync_exception(ctx);
3692 #endif
3693 }
3694
3695 #if defined(TARGET_PPC64)
3696 static void gen_rfid(DisasContext *ctx)
3697 {
3698 #if defined(CONFIG_USER_ONLY)
3699 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3700 #else
3701 /* Restore CPU state */
3702 if (unlikely(!ctx->mem_idx)) {
3703 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3704 return;
3705 }
3706 gen_update_cfar(ctx, ctx->nip);
3707 gen_helper_rfid(cpu_env);
3708 gen_sync_exception(ctx);
3709 #endif
3710 }
3711
3712 static void gen_hrfid(DisasContext *ctx)
3713 {
3714 #if defined(CONFIG_USER_ONLY)
3715 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3716 #else
3717 /* Restore CPU state */
3718 if (unlikely(ctx->mem_idx <= 1)) {
3719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3720 return;
3721 }
3722 gen_helper_hrfid(cpu_env);
3723 gen_sync_exception(ctx);
3724 #endif
3725 }
3726 #endif
3727
3728 /* sc */
3729 #if defined(CONFIG_USER_ONLY)
3730 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3731 #else
3732 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3733 #endif
3734 static void gen_sc(DisasContext *ctx)
3735 {
3736 uint32_t lev;
3737
3738 lev = (ctx->opcode >> 5) & 0x7F;
3739 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3740 }
3741
3742 /*** Trap ***/
3743
3744 /* tw */
3745 static void gen_tw(DisasContext *ctx)
3746 {
3747 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3748 /* Update the nip since this might generate a trap exception */
3749 gen_update_nip(ctx, ctx->nip);
3750 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3751 t0);
3752 tcg_temp_free_i32(t0);
3753 }
3754
3755 /* twi */
3756 static void gen_twi(DisasContext *ctx)
3757 {
3758 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3759 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3760 /* Update the nip since this might generate a trap exception */
3761 gen_update_nip(ctx, ctx->nip);
3762 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3763 tcg_temp_free(t0);
3764 tcg_temp_free_i32(t1);
3765 }
3766
3767 #if defined(TARGET_PPC64)
3768 /* td */
3769 static void gen_td(DisasContext *ctx)
3770 {
3771 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3772 /* Update the nip since this might generate a trap exception */
3773 gen_update_nip(ctx, ctx->nip);
3774 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3775 t0);
3776 tcg_temp_free_i32(t0);
3777 }
3778
3779 /* tdi */
3780 static void gen_tdi(DisasContext *ctx)
3781 {
3782 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3783 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3784 /* Update the nip since this might generate a trap exception */
3785 gen_update_nip(ctx, ctx->nip);
3786 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3787 tcg_temp_free(t0);
3788 tcg_temp_free_i32(t1);
3789 }
3790 #endif
3791
3792 /*** Processor control ***/
3793
3794 /* mcrxr */
3795 static void gen_mcrxr(DisasContext *ctx)
3796 {
3797 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3798 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3799 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3800 }
3801
3802 /* mfcr mfocrf */
3803 static void gen_mfcr(DisasContext *ctx)
3804 {
3805 uint32_t crm, crn;
3806
3807 if (likely(ctx->opcode & 0x00100000)) {
3808 crm = CRM(ctx->opcode);
3809 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3810 crn = ctz32 (crm);
3811 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3812 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3813 cpu_gpr[rD(ctx->opcode)], crn * 4);
3814 }
3815 } else {
3816 TCGv_i32 t0 = tcg_temp_new_i32();
3817 tcg_gen_mov_i32(t0, cpu_crf[0]);
3818 tcg_gen_shli_i32(t0, t0, 4);
3819 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3820 tcg_gen_shli_i32(t0, t0, 4);
3821 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3822 tcg_gen_shli_i32(t0, t0, 4);
3823 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3824 tcg_gen_shli_i32(t0, t0, 4);
3825 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3826 tcg_gen_shli_i32(t0, t0, 4);
3827 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3828 tcg_gen_shli_i32(t0, t0, 4);
3829 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3830 tcg_gen_shli_i32(t0, t0, 4);
3831 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3832 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3833 tcg_temp_free_i32(t0);
3834 }
3835 }
3836
3837 /* mfmsr */
3838 static void gen_mfmsr(DisasContext *ctx)
3839 {
3840 #if defined(CONFIG_USER_ONLY)
3841 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3842 #else
3843 if (unlikely(!ctx->mem_idx)) {
3844 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3845 return;
3846 }
3847 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3848 #endif
3849 }
3850
3851 static void spr_noaccess(void *opaque, int gprn, int sprn)
3852 {
3853 #if 0
3854 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3855 printf("ERROR: try to access SPR %d !\n", sprn);
3856 #endif
3857 }
3858 #define SPR_NOACCESS (&spr_noaccess)
3859
3860 /* mfspr */
3861 static inline void gen_op_mfspr(DisasContext *ctx)
3862 {
3863 void (*read_cb)(void *opaque, int gprn, int sprn);
3864 uint32_t sprn = SPR(ctx->opcode);
3865
3866 #if !defined(CONFIG_USER_ONLY)
3867 if (ctx->mem_idx == 2)
3868 read_cb = ctx->spr_cb[sprn].hea_read;
3869 else if (ctx->mem_idx)
3870 read_cb = ctx->spr_cb[sprn].oea_read;
3871 else
3872 #endif
3873 read_cb = ctx->spr_cb[sprn].uea_read;
3874 if (likely(read_cb != NULL)) {
3875 if (likely(read_cb != SPR_NOACCESS)) {
3876 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3877 } else {
3878 /* Privilege exception */
3879 /* This is a hack to avoid warnings when running Linux:
3880 * this OS breaks the PowerPC virtualisation model,
3881 * allowing userland application to read the PVR
3882 */
3883 if (sprn != SPR_PVR) {
3884 qemu_log("Trying to read privileged spr %d %03x at "
3885 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3886 printf("Trying to read privileged spr %d %03x at "
3887 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3888 }
3889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3890 }
3891 } else {
3892 /* Not defined */
3893 qemu_log("Trying to read invalid spr %d %03x at "
3894 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3895 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3896 sprn, sprn, ctx->nip);
3897 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3898 }
3899 }
3900
3901 static void gen_mfspr(DisasContext *ctx)
3902 {
3903 gen_op_mfspr(ctx);
3904 }
3905
3906 /* mftb */
3907 static void gen_mftb(DisasContext *ctx)
3908 {
3909 gen_op_mfspr(ctx);
3910 }
3911
3912 /* mtcrf mtocrf*/
3913 static void gen_mtcrf(DisasContext *ctx)
3914 {
3915 uint32_t crm, crn;
3916
3917 crm = CRM(ctx->opcode);
3918 if (likely((ctx->opcode & 0x00100000))) {
3919 if (crm && ((crm & (crm - 1)) == 0)) {
3920 TCGv_i32 temp = tcg_temp_new_i32();
3921 crn = ctz32 (crm);
3922 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3923 tcg_gen_shri_i32(temp, temp, crn * 4);
3924 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3925 tcg_temp_free_i32(temp);
3926 }
3927 } else {
3928 TCGv_i32 temp = tcg_temp_new_i32();
3929 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3930 for (crn = 0 ; crn < 8 ; crn++) {
3931 if (crm & (1 << crn)) {
3932 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3933 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3934 }
3935 }
3936 tcg_temp_free_i32(temp);
3937 }
3938 }
3939
3940 /* mtmsr */
3941 #if defined(TARGET_PPC64)
3942 static void gen_mtmsrd(DisasContext *ctx)
3943 {
3944 #if defined(CONFIG_USER_ONLY)
3945 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3946 #else
3947 if (unlikely(!ctx->mem_idx)) {
3948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3949 return;
3950 }
3951 if (ctx->opcode & 0x00010000) {
3952 /* Special form that does not need any synchronisation */
3953 TCGv t0 = tcg_temp_new();
3954 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3955 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3956 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3957 tcg_temp_free(t0);
3958 } else {
3959 /* XXX: we need to update nip before the store
3960 * if we enter power saving mode, we will exit the loop
3961 * directly from ppc_store_msr
3962 */
3963 gen_update_nip(ctx, ctx->nip);
3964 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3965 /* Must stop the translation as machine state (may have) changed */
3966 /* Note that mtmsr is not always defined as context-synchronizing */
3967 gen_stop_exception(ctx);
3968 }
3969 #endif
3970 }
3971 #endif
3972
3973 static void gen_mtmsr(DisasContext *ctx)
3974 {
3975 #if defined(CONFIG_USER_ONLY)
3976 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3977 #else
3978 if (unlikely(!ctx->mem_idx)) {
3979 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3980 return;
3981 }
3982 if (ctx->opcode & 0x00010000) {
3983 /* Special form that does not need any synchronisation */
3984 TCGv t0 = tcg_temp_new();
3985 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3986 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3987 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3988 tcg_temp_free(t0);
3989 } else {
3990 TCGv msr = tcg_temp_new();
3991
3992 /* XXX: we need to update nip before the store
3993 * if we enter power saving mode, we will exit the loop
3994 * directly from ppc_store_msr
3995 */
3996 gen_update_nip(ctx, ctx->nip);
3997 #if defined(TARGET_PPC64)
3998 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3999 #else
4000 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4001 #endif
4002 gen_helper_store_msr(cpu_env, msr);
4003 /* Must stop the translation as machine state (may have) changed */
4004 /* Note that mtmsr is not always defined as context-synchronizing */
4005 gen_stop_exception(ctx);
4006 }
4007 #endif
4008 }
4009
4010 /* mtspr */
4011 static void gen_mtspr(DisasContext *ctx)
4012 {
4013 void (*write_cb)(void *opaque, int sprn, int gprn);
4014 uint32_t sprn = SPR(ctx->opcode);
4015
4016 #if !defined(CONFIG_USER_ONLY)
4017 if (ctx->mem_idx == 2)
4018 write_cb = ctx->spr_cb[sprn].hea_write;
4019 else if (ctx->mem_idx)
4020 write_cb = ctx->spr_cb[sprn].oea_write;
4021 else
4022 #endif
4023 write_cb = ctx->spr_cb[sprn].uea_write;
4024 if (likely(write_cb != NULL)) {
4025 if (likely(write_cb != SPR_NOACCESS)) {
4026 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4027 } else {
4028 /* Privilege exception */
4029 qemu_log("Trying to write privileged spr %d %03x at "
4030 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4031 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
4032 "\n", sprn, sprn, ctx->nip);
4033 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4034 }
4035 } else {
4036 /* Not defined */
4037 qemu_log("Trying to write invalid spr %d %03x at "
4038 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4039 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
4040 sprn, sprn, ctx->nip);
4041 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4042 }
4043 }
4044
4045 /*** Cache management ***/
4046
4047 /* dcbf */
4048 static void gen_dcbf(DisasContext *ctx)
4049 {
4050 /* XXX: specification says this is treated as a load by the MMU */
4051 TCGv t0;
4052 gen_set_access_type(ctx, ACCESS_CACHE);
4053 t0 = tcg_temp_new();
4054 gen_addr_reg_index(ctx, t0);
4055 gen_qemu_ld8u(ctx, t0, t0);
4056 tcg_temp_free(t0);
4057 }
4058
4059 /* dcbi (Supervisor only) */
4060 static void gen_dcbi(DisasContext *ctx)
4061 {
4062 #if defined(CONFIG_USER_ONLY)
4063 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4064 #else
4065 TCGv EA, val;
4066 if (unlikely(!ctx->mem_idx)) {
4067 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4068 return;
4069 }
4070 EA = tcg_temp_new();
4071 gen_set_access_type(ctx, ACCESS_CACHE);
4072 gen_addr_reg_index(ctx, EA);
4073 val = tcg_temp_new();
4074 /* XXX: specification says this should be treated as a store by the MMU */
4075 gen_qemu_ld8u(ctx, val, EA);
4076 gen_qemu_st8(ctx, val, EA);
4077 tcg_temp_free(val);
4078 tcg_temp_free(EA);
4079 #endif
4080 }
4081
4082 /* dcdst */
4083 static void gen_dcbst(DisasContext *ctx)
4084 {
4085 /* XXX: specification say this is treated as a load by the MMU */
4086 TCGv t0;
4087 gen_set_access_type(ctx, ACCESS_CACHE);
4088 t0 = tcg_temp_new();
4089 gen_addr_reg_index(ctx, t0);
4090 gen_qemu_ld8u(ctx, t0, t0);
4091 tcg_temp_free(t0);
4092 }
4093
4094 /* dcbt */
4095 static void gen_dcbt(DisasContext *ctx)
4096 {
4097 /* interpreted as no-op */
4098 /* XXX: specification say this is treated as a load by the MMU
4099 * but does not generate any exception
4100 */
4101 }
4102
4103 /* dcbtst */
4104 static void gen_dcbtst(DisasContext *ctx)
4105 {
4106 /* interpreted as no-op */
4107 /* XXX: specification say this is treated as a load by the MMU
4108 * but does not generate any exception
4109 */
4110 }
4111
4112 /* dcbz */
4113 static void gen_dcbz(DisasContext *ctx)
4114 {
4115 TCGv tcgv_addr;
4116 TCGv_i32 tcgv_is_dcbzl;
4117 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4118
4119 gen_set_access_type(ctx, ACCESS_CACHE);
4120 /* NIP cannot be restored if the memory exception comes from an helper */
4121 gen_update_nip(ctx, ctx->nip - 4);
4122 tcgv_addr = tcg_temp_new();
4123 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4124
4125 gen_addr_reg_index(ctx, tcgv_addr);
4126 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4127
4128 tcg_temp_free(tcgv_addr);
4129 tcg_temp_free_i32(tcgv_is_dcbzl);
4130 }
4131
4132 /* dst / dstt */
4133 static void gen_dst(DisasContext *ctx)
4134 {
4135 if (rA(ctx->opcode) == 0) {
4136 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4137 } else {
4138 /* interpreted as no-op */
4139 }
4140 }
4141
4142 /* dstst /dststt */
4143 static void gen_dstst(DisasContext *ctx)
4144 {
4145 if (rA(ctx->opcode) == 0) {
4146 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4147 } else {
4148 /* interpreted as no-op */
4149 }
4150
4151 }
4152
4153 /* dss / dssall */
4154 static void gen_dss(DisasContext *ctx)
4155 {
4156 /* interpreted as no-op */
4157 }
4158
4159 /* icbi */
4160 static void gen_icbi(DisasContext *ctx)
4161 {
4162 TCGv t0;
4163 gen_set_access_type(ctx, ACCESS_CACHE);
4164 /* NIP cannot be restored if the memory exception comes from an helper */
4165 gen_update_nip(ctx, ctx->nip - 4);
4166 t0 = tcg_temp_new();
4167 gen_addr_reg_index(ctx, t0);
4168 gen_helper_icbi(cpu_env, t0);
4169 tcg_temp_free(t0);
4170 }
4171
4172 /* Optional: */
4173 /* dcba */
4174 static void gen_dcba(DisasContext *ctx)
4175 {
4176 /* interpreted as no-op */
4177 /* XXX: specification say this is treated as a store by the MMU
4178 * but does not generate any exception
4179 */
4180 }
4181
4182 /*** Segment register manipulation ***/
4183 /* Supervisor only: */
4184
4185 /* mfsr */
4186 static void gen_mfsr(DisasContext *ctx)
4187 {
4188 #if defined(CONFIG_USER_ONLY)
4189 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4190 #else
4191 TCGv t0;
4192 if (unlikely(!ctx->mem_idx)) {
4193 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4194 return;
4195 }
4196 t0 = tcg_const_tl(SR(ctx->opcode));
4197 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4198 tcg_temp_free(t0);
4199 #endif
4200 }
4201
4202 /* mfsrin */
4203 static void gen_mfsrin(DisasContext *ctx)
4204 {
4205 #if defined(CONFIG_USER_ONLY)
4206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4207 #else
4208 TCGv t0;
4209 if (unlikely(!ctx->mem_idx)) {
4210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4211 return;
4212 }
4213 t0 = tcg_temp_new();
4214 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4215 tcg_gen_andi_tl(t0, t0, 0xF);
4216 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4217 tcg_temp_free(t0);
4218 #endif
4219 }
4220
4221 /* mtsr */
4222 static void gen_mtsr(DisasContext *ctx)
4223 {
4224 #if defined(CONFIG_USER_ONLY)
4225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4226 #else
4227 TCGv t0;
4228 if (unlikely(!ctx->mem_idx)) {
4229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4230 return;
4231 }
4232 t0 = tcg_const_tl(SR(ctx->opcode));
4233 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4234 tcg_temp_free(t0);
4235 #endif
4236 }
4237
4238 /* mtsrin */
4239 static void gen_mtsrin(DisasContext *ctx)
4240 {
4241 #if defined(CONFIG_USER_ONLY)
4242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4243 #else
4244 TCGv t0;
4245 if (unlikely(!ctx->mem_idx)) {
4246 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4247 return;
4248 }
4249 t0 = tcg_temp_new();
4250 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4251 tcg_gen_andi_tl(t0, t0, 0xF);
4252 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4253 tcg_temp_free(t0);
4254 #endif
4255 }
4256
4257 #if defined(TARGET_PPC64)
4258 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4259
4260 /* mfsr */
4261 static void gen_mfsr_64b(DisasContext *ctx)
4262 {
4263 #if defined(CONFIG_USER_ONLY)
4264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4265 #else
4266 TCGv t0;
4267 if (unlikely(!ctx->mem_idx)) {
4268 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4269 return;
4270 }
4271 t0 = tcg_const_tl(SR(ctx->opcode));
4272 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4273 tcg_temp_free(t0);
4274 #endif
4275 }
4276
4277 /* mfsrin */
4278 static void gen_mfsrin_64b(DisasContext *ctx)
4279 {
4280 #if defined(CONFIG_USER_ONLY)
4281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4282 #else
4283 TCGv t0;
4284 if (unlikely(!ctx->mem_idx)) {
4285 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4286 return;
4287 }
4288 t0 = tcg_temp_new();
4289 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4290 tcg_gen_andi_tl(t0, t0, 0xF);
4291 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4292 tcg_temp_free(t0);
4293 #endif
4294 }
4295
4296 /* mtsr */
4297 static void gen_mtsr_64b(DisasContext *ctx)
4298 {
4299 #if defined(CONFIG_USER_ONLY)
4300 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4301 #else
4302 TCGv t0;
4303 if (unlikely(!ctx->mem_idx)) {
4304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4305 return;
4306 }
4307 t0 = tcg_const_tl(SR(ctx->opcode));
4308 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4309 tcg_temp_free(t0);
4310 #endif
4311 }
4312
4313 /* mtsrin */
4314 static void gen_mtsrin_64b(DisasContext *ctx)
4315 {
4316 #if defined(CONFIG_USER_ONLY)
4317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4318 #else
4319 TCGv t0;
4320 if (unlikely(!ctx->mem_idx)) {
4321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4322 return;
4323 }
4324 t0 = tcg_temp_new();
4325 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4326 tcg_gen_andi_tl(t0, t0, 0xF);
4327 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4328 tcg_temp_free(t0);
4329 #endif
4330 }
4331
4332 /* slbmte */
4333 static void gen_slbmte(DisasContext *ctx)
4334 {
4335 #if defined(CONFIG_USER_ONLY)
4336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4337 #else
4338 if (unlikely(!ctx->mem_idx)) {
4339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4340 return;
4341 }
4342 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4343 cpu_gpr[rS(ctx->opcode)]);
4344 #endif
4345 }
4346
4347 static void gen_slbmfee(DisasContext *ctx)
4348 {
4349 #if defined(CONFIG_USER_ONLY)
4350 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4351 #else
4352 if (unlikely(!ctx->mem_idx)) {
4353 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4354 return;
4355 }
4356 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4357 cpu_gpr[rB(ctx->opcode)]);
4358 #endif
4359 }
4360
4361 static void gen_slbmfev(DisasContext *ctx)
4362 {
4363 #if defined(CONFIG_USER_ONLY)
4364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4365 #else
4366 if (unlikely(!ctx->mem_idx)) {
4367 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4368 return;
4369 }
4370 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4371 cpu_gpr[rB(ctx->opcode)]);
4372 #endif
4373 }
4374 #endif /* defined(TARGET_PPC64) */
4375
4376 /*** Lookaside buffer management ***/
4377 /* Optional & mem_idx only: */
4378
4379 /* tlbia */
4380 static void gen_tlbia(DisasContext *ctx)
4381 {
4382 #if defined(CONFIG_USER_ONLY)
4383 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4384 #else
4385 if (unlikely(!ctx->mem_idx)) {
4386 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4387 return;
4388 }
4389 gen_helper_tlbia(cpu_env);
4390 #endif
4391 }
4392
4393 /* tlbiel */
4394 static void gen_tlbiel(DisasContext *ctx)
4395 {
4396 #if defined(CONFIG_USER_ONLY)
4397 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4398 #else
4399 if (unlikely(!ctx->mem_idx)) {
4400 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4401 return;
4402 }
4403 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4404 #endif
4405 }
4406
4407 /* tlbie */
4408 static void gen_tlbie(DisasContext *ctx)
4409 {
4410 #if defined(CONFIG_USER_ONLY)
4411 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4412 #else
4413 if (unlikely(!ctx->mem_idx)) {
4414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4415 return;
4416 }
4417 #if defined(TARGET_PPC64)
4418 if (!ctx->sf_mode) {
4419 TCGv t0 = tcg_temp_new();
4420 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4421 gen_helper_tlbie(cpu_env, t0);
4422 tcg_temp_free(t0);
4423 } else
4424 #endif
4425 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4426 #endif
4427 }
4428
4429 /* tlbsync */
4430 static void gen_tlbsync(DisasContext *ctx)
4431 {
4432 #if defined(CONFIG_USER_ONLY)
4433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4434 #else
4435 if (unlikely(!ctx->mem_idx)) {
4436 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4437 return;
4438 }
4439 /* This has no effect: it should ensure that all previous
4440 * tlbie have completed
4441 */
4442 gen_stop_exception(ctx);
4443 #endif
4444 }
4445
4446 #if defined(TARGET_PPC64)
4447 /* slbia */
4448 static void gen_slbia(DisasContext *ctx)
4449 {
4450 #if defined(CONFIG_USER_ONLY)
4451 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4452 #else
4453 if (unlikely(!ctx->mem_idx)) {
4454 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4455 return;
4456 }
4457 gen_helper_slbia(cpu_env);
4458 #endif
4459 }
4460
4461 /* slbie */
4462 static void gen_slbie(DisasContext *ctx)
4463 {
4464 #if defined(CONFIG_USER_ONLY)
4465 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4466 #else
4467 if (unlikely(!ctx->mem_idx)) {
4468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4469 return;
4470 }
4471 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4472 #endif
4473 }
4474 #endif
4475
4476 /*** External control ***/
4477 /* Optional: */
4478
4479 /* eciwx */
4480 static void gen_eciwx(DisasContext *ctx)
4481 {
4482 TCGv t0;
4483 /* Should check EAR[E] ! */
4484 gen_set_access_type(ctx, ACCESS_EXT);
4485 t0 = tcg_temp_new();
4486 gen_addr_reg_index(ctx, t0);
4487 gen_check_align(ctx, t0, 0x03);
4488 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4489 tcg_temp_free(t0);
4490 }
4491
4492 /* ecowx */
4493 static void gen_ecowx(DisasContext *ctx)
4494 {
4495 TCGv t0;
4496 /* Should check EAR[E] ! */
4497 gen_set_access_type(ctx, ACCESS_EXT);
4498 t0 = tcg_temp_new();
4499 gen_addr_reg_index(ctx, t0);
4500 gen_check_align(ctx, t0, 0x03);
4501 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4502 tcg_temp_free(t0);
4503 }
4504
4505 /* PowerPC 601 specific instructions */
4506
4507 /* abs - abs. */
4508 static void gen_abs(DisasContext *ctx)
4509 {
4510 int l1 = gen_new_label();
4511 int l2 = gen_new_label();
4512 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4513 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4514 tcg_gen_br(l2);
4515 gen_set_label(l1);
4516 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4517 gen_set_label(l2);
4518 if (unlikely(Rc(ctx->opcode) != 0))
4519 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4520 }
4521
4522 /* abso - abso. */
4523 static void gen_abso(DisasContext *ctx)
4524 {
4525 int l1 = gen_new_label();
4526 int l2 = gen_new_label();
4527 int l3 = gen_new_label();
4528 /* Start with XER OV disabled, the most likely case */
4529 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4530 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4531 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4532 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4533 tcg_gen_br(l2);
4534 gen_set_label(l1);
4535 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4536 tcg_gen_br(l3);
4537 gen_set_label(l2);
4538 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4539 gen_set_label(l3);
4540 if (unlikely(Rc(ctx->opcode) != 0))
4541 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4542 }
4543
4544 /* clcs */
4545 static void gen_clcs(DisasContext *ctx)
4546 {
4547 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4548 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4549 tcg_temp_free_i32(t0);
4550 /* Rc=1 sets CR0 to an undefined state */
4551 }
4552
4553 /* div - div. */
4554 static void gen_div(DisasContext *ctx)
4555 {
4556 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4557 cpu_gpr[rB(ctx->opcode)]);
4558 if (unlikely(Rc(ctx->opcode) != 0))
4559 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4560 }
4561
4562 /* divo - divo. */
4563 static void gen_divo(DisasContext *ctx)
4564 {
4565 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4566 cpu_gpr[rB(ctx->opcode)]);
4567 if (unlikely(Rc(ctx->opcode) != 0))
4568 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4569 }
4570
4571 /* divs - divs. */
4572 static void gen_divs(DisasContext *ctx)
4573 {
4574 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4575 cpu_gpr[rB(ctx->opcode)]);
4576 if (unlikely(Rc(ctx->opcode) != 0))
4577 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4578 }
4579
4580 /* divso - divso. */
4581 static void gen_divso(DisasContext *ctx)
4582 {
4583 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4584 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4585 if (unlikely(Rc(ctx->opcode) != 0))
4586 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4587 }
4588
4589 /* doz - doz. */
4590 static void gen_doz(DisasContext *ctx)
4591 {
4592 int l1 = gen_new_label();
4593 int l2 = gen_new_label();
4594 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4595 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4596 tcg_gen_br(l2);
4597 gen_set_label(l1);
4598 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4599 gen_set_label(l2);
4600 if (unlikely(Rc(ctx->opcode) != 0))
4601 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4602 }
4603
4604 /* dozo - dozo. */
4605 static void gen_dozo(DisasContext *ctx)
4606 {
4607 int l1 = gen_new_label();
4608 int l2 = gen_new_label();
4609 TCGv t0 = tcg_temp_new();
4610 TCGv t1 = tcg_temp_new();
4611 TCGv t2 = tcg_temp_new();
4612 /* Start with XER OV disabled, the most likely case */
4613 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4614 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4615 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4616 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4617 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4618 tcg_gen_andc_tl(t1, t1, t2);
4619 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4620 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4621 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4622 tcg_gen_br(l2);
4623 gen_set_label(l1);
4624 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4625 gen_set_label(l2);
4626 tcg_temp_free(t0);
4627 tcg_temp_free(t1);
4628 tcg_temp_free(t2);
4629 if (unlikely(Rc(ctx->opcode) != 0))
4630 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4631 }
4632
4633 /* dozi */
4634 static void gen_dozi(DisasContext *ctx)
4635 {
4636 target_long simm = SIMM(ctx->opcode);
4637 int l1 = gen_new_label();
4638 int l2 = gen_new_label();
4639 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4640 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4641 tcg_gen_br(l2);
4642 gen_set_label(l1);
4643 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4644 gen_set_label(l2);
4645 if (unlikely(Rc(ctx->opcode) != 0))
4646 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4647 }
4648
4649 /* lscbx - lscbx. */
4650 static void gen_lscbx(DisasContext *ctx)
4651 {
4652 TCGv t0 = tcg_temp_new();
4653 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4654 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4655 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4656
4657 gen_addr_reg_index(ctx, t0);
4658 /* NIP cannot be restored if the memory exception comes from an helper */
4659 gen_update_nip(ctx, ctx->nip - 4);
4660 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4661 tcg_temp_free_i32(t1);
4662 tcg_temp_free_i32(t2);
4663 tcg_temp_free_i32(t3);
4664 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4665 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4666 if (unlikely(Rc(ctx->opcode) != 0))
4667 gen_set_Rc0(ctx, t0);
4668 tcg_temp_free(t0);
4669 }
4670
4671 /* maskg - maskg. */
4672 static void gen_maskg(DisasContext *ctx)
4673 {
4674 int l1 = gen_new_label();
4675 TCGv t0 = tcg_temp_new();
4676 TCGv t1 = tcg_temp_new();
4677 TCGv t2 = tcg_temp_new();
4678 TCGv t3 = tcg_temp_new();
4679 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4680 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4681 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4682 tcg_gen_addi_tl(t2, t0, 1);
4683 tcg_gen_shr_tl(t2, t3, t2);
4684 tcg_gen_shr_tl(t3, t3, t1);
4685 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4686 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4687 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4688 gen_set_label(l1);
4689 tcg_temp_free(t0);
4690 tcg_temp_free(t1);
4691 tcg_temp_free(t2);
4692 tcg_temp_free(t3);
4693 if (unlikely(Rc(ctx->opcode) != 0))
4694 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4695 }
4696
4697 /* maskir - maskir. */
4698 static void gen_maskir(DisasContext *ctx)
4699 {
4700 TCGv t0 = tcg_temp_new();
4701 TCGv t1 = tcg_temp_new();
4702 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4703 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4704 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4705 tcg_temp_free(t0);
4706 tcg_temp_free(t1);
4707 if (unlikely(Rc(ctx->opcode) != 0))
4708 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4709 }
4710
4711 /* mul - mul. */
4712 static void gen_mul(DisasContext *ctx)
4713 {
4714 TCGv_i64 t0 = tcg_temp_new_i64();
4715 TCGv_i64 t1 = tcg_temp_new_i64();
4716 TCGv t2 = tcg_temp_new();
4717 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4718 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4719 tcg_gen_mul_i64(t0, t0, t1);
4720 tcg_gen_trunc_i64_tl(t2, t0);
4721 gen_store_spr(SPR_MQ, t2);
4722 tcg_gen_shri_i64(t1, t0, 32);
4723 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4724 tcg_temp_free_i64(t0);
4725 tcg_temp_free_i64(t1);
4726 tcg_temp_free(t2);
4727 if (unlikely(Rc(ctx->opcode) != 0))
4728 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4729 }
4730
4731 /* mulo - mulo. */
4732 static void gen_mulo(DisasContext *ctx)
4733 {
4734 int l1 = gen_new_label();
4735 TCGv_i64 t0 = tcg_temp_new_i64();
4736 TCGv_i64 t1 = tcg_temp_new_i64();
4737 TCGv t2 = tcg_temp_new();
4738 /* Start with XER OV disabled, the most likely case */
4739 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4740 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4741 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4742 tcg_gen_mul_i64(t0, t0, t1);
4743 tcg_gen_trunc_i64_tl(t2, t0);
4744 gen_store_spr(SPR_MQ, t2);
4745 tcg_gen_shri_i64(t1, t0, 32);
4746 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4747 tcg_gen_ext32s_i64(t1, t0);
4748 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4749 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4750 gen_set_label(l1);
4751 tcg_temp_free_i64(t0);
4752 tcg_temp_free_i64(t1);
4753 tcg_temp_free(t2);
4754 if (unlikely(Rc(ctx->opcode) != 0))
4755 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4756 }
4757
4758 /* nabs - nabs. */
4759 static void gen_nabs(DisasContext *ctx)
4760 {
4761 int l1 = gen_new_label();
4762 int l2 = gen_new_label();
4763 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4764 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4765 tcg_gen_br(l2);
4766 gen_set_label(l1);
4767 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4768 gen_set_label(l2);
4769 if (unlikely(Rc(ctx->opcode) != 0))
4770 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4771 }
4772
4773 /* nabso - nabso. */
4774 static void gen_nabso(DisasContext *ctx)
4775 {
4776 int l1 = gen_new_label();
4777 int l2 = gen_new_label();
4778 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4779 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4780 tcg_gen_br(l2);
4781 gen_set_label(l1);
4782 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4783 gen_set_label(l2);
4784 /* nabs never overflows */
4785 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4786 if (unlikely(Rc(ctx->opcode) != 0))
4787 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4788 }
4789
4790 /* rlmi - rlmi. */
4791 static void gen_rlmi(DisasContext *ctx)
4792 {
4793 uint32_t mb = MB(ctx->opcode);
4794 uint32_t me = ME(ctx->opcode);
4795 TCGv t0 = tcg_temp_new();
4796 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4797 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4798 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4799 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4800 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4801 tcg_temp_free(t0);
4802 if (unlikely(Rc(ctx->opcode) != 0))
4803 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4804 }
4805
4806 /* rrib - rrib. */
4807 static void gen_rrib(DisasContext *ctx)
4808 {
4809 TCGv t0 = tcg_temp_new();
4810 TCGv t1 = tcg_temp_new();
4811 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4812 tcg_gen_movi_tl(t1, 0x80000000);
4813 tcg_gen_shr_tl(t1, t1, t0);
4814 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4815 tcg_gen_and_tl(t0, t0, t1);
4816 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4817 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4818 tcg_temp_free(t0);
4819 tcg_temp_free(t1);
4820 if (unlikely(Rc(ctx->opcode) != 0))
4821 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4822 }
4823
4824 /* sle - sle. */
4825 static void gen_sle(DisasContext *ctx)
4826 {
4827 TCGv t0 = tcg_temp_new();
4828 TCGv t1 = tcg_temp_new();
4829 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4830 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4831 tcg_gen_subfi_tl(t1, 32, t1);
4832 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4833 tcg_gen_or_tl(t1, t0, t1);
4834 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4835 gen_store_spr(SPR_MQ, t1);
4836 tcg_temp_free(t0);
4837 tcg_temp_free(t1);
4838 if (unlikely(Rc(ctx->opcode) != 0))
4839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4840 }
4841
4842 /* sleq - sleq. */
4843 static void gen_sleq(DisasContext *ctx)
4844 {
4845 TCGv t0 = tcg_temp_new();
4846 TCGv t1 = tcg_temp_new();
4847 TCGv t2 = tcg_temp_new();
4848 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4849 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4850 tcg_gen_shl_tl(t2, t2, t0);
4851 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4852 gen_load_spr(t1, SPR_MQ);
4853 gen_store_spr(SPR_MQ, t0);
4854 tcg_gen_and_tl(t0, t0, t2);
4855 tcg_gen_andc_tl(t1, t1, t2);
4856 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4857 tcg_temp_free(t0);
4858 tcg_temp_free(t1);
4859 tcg_temp_free(t2);
4860 if (unlikely(Rc(ctx->opcode) != 0))
4861 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4862 }
4863
4864 /* sliq - sliq. */
4865 static void gen_sliq(DisasContext *ctx)
4866 {
4867 int sh = SH(ctx->opcode);
4868 TCGv t0 = tcg_temp_new();
4869 TCGv t1 = tcg_temp_new();
4870 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4871 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4872 tcg_gen_or_tl(t1, t0, t1);
4873 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4874 gen_store_spr(SPR_MQ, t1);
4875 tcg_temp_free(t0);
4876 tcg_temp_free(t1);
4877 if (unlikely(Rc(ctx->opcode) != 0))
4878 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4879 }
4880
4881 /* slliq - slliq. */
4882 static void gen_slliq(DisasContext *ctx)
4883 {
4884 int sh = SH(ctx->opcode);
4885 TCGv t0 = tcg_temp_new();
4886 TCGv t1 = tcg_temp_new();
4887 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4888 gen_load_spr(t1, SPR_MQ);
4889 gen_store_spr(SPR_MQ, t0);
4890 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4891 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4892 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4893 tcg_temp_free(t0);
4894 tcg_temp_free(t1);
4895 if (unlikely(Rc(ctx->opcode) != 0))
4896 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4897 }
4898
4899 /* sllq - sllq. */
4900 static void gen_sllq(DisasContext *ctx)
4901 {
4902 int l1 = gen_new_label();
4903 int l2 = gen_new_label();
4904 TCGv t0 = tcg_temp_local_new();
4905 TCGv t1 = tcg_temp_local_new();
4906 TCGv t2 = tcg_temp_local_new();
4907 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4908 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4909 tcg_gen_shl_tl(t1, t1, t2);
4910 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4911 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4912 gen_load_spr(t0, SPR_MQ);
4913 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4914 tcg_gen_br(l2);
4915 gen_set_label(l1);
4916 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4917 gen_load_spr(t2, SPR_MQ);
4918 tcg_gen_andc_tl(t1, t2, t1);
4919 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4920 gen_set_label(l2);
4921 tcg_temp_free(t0);
4922 tcg_temp_free(t1);
4923 tcg_temp_free(t2);
4924 if (unlikely(Rc(ctx->opcode) != 0))
4925 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4926 }
4927
4928 /* slq - slq. */
4929 static void gen_slq(DisasContext *ctx)
4930 {
4931 int l1 = gen_new_label();
4932 TCGv t0 = tcg_temp_new();
4933 TCGv t1 = tcg_temp_new();
4934 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4935 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4936 tcg_gen_subfi_tl(t1, 32, t1);
4937 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4938 tcg_gen_or_tl(t1, t0, t1);
4939 gen_store_spr(SPR_MQ, t1);
4940 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4941 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4942 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4943 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4944 gen_set_label(l1);
4945 tcg_temp_free(t0);
4946 tcg_temp_free(t1);
4947 if (unlikely(Rc(ctx->opcode) != 0))
4948 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4949 }
4950
4951 /* sraiq - sraiq. */
4952 static void gen_sraiq(DisasContext *ctx)
4953 {
4954 int sh = SH(ctx->opcode);
4955 int l1 = gen_new_label();
4956 TCGv t0 = tcg_temp_new();
4957 TCGv t1 = tcg_temp_new();
4958 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4959 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4960 tcg_gen_or_tl(t0, t0, t1);
4961 gen_store_spr(SPR_MQ, t0);
4962 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4963 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4964 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4965 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4966 gen_set_label(l1);
4967 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4968 tcg_temp_free(t0);
4969 tcg_temp_free(t1);
4970 if (unlikely(Rc(ctx->opcode) != 0))
4971 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4972 }
4973
4974 /* sraq - sraq. */
4975 static void gen_sraq(DisasContext *ctx)
4976 {
4977 int l1 = gen_new_label();
4978 int l2 = gen_new_label();
4979 TCGv t0 = tcg_temp_new();
4980 TCGv t1 = tcg_temp_local_new();
4981 TCGv t2 = tcg_temp_local_new();
4982 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4983 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4984 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4985 tcg_gen_subfi_tl(t2, 32, t2);
4986 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4987 tcg_gen_or_tl(t0, t0, t2);
4988 gen_store_spr(SPR_MQ, t0);
4989 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4990 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4991 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4992 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4993 gen_set_label(l1);
4994 tcg_temp_free(t0);
4995 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4996 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4997 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4998 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4999 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
5000 gen_set_label(l2);
5001 tcg_temp_free(t1);
5002 tcg_temp_free(t2);
5003 if (unlikely(Rc(ctx->opcode) != 0))
5004 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5005 }
5006
5007 /* sre - sre. */
5008 static void gen_sre(DisasContext *ctx)
5009 {
5010 TCGv t0 = tcg_temp_new();
5011 TCGv t1 = tcg_temp_new();
5012 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5013 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5014 tcg_gen_subfi_tl(t1, 32, t1);
5015 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5016 tcg_gen_or_tl(t1, t0, t1);
5017 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5018 gen_store_spr(SPR_MQ, t1);
5019 tcg_temp_free(t0);
5020 tcg_temp_free(t1);
5021 if (unlikely(Rc(ctx->opcode) != 0))
5022 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5023 }
5024
5025 /* srea - srea. */
5026 static void gen_srea(DisasContext *ctx)
5027 {
5028 TCGv t0 = tcg_temp_new();
5029 TCGv t1 = tcg_temp_new();
5030 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5031 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5032 gen_store_spr(SPR_MQ, t0);
5033 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5034 tcg_temp_free(t0);
5035 tcg_temp_free(t1);
5036 if (unlikely(Rc(ctx->opcode) != 0))
5037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5038 }
5039
5040 /* sreq */
5041 static void gen_sreq(DisasContext *ctx)
5042 {
5043 TCGv t0 = tcg_temp_new();
5044 TCGv t1 = tcg_temp_new();
5045 TCGv t2 = tcg_temp_new();
5046 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5047 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5048 tcg_gen_shr_tl(t1, t1, t0);
5049 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5050 gen_load_spr(t2, SPR_MQ);
5051 gen_store_spr(SPR_MQ, t0);
5052 tcg_gen_and_tl(t0, t0, t1);
5053 tcg_gen_andc_tl(t2, t2, t1);
5054 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5055 tcg_temp_free(t0);
5056 tcg_temp_free(t1);
5057 tcg_temp_free(t2);
5058 if (unlikely(Rc(ctx->opcode) != 0))
5059 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5060 }
5061
5062 /* sriq */
5063 static void gen_sriq(DisasContext *ctx)
5064 {
5065 int sh = SH(ctx->opcode);
5066 TCGv t0 = tcg_temp_new();
5067 TCGv t1 = tcg_temp_new();
5068 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5069 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5070 tcg_gen_or_tl(t1, t0, t1);
5071 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5072 gen_store_spr(SPR_MQ, t1);
5073 tcg_temp_free(t0);
5074 tcg_temp_free(t1);
5075 if (unlikely(Rc(ctx->opcode) != 0))
5076 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5077 }
5078
5079 /* srliq */
5080 static void gen_srliq(DisasContext *ctx)
5081 {
5082 int sh = SH(ctx->opcode);
5083 TCGv t0 = tcg_temp_new();
5084 TCGv t1 = tcg_temp_new();
5085 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5086 gen_load_spr(t1, SPR_MQ);
5087 gen_store_spr(SPR_MQ, t0);
5088 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5089 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5090 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5091 tcg_temp_free(t0);
5092 tcg_temp_free(t1);
5093 if (unlikely(Rc(ctx->opcode) != 0))
5094 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5095 }
5096
5097 /* srlq */
5098 static void gen_srlq(DisasContext *ctx)
5099 {
5100 int l1 = gen_new_label();
5101 int l2 = gen_new_label();
5102 TCGv t0 = tcg_temp_local_new();
5103 TCGv t1 = tcg_temp_local_new();
5104 TCGv t2 = tcg_temp_local_new();
5105 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5106 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5107 tcg_gen_shr_tl(t2, t1, t2);
5108 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5109 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5110 gen_load_spr(t0, SPR_MQ);
5111 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5112 tcg_gen_br(l2);
5113 gen_set_label(l1);
5114 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5115 tcg_gen_and_tl(t0, t0, t2);
5116 gen_load_spr(t1, SPR_MQ);
5117 tcg_gen_andc_tl(t1, t1, t2);
5118 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5119 gen_set_label(l2);
5120 tcg_temp_free(t0);
5121 tcg_temp_free(t1);
5122 tcg_temp_free(t2);
5123 if (unlikely(Rc(ctx->opcode) != 0))
5124 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5125 }
5126
5127 /* srq */
5128 static void gen_srq(DisasContext *ctx)
5129 {
5130 int l1 = gen_new_label();
5131 TCGv t0 = tcg_temp_new();
5132 TCGv t1 = tcg_temp_new();
5133 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5134 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5135 tcg_gen_subfi_tl(t1, 32, t1);
5136 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5137 tcg_gen_or_tl(t1, t0, t1);
5138 gen_store_spr(SPR_MQ, t1);
5139 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5140 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5141 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5142 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5143 gen_set_label(l1);
5144 tcg_temp_free(t0);
5145 tcg_temp_free(t1);
5146 if (unlikely(Rc(ctx->opcode) != 0))
5147 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5148 }
5149
5150 /* PowerPC 602 specific instructions */
5151
5152 /* dsa */
5153 static void gen_dsa(DisasContext *ctx)
5154 {
5155 /* XXX: TODO */
5156 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5157 }
5158
5159 /* esa */
5160 static void gen_esa(DisasContext *ctx)
5161 {
5162 /* XXX: TODO */
5163 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5164 }
5165
5166 /* mfrom */
5167 static void gen_mfrom(DisasContext *ctx)
5168 {
5169 #if defined(CONFIG_USER_ONLY)
5170 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5171 #else
5172 if (unlikely(!ctx->mem_idx)) {
5173 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5174 return;
5175 }
5176 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5177 #endif
5178 }
5179
5180 /* 602 - 603 - G2 TLB management */
5181
5182 /* tlbld */
5183 static void gen_tlbld_6xx(DisasContext *ctx)
5184 {
5185 #if defined(CONFIG_USER_ONLY)
5186 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5187 #else
5188 if (unlikely(!ctx->mem_idx)) {
5189 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5190 return;
5191 }
5192 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5193 #endif
5194 }
5195
5196 /* tlbli */
5197 static void gen_tlbli_6xx(DisasContext *ctx)
5198 {
5199 #if defined(CONFIG_USER_ONLY)
5200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5201 #else
5202 if (unlikely(!ctx->mem_idx)) {
5203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5204 return;
5205 }
5206 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5207 #endif
5208 }
5209
5210 /* 74xx TLB management */
5211
5212 /* tlbld */
5213 static void gen_tlbld_74xx(DisasContext *ctx)
5214 {
5215 #if defined(CONFIG_USER_ONLY)
5216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5217 #else
5218 if (unlikely(!ctx->mem_idx)) {
5219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5220 return;
5221 }
5222 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5223 #endif
5224 }
5225
5226 /* tlbli */
5227 static void gen_tlbli_74xx(DisasContext *ctx)
5228 {
5229 #if defined(CONFIG_USER_ONLY)
5230 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5231 #else
5232 if (unlikely(!ctx->mem_idx)) {
5233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5234 return;
5235 }
5236 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5237 #endif
5238 }
5239
5240 /* POWER instructions not in PowerPC 601 */
5241
5242 /* clf */
5243 static void gen_clf(DisasContext *ctx)
5244 {
5245 /* Cache line flush: implemented as no-op */
5246 }
5247
5248 /* cli */
5249 static void gen_cli(DisasContext *ctx)
5250 {
5251 /* Cache line invalidate: privileged and treated as no-op */
5252 #if defined(CONFIG_USER_ONLY)
5253 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5254 #else
5255 if (unlikely(!ctx->mem_idx)) {
5256 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5257 return;
5258 }
5259 #endif
5260 }
5261
5262 /* dclst */
5263 static void gen_dclst(DisasContext *ctx)
5264 {
5265 /* Data cache line store: treated as no-op */
5266 }
5267
5268 static void gen_mfsri(DisasContext *ctx)
5269 {
5270 #if defined(CONFIG_USER_ONLY)
5271 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5272 #else
5273 int ra = rA(ctx->opcode);
5274 int rd = rD(ctx->opcode);
5275 TCGv t0;
5276 if (unlikely(!ctx->mem_idx)) {
5277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5278 return;
5279 }
5280 t0 = tcg_temp_new();
5281 gen_addr_reg_index(ctx, t0);
5282 tcg_gen_shri_tl(t0, t0, 28);
5283 tcg_gen_andi_tl(t0, t0, 0xF);
5284 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5285 tcg_temp_free(t0);
5286 if (ra != 0 && ra != rd)
5287 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5288 #endif
5289 }
5290
5291 static void gen_rac(DisasContext *ctx)
5292 {
5293 #if defined(CONFIG_USER_ONLY)
5294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5295 #else
5296 TCGv t0;
5297 if (unlikely(!ctx->mem_idx)) {
5298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5299 return;
5300 }
5301 t0 = tcg_temp_new();
5302 gen_addr_reg_index(ctx, t0);
5303 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5304 tcg_temp_free(t0);
5305 #endif
5306 }
5307
5308 static void gen_rfsvc(DisasContext *ctx)
5309 {
5310 #if defined(CONFIG_USER_ONLY)
5311 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5312 #else
5313 if (unlikely(!ctx->mem_idx)) {
5314 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5315 return;
5316 }
5317 gen_helper_rfsvc(cpu_env);
5318 gen_sync_exception(ctx);
5319 #endif
5320 }
5321
5322 /* svc is not implemented for now */
5323
5324 /* POWER2 specific instructions */
5325 /* Quad manipulation (load/store two floats at a time) */
5326
5327 /* lfq */
5328 static void gen_lfq(DisasContext *ctx)
5329 {
5330 int rd = rD(ctx->opcode);
5331 TCGv t0;
5332 gen_set_access_type(ctx, ACCESS_FLOAT);
5333 t0 = tcg_temp_new();
5334 gen_addr_imm_index(ctx, t0, 0);
5335 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5336 gen_addr_add(ctx, t0, t0, 8);
5337 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5338 tcg_temp_free(t0);
5339 }
5340
5341 /* lfqu */
5342 static void gen_lfqu(DisasContext *ctx)
5343 {
5344 int ra = rA(ctx->opcode);
5345 int rd = rD(ctx->opcode);
5346 TCGv t0, t1;
5347 gen_set_access_type(ctx, ACCESS_FLOAT);
5348 t0 = tcg_temp_new();
5349 t1 = tcg_temp_new();
5350 gen_addr_imm_index(ctx, t0, 0);
5351 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5352 gen_addr_add(ctx, t1, t0, 8);
5353 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5354 if (ra != 0)
5355 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5356 tcg_temp_free(t0);
5357 tcg_temp_free(t1);
5358 }
5359
5360 /* lfqux */
5361 static void gen_lfqux(DisasContext *ctx)
5362 {
5363 int ra = rA(ctx->opcode);
5364 int rd = rD(ctx->opcode);
5365 gen_set_access_type(ctx, ACCESS_FLOAT);
5366 TCGv t0, t1;
5367 t0 = tcg_temp_new();
5368 gen_addr_reg_index(ctx, t0);
5369 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5370 t1 = tcg_temp_new();
5371 gen_addr_add(ctx, t1, t0, 8);
5372 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5373 tcg_temp_free(t1);
5374 if (ra != 0)
5375 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5376 tcg_temp_free(t0);
5377 }
5378
5379 /* lfqx */
5380 static void gen_lfqx(DisasContext *ctx)
5381 {
5382 int rd = rD(ctx->opcode);
5383 TCGv t0;
5384 gen_set_access_type(ctx, ACCESS_FLOAT);
5385 t0 = tcg_temp_new();
5386 gen_addr_reg_index(ctx, t0);
5387 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5388 gen_addr_add(ctx, t0, t0, 8);
5389 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5390 tcg_temp_free(t0);
5391 }
5392
5393 /* stfq */
5394 static void gen_stfq(DisasContext *ctx)
5395 {
5396 int rd = rD(ctx->opcode);
5397 TCGv t0;
5398 gen_set_access_type(ctx, ACCESS_FLOAT);
5399 t0 = tcg_temp_new();
5400 gen_addr_imm_index(ctx, t0, 0);
5401 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5402 gen_addr_add(ctx, t0, t0, 8);
5403 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5404 tcg_temp_free(t0);
5405 }
5406
5407 /* stfqu */
5408 static void gen_stfqu(DisasContext *ctx)
5409 {
5410 int ra = rA(ctx->opcode);
5411 int rd = rD(ctx->opcode);
5412 TCGv t0, t1;
5413 gen_set_access_type(ctx, ACCESS_FLOAT);
5414 t0 = tcg_temp_new();
5415 gen_addr_imm_index(ctx, t0, 0);
5416 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5417 t1 = tcg_temp_new();
5418 gen_addr_add(ctx, t1, t0, 8);
5419 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5420 tcg_temp_free(t1);
5421 if (ra != 0)
5422 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5423 tcg_temp_free(t0);
5424 }
5425
5426 /* stfqux */
5427 static void gen_stfqux(DisasContext *ctx)
5428 {
5429 int ra = rA(ctx->opcode);
5430 int rd = rD(ctx->opcode);
5431 TCGv t0, t1;
5432 gen_set_access_type(ctx, ACCESS_FLOAT);
5433 t0 = tcg_temp_new();
5434 gen_addr_reg_index(ctx, t0);
5435 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5436 t1 = tcg_temp_new();
5437 gen_addr_add(ctx, t1, t0, 8);
5438 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5439 tcg_temp_free(t1);
5440 if (ra != 0)
5441 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5442 tcg_temp_free(t0);
5443 }
5444
5445 /* stfqx */
5446 static void gen_stfqx(DisasContext *ctx)
5447 {
5448 int rd = rD(ctx->opcode);
5449 TCGv t0;
5450 gen_set_access_type(ctx, ACCESS_FLOAT);
5451 t0 = tcg_temp_new();
5452 gen_addr_reg_index(ctx, t0);
5453 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5454 gen_addr_add(ctx, t0, t0, 8);
5455 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5456 tcg_temp_free(t0);
5457 }
5458
5459 /* BookE specific instructions */
5460
5461 /* XXX: not implemented on 440 ? */
5462 static void gen_mfapidi(DisasContext *ctx)
5463 {
5464 /* XXX: TODO */
5465 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5466 }
5467
5468 /* XXX: not implemented on 440 ? */
5469 static void gen_tlbiva(DisasContext *ctx)
5470 {
5471 #if defined(CONFIG_USER_ONLY)
5472 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5473 #else
5474 TCGv t0;
5475 if (unlikely(!ctx->mem_idx)) {
5476 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5477 return;
5478 }
5479 t0 = tcg_temp_new();
5480 gen_addr_reg_index(ctx, t0);
5481 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5482 tcg_temp_free(t0);
5483 #endif
5484 }
5485
5486 /* All 405 MAC instructions are translated here */
5487 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5488 int ra, int rb, int rt, int Rc)
5489 {
5490 TCGv t0, t1;
5491
5492 t0 = tcg_temp_local_new();
5493 t1 = tcg_temp_local_new();
5494
5495 switch (opc3 & 0x0D) {
5496 case 0x05:
5497 /* macchw - macchw. - macchwo - macchwo. */
5498 /* macchws - macchws. - macchwso - macchwso. */
5499 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5500 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5501 /* mulchw - mulchw. */
5502 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5503 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5504 tcg_gen_ext16s_tl(t1, t1);
5505 break;
5506 case 0x04:
5507 /* macchwu - macchwu. - macchwuo - macchwuo. */
5508 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5509 /* mulchwu - mulchwu. */
5510 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5511 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5512 tcg_gen_ext16u_tl(t1, t1);
5513 break;
5514 case 0x01:
5515 /* machhw - machhw. - machhwo - machhwo. */
5516 /* machhws - machhws. - machhwso - machhwso. */
5517 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5518 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5519 /* mulhhw - mulhhw. */
5520 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5521 tcg_gen_ext16s_tl(t0, t0);
5522 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5523 tcg_gen_ext16s_tl(t1, t1);
5524 break;
5525 case 0x00:
5526 /* machhwu - machhwu. - machhwuo - machhwuo. */
5527 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5528 /* mulhhwu - mulhhwu. */
5529 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5530 tcg_gen_ext16u_tl(t0, t0);
5531 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5532 tcg_gen_ext16u_tl(t1, t1);
5533 break;
5534 case 0x0D:
5535 /* maclhw - maclhw. - maclhwo - maclhwo. */
5536 /* maclhws - maclhws. - maclhwso - maclhwso. */
5537 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5538 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5539 /* mullhw - mullhw. */
5540 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5541 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5542 break;
5543 case 0x0C:
5544 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5545 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5546 /* mullhwu - mullhwu. */
5547 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5548 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5549 break;
5550 }
5551 if (opc2 & 0x04) {
5552 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5553 tcg_gen_mul_tl(t1, t0, t1);
5554 if (opc2 & 0x02) {
5555 /* nmultiply-and-accumulate (0x0E) */
5556 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5557 } else {
5558 /* multiply-and-accumulate (0x0C) */
5559 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5560 }
5561
5562 if (opc3 & 0x12) {
5563 /* Check overflow and/or saturate */
5564 int l1 = gen_new_label();
5565
5566 if (opc3 & 0x10) {
5567 /* Start with XER OV disabled, the most likely case */
5568 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5569 }
5570 if (opc3 & 0x01) {
5571 /* Signed */
5572 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5573 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5574 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5575 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5576 if (opc3 & 0x02) {
5577 /* Saturate */
5578 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5579 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5580 }
5581 } else {
5582 /* Unsigned */
5583 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5584 if (opc3 & 0x02) {
5585 /* Saturate */
5586 tcg_gen_movi_tl(t0, UINT32_MAX);
5587 }
5588 }
5589 if (opc3 & 0x10) {
5590 /* Check overflow */
5591 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5592 }
5593 gen_set_label(l1);
5594 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5595 }
5596 } else {
5597 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5598 }
5599 tcg_temp_free(t0);
5600 tcg_temp_free(t1);
5601 if (unlikely(Rc) != 0) {
5602 /* Update Rc0 */
5603 gen_set_Rc0(ctx, cpu_gpr[rt]);
5604 }
5605 }
5606
5607 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5608 static void glue(gen_, name)(DisasContext *ctx) \
5609 { \
5610 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5611 rD(ctx->opcode), Rc(ctx->opcode)); \
5612 }
5613
5614 /* macchw - macchw. */
5615 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5616 /* macchwo - macchwo. */
5617 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5618 /* macchws - macchws. */
5619 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5620 /* macchwso - macchwso. */
5621 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5622 /* macchwsu - macchwsu. */
5623 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5624 /* macchwsuo - macchwsuo. */
5625 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5626 /* macchwu - macchwu. */
5627 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5628 /* macchwuo - macchwuo. */
5629 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5630 /* machhw - machhw. */
5631 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5632 /* machhwo - machhwo. */
5633 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5634 /* machhws - machhws. */
5635 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5636 /* machhwso - machhwso. */
5637 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5638 /* machhwsu - machhwsu. */
5639 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5640 /* machhwsuo - machhwsuo. */
5641 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5642 /* machhwu - machhwu. */
5643 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5644 /* machhwuo - machhwuo. */
5645 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5646 /* maclhw - maclhw. */
5647 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5648 /* maclhwo - maclhwo. */
5649 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5650 /* maclhws - maclhws. */
5651 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5652 /* maclhwso - maclhwso. */
5653 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5654 /* maclhwu - maclhwu. */
5655 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5656 /* maclhwuo - maclhwuo. */
5657 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5658 /* maclhwsu - maclhwsu. */
5659 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5660 /* maclhwsuo - maclhwsuo. */
5661 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5662 /* nmacchw - nmacchw. */
5663 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5664 /* nmacchwo - nmacchwo. */
5665 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5666 /* nmacchws - nmacchws. */
5667 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5668 /* nmacchwso - nmacchwso. */
5669 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5670 /* nmachhw - nmachhw. */
5671 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5672 /* nmachhwo - nmachhwo. */
5673 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5674 /* nmachhws - nmachhws. */
5675 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5676 /* nmachhwso - nmachhwso. */
5677 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5678 /* nmaclhw - nmaclhw. */
5679 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5680 /* nmaclhwo - nmaclhwo. */
5681 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5682 /* nmaclhws - nmaclhws. */
5683 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5684 /* nmaclhwso - nmaclhwso. */
5685 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5686
5687 /* mulchw - mulchw. */
5688 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5689 /* mulchwu - mulchwu. */
5690 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5691 /* mulhhw - mulhhw. */
5692 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5693 /* mulhhwu - mulhhwu. */
5694 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5695 /* mullhw - mullhw. */
5696 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5697 /* mullhwu - mullhwu. */
5698 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5699
5700 /* mfdcr */
5701 static void gen_mfdcr(DisasContext *ctx)
5702 {
5703 #if defined(CONFIG_USER_ONLY)
5704 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5705 #else
5706 TCGv dcrn;
5707 if (unlikely(!ctx->mem_idx)) {
5708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5709 return;
5710 }
5711 /* NIP cannot be restored if the memory exception comes from an helper */
5712 gen_update_nip(ctx, ctx->nip - 4);
5713 dcrn = tcg_const_tl(SPR(ctx->opcode));
5714 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5715 tcg_temp_free(dcrn);
5716 #endif
5717 }
5718
5719 /* mtdcr */
5720 static void gen_mtdcr(DisasContext *ctx)
5721 {
5722 #if defined(CONFIG_USER_ONLY)
5723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5724 #else
5725 TCGv dcrn;
5726 if (unlikely(!ctx->mem_idx)) {
5727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5728 return;
5729 }
5730 /* NIP cannot be restored if the memory exception comes from an helper */
5731 gen_update_nip(ctx, ctx->nip - 4);
5732 dcrn = tcg_const_tl(SPR(ctx->opcode));
5733 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5734 tcg_temp_free(dcrn);
5735 #endif
5736 }
5737
5738 /* mfdcrx */
5739 /* XXX: not implemented on 440 ? */
5740 static void gen_mfdcrx(DisasContext *ctx)
5741 {
5742 #if defined(CONFIG_USER_ONLY)
5743 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5744 #else
5745 if (unlikely(!ctx->mem_idx)) {
5746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5747 return;
5748 }
5749 /* NIP cannot be restored if the memory exception comes from an helper */
5750 gen_update_nip(ctx, ctx->nip - 4);
5751 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5752 cpu_gpr[rA(ctx->opcode)]);
5753 /* Note: Rc update flag set leads to undefined state of Rc0 */
5754 #endif
5755 }
5756
5757 /* mtdcrx */
5758 /* XXX: not implemented on 440 ? */
5759 static void gen_mtdcrx(DisasContext *ctx)
5760 {
5761 #if defined(CONFIG_USER_ONLY)
5762 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5763 #else
5764 if (unlikely(!ctx->mem_idx)) {
5765 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5766 return;
5767 }
5768 /* NIP cannot be restored if the memory exception comes from an helper */
5769 gen_update_nip(ctx, ctx->nip - 4);
5770 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5771 cpu_gpr[rS(ctx->opcode)]);
5772 /* Note: Rc update flag set leads to undefined state of Rc0 */
5773 #endif
5774 }
5775
5776 /* mfdcrux (PPC 460) : user-mode access to DCR */
5777 static void gen_mfdcrux(DisasContext *ctx)
5778 {
5779 /* NIP cannot be restored if the memory exception comes from an helper */
5780 gen_update_nip(ctx, ctx->nip - 4);
5781 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5782 cpu_gpr[rA(ctx->opcode)]);
5783 /* Note: Rc update flag set leads to undefined state of Rc0 */
5784 }
5785
5786 /* mtdcrux (PPC 460) : user-mode access to DCR */
5787 static void gen_mtdcrux(DisasContext *ctx)
5788 {
5789 /* NIP cannot be restored if the memory exception comes from an helper */
5790 gen_update_nip(ctx, ctx->nip - 4);
5791 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5792 cpu_gpr[rS(ctx->opcode)]);
5793 /* Note: Rc update flag set leads to undefined state of Rc0 */
5794 }
5795
5796 /* dccci */
5797 static void gen_dccci(DisasContext *ctx)
5798 {
5799 #if defined(CONFIG_USER_ONLY)
5800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5801 #else
5802 if (unlikely(!ctx->mem_idx)) {
5803 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5804 return;
5805 }
5806 /* interpreted as no-op */
5807 #endif
5808 }
5809
5810 /* dcread */
5811 static void gen_dcread(DisasContext *ctx)
5812 {
5813 #if defined(CONFIG_USER_ONLY)
5814 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5815 #else
5816 TCGv EA, val;
5817 if (unlikely(!ctx->mem_idx)) {
5818 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5819 return;
5820 }
5821 gen_set_access_type(ctx, ACCESS_CACHE);
5822 EA = tcg_temp_new();
5823 gen_addr_reg_index(ctx, EA);
5824 val = tcg_temp_new();
5825 gen_qemu_ld32u(ctx, val, EA);
5826 tcg_temp_free(val);
5827 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5828 tcg_temp_free(EA);
5829 #endif
5830 }
5831
5832 /* icbt */
5833 static void gen_icbt_40x(DisasContext *ctx)
5834 {
5835 /* interpreted as no-op */
5836 /* XXX: specification say this is treated as a load by the MMU
5837 * but does not generate any exception
5838 */
5839 }
5840
5841 /* iccci */
5842 static void gen_iccci(DisasContext *ctx)
5843 {
5844 #if defined(CONFIG_USER_ONLY)
5845 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5846 #else
5847 if (unlikely(!ctx->mem_idx)) {
5848 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5849 return;
5850 }
5851 /* interpreted as no-op */
5852 #endif
5853 }
5854
5855 /* icread */
5856 static void gen_icread(DisasContext *ctx)
5857 {
5858 #if defined(CONFIG_USER_ONLY)
5859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5860 #else
5861 if (unlikely(!ctx->mem_idx)) {
5862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5863 return;
5864 }
5865 /* interpreted as no-op */
5866 #endif
5867 }
5868
5869 /* rfci (mem_idx only) */
5870 static void gen_rfci_40x(DisasContext *ctx)
5871 {
5872 #if defined(CONFIG_USER_ONLY)
5873 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5874 #else
5875 if (unlikely(!ctx->mem_idx)) {
5876 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5877 return;
5878 }
5879 /* Restore CPU state */
5880 gen_helper_40x_rfci(cpu_env);
5881 gen_sync_exception(ctx);
5882 #endif
5883 }
5884
5885 static void gen_rfci(DisasContext *ctx)
5886 {
5887 #if defined(CONFIG_USER_ONLY)
5888 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5889 #else
5890 if (unlikely(!ctx->mem_idx)) {
5891 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5892 return;
5893 }
5894 /* Restore CPU state */
5895 gen_helper_rfci(cpu_env);
5896 gen_sync_exception(ctx);
5897 #endif
5898 }
5899
5900 /* BookE specific */
5901
5902 /* XXX: not implemented on 440 ? */
5903 static void gen_rfdi(DisasContext *ctx)
5904 {
5905 #if defined(CONFIG_USER_ONLY)
5906 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5907 #else
5908 if (unlikely(!ctx->mem_idx)) {
5909 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5910 return;
5911 }
5912 /* Restore CPU state */
5913 gen_helper_rfdi(cpu_env);
5914 gen_sync_exception(ctx);
5915 #endif
5916 }
5917
5918 /* XXX: not implemented on 440 ? */
5919 static void gen_rfmci(DisasContext *ctx)
5920 {
5921 #if defined(CONFIG_USER_ONLY)
5922 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5923 #else
5924 if (unlikely(!ctx->mem_idx)) {
5925 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5926 return;
5927 }
5928 /* Restore CPU state */
5929 gen_helper_rfmci(cpu_env);
5930 gen_sync_exception(ctx);
5931 #endif
5932 }
5933
5934 /* TLB management - PowerPC 405 implementation */
5935
5936 /* tlbre */
5937 static void gen_tlbre_40x(DisasContext *ctx)
5938 {
5939 #if defined(CONFIG_USER_ONLY)
5940 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5941 #else
5942 if (unlikely(!ctx->mem_idx)) {
5943 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5944 return;
5945 }
5946 switch (rB(ctx->opcode)) {
5947 case 0:
5948 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5949 cpu_gpr[rA(ctx->opcode)]);
5950 break;
5951 case 1:
5952 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5953 cpu_gpr[rA(ctx->opcode)]);
5954 break;
5955 default:
5956 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5957 break;
5958 }
5959 #endif
5960 }
5961
5962 /* tlbsx - tlbsx. */
5963 static void gen_tlbsx_40x(DisasContext *ctx)
5964 {
5965 #if defined(CONFIG_USER_ONLY)
5966 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5967 #else
5968 TCGv t0;
5969 if (unlikely(!ctx->mem_idx)) {
5970 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5971 return;
5972 }
5973 t0 = tcg_temp_new();
5974 gen_addr_reg_index(ctx, t0);
5975 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5976 tcg_temp_free(t0);
5977 if (Rc(ctx->opcode)) {
5978 int l1 = gen_new_label();
5979 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5980 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5981 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5982 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5983 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5984 gen_set_label(l1);
5985 }
5986 #endif
5987 }
5988
5989 /* tlbwe */
5990 static void gen_tlbwe_40x(DisasContext *ctx)
5991 {
5992 #if defined(CONFIG_USER_ONLY)
5993 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5994 #else
5995 if (unlikely(!ctx->mem_idx)) {
5996 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5997 return;
5998 }
5999 switch (rB(ctx->opcode)) {
6000 case 0:
6001 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6002 cpu_gpr[rS(ctx->opcode)]);
6003 break;
6004 case 1:
6005 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6006 cpu_gpr[rS(ctx->opcode)]);
6007 break;
6008 default:
6009 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6010 break;
6011 }
6012 #endif
6013 }
6014
6015 /* TLB management - PowerPC 440 implementation */
6016
6017 /* tlbre */
6018 static void gen_tlbre_440(DisasContext *ctx)
6019 {
6020 #if defined(CONFIG_USER_ONLY)
6021 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6022 #else
6023 if (unlikely(!ctx->mem_idx)) {
6024 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6025 return;
6026 }
6027 switch (rB(ctx->opcode)) {
6028 case 0:
6029 case 1:
6030 case 2:
6031 {
6032 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6033 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6034 t0, cpu_gpr[rA(ctx->opcode)]);
6035 tcg_temp_free_i32(t0);
6036 }
6037 break;
6038 default:
6039 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6040 break;
6041 }
6042 #endif
6043 }
6044
6045 /* tlbsx - tlbsx. */
6046 static void gen_tlbsx_440(DisasContext *ctx)
6047 {
6048 #if defined(CONFIG_USER_ONLY)
6049 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6050 #else
6051 TCGv t0;
6052 if (unlikely(!ctx->mem_idx)) {
6053 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6054 return;
6055 }
6056 t0 = tcg_temp_new();
6057 gen_addr_reg_index(ctx, t0);
6058 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6059 tcg_temp_free(t0);
6060 if (Rc(ctx->opcode)) {
6061 int l1 = gen_new_label();
6062 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6063 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6064 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6065 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6066 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6067 gen_set_label(l1);
6068 }
6069 #endif
6070 }
6071
6072 /* tlbwe */
6073 static void gen_tlbwe_440(DisasContext *ctx)
6074 {
6075 #if defined(CONFIG_USER_ONLY)
6076 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6077 #else
6078 if (unlikely(!ctx->mem_idx)) {
6079 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6080 return;
6081 }
6082 switch (rB(ctx->opcode)) {
6083 case 0:
6084 case 1:
6085 case 2:
6086 {
6087 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6088 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6089 cpu_gpr[rS(ctx->opcode)]);
6090 tcg_temp_free_i32(t0);
6091 }
6092 break;
6093 default:
6094 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6095 break;
6096 }
6097 #endif
6098 }
6099
6100 /* TLB management - PowerPC BookE 2.06 implementation */
6101
6102 /* tlbre */
6103 static void gen_tlbre_booke206(DisasContext *ctx)
6104 {
6105 #if defined(CONFIG_USER_ONLY)
6106 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6107 #else
6108 if (unlikely(!ctx->mem_idx)) {
6109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6110 return;
6111 }
6112
6113 gen_helper_booke206_tlbre(cpu_env);
6114 #endif
6115 }
6116
6117 /* tlbsx - tlbsx. */
6118 static void gen_tlbsx_booke206(DisasContext *ctx)
6119 {
6120 #if defined(CONFIG_USER_ONLY)
6121 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6122 #else
6123 TCGv t0;
6124 if (unlikely(!ctx->mem_idx)) {
6125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6126 return;
6127 }
6128
6129 if (rA(ctx->opcode)) {
6130 t0 = tcg_temp_new();
6131 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6132 } else {
6133 t0 = tcg_const_tl(0);
6134 }
6135
6136 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6137 gen_helper_booke206_tlbsx(cpu_env, t0);
6138 #endif
6139 }
6140
6141 /* tlbwe */
6142 static void gen_tlbwe_booke206(DisasContext *ctx)
6143 {
6144 #if defined(CONFIG_USER_ONLY)
6145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6146 #else
6147 if (unlikely(!ctx->mem_idx)) {
6148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6149 return;
6150 }
6151 gen_update_nip(ctx, ctx->nip - 4);
6152 gen_helper_booke206_tlbwe(cpu_env);
6153 #endif
6154 }
6155
6156 static void gen_tlbivax_booke206(DisasContext *ctx)
6157 {
6158 #if defined(CONFIG_USER_ONLY)
6159 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6160 #else
6161 TCGv t0;
6162 if (unlikely(!ctx->mem_idx)) {
6163 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6164 return;
6165 }
6166
6167 t0 = tcg_temp_new();
6168 gen_addr_reg_index(ctx, t0);
6169
6170 gen_helper_booke206_tlbivax(cpu_env, t0);
6171 #endif
6172 }
6173
6174 static void gen_tlbilx_booke206(DisasContext *ctx)
6175 {
6176 #if defined(CONFIG_USER_ONLY)
6177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6178 #else
6179 TCGv t0;
6180 if (unlikely(!ctx->mem_idx)) {
6181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6182 return;
6183 }
6184
6185 t0 = tcg_temp_new();
6186 gen_addr_reg_index(ctx, t0);
6187
6188 switch((ctx->opcode >> 21) & 0x3) {
6189 case 0:
6190 gen_helper_booke206_tlbilx0(cpu_env, t0);
6191 break;
6192 case 1:
6193 gen_helper_booke206_tlbilx1(cpu_env, t0);
6194 break;
6195 case 3:
6196 gen_helper_booke206_tlbilx3(cpu_env, t0);
6197 break;
6198 default:
6199 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6200 break;
6201 }
6202
6203 tcg_temp_free(t0);
6204 #endif
6205 }
6206
6207
6208 /* wrtee */
6209 static void gen_wrtee(DisasContext *ctx)
6210 {
6211 #if defined(CONFIG_USER_ONLY)
6212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6213 #else
6214 TCGv t0;
6215 if (unlikely(!ctx->mem_idx)) {
6216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6217 return;
6218 }
6219 t0 = tcg_temp_new();
6220 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6221 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6222 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6223 tcg_temp_free(t0);
6224 /* Stop translation to have a chance to raise an exception
6225 * if we just set msr_ee to 1
6226 */
6227 gen_stop_exception(ctx);
6228 #endif
6229 }
6230
6231 /* wrteei */
6232 static void gen_wrteei(DisasContext *ctx)
6233 {
6234 #if defined(CONFIG_USER_ONLY)
6235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6236 #else
6237 if (unlikely(!ctx->mem_idx)) {
6238 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6239 return;
6240 }
6241 if (ctx->opcode & 0x00008000) {
6242 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6243 /* Stop translation to have a chance to raise an exception */
6244 gen_stop_exception(ctx);
6245 } else {
6246 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6247 }
6248 #endif
6249 }
6250
6251 /* PowerPC 440 specific instructions */
6252
6253 /* dlmzb */
6254 static void gen_dlmzb(DisasContext *ctx)
6255 {
6256 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6257 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6258 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6259 tcg_temp_free_i32(t0);
6260 }
6261
6262 /* mbar replaces eieio on 440 */
6263 static void gen_mbar(DisasContext *ctx)
6264 {
6265 /* interpreted as no-op */
6266 }
6267
6268 /* msync replaces sync on 440 */
6269 static void gen_msync_4xx(DisasContext *ctx)
6270 {
6271 /* interpreted as no-op */
6272 }
6273
6274 /* icbt */
6275 static void gen_icbt_440(DisasContext *ctx)
6276 {
6277 /* interpreted as no-op */
6278 /* XXX: specification say this is treated as a load by the MMU
6279 * but does not generate any exception
6280 */
6281 }
6282
6283 /* Embedded.Processor Control */
6284
6285 static void gen_msgclr(DisasContext *ctx)
6286 {
6287 #if defined(CONFIG_USER_ONLY)
6288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6289 #else
6290 if (unlikely(ctx->mem_idx == 0)) {
6291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6292 return;
6293 }
6294
6295 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6296 #endif
6297 }
6298
6299 static void gen_msgsnd(DisasContext *ctx)
6300 {
6301 #if defined(CONFIG_USER_ONLY)
6302 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6303 #else
6304 if (unlikely(ctx->mem_idx == 0)) {
6305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6306 return;
6307 }
6308
6309 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6310 #endif
6311 }
6312
6313 /*** Altivec vector extension ***/
6314 /* Altivec registers moves */
6315
6316 static inline TCGv_ptr gen_avr_ptr(int reg)
6317 {
6318 TCGv_ptr r = tcg_temp_new_ptr();
6319 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6320 return r;
6321 }
6322
6323 #define GEN_VR_LDX(name, opc2, opc3) \
6324 static void glue(gen_, name)(DisasContext *ctx) \
6325 { \
6326 TCGv EA; \
6327 if (unlikely(!ctx->altivec_enabled)) { \
6328 gen_exception(ctx, POWERPC_EXCP_VPU); \
6329 return; \
6330 } \
6331 gen_set_access_type(ctx, ACCESS_INT); \
6332 EA = tcg_temp_new(); \
6333 gen_addr_reg_index(ctx, EA); \
6334 tcg_gen_andi_tl(EA, EA, ~0xf); \
6335 if (ctx->le_mode) { \
6336 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6337 tcg_gen_addi_tl(EA, EA, 8); \
6338 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6339 } else { \
6340 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6341 tcg_gen_addi_tl(EA, EA, 8); \
6342 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6343 } \
6344 tcg_temp_free(EA); \
6345 }
6346
6347 #define GEN_VR_STX(name, opc2, opc3) \
6348 static void gen_st##name(DisasContext *ctx) \
6349 { \
6350 TCGv EA; \
6351 if (unlikely(!ctx->altivec_enabled)) { \
6352 gen_exception(ctx, POWERPC_EXCP_VPU); \
6353 return; \
6354 } \
6355 gen_set_access_type(ctx, ACCESS_INT); \
6356 EA = tcg_temp_new(); \
6357 gen_addr_reg_index(ctx, EA); \
6358 tcg_gen_andi_tl(EA, EA, ~0xf); \
6359 if (ctx->le_mode) { \
6360 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6361 tcg_gen_addi_tl(EA, EA, 8); \
6362 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6363 } else { \
6364 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6365 tcg_gen_addi_tl(EA, EA, 8); \
6366 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6367 } \
6368 tcg_temp_free(EA); \
6369 }
6370
6371 #define GEN_VR_LVE(name, opc2, opc3) \
6372 static void gen_lve##name(DisasContext *ctx) \
6373 { \
6374 TCGv EA; \
6375 TCGv_ptr rs; \
6376 if (unlikely(!ctx->altivec_enabled)) { \
6377 gen_exception(ctx, POWERPC_EXCP_VPU); \
6378 return; \
6379 } \
6380 gen_set_access_type(ctx, ACCESS_INT); \
6381 EA = tcg_temp_new(); \
6382 gen_addr_reg_index(ctx, EA); \
6383 rs = gen_avr_ptr(rS(ctx->opcode)); \
6384 gen_helper_lve##name(cpu_env, rs, EA); \
6385 tcg_temp_free(EA); \
6386 tcg_temp_free_ptr(rs); \
6387 }
6388
6389 #define GEN_VR_STVE(name, opc2, opc3) \
6390 static void gen_stve##name(DisasContext *ctx) \
6391 { \
6392 TCGv EA; \
6393 TCGv_ptr rs; \
6394 if (unlikely(!ctx->altivec_enabled)) { \
6395 gen_exception(ctx, POWERPC_EXCP_VPU); \
6396 return; \
6397 } \
6398 gen_set_access_type(ctx, ACCESS_INT); \
6399 EA = tcg_temp_new(); \
6400 gen_addr_reg_index(ctx, EA); \
6401 rs = gen_avr_ptr(rS(ctx->opcode)); \
6402 gen_helper_stve##name(cpu_env, rs, EA); \
6403 tcg_temp_free(EA); \
6404 tcg_temp_free_ptr(rs); \
6405 }
6406
6407 GEN_VR_LDX(lvx, 0x07, 0x03);
6408 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6409 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6410
6411 GEN_VR_LVE(bx, 0x07, 0x00);
6412 GEN_VR_LVE(hx, 0x07, 0x01);
6413 GEN_VR_LVE(wx, 0x07, 0x02);
6414
6415 GEN_VR_STX(svx, 0x07, 0x07);
6416 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6417 GEN_VR_STX(svxl, 0x07, 0x0F);
6418
6419 GEN_VR_STVE(bx, 0x07, 0x04);
6420 GEN_VR_STVE(hx, 0x07, 0x05);
6421 GEN_VR_STVE(wx, 0x07, 0x06);
6422
6423 static void gen_lvsl(DisasContext *ctx)
6424 {
6425 TCGv_ptr rd;
6426 TCGv EA;
6427 if (unlikely(!ctx->altivec_enabled)) {
6428 gen_exception(ctx, POWERPC_EXCP_VPU);
6429 return;
6430 }
6431 EA = tcg_temp_new();
6432 gen_addr_reg_index(ctx, EA);
6433 rd = gen_avr_ptr(rD(ctx->opcode));
6434 gen_helper_lvsl(rd, EA);
6435 tcg_temp_free(EA);
6436 tcg_temp_free_ptr(rd);
6437 }
6438
6439 static void gen_lvsr(DisasContext *ctx)
6440 {
6441 TCGv_ptr rd;
6442 TCGv EA;
6443 if (unlikely(!ctx->altivec_enabled)) {
6444 gen_exception(ctx, POWERPC_EXCP_VPU);
6445 return;
6446 }
6447 EA = tcg_temp_new();
6448 gen_addr_reg_index(ctx, EA);
6449 rd = gen_avr_ptr(rD(ctx->opcode));
6450 gen_helper_lvsr(rd, EA);
6451 tcg_temp_free(EA);
6452 tcg_temp_free_ptr(rd);
6453 }
6454
6455 static void gen_mfvscr(DisasContext *ctx)
6456 {
6457 TCGv_i32 t;
6458 if (unlikely(!ctx->altivec_enabled)) {
6459 gen_exception(ctx, POWERPC_EXCP_VPU);
6460 return;
6461 }
6462 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6463 t = tcg_temp_new_i32();
6464 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6465 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6466 tcg_temp_free_i32(t);
6467 }
6468
6469 static void gen_mtvscr(DisasContext *ctx)
6470 {
6471 TCGv_ptr p;
6472 if (unlikely(!ctx->altivec_enabled)) {
6473 gen_exception(ctx, POWERPC_EXCP_VPU);
6474 return;
6475 }
6476 p = gen_avr_ptr(rD(ctx->opcode));
6477 gen_helper_mtvscr(cpu_env, p);
6478 tcg_temp_free_ptr(p);
6479 }
6480
6481 /* Logical operations */
6482 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6483 static void glue(gen_, name)(DisasContext *ctx) \
6484 { \
6485 if (unlikely(!ctx->altivec_enabled)) { \
6486 gen_exception(ctx, POWERPC_EXCP_VPU); \
6487 return; \
6488 } \
6489 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6490 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6491 }
6492
6493 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6494 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6495 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6496 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6497 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6498
6499 #define GEN_VXFORM(name, opc2, opc3) \
6500 static void glue(gen_, name)(DisasContext *ctx) \
6501 { \
6502 TCGv_ptr ra, rb, rd; \
6503 if (unlikely(!ctx->altivec_enabled)) { \
6504 gen_exception(ctx, POWERPC_EXCP_VPU); \
6505 return; \
6506 } \
6507 ra = gen_avr_ptr(rA(ctx->opcode)); \
6508 rb = gen_avr_ptr(rB(ctx->opcode)); \
6509 rd = gen_avr_ptr(rD(ctx->opcode)); \
6510 gen_helper_##name (rd, ra, rb); \
6511 tcg_temp_free_ptr(ra); \
6512 tcg_temp_free_ptr(rb); \
6513 tcg_temp_free_ptr(rd); \
6514 }
6515
6516 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6517 static void glue(gen_, name)(DisasContext *ctx) \
6518 { \
6519 TCGv_ptr ra, rb, rd; \
6520 if (unlikely(!ctx->altivec_enabled)) { \
6521 gen_exception(ctx, POWERPC_EXCP_VPU); \
6522 return; \
6523 } \
6524 ra = gen_avr_ptr(rA(ctx->opcode)); \
6525 rb = gen_avr_ptr(rB(ctx->opcode)); \
6526 rd = gen_avr_ptr(rD(ctx->opcode)); \
6527 gen_helper_##name(cpu_env, rd, ra, rb); \
6528 tcg_temp_free_ptr(ra); \
6529 tcg_temp_free_ptr(rb); \
6530 tcg_temp_free_ptr(rd); \
6531 }
6532
6533 GEN_VXFORM(vaddubm, 0, 0);
6534 GEN_VXFORM(vadduhm, 0, 1);
6535 GEN_VXFORM(vadduwm, 0, 2);
6536 GEN_VXFORM(vsububm, 0, 16);
6537 GEN_VXFORM(vsubuhm, 0, 17);
6538 GEN_VXFORM(vsubuwm, 0, 18);
6539 GEN_VXFORM(vmaxub, 1, 0);
6540 GEN_VXFORM(vmaxuh, 1, 1);
6541 GEN_VXFORM(vmaxuw, 1, 2);
6542 GEN_VXFORM(vmaxsb, 1, 4);
6543 GEN_VXFORM(vmaxsh, 1, 5);
6544 GEN_VXFORM(vmaxsw, 1, 6);
6545 GEN_VXFORM(vminub, 1, 8);
6546 GEN_VXFORM(vminuh, 1, 9);
6547 GEN_VXFORM(vminuw, 1, 10);
6548 GEN_VXFORM(vminsb, 1, 12);
6549 GEN_VXFORM(vminsh, 1, 13);
6550 GEN_VXFORM(vminsw, 1, 14);
6551 GEN_VXFORM(vavgub, 1, 16);
6552 GEN_VXFORM(vavguh, 1, 17);
6553 GEN_VXFORM(vavguw, 1, 18);
6554 GEN_VXFORM(vavgsb, 1, 20);
6555 GEN_VXFORM(vavgsh, 1, 21);
6556 GEN_VXFORM(vavgsw, 1, 22);
6557 GEN_VXFORM(vmrghb, 6, 0);
6558 GEN_VXFORM(vmrghh, 6, 1);
6559 GEN_VXFORM(vmrghw, 6, 2);
6560 GEN_VXFORM(vmrglb, 6, 4);
6561 GEN_VXFORM(vmrglh, 6, 5);
6562 GEN_VXFORM(vmrglw, 6, 6);
6563 GEN_VXFORM(vmuloub, 4, 0);
6564 GEN_VXFORM(vmulouh, 4, 1);
6565 GEN_VXFORM(vmulosb, 4, 4);
6566 GEN_VXFORM(vmulosh, 4, 5);
6567 GEN_VXFORM(vmuleub, 4, 8);
6568 GEN_VXFORM(vmuleuh, 4, 9);
6569 GEN_VXFORM(vmulesb, 4, 12);
6570 GEN_VXFORM(vmulesh, 4, 13);
6571 GEN_VXFORM(vslb, 2, 4);
6572 GEN_VXFORM(vslh, 2, 5);
6573 GEN_VXFORM(vslw, 2, 6);
6574 GEN_VXFORM(vsrb, 2, 8);
6575 GEN_VXFORM(vsrh, 2, 9);
6576 GEN_VXFORM(vsrw, 2, 10);
6577 GEN_VXFORM(vsrab, 2, 12);
6578 GEN_VXFORM(vsrah, 2, 13);
6579 GEN_VXFORM(vsraw, 2, 14);
6580 GEN_VXFORM(vslo, 6, 16);
6581 GEN_VXFORM(vsro, 6, 17);
6582 GEN_VXFORM(vaddcuw, 0, 6);
6583 GEN_VXFORM(vsubcuw, 0, 22);
6584 GEN_VXFORM_ENV(vaddubs, 0, 8);
6585 GEN_VXFORM_ENV(vadduhs, 0, 9);
6586 GEN_VXFORM_ENV(vadduws, 0, 10);
6587 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6588 GEN_VXFORM_ENV(vaddshs, 0, 13);
6589 GEN_VXFORM_ENV(vaddsws, 0, 14);
6590 GEN_VXFORM_ENV(vsububs, 0, 24);
6591 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6592 GEN_VXFORM_ENV(vsubuws, 0, 26);
6593 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6594 GEN_VXFORM_ENV(vsubshs, 0, 29);
6595 GEN_VXFORM_ENV(vsubsws, 0, 30);
6596 GEN_VXFORM(vrlb, 2, 0);
6597 GEN_VXFORM(vrlh, 2, 1);
6598 GEN_VXFORM(vrlw, 2, 2);
6599 GEN_VXFORM(vsl, 2, 7);
6600 GEN_VXFORM(vsr, 2, 11);
6601 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6602 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6603 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6604 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6605 GEN_VXFORM_ENV(vpkshus, 7, 4);
6606 GEN_VXFORM_ENV(vpkswus, 7, 5);
6607 GEN_VXFORM_ENV(vpkshss, 7, 6);
6608 GEN_VXFORM_ENV(vpkswss, 7, 7);
6609 GEN_VXFORM(vpkpx, 7, 12);
6610 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6611 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6612 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6613 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6614 GEN_VXFORM_ENV(vsumsws, 4, 30);
6615 GEN_VXFORM_ENV(vaddfp, 5, 0);
6616 GEN_VXFORM_ENV(vsubfp, 5, 1);
6617 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6618 GEN_VXFORM_ENV(vminfp, 5, 17);
6619
6620 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6621 static void glue(gen_, name)(DisasContext *ctx) \
6622 { \
6623 TCGv_ptr ra, rb, rd; \
6624 if (unlikely(!ctx->altivec_enabled)) { \
6625 gen_exception(ctx, POWERPC_EXCP_VPU); \
6626 return; \
6627 } \
6628 ra = gen_avr_ptr(rA(ctx->opcode)); \
6629 rb = gen_avr_ptr(rB(ctx->opcode)); \
6630 rd = gen_avr_ptr(rD(ctx->opcode)); \
6631 gen_helper_##opname(cpu_env, rd, ra, rb); \
6632 tcg_temp_free_ptr(ra); \
6633 tcg_temp_free_ptr(rb); \
6634 tcg_temp_free_ptr(rd); \
6635 }
6636
6637 #define GEN_VXRFORM(name, opc2, opc3) \
6638 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6639 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6640
6641 GEN_VXRFORM(vcmpequb, 3, 0)
6642 GEN_VXRFORM(vcmpequh, 3, 1)
6643 GEN_VXRFORM(vcmpequw, 3, 2)
6644 GEN_VXRFORM(vcmpgtsb, 3, 12)
6645 GEN_VXRFORM(vcmpgtsh, 3, 13)
6646 GEN_VXRFORM(vcmpgtsw, 3, 14)
6647 GEN_VXRFORM(vcmpgtub, 3, 8)
6648 GEN_VXRFORM(vcmpgtuh, 3, 9)
6649 GEN_VXRFORM(vcmpgtuw, 3, 10)
6650 GEN_VXRFORM(vcmpeqfp, 3, 3)
6651 GEN_VXRFORM(vcmpgefp, 3, 7)
6652 GEN_VXRFORM(vcmpgtfp, 3, 11)
6653 GEN_VXRFORM(vcmpbfp, 3, 15)
6654
6655 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6656 static void glue(gen_, name)(DisasContext *ctx) \
6657 { \
6658 TCGv_ptr rd; \
6659 TCGv_i32 simm; \
6660 if (unlikely(!ctx->altivec_enabled)) { \
6661 gen_exception(ctx, POWERPC_EXCP_VPU); \
6662 return; \
6663 } \
6664 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6665 rd = gen_avr_ptr(rD(ctx->opcode)); \
6666 gen_helper_##name (rd, simm); \
6667 tcg_temp_free_i32(simm); \
6668 tcg_temp_free_ptr(rd); \
6669 }
6670
6671 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6672 GEN_VXFORM_SIMM(vspltish, 6, 13);
6673 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6674
6675 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6676 static void glue(gen_, name)(DisasContext *ctx) \
6677 { \
6678 TCGv_ptr rb, rd; \
6679 if (unlikely(!ctx->altivec_enabled)) { \
6680 gen_exception(ctx, POWERPC_EXCP_VPU); \
6681 return; \
6682 } \
6683 rb = gen_avr_ptr(rB(ctx->opcode)); \
6684 rd = gen_avr_ptr(rD(ctx->opcode)); \
6685 gen_helper_##name (rd, rb); \
6686 tcg_temp_free_ptr(rb); \
6687 tcg_temp_free_ptr(rd); \
6688 }
6689
6690 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6691 static void glue(gen_, name)(DisasContext *ctx) \
6692 { \
6693 TCGv_ptr rb, rd; \
6694 \
6695 if (unlikely(!ctx->altivec_enabled)) { \
6696 gen_exception(ctx, POWERPC_EXCP_VPU); \
6697 return; \
6698 } \
6699 rb = gen_avr_ptr(rB(ctx->opcode)); \
6700 rd = gen_avr_ptr(rD(ctx->opcode)); \
6701 gen_helper_##name(cpu_env, rd, rb); \
6702 tcg_temp_free_ptr(rb); \
6703 tcg_temp_free_ptr(rd); \
6704 }
6705
6706 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6707 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6708 GEN_VXFORM_NOA(vupklsb, 7, 10);
6709 GEN_VXFORM_NOA(vupklsh, 7, 11);
6710 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6711 GEN_VXFORM_NOA(vupklpx, 7, 15);
6712 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6713 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6714 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6715 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6716 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6717 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6718 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6719 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6720
6721 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6722 static void glue(gen_, name)(DisasContext *ctx) \
6723 { \
6724 TCGv_ptr rd; \
6725 TCGv_i32 simm; \
6726 if (unlikely(!ctx->altivec_enabled)) { \
6727 gen_exception(ctx, POWERPC_EXCP_VPU); \
6728 return; \
6729 } \
6730 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6731 rd = gen_avr_ptr(rD(ctx->opcode)); \
6732 gen_helper_##name (rd, simm); \
6733 tcg_temp_free_i32(simm); \
6734 tcg_temp_free_ptr(rd); \
6735 }
6736
6737 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6738 static void glue(gen_, name)(DisasContext *ctx) \
6739 { \
6740 TCGv_ptr rb, rd; \
6741 TCGv_i32 uimm; \
6742 if (unlikely(!ctx->altivec_enabled)) { \
6743 gen_exception(ctx, POWERPC_EXCP_VPU); \
6744 return; \
6745 } \
6746 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6747 rb = gen_avr_ptr(rB(ctx->opcode)); \
6748 rd = gen_avr_ptr(rD(ctx->opcode)); \
6749 gen_helper_##name (rd, rb, uimm); \
6750 tcg_temp_free_i32(uimm); \
6751 tcg_temp_free_ptr(rb); \
6752 tcg_temp_free_ptr(rd); \
6753 }
6754
6755 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6756 static void glue(gen_, name)(DisasContext *ctx) \
6757 { \
6758 TCGv_ptr rb, rd; \
6759 TCGv_i32 uimm; \
6760 \
6761 if (unlikely(!ctx->altivec_enabled)) { \
6762 gen_exception(ctx, POWERPC_EXCP_VPU); \
6763 return; \
6764 } \
6765 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6766 rb = gen_avr_ptr(rB(ctx->opcode)); \
6767 rd = gen_avr_ptr(rD(ctx->opcode)); \
6768 gen_helper_##name(cpu_env, rd, rb, uimm); \
6769 tcg_temp_free_i32(uimm); \
6770 tcg_temp_free_ptr(rb); \
6771 tcg_temp_free_ptr(rd); \
6772 }
6773
6774 GEN_VXFORM_UIMM(vspltb, 6, 8);
6775 GEN_VXFORM_UIMM(vsplth, 6, 9);
6776 GEN_VXFORM_UIMM(vspltw, 6, 10);
6777 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6778 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6779 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6780 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6781
6782 static void gen_vsldoi(DisasContext *ctx)
6783 {
6784 TCGv_ptr ra, rb, rd;
6785 TCGv_i32 sh;
6786 if (unlikely(!ctx->altivec_enabled)) {
6787 gen_exception(ctx, POWERPC_EXCP_VPU);
6788 return;
6789 }
6790 ra = gen_avr_ptr(rA(ctx->opcode));
6791 rb = gen_avr_ptr(rB(ctx->opcode));
6792 rd = gen_avr_ptr(rD(ctx->opcode));
6793 sh = tcg_const_i32(VSH(ctx->opcode));
6794 gen_helper_vsldoi (rd, ra, rb, sh);
6795 tcg_temp_free_ptr(ra);
6796 tcg_temp_free_ptr(rb);
6797 tcg_temp_free_ptr(rd);
6798 tcg_temp_free_i32(sh);
6799 }
6800
6801 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6802 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6803 { \
6804 TCGv_ptr ra, rb, rc, rd; \
6805 if (unlikely(!ctx->altivec_enabled)) { \
6806 gen_exception(ctx, POWERPC_EXCP_VPU); \
6807 return; \
6808 } \
6809 ra = gen_avr_ptr(rA(ctx->opcode)); \
6810 rb = gen_avr_ptr(rB(ctx->opcode)); \
6811 rc = gen_avr_ptr(rC(ctx->opcode)); \
6812 rd = gen_avr_ptr(rD(ctx->opcode)); \
6813 if (Rc(ctx->opcode)) { \
6814 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6815 } else { \
6816 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6817 } \
6818 tcg_temp_free_ptr(ra); \
6819 tcg_temp_free_ptr(rb); \
6820 tcg_temp_free_ptr(rc); \
6821 tcg_temp_free_ptr(rd); \
6822 }
6823
6824 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6825
6826 static void gen_vmladduhm(DisasContext *ctx)
6827 {
6828 TCGv_ptr ra, rb, rc, rd;
6829 if (unlikely(!ctx->altivec_enabled)) {
6830 gen_exception(ctx, POWERPC_EXCP_VPU);
6831 return;
6832 }
6833 ra = gen_avr_ptr(rA(ctx->opcode));
6834 rb = gen_avr_ptr(rB(ctx->opcode));
6835 rc = gen_avr_ptr(rC(ctx->opcode));
6836 rd = gen_avr_ptr(rD(ctx->opcode));
6837 gen_helper_vmladduhm(rd, ra, rb, rc);
6838 tcg_temp_free_ptr(ra);
6839 tcg_temp_free_ptr(rb);
6840 tcg_temp_free_ptr(rc);
6841 tcg_temp_free_ptr(rd);
6842 }
6843
6844 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6845 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6846 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6847 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6848 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6849
6850 /*** SPE extension ***/
6851 /* Register moves */
6852
6853
6854 static inline void gen_evmra(DisasContext *ctx)
6855 {
6856
6857 if (unlikely(!ctx->spe_enabled)) {
6858 gen_exception(ctx, POWERPC_EXCP_SPEU);
6859 return;
6860 }
6861
6862 #if defined(TARGET_PPC64)
6863 /* rD := rA */
6864 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6865
6866 /* spe_acc := rA */
6867 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6868 cpu_env,
6869 offsetof(CPUPPCState, spe_acc));
6870 #else
6871 TCGv_i64 tmp = tcg_temp_new_i64();
6872
6873 /* tmp := rA_lo + rA_hi << 32 */
6874 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6875
6876 /* spe_acc := tmp */
6877 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6878 tcg_temp_free_i64(tmp);
6879
6880 /* rD := rA */
6881 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6882 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6883 #endif
6884 }
6885
6886 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6887 {
6888 #if defined(TARGET_PPC64)
6889 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6890 #else
6891 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6892 #endif
6893 }
6894
6895 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6896 {
6897 #if defined(TARGET_PPC64)
6898 tcg_gen_mov_i64(cpu_gpr[reg], t);
6899 #else
6900 TCGv_i64 tmp = tcg_temp_new_i64();
6901 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6902 tcg_gen_shri_i64(tmp, t, 32);
6903 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6904 tcg_temp_free_i64(tmp);
6905 #endif
6906 }
6907
6908 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6909 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6910 { \
6911 if (Rc(ctx->opcode)) \
6912 gen_##name1(ctx); \
6913 else \
6914 gen_##name0(ctx); \
6915 }
6916
6917 /* Handler for undefined SPE opcodes */
6918 static inline void gen_speundef(DisasContext *ctx)
6919 {
6920 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6921 }
6922
6923 /* SPE logic */
6924 #if defined(TARGET_PPC64)
6925 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6926 static inline void gen_##name(DisasContext *ctx) \
6927 { \
6928 if (unlikely(!ctx->spe_enabled)) { \
6929 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6930 return; \
6931 } \
6932 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6933 cpu_gpr[rB(ctx->opcode)]); \
6934 }
6935 #else
6936 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6937 static inline void gen_##name(DisasContext *ctx) \
6938 { \
6939 if (unlikely(!ctx->spe_enabled)) { \
6940 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6941 return; \
6942 } \
6943 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6944 cpu_gpr[rB(ctx->opcode)]); \
6945 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6946 cpu_gprh[rB(ctx->opcode)]); \
6947 }
6948 #endif
6949
6950 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6951 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6952 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6953 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6954 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6955 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6956 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6957 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6958
6959 /* SPE logic immediate */
6960 #if defined(TARGET_PPC64)
6961 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6962 static inline void gen_##name(DisasContext *ctx) \
6963 { \
6964 if (unlikely(!ctx->spe_enabled)) { \
6965 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6966 return; \
6967 } \
6968 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6969 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6970 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6971 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6972 tcg_opi(t0, t0, rB(ctx->opcode)); \
6973 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6974 tcg_gen_trunc_i64_i32(t1, t2); \
6975 tcg_temp_free_i64(t2); \
6976 tcg_opi(t1, t1, rB(ctx->opcode)); \
6977 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6978 tcg_temp_free_i32(t0); \
6979 tcg_temp_free_i32(t1); \
6980 }
6981 #else
6982 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6983 static inline void gen_##name(DisasContext *ctx) \
6984 { \
6985 if (unlikely(!ctx->spe_enabled)) { \
6986 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6987 return; \
6988 } \
6989 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6990 rB(ctx->opcode)); \
6991 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6992 rB(ctx->opcode)); \
6993 }
6994 #endif
6995 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6996 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6997 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6998 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6999
7000 /* SPE arithmetic */
7001 #if defined(TARGET_PPC64)
7002 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7003 static inline void gen_##name(DisasContext *ctx) \
7004 { \
7005 if (unlikely(!ctx->spe_enabled)) { \
7006 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7007 return; \
7008 } \
7009 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7010 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7011 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7012 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7013 tcg_op(t0, t0); \
7014 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7015 tcg_gen_trunc_i64_i32(t1, t2); \
7016 tcg_temp_free_i64(t2); \
7017 tcg_op(t1, t1); \
7018 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7019 tcg_temp_free_i32(t0); \
7020 tcg_temp_free_i32(t1); \
7021 }
7022 #else
7023 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7024 static inline void gen_##name(DisasContext *ctx) \
7025 { \
7026 if (unlikely(!ctx->spe_enabled)) { \
7027 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7028 return; \
7029 } \
7030 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7031 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7032 }
7033 #endif
7034
7035 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
7036 {
7037 int l1 = gen_new_label();
7038 int l2 = gen_new_label();
7039
7040 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
7041 tcg_gen_neg_i32(ret, arg1);
7042 tcg_gen_br(l2);
7043 gen_set_label(l1);
7044 tcg_gen_mov_i32(ret, arg1);
7045 gen_set_label(l2);
7046 }
7047 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7048 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7049 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7050 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7051 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7052 {
7053 tcg_gen_addi_i32(ret, arg1, 0x8000);
7054 tcg_gen_ext16u_i32(ret, ret);
7055 }
7056 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7057 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7058 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7059
7060 #if defined(TARGET_PPC64)
7061 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7062 static inline void gen_##name(DisasContext *ctx) \
7063 { \
7064 if (unlikely(!ctx->spe_enabled)) { \
7065 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7066 return; \
7067 } \
7068 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7069 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7070 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7071 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7072 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7073 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7074 tcg_op(t0, t0, t2); \
7075 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7076 tcg_gen_trunc_i64_i32(t1, t3); \
7077 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7078 tcg_gen_trunc_i64_i32(t2, t3); \
7079 tcg_temp_free_i64(t3); \
7080 tcg_op(t1, t1, t2); \
7081 tcg_temp_free_i32(t2); \
7082 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7083 tcg_temp_free_i32(t0); \
7084 tcg_temp_free_i32(t1); \
7085 }
7086 #else
7087 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7088 static inline void gen_##name(DisasContext *ctx) \
7089 { \
7090 if (unlikely(!ctx->spe_enabled)) { \
7091 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7092 return; \
7093 } \
7094 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7095 cpu_gpr[rB(ctx->opcode)]); \
7096 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7097 cpu_gprh[rB(ctx->opcode)]); \
7098 }
7099 #endif
7100
7101 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7102 {
7103 TCGv_i32 t0;
7104 int l1, l2;
7105
7106 l1 = gen_new_label();
7107 l2 = gen_new_label();
7108 t0 = tcg_temp_local_new_i32();
7109 /* No error here: 6 bits are used */
7110 tcg_gen_andi_i32(t0, arg2, 0x3F);
7111 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7112 tcg_gen_shr_i32(ret, arg1, t0);
7113 tcg_gen_br(l2);
7114 gen_set_label(l1);
7115 tcg_gen_movi_i32(ret, 0);
7116 gen_set_label(l2);
7117 tcg_temp_free_i32(t0);
7118 }
7119 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7120 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7121 {
7122 TCGv_i32 t0;
7123 int l1, l2;
7124
7125 l1 = gen_new_label();
7126 l2 = gen_new_label();
7127 t0 = tcg_temp_local_new_i32();
7128 /* No error here: 6 bits are used */
7129 tcg_gen_andi_i32(t0, arg2, 0x3F);
7130 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7131 tcg_gen_sar_i32(ret, arg1, t0);
7132 tcg_gen_br(l2);
7133 gen_set_label(l1);
7134 tcg_gen_movi_i32(ret, 0);
7135 gen_set_label(l2);
7136 tcg_temp_free_i32(t0);
7137 }
7138 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7139 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7140 {
7141 TCGv_i32 t0;
7142 int l1, l2;
7143
7144 l1 = gen_new_label();
7145 l2 = gen_new_label();
7146 t0 = tcg_temp_local_new_i32();
7147 /* No error here: 6 bits are used */
7148 tcg_gen_andi_i32(t0, arg2, 0x3F);
7149 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7150 tcg_gen_shl_i32(ret, arg1, t0);
7151 tcg_gen_br(l2);
7152 gen_set_label(l1);
7153 tcg_gen_movi_i32(ret, 0);
7154 gen_set_label(l2);
7155 tcg_temp_free_i32(t0);
7156 }
7157 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7158 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7159 {
7160 TCGv_i32 t0 = tcg_temp_new_i32();
7161 tcg_gen_andi_i32(t0, arg2, 0x1F);
7162 tcg_gen_rotl_i32(ret, arg1, t0);
7163 tcg_temp_free_i32(t0);
7164 }
7165 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7166 static inline void gen_evmergehi(DisasContext *ctx)
7167 {
7168 if (unlikely(!ctx->spe_enabled)) {
7169 gen_exception(ctx, POWERPC_EXCP_SPEU);
7170 return;
7171 }
7172 #if defined(TARGET_PPC64)
7173 TCGv t0 = tcg_temp_new();
7174 TCGv t1 = tcg_temp_new();
7175 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7176 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7177 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7178 tcg_temp_free(t0);
7179 tcg_temp_free(t1);
7180 #else
7181 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7182 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7183 #endif
7184 }
7185 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7186 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7187 {
7188 tcg_gen_sub_i32(ret, arg2, arg1);
7189 }
7190 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7191
7192 /* SPE arithmetic immediate */
7193 #if defined(TARGET_PPC64)
7194 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7195 static inline void gen_##name(DisasContext *ctx) \
7196 { \
7197 if (unlikely(!ctx->spe_enabled)) { \
7198 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7199 return; \
7200 } \
7201 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7202 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7203 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7204 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7205 tcg_op(t0, t0, rA(ctx->opcode)); \
7206 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7207 tcg_gen_trunc_i64_i32(t1, t2); \
7208 tcg_temp_free_i64(t2); \
7209 tcg_op(t1, t1, rA(ctx->opcode)); \
7210 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7211 tcg_temp_free_i32(t0); \
7212 tcg_temp_free_i32(t1); \
7213 }
7214 #else
7215 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7216 static inline void gen_##name(DisasContext *ctx) \
7217 { \
7218 if (unlikely(!ctx->spe_enabled)) { \
7219 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7220 return; \
7221 } \
7222 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7223 rA(ctx->opcode)); \
7224 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7225 rA(ctx->opcode)); \
7226 }
7227 #endif
7228 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7229 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7230
7231 /* SPE comparison */
7232 #if defined(TARGET_PPC64)
7233 #define GEN_SPEOP_COMP(name, tcg_cond) \
7234 static inline void gen_##name(DisasContext *ctx) \
7235 { \
7236 if (unlikely(!ctx->spe_enabled)) { \
7237 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7238 return; \
7239 } \
7240 int l1 = gen_new_label(); \
7241 int l2 = gen_new_label(); \
7242 int l3 = gen_new_label(); \
7243 int l4 = gen_new_label(); \
7244 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7245 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7246 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7247 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7248 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7249 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7250 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7251 tcg_gen_br(l2); \
7252 gen_set_label(l1); \
7253 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7254 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7255 gen_set_label(l2); \
7256 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7257 tcg_gen_trunc_i64_i32(t0, t2); \
7258 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7259 tcg_gen_trunc_i64_i32(t1, t2); \
7260 tcg_temp_free_i64(t2); \
7261 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7262 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7263 ~(CRF_CH | CRF_CH_AND_CL)); \
7264 tcg_gen_br(l4); \
7265 gen_set_label(l3); \
7266 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7267 CRF_CH | CRF_CH_OR_CL); \
7268 gen_set_label(l4); \
7269 tcg_temp_free_i32(t0); \
7270 tcg_temp_free_i32(t1); \
7271 }
7272 #else
7273 #define GEN_SPEOP_COMP(name, tcg_cond) \
7274 static inline void gen_##name(DisasContext *ctx) \
7275 { \
7276 if (unlikely(!ctx->spe_enabled)) { \
7277 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7278 return; \
7279 } \
7280 int l1 = gen_new_label(); \
7281 int l2 = gen_new_label(); \
7282 int l3 = gen_new_label(); \
7283 int l4 = gen_new_label(); \
7284 \
7285 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7286 cpu_gpr[rB(ctx->opcode)], l1); \
7287 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7288 tcg_gen_br(l2); \
7289 gen_set_label(l1); \
7290 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7291 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7292 gen_set_label(l2); \
7293 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7294 cpu_gprh[rB(ctx->opcode)], l3); \
7295 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7296 ~(CRF_CH | CRF_CH_AND_CL)); \
7297 tcg_gen_br(l4); \
7298 gen_set_label(l3); \
7299 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7300 CRF_CH | CRF_CH_OR_CL); \
7301 gen_set_label(l4); \
7302 }
7303 #endif
7304 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7305 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7306 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7307 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7308 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7309
7310 /* SPE misc */
7311 static inline void gen_brinc(DisasContext *ctx)
7312 {
7313 /* Note: brinc is usable even if SPE is disabled */
7314 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7315 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7316 }
7317 static inline void gen_evmergelo(DisasContext *ctx)
7318 {
7319 if (unlikely(!ctx->spe_enabled)) {
7320 gen_exception(ctx, POWERPC_EXCP_SPEU);
7321 return;
7322 }
7323 #if defined(TARGET_PPC64)
7324 TCGv t0 = tcg_temp_new();
7325 TCGv t1 = tcg_temp_new();
7326 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7327 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7328 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7329 tcg_temp_free(t0);
7330 tcg_temp_free(t1);
7331 #else
7332 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7333 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7334 #endif
7335 }
7336 static inline void gen_evmergehilo(DisasContext *ctx)
7337 {
7338 if (unlikely(!ctx->spe_enabled)) {
7339 gen_exception(ctx, POWERPC_EXCP_SPEU);
7340 return;
7341 }
7342 #if defined(TARGET_PPC64)
7343 TCGv t0 = tcg_temp_new();
7344 TCGv t1 = tcg_temp_new();
7345 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7346 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7347 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7348 tcg_temp_free(t0);
7349 tcg_temp_free(t1);
7350 #else
7351 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7352 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7353 #endif
7354 }
7355 static inline void gen_evmergelohi(DisasContext *ctx)
7356 {
7357 if (unlikely(!ctx->spe_enabled)) {
7358 gen_exception(ctx, POWERPC_EXCP_SPEU);
7359 return;
7360 }
7361 #if defined(TARGET_PPC64)
7362 TCGv t0 = tcg_temp_new();
7363 TCGv t1 = tcg_temp_new();
7364 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7365 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7366 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7367 tcg_temp_free(t0);
7368 tcg_temp_free(t1);
7369 #else
7370 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7371 TCGv_i32 tmp = tcg_temp_new_i32();
7372 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7373 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7374 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7375 tcg_temp_free_i32(tmp);
7376 } else {
7377 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7378 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7379 }
7380 #endif
7381 }
7382 static inline void gen_evsplati(DisasContext *ctx)
7383 {
7384 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7385
7386 #if defined(TARGET_PPC64)
7387 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7388 #else
7389 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7390 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7391 #endif
7392 }
7393 static inline void gen_evsplatfi(DisasContext *ctx)
7394 {
7395 uint64_t imm = rA(ctx->opcode) << 27;
7396
7397 #if defined(TARGET_PPC64)
7398 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7399 #else
7400 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7401 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7402 #endif
7403 }
7404
7405 static inline void gen_evsel(DisasContext *ctx)
7406 {
7407 int l1 = gen_new_label();
7408 int l2 = gen_new_label();
7409 int l3 = gen_new_label();
7410 int l4 = gen_new_label();
7411 TCGv_i32 t0 = tcg_temp_local_new_i32();
7412 #if defined(TARGET_PPC64)
7413 TCGv t1 = tcg_temp_local_new();
7414 TCGv t2 = tcg_temp_local_new();
7415 #endif
7416 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7417 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7418 #if defined(TARGET_PPC64)
7419 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7420 #else
7421 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7422 #endif
7423 tcg_gen_br(l2);
7424 gen_set_label(l1);
7425 #if defined(TARGET_PPC64)
7426 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7427 #else
7428 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7429 #endif
7430 gen_set_label(l2);
7431 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7432 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7433 #if defined(TARGET_PPC64)
7434 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7435 #else
7436 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7437 #endif
7438 tcg_gen_br(l4);
7439 gen_set_label(l3);
7440 #if defined(TARGET_PPC64)
7441 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7442 #else
7443 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7444 #endif
7445 gen_set_label(l4);
7446 tcg_temp_free_i32(t0);
7447 #if defined(TARGET_PPC64)
7448 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7449 tcg_temp_free(t1);
7450 tcg_temp_free(t2);
7451 #endif
7452 }
7453
7454 static void gen_evsel0(DisasContext *ctx)
7455 {
7456 gen_evsel(ctx);
7457 }
7458
7459 static void gen_evsel1(DisasContext *ctx)
7460 {
7461 gen_evsel(ctx);
7462 }
7463
7464 static void gen_evsel2(DisasContext *ctx)
7465 {
7466 gen_evsel(ctx);
7467 }
7468
7469 static void gen_evsel3(DisasContext *ctx)
7470 {
7471 gen_evsel(ctx);
7472 }
7473
7474 /* Multiply */
7475
7476 static inline void gen_evmwumi(DisasContext *ctx)
7477 {
7478 TCGv_i64 t0, t1;
7479
7480 if (unlikely(!ctx->spe_enabled)) {
7481 gen_exception(ctx, POWERPC_EXCP_SPEU);
7482 return;
7483 }
7484
7485 t0 = tcg_temp_new_i64();
7486 t1 = tcg_temp_new_i64();
7487
7488 /* t0 := rA; t1 := rB */
7489 #if defined(TARGET_PPC64)
7490 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7491 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7492 #else
7493 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7494 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7495 #endif
7496
7497 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7498
7499 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7500
7501 tcg_temp_free_i64(t0);
7502 tcg_temp_free_i64(t1);
7503 }
7504
7505 static inline void gen_evmwumia(DisasContext *ctx)
7506 {
7507 TCGv_i64 tmp;
7508
7509 if (unlikely(!ctx->spe_enabled)) {
7510 gen_exception(ctx, POWERPC_EXCP_SPEU);
7511 return;
7512 }
7513
7514 gen_evmwumi(ctx); /* rD := rA * rB */
7515
7516 tmp = tcg_temp_new_i64();
7517
7518 /* acc := rD */
7519 gen_load_gpr64(tmp, rD(ctx->opcode));
7520 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7521 tcg_temp_free_i64(tmp);
7522 }
7523
7524 static inline void gen_evmwumiaa(DisasContext *ctx)
7525 {
7526 TCGv_i64 acc;
7527 TCGv_i64 tmp;
7528
7529 if (unlikely(!ctx->spe_enabled)) {
7530 gen_exception(ctx, POWERPC_EXCP_SPEU);
7531 return;
7532 }
7533
7534 gen_evmwumi(ctx); /* rD := rA * rB */
7535
7536 acc = tcg_temp_new_i64();
7537 tmp = tcg_temp_new_i64();
7538
7539 /* tmp := rD */
7540 gen_load_gpr64(tmp, rD(ctx->opcode));
7541
7542 /* Load acc */
7543 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7544
7545 /* acc := tmp + acc */
7546 tcg_gen_add_i64(acc, acc, tmp);
7547
7548 /* Store acc */
7549 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7550
7551 /* rD := acc */
7552 gen_store_gpr64(rD(ctx->opcode), acc);
7553
7554 tcg_temp_free_i64(acc);
7555 tcg_temp_free_i64(tmp);
7556 }
7557
7558 static inline void gen_evmwsmi(DisasContext *ctx)
7559 {
7560 TCGv_i64 t0, t1;
7561
7562 if (unlikely(!ctx->spe_enabled)) {
7563 gen_exception(ctx, POWERPC_EXCP_SPEU);
7564 return;
7565 }
7566
7567 t0 = tcg_temp_new_i64();
7568 t1 = tcg_temp_new_i64();
7569
7570 /* t0 := rA; t1 := rB */
7571 #if defined(TARGET_PPC64)
7572 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7573 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7574 #else
7575 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7576 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7577 #endif
7578
7579 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7580
7581 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7582
7583 tcg_temp_free_i64(t0);
7584 tcg_temp_free_i64(t1);
7585 }
7586
7587 static inline void gen_evmwsmia(DisasContext *ctx)
7588 {
7589 TCGv_i64 tmp;
7590
7591 gen_evmwsmi(ctx); /* rD := rA * rB */
7592
7593 tmp = tcg_temp_new_i64();
7594
7595 /* acc := rD */
7596 gen_load_gpr64(tmp, rD(ctx->opcode));
7597 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7598
7599 tcg_temp_free_i64(tmp);
7600 }
7601
7602 static inline void gen_evmwsmiaa(DisasContext *ctx)
7603 {
7604 TCGv_i64 acc = tcg_temp_new_i64();
7605 TCGv_i64 tmp = tcg_temp_new_i64();
7606
7607 gen_evmwsmi(ctx); /* rD := rA * rB */
7608
7609 acc = tcg_temp_new_i64();
7610 tmp = tcg_temp_new_i64();
7611
7612 /* tmp := rD */
7613 gen_load_gpr64(tmp, rD(ctx->opcode));
7614
7615 /* Load acc */
7616 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7617
7618 /* acc := tmp + acc */
7619 tcg_gen_add_i64(acc, acc, tmp);
7620
7621 /* Store acc */
7622 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7623
7624 /* rD := acc */
7625 gen_store_gpr64(rD(ctx->opcode), acc);
7626
7627 tcg_temp_free_i64(acc);
7628 tcg_temp_free_i64(tmp);
7629 }
7630
7631 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7632 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7633 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7634 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7635 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7636 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7637 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7638 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7639 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7640 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7641 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7642 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7643 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7644 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7645 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7646 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7647 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7648 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7649 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7650 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7651 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7652 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7653 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7654 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7655 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7656 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7657 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7658 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7659 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7660
7661 /* SPE load and stores */
7662 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7663 {
7664 target_ulong uimm = rB(ctx->opcode);
7665
7666 if (rA(ctx->opcode) == 0) {
7667 tcg_gen_movi_tl(EA, uimm << sh);
7668 } else {
7669 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7670 #if defined(TARGET_PPC64)
7671 if (!ctx->sf_mode) {
7672 tcg_gen_ext32u_tl(EA, EA);
7673 }
7674 #endif
7675 }
7676 }
7677
7678 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7679 {
7680 #if defined(TARGET_PPC64)
7681 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7682 #else
7683 TCGv_i64 t0 = tcg_temp_new_i64();
7684 gen_qemu_ld64(ctx, t0, addr);
7685 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7686 tcg_gen_shri_i64(t0, t0, 32);
7687 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7688 tcg_temp_free_i64(t0);
7689 #endif
7690 }
7691
7692 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7693 {
7694 #if defined(TARGET_PPC64)
7695 TCGv t0 = tcg_temp_new();
7696 gen_qemu_ld32u(ctx, t0, addr);
7697 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7698 gen_addr_add(ctx, addr, addr, 4);
7699 gen_qemu_ld32u(ctx, t0, addr);
7700 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7701 tcg_temp_free(t0);
7702 #else
7703 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7704 gen_addr_add(ctx, addr, addr, 4);
7705 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7706 #endif
7707 }
7708
7709 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7710 {
7711 TCGv t0 = tcg_temp_new();
7712 #if defined(TARGET_PPC64)
7713 gen_qemu_ld16u(ctx, t0, addr);
7714 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7715 gen_addr_add(ctx, addr, addr, 2);
7716 gen_qemu_ld16u(ctx, t0, addr);
7717 tcg_gen_shli_tl(t0, t0, 32);
7718 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7719 gen_addr_add(ctx, addr, addr, 2);
7720 gen_qemu_ld16u(ctx, t0, addr);
7721 tcg_gen_shli_tl(t0, t0, 16);
7722 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7723 gen_addr_add(ctx, addr, addr, 2);
7724 gen_qemu_ld16u(ctx, t0, addr);
7725 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7726 #else
7727 gen_qemu_ld16u(ctx, t0, addr);
7728 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7729 gen_addr_add(ctx, addr, addr, 2);
7730 gen_qemu_ld16u(ctx, t0, addr);
7731 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7732 gen_addr_add(ctx, addr, addr, 2);
7733 gen_qemu_ld16u(ctx, t0, addr);
7734 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7735 gen_addr_add(ctx, addr, addr, 2);
7736 gen_qemu_ld16u(ctx, t0, addr);
7737 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7738 #endif
7739 tcg_temp_free(t0);
7740 }
7741
7742 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7743 {
7744 TCGv t0 = tcg_temp_new();
7745 gen_qemu_ld16u(ctx, t0, addr);
7746 #if defined(TARGET_PPC64)
7747 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7748 tcg_gen_shli_tl(t0, t0, 16);
7749 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7750 #else
7751 tcg_gen_shli_tl(t0, t0, 16);
7752 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7753 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7754 #endif
7755 tcg_temp_free(t0);
7756 }
7757
7758 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7759 {
7760 TCGv t0 = tcg_temp_new();
7761 gen_qemu_ld16u(ctx, t0, addr);
7762 #if defined(TARGET_PPC64)
7763 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7764 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7765 #else
7766 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7767 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7768 #endif
7769 tcg_temp_free(t0);
7770 }
7771
7772 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7773 {
7774 TCGv t0 = tcg_temp_new();
7775 gen_qemu_ld16s(ctx, t0, addr);
7776 #if defined(TARGET_PPC64)
7777 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7778 tcg_gen_ext32u_tl(t0, t0);
7779 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7780 #else
7781 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7782 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7783 #endif
7784 tcg_temp_free(t0);
7785 }
7786
7787 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7788 {
7789 TCGv t0 = tcg_temp_new();
7790 #if defined(TARGET_PPC64)
7791 gen_qemu_ld16u(ctx, t0, addr);
7792 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7793 gen_addr_add(ctx, addr, addr, 2);
7794 gen_qemu_ld16u(ctx, t0, addr);
7795 tcg_gen_shli_tl(t0, t0, 16);
7796 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7797 #else
7798 gen_qemu_ld16u(ctx, t0, addr);
7799 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7800 gen_addr_add(ctx, addr, addr, 2);
7801 gen_qemu_ld16u(ctx, t0, addr);
7802 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7803 #endif
7804 tcg_temp_free(t0);
7805 }
7806
7807 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7808 {
7809 #if defined(TARGET_PPC64)
7810 TCGv t0 = tcg_temp_new();
7811 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7812 gen_addr_add(ctx, addr, addr, 2);
7813 gen_qemu_ld16u(ctx, t0, addr);
7814 tcg_gen_shli_tl(t0, t0, 32);
7815 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7816 tcg_temp_free(t0);
7817 #else
7818 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7819 gen_addr_add(ctx, addr, addr, 2);
7820 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7821 #endif
7822 }
7823
7824 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7825 {
7826 #if defined(TARGET_PPC64)
7827 TCGv t0 = tcg_temp_new();
7828 gen_qemu_ld16s(ctx, t0, addr);
7829 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7830 gen_addr_add(ctx, addr, addr, 2);
7831 gen_qemu_ld16s(ctx, t0, addr);
7832 tcg_gen_shli_tl(t0, t0, 32);
7833 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7834 tcg_temp_free(t0);
7835 #else
7836 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7837 gen_addr_add(ctx, addr, addr, 2);
7838 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7839 #endif
7840 }
7841
7842 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7843 {
7844 TCGv t0 = tcg_temp_new();
7845 gen_qemu_ld32u(ctx, t0, addr);
7846 #if defined(TARGET_PPC64)
7847 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7848 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7849 #else
7850 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7851 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7852 #endif
7853 tcg_temp_free(t0);
7854 }
7855
7856 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7857 {
7858 TCGv t0 = tcg_temp_new();
7859 #if defined(TARGET_PPC64)
7860 gen_qemu_ld16u(ctx, t0, addr);
7861 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7862 tcg_gen_shli_tl(t0, t0, 32);
7863 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7864 gen_addr_add(ctx, addr, addr, 2);
7865 gen_qemu_ld16u(ctx, t0, addr);
7866 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7867 tcg_gen_shli_tl(t0, t0, 16);
7868 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7869 #else
7870 gen_qemu_ld16u(ctx, t0, addr);
7871 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7872 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7873 gen_addr_add(ctx, addr, addr, 2);
7874 gen_qemu_ld16u(ctx, t0, addr);
7875 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7876 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7877 #endif
7878 tcg_temp_free(t0);
7879 }
7880
7881 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7882 {
7883 #if defined(TARGET_PPC64)
7884 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7885 #else
7886 TCGv_i64 t0 = tcg_temp_new_i64();
7887 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7888 gen_qemu_st64(ctx, t0, addr);
7889 tcg_temp_free_i64(t0);
7890 #endif
7891 }
7892
7893 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7894 {
7895 #if defined(TARGET_PPC64)
7896 TCGv t0 = tcg_temp_new();
7897 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7898 gen_qemu_st32(ctx, t0, addr);
7899 tcg_temp_free(t0);
7900 #else
7901 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7902 #endif
7903 gen_addr_add(ctx, addr, addr, 4);
7904 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7905 }
7906
7907 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7908 {
7909 TCGv t0 = tcg_temp_new();
7910 #if defined(TARGET_PPC64)
7911 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7912 #else
7913 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7914 #endif
7915 gen_qemu_st16(ctx, t0, addr);
7916 gen_addr_add(ctx, addr, addr, 2);
7917 #if defined(TARGET_PPC64)
7918 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7919 gen_qemu_st16(ctx, t0, addr);
7920 #else
7921 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7922 #endif
7923 gen_addr_add(ctx, addr, addr, 2);
7924 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7925 gen_qemu_st16(ctx, t0, addr);
7926 tcg_temp_free(t0);
7927 gen_addr_add(ctx, addr, addr, 2);
7928 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7929 }
7930
7931 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7932 {
7933 TCGv t0 = tcg_temp_new();
7934 #if defined(TARGET_PPC64)
7935 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7936 #else
7937 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7938 #endif
7939 gen_qemu_st16(ctx, t0, addr);
7940 gen_addr_add(ctx, addr, addr, 2);
7941 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7942 gen_qemu_st16(ctx, t0, addr);
7943 tcg_temp_free(t0);
7944 }
7945
7946 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7947 {
7948 #if defined(TARGET_PPC64)
7949 TCGv t0 = tcg_temp_new();
7950 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7951 gen_qemu_st16(ctx, t0, addr);
7952 tcg_temp_free(t0);
7953 #else
7954 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7955 #endif
7956 gen_addr_add(ctx, addr, addr, 2);
7957 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7958 }
7959
7960 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7961 {
7962 #if defined(TARGET_PPC64)
7963 TCGv t0 = tcg_temp_new();
7964 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7965 gen_qemu_st32(ctx, t0, addr);
7966 tcg_temp_free(t0);
7967 #else
7968 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7969 #endif
7970 }
7971
7972 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7973 {
7974 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7975 }
7976
7977 #define GEN_SPEOP_LDST(name, opc2, sh) \
7978 static void glue(gen_, name)(DisasContext *ctx) \
7979 { \
7980 TCGv t0; \
7981 if (unlikely(!ctx->spe_enabled)) { \
7982 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7983 return; \
7984 } \
7985 gen_set_access_type(ctx, ACCESS_INT); \
7986 t0 = tcg_temp_new(); \
7987 if (Rc(ctx->opcode)) { \
7988 gen_addr_spe_imm_index(ctx, t0, sh); \
7989 } else { \
7990 gen_addr_reg_index(ctx, t0); \
7991 } \
7992 gen_op_##name(ctx, t0); \
7993 tcg_temp_free(t0); \
7994 }
7995
7996 GEN_SPEOP_LDST(evldd, 0x00, 3);
7997 GEN_SPEOP_LDST(evldw, 0x01, 3);
7998 GEN_SPEOP_LDST(evldh, 0x02, 3);
7999 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
8000 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
8001 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
8002 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
8003 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
8004 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
8005 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
8006 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
8007
8008 GEN_SPEOP_LDST(evstdd, 0x10, 3);
8009 GEN_SPEOP_LDST(evstdw, 0x11, 3);
8010 GEN_SPEOP_LDST(evstdh, 0x12, 3);
8011 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
8012 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
8013 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
8014 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
8015
8016 /* Multiply and add - TODO */
8017 #if 0
8018 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
8019 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8020 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8021 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8022 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8023 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8024 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8025 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8026 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8027 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8028 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8029 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8030
8031 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8032 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8033 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8034 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8035 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8036 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8037 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8038 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8039 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8040 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8041 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8042 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8043
8044 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8045 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8046 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8047 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8048 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8049
8050 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8051 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8052 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8053 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8054 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8055 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8056 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8057 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8058 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8059 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8060 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8061 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8062
8063 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8064 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8065 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8066 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8067
8068 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8069 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8070 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8071 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8072 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8073 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8074 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8075 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8076 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8077 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8078 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8079 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8080
8081 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8082 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8083 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8084 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8085 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8086 #endif
8087
8088 /*** SPE floating-point extension ***/
8089 #if defined(TARGET_PPC64)
8090 #define GEN_SPEFPUOP_CONV_32_32(name) \
8091 static inline void gen_##name(DisasContext *ctx) \
8092 { \
8093 TCGv_i32 t0; \
8094 TCGv t1; \
8095 t0 = tcg_temp_new_i32(); \
8096 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8097 gen_helper_##name(t0, cpu_env, t0); \
8098 t1 = tcg_temp_new(); \
8099 tcg_gen_extu_i32_tl(t1, t0); \
8100 tcg_temp_free_i32(t0); \
8101 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8102 0xFFFFFFFF00000000ULL); \
8103 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8104 tcg_temp_free(t1); \
8105 }
8106 #define GEN_SPEFPUOP_CONV_32_64(name) \
8107 static inline void gen_##name(DisasContext *ctx) \
8108 { \
8109 TCGv_i32 t0; \
8110 TCGv t1; \
8111 t0 = tcg_temp_new_i32(); \
8112 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8113 t1 = tcg_temp_new(); \
8114 tcg_gen_extu_i32_tl(t1, t0); \
8115 tcg_temp_free_i32(t0); \
8116 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8117 0xFFFFFFFF00000000ULL); \
8118 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8119 tcg_temp_free(t1); \
8120 }
8121 #define GEN_SPEFPUOP_CONV_64_32(name) \
8122 static inline void gen_##name(DisasContext *ctx) \
8123 { \
8124 TCGv_i32 t0 = tcg_temp_new_i32(); \
8125 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8126 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8127 tcg_temp_free_i32(t0); \
8128 }
8129 #define GEN_SPEFPUOP_CONV_64_64(name) \
8130 static inline void gen_##name(DisasContext *ctx) \
8131 { \
8132 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8133 cpu_gpr[rB(ctx->opcode)]); \
8134 }
8135 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8136 static inline void gen_##name(DisasContext *ctx) \
8137 { \
8138 TCGv_i32 t0, t1; \
8139 TCGv_i64 t2; \
8140 if (unlikely(!ctx->spe_enabled)) { \
8141 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8142 return; \
8143 } \
8144 t0 = tcg_temp_new_i32(); \
8145 t1 = tcg_temp_new_i32(); \
8146 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8147 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8148 gen_helper_##name(t0, cpu_env, t0, t1); \
8149 tcg_temp_free_i32(t1); \
8150 t2 = tcg_temp_new(); \
8151 tcg_gen_extu_i32_tl(t2, t0); \
8152 tcg_temp_free_i32(t0); \
8153 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8154 0xFFFFFFFF00000000ULL); \
8155 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8156 tcg_temp_free(t2); \
8157 }
8158 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8159 static inline void gen_##name(DisasContext *ctx) \
8160 { \
8161 if (unlikely(!ctx->spe_enabled)) { \
8162 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8163 return; \
8164 } \
8165 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8166 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8167 }
8168 #define GEN_SPEFPUOP_COMP_32(name) \
8169 static inline void gen_##name(DisasContext *ctx) \
8170 { \
8171 TCGv_i32 t0, t1; \
8172 if (unlikely(!ctx->spe_enabled)) { \
8173 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8174 return; \
8175 } \
8176 t0 = tcg_temp_new_i32(); \
8177 t1 = tcg_temp_new_i32(); \
8178 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8179 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8180 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8181 tcg_temp_free_i32(t0); \
8182 tcg_temp_free_i32(t1); \
8183 }
8184 #define GEN_SPEFPUOP_COMP_64(name) \
8185 static inline void gen_##name(DisasContext *ctx) \
8186 { \
8187 if (unlikely(!ctx->spe_enabled)) { \
8188 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8189 return; \
8190 } \
8191 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8192 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8193 }
8194 #else
8195 #define GEN_SPEFPUOP_CONV_32_32(name) \
8196 static inline void gen_##name(DisasContext *ctx) \
8197 { \
8198 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8199 cpu_gpr[rB(ctx->opcode)]); \
8200 }
8201 #define GEN_SPEFPUOP_CONV_32_64(name) \
8202 static inline void gen_##name(DisasContext *ctx) \
8203 { \
8204 TCGv_i64 t0 = tcg_temp_new_i64(); \
8205 gen_load_gpr64(t0, rB(ctx->opcode)); \
8206 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8207 tcg_temp_free_i64(t0); \
8208 }
8209 #define GEN_SPEFPUOP_CONV_64_32(name) \
8210 static inline void gen_##name(DisasContext *ctx) \
8211 { \
8212 TCGv_i64 t0 = tcg_temp_new_i64(); \
8213 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8214 gen_store_gpr64(rD(ctx->opcode), t0); \
8215 tcg_temp_free_i64(t0); \
8216 }
8217 #define GEN_SPEFPUOP_CONV_64_64(name) \
8218 static inline void gen_##name(DisasContext *ctx) \
8219 { \
8220 TCGv_i64 t0 = tcg_temp_new_i64(); \
8221 gen_load_gpr64(t0, rB(ctx->opcode)); \
8222 gen_helper_##name(t0, cpu_env, t0); \
8223 gen_store_gpr64(rD(ctx->opcode), t0); \
8224 tcg_temp_free_i64(t0); \
8225 }
8226 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8227 static inline void gen_##name(DisasContext *ctx) \
8228 { \
8229 if (unlikely(!ctx->spe_enabled)) { \
8230 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8231 return; \
8232 } \
8233 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8234 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8235 }
8236 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8237 static inline void gen_##name(DisasContext *ctx) \
8238 { \
8239 TCGv_i64 t0, t1; \
8240 if (unlikely(!ctx->spe_enabled)) { \
8241 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8242 return; \
8243 } \
8244 t0 = tcg_temp_new_i64(); \
8245 t1 = tcg_temp_new_i64(); \
8246 gen_load_gpr64(t0, rA(ctx->opcode)); \
8247 gen_load_gpr64(t1, rB(ctx->opcode)); \
8248 gen_helper_##name(t0, cpu_env, t0, t1); \
8249 gen_store_gpr64(rD(ctx->opcode), t0); \
8250 tcg_temp_free_i64(t0); \
8251 tcg_temp_free_i64(t1); \
8252 }
8253 #define GEN_SPEFPUOP_COMP_32(name) \
8254 static inline void gen_##name(DisasContext *ctx) \
8255 { \
8256 if (unlikely(!ctx->spe_enabled)) { \
8257 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8258 return; \
8259 } \
8260 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8261 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8262 }
8263 #define GEN_SPEFPUOP_COMP_64(name) \
8264 static inline void gen_##name(DisasContext *ctx) \
8265 { \
8266 TCGv_i64 t0, t1; \
8267 if (unlikely(!ctx->spe_enabled)) { \
8268 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8269 return; \
8270 } \
8271 t0 = tcg_temp_new_i64(); \
8272 t1 = tcg_temp_new_i64(); \
8273 gen_load_gpr64(t0, rA(ctx->opcode)); \
8274 gen_load_gpr64(t1, rB(ctx->opcode)); \
8275 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8276 tcg_temp_free_i64(t0); \
8277 tcg_temp_free_i64(t1); \
8278 }
8279 #endif
8280
8281 /* Single precision floating-point vectors operations */
8282 /* Arithmetic */
8283 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8284 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8285 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8286 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8287 static inline void gen_evfsabs(DisasContext *ctx)
8288 {
8289 if (unlikely(!ctx->spe_enabled)) {
8290 gen_exception(ctx, POWERPC_EXCP_SPEU);
8291 return;
8292 }
8293 #if defined(TARGET_PPC64)
8294 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8295 #else
8296 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8297 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8298 #endif
8299 }
8300 static inline void gen_evfsnabs(DisasContext *ctx)
8301 {
8302 if (unlikely(!ctx->spe_enabled)) {
8303 gen_exception(ctx, POWERPC_EXCP_SPEU);
8304 return;
8305 }
8306 #if defined(TARGET_PPC64)
8307 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8308 #else
8309 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8310 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8311 #endif
8312 }
8313 static inline void gen_evfsneg(DisasContext *ctx)
8314 {
8315 if (unlikely(!ctx->spe_enabled)) {
8316 gen_exception(ctx, POWERPC_EXCP_SPEU);
8317 return;
8318 }
8319 #if defined(TARGET_PPC64)
8320 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8321 #else
8322 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8323 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8324 #endif
8325 }
8326
8327 /* Conversion */
8328 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8329 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8330 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8331 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8332 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8333 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8334 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8335 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8336 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8337 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8338
8339 /* Comparison */
8340 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8341 GEN_SPEFPUOP_COMP_64(evfscmplt);
8342 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8343 GEN_SPEFPUOP_COMP_64(evfststgt);
8344 GEN_SPEFPUOP_COMP_64(evfststlt);
8345 GEN_SPEFPUOP_COMP_64(evfststeq);
8346
8347 /* Opcodes definitions */
8348 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8349 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8350 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8351 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8352 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8353 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8354 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8355 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8356 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8357 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8358 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8359 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8360 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8361 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8362
8363 /* Single precision floating-point operations */
8364 /* Arithmetic */
8365 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8366 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8367 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8368 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8369 static inline void gen_efsabs(DisasContext *ctx)
8370 {
8371 if (unlikely(!ctx->spe_enabled)) {
8372 gen_exception(ctx, POWERPC_EXCP_SPEU);
8373 return;
8374 }
8375 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8376 }
8377 static inline void gen_efsnabs(DisasContext *ctx)
8378 {
8379 if (unlikely(!ctx->spe_enabled)) {
8380 gen_exception(ctx, POWERPC_EXCP_SPEU);
8381 return;
8382 }
8383 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8384 }
8385 static inline void gen_efsneg(DisasContext *ctx)
8386 {
8387 if (unlikely(!ctx->spe_enabled)) {
8388 gen_exception(ctx, POWERPC_EXCP_SPEU);
8389 return;
8390 }
8391 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8392 }
8393
8394 /* Conversion */
8395 GEN_SPEFPUOP_CONV_32_32(efscfui);
8396 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8397 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8398 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8399 GEN_SPEFPUOP_CONV_32_32(efsctui);
8400 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8401 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8402 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8403 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8404 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8405 GEN_SPEFPUOP_CONV_32_64(efscfd);
8406
8407 /* Comparison */
8408 GEN_SPEFPUOP_COMP_32(efscmpgt);
8409 GEN_SPEFPUOP_COMP_32(efscmplt);
8410 GEN_SPEFPUOP_COMP_32(efscmpeq);
8411 GEN_SPEFPUOP_COMP_32(efststgt);
8412 GEN_SPEFPUOP_COMP_32(efststlt);
8413 GEN_SPEFPUOP_COMP_32(efststeq);
8414
8415 /* Opcodes definitions */
8416 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8417 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8418 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8419 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8420 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8421 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8422 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8423 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8424 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8425 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8426 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8427 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8428 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8429 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8430
8431 /* Double precision floating-point operations */
8432 /* Arithmetic */
8433 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8434 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8435 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8436 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8437 static inline void gen_efdabs(DisasContext *ctx)
8438 {
8439 if (unlikely(!ctx->spe_enabled)) {
8440 gen_exception(ctx, POWERPC_EXCP_SPEU);
8441 return;
8442 }
8443 #if defined(TARGET_PPC64)
8444 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8445 #else
8446 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8447 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8448 #endif
8449 }
8450 static inline void gen_efdnabs(DisasContext *ctx)
8451 {
8452 if (unlikely(!ctx->spe_enabled)) {
8453 gen_exception(ctx, POWERPC_EXCP_SPEU);
8454 return;
8455 }
8456 #if defined(TARGET_PPC64)
8457 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8458 #else
8459 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8460 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8461 #endif
8462 }
8463 static inline void gen_efdneg(DisasContext *ctx)
8464 {
8465 if (unlikely(!ctx->spe_enabled)) {
8466 gen_exception(ctx, POWERPC_EXCP_SPEU);
8467 return;
8468 }
8469 #if defined(TARGET_PPC64)
8470 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8471 #else
8472 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8473 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8474 #endif
8475 }
8476
8477 /* Conversion */
8478 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8479 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8480 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8481 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8482 GEN_SPEFPUOP_CONV_32_64(efdctui);
8483 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8484 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8485 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8486 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8487 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8488 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8489 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8490 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8491 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8492 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8493
8494 /* Comparison */
8495 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8496 GEN_SPEFPUOP_COMP_64(efdcmplt);
8497 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8498 GEN_SPEFPUOP_COMP_64(efdtstgt);
8499 GEN_SPEFPUOP_COMP_64(efdtstlt);
8500 GEN_SPEFPUOP_COMP_64(efdtsteq);
8501
8502 /* Opcodes definitions */
8503 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8504 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8505 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8506 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8507 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8508 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8509 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8510 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8511 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8512 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8513 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8514 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8515 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8516 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8517 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8518 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8519
8520 static opcode_t opcodes[] = {
8521 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8522 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8523 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8524 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8525 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8526 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8527 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8528 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8529 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8530 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8531 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8532 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8533 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8534 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8535 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8536 #if defined(TARGET_PPC64)
8537 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8538 #endif
8539 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8540 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8541 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8542 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8543 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8544 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8545 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8546 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8547 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8548 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8549 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8550 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8551 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8552 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8553 #if defined(TARGET_PPC64)
8554 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8555 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8556 #endif
8557 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8558 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8559 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8560 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8561 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8562 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8563 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8564 #if defined(TARGET_PPC64)
8565 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8566 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8567 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8568 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8569 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8570 #endif
8571 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8572 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8573 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8574 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8575 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8576 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8577 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8578 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8579 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8580 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8581 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8582 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8583 #if defined(TARGET_PPC64)
8584 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8585 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8586 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8587 #endif
8588 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8589 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8590 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8591 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8592 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8593 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8594 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8595 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8596 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8597 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8598 #if defined(TARGET_PPC64)
8599 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8600 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8601 #endif
8602 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8603 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8604 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8605 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8606 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8607 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8608 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8609 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8610 #if defined(TARGET_PPC64)
8611 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8612 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8613 #endif
8614 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8615 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8616 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8617 #if defined(TARGET_PPC64)
8618 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8619 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8620 #endif
8621 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8622 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8623 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8624 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8625 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8626 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8627 #if defined(TARGET_PPC64)
8628 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8629 #endif
8630 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8631 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8632 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8633 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8634 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8635 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8636 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8637 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8638 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8639 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8640 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8641 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8642 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8643 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8644 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8645 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8646 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8647 #if defined(TARGET_PPC64)
8648 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8649 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8650 PPC_SEGMENT_64B),
8651 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8652 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8653 PPC_SEGMENT_64B),
8654 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8655 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8656 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8657 #endif
8658 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8659 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8660 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8661 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8662 #if defined(TARGET_PPC64)
8663 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8664 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8665 #endif
8666 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8667 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8668 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8669 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8670 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8671 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8672 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8673 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8674 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8675 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8676 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8677 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8678 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8679 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8680 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8681 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8682 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8683 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8684 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8685 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8686 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8687 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8688 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8689 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8690 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8691 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8692 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8693 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8694 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8695 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8696 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8697 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8698 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8699 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8700 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8701 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8702 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8703 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8704 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8705 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8706 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8707 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8708 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8709 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8710 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8711 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8712 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8713 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8714 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8715 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8716 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8717 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8718 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8719 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8720 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8721 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8722 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8723 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8724 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8725 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8726 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8727 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8728 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8729 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8730 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8731 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8732 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8733 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8734 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8735 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8736 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8737 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8738 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8739 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8740 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8741 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8742 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8743 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8744 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8745 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8746 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8747 PPC_NONE, PPC2_BOOKE206),
8748 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8749 PPC_NONE, PPC2_BOOKE206),
8750 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8751 PPC_NONE, PPC2_BOOKE206),
8752 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8753 PPC_NONE, PPC2_BOOKE206),
8754 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8755 PPC_NONE, PPC2_BOOKE206),
8756 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8757 PPC_NONE, PPC2_PRCNTL),
8758 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8759 PPC_NONE, PPC2_PRCNTL),
8760 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8761 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8762 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8763 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8764 PPC_BOOKE, PPC2_BOOKE206),
8765 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8766 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8767 PPC_BOOKE, PPC2_BOOKE206),
8768 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8769 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8770 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8771 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8772 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8773 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8774 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8775 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8776 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8777 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8778
8779 #undef GEN_INT_ARITH_ADD
8780 #undef GEN_INT_ARITH_ADD_CONST
8781 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8782 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8783 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8784 add_ca, compute_ca, compute_ov) \
8785 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8786 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8787 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8788 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8789 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8790 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8791 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8792 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8793 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8794 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8795 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8796
8797 #undef GEN_INT_ARITH_DIVW
8798 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8799 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8800 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8801 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8802 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8803 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8804
8805 #if defined(TARGET_PPC64)
8806 #undef GEN_INT_ARITH_DIVD
8807 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8808 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8809 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8810 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8811 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8812 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8813
8814 #undef GEN_INT_ARITH_MUL_HELPER
8815 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8816 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8817 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8818 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8819 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8820 #endif
8821
8822 #undef GEN_INT_ARITH_SUBF
8823 #undef GEN_INT_ARITH_SUBF_CONST
8824 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8825 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8826 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8827 add_ca, compute_ca, compute_ov) \
8828 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8829 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8830 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8831 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8832 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8833 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8834 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8835 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8836 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8837 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8838 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8839
8840 #undef GEN_LOGICAL1
8841 #undef GEN_LOGICAL2
8842 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8843 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8844 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8845 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8846 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8847 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8848 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8849 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8850 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8851 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8852 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8853 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8854 #if defined(TARGET_PPC64)
8855 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8856 #endif
8857
8858 #if defined(TARGET_PPC64)
8859 #undef GEN_PPC64_R2
8860 #undef GEN_PPC64_R4
8861 #define GEN_PPC64_R2(name, opc1, opc2) \
8862 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8863 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8864 PPC_64B)
8865 #define GEN_PPC64_R4(name, opc1, opc2) \
8866 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8867 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8868 PPC_64B), \
8869 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8870 PPC_64B), \
8871 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8872 PPC_64B)
8873 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8874 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8875 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8876 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8877 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8878 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8879 #endif
8880
8881 #undef _GEN_FLOAT_ACB
8882 #undef GEN_FLOAT_ACB
8883 #undef _GEN_FLOAT_AB
8884 #undef GEN_FLOAT_AB
8885 #undef _GEN_FLOAT_AC
8886 #undef GEN_FLOAT_AC
8887 #undef GEN_FLOAT_B
8888 #undef GEN_FLOAT_BS
8889 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8890 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8891 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8892 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8893 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8894 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8895 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8896 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8897 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8898 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8899 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8900 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8901 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8902 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8903 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8904 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8905 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8906 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8907 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8908
8909 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8910 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8911 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8912 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8913 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8914 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8915 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8916 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8917 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8918 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8919 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8920 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8921 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8922 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8923 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8924 #if defined(TARGET_PPC64)
8925 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8926 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8927 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8928 #endif
8929 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8930 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8931 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8932 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8933 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8934 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8935 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8936
8937 #undef GEN_LD
8938 #undef GEN_LDU
8939 #undef GEN_LDUX
8940 #undef GEN_LDX_E
8941 #undef GEN_LDS
8942 #define GEN_LD(name, ldop, opc, type) \
8943 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8944 #define GEN_LDU(name, ldop, opc, type) \
8945 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8946 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8947 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8948 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8949 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8950 #define GEN_LDS(name, ldop, op, type) \
8951 GEN_LD(name, ldop, op | 0x20, type) \
8952 GEN_LDU(name, ldop, op | 0x21, type) \
8953 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8954 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8955
8956 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8957 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8958 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8959 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8960 #if defined(TARGET_PPC64)
8961 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8962 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8963 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8964 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8965 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8966 #endif
8967 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8968 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8969
8970 #undef GEN_ST
8971 #undef GEN_STU
8972 #undef GEN_STUX
8973 #undef GEN_STX_E
8974 #undef GEN_STS
8975 #define GEN_ST(name, stop, opc, type) \
8976 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8977 #define GEN_STU(name, stop, opc, type) \
8978 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8979 #define GEN_STUX(name, stop, opc2, opc3, type) \
8980 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8981 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8982 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8983 #define GEN_STS(name, stop, op, type) \
8984 GEN_ST(name, stop, op | 0x20, type) \
8985 GEN_STU(name, stop, op | 0x21, type) \
8986 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8987 GEN_STX(name, stop, 0x17, op | 0x00, type)
8988
8989 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8990 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8991 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8992 #if defined(TARGET_PPC64)
8993 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8994 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8995 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8996 #endif
8997 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8998 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8999
9000 #undef GEN_LDF
9001 #undef GEN_LDUF
9002 #undef GEN_LDUXF
9003 #undef GEN_LDXF
9004 #undef GEN_LDFS
9005 #define GEN_LDF(name, ldop, opc, type) \
9006 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9007 #define GEN_LDUF(name, ldop, opc, type) \
9008 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9009 #define GEN_LDUXF(name, ldop, opc, type) \
9010 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9011 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9012 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9013 #define GEN_LDFS(name, ldop, op, type) \
9014 GEN_LDF(name, ldop, op | 0x20, type) \
9015 GEN_LDUF(name, ldop, op | 0x21, type) \
9016 GEN_LDUXF(name, ldop, op | 0x01, type) \
9017 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9018
9019 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
9020 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
9021
9022 #undef GEN_STF
9023 #undef GEN_STUF
9024 #undef GEN_STUXF
9025 #undef GEN_STXF
9026 #undef GEN_STFS
9027 #define GEN_STF(name, stop, opc, type) \
9028 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9029 #define GEN_STUF(name, stop, opc, type) \
9030 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9031 #define GEN_STUXF(name, stop, opc, type) \
9032 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9033 #define GEN_STXF(name, stop, opc2, opc3, type) \
9034 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9035 #define GEN_STFS(name, stop, op, type) \
9036 GEN_STF(name, stop, op | 0x20, type) \
9037 GEN_STUF(name, stop, op | 0x21, type) \
9038 GEN_STUXF(name, stop, op | 0x01, type) \
9039 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9040
9041 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
9042 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
9043 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
9044
9045 #undef GEN_CRLOGIC
9046 #define GEN_CRLOGIC(name, tcg_op, opc) \
9047 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9048 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
9049 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
9050 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
9051 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9052 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9053 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9054 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9055 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9056
9057 #undef GEN_MAC_HANDLER
9058 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9059 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9060 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9061 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9062 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9063 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9064 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9065 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9066 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9067 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9068 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9069 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9070 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9071 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9072 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9073 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9074 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9075 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9076 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9077 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9078 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9079 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9080 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9081 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9082 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9083 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9084 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9085 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9086 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9087 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9088 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9089 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9090 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9091 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9092 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9093 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9094 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9095 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9096 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9097 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9098 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9099 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9100 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9101 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9102
9103 #undef GEN_VR_LDX
9104 #undef GEN_VR_STX
9105 #undef GEN_VR_LVE
9106 #undef GEN_VR_STVE
9107 #define GEN_VR_LDX(name, opc2, opc3) \
9108 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9109 #define GEN_VR_STX(name, opc2, opc3) \
9110 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9111 #define GEN_VR_LVE(name, opc2, opc3) \
9112 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9113 #define GEN_VR_STVE(name, opc2, opc3) \
9114 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9115 GEN_VR_LDX(lvx, 0x07, 0x03),
9116 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9117 GEN_VR_LVE(bx, 0x07, 0x00),
9118 GEN_VR_LVE(hx, 0x07, 0x01),
9119 GEN_VR_LVE(wx, 0x07, 0x02),
9120 GEN_VR_STX(svx, 0x07, 0x07),
9121 GEN_VR_STX(svxl, 0x07, 0x0F),
9122 GEN_VR_STVE(bx, 0x07, 0x04),
9123 GEN_VR_STVE(hx, 0x07, 0x05),
9124 GEN_VR_STVE(wx, 0x07, 0x06),
9125
9126 #undef GEN_VX_LOGICAL
9127 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9128 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9129 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9130 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9131 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9132 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9133 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9134
9135 #undef GEN_VXFORM
9136 #define GEN_VXFORM(name, opc2, opc3) \
9137 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9138 GEN_VXFORM(vaddubm, 0, 0),
9139 GEN_VXFORM(vadduhm, 0, 1),
9140 GEN_VXFORM(vadduwm, 0, 2),
9141 GEN_VXFORM(vsububm, 0, 16),
9142 GEN_VXFORM(vsubuhm, 0, 17),
9143 GEN_VXFORM(vsubuwm, 0, 18),
9144 GEN_VXFORM(vmaxub, 1, 0),
9145 GEN_VXFORM(vmaxuh, 1, 1),
9146 GEN_VXFORM(vmaxuw, 1, 2),
9147 GEN_VXFORM(vmaxsb, 1, 4),
9148 GEN_VXFORM(vmaxsh, 1, 5),
9149 GEN_VXFORM(vmaxsw, 1, 6),
9150 GEN_VXFORM(vminub, 1, 8),
9151 GEN_VXFORM(vminuh, 1, 9),
9152 GEN_VXFORM(vminuw, 1, 10),
9153 GEN_VXFORM(vminsb, 1, 12),
9154 GEN_VXFORM(vminsh, 1, 13),
9155 GEN_VXFORM(vminsw, 1, 14),
9156 GEN_VXFORM(vavgub, 1, 16),
9157 GEN_VXFORM(vavguh, 1, 17),
9158 GEN_VXFORM(vavguw, 1, 18),
9159 GEN_VXFORM(vavgsb, 1, 20),
9160 GEN_VXFORM(vavgsh, 1, 21),
9161 GEN_VXFORM(vavgsw, 1, 22),
9162 GEN_VXFORM(vmrghb, 6, 0),
9163 GEN_VXFORM(vmrghh, 6, 1),
9164 GEN_VXFORM(vmrghw, 6, 2),
9165 GEN_VXFORM(vmrglb, 6, 4),
9166 GEN_VXFORM(vmrglh, 6, 5),
9167 GEN_VXFORM(vmrglw, 6, 6),
9168 GEN_VXFORM(vmuloub, 4, 0),
9169 GEN_VXFORM(vmulouh, 4, 1),
9170 GEN_VXFORM(vmulosb, 4, 4),
9171 GEN_VXFORM(vmulosh, 4, 5),
9172 GEN_VXFORM(vmuleub, 4, 8),
9173 GEN_VXFORM(vmuleuh, 4, 9),
9174 GEN_VXFORM(vmulesb, 4, 12),
9175 GEN_VXFORM(vmulesh, 4, 13),
9176 GEN_VXFORM(vslb, 2, 4),
9177 GEN_VXFORM(vslh, 2, 5),
9178 GEN_VXFORM(vslw, 2, 6),
9179 GEN_VXFORM(vsrb, 2, 8),
9180 GEN_VXFORM(vsrh, 2, 9),
9181 GEN_VXFORM(vsrw, 2, 10),
9182 GEN_VXFORM(vsrab, 2, 12),
9183 GEN_VXFORM(vsrah, 2, 13),
9184 GEN_VXFORM(vsraw, 2, 14),
9185 GEN_VXFORM(vslo, 6, 16),
9186 GEN_VXFORM(vsro, 6, 17),
9187 GEN_VXFORM(vaddcuw, 0, 6),
9188 GEN_VXFORM(vsubcuw, 0, 22),
9189 GEN_VXFORM(vaddubs, 0, 8),
9190 GEN_VXFORM(vadduhs, 0, 9),
9191 GEN_VXFORM(vadduws, 0, 10),
9192 GEN_VXFORM(vaddsbs, 0, 12),
9193 GEN_VXFORM(vaddshs, 0, 13),
9194 GEN_VXFORM(vaddsws, 0, 14),
9195 GEN_VXFORM(vsububs, 0, 24),
9196 GEN_VXFORM(vsubuhs, 0, 25),
9197 GEN_VXFORM(vsubuws, 0, 26),
9198 GEN_VXFORM(vsubsbs, 0, 28),
9199 GEN_VXFORM(vsubshs, 0, 29),
9200 GEN_VXFORM(vsubsws, 0, 30),
9201 GEN_VXFORM(vrlb, 2, 0),
9202 GEN_VXFORM(vrlh, 2, 1),
9203 GEN_VXFORM(vrlw, 2, 2),
9204 GEN_VXFORM(vsl, 2, 7),
9205 GEN_VXFORM(vsr, 2, 11),
9206 GEN_VXFORM(vpkuhum, 7, 0),
9207 GEN_VXFORM(vpkuwum, 7, 1),
9208 GEN_VXFORM(vpkuhus, 7, 2),
9209 GEN_VXFORM(vpkuwus, 7, 3),
9210 GEN_VXFORM(vpkshus, 7, 4),
9211 GEN_VXFORM(vpkswus, 7, 5),
9212 GEN_VXFORM(vpkshss, 7, 6),
9213 GEN_VXFORM(vpkswss, 7, 7),
9214 GEN_VXFORM(vpkpx, 7, 12),
9215 GEN_VXFORM(vsum4ubs, 4, 24),
9216 GEN_VXFORM(vsum4sbs, 4, 28),
9217 GEN_VXFORM(vsum4shs, 4, 25),
9218 GEN_VXFORM(vsum2sws, 4, 26),
9219 GEN_VXFORM(vsumsws, 4, 30),
9220 GEN_VXFORM(vaddfp, 5, 0),
9221 GEN_VXFORM(vsubfp, 5, 1),
9222 GEN_VXFORM(vmaxfp, 5, 16),
9223 GEN_VXFORM(vminfp, 5, 17),
9224
9225 #undef GEN_VXRFORM1
9226 #undef GEN_VXRFORM
9227 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9228 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9229 #define GEN_VXRFORM(name, opc2, opc3) \
9230 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9231 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9232 GEN_VXRFORM(vcmpequb, 3, 0)
9233 GEN_VXRFORM(vcmpequh, 3, 1)
9234 GEN_VXRFORM(vcmpequw, 3, 2)
9235 GEN_VXRFORM(vcmpgtsb, 3, 12)
9236 GEN_VXRFORM(vcmpgtsh, 3, 13)
9237 GEN_VXRFORM(vcmpgtsw, 3, 14)
9238 GEN_VXRFORM(vcmpgtub, 3, 8)
9239 GEN_VXRFORM(vcmpgtuh, 3, 9)
9240 GEN_VXRFORM(vcmpgtuw, 3, 10)
9241 GEN_VXRFORM(vcmpeqfp, 3, 3)
9242 GEN_VXRFORM(vcmpgefp, 3, 7)
9243 GEN_VXRFORM(vcmpgtfp, 3, 11)
9244 GEN_VXRFORM(vcmpbfp, 3, 15)
9245
9246 #undef GEN_VXFORM_SIMM
9247 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9248 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9249 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9250 GEN_VXFORM_SIMM(vspltish, 6, 13),
9251 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9252
9253 #undef GEN_VXFORM_NOA
9254 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9255 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9256 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9257 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9258 GEN_VXFORM_NOA(vupklsb, 7, 10),
9259 GEN_VXFORM_NOA(vupklsh, 7, 11),
9260 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9261 GEN_VXFORM_NOA(vupklpx, 7, 15),
9262 GEN_VXFORM_NOA(vrefp, 5, 4),
9263 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9264 GEN_VXFORM_NOA(vexptefp, 5, 6),
9265 GEN_VXFORM_NOA(vlogefp, 5, 7),
9266 GEN_VXFORM_NOA(vrfim, 5, 8),
9267 GEN_VXFORM_NOA(vrfin, 5, 9),
9268 GEN_VXFORM_NOA(vrfip, 5, 10),
9269 GEN_VXFORM_NOA(vrfiz, 5, 11),
9270
9271 #undef GEN_VXFORM_UIMM
9272 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9273 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9274 GEN_VXFORM_UIMM(vspltb, 6, 8),
9275 GEN_VXFORM_UIMM(vsplth, 6, 9),
9276 GEN_VXFORM_UIMM(vspltw, 6, 10),
9277 GEN_VXFORM_UIMM(vcfux, 5, 12),
9278 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9279 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9280 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9281
9282 #undef GEN_VAFORM_PAIRED
9283 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9284 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9285 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9286 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9287 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9288 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9289 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9290 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9291
9292 #undef GEN_SPE
9293 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9294 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9295 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9296 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9297 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9298 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9299 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9300 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9301 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9302 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9303 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9304 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9305 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9306 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9307 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9308 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9309 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9310 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9311 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9312 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9313 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9314 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9315 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9316 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9317 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9318 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9319 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9320 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9321 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9322 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9323 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9324
9325 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9326 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9327 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9328 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9329 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9330 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9331 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9332 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9333 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9334 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9335 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9336 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9337 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9338 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9339
9340 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9341 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9342 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9343 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9344 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9345 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9346 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9347 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9348 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9349 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9350 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9351 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9352 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9353 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9354
9355 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9356 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9357 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9358 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9359 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9360 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9361 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9362 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9363 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9364 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9365 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9366 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9367 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9368 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9369 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9370 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9371
9372 #undef GEN_SPEOP_LDST
9373 #define GEN_SPEOP_LDST(name, opc2, sh) \
9374 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9375 GEN_SPEOP_LDST(evldd, 0x00, 3),
9376 GEN_SPEOP_LDST(evldw, 0x01, 3),
9377 GEN_SPEOP_LDST(evldh, 0x02, 3),
9378 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9379 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9380 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9381 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9382 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9383 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9384 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9385 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9386
9387 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9388 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9389 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9390 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9391 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9392 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9393 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9394 };
9395
9396 #include "helper_regs.h"
9397 #include "translate_init.c"
9398
9399 /*****************************************************************************/
9400 /* Misc PowerPC helpers */
9401 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9402 int flags)
9403 {
9404 #define RGPL 4
9405 #define RFPL 4
9406
9407 int i;
9408
9409 cpu_synchronize_state(env);
9410
9411 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9412 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9413 env->nip, env->lr, env->ctr, env->xer);
9414 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9415 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9416 env->hflags, env->mmu_idx);
9417 #if !defined(NO_TIMER_DUMP)
9418 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9419 #if !defined(CONFIG_USER_ONLY)
9420 " DECR %08" PRIu32
9421 #endif
9422 "\n",
9423 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9424 #if !defined(CONFIG_USER_ONLY)
9425 , cpu_ppc_load_decr(env)
9426 #endif
9427 );
9428 #endif
9429 for (i = 0; i < 32; i++) {
9430 if ((i & (RGPL - 1)) == 0)
9431 cpu_fprintf(f, "GPR%02d", i);
9432 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9433 if ((i & (RGPL - 1)) == (RGPL - 1))
9434 cpu_fprintf(f, "\n");
9435 }
9436 cpu_fprintf(f, "CR ");
9437 for (i = 0; i < 8; i++)
9438 cpu_fprintf(f, "%01x", env->crf[i]);
9439 cpu_fprintf(f, " [");
9440 for (i = 0; i < 8; i++) {
9441 char a = '-';
9442 if (env->crf[i] & 0x08)
9443 a = 'L';
9444 else if (env->crf[i] & 0x04)
9445 a = 'G';
9446 else if (env->crf[i] & 0x02)
9447 a = 'E';
9448 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9449 }
9450 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9451 env->reserve_addr);
9452 for (i = 0; i < 32; i++) {
9453 if ((i & (RFPL - 1)) == 0)
9454 cpu_fprintf(f, "FPR%02d", i);
9455 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9456 if ((i & (RFPL - 1)) == (RFPL - 1))
9457 cpu_fprintf(f, "\n");
9458 }
9459 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9460 #if !defined(CONFIG_USER_ONLY)
9461 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9462 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9463 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9464 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9465
9466 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9467 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9468 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9469 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9470
9471 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9472 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9473 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9474 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9475
9476 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9477 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9478 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9479 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9480 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9481
9482 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9483 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9484 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9485 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9486
9487 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9488 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9489 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9490 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9491
9492 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9493 " EPR " TARGET_FMT_lx "\n",
9494 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9495 env->spr[SPR_BOOKE_EPR]);
9496
9497 /* FSL-specific */
9498 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9499 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9500 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9501 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9502
9503 /*
9504 * IVORs are left out as they are large and do not change often --
9505 * they can be read with "p $ivor0", "p $ivor1", etc.
9506 */
9507 }
9508
9509 #if defined(TARGET_PPC64)
9510 if (env->flags & POWERPC_FLAG_CFAR) {
9511 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9512 }
9513 #endif
9514
9515 switch (env->mmu_model) {
9516 case POWERPC_MMU_32B:
9517 case POWERPC_MMU_601:
9518 case POWERPC_MMU_SOFT_6xx:
9519 case POWERPC_MMU_SOFT_74xx:
9520 #if defined(TARGET_PPC64)
9521 case POWERPC_MMU_620:
9522 case POWERPC_MMU_64B:
9523 #endif
9524 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9525 break;
9526 case POWERPC_MMU_BOOKE206:
9527 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9528 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9529 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9530 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9531
9532 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9533 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9534 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9535 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9536
9537 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9538 " TLB1CFG " TARGET_FMT_lx "\n",
9539 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9540 env->spr[SPR_BOOKE_TLB1CFG]);
9541 break;
9542 default:
9543 break;
9544 }
9545 #endif
9546
9547 #undef RGPL
9548 #undef RFPL
9549 }
9550
9551 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9552 int flags)
9553 {
9554 #if defined(DO_PPC_STATISTICS)
9555 opc_handler_t **t1, **t2, **t3, *handler;
9556 int op1, op2, op3;
9557
9558 t1 = env->opcodes;
9559 for (op1 = 0; op1 < 64; op1++) {
9560 handler = t1[op1];
9561 if (is_indirect_opcode(handler)) {
9562 t2 = ind_table(handler);
9563 for (op2 = 0; op2 < 32; op2++) {
9564 handler = t2[op2];
9565 if (is_indirect_opcode(handler)) {
9566 t3 = ind_table(handler);
9567 for (op3 = 0; op3 < 32; op3++) {
9568 handler = t3[op3];
9569 if (handler->count == 0)
9570 continue;
9571 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9572 "%016" PRIx64 " %" PRId64 "\n",
9573 op1, op2, op3, op1, (op3 << 5) | op2,
9574 handler->oname,
9575 handler->count, handler->count);
9576 }
9577 } else {
9578 if (handler->count == 0)
9579 continue;
9580 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9581 "%016" PRIx64 " %" PRId64 "\n",
9582 op1, op2, op1, op2, handler->oname,
9583 handler->count, handler->count);
9584 }
9585 }
9586 } else {
9587 if (handler->count == 0)
9588 continue;
9589 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9590 " %" PRId64 "\n",
9591 op1, op1, handler->oname,
9592 handler->count, handler->count);
9593 }
9594 }
9595 #endif
9596 }
9597
9598 /*****************************************************************************/
9599 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9600 TranslationBlock *tb,
9601 int search_pc)
9602 {
9603 DisasContext ctx, *ctxp = &ctx;
9604 opc_handler_t **table, *handler;
9605 target_ulong pc_start;
9606 uint16_t *gen_opc_end;
9607 CPUBreakpoint *bp;
9608 int j, lj = -1;
9609 int num_insns;
9610 int max_insns;
9611
9612 pc_start = tb->pc;
9613 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9614 ctx.nip = pc_start;
9615 ctx.tb = tb;
9616 ctx.exception = POWERPC_EXCP_NONE;
9617 ctx.spr_cb = env->spr_cb;
9618 ctx.mem_idx = env->mmu_idx;
9619 ctx.access_type = -1;
9620 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9621 #if defined(TARGET_PPC64)
9622 ctx.sf_mode = msr_is_64bit(env, env->msr);
9623 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9624 #endif
9625 ctx.fpu_enabled = msr_fp;
9626 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9627 ctx.spe_enabled = msr_spe;
9628 else
9629 ctx.spe_enabled = 0;
9630 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9631 ctx.altivec_enabled = msr_vr;
9632 else
9633 ctx.altivec_enabled = 0;
9634 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9635 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9636 else
9637 ctx.singlestep_enabled = 0;
9638 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9639 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9640 if (unlikely(env->singlestep_enabled))
9641 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9642 #if defined (DO_SINGLE_STEP) && 0
9643 /* Single step trace mode */
9644 msr_se = 1;
9645 #endif
9646 num_insns = 0;
9647 max_insns = tb->cflags & CF_COUNT_MASK;
9648 if (max_insns == 0)
9649 max_insns = CF_COUNT_MASK;
9650
9651 gen_icount_start();
9652 /* Set env in case of segfault during code fetch */
9653 while (ctx.exception == POWERPC_EXCP_NONE
9654 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9655 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9656 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9657 if (bp->pc == ctx.nip) {
9658 gen_debug_exception(ctxp);
9659 break;
9660 }
9661 }
9662 }
9663 if (unlikely(search_pc)) {
9664 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9665 if (lj < j) {
9666 lj++;
9667 while (lj < j)
9668 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9669 }
9670 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9671 tcg_ctx.gen_opc_instr_start[lj] = 1;
9672 tcg_ctx.gen_opc_icount[lj] = num_insns;
9673 }
9674 LOG_DISAS("----------------\n");
9675 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9676 ctx.nip, ctx.mem_idx, (int)msr_ir);
9677 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9678 gen_io_start();
9679 if (unlikely(ctx.le_mode)) {
9680 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9681 } else {
9682 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9683 }
9684 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9685 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9686 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9687 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9688 tcg_gen_debug_insn_start(ctx.nip);
9689 }
9690 ctx.nip += 4;
9691 table = env->opcodes;
9692 num_insns++;
9693 handler = table[opc1(ctx.opcode)];
9694 if (is_indirect_opcode(handler)) {
9695 table = ind_table(handler);
9696 handler = table[opc2(ctx.opcode)];
9697 if (is_indirect_opcode(handler)) {
9698 table = ind_table(handler);
9699 handler = table[opc3(ctx.opcode)];
9700 }
9701 }
9702 /* Is opcode *REALLY* valid ? */
9703 if (unlikely(handler->handler == &gen_invalid)) {
9704 if (qemu_log_enabled()) {
9705 qemu_log("invalid/unsupported opcode: "
9706 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9707 opc1(ctx.opcode), opc2(ctx.opcode),
9708 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9709 }
9710 } else {
9711 uint32_t inval;
9712
9713 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9714 inval = handler->inval2;
9715 } else {
9716 inval = handler->inval1;
9717 }
9718
9719 if (unlikely((ctx.opcode & inval) != 0)) {
9720 if (qemu_log_enabled()) {
9721 qemu_log("invalid bits: %08x for opcode: "
9722 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9723 ctx.opcode & inval, opc1(ctx.opcode),
9724 opc2(ctx.opcode), opc3(ctx.opcode),
9725 ctx.opcode, ctx.nip - 4);
9726 }
9727 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9728 break;
9729 }
9730 }
9731 (*(handler->handler))(&ctx);
9732 #if defined(DO_PPC_STATISTICS)
9733 handler->count++;
9734 #endif
9735 /* Check trace mode exceptions */
9736 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9737 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9738 ctx.exception != POWERPC_SYSCALL &&
9739 ctx.exception != POWERPC_EXCP_TRAP &&
9740 ctx.exception != POWERPC_EXCP_BRANCH)) {
9741 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9742 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9743 (env->singlestep_enabled) ||
9744 singlestep ||
9745 num_insns >= max_insns)) {
9746 /* if we reach a page boundary or are single stepping, stop
9747 * generation
9748 */
9749 break;
9750 }
9751 }
9752 if (tb->cflags & CF_LAST_IO)
9753 gen_io_end();
9754 if (ctx.exception == POWERPC_EXCP_NONE) {
9755 gen_goto_tb(&ctx, 0, ctx.nip);
9756 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9757 if (unlikely(env->singlestep_enabled)) {
9758 gen_debug_exception(ctxp);
9759 }
9760 /* Generate the return instruction */
9761 tcg_gen_exit_tb(0);
9762 }
9763 gen_icount_end(tb, num_insns);
9764 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9765 if (unlikely(search_pc)) {
9766 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9767 lj++;
9768 while (lj <= j)
9769 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9770 } else {
9771 tb->size = ctx.nip - pc_start;
9772 tb->icount = num_insns;
9773 }
9774 #if defined(DEBUG_DISAS)
9775 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9776 int flags;
9777 flags = env->bfd_mach;
9778 flags |= ctx.le_mode << 16;
9779 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9780 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9781 qemu_log("\n");
9782 }
9783 #endif
9784 }
9785
9786 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9787 {
9788 gen_intermediate_code_internal(env, tb, 0);
9789 }
9790
9791 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9792 {
9793 gen_intermediate_code_internal(env, tb, 1);
9794 }
9795
9796 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9797 {
9798 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9799 }
Qemu copy for testing