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target-ppc: Use setcond in gen_op_cmp
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 struct opc_handler_t {
208 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
209 uint32_t inval1;
210 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
211 uint32_t inval2;
212 /* instruction type */
213 uint64_t type;
214 /* extended instruction type */
215 uint64_t type2;
216 /* handler */
217 void (*handler)(DisasContext *ctx);
218 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
219 const char *oname;
220 #endif
221 #if defined(DO_PPC_STATISTICS)
222 uint64_t count;
223 #endif
224 };
225
226 static inline void gen_reset_fpstatus(void)
227 {
228 gen_helper_reset_fpstatus(cpu_env);
229 }
230
231 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
232 {
233 TCGv_i32 t0 = tcg_temp_new_i32();
234
235 if (set_fprf != 0) {
236 /* This case might be optimized later */
237 tcg_gen_movi_i32(t0, 1);
238 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
239 if (unlikely(set_rc)) {
240 tcg_gen_mov_i32(cpu_crf[1], t0);
241 }
242 gen_helper_float_check_status(cpu_env);
243 } else if (unlikely(set_rc)) {
244 /* We always need to compute fpcc */
245 tcg_gen_movi_i32(t0, 0);
246 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249
250 tcg_temp_free_i32(t0);
251 }
252
253 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
254 {
255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
259 }
260
261 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
262 {
263 #if defined(TARGET_PPC64)
264 if (ctx->sf_mode)
265 tcg_gen_movi_tl(cpu_nip, nip);
266 else
267 #endif
268 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
269 }
270
271 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
272 {
273 TCGv_i32 t0, t1;
274 if (ctx->exception == POWERPC_EXCP_NONE) {
275 gen_update_nip(ctx, ctx->nip);
276 }
277 t0 = tcg_const_i32(excp);
278 t1 = tcg_const_i32(error);
279 gen_helper_raise_exception_err(cpu_env, t0, t1);
280 tcg_temp_free_i32(t0);
281 tcg_temp_free_i32(t1);
282 ctx->exception = (excp);
283 }
284
285 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
286 {
287 TCGv_i32 t0;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 gen_helper_raise_exception(cpu_env, t0);
293 tcg_temp_free_i32(t0);
294 ctx->exception = (excp);
295 }
296
297 static inline void gen_debug_exception(DisasContext *ctx)
298 {
299 TCGv_i32 t0;
300
301 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
302 (ctx->exception != POWERPC_EXCP_SYNC)) {
303 gen_update_nip(ctx, ctx->nip);
304 }
305 t0 = tcg_const_i32(EXCP_DEBUG);
306 gen_helper_raise_exception(cpu_env, t0);
307 tcg_temp_free_i32(t0);
308 }
309
310 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
311 {
312 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
313 }
314
315 /* Stop translation */
316 static inline void gen_stop_exception(DisasContext *ctx)
317 {
318 gen_update_nip(ctx, ctx->nip);
319 ctx->exception = POWERPC_EXCP_STOP;
320 }
321
322 /* No need to update nip here, as execution flow will change */
323 static inline void gen_sync_exception(DisasContext *ctx)
324 {
325 ctx->exception = POWERPC_EXCP_SYNC;
326 }
327
328 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
333
334 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
335 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
336
337 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
338 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
339
340 typedef struct opcode_t {
341 unsigned char opc1, opc2, opc3;
342 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
343 unsigned char pad[5];
344 #else
345 unsigned char pad[1];
346 #endif
347 opc_handler_t handler;
348 const char *oname;
349 } opcode_t;
350
351 /*****************************************************************************/
352 /*** Instruction decoding ***/
353 #define EXTRACT_HELPER(name, shift, nb) \
354 static inline uint32_t name(uint32_t opcode) \
355 { \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
357 }
358
359 #define EXTRACT_SHELPER(name, shift, nb) \
360 static inline int32_t name(uint32_t opcode) \
361 { \
362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
363 }
364
365 /* Opcode part 1 */
366 EXTRACT_HELPER(opc1, 26, 6);
367 /* Opcode part 2 */
368 EXTRACT_HELPER(opc2, 1, 5);
369 /* Opcode part 3 */
370 EXTRACT_HELPER(opc3, 6, 5);
371 /* Update Cr0 flags */
372 EXTRACT_HELPER(Rc, 0, 1);
373 /* Destination */
374 EXTRACT_HELPER(rD, 21, 5);
375 /* Source */
376 EXTRACT_HELPER(rS, 21, 5);
377 /* First operand */
378 EXTRACT_HELPER(rA, 16, 5);
379 /* Second operand */
380 EXTRACT_HELPER(rB, 11, 5);
381 /* Third operand */
382 EXTRACT_HELPER(rC, 6, 5);
383 /*** Get CRn ***/
384 EXTRACT_HELPER(crfD, 23, 3);
385 EXTRACT_HELPER(crfS, 18, 3);
386 EXTRACT_HELPER(crbD, 21, 5);
387 EXTRACT_HELPER(crbA, 16, 5);
388 EXTRACT_HELPER(crbB, 11, 5);
389 /* SPR / TBL */
390 EXTRACT_HELPER(_SPR, 11, 10);
391 static inline uint32_t SPR(uint32_t opcode)
392 {
393 uint32_t sprn = _SPR(opcode);
394
395 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
396 }
397 /*** Get constants ***/
398 EXTRACT_HELPER(IMM, 12, 8);
399 /* 16 bits signed immediate value */
400 EXTRACT_SHELPER(SIMM, 0, 16);
401 /* 16 bits unsigned immediate value */
402 EXTRACT_HELPER(UIMM, 0, 16);
403 /* 5 bits signed immediate value */
404 EXTRACT_HELPER(SIMM5, 16, 5);
405 /* 5 bits signed immediate value */
406 EXTRACT_HELPER(UIMM5, 16, 5);
407 /* Bit count */
408 EXTRACT_HELPER(NB, 11, 5);
409 /* Shift count */
410 EXTRACT_HELPER(SH, 11, 5);
411 /* Vector shift count */
412 EXTRACT_HELPER(VSH, 6, 4);
413 /* Mask start */
414 EXTRACT_HELPER(MB, 6, 5);
415 /* Mask end */
416 EXTRACT_HELPER(ME, 1, 5);
417 /* Trap operand */
418 EXTRACT_HELPER(TO, 21, 5);
419
420 EXTRACT_HELPER(CRM, 12, 8);
421 EXTRACT_HELPER(FM, 17, 8);
422 EXTRACT_HELPER(SR, 16, 4);
423 EXTRACT_HELPER(FPIMM, 12, 4);
424
425 /*** Jump target decoding ***/
426 /* Displacement */
427 EXTRACT_SHELPER(d, 0, 16);
428 /* Immediate address */
429 static inline target_ulong LI(uint32_t opcode)
430 {
431 return (opcode >> 0) & 0x03FFFFFC;
432 }
433
434 static inline uint32_t BD(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0xFFFC;
437 }
438
439 EXTRACT_HELPER(BO, 21, 5);
440 EXTRACT_HELPER(BI, 16, 5);
441 /* Absolute/relative address */
442 EXTRACT_HELPER(AA, 1, 1);
443 /* Link */
444 EXTRACT_HELPER(LK, 0, 1);
445
446 /* Create a mask between <start> and <end> bits */
447 static inline target_ulong MASK(uint32_t start, uint32_t end)
448 {
449 target_ulong ret;
450
451 #if defined(TARGET_PPC64)
452 if (likely(start == 0)) {
453 ret = UINT64_MAX << (63 - end);
454 } else if (likely(end == 63)) {
455 ret = UINT64_MAX >> start;
456 }
457 #else
458 if (likely(start == 0)) {
459 ret = UINT32_MAX << (31 - end);
460 } else if (likely(end == 31)) {
461 ret = UINT32_MAX >> start;
462 }
463 #endif
464 else {
465 ret = (((target_ulong)(-1ULL)) >> (start)) ^
466 (((target_ulong)(-1ULL) >> (end)) >> 1);
467 if (unlikely(start > end))
468 return ~ret;
469 }
470
471 return ret;
472 }
473
474 /*****************************************************************************/
475 /* PowerPC instructions table */
476
477 #if defined(DO_PPC_STATISTICS)
478 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
479 { \
480 .opc1 = op1, \
481 .opc2 = op2, \
482 .opc3 = op3, \
483 .pad = { 0, }, \
484 .handler = { \
485 .inval1 = invl, \
486 .type = _typ, \
487 .type2 = _typ2, \
488 .handler = &gen_##name, \
489 .oname = stringify(name), \
490 }, \
491 .oname = stringify(name), \
492 }
493 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
494 { \
495 .opc1 = op1, \
496 .opc2 = op2, \
497 .opc3 = op3, \
498 .pad = { 0, }, \
499 .handler = { \
500 .inval1 = invl1, \
501 .inval2 = invl2, \
502 .type = _typ, \
503 .type2 = _typ2, \
504 .handler = &gen_##name, \
505 .oname = stringify(name), \
506 }, \
507 .oname = stringify(name), \
508 }
509 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
510 { \
511 .opc1 = op1, \
512 .opc2 = op2, \
513 .opc3 = op3, \
514 .pad = { 0, }, \
515 .handler = { \
516 .inval1 = invl, \
517 .type = _typ, \
518 .type2 = _typ2, \
519 .handler = &gen_##name, \
520 .oname = onam, \
521 }, \
522 .oname = onam, \
523 }
524 #else
525 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
526 { \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl, \
533 .type = _typ, \
534 .type2 = _typ2, \
535 .handler = &gen_##name, \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
548 .type = _typ, \
549 .type2 = _typ2, \
550 .handler = &gen_##name, \
551 }, \
552 .oname = stringify(name), \
553 }
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555 { \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 }, \
566 .oname = onam, \
567 }
568 #endif
569
570 /* SPR load/store helpers */
571 static inline void gen_load_spr(TCGv t, int reg)
572 {
573 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
574 }
575
576 static inline void gen_store_spr(int reg, TCGv t)
577 {
578 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 /* Invalid instruction */
582 static void gen_invalid(DisasContext *ctx)
583 {
584 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
585 }
586
587 static opc_handler_t invalid_handler = {
588 .inval1 = 0xFFFFFFFF,
589 .inval2 = 0xFFFFFFFF,
590 .type = PPC_NONE,
591 .type2 = PPC_NONE,
592 .handler = gen_invalid,
593 };
594
595 /*** Integer comparison ***/
596
597 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
598 {
599 TCGv t0 = tcg_temp_new();
600 TCGv_i32 t1 = tcg_temp_new_i32();
601
602 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
603
604 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
605 tcg_gen_trunc_tl_i32(t1, t0);
606 tcg_gen_shli_i32(t1, t1, CRF_LT);
607 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_GT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_EQ);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_temp_free(t0);
620 tcg_temp_free_i32(t1);
621 }
622
623 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
624 {
625 TCGv t0 = tcg_const_tl(arg1);
626 gen_op_cmp(arg0, t0, s, crf);
627 tcg_temp_free(t0);
628 }
629
630 #if defined(TARGET_PPC64)
631 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
632 {
633 TCGv t0, t1;
634 t0 = tcg_temp_new();
635 t1 = tcg_temp_new();
636 if (s) {
637 tcg_gen_ext32s_tl(t0, arg0);
638 tcg_gen_ext32s_tl(t1, arg1);
639 } else {
640 tcg_gen_ext32u_tl(t0, arg0);
641 tcg_gen_ext32u_tl(t1, arg1);
642 }
643 gen_op_cmp(t0, t1, s, crf);
644 tcg_temp_free(t1);
645 tcg_temp_free(t0);
646 }
647
648 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
649 {
650 TCGv t0 = tcg_const_tl(arg1);
651 gen_op_cmp32(arg0, t0, s, crf);
652 tcg_temp_free(t0);
653 }
654 #endif
655
656 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
657 {
658 #if defined(TARGET_PPC64)
659 if (!(ctx->sf_mode))
660 gen_op_cmpi32(reg, 0, 1, 0);
661 else
662 #endif
663 gen_op_cmpi(reg, 0, 1, 0);
664 }
665
666 /* cmp */
667 static void gen_cmp(DisasContext *ctx)
668 {
669 #if defined(TARGET_PPC64)
670 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
671 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 else
674 #endif
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678
679 /* cmpi */
680 static void gen_cmpi(DisasContext *ctx)
681 {
682 #if defined(TARGET_PPC64)
683 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 else
687 #endif
688 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
689 1, crfD(ctx->opcode));
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 #if defined(TARGET_PPC64)
696 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 else
700 #endif
701 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
702 0, crfD(ctx->opcode));
703 }
704
705 /* cmpli */
706 static void gen_cmpli(DisasContext *ctx)
707 {
708 #if defined(TARGET_PPC64)
709 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
710 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712 else
713 #endif
714 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
715 0, crfD(ctx->opcode));
716 }
717
718 /* isel (PowerPC 2.03 specification) */
719 static void gen_isel(DisasContext *ctx)
720 {
721 int l1, l2;
722 uint32_t bi = rC(ctx->opcode);
723 uint32_t mask;
724 TCGv_i32 t0;
725
726 l1 = gen_new_label();
727 l2 = gen_new_label();
728
729 mask = 1 << (3 - (bi & 0x03));
730 t0 = tcg_temp_new_i32();
731 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
732 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
733 if (rA(ctx->opcode) == 0)
734 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
735 else
736 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
737 tcg_gen_br(l2);
738 gen_set_label(l1);
739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
740 gen_set_label(l2);
741 tcg_temp_free_i32(t0);
742 }
743
744 /*** Integer arithmetic ***/
745
746 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
747 TCGv arg1, TCGv arg2, int sub)
748 {
749 int l1;
750 TCGv t0;
751
752 l1 = gen_new_label();
753 /* Start with XER OV disabled, the most likely case */
754 tcg_gen_movi_tl(cpu_ov, 0);
755 t0 = tcg_temp_local_new();
756 tcg_gen_xor_tl(t0, arg0, arg1);
757 #if defined(TARGET_PPC64)
758 if (!ctx->sf_mode)
759 tcg_gen_ext32s_tl(t0, t0);
760 #endif
761 if (sub)
762 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
763 else
764 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
765 tcg_gen_xor_tl(t0, arg1, arg2);
766 #if defined(TARGET_PPC64)
767 if (!ctx->sf_mode)
768 tcg_gen_ext32s_tl(t0, t0);
769 #endif
770 if (sub)
771 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
772 else
773 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
774 tcg_gen_movi_tl(cpu_ov, 1);
775 tcg_gen_movi_tl(cpu_so, 1);
776 gen_set_label(l1);
777 tcg_temp_free(t0);
778 }
779
780 static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
781 TCGv arg2, int sub)
782 {
783 int l1 = gen_new_label();
784
785 #if defined(TARGET_PPC64)
786 if (!(ctx->sf_mode)) {
787 TCGv t0, t1;
788 t0 = tcg_temp_new();
789 t1 = tcg_temp_new();
790
791 tcg_gen_ext32u_tl(t0, arg1);
792 tcg_gen_ext32u_tl(t1, arg2);
793 if (sub) {
794 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
795 } else {
796 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
797 }
798 tcg_gen_movi_tl(cpu_ca, 1);
799 gen_set_label(l1);
800 tcg_temp_free(t0);
801 tcg_temp_free(t1);
802 } else
803 #endif
804 {
805 if (sub) {
806 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
807 } else {
808 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
809 }
810 tcg_gen_movi_tl(cpu_ca, 1);
811 gen_set_label(l1);
812 }
813 }
814
815 /* Common add function */
816 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
817 TCGv arg2, int add_ca, int compute_ca,
818 int compute_ov)
819 {
820 TCGv t0, t1;
821
822 if ((!compute_ca && !compute_ov) ||
823 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
824 t0 = ret;
825 } else {
826 t0 = tcg_temp_local_new();
827 }
828
829 if (add_ca) {
830 t1 = tcg_temp_local_new();
831 tcg_gen_mov_tl(t1, cpu_ca);
832 } else {
833 TCGV_UNUSED(t1);
834 }
835
836 if (compute_ca) {
837 /* Start with XER CA disabled, the most likely case */
838 tcg_gen_movi_tl(cpu_ca, 0);
839 }
840 if (compute_ov) {
841 /* Start with XER OV disabled, the most likely case */
842 tcg_gen_movi_tl(cpu_ov, 0);
843 }
844
845 tcg_gen_add_tl(t0, arg1, arg2);
846
847 if (compute_ca) {
848 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
849 }
850 if (add_ca) {
851 tcg_gen_add_tl(t0, t0, t1);
852 gen_op_arith_compute_ca(ctx, t0, t1, 0);
853 tcg_temp_free(t1);
854 }
855 if (compute_ov) {
856 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
857 }
858
859 if (unlikely(Rc(ctx->opcode) != 0))
860 gen_set_Rc0(ctx, t0);
861
862 if (!TCGV_EQUAL(t0, ret)) {
863 tcg_gen_mov_tl(ret, t0);
864 tcg_temp_free(t0);
865 }
866 }
867 /* Add functions with two operands */
868 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
869 static void glue(gen_, name)(DisasContext *ctx) \
870 { \
871 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
872 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
873 add_ca, compute_ca, compute_ov); \
874 }
875 /* Add functions with one operand and one immediate */
876 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
877 add_ca, compute_ca, compute_ov) \
878 static void glue(gen_, name)(DisasContext *ctx) \
879 { \
880 TCGv t0 = tcg_const_local_tl(const_val); \
881 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
882 cpu_gpr[rA(ctx->opcode)], t0, \
883 add_ca, compute_ca, compute_ov); \
884 tcg_temp_free(t0); \
885 }
886
887 /* add add. addo addo. */
888 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
889 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
890 /* addc addc. addco addco. */
891 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
892 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
893 /* adde adde. addeo addeo. */
894 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
895 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
896 /* addme addme. addmeo addmeo. */
897 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
898 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
899 /* addze addze. addzeo addzeo.*/
900 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
901 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
902 /* addi */
903 static void gen_addi(DisasContext *ctx)
904 {
905 target_long simm = SIMM(ctx->opcode);
906
907 if (rA(ctx->opcode) == 0) {
908 /* li case */
909 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
910 } else {
911 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
912 }
913 }
914 /* addic addic.*/
915 static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
916 int compute_Rc0)
917 {
918 target_long simm = SIMM(ctx->opcode);
919
920 /* Start with XER CA disabled, the most likely case */
921 tcg_gen_movi_tl(cpu_ca, 0);
922
923 if (likely(simm != 0)) {
924 TCGv t0 = tcg_temp_local_new();
925 tcg_gen_addi_tl(t0, arg1, simm);
926 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
927 tcg_gen_mov_tl(ret, t0);
928 tcg_temp_free(t0);
929 } else {
930 tcg_gen_mov_tl(ret, arg1);
931 }
932 if (compute_Rc0) {
933 gen_set_Rc0(ctx, ret);
934 }
935 }
936
937 static void gen_addic(DisasContext *ctx)
938 {
939 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
940 }
941
942 static void gen_addic_(DisasContext *ctx)
943 {
944 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
945 }
946
947 /* addis */
948 static void gen_addis(DisasContext *ctx)
949 {
950 target_long simm = SIMM(ctx->opcode);
951
952 if (rA(ctx->opcode) == 0) {
953 /* lis case */
954 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
955 } else {
956 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
957 }
958 }
959
960 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
961 TCGv arg2, int sign, int compute_ov)
962 {
963 int l1 = gen_new_label();
964 int l2 = gen_new_label();
965 TCGv_i32 t0 = tcg_temp_local_new_i32();
966 TCGv_i32 t1 = tcg_temp_local_new_i32();
967
968 tcg_gen_trunc_tl_i32(t0, arg1);
969 tcg_gen_trunc_tl_i32(t1, arg2);
970 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
971 if (sign) {
972 int l3 = gen_new_label();
973 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
974 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
975 gen_set_label(l3);
976 tcg_gen_div_i32(t0, t0, t1);
977 } else {
978 tcg_gen_divu_i32(t0, t0, t1);
979 }
980 if (compute_ov) {
981 tcg_gen_movi_tl(cpu_ov, 0);
982 }
983 tcg_gen_br(l2);
984 gen_set_label(l1);
985 if (sign) {
986 tcg_gen_sari_i32(t0, t0, 31);
987 } else {
988 tcg_gen_movi_i32(t0, 0);
989 }
990 if (compute_ov) {
991 tcg_gen_movi_tl(cpu_ov, 1);
992 tcg_gen_movi_tl(cpu_so, 1);
993 }
994 gen_set_label(l2);
995 tcg_gen_extu_i32_tl(ret, t0);
996 tcg_temp_free_i32(t0);
997 tcg_temp_free_i32(t1);
998 if (unlikely(Rc(ctx->opcode) != 0))
999 gen_set_Rc0(ctx, ret);
1000 }
1001 /* Div functions */
1002 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1003 static void glue(gen_, name)(DisasContext *ctx) \
1004 { \
1005 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1006 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1007 sign, compute_ov); \
1008 }
1009 /* divwu divwu. divwuo divwuo. */
1010 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1011 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1012 /* divw divw. divwo divwo. */
1013 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1014 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1015 #if defined(TARGET_PPC64)
1016 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1017 TCGv arg2, int sign, int compute_ov)
1018 {
1019 int l1 = gen_new_label();
1020 int l2 = gen_new_label();
1021
1022 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1023 if (sign) {
1024 int l3 = gen_new_label();
1025 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1026 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1027 gen_set_label(l3);
1028 tcg_gen_div_i64(ret, arg1, arg2);
1029 } else {
1030 tcg_gen_divu_i64(ret, arg1, arg2);
1031 }
1032 if (compute_ov) {
1033 tcg_gen_movi_tl(cpu_ov, 0);
1034 }
1035 tcg_gen_br(l2);
1036 gen_set_label(l1);
1037 if (sign) {
1038 tcg_gen_sari_i64(ret, arg1, 63);
1039 } else {
1040 tcg_gen_movi_i64(ret, 0);
1041 }
1042 if (compute_ov) {
1043 tcg_gen_movi_tl(cpu_ov, 1);
1044 tcg_gen_movi_tl(cpu_so, 1);
1045 }
1046 gen_set_label(l2);
1047 if (unlikely(Rc(ctx->opcode) != 0))
1048 gen_set_Rc0(ctx, ret);
1049 }
1050 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1051 static void glue(gen_, name)(DisasContext *ctx) \
1052 { \
1053 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1054 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1055 sign, compute_ov); \
1056 }
1057 /* divwu divwu. divwuo divwuo. */
1058 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1059 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1060 /* divw divw. divwo divwo. */
1061 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1062 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1063 #endif
1064
1065 /* mulhw mulhw. */
1066 static void gen_mulhw(DisasContext *ctx)
1067 {
1068 TCGv_i32 t0 = tcg_temp_new_i32();
1069 TCGv_i32 t1 = tcg_temp_new_i32();
1070
1071 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1072 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1073 tcg_gen_muls2_i32(t0, t1, t0, t1);
1074 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1075 tcg_temp_free_i32(t0);
1076 tcg_temp_free_i32(t1);
1077 if (unlikely(Rc(ctx->opcode) != 0))
1078 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1079 }
1080
1081 /* mulhwu mulhwu. */
1082 static void gen_mulhwu(DisasContext *ctx)
1083 {
1084 TCGv_i32 t0 = tcg_temp_new_i32();
1085 TCGv_i32 t1 = tcg_temp_new_i32();
1086
1087 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1088 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1089 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1090 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1091 tcg_temp_free_i32(t0);
1092 tcg_temp_free_i32(t1);
1093 if (unlikely(Rc(ctx->opcode) != 0))
1094 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1095 }
1096
1097 /* mullw mullw. */
1098 static void gen_mullw(DisasContext *ctx)
1099 {
1100 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1101 cpu_gpr[rB(ctx->opcode)]);
1102 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1103 if (unlikely(Rc(ctx->opcode) != 0))
1104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1105 }
1106
1107 /* mullwo mullwo. */
1108 static void gen_mullwo(DisasContext *ctx)
1109 {
1110 int l1;
1111 TCGv_i64 t0, t1;
1112
1113 t0 = tcg_temp_new_i64();
1114 t1 = tcg_temp_new_i64();
1115 l1 = gen_new_label();
1116 /* Start with XER OV disabled, the most likely case */
1117 tcg_gen_movi_tl(cpu_ov, 0);
1118 #if defined(TARGET_PPC64)
1119 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1120 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1121 #else
1122 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1123 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1124 #endif
1125 tcg_gen_mul_i64(t0, t0, t1);
1126 #if defined(TARGET_PPC64)
1127 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1128 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1129 #else
1130 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1131 tcg_gen_ext32s_i64(t1, t0);
1132 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1133 #endif
1134 tcg_gen_movi_tl(cpu_ov, 1);
1135 tcg_gen_movi_tl(cpu_so, 1);
1136 gen_set_label(l1);
1137 tcg_temp_free_i64(t0);
1138 tcg_temp_free_i64(t1);
1139 if (unlikely(Rc(ctx->opcode) != 0))
1140 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1141 }
1142
1143 /* mulli */
1144 static void gen_mulli(DisasContext *ctx)
1145 {
1146 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1147 SIMM(ctx->opcode));
1148 }
1149
1150 #if defined(TARGET_PPC64)
1151 /* mulhd mulhd. */
1152 static void gen_mulhd(DisasContext *ctx)
1153 {
1154 TCGv lo = tcg_temp_new();
1155 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1156 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1157 tcg_temp_free(lo);
1158 if (unlikely(Rc(ctx->opcode) != 0)) {
1159 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1160 }
1161 }
1162
1163 /* mulhdu mulhdu. */
1164 static void gen_mulhdu(DisasContext *ctx)
1165 {
1166 TCGv lo = tcg_temp_new();
1167 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1168 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1169 tcg_temp_free(lo);
1170 if (unlikely(Rc(ctx->opcode) != 0)) {
1171 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1172 }
1173 }
1174
1175 /* mulld mulld. */
1176 static void gen_mulld(DisasContext *ctx)
1177 {
1178 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1179 cpu_gpr[rB(ctx->opcode)]);
1180 if (unlikely(Rc(ctx->opcode) != 0))
1181 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1182 }
1183
1184 /* mulldo mulldo. */
1185 static void gen_mulldo(DisasContext *ctx)
1186 {
1187 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1188 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1189 if (unlikely(Rc(ctx->opcode) != 0)) {
1190 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1191 }
1192 }
1193 #endif
1194
1195 /* neg neg. nego nego. */
1196 static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1197 int ov_check)
1198 {
1199 int l1 = gen_new_label();
1200 int l2 = gen_new_label();
1201 TCGv t0 = tcg_temp_local_new();
1202 #if defined(TARGET_PPC64)
1203 if (ctx->sf_mode) {
1204 tcg_gen_mov_tl(t0, arg1);
1205 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1206 } else
1207 #endif
1208 {
1209 tcg_gen_ext32s_tl(t0, arg1);
1210 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1211 }
1212 tcg_gen_neg_tl(ret, arg1);
1213 if (ov_check) {
1214 tcg_gen_movi_tl(cpu_ov, 0);
1215 }
1216 tcg_gen_br(l2);
1217 gen_set_label(l1);
1218 tcg_gen_mov_tl(ret, t0);
1219 if (ov_check) {
1220 tcg_gen_movi_tl(cpu_ov, 1);
1221 tcg_gen_movi_tl(cpu_so, 1);
1222 }
1223 gen_set_label(l2);
1224 tcg_temp_free(t0);
1225 if (unlikely(Rc(ctx->opcode) != 0))
1226 gen_set_Rc0(ctx, ret);
1227 }
1228
1229 static void gen_neg(DisasContext *ctx)
1230 {
1231 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1232 }
1233
1234 static void gen_nego(DisasContext *ctx)
1235 {
1236 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1237 }
1238
1239 /* Common subf function */
1240 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1241 TCGv arg2, int add_ca, int compute_ca,
1242 int compute_ov)
1243 {
1244 TCGv t0, t1;
1245
1246 if ((!compute_ca && !compute_ov) ||
1247 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1248 t0 = ret;
1249 } else {
1250 t0 = tcg_temp_local_new();
1251 }
1252
1253 if (add_ca) {
1254 t1 = tcg_temp_local_new();
1255 tcg_gen_mov_tl(t1, cpu_ca);
1256 } else {
1257 TCGV_UNUSED(t1);
1258 }
1259
1260 if (compute_ca) {
1261 /* Start with XER CA disabled, the most likely case */
1262 tcg_gen_movi_tl(cpu_ca, 0);
1263 }
1264 if (compute_ov) {
1265 /* Start with XER OV disabled, the most likely case */
1266 tcg_gen_movi_tl(cpu_ov, 0);
1267 }
1268
1269 if (add_ca) {
1270 tcg_gen_not_tl(t0, arg1);
1271 tcg_gen_add_tl(t0, t0, arg2);
1272 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1273 tcg_gen_add_tl(t0, t0, t1);
1274 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1275 tcg_temp_free(t1);
1276 } else {
1277 tcg_gen_sub_tl(t0, arg2, arg1);
1278 if (compute_ca) {
1279 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1280 }
1281 }
1282 if (compute_ov) {
1283 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1284 }
1285
1286 if (unlikely(Rc(ctx->opcode) != 0))
1287 gen_set_Rc0(ctx, t0);
1288
1289 if (!TCGV_EQUAL(t0, ret)) {
1290 tcg_gen_mov_tl(ret, t0);
1291 tcg_temp_free(t0);
1292 }
1293 }
1294 /* Sub functions with Two operands functions */
1295 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1296 static void glue(gen_, name)(DisasContext *ctx) \
1297 { \
1298 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1299 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1300 add_ca, compute_ca, compute_ov); \
1301 }
1302 /* Sub functions with one operand and one immediate */
1303 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1304 add_ca, compute_ca, compute_ov) \
1305 static void glue(gen_, name)(DisasContext *ctx) \
1306 { \
1307 TCGv t0 = tcg_const_local_tl(const_val); \
1308 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1309 cpu_gpr[rA(ctx->opcode)], t0, \
1310 add_ca, compute_ca, compute_ov); \
1311 tcg_temp_free(t0); \
1312 }
1313 /* subf subf. subfo subfo. */
1314 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1315 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1316 /* subfc subfc. subfco subfco. */
1317 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1318 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1319 /* subfe subfe. subfeo subfo. */
1320 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1321 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1322 /* subfme subfme. subfmeo subfmeo. */
1323 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1324 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1325 /* subfze subfze. subfzeo subfzeo.*/
1326 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1327 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1328
1329 /* subfic */
1330 static void gen_subfic(DisasContext *ctx)
1331 {
1332 /* Start with XER CA disabled, the most likely case */
1333 tcg_gen_movi_tl(cpu_ca, 0);
1334 TCGv t0 = tcg_temp_local_new();
1335 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1336 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1337 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1338 tcg_temp_free(t1);
1339 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1340 tcg_temp_free(t0);
1341 }
1342
1343 /*** Integer logical ***/
1344 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1345 static void glue(gen_, name)(DisasContext *ctx) \
1346 { \
1347 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1348 cpu_gpr[rB(ctx->opcode)]); \
1349 if (unlikely(Rc(ctx->opcode) != 0)) \
1350 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1351 }
1352
1353 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1354 static void glue(gen_, name)(DisasContext *ctx) \
1355 { \
1356 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1357 if (unlikely(Rc(ctx->opcode) != 0)) \
1358 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1359 }
1360
1361 /* and & and. */
1362 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1363 /* andc & andc. */
1364 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1365
1366 /* andi. */
1367 static void gen_andi_(DisasContext *ctx)
1368 {
1369 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1370 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1371 }
1372
1373 /* andis. */
1374 static void gen_andis_(DisasContext *ctx)
1375 {
1376 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1377 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1378 }
1379
1380 /* cntlzw */
1381 static void gen_cntlzw(DisasContext *ctx)
1382 {
1383 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1384 if (unlikely(Rc(ctx->opcode) != 0))
1385 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1386 }
1387 /* eqv & eqv. */
1388 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1389 /* extsb & extsb. */
1390 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1391 /* extsh & extsh. */
1392 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1393 /* nand & nand. */
1394 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1395 /* nor & nor. */
1396 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1397
1398 /* or & or. */
1399 static void gen_or(DisasContext *ctx)
1400 {
1401 int rs, ra, rb;
1402
1403 rs = rS(ctx->opcode);
1404 ra = rA(ctx->opcode);
1405 rb = rB(ctx->opcode);
1406 /* Optimisation for mr. ri case */
1407 if (rs != ra || rs != rb) {
1408 if (rs != rb)
1409 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1410 else
1411 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1412 if (unlikely(Rc(ctx->opcode) != 0))
1413 gen_set_Rc0(ctx, cpu_gpr[ra]);
1414 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1415 gen_set_Rc0(ctx, cpu_gpr[rs]);
1416 #if defined(TARGET_PPC64)
1417 } else {
1418 int prio = 0;
1419
1420 switch (rs) {
1421 case 1:
1422 /* Set process priority to low */
1423 prio = 2;
1424 break;
1425 case 6:
1426 /* Set process priority to medium-low */
1427 prio = 3;
1428 break;
1429 case 2:
1430 /* Set process priority to normal */
1431 prio = 4;
1432 break;
1433 #if !defined(CONFIG_USER_ONLY)
1434 case 31:
1435 if (ctx->mem_idx > 0) {
1436 /* Set process priority to very low */
1437 prio = 1;
1438 }
1439 break;
1440 case 5:
1441 if (ctx->mem_idx > 0) {
1442 /* Set process priority to medium-hight */
1443 prio = 5;
1444 }
1445 break;
1446 case 3:
1447 if (ctx->mem_idx > 0) {
1448 /* Set process priority to high */
1449 prio = 6;
1450 }
1451 break;
1452 case 7:
1453 if (ctx->mem_idx > 1) {
1454 /* Set process priority to very high */
1455 prio = 7;
1456 }
1457 break;
1458 #endif
1459 default:
1460 /* nop */
1461 break;
1462 }
1463 if (prio) {
1464 TCGv t0 = tcg_temp_new();
1465 gen_load_spr(t0, SPR_PPR);
1466 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1467 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1468 gen_store_spr(SPR_PPR, t0);
1469 tcg_temp_free(t0);
1470 }
1471 #endif
1472 }
1473 }
1474 /* orc & orc. */
1475 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1476
1477 /* xor & xor. */
1478 static void gen_xor(DisasContext *ctx)
1479 {
1480 /* Optimisation for "set to zero" case */
1481 if (rS(ctx->opcode) != rB(ctx->opcode))
1482 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1483 else
1484 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1485 if (unlikely(Rc(ctx->opcode) != 0))
1486 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1487 }
1488
1489 /* ori */
1490 static void gen_ori(DisasContext *ctx)
1491 {
1492 target_ulong uimm = UIMM(ctx->opcode);
1493
1494 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1495 /* NOP */
1496 /* XXX: should handle special NOPs for POWER series */
1497 return;
1498 }
1499 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1500 }
1501
1502 /* oris */
1503 static void gen_oris(DisasContext *ctx)
1504 {
1505 target_ulong uimm = UIMM(ctx->opcode);
1506
1507 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1508 /* NOP */
1509 return;
1510 }
1511 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1512 }
1513
1514 /* xori */
1515 static void gen_xori(DisasContext *ctx)
1516 {
1517 target_ulong uimm = UIMM(ctx->opcode);
1518
1519 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1520 /* NOP */
1521 return;
1522 }
1523 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1524 }
1525
1526 /* xoris */
1527 static void gen_xoris(DisasContext *ctx)
1528 {
1529 target_ulong uimm = UIMM(ctx->opcode);
1530
1531 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1532 /* NOP */
1533 return;
1534 }
1535 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1536 }
1537
1538 /* popcntb : PowerPC 2.03 specification */
1539 static void gen_popcntb(DisasContext *ctx)
1540 {
1541 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1542 }
1543
1544 static void gen_popcntw(DisasContext *ctx)
1545 {
1546 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1547 }
1548
1549 #if defined(TARGET_PPC64)
1550 /* popcntd: PowerPC 2.06 specification */
1551 static void gen_popcntd(DisasContext *ctx)
1552 {
1553 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1554 }
1555 #endif
1556
1557 #if defined(TARGET_PPC64)
1558 /* extsw & extsw. */
1559 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1560
1561 /* cntlzd */
1562 static void gen_cntlzd(DisasContext *ctx)
1563 {
1564 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1565 if (unlikely(Rc(ctx->opcode) != 0))
1566 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1567 }
1568 #endif
1569
1570 /*** Integer rotate ***/
1571
1572 /* rlwimi & rlwimi. */
1573 static void gen_rlwimi(DisasContext *ctx)
1574 {
1575 uint32_t mb, me, sh;
1576
1577 mb = MB(ctx->opcode);
1578 me = ME(ctx->opcode);
1579 sh = SH(ctx->opcode);
1580 if (likely(sh == 0 && mb == 0 && me == 31)) {
1581 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1582 } else {
1583 target_ulong mask;
1584 TCGv t1;
1585 TCGv t0 = tcg_temp_new();
1586 #if defined(TARGET_PPC64)
1587 TCGv_i32 t2 = tcg_temp_new_i32();
1588 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1589 tcg_gen_rotli_i32(t2, t2, sh);
1590 tcg_gen_extu_i32_i64(t0, t2);
1591 tcg_temp_free_i32(t2);
1592 #else
1593 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1594 #endif
1595 #if defined(TARGET_PPC64)
1596 mb += 32;
1597 me += 32;
1598 #endif
1599 mask = MASK(mb, me);
1600 t1 = tcg_temp_new();
1601 tcg_gen_andi_tl(t0, t0, mask);
1602 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1603 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1604 tcg_temp_free(t0);
1605 tcg_temp_free(t1);
1606 }
1607 if (unlikely(Rc(ctx->opcode) != 0))
1608 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1609 }
1610
1611 /* rlwinm & rlwinm. */
1612 static void gen_rlwinm(DisasContext *ctx)
1613 {
1614 uint32_t mb, me, sh;
1615
1616 sh = SH(ctx->opcode);
1617 mb = MB(ctx->opcode);
1618 me = ME(ctx->opcode);
1619
1620 if (likely(mb == 0 && me == (31 - sh))) {
1621 if (likely(sh == 0)) {
1622 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1623 } else {
1624 TCGv t0 = tcg_temp_new();
1625 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1626 tcg_gen_shli_tl(t0, t0, sh);
1627 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1628 tcg_temp_free(t0);
1629 }
1630 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1631 TCGv t0 = tcg_temp_new();
1632 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1633 tcg_gen_shri_tl(t0, t0, mb);
1634 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1635 tcg_temp_free(t0);
1636 } else {
1637 TCGv t0 = tcg_temp_new();
1638 #if defined(TARGET_PPC64)
1639 TCGv_i32 t1 = tcg_temp_new_i32();
1640 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1641 tcg_gen_rotli_i32(t1, t1, sh);
1642 tcg_gen_extu_i32_i64(t0, t1);
1643 tcg_temp_free_i32(t1);
1644 #else
1645 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1646 #endif
1647 #if defined(TARGET_PPC64)
1648 mb += 32;
1649 me += 32;
1650 #endif
1651 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1652 tcg_temp_free(t0);
1653 }
1654 if (unlikely(Rc(ctx->opcode) != 0))
1655 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1656 }
1657
1658 /* rlwnm & rlwnm. */
1659 static void gen_rlwnm(DisasContext *ctx)
1660 {
1661 uint32_t mb, me;
1662 TCGv t0;
1663 #if defined(TARGET_PPC64)
1664 TCGv_i32 t1, t2;
1665 #endif
1666
1667 mb = MB(ctx->opcode);
1668 me = ME(ctx->opcode);
1669 t0 = tcg_temp_new();
1670 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1671 #if defined(TARGET_PPC64)
1672 t1 = tcg_temp_new_i32();
1673 t2 = tcg_temp_new_i32();
1674 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1675 tcg_gen_trunc_i64_i32(t2, t0);
1676 tcg_gen_rotl_i32(t1, t1, t2);
1677 tcg_gen_extu_i32_i64(t0, t1);
1678 tcg_temp_free_i32(t1);
1679 tcg_temp_free_i32(t2);
1680 #else
1681 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1682 #endif
1683 if (unlikely(mb != 0 || me != 31)) {
1684 #if defined(TARGET_PPC64)
1685 mb += 32;
1686 me += 32;
1687 #endif
1688 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1689 } else {
1690 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1691 }
1692 tcg_temp_free(t0);
1693 if (unlikely(Rc(ctx->opcode) != 0))
1694 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1695 }
1696
1697 #if defined(TARGET_PPC64)
1698 #define GEN_PPC64_R2(name, opc1, opc2) \
1699 static void glue(gen_, name##0)(DisasContext *ctx) \
1700 { \
1701 gen_##name(ctx, 0); \
1702 } \
1703 \
1704 static void glue(gen_, name##1)(DisasContext *ctx) \
1705 { \
1706 gen_##name(ctx, 1); \
1707 }
1708 #define GEN_PPC64_R4(name, opc1, opc2) \
1709 static void glue(gen_, name##0)(DisasContext *ctx) \
1710 { \
1711 gen_##name(ctx, 0, 0); \
1712 } \
1713 \
1714 static void glue(gen_, name##1)(DisasContext *ctx) \
1715 { \
1716 gen_##name(ctx, 0, 1); \
1717 } \
1718 \
1719 static void glue(gen_, name##2)(DisasContext *ctx) \
1720 { \
1721 gen_##name(ctx, 1, 0); \
1722 } \
1723 \
1724 static void glue(gen_, name##3)(DisasContext *ctx) \
1725 { \
1726 gen_##name(ctx, 1, 1); \
1727 }
1728
1729 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1730 uint32_t sh)
1731 {
1732 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1733 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1734 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1735 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1736 } else {
1737 TCGv t0 = tcg_temp_new();
1738 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1739 if (likely(mb == 0 && me == 63)) {
1740 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1741 } else {
1742 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1743 }
1744 tcg_temp_free(t0);
1745 }
1746 if (unlikely(Rc(ctx->opcode) != 0))
1747 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1748 }
1749 /* rldicl - rldicl. */
1750 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1751 {
1752 uint32_t sh, mb;
1753
1754 sh = SH(ctx->opcode) | (shn << 5);
1755 mb = MB(ctx->opcode) | (mbn << 5);
1756 gen_rldinm(ctx, mb, 63, sh);
1757 }
1758 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1759 /* rldicr - rldicr. */
1760 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1761 {
1762 uint32_t sh, me;
1763
1764 sh = SH(ctx->opcode) | (shn << 5);
1765 me = MB(ctx->opcode) | (men << 5);
1766 gen_rldinm(ctx, 0, me, sh);
1767 }
1768 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1769 /* rldic - rldic. */
1770 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1771 {
1772 uint32_t sh, mb;
1773
1774 sh = SH(ctx->opcode) | (shn << 5);
1775 mb = MB(ctx->opcode) | (mbn << 5);
1776 gen_rldinm(ctx, mb, 63 - sh, sh);
1777 }
1778 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1779
1780 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1781 {
1782 TCGv t0;
1783
1784 mb = MB(ctx->opcode);
1785 me = ME(ctx->opcode);
1786 t0 = tcg_temp_new();
1787 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1788 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1789 if (unlikely(mb != 0 || me != 63)) {
1790 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1791 } else {
1792 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1793 }
1794 tcg_temp_free(t0);
1795 if (unlikely(Rc(ctx->opcode) != 0))
1796 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1797 }
1798
1799 /* rldcl - rldcl. */
1800 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1801 {
1802 uint32_t mb;
1803
1804 mb = MB(ctx->opcode) | (mbn << 5);
1805 gen_rldnm(ctx, mb, 63);
1806 }
1807 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1808 /* rldcr - rldcr. */
1809 static inline void gen_rldcr(DisasContext *ctx, int men)
1810 {
1811 uint32_t me;
1812
1813 me = MB(ctx->opcode) | (men << 5);
1814 gen_rldnm(ctx, 0, me);
1815 }
1816 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1817 /* rldimi - rldimi. */
1818 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1819 {
1820 uint32_t sh, mb, me;
1821
1822 sh = SH(ctx->opcode) | (shn << 5);
1823 mb = MB(ctx->opcode) | (mbn << 5);
1824 me = 63 - sh;
1825 if (unlikely(sh == 0 && mb == 0)) {
1826 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1827 } else {
1828 TCGv t0, t1;
1829 target_ulong mask;
1830
1831 t0 = tcg_temp_new();
1832 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1833 t1 = tcg_temp_new();
1834 mask = MASK(mb, me);
1835 tcg_gen_andi_tl(t0, t0, mask);
1836 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1837 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1838 tcg_temp_free(t0);
1839 tcg_temp_free(t1);
1840 }
1841 if (unlikely(Rc(ctx->opcode) != 0))
1842 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1843 }
1844 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1845 #endif
1846
1847 /*** Integer shift ***/
1848
1849 /* slw & slw. */
1850 static void gen_slw(DisasContext *ctx)
1851 {
1852 TCGv t0, t1;
1853
1854 t0 = tcg_temp_new();
1855 /* AND rS with a mask that is 0 when rB >= 0x20 */
1856 #if defined(TARGET_PPC64)
1857 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1858 tcg_gen_sari_tl(t0, t0, 0x3f);
1859 #else
1860 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1861 tcg_gen_sari_tl(t0, t0, 0x1f);
1862 #endif
1863 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1864 t1 = tcg_temp_new();
1865 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1866 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1867 tcg_temp_free(t1);
1868 tcg_temp_free(t0);
1869 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1870 if (unlikely(Rc(ctx->opcode) != 0))
1871 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1872 }
1873
1874 /* sraw & sraw. */
1875 static void gen_sraw(DisasContext *ctx)
1876 {
1877 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1878 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1879 if (unlikely(Rc(ctx->opcode) != 0))
1880 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1881 }
1882
1883 /* srawi & srawi. */
1884 static void gen_srawi(DisasContext *ctx)
1885 {
1886 int sh = SH(ctx->opcode);
1887 if (sh != 0) {
1888 int l1, l2;
1889 TCGv t0;
1890 l1 = gen_new_label();
1891 l2 = gen_new_label();
1892 t0 = tcg_temp_local_new();
1893 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1894 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1895 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1896 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1897 tcg_gen_movi_tl(cpu_ca, 1);
1898 tcg_gen_br(l2);
1899 gen_set_label(l1);
1900 tcg_gen_movi_tl(cpu_ca, 0);
1901 gen_set_label(l2);
1902 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1903 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1904 tcg_temp_free(t0);
1905 } else {
1906 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1907 tcg_gen_movi_tl(cpu_ca, 0);
1908 }
1909 if (unlikely(Rc(ctx->opcode) != 0))
1910 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1911 }
1912
1913 /* srw & srw. */
1914 static void gen_srw(DisasContext *ctx)
1915 {
1916 TCGv t0, t1;
1917
1918 t0 = tcg_temp_new();
1919 /* AND rS with a mask that is 0 when rB >= 0x20 */
1920 #if defined(TARGET_PPC64)
1921 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1922 tcg_gen_sari_tl(t0, t0, 0x3f);
1923 #else
1924 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1925 tcg_gen_sari_tl(t0, t0, 0x1f);
1926 #endif
1927 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1928 tcg_gen_ext32u_tl(t0, t0);
1929 t1 = tcg_temp_new();
1930 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1931 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1932 tcg_temp_free(t1);
1933 tcg_temp_free(t0);
1934 if (unlikely(Rc(ctx->opcode) != 0))
1935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1936 }
1937
1938 #if defined(TARGET_PPC64)
1939 /* sld & sld. */
1940 static void gen_sld(DisasContext *ctx)
1941 {
1942 TCGv t0, t1;
1943
1944 t0 = tcg_temp_new();
1945 /* AND rS with a mask that is 0 when rB >= 0x40 */
1946 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1947 tcg_gen_sari_tl(t0, t0, 0x3f);
1948 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1949 t1 = tcg_temp_new();
1950 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1951 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1952 tcg_temp_free(t1);
1953 tcg_temp_free(t0);
1954 if (unlikely(Rc(ctx->opcode) != 0))
1955 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1956 }
1957
1958 /* srad & srad. */
1959 static void gen_srad(DisasContext *ctx)
1960 {
1961 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1962 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1963 if (unlikely(Rc(ctx->opcode) != 0))
1964 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1965 }
1966 /* sradi & sradi. */
1967 static inline void gen_sradi(DisasContext *ctx, int n)
1968 {
1969 int sh = SH(ctx->opcode) + (n << 5);
1970 if (sh != 0) {
1971 int l1, l2;
1972 TCGv t0;
1973 l1 = gen_new_label();
1974 l2 = gen_new_label();
1975 t0 = tcg_temp_local_new();
1976 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1977 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1978 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1979 tcg_gen_movi_tl(cpu_ca, 1);
1980 tcg_gen_br(l2);
1981 gen_set_label(l1);
1982 tcg_gen_movi_tl(cpu_ca, 0);
1983 gen_set_label(l2);
1984 tcg_temp_free(t0);
1985 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1986 } else {
1987 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1988 tcg_gen_movi_tl(cpu_ca, 0);
1989 }
1990 if (unlikely(Rc(ctx->opcode) != 0))
1991 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1992 }
1993
1994 static void gen_sradi0(DisasContext *ctx)
1995 {
1996 gen_sradi(ctx, 0);
1997 }
1998
1999 static void gen_sradi1(DisasContext *ctx)
2000 {
2001 gen_sradi(ctx, 1);
2002 }
2003
2004 /* srd & srd. */
2005 static void gen_srd(DisasContext *ctx)
2006 {
2007 TCGv t0, t1;
2008
2009 t0 = tcg_temp_new();
2010 /* AND rS with a mask that is 0 when rB >= 0x40 */
2011 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2012 tcg_gen_sari_tl(t0, t0, 0x3f);
2013 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2014 t1 = tcg_temp_new();
2015 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2016 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2017 tcg_temp_free(t1);
2018 tcg_temp_free(t0);
2019 if (unlikely(Rc(ctx->opcode) != 0))
2020 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2021 }
2022 #endif
2023
2024 /*** Floating-Point arithmetic ***/
2025 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2026 static void gen_f##name(DisasContext *ctx) \
2027 { \
2028 if (unlikely(!ctx->fpu_enabled)) { \
2029 gen_exception(ctx, POWERPC_EXCP_FPU); \
2030 return; \
2031 } \
2032 /* NIP cannot be restored if the memory exception comes from an helper */ \
2033 gen_update_nip(ctx, ctx->nip - 4); \
2034 gen_reset_fpstatus(); \
2035 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2036 cpu_fpr[rA(ctx->opcode)], \
2037 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2038 if (isfloat) { \
2039 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2040 cpu_fpr[rD(ctx->opcode)]); \
2041 } \
2042 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2043 Rc(ctx->opcode) != 0); \
2044 }
2045
2046 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2047 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2048 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2049
2050 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2051 static void gen_f##name(DisasContext *ctx) \
2052 { \
2053 if (unlikely(!ctx->fpu_enabled)) { \
2054 gen_exception(ctx, POWERPC_EXCP_FPU); \
2055 return; \
2056 } \
2057 /* NIP cannot be restored if the memory exception comes from an helper */ \
2058 gen_update_nip(ctx, ctx->nip - 4); \
2059 gen_reset_fpstatus(); \
2060 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2061 cpu_fpr[rA(ctx->opcode)], \
2062 cpu_fpr[rB(ctx->opcode)]); \
2063 if (isfloat) { \
2064 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2065 cpu_fpr[rD(ctx->opcode)]); \
2066 } \
2067 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2068 set_fprf, Rc(ctx->opcode) != 0); \
2069 }
2070 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2071 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2072 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2073
2074 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2075 static void gen_f##name(DisasContext *ctx) \
2076 { \
2077 if (unlikely(!ctx->fpu_enabled)) { \
2078 gen_exception(ctx, POWERPC_EXCP_FPU); \
2079 return; \
2080 } \
2081 /* NIP cannot be restored if the memory exception comes from an helper */ \
2082 gen_update_nip(ctx, ctx->nip - 4); \
2083 gen_reset_fpstatus(); \
2084 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2085 cpu_fpr[rA(ctx->opcode)], \
2086 cpu_fpr[rC(ctx->opcode)]); \
2087 if (isfloat) { \
2088 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2089 cpu_fpr[rD(ctx->opcode)]); \
2090 } \
2091 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2092 set_fprf, Rc(ctx->opcode) != 0); \
2093 }
2094 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2095 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2096 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2097
2098 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2099 static void gen_f##name(DisasContext *ctx) \
2100 { \
2101 if (unlikely(!ctx->fpu_enabled)) { \
2102 gen_exception(ctx, POWERPC_EXCP_FPU); \
2103 return; \
2104 } \
2105 /* NIP cannot be restored if the memory exception comes from an helper */ \
2106 gen_update_nip(ctx, ctx->nip - 4); \
2107 gen_reset_fpstatus(); \
2108 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2109 cpu_fpr[rB(ctx->opcode)]); \
2110 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2111 set_fprf, Rc(ctx->opcode) != 0); \
2112 }
2113
2114 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2115 static void gen_f##name(DisasContext *ctx) \
2116 { \
2117 if (unlikely(!ctx->fpu_enabled)) { \
2118 gen_exception(ctx, POWERPC_EXCP_FPU); \
2119 return; \
2120 } \
2121 /* NIP cannot be restored if the memory exception comes from an helper */ \
2122 gen_update_nip(ctx, ctx->nip - 4); \
2123 gen_reset_fpstatus(); \
2124 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2125 cpu_fpr[rB(ctx->opcode)]); \
2126 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2127 set_fprf, Rc(ctx->opcode) != 0); \
2128 }
2129
2130 /* fadd - fadds */
2131 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2132 /* fdiv - fdivs */
2133 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2134 /* fmul - fmuls */
2135 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2136
2137 /* fre */
2138 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2139
2140 /* fres */
2141 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2142
2143 /* frsqrte */
2144 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2145
2146 /* frsqrtes */
2147 static void gen_frsqrtes(DisasContext *ctx)
2148 {
2149 if (unlikely(!ctx->fpu_enabled)) {
2150 gen_exception(ctx, POWERPC_EXCP_FPU);
2151 return;
2152 }
2153 /* NIP cannot be restored if the memory exception comes from an helper */
2154 gen_update_nip(ctx, ctx->nip - 4);
2155 gen_reset_fpstatus();
2156 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2157 cpu_fpr[rB(ctx->opcode)]);
2158 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2159 cpu_fpr[rD(ctx->opcode)]);
2160 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2161 }
2162
2163 /* fsel */
2164 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2165 /* fsub - fsubs */
2166 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2167 /* Optional: */
2168
2169 /* fsqrt */
2170 static void gen_fsqrt(DisasContext *ctx)
2171 {
2172 if (unlikely(!ctx->fpu_enabled)) {
2173 gen_exception(ctx, POWERPC_EXCP_FPU);
2174 return;
2175 }
2176 /* NIP cannot be restored if the memory exception comes from an helper */
2177 gen_update_nip(ctx, ctx->nip - 4);
2178 gen_reset_fpstatus();
2179 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2180 cpu_fpr[rB(ctx->opcode)]);
2181 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2182 }
2183
2184 static void gen_fsqrts(DisasContext *ctx)
2185 {
2186 if (unlikely(!ctx->fpu_enabled)) {
2187 gen_exception(ctx, POWERPC_EXCP_FPU);
2188 return;
2189 }
2190 /* NIP cannot be restored if the memory exception comes from an helper */
2191 gen_update_nip(ctx, ctx->nip - 4);
2192 gen_reset_fpstatus();
2193 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2194 cpu_fpr[rB(ctx->opcode)]);
2195 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2196 cpu_fpr[rD(ctx->opcode)]);
2197 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2198 }
2199
2200 /*** Floating-Point multiply-and-add ***/
2201 /* fmadd - fmadds */
2202 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2203 /* fmsub - fmsubs */
2204 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2205 /* fnmadd - fnmadds */
2206 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2207 /* fnmsub - fnmsubs */
2208 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2209
2210 /*** Floating-Point round & convert ***/
2211 /* fctiw */
2212 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2213 /* fctiwz */
2214 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2215 /* frsp */
2216 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2217 #if defined(TARGET_PPC64)
2218 /* fcfid */
2219 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2220 /* fctid */
2221 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2222 /* fctidz */
2223 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2224 #endif
2225
2226 /* frin */
2227 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2228 /* friz */
2229 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2230 /* frip */
2231 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2232 /* frim */
2233 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2234
2235 /*** Floating-Point compare ***/
2236
2237 /* fcmpo */
2238 static void gen_fcmpo(DisasContext *ctx)
2239 {
2240 TCGv_i32 crf;
2241 if (unlikely(!ctx->fpu_enabled)) {
2242 gen_exception(ctx, POWERPC_EXCP_FPU);
2243 return;
2244 }
2245 /* NIP cannot be restored if the memory exception comes from an helper */
2246 gen_update_nip(ctx, ctx->nip - 4);
2247 gen_reset_fpstatus();
2248 crf = tcg_const_i32(crfD(ctx->opcode));
2249 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2250 cpu_fpr[rB(ctx->opcode)], crf);
2251 tcg_temp_free_i32(crf);
2252 gen_helper_float_check_status(cpu_env);
2253 }
2254
2255 /* fcmpu */
2256 static void gen_fcmpu(DisasContext *ctx)
2257 {
2258 TCGv_i32 crf;
2259 if (unlikely(!ctx->fpu_enabled)) {
2260 gen_exception(ctx, POWERPC_EXCP_FPU);
2261 return;
2262 }
2263 /* NIP cannot be restored if the memory exception comes from an helper */
2264 gen_update_nip(ctx, ctx->nip - 4);
2265 gen_reset_fpstatus();
2266 crf = tcg_const_i32(crfD(ctx->opcode));
2267 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2268 cpu_fpr[rB(ctx->opcode)], crf);
2269 tcg_temp_free_i32(crf);
2270 gen_helper_float_check_status(cpu_env);
2271 }
2272
2273 /*** Floating-point move ***/
2274 /* fabs */
2275 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2276 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2277
2278 /* fmr - fmr. */
2279 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2280 static void gen_fmr(DisasContext *ctx)
2281 {
2282 if (unlikely(!ctx->fpu_enabled)) {
2283 gen_exception(ctx, POWERPC_EXCP_FPU);
2284 return;
2285 }
2286 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2287 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2288 }
2289
2290 /* fnabs */
2291 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2292 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2293 /* fneg */
2294 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2295 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2296
2297 /*** Floating-Point status & ctrl register ***/
2298
2299 /* mcrfs */
2300 static void gen_mcrfs(DisasContext *ctx)
2301 {
2302 TCGv tmp = tcg_temp_new();
2303 int bfa;
2304
2305 if (unlikely(!ctx->fpu_enabled)) {
2306 gen_exception(ctx, POWERPC_EXCP_FPU);
2307 return;
2308 }
2309 bfa = 4 * (7 - crfS(ctx->opcode));
2310 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2311 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2312 tcg_temp_free(tmp);
2313 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2314 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2315 }
2316
2317 /* mffs */
2318 static void gen_mffs(DisasContext *ctx)
2319 {
2320 if (unlikely(!ctx->fpu_enabled)) {
2321 gen_exception(ctx, POWERPC_EXCP_FPU);
2322 return;
2323 }
2324 gen_reset_fpstatus();
2325 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2326 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2327 }
2328
2329 /* mtfsb0 */
2330 static void gen_mtfsb0(DisasContext *ctx)
2331 {
2332 uint8_t crb;
2333
2334 if (unlikely(!ctx->fpu_enabled)) {
2335 gen_exception(ctx, POWERPC_EXCP_FPU);
2336 return;
2337 }
2338 crb = 31 - crbD(ctx->opcode);
2339 gen_reset_fpstatus();
2340 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2341 TCGv_i32 t0;
2342 /* NIP cannot be restored if the memory exception comes from an helper */
2343 gen_update_nip(ctx, ctx->nip - 4);
2344 t0 = tcg_const_i32(crb);
2345 gen_helper_fpscr_clrbit(cpu_env, t0);
2346 tcg_temp_free_i32(t0);
2347 }
2348 if (unlikely(Rc(ctx->opcode) != 0)) {
2349 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2350 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2351 }
2352 }
2353
2354 /* mtfsb1 */
2355 static void gen_mtfsb1(DisasContext *ctx)
2356 {
2357 uint8_t crb;
2358
2359 if (unlikely(!ctx->fpu_enabled)) {
2360 gen_exception(ctx, POWERPC_EXCP_FPU);
2361 return;
2362 }
2363 crb = 31 - crbD(ctx->opcode);
2364 gen_reset_fpstatus();
2365 /* XXX: we pretend we can only do IEEE floating-point computations */
2366 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2367 TCGv_i32 t0;
2368 /* NIP cannot be restored if the memory exception comes from an helper */
2369 gen_update_nip(ctx, ctx->nip - 4);
2370 t0 = tcg_const_i32(crb);
2371 gen_helper_fpscr_setbit(cpu_env, t0);
2372 tcg_temp_free_i32(t0);
2373 }
2374 if (unlikely(Rc(ctx->opcode) != 0)) {
2375 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2376 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2377 }
2378 /* We can raise a differed exception */
2379 gen_helper_float_check_status(cpu_env);
2380 }
2381
2382 /* mtfsf */
2383 static void gen_mtfsf(DisasContext *ctx)
2384 {
2385 TCGv_i32 t0;
2386 int L = ctx->opcode & 0x02000000;
2387
2388 if (unlikely(!ctx->fpu_enabled)) {
2389 gen_exception(ctx, POWERPC_EXCP_FPU);
2390 return;
2391 }
2392 /* NIP cannot be restored if the memory exception comes from an helper */
2393 gen_update_nip(ctx, ctx->nip - 4);
2394 gen_reset_fpstatus();
2395 if (L)
2396 t0 = tcg_const_i32(0xff);
2397 else
2398 t0 = tcg_const_i32(FM(ctx->opcode));
2399 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2400 tcg_temp_free_i32(t0);
2401 if (unlikely(Rc(ctx->opcode) != 0)) {
2402 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2403 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2404 }
2405 /* We can raise a differed exception */
2406 gen_helper_float_check_status(cpu_env);
2407 }
2408
2409 /* mtfsfi */
2410 static void gen_mtfsfi(DisasContext *ctx)
2411 {
2412 int bf, sh;
2413 TCGv_i64 t0;
2414 TCGv_i32 t1;
2415
2416 if (unlikely(!ctx->fpu_enabled)) {
2417 gen_exception(ctx, POWERPC_EXCP_FPU);
2418 return;
2419 }
2420 bf = crbD(ctx->opcode) >> 2;
2421 sh = 7 - bf;
2422 /* NIP cannot be restored if the memory exception comes from an helper */
2423 gen_update_nip(ctx, ctx->nip - 4);
2424 gen_reset_fpstatus();
2425 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2426 t1 = tcg_const_i32(1 << sh);
2427 gen_helper_store_fpscr(cpu_env, t0, t1);
2428 tcg_temp_free_i64(t0);
2429 tcg_temp_free_i32(t1);
2430 if (unlikely(Rc(ctx->opcode) != 0)) {
2431 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2432 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2433 }
2434 /* We can raise a differed exception */
2435 gen_helper_float_check_status(cpu_env);
2436 }
2437
2438 /*** Addressing modes ***/
2439 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2440 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2441 target_long maskl)
2442 {
2443 target_long simm = SIMM(ctx->opcode);
2444
2445 simm &= ~maskl;
2446 if (rA(ctx->opcode) == 0) {
2447 #if defined(TARGET_PPC64)
2448 if (!ctx->sf_mode) {
2449 tcg_gen_movi_tl(EA, (uint32_t)simm);
2450 } else
2451 #endif
2452 tcg_gen_movi_tl(EA, simm);
2453 } else if (likely(simm != 0)) {
2454 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2455 #if defined(TARGET_PPC64)
2456 if (!ctx->sf_mode) {
2457 tcg_gen_ext32u_tl(EA, EA);
2458 }
2459 #endif
2460 } else {
2461 #if defined(TARGET_PPC64)
2462 if (!ctx->sf_mode) {
2463 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2464 } else
2465 #endif
2466 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2467 }
2468 }
2469
2470 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2471 {
2472 if (rA(ctx->opcode) == 0) {
2473 #if defined(TARGET_PPC64)
2474 if (!ctx->sf_mode) {
2475 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2476 } else
2477 #endif
2478 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2479 } else {
2480 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2481 #if defined(TARGET_PPC64)
2482 if (!ctx->sf_mode) {
2483 tcg_gen_ext32u_tl(EA, EA);
2484 }
2485 #endif
2486 }
2487 }
2488
2489 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2490 {
2491 if (rA(ctx->opcode) == 0) {
2492 tcg_gen_movi_tl(EA, 0);
2493 } else {
2494 #if defined(TARGET_PPC64)
2495 if (!ctx->sf_mode) {
2496 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2497 } else
2498 #endif
2499 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2500 }
2501 }
2502
2503 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2504 target_long val)
2505 {
2506 tcg_gen_addi_tl(ret, arg1, val);
2507 #if defined(TARGET_PPC64)
2508 if (!ctx->sf_mode) {
2509 tcg_gen_ext32u_tl(ret, ret);
2510 }
2511 #endif
2512 }
2513
2514 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2515 {
2516 int l1 = gen_new_label();
2517 TCGv t0 = tcg_temp_new();
2518 TCGv_i32 t1, t2;
2519 /* NIP cannot be restored if the memory exception comes from an helper */
2520 gen_update_nip(ctx, ctx->nip - 4);
2521 tcg_gen_andi_tl(t0, EA, mask);
2522 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2523 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2524 t2 = tcg_const_i32(0);
2525 gen_helper_raise_exception_err(cpu_env, t1, t2);
2526 tcg_temp_free_i32(t1);
2527 tcg_temp_free_i32(t2);
2528 gen_set_label(l1);
2529 tcg_temp_free(t0);
2530 }
2531
2532 /*** Integer load ***/
2533 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2534 {
2535 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2536 }
2537
2538 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2539 {
2540 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2541 }
2542
2543 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2544 {
2545 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2546 if (unlikely(ctx->le_mode)) {
2547 tcg_gen_bswap16_tl(arg1, arg1);
2548 }
2549 }
2550
2551 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2552 {
2553 if (unlikely(ctx->le_mode)) {
2554 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2555 tcg_gen_bswap16_tl(arg1, arg1);
2556 tcg_gen_ext16s_tl(arg1, arg1);
2557 } else {
2558 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2559 }
2560 }
2561
2562 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2563 {
2564 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2565 if (unlikely(ctx->le_mode)) {
2566 tcg_gen_bswap32_tl(arg1, arg1);
2567 }
2568 }
2569
2570 #if defined(TARGET_PPC64)
2571 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2572 {
2573 if (unlikely(ctx->le_mode)) {
2574 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2575 tcg_gen_bswap32_tl(arg1, arg1);
2576 tcg_gen_ext32s_tl(arg1, arg1);
2577 } else
2578 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2579 }
2580 #endif
2581
2582 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2583 {
2584 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2585 if (unlikely(ctx->le_mode)) {
2586 tcg_gen_bswap64_i64(arg1, arg1);
2587 }
2588 }
2589
2590 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2591 {
2592 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2593 }
2594
2595 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2596 {
2597 if (unlikely(ctx->le_mode)) {
2598 TCGv t0 = tcg_temp_new();
2599 tcg_gen_ext16u_tl(t0, arg1);
2600 tcg_gen_bswap16_tl(t0, t0);
2601 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2602 tcg_temp_free(t0);
2603 } else {
2604 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2605 }
2606 }
2607
2608 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2609 {
2610 if (unlikely(ctx->le_mode)) {
2611 TCGv t0 = tcg_temp_new();
2612 tcg_gen_ext32u_tl(t0, arg1);
2613 tcg_gen_bswap32_tl(t0, t0);
2614 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2615 tcg_temp_free(t0);
2616 } else {
2617 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2618 }
2619 }
2620
2621 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2622 {
2623 if (unlikely(ctx->le_mode)) {
2624 TCGv_i64 t0 = tcg_temp_new_i64();
2625 tcg_gen_bswap64_i64(t0, arg1);
2626 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2627 tcg_temp_free_i64(t0);
2628 } else
2629 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2630 }
2631
2632 #define GEN_LD(name, ldop, opc, type) \
2633 static void glue(gen_, name)(DisasContext *ctx) \
2634 { \
2635 TCGv EA; \
2636 gen_set_access_type(ctx, ACCESS_INT); \
2637 EA = tcg_temp_new(); \
2638 gen_addr_imm_index(ctx, EA, 0); \
2639 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2640 tcg_temp_free(EA); \
2641 }
2642
2643 #define GEN_LDU(name, ldop, opc, type) \
2644 static void glue(gen_, name##u)(DisasContext *ctx) \
2645 { \
2646 TCGv EA; \
2647 if (unlikely(rA(ctx->opcode) == 0 || \
2648 rA(ctx->opcode) == rD(ctx->opcode))) { \
2649 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2650 return; \
2651 } \
2652 gen_set_access_type(ctx, ACCESS_INT); \
2653 EA = tcg_temp_new(); \
2654 if (type == PPC_64B) \
2655 gen_addr_imm_index(ctx, EA, 0x03); \
2656 else \
2657 gen_addr_imm_index(ctx, EA, 0); \
2658 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2659 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2660 tcg_temp_free(EA); \
2661 }
2662
2663 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2664 static void glue(gen_, name##ux)(DisasContext *ctx) \
2665 { \
2666 TCGv EA; \
2667 if (unlikely(rA(ctx->opcode) == 0 || \
2668 rA(ctx->opcode) == rD(ctx->opcode))) { \
2669 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2670 return; \
2671 } \
2672 gen_set_access_type(ctx, ACCESS_INT); \
2673 EA = tcg_temp_new(); \
2674 gen_addr_reg_index(ctx, EA); \
2675 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2676 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2677 tcg_temp_free(EA); \
2678 }
2679
2680 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2681 static void glue(gen_, name##x)(DisasContext *ctx) \
2682 { \
2683 TCGv EA; \
2684 gen_set_access_type(ctx, ACCESS_INT); \
2685 EA = tcg_temp_new(); \
2686 gen_addr_reg_index(ctx, EA); \
2687 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2688 tcg_temp_free(EA); \
2689 }
2690 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2691 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2692
2693 #define GEN_LDS(name, ldop, op, type) \
2694 GEN_LD(name, ldop, op | 0x20, type); \
2695 GEN_LDU(name, ldop, op | 0x21, type); \
2696 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2697 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2698
2699 /* lbz lbzu lbzux lbzx */
2700 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2701 /* lha lhau lhaux lhax */
2702 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2703 /* lhz lhzu lhzux lhzx */
2704 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2705 /* lwz lwzu lwzux lwzx */
2706 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2707 #if defined(TARGET_PPC64)
2708 /* lwaux */
2709 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2710 /* lwax */
2711 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2712 /* ldux */
2713 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2714 /* ldx */
2715 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2716
2717 static void gen_ld(DisasContext *ctx)
2718 {
2719 TCGv EA;
2720 if (Rc(ctx->opcode)) {
2721 if (unlikely(rA(ctx->opcode) == 0 ||
2722 rA(ctx->opcode) == rD(ctx->opcode))) {
2723 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2724 return;
2725 }
2726 }
2727 gen_set_access_type(ctx, ACCESS_INT);
2728 EA = tcg_temp_new();
2729 gen_addr_imm_index(ctx, EA, 0x03);
2730 if (ctx->opcode & 0x02) {
2731 /* lwa (lwau is undefined) */
2732 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2733 } else {
2734 /* ld - ldu */
2735 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2736 }
2737 if (Rc(ctx->opcode))
2738 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2739 tcg_temp_free(EA);
2740 }
2741
2742 /* lq */
2743 static void gen_lq(DisasContext *ctx)
2744 {
2745 #if defined(CONFIG_USER_ONLY)
2746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2747 #else
2748 int ra, rd;
2749 TCGv EA;
2750
2751 /* Restore CPU state */
2752 if (unlikely(ctx->mem_idx == 0)) {
2753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2754 return;
2755 }
2756 ra = rA(ctx->opcode);
2757 rd = rD(ctx->opcode);
2758 if (unlikely((rd & 1) || rd == ra)) {
2759 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2760 return;
2761 }
2762 if (unlikely(ctx->le_mode)) {
2763 /* Little-endian mode is not handled */
2764 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2765 return;
2766 }
2767 gen_set_access_type(ctx, ACCESS_INT);
2768 EA = tcg_temp_new();
2769 gen_addr_imm_index(ctx, EA, 0x0F);
2770 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2771 gen_addr_add(ctx, EA, EA, 8);
2772 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2773 tcg_temp_free(EA);
2774 #endif
2775 }
2776 #endif
2777
2778 /*** Integer store ***/
2779 #define GEN_ST(name, stop, opc, type) \
2780 static void glue(gen_, name)(DisasContext *ctx) \
2781 { \
2782 TCGv EA; \
2783 gen_set_access_type(ctx, ACCESS_INT); \
2784 EA = tcg_temp_new(); \
2785 gen_addr_imm_index(ctx, EA, 0); \
2786 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2787 tcg_temp_free(EA); \
2788 }
2789
2790 #define GEN_STU(name, stop, opc, type) \
2791 static void glue(gen_, stop##u)(DisasContext *ctx) \
2792 { \
2793 TCGv EA; \
2794 if (unlikely(rA(ctx->opcode) == 0)) { \
2795 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2796 return; \
2797 } \
2798 gen_set_access_type(ctx, ACCESS_INT); \
2799 EA = tcg_temp_new(); \
2800 if (type == PPC_64B) \
2801 gen_addr_imm_index(ctx, EA, 0x03); \
2802 else \
2803 gen_addr_imm_index(ctx, EA, 0); \
2804 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2805 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2806 tcg_temp_free(EA); \
2807 }
2808
2809 #define GEN_STUX(name, stop, opc2, opc3, type) \
2810 static void glue(gen_, name##ux)(DisasContext *ctx) \
2811 { \
2812 TCGv EA; \
2813 if (unlikely(rA(ctx->opcode) == 0)) { \
2814 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2815 return; \
2816 } \
2817 gen_set_access_type(ctx, ACCESS_INT); \
2818 EA = tcg_temp_new(); \
2819 gen_addr_reg_index(ctx, EA); \
2820 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2821 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2822 tcg_temp_free(EA); \
2823 }
2824
2825 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2826 static void glue(gen_, name##x)(DisasContext *ctx) \
2827 { \
2828 TCGv EA; \
2829 gen_set_access_type(ctx, ACCESS_INT); \
2830 EA = tcg_temp_new(); \
2831 gen_addr_reg_index(ctx, EA); \
2832 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2833 tcg_temp_free(EA); \
2834 }
2835 #define GEN_STX(name, stop, opc2, opc3, type) \
2836 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2837
2838 #define GEN_STS(name, stop, op, type) \
2839 GEN_ST(name, stop, op | 0x20, type); \
2840 GEN_STU(name, stop, op | 0x21, type); \
2841 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2842 GEN_STX(name, stop, 0x17, op | 0x00, type)
2843
2844 /* stb stbu stbux stbx */
2845 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2846 /* sth sthu sthux sthx */
2847 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2848 /* stw stwu stwux stwx */
2849 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2850 #if defined(TARGET_PPC64)
2851 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2852 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2853
2854 static void gen_std(DisasContext *ctx)
2855 {
2856 int rs;
2857 TCGv EA;
2858
2859 rs = rS(ctx->opcode);
2860 if ((ctx->opcode & 0x3) == 0x2) {
2861 #if defined(CONFIG_USER_ONLY)
2862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2863 #else
2864 /* stq */
2865 if (unlikely(ctx->mem_idx == 0)) {
2866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2867 return;
2868 }
2869 if (unlikely(rs & 1)) {
2870 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2871 return;
2872 }
2873 if (unlikely(ctx->le_mode)) {
2874 /* Little-endian mode is not handled */
2875 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2876 return;
2877 }
2878 gen_set_access_type(ctx, ACCESS_INT);
2879 EA = tcg_temp_new();
2880 gen_addr_imm_index(ctx, EA, 0x03);
2881 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2882 gen_addr_add(ctx, EA, EA, 8);
2883 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2884 tcg_temp_free(EA);
2885 #endif
2886 } else {
2887 /* std / stdu */
2888 if (Rc(ctx->opcode)) {
2889 if (unlikely(rA(ctx->opcode) == 0)) {
2890 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2891 return;
2892 }
2893 }
2894 gen_set_access_type(ctx, ACCESS_INT);
2895 EA = tcg_temp_new();
2896 gen_addr_imm_index(ctx, EA, 0x03);
2897 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2898 if (Rc(ctx->opcode))
2899 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2900 tcg_temp_free(EA);
2901 }
2902 }
2903 #endif
2904 /*** Integer load and store with byte reverse ***/
2905 /* lhbrx */
2906 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2907 {
2908 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2909 if (likely(!ctx->le_mode)) {
2910 tcg_gen_bswap16_tl(arg1, arg1);
2911 }
2912 }
2913 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2914
2915 /* lwbrx */
2916 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2917 {
2918 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2919 if (likely(!ctx->le_mode)) {
2920 tcg_gen_bswap32_tl(arg1, arg1);
2921 }
2922 }
2923 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2924
2925 #if defined(TARGET_PPC64)
2926 /* ldbrx */
2927 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2928 {
2929 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2930 if (likely(!ctx->le_mode)) {
2931 tcg_gen_bswap64_tl(arg1, arg1);
2932 }
2933 }
2934 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2935 #endif /* TARGET_PPC64 */
2936
2937 /* sthbrx */
2938 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2939 {
2940 if (likely(!ctx->le_mode)) {
2941 TCGv t0 = tcg_temp_new();
2942 tcg_gen_ext16u_tl(t0, arg1);
2943 tcg_gen_bswap16_tl(t0, t0);
2944 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2945 tcg_temp_free(t0);
2946 } else {
2947 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2948 }
2949 }
2950 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2951
2952 /* stwbrx */
2953 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2954 {
2955 if (likely(!ctx->le_mode)) {
2956 TCGv t0 = tcg_temp_new();
2957 tcg_gen_ext32u_tl(t0, arg1);
2958 tcg_gen_bswap32_tl(t0, t0);
2959 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2960 tcg_temp_free(t0);
2961 } else {
2962 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2963 }
2964 }
2965 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2966
2967 #if defined(TARGET_PPC64)
2968 /* stdbrx */
2969 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2970 {
2971 if (likely(!ctx->le_mode)) {
2972 TCGv t0 = tcg_temp_new();
2973 tcg_gen_bswap64_tl(t0, arg1);
2974 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2975 tcg_temp_free(t0);
2976 } else {
2977 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2978 }
2979 }
2980 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2981 #endif /* TARGET_PPC64 */
2982
2983 /*** Integer load and store multiple ***/
2984
2985 /* lmw */
2986 static void gen_lmw(DisasContext *ctx)
2987 {
2988 TCGv t0;
2989 TCGv_i32 t1;
2990 gen_set_access_type(ctx, ACCESS_INT);
2991 /* NIP cannot be restored if the memory exception comes from an helper */
2992 gen_update_nip(ctx, ctx->nip - 4);
2993 t0 = tcg_temp_new();
2994 t1 = tcg_const_i32(rD(ctx->opcode));
2995 gen_addr_imm_index(ctx, t0, 0);
2996 gen_helper_lmw(cpu_env, t0, t1);
2997 tcg_temp_free(t0);
2998 tcg_temp_free_i32(t1);
2999 }
3000
3001 /* stmw */
3002 static void gen_stmw(DisasContext *ctx)
3003 {
3004 TCGv t0;
3005 TCGv_i32 t1;
3006 gen_set_access_type(ctx, ACCESS_INT);
3007 /* NIP cannot be restored if the memory exception comes from an helper */
3008 gen_update_nip(ctx, ctx->nip - 4);
3009 t0 = tcg_temp_new();
3010 t1 = tcg_const_i32(rS(ctx->opcode));
3011 gen_addr_imm_index(ctx, t0, 0);
3012 gen_helper_stmw(cpu_env, t0, t1);
3013 tcg_temp_free(t0);
3014 tcg_temp_free_i32(t1);
3015 }
3016
3017 /*** Integer load and store strings ***/
3018
3019 /* lswi */
3020 /* PowerPC32 specification says we must generate an exception if
3021 * rA is in the range of registers to be loaded.
3022 * In an other hand, IBM says this is valid, but rA won't be loaded.
3023 * For now, I'll follow the spec...
3024 */
3025 static void gen_lswi(DisasContext *ctx)
3026 {
3027 TCGv t0;
3028 TCGv_i32 t1, t2;
3029 int nb = NB(ctx->opcode);
3030 int start = rD(ctx->opcode);
3031 int ra = rA(ctx->opcode);
3032 int nr;
3033
3034 if (nb == 0)
3035 nb = 32;
3036 nr = nb / 4;
3037 if (unlikely(((start + nr) > 32 &&
3038 start <= ra && (start + nr - 32) > ra) ||
3039 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3040 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3041 return;
3042 }
3043 gen_set_access_type(ctx, ACCESS_INT);
3044 /* NIP cannot be restored if the memory exception comes from an helper */
3045 gen_update_nip(ctx, ctx->nip - 4);
3046 t0 = tcg_temp_new();
3047 gen_addr_register(ctx, t0);
3048 t1 = tcg_const_i32(nb);
3049 t2 = tcg_const_i32(start);
3050 gen_helper_lsw(cpu_env, t0, t1, t2);
3051 tcg_temp_free(t0);
3052 tcg_temp_free_i32(t1);
3053 tcg_temp_free_i32(t2);
3054 }
3055
3056 /* lswx */
3057 static void gen_lswx(DisasContext *ctx)
3058 {
3059 TCGv t0;
3060 TCGv_i32 t1, t2, t3;
3061 gen_set_access_type(ctx, ACCESS_INT);
3062 /* NIP cannot be restored if the memory exception comes from an helper */
3063 gen_update_nip(ctx, ctx->nip - 4);
3064 t0 = tcg_temp_new();
3065 gen_addr_reg_index(ctx, t0);
3066 t1 = tcg_const_i32(rD(ctx->opcode));
3067 t2 = tcg_const_i32(rA(ctx->opcode));
3068 t3 = tcg_const_i32(rB(ctx->opcode));
3069 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3070 tcg_temp_free(t0);
3071 tcg_temp_free_i32(t1);
3072 tcg_temp_free_i32(t2);
3073 tcg_temp_free_i32(t3);
3074 }
3075
3076 /* stswi */
3077 static void gen_stswi(DisasContext *ctx)
3078 {
3079 TCGv t0;
3080 TCGv_i32 t1, t2;
3081 int nb = NB(ctx->opcode);
3082 gen_set_access_type(ctx, ACCESS_INT);
3083 /* NIP cannot be restored if the memory exception comes from an helper */
3084 gen_update_nip(ctx, ctx->nip - 4);
3085 t0 = tcg_temp_new();
3086 gen_addr_register(ctx, t0);
3087 if (nb == 0)
3088 nb = 32;
3089 t1 = tcg_const_i32(nb);
3090 t2 = tcg_const_i32(rS(ctx->opcode));
3091 gen_helper_stsw(cpu_env, t0, t1, t2);
3092 tcg_temp_free(t0);
3093 tcg_temp_free_i32(t1);
3094 tcg_temp_free_i32(t2);
3095 }
3096
3097 /* stswx */
3098 static void gen_stswx(DisasContext *ctx)
3099 {
3100 TCGv t0;
3101 TCGv_i32 t1, t2;
3102 gen_set_access_type(ctx, ACCESS_INT);
3103 /* NIP cannot be restored if the memory exception comes from an helper */
3104 gen_update_nip(ctx, ctx->nip - 4);
3105 t0 = tcg_temp_new();
3106 gen_addr_reg_index(ctx, t0);
3107 t1 = tcg_temp_new_i32();
3108 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3109 tcg_gen_andi_i32(t1, t1, 0x7F);
3110 t2 = tcg_const_i32(rS(ctx->opcode));
3111 gen_helper_stsw(cpu_env, t0, t1, t2);
3112 tcg_temp_free(t0);
3113 tcg_temp_free_i32(t1);
3114 tcg_temp_free_i32(t2);
3115 }
3116
3117 /*** Memory synchronisation ***/
3118 /* eieio */
3119 static void gen_eieio(DisasContext *ctx)
3120 {
3121 }
3122
3123 /* isync */
3124 static void gen_isync(DisasContext *ctx)
3125 {
3126 gen_stop_exception(ctx);
3127 }
3128
3129 /* lwarx */
3130 static void gen_lwarx(DisasContext *ctx)
3131 {
3132 TCGv t0;
3133 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3134 gen_set_access_type(ctx, ACCESS_RES);
3135 t0 = tcg_temp_local_new();
3136 gen_addr_reg_index(ctx, t0);
3137 gen_check_align(ctx, t0, 0x03);
3138 gen_qemu_ld32u(ctx, gpr, t0);
3139 tcg_gen_mov_tl(cpu_reserve, t0);
3140 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3141 tcg_temp_free(t0);
3142 }
3143
3144 #if defined(CONFIG_USER_ONLY)
3145 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3146 int reg, int size)
3147 {
3148 TCGv t0 = tcg_temp_new();
3149 uint32_t save_exception = ctx->exception;
3150
3151 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3152 tcg_gen_movi_tl(t0, (size << 5) | reg);
3153 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3154 tcg_temp_free(t0);
3155 gen_update_nip(ctx, ctx->nip-4);
3156 ctx->exception = POWERPC_EXCP_BRANCH;
3157 gen_exception(ctx, POWERPC_EXCP_STCX);
3158 ctx->exception = save_exception;
3159 }
3160 #endif
3161
3162 /* stwcx. */
3163 static void gen_stwcx_(DisasContext *ctx)
3164 {
3165 TCGv t0;
3166 gen_set_access_type(ctx, ACCESS_RES);
3167 t0 = tcg_temp_local_new();
3168 gen_addr_reg_index(ctx, t0);
3169 gen_check_align(ctx, t0, 0x03);
3170 #if defined(CONFIG_USER_ONLY)
3171 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3172 #else
3173 {
3174 int l1;
3175
3176 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3177 l1 = gen_new_label();
3178 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3179 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3180 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3181 gen_set_label(l1);
3182 tcg_gen_movi_tl(cpu_reserve, -1);
3183 }
3184 #endif
3185 tcg_temp_free(t0);
3186 }
3187
3188 #if defined(TARGET_PPC64)
3189 /* ldarx */
3190 static void gen_ldarx(DisasContext *ctx)
3191 {
3192 TCGv t0;
3193 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3194 gen_set_access_type(ctx, ACCESS_RES);
3195 t0 = tcg_temp_local_new();
3196 gen_addr_reg_index(ctx, t0);
3197 gen_check_align(ctx, t0, 0x07);
3198 gen_qemu_ld64(ctx, gpr, t0);
3199 tcg_gen_mov_tl(cpu_reserve, t0);
3200 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3201 tcg_temp_free(t0);
3202 }
3203
3204 /* stdcx. */
3205 static void gen_stdcx_(DisasContext *ctx)
3206 {
3207 TCGv t0;
3208 gen_set_access_type(ctx, ACCESS_RES);
3209 t0 = tcg_temp_local_new();
3210 gen_addr_reg_index(ctx, t0);
3211 gen_check_align(ctx, t0, 0x07);
3212 #if defined(CONFIG_USER_ONLY)
3213 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3214 #else
3215 {
3216 int l1;
3217 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3218 l1 = gen_new_label();
3219 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3220 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3221 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3222 gen_set_label(l1);
3223 tcg_gen_movi_tl(cpu_reserve, -1);
3224 }
3225 #endif
3226 tcg_temp_free(t0);
3227 }
3228 #endif /* defined(TARGET_PPC64) */
3229
3230 /* sync */
3231 static void gen_sync(DisasContext *ctx)
3232 {
3233 }
3234
3235 /* wait */
3236 static void gen_wait(DisasContext *ctx)
3237 {
3238 TCGv_i32 t0 = tcg_temp_new_i32();
3239 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
3240 tcg_temp_free_i32(t0);
3241 /* Stop translation, as the CPU is supposed to sleep from now */
3242 gen_exception_err(ctx, EXCP_HLT, 1);
3243 }
3244
3245 /*** Floating-point load ***/
3246 #define GEN_LDF(name, ldop, opc, type) \
3247 static void glue(gen_, name)(DisasContext *ctx) \
3248 { \
3249 TCGv EA; \
3250 if (unlikely(!ctx->fpu_enabled)) { \
3251 gen_exception(ctx, POWERPC_EXCP_FPU); \
3252 return; \
3253 } \
3254 gen_set_access_type(ctx, ACCESS_FLOAT); \
3255 EA = tcg_temp_new(); \
3256 gen_addr_imm_index(ctx, EA, 0); \
3257 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3258 tcg_temp_free(EA); \
3259 }
3260
3261 #define GEN_LDUF(name, ldop, opc, type) \
3262 static void glue(gen_, name##u)(DisasContext *ctx) \
3263 { \
3264 TCGv EA; \
3265 if (unlikely(!ctx->fpu_enabled)) { \
3266 gen_exception(ctx, POWERPC_EXCP_FPU); \
3267 return; \
3268 } \
3269 if (unlikely(rA(ctx->opcode) == 0)) { \
3270 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3271 return; \
3272 } \
3273 gen_set_access_type(ctx, ACCESS_FLOAT); \
3274 EA = tcg_temp_new(); \
3275 gen_addr_imm_index(ctx, EA, 0); \
3276 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3277 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3278 tcg_temp_free(EA); \
3279 }
3280
3281 #define GEN_LDUXF(name, ldop, opc, type) \
3282 static void glue(gen_, name##ux)(DisasContext *ctx) \
3283 { \
3284 TCGv EA; \
3285 if (unlikely(!ctx->fpu_enabled)) { \
3286 gen_exception(ctx, POWERPC_EXCP_FPU); \
3287 return; \
3288 } \
3289 if (unlikely(rA(ctx->opcode) == 0)) { \
3290 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3291 return; \
3292 } \
3293 gen_set_access_type(ctx, ACCESS_FLOAT); \
3294 EA = tcg_temp_new(); \
3295 gen_addr_reg_index(ctx, EA); \
3296 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3297 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3298 tcg_temp_free(EA); \
3299 }
3300
3301 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3302 static void glue(gen_, name##x)(DisasContext *ctx) \
3303 { \
3304 TCGv EA; \
3305 if (unlikely(!ctx->fpu_enabled)) { \
3306 gen_exception(ctx, POWERPC_EXCP_FPU); \
3307 return; \
3308 } \
3309 gen_set_access_type(ctx, ACCESS_FLOAT); \
3310 EA = tcg_temp_new(); \
3311 gen_addr_reg_index(ctx, EA); \
3312 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3313 tcg_temp_free(EA); \
3314 }
3315
3316 #define GEN_LDFS(name, ldop, op, type) \
3317 GEN_LDF(name, ldop, op | 0x20, type); \
3318 GEN_LDUF(name, ldop, op | 0x21, type); \
3319 GEN_LDUXF(name, ldop, op | 0x01, type); \
3320 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3321
3322 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3323 {
3324 TCGv t0 = tcg_temp_new();
3325 TCGv_i32 t1 = tcg_temp_new_i32();
3326 gen_qemu_ld32u(ctx, t0, arg2);
3327 tcg_gen_trunc_tl_i32(t1, t0);
3328 tcg_temp_free(t0);
3329 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3330 tcg_temp_free_i32(t1);
3331 }
3332
3333 /* lfd lfdu lfdux lfdx */
3334 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3335 /* lfs lfsu lfsux lfsx */
3336 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3337
3338 /*** Floating-point store ***/
3339 #define GEN_STF(name, stop, opc, type) \
3340 static void glue(gen_, name)(DisasContext *ctx) \
3341 { \
3342 TCGv EA; \
3343 if (unlikely(!ctx->fpu_enabled)) { \
3344 gen_exception(ctx, POWERPC_EXCP_FPU); \
3345 return; \
3346 } \
3347 gen_set_access_type(ctx, ACCESS_FLOAT); \
3348 EA = tcg_temp_new(); \
3349 gen_addr_imm_index(ctx, EA, 0); \
3350 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3351 tcg_temp_free(EA); \
3352 }
3353
3354 #define GEN_STUF(name, stop, opc, type) \
3355 static void glue(gen_, name##u)(DisasContext *ctx) \
3356 { \
3357 TCGv EA; \
3358 if (unlikely(!ctx->fpu_enabled)) { \
3359 gen_exception(ctx, POWERPC_EXCP_FPU); \
3360 return; \
3361 } \
3362 if (unlikely(rA(ctx->opcode) == 0)) { \
3363 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3364 return; \
3365 } \
3366 gen_set_access_type(ctx, ACCESS_FLOAT); \
3367 EA = tcg_temp_new(); \
3368 gen_addr_imm_index(ctx, EA, 0); \
3369 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3370 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3371 tcg_temp_free(EA); \
3372 }
3373
3374 #define GEN_STUXF(name, stop, opc, type) \
3375 static void glue(gen_, name##ux)(DisasContext *ctx) \
3376 { \
3377 TCGv EA; \
3378 if (unlikely(!ctx->fpu_enabled)) { \
3379 gen_exception(ctx, POWERPC_EXCP_FPU); \
3380 return; \
3381 } \
3382 if (unlikely(rA(ctx->opcode) == 0)) { \
3383 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3384 return; \
3385 } \
3386 gen_set_access_type(ctx, ACCESS_FLOAT); \
3387 EA = tcg_temp_new(); \
3388 gen_addr_reg_index(ctx, EA); \
3389 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3390 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3391 tcg_temp_free(EA); \
3392 }
3393
3394 #define GEN_STXF(name, stop, opc2, opc3, type) \
3395 static void glue(gen_, name##x)(DisasContext *ctx) \
3396 { \
3397 TCGv EA; \
3398 if (unlikely(!ctx->fpu_enabled)) { \
3399 gen_exception(ctx, POWERPC_EXCP_FPU); \
3400 return; \
3401 } \
3402 gen_set_access_type(ctx, ACCESS_FLOAT); \
3403 EA = tcg_temp_new(); \
3404 gen_addr_reg_index(ctx, EA); \
3405 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3406 tcg_temp_free(EA); \
3407 }
3408
3409 #define GEN_STFS(name, stop, op, type) \
3410 GEN_STF(name, stop, op | 0x20, type); \
3411 GEN_STUF(name, stop, op | 0x21, type); \
3412 GEN_STUXF(name, stop, op | 0x01, type); \
3413 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3414
3415 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3416 {
3417 TCGv_i32 t0 = tcg_temp_new_i32();
3418 TCGv t1 = tcg_temp_new();
3419 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3420 tcg_gen_extu_i32_tl(t1, t0);
3421 tcg_temp_free_i32(t0);
3422 gen_qemu_st32(ctx, t1, arg2);
3423 tcg_temp_free(t1);
3424 }
3425
3426 /* stfd stfdu stfdux stfdx */
3427 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3428 /* stfs stfsu stfsux stfsx */
3429 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3430
3431 /* Optional: */
3432 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3433 {
3434 TCGv t0 = tcg_temp_new();
3435 tcg_gen_trunc_i64_tl(t0, arg1),
3436 gen_qemu_st32(ctx, t0, arg2);
3437 tcg_temp_free(t0);
3438 }
3439 /* stfiwx */
3440 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3441
3442 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3443 {
3444 #if defined(TARGET_PPC64)
3445 if (ctx->has_cfar)
3446 tcg_gen_movi_tl(cpu_cfar, nip);
3447 #endif
3448 }
3449
3450 /*** Branch ***/
3451 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3452 {
3453 TranslationBlock *tb;
3454 tb = ctx->tb;
3455 #if defined(TARGET_PPC64)
3456 if (!ctx->sf_mode)
3457 dest = (uint32_t) dest;
3458 #endif
3459 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3460 likely(!ctx->singlestep_enabled)) {
3461 tcg_gen_goto_tb(n);
3462 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3463 tcg_gen_exit_tb((tcg_target_long)tb + n);
3464 } else {
3465 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3466 if (unlikely(ctx->singlestep_enabled)) {
3467 if ((ctx->singlestep_enabled &
3468 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3469 (ctx->exception == POWERPC_EXCP_BRANCH ||
3470 ctx->exception == POWERPC_EXCP_TRACE)) {
3471 target_ulong tmp = ctx->nip;
3472 ctx->nip = dest;
3473 gen_exception(ctx, POWERPC_EXCP_TRACE);
3474 ctx->nip = tmp;
3475 }
3476 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3477 gen_debug_exception(ctx);
3478 }
3479 }
3480 tcg_gen_exit_tb(0);
3481 }
3482 }
3483
3484 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3485 {
3486 #if defined(TARGET_PPC64)
3487 if (ctx->sf_mode == 0)
3488 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3489 else
3490 #endif
3491 tcg_gen_movi_tl(cpu_lr, nip);
3492 }
3493
3494 /* b ba bl bla */
3495 static void gen_b(DisasContext *ctx)
3496 {
3497 target_ulong li, target;
3498
3499 ctx->exception = POWERPC_EXCP_BRANCH;
3500 /* sign extend LI */
3501 #if defined(TARGET_PPC64)
3502 if (ctx->sf_mode)
3503 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3504 else
3505 #endif
3506 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3507 if (likely(AA(ctx->opcode) == 0))
3508 target = ctx->nip + li - 4;
3509 else
3510 target = li;
3511 if (LK(ctx->opcode))
3512 gen_setlr(ctx, ctx->nip);
3513 gen_update_cfar(ctx, ctx->nip);
3514 gen_goto_tb(ctx, 0, target);
3515 }
3516
3517 #define BCOND_IM 0
3518 #define BCOND_LR 1
3519 #define BCOND_CTR 2
3520
3521 static inline void gen_bcond(DisasContext *ctx, int type)
3522 {
3523 uint32_t bo = BO(ctx->opcode);
3524 int l1;
3525 TCGv target;
3526
3527 ctx->exception = POWERPC_EXCP_BRANCH;
3528 if (type == BCOND_LR || type == BCOND_CTR) {
3529 target = tcg_temp_local_new();
3530 if (type == BCOND_CTR)
3531 tcg_gen_mov_tl(target, cpu_ctr);
3532 else
3533 tcg_gen_mov_tl(target, cpu_lr);
3534 } else {
3535 TCGV_UNUSED(target);
3536 }
3537 if (LK(ctx->opcode))
3538 gen_setlr(ctx, ctx->nip);
3539 l1 = gen_new_label();
3540 if ((bo & 0x4) == 0) {
3541 /* Decrement and test CTR */
3542 TCGv temp = tcg_temp_new();
3543 if (unlikely(type == BCOND_CTR)) {
3544 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3545 return;
3546 }
3547 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3548 #if defined(TARGET_PPC64)
3549 if (!ctx->sf_mode)
3550 tcg_gen_ext32u_tl(temp, cpu_ctr);
3551 else
3552 #endif
3553 tcg_gen_mov_tl(temp, cpu_ctr);
3554 if (bo & 0x2) {
3555 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3556 } else {
3557 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3558 }
3559 tcg_temp_free(temp);
3560 }
3561 if ((bo & 0x10) == 0) {
3562 /* Test CR */
3563 uint32_t bi = BI(ctx->opcode);
3564 uint32_t mask = 1 << (3 - (bi & 0x03));
3565 TCGv_i32 temp = tcg_temp_new_i32();
3566
3567 if (bo & 0x8) {
3568 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3569 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3570 } else {
3571 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3572 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3573 }
3574 tcg_temp_free_i32(temp);
3575 }
3576 gen_update_cfar(ctx, ctx->nip);
3577 if (type == BCOND_IM) {
3578 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3579 if (likely(AA(ctx->opcode) == 0)) {
3580 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3581 } else {
3582 gen_goto_tb(ctx, 0, li);
3583 }
3584 gen_set_label(l1);
3585 gen_goto_tb(ctx, 1, ctx->nip);
3586 } else {
3587 #if defined(TARGET_PPC64)
3588 if (!(ctx->sf_mode))
3589 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3590 else
3591 #endif
3592 tcg_gen_andi_tl(cpu_nip, target, ~3);
3593 tcg_gen_exit_tb(0);
3594 gen_set_label(l1);
3595 #if defined(TARGET_PPC64)
3596 if (!(ctx->sf_mode))
3597 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3598 else
3599 #endif
3600 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3601 tcg_gen_exit_tb(0);
3602 }
3603 }
3604
3605 static void gen_bc(DisasContext *ctx)
3606 {
3607 gen_bcond(ctx, BCOND_IM);
3608 }
3609
3610 static void gen_bcctr(DisasContext *ctx)
3611 {
3612 gen_bcond(ctx, BCOND_CTR);
3613 }
3614
3615 static void gen_bclr(DisasContext *ctx)
3616 {
3617 gen_bcond(ctx, BCOND_LR);
3618 }
3619
3620 /*** Condition register logical ***/
3621 #define GEN_CRLOGIC(name, tcg_op, opc) \
3622 static void glue(gen_, name)(DisasContext *ctx) \
3623 { \
3624 uint8_t bitmask; \
3625 int sh; \
3626 TCGv_i32 t0, t1; \
3627 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3628 t0 = tcg_temp_new_i32(); \
3629 if (sh > 0) \
3630 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3631 else if (sh < 0) \
3632 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3633 else \
3634 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3635 t1 = tcg_temp_new_i32(); \
3636 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3637 if (sh > 0) \
3638 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3639 else if (sh < 0) \
3640 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3641 else \
3642 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3643 tcg_op(t0, t0, t1); \
3644 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3645 tcg_gen_andi_i32(t0, t0, bitmask); \
3646 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3647 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3648 tcg_temp_free_i32(t0); \
3649 tcg_temp_free_i32(t1); \
3650 }
3651
3652 /* crand */
3653 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3654 /* crandc */
3655 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3656 /* creqv */
3657 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3658 /* crnand */
3659 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3660 /* crnor */
3661 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3662 /* cror */
3663 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3664 /* crorc */
3665 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3666 /* crxor */
3667 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3668
3669 /* mcrf */
3670 static void gen_mcrf(DisasContext *ctx)
3671 {
3672 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3673 }
3674
3675 /*** System linkage ***/
3676
3677 /* rfi (mem_idx only) */
3678 static void gen_rfi(DisasContext *ctx)
3679 {
3680 #if defined(CONFIG_USER_ONLY)
3681 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3682 #else
3683 /* Restore CPU state */
3684 if (unlikely(!ctx->mem_idx)) {
3685 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3686 return;
3687 }
3688 gen_update_cfar(ctx, ctx->nip);
3689 gen_helper_rfi(cpu_env);
3690 gen_sync_exception(ctx);
3691 #endif
3692 }
3693
3694 #if defined(TARGET_PPC64)
3695 static void gen_rfid(DisasContext *ctx)
3696 {
3697 #if defined(CONFIG_USER_ONLY)
3698 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3699 #else
3700 /* Restore CPU state */
3701 if (unlikely(!ctx->mem_idx)) {
3702 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3703 return;
3704 }
3705 gen_update_cfar(ctx, ctx->nip);
3706 gen_helper_rfid(cpu_env);
3707 gen_sync_exception(ctx);
3708 #endif
3709 }
3710
3711 static void gen_hrfid(DisasContext *ctx)
3712 {
3713 #if defined(CONFIG_USER_ONLY)
3714 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3715 #else
3716 /* Restore CPU state */
3717 if (unlikely(ctx->mem_idx <= 1)) {
3718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3719 return;
3720 }
3721 gen_helper_hrfid(cpu_env);
3722 gen_sync_exception(ctx);
3723 #endif
3724 }
3725 #endif
3726
3727 /* sc */
3728 #if defined(CONFIG_USER_ONLY)
3729 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3730 #else
3731 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3732 #endif
3733 static void gen_sc(DisasContext *ctx)
3734 {
3735 uint32_t lev;
3736
3737 lev = (ctx->opcode >> 5) & 0x7F;
3738 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3739 }
3740
3741 /*** Trap ***/
3742
3743 /* tw */
3744 static void gen_tw(DisasContext *ctx)
3745 {
3746 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3747 /* Update the nip since this might generate a trap exception */
3748 gen_update_nip(ctx, ctx->nip);
3749 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3750 t0);
3751 tcg_temp_free_i32(t0);
3752 }
3753
3754 /* twi */
3755 static void gen_twi(DisasContext *ctx)
3756 {
3757 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3758 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3759 /* Update the nip since this might generate a trap exception */
3760 gen_update_nip(ctx, ctx->nip);
3761 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3762 tcg_temp_free(t0);
3763 tcg_temp_free_i32(t1);
3764 }
3765
3766 #if defined(TARGET_PPC64)
3767 /* td */
3768 static void gen_td(DisasContext *ctx)
3769 {
3770 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3771 /* Update the nip since this might generate a trap exception */
3772 gen_update_nip(ctx, ctx->nip);
3773 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3774 t0);
3775 tcg_temp_free_i32(t0);
3776 }
3777
3778 /* tdi */
3779 static void gen_tdi(DisasContext *ctx)
3780 {
3781 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3782 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3783 /* Update the nip since this might generate a trap exception */
3784 gen_update_nip(ctx, ctx->nip);
3785 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3786 tcg_temp_free(t0);
3787 tcg_temp_free_i32(t1);
3788 }
3789 #endif
3790
3791 /*** Processor control ***/
3792
3793 static void gen_read_xer(TCGv dst)
3794 {
3795 TCGv t0 = tcg_temp_new();
3796 TCGv t1 = tcg_temp_new();
3797 TCGv t2 = tcg_temp_new();
3798 tcg_gen_mov_tl(dst, cpu_xer);
3799 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3800 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3801 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3802 tcg_gen_or_tl(t0, t0, t1);
3803 tcg_gen_or_tl(dst, dst, t2);
3804 tcg_gen_or_tl(dst, dst, t0);
3805 tcg_temp_free(t0);
3806 tcg_temp_free(t1);
3807 tcg_temp_free(t2);
3808 }
3809
3810 static void gen_write_xer(TCGv src)
3811 {
3812 tcg_gen_andi_tl(cpu_xer, src,
3813 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3814 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3815 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3816 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3817 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3818 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3819 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3820 }
3821
3822 /* mcrxr */
3823 static void gen_mcrxr(DisasContext *ctx)
3824 {
3825 TCGv_i32 t0 = tcg_temp_new_i32();
3826 TCGv_i32 t1 = tcg_temp_new_i32();
3827 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3828
3829 tcg_gen_trunc_tl_i32(t0, cpu_so);
3830 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3831 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3832 tcg_gen_shri_i32(t0, t0, 2);
3833 tcg_gen_shri_i32(t1, t1, 1);
3834 tcg_gen_or_i32(dst, dst, t0);
3835 tcg_gen_or_i32(dst, dst, t1);
3836 tcg_temp_free_i32(t0);
3837 tcg_temp_free_i32(t1);
3838
3839 tcg_gen_movi_tl(cpu_so, 0);
3840 tcg_gen_movi_tl(cpu_ov, 0);
3841 tcg_gen_movi_tl(cpu_ca, 0);
3842 }
3843
3844 /* mfcr mfocrf */
3845 static void gen_mfcr(DisasContext *ctx)
3846 {
3847 uint32_t crm, crn;
3848
3849 if (likely(ctx->opcode & 0x00100000)) {
3850 crm = CRM(ctx->opcode);
3851 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3852 crn = ctz32 (crm);
3853 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3854 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3855 cpu_gpr[rD(ctx->opcode)], crn * 4);
3856 }
3857 } else {
3858 TCGv_i32 t0 = tcg_temp_new_i32();
3859 tcg_gen_mov_i32(t0, cpu_crf[0]);
3860 tcg_gen_shli_i32(t0, t0, 4);
3861 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3862 tcg_gen_shli_i32(t0, t0, 4);
3863 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3864 tcg_gen_shli_i32(t0, t0, 4);
3865 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3866 tcg_gen_shli_i32(t0, t0, 4);
3867 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3868 tcg_gen_shli_i32(t0, t0, 4);
3869 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3870 tcg_gen_shli_i32(t0, t0, 4);
3871 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3872 tcg_gen_shli_i32(t0, t0, 4);
3873 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3874 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3875 tcg_temp_free_i32(t0);
3876 }
3877 }
3878
3879 /* mfmsr */
3880 static void gen_mfmsr(DisasContext *ctx)
3881 {
3882 #if defined(CONFIG_USER_ONLY)
3883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3884 #else
3885 if (unlikely(!ctx->mem_idx)) {
3886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3887 return;
3888 }
3889 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3890 #endif
3891 }
3892
3893 static void spr_noaccess(void *opaque, int gprn, int sprn)
3894 {
3895 #if 0
3896 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3897 printf("ERROR: try to access SPR %d !\n", sprn);
3898 #endif
3899 }
3900 #define SPR_NOACCESS (&spr_noaccess)
3901
3902 /* mfspr */
3903 static inline void gen_op_mfspr(DisasContext *ctx)
3904 {
3905 void (*read_cb)(void *opaque, int gprn, int sprn);
3906 uint32_t sprn = SPR(ctx->opcode);
3907
3908 #if !defined(CONFIG_USER_ONLY)
3909 if (ctx->mem_idx == 2)
3910 read_cb = ctx->spr_cb[sprn].hea_read;
3911 else if (ctx->mem_idx)
3912 read_cb = ctx->spr_cb[sprn].oea_read;
3913 else
3914 #endif
3915 read_cb = ctx->spr_cb[sprn].uea_read;
3916 if (likely(read_cb != NULL)) {
3917 if (likely(read_cb != SPR_NOACCESS)) {
3918 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3919 } else {
3920 /* Privilege exception */
3921 /* This is a hack to avoid warnings when running Linux:
3922 * this OS breaks the PowerPC virtualisation model,
3923 * allowing userland application to read the PVR
3924 */
3925 if (sprn != SPR_PVR) {
3926 qemu_log("Trying to read privileged spr %d %03x at "
3927 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3928 printf("Trying to read privileged spr %d %03x at "
3929 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3930 }
3931 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3932 }
3933 } else {
3934 /* Not defined */
3935 qemu_log("Trying to read invalid spr %d %03x at "
3936 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3937 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3938 sprn, sprn, ctx->nip);
3939 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3940 }
3941 }
3942
3943 static void gen_mfspr(DisasContext *ctx)
3944 {
3945 gen_op_mfspr(ctx);
3946 }
3947
3948 /* mftb */
3949 static void gen_mftb(DisasContext *ctx)
3950 {
3951 gen_op_mfspr(ctx);
3952 }
3953
3954 /* mtcrf mtocrf*/
3955 static void gen_mtcrf(DisasContext *ctx)
3956 {
3957 uint32_t crm, crn;
3958
3959 crm = CRM(ctx->opcode);
3960 if (likely((ctx->opcode & 0x00100000))) {
3961 if (crm && ((crm & (crm - 1)) == 0)) {
3962 TCGv_i32 temp = tcg_temp_new_i32();
3963 crn = ctz32 (crm);
3964 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3965 tcg_gen_shri_i32(temp, temp, crn * 4);
3966 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3967 tcg_temp_free_i32(temp);
3968 }
3969 } else {
3970 TCGv_i32 temp = tcg_temp_new_i32();
3971 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3972 for (crn = 0 ; crn < 8 ; crn++) {
3973 if (crm & (1 << crn)) {
3974 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3975 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3976 }
3977 }
3978 tcg_temp_free_i32(temp);
3979 }
3980 }
3981
3982 /* mtmsr */
3983 #if defined(TARGET_PPC64)
3984 static void gen_mtmsrd(DisasContext *ctx)
3985 {
3986 #if defined(CONFIG_USER_ONLY)
3987 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3988 #else
3989 if (unlikely(!ctx->mem_idx)) {
3990 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3991 return;
3992 }
3993 if (ctx->opcode & 0x00010000) {
3994 /* Special form that does not need any synchronisation */
3995 TCGv t0 = tcg_temp_new();
3996 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3997 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3998 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3999 tcg_temp_free(t0);
4000 } else {
4001 /* XXX: we need to update nip before the store
4002 * if we enter power saving mode, we will exit the loop
4003 * directly from ppc_store_msr
4004 */
4005 gen_update_nip(ctx, ctx->nip);
4006 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4007 /* Must stop the translation as machine state (may have) changed */
4008 /* Note that mtmsr is not always defined as context-synchronizing */
4009 gen_stop_exception(ctx);
4010 }
4011 #endif
4012 }
4013 #endif
4014
4015 static void gen_mtmsr(DisasContext *ctx)
4016 {
4017 #if defined(CONFIG_USER_ONLY)
4018 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4019 #else
4020 if (unlikely(!ctx->mem_idx)) {
4021 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4022 return;
4023 }
4024 if (ctx->opcode & 0x00010000) {
4025 /* Special form that does not need any synchronisation */
4026 TCGv t0 = tcg_temp_new();
4027 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4028 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4029 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4030 tcg_temp_free(t0);
4031 } else {
4032 TCGv msr = tcg_temp_new();
4033
4034 /* XXX: we need to update nip before the store
4035 * if we enter power saving mode, we will exit the loop
4036 * directly from ppc_store_msr
4037 */
4038 gen_update_nip(ctx, ctx->nip);
4039 #if defined(TARGET_PPC64)
4040 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4041 #else
4042 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4043 #endif
4044 gen_helper_store_msr(cpu_env, msr);
4045 /* Must stop the translation as machine state (may have) changed */
4046 /* Note that mtmsr is not always defined as context-synchronizing */
4047 gen_stop_exception(ctx);
4048 }
4049 #endif
4050 }
4051
4052 /* mtspr */
4053 static void gen_mtspr(DisasContext *ctx)
4054 {
4055 void (*write_cb)(void *opaque, int sprn, int gprn);
4056 uint32_t sprn = SPR(ctx->opcode);
4057
4058 #if !defined(CONFIG_USER_ONLY)
4059 if (ctx->mem_idx == 2)
4060 write_cb = ctx->spr_cb[sprn].hea_write;
4061 else if (ctx->mem_idx)
4062 write_cb = ctx->spr_cb[sprn].oea_write;
4063 else
4064 #endif
4065 write_cb = ctx->spr_cb[sprn].uea_write;
4066 if (likely(write_cb != NULL)) {
4067 if (likely(write_cb != SPR_NOACCESS)) {
4068 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4069 } else {
4070 /* Privilege exception */
4071 qemu_log("Trying to write privileged spr %d %03x at "
4072 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4073 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
4074 "\n", sprn, sprn, ctx->nip);
4075 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4076 }
4077 } else {
4078 /* Not defined */
4079 qemu_log("Trying to write invalid spr %d %03x at "
4080 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4081 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
4082 sprn, sprn, ctx->nip);
4083 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4084 }
4085 }
4086
4087 /*** Cache management ***/
4088
4089 /* dcbf */
4090 static void gen_dcbf(DisasContext *ctx)
4091 {
4092 /* XXX: specification says this is treated as a load by the MMU */
4093 TCGv t0;
4094 gen_set_access_type(ctx, ACCESS_CACHE);
4095 t0 = tcg_temp_new();
4096 gen_addr_reg_index(ctx, t0);
4097 gen_qemu_ld8u(ctx, t0, t0);
4098 tcg_temp_free(t0);
4099 }
4100
4101 /* dcbi (Supervisor only) */
4102 static void gen_dcbi(DisasContext *ctx)
4103 {
4104 #if defined(CONFIG_USER_ONLY)
4105 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4106 #else
4107 TCGv EA, val;
4108 if (unlikely(!ctx->mem_idx)) {
4109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4110 return;
4111 }
4112 EA = tcg_temp_new();
4113 gen_set_access_type(ctx, ACCESS_CACHE);
4114 gen_addr_reg_index(ctx, EA);
4115 val = tcg_temp_new();
4116 /* XXX: specification says this should be treated as a store by the MMU */
4117 gen_qemu_ld8u(ctx, val, EA);
4118 gen_qemu_st8(ctx, val, EA);
4119 tcg_temp_free(val);
4120 tcg_temp_free(EA);
4121 #endif
4122 }
4123
4124 /* dcdst */
4125 static void gen_dcbst(DisasContext *ctx)
4126 {
4127 /* XXX: specification say this is treated as a load by the MMU */
4128 TCGv t0;
4129 gen_set_access_type(ctx, ACCESS_CACHE);
4130 t0 = tcg_temp_new();
4131 gen_addr_reg_index(ctx, t0);
4132 gen_qemu_ld8u(ctx, t0, t0);
4133 tcg_temp_free(t0);
4134 }
4135
4136 /* dcbt */
4137 static void gen_dcbt(DisasContext *ctx)
4138 {
4139 /* interpreted as no-op */
4140 /* XXX: specification say this is treated as a load by the MMU
4141 * but does not generate any exception
4142 */
4143 }
4144
4145 /* dcbtst */
4146 static void gen_dcbtst(DisasContext *ctx)
4147 {
4148 /* interpreted as no-op */
4149 /* XXX: specification say this is treated as a load by the MMU
4150 * but does not generate any exception
4151 */
4152 }
4153
4154 /* dcbz */
4155 static void gen_dcbz(DisasContext *ctx)
4156 {
4157 TCGv tcgv_addr;
4158 TCGv_i32 tcgv_is_dcbzl;
4159 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4160
4161 gen_set_access_type(ctx, ACCESS_CACHE);
4162 /* NIP cannot be restored if the memory exception comes from an helper */
4163 gen_update_nip(ctx, ctx->nip - 4);
4164 tcgv_addr = tcg_temp_new();
4165 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4166
4167 gen_addr_reg_index(ctx, tcgv_addr);
4168 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4169
4170 tcg_temp_free(tcgv_addr);
4171 tcg_temp_free_i32(tcgv_is_dcbzl);
4172 }
4173
4174 /* dst / dstt */
4175 static void gen_dst(DisasContext *ctx)
4176 {
4177 if (rA(ctx->opcode) == 0) {
4178 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4179 } else {
4180 /* interpreted as no-op */
4181 }
4182 }
4183
4184 /* dstst /dststt */
4185 static void gen_dstst(DisasContext *ctx)
4186 {
4187 if (rA(ctx->opcode) == 0) {
4188 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4189 } else {
4190 /* interpreted as no-op */
4191 }
4192
4193 }
4194
4195 /* dss / dssall */
4196 static void gen_dss(DisasContext *ctx)
4197 {
4198 /* interpreted as no-op */
4199 }
4200
4201 /* icbi */
4202 static void gen_icbi(DisasContext *ctx)
4203 {
4204 TCGv t0;
4205 gen_set_access_type(ctx, ACCESS_CACHE);
4206 /* NIP cannot be restored if the memory exception comes from an helper */
4207 gen_update_nip(ctx, ctx->nip - 4);
4208 t0 = tcg_temp_new();
4209 gen_addr_reg_index(ctx, t0);
4210 gen_helper_icbi(cpu_env, t0);
4211 tcg_temp_free(t0);
4212 }
4213
4214 /* Optional: */
4215 /* dcba */
4216 static void gen_dcba(DisasContext *ctx)
4217 {
4218 /* interpreted as no-op */
4219 /* XXX: specification say this is treated as a store by the MMU
4220 * but does not generate any exception
4221 */
4222 }
4223
4224 /*** Segment register manipulation ***/
4225 /* Supervisor only: */
4226
4227 /* mfsr */
4228 static void gen_mfsr(DisasContext *ctx)
4229 {
4230 #if defined(CONFIG_USER_ONLY)
4231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4232 #else
4233 TCGv t0;
4234 if (unlikely(!ctx->mem_idx)) {
4235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4236 return;
4237 }
4238 t0 = tcg_const_tl(SR(ctx->opcode));
4239 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4240 tcg_temp_free(t0);
4241 #endif
4242 }
4243
4244 /* mfsrin */
4245 static void gen_mfsrin(DisasContext *ctx)
4246 {
4247 #if defined(CONFIG_USER_ONLY)
4248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4249 #else
4250 TCGv t0;
4251 if (unlikely(!ctx->mem_idx)) {
4252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4253 return;
4254 }
4255 t0 = tcg_temp_new();
4256 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4257 tcg_gen_andi_tl(t0, t0, 0xF);
4258 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4259 tcg_temp_free(t0);
4260 #endif
4261 }
4262
4263 /* mtsr */
4264 static void gen_mtsr(DisasContext *ctx)
4265 {
4266 #if defined(CONFIG_USER_ONLY)
4267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4268 #else
4269 TCGv t0;
4270 if (unlikely(!ctx->mem_idx)) {
4271 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4272 return;
4273 }
4274 t0 = tcg_const_tl(SR(ctx->opcode));
4275 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4276 tcg_temp_free(t0);
4277 #endif
4278 }
4279
4280 /* mtsrin */
4281 static void gen_mtsrin(DisasContext *ctx)
4282 {
4283 #if defined(CONFIG_USER_ONLY)
4284 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4285 #else
4286 TCGv t0;
4287 if (unlikely(!ctx->mem_idx)) {
4288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4289 return;
4290 }
4291 t0 = tcg_temp_new();
4292 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4293 tcg_gen_andi_tl(t0, t0, 0xF);
4294 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4295 tcg_temp_free(t0);
4296 #endif
4297 }
4298
4299 #if defined(TARGET_PPC64)
4300 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4301
4302 /* mfsr */
4303 static void gen_mfsr_64b(DisasContext *ctx)
4304 {
4305 #if defined(CONFIG_USER_ONLY)
4306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4307 #else
4308 TCGv t0;
4309 if (unlikely(!ctx->mem_idx)) {
4310 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4311 return;
4312 }
4313 t0 = tcg_const_tl(SR(ctx->opcode));
4314 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4315 tcg_temp_free(t0);
4316 #endif
4317 }
4318
4319 /* mfsrin */
4320 static void gen_mfsrin_64b(DisasContext *ctx)
4321 {
4322 #if defined(CONFIG_USER_ONLY)
4323 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4324 #else
4325 TCGv t0;
4326 if (unlikely(!ctx->mem_idx)) {
4327 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4328 return;
4329 }
4330 t0 = tcg_temp_new();
4331 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4332 tcg_gen_andi_tl(t0, t0, 0xF);
4333 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4334 tcg_temp_free(t0);
4335 #endif
4336 }
4337
4338 /* mtsr */
4339 static void gen_mtsr_64b(DisasContext *ctx)
4340 {
4341 #if defined(CONFIG_USER_ONLY)
4342 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4343 #else
4344 TCGv t0;
4345 if (unlikely(!ctx->mem_idx)) {
4346 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4347 return;
4348 }
4349 t0 = tcg_const_tl(SR(ctx->opcode));
4350 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4351 tcg_temp_free(t0);
4352 #endif
4353 }
4354
4355 /* mtsrin */
4356 static void gen_mtsrin_64b(DisasContext *ctx)
4357 {
4358 #if defined(CONFIG_USER_ONLY)
4359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4360 #else
4361 TCGv t0;
4362 if (unlikely(!ctx->mem_idx)) {
4363 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4364 return;
4365 }
4366 t0 = tcg_temp_new();
4367 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4368 tcg_gen_andi_tl(t0, t0, 0xF);
4369 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4370 tcg_temp_free(t0);
4371 #endif
4372 }
4373
4374 /* slbmte */
4375 static void gen_slbmte(DisasContext *ctx)
4376 {
4377 #if defined(CONFIG_USER_ONLY)
4378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4379 #else
4380 if (unlikely(!ctx->mem_idx)) {
4381 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4382 return;
4383 }
4384 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4385 cpu_gpr[rS(ctx->opcode)]);
4386 #endif
4387 }
4388
4389 static void gen_slbmfee(DisasContext *ctx)
4390 {
4391 #if defined(CONFIG_USER_ONLY)
4392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4393 #else
4394 if (unlikely(!ctx->mem_idx)) {
4395 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4396 return;
4397 }
4398 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4399 cpu_gpr[rB(ctx->opcode)]);
4400 #endif
4401 }
4402
4403 static void gen_slbmfev(DisasContext *ctx)
4404 {
4405 #if defined(CONFIG_USER_ONLY)
4406 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4407 #else
4408 if (unlikely(!ctx->mem_idx)) {
4409 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4410 return;
4411 }
4412 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4413 cpu_gpr[rB(ctx->opcode)]);
4414 #endif
4415 }
4416 #endif /* defined(TARGET_PPC64) */
4417
4418 /*** Lookaside buffer management ***/
4419 /* Optional & mem_idx only: */
4420
4421 /* tlbia */
4422 static void gen_tlbia(DisasContext *ctx)
4423 {
4424 #if defined(CONFIG_USER_ONLY)
4425 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4426 #else
4427 if (unlikely(!ctx->mem_idx)) {
4428 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4429 return;
4430 }
4431 gen_helper_tlbia(cpu_env);
4432 #endif
4433 }
4434
4435 /* tlbiel */
4436 static void gen_tlbiel(DisasContext *ctx)
4437 {
4438 #if defined(CONFIG_USER_ONLY)
4439 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4440 #else
4441 if (unlikely(!ctx->mem_idx)) {
4442 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4443 return;
4444 }
4445 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4446 #endif
4447 }
4448
4449 /* tlbie */
4450 static void gen_tlbie(DisasContext *ctx)
4451 {
4452 #if defined(CONFIG_USER_ONLY)
4453 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4454 #else
4455 if (unlikely(!ctx->mem_idx)) {
4456 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4457 return;
4458 }
4459 #if defined(TARGET_PPC64)
4460 if (!ctx->sf_mode) {
4461 TCGv t0 = tcg_temp_new();
4462 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4463 gen_helper_tlbie(cpu_env, t0);
4464 tcg_temp_free(t0);
4465 } else
4466 #endif
4467 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4468 #endif
4469 }
4470
4471 /* tlbsync */
4472 static void gen_tlbsync(DisasContext *ctx)
4473 {
4474 #if defined(CONFIG_USER_ONLY)
4475 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4476 #else
4477 if (unlikely(!ctx->mem_idx)) {
4478 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4479 return;
4480 }
4481 /* This has no effect: it should ensure that all previous
4482 * tlbie have completed
4483 */
4484 gen_stop_exception(ctx);
4485 #endif
4486 }
4487
4488 #if defined(TARGET_PPC64)
4489 /* slbia */
4490 static void gen_slbia(DisasContext *ctx)
4491 {
4492 #if defined(CONFIG_USER_ONLY)
4493 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4494 #else
4495 if (unlikely(!ctx->mem_idx)) {
4496 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4497 return;
4498 }
4499 gen_helper_slbia(cpu_env);
4500 #endif
4501 }
4502
4503 /* slbie */
4504 static void gen_slbie(DisasContext *ctx)
4505 {
4506 #if defined(CONFIG_USER_ONLY)
4507 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4508 #else
4509 if (unlikely(!ctx->mem_idx)) {
4510 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4511 return;
4512 }
4513 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4514 #endif
4515 }
4516 #endif
4517
4518 /*** External control ***/
4519 /* Optional: */
4520
4521 /* eciwx */
4522 static void gen_eciwx(DisasContext *ctx)
4523 {
4524 TCGv t0;
4525 /* Should check EAR[E] ! */
4526 gen_set_access_type(ctx, ACCESS_EXT);
4527 t0 = tcg_temp_new();
4528 gen_addr_reg_index(ctx, t0);
4529 gen_check_align(ctx, t0, 0x03);
4530 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4531 tcg_temp_free(t0);
4532 }
4533
4534 /* ecowx */
4535 static void gen_ecowx(DisasContext *ctx)
4536 {
4537 TCGv t0;
4538 /* Should check EAR[E] ! */
4539 gen_set_access_type(ctx, ACCESS_EXT);
4540 t0 = tcg_temp_new();
4541 gen_addr_reg_index(ctx, t0);
4542 gen_check_align(ctx, t0, 0x03);
4543 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4544 tcg_temp_free(t0);
4545 }
4546
4547 /* PowerPC 601 specific instructions */
4548
4549 /* abs - abs. */
4550 static void gen_abs(DisasContext *ctx)
4551 {
4552 int l1 = gen_new_label();
4553 int l2 = gen_new_label();
4554 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4555 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4556 tcg_gen_br(l2);
4557 gen_set_label(l1);
4558 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4559 gen_set_label(l2);
4560 if (unlikely(Rc(ctx->opcode) != 0))
4561 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4562 }
4563
4564 /* abso - abso. */
4565 static void gen_abso(DisasContext *ctx)
4566 {
4567 int l1 = gen_new_label();
4568 int l2 = gen_new_label();
4569 int l3 = gen_new_label();
4570 /* Start with XER OV disabled, the most likely case */
4571 tcg_gen_movi_tl(cpu_ov, 0);
4572 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4573 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4574 tcg_gen_movi_tl(cpu_ov, 1);
4575 tcg_gen_movi_tl(cpu_so, 1);
4576 tcg_gen_br(l2);
4577 gen_set_label(l1);
4578 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4579 tcg_gen_br(l3);
4580 gen_set_label(l2);
4581 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4582 gen_set_label(l3);
4583 if (unlikely(Rc(ctx->opcode) != 0))
4584 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4585 }
4586
4587 /* clcs */
4588 static void gen_clcs(DisasContext *ctx)
4589 {
4590 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4591 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4592 tcg_temp_free_i32(t0);
4593 /* Rc=1 sets CR0 to an undefined state */
4594 }
4595
4596 /* div - div. */
4597 static void gen_div(DisasContext *ctx)
4598 {
4599 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4600 cpu_gpr[rB(ctx->opcode)]);
4601 if (unlikely(Rc(ctx->opcode) != 0))
4602 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4603 }
4604
4605 /* divo - divo. */
4606 static void gen_divo(DisasContext *ctx)
4607 {
4608 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4609 cpu_gpr[rB(ctx->opcode)]);
4610 if (unlikely(Rc(ctx->opcode) != 0))
4611 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4612 }
4613
4614 /* divs - divs. */
4615 static void gen_divs(DisasContext *ctx)
4616 {
4617 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4618 cpu_gpr[rB(ctx->opcode)]);
4619 if (unlikely(Rc(ctx->opcode) != 0))
4620 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4621 }
4622
4623 /* divso - divso. */
4624 static void gen_divso(DisasContext *ctx)
4625 {
4626 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4627 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4628 if (unlikely(Rc(ctx->opcode) != 0))
4629 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4630 }
4631
4632 /* doz - doz. */
4633 static void gen_doz(DisasContext *ctx)
4634 {
4635 int l1 = gen_new_label();
4636 int l2 = gen_new_label();
4637 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4638 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4639 tcg_gen_br(l2);
4640 gen_set_label(l1);
4641 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4642 gen_set_label(l2);
4643 if (unlikely(Rc(ctx->opcode) != 0))
4644 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4645 }
4646
4647 /* dozo - dozo. */
4648 static void gen_dozo(DisasContext *ctx)
4649 {
4650 int l1 = gen_new_label();
4651 int l2 = gen_new_label();
4652 TCGv t0 = tcg_temp_new();
4653 TCGv t1 = tcg_temp_new();
4654 TCGv t2 = tcg_temp_new();
4655 /* Start with XER OV disabled, the most likely case */
4656 tcg_gen_movi_tl(cpu_ov, 0);
4657 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4658 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4659 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4660 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4661 tcg_gen_andc_tl(t1, t1, t2);
4662 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4663 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4664 tcg_gen_movi_tl(cpu_ov, 1);
4665 tcg_gen_movi_tl(cpu_so, 1);
4666 tcg_gen_br(l2);
4667 gen_set_label(l1);
4668 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4669 gen_set_label(l2);
4670 tcg_temp_free(t0);
4671 tcg_temp_free(t1);
4672 tcg_temp_free(t2);
4673 if (unlikely(Rc(ctx->opcode) != 0))
4674 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4675 }
4676
4677 /* dozi */
4678 static void gen_dozi(DisasContext *ctx)
4679 {
4680 target_long simm = SIMM(ctx->opcode);
4681 int l1 = gen_new_label();
4682 int l2 = gen_new_label();
4683 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4684 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4685 tcg_gen_br(l2);
4686 gen_set_label(l1);
4687 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4688 gen_set_label(l2);
4689 if (unlikely(Rc(ctx->opcode) != 0))
4690 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4691 }
4692
4693 /* lscbx - lscbx. */
4694 static void gen_lscbx(DisasContext *ctx)
4695 {
4696 TCGv t0 = tcg_temp_new();
4697 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4698 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4699 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4700
4701 gen_addr_reg_index(ctx, t0);
4702 /* NIP cannot be restored if the memory exception comes from an helper */
4703 gen_update_nip(ctx, ctx->nip - 4);
4704 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4705 tcg_temp_free_i32(t1);
4706 tcg_temp_free_i32(t2);
4707 tcg_temp_free_i32(t3);
4708 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4709 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4710 if (unlikely(Rc(ctx->opcode) != 0))
4711 gen_set_Rc0(ctx, t0);
4712 tcg_temp_free(t0);
4713 }
4714
4715 /* maskg - maskg. */
4716 static void gen_maskg(DisasContext *ctx)
4717 {
4718 int l1 = gen_new_label();
4719 TCGv t0 = tcg_temp_new();
4720 TCGv t1 = tcg_temp_new();
4721 TCGv t2 = tcg_temp_new();
4722 TCGv t3 = tcg_temp_new();
4723 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4724 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4725 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4726 tcg_gen_addi_tl(t2, t0, 1);
4727 tcg_gen_shr_tl(t2, t3, t2);
4728 tcg_gen_shr_tl(t3, t3, t1);
4729 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4730 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4731 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4732 gen_set_label(l1);
4733 tcg_temp_free(t0);
4734 tcg_temp_free(t1);
4735 tcg_temp_free(t2);
4736 tcg_temp_free(t3);
4737 if (unlikely(Rc(ctx->opcode) != 0))
4738 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4739 }
4740
4741 /* maskir - maskir. */
4742 static void gen_maskir(DisasContext *ctx)
4743 {
4744 TCGv t0 = tcg_temp_new();
4745 TCGv t1 = tcg_temp_new();
4746 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4747 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4748 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4749 tcg_temp_free(t0);
4750 tcg_temp_free(t1);
4751 if (unlikely(Rc(ctx->opcode) != 0))
4752 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4753 }
4754
4755 /* mul - mul. */
4756 static void gen_mul(DisasContext *ctx)
4757 {
4758 TCGv_i64 t0 = tcg_temp_new_i64();
4759 TCGv_i64 t1 = tcg_temp_new_i64();
4760 TCGv t2 = tcg_temp_new();
4761 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4762 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4763 tcg_gen_mul_i64(t0, t0, t1);
4764 tcg_gen_trunc_i64_tl(t2, t0);
4765 gen_store_spr(SPR_MQ, t2);
4766 tcg_gen_shri_i64(t1, t0, 32);
4767 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4768 tcg_temp_free_i64(t0);
4769 tcg_temp_free_i64(t1);
4770 tcg_temp_free(t2);
4771 if (unlikely(Rc(ctx->opcode) != 0))
4772 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4773 }
4774
4775 /* mulo - mulo. */
4776 static void gen_mulo(DisasContext *ctx)
4777 {
4778 int l1 = gen_new_label();
4779 TCGv_i64 t0 = tcg_temp_new_i64();
4780 TCGv_i64 t1 = tcg_temp_new_i64();
4781 TCGv t2 = tcg_temp_new();
4782 /* Start with XER OV disabled, the most likely case */
4783 tcg_gen_movi_tl(cpu_ov, 0);
4784 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4785 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4786 tcg_gen_mul_i64(t0, t0, t1);
4787 tcg_gen_trunc_i64_tl(t2, t0);
4788 gen_store_spr(SPR_MQ, t2);
4789 tcg_gen_shri_i64(t1, t0, 32);
4790 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4791 tcg_gen_ext32s_i64(t1, t0);
4792 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4793 tcg_gen_movi_tl(cpu_ov, 1);
4794 tcg_gen_movi_tl(cpu_so, 1);
4795 gen_set_label(l1);
4796 tcg_temp_free_i64(t0);
4797 tcg_temp_free_i64(t1);
4798 tcg_temp_free(t2);
4799 if (unlikely(Rc(ctx->opcode) != 0))
4800 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4801 }
4802
4803 /* nabs - nabs. */
4804 static void gen_nabs(DisasContext *ctx)
4805 {
4806 int l1 = gen_new_label();
4807 int l2 = gen_new_label();
4808 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4809 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4810 tcg_gen_br(l2);
4811 gen_set_label(l1);
4812 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4813 gen_set_label(l2);
4814 if (unlikely(Rc(ctx->opcode) != 0))
4815 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4816 }
4817
4818 /* nabso - nabso. */
4819 static void gen_nabso(DisasContext *ctx)
4820 {
4821 int l1 = gen_new_label();
4822 int l2 = gen_new_label();
4823 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4824 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4825 tcg_gen_br(l2);
4826 gen_set_label(l1);
4827 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4828 gen_set_label(l2);
4829 /* nabs never overflows */
4830 tcg_gen_movi_tl(cpu_ov, 0);
4831 if (unlikely(Rc(ctx->opcode) != 0))
4832 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4833 }
4834
4835 /* rlmi - rlmi. */
4836 static void gen_rlmi(DisasContext *ctx)
4837 {
4838 uint32_t mb = MB(ctx->opcode);
4839 uint32_t me = ME(ctx->opcode);
4840 TCGv t0 = tcg_temp_new();
4841 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4842 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4843 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4844 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4845 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4846 tcg_temp_free(t0);
4847 if (unlikely(Rc(ctx->opcode) != 0))
4848 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4849 }
4850
4851 /* rrib - rrib. */
4852 static void gen_rrib(DisasContext *ctx)
4853 {
4854 TCGv t0 = tcg_temp_new();
4855 TCGv t1 = tcg_temp_new();
4856 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4857 tcg_gen_movi_tl(t1, 0x80000000);
4858 tcg_gen_shr_tl(t1, t1, t0);
4859 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4860 tcg_gen_and_tl(t0, t0, t1);
4861 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4862 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4863 tcg_temp_free(t0);
4864 tcg_temp_free(t1);
4865 if (unlikely(Rc(ctx->opcode) != 0))
4866 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4867 }
4868
4869 /* sle - sle. */
4870 static void gen_sle(DisasContext *ctx)
4871 {
4872 TCGv t0 = tcg_temp_new();
4873 TCGv t1 = tcg_temp_new();
4874 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4875 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4876 tcg_gen_subfi_tl(t1, 32, t1);
4877 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4878 tcg_gen_or_tl(t1, t0, t1);
4879 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4880 gen_store_spr(SPR_MQ, t1);
4881 tcg_temp_free(t0);
4882 tcg_temp_free(t1);
4883 if (unlikely(Rc(ctx->opcode) != 0))
4884 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4885 }
4886
4887 /* sleq - sleq. */
4888 static void gen_sleq(DisasContext *ctx)
4889 {
4890 TCGv t0 = tcg_temp_new();
4891 TCGv t1 = tcg_temp_new();
4892 TCGv t2 = tcg_temp_new();
4893 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4894 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4895 tcg_gen_shl_tl(t2, t2, t0);
4896 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4897 gen_load_spr(t1, SPR_MQ);
4898 gen_store_spr(SPR_MQ, t0);
4899 tcg_gen_and_tl(t0, t0, t2);
4900 tcg_gen_andc_tl(t1, t1, t2);
4901 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4902 tcg_temp_free(t0);
4903 tcg_temp_free(t1);
4904 tcg_temp_free(t2);
4905 if (unlikely(Rc(ctx->opcode) != 0))
4906 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4907 }
4908
4909 /* sliq - sliq. */
4910 static void gen_sliq(DisasContext *ctx)
4911 {
4912 int sh = SH(ctx->opcode);
4913 TCGv t0 = tcg_temp_new();
4914 TCGv t1 = tcg_temp_new();
4915 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4916 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4917 tcg_gen_or_tl(t1, t0, t1);
4918 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4919 gen_store_spr(SPR_MQ, t1);
4920 tcg_temp_free(t0);
4921 tcg_temp_free(t1);
4922 if (unlikely(Rc(ctx->opcode) != 0))
4923 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4924 }
4925
4926 /* slliq - slliq. */
4927 static void gen_slliq(DisasContext *ctx)
4928 {
4929 int sh = SH(ctx->opcode);
4930 TCGv t0 = tcg_temp_new();
4931 TCGv t1 = tcg_temp_new();
4932 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4933 gen_load_spr(t1, SPR_MQ);
4934 gen_store_spr(SPR_MQ, t0);
4935 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4936 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4937 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4938 tcg_temp_free(t0);
4939 tcg_temp_free(t1);
4940 if (unlikely(Rc(ctx->opcode) != 0))
4941 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4942 }
4943
4944 /* sllq - sllq. */
4945 static void gen_sllq(DisasContext *ctx)
4946 {
4947 int l1 = gen_new_label();
4948 int l2 = gen_new_label();
4949 TCGv t0 = tcg_temp_local_new();
4950 TCGv t1 = tcg_temp_local_new();
4951 TCGv t2 = tcg_temp_local_new();
4952 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4953 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4954 tcg_gen_shl_tl(t1, t1, t2);
4955 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4956 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4957 gen_load_spr(t0, SPR_MQ);
4958 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4959 tcg_gen_br(l2);
4960 gen_set_label(l1);
4961 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4962 gen_load_spr(t2, SPR_MQ);
4963 tcg_gen_andc_tl(t1, t2, t1);
4964 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4965 gen_set_label(l2);
4966 tcg_temp_free(t0);
4967 tcg_temp_free(t1);
4968 tcg_temp_free(t2);
4969 if (unlikely(Rc(ctx->opcode) != 0))
4970 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4971 }
4972
4973 /* slq - slq. */
4974 static void gen_slq(DisasContext *ctx)
4975 {
4976 int l1 = gen_new_label();
4977 TCGv t0 = tcg_temp_new();
4978 TCGv t1 = tcg_temp_new();
4979 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4980 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4981 tcg_gen_subfi_tl(t1, 32, t1);
4982 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4983 tcg_gen_or_tl(t1, t0, t1);
4984 gen_store_spr(SPR_MQ, t1);
4985 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4986 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4987 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4988 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4989 gen_set_label(l1);
4990 tcg_temp_free(t0);
4991 tcg_temp_free(t1);
4992 if (unlikely(Rc(ctx->opcode) != 0))
4993 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4994 }
4995
4996 /* sraiq - sraiq. */
4997 static void gen_sraiq(DisasContext *ctx)
4998 {
4999 int sh = SH(ctx->opcode);
5000 int l1 = gen_new_label();
5001 TCGv t0 = tcg_temp_new();
5002 TCGv t1 = tcg_temp_new();
5003 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5004 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5005 tcg_gen_or_tl(t0, t0, t1);
5006 gen_store_spr(SPR_MQ, t0);
5007 tcg_gen_movi_tl(cpu_ca, 0);
5008 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5009 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5010 tcg_gen_movi_tl(cpu_ca, 1);
5011 gen_set_label(l1);
5012 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5013 tcg_temp_free(t0);
5014 tcg_temp_free(t1);
5015 if (unlikely(Rc(ctx->opcode) != 0))
5016 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5017 }
5018
5019 /* sraq - sraq. */
5020 static void gen_sraq(DisasContext *ctx)
5021 {
5022 int l1 = gen_new_label();
5023 int l2 = gen_new_label();
5024 TCGv t0 = tcg_temp_new();
5025 TCGv t1 = tcg_temp_local_new();
5026 TCGv t2 = tcg_temp_local_new();
5027 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5028 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5029 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5030 tcg_gen_subfi_tl(t2, 32, t2);
5031 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5032 tcg_gen_or_tl(t0, t0, t2);
5033 gen_store_spr(SPR_MQ, t0);
5034 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5035 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5036 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5037 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5038 gen_set_label(l1);
5039 tcg_temp_free(t0);
5040 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5041 tcg_gen_movi_tl(cpu_ca, 0);
5042 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5043 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5044 tcg_gen_movi_tl(cpu_ca, 1);
5045 gen_set_label(l2);
5046 tcg_temp_free(t1);
5047 tcg_temp_free(t2);
5048 if (unlikely(Rc(ctx->opcode) != 0))
5049 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5050 }
5051
5052 /* sre - sre. */
5053 static void gen_sre(DisasContext *ctx)
5054 {
5055 TCGv t0 = tcg_temp_new();
5056 TCGv t1 = tcg_temp_new();
5057 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5058 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5059 tcg_gen_subfi_tl(t1, 32, t1);
5060 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5061 tcg_gen_or_tl(t1, t0, t1);
5062 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5063 gen_store_spr(SPR_MQ, t1);
5064 tcg_temp_free(t0);
5065 tcg_temp_free(t1);
5066 if (unlikely(Rc(ctx->opcode) != 0))
5067 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5068 }
5069
5070 /* srea - srea. */
5071 static void gen_srea(DisasContext *ctx)
5072 {
5073 TCGv t0 = tcg_temp_new();
5074 TCGv t1 = tcg_temp_new();
5075 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5076 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5077 gen_store_spr(SPR_MQ, t0);
5078 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5079 tcg_temp_free(t0);
5080 tcg_temp_free(t1);
5081 if (unlikely(Rc(ctx->opcode) != 0))
5082 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5083 }
5084
5085 /* sreq */
5086 static void gen_sreq(DisasContext *ctx)
5087 {
5088 TCGv t0 = tcg_temp_new();
5089 TCGv t1 = tcg_temp_new();
5090 TCGv t2 = tcg_temp_new();
5091 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5092 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5093 tcg_gen_shr_tl(t1, t1, t0);
5094 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5095 gen_load_spr(t2, SPR_MQ);
5096 gen_store_spr(SPR_MQ, t0);
5097 tcg_gen_and_tl(t0, t0, t1);
5098 tcg_gen_andc_tl(t2, t2, t1);
5099 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5100 tcg_temp_free(t0);
5101 tcg_temp_free(t1);
5102 tcg_temp_free(t2);
5103 if (unlikely(Rc(ctx->opcode) != 0))
5104 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5105 }
5106
5107 /* sriq */
5108 static void gen_sriq(DisasContext *ctx)
5109 {
5110 int sh = SH(ctx->opcode);
5111 TCGv t0 = tcg_temp_new();
5112 TCGv t1 = tcg_temp_new();
5113 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5114 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5115 tcg_gen_or_tl(t1, t0, t1);
5116 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5117 gen_store_spr(SPR_MQ, t1);
5118 tcg_temp_free(t0);
5119 tcg_temp_free(t1);
5120 if (unlikely(Rc(ctx->opcode) != 0))
5121 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5122 }
5123
5124 /* srliq */
5125 static void gen_srliq(DisasContext *ctx)
5126 {
5127 int sh = SH(ctx->opcode);
5128 TCGv t0 = tcg_temp_new();
5129 TCGv t1 = tcg_temp_new();
5130 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5131 gen_load_spr(t1, SPR_MQ);
5132 gen_store_spr(SPR_MQ, t0);
5133 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5134 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5135 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5136 tcg_temp_free(t0);
5137 tcg_temp_free(t1);
5138 if (unlikely(Rc(ctx->opcode) != 0))
5139 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5140 }
5141
5142 /* srlq */
5143 static void gen_srlq(DisasContext *ctx)
5144 {
5145 int l1 = gen_new_label();
5146 int l2 = gen_new_label();
5147 TCGv t0 = tcg_temp_local_new();
5148 TCGv t1 = tcg_temp_local_new();
5149 TCGv t2 = tcg_temp_local_new();
5150 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5151 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5152 tcg_gen_shr_tl(t2, t1, t2);
5153 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5154 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5155 gen_load_spr(t0, SPR_MQ);
5156 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5157 tcg_gen_br(l2);
5158 gen_set_label(l1);
5159 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5160 tcg_gen_and_tl(t0, t0, t2);
5161 gen_load_spr(t1, SPR_MQ);
5162 tcg_gen_andc_tl(t1, t1, t2);
5163 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5164 gen_set_label(l2);
5165 tcg_temp_free(t0);
5166 tcg_temp_free(t1);
5167 tcg_temp_free(t2);
5168 if (unlikely(Rc(ctx->opcode) != 0))
5169 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5170 }
5171
5172 /* srq */
5173 static void gen_srq(DisasContext *ctx)
5174 {
5175 int l1 = gen_new_label();
5176 TCGv t0 = tcg_temp_new();
5177 TCGv t1 = tcg_temp_new();
5178 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5179 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5180 tcg_gen_subfi_tl(t1, 32, t1);
5181 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5182 tcg_gen_or_tl(t1, t0, t1);
5183 gen_store_spr(SPR_MQ, t1);
5184 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5185 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5186 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5187 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5188 gen_set_label(l1);
5189 tcg_temp_free(t0);
5190 tcg_temp_free(t1);
5191 if (unlikely(Rc(ctx->opcode) != 0))
5192 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5193 }
5194
5195 /* PowerPC 602 specific instructions */
5196
5197 /* dsa */
5198 static void gen_dsa(DisasContext *ctx)
5199 {
5200 /* XXX: TODO */
5201 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5202 }
5203
5204 /* esa */
5205 static void gen_esa(DisasContext *ctx)
5206 {
5207 /* XXX: TODO */
5208 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5209 }
5210
5211 /* mfrom */
5212 static void gen_mfrom(DisasContext *ctx)
5213 {
5214 #if defined(CONFIG_USER_ONLY)
5215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5216 #else
5217 if (unlikely(!ctx->mem_idx)) {
5218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5219 return;
5220 }
5221 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5222 #endif
5223 }
5224
5225 /* 602 - 603 - G2 TLB management */
5226
5227 /* tlbld */
5228 static void gen_tlbld_6xx(DisasContext *ctx)
5229 {
5230 #if defined(CONFIG_USER_ONLY)
5231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5232 #else
5233 if (unlikely(!ctx->mem_idx)) {
5234 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5235 return;
5236 }
5237 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5238 #endif
5239 }
5240
5241 /* tlbli */
5242 static void gen_tlbli_6xx(DisasContext *ctx)
5243 {
5244 #if defined(CONFIG_USER_ONLY)
5245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5246 #else
5247 if (unlikely(!ctx->mem_idx)) {
5248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5249 return;
5250 }
5251 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5252 #endif
5253 }
5254
5255 /* 74xx TLB management */
5256
5257 /* tlbld */
5258 static void gen_tlbld_74xx(DisasContext *ctx)
5259 {
5260 #if defined(CONFIG_USER_ONLY)
5261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5262 #else
5263 if (unlikely(!ctx->mem_idx)) {
5264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5265 return;
5266 }
5267 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5268 #endif
5269 }
5270
5271 /* tlbli */
5272 static void gen_tlbli_74xx(DisasContext *ctx)
5273 {
5274 #if defined(CONFIG_USER_ONLY)
5275 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5276 #else
5277 if (unlikely(!ctx->mem_idx)) {
5278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5279 return;
5280 }
5281 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5282 #endif
5283 }
5284
5285 /* POWER instructions not in PowerPC 601 */
5286
5287 /* clf */
5288 static void gen_clf(DisasContext *ctx)
5289 {
5290 /* Cache line flush: implemented as no-op */
5291 }
5292
5293 /* cli */
5294 static void gen_cli(DisasContext *ctx)
5295 {
5296 /* Cache line invalidate: privileged and treated as no-op */
5297 #if defined(CONFIG_USER_ONLY)
5298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5299 #else
5300 if (unlikely(!ctx->mem_idx)) {
5301 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5302 return;
5303 }
5304 #endif
5305 }
5306
5307 /* dclst */
5308 static void gen_dclst(DisasContext *ctx)
5309 {
5310 /* Data cache line store: treated as no-op */
5311 }
5312
5313 static void gen_mfsri(DisasContext *ctx)
5314 {
5315 #if defined(CONFIG_USER_ONLY)
5316 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5317 #else
5318 int ra = rA(ctx->opcode);
5319 int rd = rD(ctx->opcode);
5320 TCGv t0;
5321 if (unlikely(!ctx->mem_idx)) {
5322 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5323 return;
5324 }
5325 t0 = tcg_temp_new();
5326 gen_addr_reg_index(ctx, t0);
5327 tcg_gen_shri_tl(t0, t0, 28);
5328 tcg_gen_andi_tl(t0, t0, 0xF);
5329 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5330 tcg_temp_free(t0);
5331 if (ra != 0 && ra != rd)
5332 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5333 #endif
5334 }
5335
5336 static void gen_rac(DisasContext *ctx)
5337 {
5338 #if defined(CONFIG_USER_ONLY)
5339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5340 #else
5341 TCGv t0;
5342 if (unlikely(!ctx->mem_idx)) {
5343 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5344 return;
5345 }
5346 t0 = tcg_temp_new();
5347 gen_addr_reg_index(ctx, t0);
5348 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5349 tcg_temp_free(t0);
5350 #endif
5351 }
5352
5353 static void gen_rfsvc(DisasContext *ctx)
5354 {
5355 #if defined(CONFIG_USER_ONLY)
5356 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5357 #else
5358 if (unlikely(!ctx->mem_idx)) {
5359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5360 return;
5361 }
5362 gen_helper_rfsvc(cpu_env);
5363 gen_sync_exception(ctx);
5364 #endif
5365 }
5366
5367 /* svc is not implemented for now */
5368
5369 /* POWER2 specific instructions */
5370 /* Quad manipulation (load/store two floats at a time) */
5371
5372 /* lfq */
5373 static void gen_lfq(DisasContext *ctx)
5374 {
5375 int rd = rD(ctx->opcode);
5376 TCGv t0;
5377 gen_set_access_type(ctx, ACCESS_FLOAT);
5378 t0 = tcg_temp_new();
5379 gen_addr_imm_index(ctx, t0, 0);
5380 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5381 gen_addr_add(ctx, t0, t0, 8);
5382 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5383 tcg_temp_free(t0);
5384 }
5385
5386 /* lfqu */
5387 static void gen_lfqu(DisasContext *ctx)
5388 {
5389 int ra = rA(ctx->opcode);
5390 int rd = rD(ctx->opcode);
5391 TCGv t0, t1;
5392 gen_set_access_type(ctx, ACCESS_FLOAT);
5393 t0 = tcg_temp_new();
5394 t1 = tcg_temp_new();
5395 gen_addr_imm_index(ctx, t0, 0);
5396 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5397 gen_addr_add(ctx, t1, t0, 8);
5398 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5399 if (ra != 0)
5400 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5401 tcg_temp_free(t0);
5402 tcg_temp_free(t1);
5403 }
5404
5405 /* lfqux */
5406 static void gen_lfqux(DisasContext *ctx)
5407 {
5408 int ra = rA(ctx->opcode);
5409 int rd = rD(ctx->opcode);
5410 gen_set_access_type(ctx, ACCESS_FLOAT);
5411 TCGv t0, t1;
5412 t0 = tcg_temp_new();
5413 gen_addr_reg_index(ctx, t0);
5414 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5415 t1 = tcg_temp_new();
5416 gen_addr_add(ctx, t1, t0, 8);
5417 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5418 tcg_temp_free(t1);
5419 if (ra != 0)
5420 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5421 tcg_temp_free(t0);
5422 }
5423
5424 /* lfqx */
5425 static void gen_lfqx(DisasContext *ctx)
5426 {
5427 int rd = rD(ctx->opcode);
5428 TCGv t0;
5429 gen_set_access_type(ctx, ACCESS_FLOAT);
5430 t0 = tcg_temp_new();
5431 gen_addr_reg_index(ctx, t0);
5432 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5433 gen_addr_add(ctx, t0, t0, 8);
5434 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5435 tcg_temp_free(t0);
5436 }
5437
5438 /* stfq */
5439 static void gen_stfq(DisasContext *ctx)
5440 {
5441 int rd = rD(ctx->opcode);
5442 TCGv t0;
5443 gen_set_access_type(ctx, ACCESS_FLOAT);
5444 t0 = tcg_temp_new();
5445 gen_addr_imm_index(ctx, t0, 0);
5446 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5447 gen_addr_add(ctx, t0, t0, 8);
5448 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5449 tcg_temp_free(t0);
5450 }
5451
5452 /* stfqu */
5453 static void gen_stfqu(DisasContext *ctx)
5454 {
5455 int ra = rA(ctx->opcode);
5456 int rd = rD(ctx->opcode);
5457 TCGv t0, t1;
5458 gen_set_access_type(ctx, ACCESS_FLOAT);
5459 t0 = tcg_temp_new();
5460 gen_addr_imm_index(ctx, t0, 0);
5461 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5462 t1 = tcg_temp_new();
5463 gen_addr_add(ctx, t1, t0, 8);
5464 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5465 tcg_temp_free(t1);
5466 if (ra != 0)
5467 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5468 tcg_temp_free(t0);
5469 }
5470
5471 /* stfqux */
5472 static void gen_stfqux(DisasContext *ctx)
5473 {
5474 int ra = rA(ctx->opcode);
5475 int rd = rD(ctx->opcode);
5476 TCGv t0, t1;
5477 gen_set_access_type(ctx, ACCESS_FLOAT);
5478 t0 = tcg_temp_new();
5479 gen_addr_reg_index(ctx, t0);
5480 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5481 t1 = tcg_temp_new();
5482 gen_addr_add(ctx, t1, t0, 8);
5483 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5484 tcg_temp_free(t1);
5485 if (ra != 0)
5486 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5487 tcg_temp_free(t0);
5488 }
5489
5490 /* stfqx */
5491 static void gen_stfqx(DisasContext *ctx)
5492 {
5493 int rd = rD(ctx->opcode);
5494 TCGv t0;
5495 gen_set_access_type(ctx, ACCESS_FLOAT);
5496 t0 = tcg_temp_new();
5497 gen_addr_reg_index(ctx, t0);
5498 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5499 gen_addr_add(ctx, t0, t0, 8);
5500 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5501 tcg_temp_free(t0);
5502 }
5503
5504 /* BookE specific instructions */
5505
5506 /* XXX: not implemented on 440 ? */
5507 static void gen_mfapidi(DisasContext *ctx)
5508 {
5509 /* XXX: TODO */
5510 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5511 }
5512
5513 /* XXX: not implemented on 440 ? */
5514 static void gen_tlbiva(DisasContext *ctx)
5515 {
5516 #if defined(CONFIG_USER_ONLY)
5517 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5518 #else
5519 TCGv t0;
5520 if (unlikely(!ctx->mem_idx)) {
5521 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5522 return;
5523 }
5524 t0 = tcg_temp_new();
5525 gen_addr_reg_index(ctx, t0);
5526 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5527 tcg_temp_free(t0);
5528 #endif
5529 }
5530
5531 /* All 405 MAC instructions are translated here */
5532 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5533 int ra, int rb, int rt, int Rc)
5534 {
5535 TCGv t0, t1;
5536
5537 t0 = tcg_temp_local_new();
5538 t1 = tcg_temp_local_new();
5539
5540 switch (opc3 & 0x0D) {
5541 case 0x05:
5542 /* macchw - macchw. - macchwo - macchwo. */
5543 /* macchws - macchws. - macchwso - macchwso. */
5544 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5545 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5546 /* mulchw - mulchw. */
5547 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5548 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5549 tcg_gen_ext16s_tl(t1, t1);
5550 break;
5551 case 0x04:
5552 /* macchwu - macchwu. - macchwuo - macchwuo. */
5553 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5554 /* mulchwu - mulchwu. */
5555 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5556 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5557 tcg_gen_ext16u_tl(t1, t1);
5558 break;
5559 case 0x01:
5560 /* machhw - machhw. - machhwo - machhwo. */
5561 /* machhws - machhws. - machhwso - machhwso. */
5562 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5563 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5564 /* mulhhw - mulhhw. */
5565 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5566 tcg_gen_ext16s_tl(t0, t0);
5567 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5568 tcg_gen_ext16s_tl(t1, t1);
5569 break;
5570 case 0x00:
5571 /* machhwu - machhwu. - machhwuo - machhwuo. */
5572 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5573 /* mulhhwu - mulhhwu. */
5574 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5575 tcg_gen_ext16u_tl(t0, t0);
5576 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5577 tcg_gen_ext16u_tl(t1, t1);
5578 break;
5579 case 0x0D:
5580 /* maclhw - maclhw. - maclhwo - maclhwo. */
5581 /* maclhws - maclhws. - maclhwso - maclhwso. */
5582 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5583 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5584 /* mullhw - mullhw. */
5585 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5586 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5587 break;
5588 case 0x0C:
5589 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5590 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5591 /* mullhwu - mullhwu. */
5592 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5593 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5594 break;
5595 }
5596 if (opc2 & 0x04) {
5597 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5598 tcg_gen_mul_tl(t1, t0, t1);
5599 if (opc2 & 0x02) {
5600 /* nmultiply-and-accumulate (0x0E) */
5601 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5602 } else {
5603 /* multiply-and-accumulate (0x0C) */
5604 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5605 }
5606
5607 if (opc3 & 0x12) {
5608 /* Check overflow and/or saturate */
5609 int l1 = gen_new_label();
5610
5611 if (opc3 & 0x10) {
5612 /* Start with XER OV disabled, the most likely case */
5613 tcg_gen_movi_tl(cpu_ov, 0);
5614 }
5615 if (opc3 & 0x01) {
5616 /* Signed */
5617 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5618 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5619 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5620 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5621 if (opc3 & 0x02) {
5622 /* Saturate */
5623 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5624 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5625 }
5626 } else {
5627 /* Unsigned */
5628 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5629 if (opc3 & 0x02) {
5630 /* Saturate */
5631 tcg_gen_movi_tl(t0, UINT32_MAX);
5632 }
5633 }
5634 if (opc3 & 0x10) {
5635 /* Check overflow */
5636 tcg_gen_movi_tl(cpu_ov, 1);
5637 tcg_gen_movi_tl(cpu_so, 1);
5638 }
5639 gen_set_label(l1);
5640 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5641 }
5642 } else {
5643 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5644 }
5645 tcg_temp_free(t0);
5646 tcg_temp_free(t1);
5647 if (unlikely(Rc) != 0) {
5648 /* Update Rc0 */
5649 gen_set_Rc0(ctx, cpu_gpr[rt]);
5650 }
5651 }
5652
5653 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5654 static void glue(gen_, name)(DisasContext *ctx) \
5655 { \
5656 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5657 rD(ctx->opcode), Rc(ctx->opcode)); \
5658 }
5659
5660 /* macchw - macchw. */
5661 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5662 /* macchwo - macchwo. */
5663 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5664 /* macchws - macchws. */
5665 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5666 /* macchwso - macchwso. */
5667 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5668 /* macchwsu - macchwsu. */
5669 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5670 /* macchwsuo - macchwsuo. */
5671 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5672 /* macchwu - macchwu. */
5673 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5674 /* macchwuo - macchwuo. */
5675 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5676 /* machhw - machhw. */
5677 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5678 /* machhwo - machhwo. */
5679 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5680 /* machhws - machhws. */
5681 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5682 /* machhwso - machhwso. */
5683 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5684 /* machhwsu - machhwsu. */
5685 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5686 /* machhwsuo - machhwsuo. */
5687 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5688 /* machhwu - machhwu. */
5689 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5690 /* machhwuo - machhwuo. */
5691 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5692 /* maclhw - maclhw. */
5693 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5694 /* maclhwo - maclhwo. */
5695 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5696 /* maclhws - maclhws. */
5697 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5698 /* maclhwso - maclhwso. */
5699 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5700 /* maclhwu - maclhwu. */
5701 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5702 /* maclhwuo - maclhwuo. */
5703 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5704 /* maclhwsu - maclhwsu. */
5705 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5706 /* maclhwsuo - maclhwsuo. */
5707 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5708 /* nmacchw - nmacchw. */
5709 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5710 /* nmacchwo - nmacchwo. */
5711 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5712 /* nmacchws - nmacchws. */
5713 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5714 /* nmacchwso - nmacchwso. */
5715 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5716 /* nmachhw - nmachhw. */
5717 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5718 /* nmachhwo - nmachhwo. */
5719 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5720 /* nmachhws - nmachhws. */
5721 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5722 /* nmachhwso - nmachhwso. */
5723 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5724 /* nmaclhw - nmaclhw. */
5725 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5726 /* nmaclhwo - nmaclhwo. */
5727 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5728 /* nmaclhws - nmaclhws. */
5729 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5730 /* nmaclhwso - nmaclhwso. */
5731 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5732
5733 /* mulchw - mulchw. */
5734 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5735 /* mulchwu - mulchwu. */
5736 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5737 /* mulhhw - mulhhw. */
5738 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5739 /* mulhhwu - mulhhwu. */
5740 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5741 /* mullhw - mullhw. */
5742 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5743 /* mullhwu - mullhwu. */
5744 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5745
5746 /* mfdcr */
5747 static void gen_mfdcr(DisasContext *ctx)
5748 {
5749 #if defined(CONFIG_USER_ONLY)
5750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5751 #else
5752 TCGv dcrn;
5753 if (unlikely(!ctx->mem_idx)) {
5754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5755 return;
5756 }
5757 /* NIP cannot be restored if the memory exception comes from an helper */
5758 gen_update_nip(ctx, ctx->nip - 4);
5759 dcrn = tcg_const_tl(SPR(ctx->opcode));
5760 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5761 tcg_temp_free(dcrn);
5762 #endif
5763 }
5764
5765 /* mtdcr */
5766 static void gen_mtdcr(DisasContext *ctx)
5767 {
5768 #if defined(CONFIG_USER_ONLY)
5769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5770 #else
5771 TCGv dcrn;
5772 if (unlikely(!ctx->mem_idx)) {
5773 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5774 return;
5775 }
5776 /* NIP cannot be restored if the memory exception comes from an helper */
5777 gen_update_nip(ctx, ctx->nip - 4);
5778 dcrn = tcg_const_tl(SPR(ctx->opcode));
5779 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5780 tcg_temp_free(dcrn);
5781 #endif
5782 }
5783
5784 /* mfdcrx */
5785 /* XXX: not implemented on 440 ? */
5786 static void gen_mfdcrx(DisasContext *ctx)
5787 {
5788 #if defined(CONFIG_USER_ONLY)
5789 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5790 #else
5791 if (unlikely(!ctx->mem_idx)) {
5792 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5793 return;
5794 }
5795 /* NIP cannot be restored if the memory exception comes from an helper */
5796 gen_update_nip(ctx, ctx->nip - 4);
5797 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5798 cpu_gpr[rA(ctx->opcode)]);
5799 /* Note: Rc update flag set leads to undefined state of Rc0 */
5800 #endif
5801 }
5802
5803 /* mtdcrx */
5804 /* XXX: not implemented on 440 ? */
5805 static void gen_mtdcrx(DisasContext *ctx)
5806 {
5807 #if defined(CONFIG_USER_ONLY)
5808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5809 #else
5810 if (unlikely(!ctx->mem_idx)) {
5811 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5812 return;
5813 }
5814 /* NIP cannot be restored if the memory exception comes from an helper */
5815 gen_update_nip(ctx, ctx->nip - 4);
5816 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5817 cpu_gpr[rS(ctx->opcode)]);
5818 /* Note: Rc update flag set leads to undefined state of Rc0 */
5819 #endif
5820 }
5821
5822 /* mfdcrux (PPC 460) : user-mode access to DCR */
5823 static void gen_mfdcrux(DisasContext *ctx)
5824 {
5825 /* NIP cannot be restored if the memory exception comes from an helper */
5826 gen_update_nip(ctx, ctx->nip - 4);
5827 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5828 cpu_gpr[rA(ctx->opcode)]);
5829 /* Note: Rc update flag set leads to undefined state of Rc0 */
5830 }
5831
5832 /* mtdcrux (PPC 460) : user-mode access to DCR */
5833 static void gen_mtdcrux(DisasContext *ctx)
5834 {
5835 /* NIP cannot be restored if the memory exception comes from an helper */
5836 gen_update_nip(ctx, ctx->nip - 4);
5837 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5838 cpu_gpr[rS(ctx->opcode)]);
5839 /* Note: Rc update flag set leads to undefined state of Rc0 */
5840 }
5841
5842 /* dccci */
5843 static void gen_dccci(DisasContext *ctx)
5844 {
5845 #if defined(CONFIG_USER_ONLY)
5846 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5847 #else
5848 if (unlikely(!ctx->mem_idx)) {
5849 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5850 return;
5851 }
5852 /* interpreted as no-op */
5853 #endif
5854 }
5855
5856 /* dcread */
5857 static void gen_dcread(DisasContext *ctx)
5858 {
5859 #if defined(CONFIG_USER_ONLY)
5860 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5861 #else
5862 TCGv EA, val;
5863 if (unlikely(!ctx->mem_idx)) {
5864 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5865 return;
5866 }
5867 gen_set_access_type(ctx, ACCESS_CACHE);
5868 EA = tcg_temp_new();
5869 gen_addr_reg_index(ctx, EA);
5870 val = tcg_temp_new();
5871 gen_qemu_ld32u(ctx, val, EA);
5872 tcg_temp_free(val);
5873 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5874 tcg_temp_free(EA);
5875 #endif
5876 }
5877
5878 /* icbt */
5879 static void gen_icbt_40x(DisasContext *ctx)
5880 {
5881 /* interpreted as no-op */
5882 /* XXX: specification say this is treated as a load by the MMU
5883 * but does not generate any exception
5884 */
5885 }
5886
5887 /* iccci */
5888 static void gen_iccci(DisasContext *ctx)
5889 {
5890 #if defined(CONFIG_USER_ONLY)
5891 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5892 #else
5893 if (unlikely(!ctx->mem_idx)) {
5894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5895 return;
5896 }
5897 /* interpreted as no-op */
5898 #endif
5899 }
5900
5901 /* icread */
5902 static void gen_icread(DisasContext *ctx)
5903 {
5904 #if defined(CONFIG_USER_ONLY)
5905 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5906 #else
5907 if (unlikely(!ctx->mem_idx)) {
5908 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5909 return;
5910 }
5911 /* interpreted as no-op */
5912 #endif
5913 }
5914
5915 /* rfci (mem_idx only) */
5916 static void gen_rfci_40x(DisasContext *ctx)
5917 {
5918 #if defined(CONFIG_USER_ONLY)
5919 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5920 #else
5921 if (unlikely(!ctx->mem_idx)) {
5922 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5923 return;
5924 }
5925 /* Restore CPU state */
5926 gen_helper_40x_rfci(cpu_env);
5927 gen_sync_exception(ctx);
5928 #endif
5929 }
5930
5931 static void gen_rfci(DisasContext *ctx)
5932 {
5933 #if defined(CONFIG_USER_ONLY)
5934 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5935 #else
5936 if (unlikely(!ctx->mem_idx)) {
5937 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5938 return;
5939 }
5940 /* Restore CPU state */
5941 gen_helper_rfci(cpu_env);
5942 gen_sync_exception(ctx);
5943 #endif
5944 }
5945
5946 /* BookE specific */
5947
5948 /* XXX: not implemented on 440 ? */
5949 static void gen_rfdi(DisasContext *ctx)
5950 {
5951 #if defined(CONFIG_USER_ONLY)
5952 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5953 #else
5954 if (unlikely(!ctx->mem_idx)) {
5955 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5956 return;
5957 }
5958 /* Restore CPU state */
5959 gen_helper_rfdi(cpu_env);
5960 gen_sync_exception(ctx);
5961 #endif
5962 }
5963
5964 /* XXX: not implemented on 440 ? */
5965 static void gen_rfmci(DisasContext *ctx)
5966 {
5967 #if defined(CONFIG_USER_ONLY)
5968 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5969 #else
5970 if (unlikely(!ctx->mem_idx)) {
5971 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5972 return;
5973 }
5974 /* Restore CPU state */
5975 gen_helper_rfmci(cpu_env);
5976 gen_sync_exception(ctx);
5977 #endif
5978 }
5979
5980 /* TLB management - PowerPC 405 implementation */
5981
5982 /* tlbre */
5983 static void gen_tlbre_40x(DisasContext *ctx)
5984 {
5985 #if defined(CONFIG_USER_ONLY)
5986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5987 #else
5988 if (unlikely(!ctx->mem_idx)) {
5989 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5990 return;
5991 }
5992 switch (rB(ctx->opcode)) {
5993 case 0:
5994 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5995 cpu_gpr[rA(ctx->opcode)]);
5996 break;
5997 case 1:
5998 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5999 cpu_gpr[rA(ctx->opcode)]);
6000 break;
6001 default:
6002 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6003 break;
6004 }
6005 #endif
6006 }
6007
6008 /* tlbsx - tlbsx. */
6009 static void gen_tlbsx_40x(DisasContext *ctx)
6010 {
6011 #if defined(CONFIG_USER_ONLY)
6012 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6013 #else
6014 TCGv t0;
6015 if (unlikely(!ctx->mem_idx)) {
6016 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6017 return;
6018 }
6019 t0 = tcg_temp_new();
6020 gen_addr_reg_index(ctx, t0);
6021 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6022 tcg_temp_free(t0);
6023 if (Rc(ctx->opcode)) {
6024 int l1 = gen_new_label();
6025 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6026 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6027 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6028 gen_set_label(l1);
6029 }
6030 #endif
6031 }
6032
6033 /* tlbwe */
6034 static void gen_tlbwe_40x(DisasContext *ctx)
6035 {
6036 #if defined(CONFIG_USER_ONLY)
6037 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6038 #else
6039 if (unlikely(!ctx->mem_idx)) {
6040 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6041 return;
6042 }
6043 switch (rB(ctx->opcode)) {
6044 case 0:
6045 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6046 cpu_gpr[rS(ctx->opcode)]);
6047 break;
6048 case 1:
6049 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6050 cpu_gpr[rS(ctx->opcode)]);
6051 break;
6052 default:
6053 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6054 break;
6055 }
6056 #endif
6057 }
6058
6059 /* TLB management - PowerPC 440 implementation */
6060
6061 /* tlbre */
6062 static void gen_tlbre_440(DisasContext *ctx)
6063 {
6064 #if defined(CONFIG_USER_ONLY)
6065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6066 #else
6067 if (unlikely(!ctx->mem_idx)) {
6068 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6069 return;
6070 }
6071 switch (rB(ctx->opcode)) {
6072 case 0:
6073 case 1:
6074 case 2:
6075 {
6076 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6077 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6078 t0, cpu_gpr[rA(ctx->opcode)]);
6079 tcg_temp_free_i32(t0);
6080 }
6081 break;
6082 default:
6083 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6084 break;
6085 }
6086 #endif
6087 }
6088
6089 /* tlbsx - tlbsx. */
6090 static void gen_tlbsx_440(DisasContext *ctx)
6091 {
6092 #if defined(CONFIG_USER_ONLY)
6093 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6094 #else
6095 TCGv t0;
6096 if (unlikely(!ctx->mem_idx)) {
6097 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6098 return;
6099 }
6100 t0 = tcg_temp_new();
6101 gen_addr_reg_index(ctx, t0);
6102 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6103 tcg_temp_free(t0);
6104 if (Rc(ctx->opcode)) {
6105 int l1 = gen_new_label();
6106 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6107 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6108 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6109 gen_set_label(l1);
6110 }
6111 #endif
6112 }
6113
6114 /* tlbwe */
6115 static void gen_tlbwe_440(DisasContext *ctx)
6116 {
6117 #if defined(CONFIG_USER_ONLY)
6118 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6119 #else
6120 if (unlikely(!ctx->mem_idx)) {
6121 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6122 return;
6123 }
6124 switch (rB(ctx->opcode)) {
6125 case 0:
6126 case 1:
6127 case 2:
6128 {
6129 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6130 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6131 cpu_gpr[rS(ctx->opcode)]);
6132 tcg_temp_free_i32(t0);
6133 }
6134 break;
6135 default:
6136 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6137 break;
6138 }
6139 #endif
6140 }
6141
6142 /* TLB management - PowerPC BookE 2.06 implementation */
6143
6144 /* tlbre */
6145 static void gen_tlbre_booke206(DisasContext *ctx)
6146 {
6147 #if defined(CONFIG_USER_ONLY)
6148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6149 #else
6150 if (unlikely(!ctx->mem_idx)) {
6151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6152 return;
6153 }
6154
6155 gen_helper_booke206_tlbre(cpu_env);
6156 #endif
6157 }
6158
6159 /* tlbsx - tlbsx. */
6160 static void gen_tlbsx_booke206(DisasContext *ctx)
6161 {
6162 #if defined(CONFIG_USER_ONLY)
6163 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6164 #else
6165 TCGv t0;
6166 if (unlikely(!ctx->mem_idx)) {
6167 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6168 return;
6169 }
6170
6171 if (rA(ctx->opcode)) {
6172 t0 = tcg_temp_new();
6173 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6174 } else {
6175 t0 = tcg_const_tl(0);
6176 }
6177
6178 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6179 gen_helper_booke206_tlbsx(cpu_env, t0);
6180 #endif
6181 }
6182
6183 /* tlbwe */
6184 static void gen_tlbwe_booke206(DisasContext *ctx)
6185 {
6186 #if defined(CONFIG_USER_ONLY)
6187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6188 #else
6189 if (unlikely(!ctx->mem_idx)) {
6190 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6191 return;
6192 }
6193 gen_update_nip(ctx, ctx->nip - 4);
6194 gen_helper_booke206_tlbwe(cpu_env);
6195 #endif
6196 }
6197
6198 static void gen_tlbivax_booke206(DisasContext *ctx)
6199 {
6200 #if defined(CONFIG_USER_ONLY)
6201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6202 #else
6203 TCGv t0;
6204 if (unlikely(!ctx->mem_idx)) {
6205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6206 return;
6207 }
6208
6209 t0 = tcg_temp_new();
6210 gen_addr_reg_index(ctx, t0);
6211
6212 gen_helper_booke206_tlbivax(cpu_env, t0);
6213 #endif
6214 }
6215
6216 static void gen_tlbilx_booke206(DisasContext *ctx)
6217 {
6218 #if defined(CONFIG_USER_ONLY)
6219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6220 #else
6221 TCGv t0;
6222 if (unlikely(!ctx->mem_idx)) {
6223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6224 return;
6225 }
6226
6227 t0 = tcg_temp_new();
6228 gen_addr_reg_index(ctx, t0);
6229
6230 switch((ctx->opcode >> 21) & 0x3) {
6231 case 0:
6232 gen_helper_booke206_tlbilx0(cpu_env, t0);
6233 break;
6234 case 1:
6235 gen_helper_booke206_tlbilx1(cpu_env, t0);
6236 break;
6237 case 3:
6238 gen_helper_booke206_tlbilx3(cpu_env, t0);
6239 break;
6240 default:
6241 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6242 break;
6243 }
6244
6245 tcg_temp_free(t0);
6246 #endif
6247 }
6248
6249
6250 /* wrtee */
6251 static void gen_wrtee(DisasContext *ctx)
6252 {
6253 #if defined(CONFIG_USER_ONLY)
6254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6255 #else
6256 TCGv t0;
6257 if (unlikely(!ctx->mem_idx)) {
6258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6259 return;
6260 }
6261 t0 = tcg_temp_new();
6262 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6263 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6264 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6265 tcg_temp_free(t0);
6266 /* Stop translation to have a chance to raise an exception
6267 * if we just set msr_ee to 1
6268 */
6269 gen_stop_exception(ctx);
6270 #endif
6271 }
6272
6273 /* wrteei */
6274 static void gen_wrteei(DisasContext *ctx)
6275 {
6276 #if defined(CONFIG_USER_ONLY)
6277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6278 #else
6279 if (unlikely(!ctx->mem_idx)) {
6280 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6281 return;
6282 }
6283 if (ctx->opcode & 0x00008000) {
6284 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6285 /* Stop translation to have a chance to raise an exception */
6286 gen_stop_exception(ctx);
6287 } else {
6288 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6289 }
6290 #endif
6291 }
6292
6293 /* PowerPC 440 specific instructions */
6294
6295 /* dlmzb */
6296 static void gen_dlmzb(DisasContext *ctx)
6297 {
6298 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6299 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6300 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6301 tcg_temp_free_i32(t0);
6302 }
6303
6304 /* mbar replaces eieio on 440 */
6305 static void gen_mbar(DisasContext *ctx)
6306 {
6307 /* interpreted as no-op */
6308 }
6309
6310 /* msync replaces sync on 440 */
6311 static void gen_msync_4xx(DisasContext *ctx)
6312 {
6313 /* interpreted as no-op */
6314 }
6315
6316 /* icbt */
6317 static void gen_icbt_440(DisasContext *ctx)
6318 {
6319 /* interpreted as no-op */
6320 /* XXX: specification say this is treated as a load by the MMU
6321 * but does not generate any exception
6322 */
6323 }
6324
6325 /* Embedded.Processor Control */
6326
6327 static void gen_msgclr(DisasContext *ctx)
6328 {
6329 #if defined(CONFIG_USER_ONLY)
6330 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6331 #else
6332 if (unlikely(ctx->mem_idx == 0)) {
6333 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6334 return;
6335 }
6336
6337 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6338 #endif
6339 }
6340
6341 static void gen_msgsnd(DisasContext *ctx)
6342 {
6343 #if defined(CONFIG_USER_ONLY)
6344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6345 #else
6346 if (unlikely(ctx->mem_idx == 0)) {
6347 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6348 return;
6349 }
6350
6351 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6352 #endif
6353 }
6354
6355 /*** Altivec vector extension ***/
6356 /* Altivec registers moves */
6357
6358 static inline TCGv_ptr gen_avr_ptr(int reg)
6359 {
6360 TCGv_ptr r = tcg_temp_new_ptr();
6361 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6362 return r;
6363 }
6364
6365 #define GEN_VR_LDX(name, opc2, opc3) \
6366 static void glue(gen_, name)(DisasContext *ctx) \
6367 { \
6368 TCGv EA; \
6369 if (unlikely(!ctx->altivec_enabled)) { \
6370 gen_exception(ctx, POWERPC_EXCP_VPU); \
6371 return; \
6372 } \
6373 gen_set_access_type(ctx, ACCESS_INT); \
6374 EA = tcg_temp_new(); \
6375 gen_addr_reg_index(ctx, EA); \
6376 tcg_gen_andi_tl(EA, EA, ~0xf); \
6377 if (ctx->le_mode) { \
6378 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6379 tcg_gen_addi_tl(EA, EA, 8); \
6380 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6381 } else { \
6382 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6383 tcg_gen_addi_tl(EA, EA, 8); \
6384 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6385 } \
6386 tcg_temp_free(EA); \
6387 }
6388
6389 #define GEN_VR_STX(name, opc2, opc3) \
6390 static void gen_st##name(DisasContext *ctx) \
6391 { \
6392 TCGv EA; \
6393 if (unlikely(!ctx->altivec_enabled)) { \
6394 gen_exception(ctx, POWERPC_EXCP_VPU); \
6395 return; \
6396 } \
6397 gen_set_access_type(ctx, ACCESS_INT); \
6398 EA = tcg_temp_new(); \
6399 gen_addr_reg_index(ctx, EA); \
6400 tcg_gen_andi_tl(EA, EA, ~0xf); \
6401 if (ctx->le_mode) { \
6402 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6403 tcg_gen_addi_tl(EA, EA, 8); \
6404 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6405 } else { \
6406 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6407 tcg_gen_addi_tl(EA, EA, 8); \
6408 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6409 } \
6410 tcg_temp_free(EA); \
6411 }
6412
6413 #define GEN_VR_LVE(name, opc2, opc3) \
6414 static void gen_lve##name(DisasContext *ctx) \
6415 { \
6416 TCGv EA; \
6417 TCGv_ptr rs; \
6418 if (unlikely(!ctx->altivec_enabled)) { \
6419 gen_exception(ctx, POWERPC_EXCP_VPU); \
6420 return; \
6421 } \
6422 gen_set_access_type(ctx, ACCESS_INT); \
6423 EA = tcg_temp_new(); \
6424 gen_addr_reg_index(ctx, EA); \
6425 rs = gen_avr_ptr(rS(ctx->opcode)); \
6426 gen_helper_lve##name(cpu_env, rs, EA); \
6427 tcg_temp_free(EA); \
6428 tcg_temp_free_ptr(rs); \
6429 }
6430
6431 #define GEN_VR_STVE(name, opc2, opc3) \
6432 static void gen_stve##name(DisasContext *ctx) \
6433 { \
6434 TCGv EA; \
6435 TCGv_ptr rs; \
6436 if (unlikely(!ctx->altivec_enabled)) { \
6437 gen_exception(ctx, POWERPC_EXCP_VPU); \
6438 return; \
6439 } \
6440 gen_set_access_type(ctx, ACCESS_INT); \
6441 EA = tcg_temp_new(); \
6442 gen_addr_reg_index(ctx, EA); \
6443 rs = gen_avr_ptr(rS(ctx->opcode)); \
6444 gen_helper_stve##name(cpu_env, rs, EA); \
6445 tcg_temp_free(EA); \
6446 tcg_temp_free_ptr(rs); \
6447 }
6448
6449 GEN_VR_LDX(lvx, 0x07, 0x03);
6450 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6451 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6452
6453 GEN_VR_LVE(bx, 0x07, 0x00);
6454 GEN_VR_LVE(hx, 0x07, 0x01);
6455 GEN_VR_LVE(wx, 0x07, 0x02);
6456
6457 GEN_VR_STX(svx, 0x07, 0x07);
6458 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6459 GEN_VR_STX(svxl, 0x07, 0x0F);
6460
6461 GEN_VR_STVE(bx, 0x07, 0x04);
6462 GEN_VR_STVE(hx, 0x07, 0x05);
6463 GEN_VR_STVE(wx, 0x07, 0x06);
6464
6465 static void gen_lvsl(DisasContext *ctx)
6466 {
6467 TCGv_ptr rd;
6468 TCGv EA;
6469 if (unlikely(!ctx->altivec_enabled)) {
6470 gen_exception(ctx, POWERPC_EXCP_VPU);
6471 return;
6472 }
6473 EA = tcg_temp_new();
6474 gen_addr_reg_index(ctx, EA);
6475 rd = gen_avr_ptr(rD(ctx->opcode));
6476 gen_helper_lvsl(rd, EA);
6477 tcg_temp_free(EA);
6478 tcg_temp_free_ptr(rd);
6479 }
6480
6481 static void gen_lvsr(DisasContext *ctx)
6482 {
6483 TCGv_ptr rd;
6484 TCGv EA;
6485 if (unlikely(!ctx->altivec_enabled)) {
6486 gen_exception(ctx, POWERPC_EXCP_VPU);
6487 return;
6488 }
6489 EA = tcg_temp_new();
6490 gen_addr_reg_index(ctx, EA);
6491 rd = gen_avr_ptr(rD(ctx->opcode));
6492 gen_helper_lvsr(rd, EA);
6493 tcg_temp_free(EA);
6494 tcg_temp_free_ptr(rd);
6495 }
6496
6497 static void gen_mfvscr(DisasContext *ctx)
6498 {
6499 TCGv_i32 t;
6500 if (unlikely(!ctx->altivec_enabled)) {
6501 gen_exception(ctx, POWERPC_EXCP_VPU);
6502 return;
6503 }
6504 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6505 t = tcg_temp_new_i32();
6506 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6507 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6508 tcg_temp_free_i32(t);
6509 }
6510
6511 static void gen_mtvscr(DisasContext *ctx)
6512 {
6513 TCGv_ptr p;
6514 if (unlikely(!ctx->altivec_enabled)) {
6515 gen_exception(ctx, POWERPC_EXCP_VPU);
6516 return;
6517 }
6518 p = gen_avr_ptr(rD(ctx->opcode));
6519 gen_helper_mtvscr(cpu_env, p);
6520 tcg_temp_free_ptr(p);
6521 }
6522
6523 /* Logical operations */
6524 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6525 static void glue(gen_, name)(DisasContext *ctx) \
6526 { \
6527 if (unlikely(!ctx->altivec_enabled)) { \
6528 gen_exception(ctx, POWERPC_EXCP_VPU); \
6529 return; \
6530 } \
6531 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6532 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6533 }
6534
6535 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6536 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6537 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6538 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6539 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6540
6541 #define GEN_VXFORM(name, opc2, opc3) \
6542 static void glue(gen_, name)(DisasContext *ctx) \
6543 { \
6544 TCGv_ptr ra, rb, rd; \
6545 if (unlikely(!ctx->altivec_enabled)) { \
6546 gen_exception(ctx, POWERPC_EXCP_VPU); \
6547 return; \
6548 } \
6549 ra = gen_avr_ptr(rA(ctx->opcode)); \
6550 rb = gen_avr_ptr(rB(ctx->opcode)); \
6551 rd = gen_avr_ptr(rD(ctx->opcode)); \
6552 gen_helper_##name (rd, ra, rb); \
6553 tcg_temp_free_ptr(ra); \
6554 tcg_temp_free_ptr(rb); \
6555 tcg_temp_free_ptr(rd); \
6556 }
6557
6558 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6559 static void glue(gen_, name)(DisasContext *ctx) \
6560 { \
6561 TCGv_ptr ra, rb, rd; \
6562 if (unlikely(!ctx->altivec_enabled)) { \
6563 gen_exception(ctx, POWERPC_EXCP_VPU); \
6564 return; \
6565 } \
6566 ra = gen_avr_ptr(rA(ctx->opcode)); \
6567 rb = gen_avr_ptr(rB(ctx->opcode)); \
6568 rd = gen_avr_ptr(rD(ctx->opcode)); \
6569 gen_helper_##name(cpu_env, rd, ra, rb); \
6570 tcg_temp_free_ptr(ra); \
6571 tcg_temp_free_ptr(rb); \
6572 tcg_temp_free_ptr(rd); \
6573 }
6574
6575 GEN_VXFORM(vaddubm, 0, 0);
6576 GEN_VXFORM(vadduhm, 0, 1);
6577 GEN_VXFORM(vadduwm, 0, 2);
6578 GEN_VXFORM(vsububm, 0, 16);
6579 GEN_VXFORM(vsubuhm, 0, 17);
6580 GEN_VXFORM(vsubuwm, 0, 18);
6581 GEN_VXFORM(vmaxub, 1, 0);
6582 GEN_VXFORM(vmaxuh, 1, 1);
6583 GEN_VXFORM(vmaxuw, 1, 2);
6584 GEN_VXFORM(vmaxsb, 1, 4);
6585 GEN_VXFORM(vmaxsh, 1, 5);
6586 GEN_VXFORM(vmaxsw, 1, 6);
6587 GEN_VXFORM(vminub, 1, 8);
6588 GEN_VXFORM(vminuh, 1, 9);
6589 GEN_VXFORM(vminuw, 1, 10);
6590 GEN_VXFORM(vminsb, 1, 12);
6591 GEN_VXFORM(vminsh, 1, 13);
6592 GEN_VXFORM(vminsw, 1, 14);
6593 GEN_VXFORM(vavgub, 1, 16);
6594 GEN_VXFORM(vavguh, 1, 17);
6595 GEN_VXFORM(vavguw, 1, 18);
6596 GEN_VXFORM(vavgsb, 1, 20);
6597 GEN_VXFORM(vavgsh, 1, 21);
6598 GEN_VXFORM(vavgsw, 1, 22);
6599 GEN_VXFORM(vmrghb, 6, 0);
6600 GEN_VXFORM(vmrghh, 6, 1);
6601 GEN_VXFORM(vmrghw, 6, 2);
6602 GEN_VXFORM(vmrglb, 6, 4);
6603 GEN_VXFORM(vmrglh, 6, 5);
6604 GEN_VXFORM(vmrglw, 6, 6);
6605 GEN_VXFORM(vmuloub, 4, 0);
6606 GEN_VXFORM(vmulouh, 4, 1);
6607 GEN_VXFORM(vmulosb, 4, 4);
6608 GEN_VXFORM(vmulosh, 4, 5);
6609 GEN_VXFORM(vmuleub, 4, 8);
6610 GEN_VXFORM(vmuleuh, 4, 9);
6611 GEN_VXFORM(vmulesb, 4, 12);
6612 GEN_VXFORM(vmulesh, 4, 13);
6613 GEN_VXFORM(vslb, 2, 4);
6614 GEN_VXFORM(vslh, 2, 5);
6615 GEN_VXFORM(vslw, 2, 6);
6616 GEN_VXFORM(vsrb, 2, 8);
6617 GEN_VXFORM(vsrh, 2, 9);
6618 GEN_VXFORM(vsrw, 2, 10);
6619 GEN_VXFORM(vsrab, 2, 12);
6620 GEN_VXFORM(vsrah, 2, 13);
6621 GEN_VXFORM(vsraw, 2, 14);
6622 GEN_VXFORM(vslo, 6, 16);
6623 GEN_VXFORM(vsro, 6, 17);
6624 GEN_VXFORM(vaddcuw, 0, 6);
6625 GEN_VXFORM(vsubcuw, 0, 22);
6626 GEN_VXFORM_ENV(vaddubs, 0, 8);
6627 GEN_VXFORM_ENV(vadduhs, 0, 9);
6628 GEN_VXFORM_ENV(vadduws, 0, 10);
6629 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6630 GEN_VXFORM_ENV(vaddshs, 0, 13);
6631 GEN_VXFORM_ENV(vaddsws, 0, 14);
6632 GEN_VXFORM_ENV(vsububs, 0, 24);
6633 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6634 GEN_VXFORM_ENV(vsubuws, 0, 26);
6635 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6636 GEN_VXFORM_ENV(vsubshs, 0, 29);
6637 GEN_VXFORM_ENV(vsubsws, 0, 30);
6638 GEN_VXFORM(vrlb, 2, 0);
6639 GEN_VXFORM(vrlh, 2, 1);
6640 GEN_VXFORM(vrlw, 2, 2);
6641 GEN_VXFORM(vsl, 2, 7);
6642 GEN_VXFORM(vsr, 2, 11);
6643 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6644 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6645 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6646 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6647 GEN_VXFORM_ENV(vpkshus, 7, 4);
6648 GEN_VXFORM_ENV(vpkswus, 7, 5);
6649 GEN_VXFORM_ENV(vpkshss, 7, 6);
6650 GEN_VXFORM_ENV(vpkswss, 7, 7);
6651 GEN_VXFORM(vpkpx, 7, 12);
6652 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6653 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6654 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6655 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6656 GEN_VXFORM_ENV(vsumsws, 4, 30);
6657 GEN_VXFORM_ENV(vaddfp, 5, 0);
6658 GEN_VXFORM_ENV(vsubfp, 5, 1);
6659 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6660 GEN_VXFORM_ENV(vminfp, 5, 17);
6661
6662 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6663 static void glue(gen_, name)(DisasContext *ctx) \
6664 { \
6665 TCGv_ptr ra, rb, rd; \
6666 if (unlikely(!ctx->altivec_enabled)) { \
6667 gen_exception(ctx, POWERPC_EXCP_VPU); \
6668 return; \
6669 } \
6670 ra = gen_avr_ptr(rA(ctx->opcode)); \
6671 rb = gen_avr_ptr(rB(ctx->opcode)); \
6672 rd = gen_avr_ptr(rD(ctx->opcode)); \
6673 gen_helper_##opname(cpu_env, rd, ra, rb); \
6674 tcg_temp_free_ptr(ra); \
6675 tcg_temp_free_ptr(rb); \
6676 tcg_temp_free_ptr(rd); \
6677 }
6678
6679 #define GEN_VXRFORM(name, opc2, opc3) \
6680 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6681 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6682
6683 GEN_VXRFORM(vcmpequb, 3, 0)
6684 GEN_VXRFORM(vcmpequh, 3, 1)
6685 GEN_VXRFORM(vcmpequw, 3, 2)
6686 GEN_VXRFORM(vcmpgtsb, 3, 12)
6687 GEN_VXRFORM(vcmpgtsh, 3, 13)
6688 GEN_VXRFORM(vcmpgtsw, 3, 14)
6689 GEN_VXRFORM(vcmpgtub, 3, 8)
6690 GEN_VXRFORM(vcmpgtuh, 3, 9)
6691 GEN_VXRFORM(vcmpgtuw, 3, 10)
6692 GEN_VXRFORM(vcmpeqfp, 3, 3)
6693 GEN_VXRFORM(vcmpgefp, 3, 7)
6694 GEN_VXRFORM(vcmpgtfp, 3, 11)
6695 GEN_VXRFORM(vcmpbfp, 3, 15)
6696
6697 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6698 static void glue(gen_, name)(DisasContext *ctx) \
6699 { \
6700 TCGv_ptr rd; \
6701 TCGv_i32 simm; \
6702 if (unlikely(!ctx->altivec_enabled)) { \
6703 gen_exception(ctx, POWERPC_EXCP_VPU); \
6704 return; \
6705 } \
6706 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6707 rd = gen_avr_ptr(rD(ctx->opcode)); \
6708 gen_helper_##name (rd, simm); \
6709 tcg_temp_free_i32(simm); \
6710 tcg_temp_free_ptr(rd); \
6711 }
6712
6713 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6714 GEN_VXFORM_SIMM(vspltish, 6, 13);
6715 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6716
6717 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6718 static void glue(gen_, name)(DisasContext *ctx) \
6719 { \
6720 TCGv_ptr rb, rd; \
6721 if (unlikely(!ctx->altivec_enabled)) { \
6722 gen_exception(ctx, POWERPC_EXCP_VPU); \
6723 return; \
6724 } \
6725 rb = gen_avr_ptr(rB(ctx->opcode)); \
6726 rd = gen_avr_ptr(rD(ctx->opcode)); \
6727 gen_helper_##name (rd, rb); \
6728 tcg_temp_free_ptr(rb); \
6729 tcg_temp_free_ptr(rd); \
6730 }
6731
6732 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6733 static void glue(gen_, name)(DisasContext *ctx) \
6734 { \
6735 TCGv_ptr rb, rd; \
6736 \
6737 if (unlikely(!ctx->altivec_enabled)) { \
6738 gen_exception(ctx, POWERPC_EXCP_VPU); \
6739 return; \
6740 } \
6741 rb = gen_avr_ptr(rB(ctx->opcode)); \
6742 rd = gen_avr_ptr(rD(ctx->opcode)); \
6743 gen_helper_##name(cpu_env, rd, rb); \
6744 tcg_temp_free_ptr(rb); \
6745 tcg_temp_free_ptr(rd); \
6746 }
6747
6748 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6749 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6750 GEN_VXFORM_NOA(vupklsb, 7, 10);
6751 GEN_VXFORM_NOA(vupklsh, 7, 11);
6752 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6753 GEN_VXFORM_NOA(vupklpx, 7, 15);
6754 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6755 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6756 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6757 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6758 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6759 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6760 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6761 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6762
6763 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6764 static void glue(gen_, name)(DisasContext *ctx) \
6765 { \
6766 TCGv_ptr rd; \
6767 TCGv_i32 simm; \
6768 if (unlikely(!ctx->altivec_enabled)) { \
6769 gen_exception(ctx, POWERPC_EXCP_VPU); \
6770 return; \
6771 } \
6772 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6773 rd = gen_avr_ptr(rD(ctx->opcode)); \
6774 gen_helper_##name (rd, simm); \
6775 tcg_temp_free_i32(simm); \
6776 tcg_temp_free_ptr(rd); \
6777 }
6778
6779 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6780 static void glue(gen_, name)(DisasContext *ctx) \
6781 { \
6782 TCGv_ptr rb, rd; \
6783 TCGv_i32 uimm; \
6784 if (unlikely(!ctx->altivec_enabled)) { \
6785 gen_exception(ctx, POWERPC_EXCP_VPU); \
6786 return; \
6787 } \
6788 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6789 rb = gen_avr_ptr(rB(ctx->opcode)); \
6790 rd = gen_avr_ptr(rD(ctx->opcode)); \
6791 gen_helper_##name (rd, rb, uimm); \
6792 tcg_temp_free_i32(uimm); \
6793 tcg_temp_free_ptr(rb); \
6794 tcg_temp_free_ptr(rd); \
6795 }
6796
6797 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6798 static void glue(gen_, name)(DisasContext *ctx) \
6799 { \
6800 TCGv_ptr rb, rd; \
6801 TCGv_i32 uimm; \
6802 \
6803 if (unlikely(!ctx->altivec_enabled)) { \
6804 gen_exception(ctx, POWERPC_EXCP_VPU); \
6805 return; \
6806 } \
6807 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6808 rb = gen_avr_ptr(rB(ctx->opcode)); \
6809 rd = gen_avr_ptr(rD(ctx->opcode)); \
6810 gen_helper_##name(cpu_env, rd, rb, uimm); \
6811 tcg_temp_free_i32(uimm); \
6812 tcg_temp_free_ptr(rb); \
6813 tcg_temp_free_ptr(rd); \
6814 }
6815
6816 GEN_VXFORM_UIMM(vspltb, 6, 8);
6817 GEN_VXFORM_UIMM(vsplth, 6, 9);
6818 GEN_VXFORM_UIMM(vspltw, 6, 10);
6819 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6820 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6821 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6822 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6823
6824 static void gen_vsldoi(DisasContext *ctx)
6825 {
6826 TCGv_ptr ra, rb, rd;
6827 TCGv_i32 sh;
6828 if (unlikely(!ctx->altivec_enabled)) {
6829 gen_exception(ctx, POWERPC_EXCP_VPU);
6830 return;
6831 }
6832 ra = gen_avr_ptr(rA(ctx->opcode));
6833 rb = gen_avr_ptr(rB(ctx->opcode));
6834 rd = gen_avr_ptr(rD(ctx->opcode));
6835 sh = tcg_const_i32(VSH(ctx->opcode));
6836 gen_helper_vsldoi (rd, ra, rb, sh);
6837 tcg_temp_free_ptr(ra);
6838 tcg_temp_free_ptr(rb);
6839 tcg_temp_free_ptr(rd);
6840 tcg_temp_free_i32(sh);
6841 }
6842
6843 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6844 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6845 { \
6846 TCGv_ptr ra, rb, rc, rd; \
6847 if (unlikely(!ctx->altivec_enabled)) { \
6848 gen_exception(ctx, POWERPC_EXCP_VPU); \
6849 return; \
6850 } \
6851 ra = gen_avr_ptr(rA(ctx->opcode)); \
6852 rb = gen_avr_ptr(rB(ctx->opcode)); \
6853 rc = gen_avr_ptr(rC(ctx->opcode)); \
6854 rd = gen_avr_ptr(rD(ctx->opcode)); \
6855 if (Rc(ctx->opcode)) { \
6856 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6857 } else { \
6858 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6859 } \
6860 tcg_temp_free_ptr(ra); \
6861 tcg_temp_free_ptr(rb); \
6862 tcg_temp_free_ptr(rc); \
6863 tcg_temp_free_ptr(rd); \
6864 }
6865
6866 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6867
6868 static void gen_vmladduhm(DisasContext *ctx)
6869 {
6870 TCGv_ptr ra, rb, rc, rd;
6871 if (unlikely(!ctx->altivec_enabled)) {
6872 gen_exception(ctx, POWERPC_EXCP_VPU);
6873 return;
6874 }
6875 ra = gen_avr_ptr(rA(ctx->opcode));
6876 rb = gen_avr_ptr(rB(ctx->opcode));
6877 rc = gen_avr_ptr(rC(ctx->opcode));
6878 rd = gen_avr_ptr(rD(ctx->opcode));
6879 gen_helper_vmladduhm(rd, ra, rb, rc);
6880 tcg_temp_free_ptr(ra);
6881 tcg_temp_free_ptr(rb);
6882 tcg_temp_free_ptr(rc);
6883 tcg_temp_free_ptr(rd);
6884 }
6885
6886 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6887 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6888 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6889 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6890 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6891
6892 /*** SPE extension ***/
6893 /* Register moves */
6894
6895
6896 static inline void gen_evmra(DisasContext *ctx)
6897 {
6898
6899 if (unlikely(!ctx->spe_enabled)) {
6900 gen_exception(ctx, POWERPC_EXCP_SPEU);
6901 return;
6902 }
6903
6904 #if defined(TARGET_PPC64)
6905 /* rD := rA */
6906 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6907
6908 /* spe_acc := rA */
6909 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6910 cpu_env,
6911 offsetof(CPUPPCState, spe_acc));
6912 #else
6913 TCGv_i64 tmp = tcg_temp_new_i64();
6914
6915 /* tmp := rA_lo + rA_hi << 32 */
6916 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6917
6918 /* spe_acc := tmp */
6919 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6920 tcg_temp_free_i64(tmp);
6921
6922 /* rD := rA */
6923 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6924 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6925 #endif
6926 }
6927
6928 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6929 {
6930 #if defined(TARGET_PPC64)
6931 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6932 #else
6933 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6934 #endif
6935 }
6936
6937 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6938 {
6939 #if defined(TARGET_PPC64)
6940 tcg_gen_mov_i64(cpu_gpr[reg], t);
6941 #else
6942 TCGv_i64 tmp = tcg_temp_new_i64();
6943 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6944 tcg_gen_shri_i64(tmp, t, 32);
6945 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6946 tcg_temp_free_i64(tmp);
6947 #endif
6948 }
6949
6950 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6951 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6952 { \
6953 if (Rc(ctx->opcode)) \
6954 gen_##name1(ctx); \
6955 else \
6956 gen_##name0(ctx); \
6957 }
6958
6959 /* Handler for undefined SPE opcodes */
6960 static inline void gen_speundef(DisasContext *ctx)
6961 {
6962 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6963 }
6964
6965 /* SPE logic */
6966 #if defined(TARGET_PPC64)
6967 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6968 static inline void gen_##name(DisasContext *ctx) \
6969 { \
6970 if (unlikely(!ctx->spe_enabled)) { \
6971 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6972 return; \
6973 } \
6974 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6975 cpu_gpr[rB(ctx->opcode)]); \
6976 }
6977 #else
6978 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6979 static inline void gen_##name(DisasContext *ctx) \
6980 { \
6981 if (unlikely(!ctx->spe_enabled)) { \
6982 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6983 return; \
6984 } \
6985 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6986 cpu_gpr[rB(ctx->opcode)]); \
6987 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6988 cpu_gprh[rB(ctx->opcode)]); \
6989 }
6990 #endif
6991
6992 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6993 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6994 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6995 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6996 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6997 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6998 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6999 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
7000
7001 /* SPE logic immediate */
7002 #if defined(TARGET_PPC64)
7003 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7004 static inline void gen_##name(DisasContext *ctx) \
7005 { \
7006 if (unlikely(!ctx->spe_enabled)) { \
7007 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7008 return; \
7009 } \
7010 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7011 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7012 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7013 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7014 tcg_opi(t0, t0, rB(ctx->opcode)); \
7015 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7016 tcg_gen_trunc_i64_i32(t1, t2); \
7017 tcg_temp_free_i64(t2); \
7018 tcg_opi(t1, t1, rB(ctx->opcode)); \
7019 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7020 tcg_temp_free_i32(t0); \
7021 tcg_temp_free_i32(t1); \
7022 }
7023 #else
7024 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7025 static inline void gen_##name(DisasContext *ctx) \
7026 { \
7027 if (unlikely(!ctx->spe_enabled)) { \
7028 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7029 return; \
7030 } \
7031 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7032 rB(ctx->opcode)); \
7033 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7034 rB(ctx->opcode)); \
7035 }
7036 #endif
7037 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
7038 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
7039 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
7040 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
7041
7042 /* SPE arithmetic */
7043 #if defined(TARGET_PPC64)
7044 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7045 static inline void gen_##name(DisasContext *ctx) \
7046 { \
7047 if (unlikely(!ctx->spe_enabled)) { \
7048 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7049 return; \
7050 } \
7051 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7052 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7053 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7054 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7055 tcg_op(t0, t0); \
7056 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7057 tcg_gen_trunc_i64_i32(t1, t2); \
7058 tcg_temp_free_i64(t2); \
7059 tcg_op(t1, t1); \
7060 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7061 tcg_temp_free_i32(t0); \
7062 tcg_temp_free_i32(t1); \
7063 }
7064 #else
7065 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7066 static inline void gen_##name(DisasContext *ctx) \
7067 { \
7068 if (unlikely(!ctx->spe_enabled)) { \
7069 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7070 return; \
7071 } \
7072 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7073 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7074 }
7075 #endif
7076
7077 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
7078 {
7079 int l1 = gen_new_label();
7080 int l2 = gen_new_label();
7081
7082 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
7083 tcg_gen_neg_i32(ret, arg1);
7084 tcg_gen_br(l2);
7085 gen_set_label(l1);
7086 tcg_gen_mov_i32(ret, arg1);
7087 gen_set_label(l2);
7088 }
7089 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7090 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7091 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7092 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7093 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7094 {
7095 tcg_gen_addi_i32(ret, arg1, 0x8000);
7096 tcg_gen_ext16u_i32(ret, ret);
7097 }
7098 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7099 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7100 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7101
7102 #if defined(TARGET_PPC64)
7103 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7104 static inline void gen_##name(DisasContext *ctx) \
7105 { \
7106 if (unlikely(!ctx->spe_enabled)) { \
7107 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7108 return; \
7109 } \
7110 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7111 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7112 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7113 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7114 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7115 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7116 tcg_op(t0, t0, t2); \
7117 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7118 tcg_gen_trunc_i64_i32(t1, t3); \
7119 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7120 tcg_gen_trunc_i64_i32(t2, t3); \
7121 tcg_temp_free_i64(t3); \
7122 tcg_op(t1, t1, t2); \
7123 tcg_temp_free_i32(t2); \
7124 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7125 tcg_temp_free_i32(t0); \
7126 tcg_temp_free_i32(t1); \
7127 }
7128 #else
7129 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7130 static inline void gen_##name(DisasContext *ctx) \
7131 { \
7132 if (unlikely(!ctx->spe_enabled)) { \
7133 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7134 return; \
7135 } \
7136 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7137 cpu_gpr[rB(ctx->opcode)]); \
7138 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7139 cpu_gprh[rB(ctx->opcode)]); \
7140 }
7141 #endif
7142
7143 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7144 {
7145 TCGv_i32 t0;
7146 int l1, l2;
7147
7148 l1 = gen_new_label();
7149 l2 = gen_new_label();
7150 t0 = tcg_temp_local_new_i32();
7151 /* No error here: 6 bits are used */
7152 tcg_gen_andi_i32(t0, arg2, 0x3F);
7153 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7154 tcg_gen_shr_i32(ret, arg1, t0);
7155 tcg_gen_br(l2);
7156 gen_set_label(l1);
7157 tcg_gen_movi_i32(ret, 0);
7158 gen_set_label(l2);
7159 tcg_temp_free_i32(t0);
7160 }
7161 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7162 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7163 {
7164 TCGv_i32 t0;
7165 int l1, l2;
7166
7167 l1 = gen_new_label();
7168 l2 = gen_new_label();
7169 t0 = tcg_temp_local_new_i32();
7170 /* No error here: 6 bits are used */
7171 tcg_gen_andi_i32(t0, arg2, 0x3F);
7172 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7173 tcg_gen_sar_i32(ret, arg1, t0);
7174 tcg_gen_br(l2);
7175 gen_set_label(l1);
7176 tcg_gen_movi_i32(ret, 0);
7177 gen_set_label(l2);
7178 tcg_temp_free_i32(t0);
7179 }
7180 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7181 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7182 {
7183 TCGv_i32 t0;
7184 int l1, l2;
7185
7186 l1 = gen_new_label();
7187 l2 = gen_new_label();
7188 t0 = tcg_temp_local_new_i32();
7189 /* No error here: 6 bits are used */
7190 tcg_gen_andi_i32(t0, arg2, 0x3F);
7191 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7192 tcg_gen_shl_i32(ret, arg1, t0);
7193 tcg_gen_br(l2);
7194 gen_set_label(l1);
7195 tcg_gen_movi_i32(ret, 0);
7196 gen_set_label(l2);
7197 tcg_temp_free_i32(t0);
7198 }
7199 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7200 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7201 {
7202 TCGv_i32 t0 = tcg_temp_new_i32();
7203 tcg_gen_andi_i32(t0, arg2, 0x1F);
7204 tcg_gen_rotl_i32(ret, arg1, t0);
7205 tcg_temp_free_i32(t0);
7206 }
7207 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7208 static inline void gen_evmergehi(DisasContext *ctx)
7209 {
7210 if (unlikely(!ctx->spe_enabled)) {
7211 gen_exception(ctx, POWERPC_EXCP_SPEU);
7212 return;
7213 }
7214 #if defined(TARGET_PPC64)
7215 TCGv t0 = tcg_temp_new();
7216 TCGv t1 = tcg_temp_new();
7217 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7218 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7219 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7220 tcg_temp_free(t0);
7221 tcg_temp_free(t1);
7222 #else
7223 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7224 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7225 #endif
7226 }
7227 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7228 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7229 {
7230 tcg_gen_sub_i32(ret, arg2, arg1);
7231 }
7232 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7233
7234 /* SPE arithmetic immediate */
7235 #if defined(TARGET_PPC64)
7236 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7237 static inline void gen_##name(DisasContext *ctx) \
7238 { \
7239 if (unlikely(!ctx->spe_enabled)) { \
7240 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7241 return; \
7242 } \
7243 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7244 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7245 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7246 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7247 tcg_op(t0, t0, rA(ctx->opcode)); \
7248 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7249 tcg_gen_trunc_i64_i32(t1, t2); \
7250 tcg_temp_free_i64(t2); \
7251 tcg_op(t1, t1, rA(ctx->opcode)); \
7252 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7253 tcg_temp_free_i32(t0); \
7254 tcg_temp_free_i32(t1); \
7255 }
7256 #else
7257 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7258 static inline void gen_##name(DisasContext *ctx) \
7259 { \
7260 if (unlikely(!ctx->spe_enabled)) { \
7261 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7262 return; \
7263 } \
7264 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7265 rA(ctx->opcode)); \
7266 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7267 rA(ctx->opcode)); \
7268 }
7269 #endif
7270 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7271 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7272
7273 /* SPE comparison */
7274 #if defined(TARGET_PPC64)
7275 #define GEN_SPEOP_COMP(name, tcg_cond) \
7276 static inline void gen_##name(DisasContext *ctx) \
7277 { \
7278 if (unlikely(!ctx->spe_enabled)) { \
7279 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7280 return; \
7281 } \
7282 int l1 = gen_new_label(); \
7283 int l2 = gen_new_label(); \
7284 int l3 = gen_new_label(); \
7285 int l4 = gen_new_label(); \
7286 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7287 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7288 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7289 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7290 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7291 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7292 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7293 tcg_gen_br(l2); \
7294 gen_set_label(l1); \
7295 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7296 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7297 gen_set_label(l2); \
7298 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7299 tcg_gen_trunc_i64_i32(t0, t2); \
7300 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7301 tcg_gen_trunc_i64_i32(t1, t2); \
7302 tcg_temp_free_i64(t2); \
7303 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7304 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7305 ~(CRF_CH | CRF_CH_AND_CL)); \
7306 tcg_gen_br(l4); \
7307 gen_set_label(l3); \
7308 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7309 CRF_CH | CRF_CH_OR_CL); \
7310 gen_set_label(l4); \
7311 tcg_temp_free_i32(t0); \
7312 tcg_temp_free_i32(t1); \
7313 }
7314 #else
7315 #define GEN_SPEOP_COMP(name, tcg_cond) \
7316 static inline void gen_##name(DisasContext *ctx) \
7317 { \
7318 if (unlikely(!ctx->spe_enabled)) { \
7319 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7320 return; \
7321 } \
7322 int l1 = gen_new_label(); \
7323 int l2 = gen_new_label(); \
7324 int l3 = gen_new_label(); \
7325 int l4 = gen_new_label(); \
7326 \
7327 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7328 cpu_gpr[rB(ctx->opcode)], l1); \
7329 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7330 tcg_gen_br(l2); \
7331 gen_set_label(l1); \
7332 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7333 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7334 gen_set_label(l2); \
7335 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7336 cpu_gprh[rB(ctx->opcode)], l3); \
7337 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7338 ~(CRF_CH | CRF_CH_AND_CL)); \
7339 tcg_gen_br(l4); \
7340 gen_set_label(l3); \
7341 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7342 CRF_CH | CRF_CH_OR_CL); \
7343 gen_set_label(l4); \
7344 }
7345 #endif
7346 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7347 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7348 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7349 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7350 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7351
7352 /* SPE misc */
7353 static inline void gen_brinc(DisasContext *ctx)
7354 {
7355 /* Note: brinc is usable even if SPE is disabled */
7356 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7357 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7358 }
7359 static inline void gen_evmergelo(DisasContext *ctx)
7360 {
7361 if (unlikely(!ctx->spe_enabled)) {
7362 gen_exception(ctx, POWERPC_EXCP_SPEU);
7363 return;
7364 }
7365 #if defined(TARGET_PPC64)
7366 TCGv t0 = tcg_temp_new();
7367 TCGv t1 = tcg_temp_new();
7368 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7369 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7370 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7371 tcg_temp_free(t0);
7372 tcg_temp_free(t1);
7373 #else
7374 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7375 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7376 #endif
7377 }
7378 static inline void gen_evmergehilo(DisasContext *ctx)
7379 {
7380 if (unlikely(!ctx->spe_enabled)) {
7381 gen_exception(ctx, POWERPC_EXCP_SPEU);
7382 return;
7383 }
7384 #if defined(TARGET_PPC64)
7385 TCGv t0 = tcg_temp_new();
7386 TCGv t1 = tcg_temp_new();
7387 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7388 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7389 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7390 tcg_temp_free(t0);
7391 tcg_temp_free(t1);
7392 #else
7393 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7394 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7395 #endif
7396 }
7397 static inline void gen_evmergelohi(DisasContext *ctx)
7398 {
7399 if (unlikely(!ctx->spe_enabled)) {
7400 gen_exception(ctx, POWERPC_EXCP_SPEU);
7401 return;
7402 }
7403 #if defined(TARGET_PPC64)
7404 TCGv t0 = tcg_temp_new();
7405 TCGv t1 = tcg_temp_new();
7406 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7407 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7408 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7409 tcg_temp_free(t0);
7410 tcg_temp_free(t1);
7411 #else
7412 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7413 TCGv_i32 tmp = tcg_temp_new_i32();
7414 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7415 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7416 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7417 tcg_temp_free_i32(tmp);
7418 } else {
7419 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7420 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7421 }
7422 #endif
7423 }
7424 static inline void gen_evsplati(DisasContext *ctx)
7425 {
7426 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7427
7428 #if defined(TARGET_PPC64)
7429 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7430 #else
7431 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7432 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7433 #endif
7434 }
7435 static inline void gen_evsplatfi(DisasContext *ctx)
7436 {
7437 uint64_t imm = rA(ctx->opcode) << 27;
7438
7439 #if defined(TARGET_PPC64)
7440 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7441 #else
7442 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7443 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7444 #endif
7445 }
7446
7447 static inline void gen_evsel(DisasContext *ctx)
7448 {
7449 int l1 = gen_new_label();
7450 int l2 = gen_new_label();
7451 int l3 = gen_new_label();
7452 int l4 = gen_new_label();
7453 TCGv_i32 t0 = tcg_temp_local_new_i32();
7454 #if defined(TARGET_PPC64)
7455 TCGv t1 = tcg_temp_local_new();
7456 TCGv t2 = tcg_temp_local_new();
7457 #endif
7458 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7459 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7460 #if defined(TARGET_PPC64)
7461 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7462 #else
7463 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7464 #endif
7465 tcg_gen_br(l2);
7466 gen_set_label(l1);
7467 #if defined(TARGET_PPC64)
7468 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7469 #else
7470 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7471 #endif
7472 gen_set_label(l2);
7473 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7474 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7475 #if defined(TARGET_PPC64)
7476 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7477 #else
7478 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7479 #endif
7480 tcg_gen_br(l4);
7481 gen_set_label(l3);
7482 #if defined(TARGET_PPC64)
7483 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7484 #else
7485 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7486 #endif
7487 gen_set_label(l4);
7488 tcg_temp_free_i32(t0);
7489 #if defined(TARGET_PPC64)
7490 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7491 tcg_temp_free(t1);
7492 tcg_temp_free(t2);
7493 #endif
7494 }
7495
7496 static void gen_evsel0(DisasContext *ctx)
7497 {
7498 gen_evsel(ctx);
7499 }
7500
7501 static void gen_evsel1(DisasContext *ctx)
7502 {
7503 gen_evsel(ctx);
7504 }
7505
7506 static void gen_evsel2(DisasContext *ctx)
7507 {
7508 gen_evsel(ctx);
7509 }
7510
7511 static void gen_evsel3(DisasContext *ctx)
7512 {
7513 gen_evsel(ctx);
7514 }
7515
7516 /* Multiply */
7517
7518 static inline void gen_evmwumi(DisasContext *ctx)
7519 {
7520 TCGv_i64 t0, t1;
7521
7522 if (unlikely(!ctx->spe_enabled)) {
7523 gen_exception(ctx, POWERPC_EXCP_SPEU);
7524 return;
7525 }
7526
7527 t0 = tcg_temp_new_i64();
7528 t1 = tcg_temp_new_i64();
7529
7530 /* t0 := rA; t1 := rB */
7531 #if defined(TARGET_PPC64)
7532 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7533 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7534 #else
7535 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7536 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7537 #endif
7538
7539 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7540
7541 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7542
7543 tcg_temp_free_i64(t0);
7544 tcg_temp_free_i64(t1);
7545 }
7546
7547 static inline void gen_evmwumia(DisasContext *ctx)
7548 {
7549 TCGv_i64 tmp;
7550
7551 if (unlikely(!ctx->spe_enabled)) {
7552 gen_exception(ctx, POWERPC_EXCP_SPEU);
7553 return;
7554 }
7555
7556 gen_evmwumi(ctx); /* rD := rA * rB */
7557
7558 tmp = tcg_temp_new_i64();
7559
7560 /* acc := rD */
7561 gen_load_gpr64(tmp, rD(ctx->opcode));
7562 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7563 tcg_temp_free_i64(tmp);
7564 }
7565
7566 static inline void gen_evmwumiaa(DisasContext *ctx)
7567 {
7568 TCGv_i64 acc;
7569 TCGv_i64 tmp;
7570
7571 if (unlikely(!ctx->spe_enabled)) {
7572 gen_exception(ctx, POWERPC_EXCP_SPEU);
7573 return;
7574 }
7575
7576 gen_evmwumi(ctx); /* rD := rA * rB */
7577
7578 acc = tcg_temp_new_i64();
7579 tmp = tcg_temp_new_i64();
7580
7581 /* tmp := rD */
7582 gen_load_gpr64(tmp, rD(ctx->opcode));
7583
7584 /* Load acc */
7585 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7586
7587 /* acc := tmp + acc */
7588 tcg_gen_add_i64(acc, acc, tmp);
7589
7590 /* Store acc */
7591 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7592
7593 /* rD := acc */
7594 gen_store_gpr64(rD(ctx->opcode), acc);
7595
7596 tcg_temp_free_i64(acc);
7597 tcg_temp_free_i64(tmp);
7598 }
7599
7600 static inline void gen_evmwsmi(DisasContext *ctx)
7601 {
7602 TCGv_i64 t0, t1;
7603
7604 if (unlikely(!ctx->spe_enabled)) {
7605 gen_exception(ctx, POWERPC_EXCP_SPEU);
7606 return;
7607 }
7608
7609 t0 = tcg_temp_new_i64();
7610 t1 = tcg_temp_new_i64();
7611
7612 /* t0 := rA; t1 := rB */
7613 #if defined(TARGET_PPC64)
7614 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7615 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7616 #else
7617 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7618 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7619 #endif
7620
7621 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7622
7623 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7624
7625 tcg_temp_free_i64(t0);
7626 tcg_temp_free_i64(t1);
7627 }
7628
7629 static inline void gen_evmwsmia(DisasContext *ctx)
7630 {
7631 TCGv_i64 tmp;
7632
7633 gen_evmwsmi(ctx); /* rD := rA * rB */
7634
7635 tmp = tcg_temp_new_i64();
7636
7637 /* acc := rD */
7638 gen_load_gpr64(tmp, rD(ctx->opcode));
7639 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7640
7641 tcg_temp_free_i64(tmp);
7642 }
7643
7644 static inline void gen_evmwsmiaa(DisasContext *ctx)
7645 {
7646 TCGv_i64 acc = tcg_temp_new_i64();
7647 TCGv_i64 tmp = tcg_temp_new_i64();
7648
7649 gen_evmwsmi(ctx); /* rD := rA * rB */
7650
7651 acc = tcg_temp_new_i64();
7652 tmp = tcg_temp_new_i64();
7653
7654 /* tmp := rD */
7655 gen_load_gpr64(tmp, rD(ctx->opcode));
7656
7657 /* Load acc */
7658 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7659
7660 /* acc := tmp + acc */
7661 tcg_gen_add_i64(acc, acc, tmp);
7662
7663 /* Store acc */
7664 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7665
7666 /* rD := acc */
7667 gen_store_gpr64(rD(ctx->opcode), acc);
7668
7669 tcg_temp_free_i64(acc);
7670 tcg_temp_free_i64(tmp);
7671 }
7672
7673 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7674 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7675 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7676 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7677 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7678 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7679 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7680 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7681 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7682 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7683 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7684 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7685 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7686 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7687 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7688 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7689 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7690 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7691 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7692 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7693 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7694 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7695 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7696 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7697 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7698 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7699 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7700 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7701 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7702
7703 /* SPE load and stores */
7704 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7705 {
7706 target_ulong uimm = rB(ctx->opcode);
7707
7708 if (rA(ctx->opcode) == 0) {
7709 tcg_gen_movi_tl(EA, uimm << sh);
7710 } else {
7711 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7712 #if defined(TARGET_PPC64)
7713 if (!ctx->sf_mode) {
7714 tcg_gen_ext32u_tl(EA, EA);
7715 }
7716 #endif
7717 }
7718 }
7719
7720 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7721 {
7722 #if defined(TARGET_PPC64)
7723 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7724 #else
7725 TCGv_i64 t0 = tcg_temp_new_i64();
7726 gen_qemu_ld64(ctx, t0, addr);
7727 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7728 tcg_gen_shri_i64(t0, t0, 32);
7729 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7730 tcg_temp_free_i64(t0);
7731 #endif
7732 }
7733
7734 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7735 {
7736 #if defined(TARGET_PPC64)
7737 TCGv t0 = tcg_temp_new();
7738 gen_qemu_ld32u(ctx, t0, addr);
7739 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7740 gen_addr_add(ctx, addr, addr, 4);
7741 gen_qemu_ld32u(ctx, t0, addr);
7742 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7743 tcg_temp_free(t0);
7744 #else
7745 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7746 gen_addr_add(ctx, addr, addr, 4);
7747 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7748 #endif
7749 }
7750
7751 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7752 {
7753 TCGv t0 = tcg_temp_new();
7754 #if defined(TARGET_PPC64)
7755 gen_qemu_ld16u(ctx, t0, addr);
7756 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7757 gen_addr_add(ctx, addr, addr, 2);
7758 gen_qemu_ld16u(ctx, t0, addr);
7759 tcg_gen_shli_tl(t0, t0, 32);
7760 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7761 gen_addr_add(ctx, addr, addr, 2);
7762 gen_qemu_ld16u(ctx, t0, addr);
7763 tcg_gen_shli_tl(t0, t0, 16);
7764 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7765 gen_addr_add(ctx, addr, addr, 2);
7766 gen_qemu_ld16u(ctx, t0, addr);
7767 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7768 #else
7769 gen_qemu_ld16u(ctx, t0, addr);
7770 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7771 gen_addr_add(ctx, addr, addr, 2);
7772 gen_qemu_ld16u(ctx, t0, addr);
7773 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7774 gen_addr_add(ctx, addr, addr, 2);
7775 gen_qemu_ld16u(ctx, t0, addr);
7776 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7777 gen_addr_add(ctx, addr, addr, 2);
7778 gen_qemu_ld16u(ctx, t0, addr);
7779 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7780 #endif
7781 tcg_temp_free(t0);
7782 }
7783
7784 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7785 {
7786 TCGv t0 = tcg_temp_new();
7787 gen_qemu_ld16u(ctx, t0, addr);
7788 #if defined(TARGET_PPC64)
7789 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7790 tcg_gen_shli_tl(t0, t0, 16);
7791 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7792 #else
7793 tcg_gen_shli_tl(t0, t0, 16);
7794 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7795 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7796 #endif
7797 tcg_temp_free(t0);
7798 }
7799
7800 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7801 {
7802 TCGv t0 = tcg_temp_new();
7803 gen_qemu_ld16u(ctx, t0, addr);
7804 #if defined(TARGET_PPC64)
7805 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7806 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7807 #else
7808 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7809 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7810 #endif
7811 tcg_temp_free(t0);
7812 }
7813
7814 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7815 {
7816 TCGv t0 = tcg_temp_new();
7817 gen_qemu_ld16s(ctx, t0, addr);
7818 #if defined(TARGET_PPC64)
7819 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7820 tcg_gen_ext32u_tl(t0, t0);
7821 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7822 #else
7823 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7824 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7825 #endif
7826 tcg_temp_free(t0);
7827 }
7828
7829 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7830 {
7831 TCGv t0 = tcg_temp_new();
7832 #if defined(TARGET_PPC64)
7833 gen_qemu_ld16u(ctx, t0, addr);
7834 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7835 gen_addr_add(ctx, addr, addr, 2);
7836 gen_qemu_ld16u(ctx, t0, addr);
7837 tcg_gen_shli_tl(t0, t0, 16);
7838 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7839 #else
7840 gen_qemu_ld16u(ctx, t0, addr);
7841 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7842 gen_addr_add(ctx, addr, addr, 2);
7843 gen_qemu_ld16u(ctx, t0, addr);
7844 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7845 #endif
7846 tcg_temp_free(t0);
7847 }
7848
7849 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7850 {
7851 #if defined(TARGET_PPC64)
7852 TCGv t0 = tcg_temp_new();
7853 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7854 gen_addr_add(ctx, addr, addr, 2);
7855 gen_qemu_ld16u(ctx, t0, addr);
7856 tcg_gen_shli_tl(t0, t0, 32);
7857 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7858 tcg_temp_free(t0);
7859 #else
7860 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7861 gen_addr_add(ctx, addr, addr, 2);
7862 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7863 #endif
7864 }
7865
7866 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7867 {
7868 #if defined(TARGET_PPC64)
7869 TCGv t0 = tcg_temp_new();
7870 gen_qemu_ld16s(ctx, t0, addr);
7871 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7872 gen_addr_add(ctx, addr, addr, 2);
7873 gen_qemu_ld16s(ctx, t0, addr);
7874 tcg_gen_shli_tl(t0, t0, 32);
7875 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7876 tcg_temp_free(t0);
7877 #else
7878 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7879 gen_addr_add(ctx, addr, addr, 2);
7880 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7881 #endif
7882 }
7883
7884 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7885 {
7886 TCGv t0 = tcg_temp_new();
7887 gen_qemu_ld32u(ctx, t0, addr);
7888 #if defined(TARGET_PPC64)
7889 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7890 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7891 #else
7892 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7893 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7894 #endif
7895 tcg_temp_free(t0);
7896 }
7897
7898 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7899 {
7900 TCGv t0 = tcg_temp_new();
7901 #if defined(TARGET_PPC64)
7902 gen_qemu_ld16u(ctx, t0, addr);
7903 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7904 tcg_gen_shli_tl(t0, t0, 32);
7905 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7906 gen_addr_add(ctx, addr, addr, 2);
7907 gen_qemu_ld16u(ctx, t0, addr);
7908 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7909 tcg_gen_shli_tl(t0, t0, 16);
7910 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7911 #else
7912 gen_qemu_ld16u(ctx, t0, addr);
7913 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7914 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7915 gen_addr_add(ctx, addr, addr, 2);
7916 gen_qemu_ld16u(ctx, t0, addr);
7917 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7918 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7919 #endif
7920 tcg_temp_free(t0);
7921 }
7922
7923 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7924 {
7925 #if defined(TARGET_PPC64)
7926 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7927 #else
7928 TCGv_i64 t0 = tcg_temp_new_i64();
7929 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7930 gen_qemu_st64(ctx, t0, addr);
7931 tcg_temp_free_i64(t0);
7932 #endif
7933 }
7934
7935 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7936 {
7937 #if defined(TARGET_PPC64)
7938 TCGv t0 = tcg_temp_new();
7939 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7940 gen_qemu_st32(ctx, t0, addr);
7941 tcg_temp_free(t0);
7942 #else
7943 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7944 #endif
7945 gen_addr_add(ctx, addr, addr, 4);
7946 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7947 }
7948
7949 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7950 {
7951 TCGv t0 = tcg_temp_new();
7952 #if defined(TARGET_PPC64)
7953 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7954 #else
7955 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7956 #endif
7957 gen_qemu_st16(ctx, t0, addr);
7958 gen_addr_add(ctx, addr, addr, 2);
7959 #if defined(TARGET_PPC64)
7960 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7961 gen_qemu_st16(ctx, t0, addr);
7962 #else
7963 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7964 #endif
7965 gen_addr_add(ctx, addr, addr, 2);
7966 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7967 gen_qemu_st16(ctx, t0, addr);
7968 tcg_temp_free(t0);
7969 gen_addr_add(ctx, addr, addr, 2);
7970 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7971 }
7972
7973 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7974 {
7975 TCGv t0 = tcg_temp_new();
7976 #if defined(TARGET_PPC64)
7977 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7978 #else
7979 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7980 #endif
7981 gen_qemu_st16(ctx, t0, addr);
7982 gen_addr_add(ctx, addr, addr, 2);
7983 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7984 gen_qemu_st16(ctx, t0, addr);
7985 tcg_temp_free(t0);
7986 }
7987
7988 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7989 {
7990 #if defined(TARGET_PPC64)
7991 TCGv t0 = tcg_temp_new();
7992 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7993 gen_qemu_st16(ctx, t0, addr);
7994 tcg_temp_free(t0);
7995 #else
7996 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7997 #endif
7998 gen_addr_add(ctx, addr, addr, 2);
7999 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8000 }
8001
8002 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
8003 {
8004 #if defined(TARGET_PPC64)
8005 TCGv t0 = tcg_temp_new();
8006 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8007 gen_qemu_st32(ctx, t0, addr);
8008 tcg_temp_free(t0);
8009 #else
8010 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8011 #endif
8012 }
8013
8014 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
8015 {
8016 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8017 }
8018
8019 #define GEN_SPEOP_LDST(name, opc2, sh) \
8020 static void glue(gen_, name)(DisasContext *ctx) \
8021 { \
8022 TCGv t0; \
8023 if (unlikely(!ctx->spe_enabled)) { \
8024 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8025 return; \
8026 } \
8027 gen_set_access_type(ctx, ACCESS_INT); \
8028 t0 = tcg_temp_new(); \
8029 if (Rc(ctx->opcode)) { \
8030 gen_addr_spe_imm_index(ctx, t0, sh); \
8031 } else { \
8032 gen_addr_reg_index(ctx, t0); \
8033 } \
8034 gen_op_##name(ctx, t0); \
8035 tcg_temp_free(t0); \
8036 }
8037
8038 GEN_SPEOP_LDST(evldd, 0x00, 3);
8039 GEN_SPEOP_LDST(evldw, 0x01, 3);
8040 GEN_SPEOP_LDST(evldh, 0x02, 3);
8041 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
8042 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
8043 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
8044 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
8045 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
8046 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
8047 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
8048 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
8049
8050 GEN_SPEOP_LDST(evstdd, 0x10, 3);
8051 GEN_SPEOP_LDST(evstdw, 0x11, 3);
8052 GEN_SPEOP_LDST(evstdh, 0x12, 3);
8053 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
8054 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
8055 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
8056 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
8057
8058 /* Multiply and add - TODO */
8059 #if 0
8060 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
8061 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8062 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8063 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8064 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8065 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8066 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8067 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8068 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8069 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8070 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8071 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8072
8073 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8074 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8075 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8076 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8077 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8078 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8079 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8080 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8081 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8082 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8083 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8084 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8085
8086 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8087 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8088 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8089 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8090 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8091
8092 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8093 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8094 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8095 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8096 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8097 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8098 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8099 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8100 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8101 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8102 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8103 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8104
8105 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8106 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8107 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8108 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8109
8110 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8111 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8112 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8113 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8114 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8115 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8116 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8117 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8118 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8119 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8120 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8121 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8122
8123 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8124 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8125 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8126 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8127 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8128 #endif
8129
8130 /*** SPE floating-point extension ***/
8131 #if defined(TARGET_PPC64)
8132 #define GEN_SPEFPUOP_CONV_32_32(name) \
8133 static inline void gen_##name(DisasContext *ctx) \
8134 { \
8135 TCGv_i32 t0; \
8136 TCGv t1; \
8137 t0 = tcg_temp_new_i32(); \
8138 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8139 gen_helper_##name(t0, cpu_env, t0); \
8140 t1 = tcg_temp_new(); \
8141 tcg_gen_extu_i32_tl(t1, t0); \
8142 tcg_temp_free_i32(t0); \
8143 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8144 0xFFFFFFFF00000000ULL); \
8145 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8146 tcg_temp_free(t1); \
8147 }
8148 #define GEN_SPEFPUOP_CONV_32_64(name) \
8149 static inline void gen_##name(DisasContext *ctx) \
8150 { \
8151 TCGv_i32 t0; \
8152 TCGv t1; \
8153 t0 = tcg_temp_new_i32(); \
8154 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8155 t1 = tcg_temp_new(); \
8156 tcg_gen_extu_i32_tl(t1, t0); \
8157 tcg_temp_free_i32(t0); \
8158 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8159 0xFFFFFFFF00000000ULL); \
8160 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8161 tcg_temp_free(t1); \
8162 }
8163 #define GEN_SPEFPUOP_CONV_64_32(name) \
8164 static inline void gen_##name(DisasContext *ctx) \
8165 { \
8166 TCGv_i32 t0 = tcg_temp_new_i32(); \
8167 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8168 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8169 tcg_temp_free_i32(t0); \
8170 }
8171 #define GEN_SPEFPUOP_CONV_64_64(name) \
8172 static inline void gen_##name(DisasContext *ctx) \
8173 { \
8174 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8175 cpu_gpr[rB(ctx->opcode)]); \
8176 }
8177 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8178 static inline void gen_##name(DisasContext *ctx) \
8179 { \
8180 TCGv_i32 t0, t1; \
8181 TCGv_i64 t2; \
8182 if (unlikely(!ctx->spe_enabled)) { \
8183 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8184 return; \
8185 } \
8186 t0 = tcg_temp_new_i32(); \
8187 t1 = tcg_temp_new_i32(); \
8188 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8189 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8190 gen_helper_##name(t0, cpu_env, t0, t1); \
8191 tcg_temp_free_i32(t1); \
8192 t2 = tcg_temp_new(); \
8193 tcg_gen_extu_i32_tl(t2, t0); \
8194 tcg_temp_free_i32(t0); \
8195 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8196 0xFFFFFFFF00000000ULL); \
8197 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8198 tcg_temp_free(t2); \
8199 }
8200 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8201 static inline void gen_##name(DisasContext *ctx) \
8202 { \
8203 if (unlikely(!ctx->spe_enabled)) { \
8204 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8205 return; \
8206 } \
8207 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8208 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8209 }
8210 #define GEN_SPEFPUOP_COMP_32(name) \
8211 static inline void gen_##name(DisasContext *ctx) \
8212 { \
8213 TCGv_i32 t0, t1; \
8214 if (unlikely(!ctx->spe_enabled)) { \
8215 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8216 return; \
8217 } \
8218 t0 = tcg_temp_new_i32(); \
8219 t1 = tcg_temp_new_i32(); \
8220 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8221 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8222 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8223 tcg_temp_free_i32(t0); \
8224 tcg_temp_free_i32(t1); \
8225 }
8226 #define GEN_SPEFPUOP_COMP_64(name) \
8227 static inline void gen_##name(DisasContext *ctx) \
8228 { \
8229 if (unlikely(!ctx->spe_enabled)) { \
8230 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8231 return; \
8232 } \
8233 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8234 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8235 }
8236 #else
8237 #define GEN_SPEFPUOP_CONV_32_32(name) \
8238 static inline void gen_##name(DisasContext *ctx) \
8239 { \
8240 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8241 cpu_gpr[rB(ctx->opcode)]); \
8242 }
8243 #define GEN_SPEFPUOP_CONV_32_64(name) \
8244 static inline void gen_##name(DisasContext *ctx) \
8245 { \
8246 TCGv_i64 t0 = tcg_temp_new_i64(); \
8247 gen_load_gpr64(t0, rB(ctx->opcode)); \
8248 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8249 tcg_temp_free_i64(t0); \
8250 }
8251 #define GEN_SPEFPUOP_CONV_64_32(name) \
8252 static inline void gen_##name(DisasContext *ctx) \
8253 { \
8254 TCGv_i64 t0 = tcg_temp_new_i64(); \
8255 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8256 gen_store_gpr64(rD(ctx->opcode), t0); \
8257 tcg_temp_free_i64(t0); \
8258 }
8259 #define GEN_SPEFPUOP_CONV_64_64(name) \
8260 static inline void gen_##name(DisasContext *ctx) \
8261 { \
8262 TCGv_i64 t0 = tcg_temp_new_i64(); \
8263 gen_load_gpr64(t0, rB(ctx->opcode)); \
8264 gen_helper_##name(t0, cpu_env, t0); \
8265 gen_store_gpr64(rD(ctx->opcode), t0); \
8266 tcg_temp_free_i64(t0); \
8267 }
8268 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8269 static inline void gen_##name(DisasContext *ctx) \
8270 { \
8271 if (unlikely(!ctx->spe_enabled)) { \
8272 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8273 return; \
8274 } \
8275 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8276 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8277 }
8278 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8279 static inline void gen_##name(DisasContext *ctx) \
8280 { \
8281 TCGv_i64 t0, t1; \
8282 if (unlikely(!ctx->spe_enabled)) { \
8283 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8284 return; \
8285 } \
8286 t0 = tcg_temp_new_i64(); \
8287 t1 = tcg_temp_new_i64(); \
8288 gen_load_gpr64(t0, rA(ctx->opcode)); \
8289 gen_load_gpr64(t1, rB(ctx->opcode)); \
8290 gen_helper_##name(t0, cpu_env, t0, t1); \
8291 gen_store_gpr64(rD(ctx->opcode), t0); \
8292 tcg_temp_free_i64(t0); \
8293 tcg_temp_free_i64(t1); \
8294 }
8295 #define GEN_SPEFPUOP_COMP_32(name) \
8296 static inline void gen_##name(DisasContext *ctx) \
8297 { \
8298 if (unlikely(!ctx->spe_enabled)) { \
8299 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8300 return; \
8301 } \
8302 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8303 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8304 }
8305 #define GEN_SPEFPUOP_COMP_64(name) \
8306 static inline void gen_##name(DisasContext *ctx) \
8307 { \
8308 TCGv_i64 t0, t1; \
8309 if (unlikely(!ctx->spe_enabled)) { \
8310 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8311 return; \
8312 } \
8313 t0 = tcg_temp_new_i64(); \
8314 t1 = tcg_temp_new_i64(); \
8315 gen_load_gpr64(t0, rA(ctx->opcode)); \
8316 gen_load_gpr64(t1, rB(ctx->opcode)); \
8317 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8318 tcg_temp_free_i64(t0); \
8319 tcg_temp_free_i64(t1); \
8320 }
8321 #endif
8322
8323 /* Single precision floating-point vectors operations */
8324 /* Arithmetic */
8325 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8326 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8327 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8328 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8329 static inline void gen_evfsabs(DisasContext *ctx)
8330 {
8331 if (unlikely(!ctx->spe_enabled)) {
8332 gen_exception(ctx, POWERPC_EXCP_SPEU);
8333 return;
8334 }
8335 #if defined(TARGET_PPC64)
8336 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8337 #else
8338 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8339 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8340 #endif
8341 }
8342 static inline void gen_evfsnabs(DisasContext *ctx)
8343 {
8344 if (unlikely(!ctx->spe_enabled)) {
8345 gen_exception(ctx, POWERPC_EXCP_SPEU);
8346 return;
8347 }
8348 #if defined(TARGET_PPC64)
8349 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8350 #else
8351 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8352 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8353 #endif
8354 }
8355 static inline void gen_evfsneg(DisasContext *ctx)
8356 {
8357 if (unlikely(!ctx->spe_enabled)) {
8358 gen_exception(ctx, POWERPC_EXCP_SPEU);
8359 return;
8360 }
8361 #if defined(TARGET_PPC64)
8362 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8363 #else
8364 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8365 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8366 #endif
8367 }
8368
8369 /* Conversion */
8370 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8371 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8372 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8373 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8374 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8375 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8376 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8377 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8378 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8379 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8380
8381 /* Comparison */
8382 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8383 GEN_SPEFPUOP_COMP_64(evfscmplt);
8384 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8385 GEN_SPEFPUOP_COMP_64(evfststgt);
8386 GEN_SPEFPUOP_COMP_64(evfststlt);
8387 GEN_SPEFPUOP_COMP_64(evfststeq);
8388
8389 /* Opcodes definitions */
8390 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8391 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8392 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8393 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8394 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8395 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8396 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8397 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8398 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8399 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8400 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8401 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8402 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8403 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8404
8405 /* Single precision floating-point operations */
8406 /* Arithmetic */
8407 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8408 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8409 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8410 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8411 static inline void gen_efsabs(DisasContext *ctx)
8412 {
8413 if (unlikely(!ctx->spe_enabled)) {
8414 gen_exception(ctx, POWERPC_EXCP_SPEU);
8415 return;
8416 }
8417 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8418 }
8419 static inline void gen_efsnabs(DisasContext *ctx)
8420 {
8421 if (unlikely(!ctx->spe_enabled)) {
8422 gen_exception(ctx, POWERPC_EXCP_SPEU);
8423 return;
8424 }
8425 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8426 }
8427 static inline void gen_efsneg(DisasContext *ctx)
8428 {
8429 if (unlikely(!ctx->spe_enabled)) {
8430 gen_exception(ctx, POWERPC_EXCP_SPEU);
8431 return;
8432 }
8433 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8434 }
8435
8436 /* Conversion */
8437 GEN_SPEFPUOP_CONV_32_32(efscfui);
8438 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8439 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8440 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8441 GEN_SPEFPUOP_CONV_32_32(efsctui);
8442 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8443 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8444 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8445 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8446 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8447 GEN_SPEFPUOP_CONV_32_64(efscfd);
8448
8449 /* Comparison */
8450 GEN_SPEFPUOP_COMP_32(efscmpgt);
8451 GEN_SPEFPUOP_COMP_32(efscmplt);
8452 GEN_SPEFPUOP_COMP_32(efscmpeq);
8453 GEN_SPEFPUOP_COMP_32(efststgt);
8454 GEN_SPEFPUOP_COMP_32(efststlt);
8455 GEN_SPEFPUOP_COMP_32(efststeq);
8456
8457 /* Opcodes definitions */
8458 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8459 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8460 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8461 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8462 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8463 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8464 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8465 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8466 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8467 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8468 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8469 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8470 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8471 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8472
8473 /* Double precision floating-point operations */
8474 /* Arithmetic */
8475 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8476 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8477 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8478 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8479 static inline void gen_efdabs(DisasContext *ctx)
8480 {
8481 if (unlikely(!ctx->spe_enabled)) {
8482 gen_exception(ctx, POWERPC_EXCP_SPEU);
8483 return;
8484 }
8485 #if defined(TARGET_PPC64)
8486 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8487 #else
8488 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8489 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8490 #endif
8491 }
8492 static inline void gen_efdnabs(DisasContext *ctx)
8493 {
8494 if (unlikely(!ctx->spe_enabled)) {
8495 gen_exception(ctx, POWERPC_EXCP_SPEU);
8496 return;
8497 }
8498 #if defined(TARGET_PPC64)
8499 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8500 #else
8501 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8502 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8503 #endif
8504 }
8505 static inline void gen_efdneg(DisasContext *ctx)
8506 {
8507 if (unlikely(!ctx->spe_enabled)) {
8508 gen_exception(ctx, POWERPC_EXCP_SPEU);
8509 return;
8510 }
8511 #if defined(TARGET_PPC64)
8512 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8513 #else
8514 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8515 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8516 #endif
8517 }
8518
8519 /* Conversion */
8520 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8521 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8522 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8523 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8524 GEN_SPEFPUOP_CONV_32_64(efdctui);
8525 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8526 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8527 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8528 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8529 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8530 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8531 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8532 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8533 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8534 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8535
8536 /* Comparison */
8537 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8538 GEN_SPEFPUOP_COMP_64(efdcmplt);
8539 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8540 GEN_SPEFPUOP_COMP_64(efdtstgt);
8541 GEN_SPEFPUOP_COMP_64(efdtstlt);
8542 GEN_SPEFPUOP_COMP_64(efdtsteq);
8543
8544 /* Opcodes definitions */
8545 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8546 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8547 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8548 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8549 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8550 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8551 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8552 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8553 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8554 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8555 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8556 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8557 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8558 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8559 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8560 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8561
8562 static opcode_t opcodes[] = {
8563 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8564 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8565 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8566 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8567 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8568 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8569 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8570 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8571 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8572 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8573 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8574 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8575 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8576 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8577 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8578 #if defined(TARGET_PPC64)
8579 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8580 #endif
8581 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8582 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8583 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8584 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8585 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8586 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8587 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8588 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8589 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8590 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8591 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8592 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8593 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8594 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8595 #if defined(TARGET_PPC64)
8596 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8597 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8598 #endif
8599 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8600 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8601 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8602 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8603 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8604 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8605 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8606 #if defined(TARGET_PPC64)
8607 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8608 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8609 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8610 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8611 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8612 #endif
8613 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8614 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8615 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8616 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8617 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8618 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8619 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8620 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8621 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8622 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8623 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8624 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8625 #if defined(TARGET_PPC64)
8626 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8627 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8628 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8629 #endif
8630 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8631 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8632 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8633 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8634 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8635 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8636 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8637 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8638 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8639 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8640 #if defined(TARGET_PPC64)
8641 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8642 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8643 #endif
8644 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8645 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8646 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8647 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8648 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8649 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8650 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8651 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8652 #if defined(TARGET_PPC64)
8653 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8654 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8655 #endif
8656 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8657 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8658 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8659 #if defined(TARGET_PPC64)
8660 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8661 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8662 #endif
8663 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8664 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8665 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8666 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8667 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8668 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8669 #if defined(TARGET_PPC64)
8670 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8671 #endif
8672 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8673 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8674 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8675 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8676 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8677 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8678 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8679 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8680 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8681 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8682 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8683 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8684 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8685 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8686 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8687 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8688 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8689 #if defined(TARGET_PPC64)
8690 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8691 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8692 PPC_SEGMENT_64B),
8693 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8694 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8695 PPC_SEGMENT_64B),
8696 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8697 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8698 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8699 #endif
8700 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8701 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8702 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8703 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8704 #if defined(TARGET_PPC64)
8705 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8706 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8707 #endif
8708 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8709 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8710 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8711 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8712 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8713 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8714 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8715 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8716 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8717 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8718 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8719 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8720 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8721 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8722 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8723 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8724 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8725 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8726 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8727 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8728 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8729 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8730 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8731 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8732 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8733 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8734 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8735 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8736 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8737 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8738 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8739 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8740 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8741 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8742 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8743 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8744 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8745 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8746 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8747 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8748 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8749 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8750 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8751 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8752 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8753 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8754 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8755 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8756 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8757 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8758 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8759 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8760 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8761 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8762 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8763 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8764 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8765 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8766 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8767 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8768 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8769 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8770 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8771 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8772 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8773 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8774 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8775 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8776 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8777 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8778 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8779 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8780 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8781 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8782 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8783 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8784 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8785 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8786 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8787 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8788 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8789 PPC_NONE, PPC2_BOOKE206),
8790 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8791 PPC_NONE, PPC2_BOOKE206),
8792 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8793 PPC_NONE, PPC2_BOOKE206),
8794 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8795 PPC_NONE, PPC2_BOOKE206),
8796 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8797 PPC_NONE, PPC2_BOOKE206),
8798 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8799 PPC_NONE, PPC2_PRCNTL),
8800 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8801 PPC_NONE, PPC2_PRCNTL),
8802 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8803 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8804 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8805 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8806 PPC_BOOKE, PPC2_BOOKE206),
8807 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8808 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8809 PPC_BOOKE, PPC2_BOOKE206),
8810 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8811 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8812 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8813 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8814 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8815 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8816 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8817 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8818 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8819 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8820
8821 #undef GEN_INT_ARITH_ADD
8822 #undef GEN_INT_ARITH_ADD_CONST
8823 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8824 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8825 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8826 add_ca, compute_ca, compute_ov) \
8827 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8828 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8829 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8830 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8831 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8832 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8833 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8834 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8835 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8836 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8837 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8838
8839 #undef GEN_INT_ARITH_DIVW
8840 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8841 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8842 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8843 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8844 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8845 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8846
8847 #if defined(TARGET_PPC64)
8848 #undef GEN_INT_ARITH_DIVD
8849 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8850 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8851 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8852 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8853 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8854 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8855
8856 #undef GEN_INT_ARITH_MUL_HELPER
8857 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8858 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8859 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8860 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8861 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8862 #endif
8863
8864 #undef GEN_INT_ARITH_SUBF
8865 #undef GEN_INT_ARITH_SUBF_CONST
8866 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8867 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8868 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8869 add_ca, compute_ca, compute_ov) \
8870 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8871 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8872 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8873 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8874 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8875 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8876 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8877 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8878 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8879 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8880 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8881
8882 #undef GEN_LOGICAL1
8883 #undef GEN_LOGICAL2
8884 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8885 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8886 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8887 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8888 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8889 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8890 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8891 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8892 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8893 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8894 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8895 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8896 #if defined(TARGET_PPC64)
8897 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8898 #endif
8899
8900 #if defined(TARGET_PPC64)
8901 #undef GEN_PPC64_R2
8902 #undef GEN_PPC64_R4
8903 #define GEN_PPC64_R2(name, opc1, opc2) \
8904 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8905 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8906 PPC_64B)
8907 #define GEN_PPC64_R4(name, opc1, opc2) \
8908 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8909 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8910 PPC_64B), \
8911 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8912 PPC_64B), \
8913 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8914 PPC_64B)
8915 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8916 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8917 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8918 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8919 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8920 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8921 #endif
8922
8923 #undef _GEN_FLOAT_ACB
8924 #undef GEN_FLOAT_ACB
8925 #undef _GEN_FLOAT_AB
8926 #undef GEN_FLOAT_AB
8927 #undef _GEN_FLOAT_AC
8928 #undef GEN_FLOAT_AC
8929 #undef GEN_FLOAT_B
8930 #undef GEN_FLOAT_BS
8931 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8932 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8933 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8934 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8935 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8936 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8937 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8938 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8939 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8940 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8941 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8942 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8943 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8944 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8945 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8946 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8947 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8948 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8949 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8950
8951 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8952 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8953 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8954 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8955 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8956 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8957 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8958 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8959 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8960 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8961 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8962 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8963 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8964 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8965 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8966 #if defined(TARGET_PPC64)
8967 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8968 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8969 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8970 #endif
8971 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8972 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8973 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8974 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8975 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8976 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8977 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8978
8979 #undef GEN_LD
8980 #undef GEN_LDU
8981 #undef GEN_LDUX
8982 #undef GEN_LDX_E
8983 #undef GEN_LDS
8984 #define GEN_LD(name, ldop, opc, type) \
8985 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8986 #define GEN_LDU(name, ldop, opc, type) \
8987 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8988 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8989 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8990 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8991 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8992 #define GEN_LDS(name, ldop, op, type) \
8993 GEN_LD(name, ldop, op | 0x20, type) \
8994 GEN_LDU(name, ldop, op | 0x21, type) \
8995 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8996 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8997
8998 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8999 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
9000 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
9001 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
9002 #if defined(TARGET_PPC64)
9003 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
9004 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
9005 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
9006 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
9007 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
9008 #endif
9009 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
9010 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
9011
9012 #undef GEN_ST
9013 #undef GEN_STU
9014 #undef GEN_STUX
9015 #undef GEN_STX_E
9016 #undef GEN_STS
9017 #define GEN_ST(name, stop, opc, type) \
9018 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9019 #define GEN_STU(name, stop, opc, type) \
9020 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
9021 #define GEN_STUX(name, stop, opc2, opc3, type) \
9022 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9023 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
9024 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9025 #define GEN_STS(name, stop, op, type) \
9026 GEN_ST(name, stop, op | 0x20, type) \
9027 GEN_STU(name, stop, op | 0x21, type) \
9028 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
9029 GEN_STX(name, stop, 0x17, op | 0x00, type)
9030
9031 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
9032 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
9033 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
9034 #if defined(TARGET_PPC64)
9035 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
9036 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
9037 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
9038 #endif
9039 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
9040 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
9041
9042 #undef GEN_LDF
9043 #undef GEN_LDUF
9044 #undef GEN_LDUXF
9045 #undef GEN_LDXF
9046 #undef GEN_LDFS
9047 #define GEN_LDF(name, ldop, opc, type) \
9048 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9049 #define GEN_LDUF(name, ldop, opc, type) \
9050 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9051 #define GEN_LDUXF(name, ldop, opc, type) \
9052 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9053 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9054 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9055 #define GEN_LDFS(name, ldop, op, type) \
9056 GEN_LDF(name, ldop, op | 0x20, type) \
9057 GEN_LDUF(name, ldop, op | 0x21, type) \
9058 GEN_LDUXF(name, ldop, op | 0x01, type) \
9059 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9060
9061 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
9062 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
9063
9064 #undef GEN_STF
9065 #undef GEN_STUF
9066 #undef GEN_STUXF
9067 #undef GEN_STXF
9068 #undef GEN_STFS
9069 #define GEN_STF(name, stop, opc, type) \
9070 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9071 #define GEN_STUF(name, stop, opc, type) \
9072 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9073 #define GEN_STUXF(name, stop, opc, type) \
9074 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9075 #define GEN_STXF(name, stop, opc2, opc3, type) \
9076 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9077 #define GEN_STFS(name, stop, op, type) \
9078 GEN_STF(name, stop, op | 0x20, type) \
9079 GEN_STUF(name, stop, op | 0x21, type) \
9080 GEN_STUXF(name, stop, op | 0x01, type) \
9081 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9082
9083 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
9084 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
9085 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
9086
9087 #undef GEN_CRLOGIC
9088 #define GEN_CRLOGIC(name, tcg_op, opc) \
9089 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9090 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
9091 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
9092 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
9093 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9094 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9095 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9096 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9097 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9098
9099 #undef GEN_MAC_HANDLER
9100 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9101 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9102 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9103 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9104 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9105 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9106 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9107 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9108 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9109 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9110 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9111 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9112 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9113 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9114 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9115 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9116 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9117 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9118 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9119 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9120 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9121 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9122 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9123 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9124 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9125 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9126 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9127 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9128 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9129 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9130 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9131 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9132 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9133 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9134 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9135 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9136 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9137 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9138 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9139 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9140 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9141 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9142 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9143 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9144
9145 #undef GEN_VR_LDX
9146 #undef GEN_VR_STX
9147 #undef GEN_VR_LVE
9148 #undef GEN_VR_STVE
9149 #define GEN_VR_LDX(name, opc2, opc3) \
9150 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9151 #define GEN_VR_STX(name, opc2, opc3) \
9152 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9153 #define GEN_VR_LVE(name, opc2, opc3) \
9154 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9155 #define GEN_VR_STVE(name, opc2, opc3) \
9156 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9157 GEN_VR_LDX(lvx, 0x07, 0x03),
9158 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9159 GEN_VR_LVE(bx, 0x07, 0x00),
9160 GEN_VR_LVE(hx, 0x07, 0x01),
9161 GEN_VR_LVE(wx, 0x07, 0x02),
9162 GEN_VR_STX(svx, 0x07, 0x07),
9163 GEN_VR_STX(svxl, 0x07, 0x0F),
9164 GEN_VR_STVE(bx, 0x07, 0x04),
9165 GEN_VR_STVE(hx, 0x07, 0x05),
9166 GEN_VR_STVE(wx, 0x07, 0x06),
9167
9168 #undef GEN_VX_LOGICAL
9169 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9170 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9171 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9172 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9173 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9174 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9175 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9176
9177 #undef GEN_VXFORM
9178 #define GEN_VXFORM(name, opc2, opc3) \
9179 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9180 GEN_VXFORM(vaddubm, 0, 0),
9181 GEN_VXFORM(vadduhm, 0, 1),
9182 GEN_VXFORM(vadduwm, 0, 2),
9183 GEN_VXFORM(vsububm, 0, 16),
9184 GEN_VXFORM(vsubuhm, 0, 17),
9185 GEN_VXFORM(vsubuwm, 0, 18),
9186 GEN_VXFORM(vmaxub, 1, 0),
9187 GEN_VXFORM(vmaxuh, 1, 1),
9188 GEN_VXFORM(vmaxuw, 1, 2),
9189 GEN_VXFORM(vmaxsb, 1, 4),
9190 GEN_VXFORM(vmaxsh, 1, 5),
9191 GEN_VXFORM(vmaxsw, 1, 6),
9192 GEN_VXFORM(vminub, 1, 8),
9193 GEN_VXFORM(vminuh, 1, 9),
9194 GEN_VXFORM(vminuw, 1, 10),
9195 GEN_VXFORM(vminsb, 1, 12),
9196 GEN_VXFORM(vminsh, 1, 13),
9197 GEN_VXFORM(vminsw, 1, 14),
9198 GEN_VXFORM(vavgub, 1, 16),
9199 GEN_VXFORM(vavguh, 1, 17),
9200 GEN_VXFORM(vavguw, 1, 18),
9201 GEN_VXFORM(vavgsb, 1, 20),
9202 GEN_VXFORM(vavgsh, 1, 21),
9203 GEN_VXFORM(vavgsw, 1, 22),
9204 GEN_VXFORM(vmrghb, 6, 0),
9205 GEN_VXFORM(vmrghh, 6, 1),
9206 GEN_VXFORM(vmrghw, 6, 2),
9207 GEN_VXFORM(vmrglb, 6, 4),
9208 GEN_VXFORM(vmrglh, 6, 5),
9209 GEN_VXFORM(vmrglw, 6, 6),
9210 GEN_VXFORM(vmuloub, 4, 0),
9211 GEN_VXFORM(vmulouh, 4, 1),
9212 GEN_VXFORM(vmulosb, 4, 4),
9213 GEN_VXFORM(vmulosh, 4, 5),
9214 GEN_VXFORM(vmuleub, 4, 8),
9215 GEN_VXFORM(vmuleuh, 4, 9),
9216 GEN_VXFORM(vmulesb, 4, 12),
9217 GEN_VXFORM(vmulesh, 4, 13),
9218 GEN_VXFORM(vslb, 2, 4),
9219 GEN_VXFORM(vslh, 2, 5),
9220 GEN_VXFORM(vslw, 2, 6),
9221 GEN_VXFORM(vsrb, 2, 8),
9222 GEN_VXFORM(vsrh, 2, 9),
9223 GEN_VXFORM(vsrw, 2, 10),
9224 GEN_VXFORM(vsrab, 2, 12),
9225 GEN_VXFORM(vsrah, 2, 13),
9226 GEN_VXFORM(vsraw, 2, 14),
9227 GEN_VXFORM(vslo, 6, 16),
9228 GEN_VXFORM(vsro, 6, 17),
9229 GEN_VXFORM(vaddcuw, 0, 6),
9230 GEN_VXFORM(vsubcuw, 0, 22),
9231 GEN_VXFORM(vaddubs, 0, 8),
9232 GEN_VXFORM(vadduhs, 0, 9),
9233 GEN_VXFORM(vadduws, 0, 10),
9234 GEN_VXFORM(vaddsbs, 0, 12),
9235 GEN_VXFORM(vaddshs, 0, 13),
9236 GEN_VXFORM(vaddsws, 0, 14),
9237 GEN_VXFORM(vsububs, 0, 24),
9238 GEN_VXFORM(vsubuhs, 0, 25),
9239 GEN_VXFORM(vsubuws, 0, 26),
9240 GEN_VXFORM(vsubsbs, 0, 28),
9241 GEN_VXFORM(vsubshs, 0, 29),
9242 GEN_VXFORM(vsubsws, 0, 30),
9243 GEN_VXFORM(vrlb, 2, 0),
9244 GEN_VXFORM(vrlh, 2, 1),
9245 GEN_VXFORM(vrlw, 2, 2),
9246 GEN_VXFORM(vsl, 2, 7),
9247 GEN_VXFORM(vsr, 2, 11),
9248 GEN_VXFORM(vpkuhum, 7, 0),
9249 GEN_VXFORM(vpkuwum, 7, 1),
9250 GEN_VXFORM(vpkuhus, 7, 2),
9251 GEN_VXFORM(vpkuwus, 7, 3),
9252 GEN_VXFORM(vpkshus, 7, 4),
9253 GEN_VXFORM(vpkswus, 7, 5),
9254 GEN_VXFORM(vpkshss, 7, 6),
9255 GEN_VXFORM(vpkswss, 7, 7),
9256 GEN_VXFORM(vpkpx, 7, 12),
9257 GEN_VXFORM(vsum4ubs, 4, 24),
9258 GEN_VXFORM(vsum4sbs, 4, 28),
9259 GEN_VXFORM(vsum4shs, 4, 25),
9260 GEN_VXFORM(vsum2sws, 4, 26),
9261 GEN_VXFORM(vsumsws, 4, 30),
9262 GEN_VXFORM(vaddfp, 5, 0),
9263 GEN_VXFORM(vsubfp, 5, 1),
9264 GEN_VXFORM(vmaxfp, 5, 16),
9265 GEN_VXFORM(vminfp, 5, 17),
9266
9267 #undef GEN_VXRFORM1
9268 #undef GEN_VXRFORM
9269 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9270 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9271 #define GEN_VXRFORM(name, opc2, opc3) \
9272 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9273 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9274 GEN_VXRFORM(vcmpequb, 3, 0)
9275 GEN_VXRFORM(vcmpequh, 3, 1)
9276 GEN_VXRFORM(vcmpequw, 3, 2)
9277 GEN_VXRFORM(vcmpgtsb, 3, 12)
9278 GEN_VXRFORM(vcmpgtsh, 3, 13)
9279 GEN_VXRFORM(vcmpgtsw, 3, 14)
9280 GEN_VXRFORM(vcmpgtub, 3, 8)
9281 GEN_VXRFORM(vcmpgtuh, 3, 9)
9282 GEN_VXRFORM(vcmpgtuw, 3, 10)
9283 GEN_VXRFORM(vcmpeqfp, 3, 3)
9284 GEN_VXRFORM(vcmpgefp, 3, 7)
9285 GEN_VXRFORM(vcmpgtfp, 3, 11)
9286 GEN_VXRFORM(vcmpbfp, 3, 15)
9287
9288 #undef GEN_VXFORM_SIMM
9289 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9290 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9291 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9292 GEN_VXFORM_SIMM(vspltish, 6, 13),
9293 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9294
9295 #undef GEN_VXFORM_NOA
9296 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9297 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9298 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9299 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9300 GEN_VXFORM_NOA(vupklsb, 7, 10),
9301 GEN_VXFORM_NOA(vupklsh, 7, 11),
9302 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9303 GEN_VXFORM_NOA(vupklpx, 7, 15),
9304 GEN_VXFORM_NOA(vrefp, 5, 4),
9305 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9306 GEN_VXFORM_NOA(vexptefp, 5, 6),
9307 GEN_VXFORM_NOA(vlogefp, 5, 7),
9308 GEN_VXFORM_NOA(vrfim, 5, 8),
9309 GEN_VXFORM_NOA(vrfin, 5, 9),
9310 GEN_VXFORM_NOA(vrfip, 5, 10),
9311 GEN_VXFORM_NOA(vrfiz, 5, 11),
9312
9313 #undef GEN_VXFORM_UIMM
9314 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9315 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9316 GEN_VXFORM_UIMM(vspltb, 6, 8),
9317 GEN_VXFORM_UIMM(vsplth, 6, 9),
9318 GEN_VXFORM_UIMM(vspltw, 6, 10),
9319 GEN_VXFORM_UIMM(vcfux, 5, 12),
9320 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9321 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9322 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9323
9324 #undef GEN_VAFORM_PAIRED
9325 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9326 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9327 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9328 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9329 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9330 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9331 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9332 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9333
9334 #undef GEN_SPE
9335 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9336 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9337 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9338 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9339 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9340 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9341 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9342 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9343 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9344 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9345 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9346 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9347 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9348 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9349 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9350 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9351 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9352 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9353 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9354 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9355 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9356 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9357 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9358 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9359 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9360 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9361 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9362 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9363 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9364 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9365 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9366
9367 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9368 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9369 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9370 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9371 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9372 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9373 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9374 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9375 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9376 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9377 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9378 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9379 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9380 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9381
9382 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9383 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9384 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9385 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9386 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9387 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9388 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9389 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9390 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9391 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9392 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9393 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9394 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9395 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9396
9397 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9398 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9399 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9400 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9401 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9402 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9403 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9404 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9405 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9406 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9407 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9408 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9409 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9410 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9411 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9412 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9413
9414 #undef GEN_SPEOP_LDST
9415 #define GEN_SPEOP_LDST(name, opc2, sh) \
9416 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9417 GEN_SPEOP_LDST(evldd, 0x00, 3),
9418 GEN_SPEOP_LDST(evldw, 0x01, 3),
9419 GEN_SPEOP_LDST(evldh, 0x02, 3),
9420 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9421 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9422 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9423 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9424 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9425 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9426 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9427 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9428
9429 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9430 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9431 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9432 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9433 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9434 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9435 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9436 };
9437
9438 #include "helper_regs.h"
9439 #include "translate_init.c"
9440
9441 /*****************************************************************************/
9442 /* Misc PowerPC helpers */
9443 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9444 int flags)
9445 {
9446 #define RGPL 4
9447 #define RFPL 4
9448
9449 int i;
9450
9451 cpu_synchronize_state(env);
9452
9453 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9454 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9455 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9456 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9457 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9458 env->hflags, env->mmu_idx);
9459 #if !defined(NO_TIMER_DUMP)
9460 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9461 #if !defined(CONFIG_USER_ONLY)
9462 " DECR %08" PRIu32
9463 #endif
9464 "\n",
9465 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9466 #if !defined(CONFIG_USER_ONLY)
9467 , cpu_ppc_load_decr(env)
9468 #endif
9469 );
9470 #endif
9471 for (i = 0; i < 32; i++) {
9472 if ((i & (RGPL - 1)) == 0)
9473 cpu_fprintf(f, "GPR%02d", i);
9474 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9475 if ((i & (RGPL - 1)) == (RGPL - 1))
9476 cpu_fprintf(f, "\n");
9477 }
9478 cpu_fprintf(f, "CR ");
9479 for (i = 0; i < 8; i++)
9480 cpu_fprintf(f, "%01x", env->crf[i]);
9481 cpu_fprintf(f, " [");
9482 for (i = 0; i < 8; i++) {
9483 char a = '-';
9484 if (env->crf[i] & 0x08)
9485 a = 'L';
9486 else if (env->crf[i] & 0x04)
9487 a = 'G';
9488 else if (env->crf[i] & 0x02)
9489 a = 'E';
9490 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9491 }
9492 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9493 env->reserve_addr);
9494 for (i = 0; i < 32; i++) {
9495 if ((i & (RFPL - 1)) == 0)
9496 cpu_fprintf(f, "FPR%02d", i);
9497 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9498 if ((i & (RFPL - 1)) == (RFPL - 1))
9499 cpu_fprintf(f, "\n");
9500 }
9501 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9502 #if !defined(CONFIG_USER_ONLY)
9503 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9504 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9505 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9506 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9507
9508 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9509 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9510 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9511 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9512
9513 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9514 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9515 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9516 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9517
9518 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9519 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9520 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9521 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9522 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9523
9524 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9525 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9526 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9527 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9528
9529 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9530 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9531 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9532 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9533
9534 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9535 " EPR " TARGET_FMT_lx "\n",
9536 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9537 env->spr[SPR_BOOKE_EPR]);
9538
9539 /* FSL-specific */
9540 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9541 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9542 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9543 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9544
9545 /*
9546 * IVORs are left out as they are large and do not change often --
9547 * they can be read with "p $ivor0", "p $ivor1", etc.
9548 */
9549 }
9550
9551 #if defined(TARGET_PPC64)
9552 if (env->flags & POWERPC_FLAG_CFAR) {
9553 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9554 }
9555 #endif
9556
9557 switch (env->mmu_model) {
9558 case POWERPC_MMU_32B:
9559 case POWERPC_MMU_601:
9560 case POWERPC_MMU_SOFT_6xx:
9561 case POWERPC_MMU_SOFT_74xx:
9562 #if defined(TARGET_PPC64)
9563 case POWERPC_MMU_620:
9564 case POWERPC_MMU_64B:
9565 #endif
9566 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9567 break;
9568 case POWERPC_MMU_BOOKE206:
9569 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9570 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9571 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9572 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9573
9574 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9575 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9576 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9577 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9578
9579 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9580 " TLB1CFG " TARGET_FMT_lx "\n",
9581 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9582 env->spr[SPR_BOOKE_TLB1CFG]);
9583 break;
9584 default:
9585 break;
9586 }
9587 #endif
9588
9589 #undef RGPL
9590 #undef RFPL
9591 }
9592
9593 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9594 int flags)
9595 {
9596 #if defined(DO_PPC_STATISTICS)
9597 opc_handler_t **t1, **t2, **t3, *handler;
9598 int op1, op2, op3;
9599
9600 t1 = env->opcodes;
9601 for (op1 = 0; op1 < 64; op1++) {
9602 handler = t1[op1];
9603 if (is_indirect_opcode(handler)) {
9604 t2 = ind_table(handler);
9605 for (op2 = 0; op2 < 32; op2++) {
9606 handler = t2[op2];
9607 if (is_indirect_opcode(handler)) {
9608 t3 = ind_table(handler);
9609 for (op3 = 0; op3 < 32; op3++) {
9610 handler = t3[op3];
9611 if (handler->count == 0)
9612 continue;
9613 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9614 "%016" PRIx64 " %" PRId64 "\n",
9615 op1, op2, op3, op1, (op3 << 5) | op2,
9616 handler->oname,
9617 handler->count, handler->count);
9618 }
9619 } else {
9620 if (handler->count == 0)
9621 continue;
9622 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9623 "%016" PRIx64 " %" PRId64 "\n",
9624 op1, op2, op1, op2, handler->oname,
9625 handler->count, handler->count);
9626 }
9627 }
9628 } else {
9629 if (handler->count == 0)
9630 continue;
9631 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9632 " %" PRId64 "\n",
9633 op1, op1, handler->oname,
9634 handler->count, handler->count);
9635 }
9636 }
9637 #endif
9638 }
9639
9640 /*****************************************************************************/
9641 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9642 TranslationBlock *tb,
9643 int search_pc)
9644 {
9645 DisasContext ctx, *ctxp = &ctx;
9646 opc_handler_t **table, *handler;
9647 target_ulong pc_start;
9648 uint16_t *gen_opc_end;
9649 CPUBreakpoint *bp;
9650 int j, lj = -1;
9651 int num_insns;
9652 int max_insns;
9653
9654 pc_start = tb->pc;
9655 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9656 ctx.nip = pc_start;
9657 ctx.tb = tb;
9658 ctx.exception = POWERPC_EXCP_NONE;
9659 ctx.spr_cb = env->spr_cb;
9660 ctx.mem_idx = env->mmu_idx;
9661 ctx.access_type = -1;
9662 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9663 #if defined(TARGET_PPC64)
9664 ctx.sf_mode = msr_is_64bit(env, env->msr);
9665 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9666 #endif
9667 ctx.fpu_enabled = msr_fp;
9668 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9669 ctx.spe_enabled = msr_spe;
9670 else
9671 ctx.spe_enabled = 0;
9672 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9673 ctx.altivec_enabled = msr_vr;
9674 else
9675 ctx.altivec_enabled = 0;
9676 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9677 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9678 else
9679 ctx.singlestep_enabled = 0;
9680 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9681 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9682 if (unlikely(env->singlestep_enabled))
9683 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9684 #if defined (DO_SINGLE_STEP) && 0
9685 /* Single step trace mode */
9686 msr_se = 1;
9687 #endif
9688 num_insns = 0;
9689 max_insns = tb->cflags & CF_COUNT_MASK;
9690 if (max_insns == 0)
9691 max_insns = CF_COUNT_MASK;
9692
9693 gen_icount_start();
9694 /* Set env in case of segfault during code fetch */
9695 while (ctx.exception == POWERPC_EXCP_NONE
9696 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9697 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9698 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9699 if (bp->pc == ctx.nip) {
9700 gen_debug_exception(ctxp);
9701 break;
9702 }
9703 }
9704 }
9705 if (unlikely(search_pc)) {
9706 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9707 if (lj < j) {
9708 lj++;
9709 while (lj < j)
9710 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9711 }
9712 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9713 tcg_ctx.gen_opc_instr_start[lj] = 1;
9714 tcg_ctx.gen_opc_icount[lj] = num_insns;
9715 }
9716 LOG_DISAS("----------------\n");
9717 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9718 ctx.nip, ctx.mem_idx, (int)msr_ir);
9719 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9720 gen_io_start();
9721 if (unlikely(ctx.le_mode)) {
9722 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9723 } else {
9724 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9725 }
9726 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9727 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9728 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9729 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9730 tcg_gen_debug_insn_start(ctx.nip);
9731 }
9732 ctx.nip += 4;
9733 table = env->opcodes;
9734 num_insns++;
9735 handler = table[opc1(ctx.opcode)];
9736 if (is_indirect_opcode(handler)) {
9737 table = ind_table(handler);
9738 handler = table[opc2(ctx.opcode)];
9739 if (is_indirect_opcode(handler)) {
9740 table = ind_table(handler);
9741 handler = table[opc3(ctx.opcode)];
9742 }
9743 }
9744 /* Is opcode *REALLY* valid ? */
9745 if (unlikely(handler->handler == &gen_invalid)) {
9746 if (qemu_log_enabled()) {
9747 qemu_log("invalid/unsupported opcode: "
9748 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9749 opc1(ctx.opcode), opc2(ctx.opcode),
9750 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9751 }
9752 } else {
9753 uint32_t inval;
9754
9755 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9756 inval = handler->inval2;
9757 } else {
9758 inval = handler->inval1;
9759 }
9760
9761 if (unlikely((ctx.opcode & inval) != 0)) {
9762 if (qemu_log_enabled()) {
9763 qemu_log("invalid bits: %08x for opcode: "
9764 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9765 ctx.opcode & inval, opc1(ctx.opcode),
9766 opc2(ctx.opcode), opc3(ctx.opcode),
9767 ctx.opcode, ctx.nip - 4);
9768 }
9769 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9770 break;
9771 }
9772 }
9773 (*(handler->handler))(&ctx);
9774 #if defined(DO_PPC_STATISTICS)
9775 handler->count++;
9776 #endif
9777 /* Check trace mode exceptions */
9778 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9779 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9780 ctx.exception != POWERPC_SYSCALL &&
9781 ctx.exception != POWERPC_EXCP_TRAP &&
9782 ctx.exception != POWERPC_EXCP_BRANCH)) {
9783 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9784 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9785 (env->singlestep_enabled) ||
9786 singlestep ||
9787 num_insns >= max_insns)) {
9788 /* if we reach a page boundary or are single stepping, stop
9789 * generation
9790 */
9791 break;
9792 }
9793 }
9794 if (tb->cflags & CF_LAST_IO)
9795 gen_io_end();
9796 if (ctx.exception == POWERPC_EXCP_NONE) {
9797 gen_goto_tb(&ctx, 0, ctx.nip);
9798 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9799 if (unlikely(env->singlestep_enabled)) {
9800 gen_debug_exception(ctxp);
9801 }
9802 /* Generate the return instruction */
9803 tcg_gen_exit_tb(0);
9804 }
9805 gen_icount_end(tb, num_insns);
9806 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9807 if (unlikely(search_pc)) {
9808 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9809 lj++;
9810 while (lj <= j)
9811 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9812 } else {
9813 tb->size = ctx.nip - pc_start;
9814 tb->icount = num_insns;
9815 }
9816 #if defined(DEBUG_DISAS)
9817 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9818 int flags;
9819 flags = env->bfd_mach;
9820 flags |= ctx.le_mode << 16;
9821 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9822 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9823 qemu_log("\n");
9824 }
9825 #endif
9826 }
9827
9828 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9829 {
9830 gen_intermediate_code_internal(env, tb, 0);
9831 }
9832
9833 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9834 {
9835 gen_intermediate_code_internal(env, tb, 1);
9836 }
9837
9838 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9839 {
9840 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9841 }
Qemu copy for testing