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target-ppc: emulate store doubleword pair instructions
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 /* True when active word size < size of target_long. */
208 #ifdef TARGET_PPC64
209 # define NARROW_MODE(C) (!(C)->sf_mode)
210 #else
211 # define NARROW_MODE(C) 0
212 #endif
213
214 struct opc_handler_t {
215 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
216 uint32_t inval1;
217 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
218 uint32_t inval2;
219 /* instruction type */
220 uint64_t type;
221 /* extended instruction type */
222 uint64_t type2;
223 /* handler */
224 void (*handler)(DisasContext *ctx);
225 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
226 const char *oname;
227 #endif
228 #if defined(DO_PPC_STATISTICS)
229 uint64_t count;
230 #endif
231 };
232
233 static inline void gen_reset_fpstatus(void)
234 {
235 gen_helper_reset_fpstatus(cpu_env);
236 }
237
238 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
239 {
240 TCGv_i32 t0 = tcg_temp_new_i32();
241
242 if (set_fprf != 0) {
243 /* This case might be optimized later */
244 tcg_gen_movi_i32(t0, 1);
245 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
246 if (unlikely(set_rc)) {
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249 gen_helper_float_check_status(cpu_env);
250 } else if (unlikely(set_rc)) {
251 /* We always need to compute fpcc */
252 tcg_gen_movi_i32(t0, 0);
253 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
254 tcg_gen_mov_i32(cpu_crf[1], t0);
255 }
256
257 tcg_temp_free_i32(t0);
258 }
259
260 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
261 {
262 if (ctx->access_type != access_type) {
263 tcg_gen_movi_i32(cpu_access_type, access_type);
264 ctx->access_type = access_type;
265 }
266 }
267
268 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
269 {
270 if (NARROW_MODE(ctx)) {
271 nip = (uint32_t)nip;
272 }
273 tcg_gen_movi_tl(cpu_nip, nip);
274 }
275
276 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
277 {
278 TCGv_i32 t0, t1;
279 if (ctx->exception == POWERPC_EXCP_NONE) {
280 gen_update_nip(ctx, ctx->nip);
281 }
282 t0 = tcg_const_i32(excp);
283 t1 = tcg_const_i32(error);
284 gen_helper_raise_exception_err(cpu_env, t0, t1);
285 tcg_temp_free_i32(t0);
286 tcg_temp_free_i32(t1);
287 ctx->exception = (excp);
288 }
289
290 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
291 {
292 TCGv_i32 t0;
293 if (ctx->exception == POWERPC_EXCP_NONE) {
294 gen_update_nip(ctx, ctx->nip);
295 }
296 t0 = tcg_const_i32(excp);
297 gen_helper_raise_exception(cpu_env, t0);
298 tcg_temp_free_i32(t0);
299 ctx->exception = (excp);
300 }
301
302 static inline void gen_debug_exception(DisasContext *ctx)
303 {
304 TCGv_i32 t0;
305
306 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
307 (ctx->exception != POWERPC_EXCP_SYNC)) {
308 gen_update_nip(ctx, ctx->nip);
309 }
310 t0 = tcg_const_i32(EXCP_DEBUG);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 }
314
315 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
316 {
317 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
318 }
319
320 /* Stop translation */
321 static inline void gen_stop_exception(DisasContext *ctx)
322 {
323 gen_update_nip(ctx, ctx->nip);
324 ctx->exception = POWERPC_EXCP_STOP;
325 }
326
327 /* No need to update nip here, as execution flow will change */
328 static inline void gen_sync_exception(DisasContext *ctx)
329 {
330 ctx->exception = POWERPC_EXCP_SYNC;
331 }
332
333 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
334 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
335
336 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
337 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
338
339 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
344
345 typedef struct opcode_t {
346 unsigned char opc1, opc2, opc3;
347 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
348 unsigned char pad[5];
349 #else
350 unsigned char pad[1];
351 #endif
352 opc_handler_t handler;
353 const char *oname;
354 } opcode_t;
355
356 /*****************************************************************************/
357 /*** Instruction decoding ***/
358 #define EXTRACT_HELPER(name, shift, nb) \
359 static inline uint32_t name(uint32_t opcode) \
360 { \
361 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
362 }
363
364 #define EXTRACT_SHELPER(name, shift, nb) \
365 static inline int32_t name(uint32_t opcode) \
366 { \
367 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
368 }
369
370 /* Opcode part 1 */
371 EXTRACT_HELPER(opc1, 26, 6);
372 /* Opcode part 2 */
373 EXTRACT_HELPER(opc2, 1, 5);
374 /* Opcode part 3 */
375 EXTRACT_HELPER(opc3, 6, 5);
376 /* Update Cr0 flags */
377 EXTRACT_HELPER(Rc, 0, 1);
378 /* Destination */
379 EXTRACT_HELPER(rD, 21, 5);
380 /* Source */
381 EXTRACT_HELPER(rS, 21, 5);
382 /* First operand */
383 EXTRACT_HELPER(rA, 16, 5);
384 /* Second operand */
385 EXTRACT_HELPER(rB, 11, 5);
386 /* Third operand */
387 EXTRACT_HELPER(rC, 6, 5);
388 /*** Get CRn ***/
389 EXTRACT_HELPER(crfD, 23, 3);
390 EXTRACT_HELPER(crfS, 18, 3);
391 EXTRACT_HELPER(crbD, 21, 5);
392 EXTRACT_HELPER(crbA, 16, 5);
393 EXTRACT_HELPER(crbB, 11, 5);
394 /* SPR / TBL */
395 EXTRACT_HELPER(_SPR, 11, 10);
396 static inline uint32_t SPR(uint32_t opcode)
397 {
398 uint32_t sprn = _SPR(opcode);
399
400 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
401 }
402 /*** Get constants ***/
403 EXTRACT_HELPER(IMM, 12, 8);
404 /* 16 bits signed immediate value */
405 EXTRACT_SHELPER(SIMM, 0, 16);
406 /* 16 bits unsigned immediate value */
407 EXTRACT_HELPER(UIMM, 0, 16);
408 /* 5 bits signed immediate value */
409 EXTRACT_HELPER(SIMM5, 16, 5);
410 /* 5 bits signed immediate value */
411 EXTRACT_HELPER(UIMM5, 16, 5);
412 /* Bit count */
413 EXTRACT_HELPER(NB, 11, 5);
414 /* Shift count */
415 EXTRACT_HELPER(SH, 11, 5);
416 /* Vector shift count */
417 EXTRACT_HELPER(VSH, 6, 4);
418 /* Mask start */
419 EXTRACT_HELPER(MB, 6, 5);
420 /* Mask end */
421 EXTRACT_HELPER(ME, 1, 5);
422 /* Trap operand */
423 EXTRACT_HELPER(TO, 21, 5);
424
425 EXTRACT_HELPER(CRM, 12, 8);
426 EXTRACT_HELPER(FM, 17, 8);
427 EXTRACT_HELPER(SR, 16, 4);
428 EXTRACT_HELPER(FPIMM, 12, 4);
429
430 /*** Jump target decoding ***/
431 /* Displacement */
432 EXTRACT_SHELPER(d, 0, 16);
433 /* Immediate address */
434 static inline target_ulong LI(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0x03FFFFFC;
437 }
438
439 static inline uint32_t BD(uint32_t opcode)
440 {
441 return (opcode >> 0) & 0xFFFC;
442 }
443
444 EXTRACT_HELPER(BO, 21, 5);
445 EXTRACT_HELPER(BI, 16, 5);
446 /* Absolute/relative address */
447 EXTRACT_HELPER(AA, 1, 1);
448 /* Link */
449 EXTRACT_HELPER(LK, 0, 1);
450
451 /* Create a mask between <start> and <end> bits */
452 static inline target_ulong MASK(uint32_t start, uint32_t end)
453 {
454 target_ulong ret;
455
456 #if defined(TARGET_PPC64)
457 if (likely(start == 0)) {
458 ret = UINT64_MAX << (63 - end);
459 } else if (likely(end == 63)) {
460 ret = UINT64_MAX >> start;
461 }
462 #else
463 if (likely(start == 0)) {
464 ret = UINT32_MAX << (31 - end);
465 } else if (likely(end == 31)) {
466 ret = UINT32_MAX >> start;
467 }
468 #endif
469 else {
470 ret = (((target_ulong)(-1ULL)) >> (start)) ^
471 (((target_ulong)(-1ULL) >> (end)) >> 1);
472 if (unlikely(start > end))
473 return ~ret;
474 }
475
476 return ret;
477 }
478
479 /*****************************************************************************/
480 /* PowerPC instructions table */
481
482 #if defined(DO_PPC_STATISTICS)
483 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
484 { \
485 .opc1 = op1, \
486 .opc2 = op2, \
487 .opc3 = op3, \
488 .pad = { 0, }, \
489 .handler = { \
490 .inval1 = invl, \
491 .type = _typ, \
492 .type2 = _typ2, \
493 .handler = &gen_##name, \
494 .oname = stringify(name), \
495 }, \
496 .oname = stringify(name), \
497 }
498 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
499 { \
500 .opc1 = op1, \
501 .opc2 = op2, \
502 .opc3 = op3, \
503 .pad = { 0, }, \
504 .handler = { \
505 .inval1 = invl1, \
506 .inval2 = invl2, \
507 .type = _typ, \
508 .type2 = _typ2, \
509 .handler = &gen_##name, \
510 .oname = stringify(name), \
511 }, \
512 .oname = stringify(name), \
513 }
514 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
515 { \
516 .opc1 = op1, \
517 .opc2 = op2, \
518 .opc3 = op3, \
519 .pad = { 0, }, \
520 .handler = { \
521 .inval1 = invl, \
522 .type = _typ, \
523 .type2 = _typ2, \
524 .handler = &gen_##name, \
525 .oname = onam, \
526 }, \
527 .oname = onam, \
528 }
529 #else
530 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
531 { \
532 .opc1 = op1, \
533 .opc2 = op2, \
534 .opc3 = op3, \
535 .pad = { 0, }, \
536 .handler = { \
537 .inval1 = invl, \
538 .type = _typ, \
539 .type2 = _typ2, \
540 .handler = &gen_##name, \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .pad = { 0, }, \
550 .handler = { \
551 .inval1 = invl1, \
552 .inval2 = invl2, \
553 .type = _typ, \
554 .type2 = _typ2, \
555 .handler = &gen_##name, \
556 }, \
557 .oname = stringify(name), \
558 }
559 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
560 { \
561 .opc1 = op1, \
562 .opc2 = op2, \
563 .opc3 = op3, \
564 .pad = { 0, }, \
565 .handler = { \
566 .inval1 = invl, \
567 .type = _typ, \
568 .type2 = _typ2, \
569 .handler = &gen_##name, \
570 }, \
571 .oname = onam, \
572 }
573 #endif
574
575 /* SPR load/store helpers */
576 static inline void gen_load_spr(TCGv t, int reg)
577 {
578 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 static inline void gen_store_spr(int reg, TCGv t)
582 {
583 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
584 }
585
586 /* Invalid instruction */
587 static void gen_invalid(DisasContext *ctx)
588 {
589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
590 }
591
592 static opc_handler_t invalid_handler = {
593 .inval1 = 0xFFFFFFFF,
594 .inval2 = 0xFFFFFFFF,
595 .type = PPC_NONE,
596 .type2 = PPC_NONE,
597 .handler = gen_invalid,
598 };
599
600 /*** Integer comparison ***/
601
602 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
603 {
604 TCGv t0 = tcg_temp_new();
605 TCGv_i32 t1 = tcg_temp_new_i32();
606
607 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_LT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_GT);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
620 tcg_gen_trunc_tl_i32(t1, t0);
621 tcg_gen_shli_i32(t1, t1, CRF_EQ);
622 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
623
624 tcg_temp_free(t0);
625 tcg_temp_free_i32(t1);
626 }
627
628 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
629 {
630 TCGv t0 = tcg_const_tl(arg1);
631 gen_op_cmp(arg0, t0, s, crf);
632 tcg_temp_free(t0);
633 }
634
635 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
636 {
637 TCGv t0, t1;
638 t0 = tcg_temp_new();
639 t1 = tcg_temp_new();
640 if (s) {
641 tcg_gen_ext32s_tl(t0, arg0);
642 tcg_gen_ext32s_tl(t1, arg1);
643 } else {
644 tcg_gen_ext32u_tl(t0, arg0);
645 tcg_gen_ext32u_tl(t1, arg1);
646 }
647 gen_op_cmp(t0, t1, s, crf);
648 tcg_temp_free(t1);
649 tcg_temp_free(t0);
650 }
651
652 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
653 {
654 TCGv t0 = tcg_const_tl(arg1);
655 gen_op_cmp32(arg0, t0, s, crf);
656 tcg_temp_free(t0);
657 }
658
659 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
660 {
661 if (NARROW_MODE(ctx)) {
662 gen_op_cmpi32(reg, 0, 1, 0);
663 } else {
664 gen_op_cmpi(reg, 0, 1, 0);
665 }
666 }
667
668 /* cmp */
669 static void gen_cmp(DisasContext *ctx)
670 {
671 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
672 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
673 1, crfD(ctx->opcode));
674 } else {
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678 }
679
680 /* cmpi */
681 static void gen_cmpi(DisasContext *ctx)
682 {
683 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 } else {
687 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
688 1, crfD(ctx->opcode));
689 }
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
696 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
697 0, crfD(ctx->opcode));
698 } else {
699 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
700 0, crfD(ctx->opcode));
701 }
702 }
703
704 /* cmpli */
705 static void gen_cmpli(DisasContext *ctx)
706 {
707 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
708 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
709 0, crfD(ctx->opcode));
710 } else {
711 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
712 0, crfD(ctx->opcode));
713 }
714 }
715
716 /* isel (PowerPC 2.03 specification) */
717 static void gen_isel(DisasContext *ctx)
718 {
719 int l1, l2;
720 uint32_t bi = rC(ctx->opcode);
721 uint32_t mask;
722 TCGv_i32 t0;
723
724 l1 = gen_new_label();
725 l2 = gen_new_label();
726
727 mask = 1 << (3 - (bi & 0x03));
728 t0 = tcg_temp_new_i32();
729 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
730 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
731 if (rA(ctx->opcode) == 0)
732 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
733 else
734 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
735 tcg_gen_br(l2);
736 gen_set_label(l1);
737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
738 gen_set_label(l2);
739 tcg_temp_free_i32(t0);
740 }
741
742 /* cmpb: PowerPC 2.05 specification */
743 static void gen_cmpb(DisasContext *ctx)
744 {
745 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
746 cpu_gpr[rB(ctx->opcode)]);
747 }
748
749 /*** Integer arithmetic ***/
750
751 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
752 TCGv arg1, TCGv arg2, int sub)
753 {
754 TCGv t0 = tcg_temp_new();
755
756 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
757 tcg_gen_xor_tl(t0, arg1, arg2);
758 if (sub) {
759 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
760 } else {
761 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
762 }
763 tcg_temp_free(t0);
764 if (NARROW_MODE(ctx)) {
765 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
766 }
767 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
768 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
769 }
770
771 /* Common add function */
772 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
773 TCGv arg2, bool add_ca, bool compute_ca,
774 bool compute_ov, bool compute_rc0)
775 {
776 TCGv t0 = ret;
777
778 if (compute_ca || compute_ov) {
779 t0 = tcg_temp_new();
780 }
781
782 if (compute_ca) {
783 if (NARROW_MODE(ctx)) {
784 /* Caution: a non-obvious corner case of the spec is that we
785 must produce the *entire* 64-bit addition, but produce the
786 carry into bit 32. */
787 TCGv t1 = tcg_temp_new();
788 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
789 tcg_gen_add_tl(t0, arg1, arg2);
790 if (add_ca) {
791 tcg_gen_add_tl(t0, t0, cpu_ca);
792 }
793 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
794 tcg_temp_free(t1);
795 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
796 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
797 } else {
798 TCGv zero = tcg_const_tl(0);
799 if (add_ca) {
800 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
801 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
802 } else {
803 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
804 }
805 tcg_temp_free(zero);
806 }
807 } else {
808 tcg_gen_add_tl(t0, arg1, arg2);
809 if (add_ca) {
810 tcg_gen_add_tl(t0, t0, cpu_ca);
811 }
812 }
813
814 if (compute_ov) {
815 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
816 }
817 if (unlikely(compute_rc0)) {
818 gen_set_Rc0(ctx, t0);
819 }
820
821 if (!TCGV_EQUAL(t0, ret)) {
822 tcg_gen_mov_tl(ret, t0);
823 tcg_temp_free(t0);
824 }
825 }
826 /* Add functions with two operands */
827 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
828 static void glue(gen_, name)(DisasContext *ctx) \
829 { \
830 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
831 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
832 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
833 }
834 /* Add functions with one operand and one immediate */
835 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
836 add_ca, compute_ca, compute_ov) \
837 static void glue(gen_, name)(DisasContext *ctx) \
838 { \
839 TCGv t0 = tcg_const_tl(const_val); \
840 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
841 cpu_gpr[rA(ctx->opcode)], t0, \
842 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
843 tcg_temp_free(t0); \
844 }
845
846 /* add add. addo addo. */
847 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
848 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
849 /* addc addc. addco addco. */
850 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
851 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
852 /* adde adde. addeo addeo. */
853 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
854 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
855 /* addme addme. addmeo addmeo. */
856 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
857 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
858 /* addze addze. addzeo addzeo.*/
859 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
860 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
861 /* addi */
862 static void gen_addi(DisasContext *ctx)
863 {
864 target_long simm = SIMM(ctx->opcode);
865
866 if (rA(ctx->opcode) == 0) {
867 /* li case */
868 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
869 } else {
870 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
871 cpu_gpr[rA(ctx->opcode)], simm);
872 }
873 }
874 /* addic addic.*/
875 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
876 {
877 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
878 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
879 c, 0, 1, 0, compute_rc0);
880 tcg_temp_free(c);
881 }
882
883 static void gen_addic(DisasContext *ctx)
884 {
885 gen_op_addic(ctx, 0);
886 }
887
888 static void gen_addic_(DisasContext *ctx)
889 {
890 gen_op_addic(ctx, 1);
891 }
892
893 /* addis */
894 static void gen_addis(DisasContext *ctx)
895 {
896 target_long simm = SIMM(ctx->opcode);
897
898 if (rA(ctx->opcode) == 0) {
899 /* lis case */
900 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
901 } else {
902 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
903 cpu_gpr[rA(ctx->opcode)], simm << 16);
904 }
905 }
906
907 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
908 TCGv arg2, int sign, int compute_ov)
909 {
910 int l1 = gen_new_label();
911 int l2 = gen_new_label();
912 TCGv_i32 t0 = tcg_temp_local_new_i32();
913 TCGv_i32 t1 = tcg_temp_local_new_i32();
914
915 tcg_gen_trunc_tl_i32(t0, arg1);
916 tcg_gen_trunc_tl_i32(t1, arg2);
917 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
918 if (sign) {
919 int l3 = gen_new_label();
920 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
921 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
922 gen_set_label(l3);
923 tcg_gen_div_i32(t0, t0, t1);
924 } else {
925 tcg_gen_divu_i32(t0, t0, t1);
926 }
927 if (compute_ov) {
928 tcg_gen_movi_tl(cpu_ov, 0);
929 }
930 tcg_gen_br(l2);
931 gen_set_label(l1);
932 if (sign) {
933 tcg_gen_sari_i32(t0, t0, 31);
934 } else {
935 tcg_gen_movi_i32(t0, 0);
936 }
937 if (compute_ov) {
938 tcg_gen_movi_tl(cpu_ov, 1);
939 tcg_gen_movi_tl(cpu_so, 1);
940 }
941 gen_set_label(l2);
942 tcg_gen_extu_i32_tl(ret, t0);
943 tcg_temp_free_i32(t0);
944 tcg_temp_free_i32(t1);
945 if (unlikely(Rc(ctx->opcode) != 0))
946 gen_set_Rc0(ctx, ret);
947 }
948 /* Div functions */
949 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
950 static void glue(gen_, name)(DisasContext *ctx) \
951 { \
952 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
953 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
954 sign, compute_ov); \
955 }
956 /* divwu divwu. divwuo divwuo. */
957 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
958 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
959 /* divw divw. divwo divwo. */
960 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
961 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
962 #if defined(TARGET_PPC64)
963 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
964 TCGv arg2, int sign, int compute_ov)
965 {
966 int l1 = gen_new_label();
967 int l2 = gen_new_label();
968
969 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
970 if (sign) {
971 int l3 = gen_new_label();
972 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
973 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
974 gen_set_label(l3);
975 tcg_gen_div_i64(ret, arg1, arg2);
976 } else {
977 tcg_gen_divu_i64(ret, arg1, arg2);
978 }
979 if (compute_ov) {
980 tcg_gen_movi_tl(cpu_ov, 0);
981 }
982 tcg_gen_br(l2);
983 gen_set_label(l1);
984 if (sign) {
985 tcg_gen_sari_i64(ret, arg1, 63);
986 } else {
987 tcg_gen_movi_i64(ret, 0);
988 }
989 if (compute_ov) {
990 tcg_gen_movi_tl(cpu_ov, 1);
991 tcg_gen_movi_tl(cpu_so, 1);
992 }
993 gen_set_label(l2);
994 if (unlikely(Rc(ctx->opcode) != 0))
995 gen_set_Rc0(ctx, ret);
996 }
997 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
998 static void glue(gen_, name)(DisasContext *ctx) \
999 { \
1000 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1001 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1002 sign, compute_ov); \
1003 }
1004 /* divwu divwu. divwuo divwuo. */
1005 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1006 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1007 /* divw divw. divwo divwo. */
1008 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1009 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1010 #endif
1011
1012 /* mulhw mulhw. */
1013 static void gen_mulhw(DisasContext *ctx)
1014 {
1015 TCGv_i32 t0 = tcg_temp_new_i32();
1016 TCGv_i32 t1 = tcg_temp_new_i32();
1017
1018 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1019 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1020 tcg_gen_muls2_i32(t0, t1, t0, t1);
1021 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1022 tcg_temp_free_i32(t0);
1023 tcg_temp_free_i32(t1);
1024 if (unlikely(Rc(ctx->opcode) != 0))
1025 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1026 }
1027
1028 /* mulhwu mulhwu. */
1029 static void gen_mulhwu(DisasContext *ctx)
1030 {
1031 TCGv_i32 t0 = tcg_temp_new_i32();
1032 TCGv_i32 t1 = tcg_temp_new_i32();
1033
1034 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1035 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1036 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1037 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1038 tcg_temp_free_i32(t0);
1039 tcg_temp_free_i32(t1);
1040 if (unlikely(Rc(ctx->opcode) != 0))
1041 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1042 }
1043
1044 /* mullw mullw. */
1045 static void gen_mullw(DisasContext *ctx)
1046 {
1047 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1048 cpu_gpr[rB(ctx->opcode)]);
1049 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1050 if (unlikely(Rc(ctx->opcode) != 0))
1051 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1052 }
1053
1054 /* mullwo mullwo. */
1055 static void gen_mullwo(DisasContext *ctx)
1056 {
1057 TCGv_i32 t0 = tcg_temp_new_i32();
1058 TCGv_i32 t1 = tcg_temp_new_i32();
1059
1060 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1061 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1062 tcg_gen_muls2_i32(t0, t1, t0, t1);
1063 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1064
1065 tcg_gen_sari_i32(t0, t0, 31);
1066 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1067 tcg_gen_extu_i32_tl(cpu_ov, t0);
1068 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1069
1070 tcg_temp_free_i32(t0);
1071 tcg_temp_free_i32(t1);
1072 if (unlikely(Rc(ctx->opcode) != 0))
1073 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1074 }
1075
1076 /* mulli */
1077 static void gen_mulli(DisasContext *ctx)
1078 {
1079 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1080 SIMM(ctx->opcode));
1081 }
1082
1083 #if defined(TARGET_PPC64)
1084 /* mulhd mulhd. */
1085 static void gen_mulhd(DisasContext *ctx)
1086 {
1087 TCGv lo = tcg_temp_new();
1088 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1089 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1090 tcg_temp_free(lo);
1091 if (unlikely(Rc(ctx->opcode) != 0)) {
1092 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1093 }
1094 }
1095
1096 /* mulhdu mulhdu. */
1097 static void gen_mulhdu(DisasContext *ctx)
1098 {
1099 TCGv lo = tcg_temp_new();
1100 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1101 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1102 tcg_temp_free(lo);
1103 if (unlikely(Rc(ctx->opcode) != 0)) {
1104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1105 }
1106 }
1107
1108 /* mulld mulld. */
1109 static void gen_mulld(DisasContext *ctx)
1110 {
1111 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1112 cpu_gpr[rB(ctx->opcode)]);
1113 if (unlikely(Rc(ctx->opcode) != 0))
1114 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1115 }
1116
1117 /* mulldo mulldo. */
1118 static void gen_mulldo(DisasContext *ctx)
1119 {
1120 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1121 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1122 if (unlikely(Rc(ctx->opcode) != 0)) {
1123 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1124 }
1125 }
1126 #endif
1127
1128 /* Common subf function */
1129 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1130 TCGv arg2, bool add_ca, bool compute_ca,
1131 bool compute_ov, bool compute_rc0)
1132 {
1133 TCGv t0 = ret;
1134
1135 if (compute_ca || compute_ov) {
1136 t0 = tcg_temp_new();
1137 }
1138
1139 if (compute_ca) {
1140 /* dest = ~arg1 + arg2 [+ ca]. */
1141 if (NARROW_MODE(ctx)) {
1142 /* Caution: a non-obvious corner case of the spec is that we
1143 must produce the *entire* 64-bit addition, but produce the
1144 carry into bit 32. */
1145 TCGv inv1 = tcg_temp_new();
1146 TCGv t1 = tcg_temp_new();
1147 tcg_gen_not_tl(inv1, arg1);
1148 if (add_ca) {
1149 tcg_gen_add_tl(t0, arg2, cpu_ca);
1150 } else {
1151 tcg_gen_addi_tl(t0, arg2, 1);
1152 }
1153 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1154 tcg_gen_add_tl(t0, t0, inv1);
1155 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1156 tcg_temp_free(t1);
1157 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1158 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1159 } else if (add_ca) {
1160 TCGv zero, inv1 = tcg_temp_new();
1161 tcg_gen_not_tl(inv1, arg1);
1162 zero = tcg_const_tl(0);
1163 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1164 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1165 tcg_temp_free(zero);
1166 tcg_temp_free(inv1);
1167 } else {
1168 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1169 tcg_gen_sub_tl(t0, arg2, arg1);
1170 }
1171 } else if (add_ca) {
1172 /* Since we're ignoring carry-out, we can simplify the
1173 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1174 tcg_gen_sub_tl(t0, arg2, arg1);
1175 tcg_gen_add_tl(t0, t0, cpu_ca);
1176 tcg_gen_subi_tl(t0, t0, 1);
1177 } else {
1178 tcg_gen_sub_tl(t0, arg2, arg1);
1179 }
1180
1181 if (compute_ov) {
1182 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1183 }
1184 if (unlikely(compute_rc0)) {
1185 gen_set_Rc0(ctx, t0);
1186 }
1187
1188 if (!TCGV_EQUAL(t0, ret)) {
1189 tcg_gen_mov_tl(ret, t0);
1190 tcg_temp_free(t0);
1191 }
1192 }
1193 /* Sub functions with Two operands functions */
1194 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1195 static void glue(gen_, name)(DisasContext *ctx) \
1196 { \
1197 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1198 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1199 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1200 }
1201 /* Sub functions with one operand and one immediate */
1202 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1203 add_ca, compute_ca, compute_ov) \
1204 static void glue(gen_, name)(DisasContext *ctx) \
1205 { \
1206 TCGv t0 = tcg_const_tl(const_val); \
1207 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1208 cpu_gpr[rA(ctx->opcode)], t0, \
1209 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1210 tcg_temp_free(t0); \
1211 }
1212 /* subf subf. subfo subfo. */
1213 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1214 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1215 /* subfc subfc. subfco subfco. */
1216 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1217 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1218 /* subfe subfe. subfeo subfo. */
1219 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1220 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1221 /* subfme subfme. subfmeo subfmeo. */
1222 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1223 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1224 /* subfze subfze. subfzeo subfzeo.*/
1225 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1226 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1227
1228 /* subfic */
1229 static void gen_subfic(DisasContext *ctx)
1230 {
1231 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1232 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1233 c, 0, 1, 0, 0);
1234 tcg_temp_free(c);
1235 }
1236
1237 /* neg neg. nego nego. */
1238 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1239 {
1240 TCGv zero = tcg_const_tl(0);
1241 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1242 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1243 tcg_temp_free(zero);
1244 }
1245
1246 static void gen_neg(DisasContext *ctx)
1247 {
1248 gen_op_arith_neg(ctx, 0);
1249 }
1250
1251 static void gen_nego(DisasContext *ctx)
1252 {
1253 gen_op_arith_neg(ctx, 1);
1254 }
1255
1256 /*** Integer logical ***/
1257 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1258 static void glue(gen_, name)(DisasContext *ctx) \
1259 { \
1260 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1261 cpu_gpr[rB(ctx->opcode)]); \
1262 if (unlikely(Rc(ctx->opcode) != 0)) \
1263 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1264 }
1265
1266 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1267 static void glue(gen_, name)(DisasContext *ctx) \
1268 { \
1269 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1270 if (unlikely(Rc(ctx->opcode) != 0)) \
1271 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1272 }
1273
1274 /* and & and. */
1275 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1276 /* andc & andc. */
1277 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1278
1279 /* andi. */
1280 static void gen_andi_(DisasContext *ctx)
1281 {
1282 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1283 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1284 }
1285
1286 /* andis. */
1287 static void gen_andis_(DisasContext *ctx)
1288 {
1289 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1290 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1291 }
1292
1293 /* cntlzw */
1294 static void gen_cntlzw(DisasContext *ctx)
1295 {
1296 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1297 if (unlikely(Rc(ctx->opcode) != 0))
1298 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1299 }
1300 /* eqv & eqv. */
1301 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1302 /* extsb & extsb. */
1303 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1304 /* extsh & extsh. */
1305 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1306 /* nand & nand. */
1307 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1308 /* nor & nor. */
1309 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1310
1311 /* or & or. */
1312 static void gen_or(DisasContext *ctx)
1313 {
1314 int rs, ra, rb;
1315
1316 rs = rS(ctx->opcode);
1317 ra = rA(ctx->opcode);
1318 rb = rB(ctx->opcode);
1319 /* Optimisation for mr. ri case */
1320 if (rs != ra || rs != rb) {
1321 if (rs != rb)
1322 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1323 else
1324 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1325 if (unlikely(Rc(ctx->opcode) != 0))
1326 gen_set_Rc0(ctx, cpu_gpr[ra]);
1327 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1328 gen_set_Rc0(ctx, cpu_gpr[rs]);
1329 #if defined(TARGET_PPC64)
1330 } else {
1331 int prio = 0;
1332
1333 switch (rs) {
1334 case 1:
1335 /* Set process priority to low */
1336 prio = 2;
1337 break;
1338 case 6:
1339 /* Set process priority to medium-low */
1340 prio = 3;
1341 break;
1342 case 2:
1343 /* Set process priority to normal */
1344 prio = 4;
1345 break;
1346 #if !defined(CONFIG_USER_ONLY)
1347 case 31:
1348 if (ctx->mem_idx > 0) {
1349 /* Set process priority to very low */
1350 prio = 1;
1351 }
1352 break;
1353 case 5:
1354 if (ctx->mem_idx > 0) {
1355 /* Set process priority to medium-hight */
1356 prio = 5;
1357 }
1358 break;
1359 case 3:
1360 if (ctx->mem_idx > 0) {
1361 /* Set process priority to high */
1362 prio = 6;
1363 }
1364 break;
1365 case 7:
1366 if (ctx->mem_idx > 1) {
1367 /* Set process priority to very high */
1368 prio = 7;
1369 }
1370 break;
1371 #endif
1372 default:
1373 /* nop */
1374 break;
1375 }
1376 if (prio) {
1377 TCGv t0 = tcg_temp_new();
1378 gen_load_spr(t0, SPR_PPR);
1379 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1380 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1381 gen_store_spr(SPR_PPR, t0);
1382 tcg_temp_free(t0);
1383 }
1384 #endif
1385 }
1386 }
1387 /* orc & orc. */
1388 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1389
1390 /* xor & xor. */
1391 static void gen_xor(DisasContext *ctx)
1392 {
1393 /* Optimisation for "set to zero" case */
1394 if (rS(ctx->opcode) != rB(ctx->opcode))
1395 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1396 else
1397 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1398 if (unlikely(Rc(ctx->opcode) != 0))
1399 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1400 }
1401
1402 /* ori */
1403 static void gen_ori(DisasContext *ctx)
1404 {
1405 target_ulong uimm = UIMM(ctx->opcode);
1406
1407 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1408 /* NOP */
1409 /* XXX: should handle special NOPs for POWER series */
1410 return;
1411 }
1412 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1413 }
1414
1415 /* oris */
1416 static void gen_oris(DisasContext *ctx)
1417 {
1418 target_ulong uimm = UIMM(ctx->opcode);
1419
1420 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1421 /* NOP */
1422 return;
1423 }
1424 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1425 }
1426
1427 /* xori */
1428 static void gen_xori(DisasContext *ctx)
1429 {
1430 target_ulong uimm = UIMM(ctx->opcode);
1431
1432 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1433 /* NOP */
1434 return;
1435 }
1436 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1437 }
1438
1439 /* xoris */
1440 static void gen_xoris(DisasContext *ctx)
1441 {
1442 target_ulong uimm = UIMM(ctx->opcode);
1443
1444 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1445 /* NOP */
1446 return;
1447 }
1448 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1449 }
1450
1451 /* popcntb : PowerPC 2.03 specification */
1452 static void gen_popcntb(DisasContext *ctx)
1453 {
1454 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1455 }
1456
1457 static void gen_popcntw(DisasContext *ctx)
1458 {
1459 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1460 }
1461
1462 #if defined(TARGET_PPC64)
1463 /* popcntd: PowerPC 2.06 specification */
1464 static void gen_popcntd(DisasContext *ctx)
1465 {
1466 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1467 }
1468 #endif
1469
1470 /* prtyw: PowerPC 2.05 specification */
1471 static void gen_prtyw(DisasContext *ctx)
1472 {
1473 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1474 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1475 TCGv t0 = tcg_temp_new();
1476 tcg_gen_shri_tl(t0, rs, 16);
1477 tcg_gen_xor_tl(ra, rs, t0);
1478 tcg_gen_shri_tl(t0, ra, 8);
1479 tcg_gen_xor_tl(ra, ra, t0);
1480 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1481 tcg_temp_free(t0);
1482 }
1483
1484 #if defined(TARGET_PPC64)
1485 /* prtyd: PowerPC 2.05 specification */
1486 static void gen_prtyd(DisasContext *ctx)
1487 {
1488 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1489 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1490 TCGv t0 = tcg_temp_new();
1491 tcg_gen_shri_tl(t0, rs, 32);
1492 tcg_gen_xor_tl(ra, rs, t0);
1493 tcg_gen_shri_tl(t0, ra, 16);
1494 tcg_gen_xor_tl(ra, ra, t0);
1495 tcg_gen_shri_tl(t0, ra, 8);
1496 tcg_gen_xor_tl(ra, ra, t0);
1497 tcg_gen_andi_tl(ra, ra, 1);
1498 tcg_temp_free(t0);
1499 }
1500 #endif
1501
1502 #if defined(TARGET_PPC64)
1503 /* extsw & extsw. */
1504 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1505
1506 /* cntlzd */
1507 static void gen_cntlzd(DisasContext *ctx)
1508 {
1509 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1510 if (unlikely(Rc(ctx->opcode) != 0))
1511 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1512 }
1513 #endif
1514
1515 /*** Integer rotate ***/
1516
1517 /* rlwimi & rlwimi. */
1518 static void gen_rlwimi(DisasContext *ctx)
1519 {
1520 uint32_t mb, me, sh;
1521
1522 mb = MB(ctx->opcode);
1523 me = ME(ctx->opcode);
1524 sh = SH(ctx->opcode);
1525 if (likely(sh == 0 && mb == 0 && me == 31)) {
1526 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1527 } else {
1528 target_ulong mask;
1529 TCGv t1;
1530 TCGv t0 = tcg_temp_new();
1531 #if defined(TARGET_PPC64)
1532 TCGv_i32 t2 = tcg_temp_new_i32();
1533 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1534 tcg_gen_rotli_i32(t2, t2, sh);
1535 tcg_gen_extu_i32_i64(t0, t2);
1536 tcg_temp_free_i32(t2);
1537 #else
1538 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1539 #endif
1540 #if defined(TARGET_PPC64)
1541 mb += 32;
1542 me += 32;
1543 #endif
1544 mask = MASK(mb, me);
1545 t1 = tcg_temp_new();
1546 tcg_gen_andi_tl(t0, t0, mask);
1547 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1548 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1549 tcg_temp_free(t0);
1550 tcg_temp_free(t1);
1551 }
1552 if (unlikely(Rc(ctx->opcode) != 0))
1553 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1554 }
1555
1556 /* rlwinm & rlwinm. */
1557 static void gen_rlwinm(DisasContext *ctx)
1558 {
1559 uint32_t mb, me, sh;
1560
1561 sh = SH(ctx->opcode);
1562 mb = MB(ctx->opcode);
1563 me = ME(ctx->opcode);
1564
1565 if (likely(mb == 0 && me == (31 - sh))) {
1566 if (likely(sh == 0)) {
1567 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1568 } else {
1569 TCGv t0 = tcg_temp_new();
1570 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1571 tcg_gen_shli_tl(t0, t0, sh);
1572 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1573 tcg_temp_free(t0);
1574 }
1575 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1576 TCGv t0 = tcg_temp_new();
1577 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1578 tcg_gen_shri_tl(t0, t0, mb);
1579 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1580 tcg_temp_free(t0);
1581 } else {
1582 TCGv t0 = tcg_temp_new();
1583 #if defined(TARGET_PPC64)
1584 TCGv_i32 t1 = tcg_temp_new_i32();
1585 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1586 tcg_gen_rotli_i32(t1, t1, sh);
1587 tcg_gen_extu_i32_i64(t0, t1);
1588 tcg_temp_free_i32(t1);
1589 #else
1590 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1591 #endif
1592 #if defined(TARGET_PPC64)
1593 mb += 32;
1594 me += 32;
1595 #endif
1596 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1597 tcg_temp_free(t0);
1598 }
1599 if (unlikely(Rc(ctx->opcode) != 0))
1600 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1601 }
1602
1603 /* rlwnm & rlwnm. */
1604 static void gen_rlwnm(DisasContext *ctx)
1605 {
1606 uint32_t mb, me;
1607 TCGv t0;
1608 #if defined(TARGET_PPC64)
1609 TCGv_i32 t1, t2;
1610 #endif
1611
1612 mb = MB(ctx->opcode);
1613 me = ME(ctx->opcode);
1614 t0 = tcg_temp_new();
1615 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1616 #if defined(TARGET_PPC64)
1617 t1 = tcg_temp_new_i32();
1618 t2 = tcg_temp_new_i32();
1619 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1620 tcg_gen_trunc_i64_i32(t2, t0);
1621 tcg_gen_rotl_i32(t1, t1, t2);
1622 tcg_gen_extu_i32_i64(t0, t1);
1623 tcg_temp_free_i32(t1);
1624 tcg_temp_free_i32(t2);
1625 #else
1626 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1627 #endif
1628 if (unlikely(mb != 0 || me != 31)) {
1629 #if defined(TARGET_PPC64)
1630 mb += 32;
1631 me += 32;
1632 #endif
1633 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1634 } else {
1635 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1636 }
1637 tcg_temp_free(t0);
1638 if (unlikely(Rc(ctx->opcode) != 0))
1639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1640 }
1641
1642 #if defined(TARGET_PPC64)
1643 #define GEN_PPC64_R2(name, opc1, opc2) \
1644 static void glue(gen_, name##0)(DisasContext *ctx) \
1645 { \
1646 gen_##name(ctx, 0); \
1647 } \
1648 \
1649 static void glue(gen_, name##1)(DisasContext *ctx) \
1650 { \
1651 gen_##name(ctx, 1); \
1652 }
1653 #define GEN_PPC64_R4(name, opc1, opc2) \
1654 static void glue(gen_, name##0)(DisasContext *ctx) \
1655 { \
1656 gen_##name(ctx, 0, 0); \
1657 } \
1658 \
1659 static void glue(gen_, name##1)(DisasContext *ctx) \
1660 { \
1661 gen_##name(ctx, 0, 1); \
1662 } \
1663 \
1664 static void glue(gen_, name##2)(DisasContext *ctx) \
1665 { \
1666 gen_##name(ctx, 1, 0); \
1667 } \
1668 \
1669 static void glue(gen_, name##3)(DisasContext *ctx) \
1670 { \
1671 gen_##name(ctx, 1, 1); \
1672 }
1673
1674 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1675 uint32_t sh)
1676 {
1677 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1678 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1679 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1680 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1681 } else {
1682 TCGv t0 = tcg_temp_new();
1683 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1684 if (likely(mb == 0 && me == 63)) {
1685 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1686 } else {
1687 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1688 }
1689 tcg_temp_free(t0);
1690 }
1691 if (unlikely(Rc(ctx->opcode) != 0))
1692 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1693 }
1694 /* rldicl - rldicl. */
1695 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1696 {
1697 uint32_t sh, mb;
1698
1699 sh = SH(ctx->opcode) | (shn << 5);
1700 mb = MB(ctx->opcode) | (mbn << 5);
1701 gen_rldinm(ctx, mb, 63, sh);
1702 }
1703 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1704 /* rldicr - rldicr. */
1705 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1706 {
1707 uint32_t sh, me;
1708
1709 sh = SH(ctx->opcode) | (shn << 5);
1710 me = MB(ctx->opcode) | (men << 5);
1711 gen_rldinm(ctx, 0, me, sh);
1712 }
1713 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1714 /* rldic - rldic. */
1715 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1716 {
1717 uint32_t sh, mb;
1718
1719 sh = SH(ctx->opcode) | (shn << 5);
1720 mb = MB(ctx->opcode) | (mbn << 5);
1721 gen_rldinm(ctx, mb, 63 - sh, sh);
1722 }
1723 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1724
1725 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1726 {
1727 TCGv t0;
1728
1729 mb = MB(ctx->opcode);
1730 me = ME(ctx->opcode);
1731 t0 = tcg_temp_new();
1732 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1733 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1734 if (unlikely(mb != 0 || me != 63)) {
1735 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1736 } else {
1737 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1738 }
1739 tcg_temp_free(t0);
1740 if (unlikely(Rc(ctx->opcode) != 0))
1741 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1742 }
1743
1744 /* rldcl - rldcl. */
1745 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1746 {
1747 uint32_t mb;
1748
1749 mb = MB(ctx->opcode) | (mbn << 5);
1750 gen_rldnm(ctx, mb, 63);
1751 }
1752 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1753 /* rldcr - rldcr. */
1754 static inline void gen_rldcr(DisasContext *ctx, int men)
1755 {
1756 uint32_t me;
1757
1758 me = MB(ctx->opcode) | (men << 5);
1759 gen_rldnm(ctx, 0, me);
1760 }
1761 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1762 /* rldimi - rldimi. */
1763 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1764 {
1765 uint32_t sh, mb, me;
1766
1767 sh = SH(ctx->opcode) | (shn << 5);
1768 mb = MB(ctx->opcode) | (mbn << 5);
1769 me = 63 - sh;
1770 if (unlikely(sh == 0 && mb == 0)) {
1771 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1772 } else {
1773 TCGv t0, t1;
1774 target_ulong mask;
1775
1776 t0 = tcg_temp_new();
1777 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1778 t1 = tcg_temp_new();
1779 mask = MASK(mb, me);
1780 tcg_gen_andi_tl(t0, t0, mask);
1781 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1782 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1783 tcg_temp_free(t0);
1784 tcg_temp_free(t1);
1785 }
1786 if (unlikely(Rc(ctx->opcode) != 0))
1787 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1788 }
1789 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1790 #endif
1791
1792 /*** Integer shift ***/
1793
1794 /* slw & slw. */
1795 static void gen_slw(DisasContext *ctx)
1796 {
1797 TCGv t0, t1;
1798
1799 t0 = tcg_temp_new();
1800 /* AND rS with a mask that is 0 when rB >= 0x20 */
1801 #if defined(TARGET_PPC64)
1802 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1803 tcg_gen_sari_tl(t0, t0, 0x3f);
1804 #else
1805 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1806 tcg_gen_sari_tl(t0, t0, 0x1f);
1807 #endif
1808 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1809 t1 = tcg_temp_new();
1810 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1811 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1812 tcg_temp_free(t1);
1813 tcg_temp_free(t0);
1814 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1815 if (unlikely(Rc(ctx->opcode) != 0))
1816 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1817 }
1818
1819 /* sraw & sraw. */
1820 static void gen_sraw(DisasContext *ctx)
1821 {
1822 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1823 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1824 if (unlikely(Rc(ctx->opcode) != 0))
1825 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1826 }
1827
1828 /* srawi & srawi. */
1829 static void gen_srawi(DisasContext *ctx)
1830 {
1831 int sh = SH(ctx->opcode);
1832 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1833 TCGv src = cpu_gpr[rS(ctx->opcode)];
1834 if (sh == 0) {
1835 tcg_gen_mov_tl(dst, src);
1836 tcg_gen_movi_tl(cpu_ca, 0);
1837 } else {
1838 TCGv t0;
1839 tcg_gen_ext32s_tl(dst, src);
1840 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1841 t0 = tcg_temp_new();
1842 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1843 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1844 tcg_temp_free(t0);
1845 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1846 tcg_gen_sari_tl(dst, dst, sh);
1847 }
1848 if (unlikely(Rc(ctx->opcode) != 0)) {
1849 gen_set_Rc0(ctx, dst);
1850 }
1851 }
1852
1853 /* srw & srw. */
1854 static void gen_srw(DisasContext *ctx)
1855 {
1856 TCGv t0, t1;
1857
1858 t0 = tcg_temp_new();
1859 /* AND rS with a mask that is 0 when rB >= 0x20 */
1860 #if defined(TARGET_PPC64)
1861 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1862 tcg_gen_sari_tl(t0, t0, 0x3f);
1863 #else
1864 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1865 tcg_gen_sari_tl(t0, t0, 0x1f);
1866 #endif
1867 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1868 tcg_gen_ext32u_tl(t0, t0);
1869 t1 = tcg_temp_new();
1870 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1871 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1872 tcg_temp_free(t1);
1873 tcg_temp_free(t0);
1874 if (unlikely(Rc(ctx->opcode) != 0))
1875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1876 }
1877
1878 #if defined(TARGET_PPC64)
1879 /* sld & sld. */
1880 static void gen_sld(DisasContext *ctx)
1881 {
1882 TCGv t0, t1;
1883
1884 t0 = tcg_temp_new();
1885 /* AND rS with a mask that is 0 when rB >= 0x40 */
1886 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1887 tcg_gen_sari_tl(t0, t0, 0x3f);
1888 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1889 t1 = tcg_temp_new();
1890 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1891 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1892 tcg_temp_free(t1);
1893 tcg_temp_free(t0);
1894 if (unlikely(Rc(ctx->opcode) != 0))
1895 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1896 }
1897
1898 /* srad & srad. */
1899 static void gen_srad(DisasContext *ctx)
1900 {
1901 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1902 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1903 if (unlikely(Rc(ctx->opcode) != 0))
1904 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1905 }
1906 /* sradi & sradi. */
1907 static inline void gen_sradi(DisasContext *ctx, int n)
1908 {
1909 int sh = SH(ctx->opcode) + (n << 5);
1910 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1911 TCGv src = cpu_gpr[rS(ctx->opcode)];
1912 if (sh == 0) {
1913 tcg_gen_mov_tl(dst, src);
1914 tcg_gen_movi_tl(cpu_ca, 0);
1915 } else {
1916 TCGv t0;
1917 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1918 t0 = tcg_temp_new();
1919 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1920 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1921 tcg_temp_free(t0);
1922 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1923 tcg_gen_sari_tl(dst, src, sh);
1924 }
1925 if (unlikely(Rc(ctx->opcode) != 0)) {
1926 gen_set_Rc0(ctx, dst);
1927 }
1928 }
1929
1930 static void gen_sradi0(DisasContext *ctx)
1931 {
1932 gen_sradi(ctx, 0);
1933 }
1934
1935 static void gen_sradi1(DisasContext *ctx)
1936 {
1937 gen_sradi(ctx, 1);
1938 }
1939
1940 /* srd & srd. */
1941 static void gen_srd(DisasContext *ctx)
1942 {
1943 TCGv t0, t1;
1944
1945 t0 = tcg_temp_new();
1946 /* AND rS with a mask that is 0 when rB >= 0x40 */
1947 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1948 tcg_gen_sari_tl(t0, t0, 0x3f);
1949 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1950 t1 = tcg_temp_new();
1951 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1952 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1953 tcg_temp_free(t1);
1954 tcg_temp_free(t0);
1955 if (unlikely(Rc(ctx->opcode) != 0))
1956 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1957 }
1958 #endif
1959
1960 /*** Floating-Point arithmetic ***/
1961 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1962 static void gen_f##name(DisasContext *ctx) \
1963 { \
1964 if (unlikely(!ctx->fpu_enabled)) { \
1965 gen_exception(ctx, POWERPC_EXCP_FPU); \
1966 return; \
1967 } \
1968 /* NIP cannot be restored if the memory exception comes from an helper */ \
1969 gen_update_nip(ctx, ctx->nip - 4); \
1970 gen_reset_fpstatus(); \
1971 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1972 cpu_fpr[rA(ctx->opcode)], \
1973 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1974 if (isfloat) { \
1975 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1976 cpu_fpr[rD(ctx->opcode)]); \
1977 } \
1978 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1979 Rc(ctx->opcode) != 0); \
1980 }
1981
1982 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1983 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1984 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1985
1986 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1987 static void gen_f##name(DisasContext *ctx) \
1988 { \
1989 if (unlikely(!ctx->fpu_enabled)) { \
1990 gen_exception(ctx, POWERPC_EXCP_FPU); \
1991 return; \
1992 } \
1993 /* NIP cannot be restored if the memory exception comes from an helper */ \
1994 gen_update_nip(ctx, ctx->nip - 4); \
1995 gen_reset_fpstatus(); \
1996 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1997 cpu_fpr[rA(ctx->opcode)], \
1998 cpu_fpr[rB(ctx->opcode)]); \
1999 if (isfloat) { \
2000 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2001 cpu_fpr[rD(ctx->opcode)]); \
2002 } \
2003 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2004 set_fprf, Rc(ctx->opcode) != 0); \
2005 }
2006 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2007 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2008 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2009
2010 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2011 static void gen_f##name(DisasContext *ctx) \
2012 { \
2013 if (unlikely(!ctx->fpu_enabled)) { \
2014 gen_exception(ctx, POWERPC_EXCP_FPU); \
2015 return; \
2016 } \
2017 /* NIP cannot be restored if the memory exception comes from an helper */ \
2018 gen_update_nip(ctx, ctx->nip - 4); \
2019 gen_reset_fpstatus(); \
2020 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2021 cpu_fpr[rA(ctx->opcode)], \
2022 cpu_fpr[rC(ctx->opcode)]); \
2023 if (isfloat) { \
2024 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2025 cpu_fpr[rD(ctx->opcode)]); \
2026 } \
2027 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2028 set_fprf, Rc(ctx->opcode) != 0); \
2029 }
2030 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2031 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2032 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2033
2034 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2035 static void gen_f##name(DisasContext *ctx) \
2036 { \
2037 if (unlikely(!ctx->fpu_enabled)) { \
2038 gen_exception(ctx, POWERPC_EXCP_FPU); \
2039 return; \
2040 } \
2041 /* NIP cannot be restored if the memory exception comes from an helper */ \
2042 gen_update_nip(ctx, ctx->nip - 4); \
2043 gen_reset_fpstatus(); \
2044 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2045 cpu_fpr[rB(ctx->opcode)]); \
2046 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2047 set_fprf, Rc(ctx->opcode) != 0); \
2048 }
2049
2050 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2051 static void gen_f##name(DisasContext *ctx) \
2052 { \
2053 if (unlikely(!ctx->fpu_enabled)) { \
2054 gen_exception(ctx, POWERPC_EXCP_FPU); \
2055 return; \
2056 } \
2057 /* NIP cannot be restored if the memory exception comes from an helper */ \
2058 gen_update_nip(ctx, ctx->nip - 4); \
2059 gen_reset_fpstatus(); \
2060 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2061 cpu_fpr[rB(ctx->opcode)]); \
2062 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2063 set_fprf, Rc(ctx->opcode) != 0); \
2064 }
2065
2066 /* fadd - fadds */
2067 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2068 /* fdiv - fdivs */
2069 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2070 /* fmul - fmuls */
2071 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2072
2073 /* fre */
2074 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2075
2076 /* fres */
2077 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2078
2079 /* frsqrte */
2080 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2081
2082 /* frsqrtes */
2083 static void gen_frsqrtes(DisasContext *ctx)
2084 {
2085 if (unlikely(!ctx->fpu_enabled)) {
2086 gen_exception(ctx, POWERPC_EXCP_FPU);
2087 return;
2088 }
2089 /* NIP cannot be restored if the memory exception comes from an helper */
2090 gen_update_nip(ctx, ctx->nip - 4);
2091 gen_reset_fpstatus();
2092 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2093 cpu_fpr[rB(ctx->opcode)]);
2094 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2095 cpu_fpr[rD(ctx->opcode)]);
2096 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2097 }
2098
2099 /* fsel */
2100 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2101 /* fsub - fsubs */
2102 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2103 /* Optional: */
2104
2105 /* fsqrt */
2106 static void gen_fsqrt(DisasContext *ctx)
2107 {
2108 if (unlikely(!ctx->fpu_enabled)) {
2109 gen_exception(ctx, POWERPC_EXCP_FPU);
2110 return;
2111 }
2112 /* NIP cannot be restored if the memory exception comes from an helper */
2113 gen_update_nip(ctx, ctx->nip - 4);
2114 gen_reset_fpstatus();
2115 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2116 cpu_fpr[rB(ctx->opcode)]);
2117 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2118 }
2119
2120 static void gen_fsqrts(DisasContext *ctx)
2121 {
2122 if (unlikely(!ctx->fpu_enabled)) {
2123 gen_exception(ctx, POWERPC_EXCP_FPU);
2124 return;
2125 }
2126 /* NIP cannot be restored if the memory exception comes from an helper */
2127 gen_update_nip(ctx, ctx->nip - 4);
2128 gen_reset_fpstatus();
2129 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2130 cpu_fpr[rB(ctx->opcode)]);
2131 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2132 cpu_fpr[rD(ctx->opcode)]);
2133 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2134 }
2135
2136 /*** Floating-Point multiply-and-add ***/
2137 /* fmadd - fmadds */
2138 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2139 /* fmsub - fmsubs */
2140 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2141 /* fnmadd - fnmadds */
2142 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2143 /* fnmsub - fnmsubs */
2144 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2145
2146 /*** Floating-Point round & convert ***/
2147 /* fctiw */
2148 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2149 /* fctiwz */
2150 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2151 /* frsp */
2152 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2153 #if defined(TARGET_PPC64)
2154 /* fcfid */
2155 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2156 /* fctid */
2157 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2158 /* fctidz */
2159 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2160 #endif
2161
2162 /* frin */
2163 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2164 /* friz */
2165 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2166 /* frip */
2167 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2168 /* frim */
2169 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2170
2171 /*** Floating-Point compare ***/
2172
2173 /* fcmpo */
2174 static void gen_fcmpo(DisasContext *ctx)
2175 {
2176 TCGv_i32 crf;
2177 if (unlikely(!ctx->fpu_enabled)) {
2178 gen_exception(ctx, POWERPC_EXCP_FPU);
2179 return;
2180 }
2181 /* NIP cannot be restored if the memory exception comes from an helper */
2182 gen_update_nip(ctx, ctx->nip - 4);
2183 gen_reset_fpstatus();
2184 crf = tcg_const_i32(crfD(ctx->opcode));
2185 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2186 cpu_fpr[rB(ctx->opcode)], crf);
2187 tcg_temp_free_i32(crf);
2188 gen_helper_float_check_status(cpu_env);
2189 }
2190
2191 /* fcmpu */
2192 static void gen_fcmpu(DisasContext *ctx)
2193 {
2194 TCGv_i32 crf;
2195 if (unlikely(!ctx->fpu_enabled)) {
2196 gen_exception(ctx, POWERPC_EXCP_FPU);
2197 return;
2198 }
2199 /* NIP cannot be restored if the memory exception comes from an helper */
2200 gen_update_nip(ctx, ctx->nip - 4);
2201 gen_reset_fpstatus();
2202 crf = tcg_const_i32(crfD(ctx->opcode));
2203 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2204 cpu_fpr[rB(ctx->opcode)], crf);
2205 tcg_temp_free_i32(crf);
2206 gen_helper_float_check_status(cpu_env);
2207 }
2208
2209 /*** Floating-point move ***/
2210 /* fabs */
2211 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2212 static void gen_fabs(DisasContext *ctx)
2213 {
2214 if (unlikely(!ctx->fpu_enabled)) {
2215 gen_exception(ctx, POWERPC_EXCP_FPU);
2216 return;
2217 }
2218 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2219 ~(1ULL << 63));
2220 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2221 }
2222
2223 /* fmr - fmr. */
2224 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2225 static void gen_fmr(DisasContext *ctx)
2226 {
2227 if (unlikely(!ctx->fpu_enabled)) {
2228 gen_exception(ctx, POWERPC_EXCP_FPU);
2229 return;
2230 }
2231 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2232 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2233 }
2234
2235 /* fnabs */
2236 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2237 static void gen_fnabs(DisasContext *ctx)
2238 {
2239 if (unlikely(!ctx->fpu_enabled)) {
2240 gen_exception(ctx, POWERPC_EXCP_FPU);
2241 return;
2242 }
2243 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2244 1ULL << 63);
2245 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2246 }
2247
2248 /* fneg */
2249 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2250 static void gen_fneg(DisasContext *ctx)
2251 {
2252 if (unlikely(!ctx->fpu_enabled)) {
2253 gen_exception(ctx, POWERPC_EXCP_FPU);
2254 return;
2255 }
2256 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2257 1ULL << 63);
2258 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2259 }
2260
2261 /* fcpsgn: PowerPC 2.05 specification */
2262 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2263 static void gen_fcpsgn(DisasContext *ctx)
2264 {
2265 if (unlikely(!ctx->fpu_enabled)) {
2266 gen_exception(ctx, POWERPC_EXCP_FPU);
2267 return;
2268 }
2269 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2270 cpu_fpr[rB(ctx->opcode)], 0, 63);
2271 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2272 }
2273
2274 /*** Floating-Point status & ctrl register ***/
2275
2276 /* mcrfs */
2277 static void gen_mcrfs(DisasContext *ctx)
2278 {
2279 TCGv tmp = tcg_temp_new();
2280 int bfa;
2281
2282 if (unlikely(!ctx->fpu_enabled)) {
2283 gen_exception(ctx, POWERPC_EXCP_FPU);
2284 return;
2285 }
2286 bfa = 4 * (7 - crfS(ctx->opcode));
2287 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2288 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2289 tcg_temp_free(tmp);
2290 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2291 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2292 }
2293
2294 /* mffs */
2295 static void gen_mffs(DisasContext *ctx)
2296 {
2297 if (unlikely(!ctx->fpu_enabled)) {
2298 gen_exception(ctx, POWERPC_EXCP_FPU);
2299 return;
2300 }
2301 gen_reset_fpstatus();
2302 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2303 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2304 }
2305
2306 /* mtfsb0 */
2307 static void gen_mtfsb0(DisasContext *ctx)
2308 {
2309 uint8_t crb;
2310
2311 if (unlikely(!ctx->fpu_enabled)) {
2312 gen_exception(ctx, POWERPC_EXCP_FPU);
2313 return;
2314 }
2315 crb = 31 - crbD(ctx->opcode);
2316 gen_reset_fpstatus();
2317 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2318 TCGv_i32 t0;
2319 /* NIP cannot be restored if the memory exception comes from an helper */
2320 gen_update_nip(ctx, ctx->nip - 4);
2321 t0 = tcg_const_i32(crb);
2322 gen_helper_fpscr_clrbit(cpu_env, t0);
2323 tcg_temp_free_i32(t0);
2324 }
2325 if (unlikely(Rc(ctx->opcode) != 0)) {
2326 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2327 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2328 }
2329 }
2330
2331 /* mtfsb1 */
2332 static void gen_mtfsb1(DisasContext *ctx)
2333 {
2334 uint8_t crb;
2335
2336 if (unlikely(!ctx->fpu_enabled)) {
2337 gen_exception(ctx, POWERPC_EXCP_FPU);
2338 return;
2339 }
2340 crb = 31 - crbD(ctx->opcode);
2341 gen_reset_fpstatus();
2342 /* XXX: we pretend we can only do IEEE floating-point computations */
2343 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2344 TCGv_i32 t0;
2345 /* NIP cannot be restored if the memory exception comes from an helper */
2346 gen_update_nip(ctx, ctx->nip - 4);
2347 t0 = tcg_const_i32(crb);
2348 gen_helper_fpscr_setbit(cpu_env, t0);
2349 tcg_temp_free_i32(t0);
2350 }
2351 if (unlikely(Rc(ctx->opcode) != 0)) {
2352 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2353 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2354 }
2355 /* We can raise a differed exception */
2356 gen_helper_float_check_status(cpu_env);
2357 }
2358
2359 /* mtfsf */
2360 static void gen_mtfsf(DisasContext *ctx)
2361 {
2362 TCGv_i32 t0;
2363 int L = ctx->opcode & 0x02000000;
2364
2365 if (unlikely(!ctx->fpu_enabled)) {
2366 gen_exception(ctx, POWERPC_EXCP_FPU);
2367 return;
2368 }
2369 /* NIP cannot be restored if the memory exception comes from an helper */
2370 gen_update_nip(ctx, ctx->nip - 4);
2371 gen_reset_fpstatus();
2372 if (L)
2373 t0 = tcg_const_i32(0xff);
2374 else
2375 t0 = tcg_const_i32(FM(ctx->opcode));
2376 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2377 tcg_temp_free_i32(t0);
2378 if (unlikely(Rc(ctx->opcode) != 0)) {
2379 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2380 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2381 }
2382 /* We can raise a differed exception */
2383 gen_helper_float_check_status(cpu_env);
2384 }
2385
2386 /* mtfsfi */
2387 static void gen_mtfsfi(DisasContext *ctx)
2388 {
2389 int bf, sh;
2390 TCGv_i64 t0;
2391 TCGv_i32 t1;
2392
2393 if (unlikely(!ctx->fpu_enabled)) {
2394 gen_exception(ctx, POWERPC_EXCP_FPU);
2395 return;
2396 }
2397 bf = crbD(ctx->opcode) >> 2;
2398 sh = 7 - bf;
2399 /* NIP cannot be restored if the memory exception comes from an helper */
2400 gen_update_nip(ctx, ctx->nip - 4);
2401 gen_reset_fpstatus();
2402 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2403 t1 = tcg_const_i32(1 << sh);
2404 gen_helper_store_fpscr(cpu_env, t0, t1);
2405 tcg_temp_free_i64(t0);
2406 tcg_temp_free_i32(t1);
2407 if (unlikely(Rc(ctx->opcode) != 0)) {
2408 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2409 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2410 }
2411 /* We can raise a differed exception */
2412 gen_helper_float_check_status(cpu_env);
2413 }
2414
2415 /*** Addressing modes ***/
2416 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2417 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2418 target_long maskl)
2419 {
2420 target_long simm = SIMM(ctx->opcode);
2421
2422 simm &= ~maskl;
2423 if (rA(ctx->opcode) == 0) {
2424 if (NARROW_MODE(ctx)) {
2425 simm = (uint32_t)simm;
2426 }
2427 tcg_gen_movi_tl(EA, simm);
2428 } else if (likely(simm != 0)) {
2429 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2430 if (NARROW_MODE(ctx)) {
2431 tcg_gen_ext32u_tl(EA, EA);
2432 }
2433 } else {
2434 if (NARROW_MODE(ctx)) {
2435 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2436 } else {
2437 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2438 }
2439 }
2440 }
2441
2442 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2443 {
2444 if (rA(ctx->opcode) == 0) {
2445 if (NARROW_MODE(ctx)) {
2446 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2447 } else {
2448 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2449 }
2450 } else {
2451 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2452 if (NARROW_MODE(ctx)) {
2453 tcg_gen_ext32u_tl(EA, EA);
2454 }
2455 }
2456 }
2457
2458 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2459 {
2460 if (rA(ctx->opcode) == 0) {
2461 tcg_gen_movi_tl(EA, 0);
2462 } else if (NARROW_MODE(ctx)) {
2463 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2464 } else {
2465 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2466 }
2467 }
2468
2469 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2470 target_long val)
2471 {
2472 tcg_gen_addi_tl(ret, arg1, val);
2473 if (NARROW_MODE(ctx)) {
2474 tcg_gen_ext32u_tl(ret, ret);
2475 }
2476 }
2477
2478 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2479 {
2480 int l1 = gen_new_label();
2481 TCGv t0 = tcg_temp_new();
2482 TCGv_i32 t1, t2;
2483 /* NIP cannot be restored if the memory exception comes from an helper */
2484 gen_update_nip(ctx, ctx->nip - 4);
2485 tcg_gen_andi_tl(t0, EA, mask);
2486 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2487 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2488 t2 = tcg_const_i32(0);
2489 gen_helper_raise_exception_err(cpu_env, t1, t2);
2490 tcg_temp_free_i32(t1);
2491 tcg_temp_free_i32(t2);
2492 gen_set_label(l1);
2493 tcg_temp_free(t0);
2494 }
2495
2496 /*** Integer load ***/
2497 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2498 {
2499 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2500 }
2501
2502 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2503 {
2504 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2505 }
2506
2507 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2508 {
2509 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2510 if (unlikely(ctx->le_mode)) {
2511 tcg_gen_bswap16_tl(arg1, arg1);
2512 }
2513 }
2514
2515 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2516 {
2517 if (unlikely(ctx->le_mode)) {
2518 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2519 tcg_gen_bswap16_tl(arg1, arg1);
2520 tcg_gen_ext16s_tl(arg1, arg1);
2521 } else {
2522 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2523 }
2524 }
2525
2526 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2527 {
2528 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2529 if (unlikely(ctx->le_mode)) {
2530 tcg_gen_bswap32_tl(arg1, arg1);
2531 }
2532 }
2533
2534 #if defined(TARGET_PPC64)
2535 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2536 {
2537 if (unlikely(ctx->le_mode)) {
2538 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2539 tcg_gen_bswap32_tl(arg1, arg1);
2540 tcg_gen_ext32s_tl(arg1, arg1);
2541 } else
2542 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2543 }
2544 #endif
2545
2546 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2547 {
2548 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2549 if (unlikely(ctx->le_mode)) {
2550 tcg_gen_bswap64_i64(arg1, arg1);
2551 }
2552 }
2553
2554 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2555 {
2556 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2557 }
2558
2559 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2560 {
2561 if (unlikely(ctx->le_mode)) {
2562 TCGv t0 = tcg_temp_new();
2563 tcg_gen_ext16u_tl(t0, arg1);
2564 tcg_gen_bswap16_tl(t0, t0);
2565 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2566 tcg_temp_free(t0);
2567 } else {
2568 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2569 }
2570 }
2571
2572 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2573 {
2574 if (unlikely(ctx->le_mode)) {
2575 TCGv t0 = tcg_temp_new();
2576 tcg_gen_ext32u_tl(t0, arg1);
2577 tcg_gen_bswap32_tl(t0, t0);
2578 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2579 tcg_temp_free(t0);
2580 } else {
2581 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2582 }
2583 }
2584
2585 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2586 {
2587 if (unlikely(ctx->le_mode)) {
2588 TCGv_i64 t0 = tcg_temp_new_i64();
2589 tcg_gen_bswap64_i64(t0, arg1);
2590 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2591 tcg_temp_free_i64(t0);
2592 } else
2593 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2594 }
2595
2596 #define GEN_LD(name, ldop, opc, type) \
2597 static void glue(gen_, name)(DisasContext *ctx) \
2598 { \
2599 TCGv EA; \
2600 gen_set_access_type(ctx, ACCESS_INT); \
2601 EA = tcg_temp_new(); \
2602 gen_addr_imm_index(ctx, EA, 0); \
2603 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2604 tcg_temp_free(EA); \
2605 }
2606
2607 #define GEN_LDU(name, ldop, opc, type) \
2608 static void glue(gen_, name##u)(DisasContext *ctx) \
2609 { \
2610 TCGv EA; \
2611 if (unlikely(rA(ctx->opcode) == 0 || \
2612 rA(ctx->opcode) == rD(ctx->opcode))) { \
2613 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2614 return; \
2615 } \
2616 gen_set_access_type(ctx, ACCESS_INT); \
2617 EA = tcg_temp_new(); \
2618 if (type == PPC_64B) \
2619 gen_addr_imm_index(ctx, EA, 0x03); \
2620 else \
2621 gen_addr_imm_index(ctx, EA, 0); \
2622 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2623 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2624 tcg_temp_free(EA); \
2625 }
2626
2627 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2628 static void glue(gen_, name##ux)(DisasContext *ctx) \
2629 { \
2630 TCGv EA; \
2631 if (unlikely(rA(ctx->opcode) == 0 || \
2632 rA(ctx->opcode) == rD(ctx->opcode))) { \
2633 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2634 return; \
2635 } \
2636 gen_set_access_type(ctx, ACCESS_INT); \
2637 EA = tcg_temp_new(); \
2638 gen_addr_reg_index(ctx, EA); \
2639 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2640 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2641 tcg_temp_free(EA); \
2642 }
2643
2644 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2645 static void glue(gen_, name##x)(DisasContext *ctx) \
2646 { \
2647 TCGv EA; \
2648 gen_set_access_type(ctx, ACCESS_INT); \
2649 EA = tcg_temp_new(); \
2650 gen_addr_reg_index(ctx, EA); \
2651 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2652 tcg_temp_free(EA); \
2653 }
2654 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2655 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2656
2657 #define GEN_LDS(name, ldop, op, type) \
2658 GEN_LD(name, ldop, op | 0x20, type); \
2659 GEN_LDU(name, ldop, op | 0x21, type); \
2660 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2661 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2662
2663 /* lbz lbzu lbzux lbzx */
2664 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2665 /* lha lhau lhaux lhax */
2666 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2667 /* lhz lhzu lhzux lhzx */
2668 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2669 /* lwz lwzu lwzux lwzx */
2670 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2671 #if defined(TARGET_PPC64)
2672 /* lwaux */
2673 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2674 /* lwax */
2675 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2676 /* ldux */
2677 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2678 /* ldx */
2679 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2680
2681 static void gen_ld(DisasContext *ctx)
2682 {
2683 TCGv EA;
2684 if (Rc(ctx->opcode)) {
2685 if (unlikely(rA(ctx->opcode) == 0 ||
2686 rA(ctx->opcode) == rD(ctx->opcode))) {
2687 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2688 return;
2689 }
2690 }
2691 gen_set_access_type(ctx, ACCESS_INT);
2692 EA = tcg_temp_new();
2693 gen_addr_imm_index(ctx, EA, 0x03);
2694 if (ctx->opcode & 0x02) {
2695 /* lwa (lwau is undefined) */
2696 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2697 } else {
2698 /* ld - ldu */
2699 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2700 }
2701 if (Rc(ctx->opcode))
2702 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2703 tcg_temp_free(EA);
2704 }
2705
2706 /* lq */
2707 static void gen_lq(DisasContext *ctx)
2708 {
2709 #if defined(CONFIG_USER_ONLY)
2710 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2711 #else
2712 int ra, rd;
2713 TCGv EA;
2714
2715 /* Restore CPU state */
2716 if (unlikely(ctx->mem_idx == 0)) {
2717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2718 return;
2719 }
2720 ra = rA(ctx->opcode);
2721 rd = rD(ctx->opcode);
2722 if (unlikely((rd & 1) || rd == ra)) {
2723 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2724 return;
2725 }
2726 if (unlikely(ctx->le_mode)) {
2727 /* Little-endian mode is not handled */
2728 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2729 return;
2730 }
2731 gen_set_access_type(ctx, ACCESS_INT);
2732 EA = tcg_temp_new();
2733 gen_addr_imm_index(ctx, EA, 0x0F);
2734 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2735 gen_addr_add(ctx, EA, EA, 8);
2736 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2737 tcg_temp_free(EA);
2738 #endif
2739 }
2740 #endif
2741
2742 /*** Integer store ***/
2743 #define GEN_ST(name, stop, opc, type) \
2744 static void glue(gen_, name)(DisasContext *ctx) \
2745 { \
2746 TCGv EA; \
2747 gen_set_access_type(ctx, ACCESS_INT); \
2748 EA = tcg_temp_new(); \
2749 gen_addr_imm_index(ctx, EA, 0); \
2750 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2751 tcg_temp_free(EA); \
2752 }
2753
2754 #define GEN_STU(name, stop, opc, type) \
2755 static void glue(gen_, stop##u)(DisasContext *ctx) \
2756 { \
2757 TCGv EA; \
2758 if (unlikely(rA(ctx->opcode) == 0)) { \
2759 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2760 return; \
2761 } \
2762 gen_set_access_type(ctx, ACCESS_INT); \
2763 EA = tcg_temp_new(); \
2764 if (type == PPC_64B) \
2765 gen_addr_imm_index(ctx, EA, 0x03); \
2766 else \
2767 gen_addr_imm_index(ctx, EA, 0); \
2768 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2770 tcg_temp_free(EA); \
2771 }
2772
2773 #define GEN_STUX(name, stop, opc2, opc3, type) \
2774 static void glue(gen_, name##ux)(DisasContext *ctx) \
2775 { \
2776 TCGv EA; \
2777 if (unlikely(rA(ctx->opcode) == 0)) { \
2778 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2779 return; \
2780 } \
2781 gen_set_access_type(ctx, ACCESS_INT); \
2782 EA = tcg_temp_new(); \
2783 gen_addr_reg_index(ctx, EA); \
2784 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2785 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2786 tcg_temp_free(EA); \
2787 }
2788
2789 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2790 static void glue(gen_, name##x)(DisasContext *ctx) \
2791 { \
2792 TCGv EA; \
2793 gen_set_access_type(ctx, ACCESS_INT); \
2794 EA = tcg_temp_new(); \
2795 gen_addr_reg_index(ctx, EA); \
2796 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2797 tcg_temp_free(EA); \
2798 }
2799 #define GEN_STX(name, stop, opc2, opc3, type) \
2800 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2801
2802 #define GEN_STS(name, stop, op, type) \
2803 GEN_ST(name, stop, op | 0x20, type); \
2804 GEN_STU(name, stop, op | 0x21, type); \
2805 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2806 GEN_STX(name, stop, 0x17, op | 0x00, type)
2807
2808 /* stb stbu stbux stbx */
2809 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2810 /* sth sthu sthux sthx */
2811 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2812 /* stw stwu stwux stwx */
2813 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2814 #if defined(TARGET_PPC64)
2815 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2816 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2817
2818 static void gen_std(DisasContext *ctx)
2819 {
2820 int rs;
2821 TCGv EA;
2822
2823 rs = rS(ctx->opcode);
2824 if ((ctx->opcode & 0x3) == 0x2) {
2825 #if defined(CONFIG_USER_ONLY)
2826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2827 #else
2828 /* stq */
2829 if (unlikely(ctx->mem_idx == 0)) {
2830 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2831 return;
2832 }
2833 if (unlikely(rs & 1)) {
2834 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2835 return;
2836 }
2837 if (unlikely(ctx->le_mode)) {
2838 /* Little-endian mode is not handled */
2839 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2840 return;
2841 }
2842 gen_set_access_type(ctx, ACCESS_INT);
2843 EA = tcg_temp_new();
2844 gen_addr_imm_index(ctx, EA, 0x03);
2845 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2846 gen_addr_add(ctx, EA, EA, 8);
2847 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2848 tcg_temp_free(EA);
2849 #endif
2850 } else {
2851 /* std / stdu */
2852 if (Rc(ctx->opcode)) {
2853 if (unlikely(rA(ctx->opcode) == 0)) {
2854 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2855 return;
2856 }
2857 }
2858 gen_set_access_type(ctx, ACCESS_INT);
2859 EA = tcg_temp_new();
2860 gen_addr_imm_index(ctx, EA, 0x03);
2861 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2862 if (Rc(ctx->opcode))
2863 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2864 tcg_temp_free(EA);
2865 }
2866 }
2867 #endif
2868 /*** Integer load and store with byte reverse ***/
2869 /* lhbrx */
2870 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2871 {
2872 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2873 if (likely(!ctx->le_mode)) {
2874 tcg_gen_bswap16_tl(arg1, arg1);
2875 }
2876 }
2877 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2878
2879 /* lwbrx */
2880 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2881 {
2882 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2883 if (likely(!ctx->le_mode)) {
2884 tcg_gen_bswap32_tl(arg1, arg1);
2885 }
2886 }
2887 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2888
2889 #if defined(TARGET_PPC64)
2890 /* ldbrx */
2891 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2892 {
2893 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2894 if (likely(!ctx->le_mode)) {
2895 tcg_gen_bswap64_tl(arg1, arg1);
2896 }
2897 }
2898 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2899 #endif /* TARGET_PPC64 */
2900
2901 /* sthbrx */
2902 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2903 {
2904 if (likely(!ctx->le_mode)) {
2905 TCGv t0 = tcg_temp_new();
2906 tcg_gen_ext16u_tl(t0, arg1);
2907 tcg_gen_bswap16_tl(t0, t0);
2908 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2909 tcg_temp_free(t0);
2910 } else {
2911 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2912 }
2913 }
2914 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2915
2916 /* stwbrx */
2917 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2918 {
2919 if (likely(!ctx->le_mode)) {
2920 TCGv t0 = tcg_temp_new();
2921 tcg_gen_ext32u_tl(t0, arg1);
2922 tcg_gen_bswap32_tl(t0, t0);
2923 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2924 tcg_temp_free(t0);
2925 } else {
2926 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2927 }
2928 }
2929 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2930
2931 #if defined(TARGET_PPC64)
2932 /* stdbrx */
2933 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2934 {
2935 if (likely(!ctx->le_mode)) {
2936 TCGv t0 = tcg_temp_new();
2937 tcg_gen_bswap64_tl(t0, arg1);
2938 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2939 tcg_temp_free(t0);
2940 } else {
2941 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2942 }
2943 }
2944 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2945 #endif /* TARGET_PPC64 */
2946
2947 /*** Integer load and store multiple ***/
2948
2949 /* lmw */
2950 static void gen_lmw(DisasContext *ctx)
2951 {
2952 TCGv t0;
2953 TCGv_i32 t1;
2954 gen_set_access_type(ctx, ACCESS_INT);
2955 /* NIP cannot be restored if the memory exception comes from an helper */
2956 gen_update_nip(ctx, ctx->nip - 4);
2957 t0 = tcg_temp_new();
2958 t1 = tcg_const_i32(rD(ctx->opcode));
2959 gen_addr_imm_index(ctx, t0, 0);
2960 gen_helper_lmw(cpu_env, t0, t1);
2961 tcg_temp_free(t0);
2962 tcg_temp_free_i32(t1);
2963 }
2964
2965 /* stmw */
2966 static void gen_stmw(DisasContext *ctx)
2967 {
2968 TCGv t0;
2969 TCGv_i32 t1;
2970 gen_set_access_type(ctx, ACCESS_INT);
2971 /* NIP cannot be restored if the memory exception comes from an helper */
2972 gen_update_nip(ctx, ctx->nip - 4);
2973 t0 = tcg_temp_new();
2974 t1 = tcg_const_i32(rS(ctx->opcode));
2975 gen_addr_imm_index(ctx, t0, 0);
2976 gen_helper_stmw(cpu_env, t0, t1);
2977 tcg_temp_free(t0);
2978 tcg_temp_free_i32(t1);
2979 }
2980
2981 /*** Integer load and store strings ***/
2982
2983 /* lswi */
2984 /* PowerPC32 specification says we must generate an exception if
2985 * rA is in the range of registers to be loaded.
2986 * In an other hand, IBM says this is valid, but rA won't be loaded.
2987 * For now, I'll follow the spec...
2988 */
2989 static void gen_lswi(DisasContext *ctx)
2990 {
2991 TCGv t0;
2992 TCGv_i32 t1, t2;
2993 int nb = NB(ctx->opcode);
2994 int start = rD(ctx->opcode);
2995 int ra = rA(ctx->opcode);
2996 int nr;
2997
2998 if (nb == 0)
2999 nb = 32;
3000 nr = nb / 4;
3001 if (unlikely(((start + nr) > 32 &&
3002 start <= ra && (start + nr - 32) > ra) ||
3003 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3004 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3005 return;
3006 }
3007 gen_set_access_type(ctx, ACCESS_INT);
3008 /* NIP cannot be restored if the memory exception comes from an helper */
3009 gen_update_nip(ctx, ctx->nip - 4);
3010 t0 = tcg_temp_new();
3011 gen_addr_register(ctx, t0);
3012 t1 = tcg_const_i32(nb);
3013 t2 = tcg_const_i32(start);
3014 gen_helper_lsw(cpu_env, t0, t1, t2);
3015 tcg_temp_free(t0);
3016 tcg_temp_free_i32(t1);
3017 tcg_temp_free_i32(t2);
3018 }
3019
3020 /* lswx */
3021 static void gen_lswx(DisasContext *ctx)
3022 {
3023 TCGv t0;
3024 TCGv_i32 t1, t2, t3;
3025 gen_set_access_type(ctx, ACCESS_INT);
3026 /* NIP cannot be restored if the memory exception comes from an helper */
3027 gen_update_nip(ctx, ctx->nip - 4);
3028 t0 = tcg_temp_new();
3029 gen_addr_reg_index(ctx, t0);
3030 t1 = tcg_const_i32(rD(ctx->opcode));
3031 t2 = tcg_const_i32(rA(ctx->opcode));
3032 t3 = tcg_const_i32(rB(ctx->opcode));
3033 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3034 tcg_temp_free(t0);
3035 tcg_temp_free_i32(t1);
3036 tcg_temp_free_i32(t2);
3037 tcg_temp_free_i32(t3);
3038 }
3039
3040 /* stswi */
3041 static void gen_stswi(DisasContext *ctx)
3042 {
3043 TCGv t0;
3044 TCGv_i32 t1, t2;
3045 int nb = NB(ctx->opcode);
3046 gen_set_access_type(ctx, ACCESS_INT);
3047 /* NIP cannot be restored if the memory exception comes from an helper */
3048 gen_update_nip(ctx, ctx->nip - 4);
3049 t0 = tcg_temp_new();
3050 gen_addr_register(ctx, t0);
3051 if (nb == 0)
3052 nb = 32;
3053 t1 = tcg_const_i32(nb);
3054 t2 = tcg_const_i32(rS(ctx->opcode));
3055 gen_helper_stsw(cpu_env, t0, t1, t2);
3056 tcg_temp_free(t0);
3057 tcg_temp_free_i32(t1);
3058 tcg_temp_free_i32(t2);
3059 }
3060
3061 /* stswx */
3062 static void gen_stswx(DisasContext *ctx)
3063 {
3064 TCGv t0;
3065 TCGv_i32 t1, t2;
3066 gen_set_access_type(ctx, ACCESS_INT);
3067 /* NIP cannot be restored if the memory exception comes from an helper */
3068 gen_update_nip(ctx, ctx->nip - 4);
3069 t0 = tcg_temp_new();
3070 gen_addr_reg_index(ctx, t0);
3071 t1 = tcg_temp_new_i32();
3072 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3073 tcg_gen_andi_i32(t1, t1, 0x7F);
3074 t2 = tcg_const_i32(rS(ctx->opcode));
3075 gen_helper_stsw(cpu_env, t0, t1, t2);
3076 tcg_temp_free(t0);
3077 tcg_temp_free_i32(t1);
3078 tcg_temp_free_i32(t2);
3079 }
3080
3081 /*** Memory synchronisation ***/
3082 /* eieio */
3083 static void gen_eieio(DisasContext *ctx)
3084 {
3085 }
3086
3087 /* isync */
3088 static void gen_isync(DisasContext *ctx)
3089 {
3090 gen_stop_exception(ctx);
3091 }
3092
3093 /* lwarx */
3094 static void gen_lwarx(DisasContext *ctx)
3095 {
3096 TCGv t0;
3097 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3098 gen_set_access_type(ctx, ACCESS_RES);
3099 t0 = tcg_temp_local_new();
3100 gen_addr_reg_index(ctx, t0);
3101 gen_check_align(ctx, t0, 0x03);
3102 gen_qemu_ld32u(ctx, gpr, t0);
3103 tcg_gen_mov_tl(cpu_reserve, t0);
3104 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3105 tcg_temp_free(t0);
3106 }
3107
3108 #if defined(CONFIG_USER_ONLY)
3109 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3110 int reg, int size)
3111 {
3112 TCGv t0 = tcg_temp_new();
3113 uint32_t save_exception = ctx->exception;
3114
3115 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3116 tcg_gen_movi_tl(t0, (size << 5) | reg);
3117 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3118 tcg_temp_free(t0);
3119 gen_update_nip(ctx, ctx->nip-4);
3120 ctx->exception = POWERPC_EXCP_BRANCH;
3121 gen_exception(ctx, POWERPC_EXCP_STCX);
3122 ctx->exception = save_exception;
3123 }
3124 #endif
3125
3126 /* stwcx. */
3127 static void gen_stwcx_(DisasContext *ctx)
3128 {
3129 TCGv t0;
3130 gen_set_access_type(ctx, ACCESS_RES);
3131 t0 = tcg_temp_local_new();
3132 gen_addr_reg_index(ctx, t0);
3133 gen_check_align(ctx, t0, 0x03);
3134 #if defined(CONFIG_USER_ONLY)
3135 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3136 #else
3137 {
3138 int l1;
3139
3140 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3141 l1 = gen_new_label();
3142 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3143 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3144 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3145 gen_set_label(l1);
3146 tcg_gen_movi_tl(cpu_reserve, -1);
3147 }
3148 #endif
3149 tcg_temp_free(t0);
3150 }
3151
3152 #if defined(TARGET_PPC64)
3153 /* ldarx */
3154 static void gen_ldarx(DisasContext *ctx)
3155 {
3156 TCGv t0;
3157 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3158 gen_set_access_type(ctx, ACCESS_RES);
3159 t0 = tcg_temp_local_new();
3160 gen_addr_reg_index(ctx, t0);
3161 gen_check_align(ctx, t0, 0x07);
3162 gen_qemu_ld64(ctx, gpr, t0);
3163 tcg_gen_mov_tl(cpu_reserve, t0);
3164 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3165 tcg_temp_free(t0);
3166 }
3167
3168 /* stdcx. */
3169 static void gen_stdcx_(DisasContext *ctx)
3170 {
3171 TCGv t0;
3172 gen_set_access_type(ctx, ACCESS_RES);
3173 t0 = tcg_temp_local_new();
3174 gen_addr_reg_index(ctx, t0);
3175 gen_check_align(ctx, t0, 0x07);
3176 #if defined(CONFIG_USER_ONLY)
3177 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3178 #else
3179 {
3180 int l1;
3181 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3182 l1 = gen_new_label();
3183 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3184 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3185 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3186 gen_set_label(l1);
3187 tcg_gen_movi_tl(cpu_reserve, -1);
3188 }
3189 #endif
3190 tcg_temp_free(t0);
3191 }
3192 #endif /* defined(TARGET_PPC64) */
3193
3194 /* sync */
3195 static void gen_sync(DisasContext *ctx)
3196 {
3197 }
3198
3199 /* wait */
3200 static void gen_wait(DisasContext *ctx)
3201 {
3202 TCGv_i32 t0 = tcg_temp_new_i32();
3203 tcg_gen_st_i32(t0, cpu_env,
3204 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3205 tcg_temp_free_i32(t0);
3206 /* Stop translation, as the CPU is supposed to sleep from now */
3207 gen_exception_err(ctx, EXCP_HLT, 1);
3208 }
3209
3210 /*** Floating-point load ***/
3211 #define GEN_LDF(name, ldop, opc, type) \
3212 static void glue(gen_, name)(DisasContext *ctx) \
3213 { \
3214 TCGv EA; \
3215 if (unlikely(!ctx->fpu_enabled)) { \
3216 gen_exception(ctx, POWERPC_EXCP_FPU); \
3217 return; \
3218 } \
3219 gen_set_access_type(ctx, ACCESS_FLOAT); \
3220 EA = tcg_temp_new(); \
3221 gen_addr_imm_index(ctx, EA, 0); \
3222 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3223 tcg_temp_free(EA); \
3224 }
3225
3226 #define GEN_LDUF(name, ldop, opc, type) \
3227 static void glue(gen_, name##u)(DisasContext *ctx) \
3228 { \
3229 TCGv EA; \
3230 if (unlikely(!ctx->fpu_enabled)) { \
3231 gen_exception(ctx, POWERPC_EXCP_FPU); \
3232 return; \
3233 } \
3234 if (unlikely(rA(ctx->opcode) == 0)) { \
3235 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3236 return; \
3237 } \
3238 gen_set_access_type(ctx, ACCESS_FLOAT); \
3239 EA = tcg_temp_new(); \
3240 gen_addr_imm_index(ctx, EA, 0); \
3241 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3242 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3243 tcg_temp_free(EA); \
3244 }
3245
3246 #define GEN_LDUXF(name, ldop, opc, type) \
3247 static void glue(gen_, name##ux)(DisasContext *ctx) \
3248 { \
3249 TCGv EA; \
3250 if (unlikely(!ctx->fpu_enabled)) { \
3251 gen_exception(ctx, POWERPC_EXCP_FPU); \
3252 return; \
3253 } \
3254 if (unlikely(rA(ctx->opcode) == 0)) { \
3255 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3256 return; \
3257 } \
3258 gen_set_access_type(ctx, ACCESS_FLOAT); \
3259 EA = tcg_temp_new(); \
3260 gen_addr_reg_index(ctx, EA); \
3261 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3262 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3263 tcg_temp_free(EA); \
3264 }
3265
3266 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3267 static void glue(gen_, name##x)(DisasContext *ctx) \
3268 { \
3269 TCGv EA; \
3270 if (unlikely(!ctx->fpu_enabled)) { \
3271 gen_exception(ctx, POWERPC_EXCP_FPU); \
3272 return; \
3273 } \
3274 gen_set_access_type(ctx, ACCESS_FLOAT); \
3275 EA = tcg_temp_new(); \
3276 gen_addr_reg_index(ctx, EA); \
3277 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3278 tcg_temp_free(EA); \
3279 }
3280
3281 #define GEN_LDFS(name, ldop, op, type) \
3282 GEN_LDF(name, ldop, op | 0x20, type); \
3283 GEN_LDUF(name, ldop, op | 0x21, type); \
3284 GEN_LDUXF(name, ldop, op | 0x01, type); \
3285 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3286
3287 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3288 {
3289 TCGv t0 = tcg_temp_new();
3290 TCGv_i32 t1 = tcg_temp_new_i32();
3291 gen_qemu_ld32u(ctx, t0, arg2);
3292 tcg_gen_trunc_tl_i32(t1, t0);
3293 tcg_temp_free(t0);
3294 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3295 tcg_temp_free_i32(t1);
3296 }
3297
3298 /* lfd lfdu lfdux lfdx */
3299 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3300 /* lfs lfsu lfsux lfsx */
3301 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3302
3303 /* lfdp */
3304 static void gen_lfdp(DisasContext *ctx)
3305 {
3306 TCGv EA;
3307 if (unlikely(!ctx->fpu_enabled)) {
3308 gen_exception(ctx, POWERPC_EXCP_FPU);
3309 return;
3310 }
3311 gen_set_access_type(ctx, ACCESS_FLOAT);
3312 EA = tcg_temp_new();
3313 gen_addr_imm_index(ctx, EA, 0); \
3314 if (unlikely(ctx->le_mode)) {
3315 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3316 tcg_gen_addi_tl(EA, EA, 8);
3317 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3318 } else {
3319 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3320 tcg_gen_addi_tl(EA, EA, 8);
3321 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3322 }
3323 tcg_temp_free(EA);
3324 }
3325
3326 /* lfdpx */
3327 static void gen_lfdpx(DisasContext *ctx)
3328 {
3329 TCGv EA;
3330 if (unlikely(!ctx->fpu_enabled)) {
3331 gen_exception(ctx, POWERPC_EXCP_FPU);
3332 return;
3333 }
3334 gen_set_access_type(ctx, ACCESS_FLOAT);
3335 EA = tcg_temp_new();
3336 gen_addr_reg_index(ctx, EA);
3337 if (unlikely(ctx->le_mode)) {
3338 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3339 tcg_gen_addi_tl(EA, EA, 8);
3340 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3341 } else {
3342 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3343 tcg_gen_addi_tl(EA, EA, 8);
3344 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3345 }
3346 tcg_temp_free(EA);
3347 }
3348
3349 /* lfiwax */
3350 static void gen_lfiwax(DisasContext *ctx)
3351 {
3352 TCGv EA;
3353 TCGv t0;
3354 if (unlikely(!ctx->fpu_enabled)) {
3355 gen_exception(ctx, POWERPC_EXCP_FPU);
3356 return;
3357 }
3358 gen_set_access_type(ctx, ACCESS_FLOAT);
3359 EA = tcg_temp_new();
3360 t0 = tcg_temp_new();
3361 gen_addr_reg_index(ctx, EA);
3362 gen_qemu_ld32u(ctx, t0, EA);
3363 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3364 tcg_gen_ext32s_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
3365 tcg_temp_free(EA);
3366 tcg_temp_free(t0);
3367 }
3368
3369 /*** Floating-point store ***/
3370 #define GEN_STF(name, stop, opc, type) \
3371 static void glue(gen_, name)(DisasContext *ctx) \
3372 { \
3373 TCGv EA; \
3374 if (unlikely(!ctx->fpu_enabled)) { \
3375 gen_exception(ctx, POWERPC_EXCP_FPU); \
3376 return; \
3377 } \
3378 gen_set_access_type(ctx, ACCESS_FLOAT); \
3379 EA = tcg_temp_new(); \
3380 gen_addr_imm_index(ctx, EA, 0); \
3381 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3382 tcg_temp_free(EA); \
3383 }
3384
3385 #define GEN_STUF(name, stop, opc, type) \
3386 static void glue(gen_, name##u)(DisasContext *ctx) \
3387 { \
3388 TCGv EA; \
3389 if (unlikely(!ctx->fpu_enabled)) { \
3390 gen_exception(ctx, POWERPC_EXCP_FPU); \
3391 return; \
3392 } \
3393 if (unlikely(rA(ctx->opcode) == 0)) { \
3394 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3395 return; \
3396 } \
3397 gen_set_access_type(ctx, ACCESS_FLOAT); \
3398 EA = tcg_temp_new(); \
3399 gen_addr_imm_index(ctx, EA, 0); \
3400 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3401 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3402 tcg_temp_free(EA); \
3403 }
3404
3405 #define GEN_STUXF(name, stop, opc, type) \
3406 static void glue(gen_, name##ux)(DisasContext *ctx) \
3407 { \
3408 TCGv EA; \
3409 if (unlikely(!ctx->fpu_enabled)) { \
3410 gen_exception(ctx, POWERPC_EXCP_FPU); \
3411 return; \
3412 } \
3413 if (unlikely(rA(ctx->opcode) == 0)) { \
3414 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3415 return; \
3416 } \
3417 gen_set_access_type(ctx, ACCESS_FLOAT); \
3418 EA = tcg_temp_new(); \
3419 gen_addr_reg_index(ctx, EA); \
3420 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3421 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3422 tcg_temp_free(EA); \
3423 }
3424
3425 #define GEN_STXF(name, stop, opc2, opc3, type) \
3426 static void glue(gen_, name##x)(DisasContext *ctx) \
3427 { \
3428 TCGv EA; \
3429 if (unlikely(!ctx->fpu_enabled)) { \
3430 gen_exception(ctx, POWERPC_EXCP_FPU); \
3431 return; \
3432 } \
3433 gen_set_access_type(ctx, ACCESS_FLOAT); \
3434 EA = tcg_temp_new(); \
3435 gen_addr_reg_index(ctx, EA); \
3436 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3437 tcg_temp_free(EA); \
3438 }
3439
3440 #define GEN_STFS(name, stop, op, type) \
3441 GEN_STF(name, stop, op | 0x20, type); \
3442 GEN_STUF(name, stop, op | 0x21, type); \
3443 GEN_STUXF(name, stop, op | 0x01, type); \
3444 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3445
3446 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3447 {
3448 TCGv_i32 t0 = tcg_temp_new_i32();
3449 TCGv t1 = tcg_temp_new();
3450 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3451 tcg_gen_extu_i32_tl(t1, t0);
3452 tcg_temp_free_i32(t0);
3453 gen_qemu_st32(ctx, t1, arg2);
3454 tcg_temp_free(t1);
3455 }
3456
3457 /* stfd stfdu stfdux stfdx */
3458 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3459 /* stfs stfsu stfsux stfsx */
3460 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3461
3462 /* stfdp */
3463 static void gen_stfdp(DisasContext *ctx)
3464 {
3465 TCGv EA;
3466 if (unlikely(!ctx->fpu_enabled)) {
3467 gen_exception(ctx, POWERPC_EXCP_FPU);
3468 return;
3469 }
3470 gen_set_access_type(ctx, ACCESS_FLOAT);
3471 EA = tcg_temp_new();
3472 gen_addr_imm_index(ctx, EA, 0); \
3473 if (unlikely(ctx->le_mode)) {
3474 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3475 tcg_gen_addi_tl(EA, EA, 8);
3476 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3477 } else {
3478 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3479 tcg_gen_addi_tl(EA, EA, 8);
3480 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3481 }
3482 tcg_temp_free(EA);
3483 }
3484
3485 /* stfdpx */
3486 static void gen_stfdpx(DisasContext *ctx)
3487 {
3488 TCGv EA;
3489 if (unlikely(!ctx->fpu_enabled)) {
3490 gen_exception(ctx, POWERPC_EXCP_FPU);
3491 return;
3492 }
3493 gen_set_access_type(ctx, ACCESS_FLOAT);
3494 EA = tcg_temp_new();
3495 gen_addr_reg_index(ctx, EA);
3496 if (unlikely(ctx->le_mode)) {
3497 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3498 tcg_gen_addi_tl(EA, EA, 8);
3499 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3500 } else {
3501 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3502 tcg_gen_addi_tl(EA, EA, 8);
3503 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3504 }
3505 tcg_temp_free(EA);
3506 }
3507
3508 /* Optional: */
3509 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3510 {
3511 TCGv t0 = tcg_temp_new();
3512 tcg_gen_trunc_i64_tl(t0, arg1),
3513 gen_qemu_st32(ctx, t0, arg2);
3514 tcg_temp_free(t0);
3515 }
3516 /* stfiwx */
3517 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3518
3519 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3520 {
3521 #if defined(TARGET_PPC64)
3522 if (ctx->has_cfar)
3523 tcg_gen_movi_tl(cpu_cfar, nip);
3524 #endif
3525 }
3526
3527 /*** Branch ***/
3528 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3529 {
3530 TranslationBlock *tb;
3531 tb = ctx->tb;
3532 if (NARROW_MODE(ctx)) {
3533 dest = (uint32_t) dest;
3534 }
3535 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3536 likely(!ctx->singlestep_enabled)) {
3537 tcg_gen_goto_tb(n);
3538 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3539 tcg_gen_exit_tb((tcg_target_long)tb + n);
3540 } else {
3541 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3542 if (unlikely(ctx->singlestep_enabled)) {
3543 if ((ctx->singlestep_enabled &
3544 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3545 (ctx->exception == POWERPC_EXCP_BRANCH ||
3546 ctx->exception == POWERPC_EXCP_TRACE)) {
3547 target_ulong tmp = ctx->nip;
3548 ctx->nip = dest;
3549 gen_exception(ctx, POWERPC_EXCP_TRACE);
3550 ctx->nip = tmp;
3551 }
3552 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3553 gen_debug_exception(ctx);
3554 }
3555 }
3556 tcg_gen_exit_tb(0);
3557 }
3558 }
3559
3560 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3561 {
3562 if (NARROW_MODE(ctx)) {
3563 nip = (uint32_t)nip;
3564 }
3565 tcg_gen_movi_tl(cpu_lr, nip);
3566 }
3567
3568 /* b ba bl bla */
3569 static void gen_b(DisasContext *ctx)
3570 {
3571 target_ulong li, target;
3572
3573 ctx->exception = POWERPC_EXCP_BRANCH;
3574 /* sign extend LI */
3575 li = LI(ctx->opcode);
3576 li = (li ^ 0x02000000) - 0x02000000;
3577 if (likely(AA(ctx->opcode) == 0)) {
3578 target = ctx->nip + li - 4;
3579 } else {
3580 target = li;
3581 }
3582 if (LK(ctx->opcode)) {
3583 gen_setlr(ctx, ctx->nip);
3584 }
3585 gen_update_cfar(ctx, ctx->nip);
3586 gen_goto_tb(ctx, 0, target);
3587 }
3588
3589 #define BCOND_IM 0
3590 #define BCOND_LR 1
3591 #define BCOND_CTR 2
3592
3593 static inline void gen_bcond(DisasContext *ctx, int type)
3594 {
3595 uint32_t bo = BO(ctx->opcode);
3596 int l1;
3597 TCGv target;
3598
3599 ctx->exception = POWERPC_EXCP_BRANCH;
3600 if (type == BCOND_LR || type == BCOND_CTR) {
3601 target = tcg_temp_local_new();
3602 if (type == BCOND_CTR)
3603 tcg_gen_mov_tl(target, cpu_ctr);
3604 else
3605 tcg_gen_mov_tl(target, cpu_lr);
3606 } else {
3607 TCGV_UNUSED(target);
3608 }
3609 if (LK(ctx->opcode))
3610 gen_setlr(ctx, ctx->nip);
3611 l1 = gen_new_label();
3612 if ((bo & 0x4) == 0) {
3613 /* Decrement and test CTR */
3614 TCGv temp = tcg_temp_new();
3615 if (unlikely(type == BCOND_CTR)) {
3616 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3617 return;
3618 }
3619 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3620 if (NARROW_MODE(ctx)) {
3621 tcg_gen_ext32u_tl(temp, cpu_ctr);
3622 } else {
3623 tcg_gen_mov_tl(temp, cpu_ctr);
3624 }
3625 if (bo & 0x2) {
3626 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3627 } else {
3628 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3629 }
3630 tcg_temp_free(temp);
3631 }
3632 if ((bo & 0x10) == 0) {
3633 /* Test CR */
3634 uint32_t bi = BI(ctx->opcode);
3635 uint32_t mask = 1 << (3 - (bi & 0x03));
3636 TCGv_i32 temp = tcg_temp_new_i32();
3637
3638 if (bo & 0x8) {
3639 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3640 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3641 } else {
3642 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3643 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3644 }
3645 tcg_temp_free_i32(temp);
3646 }
3647 gen_update_cfar(ctx, ctx->nip);
3648 if (type == BCOND_IM) {
3649 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3650 if (likely(AA(ctx->opcode) == 0)) {
3651 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3652 } else {
3653 gen_goto_tb(ctx, 0, li);
3654 }
3655 gen_set_label(l1);
3656 gen_goto_tb(ctx, 1, ctx->nip);
3657 } else {
3658 if (NARROW_MODE(ctx)) {
3659 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3660 } else {
3661 tcg_gen_andi_tl(cpu_nip, target, ~3);
3662 }
3663 tcg_gen_exit_tb(0);
3664 gen_set_label(l1);
3665 gen_update_nip(ctx, ctx->nip);
3666 tcg_gen_exit_tb(0);
3667 }
3668 }
3669
3670 static void gen_bc(DisasContext *ctx)
3671 {
3672 gen_bcond(ctx, BCOND_IM);
3673 }
3674
3675 static void gen_bcctr(DisasContext *ctx)
3676 {
3677 gen_bcond(ctx, BCOND_CTR);
3678 }
3679
3680 static void gen_bclr(DisasContext *ctx)
3681 {
3682 gen_bcond(ctx, BCOND_LR);
3683 }
3684
3685 /*** Condition register logical ***/
3686 #define GEN_CRLOGIC(name, tcg_op, opc) \
3687 static void glue(gen_, name)(DisasContext *ctx) \
3688 { \
3689 uint8_t bitmask; \
3690 int sh; \
3691 TCGv_i32 t0, t1; \
3692 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3693 t0 = tcg_temp_new_i32(); \
3694 if (sh > 0) \
3695 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3696 else if (sh < 0) \
3697 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3698 else \
3699 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3700 t1 = tcg_temp_new_i32(); \
3701 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3702 if (sh > 0) \
3703 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3704 else if (sh < 0) \
3705 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3706 else \
3707 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3708 tcg_op(t0, t0, t1); \
3709 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3710 tcg_gen_andi_i32(t0, t0, bitmask); \
3711 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3712 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3713 tcg_temp_free_i32(t0); \
3714 tcg_temp_free_i32(t1); \
3715 }
3716
3717 /* crand */
3718 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3719 /* crandc */
3720 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3721 /* creqv */
3722 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3723 /* crnand */
3724 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3725 /* crnor */
3726 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3727 /* cror */
3728 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3729 /* crorc */
3730 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3731 /* crxor */
3732 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3733
3734 /* mcrf */
3735 static void gen_mcrf(DisasContext *ctx)
3736 {
3737 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3738 }
3739
3740 /*** System linkage ***/
3741
3742 /* rfi (mem_idx only) */
3743 static void gen_rfi(DisasContext *ctx)
3744 {
3745 #if defined(CONFIG_USER_ONLY)
3746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3747 #else
3748 /* Restore CPU state */
3749 if (unlikely(!ctx->mem_idx)) {
3750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3751 return;
3752 }
3753 gen_update_cfar(ctx, ctx->nip);
3754 gen_helper_rfi(cpu_env);
3755 gen_sync_exception(ctx);
3756 #endif
3757 }
3758
3759 #if defined(TARGET_PPC64)
3760 static void gen_rfid(DisasContext *ctx)
3761 {
3762 #if defined(CONFIG_USER_ONLY)
3763 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3764 #else
3765 /* Restore CPU state */
3766 if (unlikely(!ctx->mem_idx)) {
3767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3768 return;
3769 }
3770 gen_update_cfar(ctx, ctx->nip);
3771 gen_helper_rfid(cpu_env);
3772 gen_sync_exception(ctx);
3773 #endif
3774 }
3775
3776 static void gen_hrfid(DisasContext *ctx)
3777 {
3778 #if defined(CONFIG_USER_ONLY)
3779 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3780 #else
3781 /* Restore CPU state */
3782 if (unlikely(ctx->mem_idx <= 1)) {
3783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3784 return;
3785 }
3786 gen_helper_hrfid(cpu_env);
3787 gen_sync_exception(ctx);
3788 #endif
3789 }
3790 #endif
3791
3792 /* sc */
3793 #if defined(CONFIG_USER_ONLY)
3794 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3795 #else
3796 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3797 #endif
3798 static void gen_sc(DisasContext *ctx)
3799 {
3800 uint32_t lev;
3801
3802 lev = (ctx->opcode >> 5) & 0x7F;
3803 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3804 }
3805
3806 /*** Trap ***/
3807
3808 /* tw */
3809 static void gen_tw(DisasContext *ctx)
3810 {
3811 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3812 /* Update the nip since this might generate a trap exception */
3813 gen_update_nip(ctx, ctx->nip);
3814 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3815 t0);
3816 tcg_temp_free_i32(t0);
3817 }
3818
3819 /* twi */
3820 static void gen_twi(DisasContext *ctx)
3821 {
3822 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3823 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3824 /* Update the nip since this might generate a trap exception */
3825 gen_update_nip(ctx, ctx->nip);
3826 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3827 tcg_temp_free(t0);
3828 tcg_temp_free_i32(t1);
3829 }
3830
3831 #if defined(TARGET_PPC64)
3832 /* td */
3833 static void gen_td(DisasContext *ctx)
3834 {
3835 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3836 /* Update the nip since this might generate a trap exception */
3837 gen_update_nip(ctx, ctx->nip);
3838 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3839 t0);
3840 tcg_temp_free_i32(t0);
3841 }
3842
3843 /* tdi */
3844 static void gen_tdi(DisasContext *ctx)
3845 {
3846 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3847 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3848 /* Update the nip since this might generate a trap exception */
3849 gen_update_nip(ctx, ctx->nip);
3850 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3851 tcg_temp_free(t0);
3852 tcg_temp_free_i32(t1);
3853 }
3854 #endif
3855
3856 /*** Processor control ***/
3857
3858 static void gen_read_xer(TCGv dst)
3859 {
3860 TCGv t0 = tcg_temp_new();
3861 TCGv t1 = tcg_temp_new();
3862 TCGv t2 = tcg_temp_new();
3863 tcg_gen_mov_tl(dst, cpu_xer);
3864 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3865 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3866 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3867 tcg_gen_or_tl(t0, t0, t1);
3868 tcg_gen_or_tl(dst, dst, t2);
3869 tcg_gen_or_tl(dst, dst, t0);
3870 tcg_temp_free(t0);
3871 tcg_temp_free(t1);
3872 tcg_temp_free(t2);
3873 }
3874
3875 static void gen_write_xer(TCGv src)
3876 {
3877 tcg_gen_andi_tl(cpu_xer, src,
3878 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3879 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3880 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3881 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3882 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3883 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3884 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3885 }
3886
3887 /* mcrxr */
3888 static void gen_mcrxr(DisasContext *ctx)
3889 {
3890 TCGv_i32 t0 = tcg_temp_new_i32();
3891 TCGv_i32 t1 = tcg_temp_new_i32();
3892 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3893
3894 tcg_gen_trunc_tl_i32(t0, cpu_so);
3895 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3896 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3897 tcg_gen_shri_i32(t0, t0, 2);
3898 tcg_gen_shri_i32(t1, t1, 1);
3899 tcg_gen_or_i32(dst, dst, t0);
3900 tcg_gen_or_i32(dst, dst, t1);
3901 tcg_temp_free_i32(t0);
3902 tcg_temp_free_i32(t1);
3903
3904 tcg_gen_movi_tl(cpu_so, 0);
3905 tcg_gen_movi_tl(cpu_ov, 0);
3906 tcg_gen_movi_tl(cpu_ca, 0);
3907 }
3908
3909 /* mfcr mfocrf */
3910 static void gen_mfcr(DisasContext *ctx)
3911 {
3912 uint32_t crm, crn;
3913
3914 if (likely(ctx->opcode & 0x00100000)) {
3915 crm = CRM(ctx->opcode);
3916 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3917 crn = ctz32 (crm);
3918 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3919 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3920 cpu_gpr[rD(ctx->opcode)], crn * 4);
3921 }
3922 } else {
3923 TCGv_i32 t0 = tcg_temp_new_i32();
3924 tcg_gen_mov_i32(t0, cpu_crf[0]);
3925 tcg_gen_shli_i32(t0, t0, 4);
3926 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3927 tcg_gen_shli_i32(t0, t0, 4);
3928 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3929 tcg_gen_shli_i32(t0, t0, 4);
3930 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3931 tcg_gen_shli_i32(t0, t0, 4);
3932 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3933 tcg_gen_shli_i32(t0, t0, 4);
3934 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3935 tcg_gen_shli_i32(t0, t0, 4);
3936 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3937 tcg_gen_shli_i32(t0, t0, 4);
3938 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3939 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3940 tcg_temp_free_i32(t0);
3941 }
3942 }
3943
3944 /* mfmsr */
3945 static void gen_mfmsr(DisasContext *ctx)
3946 {
3947 #if defined(CONFIG_USER_ONLY)
3948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3949 #else
3950 if (unlikely(!ctx->mem_idx)) {
3951 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3952 return;
3953 }
3954 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3955 #endif
3956 }
3957
3958 static void spr_noaccess(void *opaque, int gprn, int sprn)
3959 {
3960 #if 0
3961 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3962 printf("ERROR: try to access SPR %d !\n", sprn);
3963 #endif
3964 }
3965 #define SPR_NOACCESS (&spr_noaccess)
3966
3967 /* mfspr */
3968 static inline void gen_op_mfspr(DisasContext *ctx)
3969 {
3970 void (*read_cb)(void *opaque, int gprn, int sprn);
3971 uint32_t sprn = SPR(ctx->opcode);
3972
3973 #if !defined(CONFIG_USER_ONLY)
3974 if (ctx->mem_idx == 2)
3975 read_cb = ctx->spr_cb[sprn].hea_read;
3976 else if (ctx->mem_idx)
3977 read_cb = ctx->spr_cb[sprn].oea_read;
3978 else
3979 #endif
3980 read_cb = ctx->spr_cb[sprn].uea_read;
3981 if (likely(read_cb != NULL)) {
3982 if (likely(read_cb != SPR_NOACCESS)) {
3983 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3984 } else {
3985 /* Privilege exception */
3986 /* This is a hack to avoid warnings when running Linux:
3987 * this OS breaks the PowerPC virtualisation model,
3988 * allowing userland application to read the PVR
3989 */
3990 if (sprn != SPR_PVR) {
3991 qemu_log("Trying to read privileged spr %d %03x at "
3992 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3993 printf("Trying to read privileged spr %d %03x at "
3994 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3995 }
3996 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3997 }
3998 } else {
3999 /* Not defined */
4000 qemu_log("Trying to read invalid spr %d %03x at "
4001 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4002 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
4003 sprn, sprn, ctx->nip);
4004 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4005 }
4006 }
4007
4008 static void gen_mfspr(DisasContext *ctx)
4009 {
4010 gen_op_mfspr(ctx);
4011 }
4012
4013 /* mftb */
4014 static void gen_mftb(DisasContext *ctx)
4015 {
4016 gen_op_mfspr(ctx);
4017 }
4018
4019 /* mtcrf mtocrf*/
4020 static void gen_mtcrf(DisasContext *ctx)
4021 {
4022 uint32_t crm, crn;
4023
4024 crm = CRM(ctx->opcode);
4025 if (likely((ctx->opcode & 0x00100000))) {
4026 if (crm && ((crm & (crm - 1)) == 0)) {
4027 TCGv_i32 temp = tcg_temp_new_i32();
4028 crn = ctz32 (crm);
4029 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4030 tcg_gen_shri_i32(temp, temp, crn * 4);
4031 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4032 tcg_temp_free_i32(temp);
4033 }
4034 } else {
4035 TCGv_i32 temp = tcg_temp_new_i32();
4036 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4037 for (crn = 0 ; crn < 8 ; crn++) {
4038 if (crm & (1 << crn)) {
4039 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4040 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4041 }
4042 }
4043 tcg_temp_free_i32(temp);
4044 }
4045 }
4046
4047 /* mtmsr */
4048 #if defined(TARGET_PPC64)
4049 static void gen_mtmsrd(DisasContext *ctx)
4050 {
4051 #if defined(CONFIG_USER_ONLY)
4052 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4053 #else
4054 if (unlikely(!ctx->mem_idx)) {
4055 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4056 return;
4057 }
4058 if (ctx->opcode & 0x00010000) {
4059 /* Special form that does not need any synchronisation */
4060 TCGv t0 = tcg_temp_new();
4061 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4062 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4063 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4064 tcg_temp_free(t0);
4065 } else {
4066 /* XXX: we need to update nip before the store
4067 * if we enter power saving mode, we will exit the loop
4068 * directly from ppc_store_msr
4069 */
4070 gen_update_nip(ctx, ctx->nip);
4071 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4072 /* Must stop the translation as machine state (may have) changed */
4073 /* Note that mtmsr is not always defined as context-synchronizing */
4074 gen_stop_exception(ctx);
4075 }
4076 #endif
4077 }
4078 #endif
4079
4080 static void gen_mtmsr(DisasContext *ctx)
4081 {
4082 #if defined(CONFIG_USER_ONLY)
4083 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4084 #else
4085 if (unlikely(!ctx->mem_idx)) {
4086 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4087 return;
4088 }
4089 if (ctx->opcode & 0x00010000) {
4090 /* Special form that does not need any synchronisation */
4091 TCGv t0 = tcg_temp_new();
4092 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4093 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4094 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4095 tcg_temp_free(t0);
4096 } else {
4097 TCGv msr = tcg_temp_new();
4098
4099 /* XXX: we need to update nip before the store
4100 * if we enter power saving mode, we will exit the loop
4101 * directly from ppc_store_msr
4102 */
4103 gen_update_nip(ctx, ctx->nip);
4104 #if defined(TARGET_PPC64)
4105 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4106 #else
4107 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4108 #endif
4109 gen_helper_store_msr(cpu_env, msr);
4110 /* Must stop the translation as machine state (may have) changed */
4111 /* Note that mtmsr is not always defined as context-synchronizing */
4112 gen_stop_exception(ctx);
4113 }
4114 #endif
4115 }
4116
4117 /* mtspr */
4118 static void gen_mtspr(DisasContext *ctx)
4119 {
4120 void (*write_cb)(void *opaque, int sprn, int gprn);
4121 uint32_t sprn = SPR(ctx->opcode);
4122
4123 #if !defined(CONFIG_USER_ONLY)
4124 if (ctx->mem_idx == 2)
4125 write_cb = ctx->spr_cb[sprn].hea_write;
4126 else if (ctx->mem_idx)
4127 write_cb = ctx->spr_cb[sprn].oea_write;
4128 else
4129 #endif
4130 write_cb = ctx->spr_cb[sprn].uea_write;
4131 if (likely(write_cb != NULL)) {
4132 if (likely(write_cb != SPR_NOACCESS)) {
4133 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4134 } else {
4135 /* Privilege exception */
4136 qemu_log("Trying to write privileged spr %d %03x at "
4137 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4138 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
4139 "\n", sprn, sprn, ctx->nip);
4140 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4141 }
4142 } else {
4143 /* Not defined */
4144 qemu_log("Trying to write invalid spr %d %03x at "
4145 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4146 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
4147 sprn, sprn, ctx->nip);
4148 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4149 }
4150 }
4151
4152 /*** Cache management ***/
4153
4154 /* dcbf */
4155 static void gen_dcbf(DisasContext *ctx)
4156 {
4157 /* XXX: specification says this is treated as a load by the MMU */
4158 TCGv t0;
4159 gen_set_access_type(ctx, ACCESS_CACHE);
4160 t0 = tcg_temp_new();
4161 gen_addr_reg_index(ctx, t0);
4162 gen_qemu_ld8u(ctx, t0, t0);
4163 tcg_temp_free(t0);
4164 }
4165
4166 /* dcbi (Supervisor only) */
4167 static void gen_dcbi(DisasContext *ctx)
4168 {
4169 #if defined(CONFIG_USER_ONLY)
4170 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4171 #else
4172 TCGv EA, val;
4173 if (unlikely(!ctx->mem_idx)) {
4174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4175 return;
4176 }
4177 EA = tcg_temp_new();
4178 gen_set_access_type(ctx, ACCESS_CACHE);
4179 gen_addr_reg_index(ctx, EA);
4180 val = tcg_temp_new();
4181 /* XXX: specification says this should be treated as a store by the MMU */
4182 gen_qemu_ld8u(ctx, val, EA);
4183 gen_qemu_st8(ctx, val, EA);
4184 tcg_temp_free(val);
4185 tcg_temp_free(EA);
4186 #endif
4187 }
4188
4189 /* dcdst */
4190 static void gen_dcbst(DisasContext *ctx)
4191 {
4192 /* XXX: specification say this is treated as a load by the MMU */
4193 TCGv t0;
4194 gen_set_access_type(ctx, ACCESS_CACHE);
4195 t0 = tcg_temp_new();
4196 gen_addr_reg_index(ctx, t0);
4197 gen_qemu_ld8u(ctx, t0, t0);
4198 tcg_temp_free(t0);
4199 }
4200
4201 /* dcbt */
4202 static void gen_dcbt(DisasContext *ctx)
4203 {
4204 /* interpreted as no-op */
4205 /* XXX: specification say this is treated as a load by the MMU
4206 * but does not generate any exception
4207 */
4208 }
4209
4210 /* dcbtst */
4211 static void gen_dcbtst(DisasContext *ctx)
4212 {
4213 /* interpreted as no-op */
4214 /* XXX: specification say this is treated as a load by the MMU
4215 * but does not generate any exception
4216 */
4217 }
4218
4219 /* dcbz */
4220 static void gen_dcbz(DisasContext *ctx)
4221 {
4222 TCGv tcgv_addr;
4223 TCGv_i32 tcgv_is_dcbzl;
4224 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4225
4226 gen_set_access_type(ctx, ACCESS_CACHE);
4227 /* NIP cannot be restored if the memory exception comes from an helper */
4228 gen_update_nip(ctx, ctx->nip - 4);
4229 tcgv_addr = tcg_temp_new();
4230 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4231
4232 gen_addr_reg_index(ctx, tcgv_addr);
4233 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4234
4235 tcg_temp_free(tcgv_addr);
4236 tcg_temp_free_i32(tcgv_is_dcbzl);
4237 }
4238
4239 /* dst / dstt */
4240 static void gen_dst(DisasContext *ctx)
4241 {
4242 if (rA(ctx->opcode) == 0) {
4243 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4244 } else {
4245 /* interpreted as no-op */
4246 }
4247 }
4248
4249 /* dstst /dststt */
4250 static void gen_dstst(DisasContext *ctx)
4251 {
4252 if (rA(ctx->opcode) == 0) {
4253 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4254 } else {
4255 /* interpreted as no-op */
4256 }
4257
4258 }
4259
4260 /* dss / dssall */
4261 static void gen_dss(DisasContext *ctx)
4262 {
4263 /* interpreted as no-op */
4264 }
4265
4266 /* icbi */
4267 static void gen_icbi(DisasContext *ctx)
4268 {
4269 TCGv t0;
4270 gen_set_access_type(ctx, ACCESS_CACHE);
4271 /* NIP cannot be restored if the memory exception comes from an helper */
4272 gen_update_nip(ctx, ctx->nip - 4);
4273 t0 = tcg_temp_new();
4274 gen_addr_reg_index(ctx, t0);
4275 gen_helper_icbi(cpu_env, t0);
4276 tcg_temp_free(t0);
4277 }
4278
4279 /* Optional: */
4280 /* dcba */
4281 static void gen_dcba(DisasContext *ctx)
4282 {
4283 /* interpreted as no-op */
4284 /* XXX: specification say this is treated as a store by the MMU
4285 * but does not generate any exception
4286 */
4287 }
4288
4289 /*** Segment register manipulation ***/
4290 /* Supervisor only: */
4291
4292 /* mfsr */
4293 static void gen_mfsr(DisasContext *ctx)
4294 {
4295 #if defined(CONFIG_USER_ONLY)
4296 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4297 #else
4298 TCGv t0;
4299 if (unlikely(!ctx->mem_idx)) {
4300 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4301 return;
4302 }
4303 t0 = tcg_const_tl(SR(ctx->opcode));
4304 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4305 tcg_temp_free(t0);
4306 #endif
4307 }
4308
4309 /* mfsrin */
4310 static void gen_mfsrin(DisasContext *ctx)
4311 {
4312 #if defined(CONFIG_USER_ONLY)
4313 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4314 #else
4315 TCGv t0;
4316 if (unlikely(!ctx->mem_idx)) {
4317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4318 return;
4319 }
4320 t0 = tcg_temp_new();
4321 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4322 tcg_gen_andi_tl(t0, t0, 0xF);
4323 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4324 tcg_temp_free(t0);
4325 #endif
4326 }
4327
4328 /* mtsr */
4329 static void gen_mtsr(DisasContext *ctx)
4330 {
4331 #if defined(CONFIG_USER_ONLY)
4332 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4333 #else
4334 TCGv t0;
4335 if (unlikely(!ctx->mem_idx)) {
4336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4337 return;
4338 }
4339 t0 = tcg_const_tl(SR(ctx->opcode));
4340 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4341 tcg_temp_free(t0);
4342 #endif
4343 }
4344
4345 /* mtsrin */
4346 static void gen_mtsrin(DisasContext *ctx)
4347 {
4348 #if defined(CONFIG_USER_ONLY)
4349 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4350 #else
4351 TCGv t0;
4352 if (unlikely(!ctx->mem_idx)) {
4353 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4354 return;
4355 }
4356 t0 = tcg_temp_new();
4357 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4358 tcg_gen_andi_tl(t0, t0, 0xF);
4359 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4360 tcg_temp_free(t0);
4361 #endif
4362 }
4363
4364 #if defined(TARGET_PPC64)
4365 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4366
4367 /* mfsr */
4368 static void gen_mfsr_64b(DisasContext *ctx)
4369 {
4370 #if defined(CONFIG_USER_ONLY)
4371 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4372 #else
4373 TCGv t0;
4374 if (unlikely(!ctx->mem_idx)) {
4375 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4376 return;
4377 }
4378 t0 = tcg_const_tl(SR(ctx->opcode));
4379 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4380 tcg_temp_free(t0);
4381 #endif
4382 }
4383
4384 /* mfsrin */
4385 static void gen_mfsrin_64b(DisasContext *ctx)
4386 {
4387 #if defined(CONFIG_USER_ONLY)
4388 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4389 #else
4390 TCGv t0;
4391 if (unlikely(!ctx->mem_idx)) {
4392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4393 return;
4394 }
4395 t0 = tcg_temp_new();
4396 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4397 tcg_gen_andi_tl(t0, t0, 0xF);
4398 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4399 tcg_temp_free(t0);
4400 #endif
4401 }
4402
4403 /* mtsr */
4404 static void gen_mtsr_64b(DisasContext *ctx)
4405 {
4406 #if defined(CONFIG_USER_ONLY)
4407 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4408 #else
4409 TCGv t0;
4410 if (unlikely(!ctx->mem_idx)) {
4411 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4412 return;
4413 }
4414 t0 = tcg_const_tl(SR(ctx->opcode));
4415 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4416 tcg_temp_free(t0);
4417 #endif
4418 }
4419
4420 /* mtsrin */
4421 static void gen_mtsrin_64b(DisasContext *ctx)
4422 {
4423 #if defined(CONFIG_USER_ONLY)
4424 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4425 #else
4426 TCGv t0;
4427 if (unlikely(!ctx->mem_idx)) {
4428 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4429 return;
4430 }
4431 t0 = tcg_temp_new();
4432 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4433 tcg_gen_andi_tl(t0, t0, 0xF);
4434 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4435 tcg_temp_free(t0);
4436 #endif
4437 }
4438
4439 /* slbmte */
4440 static void gen_slbmte(DisasContext *ctx)
4441 {
4442 #if defined(CONFIG_USER_ONLY)
4443 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4444 #else
4445 if (unlikely(!ctx->mem_idx)) {
4446 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4447 return;
4448 }
4449 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4450 cpu_gpr[rS(ctx->opcode)]);
4451 #endif
4452 }
4453
4454 static void gen_slbmfee(DisasContext *ctx)
4455 {
4456 #if defined(CONFIG_USER_ONLY)
4457 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4458 #else
4459 if (unlikely(!ctx->mem_idx)) {
4460 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4461 return;
4462 }
4463 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4464 cpu_gpr[rB(ctx->opcode)]);
4465 #endif
4466 }
4467
4468 static void gen_slbmfev(DisasContext *ctx)
4469 {
4470 #if defined(CONFIG_USER_ONLY)
4471 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4472 #else
4473 if (unlikely(!ctx->mem_idx)) {
4474 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4475 return;
4476 }
4477 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4478 cpu_gpr[rB(ctx->opcode)]);
4479 #endif
4480 }
4481 #endif /* defined(TARGET_PPC64) */
4482
4483 /*** Lookaside buffer management ***/
4484 /* Optional & mem_idx only: */
4485
4486 /* tlbia */
4487 static void gen_tlbia(DisasContext *ctx)
4488 {
4489 #if defined(CONFIG_USER_ONLY)
4490 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4491 #else
4492 if (unlikely(!ctx->mem_idx)) {
4493 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4494 return;
4495 }
4496 gen_helper_tlbia(cpu_env);
4497 #endif
4498 }
4499
4500 /* tlbiel */
4501 static void gen_tlbiel(DisasContext *ctx)
4502 {
4503 #if defined(CONFIG_USER_ONLY)
4504 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4505 #else
4506 if (unlikely(!ctx->mem_idx)) {
4507 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4508 return;
4509 }
4510 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4511 #endif
4512 }
4513
4514 /* tlbie */
4515 static void gen_tlbie(DisasContext *ctx)
4516 {
4517 #if defined(CONFIG_USER_ONLY)
4518 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4519 #else
4520 if (unlikely(!ctx->mem_idx)) {
4521 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4522 return;
4523 }
4524 if (NARROW_MODE(ctx)) {
4525 TCGv t0 = tcg_temp_new();
4526 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4527 gen_helper_tlbie(cpu_env, t0);
4528 tcg_temp_free(t0);
4529 } else {
4530 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4531 }
4532 #endif
4533 }
4534
4535 /* tlbsync */
4536 static void gen_tlbsync(DisasContext *ctx)
4537 {
4538 #if defined(CONFIG_USER_ONLY)
4539 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4540 #else
4541 if (unlikely(!ctx->mem_idx)) {
4542 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4543 return;
4544 }
4545 /* This has no effect: it should ensure that all previous
4546 * tlbie have completed
4547 */
4548 gen_stop_exception(ctx);
4549 #endif
4550 }
4551
4552 #if defined(TARGET_PPC64)
4553 /* slbia */
4554 static void gen_slbia(DisasContext *ctx)
4555 {
4556 #if defined(CONFIG_USER_ONLY)
4557 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4558 #else
4559 if (unlikely(!ctx->mem_idx)) {
4560 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4561 return;
4562 }
4563 gen_helper_slbia(cpu_env);
4564 #endif
4565 }
4566
4567 /* slbie */
4568 static void gen_slbie(DisasContext *ctx)
4569 {
4570 #if defined(CONFIG_USER_ONLY)
4571 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4572 #else
4573 if (unlikely(!ctx->mem_idx)) {
4574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4575 return;
4576 }
4577 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4578 #endif
4579 }
4580 #endif
4581
4582 /*** External control ***/
4583 /* Optional: */
4584
4585 /* eciwx */
4586 static void gen_eciwx(DisasContext *ctx)
4587 {
4588 TCGv t0;
4589 /* Should check EAR[E] ! */
4590 gen_set_access_type(ctx, ACCESS_EXT);
4591 t0 = tcg_temp_new();
4592 gen_addr_reg_index(ctx, t0);
4593 gen_check_align(ctx, t0, 0x03);
4594 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4595 tcg_temp_free(t0);
4596 }
4597
4598 /* ecowx */
4599 static void gen_ecowx(DisasContext *ctx)
4600 {
4601 TCGv t0;
4602 /* Should check EAR[E] ! */
4603 gen_set_access_type(ctx, ACCESS_EXT);
4604 t0 = tcg_temp_new();
4605 gen_addr_reg_index(ctx, t0);
4606 gen_check_align(ctx, t0, 0x03);
4607 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4608 tcg_temp_free(t0);
4609 }
4610
4611 /* PowerPC 601 specific instructions */
4612
4613 /* abs - abs. */
4614 static void gen_abs(DisasContext *ctx)
4615 {
4616 int l1 = gen_new_label();
4617 int l2 = gen_new_label();
4618 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4619 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4620 tcg_gen_br(l2);
4621 gen_set_label(l1);
4622 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4623 gen_set_label(l2);
4624 if (unlikely(Rc(ctx->opcode) != 0))
4625 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4626 }
4627
4628 /* abso - abso. */
4629 static void gen_abso(DisasContext *ctx)
4630 {
4631 int l1 = gen_new_label();
4632 int l2 = gen_new_label();
4633 int l3 = gen_new_label();
4634 /* Start with XER OV disabled, the most likely case */
4635 tcg_gen_movi_tl(cpu_ov, 0);
4636 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4637 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4638 tcg_gen_movi_tl(cpu_ov, 1);
4639 tcg_gen_movi_tl(cpu_so, 1);
4640 tcg_gen_br(l2);
4641 gen_set_label(l1);
4642 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4643 tcg_gen_br(l3);
4644 gen_set_label(l2);
4645 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4646 gen_set_label(l3);
4647 if (unlikely(Rc(ctx->opcode) != 0))
4648 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4649 }
4650
4651 /* clcs */
4652 static void gen_clcs(DisasContext *ctx)
4653 {
4654 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4655 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4656 tcg_temp_free_i32(t0);
4657 /* Rc=1 sets CR0 to an undefined state */
4658 }
4659
4660 /* div - div. */
4661 static void gen_div(DisasContext *ctx)
4662 {
4663 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4664 cpu_gpr[rB(ctx->opcode)]);
4665 if (unlikely(Rc(ctx->opcode) != 0))
4666 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4667 }
4668
4669 /* divo - divo. */
4670 static void gen_divo(DisasContext *ctx)
4671 {
4672 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4673 cpu_gpr[rB(ctx->opcode)]);
4674 if (unlikely(Rc(ctx->opcode) != 0))
4675 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4676 }
4677
4678 /* divs - divs. */
4679 static void gen_divs(DisasContext *ctx)
4680 {
4681 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4682 cpu_gpr[rB(ctx->opcode)]);
4683 if (unlikely(Rc(ctx->opcode) != 0))
4684 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4685 }
4686
4687 /* divso - divso. */
4688 static void gen_divso(DisasContext *ctx)
4689 {
4690 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4691 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4692 if (unlikely(Rc(ctx->opcode) != 0))
4693 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4694 }
4695
4696 /* doz - doz. */
4697 static void gen_doz(DisasContext *ctx)
4698 {
4699 int l1 = gen_new_label();
4700 int l2 = gen_new_label();
4701 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4702 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4703 tcg_gen_br(l2);
4704 gen_set_label(l1);
4705 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4706 gen_set_label(l2);
4707 if (unlikely(Rc(ctx->opcode) != 0))
4708 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4709 }
4710
4711 /* dozo - dozo. */
4712 static void gen_dozo(DisasContext *ctx)
4713 {
4714 int l1 = gen_new_label();
4715 int l2 = gen_new_label();
4716 TCGv t0 = tcg_temp_new();
4717 TCGv t1 = tcg_temp_new();
4718 TCGv t2 = tcg_temp_new();
4719 /* Start with XER OV disabled, the most likely case */
4720 tcg_gen_movi_tl(cpu_ov, 0);
4721 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4722 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4723 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4724 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4725 tcg_gen_andc_tl(t1, t1, t2);
4726 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4727 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4728 tcg_gen_movi_tl(cpu_ov, 1);
4729 tcg_gen_movi_tl(cpu_so, 1);
4730 tcg_gen_br(l2);
4731 gen_set_label(l1);
4732 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4733 gen_set_label(l2);
4734 tcg_temp_free(t0);
4735 tcg_temp_free(t1);
4736 tcg_temp_free(t2);
4737 if (unlikely(Rc(ctx->opcode) != 0))
4738 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4739 }
4740
4741 /* dozi */
4742 static void gen_dozi(DisasContext *ctx)
4743 {
4744 target_long simm = SIMM(ctx->opcode);
4745 int l1 = gen_new_label();
4746 int l2 = gen_new_label();
4747 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4748 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4749 tcg_gen_br(l2);
4750 gen_set_label(l1);
4751 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4752 gen_set_label(l2);
4753 if (unlikely(Rc(ctx->opcode) != 0))
4754 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4755 }
4756
4757 /* lscbx - lscbx. */
4758 static void gen_lscbx(DisasContext *ctx)
4759 {
4760 TCGv t0 = tcg_temp_new();
4761 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4762 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4763 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4764
4765 gen_addr_reg_index(ctx, t0);
4766 /* NIP cannot be restored if the memory exception comes from an helper */
4767 gen_update_nip(ctx, ctx->nip - 4);
4768 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4769 tcg_temp_free_i32(t1);
4770 tcg_temp_free_i32(t2);
4771 tcg_temp_free_i32(t3);
4772 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4773 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4774 if (unlikely(Rc(ctx->opcode) != 0))
4775 gen_set_Rc0(ctx, t0);
4776 tcg_temp_free(t0);
4777 }
4778
4779 /* maskg - maskg. */
4780 static void gen_maskg(DisasContext *ctx)
4781 {
4782 int l1 = gen_new_label();
4783 TCGv t0 = tcg_temp_new();
4784 TCGv t1 = tcg_temp_new();
4785 TCGv t2 = tcg_temp_new();
4786 TCGv t3 = tcg_temp_new();
4787 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4788 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4789 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4790 tcg_gen_addi_tl(t2, t0, 1);
4791 tcg_gen_shr_tl(t2, t3, t2);
4792 tcg_gen_shr_tl(t3, t3, t1);
4793 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4794 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4795 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4796 gen_set_label(l1);
4797 tcg_temp_free(t0);
4798 tcg_temp_free(t1);
4799 tcg_temp_free(t2);
4800 tcg_temp_free(t3);
4801 if (unlikely(Rc(ctx->opcode) != 0))
4802 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4803 }
4804
4805 /* maskir - maskir. */
4806 static void gen_maskir(DisasContext *ctx)
4807 {
4808 TCGv t0 = tcg_temp_new();
4809 TCGv t1 = tcg_temp_new();
4810 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4811 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4812 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4813 tcg_temp_free(t0);
4814 tcg_temp_free(t1);
4815 if (unlikely(Rc(ctx->opcode) != 0))
4816 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4817 }
4818
4819 /* mul - mul. */
4820 static void gen_mul(DisasContext *ctx)
4821 {
4822 TCGv_i64 t0 = tcg_temp_new_i64();
4823 TCGv_i64 t1 = tcg_temp_new_i64();
4824 TCGv t2 = tcg_temp_new();
4825 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4826 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4827 tcg_gen_mul_i64(t0, t0, t1);
4828 tcg_gen_trunc_i64_tl(t2, t0);
4829 gen_store_spr(SPR_MQ, t2);
4830 tcg_gen_shri_i64(t1, t0, 32);
4831 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4832 tcg_temp_free_i64(t0);
4833 tcg_temp_free_i64(t1);
4834 tcg_temp_free(t2);
4835 if (unlikely(Rc(ctx->opcode) != 0))
4836 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4837 }
4838
4839 /* mulo - mulo. */
4840 static void gen_mulo(DisasContext *ctx)
4841 {
4842 int l1 = gen_new_label();
4843 TCGv_i64 t0 = tcg_temp_new_i64();
4844 TCGv_i64 t1 = tcg_temp_new_i64();
4845 TCGv t2 = tcg_temp_new();
4846 /* Start with XER OV disabled, the most likely case */
4847 tcg_gen_movi_tl(cpu_ov, 0);
4848 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4849 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4850 tcg_gen_mul_i64(t0, t0, t1);
4851 tcg_gen_trunc_i64_tl(t2, t0);
4852 gen_store_spr(SPR_MQ, t2);
4853 tcg_gen_shri_i64(t1, t0, 32);
4854 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4855 tcg_gen_ext32s_i64(t1, t0);
4856 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4857 tcg_gen_movi_tl(cpu_ov, 1);
4858 tcg_gen_movi_tl(cpu_so, 1);
4859 gen_set_label(l1);
4860 tcg_temp_free_i64(t0);
4861 tcg_temp_free_i64(t1);
4862 tcg_temp_free(t2);
4863 if (unlikely(Rc(ctx->opcode) != 0))
4864 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4865 }
4866
4867 /* nabs - nabs. */
4868 static void gen_nabs(DisasContext *ctx)
4869 {
4870 int l1 = gen_new_label();
4871 int l2 = gen_new_label();
4872 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4873 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4874 tcg_gen_br(l2);
4875 gen_set_label(l1);
4876 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4877 gen_set_label(l2);
4878 if (unlikely(Rc(ctx->opcode) != 0))
4879 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4880 }
4881
4882 /* nabso - nabso. */
4883 static void gen_nabso(DisasContext *ctx)
4884 {
4885 int l1 = gen_new_label();
4886 int l2 = gen_new_label();
4887 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4888 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4889 tcg_gen_br(l2);
4890 gen_set_label(l1);
4891 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4892 gen_set_label(l2);
4893 /* nabs never overflows */
4894 tcg_gen_movi_tl(cpu_ov, 0);
4895 if (unlikely(Rc(ctx->opcode) != 0))
4896 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4897 }
4898
4899 /* rlmi - rlmi. */
4900 static void gen_rlmi(DisasContext *ctx)
4901 {
4902 uint32_t mb = MB(ctx->opcode);
4903 uint32_t me = ME(ctx->opcode);
4904 TCGv t0 = tcg_temp_new();
4905 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4906 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4907 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4908 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4909 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4910 tcg_temp_free(t0);
4911 if (unlikely(Rc(ctx->opcode) != 0))
4912 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4913 }
4914
4915 /* rrib - rrib. */
4916 static void gen_rrib(DisasContext *ctx)
4917 {
4918 TCGv t0 = tcg_temp_new();
4919 TCGv t1 = tcg_temp_new();
4920 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4921 tcg_gen_movi_tl(t1, 0x80000000);
4922 tcg_gen_shr_tl(t1, t1, t0);
4923 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4924 tcg_gen_and_tl(t0, t0, t1);
4925 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4926 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4927 tcg_temp_free(t0);
4928 tcg_temp_free(t1);
4929 if (unlikely(Rc(ctx->opcode) != 0))
4930 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4931 }
4932
4933 /* sle - sle. */
4934 static void gen_sle(DisasContext *ctx)
4935 {
4936 TCGv t0 = tcg_temp_new();
4937 TCGv t1 = tcg_temp_new();
4938 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4939 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4940 tcg_gen_subfi_tl(t1, 32, t1);
4941 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4942 tcg_gen_or_tl(t1, t0, t1);
4943 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4944 gen_store_spr(SPR_MQ, t1);
4945 tcg_temp_free(t0);
4946 tcg_temp_free(t1);
4947 if (unlikely(Rc(ctx->opcode) != 0))
4948 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4949 }
4950
4951 /* sleq - sleq. */
4952 static void gen_sleq(DisasContext *ctx)
4953 {
4954 TCGv t0 = tcg_temp_new();
4955 TCGv t1 = tcg_temp_new();
4956 TCGv t2 = tcg_temp_new();
4957 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4958 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4959 tcg_gen_shl_tl(t2, t2, t0);
4960 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4961 gen_load_spr(t1, SPR_MQ);
4962 gen_store_spr(SPR_MQ, t0);
4963 tcg_gen_and_tl(t0, t0, t2);
4964 tcg_gen_andc_tl(t1, t1, t2);
4965 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4966 tcg_temp_free(t0);
4967 tcg_temp_free(t1);
4968 tcg_temp_free(t2);
4969 if (unlikely(Rc(ctx->opcode) != 0))
4970 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4971 }
4972
4973 /* sliq - sliq. */
4974 static void gen_sliq(DisasContext *ctx)
4975 {
4976 int sh = SH(ctx->opcode);
4977 TCGv t0 = tcg_temp_new();
4978 TCGv t1 = tcg_temp_new();
4979 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4980 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4981 tcg_gen_or_tl(t1, t0, t1);
4982 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4983 gen_store_spr(SPR_MQ, t1);
4984 tcg_temp_free(t0);
4985 tcg_temp_free(t1);
4986 if (unlikely(Rc(ctx->opcode) != 0))
4987 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4988 }
4989
4990 /* slliq - slliq. */
4991 static void gen_slliq(DisasContext *ctx)
4992 {
4993 int sh = SH(ctx->opcode);
4994 TCGv t0 = tcg_temp_new();
4995 TCGv t1 = tcg_temp_new();
4996 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4997 gen_load_spr(t1, SPR_MQ);
4998 gen_store_spr(SPR_MQ, t0);
4999 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5000 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5001 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5002 tcg_temp_free(t0);
5003 tcg_temp_free(t1);
5004 if (unlikely(Rc(ctx->opcode) != 0))
5005 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5006 }
5007
5008 /* sllq - sllq. */
5009 static void gen_sllq(DisasContext *ctx)
5010 {
5011 int l1 = gen_new_label();
5012 int l2 = gen_new_label();
5013 TCGv t0 = tcg_temp_local_new();
5014 TCGv t1 = tcg_temp_local_new();
5015 TCGv t2 = tcg_temp_local_new();
5016 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5017 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5018 tcg_gen_shl_tl(t1, t1, t2);
5019 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5020 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5021 gen_load_spr(t0, SPR_MQ);
5022 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5023 tcg_gen_br(l2);
5024 gen_set_label(l1);
5025 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5026 gen_load_spr(t2, SPR_MQ);
5027 tcg_gen_andc_tl(t1, t2, t1);
5028 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5029 gen_set_label(l2);
5030 tcg_temp_free(t0);
5031 tcg_temp_free(t1);
5032 tcg_temp_free(t2);
5033 if (unlikely(Rc(ctx->opcode) != 0))
5034 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5035 }
5036
5037 /* slq - slq. */
5038 static void gen_slq(DisasContext *ctx)
5039 {
5040 int l1 = gen_new_label();
5041 TCGv t0 = tcg_temp_new();
5042 TCGv t1 = tcg_temp_new();
5043 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5044 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5045 tcg_gen_subfi_tl(t1, 32, t1);
5046 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5047 tcg_gen_or_tl(t1, t0, t1);
5048 gen_store_spr(SPR_MQ, t1);
5049 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5050 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5051 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5052 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5053 gen_set_label(l1);
5054 tcg_temp_free(t0);
5055 tcg_temp_free(t1);
5056 if (unlikely(Rc(ctx->opcode) != 0))
5057 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5058 }
5059
5060 /* sraiq - sraiq. */
5061 static void gen_sraiq(DisasContext *ctx)
5062 {
5063 int sh = SH(ctx->opcode);
5064 int l1 = gen_new_label();
5065 TCGv t0 = tcg_temp_new();
5066 TCGv t1 = tcg_temp_new();
5067 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5068 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5069 tcg_gen_or_tl(t0, t0, t1);
5070 gen_store_spr(SPR_MQ, t0);
5071 tcg_gen_movi_tl(cpu_ca, 0);
5072 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5073 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5074 tcg_gen_movi_tl(cpu_ca, 1);
5075 gen_set_label(l1);
5076 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5077 tcg_temp_free(t0);
5078 tcg_temp_free(t1);
5079 if (unlikely(Rc(ctx->opcode) != 0))
5080 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5081 }
5082
5083 /* sraq - sraq. */
5084 static void gen_sraq(DisasContext *ctx)
5085 {
5086 int l1 = gen_new_label();
5087 int l2 = gen_new_label();
5088 TCGv t0 = tcg_temp_new();
5089 TCGv t1 = tcg_temp_local_new();
5090 TCGv t2 = tcg_temp_local_new();
5091 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5092 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5093 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5094 tcg_gen_subfi_tl(t2, 32, t2);
5095 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5096 tcg_gen_or_tl(t0, t0, t2);
5097 gen_store_spr(SPR_MQ, t0);
5098 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5099 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5100 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5101 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5102 gen_set_label(l1);
5103 tcg_temp_free(t0);
5104 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5105 tcg_gen_movi_tl(cpu_ca, 0);
5106 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5107 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5108 tcg_gen_movi_tl(cpu_ca, 1);
5109 gen_set_label(l2);
5110 tcg_temp_free(t1);
5111 tcg_temp_free(t2);
5112 if (unlikely(Rc(ctx->opcode) != 0))
5113 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5114 }
5115
5116 /* sre - sre. */
5117 static void gen_sre(DisasContext *ctx)
5118 {
5119 TCGv t0 = tcg_temp_new();
5120 TCGv t1 = tcg_temp_new();
5121 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5122 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5123 tcg_gen_subfi_tl(t1, 32, t1);
5124 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5125 tcg_gen_or_tl(t1, t0, t1);
5126 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5127 gen_store_spr(SPR_MQ, t1);
5128 tcg_temp_free(t0);
5129 tcg_temp_free(t1);
5130 if (unlikely(Rc(ctx->opcode) != 0))
5131 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5132 }
5133
5134 /* srea - srea. */
5135 static void gen_srea(DisasContext *ctx)
5136 {
5137 TCGv t0 = tcg_temp_new();
5138 TCGv t1 = tcg_temp_new();
5139 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5140 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5141 gen_store_spr(SPR_MQ, t0);
5142 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5143 tcg_temp_free(t0);
5144 tcg_temp_free(t1);
5145 if (unlikely(Rc(ctx->opcode) != 0))
5146 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5147 }
5148
5149 /* sreq */
5150 static void gen_sreq(DisasContext *ctx)
5151 {
5152 TCGv t0 = tcg_temp_new();
5153 TCGv t1 = tcg_temp_new();
5154 TCGv t2 = tcg_temp_new();
5155 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5156 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5157 tcg_gen_shr_tl(t1, t1, t0);
5158 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5159 gen_load_spr(t2, SPR_MQ);
5160 gen_store_spr(SPR_MQ, t0);
5161 tcg_gen_and_tl(t0, t0, t1);
5162 tcg_gen_andc_tl(t2, t2, t1);
5163 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5164 tcg_temp_free(t0);
5165 tcg_temp_free(t1);
5166 tcg_temp_free(t2);
5167 if (unlikely(Rc(ctx->opcode) != 0))
5168 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5169 }
5170
5171 /* sriq */
5172 static void gen_sriq(DisasContext *ctx)
5173 {
5174 int sh = SH(ctx->opcode);
5175 TCGv t0 = tcg_temp_new();
5176 TCGv t1 = tcg_temp_new();
5177 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5178 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5179 tcg_gen_or_tl(t1, t0, t1);
5180 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5181 gen_store_spr(SPR_MQ, t1);
5182 tcg_temp_free(t0);
5183 tcg_temp_free(t1);
5184 if (unlikely(Rc(ctx->opcode) != 0))
5185 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5186 }
5187
5188 /* srliq */
5189 static void gen_srliq(DisasContext *ctx)
5190 {
5191 int sh = SH(ctx->opcode);
5192 TCGv t0 = tcg_temp_new();
5193 TCGv t1 = tcg_temp_new();
5194 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5195 gen_load_spr(t1, SPR_MQ);
5196 gen_store_spr(SPR_MQ, t0);
5197 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5198 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5199 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5200 tcg_temp_free(t0);
5201 tcg_temp_free(t1);
5202 if (unlikely(Rc(ctx->opcode) != 0))
5203 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5204 }
5205
5206 /* srlq */
5207 static void gen_srlq(DisasContext *ctx)
5208 {
5209 int l1 = gen_new_label();
5210 int l2 = gen_new_label();
5211 TCGv t0 = tcg_temp_local_new();
5212 TCGv t1 = tcg_temp_local_new();
5213 TCGv t2 = tcg_temp_local_new();
5214 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5215 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5216 tcg_gen_shr_tl(t2, t1, t2);
5217 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5218 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5219 gen_load_spr(t0, SPR_MQ);
5220 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5221 tcg_gen_br(l2);
5222 gen_set_label(l1);
5223 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5224 tcg_gen_and_tl(t0, t0, t2);
5225 gen_load_spr(t1, SPR_MQ);
5226 tcg_gen_andc_tl(t1, t1, t2);
5227 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5228 gen_set_label(l2);
5229 tcg_temp_free(t0);
5230 tcg_temp_free(t1);
5231 tcg_temp_free(t2);
5232 if (unlikely(Rc(ctx->opcode) != 0))
5233 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5234 }
5235
5236 /* srq */
5237 static void gen_srq(DisasContext *ctx)
5238 {
5239 int l1 = gen_new_label();
5240 TCGv t0 = tcg_temp_new();
5241 TCGv t1 = tcg_temp_new();
5242 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5243 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5244 tcg_gen_subfi_tl(t1, 32, t1);
5245 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5246 tcg_gen_or_tl(t1, t0, t1);
5247 gen_store_spr(SPR_MQ, t1);
5248 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5249 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5250 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5251 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5252 gen_set_label(l1);
5253 tcg_temp_free(t0);
5254 tcg_temp_free(t1);
5255 if (unlikely(Rc(ctx->opcode) != 0))
5256 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5257 }
5258
5259 /* PowerPC 602 specific instructions */
5260
5261 /* dsa */
5262 static void gen_dsa(DisasContext *ctx)
5263 {
5264 /* XXX: TODO */
5265 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5266 }
5267
5268 /* esa */
5269 static void gen_esa(DisasContext *ctx)
5270 {
5271 /* XXX: TODO */
5272 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5273 }
5274
5275 /* mfrom */
5276 static void gen_mfrom(DisasContext *ctx)
5277 {
5278 #if defined(CONFIG_USER_ONLY)
5279 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5280 #else
5281 if (unlikely(!ctx->mem_idx)) {
5282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5283 return;
5284 }
5285 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5286 #endif
5287 }
5288
5289 /* 602 - 603 - G2 TLB management */
5290
5291 /* tlbld */
5292 static void gen_tlbld_6xx(DisasContext *ctx)
5293 {
5294 #if defined(CONFIG_USER_ONLY)
5295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5296 #else
5297 if (unlikely(!ctx->mem_idx)) {
5298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5299 return;
5300 }
5301 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5302 #endif
5303 }
5304
5305 /* tlbli */
5306 static void gen_tlbli_6xx(DisasContext *ctx)
5307 {
5308 #if defined(CONFIG_USER_ONLY)
5309 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5310 #else
5311 if (unlikely(!ctx->mem_idx)) {
5312 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5313 return;
5314 }
5315 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5316 #endif
5317 }
5318
5319 /* 74xx TLB management */
5320
5321 /* tlbld */
5322 static void gen_tlbld_74xx(DisasContext *ctx)
5323 {
5324 #if defined(CONFIG_USER_ONLY)
5325 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5326 #else
5327 if (unlikely(!ctx->mem_idx)) {
5328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5329 return;
5330 }
5331 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5332 #endif
5333 }
5334
5335 /* tlbli */
5336 static void gen_tlbli_74xx(DisasContext *ctx)
5337 {
5338 #if defined(CONFIG_USER_ONLY)
5339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5340 #else
5341 if (unlikely(!ctx->mem_idx)) {
5342 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5343 return;
5344 }
5345 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5346 #endif
5347 }
5348
5349 /* POWER instructions not in PowerPC 601 */
5350
5351 /* clf */
5352 static void gen_clf(DisasContext *ctx)
5353 {
5354 /* Cache line flush: implemented as no-op */
5355 }
5356
5357 /* cli */
5358 static void gen_cli(DisasContext *ctx)
5359 {
5360 /* Cache line invalidate: privileged and treated as no-op */
5361 #if defined(CONFIG_USER_ONLY)
5362 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5363 #else
5364 if (unlikely(!ctx->mem_idx)) {
5365 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5366 return;
5367 }
5368 #endif
5369 }
5370
5371 /* dclst */
5372 static void gen_dclst(DisasContext *ctx)
5373 {
5374 /* Data cache line store: treated as no-op */
5375 }
5376
5377 static void gen_mfsri(DisasContext *ctx)
5378 {
5379 #if defined(CONFIG_USER_ONLY)
5380 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5381 #else
5382 int ra = rA(ctx->opcode);
5383 int rd = rD(ctx->opcode);
5384 TCGv t0;
5385 if (unlikely(!ctx->mem_idx)) {
5386 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5387 return;
5388 }
5389 t0 = tcg_temp_new();
5390 gen_addr_reg_index(ctx, t0);
5391 tcg_gen_shri_tl(t0, t0, 28);
5392 tcg_gen_andi_tl(t0, t0, 0xF);
5393 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5394 tcg_temp_free(t0);
5395 if (ra != 0 && ra != rd)
5396 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5397 #endif
5398 }
5399
5400 static void gen_rac(DisasContext *ctx)
5401 {
5402 #if defined(CONFIG_USER_ONLY)
5403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5404 #else
5405 TCGv t0;
5406 if (unlikely(!ctx->mem_idx)) {
5407 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5408 return;
5409 }
5410 t0 = tcg_temp_new();
5411 gen_addr_reg_index(ctx, t0);
5412 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5413 tcg_temp_free(t0);
5414 #endif
5415 }
5416
5417 static void gen_rfsvc(DisasContext *ctx)
5418 {
5419 #if defined(CONFIG_USER_ONLY)
5420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5421 #else
5422 if (unlikely(!ctx->mem_idx)) {
5423 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5424 return;
5425 }
5426 gen_helper_rfsvc(cpu_env);
5427 gen_sync_exception(ctx);
5428 #endif
5429 }
5430
5431 /* svc is not implemented for now */
5432
5433 /* POWER2 specific instructions */
5434 /* Quad manipulation (load/store two floats at a time) */
5435
5436 /* lfq */
5437 static void gen_lfq(DisasContext *ctx)
5438 {
5439 int rd = rD(ctx->opcode);
5440 TCGv t0;
5441 gen_set_access_type(ctx, ACCESS_FLOAT);
5442 t0 = tcg_temp_new();
5443 gen_addr_imm_index(ctx, t0, 0);
5444 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5445 gen_addr_add(ctx, t0, t0, 8);
5446 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5447 tcg_temp_free(t0);
5448 }
5449
5450 /* lfqu */
5451 static void gen_lfqu(DisasContext *ctx)
5452 {
5453 int ra = rA(ctx->opcode);
5454 int rd = rD(ctx->opcode);
5455 TCGv t0, t1;
5456 gen_set_access_type(ctx, ACCESS_FLOAT);
5457 t0 = tcg_temp_new();
5458 t1 = tcg_temp_new();
5459 gen_addr_imm_index(ctx, t0, 0);
5460 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5461 gen_addr_add(ctx, t1, t0, 8);
5462 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5463 if (ra != 0)
5464 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5465 tcg_temp_free(t0);
5466 tcg_temp_free(t1);
5467 }
5468
5469 /* lfqux */
5470 static void gen_lfqux(DisasContext *ctx)
5471 {
5472 int ra = rA(ctx->opcode);
5473 int rd = rD(ctx->opcode);
5474 gen_set_access_type(ctx, ACCESS_FLOAT);
5475 TCGv t0, t1;
5476 t0 = tcg_temp_new();
5477 gen_addr_reg_index(ctx, t0);
5478 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5479 t1 = tcg_temp_new();
5480 gen_addr_add(ctx, t1, t0, 8);
5481 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5482 tcg_temp_free(t1);
5483 if (ra != 0)
5484 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5485 tcg_temp_free(t0);
5486 }
5487
5488 /* lfqx */
5489 static void gen_lfqx(DisasContext *ctx)
5490 {
5491 int rd = rD(ctx->opcode);
5492 TCGv t0;
5493 gen_set_access_type(ctx, ACCESS_FLOAT);
5494 t0 = tcg_temp_new();
5495 gen_addr_reg_index(ctx, t0);
5496 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5497 gen_addr_add(ctx, t0, t0, 8);
5498 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5499 tcg_temp_free(t0);
5500 }
5501
5502 /* stfq */
5503 static void gen_stfq(DisasContext *ctx)
5504 {
5505 int rd = rD(ctx->opcode);
5506 TCGv t0;
5507 gen_set_access_type(ctx, ACCESS_FLOAT);
5508 t0 = tcg_temp_new();
5509 gen_addr_imm_index(ctx, t0, 0);
5510 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5511 gen_addr_add(ctx, t0, t0, 8);
5512 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5513 tcg_temp_free(t0);
5514 }
5515
5516 /* stfqu */
5517 static void gen_stfqu(DisasContext *ctx)
5518 {
5519 int ra = rA(ctx->opcode);
5520 int rd = rD(ctx->opcode);
5521 TCGv t0, t1;
5522 gen_set_access_type(ctx, ACCESS_FLOAT);
5523 t0 = tcg_temp_new();
5524 gen_addr_imm_index(ctx, t0, 0);
5525 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5526 t1 = tcg_temp_new();
5527 gen_addr_add(ctx, t1, t0, 8);
5528 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5529 tcg_temp_free(t1);
5530 if (ra != 0)
5531 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5532 tcg_temp_free(t0);
5533 }
5534
5535 /* stfqux */
5536 static void gen_stfqux(DisasContext *ctx)
5537 {
5538 int ra = rA(ctx->opcode);
5539 int rd = rD(ctx->opcode);
5540 TCGv t0, t1;
5541 gen_set_access_type(ctx, ACCESS_FLOAT);
5542 t0 = tcg_temp_new();
5543 gen_addr_reg_index(ctx, t0);
5544 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5545 t1 = tcg_temp_new();
5546 gen_addr_add(ctx, t1, t0, 8);
5547 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5548 tcg_temp_free(t1);
5549 if (ra != 0)
5550 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5551 tcg_temp_free(t0);
5552 }
5553
5554 /* stfqx */
5555 static void gen_stfqx(DisasContext *ctx)
5556 {
5557 int rd = rD(ctx->opcode);
5558 TCGv t0;
5559 gen_set_access_type(ctx, ACCESS_FLOAT);
5560 t0 = tcg_temp_new();
5561 gen_addr_reg_index(ctx, t0);
5562 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5563 gen_addr_add(ctx, t0, t0, 8);
5564 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5565 tcg_temp_free(t0);
5566 }
5567
5568 /* BookE specific instructions */
5569
5570 /* XXX: not implemented on 440 ? */
5571 static void gen_mfapidi(DisasContext *ctx)
5572 {
5573 /* XXX: TODO */
5574 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5575 }
5576
5577 /* XXX: not implemented on 440 ? */
5578 static void gen_tlbiva(DisasContext *ctx)
5579 {
5580 #if defined(CONFIG_USER_ONLY)
5581 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5582 #else
5583 TCGv t0;
5584 if (unlikely(!ctx->mem_idx)) {
5585 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5586 return;
5587 }
5588 t0 = tcg_temp_new();
5589 gen_addr_reg_index(ctx, t0);
5590 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5591 tcg_temp_free(t0);
5592 #endif
5593 }
5594
5595 /* All 405 MAC instructions are translated here */
5596 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5597 int ra, int rb, int rt, int Rc)
5598 {
5599 TCGv t0, t1;
5600
5601 t0 = tcg_temp_local_new();
5602 t1 = tcg_temp_local_new();
5603
5604 switch (opc3 & 0x0D) {
5605 case 0x05:
5606 /* macchw - macchw. - macchwo - macchwo. */
5607 /* macchws - macchws. - macchwso - macchwso. */
5608 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5609 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5610 /* mulchw - mulchw. */
5611 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5612 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5613 tcg_gen_ext16s_tl(t1, t1);
5614 break;
5615 case 0x04:
5616 /* macchwu - macchwu. - macchwuo - macchwuo. */
5617 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5618 /* mulchwu - mulchwu. */
5619 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5620 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5621 tcg_gen_ext16u_tl(t1, t1);
5622 break;
5623 case 0x01:
5624 /* machhw - machhw. - machhwo - machhwo. */
5625 /* machhws - machhws. - machhwso - machhwso. */
5626 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5627 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5628 /* mulhhw - mulhhw. */
5629 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5630 tcg_gen_ext16s_tl(t0, t0);
5631 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5632 tcg_gen_ext16s_tl(t1, t1);
5633 break;
5634 case 0x00:
5635 /* machhwu - machhwu. - machhwuo - machhwuo. */
5636 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5637 /* mulhhwu - mulhhwu. */
5638 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5639 tcg_gen_ext16u_tl(t0, t0);
5640 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5641 tcg_gen_ext16u_tl(t1, t1);
5642 break;
5643 case 0x0D:
5644 /* maclhw - maclhw. - maclhwo - maclhwo. */
5645 /* maclhws - maclhws. - maclhwso - maclhwso. */
5646 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5647 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5648 /* mullhw - mullhw. */
5649 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5650 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5651 break;
5652 case 0x0C:
5653 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5654 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5655 /* mullhwu - mullhwu. */
5656 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5657 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5658 break;
5659 }
5660 if (opc2 & 0x04) {
5661 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5662 tcg_gen_mul_tl(t1, t0, t1);
5663 if (opc2 & 0x02) {
5664 /* nmultiply-and-accumulate (0x0E) */
5665 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5666 } else {
5667 /* multiply-and-accumulate (0x0C) */
5668 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5669 }
5670
5671 if (opc3 & 0x12) {
5672 /* Check overflow and/or saturate */
5673 int l1 = gen_new_label();
5674
5675 if (opc3 & 0x10) {
5676 /* Start with XER OV disabled, the most likely case */
5677 tcg_gen_movi_tl(cpu_ov, 0);
5678 }
5679 if (opc3 & 0x01) {
5680 /* Signed */
5681 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5682 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5683 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5684 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5685 if (opc3 & 0x02) {
5686 /* Saturate */
5687 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5688 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5689 }
5690 } else {
5691 /* Unsigned */
5692 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5693 if (opc3 & 0x02) {
5694 /* Saturate */
5695 tcg_gen_movi_tl(t0, UINT32_MAX);
5696 }
5697 }
5698 if (opc3 & 0x10) {
5699 /* Check overflow */
5700 tcg_gen_movi_tl(cpu_ov, 1);
5701 tcg_gen_movi_tl(cpu_so, 1);
5702 }
5703 gen_set_label(l1);
5704 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5705 }
5706 } else {
5707 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5708 }
5709 tcg_temp_free(t0);
5710 tcg_temp_free(t1);
5711 if (unlikely(Rc) != 0) {
5712 /* Update Rc0 */
5713 gen_set_Rc0(ctx, cpu_gpr[rt]);
5714 }
5715 }
5716
5717 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5718 static void glue(gen_, name)(DisasContext *ctx) \
5719 { \
5720 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5721 rD(ctx->opcode), Rc(ctx->opcode)); \
5722 }
5723
5724 /* macchw - macchw. */
5725 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5726 /* macchwo - macchwo. */
5727 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5728 /* macchws - macchws. */
5729 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5730 /* macchwso - macchwso. */
5731 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5732 /* macchwsu - macchwsu. */
5733 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5734 /* macchwsuo - macchwsuo. */
5735 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5736 /* macchwu - macchwu. */
5737 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5738 /* macchwuo - macchwuo. */
5739 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5740 /* machhw - machhw. */
5741 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5742 /* machhwo - machhwo. */
5743 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5744 /* machhws - machhws. */
5745 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5746 /* machhwso - machhwso. */
5747 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5748 /* machhwsu - machhwsu. */
5749 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5750 /* machhwsuo - machhwsuo. */
5751 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5752 /* machhwu - machhwu. */
5753 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5754 /* machhwuo - machhwuo. */
5755 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5756 /* maclhw - maclhw. */
5757 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5758 /* maclhwo - maclhwo. */
5759 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5760 /* maclhws - maclhws. */
5761 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5762 /* maclhwso - maclhwso. */
5763 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5764 /* maclhwu - maclhwu. */
5765 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5766 /* maclhwuo - maclhwuo. */
5767 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5768 /* maclhwsu - maclhwsu. */
5769 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5770 /* maclhwsuo - maclhwsuo. */
5771 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5772 /* nmacchw - nmacchw. */
5773 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5774 /* nmacchwo - nmacchwo. */
5775 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5776 /* nmacchws - nmacchws. */
5777 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5778 /* nmacchwso - nmacchwso. */
5779 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5780 /* nmachhw - nmachhw. */
5781 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5782 /* nmachhwo - nmachhwo. */
5783 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5784 /* nmachhws - nmachhws. */
5785 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5786 /* nmachhwso - nmachhwso. */
5787 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5788 /* nmaclhw - nmaclhw. */
5789 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5790 /* nmaclhwo - nmaclhwo. */
5791 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5792 /* nmaclhws - nmaclhws. */
5793 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5794 /* nmaclhwso - nmaclhwso. */
5795 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5796
5797 /* mulchw - mulchw. */
5798 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5799 /* mulchwu - mulchwu. */
5800 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5801 /* mulhhw - mulhhw. */
5802 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5803 /* mulhhwu - mulhhwu. */
5804 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5805 /* mullhw - mullhw. */
5806 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5807 /* mullhwu - mullhwu. */
5808 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5809
5810 /* mfdcr */
5811 static void gen_mfdcr(DisasContext *ctx)
5812 {
5813 #if defined(CONFIG_USER_ONLY)
5814 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5815 #else
5816 TCGv dcrn;
5817 if (unlikely(!ctx->mem_idx)) {
5818 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5819 return;
5820 }
5821 /* NIP cannot be restored if the memory exception comes from an helper */
5822 gen_update_nip(ctx, ctx->nip - 4);
5823 dcrn = tcg_const_tl(SPR(ctx->opcode));
5824 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5825 tcg_temp_free(dcrn);
5826 #endif
5827 }
5828
5829 /* mtdcr */
5830 static void gen_mtdcr(DisasContext *ctx)
5831 {
5832 #if defined(CONFIG_USER_ONLY)
5833 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5834 #else
5835 TCGv dcrn;
5836 if (unlikely(!ctx->mem_idx)) {
5837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5838 return;
5839 }
5840 /* NIP cannot be restored if the memory exception comes from an helper */
5841 gen_update_nip(ctx, ctx->nip - 4);
5842 dcrn = tcg_const_tl(SPR(ctx->opcode));
5843 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5844 tcg_temp_free(dcrn);
5845 #endif
5846 }
5847
5848 /* mfdcrx */
5849 /* XXX: not implemented on 440 ? */
5850 static void gen_mfdcrx(DisasContext *ctx)
5851 {
5852 #if defined(CONFIG_USER_ONLY)
5853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5854 #else
5855 if (unlikely(!ctx->mem_idx)) {
5856 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5857 return;
5858 }
5859 /* NIP cannot be restored if the memory exception comes from an helper */
5860 gen_update_nip(ctx, ctx->nip - 4);
5861 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5862 cpu_gpr[rA(ctx->opcode)]);
5863 /* Note: Rc update flag set leads to undefined state of Rc0 */
5864 #endif
5865 }
5866
5867 /* mtdcrx */
5868 /* XXX: not implemented on 440 ? */
5869 static void gen_mtdcrx(DisasContext *ctx)
5870 {
5871 #if defined(CONFIG_USER_ONLY)
5872 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5873 #else
5874 if (unlikely(!ctx->mem_idx)) {
5875 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5876 return;
5877 }
5878 /* NIP cannot be restored if the memory exception comes from an helper */
5879 gen_update_nip(ctx, ctx->nip - 4);
5880 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5881 cpu_gpr[rS(ctx->opcode)]);
5882 /* Note: Rc update flag set leads to undefined state of Rc0 */
5883 #endif
5884 }
5885
5886 /* mfdcrux (PPC 460) : user-mode access to DCR */
5887 static void gen_mfdcrux(DisasContext *ctx)
5888 {
5889 /* NIP cannot be restored if the memory exception comes from an helper */
5890 gen_update_nip(ctx, ctx->nip - 4);
5891 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5892 cpu_gpr[rA(ctx->opcode)]);
5893 /* Note: Rc update flag set leads to undefined state of Rc0 */
5894 }
5895
5896 /* mtdcrux (PPC 460) : user-mode access to DCR */
5897 static void gen_mtdcrux(DisasContext *ctx)
5898 {
5899 /* NIP cannot be restored if the memory exception comes from an helper */
5900 gen_update_nip(ctx, ctx->nip - 4);
5901 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5902 cpu_gpr[rS(ctx->opcode)]);
5903 /* Note: Rc update flag set leads to undefined state of Rc0 */
5904 }
5905
5906 /* dccci */
5907 static void gen_dccci(DisasContext *ctx)
5908 {
5909 #if defined(CONFIG_USER_ONLY)
5910 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5911 #else
5912 if (unlikely(!ctx->mem_idx)) {
5913 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5914 return;
5915 }
5916 /* interpreted as no-op */
5917 #endif
5918 }
5919
5920 /* dcread */
5921 static void gen_dcread(DisasContext *ctx)
5922 {
5923 #if defined(CONFIG_USER_ONLY)
5924 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5925 #else
5926 TCGv EA, val;
5927 if (unlikely(!ctx->mem_idx)) {
5928 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5929 return;
5930 }
5931 gen_set_access_type(ctx, ACCESS_CACHE);
5932 EA = tcg_temp_new();
5933 gen_addr_reg_index(ctx, EA);
5934 val = tcg_temp_new();
5935 gen_qemu_ld32u(ctx, val, EA);
5936 tcg_temp_free(val);
5937 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5938 tcg_temp_free(EA);
5939 #endif
5940 }
5941
5942 /* icbt */
5943 static void gen_icbt_40x(DisasContext *ctx)
5944 {
5945 /* interpreted as no-op */
5946 /* XXX: specification say this is treated as a load by the MMU
5947 * but does not generate any exception
5948 */
5949 }
5950
5951 /* iccci */
5952 static void gen_iccci(DisasContext *ctx)
5953 {
5954 #if defined(CONFIG_USER_ONLY)
5955 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5956 #else
5957 if (unlikely(!ctx->mem_idx)) {
5958 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5959 return;
5960 }
5961 /* interpreted as no-op */
5962 #endif
5963 }
5964
5965 /* icread */
5966 static void gen_icread(DisasContext *ctx)
5967 {
5968 #if defined(CONFIG_USER_ONLY)
5969 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5970 #else
5971 if (unlikely(!ctx->mem_idx)) {
5972 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5973 return;
5974 }
5975 /* interpreted as no-op */
5976 #endif
5977 }
5978
5979 /* rfci (mem_idx only) */
5980 static void gen_rfci_40x(DisasContext *ctx)
5981 {
5982 #if defined(CONFIG_USER_ONLY)
5983 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5984 #else
5985 if (unlikely(!ctx->mem_idx)) {
5986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5987 return;
5988 }
5989 /* Restore CPU state */
5990 gen_helper_40x_rfci(cpu_env);
5991 gen_sync_exception(ctx);
5992 #endif
5993 }
5994
5995 static void gen_rfci(DisasContext *ctx)
5996 {
5997 #if defined(CONFIG_USER_ONLY)
5998 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5999 #else
6000 if (unlikely(!ctx->mem_idx)) {
6001 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6002 return;
6003 }
6004 /* Restore CPU state */
6005 gen_helper_rfci(cpu_env);
6006 gen_sync_exception(ctx);
6007 #endif
6008 }
6009
6010 /* BookE specific */
6011
6012 /* XXX: not implemented on 440 ? */
6013 static void gen_rfdi(DisasContext *ctx)
6014 {
6015 #if defined(CONFIG_USER_ONLY)
6016 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6017 #else
6018 if (unlikely(!ctx->mem_idx)) {
6019 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6020 return;
6021 }
6022 /* Restore CPU state */
6023 gen_helper_rfdi(cpu_env);
6024 gen_sync_exception(ctx);
6025 #endif
6026 }
6027
6028 /* XXX: not implemented on 440 ? */
6029 static void gen_rfmci(DisasContext *ctx)
6030 {
6031 #if defined(CONFIG_USER_ONLY)
6032 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6033 #else
6034 if (unlikely(!ctx->mem_idx)) {
6035 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6036 return;
6037 }
6038 /* Restore CPU state */
6039 gen_helper_rfmci(cpu_env);
6040 gen_sync_exception(ctx);
6041 #endif
6042 }
6043
6044 /* TLB management - PowerPC 405 implementation */
6045
6046 /* tlbre */
6047 static void gen_tlbre_40x(DisasContext *ctx)
6048 {
6049 #if defined(CONFIG_USER_ONLY)
6050 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6051 #else
6052 if (unlikely(!ctx->mem_idx)) {
6053 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6054 return;
6055 }
6056 switch (rB(ctx->opcode)) {
6057 case 0:
6058 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6059 cpu_gpr[rA(ctx->opcode)]);
6060 break;
6061 case 1:
6062 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6063 cpu_gpr[rA(ctx->opcode)]);
6064 break;
6065 default:
6066 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6067 break;
6068 }
6069 #endif
6070 }
6071
6072 /* tlbsx - tlbsx. */
6073 static void gen_tlbsx_40x(DisasContext *ctx)
6074 {
6075 #if defined(CONFIG_USER_ONLY)
6076 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6077 #else
6078 TCGv t0;
6079 if (unlikely(!ctx->mem_idx)) {
6080 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6081 return;
6082 }
6083 t0 = tcg_temp_new();
6084 gen_addr_reg_index(ctx, t0);
6085 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6086 tcg_temp_free(t0);
6087 if (Rc(ctx->opcode)) {
6088 int l1 = gen_new_label();
6089 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6090 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6091 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6092 gen_set_label(l1);
6093 }
6094 #endif
6095 }
6096
6097 /* tlbwe */
6098 static void gen_tlbwe_40x(DisasContext *ctx)
6099 {
6100 #if defined(CONFIG_USER_ONLY)
6101 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6102 #else
6103 if (unlikely(!ctx->mem_idx)) {
6104 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6105 return;
6106 }
6107 switch (rB(ctx->opcode)) {
6108 case 0:
6109 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6110 cpu_gpr[rS(ctx->opcode)]);
6111 break;
6112 case 1:
6113 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6114 cpu_gpr[rS(ctx->opcode)]);
6115 break;
6116 default:
6117 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6118 break;
6119 }
6120 #endif
6121 }
6122
6123 /* TLB management - PowerPC 440 implementation */
6124
6125 /* tlbre */
6126 static void gen_tlbre_440(DisasContext *ctx)
6127 {
6128 #if defined(CONFIG_USER_ONLY)
6129 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6130 #else
6131 if (unlikely(!ctx->mem_idx)) {
6132 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6133 return;
6134 }
6135 switch (rB(ctx->opcode)) {
6136 case 0:
6137 case 1:
6138 case 2:
6139 {
6140 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6141 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6142 t0, cpu_gpr[rA(ctx->opcode)]);
6143 tcg_temp_free_i32(t0);
6144 }
6145 break;
6146 default:
6147 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6148 break;
6149 }
6150 #endif
6151 }
6152
6153 /* tlbsx - tlbsx. */
6154 static void gen_tlbsx_440(DisasContext *ctx)
6155 {
6156 #if defined(CONFIG_USER_ONLY)
6157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6158 #else
6159 TCGv t0;
6160 if (unlikely(!ctx->mem_idx)) {
6161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6162 return;
6163 }
6164 t0 = tcg_temp_new();
6165 gen_addr_reg_index(ctx, t0);
6166 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6167 tcg_temp_free(t0);
6168 if (Rc(ctx->opcode)) {
6169 int l1 = gen_new_label();
6170 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6171 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6172 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6173 gen_set_label(l1);
6174 }
6175 #endif
6176 }
6177
6178 /* tlbwe */
6179 static void gen_tlbwe_440(DisasContext *ctx)
6180 {
6181 #if defined(CONFIG_USER_ONLY)
6182 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6183 #else
6184 if (unlikely(!ctx->mem_idx)) {
6185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6186 return;
6187 }
6188 switch (rB(ctx->opcode)) {
6189 case 0:
6190 case 1:
6191 case 2:
6192 {
6193 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6194 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6195 cpu_gpr[rS(ctx->opcode)]);
6196 tcg_temp_free_i32(t0);
6197 }
6198 break;
6199 default:
6200 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6201 break;
6202 }
6203 #endif
6204 }
6205
6206 /* TLB management - PowerPC BookE 2.06 implementation */
6207
6208 /* tlbre */
6209 static void gen_tlbre_booke206(DisasContext *ctx)
6210 {
6211 #if defined(CONFIG_USER_ONLY)
6212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6213 #else
6214 if (unlikely(!ctx->mem_idx)) {
6215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6216 return;
6217 }
6218
6219 gen_helper_booke206_tlbre(cpu_env);
6220 #endif
6221 }
6222
6223 /* tlbsx - tlbsx. */
6224 static void gen_tlbsx_booke206(DisasContext *ctx)
6225 {
6226 #if defined(CONFIG_USER_ONLY)
6227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6228 #else
6229 TCGv t0;
6230 if (unlikely(!ctx->mem_idx)) {
6231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6232 return;
6233 }
6234
6235 if (rA(ctx->opcode)) {
6236 t0 = tcg_temp_new();
6237 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6238 } else {
6239 t0 = tcg_const_tl(0);
6240 }
6241
6242 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6243 gen_helper_booke206_tlbsx(cpu_env, t0);
6244 #endif
6245 }
6246
6247 /* tlbwe */
6248 static void gen_tlbwe_booke206(DisasContext *ctx)
6249 {
6250 #if defined(CONFIG_USER_ONLY)
6251 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6252 #else
6253 if (unlikely(!ctx->mem_idx)) {
6254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6255 return;
6256 }
6257 gen_update_nip(ctx, ctx->nip - 4);
6258 gen_helper_booke206_tlbwe(cpu_env);
6259 #endif
6260 }
6261
6262 static void gen_tlbivax_booke206(DisasContext *ctx)
6263 {
6264 #if defined(CONFIG_USER_ONLY)
6265 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6266 #else
6267 TCGv t0;
6268 if (unlikely(!ctx->mem_idx)) {
6269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6270 return;
6271 }
6272
6273 t0 = tcg_temp_new();
6274 gen_addr_reg_index(ctx, t0);
6275
6276 gen_helper_booke206_tlbivax(cpu_env, t0);
6277 #endif
6278 }
6279
6280 static void gen_tlbilx_booke206(DisasContext *ctx)
6281 {
6282 #if defined(CONFIG_USER_ONLY)
6283 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6284 #else
6285 TCGv t0;
6286 if (unlikely(!ctx->mem_idx)) {
6287 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6288 return;
6289 }
6290
6291 t0 = tcg_temp_new();
6292 gen_addr_reg_index(ctx, t0);
6293
6294 switch((ctx->opcode >> 21) & 0x3) {
6295 case 0:
6296 gen_helper_booke206_tlbilx0(cpu_env, t0);
6297 break;
6298 case 1:
6299 gen_helper_booke206_tlbilx1(cpu_env, t0);
6300 break;
6301 case 3:
6302 gen_helper_booke206_tlbilx3(cpu_env, t0);
6303 break;
6304 default:
6305 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6306 break;
6307 }
6308
6309 tcg_temp_free(t0);
6310 #endif
6311 }
6312
6313
6314 /* wrtee */
6315 static void gen_wrtee(DisasContext *ctx)
6316 {
6317 #if defined(CONFIG_USER_ONLY)
6318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6319 #else
6320 TCGv t0;
6321 if (unlikely(!ctx->mem_idx)) {
6322 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6323 return;
6324 }
6325 t0 = tcg_temp_new();
6326 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6327 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6328 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6329 tcg_temp_free(t0);
6330 /* Stop translation to have a chance to raise an exception
6331 * if we just set msr_ee to 1
6332 */
6333 gen_stop_exception(ctx);
6334 #endif
6335 }
6336
6337 /* wrteei */
6338 static void gen_wrteei(DisasContext *ctx)
6339 {
6340 #if defined(CONFIG_USER_ONLY)
6341 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6342 #else
6343 if (unlikely(!ctx->mem_idx)) {
6344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6345 return;
6346 }
6347 if (ctx->opcode & 0x00008000) {
6348 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6349 /* Stop translation to have a chance to raise an exception */
6350 gen_stop_exception(ctx);
6351 } else {
6352 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6353 }
6354 #endif
6355 }
6356
6357 /* PowerPC 440 specific instructions */
6358
6359 /* dlmzb */
6360 static void gen_dlmzb(DisasContext *ctx)
6361 {
6362 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6363 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6364 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6365 tcg_temp_free_i32(t0);
6366 }
6367
6368 /* mbar replaces eieio on 440 */
6369 static void gen_mbar(DisasContext *ctx)
6370 {
6371 /* interpreted as no-op */
6372 }
6373
6374 /* msync replaces sync on 440 */
6375 static void gen_msync_4xx(DisasContext *ctx)
6376 {
6377 /* interpreted as no-op */
6378 }
6379
6380 /* icbt */
6381 static void gen_icbt_440(DisasContext *ctx)
6382 {
6383 /* interpreted as no-op */
6384 /* XXX: specification say this is treated as a load by the MMU
6385 * but does not generate any exception
6386 */
6387 }
6388
6389 /* Embedded.Processor Control */
6390
6391 static void gen_msgclr(DisasContext *ctx)
6392 {
6393 #if defined(CONFIG_USER_ONLY)
6394 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6395 #else
6396 if (unlikely(ctx->mem_idx == 0)) {
6397 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6398 return;
6399 }
6400
6401 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6402 #endif
6403 }
6404
6405 static void gen_msgsnd(DisasContext *ctx)
6406 {
6407 #if defined(CONFIG_USER_ONLY)
6408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6409 #else
6410 if (unlikely(ctx->mem_idx == 0)) {
6411 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6412 return;
6413 }
6414
6415 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6416 #endif
6417 }
6418
6419 /*** Altivec vector extension ***/
6420 /* Altivec registers moves */
6421
6422 static inline TCGv_ptr gen_avr_ptr(int reg)
6423 {
6424 TCGv_ptr r = tcg_temp_new_ptr();
6425 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6426 return r;
6427 }
6428
6429 #define GEN_VR_LDX(name, opc2, opc3) \
6430 static void glue(gen_, name)(DisasContext *ctx) \
6431 { \
6432 TCGv EA; \
6433 if (unlikely(!ctx->altivec_enabled)) { \
6434 gen_exception(ctx, POWERPC_EXCP_VPU); \
6435 return; \
6436 } \
6437 gen_set_access_type(ctx, ACCESS_INT); \
6438 EA = tcg_temp_new(); \
6439 gen_addr_reg_index(ctx, EA); \
6440 tcg_gen_andi_tl(EA, EA, ~0xf); \
6441 if (ctx->le_mode) { \
6442 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6443 tcg_gen_addi_tl(EA, EA, 8); \
6444 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6445 } else { \
6446 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6447 tcg_gen_addi_tl(EA, EA, 8); \
6448 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6449 } \
6450 tcg_temp_free(EA); \
6451 }
6452
6453 #define GEN_VR_STX(name, opc2, opc3) \
6454 static void gen_st##name(DisasContext *ctx) \
6455 { \
6456 TCGv EA; \
6457 if (unlikely(!ctx->altivec_enabled)) { \
6458 gen_exception(ctx, POWERPC_EXCP_VPU); \
6459 return; \
6460 } \
6461 gen_set_access_type(ctx, ACCESS_INT); \
6462 EA = tcg_temp_new(); \
6463 gen_addr_reg_index(ctx, EA); \
6464 tcg_gen_andi_tl(EA, EA, ~0xf); \
6465 if (ctx->le_mode) { \
6466 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6467 tcg_gen_addi_tl(EA, EA, 8); \
6468 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6469 } else { \
6470 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6471 tcg_gen_addi_tl(EA, EA, 8); \
6472 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6473 } \
6474 tcg_temp_free(EA); \
6475 }
6476
6477 #define GEN_VR_LVE(name, opc2, opc3) \
6478 static void gen_lve##name(DisasContext *ctx) \
6479 { \
6480 TCGv EA; \
6481 TCGv_ptr rs; \
6482 if (unlikely(!ctx->altivec_enabled)) { \
6483 gen_exception(ctx, POWERPC_EXCP_VPU); \
6484 return; \
6485 } \
6486 gen_set_access_type(ctx, ACCESS_INT); \
6487 EA = tcg_temp_new(); \
6488 gen_addr_reg_index(ctx, EA); \
6489 rs = gen_avr_ptr(rS(ctx->opcode)); \
6490 gen_helper_lve##name(cpu_env, rs, EA); \
6491 tcg_temp_free(EA); \
6492 tcg_temp_free_ptr(rs); \
6493 }
6494
6495 #define GEN_VR_STVE(name, opc2, opc3) \
6496 static void gen_stve##name(DisasContext *ctx) \
6497 { \
6498 TCGv EA; \
6499 TCGv_ptr rs; \
6500 if (unlikely(!ctx->altivec_enabled)) { \
6501 gen_exception(ctx, POWERPC_EXCP_VPU); \
6502 return; \
6503 } \
6504 gen_set_access_type(ctx, ACCESS_INT); \
6505 EA = tcg_temp_new(); \
6506 gen_addr_reg_index(ctx, EA); \
6507 rs = gen_avr_ptr(rS(ctx->opcode)); \
6508 gen_helper_stve##name(cpu_env, rs, EA); \
6509 tcg_temp_free(EA); \
6510 tcg_temp_free_ptr(rs); \
6511 }
6512
6513 GEN_VR_LDX(lvx, 0x07, 0x03);
6514 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6515 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6516
6517 GEN_VR_LVE(bx, 0x07, 0x00);
6518 GEN_VR_LVE(hx, 0x07, 0x01);
6519 GEN_VR_LVE(wx, 0x07, 0x02);
6520
6521 GEN_VR_STX(svx, 0x07, 0x07);
6522 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6523 GEN_VR_STX(svxl, 0x07, 0x0F);
6524
6525 GEN_VR_STVE(bx, 0x07, 0x04);
6526 GEN_VR_STVE(hx, 0x07, 0x05);
6527 GEN_VR_STVE(wx, 0x07, 0x06);
6528
6529 static void gen_lvsl(DisasContext *ctx)
6530 {
6531 TCGv_ptr rd;
6532 TCGv EA;
6533 if (unlikely(!ctx->altivec_enabled)) {
6534 gen_exception(ctx, POWERPC_EXCP_VPU);
6535 return;
6536 }
6537 EA = tcg_temp_new();
6538 gen_addr_reg_index(ctx, EA);
6539 rd = gen_avr_ptr(rD(ctx->opcode));
6540 gen_helper_lvsl(rd, EA);
6541 tcg_temp_free(EA);
6542 tcg_temp_free_ptr(rd);
6543 }
6544
6545 static void gen_lvsr(DisasContext *ctx)
6546 {
6547 TCGv_ptr rd;
6548 TCGv EA;
6549 if (unlikely(!ctx->altivec_enabled)) {
6550 gen_exception(ctx, POWERPC_EXCP_VPU);
6551 return;
6552 }
6553 EA = tcg_temp_new();
6554 gen_addr_reg_index(ctx, EA);
6555 rd = gen_avr_ptr(rD(ctx->opcode));
6556 gen_helper_lvsr(rd, EA);
6557 tcg_temp_free(EA);
6558 tcg_temp_free_ptr(rd);
6559 }
6560
6561 static void gen_mfvscr(DisasContext *ctx)
6562 {
6563 TCGv_i32 t;
6564 if (unlikely(!ctx->altivec_enabled)) {
6565 gen_exception(ctx, POWERPC_EXCP_VPU);
6566 return;
6567 }
6568 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6569 t = tcg_temp_new_i32();
6570 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6571 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6572 tcg_temp_free_i32(t);
6573 }
6574
6575 static void gen_mtvscr(DisasContext *ctx)
6576 {
6577 TCGv_ptr p;
6578 if (unlikely(!ctx->altivec_enabled)) {
6579 gen_exception(ctx, POWERPC_EXCP_VPU);
6580 return;
6581 }
6582 p = gen_avr_ptr(rD(ctx->opcode));
6583 gen_helper_mtvscr(cpu_env, p);
6584 tcg_temp_free_ptr(p);
6585 }
6586
6587 /* Logical operations */
6588 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6589 static void glue(gen_, name)(DisasContext *ctx) \
6590 { \
6591 if (unlikely(!ctx->altivec_enabled)) { \
6592 gen_exception(ctx, POWERPC_EXCP_VPU); \
6593 return; \
6594 } \
6595 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6596 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6597 }
6598
6599 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6600 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6601 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6602 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6603 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6604
6605 #define GEN_VXFORM(name, opc2, opc3) \
6606 static void glue(gen_, name)(DisasContext *ctx) \
6607 { \
6608 TCGv_ptr ra, rb, rd; \
6609 if (unlikely(!ctx->altivec_enabled)) { \
6610 gen_exception(ctx, POWERPC_EXCP_VPU); \
6611 return; \
6612 } \
6613 ra = gen_avr_ptr(rA(ctx->opcode)); \
6614 rb = gen_avr_ptr(rB(ctx->opcode)); \
6615 rd = gen_avr_ptr(rD(ctx->opcode)); \
6616 gen_helper_##name (rd, ra, rb); \
6617 tcg_temp_free_ptr(ra); \
6618 tcg_temp_free_ptr(rb); \
6619 tcg_temp_free_ptr(rd); \
6620 }
6621
6622 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6623 static void glue(gen_, name)(DisasContext *ctx) \
6624 { \
6625 TCGv_ptr ra, rb, rd; \
6626 if (unlikely(!ctx->altivec_enabled)) { \
6627 gen_exception(ctx, POWERPC_EXCP_VPU); \
6628 return; \
6629 } \
6630 ra = gen_avr_ptr(rA(ctx->opcode)); \
6631 rb = gen_avr_ptr(rB(ctx->opcode)); \
6632 rd = gen_avr_ptr(rD(ctx->opcode)); \
6633 gen_helper_##name(cpu_env, rd, ra, rb); \
6634 tcg_temp_free_ptr(ra); \
6635 tcg_temp_free_ptr(rb); \
6636 tcg_temp_free_ptr(rd); \
6637 }
6638
6639 GEN_VXFORM(vaddubm, 0, 0);
6640 GEN_VXFORM(vadduhm, 0, 1);
6641 GEN_VXFORM(vadduwm, 0, 2);
6642 GEN_VXFORM(vsububm, 0, 16);
6643 GEN_VXFORM(vsubuhm, 0, 17);
6644 GEN_VXFORM(vsubuwm, 0, 18);
6645 GEN_VXFORM(vmaxub, 1, 0);
6646 GEN_VXFORM(vmaxuh, 1, 1);
6647 GEN_VXFORM(vmaxuw, 1, 2);
6648 GEN_VXFORM(vmaxsb, 1, 4);
6649 GEN_VXFORM(vmaxsh, 1, 5);
6650 GEN_VXFORM(vmaxsw, 1, 6);
6651 GEN_VXFORM(vminub, 1, 8);
6652 GEN_VXFORM(vminuh, 1, 9);
6653 GEN_VXFORM(vminuw, 1, 10);
6654 GEN_VXFORM(vminsb, 1, 12);
6655 GEN_VXFORM(vminsh, 1, 13);
6656 GEN_VXFORM(vminsw, 1, 14);
6657 GEN_VXFORM(vavgub, 1, 16);
6658 GEN_VXFORM(vavguh, 1, 17);
6659 GEN_VXFORM(vavguw, 1, 18);
6660 GEN_VXFORM(vavgsb, 1, 20);
6661 GEN_VXFORM(vavgsh, 1, 21);
6662 GEN_VXFORM(vavgsw, 1, 22);
6663 GEN_VXFORM(vmrghb, 6, 0);
6664 GEN_VXFORM(vmrghh, 6, 1);
6665 GEN_VXFORM(vmrghw, 6, 2);
6666 GEN_VXFORM(vmrglb, 6, 4);
6667 GEN_VXFORM(vmrglh, 6, 5);
6668 GEN_VXFORM(vmrglw, 6, 6);
6669 GEN_VXFORM(vmuloub, 4, 0);
6670 GEN_VXFORM(vmulouh, 4, 1);
6671 GEN_VXFORM(vmulosb, 4, 4);
6672 GEN_VXFORM(vmulosh, 4, 5);
6673 GEN_VXFORM(vmuleub, 4, 8);
6674 GEN_VXFORM(vmuleuh, 4, 9);
6675 GEN_VXFORM(vmulesb, 4, 12);
6676 GEN_VXFORM(vmulesh, 4, 13);
6677 GEN_VXFORM(vslb, 2, 4);
6678 GEN_VXFORM(vslh, 2, 5);
6679 GEN_VXFORM(vslw, 2, 6);
6680 GEN_VXFORM(vsrb, 2, 8);
6681 GEN_VXFORM(vsrh, 2, 9);
6682 GEN_VXFORM(vsrw, 2, 10);
6683 GEN_VXFORM(vsrab, 2, 12);
6684 GEN_VXFORM(vsrah, 2, 13);
6685 GEN_VXFORM(vsraw, 2, 14);
6686 GEN_VXFORM(vslo, 6, 16);
6687 GEN_VXFORM(vsro, 6, 17);
6688 GEN_VXFORM(vaddcuw, 0, 6);
6689 GEN_VXFORM(vsubcuw, 0, 22);
6690 GEN_VXFORM_ENV(vaddubs, 0, 8);
6691 GEN_VXFORM_ENV(vadduhs, 0, 9);
6692 GEN_VXFORM_ENV(vadduws, 0, 10);
6693 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6694 GEN_VXFORM_ENV(vaddshs, 0, 13);
6695 GEN_VXFORM_ENV(vaddsws, 0, 14);
6696 GEN_VXFORM_ENV(vsububs, 0, 24);
6697 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6698 GEN_VXFORM_ENV(vsubuws, 0, 26);
6699 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6700 GEN_VXFORM_ENV(vsubshs, 0, 29);
6701 GEN_VXFORM_ENV(vsubsws, 0, 30);
6702 GEN_VXFORM(vrlb, 2, 0);
6703 GEN_VXFORM(vrlh, 2, 1);
6704 GEN_VXFORM(vrlw, 2, 2);
6705 GEN_VXFORM(vsl, 2, 7);
6706 GEN_VXFORM(vsr, 2, 11);
6707 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6708 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6709 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6710 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6711 GEN_VXFORM_ENV(vpkshus, 7, 4);
6712 GEN_VXFORM_ENV(vpkswus, 7, 5);
6713 GEN_VXFORM_ENV(vpkshss, 7, 6);
6714 GEN_VXFORM_ENV(vpkswss, 7, 7);
6715 GEN_VXFORM(vpkpx, 7, 12);
6716 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6717 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6718 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6719 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6720 GEN_VXFORM_ENV(vsumsws, 4, 30);
6721 GEN_VXFORM_ENV(vaddfp, 5, 0);
6722 GEN_VXFORM_ENV(vsubfp, 5, 1);
6723 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6724 GEN_VXFORM_ENV(vminfp, 5, 17);
6725
6726 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6727 static void glue(gen_, name)(DisasContext *ctx) \
6728 { \
6729 TCGv_ptr ra, rb, rd; \
6730 if (unlikely(!ctx->altivec_enabled)) { \
6731 gen_exception(ctx, POWERPC_EXCP_VPU); \
6732 return; \
6733 } \
6734 ra = gen_avr_ptr(rA(ctx->opcode)); \
6735 rb = gen_avr_ptr(rB(ctx->opcode)); \
6736 rd = gen_avr_ptr(rD(ctx->opcode)); \
6737 gen_helper_##opname(cpu_env, rd, ra, rb); \
6738 tcg_temp_free_ptr(ra); \
6739 tcg_temp_free_ptr(rb); \
6740 tcg_temp_free_ptr(rd); \
6741 }
6742
6743 #define GEN_VXRFORM(name, opc2, opc3) \
6744 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6745 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6746
6747 GEN_VXRFORM(vcmpequb, 3, 0)
6748 GEN_VXRFORM(vcmpequh, 3, 1)
6749 GEN_VXRFORM(vcmpequw, 3, 2)
6750 GEN_VXRFORM(vcmpgtsb, 3, 12)
6751 GEN_VXRFORM(vcmpgtsh, 3, 13)
6752 GEN_VXRFORM(vcmpgtsw, 3, 14)
6753 GEN_VXRFORM(vcmpgtub, 3, 8)
6754 GEN_VXRFORM(vcmpgtuh, 3, 9)
6755 GEN_VXRFORM(vcmpgtuw, 3, 10)
6756 GEN_VXRFORM(vcmpeqfp, 3, 3)
6757 GEN_VXRFORM(vcmpgefp, 3, 7)
6758 GEN_VXRFORM(vcmpgtfp, 3, 11)
6759 GEN_VXRFORM(vcmpbfp, 3, 15)
6760
6761 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6762 static void glue(gen_, name)(DisasContext *ctx) \
6763 { \
6764 TCGv_ptr rd; \
6765 TCGv_i32 simm; \
6766 if (unlikely(!ctx->altivec_enabled)) { \
6767 gen_exception(ctx, POWERPC_EXCP_VPU); \
6768 return; \
6769 } \
6770 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6771 rd = gen_avr_ptr(rD(ctx->opcode)); \
6772 gen_helper_##name (rd, simm); \
6773 tcg_temp_free_i32(simm); \
6774 tcg_temp_free_ptr(rd); \
6775 }
6776
6777 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6778 GEN_VXFORM_SIMM(vspltish, 6, 13);
6779 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6780
6781 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6782 static void glue(gen_, name)(DisasContext *ctx) \
6783 { \
6784 TCGv_ptr rb, rd; \
6785 if (unlikely(!ctx->altivec_enabled)) { \
6786 gen_exception(ctx, POWERPC_EXCP_VPU); \
6787 return; \
6788 } \
6789 rb = gen_avr_ptr(rB(ctx->opcode)); \
6790 rd = gen_avr_ptr(rD(ctx->opcode)); \
6791 gen_helper_##name (rd, rb); \
6792 tcg_temp_free_ptr(rb); \
6793 tcg_temp_free_ptr(rd); \
6794 }
6795
6796 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6797 static void glue(gen_, name)(DisasContext *ctx) \
6798 { \
6799 TCGv_ptr rb, rd; \
6800 \
6801 if (unlikely(!ctx->altivec_enabled)) { \
6802 gen_exception(ctx, POWERPC_EXCP_VPU); \
6803 return; \
6804 } \
6805 rb = gen_avr_ptr(rB(ctx->opcode)); \
6806 rd = gen_avr_ptr(rD(ctx->opcode)); \
6807 gen_helper_##name(cpu_env, rd, rb); \
6808 tcg_temp_free_ptr(rb); \
6809 tcg_temp_free_ptr(rd); \
6810 }
6811
6812 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6813 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6814 GEN_VXFORM_NOA(vupklsb, 7, 10);
6815 GEN_VXFORM_NOA(vupklsh, 7, 11);
6816 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6817 GEN_VXFORM_NOA(vupklpx, 7, 15);
6818 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6819 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6820 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6821 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6822 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6823 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6824 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6825 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6826
6827 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6828 static void glue(gen_, name)(DisasContext *ctx) \
6829 { \
6830 TCGv_ptr rd; \
6831 TCGv_i32 simm; \
6832 if (unlikely(!ctx->altivec_enabled)) { \
6833 gen_exception(ctx, POWERPC_EXCP_VPU); \
6834 return; \
6835 } \
6836 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6837 rd = gen_avr_ptr(rD(ctx->opcode)); \
6838 gen_helper_##name (rd, simm); \
6839 tcg_temp_free_i32(simm); \
6840 tcg_temp_free_ptr(rd); \
6841 }
6842
6843 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6844 static void glue(gen_, name)(DisasContext *ctx) \
6845 { \
6846 TCGv_ptr rb, rd; \
6847 TCGv_i32 uimm; \
6848 if (unlikely(!ctx->altivec_enabled)) { \
6849 gen_exception(ctx, POWERPC_EXCP_VPU); \
6850 return; \
6851 } \
6852 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6853 rb = gen_avr_ptr(rB(ctx->opcode)); \
6854 rd = gen_avr_ptr(rD(ctx->opcode)); \
6855 gen_helper_##name (rd, rb, uimm); \
6856 tcg_temp_free_i32(uimm); \
6857 tcg_temp_free_ptr(rb); \
6858 tcg_temp_free_ptr(rd); \
6859 }
6860
6861 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6862 static void glue(gen_, name)(DisasContext *ctx) \
6863 { \
6864 TCGv_ptr rb, rd; \
6865 TCGv_i32 uimm; \
6866 \
6867 if (unlikely(!ctx->altivec_enabled)) { \
6868 gen_exception(ctx, POWERPC_EXCP_VPU); \
6869 return; \
6870 } \
6871 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6872 rb = gen_avr_ptr(rB(ctx->opcode)); \
6873 rd = gen_avr_ptr(rD(ctx->opcode)); \
6874 gen_helper_##name(cpu_env, rd, rb, uimm); \
6875 tcg_temp_free_i32(uimm); \
6876 tcg_temp_free_ptr(rb); \
6877 tcg_temp_free_ptr(rd); \
6878 }
6879
6880 GEN_VXFORM_UIMM(vspltb, 6, 8);
6881 GEN_VXFORM_UIMM(vsplth, 6, 9);
6882 GEN_VXFORM_UIMM(vspltw, 6, 10);
6883 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6884 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6885 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6886 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6887
6888 static void gen_vsldoi(DisasContext *ctx)
6889 {
6890 TCGv_ptr ra, rb, rd;
6891 TCGv_i32 sh;
6892 if (unlikely(!ctx->altivec_enabled)) {
6893 gen_exception(ctx, POWERPC_EXCP_VPU);
6894 return;
6895 }
6896 ra = gen_avr_ptr(rA(ctx->opcode));
6897 rb = gen_avr_ptr(rB(ctx->opcode));
6898 rd = gen_avr_ptr(rD(ctx->opcode));
6899 sh = tcg_const_i32(VSH(ctx->opcode));
6900 gen_helper_vsldoi (rd, ra, rb, sh);
6901 tcg_temp_free_ptr(ra);
6902 tcg_temp_free_ptr(rb);
6903 tcg_temp_free_ptr(rd);
6904 tcg_temp_free_i32(sh);
6905 }
6906
6907 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6908 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6909 { \
6910 TCGv_ptr ra, rb, rc, rd; \
6911 if (unlikely(!ctx->altivec_enabled)) { \
6912 gen_exception(ctx, POWERPC_EXCP_VPU); \
6913 return; \
6914 } \
6915 ra = gen_avr_ptr(rA(ctx->opcode)); \
6916 rb = gen_avr_ptr(rB(ctx->opcode)); \
6917 rc = gen_avr_ptr(rC(ctx->opcode)); \
6918 rd = gen_avr_ptr(rD(ctx->opcode)); \
6919 if (Rc(ctx->opcode)) { \
6920 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6921 } else { \
6922 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6923 } \
6924 tcg_temp_free_ptr(ra); \
6925 tcg_temp_free_ptr(rb); \
6926 tcg_temp_free_ptr(rc); \
6927 tcg_temp_free_ptr(rd); \
6928 }
6929
6930 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6931
6932 static void gen_vmladduhm(DisasContext *ctx)
6933 {
6934 TCGv_ptr ra, rb, rc, rd;
6935 if (unlikely(!ctx->altivec_enabled)) {
6936 gen_exception(ctx, POWERPC_EXCP_VPU);
6937 return;
6938 }
6939 ra = gen_avr_ptr(rA(ctx->opcode));
6940 rb = gen_avr_ptr(rB(ctx->opcode));
6941 rc = gen_avr_ptr(rC(ctx->opcode));
6942 rd = gen_avr_ptr(rD(ctx->opcode));
6943 gen_helper_vmladduhm(rd, ra, rb, rc);
6944 tcg_temp_free_ptr(ra);
6945 tcg_temp_free_ptr(rb);
6946 tcg_temp_free_ptr(rc);
6947 tcg_temp_free_ptr(rd);
6948 }
6949
6950 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6951 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6952 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6953 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6954 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6955
6956 /*** SPE extension ***/
6957 /* Register moves */
6958
6959
6960 static inline void gen_evmra(DisasContext *ctx)
6961 {
6962
6963 if (unlikely(!ctx->spe_enabled)) {
6964 gen_exception(ctx, POWERPC_EXCP_SPEU);
6965 return;
6966 }
6967
6968 #if defined(TARGET_PPC64)
6969 /* rD := rA */
6970 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6971
6972 /* spe_acc := rA */
6973 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6974 cpu_env,
6975 offsetof(CPUPPCState, spe_acc));
6976 #else
6977 TCGv_i64 tmp = tcg_temp_new_i64();
6978
6979 /* tmp := rA_lo + rA_hi << 32 */
6980 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6981
6982 /* spe_acc := tmp */
6983 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6984 tcg_temp_free_i64(tmp);
6985
6986 /* rD := rA */
6987 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6988 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6989 #endif
6990 }
6991
6992 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6993 {
6994 #if defined(TARGET_PPC64)
6995 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6996 #else
6997 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6998 #endif
6999 }
7000
7001 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
7002 {
7003 #if defined(TARGET_PPC64)
7004 tcg_gen_mov_i64(cpu_gpr[reg], t);
7005 #else
7006 TCGv_i64 tmp = tcg_temp_new_i64();
7007 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
7008 tcg_gen_shri_i64(tmp, t, 32);
7009 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
7010 tcg_temp_free_i64(tmp);
7011 #endif
7012 }
7013
7014 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
7015 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7016 { \
7017 if (Rc(ctx->opcode)) \
7018 gen_##name1(ctx); \
7019 else \
7020 gen_##name0(ctx); \
7021 }
7022
7023 /* Handler for undefined SPE opcodes */
7024 static inline void gen_speundef(DisasContext *ctx)
7025 {
7026 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7027 }
7028
7029 /* SPE logic */
7030 #if defined(TARGET_PPC64)
7031 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7032 static inline void gen_##name(DisasContext *ctx) \
7033 { \
7034 if (unlikely(!ctx->spe_enabled)) { \
7035 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7036 return; \
7037 } \
7038 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7039 cpu_gpr[rB(ctx->opcode)]); \
7040 }
7041 #else
7042 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7043 static inline void gen_##name(DisasContext *ctx) \
7044 { \
7045 if (unlikely(!ctx->spe_enabled)) { \
7046 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7047 return; \
7048 } \
7049 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7050 cpu_gpr[rB(ctx->opcode)]); \
7051 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7052 cpu_gprh[rB(ctx->opcode)]); \
7053 }
7054 #endif
7055
7056 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
7057 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
7058 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
7059 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
7060 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
7061 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
7062 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
7063 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
7064
7065 /* SPE logic immediate */
7066 #if defined(TARGET_PPC64)
7067 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7068 static inline void gen_##name(DisasContext *ctx) \
7069 { \
7070 if (unlikely(!ctx->spe_enabled)) { \
7071 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7072 return; \
7073 } \
7074 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7075 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7076 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7077 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7078 tcg_opi(t0, t0, rB(ctx->opcode)); \
7079 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7080 tcg_gen_trunc_i64_i32(t1, t2); \
7081 tcg_temp_free_i64(t2); \
7082 tcg_opi(t1, t1, rB(ctx->opcode)); \
7083 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7084 tcg_temp_free_i32(t0); \
7085 tcg_temp_free_i32(t1); \
7086 }
7087 #else
7088 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7089 static inline void gen_##name(DisasContext *ctx) \
7090 { \
7091 if (unlikely(!ctx->spe_enabled)) { \
7092 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7093 return; \
7094 } \
7095 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7096 rB(ctx->opcode)); \
7097 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7098 rB(ctx->opcode)); \
7099 }
7100 #endif
7101 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
7102 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
7103 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
7104 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
7105
7106 /* SPE arithmetic */
7107 #if defined(TARGET_PPC64)
7108 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7109 static inline void gen_##name(DisasContext *ctx) \
7110 { \
7111 if (unlikely(!ctx->spe_enabled)) { \
7112 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7113 return; \
7114 } \
7115 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7116 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7117 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7118 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7119 tcg_op(t0, t0); \
7120 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7121 tcg_gen_trunc_i64_i32(t1, t2); \
7122 tcg_temp_free_i64(t2); \
7123 tcg_op(t1, t1); \
7124 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7125 tcg_temp_free_i32(t0); \
7126 tcg_temp_free_i32(t1); \
7127 }
7128 #else
7129 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7130 static inline void gen_##name(DisasContext *ctx) \
7131 { \
7132 if (unlikely(!ctx->spe_enabled)) { \
7133 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7134 return; \
7135 } \
7136 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7137 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7138 }
7139 #endif
7140
7141 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
7142 {
7143 int l1 = gen_new_label();
7144 int l2 = gen_new_label();
7145
7146 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
7147 tcg_gen_neg_i32(ret, arg1);
7148 tcg_gen_br(l2);
7149 gen_set_label(l1);
7150 tcg_gen_mov_i32(ret, arg1);
7151 gen_set_label(l2);
7152 }
7153 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7154 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7155 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7156 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7157 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7158 {
7159 tcg_gen_addi_i32(ret, arg1, 0x8000);
7160 tcg_gen_ext16u_i32(ret, ret);
7161 }
7162 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7163 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7164 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7165
7166 #if defined(TARGET_PPC64)
7167 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7168 static inline void gen_##name(DisasContext *ctx) \
7169 { \
7170 if (unlikely(!ctx->spe_enabled)) { \
7171 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7172 return; \
7173 } \
7174 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7175 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7176 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7177 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7178 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7179 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7180 tcg_op(t0, t0, t2); \
7181 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7182 tcg_gen_trunc_i64_i32(t1, t3); \
7183 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7184 tcg_gen_trunc_i64_i32(t2, t3); \
7185 tcg_temp_free_i64(t3); \
7186 tcg_op(t1, t1, t2); \
7187 tcg_temp_free_i32(t2); \
7188 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7189 tcg_temp_free_i32(t0); \
7190 tcg_temp_free_i32(t1); \
7191 }
7192 #else
7193 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7194 static inline void gen_##name(DisasContext *ctx) \
7195 { \
7196 if (unlikely(!ctx->spe_enabled)) { \
7197 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7198 return; \
7199 } \
7200 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7201 cpu_gpr[rB(ctx->opcode)]); \
7202 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7203 cpu_gprh[rB(ctx->opcode)]); \
7204 }
7205 #endif
7206
7207 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7208 {
7209 TCGv_i32 t0;
7210 int l1, l2;
7211
7212 l1 = gen_new_label();
7213 l2 = gen_new_label();
7214 t0 = tcg_temp_local_new_i32();
7215 /* No error here: 6 bits are used */
7216 tcg_gen_andi_i32(t0, arg2, 0x3F);
7217 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7218 tcg_gen_shr_i32(ret, arg1, t0);
7219 tcg_gen_br(l2);
7220 gen_set_label(l1);
7221 tcg_gen_movi_i32(ret, 0);
7222 gen_set_label(l2);
7223 tcg_temp_free_i32(t0);
7224 }
7225 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7226 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7227 {
7228 TCGv_i32 t0;
7229 int l1, l2;
7230
7231 l1 = gen_new_label();
7232 l2 = gen_new_label();
7233 t0 = tcg_temp_local_new_i32();
7234 /* No error here: 6 bits are used */
7235 tcg_gen_andi_i32(t0, arg2, 0x3F);
7236 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7237 tcg_gen_sar_i32(ret, arg1, t0);
7238 tcg_gen_br(l2);
7239 gen_set_label(l1);
7240 tcg_gen_movi_i32(ret, 0);
7241 gen_set_label(l2);
7242 tcg_temp_free_i32(t0);
7243 }
7244 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7245 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7246 {
7247 TCGv_i32 t0;
7248 int l1, l2;
7249
7250 l1 = gen_new_label();
7251 l2 = gen_new_label();
7252 t0 = tcg_temp_local_new_i32();
7253 /* No error here: 6 bits are used */
7254 tcg_gen_andi_i32(t0, arg2, 0x3F);
7255 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7256 tcg_gen_shl_i32(ret, arg1, t0);
7257 tcg_gen_br(l2);
7258 gen_set_label(l1);
7259 tcg_gen_movi_i32(ret, 0);
7260 gen_set_label(l2);
7261 tcg_temp_free_i32(t0);
7262 }
7263 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7264 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7265 {
7266 TCGv_i32 t0 = tcg_temp_new_i32();
7267 tcg_gen_andi_i32(t0, arg2, 0x1F);
7268 tcg_gen_rotl_i32(ret, arg1, t0);
7269 tcg_temp_free_i32(t0);
7270 }
7271 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7272 static inline void gen_evmergehi(DisasContext *ctx)
7273 {
7274 if (unlikely(!ctx->spe_enabled)) {
7275 gen_exception(ctx, POWERPC_EXCP_SPEU);
7276 return;
7277 }
7278 #if defined(TARGET_PPC64)
7279 TCGv t0 = tcg_temp_new();
7280 TCGv t1 = tcg_temp_new();
7281 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7282 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7283 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7284 tcg_temp_free(t0);
7285 tcg_temp_free(t1);
7286 #else
7287 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7288 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7289 #endif
7290 }
7291 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7292 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7293 {
7294 tcg_gen_sub_i32(ret, arg2, arg1);
7295 }
7296 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7297
7298 /* SPE arithmetic immediate */
7299 #if defined(TARGET_PPC64)
7300 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7301 static inline void gen_##name(DisasContext *ctx) \
7302 { \
7303 if (unlikely(!ctx->spe_enabled)) { \
7304 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7305 return; \
7306 } \
7307 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7308 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7309 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7310 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7311 tcg_op(t0, t0, rA(ctx->opcode)); \
7312 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7313 tcg_gen_trunc_i64_i32(t1, t2); \
7314 tcg_temp_free_i64(t2); \
7315 tcg_op(t1, t1, rA(ctx->opcode)); \
7316 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7317 tcg_temp_free_i32(t0); \
7318 tcg_temp_free_i32(t1); \
7319 }
7320 #else
7321 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7322 static inline void gen_##name(DisasContext *ctx) \
7323 { \
7324 if (unlikely(!ctx->spe_enabled)) { \
7325 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7326 return; \
7327 } \
7328 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7329 rA(ctx->opcode)); \
7330 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7331 rA(ctx->opcode)); \
7332 }
7333 #endif
7334 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7335 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7336
7337 /* SPE comparison */
7338 #if defined(TARGET_PPC64)
7339 #define GEN_SPEOP_COMP(name, tcg_cond) \
7340 static inline void gen_##name(DisasContext *ctx) \
7341 { \
7342 if (unlikely(!ctx->spe_enabled)) { \
7343 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7344 return; \
7345 } \
7346 int l1 = gen_new_label(); \
7347 int l2 = gen_new_label(); \
7348 int l3 = gen_new_label(); \
7349 int l4 = gen_new_label(); \
7350 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7351 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7352 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7353 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7354 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7355 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7356 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7357 tcg_gen_br(l2); \
7358 gen_set_label(l1); \
7359 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7360 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7361 gen_set_label(l2); \
7362 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7363 tcg_gen_trunc_i64_i32(t0, t2); \
7364 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7365 tcg_gen_trunc_i64_i32(t1, t2); \
7366 tcg_temp_free_i64(t2); \
7367 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7368 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7369 ~(CRF_CH | CRF_CH_AND_CL)); \
7370 tcg_gen_br(l4); \
7371 gen_set_label(l3); \
7372 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7373 CRF_CH | CRF_CH_OR_CL); \
7374 gen_set_label(l4); \
7375 tcg_temp_free_i32(t0); \
7376 tcg_temp_free_i32(t1); \
7377 }
7378 #else
7379 #define GEN_SPEOP_COMP(name, tcg_cond) \
7380 static inline void gen_##name(DisasContext *ctx) \
7381 { \
7382 if (unlikely(!ctx->spe_enabled)) { \
7383 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7384 return; \
7385 } \
7386 int l1 = gen_new_label(); \
7387 int l2 = gen_new_label(); \
7388 int l3 = gen_new_label(); \
7389 int l4 = gen_new_label(); \
7390 \
7391 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7392 cpu_gpr[rB(ctx->opcode)], l1); \
7393 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7394 tcg_gen_br(l2); \
7395 gen_set_label(l1); \
7396 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7397 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7398 gen_set_label(l2); \
7399 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7400 cpu_gprh[rB(ctx->opcode)], l3); \
7401 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7402 ~(CRF_CH | CRF_CH_AND_CL)); \
7403 tcg_gen_br(l4); \
7404 gen_set_label(l3); \
7405 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7406 CRF_CH | CRF_CH_OR_CL); \
7407 gen_set_label(l4); \
7408 }
7409 #endif
7410 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7411 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7412 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7413 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7414 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7415
7416 /* SPE misc */
7417 static inline void gen_brinc(DisasContext *ctx)
7418 {
7419 /* Note: brinc is usable even if SPE is disabled */
7420 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7421 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7422 }
7423 static inline void gen_evmergelo(DisasContext *ctx)
7424 {
7425 if (unlikely(!ctx->spe_enabled)) {
7426 gen_exception(ctx, POWERPC_EXCP_SPEU);
7427 return;
7428 }
7429 #if defined(TARGET_PPC64)
7430 TCGv t0 = tcg_temp_new();
7431 TCGv t1 = tcg_temp_new();
7432 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7433 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7434 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7435 tcg_temp_free(t0);
7436 tcg_temp_free(t1);
7437 #else
7438 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7439 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7440 #endif
7441 }
7442 static inline void gen_evmergehilo(DisasContext *ctx)
7443 {
7444 if (unlikely(!ctx->spe_enabled)) {
7445 gen_exception(ctx, POWERPC_EXCP_SPEU);
7446 return;
7447 }
7448 #if defined(TARGET_PPC64)
7449 TCGv t0 = tcg_temp_new();
7450 TCGv t1 = tcg_temp_new();
7451 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7452 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7453 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7454 tcg_temp_free(t0);
7455 tcg_temp_free(t1);
7456 #else
7457 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7458 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7459 #endif
7460 }
7461 static inline void gen_evmergelohi(DisasContext *ctx)
7462 {
7463 if (unlikely(!ctx->spe_enabled)) {
7464 gen_exception(ctx, POWERPC_EXCP_SPEU);
7465 return;
7466 }
7467 #if defined(TARGET_PPC64)
7468 TCGv t0 = tcg_temp_new();
7469 TCGv t1 = tcg_temp_new();
7470 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7471 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7472 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7473 tcg_temp_free(t0);
7474 tcg_temp_free(t1);
7475 #else
7476 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7477 TCGv_i32 tmp = tcg_temp_new_i32();
7478 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7479 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7480 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7481 tcg_temp_free_i32(tmp);
7482 } else {
7483 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7484 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7485 }
7486 #endif
7487 }
7488 static inline void gen_evsplati(DisasContext *ctx)
7489 {
7490 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7491
7492 #if defined(TARGET_PPC64)
7493 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7494 #else
7495 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7496 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7497 #endif
7498 }
7499 static inline void gen_evsplatfi(DisasContext *ctx)
7500 {
7501 uint64_t imm = rA(ctx->opcode) << 27;
7502
7503 #if defined(TARGET_PPC64)
7504 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7505 #else
7506 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7507 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7508 #endif
7509 }
7510
7511 static inline void gen_evsel(DisasContext *ctx)
7512 {
7513 int l1 = gen_new_label();
7514 int l2 = gen_new_label();
7515 int l3 = gen_new_label();
7516 int l4 = gen_new_label();
7517 TCGv_i32 t0 = tcg_temp_local_new_i32();
7518 #if defined(TARGET_PPC64)
7519 TCGv t1 = tcg_temp_local_new();
7520 TCGv t2 = tcg_temp_local_new();
7521 #endif
7522 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7523 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7524 #if defined(TARGET_PPC64)
7525 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7526 #else
7527 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7528 #endif
7529 tcg_gen_br(l2);
7530 gen_set_label(l1);
7531 #if defined(TARGET_PPC64)
7532 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7533 #else
7534 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7535 #endif
7536 gen_set_label(l2);
7537 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7538 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7539 #if defined(TARGET_PPC64)
7540 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7541 #else
7542 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7543 #endif
7544 tcg_gen_br(l4);
7545 gen_set_label(l3);
7546 #if defined(TARGET_PPC64)
7547 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7548 #else
7549 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7550 #endif
7551 gen_set_label(l4);
7552 tcg_temp_free_i32(t0);
7553 #if defined(TARGET_PPC64)
7554 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7555 tcg_temp_free(t1);
7556 tcg_temp_free(t2);
7557 #endif
7558 }
7559
7560 static void gen_evsel0(DisasContext *ctx)
7561 {
7562 gen_evsel(ctx);
7563 }
7564
7565 static void gen_evsel1(DisasContext *ctx)
7566 {
7567 gen_evsel(ctx);
7568 }
7569
7570 static void gen_evsel2(DisasContext *ctx)
7571 {
7572 gen_evsel(ctx);
7573 }
7574
7575 static void gen_evsel3(DisasContext *ctx)
7576 {
7577 gen_evsel(ctx);
7578 }
7579
7580 /* Multiply */
7581
7582 static inline void gen_evmwumi(DisasContext *ctx)
7583 {
7584 TCGv_i64 t0, t1;
7585
7586 if (unlikely(!ctx->spe_enabled)) {
7587 gen_exception(ctx, POWERPC_EXCP_SPEU);
7588 return;
7589 }
7590
7591 t0 = tcg_temp_new_i64();
7592 t1 = tcg_temp_new_i64();
7593
7594 /* t0 := rA; t1 := rB */
7595 #if defined(TARGET_PPC64)
7596 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7597 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7598 #else
7599 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7600 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7601 #endif
7602
7603 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7604
7605 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7606
7607 tcg_temp_free_i64(t0);
7608 tcg_temp_free_i64(t1);
7609 }
7610
7611 static inline void gen_evmwumia(DisasContext *ctx)
7612 {
7613 TCGv_i64 tmp;
7614
7615 if (unlikely(!ctx->spe_enabled)) {
7616 gen_exception(ctx, POWERPC_EXCP_SPEU);
7617 return;
7618 }
7619
7620 gen_evmwumi(ctx); /* rD := rA * rB */
7621
7622 tmp = tcg_temp_new_i64();
7623
7624 /* acc := rD */
7625 gen_load_gpr64(tmp, rD(ctx->opcode));
7626 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7627 tcg_temp_free_i64(tmp);
7628 }
7629
7630 static inline void gen_evmwumiaa(DisasContext *ctx)
7631 {
7632 TCGv_i64 acc;
7633 TCGv_i64 tmp;
7634
7635 if (unlikely(!ctx->spe_enabled)) {
7636 gen_exception(ctx, POWERPC_EXCP_SPEU);
7637 return;
7638 }
7639
7640 gen_evmwumi(ctx); /* rD := rA * rB */
7641
7642 acc = tcg_temp_new_i64();
7643 tmp = tcg_temp_new_i64();
7644
7645 /* tmp := rD */
7646 gen_load_gpr64(tmp, rD(ctx->opcode));
7647
7648 /* Load acc */
7649 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7650
7651 /* acc := tmp + acc */
7652 tcg_gen_add_i64(acc, acc, tmp);
7653
7654 /* Store acc */
7655 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7656
7657 /* rD := acc */
7658 gen_store_gpr64(rD(ctx->opcode), acc);
7659
7660 tcg_temp_free_i64(acc);
7661 tcg_temp_free_i64(tmp);
7662 }
7663
7664 static inline void gen_evmwsmi(DisasContext *ctx)
7665 {
7666 TCGv_i64 t0, t1;
7667
7668 if (unlikely(!ctx->spe_enabled)) {
7669 gen_exception(ctx, POWERPC_EXCP_SPEU);
7670 return;
7671 }
7672
7673 t0 = tcg_temp_new_i64();
7674 t1 = tcg_temp_new_i64();
7675
7676 /* t0 := rA; t1 := rB */
7677 #if defined(TARGET_PPC64)
7678 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7679 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7680 #else
7681 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7682 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7683 #endif
7684
7685 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7686
7687 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7688
7689 tcg_temp_free_i64(t0);
7690 tcg_temp_free_i64(t1);
7691 }
7692
7693 static inline void gen_evmwsmia(DisasContext *ctx)
7694 {
7695 TCGv_i64 tmp;
7696
7697 gen_evmwsmi(ctx); /* rD := rA * rB */
7698
7699 tmp = tcg_temp_new_i64();
7700
7701 /* acc := rD */
7702 gen_load_gpr64(tmp, rD(ctx->opcode));
7703 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7704
7705 tcg_temp_free_i64(tmp);
7706 }
7707
7708 static inline void gen_evmwsmiaa(DisasContext *ctx)
7709 {
7710 TCGv_i64 acc = tcg_temp_new_i64();
7711 TCGv_i64 tmp = tcg_temp_new_i64();
7712
7713 gen_evmwsmi(ctx); /* rD := rA * rB */
7714
7715 acc = tcg_temp_new_i64();
7716 tmp = tcg_temp_new_i64();
7717
7718 /* tmp := rD */
7719 gen_load_gpr64(tmp, rD(ctx->opcode));
7720
7721 /* Load acc */
7722 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7723
7724 /* acc := tmp + acc */
7725 tcg_gen_add_i64(acc, acc, tmp);
7726
7727 /* Store acc */
7728 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7729
7730 /* rD := acc */
7731 gen_store_gpr64(rD(ctx->opcode), acc);
7732
7733 tcg_temp_free_i64(acc);
7734 tcg_temp_free_i64(tmp);
7735 }
7736
7737 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7738 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7739 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7740 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7741 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7742 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7743 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7744 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7745 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7746 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7747 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7748 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7749 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7750 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7751 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7752 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7753 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7754 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7755 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7756 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7757 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7758 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7759 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7760 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7761 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7762 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7763 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7764 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7765 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7766
7767 /* SPE load and stores */
7768 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7769 {
7770 target_ulong uimm = rB(ctx->opcode);
7771
7772 if (rA(ctx->opcode) == 0) {
7773 tcg_gen_movi_tl(EA, uimm << sh);
7774 } else {
7775 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7776 if (NARROW_MODE(ctx)) {
7777 tcg_gen_ext32u_tl(EA, EA);
7778 }
7779 }
7780 }
7781
7782 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7783 {
7784 #if defined(TARGET_PPC64)
7785 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7786 #else
7787 TCGv_i64 t0 = tcg_temp_new_i64();
7788 gen_qemu_ld64(ctx, t0, addr);
7789 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7790 tcg_gen_shri_i64(t0, t0, 32);
7791 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7792 tcg_temp_free_i64(t0);
7793 #endif
7794 }
7795
7796 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7797 {
7798 #if defined(TARGET_PPC64)
7799 TCGv t0 = tcg_temp_new();
7800 gen_qemu_ld32u(ctx, t0, addr);
7801 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7802 gen_addr_add(ctx, addr, addr, 4);
7803 gen_qemu_ld32u(ctx, t0, addr);
7804 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7805 tcg_temp_free(t0);
7806 #else
7807 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7808 gen_addr_add(ctx, addr, addr, 4);
7809 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7810 #endif
7811 }
7812
7813 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7814 {
7815 TCGv t0 = tcg_temp_new();
7816 #if defined(TARGET_PPC64)
7817 gen_qemu_ld16u(ctx, t0, addr);
7818 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7819 gen_addr_add(ctx, addr, addr, 2);
7820 gen_qemu_ld16u(ctx, t0, addr);
7821 tcg_gen_shli_tl(t0, t0, 32);
7822 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7823 gen_addr_add(ctx, addr, addr, 2);
7824 gen_qemu_ld16u(ctx, t0, addr);
7825 tcg_gen_shli_tl(t0, t0, 16);
7826 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7827 gen_addr_add(ctx, addr, addr, 2);
7828 gen_qemu_ld16u(ctx, t0, addr);
7829 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7830 #else
7831 gen_qemu_ld16u(ctx, t0, addr);
7832 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7833 gen_addr_add(ctx, addr, addr, 2);
7834 gen_qemu_ld16u(ctx, t0, addr);
7835 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7836 gen_addr_add(ctx, addr, addr, 2);
7837 gen_qemu_ld16u(ctx, t0, addr);
7838 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7839 gen_addr_add(ctx, addr, addr, 2);
7840 gen_qemu_ld16u(ctx, t0, addr);
7841 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7842 #endif
7843 tcg_temp_free(t0);
7844 }
7845
7846 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7847 {
7848 TCGv t0 = tcg_temp_new();
7849 gen_qemu_ld16u(ctx, t0, addr);
7850 #if defined(TARGET_PPC64)
7851 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7852 tcg_gen_shli_tl(t0, t0, 16);
7853 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7854 #else
7855 tcg_gen_shli_tl(t0, t0, 16);
7856 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7857 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7858 #endif
7859 tcg_temp_free(t0);
7860 }
7861
7862 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7863 {
7864 TCGv t0 = tcg_temp_new();
7865 gen_qemu_ld16u(ctx, t0, addr);
7866 #if defined(TARGET_PPC64)
7867 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7868 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7869 #else
7870 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7871 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7872 #endif
7873 tcg_temp_free(t0);
7874 }
7875
7876 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7877 {
7878 TCGv t0 = tcg_temp_new();
7879 gen_qemu_ld16s(ctx, t0, addr);
7880 #if defined(TARGET_PPC64)
7881 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7882 tcg_gen_ext32u_tl(t0, t0);
7883 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7884 #else
7885 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7886 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7887 #endif
7888 tcg_temp_free(t0);
7889 }
7890
7891 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7892 {
7893 TCGv t0 = tcg_temp_new();
7894 #if defined(TARGET_PPC64)
7895 gen_qemu_ld16u(ctx, t0, addr);
7896 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7897 gen_addr_add(ctx, addr, addr, 2);
7898 gen_qemu_ld16u(ctx, t0, addr);
7899 tcg_gen_shli_tl(t0, t0, 16);
7900 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7901 #else
7902 gen_qemu_ld16u(ctx, t0, addr);
7903 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7904 gen_addr_add(ctx, addr, addr, 2);
7905 gen_qemu_ld16u(ctx, t0, addr);
7906 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7907 #endif
7908 tcg_temp_free(t0);
7909 }
7910
7911 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7912 {
7913 #if defined(TARGET_PPC64)
7914 TCGv t0 = tcg_temp_new();
7915 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7916 gen_addr_add(ctx, addr, addr, 2);
7917 gen_qemu_ld16u(ctx, t0, addr);
7918 tcg_gen_shli_tl(t0, t0, 32);
7919 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7920 tcg_temp_free(t0);
7921 #else
7922 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7923 gen_addr_add(ctx, addr, addr, 2);
7924 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7925 #endif
7926 }
7927
7928 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7929 {
7930 #if defined(TARGET_PPC64)
7931 TCGv t0 = tcg_temp_new();
7932 gen_qemu_ld16s(ctx, t0, addr);
7933 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7934 gen_addr_add(ctx, addr, addr, 2);
7935 gen_qemu_ld16s(ctx, t0, addr);
7936 tcg_gen_shli_tl(t0, t0, 32);
7937 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7938 tcg_temp_free(t0);
7939 #else
7940 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7941 gen_addr_add(ctx, addr, addr, 2);
7942 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7943 #endif
7944 }
7945
7946 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7947 {
7948 TCGv t0 = tcg_temp_new();
7949 gen_qemu_ld32u(ctx, t0, addr);
7950 #if defined(TARGET_PPC64)
7951 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7952 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7953 #else
7954 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7955 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7956 #endif
7957 tcg_temp_free(t0);
7958 }
7959
7960 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7961 {
7962 TCGv t0 = tcg_temp_new();
7963 #if defined(TARGET_PPC64)
7964 gen_qemu_ld16u(ctx, t0, addr);
7965 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7966 tcg_gen_shli_tl(t0, t0, 32);
7967 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7968 gen_addr_add(ctx, addr, addr, 2);
7969 gen_qemu_ld16u(ctx, t0, addr);
7970 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7971 tcg_gen_shli_tl(t0, t0, 16);
7972 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7973 #else
7974 gen_qemu_ld16u(ctx, t0, addr);
7975 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7976 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7977 gen_addr_add(ctx, addr, addr, 2);
7978 gen_qemu_ld16u(ctx, t0, addr);
7979 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7980 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7981 #endif
7982 tcg_temp_free(t0);
7983 }
7984
7985 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7986 {
7987 #if defined(TARGET_PPC64)
7988 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7989 #else
7990 TCGv_i64 t0 = tcg_temp_new_i64();
7991 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7992 gen_qemu_st64(ctx, t0, addr);
7993 tcg_temp_free_i64(t0);
7994 #endif
7995 }
7996
7997 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7998 {
7999 #if defined(TARGET_PPC64)
8000 TCGv t0 = tcg_temp_new();
8001 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8002 gen_qemu_st32(ctx, t0, addr);
8003 tcg_temp_free(t0);
8004 #else
8005 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8006 #endif
8007 gen_addr_add(ctx, addr, addr, 4);
8008 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8009 }
8010
8011 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
8012 {
8013 TCGv t0 = tcg_temp_new();
8014 #if defined(TARGET_PPC64)
8015 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8016 #else
8017 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8018 #endif
8019 gen_qemu_st16(ctx, t0, addr);
8020 gen_addr_add(ctx, addr, addr, 2);
8021 #if defined(TARGET_PPC64)
8022 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8023 gen_qemu_st16(ctx, t0, addr);
8024 #else
8025 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8026 #endif
8027 gen_addr_add(ctx, addr, addr, 2);
8028 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8029 gen_qemu_st16(ctx, t0, addr);
8030 tcg_temp_free(t0);
8031 gen_addr_add(ctx, addr, addr, 2);
8032 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8033 }
8034
8035 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
8036 {
8037 TCGv t0 = tcg_temp_new();
8038 #if defined(TARGET_PPC64)
8039 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8040 #else
8041 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8042 #endif
8043 gen_qemu_st16(ctx, t0, addr);
8044 gen_addr_add(ctx, addr, addr, 2);
8045 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8046 gen_qemu_st16(ctx, t0, addr);
8047 tcg_temp_free(t0);
8048 }
8049
8050 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
8051 {
8052 #if defined(TARGET_PPC64)
8053 TCGv t0 = tcg_temp_new();
8054 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8055 gen_qemu_st16(ctx, t0, addr);
8056 tcg_temp_free(t0);
8057 #else
8058 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8059 #endif
8060 gen_addr_add(ctx, addr, addr, 2);
8061 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8062 }
8063
8064 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
8065 {
8066 #if defined(TARGET_PPC64)
8067 TCGv t0 = tcg_temp_new();
8068 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8069 gen_qemu_st32(ctx, t0, addr);
8070 tcg_temp_free(t0);
8071 #else
8072 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8073 #endif
8074 }
8075
8076 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
8077 {
8078 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8079 }
8080
8081 #define GEN_SPEOP_LDST(name, opc2, sh) \
8082 static void glue(gen_, name)(DisasContext *ctx) \
8083 { \
8084 TCGv t0; \
8085 if (unlikely(!ctx->spe_enabled)) { \
8086 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8087 return; \
8088 } \
8089 gen_set_access_type(ctx, ACCESS_INT); \
8090 t0 = tcg_temp_new(); \
8091 if (Rc(ctx->opcode)) { \
8092 gen_addr_spe_imm_index(ctx, t0, sh); \
8093 } else { \
8094 gen_addr_reg_index(ctx, t0); \
8095 } \
8096 gen_op_##name(ctx, t0); \
8097 tcg_temp_free(t0); \
8098 }
8099
8100 GEN_SPEOP_LDST(evldd, 0x00, 3);
8101 GEN_SPEOP_LDST(evldw, 0x01, 3);
8102 GEN_SPEOP_LDST(evldh, 0x02, 3);
8103 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
8104 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
8105 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
8106 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
8107 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
8108 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
8109 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
8110 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
8111
8112 GEN_SPEOP_LDST(evstdd, 0x10, 3);
8113 GEN_SPEOP_LDST(evstdw, 0x11, 3);
8114 GEN_SPEOP_LDST(evstdh, 0x12, 3);
8115 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
8116 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
8117 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
8118 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
8119
8120 /* Multiply and add - TODO */
8121 #if 0
8122 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
8123 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8124 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8125 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8126 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8127 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8128 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8129 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8130 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8131 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8132 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8133 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8134
8135 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8136 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8137 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8138 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8139 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8140 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8141 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8142 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8143 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8144 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8145 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8146 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8147
8148 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8149 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8150 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8151 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8152 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8153
8154 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8155 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8156 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8157 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8158 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8159 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8160 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8161 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8162 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8163 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8164 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8165 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8166
8167 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8168 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8169 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8170 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8171
8172 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8173 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8174 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8175 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8176 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8177 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8178 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8179 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8180 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8181 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8182 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8183 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8184
8185 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8186 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8187 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8188 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8189 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8190 #endif
8191
8192 /*** SPE floating-point extension ***/
8193 #if defined(TARGET_PPC64)
8194 #define GEN_SPEFPUOP_CONV_32_32(name) \
8195 static inline void gen_##name(DisasContext *ctx) \
8196 { \
8197 TCGv_i32 t0; \
8198 TCGv t1; \
8199 t0 = tcg_temp_new_i32(); \
8200 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8201 gen_helper_##name(t0, cpu_env, t0); \
8202 t1 = tcg_temp_new(); \
8203 tcg_gen_extu_i32_tl(t1, t0); \
8204 tcg_temp_free_i32(t0); \
8205 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8206 0xFFFFFFFF00000000ULL); \
8207 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8208 tcg_temp_free(t1); \
8209 }
8210 #define GEN_SPEFPUOP_CONV_32_64(name) \
8211 static inline void gen_##name(DisasContext *ctx) \
8212 { \
8213 TCGv_i32 t0; \
8214 TCGv t1; \
8215 t0 = tcg_temp_new_i32(); \
8216 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8217 t1 = tcg_temp_new(); \
8218 tcg_gen_extu_i32_tl(t1, t0); \
8219 tcg_temp_free_i32(t0); \
8220 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8221 0xFFFFFFFF00000000ULL); \
8222 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8223 tcg_temp_free(t1); \
8224 }
8225 #define GEN_SPEFPUOP_CONV_64_32(name) \
8226 static inline void gen_##name(DisasContext *ctx) \
8227 { \
8228 TCGv_i32 t0 = tcg_temp_new_i32(); \
8229 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8230 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8231 tcg_temp_free_i32(t0); \
8232 }
8233 #define GEN_SPEFPUOP_CONV_64_64(name) \
8234 static inline void gen_##name(DisasContext *ctx) \
8235 { \
8236 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8237 cpu_gpr[rB(ctx->opcode)]); \
8238 }
8239 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8240 static inline void gen_##name(DisasContext *ctx) \
8241 { \
8242 TCGv_i32 t0, t1; \
8243 TCGv_i64 t2; \
8244 if (unlikely(!ctx->spe_enabled)) { \
8245 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8246 return; \
8247 } \
8248 t0 = tcg_temp_new_i32(); \
8249 t1 = tcg_temp_new_i32(); \
8250 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8251 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8252 gen_helper_##name(t0, cpu_env, t0, t1); \
8253 tcg_temp_free_i32(t1); \
8254 t2 = tcg_temp_new(); \
8255 tcg_gen_extu_i32_tl(t2, t0); \
8256 tcg_temp_free_i32(t0); \
8257 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8258 0xFFFFFFFF00000000ULL); \
8259 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8260 tcg_temp_free(t2); \
8261 }
8262 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8263 static inline void gen_##name(DisasContext *ctx) \
8264 { \
8265 if (unlikely(!ctx->spe_enabled)) { \
8266 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8267 return; \
8268 } \
8269 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8270 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8271 }
8272 #define GEN_SPEFPUOP_COMP_32(name) \
8273 static inline void gen_##name(DisasContext *ctx) \
8274 { \
8275 TCGv_i32 t0, t1; \
8276 if (unlikely(!ctx->spe_enabled)) { \
8277 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8278 return; \
8279 } \
8280 t0 = tcg_temp_new_i32(); \
8281 t1 = tcg_temp_new_i32(); \
8282 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8283 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8284 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8285 tcg_temp_free_i32(t0); \
8286 tcg_temp_free_i32(t1); \
8287 }
8288 #define GEN_SPEFPUOP_COMP_64(name) \
8289 static inline void gen_##name(DisasContext *ctx) \
8290 { \
8291 if (unlikely(!ctx->spe_enabled)) { \
8292 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8293 return; \
8294 } \
8295 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8296 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8297 }
8298 #else
8299 #define GEN_SPEFPUOP_CONV_32_32(name) \
8300 static inline void gen_##name(DisasContext *ctx) \
8301 { \
8302 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8303 cpu_gpr[rB(ctx->opcode)]); \
8304 }
8305 #define GEN_SPEFPUOP_CONV_32_64(name) \
8306 static inline void gen_##name(DisasContext *ctx) \
8307 { \
8308 TCGv_i64 t0 = tcg_temp_new_i64(); \
8309 gen_load_gpr64(t0, rB(ctx->opcode)); \
8310 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8311 tcg_temp_free_i64(t0); \
8312 }
8313 #define GEN_SPEFPUOP_CONV_64_32(name) \
8314 static inline void gen_##name(DisasContext *ctx) \
8315 { \
8316 TCGv_i64 t0 = tcg_temp_new_i64(); \
8317 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8318 gen_store_gpr64(rD(ctx->opcode), t0); \
8319 tcg_temp_free_i64(t0); \
8320 }
8321 #define GEN_SPEFPUOP_CONV_64_64(name) \
8322 static inline void gen_##name(DisasContext *ctx) \
8323 { \
8324 TCGv_i64 t0 = tcg_temp_new_i64(); \
8325 gen_load_gpr64(t0, rB(ctx->opcode)); \
8326 gen_helper_##name(t0, cpu_env, t0); \
8327 gen_store_gpr64(rD(ctx->opcode), t0); \
8328 tcg_temp_free_i64(t0); \
8329 }
8330 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8331 static inline void gen_##name(DisasContext *ctx) \
8332 { \
8333 if (unlikely(!ctx->spe_enabled)) { \
8334 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8335 return; \
8336 } \
8337 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8338 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8339 }
8340 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8341 static inline void gen_##name(DisasContext *ctx) \
8342 { \
8343 TCGv_i64 t0, t1; \
8344 if (unlikely(!ctx->spe_enabled)) { \
8345 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8346 return; \
8347 } \
8348 t0 = tcg_temp_new_i64(); \
8349 t1 = tcg_temp_new_i64(); \
8350 gen_load_gpr64(t0, rA(ctx->opcode)); \
8351 gen_load_gpr64(t1, rB(ctx->opcode)); \
8352 gen_helper_##name(t0, cpu_env, t0, t1); \
8353 gen_store_gpr64(rD(ctx->opcode), t0); \
8354 tcg_temp_free_i64(t0); \
8355 tcg_temp_free_i64(t1); \
8356 }
8357 #define GEN_SPEFPUOP_COMP_32(name) \
8358 static inline void gen_##name(DisasContext *ctx) \
8359 { \
8360 if (unlikely(!ctx->spe_enabled)) { \
8361 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8362 return; \
8363 } \
8364 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8365 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8366 }
8367 #define GEN_SPEFPUOP_COMP_64(name) \
8368 static inline void gen_##name(DisasContext *ctx) \
8369 { \
8370 TCGv_i64 t0, t1; \
8371 if (unlikely(!ctx->spe_enabled)) { \
8372 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8373 return; \
8374 } \
8375 t0 = tcg_temp_new_i64(); \
8376 t1 = tcg_temp_new_i64(); \
8377 gen_load_gpr64(t0, rA(ctx->opcode)); \
8378 gen_load_gpr64(t1, rB(ctx->opcode)); \
8379 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8380 tcg_temp_free_i64(t0); \
8381 tcg_temp_free_i64(t1); \
8382 }
8383 #endif
8384
8385 /* Single precision floating-point vectors operations */
8386 /* Arithmetic */
8387 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8388 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8389 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8390 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8391 static inline void gen_evfsabs(DisasContext *ctx)
8392 {
8393 if (unlikely(!ctx->spe_enabled)) {
8394 gen_exception(ctx, POWERPC_EXCP_SPEU);
8395 return;
8396 }
8397 #if defined(TARGET_PPC64)
8398 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8399 #else
8400 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8401 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8402 #endif
8403 }
8404 static inline void gen_evfsnabs(DisasContext *ctx)
8405 {
8406 if (unlikely(!ctx->spe_enabled)) {
8407 gen_exception(ctx, POWERPC_EXCP_SPEU);
8408 return;
8409 }
8410 #if defined(TARGET_PPC64)
8411 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8412 #else
8413 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8414 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8415 #endif
8416 }
8417 static inline void gen_evfsneg(DisasContext *ctx)
8418 {
8419 if (unlikely(!ctx->spe_enabled)) {
8420 gen_exception(ctx, POWERPC_EXCP_SPEU);
8421 return;
8422 }
8423 #if defined(TARGET_PPC64)
8424 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8425 #else
8426 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8427 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8428 #endif
8429 }
8430
8431 /* Conversion */
8432 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8433 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8434 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8435 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8436 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8437 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8438 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8439 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8440 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8441 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8442
8443 /* Comparison */
8444 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8445 GEN_SPEFPUOP_COMP_64(evfscmplt);
8446 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8447 GEN_SPEFPUOP_COMP_64(evfststgt);
8448 GEN_SPEFPUOP_COMP_64(evfststlt);
8449 GEN_SPEFPUOP_COMP_64(evfststeq);
8450
8451 /* Opcodes definitions */
8452 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8453 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8454 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8455 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8456 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8457 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8458 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8459 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8460 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8461 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8462 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8463 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8464 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8465 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8466
8467 /* Single precision floating-point operations */
8468 /* Arithmetic */
8469 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8470 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8471 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8472 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8473 static inline void gen_efsabs(DisasContext *ctx)
8474 {
8475 if (unlikely(!ctx->spe_enabled)) {
8476 gen_exception(ctx, POWERPC_EXCP_SPEU);
8477 return;
8478 }
8479 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8480 }
8481 static inline void gen_efsnabs(DisasContext *ctx)
8482 {
8483 if (unlikely(!ctx->spe_enabled)) {
8484 gen_exception(ctx, POWERPC_EXCP_SPEU);
8485 return;
8486 }
8487 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8488 }
8489 static inline void gen_efsneg(DisasContext *ctx)
8490 {
8491 if (unlikely(!ctx->spe_enabled)) {
8492 gen_exception(ctx, POWERPC_EXCP_SPEU);
8493 return;
8494 }
8495 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8496 }
8497
8498 /* Conversion */
8499 GEN_SPEFPUOP_CONV_32_32(efscfui);
8500 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8501 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8502 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8503 GEN_SPEFPUOP_CONV_32_32(efsctui);
8504 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8505 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8506 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8507 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8508 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8509 GEN_SPEFPUOP_CONV_32_64(efscfd);
8510
8511 /* Comparison */
8512 GEN_SPEFPUOP_COMP_32(efscmpgt);
8513 GEN_SPEFPUOP_COMP_32(efscmplt);
8514 GEN_SPEFPUOP_COMP_32(efscmpeq);
8515 GEN_SPEFPUOP_COMP_32(efststgt);
8516 GEN_SPEFPUOP_COMP_32(efststlt);
8517 GEN_SPEFPUOP_COMP_32(efststeq);
8518
8519 /* Opcodes definitions */
8520 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8521 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8522 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8523 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8524 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8525 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8526 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8527 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8528 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8529 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8530 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8531 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8532 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8533 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8534
8535 /* Double precision floating-point operations */
8536 /* Arithmetic */
8537 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8538 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8539 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8540 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8541 static inline void gen_efdabs(DisasContext *ctx)
8542 {
8543 if (unlikely(!ctx->spe_enabled)) {
8544 gen_exception(ctx, POWERPC_EXCP_SPEU);
8545 return;
8546 }
8547 #if defined(TARGET_PPC64)
8548 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8549 #else
8550 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8551 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8552 #endif
8553 }
8554 static inline void gen_efdnabs(DisasContext *ctx)
8555 {
8556 if (unlikely(!ctx->spe_enabled)) {
8557 gen_exception(ctx, POWERPC_EXCP_SPEU);
8558 return;
8559 }
8560 #if defined(TARGET_PPC64)
8561 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8562 #else
8563 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8564 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8565 #endif
8566 }
8567 static inline void gen_efdneg(DisasContext *ctx)
8568 {
8569 if (unlikely(!ctx->spe_enabled)) {
8570 gen_exception(ctx, POWERPC_EXCP_SPEU);
8571 return;
8572 }
8573 #if defined(TARGET_PPC64)
8574 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8575 #else
8576 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8577 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8578 #endif
8579 }
8580
8581 /* Conversion */
8582 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8583 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8584 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8585 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8586 GEN_SPEFPUOP_CONV_32_64(efdctui);
8587 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8588 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8589 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8590 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8591 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8592 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8593 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8594 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8595 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8596 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8597
8598 /* Comparison */
8599 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8600 GEN_SPEFPUOP_COMP_64(efdcmplt);
8601 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8602 GEN_SPEFPUOP_COMP_64(efdtstgt);
8603 GEN_SPEFPUOP_COMP_64(efdtstlt);
8604 GEN_SPEFPUOP_COMP_64(efdtsteq);
8605
8606 /* Opcodes definitions */
8607 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8608 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8609 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8610 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8611 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8612 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8613 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8614 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8615 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8616 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8617 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8618 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8619 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8620 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8621 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8622 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8623
8624 static opcode_t opcodes[] = {
8625 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8626 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8627 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8628 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8629 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8630 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
8631 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8632 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8633 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8634 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8635 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8636 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8637 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8638 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8639 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8640 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8641 #if defined(TARGET_PPC64)
8642 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8643 #endif
8644 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8645 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8646 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8647 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8648 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8649 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8650 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8651 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8652 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8653 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8654 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8655 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8656 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8657 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8658 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
8659 #if defined(TARGET_PPC64)
8660 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8661 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8662 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
8663 #endif
8664 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8665 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8666 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8667 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8668 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8669 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8670 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8671 #if defined(TARGET_PPC64)
8672 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8673 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8674 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8675 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8676 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8677 #endif
8678 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8679 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8680 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8681 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8682 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8683 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
8684 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8685 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
8686 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
8687 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
8688 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8689 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8690 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8691 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8692 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8693 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8694 #if defined(TARGET_PPC64)
8695 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8696 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8697 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8698 #endif
8699 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8700 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8701 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8702 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8703 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8704 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8705 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8706 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8707 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8708 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8709 #if defined(TARGET_PPC64)
8710 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8711 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8712 #endif
8713 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8714 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8715 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8716 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8717 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8718 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8719 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8720 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8721 #if defined(TARGET_PPC64)
8722 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8723 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8724 #endif
8725 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8726 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8727 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8728 #if defined(TARGET_PPC64)
8729 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8730 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8731 #endif
8732 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8733 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8734 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8735 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8736 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8737 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8738 #if defined(TARGET_PPC64)
8739 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8740 #endif
8741 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8742 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8743 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8744 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8745 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8746 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8747 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8748 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8749 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8750 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8751 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8752 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8753 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8754 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8755 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8756 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8757 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8758 #if defined(TARGET_PPC64)
8759 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8760 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8761 PPC_SEGMENT_64B),
8762 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8763 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8764 PPC_SEGMENT_64B),
8765 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8766 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8767 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8768 #endif
8769 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8770 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8771 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8772 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8773 #if defined(TARGET_PPC64)
8774 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8775 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8776 #endif
8777 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8778 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8779 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8780 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8781 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8782 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8783 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8784 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8785 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8786 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8787 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8788 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8789 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8790 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8791 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8792 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8793 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8794 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8795 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8796 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8797 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8798 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8799 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8800 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8801 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8802 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8803 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8804 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8805 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8806 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8807 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8808 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8809 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8810 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8811 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8812 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8813 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8814 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8815 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8816 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8817 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8818 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8819 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8820 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8821 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8822 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8823 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8824 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8825 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8826 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8827 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8828 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8829 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8830 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8831 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8832 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8833 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8834 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8835 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8836 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8837 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8838 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8839 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8840 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8841 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8842 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8843 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8844 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8845 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8846 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8847 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8848 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8849 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8850 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8851 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8852 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8853 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8854 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8855 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8856 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8857 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8858 PPC_NONE, PPC2_BOOKE206),
8859 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8860 PPC_NONE, PPC2_BOOKE206),
8861 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8862 PPC_NONE, PPC2_BOOKE206),
8863 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8864 PPC_NONE, PPC2_BOOKE206),
8865 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8866 PPC_NONE, PPC2_BOOKE206),
8867 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8868 PPC_NONE, PPC2_PRCNTL),
8869 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8870 PPC_NONE, PPC2_PRCNTL),
8871 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8872 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8873 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8874 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8875 PPC_BOOKE, PPC2_BOOKE206),
8876 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8877 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8878 PPC_BOOKE, PPC2_BOOKE206),
8879 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8880 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8881 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8882 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8883 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8884 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8885 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8886 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8887 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8888 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8889
8890 #undef GEN_INT_ARITH_ADD
8891 #undef GEN_INT_ARITH_ADD_CONST
8892 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8893 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8894 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8895 add_ca, compute_ca, compute_ov) \
8896 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8897 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8898 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8899 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8900 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8901 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8902 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8903 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8904 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8905 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8906 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8907
8908 #undef GEN_INT_ARITH_DIVW
8909 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8910 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8911 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8912 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8913 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8914 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8915
8916 #if defined(TARGET_PPC64)
8917 #undef GEN_INT_ARITH_DIVD
8918 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8919 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8920 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8921 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8922 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8923 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8924
8925 #undef GEN_INT_ARITH_MUL_HELPER
8926 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8927 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8928 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8929 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8930 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8931 #endif
8932
8933 #undef GEN_INT_ARITH_SUBF
8934 #undef GEN_INT_ARITH_SUBF_CONST
8935 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8936 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8937 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8938 add_ca, compute_ca, compute_ov) \
8939 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8940 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8941 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8942 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8943 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8944 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8945 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8946 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8947 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8948 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8949 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8950
8951 #undef GEN_LOGICAL1
8952 #undef GEN_LOGICAL2
8953 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8954 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8955 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8956 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8957 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8958 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8959 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8960 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8961 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8962 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8963 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8964 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8965 #if defined(TARGET_PPC64)
8966 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8967 #endif
8968
8969 #if defined(TARGET_PPC64)
8970 #undef GEN_PPC64_R2
8971 #undef GEN_PPC64_R4
8972 #define GEN_PPC64_R2(name, opc1, opc2) \
8973 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8974 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8975 PPC_64B)
8976 #define GEN_PPC64_R4(name, opc1, opc2) \
8977 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8978 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8979 PPC_64B), \
8980 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8981 PPC_64B), \
8982 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8983 PPC_64B)
8984 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8985 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8986 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8987 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8988 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8989 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8990 #endif
8991
8992 #undef _GEN_FLOAT_ACB
8993 #undef GEN_FLOAT_ACB
8994 #undef _GEN_FLOAT_AB
8995 #undef GEN_FLOAT_AB
8996 #undef _GEN_FLOAT_AC
8997 #undef GEN_FLOAT_AC
8998 #undef GEN_FLOAT_B
8999 #undef GEN_FLOAT_BS
9000 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
9001 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
9002 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
9003 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
9004 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
9005 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9006 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9007 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
9008 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9009 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9010 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9011 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9012 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
9013 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9014 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9015 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
9016 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
9017 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
9018 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
9019
9020 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
9021 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
9022 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
9023 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
9024 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
9025 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
9026 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
9027 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
9028 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
9029 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
9030 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
9031 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
9032 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
9033 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
9034 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
9035 #if defined(TARGET_PPC64)
9036 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
9037 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
9038 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
9039 #endif
9040 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
9041 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
9042 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
9043 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
9044
9045 #undef GEN_LD
9046 #undef GEN_LDU
9047 #undef GEN_LDUX
9048 #undef GEN_LDX_E
9049 #undef GEN_LDS
9050 #define GEN_LD(name, ldop, opc, type) \
9051 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9052 #define GEN_LDU(name, ldop, opc, type) \
9053 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9054 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
9055 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9056 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
9057 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9058 #define GEN_LDS(name, ldop, op, type) \
9059 GEN_LD(name, ldop, op | 0x20, type) \
9060 GEN_LDU(name, ldop, op | 0x21, type) \
9061 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
9062 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
9063
9064 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
9065 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
9066 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
9067 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
9068 #if defined(TARGET_PPC64)
9069 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
9070 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
9071 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
9072 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
9073 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
9074 #endif
9075 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
9076 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
9077
9078 #undef GEN_ST
9079 #undef GEN_STU
9080 #undef GEN_STUX
9081 #undef GEN_STX_E
9082 #undef GEN_STS
9083 #define GEN_ST(name, stop, opc, type) \
9084 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9085 #define GEN_STU(name, stop, opc, type) \
9086 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
9087 #define GEN_STUX(name, stop, opc2, opc3, type) \
9088 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9089 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
9090 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9091 #define GEN_STS(name, stop, op, type) \
9092 GEN_ST(name, stop, op | 0x20, type) \
9093 GEN_STU(name, stop, op | 0x21, type) \
9094 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
9095 GEN_STX(name, stop, 0x17, op | 0x00, type)
9096
9097 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
9098 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
9099 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
9100 #if defined(TARGET_PPC64)
9101 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
9102 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
9103 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
9104 #endif
9105 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
9106 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
9107
9108 #undef GEN_LDF
9109 #undef GEN_LDUF
9110 #undef GEN_LDUXF
9111 #undef GEN_LDXF
9112 #undef GEN_LDFS
9113 #define GEN_LDF(name, ldop, opc, type) \
9114 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9115 #define GEN_LDUF(name, ldop, opc, type) \
9116 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9117 #define GEN_LDUXF(name, ldop, opc, type) \
9118 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9119 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9120 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9121 #define GEN_LDFS(name, ldop, op, type) \
9122 GEN_LDF(name, ldop, op | 0x20, type) \
9123 GEN_LDUF(name, ldop, op | 0x21, type) \
9124 GEN_LDUXF(name, ldop, op | 0x01, type) \
9125 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9126
9127 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
9128 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
9129 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
9130 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
9131 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
9132
9133 #undef GEN_STF
9134 #undef GEN_STUF
9135 #undef GEN_STUXF
9136 #undef GEN_STXF
9137 #undef GEN_STFS
9138 #define GEN_STF(name, stop, opc, type) \
9139 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9140 #define GEN_STUF(name, stop, opc, type) \
9141 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9142 #define GEN_STUXF(name, stop, opc, type) \
9143 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9144 #define GEN_STXF(name, stop, opc2, opc3, type) \
9145 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9146 #define GEN_STFS(name, stop, op, type) \
9147 GEN_STF(name, stop, op | 0x20, type) \
9148 GEN_STUF(name, stop, op | 0x21, type) \
9149 GEN_STUXF(name, stop, op | 0x01, type) \
9150 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9151
9152 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
9153 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
9154 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
9155 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
9156 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
9157
9158 #undef GEN_CRLOGIC
9159 #define GEN_CRLOGIC(name, tcg_op, opc) \
9160 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9161 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
9162 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
9163 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
9164 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9165 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9166 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9167 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9168 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9169
9170 #undef GEN_MAC_HANDLER
9171 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9172 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9173 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9174 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9175 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9176 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9177 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9178 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9179 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9180 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9181 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9182 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9183 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9184 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9185 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9186 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9187 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9188 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9189 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9190 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9191 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9192 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9193 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9194 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9195 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9196 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9197 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9198 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9199 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9200 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9201 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9202 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9203 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9204 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9205 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9206 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9207 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9208 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9209 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9210 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9211 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9212 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9213 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9214 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9215
9216 #undef GEN_VR_LDX
9217 #undef GEN_VR_STX
9218 #undef GEN_VR_LVE
9219 #undef GEN_VR_STVE
9220 #define GEN_VR_LDX(name, opc2, opc3) \
9221 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9222 #define GEN_VR_STX(name, opc2, opc3) \
9223 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9224 #define GEN_VR_LVE(name, opc2, opc3) \
9225 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9226 #define GEN_VR_STVE(name, opc2, opc3) \
9227 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9228 GEN_VR_LDX(lvx, 0x07, 0x03),
9229 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9230 GEN_VR_LVE(bx, 0x07, 0x00),
9231 GEN_VR_LVE(hx, 0x07, 0x01),
9232 GEN_VR_LVE(wx, 0x07, 0x02),
9233 GEN_VR_STX(svx, 0x07, 0x07),
9234 GEN_VR_STX(svxl, 0x07, 0x0F),
9235 GEN_VR_STVE(bx, 0x07, 0x04),
9236 GEN_VR_STVE(hx, 0x07, 0x05),
9237 GEN_VR_STVE(wx, 0x07, 0x06),
9238
9239 #undef GEN_VX_LOGICAL
9240 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9241 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9242 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9243 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9244 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9245 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9246 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9247
9248 #undef GEN_VXFORM
9249 #define GEN_VXFORM(name, opc2, opc3) \
9250 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9251 GEN_VXFORM(vaddubm, 0, 0),
9252 GEN_VXFORM(vadduhm, 0, 1),
9253 GEN_VXFORM(vadduwm, 0, 2),
9254 GEN_VXFORM(vsububm, 0, 16),
9255 GEN_VXFORM(vsubuhm, 0, 17),
9256 GEN_VXFORM(vsubuwm, 0, 18),
9257 GEN_VXFORM(vmaxub, 1, 0),
9258 GEN_VXFORM(vmaxuh, 1, 1),
9259 GEN_VXFORM(vmaxuw, 1, 2),
9260 GEN_VXFORM(vmaxsb, 1, 4),
9261 GEN_VXFORM(vmaxsh, 1, 5),
9262 GEN_VXFORM(vmaxsw, 1, 6),
9263 GEN_VXFORM(vminub, 1, 8),
9264 GEN_VXFORM(vminuh, 1, 9),
9265 GEN_VXFORM(vminuw, 1, 10),
9266 GEN_VXFORM(vminsb, 1, 12),
9267 GEN_VXFORM(vminsh, 1, 13),
9268 GEN_VXFORM(vminsw, 1, 14),
9269 GEN_VXFORM(vavgub, 1, 16),
9270 GEN_VXFORM(vavguh, 1, 17),
9271 GEN_VXFORM(vavguw, 1, 18),
9272 GEN_VXFORM(vavgsb, 1, 20),
9273 GEN_VXFORM(vavgsh, 1, 21),
9274 GEN_VXFORM(vavgsw, 1, 22),
9275 GEN_VXFORM(vmrghb, 6, 0),
9276 GEN_VXFORM(vmrghh, 6, 1),
9277 GEN_VXFORM(vmrghw, 6, 2),
9278 GEN_VXFORM(vmrglb, 6, 4),
9279 GEN_VXFORM(vmrglh, 6, 5),
9280 GEN_VXFORM(vmrglw, 6, 6),
9281 GEN_VXFORM(vmuloub, 4, 0),
9282 GEN_VXFORM(vmulouh, 4, 1),
9283 GEN_VXFORM(vmulosb, 4, 4),
9284 GEN_VXFORM(vmulosh, 4, 5),
9285 GEN_VXFORM(vmuleub, 4, 8),
9286 GEN_VXFORM(vmuleuh, 4, 9),
9287 GEN_VXFORM(vmulesb, 4, 12),
9288 GEN_VXFORM(vmulesh, 4, 13),
9289 GEN_VXFORM(vslb, 2, 4),
9290 GEN_VXFORM(vslh, 2, 5),
9291 GEN_VXFORM(vslw, 2, 6),
9292 GEN_VXFORM(vsrb, 2, 8),
9293 GEN_VXFORM(vsrh, 2, 9),
9294 GEN_VXFORM(vsrw, 2, 10),
9295 GEN_VXFORM(vsrab, 2, 12),
9296 GEN_VXFORM(vsrah, 2, 13),
9297 GEN_VXFORM(vsraw, 2, 14),
9298 GEN_VXFORM(vslo, 6, 16),
9299 GEN_VXFORM(vsro, 6, 17),
9300 GEN_VXFORM(vaddcuw, 0, 6),
9301 GEN_VXFORM(vsubcuw, 0, 22),
9302 GEN_VXFORM(vaddubs, 0, 8),
9303 GEN_VXFORM(vadduhs, 0, 9),
9304 GEN_VXFORM(vadduws, 0, 10),
9305 GEN_VXFORM(vaddsbs, 0, 12),
9306 GEN_VXFORM(vaddshs, 0, 13),
9307 GEN_VXFORM(vaddsws, 0, 14),
9308 GEN_VXFORM(vsububs, 0, 24),
9309 GEN_VXFORM(vsubuhs, 0, 25),
9310 GEN_VXFORM(vsubuws, 0, 26),
9311 GEN_VXFORM(vsubsbs, 0, 28),
9312 GEN_VXFORM(vsubshs, 0, 29),
9313 GEN_VXFORM(vsubsws, 0, 30),
9314 GEN_VXFORM(vrlb, 2, 0),
9315 GEN_VXFORM(vrlh, 2, 1),
9316 GEN_VXFORM(vrlw, 2, 2),
9317 GEN_VXFORM(vsl, 2, 7),
9318 GEN_VXFORM(vsr, 2, 11),
9319 GEN_VXFORM(vpkuhum, 7, 0),
9320 GEN_VXFORM(vpkuwum, 7, 1),
9321 GEN_VXFORM(vpkuhus, 7, 2),
9322 GEN_VXFORM(vpkuwus, 7, 3),
9323 GEN_VXFORM(vpkshus, 7, 4),
9324 GEN_VXFORM(vpkswus, 7, 5),
9325 GEN_VXFORM(vpkshss, 7, 6),
9326 GEN_VXFORM(vpkswss, 7, 7),
9327 GEN_VXFORM(vpkpx, 7, 12),
9328 GEN_VXFORM(vsum4ubs, 4, 24),
9329 GEN_VXFORM(vsum4sbs, 4, 28),
9330 GEN_VXFORM(vsum4shs, 4, 25),
9331 GEN_VXFORM(vsum2sws, 4, 26),
9332 GEN_VXFORM(vsumsws, 4, 30),
9333 GEN_VXFORM(vaddfp, 5, 0),
9334 GEN_VXFORM(vsubfp, 5, 1),
9335 GEN_VXFORM(vmaxfp, 5, 16),
9336 GEN_VXFORM(vminfp, 5, 17),
9337
9338 #undef GEN_VXRFORM1
9339 #undef GEN_VXRFORM
9340 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9341 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9342 #define GEN_VXRFORM(name, opc2, opc3) \
9343 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9344 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9345 GEN_VXRFORM(vcmpequb, 3, 0)
9346 GEN_VXRFORM(vcmpequh, 3, 1)
9347 GEN_VXRFORM(vcmpequw, 3, 2)
9348 GEN_VXRFORM(vcmpgtsb, 3, 12)
9349 GEN_VXRFORM(vcmpgtsh, 3, 13)
9350 GEN_VXRFORM(vcmpgtsw, 3, 14)
9351 GEN_VXRFORM(vcmpgtub, 3, 8)
9352 GEN_VXRFORM(vcmpgtuh, 3, 9)
9353 GEN_VXRFORM(vcmpgtuw, 3, 10)
9354 GEN_VXRFORM(vcmpeqfp, 3, 3)
9355 GEN_VXRFORM(vcmpgefp, 3, 7)
9356 GEN_VXRFORM(vcmpgtfp, 3, 11)
9357 GEN_VXRFORM(vcmpbfp, 3, 15)
9358
9359 #undef GEN_VXFORM_SIMM
9360 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9361 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9362 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9363 GEN_VXFORM_SIMM(vspltish, 6, 13),
9364 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9365
9366 #undef GEN_VXFORM_NOA
9367 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9368 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9369 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9370 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9371 GEN_VXFORM_NOA(vupklsb, 7, 10),
9372 GEN_VXFORM_NOA(vupklsh, 7, 11),
9373 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9374 GEN_VXFORM_NOA(vupklpx, 7, 15),
9375 GEN_VXFORM_NOA(vrefp, 5, 4),
9376 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9377 GEN_VXFORM_NOA(vexptefp, 5, 6),
9378 GEN_VXFORM_NOA(vlogefp, 5, 7),
9379 GEN_VXFORM_NOA(vrfim, 5, 8),
9380 GEN_VXFORM_NOA(vrfin, 5, 9),
9381 GEN_VXFORM_NOA(vrfip, 5, 10),
9382 GEN_VXFORM_NOA(vrfiz, 5, 11),
9383
9384 #undef GEN_VXFORM_UIMM
9385 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9386 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9387 GEN_VXFORM_UIMM(vspltb, 6, 8),
9388 GEN_VXFORM_UIMM(vsplth, 6, 9),
9389 GEN_VXFORM_UIMM(vspltw, 6, 10),
9390 GEN_VXFORM_UIMM(vcfux, 5, 12),
9391 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9392 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9393 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9394
9395 #undef GEN_VAFORM_PAIRED
9396 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9397 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9398 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9399 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9400 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9401 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9402 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9403 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9404
9405 #undef GEN_SPE
9406 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9407 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9408 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9409 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9410 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9411 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9412 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9413 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9414 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9415 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9416 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9417 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9418 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9419 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9420 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9421 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9422 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9423 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9424 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9425 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9426 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9427 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9428 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9429 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9430 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9431 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9432 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9433 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9434 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9435 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9436 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9437
9438 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9439 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9440 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9441 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9442 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9443 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9444 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9445 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9446 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9447 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9448 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9449 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9450 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9451 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9452
9453 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9454 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9455 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9456 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9457 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9458 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9459 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9460 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9461 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9462 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9463 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9464 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9465 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9466 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9467
9468 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9469 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9470 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9471 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9472 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9473 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9474 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9475 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9476 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9477 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9478 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9479 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9480 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9481 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9482 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9483 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9484
9485 #undef GEN_SPEOP_LDST
9486 #define GEN_SPEOP_LDST(name, opc2, sh) \
9487 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9488 GEN_SPEOP_LDST(evldd, 0x00, 3),
9489 GEN_SPEOP_LDST(evldw, 0x01, 3),
9490 GEN_SPEOP_LDST(evldh, 0x02, 3),
9491 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9492 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9493 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9494 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9495 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9496 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9497 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9498 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9499
9500 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9501 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9502 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9503 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9504 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9505 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9506 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9507 };
9508
9509 #include "helper_regs.h"
9510 #include "translate_init.c"
9511
9512 /*****************************************************************************/
9513 /* Misc PowerPC helpers */
9514 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9515 int flags)
9516 {
9517 #define RGPL 4
9518 #define RFPL 4
9519
9520 int i;
9521
9522 cpu_synchronize_state(env);
9523
9524 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9525 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9526 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9527 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9528 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9529 env->hflags, env->mmu_idx);
9530 #if !defined(NO_TIMER_DUMP)
9531 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9532 #if !defined(CONFIG_USER_ONLY)
9533 " DECR %08" PRIu32
9534 #endif
9535 "\n",
9536 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9537 #if !defined(CONFIG_USER_ONLY)
9538 , cpu_ppc_load_decr(env)
9539 #endif
9540 );
9541 #endif
9542 for (i = 0; i < 32; i++) {
9543 if ((i & (RGPL - 1)) == 0)
9544 cpu_fprintf(f, "GPR%02d", i);
9545 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9546 if ((i & (RGPL - 1)) == (RGPL - 1))
9547 cpu_fprintf(f, "\n");
9548 }
9549 cpu_fprintf(f, "CR ");
9550 for (i = 0; i < 8; i++)
9551 cpu_fprintf(f, "%01x", env->crf[i]);
9552 cpu_fprintf(f, " [");
9553 for (i = 0; i < 8; i++) {
9554 char a = '-';
9555 if (env->crf[i] & 0x08)
9556 a = 'L';
9557 else if (env->crf[i] & 0x04)
9558 a = 'G';
9559 else if (env->crf[i] & 0x02)
9560 a = 'E';
9561 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9562 }
9563 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9564 env->reserve_addr);
9565 for (i = 0; i < 32; i++) {
9566 if ((i & (RFPL - 1)) == 0)
9567 cpu_fprintf(f, "FPR%02d", i);
9568 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9569 if ((i & (RFPL - 1)) == (RFPL - 1))
9570 cpu_fprintf(f, "\n");
9571 }
9572 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9573 #if !defined(CONFIG_USER_ONLY)
9574 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9575 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9576 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9577 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9578
9579 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9580 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9581 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9582 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9583
9584 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9585 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9586 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9587 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9588
9589 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9590 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9591 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9592 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9593 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9594
9595 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9596 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9597 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9598 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9599
9600 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9601 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9602 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9603 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9604
9605 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9606 " EPR " TARGET_FMT_lx "\n",
9607 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9608 env->spr[SPR_BOOKE_EPR]);
9609
9610 /* FSL-specific */
9611 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9612 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9613 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9614 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9615
9616 /*
9617 * IVORs are left out as they are large and do not change often --
9618 * they can be read with "p $ivor0", "p $ivor1", etc.
9619 */
9620 }
9621
9622 #if defined(TARGET_PPC64)
9623 if (env->flags & POWERPC_FLAG_CFAR) {
9624 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9625 }
9626 #endif
9627
9628 switch (env->mmu_model) {
9629 case POWERPC_MMU_32B:
9630 case POWERPC_MMU_601:
9631 case POWERPC_MMU_SOFT_6xx:
9632 case POWERPC_MMU_SOFT_74xx:
9633 #if defined(TARGET_PPC64)
9634 case POWERPC_MMU_64B:
9635 #endif
9636 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9637 break;
9638 case POWERPC_MMU_BOOKE206:
9639 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9640 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9641 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9642 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9643
9644 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9645 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9646 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9647 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9648
9649 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9650 " TLB1CFG " TARGET_FMT_lx "\n",
9651 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9652 env->spr[SPR_BOOKE_TLB1CFG]);
9653 break;
9654 default:
9655 break;
9656 }
9657 #endif
9658
9659 #undef RGPL
9660 #undef RFPL
9661 }
9662
9663 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9664 int flags)
9665 {
9666 #if defined(DO_PPC_STATISTICS)
9667 opc_handler_t **t1, **t2, **t3, *handler;
9668 int op1, op2, op3;
9669
9670 t1 = env->opcodes;
9671 for (op1 = 0; op1 < 64; op1++) {
9672 handler = t1[op1];
9673 if (is_indirect_opcode(handler)) {
9674 t2 = ind_table(handler);
9675 for (op2 = 0; op2 < 32; op2++) {
9676 handler = t2[op2];
9677 if (is_indirect_opcode(handler)) {
9678 t3 = ind_table(handler);
9679 for (op3 = 0; op3 < 32; op3++) {
9680 handler = t3[op3];
9681 if (handler->count == 0)
9682 continue;
9683 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9684 "%016" PRIx64 " %" PRId64 "\n",
9685 op1, op2, op3, op1, (op3 << 5) | op2,
9686 handler->oname,
9687 handler->count, handler->count);
9688 }
9689 } else {
9690 if (handler->count == 0)
9691 continue;
9692 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9693 "%016" PRIx64 " %" PRId64 "\n",
9694 op1, op2, op1, op2, handler->oname,
9695 handler->count, handler->count);
9696 }
9697 }
9698 } else {
9699 if (handler->count == 0)
9700 continue;
9701 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9702 " %" PRId64 "\n",
9703 op1, op1, handler->oname,
9704 handler->count, handler->count);
9705 }
9706 }
9707 #endif
9708 }
9709
9710 /*****************************************************************************/
9711 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9712 TranslationBlock *tb,
9713 int search_pc)
9714 {
9715 DisasContext ctx, *ctxp = &ctx;
9716 opc_handler_t **table, *handler;
9717 target_ulong pc_start;
9718 uint16_t *gen_opc_end;
9719 CPUBreakpoint *bp;
9720 int j, lj = -1;
9721 int num_insns;
9722 int max_insns;
9723
9724 pc_start = tb->pc;
9725 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9726 ctx.nip = pc_start;
9727 ctx.tb = tb;
9728 ctx.exception = POWERPC_EXCP_NONE;
9729 ctx.spr_cb = env->spr_cb;
9730 ctx.mem_idx = env->mmu_idx;
9731 ctx.access_type = -1;
9732 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9733 #if defined(TARGET_PPC64)
9734 ctx.sf_mode = msr_is_64bit(env, env->msr);
9735 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9736 #endif
9737 ctx.fpu_enabled = msr_fp;
9738 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9739 ctx.spe_enabled = msr_spe;
9740 else
9741 ctx.spe_enabled = 0;
9742 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9743 ctx.altivec_enabled = msr_vr;
9744 else
9745 ctx.altivec_enabled = 0;
9746 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9747 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9748 else
9749 ctx.singlestep_enabled = 0;
9750 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9751 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9752 if (unlikely(env->singlestep_enabled))
9753 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9754 #if defined (DO_SINGLE_STEP) && 0
9755 /* Single step trace mode */
9756 msr_se = 1;
9757 #endif
9758 num_insns = 0;
9759 max_insns = tb->cflags & CF_COUNT_MASK;
9760 if (max_insns == 0)
9761 max_insns = CF_COUNT_MASK;
9762
9763 gen_tb_start();
9764 /* Set env in case of segfault during code fetch */
9765 while (ctx.exception == POWERPC_EXCP_NONE
9766 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9767 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9768 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9769 if (bp->pc == ctx.nip) {
9770 gen_debug_exception(ctxp);
9771 break;
9772 }
9773 }
9774 }
9775 if (unlikely(search_pc)) {
9776 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9777 if (lj < j) {
9778 lj++;
9779 while (lj < j)
9780 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9781 }
9782 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9783 tcg_ctx.gen_opc_instr_start[lj] = 1;
9784 tcg_ctx.gen_opc_icount[lj] = num_insns;
9785 }
9786 LOG_DISAS("----------------\n");
9787 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9788 ctx.nip, ctx.mem_idx, (int)msr_ir);
9789 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9790 gen_io_start();
9791 if (unlikely(ctx.le_mode)) {
9792 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9793 } else {
9794 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9795 }
9796 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9797 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9798 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9799 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9800 tcg_gen_debug_insn_start(ctx.nip);
9801 }
9802 ctx.nip += 4;
9803 table = env->opcodes;
9804 num_insns++;
9805 handler = table[opc1(ctx.opcode)];
9806 if (is_indirect_opcode(handler)) {
9807 table = ind_table(handler);
9808 handler = table[opc2(ctx.opcode)];
9809 if (is_indirect_opcode(handler)) {
9810 table = ind_table(handler);
9811 handler = table[opc3(ctx.opcode)];
9812 }
9813 }
9814 /* Is opcode *REALLY* valid ? */
9815 if (unlikely(handler->handler == &gen_invalid)) {
9816 if (qemu_log_enabled()) {
9817 qemu_log("invalid/unsupported opcode: "
9818 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9819 opc1(ctx.opcode), opc2(ctx.opcode),
9820 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9821 }
9822 } else {
9823 uint32_t inval;
9824
9825 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9826 inval = handler->inval2;
9827 } else {
9828 inval = handler->inval1;
9829 }
9830
9831 if (unlikely((ctx.opcode & inval) != 0)) {
9832 if (qemu_log_enabled()) {
9833 qemu_log("invalid bits: %08x for opcode: "
9834 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9835 ctx.opcode & inval, opc1(ctx.opcode),
9836 opc2(ctx.opcode), opc3(ctx.opcode),
9837 ctx.opcode, ctx.nip - 4);
9838 }
9839 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9840 break;
9841 }
9842 }
9843 (*(handler->handler))(&ctx);
9844 #if defined(DO_PPC_STATISTICS)
9845 handler->count++;
9846 #endif
9847 /* Check trace mode exceptions */
9848 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9849 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9850 ctx.exception != POWERPC_SYSCALL &&
9851 ctx.exception != POWERPC_EXCP_TRAP &&
9852 ctx.exception != POWERPC_EXCP_BRANCH)) {
9853 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9854 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9855 (env->singlestep_enabled) ||
9856 singlestep ||
9857 num_insns >= max_insns)) {
9858 /* if we reach a page boundary or are single stepping, stop
9859 * generation
9860 */
9861 break;
9862 }
9863 }
9864 if (tb->cflags & CF_LAST_IO)
9865 gen_io_end();
9866 if (ctx.exception == POWERPC_EXCP_NONE) {
9867 gen_goto_tb(&ctx, 0, ctx.nip);
9868 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9869 if (unlikely(env->singlestep_enabled)) {
9870 gen_debug_exception(ctxp);
9871 }
9872 /* Generate the return instruction */
9873 tcg_gen_exit_tb(0);
9874 }
9875 gen_tb_end(tb, num_insns);
9876 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9877 if (unlikely(search_pc)) {
9878 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9879 lj++;
9880 while (lj <= j)
9881 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9882 } else {
9883 tb->size = ctx.nip - pc_start;
9884 tb->icount = num_insns;
9885 }
9886 #if defined(DEBUG_DISAS)
9887 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9888 int flags;
9889 flags = env->bfd_mach;
9890 flags |= ctx.le_mode << 16;
9891 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9892 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9893 qemu_log("\n");
9894 }
9895 #endif
9896 }
9897
9898 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9899 {
9900 gen_intermediate_code_internal(env, tb, 0);
9901 }
9902
9903 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9904 {
9905 gen_intermediate_code_internal(env, tb, 1);
9906 }
9907
9908 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9909 {
9910 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9911 }
Qemu copy for testing