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[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "disas.h"
28 #include "tcg-op.h"
29 #include "qemu-common.h"
30 #include "host-utils.h"
31
32 #include "helper.h"
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_ptr cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 #if !defined(TARGET_PPC64)
56 + 10*4 + 22*5 /* SPE GPRh */
57 #endif
58 + 10*4 + 22*5 /* FPR */
59 + 2*(10*6 + 22*7) /* AVRh, AVRl */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 #if !defined(TARGET_PPC64)
63 static TCGv cpu_gprh[32];
64 #endif
65 static TCGv_i64 cpu_fpr[32];
66 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
67 static TCGv_i32 cpu_crf[8];
68 static TCGv cpu_nip;
69 static TCGv cpu_msr;
70 static TCGv cpu_ctr;
71 static TCGv cpu_lr;
72 static TCGv cpu_xer;
73 static TCGv cpu_reserve;
74 static TCGv_i32 cpu_fpscr;
75 static TCGv_i32 cpu_access_type;
76
77 #include "gen-icount.h"
78
79 void ppc_translate_init(void)
80 {
81 int i;
82 char* p;
83 size_t cpu_reg_names_size;
84 static int done_init = 0;
85
86 if (done_init)
87 return;
88
89 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
90
91 p = cpu_reg_names;
92 cpu_reg_names_size = sizeof(cpu_reg_names);
93
94 for (i = 0; i < 8; i++) {
95 snprintf(p, cpu_reg_names_size, "crf%d", i);
96 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
97 offsetof(CPUState, crf[i]), p);
98 p += 5;
99 cpu_reg_names_size -= 5;
100 }
101
102 for (i = 0; i < 32; i++) {
103 snprintf(p, cpu_reg_names_size, "r%d", i);
104 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
105 offsetof(CPUState, gpr[i]), p);
106 p += (i < 10) ? 3 : 4;
107 cpu_reg_names_size -= (i < 10) ? 3 : 4;
108 #if !defined(TARGET_PPC64)
109 snprintf(p, cpu_reg_names_size, "r%dH", i);
110 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, gprh[i]), p);
112 p += (i < 10) ? 4 : 5;
113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
114 #endif
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
118 offsetof(CPUState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
128 offsetof(CPUState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
139 offsetof(CPUState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 }
144
145 cpu_nip = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUState, nip), "nip");
147
148 cpu_msr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUState, msr), "msr");
150
151 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUState, ctr), "ctr");
153
154 cpu_lr = tcg_global_mem_new(TCG_AREG0,
155 offsetof(CPUState, lr), "lr");
156
157 cpu_xer = tcg_global_mem_new(TCG_AREG0,
158 offsetof(CPUState, xer), "xer");
159
160 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
161 offsetof(CPUState, reserve_addr),
162 "reserve_addr");
163
164 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
165 offsetof(CPUState, fpscr), "fpscr");
166
167 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
168 offsetof(CPUState, access_type), "access_type");
169
170 /* register helpers */
171 #define GEN_HELPER 2
172 #include "helper.h"
173
174 done_init = 1;
175 }
176
177 /* internal defines */
178 typedef struct DisasContext {
179 struct TranslationBlock *tb;
180 target_ulong nip;
181 uint32_t opcode;
182 uint32_t exception;
183 /* Routine used to access memory */
184 int mem_idx;
185 int access_type;
186 /* Translation flags */
187 int le_mode;
188 #if defined(TARGET_PPC64)
189 int sf_mode;
190 #endif
191 int fpu_enabled;
192 int altivec_enabled;
193 int spe_enabled;
194 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
195 int singlestep_enabled;
196 } DisasContext;
197
198 struct opc_handler_t {
199 /* invalid bits */
200 uint32_t inval;
201 /* instruction type */
202 uint64_t type;
203 /* extended instruction type */
204 uint64_t type2;
205 /* handler */
206 void (*handler)(DisasContext *ctx);
207 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
208 const char *oname;
209 #endif
210 #if defined(DO_PPC_STATISTICS)
211 uint64_t count;
212 #endif
213 };
214
215 static inline void gen_reset_fpstatus(void)
216 {
217 gen_helper_reset_fpstatus();
218 }
219
220 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
221 {
222 TCGv_i32 t0 = tcg_temp_new_i32();
223
224 if (set_fprf != 0) {
225 /* This case might be optimized later */
226 tcg_gen_movi_i32(t0, 1);
227 gen_helper_compute_fprf(t0, arg, t0);
228 if (unlikely(set_rc)) {
229 tcg_gen_mov_i32(cpu_crf[1], t0);
230 }
231 gen_helper_float_check_status();
232 } else if (unlikely(set_rc)) {
233 /* We always need to compute fpcc */
234 tcg_gen_movi_i32(t0, 0);
235 gen_helper_compute_fprf(t0, arg, t0);
236 tcg_gen_mov_i32(cpu_crf[1], t0);
237 }
238
239 tcg_temp_free_i32(t0);
240 }
241
242 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
243 {
244 if (ctx->access_type != access_type) {
245 tcg_gen_movi_i32(cpu_access_type, access_type);
246 ctx->access_type = access_type;
247 }
248 }
249
250 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
251 {
252 #if defined(TARGET_PPC64)
253 if (ctx->sf_mode)
254 tcg_gen_movi_tl(cpu_nip, nip);
255 else
256 #endif
257 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
258 }
259
260 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
261 {
262 TCGv_i32 t0, t1;
263 if (ctx->exception == POWERPC_EXCP_NONE) {
264 gen_update_nip(ctx, ctx->nip);
265 }
266 t0 = tcg_const_i32(excp);
267 t1 = tcg_const_i32(error);
268 gen_helper_raise_exception_err(t0, t1);
269 tcg_temp_free_i32(t0);
270 tcg_temp_free_i32(t1);
271 ctx->exception = (excp);
272 }
273
274 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
275 {
276 TCGv_i32 t0;
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->nip);
279 }
280 t0 = tcg_const_i32(excp);
281 gen_helper_raise_exception(t0);
282 tcg_temp_free_i32(t0);
283 ctx->exception = (excp);
284 }
285
286 static inline void gen_debug_exception(DisasContext *ctx)
287 {
288 TCGv_i32 t0;
289
290 if (ctx->exception != POWERPC_EXCP_BRANCH)
291 gen_update_nip(ctx, ctx->nip);
292 t0 = tcg_const_i32(EXCP_DEBUG);
293 gen_helper_raise_exception(t0);
294 tcg_temp_free_i32(t0);
295 }
296
297 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
298 {
299 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
300 }
301
302 /* Stop translation */
303 static inline void gen_stop_exception(DisasContext *ctx)
304 {
305 gen_update_nip(ctx, ctx->nip);
306 ctx->exception = POWERPC_EXCP_STOP;
307 }
308
309 /* No need to update nip here, as execution flow will change */
310 static inline void gen_sync_exception(DisasContext *ctx)
311 {
312 ctx->exception = POWERPC_EXCP_SYNC;
313 }
314
315 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
316 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
317
318 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
319 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
320
321 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
322 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
323
324 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
325 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
326
327 typedef struct opcode_t {
328 unsigned char opc1, opc2, opc3;
329 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
330 unsigned char pad[5];
331 #else
332 unsigned char pad[1];
333 #endif
334 opc_handler_t handler;
335 const char *oname;
336 } opcode_t;
337
338 /*****************************************************************************/
339 /*** Instruction decoding ***/
340 #define EXTRACT_HELPER(name, shift, nb) \
341 static inline uint32_t name(uint32_t opcode) \
342 { \
343 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
344 }
345
346 #define EXTRACT_SHELPER(name, shift, nb) \
347 static inline int32_t name(uint32_t opcode) \
348 { \
349 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
350 }
351
352 /* Opcode part 1 */
353 EXTRACT_HELPER(opc1, 26, 6);
354 /* Opcode part 2 */
355 EXTRACT_HELPER(opc2, 1, 5);
356 /* Opcode part 3 */
357 EXTRACT_HELPER(opc3, 6, 5);
358 /* Update Cr0 flags */
359 EXTRACT_HELPER(Rc, 0, 1);
360 /* Destination */
361 EXTRACT_HELPER(rD, 21, 5);
362 /* Source */
363 EXTRACT_HELPER(rS, 21, 5);
364 /* First operand */
365 EXTRACT_HELPER(rA, 16, 5);
366 /* Second operand */
367 EXTRACT_HELPER(rB, 11, 5);
368 /* Third operand */
369 EXTRACT_HELPER(rC, 6, 5);
370 /*** Get CRn ***/
371 EXTRACT_HELPER(crfD, 23, 3);
372 EXTRACT_HELPER(crfS, 18, 3);
373 EXTRACT_HELPER(crbD, 21, 5);
374 EXTRACT_HELPER(crbA, 16, 5);
375 EXTRACT_HELPER(crbB, 11, 5);
376 /* SPR / TBL */
377 EXTRACT_HELPER(_SPR, 11, 10);
378 static inline uint32_t SPR(uint32_t opcode)
379 {
380 uint32_t sprn = _SPR(opcode);
381
382 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
383 }
384 /*** Get constants ***/
385 EXTRACT_HELPER(IMM, 12, 8);
386 /* 16 bits signed immediate value */
387 EXTRACT_SHELPER(SIMM, 0, 16);
388 /* 16 bits unsigned immediate value */
389 EXTRACT_HELPER(UIMM, 0, 16);
390 /* 5 bits signed immediate value */
391 EXTRACT_HELPER(SIMM5, 16, 5);
392 /* 5 bits signed immediate value */
393 EXTRACT_HELPER(UIMM5, 16, 5);
394 /* Bit count */
395 EXTRACT_HELPER(NB, 11, 5);
396 /* Shift count */
397 EXTRACT_HELPER(SH, 11, 5);
398 /* Vector shift count */
399 EXTRACT_HELPER(VSH, 6, 4);
400 /* Mask start */
401 EXTRACT_HELPER(MB, 6, 5);
402 /* Mask end */
403 EXTRACT_HELPER(ME, 1, 5);
404 /* Trap operand */
405 EXTRACT_HELPER(TO, 21, 5);
406
407 EXTRACT_HELPER(CRM, 12, 8);
408 EXTRACT_HELPER(FM, 17, 8);
409 EXTRACT_HELPER(SR, 16, 4);
410 EXTRACT_HELPER(FPIMM, 12, 4);
411
412 /*** Jump target decoding ***/
413 /* Displacement */
414 EXTRACT_SHELPER(d, 0, 16);
415 /* Immediate address */
416 static inline target_ulong LI(uint32_t opcode)
417 {
418 return (opcode >> 0) & 0x03FFFFFC;
419 }
420
421 static inline uint32_t BD(uint32_t opcode)
422 {
423 return (opcode >> 0) & 0xFFFC;
424 }
425
426 EXTRACT_HELPER(BO, 21, 5);
427 EXTRACT_HELPER(BI, 16, 5);
428 /* Absolute/relative address */
429 EXTRACT_HELPER(AA, 1, 1);
430 /* Link */
431 EXTRACT_HELPER(LK, 0, 1);
432
433 /* Create a mask between <start> and <end> bits */
434 static inline target_ulong MASK(uint32_t start, uint32_t end)
435 {
436 target_ulong ret;
437
438 #if defined(TARGET_PPC64)
439 if (likely(start == 0)) {
440 ret = UINT64_MAX << (63 - end);
441 } else if (likely(end == 63)) {
442 ret = UINT64_MAX >> start;
443 }
444 #else
445 if (likely(start == 0)) {
446 ret = UINT32_MAX << (31 - end);
447 } else if (likely(end == 31)) {
448 ret = UINT32_MAX >> start;
449 }
450 #endif
451 else {
452 ret = (((target_ulong)(-1ULL)) >> (start)) ^
453 (((target_ulong)(-1ULL) >> (end)) >> 1);
454 if (unlikely(start > end))
455 return ~ret;
456 }
457
458 return ret;
459 }
460
461 /*****************************************************************************/
462 /* PowerPC instructions table */
463
464 #if defined(DO_PPC_STATISTICS)
465 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
466 { \
467 .opc1 = op1, \
468 .opc2 = op2, \
469 .opc3 = op3, \
470 .pad = { 0, }, \
471 .handler = { \
472 .inval = invl, \
473 .type = _typ, \
474 .type2 = _typ2, \
475 .handler = &gen_##name, \
476 .oname = stringify(name), \
477 }, \
478 .oname = stringify(name), \
479 }
480 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
481 { \
482 .opc1 = op1, \
483 .opc2 = op2, \
484 .opc3 = op3, \
485 .pad = { 0, }, \
486 .handler = { \
487 .inval = invl, \
488 .type = _typ, \
489 .type2 = _typ2, \
490 .handler = &gen_##name, \
491 .oname = onam, \
492 }, \
493 .oname = onam, \
494 }
495 #else
496 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
497 { \
498 .opc1 = op1, \
499 .opc2 = op2, \
500 .opc3 = op3, \
501 .pad = { 0, }, \
502 .handler = { \
503 .inval = invl, \
504 .type = _typ, \
505 .type2 = _typ2, \
506 .handler = &gen_##name, \
507 }, \
508 .oname = stringify(name), \
509 }
510 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
511 { \
512 .opc1 = op1, \
513 .opc2 = op2, \
514 .opc3 = op3, \
515 .pad = { 0, }, \
516 .handler = { \
517 .inval = invl, \
518 .type = _typ, \
519 .type2 = _typ2, \
520 .handler = &gen_##name, \
521 }, \
522 .oname = onam, \
523 }
524 #endif
525
526 /* SPR load/store helpers */
527 static inline void gen_load_spr(TCGv t, int reg)
528 {
529 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
530 }
531
532 static inline void gen_store_spr(int reg, TCGv t)
533 {
534 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
535 }
536
537 /* Invalid instruction */
538 static void gen_invalid(DisasContext *ctx)
539 {
540 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
541 }
542
543 static opc_handler_t invalid_handler = {
544 .inval = 0xFFFFFFFF,
545 .type = PPC_NONE,
546 .type2 = PPC_NONE,
547 .handler = gen_invalid,
548 };
549
550 /*** Integer comparison ***/
551
552 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
553 {
554 int l1, l2, l3;
555
556 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
557 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
558 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
559
560 l1 = gen_new_label();
561 l2 = gen_new_label();
562 l3 = gen_new_label();
563 if (s) {
564 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
565 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
566 } else {
567 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
568 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
569 }
570 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
571 tcg_gen_br(l3);
572 gen_set_label(l1);
573 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
574 tcg_gen_br(l3);
575 gen_set_label(l2);
576 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
577 gen_set_label(l3);
578 }
579
580 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
581 {
582 TCGv t0 = tcg_const_local_tl(arg1);
583 gen_op_cmp(arg0, t0, s, crf);
584 tcg_temp_free(t0);
585 }
586
587 #if defined(TARGET_PPC64)
588 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
589 {
590 TCGv t0, t1;
591 t0 = tcg_temp_local_new();
592 t1 = tcg_temp_local_new();
593 if (s) {
594 tcg_gen_ext32s_tl(t0, arg0);
595 tcg_gen_ext32s_tl(t1, arg1);
596 } else {
597 tcg_gen_ext32u_tl(t0, arg0);
598 tcg_gen_ext32u_tl(t1, arg1);
599 }
600 gen_op_cmp(t0, t1, s, crf);
601 tcg_temp_free(t1);
602 tcg_temp_free(t0);
603 }
604
605 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
606 {
607 TCGv t0 = tcg_const_local_tl(arg1);
608 gen_op_cmp32(arg0, t0, s, crf);
609 tcg_temp_free(t0);
610 }
611 #endif
612
613 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
614 {
615 #if defined(TARGET_PPC64)
616 if (!(ctx->sf_mode))
617 gen_op_cmpi32(reg, 0, 1, 0);
618 else
619 #endif
620 gen_op_cmpi(reg, 0, 1, 0);
621 }
622
623 /* cmp */
624 static void gen_cmp(DisasContext *ctx)
625 {
626 #if defined(TARGET_PPC64)
627 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
628 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
629 1, crfD(ctx->opcode));
630 else
631 #endif
632 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
633 1, crfD(ctx->opcode));
634 }
635
636 /* cmpi */
637 static void gen_cmpi(DisasContext *ctx)
638 {
639 #if defined(TARGET_PPC64)
640 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
641 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
642 1, crfD(ctx->opcode));
643 else
644 #endif
645 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
646 1, crfD(ctx->opcode));
647 }
648
649 /* cmpl */
650 static void gen_cmpl(DisasContext *ctx)
651 {
652 #if defined(TARGET_PPC64)
653 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
654 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
655 0, crfD(ctx->opcode));
656 else
657 #endif
658 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
659 0, crfD(ctx->opcode));
660 }
661
662 /* cmpli */
663 static void gen_cmpli(DisasContext *ctx)
664 {
665 #if defined(TARGET_PPC64)
666 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
667 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
668 0, crfD(ctx->opcode));
669 else
670 #endif
671 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
672 0, crfD(ctx->opcode));
673 }
674
675 /* isel (PowerPC 2.03 specification) */
676 static void gen_isel(DisasContext *ctx)
677 {
678 int l1, l2;
679 uint32_t bi = rC(ctx->opcode);
680 uint32_t mask;
681 TCGv_i32 t0;
682
683 l1 = gen_new_label();
684 l2 = gen_new_label();
685
686 mask = 1 << (3 - (bi & 0x03));
687 t0 = tcg_temp_new_i32();
688 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
689 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
690 if (rA(ctx->opcode) == 0)
691 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
692 else
693 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
694 tcg_gen_br(l2);
695 gen_set_label(l1);
696 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
697 gen_set_label(l2);
698 tcg_temp_free_i32(t0);
699 }
700
701 /*** Integer arithmetic ***/
702
703 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
704 TCGv arg1, TCGv arg2, int sub)
705 {
706 int l1;
707 TCGv t0;
708
709 l1 = gen_new_label();
710 /* Start with XER OV disabled, the most likely case */
711 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
712 t0 = tcg_temp_local_new();
713 tcg_gen_xor_tl(t0, arg0, arg1);
714 #if defined(TARGET_PPC64)
715 if (!ctx->sf_mode)
716 tcg_gen_ext32s_tl(t0, t0);
717 #endif
718 if (sub)
719 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
720 else
721 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
722 tcg_gen_xor_tl(t0, arg1, arg2);
723 #if defined(TARGET_PPC64)
724 if (!ctx->sf_mode)
725 tcg_gen_ext32s_tl(t0, t0);
726 #endif
727 if (sub)
728 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
729 else
730 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
731 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
732 gen_set_label(l1);
733 tcg_temp_free(t0);
734 }
735
736 static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
737 TCGv arg2, int sub)
738 {
739 int l1 = gen_new_label();
740
741 #if defined(TARGET_PPC64)
742 if (!(ctx->sf_mode)) {
743 TCGv t0, t1;
744 t0 = tcg_temp_new();
745 t1 = tcg_temp_new();
746
747 tcg_gen_ext32u_tl(t0, arg1);
748 tcg_gen_ext32u_tl(t1, arg2);
749 if (sub) {
750 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
751 } else {
752 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
753 }
754 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
755 gen_set_label(l1);
756 tcg_temp_free(t0);
757 tcg_temp_free(t1);
758 } else
759 #endif
760 {
761 if (sub) {
762 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
763 } else {
764 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
765 }
766 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
767 gen_set_label(l1);
768 }
769 }
770
771 /* Common add function */
772 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
773 TCGv arg2, int add_ca, int compute_ca,
774 int compute_ov)
775 {
776 TCGv t0, t1;
777
778 if ((!compute_ca && !compute_ov) ||
779 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
780 t0 = ret;
781 } else {
782 t0 = tcg_temp_local_new();
783 }
784
785 if (add_ca) {
786 t1 = tcg_temp_local_new();
787 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
788 tcg_gen_shri_tl(t1, t1, XER_CA);
789 } else {
790 TCGV_UNUSED(t1);
791 }
792
793 if (compute_ca && compute_ov) {
794 /* Start with XER CA and OV disabled, the most likely case */
795 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
796 } else if (compute_ca) {
797 /* Start with XER CA disabled, the most likely case */
798 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
799 } else if (compute_ov) {
800 /* Start with XER OV disabled, the most likely case */
801 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
802 }
803
804 tcg_gen_add_tl(t0, arg1, arg2);
805
806 if (compute_ca) {
807 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
808 }
809 if (add_ca) {
810 tcg_gen_add_tl(t0, t0, t1);
811 gen_op_arith_compute_ca(ctx, t0, t1, 0);
812 tcg_temp_free(t1);
813 }
814 if (compute_ov) {
815 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
816 }
817
818 if (unlikely(Rc(ctx->opcode) != 0))
819 gen_set_Rc0(ctx, t0);
820
821 if (!TCGV_EQUAL(t0, ret)) {
822 tcg_gen_mov_tl(ret, t0);
823 tcg_temp_free(t0);
824 }
825 }
826 /* Add functions with two operands */
827 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
828 static void glue(gen_, name)(DisasContext *ctx) \
829 { \
830 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
831 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
832 add_ca, compute_ca, compute_ov); \
833 }
834 /* Add functions with one operand and one immediate */
835 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
836 add_ca, compute_ca, compute_ov) \
837 static void glue(gen_, name)(DisasContext *ctx) \
838 { \
839 TCGv t0 = tcg_const_local_tl(const_val); \
840 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
841 cpu_gpr[rA(ctx->opcode)], t0, \
842 add_ca, compute_ca, compute_ov); \
843 tcg_temp_free(t0); \
844 }
845
846 /* add add. addo addo. */
847 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
848 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
849 /* addc addc. addco addco. */
850 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
851 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
852 /* adde adde. addeo addeo. */
853 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
854 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
855 /* addme addme. addmeo addmeo. */
856 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
857 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
858 /* addze addze. addzeo addzeo.*/
859 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
860 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
861 /* addi */
862 static void gen_addi(DisasContext *ctx)
863 {
864 target_long simm = SIMM(ctx->opcode);
865
866 if (rA(ctx->opcode) == 0) {
867 /* li case */
868 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
869 } else {
870 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
871 }
872 }
873 /* addic addic.*/
874 static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
875 int compute_Rc0)
876 {
877 target_long simm = SIMM(ctx->opcode);
878
879 /* Start with XER CA and OV disabled, the most likely case */
880 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
881
882 if (likely(simm != 0)) {
883 TCGv t0 = tcg_temp_local_new();
884 tcg_gen_addi_tl(t0, arg1, simm);
885 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
886 tcg_gen_mov_tl(ret, t0);
887 tcg_temp_free(t0);
888 } else {
889 tcg_gen_mov_tl(ret, arg1);
890 }
891 if (compute_Rc0) {
892 gen_set_Rc0(ctx, ret);
893 }
894 }
895
896 static void gen_addic(DisasContext *ctx)
897 {
898 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
899 }
900
901 static void gen_addic_(DisasContext *ctx)
902 {
903 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
904 }
905
906 /* addis */
907 static void gen_addis(DisasContext *ctx)
908 {
909 target_long simm = SIMM(ctx->opcode);
910
911 if (rA(ctx->opcode) == 0) {
912 /* lis case */
913 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
914 } else {
915 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
916 }
917 }
918
919 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
920 TCGv arg2, int sign, int compute_ov)
921 {
922 int l1 = gen_new_label();
923 int l2 = gen_new_label();
924 TCGv_i32 t0 = tcg_temp_local_new_i32();
925 TCGv_i32 t1 = tcg_temp_local_new_i32();
926
927 tcg_gen_trunc_tl_i32(t0, arg1);
928 tcg_gen_trunc_tl_i32(t1, arg2);
929 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
930 if (sign) {
931 int l3 = gen_new_label();
932 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
933 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
934 gen_set_label(l3);
935 tcg_gen_div_i32(t0, t0, t1);
936 } else {
937 tcg_gen_divu_i32(t0, t0, t1);
938 }
939 if (compute_ov) {
940 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
941 }
942 tcg_gen_br(l2);
943 gen_set_label(l1);
944 if (sign) {
945 tcg_gen_sari_i32(t0, t0, 31);
946 } else {
947 tcg_gen_movi_i32(t0, 0);
948 }
949 if (compute_ov) {
950 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
951 }
952 gen_set_label(l2);
953 tcg_gen_extu_i32_tl(ret, t0);
954 tcg_temp_free_i32(t0);
955 tcg_temp_free_i32(t1);
956 if (unlikely(Rc(ctx->opcode) != 0))
957 gen_set_Rc0(ctx, ret);
958 }
959 /* Div functions */
960 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
961 static void glue(gen_, name)(DisasContext *ctx) \
962 { \
963 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
964 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
965 sign, compute_ov); \
966 }
967 /* divwu divwu. divwuo divwuo. */
968 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
969 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
970 /* divw divw. divwo divwo. */
971 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
972 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
973 #if defined(TARGET_PPC64)
974 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
975 TCGv arg2, int sign, int compute_ov)
976 {
977 int l1 = gen_new_label();
978 int l2 = gen_new_label();
979
980 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
981 if (sign) {
982 int l3 = gen_new_label();
983 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
984 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
985 gen_set_label(l3);
986 tcg_gen_div_i64(ret, arg1, arg2);
987 } else {
988 tcg_gen_divu_i64(ret, arg1, arg2);
989 }
990 if (compute_ov) {
991 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
992 }
993 tcg_gen_br(l2);
994 gen_set_label(l1);
995 if (sign) {
996 tcg_gen_sari_i64(ret, arg1, 63);
997 } else {
998 tcg_gen_movi_i64(ret, 0);
999 }
1000 if (compute_ov) {
1001 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1002 }
1003 gen_set_label(l2);
1004 if (unlikely(Rc(ctx->opcode) != 0))
1005 gen_set_Rc0(ctx, ret);
1006 }
1007 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1008 static void glue(gen_, name)(DisasContext *ctx) \
1009 { \
1010 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1011 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1012 sign, compute_ov); \
1013 }
1014 /* divwu divwu. divwuo divwuo. */
1015 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1016 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1017 /* divw divw. divwo divwo. */
1018 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1019 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1020 #endif
1021
1022 /* mulhw mulhw. */
1023 static void gen_mulhw(DisasContext *ctx)
1024 {
1025 TCGv_i64 t0, t1;
1026
1027 t0 = tcg_temp_new_i64();
1028 t1 = tcg_temp_new_i64();
1029 #if defined(TARGET_PPC64)
1030 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1031 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1032 tcg_gen_mul_i64(t0, t0, t1);
1033 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1034 #else
1035 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1036 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1037 tcg_gen_mul_i64(t0, t0, t1);
1038 tcg_gen_shri_i64(t0, t0, 32);
1039 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1040 #endif
1041 tcg_temp_free_i64(t0);
1042 tcg_temp_free_i64(t1);
1043 if (unlikely(Rc(ctx->opcode) != 0))
1044 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1045 }
1046
1047 /* mulhwu mulhwu. */
1048 static void gen_mulhwu(DisasContext *ctx)
1049 {
1050 TCGv_i64 t0, t1;
1051
1052 t0 = tcg_temp_new_i64();
1053 t1 = tcg_temp_new_i64();
1054 #if defined(TARGET_PPC64)
1055 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1056 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1057 tcg_gen_mul_i64(t0, t0, t1);
1058 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1059 #else
1060 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1061 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1062 tcg_gen_mul_i64(t0, t0, t1);
1063 tcg_gen_shri_i64(t0, t0, 32);
1064 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1065 #endif
1066 tcg_temp_free_i64(t0);
1067 tcg_temp_free_i64(t1);
1068 if (unlikely(Rc(ctx->opcode) != 0))
1069 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1070 }
1071
1072 /* mullw mullw. */
1073 static void gen_mullw(DisasContext *ctx)
1074 {
1075 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1076 cpu_gpr[rB(ctx->opcode)]);
1077 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1078 if (unlikely(Rc(ctx->opcode) != 0))
1079 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1080 }
1081
1082 /* mullwo mullwo. */
1083 static void gen_mullwo(DisasContext *ctx)
1084 {
1085 int l1;
1086 TCGv_i64 t0, t1;
1087
1088 t0 = tcg_temp_new_i64();
1089 t1 = tcg_temp_new_i64();
1090 l1 = gen_new_label();
1091 /* Start with XER OV disabled, the most likely case */
1092 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1093 #if defined(TARGET_PPC64)
1094 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1095 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1096 #else
1097 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1098 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1099 #endif
1100 tcg_gen_mul_i64(t0, t0, t1);
1101 #if defined(TARGET_PPC64)
1102 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1103 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1104 #else
1105 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1106 tcg_gen_ext32s_i64(t1, t0);
1107 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1108 #endif
1109 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1110 gen_set_label(l1);
1111 tcg_temp_free_i64(t0);
1112 tcg_temp_free_i64(t1);
1113 if (unlikely(Rc(ctx->opcode) != 0))
1114 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1115 }
1116
1117 /* mulli */
1118 static void gen_mulli(DisasContext *ctx)
1119 {
1120 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1121 SIMM(ctx->opcode));
1122 }
1123 #if defined(TARGET_PPC64)
1124 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1125 static void glue(gen_, name)(DisasContext *ctx) \
1126 { \
1127 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1128 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1129 if (unlikely(Rc(ctx->opcode) != 0)) \
1130 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1131 }
1132 /* mulhd mulhd. */
1133 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1134 /* mulhdu mulhdu. */
1135 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1136
1137 /* mulld mulld. */
1138 static void gen_mulld(DisasContext *ctx)
1139 {
1140 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1141 cpu_gpr[rB(ctx->opcode)]);
1142 if (unlikely(Rc(ctx->opcode) != 0))
1143 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1144 }
1145 /* mulldo mulldo. */
1146 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1147 #endif
1148
1149 /* neg neg. nego nego. */
1150 static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1151 int ov_check)
1152 {
1153 int l1 = gen_new_label();
1154 int l2 = gen_new_label();
1155 TCGv t0 = tcg_temp_local_new();
1156 #if defined(TARGET_PPC64)
1157 if (ctx->sf_mode) {
1158 tcg_gen_mov_tl(t0, arg1);
1159 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1160 } else
1161 #endif
1162 {
1163 tcg_gen_ext32s_tl(t0, arg1);
1164 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1165 }
1166 tcg_gen_neg_tl(ret, arg1);
1167 if (ov_check) {
1168 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1169 }
1170 tcg_gen_br(l2);
1171 gen_set_label(l1);
1172 tcg_gen_mov_tl(ret, t0);
1173 if (ov_check) {
1174 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1175 }
1176 gen_set_label(l2);
1177 tcg_temp_free(t0);
1178 if (unlikely(Rc(ctx->opcode) != 0))
1179 gen_set_Rc0(ctx, ret);
1180 }
1181
1182 static void gen_neg(DisasContext *ctx)
1183 {
1184 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1185 }
1186
1187 static void gen_nego(DisasContext *ctx)
1188 {
1189 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1190 }
1191
1192 /* Common subf function */
1193 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1194 TCGv arg2, int add_ca, int compute_ca,
1195 int compute_ov)
1196 {
1197 TCGv t0, t1;
1198
1199 if ((!compute_ca && !compute_ov) ||
1200 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1201 t0 = ret;
1202 } else {
1203 t0 = tcg_temp_local_new();
1204 }
1205
1206 if (add_ca) {
1207 t1 = tcg_temp_local_new();
1208 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1209 tcg_gen_shri_tl(t1, t1, XER_CA);
1210 } else {
1211 TCGV_UNUSED(t1);
1212 }
1213
1214 if (compute_ca && compute_ov) {
1215 /* Start with XER CA and OV disabled, the most likely case */
1216 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1217 } else if (compute_ca) {
1218 /* Start with XER CA disabled, the most likely case */
1219 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1220 } else if (compute_ov) {
1221 /* Start with XER OV disabled, the most likely case */
1222 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1223 }
1224
1225 if (add_ca) {
1226 tcg_gen_not_tl(t0, arg1);
1227 tcg_gen_add_tl(t0, t0, arg2);
1228 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1229 tcg_gen_add_tl(t0, t0, t1);
1230 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1231 tcg_temp_free(t1);
1232 } else {
1233 tcg_gen_sub_tl(t0, arg2, arg1);
1234 if (compute_ca) {
1235 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1236 }
1237 }
1238 if (compute_ov) {
1239 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1240 }
1241
1242 if (unlikely(Rc(ctx->opcode) != 0))
1243 gen_set_Rc0(ctx, t0);
1244
1245 if (!TCGV_EQUAL(t0, ret)) {
1246 tcg_gen_mov_tl(ret, t0);
1247 tcg_temp_free(t0);
1248 }
1249 }
1250 /* Sub functions with Two operands functions */
1251 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1252 static void glue(gen_, name)(DisasContext *ctx) \
1253 { \
1254 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1255 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1256 add_ca, compute_ca, compute_ov); \
1257 }
1258 /* Sub functions with one operand and one immediate */
1259 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1260 add_ca, compute_ca, compute_ov) \
1261 static void glue(gen_, name)(DisasContext *ctx) \
1262 { \
1263 TCGv t0 = tcg_const_local_tl(const_val); \
1264 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1265 cpu_gpr[rA(ctx->opcode)], t0, \
1266 add_ca, compute_ca, compute_ov); \
1267 tcg_temp_free(t0); \
1268 }
1269 /* subf subf. subfo subfo. */
1270 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1271 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1272 /* subfc subfc. subfco subfco. */
1273 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1274 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1275 /* subfe subfe. subfeo subfo. */
1276 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1277 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1278 /* subfme subfme. subfmeo subfmeo. */
1279 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1280 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1281 /* subfze subfze. subfzeo subfzeo.*/
1282 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1283 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1284
1285 /* subfic */
1286 static void gen_subfic(DisasContext *ctx)
1287 {
1288 /* Start with XER CA and OV disabled, the most likely case */
1289 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1290 TCGv t0 = tcg_temp_local_new();
1291 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1292 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1293 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1294 tcg_temp_free(t1);
1295 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1296 tcg_temp_free(t0);
1297 }
1298
1299 /*** Integer logical ***/
1300 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1301 static void glue(gen_, name)(DisasContext *ctx) \
1302 { \
1303 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1304 cpu_gpr[rB(ctx->opcode)]); \
1305 if (unlikely(Rc(ctx->opcode) != 0)) \
1306 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1307 }
1308
1309 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1310 static void glue(gen_, name)(DisasContext *ctx) \
1311 { \
1312 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1313 if (unlikely(Rc(ctx->opcode) != 0)) \
1314 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1315 }
1316
1317 /* and & and. */
1318 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1319 /* andc & andc. */
1320 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1321
1322 /* andi. */
1323 static void gen_andi_(DisasContext *ctx)
1324 {
1325 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1326 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1327 }
1328
1329 /* andis. */
1330 static void gen_andis_(DisasContext *ctx)
1331 {
1332 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1333 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1334 }
1335
1336 /* cntlzw */
1337 static void gen_cntlzw(DisasContext *ctx)
1338 {
1339 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1340 if (unlikely(Rc(ctx->opcode) != 0))
1341 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1342 }
1343 /* eqv & eqv. */
1344 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1345 /* extsb & extsb. */
1346 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1347 /* extsh & extsh. */
1348 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1349 /* nand & nand. */
1350 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1351 /* nor & nor. */
1352 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1353
1354 /* or & or. */
1355 static void gen_or(DisasContext *ctx)
1356 {
1357 int rs, ra, rb;
1358
1359 rs = rS(ctx->opcode);
1360 ra = rA(ctx->opcode);
1361 rb = rB(ctx->opcode);
1362 /* Optimisation for mr. ri case */
1363 if (rs != ra || rs != rb) {
1364 if (rs != rb)
1365 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1366 else
1367 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1368 if (unlikely(Rc(ctx->opcode) != 0))
1369 gen_set_Rc0(ctx, cpu_gpr[ra]);
1370 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1371 gen_set_Rc0(ctx, cpu_gpr[rs]);
1372 #if defined(TARGET_PPC64)
1373 } else {
1374 int prio = 0;
1375
1376 switch (rs) {
1377 case 1:
1378 /* Set process priority to low */
1379 prio = 2;
1380 break;
1381 case 6:
1382 /* Set process priority to medium-low */
1383 prio = 3;
1384 break;
1385 case 2:
1386 /* Set process priority to normal */
1387 prio = 4;
1388 break;
1389 #if !defined(CONFIG_USER_ONLY)
1390 case 31:
1391 if (ctx->mem_idx > 0) {
1392 /* Set process priority to very low */
1393 prio = 1;
1394 }
1395 break;
1396 case 5:
1397 if (ctx->mem_idx > 0) {
1398 /* Set process priority to medium-hight */
1399 prio = 5;
1400 }
1401 break;
1402 case 3:
1403 if (ctx->mem_idx > 0) {
1404 /* Set process priority to high */
1405 prio = 6;
1406 }
1407 break;
1408 case 7:
1409 if (ctx->mem_idx > 1) {
1410 /* Set process priority to very high */
1411 prio = 7;
1412 }
1413 break;
1414 #endif
1415 default:
1416 /* nop */
1417 break;
1418 }
1419 if (prio) {
1420 TCGv t0 = tcg_temp_new();
1421 gen_load_spr(t0, SPR_PPR);
1422 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1423 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1424 gen_store_spr(SPR_PPR, t0);
1425 tcg_temp_free(t0);
1426 }
1427 #endif
1428 }
1429 }
1430 /* orc & orc. */
1431 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1432
1433 /* xor & xor. */
1434 static void gen_xor(DisasContext *ctx)
1435 {
1436 /* Optimisation for "set to zero" case */
1437 if (rS(ctx->opcode) != rB(ctx->opcode))
1438 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1439 else
1440 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1441 if (unlikely(Rc(ctx->opcode) != 0))
1442 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1443 }
1444
1445 /* ori */
1446 static void gen_ori(DisasContext *ctx)
1447 {
1448 target_ulong uimm = UIMM(ctx->opcode);
1449
1450 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1451 /* NOP */
1452 /* XXX: should handle special NOPs for POWER series */
1453 return;
1454 }
1455 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1456 }
1457
1458 /* oris */
1459 static void gen_oris(DisasContext *ctx)
1460 {
1461 target_ulong uimm = UIMM(ctx->opcode);
1462
1463 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1464 /* NOP */
1465 return;
1466 }
1467 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1468 }
1469
1470 /* xori */
1471 static void gen_xori(DisasContext *ctx)
1472 {
1473 target_ulong uimm = UIMM(ctx->opcode);
1474
1475 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1476 /* NOP */
1477 return;
1478 }
1479 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1480 }
1481
1482 /* xoris */
1483 static void gen_xoris(DisasContext *ctx)
1484 {
1485 target_ulong uimm = UIMM(ctx->opcode);
1486
1487 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1488 /* NOP */
1489 return;
1490 }
1491 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1492 }
1493
1494 /* popcntb : PowerPC 2.03 specification */
1495 static void gen_popcntb(DisasContext *ctx)
1496 {
1497 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1498 }
1499
1500 static void gen_popcntw(DisasContext *ctx)
1501 {
1502 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1503 }
1504
1505 #if defined(TARGET_PPC64)
1506 /* popcntd: PowerPC 2.06 specification */
1507 static void gen_popcntd(DisasContext *ctx)
1508 {
1509 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1510 }
1511 #endif
1512
1513 #if defined(TARGET_PPC64)
1514 /* extsw & extsw. */
1515 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1516
1517 /* cntlzd */
1518 static void gen_cntlzd(DisasContext *ctx)
1519 {
1520 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1521 if (unlikely(Rc(ctx->opcode) != 0))
1522 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1523 }
1524 #endif
1525
1526 /*** Integer rotate ***/
1527
1528 /* rlwimi & rlwimi. */
1529 static void gen_rlwimi(DisasContext *ctx)
1530 {
1531 uint32_t mb, me, sh;
1532
1533 mb = MB(ctx->opcode);
1534 me = ME(ctx->opcode);
1535 sh = SH(ctx->opcode);
1536 if (likely(sh == 0 && mb == 0 && me == 31)) {
1537 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1538 } else {
1539 target_ulong mask;
1540 TCGv t1;
1541 TCGv t0 = tcg_temp_new();
1542 #if defined(TARGET_PPC64)
1543 TCGv_i32 t2 = tcg_temp_new_i32();
1544 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1545 tcg_gen_rotli_i32(t2, t2, sh);
1546 tcg_gen_extu_i32_i64(t0, t2);
1547 tcg_temp_free_i32(t2);
1548 #else
1549 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1550 #endif
1551 #if defined(TARGET_PPC64)
1552 mb += 32;
1553 me += 32;
1554 #endif
1555 mask = MASK(mb, me);
1556 t1 = tcg_temp_new();
1557 tcg_gen_andi_tl(t0, t0, mask);
1558 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1559 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1560 tcg_temp_free(t0);
1561 tcg_temp_free(t1);
1562 }
1563 if (unlikely(Rc(ctx->opcode) != 0))
1564 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1565 }
1566
1567 /* rlwinm & rlwinm. */
1568 static void gen_rlwinm(DisasContext *ctx)
1569 {
1570 uint32_t mb, me, sh;
1571
1572 sh = SH(ctx->opcode);
1573 mb = MB(ctx->opcode);
1574 me = ME(ctx->opcode);
1575
1576 if (likely(mb == 0 && me == (31 - sh))) {
1577 if (likely(sh == 0)) {
1578 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1579 } else {
1580 TCGv t0 = tcg_temp_new();
1581 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1582 tcg_gen_shli_tl(t0, t0, sh);
1583 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1584 tcg_temp_free(t0);
1585 }
1586 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1587 TCGv t0 = tcg_temp_new();
1588 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1589 tcg_gen_shri_tl(t0, t0, mb);
1590 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1591 tcg_temp_free(t0);
1592 } else {
1593 TCGv t0 = tcg_temp_new();
1594 #if defined(TARGET_PPC64)
1595 TCGv_i32 t1 = tcg_temp_new_i32();
1596 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1597 tcg_gen_rotli_i32(t1, t1, sh);
1598 tcg_gen_extu_i32_i64(t0, t1);
1599 tcg_temp_free_i32(t1);
1600 #else
1601 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1602 #endif
1603 #if defined(TARGET_PPC64)
1604 mb += 32;
1605 me += 32;
1606 #endif
1607 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1608 tcg_temp_free(t0);
1609 }
1610 if (unlikely(Rc(ctx->opcode) != 0))
1611 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1612 }
1613
1614 /* rlwnm & rlwnm. */
1615 static void gen_rlwnm(DisasContext *ctx)
1616 {
1617 uint32_t mb, me;
1618 TCGv t0;
1619 #if defined(TARGET_PPC64)
1620 TCGv_i32 t1, t2;
1621 #endif
1622
1623 mb = MB(ctx->opcode);
1624 me = ME(ctx->opcode);
1625 t0 = tcg_temp_new();
1626 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1627 #if defined(TARGET_PPC64)
1628 t1 = tcg_temp_new_i32();
1629 t2 = tcg_temp_new_i32();
1630 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1631 tcg_gen_trunc_i64_i32(t2, t0);
1632 tcg_gen_rotl_i32(t1, t1, t2);
1633 tcg_gen_extu_i32_i64(t0, t1);
1634 tcg_temp_free_i32(t1);
1635 tcg_temp_free_i32(t2);
1636 #else
1637 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1638 #endif
1639 if (unlikely(mb != 0 || me != 31)) {
1640 #if defined(TARGET_PPC64)
1641 mb += 32;
1642 me += 32;
1643 #endif
1644 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1645 } else {
1646 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1647 }
1648 tcg_temp_free(t0);
1649 if (unlikely(Rc(ctx->opcode) != 0))
1650 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1651 }
1652
1653 #if defined(TARGET_PPC64)
1654 #define GEN_PPC64_R2(name, opc1, opc2) \
1655 static void glue(gen_, name##0)(DisasContext *ctx) \
1656 { \
1657 gen_##name(ctx, 0); \
1658 } \
1659 \
1660 static void glue(gen_, name##1)(DisasContext *ctx) \
1661 { \
1662 gen_##name(ctx, 1); \
1663 }
1664 #define GEN_PPC64_R4(name, opc1, opc2) \
1665 static void glue(gen_, name##0)(DisasContext *ctx) \
1666 { \
1667 gen_##name(ctx, 0, 0); \
1668 } \
1669 \
1670 static void glue(gen_, name##1)(DisasContext *ctx) \
1671 { \
1672 gen_##name(ctx, 0, 1); \
1673 } \
1674 \
1675 static void glue(gen_, name##2)(DisasContext *ctx) \
1676 { \
1677 gen_##name(ctx, 1, 0); \
1678 } \
1679 \
1680 static void glue(gen_, name##3)(DisasContext *ctx) \
1681 { \
1682 gen_##name(ctx, 1, 1); \
1683 }
1684
1685 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1686 uint32_t sh)
1687 {
1688 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1689 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1690 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1691 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1692 } else {
1693 TCGv t0 = tcg_temp_new();
1694 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1695 if (likely(mb == 0 && me == 63)) {
1696 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1697 } else {
1698 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1699 }
1700 tcg_temp_free(t0);
1701 }
1702 if (unlikely(Rc(ctx->opcode) != 0))
1703 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1704 }
1705 /* rldicl - rldicl. */
1706 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1707 {
1708 uint32_t sh, mb;
1709
1710 sh = SH(ctx->opcode) | (shn << 5);
1711 mb = MB(ctx->opcode) | (mbn << 5);
1712 gen_rldinm(ctx, mb, 63, sh);
1713 }
1714 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1715 /* rldicr - rldicr. */
1716 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1717 {
1718 uint32_t sh, me;
1719
1720 sh = SH(ctx->opcode) | (shn << 5);
1721 me = MB(ctx->opcode) | (men << 5);
1722 gen_rldinm(ctx, 0, me, sh);
1723 }
1724 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1725 /* rldic - rldic. */
1726 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1727 {
1728 uint32_t sh, mb;
1729
1730 sh = SH(ctx->opcode) | (shn << 5);
1731 mb = MB(ctx->opcode) | (mbn << 5);
1732 gen_rldinm(ctx, mb, 63 - sh, sh);
1733 }
1734 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1735
1736 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1737 {
1738 TCGv t0;
1739
1740 mb = MB(ctx->opcode);
1741 me = ME(ctx->opcode);
1742 t0 = tcg_temp_new();
1743 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1744 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1745 if (unlikely(mb != 0 || me != 63)) {
1746 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1747 } else {
1748 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1749 }
1750 tcg_temp_free(t0);
1751 if (unlikely(Rc(ctx->opcode) != 0))
1752 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1753 }
1754
1755 /* rldcl - rldcl. */
1756 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1757 {
1758 uint32_t mb;
1759
1760 mb = MB(ctx->opcode) | (mbn << 5);
1761 gen_rldnm(ctx, mb, 63);
1762 }
1763 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1764 /* rldcr - rldcr. */
1765 static inline void gen_rldcr(DisasContext *ctx, int men)
1766 {
1767 uint32_t me;
1768
1769 me = MB(ctx->opcode) | (men << 5);
1770 gen_rldnm(ctx, 0, me);
1771 }
1772 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1773 /* rldimi - rldimi. */
1774 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1775 {
1776 uint32_t sh, mb, me;
1777
1778 sh = SH(ctx->opcode) | (shn << 5);
1779 mb = MB(ctx->opcode) | (mbn << 5);
1780 me = 63 - sh;
1781 if (unlikely(sh == 0 && mb == 0)) {
1782 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1783 } else {
1784 TCGv t0, t1;
1785 target_ulong mask;
1786
1787 t0 = tcg_temp_new();
1788 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1789 t1 = tcg_temp_new();
1790 mask = MASK(mb, me);
1791 tcg_gen_andi_tl(t0, t0, mask);
1792 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1793 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1794 tcg_temp_free(t0);
1795 tcg_temp_free(t1);
1796 }
1797 if (unlikely(Rc(ctx->opcode) != 0))
1798 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1799 }
1800 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1801 #endif
1802
1803 /*** Integer shift ***/
1804
1805 /* slw & slw. */
1806 static void gen_slw(DisasContext *ctx)
1807 {
1808 TCGv t0, t1;
1809
1810 t0 = tcg_temp_new();
1811 /* AND rS with a mask that is 0 when rB >= 0x20 */
1812 #if defined(TARGET_PPC64)
1813 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1814 tcg_gen_sari_tl(t0, t0, 0x3f);
1815 #else
1816 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1817 tcg_gen_sari_tl(t0, t0, 0x1f);
1818 #endif
1819 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1820 t1 = tcg_temp_new();
1821 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1822 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1823 tcg_temp_free(t1);
1824 tcg_temp_free(t0);
1825 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1826 if (unlikely(Rc(ctx->opcode) != 0))
1827 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1828 }
1829
1830 /* sraw & sraw. */
1831 static void gen_sraw(DisasContext *ctx)
1832 {
1833 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1834 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1835 if (unlikely(Rc(ctx->opcode) != 0))
1836 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1837 }
1838
1839 /* srawi & srawi. */
1840 static void gen_srawi(DisasContext *ctx)
1841 {
1842 int sh = SH(ctx->opcode);
1843 if (sh != 0) {
1844 int l1, l2;
1845 TCGv t0;
1846 l1 = gen_new_label();
1847 l2 = gen_new_label();
1848 t0 = tcg_temp_local_new();
1849 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1850 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1851 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1852 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1853 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1854 tcg_gen_br(l2);
1855 gen_set_label(l1);
1856 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1857 gen_set_label(l2);
1858 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1859 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1860 tcg_temp_free(t0);
1861 } else {
1862 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1863 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1864 }
1865 if (unlikely(Rc(ctx->opcode) != 0))
1866 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1867 }
1868
1869 /* srw & srw. */
1870 static void gen_srw(DisasContext *ctx)
1871 {
1872 TCGv t0, t1;
1873
1874 t0 = tcg_temp_new();
1875 /* AND rS with a mask that is 0 when rB >= 0x20 */
1876 #if defined(TARGET_PPC64)
1877 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1878 tcg_gen_sari_tl(t0, t0, 0x3f);
1879 #else
1880 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1881 tcg_gen_sari_tl(t0, t0, 0x1f);
1882 #endif
1883 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1884 tcg_gen_ext32u_tl(t0, t0);
1885 t1 = tcg_temp_new();
1886 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1887 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1888 tcg_temp_free(t1);
1889 tcg_temp_free(t0);
1890 if (unlikely(Rc(ctx->opcode) != 0))
1891 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1892 }
1893
1894 #if defined(TARGET_PPC64)
1895 /* sld & sld. */
1896 static void gen_sld(DisasContext *ctx)
1897 {
1898 TCGv t0, t1;
1899
1900 t0 = tcg_temp_new();
1901 /* AND rS with a mask that is 0 when rB >= 0x40 */
1902 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1903 tcg_gen_sari_tl(t0, t0, 0x3f);
1904 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1905 t1 = tcg_temp_new();
1906 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1907 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1908 tcg_temp_free(t1);
1909 tcg_temp_free(t0);
1910 if (unlikely(Rc(ctx->opcode) != 0))
1911 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1912 }
1913
1914 /* srad & srad. */
1915 static void gen_srad(DisasContext *ctx)
1916 {
1917 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
1918 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1919 if (unlikely(Rc(ctx->opcode) != 0))
1920 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1921 }
1922 /* sradi & sradi. */
1923 static inline void gen_sradi(DisasContext *ctx, int n)
1924 {
1925 int sh = SH(ctx->opcode) + (n << 5);
1926 if (sh != 0) {
1927 int l1, l2;
1928 TCGv t0;
1929 l1 = gen_new_label();
1930 l2 = gen_new_label();
1931 t0 = tcg_temp_local_new();
1932 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1933 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1934 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1935 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1936 tcg_gen_br(l2);
1937 gen_set_label(l1);
1938 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1939 gen_set_label(l2);
1940 tcg_temp_free(t0);
1941 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1942 } else {
1943 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1944 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1945 }
1946 if (unlikely(Rc(ctx->opcode) != 0))
1947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1948 }
1949
1950 static void gen_sradi0(DisasContext *ctx)
1951 {
1952 gen_sradi(ctx, 0);
1953 }
1954
1955 static void gen_sradi1(DisasContext *ctx)
1956 {
1957 gen_sradi(ctx, 1);
1958 }
1959
1960 /* srd & srd. */
1961 static void gen_srd(DisasContext *ctx)
1962 {
1963 TCGv t0, t1;
1964
1965 t0 = tcg_temp_new();
1966 /* AND rS with a mask that is 0 when rB >= 0x40 */
1967 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1968 tcg_gen_sari_tl(t0, t0, 0x3f);
1969 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1970 t1 = tcg_temp_new();
1971 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1972 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1973 tcg_temp_free(t1);
1974 tcg_temp_free(t0);
1975 if (unlikely(Rc(ctx->opcode) != 0))
1976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1977 }
1978 #endif
1979
1980 /*** Floating-Point arithmetic ***/
1981 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1982 static void gen_f##name(DisasContext *ctx) \
1983 { \
1984 if (unlikely(!ctx->fpu_enabled)) { \
1985 gen_exception(ctx, POWERPC_EXCP_FPU); \
1986 return; \
1987 } \
1988 /* NIP cannot be restored if the memory exception comes from an helper */ \
1989 gen_update_nip(ctx, ctx->nip - 4); \
1990 gen_reset_fpstatus(); \
1991 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
1992 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1993 if (isfloat) { \
1994 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
1995 } \
1996 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1997 Rc(ctx->opcode) != 0); \
1998 }
1999
2000 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2001 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2002 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2003
2004 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2005 static void gen_f##name(DisasContext *ctx) \
2006 { \
2007 if (unlikely(!ctx->fpu_enabled)) { \
2008 gen_exception(ctx, POWERPC_EXCP_FPU); \
2009 return; \
2010 } \
2011 /* NIP cannot be restored if the memory exception comes from an helper */ \
2012 gen_update_nip(ctx, ctx->nip - 4); \
2013 gen_reset_fpstatus(); \
2014 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2015 cpu_fpr[rB(ctx->opcode)]); \
2016 if (isfloat) { \
2017 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2018 } \
2019 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2020 set_fprf, Rc(ctx->opcode) != 0); \
2021 }
2022 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2023 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2024 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2025
2026 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2027 static void gen_f##name(DisasContext *ctx) \
2028 { \
2029 if (unlikely(!ctx->fpu_enabled)) { \
2030 gen_exception(ctx, POWERPC_EXCP_FPU); \
2031 return; \
2032 } \
2033 /* NIP cannot be restored if the memory exception comes from an helper */ \
2034 gen_update_nip(ctx, ctx->nip - 4); \
2035 gen_reset_fpstatus(); \
2036 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2037 cpu_fpr[rC(ctx->opcode)]); \
2038 if (isfloat) { \
2039 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2040 } \
2041 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2042 set_fprf, Rc(ctx->opcode) != 0); \
2043 }
2044 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2045 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2046 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2047
2048 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2049 static void gen_f##name(DisasContext *ctx) \
2050 { \
2051 if (unlikely(!ctx->fpu_enabled)) { \
2052 gen_exception(ctx, POWERPC_EXCP_FPU); \
2053 return; \
2054 } \
2055 /* NIP cannot be restored if the memory exception comes from an helper */ \
2056 gen_update_nip(ctx, ctx->nip - 4); \
2057 gen_reset_fpstatus(); \
2058 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2059 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2060 set_fprf, Rc(ctx->opcode) != 0); \
2061 }
2062
2063 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2064 static void gen_f##name(DisasContext *ctx) \
2065 { \
2066 if (unlikely(!ctx->fpu_enabled)) { \
2067 gen_exception(ctx, POWERPC_EXCP_FPU); \
2068 return; \
2069 } \
2070 /* NIP cannot be restored if the memory exception comes from an helper */ \
2071 gen_update_nip(ctx, ctx->nip - 4); \
2072 gen_reset_fpstatus(); \
2073 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2074 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2075 set_fprf, Rc(ctx->opcode) != 0); \
2076 }
2077
2078 /* fadd - fadds */
2079 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2080 /* fdiv - fdivs */
2081 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2082 /* fmul - fmuls */
2083 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2084
2085 /* fre */
2086 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2087
2088 /* fres */
2089 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2090
2091 /* frsqrte */
2092 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2093
2094 /* frsqrtes */
2095 static void gen_frsqrtes(DisasContext *ctx)
2096 {
2097 if (unlikely(!ctx->fpu_enabled)) {
2098 gen_exception(ctx, POWERPC_EXCP_FPU);
2099 return;
2100 }
2101 /* NIP cannot be restored if the memory exception comes from an helper */
2102 gen_update_nip(ctx, ctx->nip - 4);
2103 gen_reset_fpstatus();
2104 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2105 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2106 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2107 }
2108
2109 /* fsel */
2110 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2111 /* fsub - fsubs */
2112 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2113 /* Optional: */
2114
2115 /* fsqrt */
2116 static void gen_fsqrt(DisasContext *ctx)
2117 {
2118 if (unlikely(!ctx->fpu_enabled)) {
2119 gen_exception(ctx, POWERPC_EXCP_FPU);
2120 return;
2121 }
2122 /* NIP cannot be restored if the memory exception comes from an helper */
2123 gen_update_nip(ctx, ctx->nip - 4);
2124 gen_reset_fpstatus();
2125 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2126 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2127 }
2128
2129 static void gen_fsqrts(DisasContext *ctx)
2130 {
2131 if (unlikely(!ctx->fpu_enabled)) {
2132 gen_exception(ctx, POWERPC_EXCP_FPU);
2133 return;
2134 }
2135 /* NIP cannot be restored if the memory exception comes from an helper */
2136 gen_update_nip(ctx, ctx->nip - 4);
2137 gen_reset_fpstatus();
2138 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2139 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2140 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2141 }
2142
2143 /*** Floating-Point multiply-and-add ***/
2144 /* fmadd - fmadds */
2145 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2146 /* fmsub - fmsubs */
2147 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2148 /* fnmadd - fnmadds */
2149 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2150 /* fnmsub - fnmsubs */
2151 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2152
2153 /*** Floating-Point round & convert ***/
2154 /* fctiw */
2155 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2156 /* fctiwz */
2157 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2158 /* frsp */
2159 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2160 #if defined(TARGET_PPC64)
2161 /* fcfid */
2162 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2163 /* fctid */
2164 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2165 /* fctidz */
2166 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2167 #endif
2168
2169 /* frin */
2170 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2171 /* friz */
2172 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2173 /* frip */
2174 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2175 /* frim */
2176 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2177
2178 /*** Floating-Point compare ***/
2179
2180 /* fcmpo */
2181 static void gen_fcmpo(DisasContext *ctx)
2182 {
2183 TCGv_i32 crf;
2184 if (unlikely(!ctx->fpu_enabled)) {
2185 gen_exception(ctx, POWERPC_EXCP_FPU);
2186 return;
2187 }
2188 /* NIP cannot be restored if the memory exception comes from an helper */
2189 gen_update_nip(ctx, ctx->nip - 4);
2190 gen_reset_fpstatus();
2191 crf = tcg_const_i32(crfD(ctx->opcode));
2192 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2193 tcg_temp_free_i32(crf);
2194 gen_helper_float_check_status();
2195 }
2196
2197 /* fcmpu */
2198 static void gen_fcmpu(DisasContext *ctx)
2199 {
2200 TCGv_i32 crf;
2201 if (unlikely(!ctx->fpu_enabled)) {
2202 gen_exception(ctx, POWERPC_EXCP_FPU);
2203 return;
2204 }
2205 /* NIP cannot be restored if the memory exception comes from an helper */
2206 gen_update_nip(ctx, ctx->nip - 4);
2207 gen_reset_fpstatus();
2208 crf = tcg_const_i32(crfD(ctx->opcode));
2209 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2210 tcg_temp_free_i32(crf);
2211 gen_helper_float_check_status();
2212 }
2213
2214 /*** Floating-point move ***/
2215 /* fabs */
2216 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2217 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2218
2219 /* fmr - fmr. */
2220 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2221 static void gen_fmr(DisasContext *ctx)
2222 {
2223 if (unlikely(!ctx->fpu_enabled)) {
2224 gen_exception(ctx, POWERPC_EXCP_FPU);
2225 return;
2226 }
2227 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2228 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2229 }
2230
2231 /* fnabs */
2232 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2233 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2234 /* fneg */
2235 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2236 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2237
2238 /*** Floating-Point status & ctrl register ***/
2239
2240 /* mcrfs */
2241 static void gen_mcrfs(DisasContext *ctx)
2242 {
2243 int bfa;
2244
2245 if (unlikely(!ctx->fpu_enabled)) {
2246 gen_exception(ctx, POWERPC_EXCP_FPU);
2247 return;
2248 }
2249 bfa = 4 * (7 - crfS(ctx->opcode));
2250 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2251 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2252 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2253 }
2254
2255 /* mffs */
2256 static void gen_mffs(DisasContext *ctx)
2257 {
2258 if (unlikely(!ctx->fpu_enabled)) {
2259 gen_exception(ctx, POWERPC_EXCP_FPU);
2260 return;
2261 }
2262 gen_reset_fpstatus();
2263 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2264 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2265 }
2266
2267 /* mtfsb0 */
2268 static void gen_mtfsb0(DisasContext *ctx)
2269 {
2270 uint8_t crb;
2271
2272 if (unlikely(!ctx->fpu_enabled)) {
2273 gen_exception(ctx, POWERPC_EXCP_FPU);
2274 return;
2275 }
2276 crb = 31 - crbD(ctx->opcode);
2277 gen_reset_fpstatus();
2278 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2279 TCGv_i32 t0;
2280 /* NIP cannot be restored if the memory exception comes from an helper */
2281 gen_update_nip(ctx, ctx->nip - 4);
2282 t0 = tcg_const_i32(crb);
2283 gen_helper_fpscr_clrbit(t0);
2284 tcg_temp_free_i32(t0);
2285 }
2286 if (unlikely(Rc(ctx->opcode) != 0)) {
2287 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2288 }
2289 }
2290
2291 /* mtfsb1 */
2292 static void gen_mtfsb1(DisasContext *ctx)
2293 {
2294 uint8_t crb;
2295
2296 if (unlikely(!ctx->fpu_enabled)) {
2297 gen_exception(ctx, POWERPC_EXCP_FPU);
2298 return;
2299 }
2300 crb = 31 - crbD(ctx->opcode);
2301 gen_reset_fpstatus();
2302 /* XXX: we pretend we can only do IEEE floating-point computations */
2303 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2304 TCGv_i32 t0;
2305 /* NIP cannot be restored if the memory exception comes from an helper */
2306 gen_update_nip(ctx, ctx->nip - 4);
2307 t0 = tcg_const_i32(crb);
2308 gen_helper_fpscr_setbit(t0);
2309 tcg_temp_free_i32(t0);
2310 }
2311 if (unlikely(Rc(ctx->opcode) != 0)) {
2312 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2313 }
2314 /* We can raise a differed exception */
2315 gen_helper_float_check_status();
2316 }
2317
2318 /* mtfsf */
2319 static void gen_mtfsf(DisasContext *ctx)
2320 {
2321 TCGv_i32 t0;
2322 int L = ctx->opcode & 0x02000000;
2323
2324 if (unlikely(!ctx->fpu_enabled)) {
2325 gen_exception(ctx, POWERPC_EXCP_FPU);
2326 return;
2327 }
2328 /* NIP cannot be restored if the memory exception comes from an helper */
2329 gen_update_nip(ctx, ctx->nip - 4);
2330 gen_reset_fpstatus();
2331 if (L)
2332 t0 = tcg_const_i32(0xff);
2333 else
2334 t0 = tcg_const_i32(FM(ctx->opcode));
2335 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2336 tcg_temp_free_i32(t0);
2337 if (unlikely(Rc(ctx->opcode) != 0)) {
2338 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2339 }
2340 /* We can raise a differed exception */
2341 gen_helper_float_check_status();
2342 }
2343
2344 /* mtfsfi */
2345 static void gen_mtfsfi(DisasContext *ctx)
2346 {
2347 int bf, sh;
2348 TCGv_i64 t0;
2349 TCGv_i32 t1;
2350
2351 if (unlikely(!ctx->fpu_enabled)) {
2352 gen_exception(ctx, POWERPC_EXCP_FPU);
2353 return;
2354 }
2355 bf = crbD(ctx->opcode) >> 2;
2356 sh = 7 - bf;
2357 /* NIP cannot be restored if the memory exception comes from an helper */
2358 gen_update_nip(ctx, ctx->nip - 4);
2359 gen_reset_fpstatus();
2360 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2361 t1 = tcg_const_i32(1 << sh);
2362 gen_helper_store_fpscr(t0, t1);
2363 tcg_temp_free_i64(t0);
2364 tcg_temp_free_i32(t1);
2365 if (unlikely(Rc(ctx->opcode) != 0)) {
2366 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2367 }
2368 /* We can raise a differed exception */
2369 gen_helper_float_check_status();
2370 }
2371
2372 /*** Addressing modes ***/
2373 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2374 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2375 target_long maskl)
2376 {
2377 target_long simm = SIMM(ctx->opcode);
2378
2379 simm &= ~maskl;
2380 if (rA(ctx->opcode) == 0) {
2381 #if defined(TARGET_PPC64)
2382 if (!ctx->sf_mode) {
2383 tcg_gen_movi_tl(EA, (uint32_t)simm);
2384 } else
2385 #endif
2386 tcg_gen_movi_tl(EA, simm);
2387 } else if (likely(simm != 0)) {
2388 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2389 #if defined(TARGET_PPC64)
2390 if (!ctx->sf_mode) {
2391 tcg_gen_ext32u_tl(EA, EA);
2392 }
2393 #endif
2394 } else {
2395 #if defined(TARGET_PPC64)
2396 if (!ctx->sf_mode) {
2397 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2398 } else
2399 #endif
2400 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2401 }
2402 }
2403
2404 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2405 {
2406 if (rA(ctx->opcode) == 0) {
2407 #if defined(TARGET_PPC64)
2408 if (!ctx->sf_mode) {
2409 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2410 } else
2411 #endif
2412 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2413 } else {
2414 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2415 #if defined(TARGET_PPC64)
2416 if (!ctx->sf_mode) {
2417 tcg_gen_ext32u_tl(EA, EA);
2418 }
2419 #endif
2420 }
2421 }
2422
2423 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2424 {
2425 if (rA(ctx->opcode) == 0) {
2426 tcg_gen_movi_tl(EA, 0);
2427 } else {
2428 #if defined(TARGET_PPC64)
2429 if (!ctx->sf_mode) {
2430 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2431 } else
2432 #endif
2433 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2434 }
2435 }
2436
2437 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2438 target_long val)
2439 {
2440 tcg_gen_addi_tl(ret, arg1, val);
2441 #if defined(TARGET_PPC64)
2442 if (!ctx->sf_mode) {
2443 tcg_gen_ext32u_tl(ret, ret);
2444 }
2445 #endif
2446 }
2447
2448 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2449 {
2450 int l1 = gen_new_label();
2451 TCGv t0 = tcg_temp_new();
2452 TCGv_i32 t1, t2;
2453 /* NIP cannot be restored if the memory exception comes from an helper */
2454 gen_update_nip(ctx, ctx->nip - 4);
2455 tcg_gen_andi_tl(t0, EA, mask);
2456 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2457 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2458 t2 = tcg_const_i32(0);
2459 gen_helper_raise_exception_err(t1, t2);
2460 tcg_temp_free_i32(t1);
2461 tcg_temp_free_i32(t2);
2462 gen_set_label(l1);
2463 tcg_temp_free(t0);
2464 }
2465
2466 /*** Integer load ***/
2467 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2468 {
2469 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2470 }
2471
2472 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2473 {
2474 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2475 }
2476
2477 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2478 {
2479 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2480 if (unlikely(ctx->le_mode)) {
2481 tcg_gen_bswap16_tl(arg1, arg1);
2482 }
2483 }
2484
2485 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2486 {
2487 if (unlikely(ctx->le_mode)) {
2488 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2489 tcg_gen_bswap16_tl(arg1, arg1);
2490 tcg_gen_ext16s_tl(arg1, arg1);
2491 } else {
2492 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2493 }
2494 }
2495
2496 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2497 {
2498 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2499 if (unlikely(ctx->le_mode)) {
2500 tcg_gen_bswap32_tl(arg1, arg1);
2501 }
2502 }
2503
2504 #if defined(TARGET_PPC64)
2505 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2506 {
2507 if (unlikely(ctx->le_mode)) {
2508 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2509 tcg_gen_bswap32_tl(arg1, arg1);
2510 tcg_gen_ext32s_tl(arg1, arg1);
2511 } else
2512 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2513 }
2514 #endif
2515
2516 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2517 {
2518 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2519 if (unlikely(ctx->le_mode)) {
2520 tcg_gen_bswap64_i64(arg1, arg1);
2521 }
2522 }
2523
2524 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2525 {
2526 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2527 }
2528
2529 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2530 {
2531 if (unlikely(ctx->le_mode)) {
2532 TCGv t0 = tcg_temp_new();
2533 tcg_gen_ext16u_tl(t0, arg1);
2534 tcg_gen_bswap16_tl(t0, t0);
2535 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2536 tcg_temp_free(t0);
2537 } else {
2538 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2539 }
2540 }
2541
2542 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2543 {
2544 if (unlikely(ctx->le_mode)) {
2545 TCGv t0 = tcg_temp_new();
2546 tcg_gen_ext32u_tl(t0, arg1);
2547 tcg_gen_bswap32_tl(t0, t0);
2548 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2549 tcg_temp_free(t0);
2550 } else {
2551 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2552 }
2553 }
2554
2555 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2556 {
2557 if (unlikely(ctx->le_mode)) {
2558 TCGv_i64 t0 = tcg_temp_new_i64();
2559 tcg_gen_bswap64_i64(t0, arg1);
2560 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2561 tcg_temp_free_i64(t0);
2562 } else
2563 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2564 }
2565
2566 #define GEN_LD(name, ldop, opc, type) \
2567 static void glue(gen_, name)(DisasContext *ctx) \
2568 { \
2569 TCGv EA; \
2570 gen_set_access_type(ctx, ACCESS_INT); \
2571 EA = tcg_temp_new(); \
2572 gen_addr_imm_index(ctx, EA, 0); \
2573 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2574 tcg_temp_free(EA); \
2575 }
2576
2577 #define GEN_LDU(name, ldop, opc, type) \
2578 static void glue(gen_, name##u)(DisasContext *ctx) \
2579 { \
2580 TCGv EA; \
2581 if (unlikely(rA(ctx->opcode) == 0 || \
2582 rA(ctx->opcode) == rD(ctx->opcode))) { \
2583 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2584 return; \
2585 } \
2586 gen_set_access_type(ctx, ACCESS_INT); \
2587 EA = tcg_temp_new(); \
2588 if (type == PPC_64B) \
2589 gen_addr_imm_index(ctx, EA, 0x03); \
2590 else \
2591 gen_addr_imm_index(ctx, EA, 0); \
2592 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2593 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2594 tcg_temp_free(EA); \
2595 }
2596
2597 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2598 static void glue(gen_, name##ux)(DisasContext *ctx) \
2599 { \
2600 TCGv EA; \
2601 if (unlikely(rA(ctx->opcode) == 0 || \
2602 rA(ctx->opcode) == rD(ctx->opcode))) { \
2603 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2604 return; \
2605 } \
2606 gen_set_access_type(ctx, ACCESS_INT); \
2607 EA = tcg_temp_new(); \
2608 gen_addr_reg_index(ctx, EA); \
2609 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2610 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2611 tcg_temp_free(EA); \
2612 }
2613
2614 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2615 static void glue(gen_, name##x)(DisasContext *ctx) \
2616 { \
2617 TCGv EA; \
2618 gen_set_access_type(ctx, ACCESS_INT); \
2619 EA = tcg_temp_new(); \
2620 gen_addr_reg_index(ctx, EA); \
2621 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2622 tcg_temp_free(EA); \
2623 }
2624
2625 #define GEN_LDS(name, ldop, op, type) \
2626 GEN_LD(name, ldop, op | 0x20, type); \
2627 GEN_LDU(name, ldop, op | 0x21, type); \
2628 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2629 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2630
2631 /* lbz lbzu lbzux lbzx */
2632 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2633 /* lha lhau lhaux lhax */
2634 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2635 /* lhz lhzu lhzux lhzx */
2636 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2637 /* lwz lwzu lwzux lwzx */
2638 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2639 #if defined(TARGET_PPC64)
2640 /* lwaux */
2641 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2642 /* lwax */
2643 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2644 /* ldux */
2645 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2646 /* ldx */
2647 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2648
2649 static void gen_ld(DisasContext *ctx)
2650 {
2651 TCGv EA;
2652 if (Rc(ctx->opcode)) {
2653 if (unlikely(rA(ctx->opcode) == 0 ||
2654 rA(ctx->opcode) == rD(ctx->opcode))) {
2655 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2656 return;
2657 }
2658 }
2659 gen_set_access_type(ctx, ACCESS_INT);
2660 EA = tcg_temp_new();
2661 gen_addr_imm_index(ctx, EA, 0x03);
2662 if (ctx->opcode & 0x02) {
2663 /* lwa (lwau is undefined) */
2664 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2665 } else {
2666 /* ld - ldu */
2667 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2668 }
2669 if (Rc(ctx->opcode))
2670 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2671 tcg_temp_free(EA);
2672 }
2673
2674 /* lq */
2675 static void gen_lq(DisasContext *ctx)
2676 {
2677 #if defined(CONFIG_USER_ONLY)
2678 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2679 #else
2680 int ra, rd;
2681 TCGv EA;
2682
2683 /* Restore CPU state */
2684 if (unlikely(ctx->mem_idx == 0)) {
2685 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2686 return;
2687 }
2688 ra = rA(ctx->opcode);
2689 rd = rD(ctx->opcode);
2690 if (unlikely((rd & 1) || rd == ra)) {
2691 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2692 return;
2693 }
2694 if (unlikely(ctx->le_mode)) {
2695 /* Little-endian mode is not handled */
2696 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2697 return;
2698 }
2699 gen_set_access_type(ctx, ACCESS_INT);
2700 EA = tcg_temp_new();
2701 gen_addr_imm_index(ctx, EA, 0x0F);
2702 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2703 gen_addr_add(ctx, EA, EA, 8);
2704 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2705 tcg_temp_free(EA);
2706 #endif
2707 }
2708 #endif
2709
2710 /*** Integer store ***/
2711 #define GEN_ST(name, stop, opc, type) \
2712 static void glue(gen_, name)(DisasContext *ctx) \
2713 { \
2714 TCGv EA; \
2715 gen_set_access_type(ctx, ACCESS_INT); \
2716 EA = tcg_temp_new(); \
2717 gen_addr_imm_index(ctx, EA, 0); \
2718 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2719 tcg_temp_free(EA); \
2720 }
2721
2722 #define GEN_STU(name, stop, opc, type) \
2723 static void glue(gen_, stop##u)(DisasContext *ctx) \
2724 { \
2725 TCGv EA; \
2726 if (unlikely(rA(ctx->opcode) == 0)) { \
2727 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2728 return; \
2729 } \
2730 gen_set_access_type(ctx, ACCESS_INT); \
2731 EA = tcg_temp_new(); \
2732 if (type == PPC_64B) \
2733 gen_addr_imm_index(ctx, EA, 0x03); \
2734 else \
2735 gen_addr_imm_index(ctx, EA, 0); \
2736 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2737 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2738 tcg_temp_free(EA); \
2739 }
2740
2741 #define GEN_STUX(name, stop, opc2, opc3, type) \
2742 static void glue(gen_, name##ux)(DisasContext *ctx) \
2743 { \
2744 TCGv EA; \
2745 if (unlikely(rA(ctx->opcode) == 0)) { \
2746 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2747 return; \
2748 } \
2749 gen_set_access_type(ctx, ACCESS_INT); \
2750 EA = tcg_temp_new(); \
2751 gen_addr_reg_index(ctx, EA); \
2752 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2753 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2754 tcg_temp_free(EA); \
2755 }
2756
2757 #define GEN_STX(name, stop, opc2, opc3, type) \
2758 static void glue(gen_, name##x)(DisasContext *ctx) \
2759 { \
2760 TCGv EA; \
2761 gen_set_access_type(ctx, ACCESS_INT); \
2762 EA = tcg_temp_new(); \
2763 gen_addr_reg_index(ctx, EA); \
2764 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2765 tcg_temp_free(EA); \
2766 }
2767
2768 #define GEN_STS(name, stop, op, type) \
2769 GEN_ST(name, stop, op | 0x20, type); \
2770 GEN_STU(name, stop, op | 0x21, type); \
2771 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2772 GEN_STX(name, stop, 0x17, op | 0x00, type)
2773
2774 /* stb stbu stbux stbx */
2775 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2776 /* sth sthu sthux sthx */
2777 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2778 /* stw stwu stwux stwx */
2779 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2780 #if defined(TARGET_PPC64)
2781 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2782 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2783
2784 static void gen_std(DisasContext *ctx)
2785 {
2786 int rs;
2787 TCGv EA;
2788
2789 rs = rS(ctx->opcode);
2790 if ((ctx->opcode & 0x3) == 0x2) {
2791 #if defined(CONFIG_USER_ONLY)
2792 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2793 #else
2794 /* stq */
2795 if (unlikely(ctx->mem_idx == 0)) {
2796 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2797 return;
2798 }
2799 if (unlikely(rs & 1)) {
2800 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2801 return;
2802 }
2803 if (unlikely(ctx->le_mode)) {
2804 /* Little-endian mode is not handled */
2805 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2806 return;
2807 }
2808 gen_set_access_type(ctx, ACCESS_INT);
2809 EA = tcg_temp_new();
2810 gen_addr_imm_index(ctx, EA, 0x03);
2811 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2812 gen_addr_add(ctx, EA, EA, 8);
2813 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2814 tcg_temp_free(EA);
2815 #endif
2816 } else {
2817 /* std / stdu */
2818 if (Rc(ctx->opcode)) {
2819 if (unlikely(rA(ctx->opcode) == 0)) {
2820 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2821 return;
2822 }
2823 }
2824 gen_set_access_type(ctx, ACCESS_INT);
2825 EA = tcg_temp_new();
2826 gen_addr_imm_index(ctx, EA, 0x03);
2827 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2828 if (Rc(ctx->opcode))
2829 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2830 tcg_temp_free(EA);
2831 }
2832 }
2833 #endif
2834 /*** Integer load and store with byte reverse ***/
2835 /* lhbrx */
2836 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2837 {
2838 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2839 if (likely(!ctx->le_mode)) {
2840 tcg_gen_bswap16_tl(arg1, arg1);
2841 }
2842 }
2843 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2844
2845 /* lwbrx */
2846 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2847 {
2848 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2849 if (likely(!ctx->le_mode)) {
2850 tcg_gen_bswap32_tl(arg1, arg1);
2851 }
2852 }
2853 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2854
2855 /* sthbrx */
2856 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2857 {
2858 if (likely(!ctx->le_mode)) {
2859 TCGv t0 = tcg_temp_new();
2860 tcg_gen_ext16u_tl(t0, arg1);
2861 tcg_gen_bswap16_tl(t0, t0);
2862 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2863 tcg_temp_free(t0);
2864 } else {
2865 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2866 }
2867 }
2868 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2869
2870 /* stwbrx */
2871 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2872 {
2873 if (likely(!ctx->le_mode)) {
2874 TCGv t0 = tcg_temp_new();
2875 tcg_gen_ext32u_tl(t0, arg1);
2876 tcg_gen_bswap32_tl(t0, t0);
2877 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2878 tcg_temp_free(t0);
2879 } else {
2880 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2881 }
2882 }
2883 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2884
2885 /*** Integer load and store multiple ***/
2886
2887 /* lmw */
2888 static void gen_lmw(DisasContext *ctx)
2889 {
2890 TCGv t0;
2891 TCGv_i32 t1;
2892 gen_set_access_type(ctx, ACCESS_INT);
2893 /* NIP cannot be restored if the memory exception comes from an helper */
2894 gen_update_nip(ctx, ctx->nip - 4);
2895 t0 = tcg_temp_new();
2896 t1 = tcg_const_i32(rD(ctx->opcode));
2897 gen_addr_imm_index(ctx, t0, 0);
2898 gen_helper_lmw(t0, t1);
2899 tcg_temp_free(t0);
2900 tcg_temp_free_i32(t1);
2901 }
2902
2903 /* stmw */
2904 static void gen_stmw(DisasContext *ctx)
2905 {
2906 TCGv t0;
2907 TCGv_i32 t1;
2908 gen_set_access_type(ctx, ACCESS_INT);
2909 /* NIP cannot be restored if the memory exception comes from an helper */
2910 gen_update_nip(ctx, ctx->nip - 4);
2911 t0 = tcg_temp_new();
2912 t1 = tcg_const_i32(rS(ctx->opcode));
2913 gen_addr_imm_index(ctx, t0, 0);
2914 gen_helper_stmw(t0, t1);
2915 tcg_temp_free(t0);
2916 tcg_temp_free_i32(t1);
2917 }
2918
2919 /*** Integer load and store strings ***/
2920
2921 /* lswi */
2922 /* PowerPC32 specification says we must generate an exception if
2923 * rA is in the range of registers to be loaded.
2924 * In an other hand, IBM says this is valid, but rA won't be loaded.
2925 * For now, I'll follow the spec...
2926 */
2927 static void gen_lswi(DisasContext *ctx)
2928 {
2929 TCGv t0;
2930 TCGv_i32 t1, t2;
2931 int nb = NB(ctx->opcode);
2932 int start = rD(ctx->opcode);
2933 int ra = rA(ctx->opcode);
2934 int nr;
2935
2936 if (nb == 0)
2937 nb = 32;
2938 nr = nb / 4;
2939 if (unlikely(((start + nr) > 32 &&
2940 start <= ra && (start + nr - 32) > ra) ||
2941 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2942 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2943 return;
2944 }
2945 gen_set_access_type(ctx, ACCESS_INT);
2946 /* NIP cannot be restored if the memory exception comes from an helper */
2947 gen_update_nip(ctx, ctx->nip - 4);
2948 t0 = tcg_temp_new();
2949 gen_addr_register(ctx, t0);
2950 t1 = tcg_const_i32(nb);
2951 t2 = tcg_const_i32(start);
2952 gen_helper_lsw(t0, t1, t2);
2953 tcg_temp_free(t0);
2954 tcg_temp_free_i32(t1);
2955 tcg_temp_free_i32(t2);
2956 }
2957
2958 /* lswx */
2959 static void gen_lswx(DisasContext *ctx)
2960 {
2961 TCGv t0;
2962 TCGv_i32 t1, t2, t3;
2963 gen_set_access_type(ctx, ACCESS_INT);
2964 /* NIP cannot be restored if the memory exception comes from an helper */
2965 gen_update_nip(ctx, ctx->nip - 4);
2966 t0 = tcg_temp_new();
2967 gen_addr_reg_index(ctx, t0);
2968 t1 = tcg_const_i32(rD(ctx->opcode));
2969 t2 = tcg_const_i32(rA(ctx->opcode));
2970 t3 = tcg_const_i32(rB(ctx->opcode));
2971 gen_helper_lswx(t0, t1, t2, t3);
2972 tcg_temp_free(t0);
2973 tcg_temp_free_i32(t1);
2974 tcg_temp_free_i32(t2);
2975 tcg_temp_free_i32(t3);
2976 }
2977
2978 /* stswi */
2979 static void gen_stswi(DisasContext *ctx)
2980 {
2981 TCGv t0;
2982 TCGv_i32 t1, t2;
2983 int nb = NB(ctx->opcode);
2984 gen_set_access_type(ctx, ACCESS_INT);
2985 /* NIP cannot be restored if the memory exception comes from an helper */
2986 gen_update_nip(ctx, ctx->nip - 4);
2987 t0 = tcg_temp_new();
2988 gen_addr_register(ctx, t0);
2989 if (nb == 0)
2990 nb = 32;
2991 t1 = tcg_const_i32(nb);
2992 t2 = tcg_const_i32(rS(ctx->opcode));
2993 gen_helper_stsw(t0, t1, t2);
2994 tcg_temp_free(t0);
2995 tcg_temp_free_i32(t1);
2996 tcg_temp_free_i32(t2);
2997 }
2998
2999 /* stswx */
3000 static void gen_stswx(DisasContext *ctx)
3001 {
3002 TCGv t0;
3003 TCGv_i32 t1, t2;
3004 gen_set_access_type(ctx, ACCESS_INT);
3005 /* NIP cannot be restored if the memory exception comes from an helper */
3006 gen_update_nip(ctx, ctx->nip - 4);
3007 t0 = tcg_temp_new();
3008 gen_addr_reg_index(ctx, t0);
3009 t1 = tcg_temp_new_i32();
3010 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3011 tcg_gen_andi_i32(t1, t1, 0x7F);
3012 t2 = tcg_const_i32(rS(ctx->opcode));
3013 gen_helper_stsw(t0, t1, t2);
3014 tcg_temp_free(t0);
3015 tcg_temp_free_i32(t1);
3016 tcg_temp_free_i32(t2);
3017 }
3018
3019 /*** Memory synchronisation ***/
3020 /* eieio */
3021 static void gen_eieio(DisasContext *ctx)
3022 {
3023 }
3024
3025 /* isync */
3026 static void gen_isync(DisasContext *ctx)
3027 {
3028 gen_stop_exception(ctx);
3029 }
3030
3031 /* lwarx */
3032 static void gen_lwarx(DisasContext *ctx)
3033 {
3034 TCGv t0;
3035 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3036 gen_set_access_type(ctx, ACCESS_RES);
3037 t0 = tcg_temp_local_new();
3038 gen_addr_reg_index(ctx, t0);
3039 gen_check_align(ctx, t0, 0x03);
3040 gen_qemu_ld32u(ctx, gpr, t0);
3041 tcg_gen_mov_tl(cpu_reserve, t0);
3042 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
3043 tcg_temp_free(t0);
3044 }
3045
3046 #if defined(CONFIG_USER_ONLY)
3047 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3048 int reg, int size)
3049 {
3050 TCGv t0 = tcg_temp_new();
3051 uint32_t save_exception = ctx->exception;
3052
3053 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea));
3054 tcg_gen_movi_tl(t0, (size << 5) | reg);
3055 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info));
3056 tcg_temp_free(t0);
3057 gen_update_nip(ctx, ctx->nip-4);
3058 ctx->exception = POWERPC_EXCP_BRANCH;
3059 gen_exception(ctx, POWERPC_EXCP_STCX);
3060 ctx->exception = save_exception;
3061 }
3062 #endif
3063
3064 /* stwcx. */
3065 static void gen_stwcx_(DisasContext *ctx)
3066 {
3067 TCGv t0;
3068 gen_set_access_type(ctx, ACCESS_RES);
3069 t0 = tcg_temp_local_new();
3070 gen_addr_reg_index(ctx, t0);
3071 gen_check_align(ctx, t0, 0x03);
3072 #if defined(CONFIG_USER_ONLY)
3073 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3074 #else
3075 {
3076 int l1;
3077
3078 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3079 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3080 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3081 l1 = gen_new_label();
3082 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3083 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3084 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3085 gen_set_label(l1);
3086 tcg_gen_movi_tl(cpu_reserve, -1);
3087 }
3088 #endif
3089 tcg_temp_free(t0);
3090 }
3091
3092 #if defined(TARGET_PPC64)
3093 /* ldarx */
3094 static void gen_ldarx(DisasContext *ctx)
3095 {
3096 TCGv t0;
3097 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3098 gen_set_access_type(ctx, ACCESS_RES);
3099 t0 = tcg_temp_local_new();
3100 gen_addr_reg_index(ctx, t0);
3101 gen_check_align(ctx, t0, 0x07);
3102 gen_qemu_ld64(ctx, gpr, t0);
3103 tcg_gen_mov_tl(cpu_reserve, t0);
3104 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
3105 tcg_temp_free(t0);
3106 }
3107
3108 /* stdcx. */
3109 static void gen_stdcx_(DisasContext *ctx)
3110 {
3111 TCGv t0;
3112 gen_set_access_type(ctx, ACCESS_RES);
3113 t0 = tcg_temp_local_new();
3114 gen_addr_reg_index(ctx, t0);
3115 gen_check_align(ctx, t0, 0x07);
3116 #if defined(CONFIG_USER_ONLY)
3117 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3118 #else
3119 {
3120 int l1;
3121 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3122 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3123 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3124 l1 = gen_new_label();
3125 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3126 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3127 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3128 gen_set_label(l1);
3129 tcg_gen_movi_tl(cpu_reserve, -1);
3130 }
3131 #endif
3132 tcg_temp_free(t0);
3133 }
3134 #endif /* defined(TARGET_PPC64) */
3135
3136 /* sync */
3137 static void gen_sync(DisasContext *ctx)
3138 {
3139 }
3140
3141 /* wait */
3142 static void gen_wait(DisasContext *ctx)
3143 {
3144 TCGv_i32 t0 = tcg_temp_new_i32();
3145 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3146 tcg_temp_free_i32(t0);
3147 /* Stop translation, as the CPU is supposed to sleep from now */
3148 gen_exception_err(ctx, EXCP_HLT, 1);
3149 }
3150
3151 /*** Floating-point load ***/
3152 #define GEN_LDF(name, ldop, opc, type) \
3153 static void glue(gen_, name)(DisasContext *ctx) \
3154 { \
3155 TCGv EA; \
3156 if (unlikely(!ctx->fpu_enabled)) { \
3157 gen_exception(ctx, POWERPC_EXCP_FPU); \
3158 return; \
3159 } \
3160 gen_set_access_type(ctx, ACCESS_FLOAT); \
3161 EA = tcg_temp_new(); \
3162 gen_addr_imm_index(ctx, EA, 0); \
3163 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3164 tcg_temp_free(EA); \
3165 }
3166
3167 #define GEN_LDUF(name, ldop, opc, type) \
3168 static void glue(gen_, name##u)(DisasContext *ctx) \
3169 { \
3170 TCGv EA; \
3171 if (unlikely(!ctx->fpu_enabled)) { \
3172 gen_exception(ctx, POWERPC_EXCP_FPU); \
3173 return; \
3174 } \
3175 if (unlikely(rA(ctx->opcode) == 0)) { \
3176 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3177 return; \
3178 } \
3179 gen_set_access_type(ctx, ACCESS_FLOAT); \
3180 EA = tcg_temp_new(); \
3181 gen_addr_imm_index(ctx, EA, 0); \
3182 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3183 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3184 tcg_temp_free(EA); \
3185 }
3186
3187 #define GEN_LDUXF(name, ldop, opc, type) \
3188 static void glue(gen_, name##ux)(DisasContext *ctx) \
3189 { \
3190 TCGv EA; \
3191 if (unlikely(!ctx->fpu_enabled)) { \
3192 gen_exception(ctx, POWERPC_EXCP_FPU); \
3193 return; \
3194 } \
3195 if (unlikely(rA(ctx->opcode) == 0)) { \
3196 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3197 return; \
3198 } \
3199 gen_set_access_type(ctx, ACCESS_FLOAT); \
3200 EA = tcg_temp_new(); \
3201 gen_addr_reg_index(ctx, EA); \
3202 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3203 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3204 tcg_temp_free(EA); \
3205 }
3206
3207 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3208 static void glue(gen_, name##x)(DisasContext *ctx) \
3209 { \
3210 TCGv EA; \
3211 if (unlikely(!ctx->fpu_enabled)) { \
3212 gen_exception(ctx, POWERPC_EXCP_FPU); \
3213 return; \
3214 } \
3215 gen_set_access_type(ctx, ACCESS_FLOAT); \
3216 EA = tcg_temp_new(); \
3217 gen_addr_reg_index(ctx, EA); \
3218 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3219 tcg_temp_free(EA); \
3220 }
3221
3222 #define GEN_LDFS(name, ldop, op, type) \
3223 GEN_LDF(name, ldop, op | 0x20, type); \
3224 GEN_LDUF(name, ldop, op | 0x21, type); \
3225 GEN_LDUXF(name, ldop, op | 0x01, type); \
3226 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3227
3228 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3229 {
3230 TCGv t0 = tcg_temp_new();
3231 TCGv_i32 t1 = tcg_temp_new_i32();
3232 gen_qemu_ld32u(ctx, t0, arg2);
3233 tcg_gen_trunc_tl_i32(t1, t0);
3234 tcg_temp_free(t0);
3235 gen_helper_float32_to_float64(arg1, t1);
3236 tcg_temp_free_i32(t1);
3237 }
3238
3239 /* lfd lfdu lfdux lfdx */
3240 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3241 /* lfs lfsu lfsux lfsx */
3242 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3243
3244 /*** Floating-point store ***/
3245 #define GEN_STF(name, stop, opc, type) \
3246 static void glue(gen_, name)(DisasContext *ctx) \
3247 { \
3248 TCGv EA; \
3249 if (unlikely(!ctx->fpu_enabled)) { \
3250 gen_exception(ctx, POWERPC_EXCP_FPU); \
3251 return; \
3252 } \
3253 gen_set_access_type(ctx, ACCESS_FLOAT); \
3254 EA = tcg_temp_new(); \
3255 gen_addr_imm_index(ctx, EA, 0); \
3256 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3257 tcg_temp_free(EA); \
3258 }
3259
3260 #define GEN_STUF(name, stop, opc, type) \
3261 static void glue(gen_, name##u)(DisasContext *ctx) \
3262 { \
3263 TCGv EA; \
3264 if (unlikely(!ctx->fpu_enabled)) { \
3265 gen_exception(ctx, POWERPC_EXCP_FPU); \
3266 return; \
3267 } \
3268 if (unlikely(rA(ctx->opcode) == 0)) { \
3269 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3270 return; \
3271 } \
3272 gen_set_access_type(ctx, ACCESS_FLOAT); \
3273 EA = tcg_temp_new(); \
3274 gen_addr_imm_index(ctx, EA, 0); \
3275 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3276 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3277 tcg_temp_free(EA); \
3278 }
3279
3280 #define GEN_STUXF(name, stop, opc, type) \
3281 static void glue(gen_, name##ux)(DisasContext *ctx) \
3282 { \
3283 TCGv EA; \
3284 if (unlikely(!ctx->fpu_enabled)) { \
3285 gen_exception(ctx, POWERPC_EXCP_FPU); \
3286 return; \
3287 } \
3288 if (unlikely(rA(ctx->opcode) == 0)) { \
3289 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3290 return; \
3291 } \
3292 gen_set_access_type(ctx, ACCESS_FLOAT); \
3293 EA = tcg_temp_new(); \
3294 gen_addr_reg_index(ctx, EA); \
3295 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3296 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3297 tcg_temp_free(EA); \
3298 }
3299
3300 #define GEN_STXF(name, stop, opc2, opc3, type) \
3301 static void glue(gen_, name##x)(DisasContext *ctx) \
3302 { \
3303 TCGv EA; \
3304 if (unlikely(!ctx->fpu_enabled)) { \
3305 gen_exception(ctx, POWERPC_EXCP_FPU); \
3306 return; \
3307 } \
3308 gen_set_access_type(ctx, ACCESS_FLOAT); \
3309 EA = tcg_temp_new(); \
3310 gen_addr_reg_index(ctx, EA); \
3311 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3312 tcg_temp_free(EA); \
3313 }
3314
3315 #define GEN_STFS(name, stop, op, type) \
3316 GEN_STF(name, stop, op | 0x20, type); \
3317 GEN_STUF(name, stop, op | 0x21, type); \
3318 GEN_STUXF(name, stop, op | 0x01, type); \
3319 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3320
3321 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3322 {
3323 TCGv_i32 t0 = tcg_temp_new_i32();
3324 TCGv t1 = tcg_temp_new();
3325 gen_helper_float64_to_float32(t0, arg1);
3326 tcg_gen_extu_i32_tl(t1, t0);
3327 tcg_temp_free_i32(t0);
3328 gen_qemu_st32(ctx, t1, arg2);
3329 tcg_temp_free(t1);
3330 }
3331
3332 /* stfd stfdu stfdux stfdx */
3333 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3334 /* stfs stfsu stfsux stfsx */
3335 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3336
3337 /* Optional: */
3338 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3339 {
3340 TCGv t0 = tcg_temp_new();
3341 tcg_gen_trunc_i64_tl(t0, arg1),
3342 gen_qemu_st32(ctx, t0, arg2);
3343 tcg_temp_free(t0);
3344 }
3345 /* stfiwx */
3346 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3347
3348 /*** Branch ***/
3349 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3350 {
3351 TranslationBlock *tb;
3352 tb = ctx->tb;
3353 #if defined(TARGET_PPC64)
3354 if (!ctx->sf_mode)
3355 dest = (uint32_t) dest;
3356 #endif
3357 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3358 likely(!ctx->singlestep_enabled)) {
3359 tcg_gen_goto_tb(n);
3360 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3361 tcg_gen_exit_tb((tcg_target_long)tb + n);
3362 } else {
3363 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3364 if (unlikely(ctx->singlestep_enabled)) {
3365 if ((ctx->singlestep_enabled &
3366 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3367 ctx->exception == POWERPC_EXCP_BRANCH) {
3368 target_ulong tmp = ctx->nip;
3369 ctx->nip = dest;
3370 gen_exception(ctx, POWERPC_EXCP_TRACE);
3371 ctx->nip = tmp;
3372 }
3373 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3374 gen_debug_exception(ctx);
3375 }
3376 }
3377 tcg_gen_exit_tb(0);
3378 }
3379 }
3380
3381 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3382 {
3383 #if defined(TARGET_PPC64)
3384 if (ctx->sf_mode == 0)
3385 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3386 else
3387 #endif
3388 tcg_gen_movi_tl(cpu_lr, nip);
3389 }
3390
3391 /* b ba bl bla */
3392 static void gen_b(DisasContext *ctx)
3393 {
3394 target_ulong li, target;
3395
3396 ctx->exception = POWERPC_EXCP_BRANCH;
3397 /* sign extend LI */
3398 #if defined(TARGET_PPC64)
3399 if (ctx->sf_mode)
3400 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3401 else
3402 #endif
3403 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3404 if (likely(AA(ctx->opcode) == 0))
3405 target = ctx->nip + li - 4;
3406 else
3407 target = li;
3408 if (LK(ctx->opcode))
3409 gen_setlr(ctx, ctx->nip);
3410 gen_goto_tb(ctx, 0, target);
3411 }
3412
3413 #define BCOND_IM 0
3414 #define BCOND_LR 1
3415 #define BCOND_CTR 2
3416
3417 static inline void gen_bcond(DisasContext *ctx, int type)
3418 {
3419 uint32_t bo = BO(ctx->opcode);
3420 int l1;
3421 TCGv target;
3422
3423 ctx->exception = POWERPC_EXCP_BRANCH;
3424 if (type == BCOND_LR || type == BCOND_CTR) {
3425 target = tcg_temp_local_new();
3426 if (type == BCOND_CTR)
3427 tcg_gen_mov_tl(target, cpu_ctr);
3428 else
3429 tcg_gen_mov_tl(target, cpu_lr);
3430 } else {
3431 TCGV_UNUSED(target);
3432 }
3433 if (LK(ctx->opcode))
3434 gen_setlr(ctx, ctx->nip);
3435 l1 = gen_new_label();
3436 if ((bo & 0x4) == 0) {
3437 /* Decrement and test CTR */
3438 TCGv temp = tcg_temp_new();
3439 if (unlikely(type == BCOND_CTR)) {
3440 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3441 return;
3442 }
3443 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3444 #if defined(TARGET_PPC64)
3445 if (!ctx->sf_mode)
3446 tcg_gen_ext32u_tl(temp, cpu_ctr);
3447 else
3448 #endif
3449 tcg_gen_mov_tl(temp, cpu_ctr);
3450 if (bo & 0x2) {
3451 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3452 } else {
3453 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3454 }
3455 tcg_temp_free(temp);
3456 }
3457 if ((bo & 0x10) == 0) {
3458 /* Test CR */
3459 uint32_t bi = BI(ctx->opcode);
3460 uint32_t mask = 1 << (3 - (bi & 0x03));
3461 TCGv_i32 temp = tcg_temp_new_i32();
3462
3463 if (bo & 0x8) {
3464 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3465 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3466 } else {
3467 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3468 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3469 }
3470 tcg_temp_free_i32(temp);
3471 }
3472 if (type == BCOND_IM) {
3473 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3474 if (likely(AA(ctx->opcode) == 0)) {
3475 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3476 } else {
3477 gen_goto_tb(ctx, 0, li);
3478 }
3479 gen_set_label(l1);
3480 gen_goto_tb(ctx, 1, ctx->nip);
3481 } else {
3482 #if defined(TARGET_PPC64)
3483 if (!(ctx->sf_mode))
3484 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3485 else
3486 #endif
3487 tcg_gen_andi_tl(cpu_nip, target, ~3);
3488 tcg_gen_exit_tb(0);
3489 gen_set_label(l1);
3490 #if defined(TARGET_PPC64)
3491 if (!(ctx->sf_mode))
3492 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3493 else
3494 #endif
3495 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3496 tcg_gen_exit_tb(0);
3497 }
3498 }
3499
3500 static void gen_bc(DisasContext *ctx)
3501 {
3502 gen_bcond(ctx, BCOND_IM);
3503 }
3504
3505 static void gen_bcctr(DisasContext *ctx)
3506 {
3507 gen_bcond(ctx, BCOND_CTR);
3508 }
3509
3510 static void gen_bclr(DisasContext *ctx)
3511 {
3512 gen_bcond(ctx, BCOND_LR);
3513 }
3514
3515 /*** Condition register logical ***/
3516 #define GEN_CRLOGIC(name, tcg_op, opc) \
3517 static void glue(gen_, name)(DisasContext *ctx) \
3518 { \
3519 uint8_t bitmask; \
3520 int sh; \
3521 TCGv_i32 t0, t1; \
3522 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3523 t0 = tcg_temp_new_i32(); \
3524 if (sh > 0) \
3525 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3526 else if (sh < 0) \
3527 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3528 else \
3529 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3530 t1 = tcg_temp_new_i32(); \
3531 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3532 if (sh > 0) \
3533 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3534 else if (sh < 0) \
3535 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3536 else \
3537 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3538 tcg_op(t0, t0, t1); \
3539 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3540 tcg_gen_andi_i32(t0, t0, bitmask); \
3541 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3542 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3543 tcg_temp_free_i32(t0); \
3544 tcg_temp_free_i32(t1); \
3545 }
3546
3547 /* crand */
3548 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3549 /* crandc */
3550 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3551 /* creqv */
3552 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3553 /* crnand */
3554 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3555 /* crnor */
3556 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3557 /* cror */
3558 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3559 /* crorc */
3560 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3561 /* crxor */
3562 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3563
3564 /* mcrf */
3565 static void gen_mcrf(DisasContext *ctx)
3566 {
3567 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3568 }
3569
3570 /*** System linkage ***/
3571
3572 /* rfi (mem_idx only) */
3573 static void gen_rfi(DisasContext *ctx)
3574 {
3575 #if defined(CONFIG_USER_ONLY)
3576 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3577 #else
3578 /* Restore CPU state */
3579 if (unlikely(!ctx->mem_idx)) {
3580 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3581 return;
3582 }
3583 gen_helper_rfi();
3584 gen_sync_exception(ctx);
3585 #endif
3586 }
3587
3588 #if defined(TARGET_PPC64)
3589 static void gen_rfid(DisasContext *ctx)
3590 {
3591 #if defined(CONFIG_USER_ONLY)
3592 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3593 #else
3594 /* Restore CPU state */
3595 if (unlikely(!ctx->mem_idx)) {
3596 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3597 return;
3598 }
3599 gen_helper_rfid();
3600 gen_sync_exception(ctx);
3601 #endif
3602 }
3603
3604 static void gen_hrfid(DisasContext *ctx)
3605 {
3606 #if defined(CONFIG_USER_ONLY)
3607 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3608 #else
3609 /* Restore CPU state */
3610 if (unlikely(ctx->mem_idx <= 1)) {
3611 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3612 return;
3613 }
3614 gen_helper_hrfid();
3615 gen_sync_exception(ctx);
3616 #endif
3617 }
3618 #endif
3619
3620 /* sc */
3621 #if defined(CONFIG_USER_ONLY)
3622 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3623 #else
3624 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3625 #endif
3626 static void gen_sc(DisasContext *ctx)
3627 {
3628 uint32_t lev;
3629
3630 lev = (ctx->opcode >> 5) & 0x7F;
3631 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3632 }
3633
3634 /*** Trap ***/
3635
3636 /* tw */
3637 static void gen_tw(DisasContext *ctx)
3638 {
3639 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3640 /* Update the nip since this might generate a trap exception */
3641 gen_update_nip(ctx, ctx->nip);
3642 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3643 tcg_temp_free_i32(t0);
3644 }
3645
3646 /* twi */
3647 static void gen_twi(DisasContext *ctx)
3648 {
3649 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3650 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3651 /* Update the nip since this might generate a trap exception */
3652 gen_update_nip(ctx, ctx->nip);
3653 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3654 tcg_temp_free(t0);
3655 tcg_temp_free_i32(t1);
3656 }
3657
3658 #if defined(TARGET_PPC64)
3659 /* td */
3660 static void gen_td(DisasContext *ctx)
3661 {
3662 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3663 /* Update the nip since this might generate a trap exception */
3664 gen_update_nip(ctx, ctx->nip);
3665 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3666 tcg_temp_free_i32(t0);
3667 }
3668
3669 /* tdi */
3670 static void gen_tdi(DisasContext *ctx)
3671 {
3672 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3673 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3674 /* Update the nip since this might generate a trap exception */
3675 gen_update_nip(ctx, ctx->nip);
3676 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3677 tcg_temp_free(t0);
3678 tcg_temp_free_i32(t1);
3679 }
3680 #endif
3681
3682 /*** Processor control ***/
3683
3684 /* mcrxr */
3685 static void gen_mcrxr(DisasContext *ctx)
3686 {
3687 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3688 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3689 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3690 }
3691
3692 /* mfcr mfocrf */
3693 static void gen_mfcr(DisasContext *ctx)
3694 {
3695 uint32_t crm, crn;
3696
3697 if (likely(ctx->opcode & 0x00100000)) {
3698 crm = CRM(ctx->opcode);
3699 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3700 crn = ctz32 (crm);
3701 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3702 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3703 cpu_gpr[rD(ctx->opcode)], crn * 4);
3704 }
3705 } else {
3706 TCGv_i32 t0 = tcg_temp_new_i32();
3707 tcg_gen_mov_i32(t0, cpu_crf[0]);
3708 tcg_gen_shli_i32(t0, t0, 4);
3709 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3710 tcg_gen_shli_i32(t0, t0, 4);
3711 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3712 tcg_gen_shli_i32(t0, t0, 4);
3713 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3714 tcg_gen_shli_i32(t0, t0, 4);
3715 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3716 tcg_gen_shli_i32(t0, t0, 4);
3717 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3718 tcg_gen_shli_i32(t0, t0, 4);
3719 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3720 tcg_gen_shli_i32(t0, t0, 4);
3721 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3722 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3723 tcg_temp_free_i32(t0);
3724 }
3725 }
3726
3727 /* mfmsr */
3728 static void gen_mfmsr(DisasContext *ctx)
3729 {
3730 #if defined(CONFIG_USER_ONLY)
3731 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3732 #else
3733 if (unlikely(!ctx->mem_idx)) {
3734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3735 return;
3736 }
3737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3738 #endif
3739 }
3740
3741 static void spr_noaccess(void *opaque, int gprn, int sprn)
3742 {
3743 #if 0
3744 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3745 printf("ERROR: try to access SPR %d !\n", sprn);
3746 #endif
3747 }
3748 #define SPR_NOACCESS (&spr_noaccess)
3749
3750 /* mfspr */
3751 static inline void gen_op_mfspr(DisasContext *ctx)
3752 {
3753 void (*read_cb)(void *opaque, int gprn, int sprn);
3754 uint32_t sprn = SPR(ctx->opcode);
3755
3756 #if !defined(CONFIG_USER_ONLY)
3757 if (ctx->mem_idx == 2)
3758 read_cb = ctx->spr_cb[sprn].hea_read;
3759 else if (ctx->mem_idx)
3760 read_cb = ctx->spr_cb[sprn].oea_read;
3761 else
3762 #endif
3763 read_cb = ctx->spr_cb[sprn].uea_read;
3764 if (likely(read_cb != NULL)) {
3765 if (likely(read_cb != SPR_NOACCESS)) {
3766 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3767 } else {
3768 /* Privilege exception */
3769 /* This is a hack to avoid warnings when running Linux:
3770 * this OS breaks the PowerPC virtualisation model,
3771 * allowing userland application to read the PVR
3772 */
3773 if (sprn != SPR_PVR) {
3774 qemu_log("Trying to read privileged spr %d %03x at "
3775 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3776 printf("Trying to read privileged spr %d %03x at "
3777 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3778 }
3779 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3780 }
3781 } else {
3782 /* Not defined */
3783 qemu_log("Trying to read invalid spr %d %03x at "
3784 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3785 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3786 sprn, sprn, ctx->nip);
3787 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3788 }
3789 }
3790
3791 static void gen_mfspr(DisasContext *ctx)
3792 {
3793 gen_op_mfspr(ctx);
3794 }
3795
3796 /* mftb */
3797 static void gen_mftb(DisasContext *ctx)
3798 {
3799 gen_op_mfspr(ctx);
3800 }
3801
3802 /* mtcrf mtocrf*/
3803 static void gen_mtcrf(DisasContext *ctx)
3804 {
3805 uint32_t crm, crn;
3806
3807 crm = CRM(ctx->opcode);
3808 if (likely((ctx->opcode & 0x00100000))) {
3809 if (crm && ((crm & (crm - 1)) == 0)) {
3810 TCGv_i32 temp = tcg_temp_new_i32();
3811 crn = ctz32 (crm);
3812 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3813 tcg_gen_shri_i32(temp, temp, crn * 4);
3814 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3815 tcg_temp_free_i32(temp);
3816 }
3817 } else {
3818 TCGv_i32 temp = tcg_temp_new_i32();
3819 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3820 for (crn = 0 ; crn < 8 ; crn++) {
3821 if (crm & (1 << crn)) {
3822 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3823 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3824 }
3825 }
3826 tcg_temp_free_i32(temp);
3827 }
3828 }
3829
3830 /* mtmsr */
3831 #if defined(TARGET_PPC64)
3832 static void gen_mtmsrd(DisasContext *ctx)
3833 {
3834 #if defined(CONFIG_USER_ONLY)
3835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3836 #else
3837 if (unlikely(!ctx->mem_idx)) {
3838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3839 return;
3840 }
3841 if (ctx->opcode & 0x00010000) {
3842 /* Special form that does not need any synchronisation */
3843 TCGv t0 = tcg_temp_new();
3844 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3845 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3846 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3847 tcg_temp_free(t0);
3848 } else {
3849 /* XXX: we need to update nip before the store
3850 * if we enter power saving mode, we will exit the loop
3851 * directly from ppc_store_msr
3852 */
3853 gen_update_nip(ctx, ctx->nip);
3854 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3855 /* Must stop the translation as machine state (may have) changed */
3856 /* Note that mtmsr is not always defined as context-synchronizing */
3857 gen_stop_exception(ctx);
3858 }
3859 #endif
3860 }
3861 #endif
3862
3863 static void gen_mtmsr(DisasContext *ctx)
3864 {
3865 #if defined(CONFIG_USER_ONLY)
3866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3867 #else
3868 if (unlikely(!ctx->mem_idx)) {
3869 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3870 return;
3871 }
3872 if (ctx->opcode & 0x00010000) {
3873 /* Special form that does not need any synchronisation */
3874 TCGv t0 = tcg_temp_new();
3875 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3876 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3877 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3878 tcg_temp_free(t0);
3879 } else {
3880 /* XXX: we need to update nip before the store
3881 * if we enter power saving mode, we will exit the loop
3882 * directly from ppc_store_msr
3883 */
3884 gen_update_nip(ctx, ctx->nip);
3885 #if defined(TARGET_PPC64)
3886 if (!ctx->sf_mode) {
3887 TCGv t0 = tcg_temp_new();
3888 TCGv t1 = tcg_temp_new();
3889 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
3890 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
3891 tcg_gen_or_tl(t0, t0, t1);
3892 tcg_temp_free(t1);
3893 gen_helper_store_msr(t0);
3894 tcg_temp_free(t0);
3895 } else
3896 #endif
3897 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3898 /* Must stop the translation as machine state (may have) changed */
3899 /* Note that mtmsr is not always defined as context-synchronizing */
3900 gen_stop_exception(ctx);
3901 }
3902 #endif
3903 }
3904
3905 /* mtspr */
3906 static void gen_mtspr(DisasContext *ctx)
3907 {
3908 void (*write_cb)(void *opaque, int sprn, int gprn);
3909 uint32_t sprn = SPR(ctx->opcode);
3910
3911 #if !defined(CONFIG_USER_ONLY)
3912 if (ctx->mem_idx == 2)
3913 write_cb = ctx->spr_cb[sprn].hea_write;
3914 else if (ctx->mem_idx)
3915 write_cb = ctx->spr_cb[sprn].oea_write;
3916 else
3917 #endif
3918 write_cb = ctx->spr_cb[sprn].uea_write;
3919 if (likely(write_cb != NULL)) {
3920 if (likely(write_cb != SPR_NOACCESS)) {
3921 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3922 } else {
3923 /* Privilege exception */
3924 qemu_log("Trying to write privileged spr %d %03x at "
3925 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3926 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3927 "\n", sprn, sprn, ctx->nip);
3928 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3929 }
3930 } else {
3931 /* Not defined */
3932 qemu_log("Trying to write invalid spr %d %03x at "
3933 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3934 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3935 sprn, sprn, ctx->nip);
3936 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3937 }
3938 }
3939
3940 /*** Cache management ***/
3941
3942 /* dcbf */
3943 static void gen_dcbf(DisasContext *ctx)
3944 {
3945 /* XXX: specification says this is treated as a load by the MMU */
3946 TCGv t0;
3947 gen_set_access_type(ctx, ACCESS_CACHE);
3948 t0 = tcg_temp_new();
3949 gen_addr_reg_index(ctx, t0);
3950 gen_qemu_ld8u(ctx, t0, t0);
3951 tcg_temp_free(t0);
3952 }
3953
3954 /* dcbi (Supervisor only) */
3955 static void gen_dcbi(DisasContext *ctx)
3956 {
3957 #if defined(CONFIG_USER_ONLY)
3958 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3959 #else
3960 TCGv EA, val;
3961 if (unlikely(!ctx->mem_idx)) {
3962 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3963 return;
3964 }
3965 EA = tcg_temp_new();
3966 gen_set_access_type(ctx, ACCESS_CACHE);
3967 gen_addr_reg_index(ctx, EA);
3968 val = tcg_temp_new();
3969 /* XXX: specification says this should be treated as a store by the MMU */
3970 gen_qemu_ld8u(ctx, val, EA);
3971 gen_qemu_st8(ctx, val, EA);
3972 tcg_temp_free(val);
3973 tcg_temp_free(EA);
3974 #endif
3975 }
3976
3977 /* dcdst */
3978 static void gen_dcbst(DisasContext *ctx)
3979 {
3980 /* XXX: specification say this is treated as a load by the MMU */
3981 TCGv t0;
3982 gen_set_access_type(ctx, ACCESS_CACHE);
3983 t0 = tcg_temp_new();
3984 gen_addr_reg_index(ctx, t0);
3985 gen_qemu_ld8u(ctx, t0, t0);
3986 tcg_temp_free(t0);
3987 }
3988
3989 /* dcbt */
3990 static void gen_dcbt(DisasContext *ctx)
3991 {
3992 /* interpreted as no-op */
3993 /* XXX: specification say this is treated as a load by the MMU
3994 * but does not generate any exception
3995 */
3996 }
3997
3998 /* dcbtst */
3999 static void gen_dcbtst(DisasContext *ctx)
4000 {
4001 /* interpreted as no-op */
4002 /* XXX: specification say this is treated as a load by the MMU
4003 * but does not generate any exception
4004 */
4005 }
4006
4007 /* dcbz */
4008 static void gen_dcbz(DisasContext *ctx)
4009 {
4010 TCGv t0;
4011 gen_set_access_type(ctx, ACCESS_CACHE);
4012 /* NIP cannot be restored if the memory exception comes from an helper */
4013 gen_update_nip(ctx, ctx->nip - 4);
4014 t0 = tcg_temp_new();
4015 gen_addr_reg_index(ctx, t0);
4016 gen_helper_dcbz(t0);
4017 tcg_temp_free(t0);
4018 }
4019
4020 static void gen_dcbz_970(DisasContext *ctx)
4021 {
4022 TCGv t0;
4023 gen_set_access_type(ctx, ACCESS_CACHE);
4024 /* NIP cannot be restored if the memory exception comes from an helper */
4025 gen_update_nip(ctx, ctx->nip - 4);
4026 t0 = tcg_temp_new();
4027 gen_addr_reg_index(ctx, t0);
4028 if (ctx->opcode & 0x00200000)
4029 gen_helper_dcbz(t0);
4030 else
4031 gen_helper_dcbz_970(t0);
4032 tcg_temp_free(t0);
4033 }
4034
4035 /* dst / dstt */
4036 static void gen_dst(DisasContext *ctx)
4037 {
4038 if (rA(ctx->opcode) == 0) {
4039 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4040 } else {
4041 /* interpreted as no-op */
4042 }
4043 }
4044
4045 /* dstst /dststt */
4046 static void gen_dstst(DisasContext *ctx)
4047 {
4048 if (rA(ctx->opcode) == 0) {
4049 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4050 } else {
4051 /* interpreted as no-op */
4052 }
4053
4054 }
4055
4056 /* dss / dssall */
4057 static void gen_dss(DisasContext *ctx)
4058 {
4059 /* interpreted as no-op */
4060 }
4061
4062 /* icbi */
4063 static void gen_icbi(DisasContext *ctx)
4064 {
4065 TCGv t0;
4066 gen_set_access_type(ctx, ACCESS_CACHE);
4067 /* NIP cannot be restored if the memory exception comes from an helper */
4068 gen_update_nip(ctx, ctx->nip - 4);
4069 t0 = tcg_temp_new();
4070 gen_addr_reg_index(ctx, t0);
4071 gen_helper_icbi(t0);
4072 tcg_temp_free(t0);
4073 }
4074
4075 /* Optional: */
4076 /* dcba */
4077 static void gen_dcba(DisasContext *ctx)
4078 {
4079 /* interpreted as no-op */
4080 /* XXX: specification say this is treated as a store by the MMU
4081 * but does not generate any exception
4082 */
4083 }
4084
4085 /*** Segment register manipulation ***/
4086 /* Supervisor only: */
4087
4088 /* mfsr */
4089 static void gen_mfsr(DisasContext *ctx)
4090 {
4091 #if defined(CONFIG_USER_ONLY)
4092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4093 #else
4094 TCGv t0;
4095 if (unlikely(!ctx->mem_idx)) {
4096 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4097 return;
4098 }
4099 t0 = tcg_const_tl(SR(ctx->opcode));
4100 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4101 tcg_temp_free(t0);
4102 #endif
4103 }
4104
4105 /* mfsrin */
4106 static void gen_mfsrin(DisasContext *ctx)
4107 {
4108 #if defined(CONFIG_USER_ONLY)
4109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4110 #else
4111 TCGv t0;
4112 if (unlikely(!ctx->mem_idx)) {
4113 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4114 return;
4115 }
4116 t0 = tcg_temp_new();
4117 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4118 tcg_gen_andi_tl(t0, t0, 0xF);
4119 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4120 tcg_temp_free(t0);
4121 #endif
4122 }
4123
4124 /* mtsr */
4125 static void gen_mtsr(DisasContext *ctx)
4126 {
4127 #if defined(CONFIG_USER_ONLY)
4128 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4129 #else
4130 TCGv t0;
4131 if (unlikely(!ctx->mem_idx)) {
4132 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4133 return;
4134 }
4135 t0 = tcg_const_tl(SR(ctx->opcode));
4136 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4137 tcg_temp_free(t0);
4138 #endif
4139 }
4140
4141 /* mtsrin */
4142 static void gen_mtsrin(DisasContext *ctx)
4143 {
4144 #if defined(CONFIG_USER_ONLY)
4145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4146 #else
4147 TCGv t0;
4148 if (unlikely(!ctx->mem_idx)) {
4149 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4150 return;
4151 }
4152 t0 = tcg_temp_new();
4153 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4154 tcg_gen_andi_tl(t0, t0, 0xF);
4155 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4156 tcg_temp_free(t0);
4157 #endif
4158 }
4159
4160 #if defined(TARGET_PPC64)
4161 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4162
4163 /* mfsr */
4164 static void gen_mfsr_64b(DisasContext *ctx)
4165 {
4166 #if defined(CONFIG_USER_ONLY)
4167 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4168 #else
4169 TCGv t0;
4170 if (unlikely(!ctx->mem_idx)) {
4171 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4172 return;
4173 }
4174 t0 = tcg_const_tl(SR(ctx->opcode));
4175 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4176 tcg_temp_free(t0);
4177 #endif
4178 }
4179
4180 /* mfsrin */
4181 static void gen_mfsrin_64b(DisasContext *ctx)
4182 {
4183 #if defined(CONFIG_USER_ONLY)
4184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4185 #else
4186 TCGv t0;
4187 if (unlikely(!ctx->mem_idx)) {
4188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4189 return;
4190 }
4191 t0 = tcg_temp_new();
4192 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4193 tcg_gen_andi_tl(t0, t0, 0xF);
4194 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4195 tcg_temp_free(t0);
4196 #endif
4197 }
4198
4199 /* mtsr */
4200 static void gen_mtsr_64b(DisasContext *ctx)
4201 {
4202 #if defined(CONFIG_USER_ONLY)
4203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4204 #else
4205 TCGv t0;
4206 if (unlikely(!ctx->mem_idx)) {
4207 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4208 return;
4209 }
4210 t0 = tcg_const_tl(SR(ctx->opcode));
4211 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4212 tcg_temp_free(t0);
4213 #endif
4214 }
4215
4216 /* mtsrin */
4217 static void gen_mtsrin_64b(DisasContext *ctx)
4218 {
4219 #if defined(CONFIG_USER_ONLY)
4220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4221 #else
4222 TCGv t0;
4223 if (unlikely(!ctx->mem_idx)) {
4224 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4225 return;
4226 }
4227 t0 = tcg_temp_new();
4228 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4229 tcg_gen_andi_tl(t0, t0, 0xF);
4230 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4231 tcg_temp_free(t0);
4232 #endif
4233 }
4234
4235 /* slbmte */
4236 static void gen_slbmte(DisasContext *ctx)
4237 {
4238 #if defined(CONFIG_USER_ONLY)
4239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4240 #else
4241 if (unlikely(!ctx->mem_idx)) {
4242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4243 return;
4244 }
4245 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4246 #endif
4247 }
4248
4249 static void gen_slbmfee(DisasContext *ctx)
4250 {
4251 #if defined(CONFIG_USER_ONLY)
4252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4253 #else
4254 if (unlikely(!ctx->mem_idx)) {
4255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4256 return;
4257 }
4258 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)],
4259 cpu_gpr[rB(ctx->opcode)]);
4260 #endif
4261 }
4262
4263 static void gen_slbmfev(DisasContext *ctx)
4264 {
4265 #if defined(CONFIG_USER_ONLY)
4266 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4267 #else
4268 if (unlikely(!ctx->mem_idx)) {
4269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4270 return;
4271 }
4272 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)],
4273 cpu_gpr[rB(ctx->opcode)]);
4274 #endif
4275 }
4276 #endif /* defined(TARGET_PPC64) */
4277
4278 /*** Lookaside buffer management ***/
4279 /* Optional & mem_idx only: */
4280
4281 /* tlbia */
4282 static void gen_tlbia(DisasContext *ctx)
4283 {
4284 #if defined(CONFIG_USER_ONLY)
4285 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4286 #else
4287 if (unlikely(!ctx->mem_idx)) {
4288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4289 return;
4290 }
4291 gen_helper_tlbia();
4292 #endif
4293 }
4294
4295 /* tlbiel */
4296 static void gen_tlbiel(DisasContext *ctx)
4297 {
4298 #if defined(CONFIG_USER_ONLY)
4299 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4300 #else
4301 if (unlikely(!ctx->mem_idx)) {
4302 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4303 return;
4304 }
4305 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4306 #endif
4307 }
4308
4309 /* tlbie */
4310 static void gen_tlbie(DisasContext *ctx)
4311 {
4312 #if defined(CONFIG_USER_ONLY)
4313 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4314 #else
4315 if (unlikely(!ctx->mem_idx)) {
4316 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4317 return;
4318 }
4319 #if defined(TARGET_PPC64)
4320 if (!ctx->sf_mode) {
4321 TCGv t0 = tcg_temp_new();
4322 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4323 gen_helper_tlbie(t0);
4324 tcg_temp_free(t0);
4325 } else
4326 #endif
4327 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4328 #endif
4329 }
4330
4331 /* tlbsync */
4332 static void gen_tlbsync(DisasContext *ctx)
4333 {
4334 #if defined(CONFIG_USER_ONLY)
4335 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4336 #else
4337 if (unlikely(!ctx->mem_idx)) {
4338 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4339 return;
4340 }
4341 /* This has no effect: it should ensure that all previous
4342 * tlbie have completed
4343 */
4344 gen_stop_exception(ctx);
4345 #endif
4346 }
4347
4348 #if defined(TARGET_PPC64)
4349 /* slbia */
4350 static void gen_slbia(DisasContext *ctx)
4351 {
4352 #if defined(CONFIG_USER_ONLY)
4353 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4354 #else
4355 if (unlikely(!ctx->mem_idx)) {
4356 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4357 return;
4358 }
4359 gen_helper_slbia();
4360 #endif
4361 }
4362
4363 /* slbie */
4364 static void gen_slbie(DisasContext *ctx)
4365 {
4366 #if defined(CONFIG_USER_ONLY)
4367 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4368 #else
4369 if (unlikely(!ctx->mem_idx)) {
4370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4371 return;
4372 }
4373 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4374 #endif
4375 }
4376 #endif
4377
4378 /*** External control ***/
4379 /* Optional: */
4380
4381 /* eciwx */
4382 static void gen_eciwx(DisasContext *ctx)
4383 {
4384 TCGv t0;
4385 /* Should check EAR[E] ! */
4386 gen_set_access_type(ctx, ACCESS_EXT);
4387 t0 = tcg_temp_new();
4388 gen_addr_reg_index(ctx, t0);
4389 gen_check_align(ctx, t0, 0x03);
4390 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4391 tcg_temp_free(t0);
4392 }
4393
4394 /* ecowx */
4395 static void gen_ecowx(DisasContext *ctx)
4396 {
4397 TCGv t0;
4398 /* Should check EAR[E] ! */
4399 gen_set_access_type(ctx, ACCESS_EXT);
4400 t0 = tcg_temp_new();
4401 gen_addr_reg_index(ctx, t0);
4402 gen_check_align(ctx, t0, 0x03);
4403 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4404 tcg_temp_free(t0);
4405 }
4406
4407 /* PowerPC 601 specific instructions */
4408
4409 /* abs - abs. */
4410 static void gen_abs(DisasContext *ctx)
4411 {
4412 int l1 = gen_new_label();
4413 int l2 = gen_new_label();
4414 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4415 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4416 tcg_gen_br(l2);
4417 gen_set_label(l1);
4418 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4419 gen_set_label(l2);
4420 if (unlikely(Rc(ctx->opcode) != 0))
4421 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4422 }
4423
4424 /* abso - abso. */
4425 static void gen_abso(DisasContext *ctx)
4426 {
4427 int l1 = gen_new_label();
4428 int l2 = gen_new_label();
4429 int l3 = gen_new_label();
4430 /* Start with XER OV disabled, the most likely case */
4431 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4432 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4433 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4434 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4435 tcg_gen_br(l2);
4436 gen_set_label(l1);
4437 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4438 tcg_gen_br(l3);
4439 gen_set_label(l2);
4440 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4441 gen_set_label(l3);
4442 if (unlikely(Rc(ctx->opcode) != 0))
4443 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4444 }
4445
4446 /* clcs */
4447 static void gen_clcs(DisasContext *ctx)
4448 {
4449 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4450 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4451 tcg_temp_free_i32(t0);
4452 /* Rc=1 sets CR0 to an undefined state */
4453 }
4454
4455 /* div - div. */
4456 static void gen_div(DisasContext *ctx)
4457 {
4458 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4459 if (unlikely(Rc(ctx->opcode) != 0))
4460 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4461 }
4462
4463 /* divo - divo. */
4464 static void gen_divo(DisasContext *ctx)
4465 {
4466 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4467 if (unlikely(Rc(ctx->opcode) != 0))
4468 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4469 }
4470
4471 /* divs - divs. */
4472 static void gen_divs(DisasContext *ctx)
4473 {
4474 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4475 if (unlikely(Rc(ctx->opcode) != 0))
4476 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4477 }
4478
4479 /* divso - divso. */
4480 static void gen_divso(DisasContext *ctx)
4481 {
4482 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4483 if (unlikely(Rc(ctx->opcode) != 0))
4484 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4485 }
4486
4487 /* doz - doz. */
4488 static void gen_doz(DisasContext *ctx)
4489 {
4490 int l1 = gen_new_label();
4491 int l2 = gen_new_label();
4492 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4493 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4494 tcg_gen_br(l2);
4495 gen_set_label(l1);
4496 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4497 gen_set_label(l2);
4498 if (unlikely(Rc(ctx->opcode) != 0))
4499 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4500 }
4501
4502 /* dozo - dozo. */
4503 static void gen_dozo(DisasContext *ctx)
4504 {
4505 int l1 = gen_new_label();
4506 int l2 = gen_new_label();
4507 TCGv t0 = tcg_temp_new();
4508 TCGv t1 = tcg_temp_new();
4509 TCGv t2 = tcg_temp_new();
4510 /* Start with XER OV disabled, the most likely case */
4511 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4512 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4513 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4514 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4515 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4516 tcg_gen_andc_tl(t1, t1, t2);
4517 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4518 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4519 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4520 tcg_gen_br(l2);
4521 gen_set_label(l1);
4522 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4523 gen_set_label(l2);
4524 tcg_temp_free(t0);
4525 tcg_temp_free(t1);
4526 tcg_temp_free(t2);
4527 if (unlikely(Rc(ctx->opcode) != 0))
4528 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4529 }
4530
4531 /* dozi */
4532 static void gen_dozi(DisasContext *ctx)
4533 {
4534 target_long simm = SIMM(ctx->opcode);
4535 int l1 = gen_new_label();
4536 int l2 = gen_new_label();
4537 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4538 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4539 tcg_gen_br(l2);
4540 gen_set_label(l1);
4541 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4542 gen_set_label(l2);
4543 if (unlikely(Rc(ctx->opcode) != 0))
4544 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4545 }
4546
4547 /* lscbx - lscbx. */
4548 static void gen_lscbx(DisasContext *ctx)
4549 {
4550 TCGv t0 = tcg_temp_new();
4551 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4552 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4553 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4554
4555 gen_addr_reg_index(ctx, t0);
4556 /* NIP cannot be restored if the memory exception comes from an helper */
4557 gen_update_nip(ctx, ctx->nip - 4);
4558 gen_helper_lscbx(t0, t0, t1, t2, t3);
4559 tcg_temp_free_i32(t1);
4560 tcg_temp_free_i32(t2);
4561 tcg_temp_free_i32(t3);
4562 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4563 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4564 if (unlikely(Rc(ctx->opcode) != 0))
4565 gen_set_Rc0(ctx, t0);
4566 tcg_temp_free(t0);
4567 }
4568
4569 /* maskg - maskg. */
4570 static void gen_maskg(DisasContext *ctx)
4571 {
4572 int l1 = gen_new_label();
4573 TCGv t0 = tcg_temp_new();
4574 TCGv t1 = tcg_temp_new();
4575 TCGv t2 = tcg_temp_new();
4576 TCGv t3 = tcg_temp_new();
4577 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4578 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4579 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4580 tcg_gen_addi_tl(t2, t0, 1);
4581 tcg_gen_shr_tl(t2, t3, t2);
4582 tcg_gen_shr_tl(t3, t3, t1);
4583 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4584 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4585 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4586 gen_set_label(l1);
4587 tcg_temp_free(t0);
4588 tcg_temp_free(t1);
4589 tcg_temp_free(t2);
4590 tcg_temp_free(t3);
4591 if (unlikely(Rc(ctx->opcode) != 0))
4592 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4593 }
4594
4595 /* maskir - maskir. */
4596 static void gen_maskir(DisasContext *ctx)
4597 {
4598 TCGv t0 = tcg_temp_new();
4599 TCGv t1 = tcg_temp_new();
4600 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4601 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4602 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4603 tcg_temp_free(t0);
4604 tcg_temp_free(t1);
4605 if (unlikely(Rc(ctx->opcode) != 0))
4606 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4607 }
4608
4609 /* mul - mul. */
4610 static void gen_mul(DisasContext *ctx)
4611 {
4612 TCGv_i64 t0 = tcg_temp_new_i64();
4613 TCGv_i64 t1 = tcg_temp_new_i64();
4614 TCGv t2 = tcg_temp_new();
4615 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4616 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4617 tcg_gen_mul_i64(t0, t0, t1);
4618 tcg_gen_trunc_i64_tl(t2, t0);
4619 gen_store_spr(SPR_MQ, t2);
4620 tcg_gen_shri_i64(t1, t0, 32);
4621 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4622 tcg_temp_free_i64(t0);
4623 tcg_temp_free_i64(t1);
4624 tcg_temp_free(t2);
4625 if (unlikely(Rc(ctx->opcode) != 0))
4626 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4627 }
4628
4629 /* mulo - mulo. */
4630 static void gen_mulo(DisasContext *ctx)
4631 {
4632 int l1 = gen_new_label();
4633 TCGv_i64 t0 = tcg_temp_new_i64();
4634 TCGv_i64 t1 = tcg_temp_new_i64();
4635 TCGv t2 = tcg_temp_new();
4636 /* Start with XER OV disabled, the most likely case */
4637 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4638 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4639 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4640 tcg_gen_mul_i64(t0, t0, t1);
4641 tcg_gen_trunc_i64_tl(t2, t0);
4642 gen_store_spr(SPR_MQ, t2);
4643 tcg_gen_shri_i64(t1, t0, 32);
4644 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4645 tcg_gen_ext32s_i64(t1, t0);
4646 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4647 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4648 gen_set_label(l1);
4649 tcg_temp_free_i64(t0);
4650 tcg_temp_free_i64(t1);
4651 tcg_temp_free(t2);
4652 if (unlikely(Rc(ctx->opcode) != 0))
4653 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4654 }
4655
4656 /* nabs - nabs. */
4657 static void gen_nabs(DisasContext *ctx)
4658 {
4659 int l1 = gen_new_label();
4660 int l2 = gen_new_label();
4661 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4662 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4663 tcg_gen_br(l2);
4664 gen_set_label(l1);
4665 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4666 gen_set_label(l2);
4667 if (unlikely(Rc(ctx->opcode) != 0))
4668 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4669 }
4670
4671 /* nabso - nabso. */
4672 static void gen_nabso(DisasContext *ctx)
4673 {
4674 int l1 = gen_new_label();
4675 int l2 = gen_new_label();
4676 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4677 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4678 tcg_gen_br(l2);
4679 gen_set_label(l1);
4680 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4681 gen_set_label(l2);
4682 /* nabs never overflows */
4683 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4684 if (unlikely(Rc(ctx->opcode) != 0))
4685 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4686 }
4687
4688 /* rlmi - rlmi. */
4689 static void gen_rlmi(DisasContext *ctx)
4690 {
4691 uint32_t mb = MB(ctx->opcode);
4692 uint32_t me = ME(ctx->opcode);
4693 TCGv t0 = tcg_temp_new();
4694 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4695 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4696 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4697 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4698 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4699 tcg_temp_free(t0);
4700 if (unlikely(Rc(ctx->opcode) != 0))
4701 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4702 }
4703
4704 /* rrib - rrib. */
4705 static void gen_rrib(DisasContext *ctx)
4706 {
4707 TCGv t0 = tcg_temp_new();
4708 TCGv t1 = tcg_temp_new();
4709 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4710 tcg_gen_movi_tl(t1, 0x80000000);
4711 tcg_gen_shr_tl(t1, t1, t0);
4712 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4713 tcg_gen_and_tl(t0, t0, t1);
4714 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4715 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4716 tcg_temp_free(t0);
4717 tcg_temp_free(t1);
4718 if (unlikely(Rc(ctx->opcode) != 0))
4719 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4720 }
4721
4722 /* sle - sle. */
4723 static void gen_sle(DisasContext *ctx)
4724 {
4725 TCGv t0 = tcg_temp_new();
4726 TCGv t1 = tcg_temp_new();
4727 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4728 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4729 tcg_gen_subfi_tl(t1, 32, t1);
4730 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4731 tcg_gen_or_tl(t1, t0, t1);
4732 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4733 gen_store_spr(SPR_MQ, t1);
4734 tcg_temp_free(t0);
4735 tcg_temp_free(t1);
4736 if (unlikely(Rc(ctx->opcode) != 0))
4737 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4738 }
4739
4740 /* sleq - sleq. */
4741 static void gen_sleq(DisasContext *ctx)
4742 {
4743 TCGv t0 = tcg_temp_new();
4744 TCGv t1 = tcg_temp_new();
4745 TCGv t2 = tcg_temp_new();
4746 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4747 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4748 tcg_gen_shl_tl(t2, t2, t0);
4749 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4750 gen_load_spr(t1, SPR_MQ);
4751 gen_store_spr(SPR_MQ, t0);
4752 tcg_gen_and_tl(t0, t0, t2);
4753 tcg_gen_andc_tl(t1, t1, t2);
4754 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4755 tcg_temp_free(t0);
4756 tcg_temp_free(t1);
4757 tcg_temp_free(t2);
4758 if (unlikely(Rc(ctx->opcode) != 0))
4759 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4760 }
4761
4762 /* sliq - sliq. */
4763 static void gen_sliq(DisasContext *ctx)
4764 {
4765 int sh = SH(ctx->opcode);
4766 TCGv t0 = tcg_temp_new();
4767 TCGv t1 = tcg_temp_new();
4768 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4769 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4770 tcg_gen_or_tl(t1, t0, t1);
4771 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4772 gen_store_spr(SPR_MQ, t1);
4773 tcg_temp_free(t0);
4774 tcg_temp_free(t1);
4775 if (unlikely(Rc(ctx->opcode) != 0))
4776 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4777 }
4778
4779 /* slliq - slliq. */
4780 static void gen_slliq(DisasContext *ctx)
4781 {
4782 int sh = SH(ctx->opcode);
4783 TCGv t0 = tcg_temp_new();
4784 TCGv t1 = tcg_temp_new();
4785 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4786 gen_load_spr(t1, SPR_MQ);
4787 gen_store_spr(SPR_MQ, t0);
4788 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4789 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4790 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4791 tcg_temp_free(t0);
4792 tcg_temp_free(t1);
4793 if (unlikely(Rc(ctx->opcode) != 0))
4794 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4795 }
4796
4797 /* sllq - sllq. */
4798 static void gen_sllq(DisasContext *ctx)
4799 {
4800 int l1 = gen_new_label();
4801 int l2 = gen_new_label();
4802 TCGv t0 = tcg_temp_local_new();
4803 TCGv t1 = tcg_temp_local_new();
4804 TCGv t2 = tcg_temp_local_new();
4805 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4806 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4807 tcg_gen_shl_tl(t1, t1, t2);
4808 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4809 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4810 gen_load_spr(t0, SPR_MQ);
4811 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4812 tcg_gen_br(l2);
4813 gen_set_label(l1);
4814 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4815 gen_load_spr(t2, SPR_MQ);
4816 tcg_gen_andc_tl(t1, t2, t1);
4817 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4818 gen_set_label(l2);
4819 tcg_temp_free(t0);
4820 tcg_temp_free(t1);
4821 tcg_temp_free(t2);
4822 if (unlikely(Rc(ctx->opcode) != 0))
4823 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4824 }
4825
4826 /* slq - slq. */
4827 static void gen_slq(DisasContext *ctx)
4828 {
4829 int l1 = gen_new_label();
4830 TCGv t0 = tcg_temp_new();
4831 TCGv t1 = tcg_temp_new();
4832 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4833 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4834 tcg_gen_subfi_tl(t1, 32, t1);
4835 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4836 tcg_gen_or_tl(t1, t0, t1);
4837 gen_store_spr(SPR_MQ, t1);
4838 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4839 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4840 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4841 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4842 gen_set_label(l1);
4843 tcg_temp_free(t0);
4844 tcg_temp_free(t1);
4845 if (unlikely(Rc(ctx->opcode) != 0))
4846 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4847 }
4848
4849 /* sraiq - sraiq. */
4850 static void gen_sraiq(DisasContext *ctx)
4851 {
4852 int sh = SH(ctx->opcode);
4853 int l1 = gen_new_label();
4854 TCGv t0 = tcg_temp_new();
4855 TCGv t1 = tcg_temp_new();
4856 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4857 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4858 tcg_gen_or_tl(t0, t0, t1);
4859 gen_store_spr(SPR_MQ, t0);
4860 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4861 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4862 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4863 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4864 gen_set_label(l1);
4865 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4866 tcg_temp_free(t0);
4867 tcg_temp_free(t1);
4868 if (unlikely(Rc(ctx->opcode) != 0))
4869 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4870 }
4871
4872 /* sraq - sraq. */
4873 static void gen_sraq(DisasContext *ctx)
4874 {
4875 int l1 = gen_new_label();
4876 int l2 = gen_new_label();
4877 TCGv t0 = tcg_temp_new();
4878 TCGv t1 = tcg_temp_local_new();
4879 TCGv t2 = tcg_temp_local_new();
4880 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4881 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4882 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4883 tcg_gen_subfi_tl(t2, 32, t2);
4884 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4885 tcg_gen_or_tl(t0, t0, t2);
4886 gen_store_spr(SPR_MQ, t0);
4887 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4888 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4889 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4890 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4891 gen_set_label(l1);
4892 tcg_temp_free(t0);
4893 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4894 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4895 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4896 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4897 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4898 gen_set_label(l2);
4899 tcg_temp_free(t1);
4900 tcg_temp_free(t2);
4901 if (unlikely(Rc(ctx->opcode) != 0))
4902 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4903 }
4904
4905 /* sre - sre. */
4906 static void gen_sre(DisasContext *ctx)
4907 {
4908 TCGv t0 = tcg_temp_new();
4909 TCGv t1 = tcg_temp_new();
4910 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4911 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4912 tcg_gen_subfi_tl(t1, 32, t1);
4913 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4914 tcg_gen_or_tl(t1, t0, t1);
4915 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4916 gen_store_spr(SPR_MQ, t1);
4917 tcg_temp_free(t0);
4918 tcg_temp_free(t1);
4919 if (unlikely(Rc(ctx->opcode) != 0))
4920 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4921 }
4922
4923 /* srea - srea. */
4924 static void gen_srea(DisasContext *ctx)
4925 {
4926 TCGv t0 = tcg_temp_new();
4927 TCGv t1 = tcg_temp_new();
4928 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4929 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4930 gen_store_spr(SPR_MQ, t0);
4931 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4932 tcg_temp_free(t0);
4933 tcg_temp_free(t1);
4934 if (unlikely(Rc(ctx->opcode) != 0))
4935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4936 }
4937
4938 /* sreq */
4939 static void gen_sreq(DisasContext *ctx)
4940 {
4941 TCGv t0 = tcg_temp_new();
4942 TCGv t1 = tcg_temp_new();
4943 TCGv t2 = tcg_temp_new();
4944 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4945 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4946 tcg_gen_shr_tl(t1, t1, t0);
4947 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4948 gen_load_spr(t2, SPR_MQ);
4949 gen_store_spr(SPR_MQ, t0);
4950 tcg_gen_and_tl(t0, t0, t1);
4951 tcg_gen_andc_tl(t2, t2, t1);
4952 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4953 tcg_temp_free(t0);
4954 tcg_temp_free(t1);
4955 tcg_temp_free(t2);
4956 if (unlikely(Rc(ctx->opcode) != 0))
4957 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4958 }
4959
4960 /* sriq */
4961 static void gen_sriq(DisasContext *ctx)
4962 {
4963 int sh = SH(ctx->opcode);
4964 TCGv t0 = tcg_temp_new();
4965 TCGv t1 = tcg_temp_new();
4966 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4967 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4968 tcg_gen_or_tl(t1, t0, t1);
4969 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4970 gen_store_spr(SPR_MQ, t1);
4971 tcg_temp_free(t0);
4972 tcg_temp_free(t1);
4973 if (unlikely(Rc(ctx->opcode) != 0))
4974 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4975 }
4976
4977 /* srliq */
4978 static void gen_srliq(DisasContext *ctx)
4979 {
4980 int sh = SH(ctx->opcode);
4981 TCGv t0 = tcg_temp_new();
4982 TCGv t1 = tcg_temp_new();
4983 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4984 gen_load_spr(t1, SPR_MQ);
4985 gen_store_spr(SPR_MQ, t0);
4986 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
4987 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
4988 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4989 tcg_temp_free(t0);
4990 tcg_temp_free(t1);
4991 if (unlikely(Rc(ctx->opcode) != 0))
4992 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4993 }
4994
4995 /* srlq */
4996 static void gen_srlq(DisasContext *ctx)
4997 {
4998 int l1 = gen_new_label();
4999 int l2 = gen_new_label();
5000 TCGv t0 = tcg_temp_local_new();
5001 TCGv t1 = tcg_temp_local_new();
5002 TCGv t2 = tcg_temp_local_new();
5003 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5004 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5005 tcg_gen_shr_tl(t2, t1, t2);
5006 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5007 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5008 gen_load_spr(t0, SPR_MQ);
5009 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5010 tcg_gen_br(l2);
5011 gen_set_label(l1);
5012 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5013 tcg_gen_and_tl(t0, t0, t2);
5014 gen_load_spr(t1, SPR_MQ);
5015 tcg_gen_andc_tl(t1, t1, t2);
5016 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5017 gen_set_label(l2);
5018 tcg_temp_free(t0);
5019 tcg_temp_free(t1);
5020 tcg_temp_free(t2);
5021 if (unlikely(Rc(ctx->opcode) != 0))
5022 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5023 }
5024
5025 /* srq */
5026 static void gen_srq(DisasContext *ctx)
5027 {
5028 int l1 = gen_new_label();
5029 TCGv t0 = tcg_temp_new();
5030 TCGv t1 = tcg_temp_new();
5031 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5032 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5033 tcg_gen_subfi_tl(t1, 32, t1);
5034 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5035 tcg_gen_or_tl(t1, t0, t1);
5036 gen_store_spr(SPR_MQ, t1);
5037 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5038 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5039 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5040 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5041 gen_set_label(l1);
5042 tcg_temp_free(t0);
5043 tcg_temp_free(t1);
5044 if (unlikely(Rc(ctx->opcode) != 0))
5045 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5046 }
5047
5048 /* PowerPC 602 specific instructions */
5049
5050 /* dsa */
5051 static void gen_dsa(DisasContext *ctx)
5052 {
5053 /* XXX: TODO */
5054 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5055 }
5056
5057 /* esa */
5058 static void gen_esa(DisasContext *ctx)
5059 {
5060 /* XXX: TODO */
5061 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5062 }
5063
5064 /* mfrom */
5065 static void gen_mfrom(DisasContext *ctx)
5066 {
5067 #if defined(CONFIG_USER_ONLY)
5068 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5069 #else
5070 if (unlikely(!ctx->mem_idx)) {
5071 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5072 return;
5073 }
5074 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5075 #endif
5076 }
5077
5078 /* 602 - 603 - G2 TLB management */
5079
5080 /* tlbld */
5081 static void gen_tlbld_6xx(DisasContext *ctx)
5082 {
5083 #if defined(CONFIG_USER_ONLY)
5084 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5085 #else
5086 if (unlikely(!ctx->mem_idx)) {
5087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5088 return;
5089 }
5090 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5091 #endif
5092 }
5093
5094 /* tlbli */
5095 static void gen_tlbli_6xx(DisasContext *ctx)
5096 {
5097 #if defined(CONFIG_USER_ONLY)
5098 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5099 #else
5100 if (unlikely(!ctx->mem_idx)) {
5101 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5102 return;
5103 }
5104 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5105 #endif
5106 }
5107
5108 /* 74xx TLB management */
5109
5110 /* tlbld */
5111 static void gen_tlbld_74xx(DisasContext *ctx)
5112 {
5113 #if defined(CONFIG_USER_ONLY)
5114 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5115 #else
5116 if (unlikely(!ctx->mem_idx)) {
5117 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5118 return;
5119 }
5120 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5121 #endif
5122 }
5123
5124 /* tlbli */
5125 static void gen_tlbli_74xx(DisasContext *ctx)
5126 {
5127 #if defined(CONFIG_USER_ONLY)
5128 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5129 #else
5130 if (unlikely(!ctx->mem_idx)) {
5131 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5132 return;
5133 }
5134 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5135 #endif
5136 }
5137
5138 /* POWER instructions not in PowerPC 601 */
5139
5140 /* clf */
5141 static void gen_clf(DisasContext *ctx)
5142 {
5143 /* Cache line flush: implemented as no-op */
5144 }
5145
5146 /* cli */
5147 static void gen_cli(DisasContext *ctx)
5148 {
5149 /* Cache line invalidate: privileged and treated as no-op */
5150 #if defined(CONFIG_USER_ONLY)
5151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5152 #else
5153 if (unlikely(!ctx->mem_idx)) {
5154 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5155 return;
5156 }
5157 #endif
5158 }
5159
5160 /* dclst */
5161 static void gen_dclst(DisasContext *ctx)
5162 {
5163 /* Data cache line store: treated as no-op */
5164 }
5165
5166 static void gen_mfsri(DisasContext *ctx)
5167 {
5168 #if defined(CONFIG_USER_ONLY)
5169 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5170 #else
5171 int ra = rA(ctx->opcode);
5172 int rd = rD(ctx->opcode);
5173 TCGv t0;
5174 if (unlikely(!ctx->mem_idx)) {
5175 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5176 return;
5177 }
5178 t0 = tcg_temp_new();
5179 gen_addr_reg_index(ctx, t0);
5180 tcg_gen_shri_tl(t0, t0, 28);
5181 tcg_gen_andi_tl(t0, t0, 0xF);
5182 gen_helper_load_sr(cpu_gpr[rd], t0);
5183 tcg_temp_free(t0);
5184 if (ra != 0 && ra != rd)
5185 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5186 #endif
5187 }
5188
5189 static void gen_rac(DisasContext *ctx)
5190 {
5191 #if defined(CONFIG_USER_ONLY)
5192 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5193 #else
5194 TCGv t0;
5195 if (unlikely(!ctx->mem_idx)) {
5196 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5197 return;
5198 }
5199 t0 = tcg_temp_new();
5200 gen_addr_reg_index(ctx, t0);
5201 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5202 tcg_temp_free(t0);
5203 #endif
5204 }
5205
5206 static void gen_rfsvc(DisasContext *ctx)
5207 {
5208 #if defined(CONFIG_USER_ONLY)
5209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5210 #else
5211 if (unlikely(!ctx->mem_idx)) {
5212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5213 return;
5214 }
5215 gen_helper_rfsvc();
5216 gen_sync_exception(ctx);
5217 #endif
5218 }
5219
5220 /* svc is not implemented for now */
5221
5222 /* POWER2 specific instructions */
5223 /* Quad manipulation (load/store two floats at a time) */
5224
5225 /* lfq */
5226 static void gen_lfq(DisasContext *ctx)
5227 {
5228 int rd = rD(ctx->opcode);
5229 TCGv t0;
5230 gen_set_access_type(ctx, ACCESS_FLOAT);
5231 t0 = tcg_temp_new();
5232 gen_addr_imm_index(ctx, t0, 0);
5233 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5234 gen_addr_add(ctx, t0, t0, 8);
5235 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5236 tcg_temp_free(t0);
5237 }
5238
5239 /* lfqu */
5240 static void gen_lfqu(DisasContext *ctx)
5241 {
5242 int ra = rA(ctx->opcode);
5243 int rd = rD(ctx->opcode);
5244 TCGv t0, t1;
5245 gen_set_access_type(ctx, ACCESS_FLOAT);
5246 t0 = tcg_temp_new();
5247 t1 = tcg_temp_new();
5248 gen_addr_imm_index(ctx, t0, 0);
5249 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5250 gen_addr_add(ctx, t1, t0, 8);
5251 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5252 if (ra != 0)
5253 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5254 tcg_temp_free(t0);
5255 tcg_temp_free(t1);
5256 }
5257
5258 /* lfqux */
5259 static void gen_lfqux(DisasContext *ctx)
5260 {
5261 int ra = rA(ctx->opcode);
5262 int rd = rD(ctx->opcode);
5263 gen_set_access_type(ctx, ACCESS_FLOAT);
5264 TCGv t0, t1;
5265 t0 = tcg_temp_new();
5266 gen_addr_reg_index(ctx, t0);
5267 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5268 t1 = tcg_temp_new();
5269 gen_addr_add(ctx, t1, t0, 8);
5270 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5271 tcg_temp_free(t1);
5272 if (ra != 0)
5273 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5274 tcg_temp_free(t0);
5275 }
5276
5277 /* lfqx */
5278 static void gen_lfqx(DisasContext *ctx)
5279 {
5280 int rd = rD(ctx->opcode);
5281 TCGv t0;
5282 gen_set_access_type(ctx, ACCESS_FLOAT);
5283 t0 = tcg_temp_new();
5284 gen_addr_reg_index(ctx, t0);
5285 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5286 gen_addr_add(ctx, t0, t0, 8);
5287 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5288 tcg_temp_free(t0);
5289 }
5290
5291 /* stfq */
5292 static void gen_stfq(DisasContext *ctx)
5293 {
5294 int rd = rD(ctx->opcode);
5295 TCGv t0;
5296 gen_set_access_type(ctx, ACCESS_FLOAT);
5297 t0 = tcg_temp_new();
5298 gen_addr_imm_index(ctx, t0, 0);
5299 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5300 gen_addr_add(ctx, t0, t0, 8);
5301 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5302 tcg_temp_free(t0);
5303 }
5304
5305 /* stfqu */
5306 static void gen_stfqu(DisasContext *ctx)
5307 {
5308 int ra = rA(ctx->opcode);
5309 int rd = rD(ctx->opcode);
5310 TCGv t0, t1;
5311 gen_set_access_type(ctx, ACCESS_FLOAT);
5312 t0 = tcg_temp_new();
5313 gen_addr_imm_index(ctx, t0, 0);
5314 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5315 t1 = tcg_temp_new();
5316 gen_addr_add(ctx, t1, t0, 8);
5317 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5318 tcg_temp_free(t1);
5319 if (ra != 0)
5320 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5321 tcg_temp_free(t0);
5322 }
5323
5324 /* stfqux */
5325 static void gen_stfqux(DisasContext *ctx)
5326 {
5327 int ra = rA(ctx->opcode);
5328 int rd = rD(ctx->opcode);
5329 TCGv t0, t1;
5330 gen_set_access_type(ctx, ACCESS_FLOAT);
5331 t0 = tcg_temp_new();
5332 gen_addr_reg_index(ctx, t0);
5333 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5334 t1 = tcg_temp_new();
5335 gen_addr_add(ctx, t1, t0, 8);
5336 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5337 tcg_temp_free(t1);
5338 if (ra != 0)
5339 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5340 tcg_temp_free(t0);
5341 }
5342
5343 /* stfqx */
5344 static void gen_stfqx(DisasContext *ctx)
5345 {
5346 int rd = rD(ctx->opcode);
5347 TCGv t0;
5348 gen_set_access_type(ctx, ACCESS_FLOAT);
5349 t0 = tcg_temp_new();
5350 gen_addr_reg_index(ctx, t0);
5351 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5352 gen_addr_add(ctx, t0, t0, 8);
5353 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5354 tcg_temp_free(t0);
5355 }
5356
5357 /* BookE specific instructions */
5358
5359 /* XXX: not implemented on 440 ? */
5360 static void gen_mfapidi(DisasContext *ctx)
5361 {
5362 /* XXX: TODO */
5363 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5364 }
5365
5366 /* XXX: not implemented on 440 ? */
5367 static void gen_tlbiva(DisasContext *ctx)
5368 {
5369 #if defined(CONFIG_USER_ONLY)
5370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5371 #else
5372 TCGv t0;
5373 if (unlikely(!ctx->mem_idx)) {
5374 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5375 return;
5376 }
5377 t0 = tcg_temp_new();
5378 gen_addr_reg_index(ctx, t0);
5379 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5380 tcg_temp_free(t0);
5381 #endif
5382 }
5383
5384 /* All 405 MAC instructions are translated here */
5385 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5386 int ra, int rb, int rt, int Rc)
5387 {
5388 TCGv t0, t1;
5389
5390 t0 = tcg_temp_local_new();
5391 t1 = tcg_temp_local_new();
5392
5393 switch (opc3 & 0x0D) {
5394 case 0x05:
5395 /* macchw - macchw. - macchwo - macchwo. */
5396 /* macchws - macchws. - macchwso - macchwso. */
5397 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5398 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5399 /* mulchw - mulchw. */
5400 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5401 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5402 tcg_gen_ext16s_tl(t1, t1);
5403 break;
5404 case 0x04:
5405 /* macchwu - macchwu. - macchwuo - macchwuo. */
5406 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5407 /* mulchwu - mulchwu. */
5408 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5409 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5410 tcg_gen_ext16u_tl(t1, t1);
5411 break;
5412 case 0x01:
5413 /* machhw - machhw. - machhwo - machhwo. */
5414 /* machhws - machhws. - machhwso - machhwso. */
5415 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5416 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5417 /* mulhhw - mulhhw. */
5418 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5419 tcg_gen_ext16s_tl(t0, t0);
5420 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5421 tcg_gen_ext16s_tl(t1, t1);
5422 break;
5423 case 0x00:
5424 /* machhwu - machhwu. - machhwuo - machhwuo. */
5425 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5426 /* mulhhwu - mulhhwu. */
5427 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5428 tcg_gen_ext16u_tl(t0, t0);
5429 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5430 tcg_gen_ext16u_tl(t1, t1);
5431 break;
5432 case 0x0D:
5433 /* maclhw - maclhw. - maclhwo - maclhwo. */
5434 /* maclhws - maclhws. - maclhwso - maclhwso. */
5435 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5436 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5437 /* mullhw - mullhw. */
5438 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5439 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5440 break;
5441 case 0x0C:
5442 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5443 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5444 /* mullhwu - mullhwu. */
5445 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5446 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5447 break;
5448 }
5449 if (opc2 & 0x04) {
5450 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5451 tcg_gen_mul_tl(t1, t0, t1);
5452 if (opc2 & 0x02) {
5453 /* nmultiply-and-accumulate (0x0E) */
5454 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5455 } else {
5456 /* multiply-and-accumulate (0x0C) */
5457 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5458 }
5459
5460 if (opc3 & 0x12) {
5461 /* Check overflow and/or saturate */
5462 int l1 = gen_new_label();
5463
5464 if (opc3 & 0x10) {
5465 /* Start with XER OV disabled, the most likely case */
5466 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5467 }
5468 if (opc3 & 0x01) {
5469 /* Signed */
5470 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5471 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5472 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5473 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5474 if (opc3 & 0x02) {
5475 /* Saturate */
5476 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5477 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5478 }
5479 } else {
5480 /* Unsigned */
5481 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5482 if (opc3 & 0x02) {
5483 /* Saturate */
5484 tcg_gen_movi_tl(t0, UINT32_MAX);
5485 }
5486 }
5487 if (opc3 & 0x10) {
5488 /* Check overflow */
5489 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5490 }
5491 gen_set_label(l1);
5492 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5493 }
5494 } else {
5495 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5496 }
5497 tcg_temp_free(t0);
5498 tcg_temp_free(t1);
5499 if (unlikely(Rc) != 0) {
5500 /* Update Rc0 */
5501 gen_set_Rc0(ctx, cpu_gpr[rt]);
5502 }
5503 }
5504
5505 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5506 static void glue(gen_, name)(DisasContext *ctx) \
5507 { \
5508 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5509 rD(ctx->opcode), Rc(ctx->opcode)); \
5510 }
5511
5512 /* macchw - macchw. */
5513 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5514 /* macchwo - macchwo. */
5515 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5516 /* macchws - macchws. */
5517 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5518 /* macchwso - macchwso. */
5519 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5520 /* macchwsu - macchwsu. */
5521 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5522 /* macchwsuo - macchwsuo. */
5523 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5524 /* macchwu - macchwu. */
5525 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5526 /* macchwuo - macchwuo. */
5527 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5528 /* machhw - machhw. */
5529 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5530 /* machhwo - machhwo. */
5531 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5532 /* machhws - machhws. */
5533 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5534 /* machhwso - machhwso. */
5535 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5536 /* machhwsu - machhwsu. */
5537 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5538 /* machhwsuo - machhwsuo. */
5539 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5540 /* machhwu - machhwu. */
5541 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5542 /* machhwuo - machhwuo. */
5543 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5544 /* maclhw - maclhw. */
5545 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5546 /* maclhwo - maclhwo. */
5547 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5548 /* maclhws - maclhws. */
5549 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5550 /* maclhwso - maclhwso. */
5551 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5552 /* maclhwu - maclhwu. */
5553 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5554 /* maclhwuo - maclhwuo. */
5555 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5556 /* maclhwsu - maclhwsu. */
5557 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5558 /* maclhwsuo - maclhwsuo. */
5559 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5560 /* nmacchw - nmacchw. */
5561 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5562 /* nmacchwo - nmacchwo. */
5563 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5564 /* nmacchws - nmacchws. */
5565 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5566 /* nmacchwso - nmacchwso. */
5567 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5568 /* nmachhw - nmachhw. */
5569 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5570 /* nmachhwo - nmachhwo. */
5571 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5572 /* nmachhws - nmachhws. */
5573 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5574 /* nmachhwso - nmachhwso. */
5575 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5576 /* nmaclhw - nmaclhw. */
5577 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5578 /* nmaclhwo - nmaclhwo. */
5579 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5580 /* nmaclhws - nmaclhws. */
5581 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5582 /* nmaclhwso - nmaclhwso. */
5583 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5584
5585 /* mulchw - mulchw. */
5586 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5587 /* mulchwu - mulchwu. */
5588 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5589 /* mulhhw - mulhhw. */
5590 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5591 /* mulhhwu - mulhhwu. */
5592 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5593 /* mullhw - mullhw. */
5594 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5595 /* mullhwu - mullhwu. */
5596 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5597
5598 /* mfdcr */
5599 static void gen_mfdcr(DisasContext *ctx)
5600 {
5601 #if defined(CONFIG_USER_ONLY)
5602 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5603 #else
5604 TCGv dcrn;
5605 if (unlikely(!ctx->mem_idx)) {
5606 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5607 return;
5608 }
5609 /* NIP cannot be restored if the memory exception comes from an helper */
5610 gen_update_nip(ctx, ctx->nip - 4);
5611 dcrn = tcg_const_tl(SPR(ctx->opcode));
5612 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5613 tcg_temp_free(dcrn);
5614 #endif
5615 }
5616
5617 /* mtdcr */
5618 static void gen_mtdcr(DisasContext *ctx)
5619 {
5620 #if defined(CONFIG_USER_ONLY)
5621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5622 #else
5623 TCGv dcrn;
5624 if (unlikely(!ctx->mem_idx)) {
5625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5626 return;
5627 }
5628 /* NIP cannot be restored if the memory exception comes from an helper */
5629 gen_update_nip(ctx, ctx->nip - 4);
5630 dcrn = tcg_const_tl(SPR(ctx->opcode));
5631 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5632 tcg_temp_free(dcrn);
5633 #endif
5634 }
5635
5636 /* mfdcrx */
5637 /* XXX: not implemented on 440 ? */
5638 static void gen_mfdcrx(DisasContext *ctx)
5639 {
5640 #if defined(CONFIG_USER_ONLY)
5641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5642 #else
5643 if (unlikely(!ctx->mem_idx)) {
5644 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5645 return;
5646 }
5647 /* NIP cannot be restored if the memory exception comes from an helper */
5648 gen_update_nip(ctx, ctx->nip - 4);
5649 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5650 /* Note: Rc update flag set leads to undefined state of Rc0 */
5651 #endif
5652 }
5653
5654 /* mtdcrx */
5655 /* XXX: not implemented on 440 ? */
5656 static void gen_mtdcrx(DisasContext *ctx)
5657 {
5658 #if defined(CONFIG_USER_ONLY)
5659 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5660 #else
5661 if (unlikely(!ctx->mem_idx)) {
5662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5663 return;
5664 }
5665 /* NIP cannot be restored if the memory exception comes from an helper */
5666 gen_update_nip(ctx, ctx->nip - 4);
5667 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5668 /* Note: Rc update flag set leads to undefined state of Rc0 */
5669 #endif
5670 }
5671
5672 /* mfdcrux (PPC 460) : user-mode access to DCR */
5673 static void gen_mfdcrux(DisasContext *ctx)
5674 {
5675 /* NIP cannot be restored if the memory exception comes from an helper */
5676 gen_update_nip(ctx, ctx->nip - 4);
5677 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5678 /* Note: Rc update flag set leads to undefined state of Rc0 */
5679 }
5680
5681 /* mtdcrux (PPC 460) : user-mode access to DCR */
5682 static void gen_mtdcrux(DisasContext *ctx)
5683 {
5684 /* NIP cannot be restored if the memory exception comes from an helper */
5685 gen_update_nip(ctx, ctx->nip - 4);
5686 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5687 /* Note: Rc update flag set leads to undefined state of Rc0 */
5688 }
5689
5690 /* dccci */
5691 static void gen_dccci(DisasContext *ctx)
5692 {
5693 #if defined(CONFIG_USER_ONLY)
5694 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5695 #else
5696 if (unlikely(!ctx->mem_idx)) {
5697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5698 return;
5699 }
5700 /* interpreted as no-op */
5701 #endif
5702 }
5703
5704 /* dcread */
5705 static void gen_dcread(DisasContext *ctx)
5706 {
5707 #if defined(CONFIG_USER_ONLY)
5708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5709 #else
5710 TCGv EA, val;
5711 if (unlikely(!ctx->mem_idx)) {
5712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5713 return;
5714 }
5715 gen_set_access_type(ctx, ACCESS_CACHE);
5716 EA = tcg_temp_new();
5717 gen_addr_reg_index(ctx, EA);
5718 val = tcg_temp_new();
5719 gen_qemu_ld32u(ctx, val, EA);
5720 tcg_temp_free(val);
5721 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5722 tcg_temp_free(EA);
5723 #endif
5724 }
5725
5726 /* icbt */
5727 static void gen_icbt_40x(DisasContext *ctx)
5728 {
5729 /* interpreted as no-op */
5730 /* XXX: specification say this is treated as a load by the MMU
5731 * but does not generate any exception
5732 */
5733 }
5734
5735 /* iccci */
5736 static void gen_iccci(DisasContext *ctx)
5737 {
5738 #if defined(CONFIG_USER_ONLY)
5739 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5740 #else
5741 if (unlikely(!ctx->mem_idx)) {
5742 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5743 return;
5744 }
5745 /* interpreted as no-op */
5746 #endif
5747 }
5748
5749 /* icread */
5750 static void gen_icread(DisasContext *ctx)
5751 {
5752 #if defined(CONFIG_USER_ONLY)
5753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5754 #else
5755 if (unlikely(!ctx->mem_idx)) {
5756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5757 return;
5758 }
5759 /* interpreted as no-op */
5760 #endif
5761 }
5762
5763 /* rfci (mem_idx only) */
5764 static void gen_rfci_40x(DisasContext *ctx)
5765 {
5766 #if defined(CONFIG_USER_ONLY)
5767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5768 #else
5769 if (unlikely(!ctx->mem_idx)) {
5770 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5771 return;
5772 }
5773 /* Restore CPU state */
5774 gen_helper_40x_rfci();
5775 gen_sync_exception(ctx);
5776 #endif
5777 }
5778
5779 static void gen_rfci(DisasContext *ctx)
5780 {
5781 #if defined(CONFIG_USER_ONLY)
5782 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5783 #else
5784 if (unlikely(!ctx->mem_idx)) {
5785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5786 return;
5787 }
5788 /* Restore CPU state */
5789 gen_helper_rfci();
5790 gen_sync_exception(ctx);
5791 #endif
5792 }
5793
5794 /* BookE specific */
5795
5796 /* XXX: not implemented on 440 ? */
5797 static void gen_rfdi(DisasContext *ctx)
5798 {
5799 #if defined(CONFIG_USER_ONLY)
5800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5801 #else
5802 if (unlikely(!ctx->mem_idx)) {
5803 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5804 return;
5805 }
5806 /* Restore CPU state */
5807 gen_helper_rfdi();
5808 gen_sync_exception(ctx);
5809 #endif
5810 }
5811
5812 /* XXX: not implemented on 440 ? */
5813 static void gen_rfmci(DisasContext *ctx)
5814 {
5815 #if defined(CONFIG_USER_ONLY)
5816 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5817 #else
5818 if (unlikely(!ctx->mem_idx)) {
5819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5820 return;
5821 }
5822 /* Restore CPU state */
5823 gen_helper_rfmci();
5824 gen_sync_exception(ctx);
5825 #endif
5826 }
5827
5828 /* TLB management - PowerPC 405 implementation */
5829
5830 /* tlbre */
5831 static void gen_tlbre_40x(DisasContext *ctx)
5832 {
5833 #if defined(CONFIG_USER_ONLY)
5834 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5835 #else
5836 if (unlikely(!ctx->mem_idx)) {
5837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5838 return;
5839 }
5840 switch (rB(ctx->opcode)) {
5841 case 0:
5842 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5843 break;
5844 case 1:
5845 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5846 break;
5847 default:
5848 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5849 break;
5850 }
5851 #endif
5852 }
5853
5854 /* tlbsx - tlbsx. */
5855 static void gen_tlbsx_40x(DisasContext *ctx)
5856 {
5857 #if defined(CONFIG_USER_ONLY)
5858 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5859 #else
5860 TCGv t0;
5861 if (unlikely(!ctx->mem_idx)) {
5862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5863 return;
5864 }
5865 t0 = tcg_temp_new();
5866 gen_addr_reg_index(ctx, t0);
5867 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5868 tcg_temp_free(t0);
5869 if (Rc(ctx->opcode)) {
5870 int l1 = gen_new_label();
5871 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5872 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5873 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5874 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5875 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5876 gen_set_label(l1);
5877 }
5878 #endif
5879 }
5880
5881 /* tlbwe */
5882 static void gen_tlbwe_40x(DisasContext *ctx)
5883 {
5884 #if defined(CONFIG_USER_ONLY)
5885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5886 #else
5887 if (unlikely(!ctx->mem_idx)) {
5888 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5889 return;
5890 }
5891 switch (rB(ctx->opcode)) {
5892 case 0:
5893 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5894 break;
5895 case 1:
5896 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5897 break;
5898 default:
5899 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5900 break;
5901 }
5902 #endif
5903 }
5904
5905 /* TLB management - PowerPC 440 implementation */
5906
5907 /* tlbre */
5908 static void gen_tlbre_440(DisasContext *ctx)
5909 {
5910 #if defined(CONFIG_USER_ONLY)
5911 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5912 #else
5913 if (unlikely(!ctx->mem_idx)) {
5914 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5915 return;
5916 }
5917 switch (rB(ctx->opcode)) {
5918 case 0:
5919 case 1:
5920 case 2:
5921 {
5922 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5923 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], t0, cpu_gpr[rA(ctx->opcode)]);
5924 tcg_temp_free_i32(t0);
5925 }
5926 break;
5927 default:
5928 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5929 break;
5930 }
5931 #endif
5932 }
5933
5934 /* tlbsx - tlbsx. */
5935 static void gen_tlbsx_440(DisasContext *ctx)
5936 {
5937 #if defined(CONFIG_USER_ONLY)
5938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5939 #else
5940 TCGv t0;
5941 if (unlikely(!ctx->mem_idx)) {
5942 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5943 return;
5944 }
5945 t0 = tcg_temp_new();
5946 gen_addr_reg_index(ctx, t0);
5947 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5948 tcg_temp_free(t0);
5949 if (Rc(ctx->opcode)) {
5950 int l1 = gen_new_label();
5951 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5952 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5953 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5954 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5955 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5956 gen_set_label(l1);
5957 }
5958 #endif
5959 }
5960
5961 /* tlbwe */
5962 static void gen_tlbwe_440(DisasContext *ctx)
5963 {
5964 #if defined(CONFIG_USER_ONLY)
5965 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5966 #else
5967 if (unlikely(!ctx->mem_idx)) {
5968 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5969 return;
5970 }
5971 switch (rB(ctx->opcode)) {
5972 case 0:
5973 case 1:
5974 case 2:
5975 {
5976 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5977 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5978 tcg_temp_free_i32(t0);
5979 }
5980 break;
5981 default:
5982 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5983 break;
5984 }
5985 #endif
5986 }
5987
5988 /* TLB management - PowerPC BookE 2.06 implementation */
5989
5990 /* tlbre */
5991 static void gen_tlbre_booke206(DisasContext *ctx)
5992 {
5993 #if defined(CONFIG_USER_ONLY)
5994 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5995 #else
5996 if (unlikely(!ctx->mem_idx)) {
5997 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5998 return;
5999 }
6000
6001 gen_helper_booke206_tlbre();
6002 #endif
6003 }
6004
6005 /* tlbsx - tlbsx. */
6006 static void gen_tlbsx_booke206(DisasContext *ctx)
6007 {
6008 #if defined(CONFIG_USER_ONLY)
6009 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6010 #else
6011 TCGv t0;
6012 if (unlikely(!ctx->mem_idx)) {
6013 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6014 return;
6015 }
6016
6017 if (rA(ctx->opcode)) {
6018 t0 = tcg_temp_new();
6019 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6020 } else {
6021 t0 = tcg_const_tl(0);
6022 }
6023
6024 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6025 gen_helper_booke206_tlbsx(t0);
6026 #endif
6027 }
6028
6029 /* tlbwe */
6030 static void gen_tlbwe_booke206(DisasContext *ctx)
6031 {
6032 #if defined(CONFIG_USER_ONLY)
6033 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6034 #else
6035 if (unlikely(!ctx->mem_idx)) {
6036 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6037 return;
6038 }
6039 gen_helper_booke206_tlbwe();
6040 #endif
6041 }
6042
6043 static void gen_tlbivax_booke206(DisasContext *ctx)
6044 {
6045 #if defined(CONFIG_USER_ONLY)
6046 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6047 #else
6048 TCGv t0;
6049 if (unlikely(!ctx->mem_idx)) {
6050 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6051 return;
6052 }
6053
6054 t0 = tcg_temp_new();
6055 gen_addr_reg_index(ctx, t0);
6056
6057 gen_helper_booke206_tlbivax(t0);
6058 #endif
6059 }
6060
6061
6062 /* wrtee */
6063 static void gen_wrtee(DisasContext *ctx)
6064 {
6065 #if defined(CONFIG_USER_ONLY)
6066 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6067 #else
6068 TCGv t0;
6069 if (unlikely(!ctx->mem_idx)) {
6070 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6071 return;
6072 }
6073 t0 = tcg_temp_new();
6074 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6075 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6076 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6077 tcg_temp_free(t0);
6078 /* Stop translation to have a chance to raise an exception
6079 * if we just set msr_ee to 1
6080 */
6081 gen_stop_exception(ctx);
6082 #endif
6083 }
6084
6085 /* wrteei */
6086 static void gen_wrteei(DisasContext *ctx)
6087 {
6088 #if defined(CONFIG_USER_ONLY)
6089 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6090 #else
6091 if (unlikely(!ctx->mem_idx)) {
6092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6093 return;
6094 }
6095 if (ctx->opcode & 0x00008000) {
6096 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6097 /* Stop translation to have a chance to raise an exception */
6098 gen_stop_exception(ctx);
6099 } else {
6100 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6101 }
6102 #endif
6103 }
6104
6105 /* PowerPC 440 specific instructions */
6106
6107 /* dlmzb */
6108 static void gen_dlmzb(DisasContext *ctx)
6109 {
6110 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6111 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6112 cpu_gpr[rB(ctx->opcode)], t0);
6113 tcg_temp_free_i32(t0);
6114 }
6115
6116 /* mbar replaces eieio on 440 */
6117 static void gen_mbar(DisasContext *ctx)
6118 {
6119 /* interpreted as no-op */
6120 }
6121
6122 /* msync replaces sync on 440 */
6123 static void gen_msync(DisasContext *ctx)
6124 {
6125 /* interpreted as no-op */
6126 }
6127
6128 /* icbt */
6129 static void gen_icbt_440(DisasContext *ctx)
6130 {
6131 /* interpreted as no-op */
6132 /* XXX: specification say this is treated as a load by the MMU
6133 * but does not generate any exception
6134 */
6135 }
6136
6137 /*** Altivec vector extension ***/
6138 /* Altivec registers moves */
6139
6140 static inline TCGv_ptr gen_avr_ptr(int reg)
6141 {
6142 TCGv_ptr r = tcg_temp_new_ptr();
6143 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6144 return r;
6145 }
6146
6147 #define GEN_VR_LDX(name, opc2, opc3) \
6148 static void glue(gen_, name)(DisasContext *ctx) \
6149 { \
6150 TCGv EA; \
6151 if (unlikely(!ctx->altivec_enabled)) { \
6152 gen_exception(ctx, POWERPC_EXCP_VPU); \
6153 return; \
6154 } \
6155 gen_set_access_type(ctx, ACCESS_INT); \
6156 EA = tcg_temp_new(); \
6157 gen_addr_reg_index(ctx, EA); \
6158 tcg_gen_andi_tl(EA, EA, ~0xf); \
6159 if (ctx->le_mode) { \
6160 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6161 tcg_gen_addi_tl(EA, EA, 8); \
6162 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6163 } else { \
6164 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6165 tcg_gen_addi_tl(EA, EA, 8); \
6166 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6167 } \
6168 tcg_temp_free(EA); \
6169 }
6170
6171 #define GEN_VR_STX(name, opc2, opc3) \
6172 static void gen_st##name(DisasContext *ctx) \
6173 { \
6174 TCGv EA; \
6175 if (unlikely(!ctx->altivec_enabled)) { \
6176 gen_exception(ctx, POWERPC_EXCP_VPU); \
6177 return; \
6178 } \
6179 gen_set_access_type(ctx, ACCESS_INT); \
6180 EA = tcg_temp_new(); \
6181 gen_addr_reg_index(ctx, EA); \
6182 tcg_gen_andi_tl(EA, EA, ~0xf); \
6183 if (ctx->le_mode) { \
6184 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6185 tcg_gen_addi_tl(EA, EA, 8); \
6186 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6187 } else { \
6188 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6189 tcg_gen_addi_tl(EA, EA, 8); \
6190 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6191 } \
6192 tcg_temp_free(EA); \
6193 }
6194
6195 #define GEN_VR_LVE(name, opc2, opc3) \
6196 static void gen_lve##name(DisasContext *ctx) \
6197 { \
6198 TCGv EA; \
6199 TCGv_ptr rs; \
6200 if (unlikely(!ctx->altivec_enabled)) { \
6201 gen_exception(ctx, POWERPC_EXCP_VPU); \
6202 return; \
6203 } \
6204 gen_set_access_type(ctx, ACCESS_INT); \
6205 EA = tcg_temp_new(); \
6206 gen_addr_reg_index(ctx, EA); \
6207 rs = gen_avr_ptr(rS(ctx->opcode)); \
6208 gen_helper_lve##name (rs, EA); \
6209 tcg_temp_free(EA); \
6210 tcg_temp_free_ptr(rs); \
6211 }
6212
6213 #define GEN_VR_STVE(name, opc2, opc3) \
6214 static void gen_stve##name(DisasContext *ctx) \
6215 { \
6216 TCGv EA; \
6217 TCGv_ptr rs; \
6218 if (unlikely(!ctx->altivec_enabled)) { \
6219 gen_exception(ctx, POWERPC_EXCP_VPU); \
6220 return; \
6221 } \
6222 gen_set_access_type(ctx, ACCESS_INT); \
6223 EA = tcg_temp_new(); \
6224 gen_addr_reg_index(ctx, EA); \
6225 rs = gen_avr_ptr(rS(ctx->opcode)); \
6226 gen_helper_stve##name (rs, EA); \
6227 tcg_temp_free(EA); \
6228 tcg_temp_free_ptr(rs); \
6229 }
6230
6231 GEN_VR_LDX(lvx, 0x07, 0x03);
6232 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6233 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6234
6235 GEN_VR_LVE(bx, 0x07, 0x00);
6236 GEN_VR_LVE(hx, 0x07, 0x01);
6237 GEN_VR_LVE(wx, 0x07, 0x02);
6238
6239 GEN_VR_STX(svx, 0x07, 0x07);
6240 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6241 GEN_VR_STX(svxl, 0x07, 0x0F);
6242
6243 GEN_VR_STVE(bx, 0x07, 0x04);
6244 GEN_VR_STVE(hx, 0x07, 0x05);
6245 GEN_VR_STVE(wx, 0x07, 0x06);
6246
6247 static void gen_lvsl(DisasContext *ctx)
6248 {
6249 TCGv_ptr rd;
6250 TCGv EA;
6251 if (unlikely(!ctx->altivec_enabled)) {
6252 gen_exception(ctx, POWERPC_EXCP_VPU);
6253 return;
6254 }
6255 EA = tcg_temp_new();
6256 gen_addr_reg_index(ctx, EA);
6257 rd = gen_avr_ptr(rD(ctx->opcode));
6258 gen_helper_lvsl(rd, EA);
6259 tcg_temp_free(EA);
6260 tcg_temp_free_ptr(rd);
6261 }
6262
6263 static void gen_lvsr(DisasContext *ctx)
6264 {
6265 TCGv_ptr rd;
6266 TCGv EA;
6267 if (unlikely(!ctx->altivec_enabled)) {
6268 gen_exception(ctx, POWERPC_EXCP_VPU);
6269 return;
6270 }
6271 EA = tcg_temp_new();
6272 gen_addr_reg_index(ctx, EA);
6273 rd = gen_avr_ptr(rD(ctx->opcode));
6274 gen_helper_lvsr(rd, EA);
6275 tcg_temp_free(EA);
6276 tcg_temp_free_ptr(rd);
6277 }
6278
6279 static void gen_mfvscr(DisasContext *ctx)
6280 {
6281 TCGv_i32 t;
6282 if (unlikely(!ctx->altivec_enabled)) {
6283 gen_exception(ctx, POWERPC_EXCP_VPU);
6284 return;
6285 }
6286 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6287 t = tcg_temp_new_i32();
6288 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6289 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6290 tcg_temp_free_i32(t);
6291 }
6292
6293 static void gen_mtvscr(DisasContext *ctx)
6294 {
6295 TCGv_ptr p;
6296 if (unlikely(!ctx->altivec_enabled)) {
6297 gen_exception(ctx, POWERPC_EXCP_VPU);
6298 return;
6299 }
6300 p = gen_avr_ptr(rD(ctx->opcode));
6301 gen_helper_mtvscr(p);
6302 tcg_temp_free_ptr(p);
6303 }
6304
6305 /* Logical operations */
6306 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6307 static void glue(gen_, name)(DisasContext *ctx) \
6308 { \
6309 if (unlikely(!ctx->altivec_enabled)) { \
6310 gen_exception(ctx, POWERPC_EXCP_VPU); \
6311 return; \
6312 } \
6313 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6314 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6315 }
6316
6317 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6318 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6319 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6320 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6321 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6322
6323 #define GEN_VXFORM(name, opc2, opc3) \
6324 static void glue(gen_, name)(DisasContext *ctx) \
6325 { \
6326 TCGv_ptr ra, rb, rd; \
6327 if (unlikely(!ctx->altivec_enabled)) { \
6328 gen_exception(ctx, POWERPC_EXCP_VPU); \
6329 return; \
6330 } \
6331 ra = gen_avr_ptr(rA(ctx->opcode)); \
6332 rb = gen_avr_ptr(rB(ctx->opcode)); \
6333 rd = gen_avr_ptr(rD(ctx->opcode)); \
6334 gen_helper_##name (rd, ra, rb); \
6335 tcg_temp_free_ptr(ra); \
6336 tcg_temp_free_ptr(rb); \
6337 tcg_temp_free_ptr(rd); \
6338 }
6339
6340 GEN_VXFORM(vaddubm, 0, 0);
6341 GEN_VXFORM(vadduhm, 0, 1);
6342 GEN_VXFORM(vadduwm, 0, 2);
6343 GEN_VXFORM(vsububm, 0, 16);
6344 GEN_VXFORM(vsubuhm, 0, 17);
6345 GEN_VXFORM(vsubuwm, 0, 18);
6346 GEN_VXFORM(vmaxub, 1, 0);
6347 GEN_VXFORM(vmaxuh, 1, 1);
6348 GEN_VXFORM(vmaxuw, 1, 2);
6349 GEN_VXFORM(vmaxsb, 1, 4);
6350 GEN_VXFORM(vmaxsh, 1, 5);
6351 GEN_VXFORM(vmaxsw, 1, 6);
6352 GEN_VXFORM(vminub, 1, 8);
6353 GEN_VXFORM(vminuh, 1, 9);
6354 GEN_VXFORM(vminuw, 1, 10);
6355 GEN_VXFORM(vminsb, 1, 12);
6356 GEN_VXFORM(vminsh, 1, 13);
6357 GEN_VXFORM(vminsw, 1, 14);
6358 GEN_VXFORM(vavgub, 1, 16);
6359 GEN_VXFORM(vavguh, 1, 17);
6360 GEN_VXFORM(vavguw, 1, 18);
6361 GEN_VXFORM(vavgsb, 1, 20);
6362 GEN_VXFORM(vavgsh, 1, 21);
6363 GEN_VXFORM(vavgsw, 1, 22);
6364 GEN_VXFORM(vmrghb, 6, 0);
6365 GEN_VXFORM(vmrghh, 6, 1);
6366 GEN_VXFORM(vmrghw, 6, 2);
6367 GEN_VXFORM(vmrglb, 6, 4);
6368 GEN_VXFORM(vmrglh, 6, 5);
6369 GEN_VXFORM(vmrglw, 6, 6);
6370 GEN_VXFORM(vmuloub, 4, 0);
6371 GEN_VXFORM(vmulouh, 4, 1);
6372 GEN_VXFORM(vmulosb, 4, 4);
6373 GEN_VXFORM(vmulosh, 4, 5);
6374 GEN_VXFORM(vmuleub, 4, 8);
6375 GEN_VXFORM(vmuleuh, 4, 9);
6376 GEN_VXFORM(vmulesb, 4, 12);
6377 GEN_VXFORM(vmulesh, 4, 13);
6378 GEN_VXFORM(vslb, 2, 4);
6379 GEN_VXFORM(vslh, 2, 5);
6380 GEN_VXFORM(vslw, 2, 6);
6381 GEN_VXFORM(vsrb, 2, 8);
6382 GEN_VXFORM(vsrh, 2, 9);
6383 GEN_VXFORM(vsrw, 2, 10);
6384 GEN_VXFORM(vsrab, 2, 12);
6385 GEN_VXFORM(vsrah, 2, 13);
6386 GEN_VXFORM(vsraw, 2, 14);
6387 GEN_VXFORM(vslo, 6, 16);
6388 GEN_VXFORM(vsro, 6, 17);
6389 GEN_VXFORM(vaddcuw, 0, 6);
6390 GEN_VXFORM(vsubcuw, 0, 22);
6391 GEN_VXFORM(vaddubs, 0, 8);
6392 GEN_VXFORM(vadduhs, 0, 9);
6393 GEN_VXFORM(vadduws, 0, 10);
6394 GEN_VXFORM(vaddsbs, 0, 12);
6395 GEN_VXFORM(vaddshs, 0, 13);
6396 GEN_VXFORM(vaddsws, 0, 14);
6397 GEN_VXFORM(vsububs, 0, 24);
6398 GEN_VXFORM(vsubuhs, 0, 25);
6399 GEN_VXFORM(vsubuws, 0, 26);
6400 GEN_VXFORM(vsubsbs, 0, 28);
6401 GEN_VXFORM(vsubshs, 0, 29);
6402 GEN_VXFORM(vsubsws, 0, 30);
6403 GEN_VXFORM(vrlb, 2, 0);
6404 GEN_VXFORM(vrlh, 2, 1);
6405 GEN_VXFORM(vrlw, 2, 2);
6406 GEN_VXFORM(vsl, 2, 7);
6407 GEN_VXFORM(vsr, 2, 11);
6408 GEN_VXFORM(vpkuhum, 7, 0);
6409 GEN_VXFORM(vpkuwum, 7, 1);
6410 GEN_VXFORM(vpkuhus, 7, 2);
6411 GEN_VXFORM(vpkuwus, 7, 3);
6412 GEN_VXFORM(vpkshus, 7, 4);
6413 GEN_VXFORM(vpkswus, 7, 5);
6414 GEN_VXFORM(vpkshss, 7, 6);
6415 GEN_VXFORM(vpkswss, 7, 7);
6416 GEN_VXFORM(vpkpx, 7, 12);
6417 GEN_VXFORM(vsum4ubs, 4, 24);
6418 GEN_VXFORM(vsum4sbs, 4, 28);
6419 GEN_VXFORM(vsum4shs, 4, 25);
6420 GEN_VXFORM(vsum2sws, 4, 26);
6421 GEN_VXFORM(vsumsws, 4, 30);
6422 GEN_VXFORM(vaddfp, 5, 0);
6423 GEN_VXFORM(vsubfp, 5, 1);
6424 GEN_VXFORM(vmaxfp, 5, 16);
6425 GEN_VXFORM(vminfp, 5, 17);
6426
6427 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6428 static void glue(gen_, name)(DisasContext *ctx) \
6429 { \
6430 TCGv_ptr ra, rb, rd; \
6431 if (unlikely(!ctx->altivec_enabled)) { \
6432 gen_exception(ctx, POWERPC_EXCP_VPU); \
6433 return; \
6434 } \
6435 ra = gen_avr_ptr(rA(ctx->opcode)); \
6436 rb = gen_avr_ptr(rB(ctx->opcode)); \
6437 rd = gen_avr_ptr(rD(ctx->opcode)); \
6438 gen_helper_##opname (rd, ra, rb); \
6439 tcg_temp_free_ptr(ra); \
6440 tcg_temp_free_ptr(rb); \
6441 tcg_temp_free_ptr(rd); \
6442 }
6443
6444 #define GEN_VXRFORM(name, opc2, opc3) \
6445 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6446 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6447
6448 GEN_VXRFORM(vcmpequb, 3, 0)
6449 GEN_VXRFORM(vcmpequh, 3, 1)
6450 GEN_VXRFORM(vcmpequw, 3, 2)
6451 GEN_VXRFORM(vcmpgtsb, 3, 12)
6452 GEN_VXRFORM(vcmpgtsh, 3, 13)
6453 GEN_VXRFORM(vcmpgtsw, 3, 14)
6454 GEN_VXRFORM(vcmpgtub, 3, 8)
6455 GEN_VXRFORM(vcmpgtuh, 3, 9)
6456 GEN_VXRFORM(vcmpgtuw, 3, 10)
6457 GEN_VXRFORM(vcmpeqfp, 3, 3)
6458 GEN_VXRFORM(vcmpgefp, 3, 7)
6459 GEN_VXRFORM(vcmpgtfp, 3, 11)
6460 GEN_VXRFORM(vcmpbfp, 3, 15)
6461
6462 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6463 static void glue(gen_, name)(DisasContext *ctx) \
6464 { \
6465 TCGv_ptr rd; \
6466 TCGv_i32 simm; \
6467 if (unlikely(!ctx->altivec_enabled)) { \
6468 gen_exception(ctx, POWERPC_EXCP_VPU); \
6469 return; \
6470 } \
6471 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6472 rd = gen_avr_ptr(rD(ctx->opcode)); \
6473 gen_helper_##name (rd, simm); \
6474 tcg_temp_free_i32(simm); \
6475 tcg_temp_free_ptr(rd); \
6476 }
6477
6478 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6479 GEN_VXFORM_SIMM(vspltish, 6, 13);
6480 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6481
6482 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6483 static void glue(gen_, name)(DisasContext *ctx) \
6484 { \
6485 TCGv_ptr rb, rd; \
6486 if (unlikely(!ctx->altivec_enabled)) { \
6487 gen_exception(ctx, POWERPC_EXCP_VPU); \
6488 return; \
6489 } \
6490 rb = gen_avr_ptr(rB(ctx->opcode)); \
6491 rd = gen_avr_ptr(rD(ctx->opcode)); \
6492 gen_helper_##name (rd, rb); \
6493 tcg_temp_free_ptr(rb); \
6494 tcg_temp_free_ptr(rd); \
6495 }
6496
6497 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6498 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6499 GEN_VXFORM_NOA(vupklsb, 7, 10);
6500 GEN_VXFORM_NOA(vupklsh, 7, 11);
6501 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6502 GEN_VXFORM_NOA(vupklpx, 7, 15);
6503 GEN_VXFORM_NOA(vrefp, 5, 4);
6504 GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
6505 GEN_VXFORM_NOA(vexptefp, 5, 6);
6506 GEN_VXFORM_NOA(vlogefp, 5, 7);
6507 GEN_VXFORM_NOA(vrfim, 5, 8);
6508 GEN_VXFORM_NOA(vrfin, 5, 9);
6509 GEN_VXFORM_NOA(vrfip, 5, 10);
6510 GEN_VXFORM_NOA(vrfiz, 5, 11);
6511
6512 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6513 static void glue(gen_, name)(DisasContext *ctx) \
6514 { \
6515 TCGv_ptr rd; \
6516 TCGv_i32 simm; \
6517 if (unlikely(!ctx->altivec_enabled)) { \
6518 gen_exception(ctx, POWERPC_EXCP_VPU); \
6519 return; \
6520 } \
6521 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6522 rd = gen_avr_ptr(rD(ctx->opcode)); \
6523 gen_helper_##name (rd, simm); \
6524 tcg_temp_free_i32(simm); \
6525 tcg_temp_free_ptr(rd); \
6526 }
6527
6528 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6529 static void glue(gen_, name)(DisasContext *ctx) \
6530 { \
6531 TCGv_ptr rb, rd; \
6532 TCGv_i32 uimm; \
6533 if (unlikely(!ctx->altivec_enabled)) { \
6534 gen_exception(ctx, POWERPC_EXCP_VPU); \
6535 return; \
6536 } \
6537 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6538 rb = gen_avr_ptr(rB(ctx->opcode)); \
6539 rd = gen_avr_ptr(rD(ctx->opcode)); \
6540 gen_helper_##name (rd, rb, uimm); \
6541 tcg_temp_free_i32(uimm); \
6542 tcg_temp_free_ptr(rb); \
6543 tcg_temp_free_ptr(rd); \
6544 }
6545
6546 GEN_VXFORM_UIMM(vspltb, 6, 8);
6547 GEN_VXFORM_UIMM(vsplth, 6, 9);
6548 GEN_VXFORM_UIMM(vspltw, 6, 10);
6549 GEN_VXFORM_UIMM(vcfux, 5, 12);
6550 GEN_VXFORM_UIMM(vcfsx, 5, 13);
6551 GEN_VXFORM_UIMM(vctuxs, 5, 14);
6552 GEN_VXFORM_UIMM(vctsxs, 5, 15);
6553
6554 static void gen_vsldoi(DisasContext *ctx)
6555 {
6556 TCGv_ptr ra, rb, rd;
6557 TCGv_i32 sh;
6558 if (unlikely(!ctx->altivec_enabled)) {
6559 gen_exception(ctx, POWERPC_EXCP_VPU);
6560 return;
6561 }
6562 ra = gen_avr_ptr(rA(ctx->opcode));
6563 rb = gen_avr_ptr(rB(ctx->opcode));
6564 rd = gen_avr_ptr(rD(ctx->opcode));
6565 sh = tcg_const_i32(VSH(ctx->opcode));
6566 gen_helper_vsldoi (rd, ra, rb, sh);
6567 tcg_temp_free_ptr(ra);
6568 tcg_temp_free_ptr(rb);
6569 tcg_temp_free_ptr(rd);
6570 tcg_temp_free_i32(sh);
6571 }
6572
6573 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6574 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6575 { \
6576 TCGv_ptr ra, rb, rc, rd; \
6577 if (unlikely(!ctx->altivec_enabled)) { \
6578 gen_exception(ctx, POWERPC_EXCP_VPU); \
6579 return; \
6580 } \
6581 ra = gen_avr_ptr(rA(ctx->opcode)); \
6582 rb = gen_avr_ptr(rB(ctx->opcode)); \
6583 rc = gen_avr_ptr(rC(ctx->opcode)); \
6584 rd = gen_avr_ptr(rD(ctx->opcode)); \
6585 if (Rc(ctx->opcode)) { \
6586 gen_helper_##name1 (rd, ra, rb, rc); \
6587 } else { \
6588 gen_helper_##name0 (rd, ra, rb, rc); \
6589 } \
6590 tcg_temp_free_ptr(ra); \
6591 tcg_temp_free_ptr(rb); \
6592 tcg_temp_free_ptr(rc); \
6593 tcg_temp_free_ptr(rd); \
6594 }
6595
6596 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6597
6598 static void gen_vmladduhm(DisasContext *ctx)
6599 {
6600 TCGv_ptr ra, rb, rc, rd;
6601 if (unlikely(!ctx->altivec_enabled)) {
6602 gen_exception(ctx, POWERPC_EXCP_VPU);
6603 return;
6604 }
6605 ra = gen_avr_ptr(rA(ctx->opcode));
6606 rb = gen_avr_ptr(rB(ctx->opcode));
6607 rc = gen_avr_ptr(rC(ctx->opcode));
6608 rd = gen_avr_ptr(rD(ctx->opcode));
6609 gen_helper_vmladduhm(rd, ra, rb, rc);
6610 tcg_temp_free_ptr(ra);
6611 tcg_temp_free_ptr(rb);
6612 tcg_temp_free_ptr(rc);
6613 tcg_temp_free_ptr(rd);
6614 }
6615
6616 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6617 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6618 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6619 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6620 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6621
6622 /*** SPE extension ***/
6623 /* Register moves */
6624
6625
6626 static inline void gen_evmra(DisasContext *ctx)
6627 {
6628
6629 if (unlikely(!ctx->spe_enabled)) {
6630 gen_exception(ctx, POWERPC_EXCP_APU);
6631 return;
6632 }
6633
6634 #if defined(TARGET_PPC64)
6635 /* rD := rA */
6636 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6637
6638 /* spe_acc := rA */
6639 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6640 cpu_env,
6641 offsetof(CPUState, spe_acc));
6642 #else
6643 TCGv_i64 tmp = tcg_temp_new_i64();
6644
6645 /* tmp := rA_lo + rA_hi << 32 */
6646 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6647
6648 /* spe_acc := tmp */
6649 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
6650 tcg_temp_free_i64(tmp);
6651
6652 /* rD := rA */
6653 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6654 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6655 #endif
6656 }
6657
6658 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6659 {
6660 #if defined(TARGET_PPC64)
6661 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6662 #else
6663 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6664 #endif
6665 }
6666
6667 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6668 {
6669 #if defined(TARGET_PPC64)
6670 tcg_gen_mov_i64(cpu_gpr[reg], t);
6671 #else
6672 TCGv_i64 tmp = tcg_temp_new_i64();
6673 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6674 tcg_gen_shri_i64(tmp, t, 32);
6675 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6676 tcg_temp_free_i64(tmp);
6677 #endif
6678 }
6679
6680 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6681 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6682 { \
6683 if (Rc(ctx->opcode)) \
6684 gen_##name1(ctx); \
6685 else \
6686 gen_##name0(ctx); \
6687 }
6688
6689 /* Handler for undefined SPE opcodes */
6690 static inline void gen_speundef(DisasContext *ctx)
6691 {
6692 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6693 }
6694
6695 /* SPE logic */
6696 #if defined(TARGET_PPC64)
6697 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6698 static inline void gen_##name(DisasContext *ctx) \
6699 { \
6700 if (unlikely(!ctx->spe_enabled)) { \
6701 gen_exception(ctx, POWERPC_EXCP_APU); \
6702 return; \
6703 } \
6704 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6705 cpu_gpr[rB(ctx->opcode)]); \
6706 }
6707 #else
6708 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6709 static inline void gen_##name(DisasContext *ctx) \
6710 { \
6711 if (unlikely(!ctx->spe_enabled)) { \
6712 gen_exception(ctx, POWERPC_EXCP_APU); \
6713 return; \
6714 } \
6715 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6716 cpu_gpr[rB(ctx->opcode)]); \
6717 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6718 cpu_gprh[rB(ctx->opcode)]); \
6719 }
6720 #endif
6721
6722 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6723 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6724 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6725 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6726 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6727 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6728 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6729 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6730
6731 /* SPE logic immediate */
6732 #if defined(TARGET_PPC64)
6733 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6734 static inline void gen_##name(DisasContext *ctx) \
6735 { \
6736 if (unlikely(!ctx->spe_enabled)) { \
6737 gen_exception(ctx, POWERPC_EXCP_APU); \
6738 return; \
6739 } \
6740 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6741 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6742 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6743 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6744 tcg_opi(t0, t0, rB(ctx->opcode)); \
6745 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6746 tcg_gen_trunc_i64_i32(t1, t2); \
6747 tcg_temp_free_i64(t2); \
6748 tcg_opi(t1, t1, rB(ctx->opcode)); \
6749 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6750 tcg_temp_free_i32(t0); \
6751 tcg_temp_free_i32(t1); \
6752 }
6753 #else
6754 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6755 static inline void gen_##name(DisasContext *ctx) \
6756 { \
6757 if (unlikely(!ctx->spe_enabled)) { \
6758 gen_exception(ctx, POWERPC_EXCP_APU); \
6759 return; \
6760 } \
6761 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6762 rB(ctx->opcode)); \
6763 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6764 rB(ctx->opcode)); \
6765 }
6766 #endif
6767 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6768 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6769 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6770 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6771
6772 /* SPE arithmetic */
6773 #if defined(TARGET_PPC64)
6774 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6775 static inline void gen_##name(DisasContext *ctx) \
6776 { \
6777 if (unlikely(!ctx->spe_enabled)) { \
6778 gen_exception(ctx, POWERPC_EXCP_APU); \
6779 return; \
6780 } \
6781 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6782 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6783 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6784 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6785 tcg_op(t0, t0); \
6786 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6787 tcg_gen_trunc_i64_i32(t1, t2); \
6788 tcg_temp_free_i64(t2); \
6789 tcg_op(t1, t1); \
6790 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6791 tcg_temp_free_i32(t0); \
6792 tcg_temp_free_i32(t1); \
6793 }
6794 #else
6795 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6796 static inline void gen_##name(DisasContext *ctx) \
6797 { \
6798 if (unlikely(!ctx->spe_enabled)) { \
6799 gen_exception(ctx, POWERPC_EXCP_APU); \
6800 return; \
6801 } \
6802 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6803 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6804 }
6805 #endif
6806
6807 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6808 {
6809 int l1 = gen_new_label();
6810 int l2 = gen_new_label();
6811
6812 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6813 tcg_gen_neg_i32(ret, arg1);
6814 tcg_gen_br(l2);
6815 gen_set_label(l1);
6816 tcg_gen_mov_i32(ret, arg1);
6817 gen_set_label(l2);
6818 }
6819 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6820 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6821 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6822 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6823 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6824 {
6825 tcg_gen_addi_i32(ret, arg1, 0x8000);
6826 tcg_gen_ext16u_i32(ret, ret);
6827 }
6828 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6829 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6830 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6831
6832 #if defined(TARGET_PPC64)
6833 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6834 static inline void gen_##name(DisasContext *ctx) \
6835 { \
6836 if (unlikely(!ctx->spe_enabled)) { \
6837 gen_exception(ctx, POWERPC_EXCP_APU); \
6838 return; \
6839 } \
6840 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6841 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6842 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6843 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6844 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6845 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6846 tcg_op(t0, t0, t2); \
6847 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6848 tcg_gen_trunc_i64_i32(t1, t3); \
6849 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6850 tcg_gen_trunc_i64_i32(t2, t3); \
6851 tcg_temp_free_i64(t3); \
6852 tcg_op(t1, t1, t2); \
6853 tcg_temp_free_i32(t2); \
6854 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6855 tcg_temp_free_i32(t0); \
6856 tcg_temp_free_i32(t1); \
6857 }
6858 #else
6859 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6860 static inline void gen_##name(DisasContext *ctx) \
6861 { \
6862 if (unlikely(!ctx->spe_enabled)) { \
6863 gen_exception(ctx, POWERPC_EXCP_APU); \
6864 return; \
6865 } \
6866 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6867 cpu_gpr[rB(ctx->opcode)]); \
6868 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6869 cpu_gprh[rB(ctx->opcode)]); \
6870 }
6871 #endif
6872
6873 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6874 {
6875 TCGv_i32 t0;
6876 int l1, l2;
6877
6878 l1 = gen_new_label();
6879 l2 = gen_new_label();
6880 t0 = tcg_temp_local_new_i32();
6881 /* No error here: 6 bits are used */
6882 tcg_gen_andi_i32(t0, arg2, 0x3F);
6883 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6884 tcg_gen_shr_i32(ret, arg1, t0);
6885 tcg_gen_br(l2);
6886 gen_set_label(l1);
6887 tcg_gen_movi_i32(ret, 0);
6888 gen_set_label(l2);
6889 tcg_temp_free_i32(t0);
6890 }
6891 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6892 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6893 {
6894 TCGv_i32 t0;
6895 int l1, l2;
6896
6897 l1 = gen_new_label();
6898 l2 = gen_new_label();
6899 t0 = tcg_temp_local_new_i32();
6900 /* No error here: 6 bits are used */
6901 tcg_gen_andi_i32(t0, arg2, 0x3F);
6902 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6903 tcg_gen_sar_i32(ret, arg1, t0);
6904 tcg_gen_br(l2);
6905 gen_set_label(l1);
6906 tcg_gen_movi_i32(ret, 0);
6907 gen_set_label(l2);
6908 tcg_temp_free_i32(t0);
6909 }
6910 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6911 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6912 {
6913 TCGv_i32 t0;
6914 int l1, l2;
6915
6916 l1 = gen_new_label();
6917 l2 = gen_new_label();
6918 t0 = tcg_temp_local_new_i32();
6919 /* No error here: 6 bits are used */
6920 tcg_gen_andi_i32(t0, arg2, 0x3F);
6921 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6922 tcg_gen_shl_i32(ret, arg1, t0);
6923 tcg_gen_br(l2);
6924 gen_set_label(l1);
6925 tcg_gen_movi_i32(ret, 0);
6926 gen_set_label(l2);
6927 tcg_temp_free_i32(t0);
6928 }
6929 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6930 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6931 {
6932 TCGv_i32 t0 = tcg_temp_new_i32();
6933 tcg_gen_andi_i32(t0, arg2, 0x1F);
6934 tcg_gen_rotl_i32(ret, arg1, t0);
6935 tcg_temp_free_i32(t0);
6936 }
6937 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6938 static inline void gen_evmergehi(DisasContext *ctx)
6939 {
6940 if (unlikely(!ctx->spe_enabled)) {
6941 gen_exception(ctx, POWERPC_EXCP_APU);
6942 return;
6943 }
6944 #if defined(TARGET_PPC64)
6945 TCGv t0 = tcg_temp_new();
6946 TCGv t1 = tcg_temp_new();
6947 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6948 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6949 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6950 tcg_temp_free(t0);
6951 tcg_temp_free(t1);
6952 #else
6953 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6954 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6955 #endif
6956 }
6957 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6958 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6959 {
6960 tcg_gen_sub_i32(ret, arg2, arg1);
6961 }
6962 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6963
6964 /* SPE arithmetic immediate */
6965 #if defined(TARGET_PPC64)
6966 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6967 static inline void gen_##name(DisasContext *ctx) \
6968 { \
6969 if (unlikely(!ctx->spe_enabled)) { \
6970 gen_exception(ctx, POWERPC_EXCP_APU); \
6971 return; \
6972 } \
6973 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6974 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6975 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6976 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6977 tcg_op(t0, t0, rA(ctx->opcode)); \
6978 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6979 tcg_gen_trunc_i64_i32(t1, t2); \
6980 tcg_temp_free_i64(t2); \
6981 tcg_op(t1, t1, rA(ctx->opcode)); \
6982 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6983 tcg_temp_free_i32(t0); \
6984 tcg_temp_free_i32(t1); \
6985 }
6986 #else
6987 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6988 static inline void gen_##name(DisasContext *ctx) \
6989 { \
6990 if (unlikely(!ctx->spe_enabled)) { \
6991 gen_exception(ctx, POWERPC_EXCP_APU); \
6992 return; \
6993 } \
6994 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6995 rA(ctx->opcode)); \
6996 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6997 rA(ctx->opcode)); \
6998 }
6999 #endif
7000 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7001 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7002
7003 /* SPE comparison */
7004 #if defined(TARGET_PPC64)
7005 #define GEN_SPEOP_COMP(name, tcg_cond) \
7006 static inline void gen_##name(DisasContext *ctx) \
7007 { \
7008 if (unlikely(!ctx->spe_enabled)) { \
7009 gen_exception(ctx, POWERPC_EXCP_APU); \
7010 return; \
7011 } \
7012 int l1 = gen_new_label(); \
7013 int l2 = gen_new_label(); \
7014 int l3 = gen_new_label(); \
7015 int l4 = gen_new_label(); \
7016 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7017 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7018 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7019 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7020 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7021 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7022 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7023 tcg_gen_br(l2); \
7024 gen_set_label(l1); \
7025 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7026 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7027 gen_set_label(l2); \
7028 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7029 tcg_gen_trunc_i64_i32(t0, t2); \
7030 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7031 tcg_gen_trunc_i64_i32(t1, t2); \
7032 tcg_temp_free_i64(t2); \
7033 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7034 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7035 ~(CRF_CH | CRF_CH_AND_CL)); \
7036 tcg_gen_br(l4); \
7037 gen_set_label(l3); \
7038 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7039 CRF_CH | CRF_CH_OR_CL); \
7040 gen_set_label(l4); \
7041 tcg_temp_free_i32(t0); \
7042 tcg_temp_free_i32(t1); \
7043 }
7044 #else
7045 #define GEN_SPEOP_COMP(name, tcg_cond) \
7046 static inline void gen_##name(DisasContext *ctx) \
7047 { \
7048 if (unlikely(!ctx->spe_enabled)) { \
7049 gen_exception(ctx, POWERPC_EXCP_APU); \
7050 return; \
7051 } \
7052 int l1 = gen_new_label(); \
7053 int l2 = gen_new_label(); \
7054 int l3 = gen_new_label(); \
7055 int l4 = gen_new_label(); \
7056 \
7057 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7058 cpu_gpr[rB(ctx->opcode)], l1); \
7059 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7060 tcg_gen_br(l2); \
7061 gen_set_label(l1); \
7062 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7063 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7064 gen_set_label(l2); \
7065 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7066 cpu_gprh[rB(ctx->opcode)], l3); \
7067 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7068 ~(CRF_CH | CRF_CH_AND_CL)); \
7069 tcg_gen_br(l4); \
7070 gen_set_label(l3); \
7071 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7072 CRF_CH | CRF_CH_OR_CL); \
7073 gen_set_label(l4); \
7074 }
7075 #endif
7076 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7077 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7078 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7079 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7080 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7081
7082 /* SPE misc */
7083 static inline void gen_brinc(DisasContext *ctx)
7084 {
7085 /* Note: brinc is usable even if SPE is disabled */
7086 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7087 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7088 }
7089 static inline void gen_evmergelo(DisasContext *ctx)
7090 {
7091 if (unlikely(!ctx->spe_enabled)) {
7092 gen_exception(ctx, POWERPC_EXCP_APU);
7093 return;
7094 }
7095 #if defined(TARGET_PPC64)
7096 TCGv t0 = tcg_temp_new();
7097 TCGv t1 = tcg_temp_new();
7098 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7099 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7100 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7101 tcg_temp_free(t0);
7102 tcg_temp_free(t1);
7103 #else
7104 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7105 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7106 #endif
7107 }
7108 static inline void gen_evmergehilo(DisasContext *ctx)
7109 {
7110 if (unlikely(!ctx->spe_enabled)) {
7111 gen_exception(ctx, POWERPC_EXCP_APU);
7112 return;
7113 }
7114 #if defined(TARGET_PPC64)
7115 TCGv t0 = tcg_temp_new();
7116 TCGv t1 = tcg_temp_new();
7117 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7118 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7119 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7120 tcg_temp_free(t0);
7121 tcg_temp_free(t1);
7122 #else
7123 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7124 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7125 #endif
7126 }
7127 static inline void gen_evmergelohi(DisasContext *ctx)
7128 {
7129 if (unlikely(!ctx->spe_enabled)) {
7130 gen_exception(ctx, POWERPC_EXCP_APU);
7131 return;
7132 }
7133 #if defined(TARGET_PPC64)
7134 TCGv t0 = tcg_temp_new();
7135 TCGv t1 = tcg_temp_new();
7136 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7137 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7138 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7139 tcg_temp_free(t0);
7140 tcg_temp_free(t1);
7141 #else
7142 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7143 TCGv_i32 tmp = tcg_temp_new_i32();
7144 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7145 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7146 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7147 tcg_temp_free_i32(tmp);
7148 } else {
7149 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7150 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7151 }
7152 #endif
7153 }
7154 static inline void gen_evsplati(DisasContext *ctx)
7155 {
7156 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7157
7158 #if defined(TARGET_PPC64)
7159 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7160 #else
7161 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7162 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7163 #endif
7164 }
7165 static inline void gen_evsplatfi(DisasContext *ctx)
7166 {
7167 uint64_t imm = rA(ctx->opcode) << 27;
7168
7169 #if defined(TARGET_PPC64)
7170 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7171 #else
7172 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7173 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7174 #endif
7175 }
7176
7177 static inline void gen_evsel(DisasContext *ctx)
7178 {
7179 int l1 = gen_new_label();
7180 int l2 = gen_new_label();
7181 int l3 = gen_new_label();
7182 int l4 = gen_new_label();
7183 TCGv_i32 t0 = tcg_temp_local_new_i32();
7184 #if defined(TARGET_PPC64)
7185 TCGv t1 = tcg_temp_local_new();
7186 TCGv t2 = tcg_temp_local_new();
7187 #endif
7188 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7189 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7190 #if defined(TARGET_PPC64)
7191 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7192 #else
7193 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7194 #endif
7195 tcg_gen_br(l2);
7196 gen_set_label(l1);
7197 #if defined(TARGET_PPC64)
7198 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7199 #else
7200 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7201 #endif
7202 gen_set_label(l2);
7203 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7204 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7205 #if defined(TARGET_PPC64)
7206 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7207 #else
7208 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7209 #endif
7210 tcg_gen_br(l4);
7211 gen_set_label(l3);
7212 #if defined(TARGET_PPC64)
7213 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7214 #else
7215 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7216 #endif
7217 gen_set_label(l4);
7218 tcg_temp_free_i32(t0);
7219 #if defined(TARGET_PPC64)
7220 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7221 tcg_temp_free(t1);
7222 tcg_temp_free(t2);
7223 #endif
7224 }
7225
7226 static void gen_evsel0(DisasContext *ctx)
7227 {
7228 gen_evsel(ctx);
7229 }
7230
7231 static void gen_evsel1(DisasContext *ctx)
7232 {
7233 gen_evsel(ctx);
7234 }
7235
7236 static void gen_evsel2(DisasContext *ctx)
7237 {
7238 gen_evsel(ctx);
7239 }
7240
7241 static void gen_evsel3(DisasContext *ctx)
7242 {
7243 gen_evsel(ctx);
7244 }
7245
7246 /* Multiply */
7247
7248 static inline void gen_evmwumi(DisasContext *ctx)
7249 {
7250 TCGv_i64 t0, t1;
7251
7252 if (unlikely(!ctx->spe_enabled)) {
7253 gen_exception(ctx, POWERPC_EXCP_APU);
7254 return;
7255 }
7256
7257 t0 = tcg_temp_new_i64();
7258 t1 = tcg_temp_new_i64();
7259
7260 /* t0 := rA; t1 := rB */
7261 #if defined(TARGET_PPC64)
7262 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7263 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7264 #else
7265 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7266 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7267 #endif
7268
7269 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7270
7271 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7272
7273 tcg_temp_free_i64(t0);
7274 tcg_temp_free_i64(t1);
7275 }
7276
7277 static inline void gen_evmwumia(DisasContext *ctx)
7278 {
7279 TCGv_i64 tmp;
7280
7281 if (unlikely(!ctx->spe_enabled)) {
7282 gen_exception(ctx, POWERPC_EXCP_APU);
7283 return;
7284 }
7285
7286 gen_evmwumi(ctx); /* rD := rA * rB */
7287
7288 tmp = tcg_temp_new_i64();
7289
7290 /* acc := rD */
7291 gen_load_gpr64(tmp, rD(ctx->opcode));
7292 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
7293 tcg_temp_free_i64(tmp);
7294 }
7295
7296 static inline void gen_evmwumiaa(DisasContext *ctx)
7297 {
7298 TCGv_i64 acc;
7299 TCGv_i64 tmp;
7300
7301 if (unlikely(!ctx->spe_enabled)) {
7302 gen_exception(ctx, POWERPC_EXCP_APU);
7303 return;
7304 }
7305
7306 gen_evmwumi(ctx); /* rD := rA * rB */
7307
7308 acc = tcg_temp_new_i64();
7309 tmp = tcg_temp_new_i64();
7310
7311 /* tmp := rD */
7312 gen_load_gpr64(tmp, rD(ctx->opcode));
7313
7314 /* Load acc */
7315 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7316
7317 /* acc := tmp + acc */
7318 tcg_gen_add_i64(acc, acc, tmp);
7319
7320 /* Store acc */
7321 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7322
7323 /* rD := acc */
7324 gen_store_gpr64(rD(ctx->opcode), acc);
7325
7326 tcg_temp_free_i64(acc);
7327 tcg_temp_free_i64(tmp);
7328 }
7329
7330 static inline void gen_evmwsmi(DisasContext *ctx)
7331 {
7332 TCGv_i64 t0, t1;
7333
7334 if (unlikely(!ctx->spe_enabled)) {
7335 gen_exception(ctx, POWERPC_EXCP_APU);
7336 return;
7337 }
7338
7339 t0 = tcg_temp_new_i64();
7340 t1 = tcg_temp_new_i64();
7341
7342 /* t0 := rA; t1 := rB */
7343 #if defined(TARGET_PPC64)
7344 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7345 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7346 #else
7347 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7348 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7349 #endif
7350
7351 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7352
7353 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7354
7355 tcg_temp_free_i64(t0);
7356 tcg_temp_free_i64(t1);
7357 }
7358
7359 static inline void gen_evmwsmia(DisasContext *ctx)
7360 {
7361 TCGv_i64 tmp;
7362
7363 gen_evmwsmi(ctx); /* rD := rA * rB */
7364
7365 tmp = tcg_temp_new_i64();
7366
7367 /* acc := rD */
7368 gen_load_gpr64(tmp, rD(ctx->opcode));
7369 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
7370
7371 tcg_temp_free_i64(tmp);
7372 }
7373
7374 static inline void gen_evmwsmiaa(DisasContext *ctx)
7375 {
7376 TCGv_i64 acc = tcg_temp_new_i64();
7377 TCGv_i64 tmp = tcg_temp_new_i64();
7378
7379 gen_evmwsmi(ctx); /* rD := rA * rB */
7380
7381 acc = tcg_temp_new_i64();
7382 tmp = tcg_temp_new_i64();
7383
7384 /* tmp := rD */
7385 gen_load_gpr64(tmp, rD(ctx->opcode));
7386
7387 /* Load acc */
7388 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7389
7390 /* acc := tmp + acc */
7391 tcg_gen_add_i64(acc, acc, tmp);
7392
7393 /* Store acc */
7394 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7395
7396 /* rD := acc */
7397 gen_store_gpr64(rD(ctx->opcode), acc);
7398
7399 tcg_temp_free_i64(acc);
7400 tcg_temp_free_i64(tmp);
7401 }
7402
7403 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7404 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7405 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7406 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7407 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7408 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7409 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7410 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7411 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, PPC_SPE);
7412 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7413 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7414 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7415 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7416 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7417 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7418 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7419 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7420 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7421 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7422 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7423 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7424 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7425 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7426 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7427 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7428 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7429 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7430 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7431 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7432
7433 /* SPE load and stores */
7434 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7435 {
7436 target_ulong uimm = rB(ctx->opcode);
7437
7438 if (rA(ctx->opcode) == 0) {
7439 tcg_gen_movi_tl(EA, uimm << sh);
7440 } else {
7441 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7442 #if defined(TARGET_PPC64)
7443 if (!ctx->sf_mode) {
7444 tcg_gen_ext32u_tl(EA, EA);
7445 }
7446 #endif
7447 }
7448 }
7449
7450 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7451 {
7452 #if defined(TARGET_PPC64)
7453 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7454 #else
7455 TCGv_i64 t0 = tcg_temp_new_i64();
7456 gen_qemu_ld64(ctx, t0, addr);
7457 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7458 tcg_gen_shri_i64(t0, t0, 32);
7459 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7460 tcg_temp_free_i64(t0);
7461 #endif
7462 }
7463
7464 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7465 {
7466 #if defined(TARGET_PPC64)
7467 TCGv t0 = tcg_temp_new();
7468 gen_qemu_ld32u(ctx, t0, addr);
7469 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7470 gen_addr_add(ctx, addr, addr, 4);
7471 gen_qemu_ld32u(ctx, t0, addr);
7472 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7473 tcg_temp_free(t0);
7474 #else
7475 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7476 gen_addr_add(ctx, addr, addr, 4);
7477 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7478 #endif
7479 }
7480
7481 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7482 {
7483 TCGv t0 = tcg_temp_new();
7484 #if defined(TARGET_PPC64)
7485 gen_qemu_ld16u(ctx, t0, addr);
7486 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7487 gen_addr_add(ctx, addr, addr, 2);
7488 gen_qemu_ld16u(ctx, t0, addr);
7489 tcg_gen_shli_tl(t0, t0, 32);
7490 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7491 gen_addr_add(ctx, addr, addr, 2);
7492 gen_qemu_ld16u(ctx, t0, addr);
7493 tcg_gen_shli_tl(t0, t0, 16);
7494 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7495 gen_addr_add(ctx, addr, addr, 2);
7496 gen_qemu_ld16u(ctx, t0, addr);
7497 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7498 #else
7499 gen_qemu_ld16u(ctx, t0, addr);
7500 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7501 gen_addr_add(ctx, addr, addr, 2);
7502 gen_qemu_ld16u(ctx, t0, addr);
7503 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7504 gen_addr_add(ctx, addr, addr, 2);
7505 gen_qemu_ld16u(ctx, t0, addr);
7506 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7507 gen_addr_add(ctx, addr, addr, 2);
7508 gen_qemu_ld16u(ctx, t0, addr);
7509 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7510 #endif
7511 tcg_temp_free(t0);
7512 }
7513
7514 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7515 {
7516 TCGv t0 = tcg_temp_new();
7517 gen_qemu_ld16u(ctx, t0, addr);
7518 #if defined(TARGET_PPC64)
7519 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7520 tcg_gen_shli_tl(t0, t0, 16);
7521 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7522 #else
7523 tcg_gen_shli_tl(t0, t0, 16);
7524 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7525 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7526 #endif
7527 tcg_temp_free(t0);
7528 }
7529
7530 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7531 {
7532 TCGv t0 = tcg_temp_new();
7533 gen_qemu_ld16u(ctx, t0, addr);
7534 #if defined(TARGET_PPC64)
7535 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7536 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7537 #else
7538 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7539 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7540 #endif
7541 tcg_temp_free(t0);
7542 }
7543
7544 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7545 {
7546 TCGv t0 = tcg_temp_new();
7547 gen_qemu_ld16s(ctx, t0, addr);
7548 #if defined(TARGET_PPC64)
7549 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7550 tcg_gen_ext32u_tl(t0, t0);
7551 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7552 #else
7553 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7554 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7555 #endif
7556 tcg_temp_free(t0);
7557 }
7558
7559 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7560 {
7561 TCGv t0 = tcg_temp_new();
7562 #if defined(TARGET_PPC64)
7563 gen_qemu_ld16u(ctx, t0, addr);
7564 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7565 gen_addr_add(ctx, addr, addr, 2);
7566 gen_qemu_ld16u(ctx, t0, addr);
7567 tcg_gen_shli_tl(t0, t0, 16);
7568 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7569 #else
7570 gen_qemu_ld16u(ctx, t0, addr);
7571 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7572 gen_addr_add(ctx, addr, addr, 2);
7573 gen_qemu_ld16u(ctx, t0, addr);
7574 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7575 #endif
7576 tcg_temp_free(t0);
7577 }
7578
7579 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7580 {
7581 #if defined(TARGET_PPC64)
7582 TCGv t0 = tcg_temp_new();
7583 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7584 gen_addr_add(ctx, addr, addr, 2);
7585 gen_qemu_ld16u(ctx, t0, addr);
7586 tcg_gen_shli_tl(t0, t0, 32);
7587 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7588 tcg_temp_free(t0);
7589 #else
7590 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7591 gen_addr_add(ctx, addr, addr, 2);
7592 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7593 #endif
7594 }
7595
7596 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7597 {
7598 #if defined(TARGET_PPC64)
7599 TCGv t0 = tcg_temp_new();
7600 gen_qemu_ld16s(ctx, t0, addr);
7601 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7602 gen_addr_add(ctx, addr, addr, 2);
7603 gen_qemu_ld16s(ctx, t0, addr);
7604 tcg_gen_shli_tl(t0, t0, 32);
7605 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7606 tcg_temp_free(t0);
7607 #else
7608 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7609 gen_addr_add(ctx, addr, addr, 2);
7610 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7611 #endif
7612 }
7613
7614 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7615 {
7616 TCGv t0 = tcg_temp_new();
7617 gen_qemu_ld32u(ctx, t0, addr);
7618 #if defined(TARGET_PPC64)
7619 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7620 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7621 #else
7622 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7623 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7624 #endif
7625 tcg_temp_free(t0);
7626 }
7627
7628 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7629 {
7630 TCGv t0 = tcg_temp_new();
7631 #if defined(TARGET_PPC64)
7632 gen_qemu_ld16u(ctx, t0, addr);
7633 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7634 tcg_gen_shli_tl(t0, t0, 32);
7635 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7636 gen_addr_add(ctx, addr, addr, 2);
7637 gen_qemu_ld16u(ctx, t0, addr);
7638 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7639 tcg_gen_shli_tl(t0, t0, 16);
7640 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7641 #else
7642 gen_qemu_ld16u(ctx, t0, addr);
7643 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7644 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7645 gen_addr_add(ctx, addr, addr, 2);
7646 gen_qemu_ld16u(ctx, t0, addr);
7647 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7648 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7649 #endif
7650 tcg_temp_free(t0);
7651 }
7652
7653 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7654 {
7655 #if defined(TARGET_PPC64)
7656 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7657 #else
7658 TCGv_i64 t0 = tcg_temp_new_i64();
7659 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7660 gen_qemu_st64(ctx, t0, addr);
7661 tcg_temp_free_i64(t0);
7662 #endif
7663 }
7664
7665 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7666 {
7667 #if defined(TARGET_PPC64)
7668 TCGv t0 = tcg_temp_new();
7669 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7670 gen_qemu_st32(ctx, t0, addr);
7671 tcg_temp_free(t0);
7672 #else
7673 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7674 #endif
7675 gen_addr_add(ctx, addr, addr, 4);
7676 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7677 }
7678
7679 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7680 {
7681 TCGv t0 = tcg_temp_new();
7682 #if defined(TARGET_PPC64)
7683 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7684 #else
7685 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7686 #endif
7687 gen_qemu_st16(ctx, t0, addr);
7688 gen_addr_add(ctx, addr, addr, 2);
7689 #if defined(TARGET_PPC64)
7690 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7691 gen_qemu_st16(ctx, t0, addr);
7692 #else
7693 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7694 #endif
7695 gen_addr_add(ctx, addr, addr, 2);
7696 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7697 gen_qemu_st16(ctx, t0, addr);
7698 tcg_temp_free(t0);
7699 gen_addr_add(ctx, addr, addr, 2);
7700 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7701 }
7702
7703 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7704 {
7705 TCGv t0 = tcg_temp_new();
7706 #if defined(TARGET_PPC64)
7707 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7708 #else
7709 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7710 #endif
7711 gen_qemu_st16(ctx, t0, addr);
7712 gen_addr_add(ctx, addr, addr, 2);
7713 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7714 gen_qemu_st16(ctx, t0, addr);
7715 tcg_temp_free(t0);
7716 }
7717
7718 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7719 {
7720 #if defined(TARGET_PPC64)
7721 TCGv t0 = tcg_temp_new();
7722 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7723 gen_qemu_st16(ctx, t0, addr);
7724 tcg_temp_free(t0);
7725 #else
7726 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7727 #endif
7728 gen_addr_add(ctx, addr, addr, 2);
7729 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7730 }
7731
7732 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7733 {
7734 #if defined(TARGET_PPC64)
7735 TCGv t0 = tcg_temp_new();
7736 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7737 gen_qemu_st32(ctx, t0, addr);
7738 tcg_temp_free(t0);
7739 #else
7740 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7741 #endif
7742 }
7743
7744 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7745 {
7746 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7747 }
7748
7749 #define GEN_SPEOP_LDST(name, opc2, sh) \
7750 static void glue(gen_, name)(DisasContext *ctx) \
7751 { \
7752 TCGv t0; \
7753 if (unlikely(!ctx->spe_enabled)) { \
7754 gen_exception(ctx, POWERPC_EXCP_APU); \
7755 return; \
7756 } \
7757 gen_set_access_type(ctx, ACCESS_INT); \
7758 t0 = tcg_temp_new(); \
7759 if (Rc(ctx->opcode)) { \
7760 gen_addr_spe_imm_index(ctx, t0, sh); \
7761 } else { \
7762 gen_addr_reg_index(ctx, t0); \
7763 } \
7764 gen_op_##name(ctx, t0); \
7765 tcg_temp_free(t0); \
7766 }
7767
7768 GEN_SPEOP_LDST(evldd, 0x00, 3);
7769 GEN_SPEOP_LDST(evldw, 0x01, 3);
7770 GEN_SPEOP_LDST(evldh, 0x02, 3);
7771 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7772 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7773 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7774 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7775 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7776 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7777 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7778 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7779
7780 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7781 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7782 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7783 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7784 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7785 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7786 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7787
7788 /* Multiply and add - TODO */
7789 #if 0
7790 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7791 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7792 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7793 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7794 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7795 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7796 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7797 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7798 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7799 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7800 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7801 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7802
7803 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7804 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7805 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7806 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7807 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7808 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7809 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7810 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7811 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7812 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7813 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7814 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7815
7816 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7817 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7818 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7819 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7820 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7821
7822 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7823 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7824 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7825 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7826 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7827 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7828 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7829 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7830 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7831 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7832 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7833 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7834
7835 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7836 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7837 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7838 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7839
7840 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7841 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7842 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7843 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7844 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7845 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7846 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7847 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7848 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7849 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7850 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7851 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7852
7853 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7854 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7855 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7856 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7857 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7858 #endif
7859
7860 /*** SPE floating-point extension ***/
7861 #if defined(TARGET_PPC64)
7862 #define GEN_SPEFPUOP_CONV_32_32(name) \
7863 static inline void gen_##name(DisasContext *ctx) \
7864 { \
7865 TCGv_i32 t0; \
7866 TCGv t1; \
7867 t0 = tcg_temp_new_i32(); \
7868 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7869 gen_helper_##name(t0, t0); \
7870 t1 = tcg_temp_new(); \
7871 tcg_gen_extu_i32_tl(t1, t0); \
7872 tcg_temp_free_i32(t0); \
7873 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7874 0xFFFFFFFF00000000ULL); \
7875 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7876 tcg_temp_free(t1); \
7877 }
7878 #define GEN_SPEFPUOP_CONV_32_64(name) \
7879 static inline void gen_##name(DisasContext *ctx) \
7880 { \
7881 TCGv_i32 t0; \
7882 TCGv t1; \
7883 t0 = tcg_temp_new_i32(); \
7884 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7885 t1 = tcg_temp_new(); \
7886 tcg_gen_extu_i32_tl(t1, t0); \
7887 tcg_temp_free_i32(t0); \
7888 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7889 0xFFFFFFFF00000000ULL); \
7890 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7891 tcg_temp_free(t1); \
7892 }
7893 #define GEN_SPEFPUOP_CONV_64_32(name) \
7894 static inline void gen_##name(DisasContext *ctx) \
7895 { \
7896 TCGv_i32 t0 = tcg_temp_new_i32(); \
7897 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7898 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7899 tcg_temp_free_i32(t0); \
7900 }
7901 #define GEN_SPEFPUOP_CONV_64_64(name) \
7902 static inline void gen_##name(DisasContext *ctx) \
7903 { \
7904 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7905 }
7906 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7907 static inline void gen_##name(DisasContext *ctx) \
7908 { \
7909 TCGv_i32 t0, t1; \
7910 TCGv_i64 t2; \
7911 if (unlikely(!ctx->spe_enabled)) { \
7912 gen_exception(ctx, POWERPC_EXCP_APU); \
7913 return; \
7914 } \
7915 t0 = tcg_temp_new_i32(); \
7916 t1 = tcg_temp_new_i32(); \
7917 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7918 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7919 gen_helper_##name(t0, t0, t1); \
7920 tcg_temp_free_i32(t1); \
7921 t2 = tcg_temp_new(); \
7922 tcg_gen_extu_i32_tl(t2, t0); \
7923 tcg_temp_free_i32(t0); \
7924 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7925 0xFFFFFFFF00000000ULL); \
7926 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7927 tcg_temp_free(t2); \
7928 }
7929 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7930 static inline void gen_##name(DisasContext *ctx) \
7931 { \
7932 if (unlikely(!ctx->spe_enabled)) { \
7933 gen_exception(ctx, POWERPC_EXCP_APU); \
7934 return; \
7935 } \
7936 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7937 cpu_gpr[rB(ctx->opcode)]); \
7938 }
7939 #define GEN_SPEFPUOP_COMP_32(name) \
7940 static inline void gen_##name(DisasContext *ctx) \
7941 { \
7942 TCGv_i32 t0, t1; \
7943 if (unlikely(!ctx->spe_enabled)) { \
7944 gen_exception(ctx, POWERPC_EXCP_APU); \
7945 return; \
7946 } \
7947 t0 = tcg_temp_new_i32(); \
7948 t1 = tcg_temp_new_i32(); \
7949 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7950 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7951 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7952 tcg_temp_free_i32(t0); \
7953 tcg_temp_free_i32(t1); \
7954 }
7955 #define GEN_SPEFPUOP_COMP_64(name) \
7956 static inline void gen_##name(DisasContext *ctx) \
7957 { \
7958 if (unlikely(!ctx->spe_enabled)) { \
7959 gen_exception(ctx, POWERPC_EXCP_APU); \
7960 return; \
7961 } \
7962 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7963 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7964 }
7965 #else
7966 #define GEN_SPEFPUOP_CONV_32_32(name) \
7967 static inline void gen_##name(DisasContext *ctx) \
7968 { \
7969 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7970 }
7971 #define GEN_SPEFPUOP_CONV_32_64(name) \
7972 static inline void gen_##name(DisasContext *ctx) \
7973 { \
7974 TCGv_i64 t0 = tcg_temp_new_i64(); \
7975 gen_load_gpr64(t0, rB(ctx->opcode)); \
7976 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7977 tcg_temp_free_i64(t0); \
7978 }
7979 #define GEN_SPEFPUOP_CONV_64_32(name) \
7980 static inline void gen_##name(DisasContext *ctx) \
7981 { \
7982 TCGv_i64 t0 = tcg_temp_new_i64(); \
7983 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7984 gen_store_gpr64(rD(ctx->opcode), t0); \
7985 tcg_temp_free_i64(t0); \
7986 }
7987 #define GEN_SPEFPUOP_CONV_64_64(name) \
7988 static inline void gen_##name(DisasContext *ctx) \
7989 { \
7990 TCGv_i64 t0 = tcg_temp_new_i64(); \
7991 gen_load_gpr64(t0, rB(ctx->opcode)); \
7992 gen_helper_##name(t0, t0); \
7993 gen_store_gpr64(rD(ctx->opcode), t0); \
7994 tcg_temp_free_i64(t0); \
7995 }
7996 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7997 static inline void gen_##name(DisasContext *ctx) \
7998 { \
7999 if (unlikely(!ctx->spe_enabled)) { \
8000 gen_exception(ctx, POWERPC_EXCP_APU); \
8001 return; \
8002 } \
8003 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
8004 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8005 }
8006 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8007 static inline void gen_##name(DisasContext *ctx) \
8008 { \
8009 TCGv_i64 t0, t1; \
8010 if (unlikely(!ctx->spe_enabled)) { \
8011 gen_exception(ctx, POWERPC_EXCP_APU); \
8012 return; \
8013 } \
8014 t0 = tcg_temp_new_i64(); \
8015 t1 = tcg_temp_new_i64(); \
8016 gen_load_gpr64(t0, rA(ctx->opcode)); \
8017 gen_load_gpr64(t1, rB(ctx->opcode)); \
8018 gen_helper_##name(t0, t0, t1); \
8019 gen_store_gpr64(rD(ctx->opcode), t0); \
8020 tcg_temp_free_i64(t0); \
8021 tcg_temp_free_i64(t1); \
8022 }
8023 #define GEN_SPEFPUOP_COMP_32(name) \
8024 static inline void gen_##name(DisasContext *ctx) \
8025 { \
8026 if (unlikely(!ctx->spe_enabled)) { \
8027 gen_exception(ctx, POWERPC_EXCP_APU); \
8028 return; \
8029 } \
8030 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8031 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8032 }
8033 #define GEN_SPEFPUOP_COMP_64(name) \
8034 static inline void gen_##name(DisasContext *ctx) \
8035 { \
8036 TCGv_i64 t0, t1; \
8037 if (unlikely(!ctx->spe_enabled)) { \
8038 gen_exception(ctx, POWERPC_EXCP_APU); \
8039 return; \
8040 } \
8041 t0 = tcg_temp_new_i64(); \
8042 t1 = tcg_temp_new_i64(); \
8043 gen_load_gpr64(t0, rA(ctx->opcode)); \
8044 gen_load_gpr64(t1, rB(ctx->opcode)); \
8045 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
8046 tcg_temp_free_i64(t0); \
8047 tcg_temp_free_i64(t1); \
8048 }
8049 #endif
8050
8051 /* Single precision floating-point vectors operations */
8052 /* Arithmetic */
8053 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8054 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8055 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8056 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8057 static inline void gen_evfsabs(DisasContext *ctx)
8058 {
8059 if (unlikely(!ctx->spe_enabled)) {
8060 gen_exception(ctx, POWERPC_EXCP_APU);
8061 return;
8062 }
8063 #if defined(TARGET_PPC64)
8064 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8065 #else
8066 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8067 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8068 #endif
8069 }
8070 static inline void gen_evfsnabs(DisasContext *ctx)
8071 {
8072 if (unlikely(!ctx->spe_enabled)) {
8073 gen_exception(ctx, POWERPC_EXCP_APU);
8074 return;
8075 }
8076 #if defined(TARGET_PPC64)
8077 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8078 #else
8079 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8080 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8081 #endif
8082 }
8083 static inline void gen_evfsneg(DisasContext *ctx)
8084 {
8085 if (unlikely(!ctx->spe_enabled)) {
8086 gen_exception(ctx, POWERPC_EXCP_APU);
8087 return;
8088 }
8089 #if defined(TARGET_PPC64)
8090 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8091 #else
8092 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8093 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8094 #endif
8095 }
8096
8097 /* Conversion */
8098 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8099 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8100 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8101 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8102 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8103 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8104 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8105 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8106 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8107 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8108
8109 /* Comparison */
8110 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8111 GEN_SPEFPUOP_COMP_64(evfscmplt);
8112 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8113 GEN_SPEFPUOP_COMP_64(evfststgt);
8114 GEN_SPEFPUOP_COMP_64(evfststlt);
8115 GEN_SPEFPUOP_COMP_64(evfststeq);
8116
8117 /* Opcodes definitions */
8118 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
8119 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
8120 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
8121 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
8122 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
8123 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
8124 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
8125 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
8126 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
8127 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
8128 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
8129 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
8130 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
8131 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
8132
8133 /* Single precision floating-point operations */
8134 /* Arithmetic */
8135 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8136 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8137 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8138 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8139 static inline void gen_efsabs(DisasContext *ctx)
8140 {
8141 if (unlikely(!ctx->spe_enabled)) {
8142 gen_exception(ctx, POWERPC_EXCP_APU);
8143 return;
8144 }
8145 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8146 }
8147 static inline void gen_efsnabs(DisasContext *ctx)
8148 {
8149 if (unlikely(!ctx->spe_enabled)) {
8150 gen_exception(ctx, POWERPC_EXCP_APU);
8151 return;
8152 }
8153 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8154 }
8155 static inline void gen_efsneg(DisasContext *ctx)
8156 {
8157 if (unlikely(!ctx->spe_enabled)) {
8158 gen_exception(ctx, POWERPC_EXCP_APU);
8159 return;
8160 }
8161 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8162 }
8163
8164 /* Conversion */
8165 GEN_SPEFPUOP_CONV_32_32(efscfui);
8166 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8167 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8168 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8169 GEN_SPEFPUOP_CONV_32_32(efsctui);
8170 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8171 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8172 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8173 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8174 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8175 GEN_SPEFPUOP_CONV_32_64(efscfd);
8176
8177 /* Comparison */
8178 GEN_SPEFPUOP_COMP_32(efscmpgt);
8179 GEN_SPEFPUOP_COMP_32(efscmplt);
8180 GEN_SPEFPUOP_COMP_32(efscmpeq);
8181 GEN_SPEFPUOP_COMP_32(efststgt);
8182 GEN_SPEFPUOP_COMP_32(efststlt);
8183 GEN_SPEFPUOP_COMP_32(efststeq);
8184
8185 /* Opcodes definitions */
8186 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
8187 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
8188 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
8189 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
8190 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8191 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8192 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8193 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8194 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8195 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8196 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8197 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8198 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8199 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8200
8201 /* Double precision floating-point operations */
8202 /* Arithmetic */
8203 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8204 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8205 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8206 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8207 static inline void gen_efdabs(DisasContext *ctx)
8208 {
8209 if (unlikely(!ctx->spe_enabled)) {
8210 gen_exception(ctx, POWERPC_EXCP_APU);
8211 return;
8212 }
8213 #if defined(TARGET_PPC64)
8214 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8215 #else
8216 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8217 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8218 #endif
8219 }
8220 static inline void gen_efdnabs(DisasContext *ctx)
8221 {
8222 if (unlikely(!ctx->spe_enabled)) {
8223 gen_exception(ctx, POWERPC_EXCP_APU);
8224 return;
8225 }
8226 #if defined(TARGET_PPC64)
8227 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8228 #else
8229 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8230 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8231 #endif
8232 }
8233 static inline void gen_efdneg(DisasContext *ctx)
8234 {
8235 if (unlikely(!ctx->spe_enabled)) {
8236 gen_exception(ctx, POWERPC_EXCP_APU);
8237 return;
8238 }
8239 #if defined(TARGET_PPC64)
8240 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8241 #else
8242 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8243 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8244 #endif
8245 }
8246
8247 /* Conversion */
8248 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8249 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8250 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8251 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8252 GEN_SPEFPUOP_CONV_32_64(efdctui);
8253 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8254 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8255 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8256 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8257 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8258 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8259 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8260 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8261 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8262 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8263
8264 /* Comparison */
8265 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8266 GEN_SPEFPUOP_COMP_64(efdcmplt);
8267 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8268 GEN_SPEFPUOP_COMP_64(efdtstgt);
8269 GEN_SPEFPUOP_COMP_64(efdtstlt);
8270 GEN_SPEFPUOP_COMP_64(efdtsteq);
8271
8272 /* Opcodes definitions */
8273 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8274 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8275 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8276 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8277 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8278 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8279 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8280 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8281 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8282 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8283 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8284 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8285 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8286 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8287 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8288 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8289
8290 static opcode_t opcodes[] = {
8291 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8292 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8293 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8294 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8295 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8296 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8297 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8298 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8299 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8300 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8301 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8302 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8303 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8304 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8305 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8306 #if defined(TARGET_PPC64)
8307 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8308 #endif
8309 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8310 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8311 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8312 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8313 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8314 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8315 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8316 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8317 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8318 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8319 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8320 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8321 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8322 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8323 #if defined(TARGET_PPC64)
8324 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8325 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8326 #endif
8327 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8328 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8329 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8330 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8331 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8332 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8333 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8334 #if defined(TARGET_PPC64)
8335 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8336 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8337 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8338 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8339 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8340 #endif
8341 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8342 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8343 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8344 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8345 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8346 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8347 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8348 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8349 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8350 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8351 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8352 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8353 #if defined(TARGET_PPC64)
8354 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8355 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8356 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8357 #endif
8358 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8359 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8360 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8361 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8362 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8363 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8364 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8365 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8366 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8367 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8368 #if defined(TARGET_PPC64)
8369 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8370 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8371 #endif
8372 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8373 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8374 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8375 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8376 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8377 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8378 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8379 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8380 #if defined(TARGET_PPC64)
8381 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8382 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8383 #endif
8384 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8385 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8386 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8387 #if defined(TARGET_PPC64)
8388 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8389 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8390 #endif
8391 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8392 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8393 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8394 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8395 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8396 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8397 #if defined(TARGET_PPC64)
8398 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8399 #endif
8400 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8401 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8402 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8403 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8404 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8405 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8406 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8407 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ),
8408 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT),
8409 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8410 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8411 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8412 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8413 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8414 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8415 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8416 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8417 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8418 #if defined(TARGET_PPC64)
8419 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8420 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8421 PPC_SEGMENT_64B),
8422 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8423 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8424 PPC_SEGMENT_64B),
8425 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8426 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8427 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8428 #endif
8429 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8430 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8431 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8432 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8433 #if defined(TARGET_PPC64)
8434 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8435 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8436 #endif
8437 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8438 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8439 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8440 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8441 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8442 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8443 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8444 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8445 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8446 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8447 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8448 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8449 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8450 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8451 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8452 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8453 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8454 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8455 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8456 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8457 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8458 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8459 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8460 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8461 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8462 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8463 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8464 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8465 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8466 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8467 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8468 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8469 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8470 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8471 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8472 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8473 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8474 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8475 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8476 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8477 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8478 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8479 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8480 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8481 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8482 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8483 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8484 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8485 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8486 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8487 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8488 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8489 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8490 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8491 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8492 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8493 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8494 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8495 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8496 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8497 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8498 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8499 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8500 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8501 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8502 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8503 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8504 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8505 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8506 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8507 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8508 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8509 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8510 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8511 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8512 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8513 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8514 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8515 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8516 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8517 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8518 PPC_NONE, PPC2_BOOKE206),
8519 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8520 PPC_NONE, PPC2_BOOKE206),
8521 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8522 PPC_NONE, PPC2_BOOKE206),
8523 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8524 PPC_NONE, PPC2_BOOKE206),
8525 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8526 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8527 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8528 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8529 PPC_BOOKE, PPC2_BOOKE206),
8530 GEN_HANDLER_E(msync, 0x1F, 0x16, 0x12, 0x03FFF801,
8531 PPC_BOOKE, PPC2_BOOKE206),
8532 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8533 PPC_BOOKE, PPC2_BOOKE206),
8534 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8535 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8536 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8537 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8538 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8539 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8540 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8541 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8542 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8543 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8544
8545 #undef GEN_INT_ARITH_ADD
8546 #undef GEN_INT_ARITH_ADD_CONST
8547 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8548 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8549 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8550 add_ca, compute_ca, compute_ov) \
8551 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8552 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8553 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8554 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8555 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8556 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8557 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8558 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8559 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8560 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8561 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8562
8563 #undef GEN_INT_ARITH_DIVW
8564 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8565 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8566 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8567 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8568 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8569 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8570
8571 #if defined(TARGET_PPC64)
8572 #undef GEN_INT_ARITH_DIVD
8573 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8574 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8575 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8576 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8577 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8578 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8579
8580 #undef GEN_INT_ARITH_MUL_HELPER
8581 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8582 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8583 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8584 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8585 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8586 #endif
8587
8588 #undef GEN_INT_ARITH_SUBF
8589 #undef GEN_INT_ARITH_SUBF_CONST
8590 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8591 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8592 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8593 add_ca, compute_ca, compute_ov) \
8594 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8595 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8596 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8597 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8598 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8599 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8600 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8601 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8602 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8603 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8604 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8605
8606 #undef GEN_LOGICAL1
8607 #undef GEN_LOGICAL2
8608 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8609 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8610 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8611 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8612 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8613 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8614 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8615 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8616 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8617 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8618 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8619 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8620 #if defined(TARGET_PPC64)
8621 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8622 #endif
8623
8624 #if defined(TARGET_PPC64)
8625 #undef GEN_PPC64_R2
8626 #undef GEN_PPC64_R4
8627 #define GEN_PPC64_R2(name, opc1, opc2) \
8628 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8629 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8630 PPC_64B)
8631 #define GEN_PPC64_R4(name, opc1, opc2) \
8632 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8633 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8634 PPC_64B), \
8635 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8636 PPC_64B), \
8637 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8638 PPC_64B)
8639 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8640 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8641 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8642 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8643 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8644 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8645 #endif
8646
8647 #undef _GEN_FLOAT_ACB
8648 #undef GEN_FLOAT_ACB
8649 #undef _GEN_FLOAT_AB
8650 #undef GEN_FLOAT_AB
8651 #undef _GEN_FLOAT_AC
8652 #undef GEN_FLOAT_AC
8653 #undef GEN_FLOAT_B
8654 #undef GEN_FLOAT_BS
8655 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8656 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8657 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8658 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8659 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8660 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8661 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8662 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8663 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8664 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8665 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8666 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8667 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8668 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8669 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8670 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8671 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8672 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8673 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8674
8675 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8676 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8677 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8678 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8679 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8680 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8681 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8682 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8683 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8684 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8685 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8686 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8687 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8688 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8689 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8690 #if defined(TARGET_PPC64)
8691 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8692 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8693 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8694 #endif
8695 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8696 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8697 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8698 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8699 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8700 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8701 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8702
8703 #undef GEN_LD
8704 #undef GEN_LDU
8705 #undef GEN_LDUX
8706 #undef GEN_LDX
8707 #undef GEN_LDS
8708 #define GEN_LD(name, ldop, opc, type) \
8709 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8710 #define GEN_LDU(name, ldop, opc, type) \
8711 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8712 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8713 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8714 #define GEN_LDX(name, ldop, opc2, opc3, type) \
8715 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8716 #define GEN_LDS(name, ldop, op, type) \
8717 GEN_LD(name, ldop, op | 0x20, type) \
8718 GEN_LDU(name, ldop, op | 0x21, type) \
8719 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8720 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8721
8722 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8723 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8724 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8725 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8726 #if defined(TARGET_PPC64)
8727 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8728 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8729 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8730 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8731 #endif
8732 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8733 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8734
8735 #undef GEN_ST
8736 #undef GEN_STU
8737 #undef GEN_STUX
8738 #undef GEN_STX
8739 #undef GEN_STS
8740 #define GEN_ST(name, stop, opc, type) \
8741 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8742 #define GEN_STU(name, stop, opc, type) \
8743 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8744 #define GEN_STUX(name, stop, opc2, opc3, type) \
8745 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8746 #define GEN_STX(name, stop, opc2, opc3, type) \
8747 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8748 #define GEN_STS(name, stop, op, type) \
8749 GEN_ST(name, stop, op | 0x20, type) \
8750 GEN_STU(name, stop, op | 0x21, type) \
8751 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8752 GEN_STX(name, stop, 0x17, op | 0x00, type)
8753
8754 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8755 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8756 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8757 #if defined(TARGET_PPC64)
8758 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8759 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8760 #endif
8761 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8762 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8763
8764 #undef GEN_LDF
8765 #undef GEN_LDUF
8766 #undef GEN_LDUXF
8767 #undef GEN_LDXF
8768 #undef GEN_LDFS
8769 #define GEN_LDF(name, ldop, opc, type) \
8770 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8771 #define GEN_LDUF(name, ldop, opc, type) \
8772 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8773 #define GEN_LDUXF(name, ldop, opc, type) \
8774 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8775 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8776 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8777 #define GEN_LDFS(name, ldop, op, type) \
8778 GEN_LDF(name, ldop, op | 0x20, type) \
8779 GEN_LDUF(name, ldop, op | 0x21, type) \
8780 GEN_LDUXF(name, ldop, op | 0x01, type) \
8781 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8782
8783 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8784 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8785
8786 #undef GEN_STF
8787 #undef GEN_STUF
8788 #undef GEN_STUXF
8789 #undef GEN_STXF
8790 #undef GEN_STFS
8791 #define GEN_STF(name, stop, opc, type) \
8792 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8793 #define GEN_STUF(name, stop, opc, type) \
8794 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8795 #define GEN_STUXF(name, stop, opc, type) \
8796 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8797 #define GEN_STXF(name, stop, opc2, opc3, type) \
8798 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8799 #define GEN_STFS(name, stop, op, type) \
8800 GEN_STF(name, stop, op | 0x20, type) \
8801 GEN_STUF(name, stop, op | 0x21, type) \
8802 GEN_STUXF(name, stop, op | 0x01, type) \
8803 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8804
8805 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8806 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8807 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8808
8809 #undef GEN_CRLOGIC
8810 #define GEN_CRLOGIC(name, tcg_op, opc) \
8811 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8812 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8813 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8814 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8815 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8816 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8817 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8818 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8819 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8820
8821 #undef GEN_MAC_HANDLER
8822 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8823 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8824 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8825 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8826 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8827 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8828 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8829 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8830 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8831 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8832 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8833 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8834 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8835 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8836 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8837 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8838 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8839 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8840 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8841 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8842 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8843 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8844 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8845 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8846 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8847 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8848 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8849 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8850 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8851 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8852 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8853 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8854 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8855 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
8856 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
8857 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
8858 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
8859 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
8860 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
8861 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
8862 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
8863 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
8864 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
8865 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
8866
8867 #undef GEN_VR_LDX
8868 #undef GEN_VR_STX
8869 #undef GEN_VR_LVE
8870 #undef GEN_VR_STVE
8871 #define GEN_VR_LDX(name, opc2, opc3) \
8872 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8873 #define GEN_VR_STX(name, opc2, opc3) \
8874 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8875 #define GEN_VR_LVE(name, opc2, opc3) \
8876 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8877 #define GEN_VR_STVE(name, opc2, opc3) \
8878 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8879 GEN_VR_LDX(lvx, 0x07, 0x03),
8880 GEN_VR_LDX(lvxl, 0x07, 0x0B),
8881 GEN_VR_LVE(bx, 0x07, 0x00),
8882 GEN_VR_LVE(hx, 0x07, 0x01),
8883 GEN_VR_LVE(wx, 0x07, 0x02),
8884 GEN_VR_STX(svx, 0x07, 0x07),
8885 GEN_VR_STX(svxl, 0x07, 0x0F),
8886 GEN_VR_STVE(bx, 0x07, 0x04),
8887 GEN_VR_STVE(hx, 0x07, 0x05),
8888 GEN_VR_STVE(wx, 0x07, 0x06),
8889
8890 #undef GEN_VX_LOGICAL
8891 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
8892 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8893 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
8894 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
8895 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
8896 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
8897 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
8898
8899 #undef GEN_VXFORM
8900 #define GEN_VXFORM(name, opc2, opc3) \
8901 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8902 GEN_VXFORM(vaddubm, 0, 0),
8903 GEN_VXFORM(vadduhm, 0, 1),
8904 GEN_VXFORM(vadduwm, 0, 2),
8905 GEN_VXFORM(vsububm, 0, 16),
8906 GEN_VXFORM(vsubuhm, 0, 17),
8907 GEN_VXFORM(vsubuwm, 0, 18),
8908 GEN_VXFORM(vmaxub, 1, 0),
8909 GEN_VXFORM(vmaxuh, 1, 1),
8910 GEN_VXFORM(vmaxuw, 1, 2),
8911 GEN_VXFORM(vmaxsb, 1, 4),
8912 GEN_VXFORM(vmaxsh, 1, 5),
8913 GEN_VXFORM(vmaxsw, 1, 6),
8914 GEN_VXFORM(vminub, 1, 8),
8915 GEN_VXFORM(vminuh, 1, 9),
8916 GEN_VXFORM(vminuw, 1, 10),
8917 GEN_VXFORM(vminsb, 1, 12),
8918 GEN_VXFORM(vminsh, 1, 13),
8919 GEN_VXFORM(vminsw, 1, 14),
8920 GEN_VXFORM(vavgub, 1, 16),
8921 GEN_VXFORM(vavguh, 1, 17),
8922 GEN_VXFORM(vavguw, 1, 18),
8923 GEN_VXFORM(vavgsb, 1, 20),
8924 GEN_VXFORM(vavgsh, 1, 21),
8925 GEN_VXFORM(vavgsw, 1, 22),
8926 GEN_VXFORM(vmrghb, 6, 0),
8927 GEN_VXFORM(vmrghh, 6, 1),
8928 GEN_VXFORM(vmrghw, 6, 2),
8929 GEN_VXFORM(vmrglb, 6, 4),
8930 GEN_VXFORM(vmrglh, 6, 5),
8931 GEN_VXFORM(vmrglw, 6, 6),
8932 GEN_VXFORM(vmuloub, 4, 0),
8933 GEN_VXFORM(vmulouh, 4, 1),
8934 GEN_VXFORM(vmulosb, 4, 4),
8935 GEN_VXFORM(vmulosh, 4, 5),
8936 GEN_VXFORM(vmuleub, 4, 8),
8937 GEN_VXFORM(vmuleuh, 4, 9),
8938 GEN_VXFORM(vmulesb, 4, 12),
8939 GEN_VXFORM(vmulesh, 4, 13),
8940 GEN_VXFORM(vslb, 2, 4),
8941 GEN_VXFORM(vslh, 2, 5),
8942 GEN_VXFORM(vslw, 2, 6),
8943 GEN_VXFORM(vsrb, 2, 8),
8944 GEN_VXFORM(vsrh, 2, 9),
8945 GEN_VXFORM(vsrw, 2, 10),
8946 GEN_VXFORM(vsrab, 2, 12),
8947 GEN_VXFORM(vsrah, 2, 13),
8948 GEN_VXFORM(vsraw, 2, 14),
8949 GEN_VXFORM(vslo, 6, 16),
8950 GEN_VXFORM(vsro, 6, 17),
8951 GEN_VXFORM(vaddcuw, 0, 6),
8952 GEN_VXFORM(vsubcuw, 0, 22),
8953 GEN_VXFORM(vaddubs, 0, 8),
8954 GEN_VXFORM(vadduhs, 0, 9),
8955 GEN_VXFORM(vadduws, 0, 10),
8956 GEN_VXFORM(vaddsbs, 0, 12),
8957 GEN_VXFORM(vaddshs, 0, 13),
8958 GEN_VXFORM(vaddsws, 0, 14),
8959 GEN_VXFORM(vsububs, 0, 24),
8960 GEN_VXFORM(vsubuhs, 0, 25),
8961 GEN_VXFORM(vsubuws, 0, 26),
8962 GEN_VXFORM(vsubsbs, 0, 28),
8963 GEN_VXFORM(vsubshs, 0, 29),
8964 GEN_VXFORM(vsubsws, 0, 30),
8965 GEN_VXFORM(vrlb, 2, 0),
8966 GEN_VXFORM(vrlh, 2, 1),
8967 GEN_VXFORM(vrlw, 2, 2),
8968 GEN_VXFORM(vsl, 2, 7),
8969 GEN_VXFORM(vsr, 2, 11),
8970 GEN_VXFORM(vpkuhum, 7, 0),
8971 GEN_VXFORM(vpkuwum, 7, 1),
8972 GEN_VXFORM(vpkuhus, 7, 2),
8973 GEN_VXFORM(vpkuwus, 7, 3),
8974 GEN_VXFORM(vpkshus, 7, 4),
8975 GEN_VXFORM(vpkswus, 7, 5),
8976 GEN_VXFORM(vpkshss, 7, 6),
8977 GEN_VXFORM(vpkswss, 7, 7),
8978 GEN_VXFORM(vpkpx, 7, 12),
8979 GEN_VXFORM(vsum4ubs, 4, 24),
8980 GEN_VXFORM(vsum4sbs, 4, 28),
8981 GEN_VXFORM(vsum4shs, 4, 25),
8982 GEN_VXFORM(vsum2sws, 4, 26),
8983 GEN_VXFORM(vsumsws, 4, 30),
8984 GEN_VXFORM(vaddfp, 5, 0),
8985 GEN_VXFORM(vsubfp, 5, 1),
8986 GEN_VXFORM(vmaxfp, 5, 16),
8987 GEN_VXFORM(vminfp, 5, 17),
8988
8989 #undef GEN_VXRFORM1
8990 #undef GEN_VXRFORM
8991 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
8992 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
8993 #define GEN_VXRFORM(name, opc2, opc3) \
8994 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
8995 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
8996 GEN_VXRFORM(vcmpequb, 3, 0)
8997 GEN_VXRFORM(vcmpequh, 3, 1)
8998 GEN_VXRFORM(vcmpequw, 3, 2)
8999 GEN_VXRFORM(vcmpgtsb, 3, 12)
9000 GEN_VXRFORM(vcmpgtsh, 3, 13)
9001 GEN_VXRFORM(vcmpgtsw, 3, 14)
9002 GEN_VXRFORM(vcmpgtub, 3, 8)
9003 GEN_VXRFORM(vcmpgtuh, 3, 9)
9004 GEN_VXRFORM(vcmpgtuw, 3, 10)
9005 GEN_VXRFORM(vcmpeqfp, 3, 3)
9006 GEN_VXRFORM(vcmpgefp, 3, 7)
9007 GEN_VXRFORM(vcmpgtfp, 3, 11)
9008 GEN_VXRFORM(vcmpbfp, 3, 15)
9009
9010 #undef GEN_VXFORM_SIMM
9011 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9012 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9013 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9014 GEN_VXFORM_SIMM(vspltish, 6, 13),
9015 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9016
9017 #undef GEN_VXFORM_NOA
9018 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9019 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9020 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9021 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9022 GEN_VXFORM_NOA(vupklsb, 7, 10),
9023 GEN_VXFORM_NOA(vupklsh, 7, 11),
9024 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9025 GEN_VXFORM_NOA(vupklpx, 7, 15),
9026 GEN_VXFORM_NOA(vrefp, 5, 4),
9027 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9028 GEN_VXFORM_NOA(vexptefp, 5, 6),
9029 GEN_VXFORM_NOA(vlogefp, 5, 7),
9030 GEN_VXFORM_NOA(vrfim, 5, 8),
9031 GEN_VXFORM_NOA(vrfin, 5, 9),
9032 GEN_VXFORM_NOA(vrfip, 5, 10),
9033 GEN_VXFORM_NOA(vrfiz, 5, 11),
9034
9035 #undef GEN_VXFORM_UIMM
9036 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9037 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9038 GEN_VXFORM_UIMM(vspltb, 6, 8),
9039 GEN_VXFORM_UIMM(vsplth, 6, 9),
9040 GEN_VXFORM_UIMM(vspltw, 6, 10),
9041 GEN_VXFORM_UIMM(vcfux, 5, 12),
9042 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9043 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9044 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9045
9046 #undef GEN_VAFORM_PAIRED
9047 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9048 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9049 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9050 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9051 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9052 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9053 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9054 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9055
9056 #undef GEN_SPE
9057 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
9058 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type)
9059 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE),
9060 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE),
9061 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE),
9062 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE),
9063 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE),
9064 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE),
9065 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE),
9066 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE),
9067 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, PPC_SPE),
9068 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE),
9069 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE),
9070 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE),
9071 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE),
9072 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE),
9073 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE),
9074 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE),
9075 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE),
9076 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE),
9077 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE),
9078 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE),
9079 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE),
9080 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE),
9081 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE),
9082 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE),
9083 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE),
9084 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE),
9085 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE),
9086 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE),
9087 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE),
9088
9089 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE),
9090 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE),
9091 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE),
9092 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE),
9093 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE),
9094 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE),
9095 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE),
9096 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE),
9097 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE),
9098 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE),
9099 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE),
9100 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE),
9101 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE),
9102 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE),
9103
9104 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE),
9105 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE),
9106 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE),
9107 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE),
9108 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE),
9109 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE),
9110 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE),
9111 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE),
9112 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE),
9113 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE),
9114 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE),
9115 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE),
9116 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE),
9117 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE),
9118
9119 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE),
9120 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9121 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE),
9122 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE),
9123 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE),
9124 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9125 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
9126 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
9127 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9128 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9129 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9130 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9131 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9132 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
9133 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
9134 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
9135
9136 #undef GEN_SPEOP_LDST
9137 #define GEN_SPEOP_LDST(name, opc2, sh) \
9138 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9139 GEN_SPEOP_LDST(evldd, 0x00, 3),
9140 GEN_SPEOP_LDST(evldw, 0x01, 3),
9141 GEN_SPEOP_LDST(evldh, 0x02, 3),
9142 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9143 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9144 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9145 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9146 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9147 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9148 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9149 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9150
9151 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9152 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9153 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9154 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9155 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9156 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9157 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9158 };
9159
9160 #include "translate_init.c"
9161 #include "helper_regs.h"
9162
9163 /*****************************************************************************/
9164 /* Misc PowerPC helpers */
9165 void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
9166 int flags)
9167 {
9168 #define RGPL 4
9169 #define RFPL 4
9170
9171 int i;
9172
9173 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9174 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9175 env->nip, env->lr, env->ctr, env->xer);
9176 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9177 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9178 env->hflags, env->mmu_idx);
9179 #if !defined(NO_TIMER_DUMP)
9180 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9181 #if !defined(CONFIG_USER_ONLY)
9182 " DECR %08" PRIu32
9183 #endif
9184 "\n",
9185 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9186 #if !defined(CONFIG_USER_ONLY)
9187 , cpu_ppc_load_decr(env)
9188 #endif
9189 );
9190 #endif
9191 for (i = 0; i < 32; i++) {
9192 if ((i & (RGPL - 1)) == 0)
9193 cpu_fprintf(f, "GPR%02d", i);
9194 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9195 if ((i & (RGPL - 1)) == (RGPL - 1))
9196 cpu_fprintf(f, "\n");
9197 }
9198 cpu_fprintf(f, "CR ");
9199 for (i = 0; i < 8; i++)
9200 cpu_fprintf(f, "%01x", env->crf[i]);
9201 cpu_fprintf(f, " [");
9202 for (i = 0; i < 8; i++) {
9203 char a = '-';
9204 if (env->crf[i] & 0x08)
9205 a = 'L';
9206 else if (env->crf[i] & 0x04)
9207 a = 'G';
9208 else if (env->crf[i] & 0x02)
9209 a = 'E';
9210 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9211 }
9212 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9213 env->reserve_addr);
9214 for (i = 0; i < 32; i++) {
9215 if ((i & (RFPL - 1)) == 0)
9216 cpu_fprintf(f, "FPR%02d", i);
9217 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9218 if ((i & (RFPL - 1)) == (RFPL - 1))
9219 cpu_fprintf(f, "\n");
9220 }
9221 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
9222 #if !defined(CONFIG_USER_ONLY)
9223 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9224 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9225 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9226 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9227
9228 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9229 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9230 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9231 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9232
9233 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9234 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9235 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9236 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9237
9238 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9239 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9240 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9241 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9242 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9243
9244 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9245 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9246 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9247 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9248
9249 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9250 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9251 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9252 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9253
9254 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9255 " EPR " TARGET_FMT_lx "\n",
9256 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9257 env->spr[SPR_BOOKE_EPR]);
9258
9259 /* FSL-specific */
9260 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9261 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9262 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9263 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9264
9265 /*
9266 * IVORs are left out as they are large and do not change often --
9267 * they can be read with "p $ivor0", "p $ivor1", etc.
9268 */
9269 }
9270
9271 switch (env->mmu_model) {
9272 case POWERPC_MMU_32B:
9273 case POWERPC_MMU_601:
9274 case POWERPC_MMU_SOFT_6xx:
9275 case POWERPC_MMU_SOFT_74xx:
9276 #if defined(TARGET_PPC64)
9277 case POWERPC_MMU_620:
9278 case POWERPC_MMU_64B:
9279 #endif
9280 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9281 break;
9282 case POWERPC_MMU_BOOKE206:
9283 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9284 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9285 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9286 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9287
9288 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9289 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9290 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9291 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9292
9293 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9294 " TLB1CFG " TARGET_FMT_lx "\n",
9295 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9296 env->spr[SPR_BOOKE_TLB1CFG]);
9297 break;
9298 default:
9299 break;
9300 }
9301 #endif
9302
9303 #undef RGPL
9304 #undef RFPL
9305 }
9306
9307 void cpu_dump_statistics (CPUState *env, FILE*f, fprintf_function cpu_fprintf,
9308 int flags)
9309 {
9310 #if defined(DO_PPC_STATISTICS)
9311 opc_handler_t **t1, **t2, **t3, *handler;
9312 int op1, op2, op3;
9313
9314 t1 = env->opcodes;
9315 for (op1 = 0; op1 < 64; op1++) {
9316 handler = t1[op1];
9317 if (is_indirect_opcode(handler)) {
9318 t2 = ind_table(handler);
9319 for (op2 = 0; op2 < 32; op2++) {
9320 handler = t2[op2];
9321 if (is_indirect_opcode(handler)) {
9322 t3 = ind_table(handler);
9323 for (op3 = 0; op3 < 32; op3++) {
9324 handler = t3[op3];
9325 if (handler->count == 0)
9326 continue;
9327 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9328 "%016" PRIx64 " %" PRId64 "\n",
9329 op1, op2, op3, op1, (op3 << 5) | op2,
9330 handler->oname,
9331 handler->count, handler->count);
9332 }
9333 } else {
9334 if (handler->count == 0)
9335 continue;
9336 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9337 "%016" PRIx64 " %" PRId64 "\n",
9338 op1, op2, op1, op2, handler->oname,
9339 handler->count, handler->count);
9340 }
9341 }
9342 } else {
9343 if (handler->count == 0)
9344 continue;
9345 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9346 " %" PRId64 "\n",
9347 op1, op1, handler->oname,
9348 handler->count, handler->count);
9349 }
9350 }
9351 #endif
9352 }
9353
9354 /*****************************************************************************/
9355 static inline void gen_intermediate_code_internal(CPUState *env,
9356 TranslationBlock *tb,
9357 int search_pc)
9358 {
9359 DisasContext ctx, *ctxp = &ctx;
9360 opc_handler_t **table, *handler;
9361 target_ulong pc_start;
9362 uint16_t *gen_opc_end;
9363 CPUBreakpoint *bp;
9364 int j, lj = -1;
9365 int num_insns;
9366 int max_insns;
9367
9368 pc_start = tb->pc;
9369 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9370 ctx.nip = pc_start;
9371 ctx.tb = tb;
9372 ctx.exception = POWERPC_EXCP_NONE;
9373 ctx.spr_cb = env->spr_cb;
9374 ctx.mem_idx = env->mmu_idx;
9375 ctx.access_type = -1;
9376 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9377 #if defined(TARGET_PPC64)
9378 ctx.sf_mode = msr_sf;
9379 #endif
9380 ctx.fpu_enabled = msr_fp;
9381 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9382 ctx.spe_enabled = msr_spe;
9383 else
9384 ctx.spe_enabled = 0;
9385 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9386 ctx.altivec_enabled = msr_vr;
9387 else
9388 ctx.altivec_enabled = 0;
9389 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9390 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9391 else
9392 ctx.singlestep_enabled = 0;
9393 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9394 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9395 if (unlikely(env->singlestep_enabled))
9396 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9397 #if defined (DO_SINGLE_STEP) && 0
9398 /* Single step trace mode */
9399 msr_se = 1;
9400 #endif
9401 num_insns = 0;
9402 max_insns = tb->cflags & CF_COUNT_MASK;
9403 if (max_insns == 0)
9404 max_insns = CF_COUNT_MASK;
9405
9406 gen_icount_start();
9407 /* Set env in case of segfault during code fetch */
9408 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
9409 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9410 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9411 if (bp->pc == ctx.nip) {
9412 gen_debug_exception(ctxp);
9413 break;
9414 }
9415 }
9416 }
9417 if (unlikely(search_pc)) {
9418 j = gen_opc_ptr - gen_opc_buf;
9419 if (lj < j) {
9420 lj++;
9421 while (lj < j)
9422 gen_opc_instr_start[lj++] = 0;
9423 }
9424 gen_opc_pc[lj] = ctx.nip;
9425 gen_opc_instr_start[lj] = 1;
9426 gen_opc_icount[lj] = num_insns;
9427 }
9428 LOG_DISAS("----------------\n");
9429 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9430 ctx.nip, ctx.mem_idx, (int)msr_ir);
9431 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9432 gen_io_start();
9433 if (unlikely(ctx.le_mode)) {
9434 ctx.opcode = bswap32(ldl_code(ctx.nip));
9435 } else {
9436 ctx.opcode = ldl_code(ctx.nip);
9437 }
9438 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9439 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9440 opc3(ctx.opcode), little_endian ? "little" : "big");
9441 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
9442 tcg_gen_debug_insn_start(ctx.nip);
9443 ctx.nip += 4;
9444 table = env->opcodes;
9445 num_insns++;
9446 handler = table[opc1(ctx.opcode)];
9447 if (is_indirect_opcode(handler)) {
9448 table = ind_table(handler);
9449 handler = table[opc2(ctx.opcode)];
9450 if (is_indirect_opcode(handler)) {
9451 table = ind_table(handler);
9452 handler = table[opc3(ctx.opcode)];
9453 }
9454 }
9455 /* Is opcode *REALLY* valid ? */
9456 if (unlikely(handler->handler == &gen_invalid)) {
9457 if (qemu_log_enabled()) {
9458 qemu_log("invalid/unsupported opcode: "
9459 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9460 opc1(ctx.opcode), opc2(ctx.opcode),
9461 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9462 }
9463 } else {
9464 if (unlikely((ctx.opcode & handler->inval) != 0)) {
9465 if (qemu_log_enabled()) {
9466 qemu_log("invalid bits: %08x for opcode: "
9467 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9468 ctx.opcode & handler->inval, opc1(ctx.opcode),
9469 opc2(ctx.opcode), opc3(ctx.opcode),
9470 ctx.opcode, ctx.nip - 4);
9471 }
9472 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9473 break;
9474 }
9475 }
9476 (*(handler->handler))(&ctx);
9477 #if defined(DO_PPC_STATISTICS)
9478 handler->count++;
9479 #endif
9480 /* Check trace mode exceptions */
9481 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9482 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9483 ctx.exception != POWERPC_SYSCALL &&
9484 ctx.exception != POWERPC_EXCP_TRAP &&
9485 ctx.exception != POWERPC_EXCP_BRANCH)) {
9486 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9487 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9488 (env->singlestep_enabled) ||
9489 singlestep ||
9490 num_insns >= max_insns)) {
9491 /* if we reach a page boundary or are single stepping, stop
9492 * generation
9493 */
9494 break;
9495 }
9496 }
9497 if (tb->cflags & CF_LAST_IO)
9498 gen_io_end();
9499 if (ctx.exception == POWERPC_EXCP_NONE) {
9500 gen_goto_tb(&ctx, 0, ctx.nip);
9501 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9502 if (unlikely(env->singlestep_enabled)) {
9503 gen_debug_exception(ctxp);
9504 }
9505 /* Generate the return instruction */
9506 tcg_gen_exit_tb(0);
9507 }
9508 gen_icount_end(tb, num_insns);
9509 *gen_opc_ptr = INDEX_op_end;
9510 if (unlikely(search_pc)) {
9511 j = gen_opc_ptr - gen_opc_buf;
9512 lj++;
9513 while (lj <= j)
9514 gen_opc_instr_start[lj++] = 0;
9515 } else {
9516 tb->size = ctx.nip - pc_start;
9517 tb->icount = num_insns;
9518 }
9519 #if defined(DEBUG_DISAS)
9520 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9521 int flags;
9522 flags = env->bfd_mach;
9523 flags |= ctx.le_mode << 16;
9524 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9525 log_target_disas(pc_start, ctx.nip - pc_start, flags);
9526 qemu_log("\n");
9527 }
9528 #endif
9529 }
9530
9531 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
9532 {
9533 gen_intermediate_code_internal(env, tb, 0);
9534 }
9535
9536 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
9537 {
9538 gen_intermediate_code_internal(env, tb, 1);
9539 }
9540
9541 void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
9542 {
9543 env->nip = gen_opc_pc[pc_pos];
9544 }
Qemu copy for testing