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target-ppc: emulate prtyw and prtyd instructions
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 /* True when active word size < size of target_long. */
208 #ifdef TARGET_PPC64
209 # define NARROW_MODE(C) (!(C)->sf_mode)
210 #else
211 # define NARROW_MODE(C) 0
212 #endif
213
214 struct opc_handler_t {
215 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
216 uint32_t inval1;
217 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
218 uint32_t inval2;
219 /* instruction type */
220 uint64_t type;
221 /* extended instruction type */
222 uint64_t type2;
223 /* handler */
224 void (*handler)(DisasContext *ctx);
225 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
226 const char *oname;
227 #endif
228 #if defined(DO_PPC_STATISTICS)
229 uint64_t count;
230 #endif
231 };
232
233 static inline void gen_reset_fpstatus(void)
234 {
235 gen_helper_reset_fpstatus(cpu_env);
236 }
237
238 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
239 {
240 TCGv_i32 t0 = tcg_temp_new_i32();
241
242 if (set_fprf != 0) {
243 /* This case might be optimized later */
244 tcg_gen_movi_i32(t0, 1);
245 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
246 if (unlikely(set_rc)) {
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249 gen_helper_float_check_status(cpu_env);
250 } else if (unlikely(set_rc)) {
251 /* We always need to compute fpcc */
252 tcg_gen_movi_i32(t0, 0);
253 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
254 tcg_gen_mov_i32(cpu_crf[1], t0);
255 }
256
257 tcg_temp_free_i32(t0);
258 }
259
260 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
261 {
262 if (ctx->access_type != access_type) {
263 tcg_gen_movi_i32(cpu_access_type, access_type);
264 ctx->access_type = access_type;
265 }
266 }
267
268 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
269 {
270 if (NARROW_MODE(ctx)) {
271 nip = (uint32_t)nip;
272 }
273 tcg_gen_movi_tl(cpu_nip, nip);
274 }
275
276 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
277 {
278 TCGv_i32 t0, t1;
279 if (ctx->exception == POWERPC_EXCP_NONE) {
280 gen_update_nip(ctx, ctx->nip);
281 }
282 t0 = tcg_const_i32(excp);
283 t1 = tcg_const_i32(error);
284 gen_helper_raise_exception_err(cpu_env, t0, t1);
285 tcg_temp_free_i32(t0);
286 tcg_temp_free_i32(t1);
287 ctx->exception = (excp);
288 }
289
290 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
291 {
292 TCGv_i32 t0;
293 if (ctx->exception == POWERPC_EXCP_NONE) {
294 gen_update_nip(ctx, ctx->nip);
295 }
296 t0 = tcg_const_i32(excp);
297 gen_helper_raise_exception(cpu_env, t0);
298 tcg_temp_free_i32(t0);
299 ctx->exception = (excp);
300 }
301
302 static inline void gen_debug_exception(DisasContext *ctx)
303 {
304 TCGv_i32 t0;
305
306 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
307 (ctx->exception != POWERPC_EXCP_SYNC)) {
308 gen_update_nip(ctx, ctx->nip);
309 }
310 t0 = tcg_const_i32(EXCP_DEBUG);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 }
314
315 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
316 {
317 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
318 }
319
320 /* Stop translation */
321 static inline void gen_stop_exception(DisasContext *ctx)
322 {
323 gen_update_nip(ctx, ctx->nip);
324 ctx->exception = POWERPC_EXCP_STOP;
325 }
326
327 /* No need to update nip here, as execution flow will change */
328 static inline void gen_sync_exception(DisasContext *ctx)
329 {
330 ctx->exception = POWERPC_EXCP_SYNC;
331 }
332
333 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
334 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
335
336 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
337 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
338
339 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
344
345 typedef struct opcode_t {
346 unsigned char opc1, opc2, opc3;
347 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
348 unsigned char pad[5];
349 #else
350 unsigned char pad[1];
351 #endif
352 opc_handler_t handler;
353 const char *oname;
354 } opcode_t;
355
356 /*****************************************************************************/
357 /*** Instruction decoding ***/
358 #define EXTRACT_HELPER(name, shift, nb) \
359 static inline uint32_t name(uint32_t opcode) \
360 { \
361 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
362 }
363
364 #define EXTRACT_SHELPER(name, shift, nb) \
365 static inline int32_t name(uint32_t opcode) \
366 { \
367 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
368 }
369
370 /* Opcode part 1 */
371 EXTRACT_HELPER(opc1, 26, 6);
372 /* Opcode part 2 */
373 EXTRACT_HELPER(opc2, 1, 5);
374 /* Opcode part 3 */
375 EXTRACT_HELPER(opc3, 6, 5);
376 /* Update Cr0 flags */
377 EXTRACT_HELPER(Rc, 0, 1);
378 /* Destination */
379 EXTRACT_HELPER(rD, 21, 5);
380 /* Source */
381 EXTRACT_HELPER(rS, 21, 5);
382 /* First operand */
383 EXTRACT_HELPER(rA, 16, 5);
384 /* Second operand */
385 EXTRACT_HELPER(rB, 11, 5);
386 /* Third operand */
387 EXTRACT_HELPER(rC, 6, 5);
388 /*** Get CRn ***/
389 EXTRACT_HELPER(crfD, 23, 3);
390 EXTRACT_HELPER(crfS, 18, 3);
391 EXTRACT_HELPER(crbD, 21, 5);
392 EXTRACT_HELPER(crbA, 16, 5);
393 EXTRACT_HELPER(crbB, 11, 5);
394 /* SPR / TBL */
395 EXTRACT_HELPER(_SPR, 11, 10);
396 static inline uint32_t SPR(uint32_t opcode)
397 {
398 uint32_t sprn = _SPR(opcode);
399
400 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
401 }
402 /*** Get constants ***/
403 EXTRACT_HELPER(IMM, 12, 8);
404 /* 16 bits signed immediate value */
405 EXTRACT_SHELPER(SIMM, 0, 16);
406 /* 16 bits unsigned immediate value */
407 EXTRACT_HELPER(UIMM, 0, 16);
408 /* 5 bits signed immediate value */
409 EXTRACT_HELPER(SIMM5, 16, 5);
410 /* 5 bits signed immediate value */
411 EXTRACT_HELPER(UIMM5, 16, 5);
412 /* Bit count */
413 EXTRACT_HELPER(NB, 11, 5);
414 /* Shift count */
415 EXTRACT_HELPER(SH, 11, 5);
416 /* Vector shift count */
417 EXTRACT_HELPER(VSH, 6, 4);
418 /* Mask start */
419 EXTRACT_HELPER(MB, 6, 5);
420 /* Mask end */
421 EXTRACT_HELPER(ME, 1, 5);
422 /* Trap operand */
423 EXTRACT_HELPER(TO, 21, 5);
424
425 EXTRACT_HELPER(CRM, 12, 8);
426 EXTRACT_HELPER(FM, 17, 8);
427 EXTRACT_HELPER(SR, 16, 4);
428 EXTRACT_HELPER(FPIMM, 12, 4);
429
430 /*** Jump target decoding ***/
431 /* Displacement */
432 EXTRACT_SHELPER(d, 0, 16);
433 /* Immediate address */
434 static inline target_ulong LI(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0x03FFFFFC;
437 }
438
439 static inline uint32_t BD(uint32_t opcode)
440 {
441 return (opcode >> 0) & 0xFFFC;
442 }
443
444 EXTRACT_HELPER(BO, 21, 5);
445 EXTRACT_HELPER(BI, 16, 5);
446 /* Absolute/relative address */
447 EXTRACT_HELPER(AA, 1, 1);
448 /* Link */
449 EXTRACT_HELPER(LK, 0, 1);
450
451 /* Create a mask between <start> and <end> bits */
452 static inline target_ulong MASK(uint32_t start, uint32_t end)
453 {
454 target_ulong ret;
455
456 #if defined(TARGET_PPC64)
457 if (likely(start == 0)) {
458 ret = UINT64_MAX << (63 - end);
459 } else if (likely(end == 63)) {
460 ret = UINT64_MAX >> start;
461 }
462 #else
463 if (likely(start == 0)) {
464 ret = UINT32_MAX << (31 - end);
465 } else if (likely(end == 31)) {
466 ret = UINT32_MAX >> start;
467 }
468 #endif
469 else {
470 ret = (((target_ulong)(-1ULL)) >> (start)) ^
471 (((target_ulong)(-1ULL) >> (end)) >> 1);
472 if (unlikely(start > end))
473 return ~ret;
474 }
475
476 return ret;
477 }
478
479 /*****************************************************************************/
480 /* PowerPC instructions table */
481
482 #if defined(DO_PPC_STATISTICS)
483 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
484 { \
485 .opc1 = op1, \
486 .opc2 = op2, \
487 .opc3 = op3, \
488 .pad = { 0, }, \
489 .handler = { \
490 .inval1 = invl, \
491 .type = _typ, \
492 .type2 = _typ2, \
493 .handler = &gen_##name, \
494 .oname = stringify(name), \
495 }, \
496 .oname = stringify(name), \
497 }
498 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
499 { \
500 .opc1 = op1, \
501 .opc2 = op2, \
502 .opc3 = op3, \
503 .pad = { 0, }, \
504 .handler = { \
505 .inval1 = invl1, \
506 .inval2 = invl2, \
507 .type = _typ, \
508 .type2 = _typ2, \
509 .handler = &gen_##name, \
510 .oname = stringify(name), \
511 }, \
512 .oname = stringify(name), \
513 }
514 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
515 { \
516 .opc1 = op1, \
517 .opc2 = op2, \
518 .opc3 = op3, \
519 .pad = { 0, }, \
520 .handler = { \
521 .inval1 = invl, \
522 .type = _typ, \
523 .type2 = _typ2, \
524 .handler = &gen_##name, \
525 .oname = onam, \
526 }, \
527 .oname = onam, \
528 }
529 #else
530 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
531 { \
532 .opc1 = op1, \
533 .opc2 = op2, \
534 .opc3 = op3, \
535 .pad = { 0, }, \
536 .handler = { \
537 .inval1 = invl, \
538 .type = _typ, \
539 .type2 = _typ2, \
540 .handler = &gen_##name, \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .pad = { 0, }, \
550 .handler = { \
551 .inval1 = invl1, \
552 .inval2 = invl2, \
553 .type = _typ, \
554 .type2 = _typ2, \
555 .handler = &gen_##name, \
556 }, \
557 .oname = stringify(name), \
558 }
559 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
560 { \
561 .opc1 = op1, \
562 .opc2 = op2, \
563 .opc3 = op3, \
564 .pad = { 0, }, \
565 .handler = { \
566 .inval1 = invl, \
567 .type = _typ, \
568 .type2 = _typ2, \
569 .handler = &gen_##name, \
570 }, \
571 .oname = onam, \
572 }
573 #endif
574
575 /* SPR load/store helpers */
576 static inline void gen_load_spr(TCGv t, int reg)
577 {
578 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 static inline void gen_store_spr(int reg, TCGv t)
582 {
583 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
584 }
585
586 /* Invalid instruction */
587 static void gen_invalid(DisasContext *ctx)
588 {
589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
590 }
591
592 static opc_handler_t invalid_handler = {
593 .inval1 = 0xFFFFFFFF,
594 .inval2 = 0xFFFFFFFF,
595 .type = PPC_NONE,
596 .type2 = PPC_NONE,
597 .handler = gen_invalid,
598 };
599
600 /*** Integer comparison ***/
601
602 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
603 {
604 TCGv t0 = tcg_temp_new();
605 TCGv_i32 t1 = tcg_temp_new_i32();
606
607 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_LT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_GT);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
620 tcg_gen_trunc_tl_i32(t1, t0);
621 tcg_gen_shli_i32(t1, t1, CRF_EQ);
622 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
623
624 tcg_temp_free(t0);
625 tcg_temp_free_i32(t1);
626 }
627
628 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
629 {
630 TCGv t0 = tcg_const_tl(arg1);
631 gen_op_cmp(arg0, t0, s, crf);
632 tcg_temp_free(t0);
633 }
634
635 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
636 {
637 TCGv t0, t1;
638 t0 = tcg_temp_new();
639 t1 = tcg_temp_new();
640 if (s) {
641 tcg_gen_ext32s_tl(t0, arg0);
642 tcg_gen_ext32s_tl(t1, arg1);
643 } else {
644 tcg_gen_ext32u_tl(t0, arg0);
645 tcg_gen_ext32u_tl(t1, arg1);
646 }
647 gen_op_cmp(t0, t1, s, crf);
648 tcg_temp_free(t1);
649 tcg_temp_free(t0);
650 }
651
652 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
653 {
654 TCGv t0 = tcg_const_tl(arg1);
655 gen_op_cmp32(arg0, t0, s, crf);
656 tcg_temp_free(t0);
657 }
658
659 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
660 {
661 if (NARROW_MODE(ctx)) {
662 gen_op_cmpi32(reg, 0, 1, 0);
663 } else {
664 gen_op_cmpi(reg, 0, 1, 0);
665 }
666 }
667
668 /* cmp */
669 static void gen_cmp(DisasContext *ctx)
670 {
671 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
672 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
673 1, crfD(ctx->opcode));
674 } else {
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678 }
679
680 /* cmpi */
681 static void gen_cmpi(DisasContext *ctx)
682 {
683 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 } else {
687 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
688 1, crfD(ctx->opcode));
689 }
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
696 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
697 0, crfD(ctx->opcode));
698 } else {
699 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
700 0, crfD(ctx->opcode));
701 }
702 }
703
704 /* cmpli */
705 static void gen_cmpli(DisasContext *ctx)
706 {
707 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
708 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
709 0, crfD(ctx->opcode));
710 } else {
711 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
712 0, crfD(ctx->opcode));
713 }
714 }
715
716 /* isel (PowerPC 2.03 specification) */
717 static void gen_isel(DisasContext *ctx)
718 {
719 int l1, l2;
720 uint32_t bi = rC(ctx->opcode);
721 uint32_t mask;
722 TCGv_i32 t0;
723
724 l1 = gen_new_label();
725 l2 = gen_new_label();
726
727 mask = 1 << (3 - (bi & 0x03));
728 t0 = tcg_temp_new_i32();
729 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
730 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
731 if (rA(ctx->opcode) == 0)
732 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
733 else
734 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
735 tcg_gen_br(l2);
736 gen_set_label(l1);
737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
738 gen_set_label(l2);
739 tcg_temp_free_i32(t0);
740 }
741
742 /* cmpb: PowerPC 2.05 specification */
743 static void gen_cmpb(DisasContext *ctx)
744 {
745 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
746 cpu_gpr[rB(ctx->opcode)]);
747 }
748
749 /*** Integer arithmetic ***/
750
751 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
752 TCGv arg1, TCGv arg2, int sub)
753 {
754 TCGv t0 = tcg_temp_new();
755
756 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
757 tcg_gen_xor_tl(t0, arg1, arg2);
758 if (sub) {
759 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
760 } else {
761 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
762 }
763 tcg_temp_free(t0);
764 if (NARROW_MODE(ctx)) {
765 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
766 }
767 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
768 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
769 }
770
771 /* Common add function */
772 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
773 TCGv arg2, bool add_ca, bool compute_ca,
774 bool compute_ov, bool compute_rc0)
775 {
776 TCGv t0 = ret;
777
778 if (compute_ca || compute_ov) {
779 t0 = tcg_temp_new();
780 }
781
782 if (compute_ca) {
783 if (NARROW_MODE(ctx)) {
784 /* Caution: a non-obvious corner case of the spec is that we
785 must produce the *entire* 64-bit addition, but produce the
786 carry into bit 32. */
787 TCGv t1 = tcg_temp_new();
788 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
789 tcg_gen_add_tl(t0, arg1, arg2);
790 if (add_ca) {
791 tcg_gen_add_tl(t0, t0, cpu_ca);
792 }
793 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
794 tcg_temp_free(t1);
795 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
796 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
797 } else {
798 TCGv zero = tcg_const_tl(0);
799 if (add_ca) {
800 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
801 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
802 } else {
803 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
804 }
805 tcg_temp_free(zero);
806 }
807 } else {
808 tcg_gen_add_tl(t0, arg1, arg2);
809 if (add_ca) {
810 tcg_gen_add_tl(t0, t0, cpu_ca);
811 }
812 }
813
814 if (compute_ov) {
815 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
816 }
817 if (unlikely(compute_rc0)) {
818 gen_set_Rc0(ctx, t0);
819 }
820
821 if (!TCGV_EQUAL(t0, ret)) {
822 tcg_gen_mov_tl(ret, t0);
823 tcg_temp_free(t0);
824 }
825 }
826 /* Add functions with two operands */
827 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
828 static void glue(gen_, name)(DisasContext *ctx) \
829 { \
830 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
831 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
832 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
833 }
834 /* Add functions with one operand and one immediate */
835 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
836 add_ca, compute_ca, compute_ov) \
837 static void glue(gen_, name)(DisasContext *ctx) \
838 { \
839 TCGv t0 = tcg_const_tl(const_val); \
840 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
841 cpu_gpr[rA(ctx->opcode)], t0, \
842 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
843 tcg_temp_free(t0); \
844 }
845
846 /* add add. addo addo. */
847 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
848 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
849 /* addc addc. addco addco. */
850 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
851 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
852 /* adde adde. addeo addeo. */
853 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
854 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
855 /* addme addme. addmeo addmeo. */
856 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
857 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
858 /* addze addze. addzeo addzeo.*/
859 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
860 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
861 /* addi */
862 static void gen_addi(DisasContext *ctx)
863 {
864 target_long simm = SIMM(ctx->opcode);
865
866 if (rA(ctx->opcode) == 0) {
867 /* li case */
868 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
869 } else {
870 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
871 cpu_gpr[rA(ctx->opcode)], simm);
872 }
873 }
874 /* addic addic.*/
875 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
876 {
877 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
878 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
879 c, 0, 1, 0, compute_rc0);
880 tcg_temp_free(c);
881 }
882
883 static void gen_addic(DisasContext *ctx)
884 {
885 gen_op_addic(ctx, 0);
886 }
887
888 static void gen_addic_(DisasContext *ctx)
889 {
890 gen_op_addic(ctx, 1);
891 }
892
893 /* addis */
894 static void gen_addis(DisasContext *ctx)
895 {
896 target_long simm = SIMM(ctx->opcode);
897
898 if (rA(ctx->opcode) == 0) {
899 /* lis case */
900 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
901 } else {
902 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
903 cpu_gpr[rA(ctx->opcode)], simm << 16);
904 }
905 }
906
907 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
908 TCGv arg2, int sign, int compute_ov)
909 {
910 int l1 = gen_new_label();
911 int l2 = gen_new_label();
912 TCGv_i32 t0 = tcg_temp_local_new_i32();
913 TCGv_i32 t1 = tcg_temp_local_new_i32();
914
915 tcg_gen_trunc_tl_i32(t0, arg1);
916 tcg_gen_trunc_tl_i32(t1, arg2);
917 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
918 if (sign) {
919 int l3 = gen_new_label();
920 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
921 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
922 gen_set_label(l3);
923 tcg_gen_div_i32(t0, t0, t1);
924 } else {
925 tcg_gen_divu_i32(t0, t0, t1);
926 }
927 if (compute_ov) {
928 tcg_gen_movi_tl(cpu_ov, 0);
929 }
930 tcg_gen_br(l2);
931 gen_set_label(l1);
932 if (sign) {
933 tcg_gen_sari_i32(t0, t0, 31);
934 } else {
935 tcg_gen_movi_i32(t0, 0);
936 }
937 if (compute_ov) {
938 tcg_gen_movi_tl(cpu_ov, 1);
939 tcg_gen_movi_tl(cpu_so, 1);
940 }
941 gen_set_label(l2);
942 tcg_gen_extu_i32_tl(ret, t0);
943 tcg_temp_free_i32(t0);
944 tcg_temp_free_i32(t1);
945 if (unlikely(Rc(ctx->opcode) != 0))
946 gen_set_Rc0(ctx, ret);
947 }
948 /* Div functions */
949 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
950 static void glue(gen_, name)(DisasContext *ctx) \
951 { \
952 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
953 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
954 sign, compute_ov); \
955 }
956 /* divwu divwu. divwuo divwuo. */
957 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
958 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
959 /* divw divw. divwo divwo. */
960 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
961 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
962 #if defined(TARGET_PPC64)
963 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
964 TCGv arg2, int sign, int compute_ov)
965 {
966 int l1 = gen_new_label();
967 int l2 = gen_new_label();
968
969 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
970 if (sign) {
971 int l3 = gen_new_label();
972 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
973 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
974 gen_set_label(l3);
975 tcg_gen_div_i64(ret, arg1, arg2);
976 } else {
977 tcg_gen_divu_i64(ret, arg1, arg2);
978 }
979 if (compute_ov) {
980 tcg_gen_movi_tl(cpu_ov, 0);
981 }
982 tcg_gen_br(l2);
983 gen_set_label(l1);
984 if (sign) {
985 tcg_gen_sari_i64(ret, arg1, 63);
986 } else {
987 tcg_gen_movi_i64(ret, 0);
988 }
989 if (compute_ov) {
990 tcg_gen_movi_tl(cpu_ov, 1);
991 tcg_gen_movi_tl(cpu_so, 1);
992 }
993 gen_set_label(l2);
994 if (unlikely(Rc(ctx->opcode) != 0))
995 gen_set_Rc0(ctx, ret);
996 }
997 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
998 static void glue(gen_, name)(DisasContext *ctx) \
999 { \
1000 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1001 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1002 sign, compute_ov); \
1003 }
1004 /* divwu divwu. divwuo divwuo. */
1005 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1006 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1007 /* divw divw. divwo divwo. */
1008 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1009 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1010 #endif
1011
1012 /* mulhw mulhw. */
1013 static void gen_mulhw(DisasContext *ctx)
1014 {
1015 TCGv_i32 t0 = tcg_temp_new_i32();
1016 TCGv_i32 t1 = tcg_temp_new_i32();
1017
1018 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1019 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1020 tcg_gen_muls2_i32(t0, t1, t0, t1);
1021 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1022 tcg_temp_free_i32(t0);
1023 tcg_temp_free_i32(t1);
1024 if (unlikely(Rc(ctx->opcode) != 0))
1025 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1026 }
1027
1028 /* mulhwu mulhwu. */
1029 static void gen_mulhwu(DisasContext *ctx)
1030 {
1031 TCGv_i32 t0 = tcg_temp_new_i32();
1032 TCGv_i32 t1 = tcg_temp_new_i32();
1033
1034 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1035 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1036 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1037 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1038 tcg_temp_free_i32(t0);
1039 tcg_temp_free_i32(t1);
1040 if (unlikely(Rc(ctx->opcode) != 0))
1041 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1042 }
1043
1044 /* mullw mullw. */
1045 static void gen_mullw(DisasContext *ctx)
1046 {
1047 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1048 cpu_gpr[rB(ctx->opcode)]);
1049 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1050 if (unlikely(Rc(ctx->opcode) != 0))
1051 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1052 }
1053
1054 /* mullwo mullwo. */
1055 static void gen_mullwo(DisasContext *ctx)
1056 {
1057 TCGv_i32 t0 = tcg_temp_new_i32();
1058 TCGv_i32 t1 = tcg_temp_new_i32();
1059
1060 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1061 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1062 tcg_gen_muls2_i32(t0, t1, t0, t1);
1063 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1064
1065 tcg_gen_sari_i32(t0, t0, 31);
1066 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1067 tcg_gen_extu_i32_tl(cpu_ov, t0);
1068 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1069
1070 tcg_temp_free_i32(t0);
1071 tcg_temp_free_i32(t1);
1072 if (unlikely(Rc(ctx->opcode) != 0))
1073 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1074 }
1075
1076 /* mulli */
1077 static void gen_mulli(DisasContext *ctx)
1078 {
1079 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1080 SIMM(ctx->opcode));
1081 }
1082
1083 #if defined(TARGET_PPC64)
1084 /* mulhd mulhd. */
1085 static void gen_mulhd(DisasContext *ctx)
1086 {
1087 TCGv lo = tcg_temp_new();
1088 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1089 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1090 tcg_temp_free(lo);
1091 if (unlikely(Rc(ctx->opcode) != 0)) {
1092 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1093 }
1094 }
1095
1096 /* mulhdu mulhdu. */
1097 static void gen_mulhdu(DisasContext *ctx)
1098 {
1099 TCGv lo = tcg_temp_new();
1100 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1101 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1102 tcg_temp_free(lo);
1103 if (unlikely(Rc(ctx->opcode) != 0)) {
1104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1105 }
1106 }
1107
1108 /* mulld mulld. */
1109 static void gen_mulld(DisasContext *ctx)
1110 {
1111 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1112 cpu_gpr[rB(ctx->opcode)]);
1113 if (unlikely(Rc(ctx->opcode) != 0))
1114 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1115 }
1116
1117 /* mulldo mulldo. */
1118 static void gen_mulldo(DisasContext *ctx)
1119 {
1120 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1121 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1122 if (unlikely(Rc(ctx->opcode) != 0)) {
1123 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1124 }
1125 }
1126 #endif
1127
1128 /* Common subf function */
1129 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1130 TCGv arg2, bool add_ca, bool compute_ca,
1131 bool compute_ov, bool compute_rc0)
1132 {
1133 TCGv t0 = ret;
1134
1135 if (compute_ca || compute_ov) {
1136 t0 = tcg_temp_new();
1137 }
1138
1139 if (compute_ca) {
1140 /* dest = ~arg1 + arg2 [+ ca]. */
1141 if (NARROW_MODE(ctx)) {
1142 /* Caution: a non-obvious corner case of the spec is that we
1143 must produce the *entire* 64-bit addition, but produce the
1144 carry into bit 32. */
1145 TCGv inv1 = tcg_temp_new();
1146 TCGv t1 = tcg_temp_new();
1147 tcg_gen_not_tl(inv1, arg1);
1148 if (add_ca) {
1149 tcg_gen_add_tl(t0, arg2, cpu_ca);
1150 } else {
1151 tcg_gen_addi_tl(t0, arg2, 1);
1152 }
1153 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1154 tcg_gen_add_tl(t0, t0, inv1);
1155 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1156 tcg_temp_free(t1);
1157 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1158 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1159 } else if (add_ca) {
1160 TCGv zero, inv1 = tcg_temp_new();
1161 tcg_gen_not_tl(inv1, arg1);
1162 zero = tcg_const_tl(0);
1163 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1164 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1165 tcg_temp_free(zero);
1166 tcg_temp_free(inv1);
1167 } else {
1168 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1169 tcg_gen_sub_tl(t0, arg2, arg1);
1170 }
1171 } else if (add_ca) {
1172 /* Since we're ignoring carry-out, we can simplify the
1173 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1174 tcg_gen_sub_tl(t0, arg2, arg1);
1175 tcg_gen_add_tl(t0, t0, cpu_ca);
1176 tcg_gen_subi_tl(t0, t0, 1);
1177 } else {
1178 tcg_gen_sub_tl(t0, arg2, arg1);
1179 }
1180
1181 if (compute_ov) {
1182 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1183 }
1184 if (unlikely(compute_rc0)) {
1185 gen_set_Rc0(ctx, t0);
1186 }
1187
1188 if (!TCGV_EQUAL(t0, ret)) {
1189 tcg_gen_mov_tl(ret, t0);
1190 tcg_temp_free(t0);
1191 }
1192 }
1193 /* Sub functions with Two operands functions */
1194 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1195 static void glue(gen_, name)(DisasContext *ctx) \
1196 { \
1197 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1198 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1199 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1200 }
1201 /* Sub functions with one operand and one immediate */
1202 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1203 add_ca, compute_ca, compute_ov) \
1204 static void glue(gen_, name)(DisasContext *ctx) \
1205 { \
1206 TCGv t0 = tcg_const_tl(const_val); \
1207 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1208 cpu_gpr[rA(ctx->opcode)], t0, \
1209 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1210 tcg_temp_free(t0); \
1211 }
1212 /* subf subf. subfo subfo. */
1213 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1214 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1215 /* subfc subfc. subfco subfco. */
1216 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1217 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1218 /* subfe subfe. subfeo subfo. */
1219 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1220 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1221 /* subfme subfme. subfmeo subfmeo. */
1222 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1223 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1224 /* subfze subfze. subfzeo subfzeo.*/
1225 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1226 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1227
1228 /* subfic */
1229 static void gen_subfic(DisasContext *ctx)
1230 {
1231 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1232 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1233 c, 0, 1, 0, 0);
1234 tcg_temp_free(c);
1235 }
1236
1237 /* neg neg. nego nego. */
1238 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1239 {
1240 TCGv zero = tcg_const_tl(0);
1241 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1242 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1243 tcg_temp_free(zero);
1244 }
1245
1246 static void gen_neg(DisasContext *ctx)
1247 {
1248 gen_op_arith_neg(ctx, 0);
1249 }
1250
1251 static void gen_nego(DisasContext *ctx)
1252 {
1253 gen_op_arith_neg(ctx, 1);
1254 }
1255
1256 /*** Integer logical ***/
1257 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1258 static void glue(gen_, name)(DisasContext *ctx) \
1259 { \
1260 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1261 cpu_gpr[rB(ctx->opcode)]); \
1262 if (unlikely(Rc(ctx->opcode) != 0)) \
1263 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1264 }
1265
1266 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1267 static void glue(gen_, name)(DisasContext *ctx) \
1268 { \
1269 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1270 if (unlikely(Rc(ctx->opcode) != 0)) \
1271 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1272 }
1273
1274 /* and & and. */
1275 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1276 /* andc & andc. */
1277 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1278
1279 /* andi. */
1280 static void gen_andi_(DisasContext *ctx)
1281 {
1282 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1283 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1284 }
1285
1286 /* andis. */
1287 static void gen_andis_(DisasContext *ctx)
1288 {
1289 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1290 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1291 }
1292
1293 /* cntlzw */
1294 static void gen_cntlzw(DisasContext *ctx)
1295 {
1296 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1297 if (unlikely(Rc(ctx->opcode) != 0))
1298 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1299 }
1300 /* eqv & eqv. */
1301 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1302 /* extsb & extsb. */
1303 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1304 /* extsh & extsh. */
1305 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1306 /* nand & nand. */
1307 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1308 /* nor & nor. */
1309 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1310
1311 /* or & or. */
1312 static void gen_or(DisasContext *ctx)
1313 {
1314 int rs, ra, rb;
1315
1316 rs = rS(ctx->opcode);
1317 ra = rA(ctx->opcode);
1318 rb = rB(ctx->opcode);
1319 /* Optimisation for mr. ri case */
1320 if (rs != ra || rs != rb) {
1321 if (rs != rb)
1322 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1323 else
1324 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1325 if (unlikely(Rc(ctx->opcode) != 0))
1326 gen_set_Rc0(ctx, cpu_gpr[ra]);
1327 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1328 gen_set_Rc0(ctx, cpu_gpr[rs]);
1329 #if defined(TARGET_PPC64)
1330 } else {
1331 int prio = 0;
1332
1333 switch (rs) {
1334 case 1:
1335 /* Set process priority to low */
1336 prio = 2;
1337 break;
1338 case 6:
1339 /* Set process priority to medium-low */
1340 prio = 3;
1341 break;
1342 case 2:
1343 /* Set process priority to normal */
1344 prio = 4;
1345 break;
1346 #if !defined(CONFIG_USER_ONLY)
1347 case 31:
1348 if (ctx->mem_idx > 0) {
1349 /* Set process priority to very low */
1350 prio = 1;
1351 }
1352 break;
1353 case 5:
1354 if (ctx->mem_idx > 0) {
1355 /* Set process priority to medium-hight */
1356 prio = 5;
1357 }
1358 break;
1359 case 3:
1360 if (ctx->mem_idx > 0) {
1361 /* Set process priority to high */
1362 prio = 6;
1363 }
1364 break;
1365 case 7:
1366 if (ctx->mem_idx > 1) {
1367 /* Set process priority to very high */
1368 prio = 7;
1369 }
1370 break;
1371 #endif
1372 default:
1373 /* nop */
1374 break;
1375 }
1376 if (prio) {
1377 TCGv t0 = tcg_temp_new();
1378 gen_load_spr(t0, SPR_PPR);
1379 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1380 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1381 gen_store_spr(SPR_PPR, t0);
1382 tcg_temp_free(t0);
1383 }
1384 #endif
1385 }
1386 }
1387 /* orc & orc. */
1388 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1389
1390 /* xor & xor. */
1391 static void gen_xor(DisasContext *ctx)
1392 {
1393 /* Optimisation for "set to zero" case */
1394 if (rS(ctx->opcode) != rB(ctx->opcode))
1395 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1396 else
1397 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1398 if (unlikely(Rc(ctx->opcode) != 0))
1399 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1400 }
1401
1402 /* ori */
1403 static void gen_ori(DisasContext *ctx)
1404 {
1405 target_ulong uimm = UIMM(ctx->opcode);
1406
1407 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1408 /* NOP */
1409 /* XXX: should handle special NOPs for POWER series */
1410 return;
1411 }
1412 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1413 }
1414
1415 /* oris */
1416 static void gen_oris(DisasContext *ctx)
1417 {
1418 target_ulong uimm = UIMM(ctx->opcode);
1419
1420 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1421 /* NOP */
1422 return;
1423 }
1424 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1425 }
1426
1427 /* xori */
1428 static void gen_xori(DisasContext *ctx)
1429 {
1430 target_ulong uimm = UIMM(ctx->opcode);
1431
1432 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1433 /* NOP */
1434 return;
1435 }
1436 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1437 }
1438
1439 /* xoris */
1440 static void gen_xoris(DisasContext *ctx)
1441 {
1442 target_ulong uimm = UIMM(ctx->opcode);
1443
1444 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1445 /* NOP */
1446 return;
1447 }
1448 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1449 }
1450
1451 /* popcntb : PowerPC 2.03 specification */
1452 static void gen_popcntb(DisasContext *ctx)
1453 {
1454 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1455 }
1456
1457 static void gen_popcntw(DisasContext *ctx)
1458 {
1459 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1460 }
1461
1462 #if defined(TARGET_PPC64)
1463 /* popcntd: PowerPC 2.06 specification */
1464 static void gen_popcntd(DisasContext *ctx)
1465 {
1466 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1467 }
1468 #endif
1469
1470 /* prtyw: PowerPC 2.05 specification */
1471 static void gen_prtyw(DisasContext *ctx)
1472 {
1473 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1474 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1475 TCGv t0 = tcg_temp_new();
1476 tcg_gen_shri_tl(t0, rs, 16);
1477 tcg_gen_xor_tl(ra, rs, t0);
1478 tcg_gen_shri_tl(t0, ra, 8);
1479 tcg_gen_xor_tl(ra, ra, t0);
1480 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1481 tcg_temp_free(t0);
1482 }
1483
1484 #if defined(TARGET_PPC64)
1485 /* prtyd: PowerPC 2.05 specification */
1486 static void gen_prtyd(DisasContext *ctx)
1487 {
1488 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1489 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1490 TCGv t0 = tcg_temp_new();
1491 tcg_gen_shri_tl(t0, rs, 32);
1492 tcg_gen_xor_tl(ra, rs, t0);
1493 tcg_gen_shri_tl(t0, ra, 16);
1494 tcg_gen_xor_tl(ra, ra, t0);
1495 tcg_gen_shri_tl(t0, ra, 8);
1496 tcg_gen_xor_tl(ra, ra, t0);
1497 tcg_gen_andi_tl(ra, ra, 1);
1498 tcg_temp_free(t0);
1499 }
1500 #endif
1501
1502 #if defined(TARGET_PPC64)
1503 /* extsw & extsw. */
1504 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1505
1506 /* cntlzd */
1507 static void gen_cntlzd(DisasContext *ctx)
1508 {
1509 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1510 if (unlikely(Rc(ctx->opcode) != 0))
1511 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1512 }
1513 #endif
1514
1515 /*** Integer rotate ***/
1516
1517 /* rlwimi & rlwimi. */
1518 static void gen_rlwimi(DisasContext *ctx)
1519 {
1520 uint32_t mb, me, sh;
1521
1522 mb = MB(ctx->opcode);
1523 me = ME(ctx->opcode);
1524 sh = SH(ctx->opcode);
1525 if (likely(sh == 0 && mb == 0 && me == 31)) {
1526 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1527 } else {
1528 target_ulong mask;
1529 TCGv t1;
1530 TCGv t0 = tcg_temp_new();
1531 #if defined(TARGET_PPC64)
1532 TCGv_i32 t2 = tcg_temp_new_i32();
1533 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1534 tcg_gen_rotli_i32(t2, t2, sh);
1535 tcg_gen_extu_i32_i64(t0, t2);
1536 tcg_temp_free_i32(t2);
1537 #else
1538 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1539 #endif
1540 #if defined(TARGET_PPC64)
1541 mb += 32;
1542 me += 32;
1543 #endif
1544 mask = MASK(mb, me);
1545 t1 = tcg_temp_new();
1546 tcg_gen_andi_tl(t0, t0, mask);
1547 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1548 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1549 tcg_temp_free(t0);
1550 tcg_temp_free(t1);
1551 }
1552 if (unlikely(Rc(ctx->opcode) != 0))
1553 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1554 }
1555
1556 /* rlwinm & rlwinm. */
1557 static void gen_rlwinm(DisasContext *ctx)
1558 {
1559 uint32_t mb, me, sh;
1560
1561 sh = SH(ctx->opcode);
1562 mb = MB(ctx->opcode);
1563 me = ME(ctx->opcode);
1564
1565 if (likely(mb == 0 && me == (31 - sh))) {
1566 if (likely(sh == 0)) {
1567 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1568 } else {
1569 TCGv t0 = tcg_temp_new();
1570 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1571 tcg_gen_shli_tl(t0, t0, sh);
1572 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1573 tcg_temp_free(t0);
1574 }
1575 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1576 TCGv t0 = tcg_temp_new();
1577 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1578 tcg_gen_shri_tl(t0, t0, mb);
1579 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1580 tcg_temp_free(t0);
1581 } else {
1582 TCGv t0 = tcg_temp_new();
1583 #if defined(TARGET_PPC64)
1584 TCGv_i32 t1 = tcg_temp_new_i32();
1585 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1586 tcg_gen_rotli_i32(t1, t1, sh);
1587 tcg_gen_extu_i32_i64(t0, t1);
1588 tcg_temp_free_i32(t1);
1589 #else
1590 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1591 #endif
1592 #if defined(TARGET_PPC64)
1593 mb += 32;
1594 me += 32;
1595 #endif
1596 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1597 tcg_temp_free(t0);
1598 }
1599 if (unlikely(Rc(ctx->opcode) != 0))
1600 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1601 }
1602
1603 /* rlwnm & rlwnm. */
1604 static void gen_rlwnm(DisasContext *ctx)
1605 {
1606 uint32_t mb, me;
1607 TCGv t0;
1608 #if defined(TARGET_PPC64)
1609 TCGv_i32 t1, t2;
1610 #endif
1611
1612 mb = MB(ctx->opcode);
1613 me = ME(ctx->opcode);
1614 t0 = tcg_temp_new();
1615 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1616 #if defined(TARGET_PPC64)
1617 t1 = tcg_temp_new_i32();
1618 t2 = tcg_temp_new_i32();
1619 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1620 tcg_gen_trunc_i64_i32(t2, t0);
1621 tcg_gen_rotl_i32(t1, t1, t2);
1622 tcg_gen_extu_i32_i64(t0, t1);
1623 tcg_temp_free_i32(t1);
1624 tcg_temp_free_i32(t2);
1625 #else
1626 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1627 #endif
1628 if (unlikely(mb != 0 || me != 31)) {
1629 #if defined(TARGET_PPC64)
1630 mb += 32;
1631 me += 32;
1632 #endif
1633 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1634 } else {
1635 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1636 }
1637 tcg_temp_free(t0);
1638 if (unlikely(Rc(ctx->opcode) != 0))
1639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1640 }
1641
1642 #if defined(TARGET_PPC64)
1643 #define GEN_PPC64_R2(name, opc1, opc2) \
1644 static void glue(gen_, name##0)(DisasContext *ctx) \
1645 { \
1646 gen_##name(ctx, 0); \
1647 } \
1648 \
1649 static void glue(gen_, name##1)(DisasContext *ctx) \
1650 { \
1651 gen_##name(ctx, 1); \
1652 }
1653 #define GEN_PPC64_R4(name, opc1, opc2) \
1654 static void glue(gen_, name##0)(DisasContext *ctx) \
1655 { \
1656 gen_##name(ctx, 0, 0); \
1657 } \
1658 \
1659 static void glue(gen_, name##1)(DisasContext *ctx) \
1660 { \
1661 gen_##name(ctx, 0, 1); \
1662 } \
1663 \
1664 static void glue(gen_, name##2)(DisasContext *ctx) \
1665 { \
1666 gen_##name(ctx, 1, 0); \
1667 } \
1668 \
1669 static void glue(gen_, name##3)(DisasContext *ctx) \
1670 { \
1671 gen_##name(ctx, 1, 1); \
1672 }
1673
1674 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1675 uint32_t sh)
1676 {
1677 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1678 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1679 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1680 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1681 } else {
1682 TCGv t0 = tcg_temp_new();
1683 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1684 if (likely(mb == 0 && me == 63)) {
1685 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1686 } else {
1687 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1688 }
1689 tcg_temp_free(t0);
1690 }
1691 if (unlikely(Rc(ctx->opcode) != 0))
1692 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1693 }
1694 /* rldicl - rldicl. */
1695 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1696 {
1697 uint32_t sh, mb;
1698
1699 sh = SH(ctx->opcode) | (shn << 5);
1700 mb = MB(ctx->opcode) | (mbn << 5);
1701 gen_rldinm(ctx, mb, 63, sh);
1702 }
1703 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1704 /* rldicr - rldicr. */
1705 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1706 {
1707 uint32_t sh, me;
1708
1709 sh = SH(ctx->opcode) | (shn << 5);
1710 me = MB(ctx->opcode) | (men << 5);
1711 gen_rldinm(ctx, 0, me, sh);
1712 }
1713 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1714 /* rldic - rldic. */
1715 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1716 {
1717 uint32_t sh, mb;
1718
1719 sh = SH(ctx->opcode) | (shn << 5);
1720 mb = MB(ctx->opcode) | (mbn << 5);
1721 gen_rldinm(ctx, mb, 63 - sh, sh);
1722 }
1723 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1724
1725 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1726 {
1727 TCGv t0;
1728
1729 mb = MB(ctx->opcode);
1730 me = ME(ctx->opcode);
1731 t0 = tcg_temp_new();
1732 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1733 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1734 if (unlikely(mb != 0 || me != 63)) {
1735 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1736 } else {
1737 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1738 }
1739 tcg_temp_free(t0);
1740 if (unlikely(Rc(ctx->opcode) != 0))
1741 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1742 }
1743
1744 /* rldcl - rldcl. */
1745 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1746 {
1747 uint32_t mb;
1748
1749 mb = MB(ctx->opcode) | (mbn << 5);
1750 gen_rldnm(ctx, mb, 63);
1751 }
1752 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1753 /* rldcr - rldcr. */
1754 static inline void gen_rldcr(DisasContext *ctx, int men)
1755 {
1756 uint32_t me;
1757
1758 me = MB(ctx->opcode) | (men << 5);
1759 gen_rldnm(ctx, 0, me);
1760 }
1761 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1762 /* rldimi - rldimi. */
1763 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1764 {
1765 uint32_t sh, mb, me;
1766
1767 sh = SH(ctx->opcode) | (shn << 5);
1768 mb = MB(ctx->opcode) | (mbn << 5);
1769 me = 63 - sh;
1770 if (unlikely(sh == 0 && mb == 0)) {
1771 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1772 } else {
1773 TCGv t0, t1;
1774 target_ulong mask;
1775
1776 t0 = tcg_temp_new();
1777 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1778 t1 = tcg_temp_new();
1779 mask = MASK(mb, me);
1780 tcg_gen_andi_tl(t0, t0, mask);
1781 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1782 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1783 tcg_temp_free(t0);
1784 tcg_temp_free(t1);
1785 }
1786 if (unlikely(Rc(ctx->opcode) != 0))
1787 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1788 }
1789 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1790 #endif
1791
1792 /*** Integer shift ***/
1793
1794 /* slw & slw. */
1795 static void gen_slw(DisasContext *ctx)
1796 {
1797 TCGv t0, t1;
1798
1799 t0 = tcg_temp_new();
1800 /* AND rS with a mask that is 0 when rB >= 0x20 */
1801 #if defined(TARGET_PPC64)
1802 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1803 tcg_gen_sari_tl(t0, t0, 0x3f);
1804 #else
1805 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1806 tcg_gen_sari_tl(t0, t0, 0x1f);
1807 #endif
1808 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1809 t1 = tcg_temp_new();
1810 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1811 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1812 tcg_temp_free(t1);
1813 tcg_temp_free(t0);
1814 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1815 if (unlikely(Rc(ctx->opcode) != 0))
1816 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1817 }
1818
1819 /* sraw & sraw. */
1820 static void gen_sraw(DisasContext *ctx)
1821 {
1822 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1823 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1824 if (unlikely(Rc(ctx->opcode) != 0))
1825 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1826 }
1827
1828 /* srawi & srawi. */
1829 static void gen_srawi(DisasContext *ctx)
1830 {
1831 int sh = SH(ctx->opcode);
1832 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1833 TCGv src = cpu_gpr[rS(ctx->opcode)];
1834 if (sh == 0) {
1835 tcg_gen_mov_tl(dst, src);
1836 tcg_gen_movi_tl(cpu_ca, 0);
1837 } else {
1838 TCGv t0;
1839 tcg_gen_ext32s_tl(dst, src);
1840 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1841 t0 = tcg_temp_new();
1842 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1843 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1844 tcg_temp_free(t0);
1845 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1846 tcg_gen_sari_tl(dst, dst, sh);
1847 }
1848 if (unlikely(Rc(ctx->opcode) != 0)) {
1849 gen_set_Rc0(ctx, dst);
1850 }
1851 }
1852
1853 /* srw & srw. */
1854 static void gen_srw(DisasContext *ctx)
1855 {
1856 TCGv t0, t1;
1857
1858 t0 = tcg_temp_new();
1859 /* AND rS with a mask that is 0 when rB >= 0x20 */
1860 #if defined(TARGET_PPC64)
1861 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1862 tcg_gen_sari_tl(t0, t0, 0x3f);
1863 #else
1864 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1865 tcg_gen_sari_tl(t0, t0, 0x1f);
1866 #endif
1867 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1868 tcg_gen_ext32u_tl(t0, t0);
1869 t1 = tcg_temp_new();
1870 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1871 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1872 tcg_temp_free(t1);
1873 tcg_temp_free(t0);
1874 if (unlikely(Rc(ctx->opcode) != 0))
1875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1876 }
1877
1878 #if defined(TARGET_PPC64)
1879 /* sld & sld. */
1880 static void gen_sld(DisasContext *ctx)
1881 {
1882 TCGv t0, t1;
1883
1884 t0 = tcg_temp_new();
1885 /* AND rS with a mask that is 0 when rB >= 0x40 */
1886 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1887 tcg_gen_sari_tl(t0, t0, 0x3f);
1888 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1889 t1 = tcg_temp_new();
1890 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1891 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1892 tcg_temp_free(t1);
1893 tcg_temp_free(t0);
1894 if (unlikely(Rc(ctx->opcode) != 0))
1895 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1896 }
1897
1898 /* srad & srad. */
1899 static void gen_srad(DisasContext *ctx)
1900 {
1901 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1902 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1903 if (unlikely(Rc(ctx->opcode) != 0))
1904 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1905 }
1906 /* sradi & sradi. */
1907 static inline void gen_sradi(DisasContext *ctx, int n)
1908 {
1909 int sh = SH(ctx->opcode) + (n << 5);
1910 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1911 TCGv src = cpu_gpr[rS(ctx->opcode)];
1912 if (sh == 0) {
1913 tcg_gen_mov_tl(dst, src);
1914 tcg_gen_movi_tl(cpu_ca, 0);
1915 } else {
1916 TCGv t0;
1917 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1918 t0 = tcg_temp_new();
1919 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1920 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1921 tcg_temp_free(t0);
1922 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1923 tcg_gen_sari_tl(dst, src, sh);
1924 }
1925 if (unlikely(Rc(ctx->opcode) != 0)) {
1926 gen_set_Rc0(ctx, dst);
1927 }
1928 }
1929
1930 static void gen_sradi0(DisasContext *ctx)
1931 {
1932 gen_sradi(ctx, 0);
1933 }
1934
1935 static void gen_sradi1(DisasContext *ctx)
1936 {
1937 gen_sradi(ctx, 1);
1938 }
1939
1940 /* srd & srd. */
1941 static void gen_srd(DisasContext *ctx)
1942 {
1943 TCGv t0, t1;
1944
1945 t0 = tcg_temp_new();
1946 /* AND rS with a mask that is 0 when rB >= 0x40 */
1947 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1948 tcg_gen_sari_tl(t0, t0, 0x3f);
1949 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1950 t1 = tcg_temp_new();
1951 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1952 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1953 tcg_temp_free(t1);
1954 tcg_temp_free(t0);
1955 if (unlikely(Rc(ctx->opcode) != 0))
1956 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1957 }
1958 #endif
1959
1960 /*** Floating-Point arithmetic ***/
1961 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1962 static void gen_f##name(DisasContext *ctx) \
1963 { \
1964 if (unlikely(!ctx->fpu_enabled)) { \
1965 gen_exception(ctx, POWERPC_EXCP_FPU); \
1966 return; \
1967 } \
1968 /* NIP cannot be restored if the memory exception comes from an helper */ \
1969 gen_update_nip(ctx, ctx->nip - 4); \
1970 gen_reset_fpstatus(); \
1971 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1972 cpu_fpr[rA(ctx->opcode)], \
1973 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1974 if (isfloat) { \
1975 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1976 cpu_fpr[rD(ctx->opcode)]); \
1977 } \
1978 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1979 Rc(ctx->opcode) != 0); \
1980 }
1981
1982 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1983 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1984 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1985
1986 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1987 static void gen_f##name(DisasContext *ctx) \
1988 { \
1989 if (unlikely(!ctx->fpu_enabled)) { \
1990 gen_exception(ctx, POWERPC_EXCP_FPU); \
1991 return; \
1992 } \
1993 /* NIP cannot be restored if the memory exception comes from an helper */ \
1994 gen_update_nip(ctx, ctx->nip - 4); \
1995 gen_reset_fpstatus(); \
1996 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1997 cpu_fpr[rA(ctx->opcode)], \
1998 cpu_fpr[rB(ctx->opcode)]); \
1999 if (isfloat) { \
2000 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2001 cpu_fpr[rD(ctx->opcode)]); \
2002 } \
2003 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2004 set_fprf, Rc(ctx->opcode) != 0); \
2005 }
2006 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2007 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2008 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2009
2010 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2011 static void gen_f##name(DisasContext *ctx) \
2012 { \
2013 if (unlikely(!ctx->fpu_enabled)) { \
2014 gen_exception(ctx, POWERPC_EXCP_FPU); \
2015 return; \
2016 } \
2017 /* NIP cannot be restored if the memory exception comes from an helper */ \
2018 gen_update_nip(ctx, ctx->nip - 4); \
2019 gen_reset_fpstatus(); \
2020 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2021 cpu_fpr[rA(ctx->opcode)], \
2022 cpu_fpr[rC(ctx->opcode)]); \
2023 if (isfloat) { \
2024 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2025 cpu_fpr[rD(ctx->opcode)]); \
2026 } \
2027 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2028 set_fprf, Rc(ctx->opcode) != 0); \
2029 }
2030 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2031 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2032 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2033
2034 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2035 static void gen_f##name(DisasContext *ctx) \
2036 { \
2037 if (unlikely(!ctx->fpu_enabled)) { \
2038 gen_exception(ctx, POWERPC_EXCP_FPU); \
2039 return; \
2040 } \
2041 /* NIP cannot be restored if the memory exception comes from an helper */ \
2042 gen_update_nip(ctx, ctx->nip - 4); \
2043 gen_reset_fpstatus(); \
2044 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2045 cpu_fpr[rB(ctx->opcode)]); \
2046 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2047 set_fprf, Rc(ctx->opcode) != 0); \
2048 }
2049
2050 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2051 static void gen_f##name(DisasContext *ctx) \
2052 { \
2053 if (unlikely(!ctx->fpu_enabled)) { \
2054 gen_exception(ctx, POWERPC_EXCP_FPU); \
2055 return; \
2056 } \
2057 /* NIP cannot be restored if the memory exception comes from an helper */ \
2058 gen_update_nip(ctx, ctx->nip - 4); \
2059 gen_reset_fpstatus(); \
2060 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2061 cpu_fpr[rB(ctx->opcode)]); \
2062 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2063 set_fprf, Rc(ctx->opcode) != 0); \
2064 }
2065
2066 /* fadd - fadds */
2067 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2068 /* fdiv - fdivs */
2069 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2070 /* fmul - fmuls */
2071 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2072
2073 /* fre */
2074 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2075
2076 /* fres */
2077 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2078
2079 /* frsqrte */
2080 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2081
2082 /* frsqrtes */
2083 static void gen_frsqrtes(DisasContext *ctx)
2084 {
2085 if (unlikely(!ctx->fpu_enabled)) {
2086 gen_exception(ctx, POWERPC_EXCP_FPU);
2087 return;
2088 }
2089 /* NIP cannot be restored if the memory exception comes from an helper */
2090 gen_update_nip(ctx, ctx->nip - 4);
2091 gen_reset_fpstatus();
2092 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2093 cpu_fpr[rB(ctx->opcode)]);
2094 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2095 cpu_fpr[rD(ctx->opcode)]);
2096 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2097 }
2098
2099 /* fsel */
2100 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2101 /* fsub - fsubs */
2102 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2103 /* Optional: */
2104
2105 /* fsqrt */
2106 static void gen_fsqrt(DisasContext *ctx)
2107 {
2108 if (unlikely(!ctx->fpu_enabled)) {
2109 gen_exception(ctx, POWERPC_EXCP_FPU);
2110 return;
2111 }
2112 /* NIP cannot be restored if the memory exception comes from an helper */
2113 gen_update_nip(ctx, ctx->nip - 4);
2114 gen_reset_fpstatus();
2115 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2116 cpu_fpr[rB(ctx->opcode)]);
2117 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2118 }
2119
2120 static void gen_fsqrts(DisasContext *ctx)
2121 {
2122 if (unlikely(!ctx->fpu_enabled)) {
2123 gen_exception(ctx, POWERPC_EXCP_FPU);
2124 return;
2125 }
2126 /* NIP cannot be restored if the memory exception comes from an helper */
2127 gen_update_nip(ctx, ctx->nip - 4);
2128 gen_reset_fpstatus();
2129 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2130 cpu_fpr[rB(ctx->opcode)]);
2131 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2132 cpu_fpr[rD(ctx->opcode)]);
2133 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2134 }
2135
2136 /*** Floating-Point multiply-and-add ***/
2137 /* fmadd - fmadds */
2138 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2139 /* fmsub - fmsubs */
2140 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2141 /* fnmadd - fnmadds */
2142 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2143 /* fnmsub - fnmsubs */
2144 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2145
2146 /*** Floating-Point round & convert ***/
2147 /* fctiw */
2148 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2149 /* fctiwz */
2150 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2151 /* frsp */
2152 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2153 #if defined(TARGET_PPC64)
2154 /* fcfid */
2155 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2156 /* fctid */
2157 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2158 /* fctidz */
2159 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2160 #endif
2161
2162 /* frin */
2163 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2164 /* friz */
2165 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2166 /* frip */
2167 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2168 /* frim */
2169 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2170
2171 /*** Floating-Point compare ***/
2172
2173 /* fcmpo */
2174 static void gen_fcmpo(DisasContext *ctx)
2175 {
2176 TCGv_i32 crf;
2177 if (unlikely(!ctx->fpu_enabled)) {
2178 gen_exception(ctx, POWERPC_EXCP_FPU);
2179 return;
2180 }
2181 /* NIP cannot be restored if the memory exception comes from an helper */
2182 gen_update_nip(ctx, ctx->nip - 4);
2183 gen_reset_fpstatus();
2184 crf = tcg_const_i32(crfD(ctx->opcode));
2185 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2186 cpu_fpr[rB(ctx->opcode)], crf);
2187 tcg_temp_free_i32(crf);
2188 gen_helper_float_check_status(cpu_env);
2189 }
2190
2191 /* fcmpu */
2192 static void gen_fcmpu(DisasContext *ctx)
2193 {
2194 TCGv_i32 crf;
2195 if (unlikely(!ctx->fpu_enabled)) {
2196 gen_exception(ctx, POWERPC_EXCP_FPU);
2197 return;
2198 }
2199 /* NIP cannot be restored if the memory exception comes from an helper */
2200 gen_update_nip(ctx, ctx->nip - 4);
2201 gen_reset_fpstatus();
2202 crf = tcg_const_i32(crfD(ctx->opcode));
2203 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2204 cpu_fpr[rB(ctx->opcode)], crf);
2205 tcg_temp_free_i32(crf);
2206 gen_helper_float_check_status(cpu_env);
2207 }
2208
2209 /*** Floating-point move ***/
2210 /* fabs */
2211 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2212 static void gen_fabs(DisasContext *ctx)
2213 {
2214 if (unlikely(!ctx->fpu_enabled)) {
2215 gen_exception(ctx, POWERPC_EXCP_FPU);
2216 return;
2217 }
2218 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2219 ~(1ULL << 63));
2220 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2221 }
2222
2223 /* fmr - fmr. */
2224 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2225 static void gen_fmr(DisasContext *ctx)
2226 {
2227 if (unlikely(!ctx->fpu_enabled)) {
2228 gen_exception(ctx, POWERPC_EXCP_FPU);
2229 return;
2230 }
2231 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2232 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2233 }
2234
2235 /* fnabs */
2236 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2237 static void gen_fnabs(DisasContext *ctx)
2238 {
2239 if (unlikely(!ctx->fpu_enabled)) {
2240 gen_exception(ctx, POWERPC_EXCP_FPU);
2241 return;
2242 }
2243 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2244 1ULL << 63);
2245 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2246 }
2247
2248 /* fneg */
2249 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2250 static void gen_fneg(DisasContext *ctx)
2251 {
2252 if (unlikely(!ctx->fpu_enabled)) {
2253 gen_exception(ctx, POWERPC_EXCP_FPU);
2254 return;
2255 }
2256 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2257 1ULL << 63);
2258 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2259 }
2260
2261 /*** Floating-Point status & ctrl register ***/
2262
2263 /* mcrfs */
2264 static void gen_mcrfs(DisasContext *ctx)
2265 {
2266 TCGv tmp = tcg_temp_new();
2267 int bfa;
2268
2269 if (unlikely(!ctx->fpu_enabled)) {
2270 gen_exception(ctx, POWERPC_EXCP_FPU);
2271 return;
2272 }
2273 bfa = 4 * (7 - crfS(ctx->opcode));
2274 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2275 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2276 tcg_temp_free(tmp);
2277 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2278 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2279 }
2280
2281 /* mffs */
2282 static void gen_mffs(DisasContext *ctx)
2283 {
2284 if (unlikely(!ctx->fpu_enabled)) {
2285 gen_exception(ctx, POWERPC_EXCP_FPU);
2286 return;
2287 }
2288 gen_reset_fpstatus();
2289 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2290 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2291 }
2292
2293 /* mtfsb0 */
2294 static void gen_mtfsb0(DisasContext *ctx)
2295 {
2296 uint8_t crb;
2297
2298 if (unlikely(!ctx->fpu_enabled)) {
2299 gen_exception(ctx, POWERPC_EXCP_FPU);
2300 return;
2301 }
2302 crb = 31 - crbD(ctx->opcode);
2303 gen_reset_fpstatus();
2304 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2305 TCGv_i32 t0;
2306 /* NIP cannot be restored if the memory exception comes from an helper */
2307 gen_update_nip(ctx, ctx->nip - 4);
2308 t0 = tcg_const_i32(crb);
2309 gen_helper_fpscr_clrbit(cpu_env, t0);
2310 tcg_temp_free_i32(t0);
2311 }
2312 if (unlikely(Rc(ctx->opcode) != 0)) {
2313 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2314 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2315 }
2316 }
2317
2318 /* mtfsb1 */
2319 static void gen_mtfsb1(DisasContext *ctx)
2320 {
2321 uint8_t crb;
2322
2323 if (unlikely(!ctx->fpu_enabled)) {
2324 gen_exception(ctx, POWERPC_EXCP_FPU);
2325 return;
2326 }
2327 crb = 31 - crbD(ctx->opcode);
2328 gen_reset_fpstatus();
2329 /* XXX: we pretend we can only do IEEE floating-point computations */
2330 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2331 TCGv_i32 t0;
2332 /* NIP cannot be restored if the memory exception comes from an helper */
2333 gen_update_nip(ctx, ctx->nip - 4);
2334 t0 = tcg_const_i32(crb);
2335 gen_helper_fpscr_setbit(cpu_env, t0);
2336 tcg_temp_free_i32(t0);
2337 }
2338 if (unlikely(Rc(ctx->opcode) != 0)) {
2339 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2340 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2341 }
2342 /* We can raise a differed exception */
2343 gen_helper_float_check_status(cpu_env);
2344 }
2345
2346 /* mtfsf */
2347 static void gen_mtfsf(DisasContext *ctx)
2348 {
2349 TCGv_i32 t0;
2350 int L = ctx->opcode & 0x02000000;
2351
2352 if (unlikely(!ctx->fpu_enabled)) {
2353 gen_exception(ctx, POWERPC_EXCP_FPU);
2354 return;
2355 }
2356 /* NIP cannot be restored if the memory exception comes from an helper */
2357 gen_update_nip(ctx, ctx->nip - 4);
2358 gen_reset_fpstatus();
2359 if (L)
2360 t0 = tcg_const_i32(0xff);
2361 else
2362 t0 = tcg_const_i32(FM(ctx->opcode));
2363 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2364 tcg_temp_free_i32(t0);
2365 if (unlikely(Rc(ctx->opcode) != 0)) {
2366 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2367 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2368 }
2369 /* We can raise a differed exception */
2370 gen_helper_float_check_status(cpu_env);
2371 }
2372
2373 /* mtfsfi */
2374 static void gen_mtfsfi(DisasContext *ctx)
2375 {
2376 int bf, sh;
2377 TCGv_i64 t0;
2378 TCGv_i32 t1;
2379
2380 if (unlikely(!ctx->fpu_enabled)) {
2381 gen_exception(ctx, POWERPC_EXCP_FPU);
2382 return;
2383 }
2384 bf = crbD(ctx->opcode) >> 2;
2385 sh = 7 - bf;
2386 /* NIP cannot be restored if the memory exception comes from an helper */
2387 gen_update_nip(ctx, ctx->nip - 4);
2388 gen_reset_fpstatus();
2389 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2390 t1 = tcg_const_i32(1 << sh);
2391 gen_helper_store_fpscr(cpu_env, t0, t1);
2392 tcg_temp_free_i64(t0);
2393 tcg_temp_free_i32(t1);
2394 if (unlikely(Rc(ctx->opcode) != 0)) {
2395 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2396 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2397 }
2398 /* We can raise a differed exception */
2399 gen_helper_float_check_status(cpu_env);
2400 }
2401
2402 /*** Addressing modes ***/
2403 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2404 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2405 target_long maskl)
2406 {
2407 target_long simm = SIMM(ctx->opcode);
2408
2409 simm &= ~maskl;
2410 if (rA(ctx->opcode) == 0) {
2411 if (NARROW_MODE(ctx)) {
2412 simm = (uint32_t)simm;
2413 }
2414 tcg_gen_movi_tl(EA, simm);
2415 } else if (likely(simm != 0)) {
2416 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2417 if (NARROW_MODE(ctx)) {
2418 tcg_gen_ext32u_tl(EA, EA);
2419 }
2420 } else {
2421 if (NARROW_MODE(ctx)) {
2422 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2423 } else {
2424 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2425 }
2426 }
2427 }
2428
2429 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2430 {
2431 if (rA(ctx->opcode) == 0) {
2432 if (NARROW_MODE(ctx)) {
2433 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2434 } else {
2435 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2436 }
2437 } else {
2438 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2439 if (NARROW_MODE(ctx)) {
2440 tcg_gen_ext32u_tl(EA, EA);
2441 }
2442 }
2443 }
2444
2445 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2446 {
2447 if (rA(ctx->opcode) == 0) {
2448 tcg_gen_movi_tl(EA, 0);
2449 } else if (NARROW_MODE(ctx)) {
2450 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2451 } else {
2452 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2453 }
2454 }
2455
2456 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2457 target_long val)
2458 {
2459 tcg_gen_addi_tl(ret, arg1, val);
2460 if (NARROW_MODE(ctx)) {
2461 tcg_gen_ext32u_tl(ret, ret);
2462 }
2463 }
2464
2465 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2466 {
2467 int l1 = gen_new_label();
2468 TCGv t0 = tcg_temp_new();
2469 TCGv_i32 t1, t2;
2470 /* NIP cannot be restored if the memory exception comes from an helper */
2471 gen_update_nip(ctx, ctx->nip - 4);
2472 tcg_gen_andi_tl(t0, EA, mask);
2473 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2474 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2475 t2 = tcg_const_i32(0);
2476 gen_helper_raise_exception_err(cpu_env, t1, t2);
2477 tcg_temp_free_i32(t1);
2478 tcg_temp_free_i32(t2);
2479 gen_set_label(l1);
2480 tcg_temp_free(t0);
2481 }
2482
2483 /*** Integer load ***/
2484 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2485 {
2486 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2487 }
2488
2489 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2490 {
2491 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2492 }
2493
2494 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2495 {
2496 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2497 if (unlikely(ctx->le_mode)) {
2498 tcg_gen_bswap16_tl(arg1, arg1);
2499 }
2500 }
2501
2502 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2503 {
2504 if (unlikely(ctx->le_mode)) {
2505 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2506 tcg_gen_bswap16_tl(arg1, arg1);
2507 tcg_gen_ext16s_tl(arg1, arg1);
2508 } else {
2509 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2510 }
2511 }
2512
2513 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2514 {
2515 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2516 if (unlikely(ctx->le_mode)) {
2517 tcg_gen_bswap32_tl(arg1, arg1);
2518 }
2519 }
2520
2521 #if defined(TARGET_PPC64)
2522 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2523 {
2524 if (unlikely(ctx->le_mode)) {
2525 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2526 tcg_gen_bswap32_tl(arg1, arg1);
2527 tcg_gen_ext32s_tl(arg1, arg1);
2528 } else
2529 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2530 }
2531 #endif
2532
2533 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2534 {
2535 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2536 if (unlikely(ctx->le_mode)) {
2537 tcg_gen_bswap64_i64(arg1, arg1);
2538 }
2539 }
2540
2541 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2542 {
2543 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2544 }
2545
2546 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2547 {
2548 if (unlikely(ctx->le_mode)) {
2549 TCGv t0 = tcg_temp_new();
2550 tcg_gen_ext16u_tl(t0, arg1);
2551 tcg_gen_bswap16_tl(t0, t0);
2552 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2553 tcg_temp_free(t0);
2554 } else {
2555 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2556 }
2557 }
2558
2559 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2560 {
2561 if (unlikely(ctx->le_mode)) {
2562 TCGv t0 = tcg_temp_new();
2563 tcg_gen_ext32u_tl(t0, arg1);
2564 tcg_gen_bswap32_tl(t0, t0);
2565 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2566 tcg_temp_free(t0);
2567 } else {
2568 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2569 }
2570 }
2571
2572 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2573 {
2574 if (unlikely(ctx->le_mode)) {
2575 TCGv_i64 t0 = tcg_temp_new_i64();
2576 tcg_gen_bswap64_i64(t0, arg1);
2577 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2578 tcg_temp_free_i64(t0);
2579 } else
2580 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2581 }
2582
2583 #define GEN_LD(name, ldop, opc, type) \
2584 static void glue(gen_, name)(DisasContext *ctx) \
2585 { \
2586 TCGv EA; \
2587 gen_set_access_type(ctx, ACCESS_INT); \
2588 EA = tcg_temp_new(); \
2589 gen_addr_imm_index(ctx, EA, 0); \
2590 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2591 tcg_temp_free(EA); \
2592 }
2593
2594 #define GEN_LDU(name, ldop, opc, type) \
2595 static void glue(gen_, name##u)(DisasContext *ctx) \
2596 { \
2597 TCGv EA; \
2598 if (unlikely(rA(ctx->opcode) == 0 || \
2599 rA(ctx->opcode) == rD(ctx->opcode))) { \
2600 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2601 return; \
2602 } \
2603 gen_set_access_type(ctx, ACCESS_INT); \
2604 EA = tcg_temp_new(); \
2605 if (type == PPC_64B) \
2606 gen_addr_imm_index(ctx, EA, 0x03); \
2607 else \
2608 gen_addr_imm_index(ctx, EA, 0); \
2609 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2610 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2611 tcg_temp_free(EA); \
2612 }
2613
2614 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2615 static void glue(gen_, name##ux)(DisasContext *ctx) \
2616 { \
2617 TCGv EA; \
2618 if (unlikely(rA(ctx->opcode) == 0 || \
2619 rA(ctx->opcode) == rD(ctx->opcode))) { \
2620 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2621 return; \
2622 } \
2623 gen_set_access_type(ctx, ACCESS_INT); \
2624 EA = tcg_temp_new(); \
2625 gen_addr_reg_index(ctx, EA); \
2626 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2627 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2628 tcg_temp_free(EA); \
2629 }
2630
2631 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2632 static void glue(gen_, name##x)(DisasContext *ctx) \
2633 { \
2634 TCGv EA; \
2635 gen_set_access_type(ctx, ACCESS_INT); \
2636 EA = tcg_temp_new(); \
2637 gen_addr_reg_index(ctx, EA); \
2638 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2639 tcg_temp_free(EA); \
2640 }
2641 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2642 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2643
2644 #define GEN_LDS(name, ldop, op, type) \
2645 GEN_LD(name, ldop, op | 0x20, type); \
2646 GEN_LDU(name, ldop, op | 0x21, type); \
2647 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2648 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2649
2650 /* lbz lbzu lbzux lbzx */
2651 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2652 /* lha lhau lhaux lhax */
2653 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2654 /* lhz lhzu lhzux lhzx */
2655 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2656 /* lwz lwzu lwzux lwzx */
2657 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2658 #if defined(TARGET_PPC64)
2659 /* lwaux */
2660 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2661 /* lwax */
2662 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2663 /* ldux */
2664 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2665 /* ldx */
2666 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2667
2668 static void gen_ld(DisasContext *ctx)
2669 {
2670 TCGv EA;
2671 if (Rc(ctx->opcode)) {
2672 if (unlikely(rA(ctx->opcode) == 0 ||
2673 rA(ctx->opcode) == rD(ctx->opcode))) {
2674 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2675 return;
2676 }
2677 }
2678 gen_set_access_type(ctx, ACCESS_INT);
2679 EA = tcg_temp_new();
2680 gen_addr_imm_index(ctx, EA, 0x03);
2681 if (ctx->opcode & 0x02) {
2682 /* lwa (lwau is undefined) */
2683 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2684 } else {
2685 /* ld - ldu */
2686 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2687 }
2688 if (Rc(ctx->opcode))
2689 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2690 tcg_temp_free(EA);
2691 }
2692
2693 /* lq */
2694 static void gen_lq(DisasContext *ctx)
2695 {
2696 #if defined(CONFIG_USER_ONLY)
2697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2698 #else
2699 int ra, rd;
2700 TCGv EA;
2701
2702 /* Restore CPU state */
2703 if (unlikely(ctx->mem_idx == 0)) {
2704 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2705 return;
2706 }
2707 ra = rA(ctx->opcode);
2708 rd = rD(ctx->opcode);
2709 if (unlikely((rd & 1) || rd == ra)) {
2710 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2711 return;
2712 }
2713 if (unlikely(ctx->le_mode)) {
2714 /* Little-endian mode is not handled */
2715 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2716 return;
2717 }
2718 gen_set_access_type(ctx, ACCESS_INT);
2719 EA = tcg_temp_new();
2720 gen_addr_imm_index(ctx, EA, 0x0F);
2721 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2722 gen_addr_add(ctx, EA, EA, 8);
2723 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2724 tcg_temp_free(EA);
2725 #endif
2726 }
2727 #endif
2728
2729 /*** Integer store ***/
2730 #define GEN_ST(name, stop, opc, type) \
2731 static void glue(gen_, name)(DisasContext *ctx) \
2732 { \
2733 TCGv EA; \
2734 gen_set_access_type(ctx, ACCESS_INT); \
2735 EA = tcg_temp_new(); \
2736 gen_addr_imm_index(ctx, EA, 0); \
2737 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2738 tcg_temp_free(EA); \
2739 }
2740
2741 #define GEN_STU(name, stop, opc, type) \
2742 static void glue(gen_, stop##u)(DisasContext *ctx) \
2743 { \
2744 TCGv EA; \
2745 if (unlikely(rA(ctx->opcode) == 0)) { \
2746 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2747 return; \
2748 } \
2749 gen_set_access_type(ctx, ACCESS_INT); \
2750 EA = tcg_temp_new(); \
2751 if (type == PPC_64B) \
2752 gen_addr_imm_index(ctx, EA, 0x03); \
2753 else \
2754 gen_addr_imm_index(ctx, EA, 0); \
2755 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2756 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2757 tcg_temp_free(EA); \
2758 }
2759
2760 #define GEN_STUX(name, stop, opc2, opc3, type) \
2761 static void glue(gen_, name##ux)(DisasContext *ctx) \
2762 { \
2763 TCGv EA; \
2764 if (unlikely(rA(ctx->opcode) == 0)) { \
2765 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2766 return; \
2767 } \
2768 gen_set_access_type(ctx, ACCESS_INT); \
2769 EA = tcg_temp_new(); \
2770 gen_addr_reg_index(ctx, EA); \
2771 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2772 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2773 tcg_temp_free(EA); \
2774 }
2775
2776 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2777 static void glue(gen_, name##x)(DisasContext *ctx) \
2778 { \
2779 TCGv EA; \
2780 gen_set_access_type(ctx, ACCESS_INT); \
2781 EA = tcg_temp_new(); \
2782 gen_addr_reg_index(ctx, EA); \
2783 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2784 tcg_temp_free(EA); \
2785 }
2786 #define GEN_STX(name, stop, opc2, opc3, type) \
2787 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2788
2789 #define GEN_STS(name, stop, op, type) \
2790 GEN_ST(name, stop, op | 0x20, type); \
2791 GEN_STU(name, stop, op | 0x21, type); \
2792 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2793 GEN_STX(name, stop, 0x17, op | 0x00, type)
2794
2795 /* stb stbu stbux stbx */
2796 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2797 /* sth sthu sthux sthx */
2798 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2799 /* stw stwu stwux stwx */
2800 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2801 #if defined(TARGET_PPC64)
2802 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2803 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2804
2805 static void gen_std(DisasContext *ctx)
2806 {
2807 int rs;
2808 TCGv EA;
2809
2810 rs = rS(ctx->opcode);
2811 if ((ctx->opcode & 0x3) == 0x2) {
2812 #if defined(CONFIG_USER_ONLY)
2813 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2814 #else
2815 /* stq */
2816 if (unlikely(ctx->mem_idx == 0)) {
2817 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2818 return;
2819 }
2820 if (unlikely(rs & 1)) {
2821 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2822 return;
2823 }
2824 if (unlikely(ctx->le_mode)) {
2825 /* Little-endian mode is not handled */
2826 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2827 return;
2828 }
2829 gen_set_access_type(ctx, ACCESS_INT);
2830 EA = tcg_temp_new();
2831 gen_addr_imm_index(ctx, EA, 0x03);
2832 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2833 gen_addr_add(ctx, EA, EA, 8);
2834 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2835 tcg_temp_free(EA);
2836 #endif
2837 } else {
2838 /* std / stdu */
2839 if (Rc(ctx->opcode)) {
2840 if (unlikely(rA(ctx->opcode) == 0)) {
2841 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2842 return;
2843 }
2844 }
2845 gen_set_access_type(ctx, ACCESS_INT);
2846 EA = tcg_temp_new();
2847 gen_addr_imm_index(ctx, EA, 0x03);
2848 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2849 if (Rc(ctx->opcode))
2850 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2851 tcg_temp_free(EA);
2852 }
2853 }
2854 #endif
2855 /*** Integer load and store with byte reverse ***/
2856 /* lhbrx */
2857 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2858 {
2859 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2860 if (likely(!ctx->le_mode)) {
2861 tcg_gen_bswap16_tl(arg1, arg1);
2862 }
2863 }
2864 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2865
2866 /* lwbrx */
2867 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2868 {
2869 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2870 if (likely(!ctx->le_mode)) {
2871 tcg_gen_bswap32_tl(arg1, arg1);
2872 }
2873 }
2874 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2875
2876 #if defined(TARGET_PPC64)
2877 /* ldbrx */
2878 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2879 {
2880 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2881 if (likely(!ctx->le_mode)) {
2882 tcg_gen_bswap64_tl(arg1, arg1);
2883 }
2884 }
2885 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2886 #endif /* TARGET_PPC64 */
2887
2888 /* sthbrx */
2889 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2890 {
2891 if (likely(!ctx->le_mode)) {
2892 TCGv t0 = tcg_temp_new();
2893 tcg_gen_ext16u_tl(t0, arg1);
2894 tcg_gen_bswap16_tl(t0, t0);
2895 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2896 tcg_temp_free(t0);
2897 } else {
2898 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2899 }
2900 }
2901 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2902
2903 /* stwbrx */
2904 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2905 {
2906 if (likely(!ctx->le_mode)) {
2907 TCGv t0 = tcg_temp_new();
2908 tcg_gen_ext32u_tl(t0, arg1);
2909 tcg_gen_bswap32_tl(t0, t0);
2910 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2911 tcg_temp_free(t0);
2912 } else {
2913 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2914 }
2915 }
2916 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2917
2918 #if defined(TARGET_PPC64)
2919 /* stdbrx */
2920 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2921 {
2922 if (likely(!ctx->le_mode)) {
2923 TCGv t0 = tcg_temp_new();
2924 tcg_gen_bswap64_tl(t0, arg1);
2925 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2926 tcg_temp_free(t0);
2927 } else {
2928 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2929 }
2930 }
2931 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2932 #endif /* TARGET_PPC64 */
2933
2934 /*** Integer load and store multiple ***/
2935
2936 /* lmw */
2937 static void gen_lmw(DisasContext *ctx)
2938 {
2939 TCGv t0;
2940 TCGv_i32 t1;
2941 gen_set_access_type(ctx, ACCESS_INT);
2942 /* NIP cannot be restored if the memory exception comes from an helper */
2943 gen_update_nip(ctx, ctx->nip - 4);
2944 t0 = tcg_temp_new();
2945 t1 = tcg_const_i32(rD(ctx->opcode));
2946 gen_addr_imm_index(ctx, t0, 0);
2947 gen_helper_lmw(cpu_env, t0, t1);
2948 tcg_temp_free(t0);
2949 tcg_temp_free_i32(t1);
2950 }
2951
2952 /* stmw */
2953 static void gen_stmw(DisasContext *ctx)
2954 {
2955 TCGv t0;
2956 TCGv_i32 t1;
2957 gen_set_access_type(ctx, ACCESS_INT);
2958 /* NIP cannot be restored if the memory exception comes from an helper */
2959 gen_update_nip(ctx, ctx->nip - 4);
2960 t0 = tcg_temp_new();
2961 t1 = tcg_const_i32(rS(ctx->opcode));
2962 gen_addr_imm_index(ctx, t0, 0);
2963 gen_helper_stmw(cpu_env, t0, t1);
2964 tcg_temp_free(t0);
2965 tcg_temp_free_i32(t1);
2966 }
2967
2968 /*** Integer load and store strings ***/
2969
2970 /* lswi */
2971 /* PowerPC32 specification says we must generate an exception if
2972 * rA is in the range of registers to be loaded.
2973 * In an other hand, IBM says this is valid, but rA won't be loaded.
2974 * For now, I'll follow the spec...
2975 */
2976 static void gen_lswi(DisasContext *ctx)
2977 {
2978 TCGv t0;
2979 TCGv_i32 t1, t2;
2980 int nb = NB(ctx->opcode);
2981 int start = rD(ctx->opcode);
2982 int ra = rA(ctx->opcode);
2983 int nr;
2984
2985 if (nb == 0)
2986 nb = 32;
2987 nr = nb / 4;
2988 if (unlikely(((start + nr) > 32 &&
2989 start <= ra && (start + nr - 32) > ra) ||
2990 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2991 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2992 return;
2993 }
2994 gen_set_access_type(ctx, ACCESS_INT);
2995 /* NIP cannot be restored if the memory exception comes from an helper */
2996 gen_update_nip(ctx, ctx->nip - 4);
2997 t0 = tcg_temp_new();
2998 gen_addr_register(ctx, t0);
2999 t1 = tcg_const_i32(nb);
3000 t2 = tcg_const_i32(start);
3001 gen_helper_lsw(cpu_env, t0, t1, t2);
3002 tcg_temp_free(t0);
3003 tcg_temp_free_i32(t1);
3004 tcg_temp_free_i32(t2);
3005 }
3006
3007 /* lswx */
3008 static void gen_lswx(DisasContext *ctx)
3009 {
3010 TCGv t0;
3011 TCGv_i32 t1, t2, t3;
3012 gen_set_access_type(ctx, ACCESS_INT);
3013 /* NIP cannot be restored if the memory exception comes from an helper */
3014 gen_update_nip(ctx, ctx->nip - 4);
3015 t0 = tcg_temp_new();
3016 gen_addr_reg_index(ctx, t0);
3017 t1 = tcg_const_i32(rD(ctx->opcode));
3018 t2 = tcg_const_i32(rA(ctx->opcode));
3019 t3 = tcg_const_i32(rB(ctx->opcode));
3020 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3021 tcg_temp_free(t0);
3022 tcg_temp_free_i32(t1);
3023 tcg_temp_free_i32(t2);
3024 tcg_temp_free_i32(t3);
3025 }
3026
3027 /* stswi */
3028 static void gen_stswi(DisasContext *ctx)
3029 {
3030 TCGv t0;
3031 TCGv_i32 t1, t2;
3032 int nb = NB(ctx->opcode);
3033 gen_set_access_type(ctx, ACCESS_INT);
3034 /* NIP cannot be restored if the memory exception comes from an helper */
3035 gen_update_nip(ctx, ctx->nip - 4);
3036 t0 = tcg_temp_new();
3037 gen_addr_register(ctx, t0);
3038 if (nb == 0)
3039 nb = 32;
3040 t1 = tcg_const_i32(nb);
3041 t2 = tcg_const_i32(rS(ctx->opcode));
3042 gen_helper_stsw(cpu_env, t0, t1, t2);
3043 tcg_temp_free(t0);
3044 tcg_temp_free_i32(t1);
3045 tcg_temp_free_i32(t2);
3046 }
3047
3048 /* stswx */
3049 static void gen_stswx(DisasContext *ctx)
3050 {
3051 TCGv t0;
3052 TCGv_i32 t1, t2;
3053 gen_set_access_type(ctx, ACCESS_INT);
3054 /* NIP cannot be restored if the memory exception comes from an helper */
3055 gen_update_nip(ctx, ctx->nip - 4);
3056 t0 = tcg_temp_new();
3057 gen_addr_reg_index(ctx, t0);
3058 t1 = tcg_temp_new_i32();
3059 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3060 tcg_gen_andi_i32(t1, t1, 0x7F);
3061 t2 = tcg_const_i32(rS(ctx->opcode));
3062 gen_helper_stsw(cpu_env, t0, t1, t2);
3063 tcg_temp_free(t0);
3064 tcg_temp_free_i32(t1);
3065 tcg_temp_free_i32(t2);
3066 }
3067
3068 /*** Memory synchronisation ***/
3069 /* eieio */
3070 static void gen_eieio(DisasContext *ctx)
3071 {
3072 }
3073
3074 /* isync */
3075 static void gen_isync(DisasContext *ctx)
3076 {
3077 gen_stop_exception(ctx);
3078 }
3079
3080 /* lwarx */
3081 static void gen_lwarx(DisasContext *ctx)
3082 {
3083 TCGv t0;
3084 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3085 gen_set_access_type(ctx, ACCESS_RES);
3086 t0 = tcg_temp_local_new();
3087 gen_addr_reg_index(ctx, t0);
3088 gen_check_align(ctx, t0, 0x03);
3089 gen_qemu_ld32u(ctx, gpr, t0);
3090 tcg_gen_mov_tl(cpu_reserve, t0);
3091 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3092 tcg_temp_free(t0);
3093 }
3094
3095 #if defined(CONFIG_USER_ONLY)
3096 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3097 int reg, int size)
3098 {
3099 TCGv t0 = tcg_temp_new();
3100 uint32_t save_exception = ctx->exception;
3101
3102 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3103 tcg_gen_movi_tl(t0, (size << 5) | reg);
3104 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3105 tcg_temp_free(t0);
3106 gen_update_nip(ctx, ctx->nip-4);
3107 ctx->exception = POWERPC_EXCP_BRANCH;
3108 gen_exception(ctx, POWERPC_EXCP_STCX);
3109 ctx->exception = save_exception;
3110 }
3111 #endif
3112
3113 /* stwcx. */
3114 static void gen_stwcx_(DisasContext *ctx)
3115 {
3116 TCGv t0;
3117 gen_set_access_type(ctx, ACCESS_RES);
3118 t0 = tcg_temp_local_new();
3119 gen_addr_reg_index(ctx, t0);
3120 gen_check_align(ctx, t0, 0x03);
3121 #if defined(CONFIG_USER_ONLY)
3122 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3123 #else
3124 {
3125 int l1;
3126
3127 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3128 l1 = gen_new_label();
3129 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3130 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3131 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3132 gen_set_label(l1);
3133 tcg_gen_movi_tl(cpu_reserve, -1);
3134 }
3135 #endif
3136 tcg_temp_free(t0);
3137 }
3138
3139 #if defined(TARGET_PPC64)
3140 /* ldarx */
3141 static void gen_ldarx(DisasContext *ctx)
3142 {
3143 TCGv t0;
3144 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3145 gen_set_access_type(ctx, ACCESS_RES);
3146 t0 = tcg_temp_local_new();
3147 gen_addr_reg_index(ctx, t0);
3148 gen_check_align(ctx, t0, 0x07);
3149 gen_qemu_ld64(ctx, gpr, t0);
3150 tcg_gen_mov_tl(cpu_reserve, t0);
3151 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3152 tcg_temp_free(t0);
3153 }
3154
3155 /* stdcx. */
3156 static void gen_stdcx_(DisasContext *ctx)
3157 {
3158 TCGv t0;
3159 gen_set_access_type(ctx, ACCESS_RES);
3160 t0 = tcg_temp_local_new();
3161 gen_addr_reg_index(ctx, t0);
3162 gen_check_align(ctx, t0, 0x07);
3163 #if defined(CONFIG_USER_ONLY)
3164 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3165 #else
3166 {
3167 int l1;
3168 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3169 l1 = gen_new_label();
3170 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3171 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3172 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3173 gen_set_label(l1);
3174 tcg_gen_movi_tl(cpu_reserve, -1);
3175 }
3176 #endif
3177 tcg_temp_free(t0);
3178 }
3179 #endif /* defined(TARGET_PPC64) */
3180
3181 /* sync */
3182 static void gen_sync(DisasContext *ctx)
3183 {
3184 }
3185
3186 /* wait */
3187 static void gen_wait(DisasContext *ctx)
3188 {
3189 TCGv_i32 t0 = tcg_temp_new_i32();
3190 tcg_gen_st_i32(t0, cpu_env,
3191 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3192 tcg_temp_free_i32(t0);
3193 /* Stop translation, as the CPU is supposed to sleep from now */
3194 gen_exception_err(ctx, EXCP_HLT, 1);
3195 }
3196
3197 /*** Floating-point load ***/
3198 #define GEN_LDF(name, ldop, opc, type) \
3199 static void glue(gen_, name)(DisasContext *ctx) \
3200 { \
3201 TCGv EA; \
3202 if (unlikely(!ctx->fpu_enabled)) { \
3203 gen_exception(ctx, POWERPC_EXCP_FPU); \
3204 return; \
3205 } \
3206 gen_set_access_type(ctx, ACCESS_FLOAT); \
3207 EA = tcg_temp_new(); \
3208 gen_addr_imm_index(ctx, EA, 0); \
3209 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3210 tcg_temp_free(EA); \
3211 }
3212
3213 #define GEN_LDUF(name, ldop, opc, type) \
3214 static void glue(gen_, name##u)(DisasContext *ctx) \
3215 { \
3216 TCGv EA; \
3217 if (unlikely(!ctx->fpu_enabled)) { \
3218 gen_exception(ctx, POWERPC_EXCP_FPU); \
3219 return; \
3220 } \
3221 if (unlikely(rA(ctx->opcode) == 0)) { \
3222 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3223 return; \
3224 } \
3225 gen_set_access_type(ctx, ACCESS_FLOAT); \
3226 EA = tcg_temp_new(); \
3227 gen_addr_imm_index(ctx, EA, 0); \
3228 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3229 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3230 tcg_temp_free(EA); \
3231 }
3232
3233 #define GEN_LDUXF(name, ldop, opc, type) \
3234 static void glue(gen_, name##ux)(DisasContext *ctx) \
3235 { \
3236 TCGv EA; \
3237 if (unlikely(!ctx->fpu_enabled)) { \
3238 gen_exception(ctx, POWERPC_EXCP_FPU); \
3239 return; \
3240 } \
3241 if (unlikely(rA(ctx->opcode) == 0)) { \
3242 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3243 return; \
3244 } \
3245 gen_set_access_type(ctx, ACCESS_FLOAT); \
3246 EA = tcg_temp_new(); \
3247 gen_addr_reg_index(ctx, EA); \
3248 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3249 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3250 tcg_temp_free(EA); \
3251 }
3252
3253 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3254 static void glue(gen_, name##x)(DisasContext *ctx) \
3255 { \
3256 TCGv EA; \
3257 if (unlikely(!ctx->fpu_enabled)) { \
3258 gen_exception(ctx, POWERPC_EXCP_FPU); \
3259 return; \
3260 } \
3261 gen_set_access_type(ctx, ACCESS_FLOAT); \
3262 EA = tcg_temp_new(); \
3263 gen_addr_reg_index(ctx, EA); \
3264 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3265 tcg_temp_free(EA); \
3266 }
3267
3268 #define GEN_LDFS(name, ldop, op, type) \
3269 GEN_LDF(name, ldop, op | 0x20, type); \
3270 GEN_LDUF(name, ldop, op | 0x21, type); \
3271 GEN_LDUXF(name, ldop, op | 0x01, type); \
3272 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3273
3274 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3275 {
3276 TCGv t0 = tcg_temp_new();
3277 TCGv_i32 t1 = tcg_temp_new_i32();
3278 gen_qemu_ld32u(ctx, t0, arg2);
3279 tcg_gen_trunc_tl_i32(t1, t0);
3280 tcg_temp_free(t0);
3281 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3282 tcg_temp_free_i32(t1);
3283 }
3284
3285 /* lfd lfdu lfdux lfdx */
3286 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3287 /* lfs lfsu lfsux lfsx */
3288 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3289
3290 /*** Floating-point store ***/
3291 #define GEN_STF(name, stop, opc, type) \
3292 static void glue(gen_, name)(DisasContext *ctx) \
3293 { \
3294 TCGv EA; \
3295 if (unlikely(!ctx->fpu_enabled)) { \
3296 gen_exception(ctx, POWERPC_EXCP_FPU); \
3297 return; \
3298 } \
3299 gen_set_access_type(ctx, ACCESS_FLOAT); \
3300 EA = tcg_temp_new(); \
3301 gen_addr_imm_index(ctx, EA, 0); \
3302 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3303 tcg_temp_free(EA); \
3304 }
3305
3306 #define GEN_STUF(name, stop, opc, type) \
3307 static void glue(gen_, name##u)(DisasContext *ctx) \
3308 { \
3309 TCGv EA; \
3310 if (unlikely(!ctx->fpu_enabled)) { \
3311 gen_exception(ctx, POWERPC_EXCP_FPU); \
3312 return; \
3313 } \
3314 if (unlikely(rA(ctx->opcode) == 0)) { \
3315 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3316 return; \
3317 } \
3318 gen_set_access_type(ctx, ACCESS_FLOAT); \
3319 EA = tcg_temp_new(); \
3320 gen_addr_imm_index(ctx, EA, 0); \
3321 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3322 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3323 tcg_temp_free(EA); \
3324 }
3325
3326 #define GEN_STUXF(name, stop, opc, type) \
3327 static void glue(gen_, name##ux)(DisasContext *ctx) \
3328 { \
3329 TCGv EA; \
3330 if (unlikely(!ctx->fpu_enabled)) { \
3331 gen_exception(ctx, POWERPC_EXCP_FPU); \
3332 return; \
3333 } \
3334 if (unlikely(rA(ctx->opcode) == 0)) { \
3335 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3336 return; \
3337 } \
3338 gen_set_access_type(ctx, ACCESS_FLOAT); \
3339 EA = tcg_temp_new(); \
3340 gen_addr_reg_index(ctx, EA); \
3341 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3342 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3343 tcg_temp_free(EA); \
3344 }
3345
3346 #define GEN_STXF(name, stop, opc2, opc3, type) \
3347 static void glue(gen_, name##x)(DisasContext *ctx) \
3348 { \
3349 TCGv EA; \
3350 if (unlikely(!ctx->fpu_enabled)) { \
3351 gen_exception(ctx, POWERPC_EXCP_FPU); \
3352 return; \
3353 } \
3354 gen_set_access_type(ctx, ACCESS_FLOAT); \
3355 EA = tcg_temp_new(); \
3356 gen_addr_reg_index(ctx, EA); \
3357 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3358 tcg_temp_free(EA); \
3359 }
3360
3361 #define GEN_STFS(name, stop, op, type) \
3362 GEN_STF(name, stop, op | 0x20, type); \
3363 GEN_STUF(name, stop, op | 0x21, type); \
3364 GEN_STUXF(name, stop, op | 0x01, type); \
3365 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3366
3367 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3368 {
3369 TCGv_i32 t0 = tcg_temp_new_i32();
3370 TCGv t1 = tcg_temp_new();
3371 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3372 tcg_gen_extu_i32_tl(t1, t0);
3373 tcg_temp_free_i32(t0);
3374 gen_qemu_st32(ctx, t1, arg2);
3375 tcg_temp_free(t1);
3376 }
3377
3378 /* stfd stfdu stfdux stfdx */
3379 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3380 /* stfs stfsu stfsux stfsx */
3381 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3382
3383 /* Optional: */
3384 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3385 {
3386 TCGv t0 = tcg_temp_new();
3387 tcg_gen_trunc_i64_tl(t0, arg1),
3388 gen_qemu_st32(ctx, t0, arg2);
3389 tcg_temp_free(t0);
3390 }
3391 /* stfiwx */
3392 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3393
3394 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3395 {
3396 #if defined(TARGET_PPC64)
3397 if (ctx->has_cfar)
3398 tcg_gen_movi_tl(cpu_cfar, nip);
3399 #endif
3400 }
3401
3402 /*** Branch ***/
3403 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3404 {
3405 TranslationBlock *tb;
3406 tb = ctx->tb;
3407 if (NARROW_MODE(ctx)) {
3408 dest = (uint32_t) dest;
3409 }
3410 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3411 likely(!ctx->singlestep_enabled)) {
3412 tcg_gen_goto_tb(n);
3413 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3414 tcg_gen_exit_tb((tcg_target_long)tb + n);
3415 } else {
3416 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3417 if (unlikely(ctx->singlestep_enabled)) {
3418 if ((ctx->singlestep_enabled &
3419 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3420 (ctx->exception == POWERPC_EXCP_BRANCH ||
3421 ctx->exception == POWERPC_EXCP_TRACE)) {
3422 target_ulong tmp = ctx->nip;
3423 ctx->nip = dest;
3424 gen_exception(ctx, POWERPC_EXCP_TRACE);
3425 ctx->nip = tmp;
3426 }
3427 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3428 gen_debug_exception(ctx);
3429 }
3430 }
3431 tcg_gen_exit_tb(0);
3432 }
3433 }
3434
3435 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3436 {
3437 if (NARROW_MODE(ctx)) {
3438 nip = (uint32_t)nip;
3439 }
3440 tcg_gen_movi_tl(cpu_lr, nip);
3441 }
3442
3443 /* b ba bl bla */
3444 static void gen_b(DisasContext *ctx)
3445 {
3446 target_ulong li, target;
3447
3448 ctx->exception = POWERPC_EXCP_BRANCH;
3449 /* sign extend LI */
3450 li = LI(ctx->opcode);
3451 li = (li ^ 0x02000000) - 0x02000000;
3452 if (likely(AA(ctx->opcode) == 0)) {
3453 target = ctx->nip + li - 4;
3454 } else {
3455 target = li;
3456 }
3457 if (LK(ctx->opcode)) {
3458 gen_setlr(ctx, ctx->nip);
3459 }
3460 gen_update_cfar(ctx, ctx->nip);
3461 gen_goto_tb(ctx, 0, target);
3462 }
3463
3464 #define BCOND_IM 0
3465 #define BCOND_LR 1
3466 #define BCOND_CTR 2
3467
3468 static inline void gen_bcond(DisasContext *ctx, int type)
3469 {
3470 uint32_t bo = BO(ctx->opcode);
3471 int l1;
3472 TCGv target;
3473
3474 ctx->exception = POWERPC_EXCP_BRANCH;
3475 if (type == BCOND_LR || type == BCOND_CTR) {
3476 target = tcg_temp_local_new();
3477 if (type == BCOND_CTR)
3478 tcg_gen_mov_tl(target, cpu_ctr);
3479 else
3480 tcg_gen_mov_tl(target, cpu_lr);
3481 } else {
3482 TCGV_UNUSED(target);
3483 }
3484 if (LK(ctx->opcode))
3485 gen_setlr(ctx, ctx->nip);
3486 l1 = gen_new_label();
3487 if ((bo & 0x4) == 0) {
3488 /* Decrement and test CTR */
3489 TCGv temp = tcg_temp_new();
3490 if (unlikely(type == BCOND_CTR)) {
3491 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3492 return;
3493 }
3494 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3495 if (NARROW_MODE(ctx)) {
3496 tcg_gen_ext32u_tl(temp, cpu_ctr);
3497 } else {
3498 tcg_gen_mov_tl(temp, cpu_ctr);
3499 }
3500 if (bo & 0x2) {
3501 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3502 } else {
3503 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3504 }
3505 tcg_temp_free(temp);
3506 }
3507 if ((bo & 0x10) == 0) {
3508 /* Test CR */
3509 uint32_t bi = BI(ctx->opcode);
3510 uint32_t mask = 1 << (3 - (bi & 0x03));
3511 TCGv_i32 temp = tcg_temp_new_i32();
3512
3513 if (bo & 0x8) {
3514 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3515 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3516 } else {
3517 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3518 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3519 }
3520 tcg_temp_free_i32(temp);
3521 }
3522 gen_update_cfar(ctx, ctx->nip);
3523 if (type == BCOND_IM) {
3524 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3525 if (likely(AA(ctx->opcode) == 0)) {
3526 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3527 } else {
3528 gen_goto_tb(ctx, 0, li);
3529 }
3530 gen_set_label(l1);
3531 gen_goto_tb(ctx, 1, ctx->nip);
3532 } else {
3533 if (NARROW_MODE(ctx)) {
3534 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3535 } else {
3536 tcg_gen_andi_tl(cpu_nip, target, ~3);
3537 }
3538 tcg_gen_exit_tb(0);
3539 gen_set_label(l1);
3540 gen_update_nip(ctx, ctx->nip);
3541 tcg_gen_exit_tb(0);
3542 }
3543 }
3544
3545 static void gen_bc(DisasContext *ctx)
3546 {
3547 gen_bcond(ctx, BCOND_IM);
3548 }
3549
3550 static void gen_bcctr(DisasContext *ctx)
3551 {
3552 gen_bcond(ctx, BCOND_CTR);
3553 }
3554
3555 static void gen_bclr(DisasContext *ctx)
3556 {
3557 gen_bcond(ctx, BCOND_LR);
3558 }
3559
3560 /*** Condition register logical ***/
3561 #define GEN_CRLOGIC(name, tcg_op, opc) \
3562 static void glue(gen_, name)(DisasContext *ctx) \
3563 { \
3564 uint8_t bitmask; \
3565 int sh; \
3566 TCGv_i32 t0, t1; \
3567 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3568 t0 = tcg_temp_new_i32(); \
3569 if (sh > 0) \
3570 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3571 else if (sh < 0) \
3572 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3573 else \
3574 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3575 t1 = tcg_temp_new_i32(); \
3576 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3577 if (sh > 0) \
3578 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3579 else if (sh < 0) \
3580 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3581 else \
3582 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3583 tcg_op(t0, t0, t1); \
3584 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3585 tcg_gen_andi_i32(t0, t0, bitmask); \
3586 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3587 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3588 tcg_temp_free_i32(t0); \
3589 tcg_temp_free_i32(t1); \
3590 }
3591
3592 /* crand */
3593 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3594 /* crandc */
3595 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3596 /* creqv */
3597 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3598 /* crnand */
3599 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3600 /* crnor */
3601 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3602 /* cror */
3603 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3604 /* crorc */
3605 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3606 /* crxor */
3607 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3608
3609 /* mcrf */
3610 static void gen_mcrf(DisasContext *ctx)
3611 {
3612 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3613 }
3614
3615 /*** System linkage ***/
3616
3617 /* rfi (mem_idx only) */
3618 static void gen_rfi(DisasContext *ctx)
3619 {
3620 #if defined(CONFIG_USER_ONLY)
3621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3622 #else
3623 /* Restore CPU state */
3624 if (unlikely(!ctx->mem_idx)) {
3625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3626 return;
3627 }
3628 gen_update_cfar(ctx, ctx->nip);
3629 gen_helper_rfi(cpu_env);
3630 gen_sync_exception(ctx);
3631 #endif
3632 }
3633
3634 #if defined(TARGET_PPC64)
3635 static void gen_rfid(DisasContext *ctx)
3636 {
3637 #if defined(CONFIG_USER_ONLY)
3638 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3639 #else
3640 /* Restore CPU state */
3641 if (unlikely(!ctx->mem_idx)) {
3642 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3643 return;
3644 }
3645 gen_update_cfar(ctx, ctx->nip);
3646 gen_helper_rfid(cpu_env);
3647 gen_sync_exception(ctx);
3648 #endif
3649 }
3650
3651 static void gen_hrfid(DisasContext *ctx)
3652 {
3653 #if defined(CONFIG_USER_ONLY)
3654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3655 #else
3656 /* Restore CPU state */
3657 if (unlikely(ctx->mem_idx <= 1)) {
3658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3659 return;
3660 }
3661 gen_helper_hrfid(cpu_env);
3662 gen_sync_exception(ctx);
3663 #endif
3664 }
3665 #endif
3666
3667 /* sc */
3668 #if defined(CONFIG_USER_ONLY)
3669 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3670 #else
3671 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3672 #endif
3673 static void gen_sc(DisasContext *ctx)
3674 {
3675 uint32_t lev;
3676
3677 lev = (ctx->opcode >> 5) & 0x7F;
3678 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3679 }
3680
3681 /*** Trap ***/
3682
3683 /* tw */
3684 static void gen_tw(DisasContext *ctx)
3685 {
3686 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3687 /* Update the nip since this might generate a trap exception */
3688 gen_update_nip(ctx, ctx->nip);
3689 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3690 t0);
3691 tcg_temp_free_i32(t0);
3692 }
3693
3694 /* twi */
3695 static void gen_twi(DisasContext *ctx)
3696 {
3697 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3698 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3699 /* Update the nip since this might generate a trap exception */
3700 gen_update_nip(ctx, ctx->nip);
3701 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3702 tcg_temp_free(t0);
3703 tcg_temp_free_i32(t1);
3704 }
3705
3706 #if defined(TARGET_PPC64)
3707 /* td */
3708 static void gen_td(DisasContext *ctx)
3709 {
3710 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3711 /* Update the nip since this might generate a trap exception */
3712 gen_update_nip(ctx, ctx->nip);
3713 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3714 t0);
3715 tcg_temp_free_i32(t0);
3716 }
3717
3718 /* tdi */
3719 static void gen_tdi(DisasContext *ctx)
3720 {
3721 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3722 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3723 /* Update the nip since this might generate a trap exception */
3724 gen_update_nip(ctx, ctx->nip);
3725 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3726 tcg_temp_free(t0);
3727 tcg_temp_free_i32(t1);
3728 }
3729 #endif
3730
3731 /*** Processor control ***/
3732
3733 static void gen_read_xer(TCGv dst)
3734 {
3735 TCGv t0 = tcg_temp_new();
3736 TCGv t1 = tcg_temp_new();
3737 TCGv t2 = tcg_temp_new();
3738 tcg_gen_mov_tl(dst, cpu_xer);
3739 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3740 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3741 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3742 tcg_gen_or_tl(t0, t0, t1);
3743 tcg_gen_or_tl(dst, dst, t2);
3744 tcg_gen_or_tl(dst, dst, t0);
3745 tcg_temp_free(t0);
3746 tcg_temp_free(t1);
3747 tcg_temp_free(t2);
3748 }
3749
3750 static void gen_write_xer(TCGv src)
3751 {
3752 tcg_gen_andi_tl(cpu_xer, src,
3753 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3754 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3755 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3756 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3757 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3758 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3759 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3760 }
3761
3762 /* mcrxr */
3763 static void gen_mcrxr(DisasContext *ctx)
3764 {
3765 TCGv_i32 t0 = tcg_temp_new_i32();
3766 TCGv_i32 t1 = tcg_temp_new_i32();
3767 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3768
3769 tcg_gen_trunc_tl_i32(t0, cpu_so);
3770 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3771 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3772 tcg_gen_shri_i32(t0, t0, 2);
3773 tcg_gen_shri_i32(t1, t1, 1);
3774 tcg_gen_or_i32(dst, dst, t0);
3775 tcg_gen_or_i32(dst, dst, t1);
3776 tcg_temp_free_i32(t0);
3777 tcg_temp_free_i32(t1);
3778
3779 tcg_gen_movi_tl(cpu_so, 0);
3780 tcg_gen_movi_tl(cpu_ov, 0);
3781 tcg_gen_movi_tl(cpu_ca, 0);
3782 }
3783
3784 /* mfcr mfocrf */
3785 static void gen_mfcr(DisasContext *ctx)
3786 {
3787 uint32_t crm, crn;
3788
3789 if (likely(ctx->opcode & 0x00100000)) {
3790 crm = CRM(ctx->opcode);
3791 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3792 crn = ctz32 (crm);
3793 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3794 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3795 cpu_gpr[rD(ctx->opcode)], crn * 4);
3796 }
3797 } else {
3798 TCGv_i32 t0 = tcg_temp_new_i32();
3799 tcg_gen_mov_i32(t0, cpu_crf[0]);
3800 tcg_gen_shli_i32(t0, t0, 4);
3801 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3802 tcg_gen_shli_i32(t0, t0, 4);
3803 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3804 tcg_gen_shli_i32(t0, t0, 4);
3805 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3806 tcg_gen_shli_i32(t0, t0, 4);
3807 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3808 tcg_gen_shli_i32(t0, t0, 4);
3809 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3810 tcg_gen_shli_i32(t0, t0, 4);
3811 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3812 tcg_gen_shli_i32(t0, t0, 4);
3813 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3814 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3815 tcg_temp_free_i32(t0);
3816 }
3817 }
3818
3819 /* mfmsr */
3820 static void gen_mfmsr(DisasContext *ctx)
3821 {
3822 #if defined(CONFIG_USER_ONLY)
3823 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3824 #else
3825 if (unlikely(!ctx->mem_idx)) {
3826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3827 return;
3828 }
3829 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3830 #endif
3831 }
3832
3833 static void spr_noaccess(void *opaque, int gprn, int sprn)
3834 {
3835 #if 0
3836 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3837 printf("ERROR: try to access SPR %d !\n", sprn);
3838 #endif
3839 }
3840 #define SPR_NOACCESS (&spr_noaccess)
3841
3842 /* mfspr */
3843 static inline void gen_op_mfspr(DisasContext *ctx)
3844 {
3845 void (*read_cb)(void *opaque, int gprn, int sprn);
3846 uint32_t sprn = SPR(ctx->opcode);
3847
3848 #if !defined(CONFIG_USER_ONLY)
3849 if (ctx->mem_idx == 2)
3850 read_cb = ctx->spr_cb[sprn].hea_read;
3851 else if (ctx->mem_idx)
3852 read_cb = ctx->spr_cb[sprn].oea_read;
3853 else
3854 #endif
3855 read_cb = ctx->spr_cb[sprn].uea_read;
3856 if (likely(read_cb != NULL)) {
3857 if (likely(read_cb != SPR_NOACCESS)) {
3858 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3859 } else {
3860 /* Privilege exception */
3861 /* This is a hack to avoid warnings when running Linux:
3862 * this OS breaks the PowerPC virtualisation model,
3863 * allowing userland application to read the PVR
3864 */
3865 if (sprn != SPR_PVR) {
3866 qemu_log("Trying to read privileged spr %d %03x at "
3867 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3868 printf("Trying to read privileged spr %d %03x at "
3869 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3870 }
3871 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3872 }
3873 } else {
3874 /* Not defined */
3875 qemu_log("Trying to read invalid spr %d %03x at "
3876 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3877 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3878 sprn, sprn, ctx->nip);
3879 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3880 }
3881 }
3882
3883 static void gen_mfspr(DisasContext *ctx)
3884 {
3885 gen_op_mfspr(ctx);
3886 }
3887
3888 /* mftb */
3889 static void gen_mftb(DisasContext *ctx)
3890 {
3891 gen_op_mfspr(ctx);
3892 }
3893
3894 /* mtcrf mtocrf*/
3895 static void gen_mtcrf(DisasContext *ctx)
3896 {
3897 uint32_t crm, crn;
3898
3899 crm = CRM(ctx->opcode);
3900 if (likely((ctx->opcode & 0x00100000))) {
3901 if (crm && ((crm & (crm - 1)) == 0)) {
3902 TCGv_i32 temp = tcg_temp_new_i32();
3903 crn = ctz32 (crm);
3904 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3905 tcg_gen_shri_i32(temp, temp, crn * 4);
3906 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3907 tcg_temp_free_i32(temp);
3908 }
3909 } else {
3910 TCGv_i32 temp = tcg_temp_new_i32();
3911 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3912 for (crn = 0 ; crn < 8 ; crn++) {
3913 if (crm & (1 << crn)) {
3914 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3915 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3916 }
3917 }
3918 tcg_temp_free_i32(temp);
3919 }
3920 }
3921
3922 /* mtmsr */
3923 #if defined(TARGET_PPC64)
3924 static void gen_mtmsrd(DisasContext *ctx)
3925 {
3926 #if defined(CONFIG_USER_ONLY)
3927 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3928 #else
3929 if (unlikely(!ctx->mem_idx)) {
3930 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3931 return;
3932 }
3933 if (ctx->opcode & 0x00010000) {
3934 /* Special form that does not need any synchronisation */
3935 TCGv t0 = tcg_temp_new();
3936 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3937 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3938 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3939 tcg_temp_free(t0);
3940 } else {
3941 /* XXX: we need to update nip before the store
3942 * if we enter power saving mode, we will exit the loop
3943 * directly from ppc_store_msr
3944 */
3945 gen_update_nip(ctx, ctx->nip);
3946 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3947 /* Must stop the translation as machine state (may have) changed */
3948 /* Note that mtmsr is not always defined as context-synchronizing */
3949 gen_stop_exception(ctx);
3950 }
3951 #endif
3952 }
3953 #endif
3954
3955 static void gen_mtmsr(DisasContext *ctx)
3956 {
3957 #if defined(CONFIG_USER_ONLY)
3958 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3959 #else
3960 if (unlikely(!ctx->mem_idx)) {
3961 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3962 return;
3963 }
3964 if (ctx->opcode & 0x00010000) {
3965 /* Special form that does not need any synchronisation */
3966 TCGv t0 = tcg_temp_new();
3967 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3968 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3969 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3970 tcg_temp_free(t0);
3971 } else {
3972 TCGv msr = tcg_temp_new();
3973
3974 /* XXX: we need to update nip before the store
3975 * if we enter power saving mode, we will exit the loop
3976 * directly from ppc_store_msr
3977 */
3978 gen_update_nip(ctx, ctx->nip);
3979 #if defined(TARGET_PPC64)
3980 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3981 #else
3982 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3983 #endif
3984 gen_helper_store_msr(cpu_env, msr);
3985 /* Must stop the translation as machine state (may have) changed */
3986 /* Note that mtmsr is not always defined as context-synchronizing */
3987 gen_stop_exception(ctx);
3988 }
3989 #endif
3990 }
3991
3992 /* mtspr */
3993 static void gen_mtspr(DisasContext *ctx)
3994 {
3995 void (*write_cb)(void *opaque, int sprn, int gprn);
3996 uint32_t sprn = SPR(ctx->opcode);
3997
3998 #if !defined(CONFIG_USER_ONLY)
3999 if (ctx->mem_idx == 2)
4000 write_cb = ctx->spr_cb[sprn].hea_write;
4001 else if (ctx->mem_idx)
4002 write_cb = ctx->spr_cb[sprn].oea_write;
4003 else
4004 #endif
4005 write_cb = ctx->spr_cb[sprn].uea_write;
4006 if (likely(write_cb != NULL)) {
4007 if (likely(write_cb != SPR_NOACCESS)) {
4008 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4009 } else {
4010 /* Privilege exception */
4011 qemu_log("Trying to write privileged spr %d %03x at "
4012 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4013 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
4014 "\n", sprn, sprn, ctx->nip);
4015 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4016 }
4017 } else {
4018 /* Not defined */
4019 qemu_log("Trying to write invalid spr %d %03x at "
4020 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4021 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
4022 sprn, sprn, ctx->nip);
4023 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4024 }
4025 }
4026
4027 /*** Cache management ***/
4028
4029 /* dcbf */
4030 static void gen_dcbf(DisasContext *ctx)
4031 {
4032 /* XXX: specification says this is treated as a load by the MMU */
4033 TCGv t0;
4034 gen_set_access_type(ctx, ACCESS_CACHE);
4035 t0 = tcg_temp_new();
4036 gen_addr_reg_index(ctx, t0);
4037 gen_qemu_ld8u(ctx, t0, t0);
4038 tcg_temp_free(t0);
4039 }
4040
4041 /* dcbi (Supervisor only) */
4042 static void gen_dcbi(DisasContext *ctx)
4043 {
4044 #if defined(CONFIG_USER_ONLY)
4045 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4046 #else
4047 TCGv EA, val;
4048 if (unlikely(!ctx->mem_idx)) {
4049 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4050 return;
4051 }
4052 EA = tcg_temp_new();
4053 gen_set_access_type(ctx, ACCESS_CACHE);
4054 gen_addr_reg_index(ctx, EA);
4055 val = tcg_temp_new();
4056 /* XXX: specification says this should be treated as a store by the MMU */
4057 gen_qemu_ld8u(ctx, val, EA);
4058 gen_qemu_st8(ctx, val, EA);
4059 tcg_temp_free(val);
4060 tcg_temp_free(EA);
4061 #endif
4062 }
4063
4064 /* dcdst */
4065 static void gen_dcbst(DisasContext *ctx)
4066 {
4067 /* XXX: specification say this is treated as a load by the MMU */
4068 TCGv t0;
4069 gen_set_access_type(ctx, ACCESS_CACHE);
4070 t0 = tcg_temp_new();
4071 gen_addr_reg_index(ctx, t0);
4072 gen_qemu_ld8u(ctx, t0, t0);
4073 tcg_temp_free(t0);
4074 }
4075
4076 /* dcbt */
4077 static void gen_dcbt(DisasContext *ctx)
4078 {
4079 /* interpreted as no-op */
4080 /* XXX: specification say this is treated as a load by the MMU
4081 * but does not generate any exception
4082 */
4083 }
4084
4085 /* dcbtst */
4086 static void gen_dcbtst(DisasContext *ctx)
4087 {
4088 /* interpreted as no-op */
4089 /* XXX: specification say this is treated as a load by the MMU
4090 * but does not generate any exception
4091 */
4092 }
4093
4094 /* dcbz */
4095 static void gen_dcbz(DisasContext *ctx)
4096 {
4097 TCGv tcgv_addr;
4098 TCGv_i32 tcgv_is_dcbzl;
4099 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4100
4101 gen_set_access_type(ctx, ACCESS_CACHE);
4102 /* NIP cannot be restored if the memory exception comes from an helper */
4103 gen_update_nip(ctx, ctx->nip - 4);
4104 tcgv_addr = tcg_temp_new();
4105 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4106
4107 gen_addr_reg_index(ctx, tcgv_addr);
4108 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4109
4110 tcg_temp_free(tcgv_addr);
4111 tcg_temp_free_i32(tcgv_is_dcbzl);
4112 }
4113
4114 /* dst / dstt */
4115 static void gen_dst(DisasContext *ctx)
4116 {
4117 if (rA(ctx->opcode) == 0) {
4118 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4119 } else {
4120 /* interpreted as no-op */
4121 }
4122 }
4123
4124 /* dstst /dststt */
4125 static void gen_dstst(DisasContext *ctx)
4126 {
4127 if (rA(ctx->opcode) == 0) {
4128 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4129 } else {
4130 /* interpreted as no-op */
4131 }
4132
4133 }
4134
4135 /* dss / dssall */
4136 static void gen_dss(DisasContext *ctx)
4137 {
4138 /* interpreted as no-op */
4139 }
4140
4141 /* icbi */
4142 static void gen_icbi(DisasContext *ctx)
4143 {
4144 TCGv t0;
4145 gen_set_access_type(ctx, ACCESS_CACHE);
4146 /* NIP cannot be restored if the memory exception comes from an helper */
4147 gen_update_nip(ctx, ctx->nip - 4);
4148 t0 = tcg_temp_new();
4149 gen_addr_reg_index(ctx, t0);
4150 gen_helper_icbi(cpu_env, t0);
4151 tcg_temp_free(t0);
4152 }
4153
4154 /* Optional: */
4155 /* dcba */
4156 static void gen_dcba(DisasContext *ctx)
4157 {
4158 /* interpreted as no-op */
4159 /* XXX: specification say this is treated as a store by the MMU
4160 * but does not generate any exception
4161 */
4162 }
4163
4164 /*** Segment register manipulation ***/
4165 /* Supervisor only: */
4166
4167 /* mfsr */
4168 static void gen_mfsr(DisasContext *ctx)
4169 {
4170 #if defined(CONFIG_USER_ONLY)
4171 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4172 #else
4173 TCGv t0;
4174 if (unlikely(!ctx->mem_idx)) {
4175 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4176 return;
4177 }
4178 t0 = tcg_const_tl(SR(ctx->opcode));
4179 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4180 tcg_temp_free(t0);
4181 #endif
4182 }
4183
4184 /* mfsrin */
4185 static void gen_mfsrin(DisasContext *ctx)
4186 {
4187 #if defined(CONFIG_USER_ONLY)
4188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4189 #else
4190 TCGv t0;
4191 if (unlikely(!ctx->mem_idx)) {
4192 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4193 return;
4194 }
4195 t0 = tcg_temp_new();
4196 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4197 tcg_gen_andi_tl(t0, t0, 0xF);
4198 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4199 tcg_temp_free(t0);
4200 #endif
4201 }
4202
4203 /* mtsr */
4204 static void gen_mtsr(DisasContext *ctx)
4205 {
4206 #if defined(CONFIG_USER_ONLY)
4207 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4208 #else
4209 TCGv t0;
4210 if (unlikely(!ctx->mem_idx)) {
4211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4212 return;
4213 }
4214 t0 = tcg_const_tl(SR(ctx->opcode));
4215 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4216 tcg_temp_free(t0);
4217 #endif
4218 }
4219
4220 /* mtsrin */
4221 static void gen_mtsrin(DisasContext *ctx)
4222 {
4223 #if defined(CONFIG_USER_ONLY)
4224 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4225 #else
4226 TCGv t0;
4227 if (unlikely(!ctx->mem_idx)) {
4228 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4229 return;
4230 }
4231 t0 = tcg_temp_new();
4232 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4233 tcg_gen_andi_tl(t0, t0, 0xF);
4234 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4235 tcg_temp_free(t0);
4236 #endif
4237 }
4238
4239 #if defined(TARGET_PPC64)
4240 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4241
4242 /* mfsr */
4243 static void gen_mfsr_64b(DisasContext *ctx)
4244 {
4245 #if defined(CONFIG_USER_ONLY)
4246 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4247 #else
4248 TCGv t0;
4249 if (unlikely(!ctx->mem_idx)) {
4250 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4251 return;
4252 }
4253 t0 = tcg_const_tl(SR(ctx->opcode));
4254 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4255 tcg_temp_free(t0);
4256 #endif
4257 }
4258
4259 /* mfsrin */
4260 static void gen_mfsrin_64b(DisasContext *ctx)
4261 {
4262 #if defined(CONFIG_USER_ONLY)
4263 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4264 #else
4265 TCGv t0;
4266 if (unlikely(!ctx->mem_idx)) {
4267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4268 return;
4269 }
4270 t0 = tcg_temp_new();
4271 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4272 tcg_gen_andi_tl(t0, t0, 0xF);
4273 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4274 tcg_temp_free(t0);
4275 #endif
4276 }
4277
4278 /* mtsr */
4279 static void gen_mtsr_64b(DisasContext *ctx)
4280 {
4281 #if defined(CONFIG_USER_ONLY)
4282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4283 #else
4284 TCGv t0;
4285 if (unlikely(!ctx->mem_idx)) {
4286 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4287 return;
4288 }
4289 t0 = tcg_const_tl(SR(ctx->opcode));
4290 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4291 tcg_temp_free(t0);
4292 #endif
4293 }
4294
4295 /* mtsrin */
4296 static void gen_mtsrin_64b(DisasContext *ctx)
4297 {
4298 #if defined(CONFIG_USER_ONLY)
4299 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4300 #else
4301 TCGv t0;
4302 if (unlikely(!ctx->mem_idx)) {
4303 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4304 return;
4305 }
4306 t0 = tcg_temp_new();
4307 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4308 tcg_gen_andi_tl(t0, t0, 0xF);
4309 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4310 tcg_temp_free(t0);
4311 #endif
4312 }
4313
4314 /* slbmte */
4315 static void gen_slbmte(DisasContext *ctx)
4316 {
4317 #if defined(CONFIG_USER_ONLY)
4318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4319 #else
4320 if (unlikely(!ctx->mem_idx)) {
4321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4322 return;
4323 }
4324 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4325 cpu_gpr[rS(ctx->opcode)]);
4326 #endif
4327 }
4328
4329 static void gen_slbmfee(DisasContext *ctx)
4330 {
4331 #if defined(CONFIG_USER_ONLY)
4332 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4333 #else
4334 if (unlikely(!ctx->mem_idx)) {
4335 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4336 return;
4337 }
4338 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4339 cpu_gpr[rB(ctx->opcode)]);
4340 #endif
4341 }
4342
4343 static void gen_slbmfev(DisasContext *ctx)
4344 {
4345 #if defined(CONFIG_USER_ONLY)
4346 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4347 #else
4348 if (unlikely(!ctx->mem_idx)) {
4349 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4350 return;
4351 }
4352 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4353 cpu_gpr[rB(ctx->opcode)]);
4354 #endif
4355 }
4356 #endif /* defined(TARGET_PPC64) */
4357
4358 /*** Lookaside buffer management ***/
4359 /* Optional & mem_idx only: */
4360
4361 /* tlbia */
4362 static void gen_tlbia(DisasContext *ctx)
4363 {
4364 #if defined(CONFIG_USER_ONLY)
4365 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4366 #else
4367 if (unlikely(!ctx->mem_idx)) {
4368 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4369 return;
4370 }
4371 gen_helper_tlbia(cpu_env);
4372 #endif
4373 }
4374
4375 /* tlbiel */
4376 static void gen_tlbiel(DisasContext *ctx)
4377 {
4378 #if defined(CONFIG_USER_ONLY)
4379 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4380 #else
4381 if (unlikely(!ctx->mem_idx)) {
4382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4383 return;
4384 }
4385 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4386 #endif
4387 }
4388
4389 /* tlbie */
4390 static void gen_tlbie(DisasContext *ctx)
4391 {
4392 #if defined(CONFIG_USER_ONLY)
4393 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4394 #else
4395 if (unlikely(!ctx->mem_idx)) {
4396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4397 return;
4398 }
4399 if (NARROW_MODE(ctx)) {
4400 TCGv t0 = tcg_temp_new();
4401 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4402 gen_helper_tlbie(cpu_env, t0);
4403 tcg_temp_free(t0);
4404 } else {
4405 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4406 }
4407 #endif
4408 }
4409
4410 /* tlbsync */
4411 static void gen_tlbsync(DisasContext *ctx)
4412 {
4413 #if defined(CONFIG_USER_ONLY)
4414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4415 #else
4416 if (unlikely(!ctx->mem_idx)) {
4417 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4418 return;
4419 }
4420 /* This has no effect: it should ensure that all previous
4421 * tlbie have completed
4422 */
4423 gen_stop_exception(ctx);
4424 #endif
4425 }
4426
4427 #if defined(TARGET_PPC64)
4428 /* slbia */
4429 static void gen_slbia(DisasContext *ctx)
4430 {
4431 #if defined(CONFIG_USER_ONLY)
4432 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4433 #else
4434 if (unlikely(!ctx->mem_idx)) {
4435 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4436 return;
4437 }
4438 gen_helper_slbia(cpu_env);
4439 #endif
4440 }
4441
4442 /* slbie */
4443 static void gen_slbie(DisasContext *ctx)
4444 {
4445 #if defined(CONFIG_USER_ONLY)
4446 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4447 #else
4448 if (unlikely(!ctx->mem_idx)) {
4449 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4450 return;
4451 }
4452 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4453 #endif
4454 }
4455 #endif
4456
4457 /*** External control ***/
4458 /* Optional: */
4459
4460 /* eciwx */
4461 static void gen_eciwx(DisasContext *ctx)
4462 {
4463 TCGv t0;
4464 /* Should check EAR[E] ! */
4465 gen_set_access_type(ctx, ACCESS_EXT);
4466 t0 = tcg_temp_new();
4467 gen_addr_reg_index(ctx, t0);
4468 gen_check_align(ctx, t0, 0x03);
4469 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4470 tcg_temp_free(t0);
4471 }
4472
4473 /* ecowx */
4474 static void gen_ecowx(DisasContext *ctx)
4475 {
4476 TCGv t0;
4477 /* Should check EAR[E] ! */
4478 gen_set_access_type(ctx, ACCESS_EXT);
4479 t0 = tcg_temp_new();
4480 gen_addr_reg_index(ctx, t0);
4481 gen_check_align(ctx, t0, 0x03);
4482 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4483 tcg_temp_free(t0);
4484 }
4485
4486 /* PowerPC 601 specific instructions */
4487
4488 /* abs - abs. */
4489 static void gen_abs(DisasContext *ctx)
4490 {
4491 int l1 = gen_new_label();
4492 int l2 = gen_new_label();
4493 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4494 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4495 tcg_gen_br(l2);
4496 gen_set_label(l1);
4497 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4498 gen_set_label(l2);
4499 if (unlikely(Rc(ctx->opcode) != 0))
4500 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4501 }
4502
4503 /* abso - abso. */
4504 static void gen_abso(DisasContext *ctx)
4505 {
4506 int l1 = gen_new_label();
4507 int l2 = gen_new_label();
4508 int l3 = gen_new_label();
4509 /* Start with XER OV disabled, the most likely case */
4510 tcg_gen_movi_tl(cpu_ov, 0);
4511 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4512 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4513 tcg_gen_movi_tl(cpu_ov, 1);
4514 tcg_gen_movi_tl(cpu_so, 1);
4515 tcg_gen_br(l2);
4516 gen_set_label(l1);
4517 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4518 tcg_gen_br(l3);
4519 gen_set_label(l2);
4520 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4521 gen_set_label(l3);
4522 if (unlikely(Rc(ctx->opcode) != 0))
4523 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4524 }
4525
4526 /* clcs */
4527 static void gen_clcs(DisasContext *ctx)
4528 {
4529 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4530 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4531 tcg_temp_free_i32(t0);
4532 /* Rc=1 sets CR0 to an undefined state */
4533 }
4534
4535 /* div - div. */
4536 static void gen_div(DisasContext *ctx)
4537 {
4538 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4539 cpu_gpr[rB(ctx->opcode)]);
4540 if (unlikely(Rc(ctx->opcode) != 0))
4541 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4542 }
4543
4544 /* divo - divo. */
4545 static void gen_divo(DisasContext *ctx)
4546 {
4547 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4548 cpu_gpr[rB(ctx->opcode)]);
4549 if (unlikely(Rc(ctx->opcode) != 0))
4550 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4551 }
4552
4553 /* divs - divs. */
4554 static void gen_divs(DisasContext *ctx)
4555 {
4556 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4557 cpu_gpr[rB(ctx->opcode)]);
4558 if (unlikely(Rc(ctx->opcode) != 0))
4559 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4560 }
4561
4562 /* divso - divso. */
4563 static void gen_divso(DisasContext *ctx)
4564 {
4565 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4566 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4567 if (unlikely(Rc(ctx->opcode) != 0))
4568 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4569 }
4570
4571 /* doz - doz. */
4572 static void gen_doz(DisasContext *ctx)
4573 {
4574 int l1 = gen_new_label();
4575 int l2 = gen_new_label();
4576 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4577 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4578 tcg_gen_br(l2);
4579 gen_set_label(l1);
4580 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4581 gen_set_label(l2);
4582 if (unlikely(Rc(ctx->opcode) != 0))
4583 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4584 }
4585
4586 /* dozo - dozo. */
4587 static void gen_dozo(DisasContext *ctx)
4588 {
4589 int l1 = gen_new_label();
4590 int l2 = gen_new_label();
4591 TCGv t0 = tcg_temp_new();
4592 TCGv t1 = tcg_temp_new();
4593 TCGv t2 = tcg_temp_new();
4594 /* Start with XER OV disabled, the most likely case */
4595 tcg_gen_movi_tl(cpu_ov, 0);
4596 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4597 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4598 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4599 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4600 tcg_gen_andc_tl(t1, t1, t2);
4601 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4602 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4603 tcg_gen_movi_tl(cpu_ov, 1);
4604 tcg_gen_movi_tl(cpu_so, 1);
4605 tcg_gen_br(l2);
4606 gen_set_label(l1);
4607 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4608 gen_set_label(l2);
4609 tcg_temp_free(t0);
4610 tcg_temp_free(t1);
4611 tcg_temp_free(t2);
4612 if (unlikely(Rc(ctx->opcode) != 0))
4613 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4614 }
4615
4616 /* dozi */
4617 static void gen_dozi(DisasContext *ctx)
4618 {
4619 target_long simm = SIMM(ctx->opcode);
4620 int l1 = gen_new_label();
4621 int l2 = gen_new_label();
4622 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4623 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4624 tcg_gen_br(l2);
4625 gen_set_label(l1);
4626 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4627 gen_set_label(l2);
4628 if (unlikely(Rc(ctx->opcode) != 0))
4629 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4630 }
4631
4632 /* lscbx - lscbx. */
4633 static void gen_lscbx(DisasContext *ctx)
4634 {
4635 TCGv t0 = tcg_temp_new();
4636 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4637 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4638 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4639
4640 gen_addr_reg_index(ctx, t0);
4641 /* NIP cannot be restored if the memory exception comes from an helper */
4642 gen_update_nip(ctx, ctx->nip - 4);
4643 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4644 tcg_temp_free_i32(t1);
4645 tcg_temp_free_i32(t2);
4646 tcg_temp_free_i32(t3);
4647 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4648 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4649 if (unlikely(Rc(ctx->opcode) != 0))
4650 gen_set_Rc0(ctx, t0);
4651 tcg_temp_free(t0);
4652 }
4653
4654 /* maskg - maskg. */
4655 static void gen_maskg(DisasContext *ctx)
4656 {
4657 int l1 = gen_new_label();
4658 TCGv t0 = tcg_temp_new();
4659 TCGv t1 = tcg_temp_new();
4660 TCGv t2 = tcg_temp_new();
4661 TCGv t3 = tcg_temp_new();
4662 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4663 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4664 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4665 tcg_gen_addi_tl(t2, t0, 1);
4666 tcg_gen_shr_tl(t2, t3, t2);
4667 tcg_gen_shr_tl(t3, t3, t1);
4668 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4669 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4670 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4671 gen_set_label(l1);
4672 tcg_temp_free(t0);
4673 tcg_temp_free(t1);
4674 tcg_temp_free(t2);
4675 tcg_temp_free(t3);
4676 if (unlikely(Rc(ctx->opcode) != 0))
4677 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4678 }
4679
4680 /* maskir - maskir. */
4681 static void gen_maskir(DisasContext *ctx)
4682 {
4683 TCGv t0 = tcg_temp_new();
4684 TCGv t1 = tcg_temp_new();
4685 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4686 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4687 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4688 tcg_temp_free(t0);
4689 tcg_temp_free(t1);
4690 if (unlikely(Rc(ctx->opcode) != 0))
4691 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4692 }
4693
4694 /* mul - mul. */
4695 static void gen_mul(DisasContext *ctx)
4696 {
4697 TCGv_i64 t0 = tcg_temp_new_i64();
4698 TCGv_i64 t1 = tcg_temp_new_i64();
4699 TCGv t2 = tcg_temp_new();
4700 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4701 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4702 tcg_gen_mul_i64(t0, t0, t1);
4703 tcg_gen_trunc_i64_tl(t2, t0);
4704 gen_store_spr(SPR_MQ, t2);
4705 tcg_gen_shri_i64(t1, t0, 32);
4706 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4707 tcg_temp_free_i64(t0);
4708 tcg_temp_free_i64(t1);
4709 tcg_temp_free(t2);
4710 if (unlikely(Rc(ctx->opcode) != 0))
4711 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4712 }
4713
4714 /* mulo - mulo. */
4715 static void gen_mulo(DisasContext *ctx)
4716 {
4717 int l1 = gen_new_label();
4718 TCGv_i64 t0 = tcg_temp_new_i64();
4719 TCGv_i64 t1 = tcg_temp_new_i64();
4720 TCGv t2 = tcg_temp_new();
4721 /* Start with XER OV disabled, the most likely case */
4722 tcg_gen_movi_tl(cpu_ov, 0);
4723 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4724 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4725 tcg_gen_mul_i64(t0, t0, t1);
4726 tcg_gen_trunc_i64_tl(t2, t0);
4727 gen_store_spr(SPR_MQ, t2);
4728 tcg_gen_shri_i64(t1, t0, 32);
4729 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4730 tcg_gen_ext32s_i64(t1, t0);
4731 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4732 tcg_gen_movi_tl(cpu_ov, 1);
4733 tcg_gen_movi_tl(cpu_so, 1);
4734 gen_set_label(l1);
4735 tcg_temp_free_i64(t0);
4736 tcg_temp_free_i64(t1);
4737 tcg_temp_free(t2);
4738 if (unlikely(Rc(ctx->opcode) != 0))
4739 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4740 }
4741
4742 /* nabs - nabs. */
4743 static void gen_nabs(DisasContext *ctx)
4744 {
4745 int l1 = gen_new_label();
4746 int l2 = gen_new_label();
4747 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4748 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4749 tcg_gen_br(l2);
4750 gen_set_label(l1);
4751 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4752 gen_set_label(l2);
4753 if (unlikely(Rc(ctx->opcode) != 0))
4754 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4755 }
4756
4757 /* nabso - nabso. */
4758 static void gen_nabso(DisasContext *ctx)
4759 {
4760 int l1 = gen_new_label();
4761 int l2 = gen_new_label();
4762 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4763 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4764 tcg_gen_br(l2);
4765 gen_set_label(l1);
4766 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4767 gen_set_label(l2);
4768 /* nabs never overflows */
4769 tcg_gen_movi_tl(cpu_ov, 0);
4770 if (unlikely(Rc(ctx->opcode) != 0))
4771 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4772 }
4773
4774 /* rlmi - rlmi. */
4775 static void gen_rlmi(DisasContext *ctx)
4776 {
4777 uint32_t mb = MB(ctx->opcode);
4778 uint32_t me = ME(ctx->opcode);
4779 TCGv t0 = tcg_temp_new();
4780 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4781 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4782 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4783 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4784 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4785 tcg_temp_free(t0);
4786 if (unlikely(Rc(ctx->opcode) != 0))
4787 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4788 }
4789
4790 /* rrib - rrib. */
4791 static void gen_rrib(DisasContext *ctx)
4792 {
4793 TCGv t0 = tcg_temp_new();
4794 TCGv t1 = tcg_temp_new();
4795 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4796 tcg_gen_movi_tl(t1, 0x80000000);
4797 tcg_gen_shr_tl(t1, t1, t0);
4798 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4799 tcg_gen_and_tl(t0, t0, t1);
4800 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4801 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4802 tcg_temp_free(t0);
4803 tcg_temp_free(t1);
4804 if (unlikely(Rc(ctx->opcode) != 0))
4805 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4806 }
4807
4808 /* sle - sle. */
4809 static void gen_sle(DisasContext *ctx)
4810 {
4811 TCGv t0 = tcg_temp_new();
4812 TCGv t1 = tcg_temp_new();
4813 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4814 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4815 tcg_gen_subfi_tl(t1, 32, t1);
4816 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4817 tcg_gen_or_tl(t1, t0, t1);
4818 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4819 gen_store_spr(SPR_MQ, t1);
4820 tcg_temp_free(t0);
4821 tcg_temp_free(t1);
4822 if (unlikely(Rc(ctx->opcode) != 0))
4823 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4824 }
4825
4826 /* sleq - sleq. */
4827 static void gen_sleq(DisasContext *ctx)
4828 {
4829 TCGv t0 = tcg_temp_new();
4830 TCGv t1 = tcg_temp_new();
4831 TCGv t2 = tcg_temp_new();
4832 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4833 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4834 tcg_gen_shl_tl(t2, t2, t0);
4835 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4836 gen_load_spr(t1, SPR_MQ);
4837 gen_store_spr(SPR_MQ, t0);
4838 tcg_gen_and_tl(t0, t0, t2);
4839 tcg_gen_andc_tl(t1, t1, t2);
4840 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4841 tcg_temp_free(t0);
4842 tcg_temp_free(t1);
4843 tcg_temp_free(t2);
4844 if (unlikely(Rc(ctx->opcode) != 0))
4845 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4846 }
4847
4848 /* sliq - sliq. */
4849 static void gen_sliq(DisasContext *ctx)
4850 {
4851 int sh = SH(ctx->opcode);
4852 TCGv t0 = tcg_temp_new();
4853 TCGv t1 = tcg_temp_new();
4854 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4855 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4856 tcg_gen_or_tl(t1, t0, t1);
4857 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4858 gen_store_spr(SPR_MQ, t1);
4859 tcg_temp_free(t0);
4860 tcg_temp_free(t1);
4861 if (unlikely(Rc(ctx->opcode) != 0))
4862 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4863 }
4864
4865 /* slliq - slliq. */
4866 static void gen_slliq(DisasContext *ctx)
4867 {
4868 int sh = SH(ctx->opcode);
4869 TCGv t0 = tcg_temp_new();
4870 TCGv t1 = tcg_temp_new();
4871 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4872 gen_load_spr(t1, SPR_MQ);
4873 gen_store_spr(SPR_MQ, t0);
4874 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4875 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4876 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4877 tcg_temp_free(t0);
4878 tcg_temp_free(t1);
4879 if (unlikely(Rc(ctx->opcode) != 0))
4880 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4881 }
4882
4883 /* sllq - sllq. */
4884 static void gen_sllq(DisasContext *ctx)
4885 {
4886 int l1 = gen_new_label();
4887 int l2 = gen_new_label();
4888 TCGv t0 = tcg_temp_local_new();
4889 TCGv t1 = tcg_temp_local_new();
4890 TCGv t2 = tcg_temp_local_new();
4891 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4892 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4893 tcg_gen_shl_tl(t1, t1, t2);
4894 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4895 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4896 gen_load_spr(t0, SPR_MQ);
4897 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4898 tcg_gen_br(l2);
4899 gen_set_label(l1);
4900 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4901 gen_load_spr(t2, SPR_MQ);
4902 tcg_gen_andc_tl(t1, t2, t1);
4903 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4904 gen_set_label(l2);
4905 tcg_temp_free(t0);
4906 tcg_temp_free(t1);
4907 tcg_temp_free(t2);
4908 if (unlikely(Rc(ctx->opcode) != 0))
4909 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4910 }
4911
4912 /* slq - slq. */
4913 static void gen_slq(DisasContext *ctx)
4914 {
4915 int l1 = gen_new_label();
4916 TCGv t0 = tcg_temp_new();
4917 TCGv t1 = tcg_temp_new();
4918 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4919 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4920 tcg_gen_subfi_tl(t1, 32, t1);
4921 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4922 tcg_gen_or_tl(t1, t0, t1);
4923 gen_store_spr(SPR_MQ, t1);
4924 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4925 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4926 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4927 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4928 gen_set_label(l1);
4929 tcg_temp_free(t0);
4930 tcg_temp_free(t1);
4931 if (unlikely(Rc(ctx->opcode) != 0))
4932 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4933 }
4934
4935 /* sraiq - sraiq. */
4936 static void gen_sraiq(DisasContext *ctx)
4937 {
4938 int sh = SH(ctx->opcode);
4939 int l1 = gen_new_label();
4940 TCGv t0 = tcg_temp_new();
4941 TCGv t1 = tcg_temp_new();
4942 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4943 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4944 tcg_gen_or_tl(t0, t0, t1);
4945 gen_store_spr(SPR_MQ, t0);
4946 tcg_gen_movi_tl(cpu_ca, 0);
4947 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4948 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4949 tcg_gen_movi_tl(cpu_ca, 1);
4950 gen_set_label(l1);
4951 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4952 tcg_temp_free(t0);
4953 tcg_temp_free(t1);
4954 if (unlikely(Rc(ctx->opcode) != 0))
4955 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4956 }
4957
4958 /* sraq - sraq. */
4959 static void gen_sraq(DisasContext *ctx)
4960 {
4961 int l1 = gen_new_label();
4962 int l2 = gen_new_label();
4963 TCGv t0 = tcg_temp_new();
4964 TCGv t1 = tcg_temp_local_new();
4965 TCGv t2 = tcg_temp_local_new();
4966 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4967 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4968 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4969 tcg_gen_subfi_tl(t2, 32, t2);
4970 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4971 tcg_gen_or_tl(t0, t0, t2);
4972 gen_store_spr(SPR_MQ, t0);
4973 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4974 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4975 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4976 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4977 gen_set_label(l1);
4978 tcg_temp_free(t0);
4979 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4980 tcg_gen_movi_tl(cpu_ca, 0);
4981 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4982 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4983 tcg_gen_movi_tl(cpu_ca, 1);
4984 gen_set_label(l2);
4985 tcg_temp_free(t1);
4986 tcg_temp_free(t2);
4987 if (unlikely(Rc(ctx->opcode) != 0))
4988 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4989 }
4990
4991 /* sre - sre. */
4992 static void gen_sre(DisasContext *ctx)
4993 {
4994 TCGv t0 = tcg_temp_new();
4995 TCGv t1 = tcg_temp_new();
4996 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4997 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4998 tcg_gen_subfi_tl(t1, 32, t1);
4999 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5000 tcg_gen_or_tl(t1, t0, t1);
5001 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5002 gen_store_spr(SPR_MQ, t1);
5003 tcg_temp_free(t0);
5004 tcg_temp_free(t1);
5005 if (unlikely(Rc(ctx->opcode) != 0))
5006 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5007 }
5008
5009 /* srea - srea. */
5010 static void gen_srea(DisasContext *ctx)
5011 {
5012 TCGv t0 = tcg_temp_new();
5013 TCGv t1 = tcg_temp_new();
5014 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5015 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5016 gen_store_spr(SPR_MQ, t0);
5017 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5018 tcg_temp_free(t0);
5019 tcg_temp_free(t1);
5020 if (unlikely(Rc(ctx->opcode) != 0))
5021 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5022 }
5023
5024 /* sreq */
5025 static void gen_sreq(DisasContext *ctx)
5026 {
5027 TCGv t0 = tcg_temp_new();
5028 TCGv t1 = tcg_temp_new();
5029 TCGv t2 = tcg_temp_new();
5030 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5031 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5032 tcg_gen_shr_tl(t1, t1, t0);
5033 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5034 gen_load_spr(t2, SPR_MQ);
5035 gen_store_spr(SPR_MQ, t0);
5036 tcg_gen_and_tl(t0, t0, t1);
5037 tcg_gen_andc_tl(t2, t2, t1);
5038 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5039 tcg_temp_free(t0);
5040 tcg_temp_free(t1);
5041 tcg_temp_free(t2);
5042 if (unlikely(Rc(ctx->opcode) != 0))
5043 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5044 }
5045
5046 /* sriq */
5047 static void gen_sriq(DisasContext *ctx)
5048 {
5049 int sh = SH(ctx->opcode);
5050 TCGv t0 = tcg_temp_new();
5051 TCGv t1 = tcg_temp_new();
5052 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5053 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5054 tcg_gen_or_tl(t1, t0, t1);
5055 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5056 gen_store_spr(SPR_MQ, t1);
5057 tcg_temp_free(t0);
5058 tcg_temp_free(t1);
5059 if (unlikely(Rc(ctx->opcode) != 0))
5060 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5061 }
5062
5063 /* srliq */
5064 static void gen_srliq(DisasContext *ctx)
5065 {
5066 int sh = SH(ctx->opcode);
5067 TCGv t0 = tcg_temp_new();
5068 TCGv t1 = tcg_temp_new();
5069 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5070 gen_load_spr(t1, SPR_MQ);
5071 gen_store_spr(SPR_MQ, t0);
5072 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5073 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5074 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5075 tcg_temp_free(t0);
5076 tcg_temp_free(t1);
5077 if (unlikely(Rc(ctx->opcode) != 0))
5078 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5079 }
5080
5081 /* srlq */
5082 static void gen_srlq(DisasContext *ctx)
5083 {
5084 int l1 = gen_new_label();
5085 int l2 = gen_new_label();
5086 TCGv t0 = tcg_temp_local_new();
5087 TCGv t1 = tcg_temp_local_new();
5088 TCGv t2 = tcg_temp_local_new();
5089 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5090 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5091 tcg_gen_shr_tl(t2, t1, t2);
5092 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5093 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5094 gen_load_spr(t0, SPR_MQ);
5095 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5096 tcg_gen_br(l2);
5097 gen_set_label(l1);
5098 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5099 tcg_gen_and_tl(t0, t0, t2);
5100 gen_load_spr(t1, SPR_MQ);
5101 tcg_gen_andc_tl(t1, t1, t2);
5102 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5103 gen_set_label(l2);
5104 tcg_temp_free(t0);
5105 tcg_temp_free(t1);
5106 tcg_temp_free(t2);
5107 if (unlikely(Rc(ctx->opcode) != 0))
5108 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5109 }
5110
5111 /* srq */
5112 static void gen_srq(DisasContext *ctx)
5113 {
5114 int l1 = gen_new_label();
5115 TCGv t0 = tcg_temp_new();
5116 TCGv t1 = tcg_temp_new();
5117 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5118 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5119 tcg_gen_subfi_tl(t1, 32, t1);
5120 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5121 tcg_gen_or_tl(t1, t0, t1);
5122 gen_store_spr(SPR_MQ, t1);
5123 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5124 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5125 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5126 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5127 gen_set_label(l1);
5128 tcg_temp_free(t0);
5129 tcg_temp_free(t1);
5130 if (unlikely(Rc(ctx->opcode) != 0))
5131 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5132 }
5133
5134 /* PowerPC 602 specific instructions */
5135
5136 /* dsa */
5137 static void gen_dsa(DisasContext *ctx)
5138 {
5139 /* XXX: TODO */
5140 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5141 }
5142
5143 /* esa */
5144 static void gen_esa(DisasContext *ctx)
5145 {
5146 /* XXX: TODO */
5147 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5148 }
5149
5150 /* mfrom */
5151 static void gen_mfrom(DisasContext *ctx)
5152 {
5153 #if defined(CONFIG_USER_ONLY)
5154 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5155 #else
5156 if (unlikely(!ctx->mem_idx)) {
5157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5158 return;
5159 }
5160 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5161 #endif
5162 }
5163
5164 /* 602 - 603 - G2 TLB management */
5165
5166 /* tlbld */
5167 static void gen_tlbld_6xx(DisasContext *ctx)
5168 {
5169 #if defined(CONFIG_USER_ONLY)
5170 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5171 #else
5172 if (unlikely(!ctx->mem_idx)) {
5173 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5174 return;
5175 }
5176 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5177 #endif
5178 }
5179
5180 /* tlbli */
5181 static void gen_tlbli_6xx(DisasContext *ctx)
5182 {
5183 #if defined(CONFIG_USER_ONLY)
5184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5185 #else
5186 if (unlikely(!ctx->mem_idx)) {
5187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5188 return;
5189 }
5190 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5191 #endif
5192 }
5193
5194 /* 74xx TLB management */
5195
5196 /* tlbld */
5197 static void gen_tlbld_74xx(DisasContext *ctx)
5198 {
5199 #if defined(CONFIG_USER_ONLY)
5200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5201 #else
5202 if (unlikely(!ctx->mem_idx)) {
5203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5204 return;
5205 }
5206 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5207 #endif
5208 }
5209
5210 /* tlbli */
5211 static void gen_tlbli_74xx(DisasContext *ctx)
5212 {
5213 #if defined(CONFIG_USER_ONLY)
5214 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5215 #else
5216 if (unlikely(!ctx->mem_idx)) {
5217 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5218 return;
5219 }
5220 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5221 #endif
5222 }
5223
5224 /* POWER instructions not in PowerPC 601 */
5225
5226 /* clf */
5227 static void gen_clf(DisasContext *ctx)
5228 {
5229 /* Cache line flush: implemented as no-op */
5230 }
5231
5232 /* cli */
5233 static void gen_cli(DisasContext *ctx)
5234 {
5235 /* Cache line invalidate: privileged and treated as no-op */
5236 #if defined(CONFIG_USER_ONLY)
5237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5238 #else
5239 if (unlikely(!ctx->mem_idx)) {
5240 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5241 return;
5242 }
5243 #endif
5244 }
5245
5246 /* dclst */
5247 static void gen_dclst(DisasContext *ctx)
5248 {
5249 /* Data cache line store: treated as no-op */
5250 }
5251
5252 static void gen_mfsri(DisasContext *ctx)
5253 {
5254 #if defined(CONFIG_USER_ONLY)
5255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5256 #else
5257 int ra = rA(ctx->opcode);
5258 int rd = rD(ctx->opcode);
5259 TCGv t0;
5260 if (unlikely(!ctx->mem_idx)) {
5261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5262 return;
5263 }
5264 t0 = tcg_temp_new();
5265 gen_addr_reg_index(ctx, t0);
5266 tcg_gen_shri_tl(t0, t0, 28);
5267 tcg_gen_andi_tl(t0, t0, 0xF);
5268 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5269 tcg_temp_free(t0);
5270 if (ra != 0 && ra != rd)
5271 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5272 #endif
5273 }
5274
5275 static void gen_rac(DisasContext *ctx)
5276 {
5277 #if defined(CONFIG_USER_ONLY)
5278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5279 #else
5280 TCGv t0;
5281 if (unlikely(!ctx->mem_idx)) {
5282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5283 return;
5284 }
5285 t0 = tcg_temp_new();
5286 gen_addr_reg_index(ctx, t0);
5287 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5288 tcg_temp_free(t0);
5289 #endif
5290 }
5291
5292 static void gen_rfsvc(DisasContext *ctx)
5293 {
5294 #if defined(CONFIG_USER_ONLY)
5295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5296 #else
5297 if (unlikely(!ctx->mem_idx)) {
5298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5299 return;
5300 }
5301 gen_helper_rfsvc(cpu_env);
5302 gen_sync_exception(ctx);
5303 #endif
5304 }
5305
5306 /* svc is not implemented for now */
5307
5308 /* POWER2 specific instructions */
5309 /* Quad manipulation (load/store two floats at a time) */
5310
5311 /* lfq */
5312 static void gen_lfq(DisasContext *ctx)
5313 {
5314 int rd = rD(ctx->opcode);
5315 TCGv t0;
5316 gen_set_access_type(ctx, ACCESS_FLOAT);
5317 t0 = tcg_temp_new();
5318 gen_addr_imm_index(ctx, t0, 0);
5319 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5320 gen_addr_add(ctx, t0, t0, 8);
5321 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5322 tcg_temp_free(t0);
5323 }
5324
5325 /* lfqu */
5326 static void gen_lfqu(DisasContext *ctx)
5327 {
5328 int ra = rA(ctx->opcode);
5329 int rd = rD(ctx->opcode);
5330 TCGv t0, t1;
5331 gen_set_access_type(ctx, ACCESS_FLOAT);
5332 t0 = tcg_temp_new();
5333 t1 = tcg_temp_new();
5334 gen_addr_imm_index(ctx, t0, 0);
5335 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5336 gen_addr_add(ctx, t1, t0, 8);
5337 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5338 if (ra != 0)
5339 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5340 tcg_temp_free(t0);
5341 tcg_temp_free(t1);
5342 }
5343
5344 /* lfqux */
5345 static void gen_lfqux(DisasContext *ctx)
5346 {
5347 int ra = rA(ctx->opcode);
5348 int rd = rD(ctx->opcode);
5349 gen_set_access_type(ctx, ACCESS_FLOAT);
5350 TCGv t0, t1;
5351 t0 = tcg_temp_new();
5352 gen_addr_reg_index(ctx, t0);
5353 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5354 t1 = tcg_temp_new();
5355 gen_addr_add(ctx, t1, t0, 8);
5356 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5357 tcg_temp_free(t1);
5358 if (ra != 0)
5359 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5360 tcg_temp_free(t0);
5361 }
5362
5363 /* lfqx */
5364 static void gen_lfqx(DisasContext *ctx)
5365 {
5366 int rd = rD(ctx->opcode);
5367 TCGv t0;
5368 gen_set_access_type(ctx, ACCESS_FLOAT);
5369 t0 = tcg_temp_new();
5370 gen_addr_reg_index(ctx, t0);
5371 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5372 gen_addr_add(ctx, t0, t0, 8);
5373 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5374 tcg_temp_free(t0);
5375 }
5376
5377 /* stfq */
5378 static void gen_stfq(DisasContext *ctx)
5379 {
5380 int rd = rD(ctx->opcode);
5381 TCGv t0;
5382 gen_set_access_type(ctx, ACCESS_FLOAT);
5383 t0 = tcg_temp_new();
5384 gen_addr_imm_index(ctx, t0, 0);
5385 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5386 gen_addr_add(ctx, t0, t0, 8);
5387 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5388 tcg_temp_free(t0);
5389 }
5390
5391 /* stfqu */
5392 static void gen_stfqu(DisasContext *ctx)
5393 {
5394 int ra = rA(ctx->opcode);
5395 int rd = rD(ctx->opcode);
5396 TCGv t0, t1;
5397 gen_set_access_type(ctx, ACCESS_FLOAT);
5398 t0 = tcg_temp_new();
5399 gen_addr_imm_index(ctx, t0, 0);
5400 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5401 t1 = tcg_temp_new();
5402 gen_addr_add(ctx, t1, t0, 8);
5403 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5404 tcg_temp_free(t1);
5405 if (ra != 0)
5406 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5407 tcg_temp_free(t0);
5408 }
5409
5410 /* stfqux */
5411 static void gen_stfqux(DisasContext *ctx)
5412 {
5413 int ra = rA(ctx->opcode);
5414 int rd = rD(ctx->opcode);
5415 TCGv t0, t1;
5416 gen_set_access_type(ctx, ACCESS_FLOAT);
5417 t0 = tcg_temp_new();
5418 gen_addr_reg_index(ctx, t0);
5419 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5420 t1 = tcg_temp_new();
5421 gen_addr_add(ctx, t1, t0, 8);
5422 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5423 tcg_temp_free(t1);
5424 if (ra != 0)
5425 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5426 tcg_temp_free(t0);
5427 }
5428
5429 /* stfqx */
5430 static void gen_stfqx(DisasContext *ctx)
5431 {
5432 int rd = rD(ctx->opcode);
5433 TCGv t0;
5434 gen_set_access_type(ctx, ACCESS_FLOAT);
5435 t0 = tcg_temp_new();
5436 gen_addr_reg_index(ctx, t0);
5437 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5438 gen_addr_add(ctx, t0, t0, 8);
5439 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5440 tcg_temp_free(t0);
5441 }
5442
5443 /* BookE specific instructions */
5444
5445 /* XXX: not implemented on 440 ? */
5446 static void gen_mfapidi(DisasContext *ctx)
5447 {
5448 /* XXX: TODO */
5449 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5450 }
5451
5452 /* XXX: not implemented on 440 ? */
5453 static void gen_tlbiva(DisasContext *ctx)
5454 {
5455 #if defined(CONFIG_USER_ONLY)
5456 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5457 #else
5458 TCGv t0;
5459 if (unlikely(!ctx->mem_idx)) {
5460 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5461 return;
5462 }
5463 t0 = tcg_temp_new();
5464 gen_addr_reg_index(ctx, t0);
5465 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5466 tcg_temp_free(t0);
5467 #endif
5468 }
5469
5470 /* All 405 MAC instructions are translated here */
5471 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5472 int ra, int rb, int rt, int Rc)
5473 {
5474 TCGv t0, t1;
5475
5476 t0 = tcg_temp_local_new();
5477 t1 = tcg_temp_local_new();
5478
5479 switch (opc3 & 0x0D) {
5480 case 0x05:
5481 /* macchw - macchw. - macchwo - macchwo. */
5482 /* macchws - macchws. - macchwso - macchwso. */
5483 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5484 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5485 /* mulchw - mulchw. */
5486 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5487 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5488 tcg_gen_ext16s_tl(t1, t1);
5489 break;
5490 case 0x04:
5491 /* macchwu - macchwu. - macchwuo - macchwuo. */
5492 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5493 /* mulchwu - mulchwu. */
5494 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5495 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5496 tcg_gen_ext16u_tl(t1, t1);
5497 break;
5498 case 0x01:
5499 /* machhw - machhw. - machhwo - machhwo. */
5500 /* machhws - machhws. - machhwso - machhwso. */
5501 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5502 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5503 /* mulhhw - mulhhw. */
5504 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5505 tcg_gen_ext16s_tl(t0, t0);
5506 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5507 tcg_gen_ext16s_tl(t1, t1);
5508 break;
5509 case 0x00:
5510 /* machhwu - machhwu. - machhwuo - machhwuo. */
5511 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5512 /* mulhhwu - mulhhwu. */
5513 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5514 tcg_gen_ext16u_tl(t0, t0);
5515 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5516 tcg_gen_ext16u_tl(t1, t1);
5517 break;
5518 case 0x0D:
5519 /* maclhw - maclhw. - maclhwo - maclhwo. */
5520 /* maclhws - maclhws. - maclhwso - maclhwso. */
5521 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5522 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5523 /* mullhw - mullhw. */
5524 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5525 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5526 break;
5527 case 0x0C:
5528 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5529 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5530 /* mullhwu - mullhwu. */
5531 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5532 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5533 break;
5534 }
5535 if (opc2 & 0x04) {
5536 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5537 tcg_gen_mul_tl(t1, t0, t1);
5538 if (opc2 & 0x02) {
5539 /* nmultiply-and-accumulate (0x0E) */
5540 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5541 } else {
5542 /* multiply-and-accumulate (0x0C) */
5543 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5544 }
5545
5546 if (opc3 & 0x12) {
5547 /* Check overflow and/or saturate */
5548 int l1 = gen_new_label();
5549
5550 if (opc3 & 0x10) {
5551 /* Start with XER OV disabled, the most likely case */
5552 tcg_gen_movi_tl(cpu_ov, 0);
5553 }
5554 if (opc3 & 0x01) {
5555 /* Signed */
5556 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5557 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5558 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5559 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5560 if (opc3 & 0x02) {
5561 /* Saturate */
5562 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5563 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5564 }
5565 } else {
5566 /* Unsigned */
5567 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5568 if (opc3 & 0x02) {
5569 /* Saturate */
5570 tcg_gen_movi_tl(t0, UINT32_MAX);
5571 }
5572 }
5573 if (opc3 & 0x10) {
5574 /* Check overflow */
5575 tcg_gen_movi_tl(cpu_ov, 1);
5576 tcg_gen_movi_tl(cpu_so, 1);
5577 }
5578 gen_set_label(l1);
5579 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5580 }
5581 } else {
5582 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5583 }
5584 tcg_temp_free(t0);
5585 tcg_temp_free(t1);
5586 if (unlikely(Rc) != 0) {
5587 /* Update Rc0 */
5588 gen_set_Rc0(ctx, cpu_gpr[rt]);
5589 }
5590 }
5591
5592 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5593 static void glue(gen_, name)(DisasContext *ctx) \
5594 { \
5595 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5596 rD(ctx->opcode), Rc(ctx->opcode)); \
5597 }
5598
5599 /* macchw - macchw. */
5600 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5601 /* macchwo - macchwo. */
5602 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5603 /* macchws - macchws. */
5604 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5605 /* macchwso - macchwso. */
5606 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5607 /* macchwsu - macchwsu. */
5608 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5609 /* macchwsuo - macchwsuo. */
5610 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5611 /* macchwu - macchwu. */
5612 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5613 /* macchwuo - macchwuo. */
5614 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5615 /* machhw - machhw. */
5616 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5617 /* machhwo - machhwo. */
5618 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5619 /* machhws - machhws. */
5620 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5621 /* machhwso - machhwso. */
5622 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5623 /* machhwsu - machhwsu. */
5624 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5625 /* machhwsuo - machhwsuo. */
5626 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5627 /* machhwu - machhwu. */
5628 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5629 /* machhwuo - machhwuo. */
5630 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5631 /* maclhw - maclhw. */
5632 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5633 /* maclhwo - maclhwo. */
5634 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5635 /* maclhws - maclhws. */
5636 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5637 /* maclhwso - maclhwso. */
5638 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5639 /* maclhwu - maclhwu. */
5640 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5641 /* maclhwuo - maclhwuo. */
5642 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5643 /* maclhwsu - maclhwsu. */
5644 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5645 /* maclhwsuo - maclhwsuo. */
5646 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5647 /* nmacchw - nmacchw. */
5648 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5649 /* nmacchwo - nmacchwo. */
5650 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5651 /* nmacchws - nmacchws. */
5652 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5653 /* nmacchwso - nmacchwso. */
5654 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5655 /* nmachhw - nmachhw. */
5656 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5657 /* nmachhwo - nmachhwo. */
5658 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5659 /* nmachhws - nmachhws. */
5660 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5661 /* nmachhwso - nmachhwso. */
5662 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5663 /* nmaclhw - nmaclhw. */
5664 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5665 /* nmaclhwo - nmaclhwo. */
5666 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5667 /* nmaclhws - nmaclhws. */
5668 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5669 /* nmaclhwso - nmaclhwso. */
5670 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5671
5672 /* mulchw - mulchw. */
5673 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5674 /* mulchwu - mulchwu. */
5675 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5676 /* mulhhw - mulhhw. */
5677 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5678 /* mulhhwu - mulhhwu. */
5679 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5680 /* mullhw - mullhw. */
5681 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5682 /* mullhwu - mullhwu. */
5683 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5684
5685 /* mfdcr */
5686 static void gen_mfdcr(DisasContext *ctx)
5687 {
5688 #if defined(CONFIG_USER_ONLY)
5689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5690 #else
5691 TCGv dcrn;
5692 if (unlikely(!ctx->mem_idx)) {
5693 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5694 return;
5695 }
5696 /* NIP cannot be restored if the memory exception comes from an helper */
5697 gen_update_nip(ctx, ctx->nip - 4);
5698 dcrn = tcg_const_tl(SPR(ctx->opcode));
5699 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5700 tcg_temp_free(dcrn);
5701 #endif
5702 }
5703
5704 /* mtdcr */
5705 static void gen_mtdcr(DisasContext *ctx)
5706 {
5707 #if defined(CONFIG_USER_ONLY)
5708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5709 #else
5710 TCGv dcrn;
5711 if (unlikely(!ctx->mem_idx)) {
5712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5713 return;
5714 }
5715 /* NIP cannot be restored if the memory exception comes from an helper */
5716 gen_update_nip(ctx, ctx->nip - 4);
5717 dcrn = tcg_const_tl(SPR(ctx->opcode));
5718 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5719 tcg_temp_free(dcrn);
5720 #endif
5721 }
5722
5723 /* mfdcrx */
5724 /* XXX: not implemented on 440 ? */
5725 static void gen_mfdcrx(DisasContext *ctx)
5726 {
5727 #if defined(CONFIG_USER_ONLY)
5728 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5729 #else
5730 if (unlikely(!ctx->mem_idx)) {
5731 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5732 return;
5733 }
5734 /* NIP cannot be restored if the memory exception comes from an helper */
5735 gen_update_nip(ctx, ctx->nip - 4);
5736 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5737 cpu_gpr[rA(ctx->opcode)]);
5738 /* Note: Rc update flag set leads to undefined state of Rc0 */
5739 #endif
5740 }
5741
5742 /* mtdcrx */
5743 /* XXX: not implemented on 440 ? */
5744 static void gen_mtdcrx(DisasContext *ctx)
5745 {
5746 #if defined(CONFIG_USER_ONLY)
5747 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5748 #else
5749 if (unlikely(!ctx->mem_idx)) {
5750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5751 return;
5752 }
5753 /* NIP cannot be restored if the memory exception comes from an helper */
5754 gen_update_nip(ctx, ctx->nip - 4);
5755 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5756 cpu_gpr[rS(ctx->opcode)]);
5757 /* Note: Rc update flag set leads to undefined state of Rc0 */
5758 #endif
5759 }
5760
5761 /* mfdcrux (PPC 460) : user-mode access to DCR */
5762 static void gen_mfdcrux(DisasContext *ctx)
5763 {
5764 /* NIP cannot be restored if the memory exception comes from an helper */
5765 gen_update_nip(ctx, ctx->nip - 4);
5766 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5767 cpu_gpr[rA(ctx->opcode)]);
5768 /* Note: Rc update flag set leads to undefined state of Rc0 */
5769 }
5770
5771 /* mtdcrux (PPC 460) : user-mode access to DCR */
5772 static void gen_mtdcrux(DisasContext *ctx)
5773 {
5774 /* NIP cannot be restored if the memory exception comes from an helper */
5775 gen_update_nip(ctx, ctx->nip - 4);
5776 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5777 cpu_gpr[rS(ctx->opcode)]);
5778 /* Note: Rc update flag set leads to undefined state of Rc0 */
5779 }
5780
5781 /* dccci */
5782 static void gen_dccci(DisasContext *ctx)
5783 {
5784 #if defined(CONFIG_USER_ONLY)
5785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5786 #else
5787 if (unlikely(!ctx->mem_idx)) {
5788 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5789 return;
5790 }
5791 /* interpreted as no-op */
5792 #endif
5793 }
5794
5795 /* dcread */
5796 static void gen_dcread(DisasContext *ctx)
5797 {
5798 #if defined(CONFIG_USER_ONLY)
5799 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5800 #else
5801 TCGv EA, val;
5802 if (unlikely(!ctx->mem_idx)) {
5803 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5804 return;
5805 }
5806 gen_set_access_type(ctx, ACCESS_CACHE);
5807 EA = tcg_temp_new();
5808 gen_addr_reg_index(ctx, EA);
5809 val = tcg_temp_new();
5810 gen_qemu_ld32u(ctx, val, EA);
5811 tcg_temp_free(val);
5812 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5813 tcg_temp_free(EA);
5814 #endif
5815 }
5816
5817 /* icbt */
5818 static void gen_icbt_40x(DisasContext *ctx)
5819 {
5820 /* interpreted as no-op */
5821 /* XXX: specification say this is treated as a load by the MMU
5822 * but does not generate any exception
5823 */
5824 }
5825
5826 /* iccci */
5827 static void gen_iccci(DisasContext *ctx)
5828 {
5829 #if defined(CONFIG_USER_ONLY)
5830 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5831 #else
5832 if (unlikely(!ctx->mem_idx)) {
5833 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5834 return;
5835 }
5836 /* interpreted as no-op */
5837 #endif
5838 }
5839
5840 /* icread */
5841 static void gen_icread(DisasContext *ctx)
5842 {
5843 #if defined(CONFIG_USER_ONLY)
5844 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5845 #else
5846 if (unlikely(!ctx->mem_idx)) {
5847 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5848 return;
5849 }
5850 /* interpreted as no-op */
5851 #endif
5852 }
5853
5854 /* rfci (mem_idx only) */
5855 static void gen_rfci_40x(DisasContext *ctx)
5856 {
5857 #if defined(CONFIG_USER_ONLY)
5858 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5859 #else
5860 if (unlikely(!ctx->mem_idx)) {
5861 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5862 return;
5863 }
5864 /* Restore CPU state */
5865 gen_helper_40x_rfci(cpu_env);
5866 gen_sync_exception(ctx);
5867 #endif
5868 }
5869
5870 static void gen_rfci(DisasContext *ctx)
5871 {
5872 #if defined(CONFIG_USER_ONLY)
5873 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5874 #else
5875 if (unlikely(!ctx->mem_idx)) {
5876 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5877 return;
5878 }
5879 /* Restore CPU state */
5880 gen_helper_rfci(cpu_env);
5881 gen_sync_exception(ctx);
5882 #endif
5883 }
5884
5885 /* BookE specific */
5886
5887 /* XXX: not implemented on 440 ? */
5888 static void gen_rfdi(DisasContext *ctx)
5889 {
5890 #if defined(CONFIG_USER_ONLY)
5891 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5892 #else
5893 if (unlikely(!ctx->mem_idx)) {
5894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5895 return;
5896 }
5897 /* Restore CPU state */
5898 gen_helper_rfdi(cpu_env);
5899 gen_sync_exception(ctx);
5900 #endif
5901 }
5902
5903 /* XXX: not implemented on 440 ? */
5904 static void gen_rfmci(DisasContext *ctx)
5905 {
5906 #if defined(CONFIG_USER_ONLY)
5907 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5908 #else
5909 if (unlikely(!ctx->mem_idx)) {
5910 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5911 return;
5912 }
5913 /* Restore CPU state */
5914 gen_helper_rfmci(cpu_env);
5915 gen_sync_exception(ctx);
5916 #endif
5917 }
5918
5919 /* TLB management - PowerPC 405 implementation */
5920
5921 /* tlbre */
5922 static void gen_tlbre_40x(DisasContext *ctx)
5923 {
5924 #if defined(CONFIG_USER_ONLY)
5925 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5926 #else
5927 if (unlikely(!ctx->mem_idx)) {
5928 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5929 return;
5930 }
5931 switch (rB(ctx->opcode)) {
5932 case 0:
5933 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5934 cpu_gpr[rA(ctx->opcode)]);
5935 break;
5936 case 1:
5937 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5938 cpu_gpr[rA(ctx->opcode)]);
5939 break;
5940 default:
5941 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5942 break;
5943 }
5944 #endif
5945 }
5946
5947 /* tlbsx - tlbsx. */
5948 static void gen_tlbsx_40x(DisasContext *ctx)
5949 {
5950 #if defined(CONFIG_USER_ONLY)
5951 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5952 #else
5953 TCGv t0;
5954 if (unlikely(!ctx->mem_idx)) {
5955 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5956 return;
5957 }
5958 t0 = tcg_temp_new();
5959 gen_addr_reg_index(ctx, t0);
5960 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5961 tcg_temp_free(t0);
5962 if (Rc(ctx->opcode)) {
5963 int l1 = gen_new_label();
5964 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5965 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5966 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5967 gen_set_label(l1);
5968 }
5969 #endif
5970 }
5971
5972 /* tlbwe */
5973 static void gen_tlbwe_40x(DisasContext *ctx)
5974 {
5975 #if defined(CONFIG_USER_ONLY)
5976 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5977 #else
5978 if (unlikely(!ctx->mem_idx)) {
5979 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5980 return;
5981 }
5982 switch (rB(ctx->opcode)) {
5983 case 0:
5984 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5985 cpu_gpr[rS(ctx->opcode)]);
5986 break;
5987 case 1:
5988 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5989 cpu_gpr[rS(ctx->opcode)]);
5990 break;
5991 default:
5992 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5993 break;
5994 }
5995 #endif
5996 }
5997
5998 /* TLB management - PowerPC 440 implementation */
5999
6000 /* tlbre */
6001 static void gen_tlbre_440(DisasContext *ctx)
6002 {
6003 #if defined(CONFIG_USER_ONLY)
6004 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6005 #else
6006 if (unlikely(!ctx->mem_idx)) {
6007 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6008 return;
6009 }
6010 switch (rB(ctx->opcode)) {
6011 case 0:
6012 case 1:
6013 case 2:
6014 {
6015 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6016 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6017 t0, cpu_gpr[rA(ctx->opcode)]);
6018 tcg_temp_free_i32(t0);
6019 }
6020 break;
6021 default:
6022 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6023 break;
6024 }
6025 #endif
6026 }
6027
6028 /* tlbsx - tlbsx. */
6029 static void gen_tlbsx_440(DisasContext *ctx)
6030 {
6031 #if defined(CONFIG_USER_ONLY)
6032 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6033 #else
6034 TCGv t0;
6035 if (unlikely(!ctx->mem_idx)) {
6036 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6037 return;
6038 }
6039 t0 = tcg_temp_new();
6040 gen_addr_reg_index(ctx, t0);
6041 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6042 tcg_temp_free(t0);
6043 if (Rc(ctx->opcode)) {
6044 int l1 = gen_new_label();
6045 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6046 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6047 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6048 gen_set_label(l1);
6049 }
6050 #endif
6051 }
6052
6053 /* tlbwe */
6054 static void gen_tlbwe_440(DisasContext *ctx)
6055 {
6056 #if defined(CONFIG_USER_ONLY)
6057 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6058 #else
6059 if (unlikely(!ctx->mem_idx)) {
6060 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6061 return;
6062 }
6063 switch (rB(ctx->opcode)) {
6064 case 0:
6065 case 1:
6066 case 2:
6067 {
6068 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6069 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6070 cpu_gpr[rS(ctx->opcode)]);
6071 tcg_temp_free_i32(t0);
6072 }
6073 break;
6074 default:
6075 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6076 break;
6077 }
6078 #endif
6079 }
6080
6081 /* TLB management - PowerPC BookE 2.06 implementation */
6082
6083 /* tlbre */
6084 static void gen_tlbre_booke206(DisasContext *ctx)
6085 {
6086 #if defined(CONFIG_USER_ONLY)
6087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6088 #else
6089 if (unlikely(!ctx->mem_idx)) {
6090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6091 return;
6092 }
6093
6094 gen_helper_booke206_tlbre(cpu_env);
6095 #endif
6096 }
6097
6098 /* tlbsx - tlbsx. */
6099 static void gen_tlbsx_booke206(DisasContext *ctx)
6100 {
6101 #if defined(CONFIG_USER_ONLY)
6102 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6103 #else
6104 TCGv t0;
6105 if (unlikely(!ctx->mem_idx)) {
6106 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6107 return;
6108 }
6109
6110 if (rA(ctx->opcode)) {
6111 t0 = tcg_temp_new();
6112 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6113 } else {
6114 t0 = tcg_const_tl(0);
6115 }
6116
6117 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6118 gen_helper_booke206_tlbsx(cpu_env, t0);
6119 #endif
6120 }
6121
6122 /* tlbwe */
6123 static void gen_tlbwe_booke206(DisasContext *ctx)
6124 {
6125 #if defined(CONFIG_USER_ONLY)
6126 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6127 #else
6128 if (unlikely(!ctx->mem_idx)) {
6129 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6130 return;
6131 }
6132 gen_update_nip(ctx, ctx->nip - 4);
6133 gen_helper_booke206_tlbwe(cpu_env);
6134 #endif
6135 }
6136
6137 static void gen_tlbivax_booke206(DisasContext *ctx)
6138 {
6139 #if defined(CONFIG_USER_ONLY)
6140 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6141 #else
6142 TCGv t0;
6143 if (unlikely(!ctx->mem_idx)) {
6144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6145 return;
6146 }
6147
6148 t0 = tcg_temp_new();
6149 gen_addr_reg_index(ctx, t0);
6150
6151 gen_helper_booke206_tlbivax(cpu_env, t0);
6152 #endif
6153 }
6154
6155 static void gen_tlbilx_booke206(DisasContext *ctx)
6156 {
6157 #if defined(CONFIG_USER_ONLY)
6158 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6159 #else
6160 TCGv t0;
6161 if (unlikely(!ctx->mem_idx)) {
6162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6163 return;
6164 }
6165
6166 t0 = tcg_temp_new();
6167 gen_addr_reg_index(ctx, t0);
6168
6169 switch((ctx->opcode >> 21) & 0x3) {
6170 case 0:
6171 gen_helper_booke206_tlbilx0(cpu_env, t0);
6172 break;
6173 case 1:
6174 gen_helper_booke206_tlbilx1(cpu_env, t0);
6175 break;
6176 case 3:
6177 gen_helper_booke206_tlbilx3(cpu_env, t0);
6178 break;
6179 default:
6180 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6181 break;
6182 }
6183
6184 tcg_temp_free(t0);
6185 #endif
6186 }
6187
6188
6189 /* wrtee */
6190 static void gen_wrtee(DisasContext *ctx)
6191 {
6192 #if defined(CONFIG_USER_ONLY)
6193 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6194 #else
6195 TCGv t0;
6196 if (unlikely(!ctx->mem_idx)) {
6197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6198 return;
6199 }
6200 t0 = tcg_temp_new();
6201 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6202 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6203 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6204 tcg_temp_free(t0);
6205 /* Stop translation to have a chance to raise an exception
6206 * if we just set msr_ee to 1
6207 */
6208 gen_stop_exception(ctx);
6209 #endif
6210 }
6211
6212 /* wrteei */
6213 static void gen_wrteei(DisasContext *ctx)
6214 {
6215 #if defined(CONFIG_USER_ONLY)
6216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6217 #else
6218 if (unlikely(!ctx->mem_idx)) {
6219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6220 return;
6221 }
6222 if (ctx->opcode & 0x00008000) {
6223 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6224 /* Stop translation to have a chance to raise an exception */
6225 gen_stop_exception(ctx);
6226 } else {
6227 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6228 }
6229 #endif
6230 }
6231
6232 /* PowerPC 440 specific instructions */
6233
6234 /* dlmzb */
6235 static void gen_dlmzb(DisasContext *ctx)
6236 {
6237 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6238 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6239 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6240 tcg_temp_free_i32(t0);
6241 }
6242
6243 /* mbar replaces eieio on 440 */
6244 static void gen_mbar(DisasContext *ctx)
6245 {
6246 /* interpreted as no-op */
6247 }
6248
6249 /* msync replaces sync on 440 */
6250 static void gen_msync_4xx(DisasContext *ctx)
6251 {
6252 /* interpreted as no-op */
6253 }
6254
6255 /* icbt */
6256 static void gen_icbt_440(DisasContext *ctx)
6257 {
6258 /* interpreted as no-op */
6259 /* XXX: specification say this is treated as a load by the MMU
6260 * but does not generate any exception
6261 */
6262 }
6263
6264 /* Embedded.Processor Control */
6265
6266 static void gen_msgclr(DisasContext *ctx)
6267 {
6268 #if defined(CONFIG_USER_ONLY)
6269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6270 #else
6271 if (unlikely(ctx->mem_idx == 0)) {
6272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6273 return;
6274 }
6275
6276 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6277 #endif
6278 }
6279
6280 static void gen_msgsnd(DisasContext *ctx)
6281 {
6282 #if defined(CONFIG_USER_ONLY)
6283 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6284 #else
6285 if (unlikely(ctx->mem_idx == 0)) {
6286 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6287 return;
6288 }
6289
6290 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6291 #endif
6292 }
6293
6294 /*** Altivec vector extension ***/
6295 /* Altivec registers moves */
6296
6297 static inline TCGv_ptr gen_avr_ptr(int reg)
6298 {
6299 TCGv_ptr r = tcg_temp_new_ptr();
6300 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6301 return r;
6302 }
6303
6304 #define GEN_VR_LDX(name, opc2, opc3) \
6305 static void glue(gen_, name)(DisasContext *ctx) \
6306 { \
6307 TCGv EA; \
6308 if (unlikely(!ctx->altivec_enabled)) { \
6309 gen_exception(ctx, POWERPC_EXCP_VPU); \
6310 return; \
6311 } \
6312 gen_set_access_type(ctx, ACCESS_INT); \
6313 EA = tcg_temp_new(); \
6314 gen_addr_reg_index(ctx, EA); \
6315 tcg_gen_andi_tl(EA, EA, ~0xf); \
6316 if (ctx->le_mode) { \
6317 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6318 tcg_gen_addi_tl(EA, EA, 8); \
6319 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6320 } else { \
6321 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6322 tcg_gen_addi_tl(EA, EA, 8); \
6323 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6324 } \
6325 tcg_temp_free(EA); \
6326 }
6327
6328 #define GEN_VR_STX(name, opc2, opc3) \
6329 static void gen_st##name(DisasContext *ctx) \
6330 { \
6331 TCGv EA; \
6332 if (unlikely(!ctx->altivec_enabled)) { \
6333 gen_exception(ctx, POWERPC_EXCP_VPU); \
6334 return; \
6335 } \
6336 gen_set_access_type(ctx, ACCESS_INT); \
6337 EA = tcg_temp_new(); \
6338 gen_addr_reg_index(ctx, EA); \
6339 tcg_gen_andi_tl(EA, EA, ~0xf); \
6340 if (ctx->le_mode) { \
6341 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6342 tcg_gen_addi_tl(EA, EA, 8); \
6343 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6344 } else { \
6345 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6346 tcg_gen_addi_tl(EA, EA, 8); \
6347 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6348 } \
6349 tcg_temp_free(EA); \
6350 }
6351
6352 #define GEN_VR_LVE(name, opc2, opc3) \
6353 static void gen_lve##name(DisasContext *ctx) \
6354 { \
6355 TCGv EA; \
6356 TCGv_ptr rs; \
6357 if (unlikely(!ctx->altivec_enabled)) { \
6358 gen_exception(ctx, POWERPC_EXCP_VPU); \
6359 return; \
6360 } \
6361 gen_set_access_type(ctx, ACCESS_INT); \
6362 EA = tcg_temp_new(); \
6363 gen_addr_reg_index(ctx, EA); \
6364 rs = gen_avr_ptr(rS(ctx->opcode)); \
6365 gen_helper_lve##name(cpu_env, rs, EA); \
6366 tcg_temp_free(EA); \
6367 tcg_temp_free_ptr(rs); \
6368 }
6369
6370 #define GEN_VR_STVE(name, opc2, opc3) \
6371 static void gen_stve##name(DisasContext *ctx) \
6372 { \
6373 TCGv EA; \
6374 TCGv_ptr rs; \
6375 if (unlikely(!ctx->altivec_enabled)) { \
6376 gen_exception(ctx, POWERPC_EXCP_VPU); \
6377 return; \
6378 } \
6379 gen_set_access_type(ctx, ACCESS_INT); \
6380 EA = tcg_temp_new(); \
6381 gen_addr_reg_index(ctx, EA); \
6382 rs = gen_avr_ptr(rS(ctx->opcode)); \
6383 gen_helper_stve##name(cpu_env, rs, EA); \
6384 tcg_temp_free(EA); \
6385 tcg_temp_free_ptr(rs); \
6386 }
6387
6388 GEN_VR_LDX(lvx, 0x07, 0x03);
6389 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6390 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6391
6392 GEN_VR_LVE(bx, 0x07, 0x00);
6393 GEN_VR_LVE(hx, 0x07, 0x01);
6394 GEN_VR_LVE(wx, 0x07, 0x02);
6395
6396 GEN_VR_STX(svx, 0x07, 0x07);
6397 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6398 GEN_VR_STX(svxl, 0x07, 0x0F);
6399
6400 GEN_VR_STVE(bx, 0x07, 0x04);
6401 GEN_VR_STVE(hx, 0x07, 0x05);
6402 GEN_VR_STVE(wx, 0x07, 0x06);
6403
6404 static void gen_lvsl(DisasContext *ctx)
6405 {
6406 TCGv_ptr rd;
6407 TCGv EA;
6408 if (unlikely(!ctx->altivec_enabled)) {
6409 gen_exception(ctx, POWERPC_EXCP_VPU);
6410 return;
6411 }
6412 EA = tcg_temp_new();
6413 gen_addr_reg_index(ctx, EA);
6414 rd = gen_avr_ptr(rD(ctx->opcode));
6415 gen_helper_lvsl(rd, EA);
6416 tcg_temp_free(EA);
6417 tcg_temp_free_ptr(rd);
6418 }
6419
6420 static void gen_lvsr(DisasContext *ctx)
6421 {
6422 TCGv_ptr rd;
6423 TCGv EA;
6424 if (unlikely(!ctx->altivec_enabled)) {
6425 gen_exception(ctx, POWERPC_EXCP_VPU);
6426 return;
6427 }
6428 EA = tcg_temp_new();
6429 gen_addr_reg_index(ctx, EA);
6430 rd = gen_avr_ptr(rD(ctx->opcode));
6431 gen_helper_lvsr(rd, EA);
6432 tcg_temp_free(EA);
6433 tcg_temp_free_ptr(rd);
6434 }
6435
6436 static void gen_mfvscr(DisasContext *ctx)
6437 {
6438 TCGv_i32 t;
6439 if (unlikely(!ctx->altivec_enabled)) {
6440 gen_exception(ctx, POWERPC_EXCP_VPU);
6441 return;
6442 }
6443 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6444 t = tcg_temp_new_i32();
6445 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6446 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6447 tcg_temp_free_i32(t);
6448 }
6449
6450 static void gen_mtvscr(DisasContext *ctx)
6451 {
6452 TCGv_ptr p;
6453 if (unlikely(!ctx->altivec_enabled)) {
6454 gen_exception(ctx, POWERPC_EXCP_VPU);
6455 return;
6456 }
6457 p = gen_avr_ptr(rD(ctx->opcode));
6458 gen_helper_mtvscr(cpu_env, p);
6459 tcg_temp_free_ptr(p);
6460 }
6461
6462 /* Logical operations */
6463 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6464 static void glue(gen_, name)(DisasContext *ctx) \
6465 { \
6466 if (unlikely(!ctx->altivec_enabled)) { \
6467 gen_exception(ctx, POWERPC_EXCP_VPU); \
6468 return; \
6469 } \
6470 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6471 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6472 }
6473
6474 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6475 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6476 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6477 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6478 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6479
6480 #define GEN_VXFORM(name, opc2, opc3) \
6481 static void glue(gen_, name)(DisasContext *ctx) \
6482 { \
6483 TCGv_ptr ra, rb, rd; \
6484 if (unlikely(!ctx->altivec_enabled)) { \
6485 gen_exception(ctx, POWERPC_EXCP_VPU); \
6486 return; \
6487 } \
6488 ra = gen_avr_ptr(rA(ctx->opcode)); \
6489 rb = gen_avr_ptr(rB(ctx->opcode)); \
6490 rd = gen_avr_ptr(rD(ctx->opcode)); \
6491 gen_helper_##name (rd, ra, rb); \
6492 tcg_temp_free_ptr(ra); \
6493 tcg_temp_free_ptr(rb); \
6494 tcg_temp_free_ptr(rd); \
6495 }
6496
6497 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6498 static void glue(gen_, name)(DisasContext *ctx) \
6499 { \
6500 TCGv_ptr ra, rb, rd; \
6501 if (unlikely(!ctx->altivec_enabled)) { \
6502 gen_exception(ctx, POWERPC_EXCP_VPU); \
6503 return; \
6504 } \
6505 ra = gen_avr_ptr(rA(ctx->opcode)); \
6506 rb = gen_avr_ptr(rB(ctx->opcode)); \
6507 rd = gen_avr_ptr(rD(ctx->opcode)); \
6508 gen_helper_##name(cpu_env, rd, ra, rb); \
6509 tcg_temp_free_ptr(ra); \
6510 tcg_temp_free_ptr(rb); \
6511 tcg_temp_free_ptr(rd); \
6512 }
6513
6514 GEN_VXFORM(vaddubm, 0, 0);
6515 GEN_VXFORM(vadduhm, 0, 1);
6516 GEN_VXFORM(vadduwm, 0, 2);
6517 GEN_VXFORM(vsububm, 0, 16);
6518 GEN_VXFORM(vsubuhm, 0, 17);
6519 GEN_VXFORM(vsubuwm, 0, 18);
6520 GEN_VXFORM(vmaxub, 1, 0);
6521 GEN_VXFORM(vmaxuh, 1, 1);
6522 GEN_VXFORM(vmaxuw, 1, 2);
6523 GEN_VXFORM(vmaxsb, 1, 4);
6524 GEN_VXFORM(vmaxsh, 1, 5);
6525 GEN_VXFORM(vmaxsw, 1, 6);
6526 GEN_VXFORM(vminub, 1, 8);
6527 GEN_VXFORM(vminuh, 1, 9);
6528 GEN_VXFORM(vminuw, 1, 10);
6529 GEN_VXFORM(vminsb, 1, 12);
6530 GEN_VXFORM(vminsh, 1, 13);
6531 GEN_VXFORM(vminsw, 1, 14);
6532 GEN_VXFORM(vavgub, 1, 16);
6533 GEN_VXFORM(vavguh, 1, 17);
6534 GEN_VXFORM(vavguw, 1, 18);
6535 GEN_VXFORM(vavgsb, 1, 20);
6536 GEN_VXFORM(vavgsh, 1, 21);
6537 GEN_VXFORM(vavgsw, 1, 22);
6538 GEN_VXFORM(vmrghb, 6, 0);
6539 GEN_VXFORM(vmrghh, 6, 1);
6540 GEN_VXFORM(vmrghw, 6, 2);
6541 GEN_VXFORM(vmrglb, 6, 4);
6542 GEN_VXFORM(vmrglh, 6, 5);
6543 GEN_VXFORM(vmrglw, 6, 6);
6544 GEN_VXFORM(vmuloub, 4, 0);
6545 GEN_VXFORM(vmulouh, 4, 1);
6546 GEN_VXFORM(vmulosb, 4, 4);
6547 GEN_VXFORM(vmulosh, 4, 5);
6548 GEN_VXFORM(vmuleub, 4, 8);
6549 GEN_VXFORM(vmuleuh, 4, 9);
6550 GEN_VXFORM(vmulesb, 4, 12);
6551 GEN_VXFORM(vmulesh, 4, 13);
6552 GEN_VXFORM(vslb, 2, 4);
6553 GEN_VXFORM(vslh, 2, 5);
6554 GEN_VXFORM(vslw, 2, 6);
6555 GEN_VXFORM(vsrb, 2, 8);
6556 GEN_VXFORM(vsrh, 2, 9);
6557 GEN_VXFORM(vsrw, 2, 10);
6558 GEN_VXFORM(vsrab, 2, 12);
6559 GEN_VXFORM(vsrah, 2, 13);
6560 GEN_VXFORM(vsraw, 2, 14);
6561 GEN_VXFORM(vslo, 6, 16);
6562 GEN_VXFORM(vsro, 6, 17);
6563 GEN_VXFORM(vaddcuw, 0, 6);
6564 GEN_VXFORM(vsubcuw, 0, 22);
6565 GEN_VXFORM_ENV(vaddubs, 0, 8);
6566 GEN_VXFORM_ENV(vadduhs, 0, 9);
6567 GEN_VXFORM_ENV(vadduws, 0, 10);
6568 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6569 GEN_VXFORM_ENV(vaddshs, 0, 13);
6570 GEN_VXFORM_ENV(vaddsws, 0, 14);
6571 GEN_VXFORM_ENV(vsububs, 0, 24);
6572 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6573 GEN_VXFORM_ENV(vsubuws, 0, 26);
6574 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6575 GEN_VXFORM_ENV(vsubshs, 0, 29);
6576 GEN_VXFORM_ENV(vsubsws, 0, 30);
6577 GEN_VXFORM(vrlb, 2, 0);
6578 GEN_VXFORM(vrlh, 2, 1);
6579 GEN_VXFORM(vrlw, 2, 2);
6580 GEN_VXFORM(vsl, 2, 7);
6581 GEN_VXFORM(vsr, 2, 11);
6582 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6583 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6584 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6585 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6586 GEN_VXFORM_ENV(vpkshus, 7, 4);
6587 GEN_VXFORM_ENV(vpkswus, 7, 5);
6588 GEN_VXFORM_ENV(vpkshss, 7, 6);
6589 GEN_VXFORM_ENV(vpkswss, 7, 7);
6590 GEN_VXFORM(vpkpx, 7, 12);
6591 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6592 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6593 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6594 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6595 GEN_VXFORM_ENV(vsumsws, 4, 30);
6596 GEN_VXFORM_ENV(vaddfp, 5, 0);
6597 GEN_VXFORM_ENV(vsubfp, 5, 1);
6598 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6599 GEN_VXFORM_ENV(vminfp, 5, 17);
6600
6601 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6602 static void glue(gen_, name)(DisasContext *ctx) \
6603 { \
6604 TCGv_ptr ra, rb, rd; \
6605 if (unlikely(!ctx->altivec_enabled)) { \
6606 gen_exception(ctx, POWERPC_EXCP_VPU); \
6607 return; \
6608 } \
6609 ra = gen_avr_ptr(rA(ctx->opcode)); \
6610 rb = gen_avr_ptr(rB(ctx->opcode)); \
6611 rd = gen_avr_ptr(rD(ctx->opcode)); \
6612 gen_helper_##opname(cpu_env, rd, ra, rb); \
6613 tcg_temp_free_ptr(ra); \
6614 tcg_temp_free_ptr(rb); \
6615 tcg_temp_free_ptr(rd); \
6616 }
6617
6618 #define GEN_VXRFORM(name, opc2, opc3) \
6619 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6620 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6621
6622 GEN_VXRFORM(vcmpequb, 3, 0)
6623 GEN_VXRFORM(vcmpequh, 3, 1)
6624 GEN_VXRFORM(vcmpequw, 3, 2)
6625 GEN_VXRFORM(vcmpgtsb, 3, 12)
6626 GEN_VXRFORM(vcmpgtsh, 3, 13)
6627 GEN_VXRFORM(vcmpgtsw, 3, 14)
6628 GEN_VXRFORM(vcmpgtub, 3, 8)
6629 GEN_VXRFORM(vcmpgtuh, 3, 9)
6630 GEN_VXRFORM(vcmpgtuw, 3, 10)
6631 GEN_VXRFORM(vcmpeqfp, 3, 3)
6632 GEN_VXRFORM(vcmpgefp, 3, 7)
6633 GEN_VXRFORM(vcmpgtfp, 3, 11)
6634 GEN_VXRFORM(vcmpbfp, 3, 15)
6635
6636 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6637 static void glue(gen_, name)(DisasContext *ctx) \
6638 { \
6639 TCGv_ptr rd; \
6640 TCGv_i32 simm; \
6641 if (unlikely(!ctx->altivec_enabled)) { \
6642 gen_exception(ctx, POWERPC_EXCP_VPU); \
6643 return; \
6644 } \
6645 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6646 rd = gen_avr_ptr(rD(ctx->opcode)); \
6647 gen_helper_##name (rd, simm); \
6648 tcg_temp_free_i32(simm); \
6649 tcg_temp_free_ptr(rd); \
6650 }
6651
6652 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6653 GEN_VXFORM_SIMM(vspltish, 6, 13);
6654 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6655
6656 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6657 static void glue(gen_, name)(DisasContext *ctx) \
6658 { \
6659 TCGv_ptr rb, rd; \
6660 if (unlikely(!ctx->altivec_enabled)) { \
6661 gen_exception(ctx, POWERPC_EXCP_VPU); \
6662 return; \
6663 } \
6664 rb = gen_avr_ptr(rB(ctx->opcode)); \
6665 rd = gen_avr_ptr(rD(ctx->opcode)); \
6666 gen_helper_##name (rd, rb); \
6667 tcg_temp_free_ptr(rb); \
6668 tcg_temp_free_ptr(rd); \
6669 }
6670
6671 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6672 static void glue(gen_, name)(DisasContext *ctx) \
6673 { \
6674 TCGv_ptr rb, rd; \
6675 \
6676 if (unlikely(!ctx->altivec_enabled)) { \
6677 gen_exception(ctx, POWERPC_EXCP_VPU); \
6678 return; \
6679 } \
6680 rb = gen_avr_ptr(rB(ctx->opcode)); \
6681 rd = gen_avr_ptr(rD(ctx->opcode)); \
6682 gen_helper_##name(cpu_env, rd, rb); \
6683 tcg_temp_free_ptr(rb); \
6684 tcg_temp_free_ptr(rd); \
6685 }
6686
6687 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6688 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6689 GEN_VXFORM_NOA(vupklsb, 7, 10);
6690 GEN_VXFORM_NOA(vupklsh, 7, 11);
6691 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6692 GEN_VXFORM_NOA(vupklpx, 7, 15);
6693 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6694 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6695 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6696 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6697 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6698 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6699 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6700 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6701
6702 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6703 static void glue(gen_, name)(DisasContext *ctx) \
6704 { \
6705 TCGv_ptr rd; \
6706 TCGv_i32 simm; \
6707 if (unlikely(!ctx->altivec_enabled)) { \
6708 gen_exception(ctx, POWERPC_EXCP_VPU); \
6709 return; \
6710 } \
6711 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6712 rd = gen_avr_ptr(rD(ctx->opcode)); \
6713 gen_helper_##name (rd, simm); \
6714 tcg_temp_free_i32(simm); \
6715 tcg_temp_free_ptr(rd); \
6716 }
6717
6718 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6719 static void glue(gen_, name)(DisasContext *ctx) \
6720 { \
6721 TCGv_ptr rb, rd; \
6722 TCGv_i32 uimm; \
6723 if (unlikely(!ctx->altivec_enabled)) { \
6724 gen_exception(ctx, POWERPC_EXCP_VPU); \
6725 return; \
6726 } \
6727 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6728 rb = gen_avr_ptr(rB(ctx->opcode)); \
6729 rd = gen_avr_ptr(rD(ctx->opcode)); \
6730 gen_helper_##name (rd, rb, uimm); \
6731 tcg_temp_free_i32(uimm); \
6732 tcg_temp_free_ptr(rb); \
6733 tcg_temp_free_ptr(rd); \
6734 }
6735
6736 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6737 static void glue(gen_, name)(DisasContext *ctx) \
6738 { \
6739 TCGv_ptr rb, rd; \
6740 TCGv_i32 uimm; \
6741 \
6742 if (unlikely(!ctx->altivec_enabled)) { \
6743 gen_exception(ctx, POWERPC_EXCP_VPU); \
6744 return; \
6745 } \
6746 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6747 rb = gen_avr_ptr(rB(ctx->opcode)); \
6748 rd = gen_avr_ptr(rD(ctx->opcode)); \
6749 gen_helper_##name(cpu_env, rd, rb, uimm); \
6750 tcg_temp_free_i32(uimm); \
6751 tcg_temp_free_ptr(rb); \
6752 tcg_temp_free_ptr(rd); \
6753 }
6754
6755 GEN_VXFORM_UIMM(vspltb, 6, 8);
6756 GEN_VXFORM_UIMM(vsplth, 6, 9);
6757 GEN_VXFORM_UIMM(vspltw, 6, 10);
6758 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6759 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6760 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6761 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6762
6763 static void gen_vsldoi(DisasContext *ctx)
6764 {
6765 TCGv_ptr ra, rb, rd;
6766 TCGv_i32 sh;
6767 if (unlikely(!ctx->altivec_enabled)) {
6768 gen_exception(ctx, POWERPC_EXCP_VPU);
6769 return;
6770 }
6771 ra = gen_avr_ptr(rA(ctx->opcode));
6772 rb = gen_avr_ptr(rB(ctx->opcode));
6773 rd = gen_avr_ptr(rD(ctx->opcode));
6774 sh = tcg_const_i32(VSH(ctx->opcode));
6775 gen_helper_vsldoi (rd, ra, rb, sh);
6776 tcg_temp_free_ptr(ra);
6777 tcg_temp_free_ptr(rb);
6778 tcg_temp_free_ptr(rd);
6779 tcg_temp_free_i32(sh);
6780 }
6781
6782 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6783 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6784 { \
6785 TCGv_ptr ra, rb, rc, rd; \
6786 if (unlikely(!ctx->altivec_enabled)) { \
6787 gen_exception(ctx, POWERPC_EXCP_VPU); \
6788 return; \
6789 } \
6790 ra = gen_avr_ptr(rA(ctx->opcode)); \
6791 rb = gen_avr_ptr(rB(ctx->opcode)); \
6792 rc = gen_avr_ptr(rC(ctx->opcode)); \
6793 rd = gen_avr_ptr(rD(ctx->opcode)); \
6794 if (Rc(ctx->opcode)) { \
6795 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6796 } else { \
6797 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6798 } \
6799 tcg_temp_free_ptr(ra); \
6800 tcg_temp_free_ptr(rb); \
6801 tcg_temp_free_ptr(rc); \
6802 tcg_temp_free_ptr(rd); \
6803 }
6804
6805 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6806
6807 static void gen_vmladduhm(DisasContext *ctx)
6808 {
6809 TCGv_ptr ra, rb, rc, rd;
6810 if (unlikely(!ctx->altivec_enabled)) {
6811 gen_exception(ctx, POWERPC_EXCP_VPU);
6812 return;
6813 }
6814 ra = gen_avr_ptr(rA(ctx->opcode));
6815 rb = gen_avr_ptr(rB(ctx->opcode));
6816 rc = gen_avr_ptr(rC(ctx->opcode));
6817 rd = gen_avr_ptr(rD(ctx->opcode));
6818 gen_helper_vmladduhm(rd, ra, rb, rc);
6819 tcg_temp_free_ptr(ra);
6820 tcg_temp_free_ptr(rb);
6821 tcg_temp_free_ptr(rc);
6822 tcg_temp_free_ptr(rd);
6823 }
6824
6825 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6826 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6827 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6828 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6829 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6830
6831 /*** SPE extension ***/
6832 /* Register moves */
6833
6834
6835 static inline void gen_evmra(DisasContext *ctx)
6836 {
6837
6838 if (unlikely(!ctx->spe_enabled)) {
6839 gen_exception(ctx, POWERPC_EXCP_SPEU);
6840 return;
6841 }
6842
6843 #if defined(TARGET_PPC64)
6844 /* rD := rA */
6845 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6846
6847 /* spe_acc := rA */
6848 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6849 cpu_env,
6850 offsetof(CPUPPCState, spe_acc));
6851 #else
6852 TCGv_i64 tmp = tcg_temp_new_i64();
6853
6854 /* tmp := rA_lo + rA_hi << 32 */
6855 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6856
6857 /* spe_acc := tmp */
6858 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6859 tcg_temp_free_i64(tmp);
6860
6861 /* rD := rA */
6862 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6863 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6864 #endif
6865 }
6866
6867 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6868 {
6869 #if defined(TARGET_PPC64)
6870 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6871 #else
6872 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6873 #endif
6874 }
6875
6876 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6877 {
6878 #if defined(TARGET_PPC64)
6879 tcg_gen_mov_i64(cpu_gpr[reg], t);
6880 #else
6881 TCGv_i64 tmp = tcg_temp_new_i64();
6882 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6883 tcg_gen_shri_i64(tmp, t, 32);
6884 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6885 tcg_temp_free_i64(tmp);
6886 #endif
6887 }
6888
6889 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6890 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6891 { \
6892 if (Rc(ctx->opcode)) \
6893 gen_##name1(ctx); \
6894 else \
6895 gen_##name0(ctx); \
6896 }
6897
6898 /* Handler for undefined SPE opcodes */
6899 static inline void gen_speundef(DisasContext *ctx)
6900 {
6901 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6902 }
6903
6904 /* SPE logic */
6905 #if defined(TARGET_PPC64)
6906 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6907 static inline void gen_##name(DisasContext *ctx) \
6908 { \
6909 if (unlikely(!ctx->spe_enabled)) { \
6910 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6911 return; \
6912 } \
6913 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6914 cpu_gpr[rB(ctx->opcode)]); \
6915 }
6916 #else
6917 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6918 static inline void gen_##name(DisasContext *ctx) \
6919 { \
6920 if (unlikely(!ctx->spe_enabled)) { \
6921 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6922 return; \
6923 } \
6924 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6925 cpu_gpr[rB(ctx->opcode)]); \
6926 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6927 cpu_gprh[rB(ctx->opcode)]); \
6928 }
6929 #endif
6930
6931 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6932 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6933 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6934 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6935 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6936 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6937 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6938 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6939
6940 /* SPE logic immediate */
6941 #if defined(TARGET_PPC64)
6942 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6943 static inline void gen_##name(DisasContext *ctx) \
6944 { \
6945 if (unlikely(!ctx->spe_enabled)) { \
6946 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6947 return; \
6948 } \
6949 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6950 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6951 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6952 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6953 tcg_opi(t0, t0, rB(ctx->opcode)); \
6954 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6955 tcg_gen_trunc_i64_i32(t1, t2); \
6956 tcg_temp_free_i64(t2); \
6957 tcg_opi(t1, t1, rB(ctx->opcode)); \
6958 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6959 tcg_temp_free_i32(t0); \
6960 tcg_temp_free_i32(t1); \
6961 }
6962 #else
6963 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6964 static inline void gen_##name(DisasContext *ctx) \
6965 { \
6966 if (unlikely(!ctx->spe_enabled)) { \
6967 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6968 return; \
6969 } \
6970 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6971 rB(ctx->opcode)); \
6972 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6973 rB(ctx->opcode)); \
6974 }
6975 #endif
6976 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6977 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6978 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6979 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6980
6981 /* SPE arithmetic */
6982 #if defined(TARGET_PPC64)
6983 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6984 static inline void gen_##name(DisasContext *ctx) \
6985 { \
6986 if (unlikely(!ctx->spe_enabled)) { \
6987 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6988 return; \
6989 } \
6990 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6991 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6992 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6993 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6994 tcg_op(t0, t0); \
6995 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6996 tcg_gen_trunc_i64_i32(t1, t2); \
6997 tcg_temp_free_i64(t2); \
6998 tcg_op(t1, t1); \
6999 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7000 tcg_temp_free_i32(t0); \
7001 tcg_temp_free_i32(t1); \
7002 }
7003 #else
7004 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7005 static inline void gen_##name(DisasContext *ctx) \
7006 { \
7007 if (unlikely(!ctx->spe_enabled)) { \
7008 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7009 return; \
7010 } \
7011 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7012 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7013 }
7014 #endif
7015
7016 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
7017 {
7018 int l1 = gen_new_label();
7019 int l2 = gen_new_label();
7020
7021 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
7022 tcg_gen_neg_i32(ret, arg1);
7023 tcg_gen_br(l2);
7024 gen_set_label(l1);
7025 tcg_gen_mov_i32(ret, arg1);
7026 gen_set_label(l2);
7027 }
7028 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7029 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7030 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7031 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7032 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7033 {
7034 tcg_gen_addi_i32(ret, arg1, 0x8000);
7035 tcg_gen_ext16u_i32(ret, ret);
7036 }
7037 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7038 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7039 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7040
7041 #if defined(TARGET_PPC64)
7042 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7043 static inline void gen_##name(DisasContext *ctx) \
7044 { \
7045 if (unlikely(!ctx->spe_enabled)) { \
7046 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7047 return; \
7048 } \
7049 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7050 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7051 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7052 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7053 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7054 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7055 tcg_op(t0, t0, t2); \
7056 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7057 tcg_gen_trunc_i64_i32(t1, t3); \
7058 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7059 tcg_gen_trunc_i64_i32(t2, t3); \
7060 tcg_temp_free_i64(t3); \
7061 tcg_op(t1, t1, t2); \
7062 tcg_temp_free_i32(t2); \
7063 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7064 tcg_temp_free_i32(t0); \
7065 tcg_temp_free_i32(t1); \
7066 }
7067 #else
7068 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7069 static inline void gen_##name(DisasContext *ctx) \
7070 { \
7071 if (unlikely(!ctx->spe_enabled)) { \
7072 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7073 return; \
7074 } \
7075 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7076 cpu_gpr[rB(ctx->opcode)]); \
7077 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7078 cpu_gprh[rB(ctx->opcode)]); \
7079 }
7080 #endif
7081
7082 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7083 {
7084 TCGv_i32 t0;
7085 int l1, l2;
7086
7087 l1 = gen_new_label();
7088 l2 = gen_new_label();
7089 t0 = tcg_temp_local_new_i32();
7090 /* No error here: 6 bits are used */
7091 tcg_gen_andi_i32(t0, arg2, 0x3F);
7092 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7093 tcg_gen_shr_i32(ret, arg1, t0);
7094 tcg_gen_br(l2);
7095 gen_set_label(l1);
7096 tcg_gen_movi_i32(ret, 0);
7097 gen_set_label(l2);
7098 tcg_temp_free_i32(t0);
7099 }
7100 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7101 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7102 {
7103 TCGv_i32 t0;
7104 int l1, l2;
7105
7106 l1 = gen_new_label();
7107 l2 = gen_new_label();
7108 t0 = tcg_temp_local_new_i32();
7109 /* No error here: 6 bits are used */
7110 tcg_gen_andi_i32(t0, arg2, 0x3F);
7111 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7112 tcg_gen_sar_i32(ret, arg1, t0);
7113 tcg_gen_br(l2);
7114 gen_set_label(l1);
7115 tcg_gen_movi_i32(ret, 0);
7116 gen_set_label(l2);
7117 tcg_temp_free_i32(t0);
7118 }
7119 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7120 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7121 {
7122 TCGv_i32 t0;
7123 int l1, l2;
7124
7125 l1 = gen_new_label();
7126 l2 = gen_new_label();
7127 t0 = tcg_temp_local_new_i32();
7128 /* No error here: 6 bits are used */
7129 tcg_gen_andi_i32(t0, arg2, 0x3F);
7130 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7131 tcg_gen_shl_i32(ret, arg1, t0);
7132 tcg_gen_br(l2);
7133 gen_set_label(l1);
7134 tcg_gen_movi_i32(ret, 0);
7135 gen_set_label(l2);
7136 tcg_temp_free_i32(t0);
7137 }
7138 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7139 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7140 {
7141 TCGv_i32 t0 = tcg_temp_new_i32();
7142 tcg_gen_andi_i32(t0, arg2, 0x1F);
7143 tcg_gen_rotl_i32(ret, arg1, t0);
7144 tcg_temp_free_i32(t0);
7145 }
7146 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7147 static inline void gen_evmergehi(DisasContext *ctx)
7148 {
7149 if (unlikely(!ctx->spe_enabled)) {
7150 gen_exception(ctx, POWERPC_EXCP_SPEU);
7151 return;
7152 }
7153 #if defined(TARGET_PPC64)
7154 TCGv t0 = tcg_temp_new();
7155 TCGv t1 = tcg_temp_new();
7156 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7157 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7158 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7159 tcg_temp_free(t0);
7160 tcg_temp_free(t1);
7161 #else
7162 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7163 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7164 #endif
7165 }
7166 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7167 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7168 {
7169 tcg_gen_sub_i32(ret, arg2, arg1);
7170 }
7171 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7172
7173 /* SPE arithmetic immediate */
7174 #if defined(TARGET_PPC64)
7175 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7176 static inline void gen_##name(DisasContext *ctx) \
7177 { \
7178 if (unlikely(!ctx->spe_enabled)) { \
7179 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7180 return; \
7181 } \
7182 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7183 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7184 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7185 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7186 tcg_op(t0, t0, rA(ctx->opcode)); \
7187 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7188 tcg_gen_trunc_i64_i32(t1, t2); \
7189 tcg_temp_free_i64(t2); \
7190 tcg_op(t1, t1, rA(ctx->opcode)); \
7191 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7192 tcg_temp_free_i32(t0); \
7193 tcg_temp_free_i32(t1); \
7194 }
7195 #else
7196 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7197 static inline void gen_##name(DisasContext *ctx) \
7198 { \
7199 if (unlikely(!ctx->spe_enabled)) { \
7200 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7201 return; \
7202 } \
7203 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7204 rA(ctx->opcode)); \
7205 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7206 rA(ctx->opcode)); \
7207 }
7208 #endif
7209 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7210 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7211
7212 /* SPE comparison */
7213 #if defined(TARGET_PPC64)
7214 #define GEN_SPEOP_COMP(name, tcg_cond) \
7215 static inline void gen_##name(DisasContext *ctx) \
7216 { \
7217 if (unlikely(!ctx->spe_enabled)) { \
7218 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7219 return; \
7220 } \
7221 int l1 = gen_new_label(); \
7222 int l2 = gen_new_label(); \
7223 int l3 = gen_new_label(); \
7224 int l4 = gen_new_label(); \
7225 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7226 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7227 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7228 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7229 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7230 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7231 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7232 tcg_gen_br(l2); \
7233 gen_set_label(l1); \
7234 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7235 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7236 gen_set_label(l2); \
7237 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7238 tcg_gen_trunc_i64_i32(t0, t2); \
7239 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7240 tcg_gen_trunc_i64_i32(t1, t2); \
7241 tcg_temp_free_i64(t2); \
7242 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7243 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7244 ~(CRF_CH | CRF_CH_AND_CL)); \
7245 tcg_gen_br(l4); \
7246 gen_set_label(l3); \
7247 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7248 CRF_CH | CRF_CH_OR_CL); \
7249 gen_set_label(l4); \
7250 tcg_temp_free_i32(t0); \
7251 tcg_temp_free_i32(t1); \
7252 }
7253 #else
7254 #define GEN_SPEOP_COMP(name, tcg_cond) \
7255 static inline void gen_##name(DisasContext *ctx) \
7256 { \
7257 if (unlikely(!ctx->spe_enabled)) { \
7258 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7259 return; \
7260 } \
7261 int l1 = gen_new_label(); \
7262 int l2 = gen_new_label(); \
7263 int l3 = gen_new_label(); \
7264 int l4 = gen_new_label(); \
7265 \
7266 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7267 cpu_gpr[rB(ctx->opcode)], l1); \
7268 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7269 tcg_gen_br(l2); \
7270 gen_set_label(l1); \
7271 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7272 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7273 gen_set_label(l2); \
7274 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7275 cpu_gprh[rB(ctx->opcode)], l3); \
7276 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7277 ~(CRF_CH | CRF_CH_AND_CL)); \
7278 tcg_gen_br(l4); \
7279 gen_set_label(l3); \
7280 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7281 CRF_CH | CRF_CH_OR_CL); \
7282 gen_set_label(l4); \
7283 }
7284 #endif
7285 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7286 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7287 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7288 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7289 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7290
7291 /* SPE misc */
7292 static inline void gen_brinc(DisasContext *ctx)
7293 {
7294 /* Note: brinc is usable even if SPE is disabled */
7295 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7296 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7297 }
7298 static inline void gen_evmergelo(DisasContext *ctx)
7299 {
7300 if (unlikely(!ctx->spe_enabled)) {
7301 gen_exception(ctx, POWERPC_EXCP_SPEU);
7302 return;
7303 }
7304 #if defined(TARGET_PPC64)
7305 TCGv t0 = tcg_temp_new();
7306 TCGv t1 = tcg_temp_new();
7307 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7308 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7309 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7310 tcg_temp_free(t0);
7311 tcg_temp_free(t1);
7312 #else
7313 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7314 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7315 #endif
7316 }
7317 static inline void gen_evmergehilo(DisasContext *ctx)
7318 {
7319 if (unlikely(!ctx->spe_enabled)) {
7320 gen_exception(ctx, POWERPC_EXCP_SPEU);
7321 return;
7322 }
7323 #if defined(TARGET_PPC64)
7324 TCGv t0 = tcg_temp_new();
7325 TCGv t1 = tcg_temp_new();
7326 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7327 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7328 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7329 tcg_temp_free(t0);
7330 tcg_temp_free(t1);
7331 #else
7332 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7333 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7334 #endif
7335 }
7336 static inline void gen_evmergelohi(DisasContext *ctx)
7337 {
7338 if (unlikely(!ctx->spe_enabled)) {
7339 gen_exception(ctx, POWERPC_EXCP_SPEU);
7340 return;
7341 }
7342 #if defined(TARGET_PPC64)
7343 TCGv t0 = tcg_temp_new();
7344 TCGv t1 = tcg_temp_new();
7345 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7346 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7347 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7348 tcg_temp_free(t0);
7349 tcg_temp_free(t1);
7350 #else
7351 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7352 TCGv_i32 tmp = tcg_temp_new_i32();
7353 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7354 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7355 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7356 tcg_temp_free_i32(tmp);
7357 } else {
7358 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7359 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7360 }
7361 #endif
7362 }
7363 static inline void gen_evsplati(DisasContext *ctx)
7364 {
7365 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7366
7367 #if defined(TARGET_PPC64)
7368 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7369 #else
7370 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7371 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7372 #endif
7373 }
7374 static inline void gen_evsplatfi(DisasContext *ctx)
7375 {
7376 uint64_t imm = rA(ctx->opcode) << 27;
7377
7378 #if defined(TARGET_PPC64)
7379 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7380 #else
7381 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7382 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7383 #endif
7384 }
7385
7386 static inline void gen_evsel(DisasContext *ctx)
7387 {
7388 int l1 = gen_new_label();
7389 int l2 = gen_new_label();
7390 int l3 = gen_new_label();
7391 int l4 = gen_new_label();
7392 TCGv_i32 t0 = tcg_temp_local_new_i32();
7393 #if defined(TARGET_PPC64)
7394 TCGv t1 = tcg_temp_local_new();
7395 TCGv t2 = tcg_temp_local_new();
7396 #endif
7397 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7398 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7399 #if defined(TARGET_PPC64)
7400 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7401 #else
7402 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7403 #endif
7404 tcg_gen_br(l2);
7405 gen_set_label(l1);
7406 #if defined(TARGET_PPC64)
7407 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7408 #else
7409 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7410 #endif
7411 gen_set_label(l2);
7412 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7413 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7414 #if defined(TARGET_PPC64)
7415 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7416 #else
7417 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7418 #endif
7419 tcg_gen_br(l4);
7420 gen_set_label(l3);
7421 #if defined(TARGET_PPC64)
7422 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7423 #else
7424 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7425 #endif
7426 gen_set_label(l4);
7427 tcg_temp_free_i32(t0);
7428 #if defined(TARGET_PPC64)
7429 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7430 tcg_temp_free(t1);
7431 tcg_temp_free(t2);
7432 #endif
7433 }
7434
7435 static void gen_evsel0(DisasContext *ctx)
7436 {
7437 gen_evsel(ctx);
7438 }
7439
7440 static void gen_evsel1(DisasContext *ctx)
7441 {
7442 gen_evsel(ctx);
7443 }
7444
7445 static void gen_evsel2(DisasContext *ctx)
7446 {
7447 gen_evsel(ctx);
7448 }
7449
7450 static void gen_evsel3(DisasContext *ctx)
7451 {
7452 gen_evsel(ctx);
7453 }
7454
7455 /* Multiply */
7456
7457 static inline void gen_evmwumi(DisasContext *ctx)
7458 {
7459 TCGv_i64 t0, t1;
7460
7461 if (unlikely(!ctx->spe_enabled)) {
7462 gen_exception(ctx, POWERPC_EXCP_SPEU);
7463 return;
7464 }
7465
7466 t0 = tcg_temp_new_i64();
7467 t1 = tcg_temp_new_i64();
7468
7469 /* t0 := rA; t1 := rB */
7470 #if defined(TARGET_PPC64)
7471 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7472 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7473 #else
7474 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7475 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7476 #endif
7477
7478 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7479
7480 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7481
7482 tcg_temp_free_i64(t0);
7483 tcg_temp_free_i64(t1);
7484 }
7485
7486 static inline void gen_evmwumia(DisasContext *ctx)
7487 {
7488 TCGv_i64 tmp;
7489
7490 if (unlikely(!ctx->spe_enabled)) {
7491 gen_exception(ctx, POWERPC_EXCP_SPEU);
7492 return;
7493 }
7494
7495 gen_evmwumi(ctx); /* rD := rA * rB */
7496
7497 tmp = tcg_temp_new_i64();
7498
7499 /* acc := rD */
7500 gen_load_gpr64(tmp, rD(ctx->opcode));
7501 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7502 tcg_temp_free_i64(tmp);
7503 }
7504
7505 static inline void gen_evmwumiaa(DisasContext *ctx)
7506 {
7507 TCGv_i64 acc;
7508 TCGv_i64 tmp;
7509
7510 if (unlikely(!ctx->spe_enabled)) {
7511 gen_exception(ctx, POWERPC_EXCP_SPEU);
7512 return;
7513 }
7514
7515 gen_evmwumi(ctx); /* rD := rA * rB */
7516
7517 acc = tcg_temp_new_i64();
7518 tmp = tcg_temp_new_i64();
7519
7520 /* tmp := rD */
7521 gen_load_gpr64(tmp, rD(ctx->opcode));
7522
7523 /* Load acc */
7524 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7525
7526 /* acc := tmp + acc */
7527 tcg_gen_add_i64(acc, acc, tmp);
7528
7529 /* Store acc */
7530 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7531
7532 /* rD := acc */
7533 gen_store_gpr64(rD(ctx->opcode), acc);
7534
7535 tcg_temp_free_i64(acc);
7536 tcg_temp_free_i64(tmp);
7537 }
7538
7539 static inline void gen_evmwsmi(DisasContext *ctx)
7540 {
7541 TCGv_i64 t0, t1;
7542
7543 if (unlikely(!ctx->spe_enabled)) {
7544 gen_exception(ctx, POWERPC_EXCP_SPEU);
7545 return;
7546 }
7547
7548 t0 = tcg_temp_new_i64();
7549 t1 = tcg_temp_new_i64();
7550
7551 /* t0 := rA; t1 := rB */
7552 #if defined(TARGET_PPC64)
7553 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7554 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7555 #else
7556 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7557 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7558 #endif
7559
7560 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7561
7562 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7563
7564 tcg_temp_free_i64(t0);
7565 tcg_temp_free_i64(t1);
7566 }
7567
7568 static inline void gen_evmwsmia(DisasContext *ctx)
7569 {
7570 TCGv_i64 tmp;
7571
7572 gen_evmwsmi(ctx); /* rD := rA * rB */
7573
7574 tmp = tcg_temp_new_i64();
7575
7576 /* acc := rD */
7577 gen_load_gpr64(tmp, rD(ctx->opcode));
7578 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7579
7580 tcg_temp_free_i64(tmp);
7581 }
7582
7583 static inline void gen_evmwsmiaa(DisasContext *ctx)
7584 {
7585 TCGv_i64 acc = tcg_temp_new_i64();
7586 TCGv_i64 tmp = tcg_temp_new_i64();
7587
7588 gen_evmwsmi(ctx); /* rD := rA * rB */
7589
7590 acc = tcg_temp_new_i64();
7591 tmp = tcg_temp_new_i64();
7592
7593 /* tmp := rD */
7594 gen_load_gpr64(tmp, rD(ctx->opcode));
7595
7596 /* Load acc */
7597 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7598
7599 /* acc := tmp + acc */
7600 tcg_gen_add_i64(acc, acc, tmp);
7601
7602 /* Store acc */
7603 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7604
7605 /* rD := acc */
7606 gen_store_gpr64(rD(ctx->opcode), acc);
7607
7608 tcg_temp_free_i64(acc);
7609 tcg_temp_free_i64(tmp);
7610 }
7611
7612 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7613 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7614 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7615 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7616 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7617 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7618 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7619 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7620 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7621 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7622 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7623 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7624 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7625 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7626 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7627 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7628 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7629 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7630 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7631 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7632 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7633 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7634 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7635 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7636 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7637 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7638 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7639 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7640 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7641
7642 /* SPE load and stores */
7643 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7644 {
7645 target_ulong uimm = rB(ctx->opcode);
7646
7647 if (rA(ctx->opcode) == 0) {
7648 tcg_gen_movi_tl(EA, uimm << sh);
7649 } else {
7650 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7651 if (NARROW_MODE(ctx)) {
7652 tcg_gen_ext32u_tl(EA, EA);
7653 }
7654 }
7655 }
7656
7657 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7658 {
7659 #if defined(TARGET_PPC64)
7660 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7661 #else
7662 TCGv_i64 t0 = tcg_temp_new_i64();
7663 gen_qemu_ld64(ctx, t0, addr);
7664 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7665 tcg_gen_shri_i64(t0, t0, 32);
7666 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7667 tcg_temp_free_i64(t0);
7668 #endif
7669 }
7670
7671 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7672 {
7673 #if defined(TARGET_PPC64)
7674 TCGv t0 = tcg_temp_new();
7675 gen_qemu_ld32u(ctx, t0, addr);
7676 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7677 gen_addr_add(ctx, addr, addr, 4);
7678 gen_qemu_ld32u(ctx, t0, addr);
7679 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7680 tcg_temp_free(t0);
7681 #else
7682 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7683 gen_addr_add(ctx, addr, addr, 4);
7684 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7685 #endif
7686 }
7687
7688 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7689 {
7690 TCGv t0 = tcg_temp_new();
7691 #if defined(TARGET_PPC64)
7692 gen_qemu_ld16u(ctx, t0, addr);
7693 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7694 gen_addr_add(ctx, addr, addr, 2);
7695 gen_qemu_ld16u(ctx, t0, addr);
7696 tcg_gen_shli_tl(t0, t0, 32);
7697 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7698 gen_addr_add(ctx, addr, addr, 2);
7699 gen_qemu_ld16u(ctx, t0, addr);
7700 tcg_gen_shli_tl(t0, t0, 16);
7701 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7702 gen_addr_add(ctx, addr, addr, 2);
7703 gen_qemu_ld16u(ctx, t0, addr);
7704 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7705 #else
7706 gen_qemu_ld16u(ctx, t0, addr);
7707 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7708 gen_addr_add(ctx, addr, addr, 2);
7709 gen_qemu_ld16u(ctx, t0, addr);
7710 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7711 gen_addr_add(ctx, addr, addr, 2);
7712 gen_qemu_ld16u(ctx, t0, addr);
7713 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7714 gen_addr_add(ctx, addr, addr, 2);
7715 gen_qemu_ld16u(ctx, t0, addr);
7716 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7717 #endif
7718 tcg_temp_free(t0);
7719 }
7720
7721 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7722 {
7723 TCGv t0 = tcg_temp_new();
7724 gen_qemu_ld16u(ctx, t0, addr);
7725 #if defined(TARGET_PPC64)
7726 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7727 tcg_gen_shli_tl(t0, t0, 16);
7728 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7729 #else
7730 tcg_gen_shli_tl(t0, t0, 16);
7731 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7732 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7733 #endif
7734 tcg_temp_free(t0);
7735 }
7736
7737 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7738 {
7739 TCGv t0 = tcg_temp_new();
7740 gen_qemu_ld16u(ctx, t0, addr);
7741 #if defined(TARGET_PPC64)
7742 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7743 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7744 #else
7745 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7746 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7747 #endif
7748 tcg_temp_free(t0);
7749 }
7750
7751 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7752 {
7753 TCGv t0 = tcg_temp_new();
7754 gen_qemu_ld16s(ctx, t0, addr);
7755 #if defined(TARGET_PPC64)
7756 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7757 tcg_gen_ext32u_tl(t0, t0);
7758 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7759 #else
7760 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7761 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7762 #endif
7763 tcg_temp_free(t0);
7764 }
7765
7766 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7767 {
7768 TCGv t0 = tcg_temp_new();
7769 #if defined(TARGET_PPC64)
7770 gen_qemu_ld16u(ctx, t0, addr);
7771 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7772 gen_addr_add(ctx, addr, addr, 2);
7773 gen_qemu_ld16u(ctx, t0, addr);
7774 tcg_gen_shli_tl(t0, t0, 16);
7775 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7776 #else
7777 gen_qemu_ld16u(ctx, t0, addr);
7778 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7779 gen_addr_add(ctx, addr, addr, 2);
7780 gen_qemu_ld16u(ctx, t0, addr);
7781 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7782 #endif
7783 tcg_temp_free(t0);
7784 }
7785
7786 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7787 {
7788 #if defined(TARGET_PPC64)
7789 TCGv t0 = tcg_temp_new();
7790 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7791 gen_addr_add(ctx, addr, addr, 2);
7792 gen_qemu_ld16u(ctx, t0, addr);
7793 tcg_gen_shli_tl(t0, t0, 32);
7794 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7795 tcg_temp_free(t0);
7796 #else
7797 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7798 gen_addr_add(ctx, addr, addr, 2);
7799 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7800 #endif
7801 }
7802
7803 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7804 {
7805 #if defined(TARGET_PPC64)
7806 TCGv t0 = tcg_temp_new();
7807 gen_qemu_ld16s(ctx, t0, addr);
7808 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7809 gen_addr_add(ctx, addr, addr, 2);
7810 gen_qemu_ld16s(ctx, t0, addr);
7811 tcg_gen_shli_tl(t0, t0, 32);
7812 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7813 tcg_temp_free(t0);
7814 #else
7815 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7816 gen_addr_add(ctx, addr, addr, 2);
7817 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7818 #endif
7819 }
7820
7821 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7822 {
7823 TCGv t0 = tcg_temp_new();
7824 gen_qemu_ld32u(ctx, t0, addr);
7825 #if defined(TARGET_PPC64)
7826 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7827 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7828 #else
7829 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7830 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7831 #endif
7832 tcg_temp_free(t0);
7833 }
7834
7835 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7836 {
7837 TCGv t0 = tcg_temp_new();
7838 #if defined(TARGET_PPC64)
7839 gen_qemu_ld16u(ctx, t0, addr);
7840 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7841 tcg_gen_shli_tl(t0, t0, 32);
7842 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7843 gen_addr_add(ctx, addr, addr, 2);
7844 gen_qemu_ld16u(ctx, t0, addr);
7845 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7846 tcg_gen_shli_tl(t0, t0, 16);
7847 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7848 #else
7849 gen_qemu_ld16u(ctx, t0, addr);
7850 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7851 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7852 gen_addr_add(ctx, addr, addr, 2);
7853 gen_qemu_ld16u(ctx, t0, addr);
7854 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7855 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7856 #endif
7857 tcg_temp_free(t0);
7858 }
7859
7860 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7861 {
7862 #if defined(TARGET_PPC64)
7863 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7864 #else
7865 TCGv_i64 t0 = tcg_temp_new_i64();
7866 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7867 gen_qemu_st64(ctx, t0, addr);
7868 tcg_temp_free_i64(t0);
7869 #endif
7870 }
7871
7872 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7873 {
7874 #if defined(TARGET_PPC64)
7875 TCGv t0 = tcg_temp_new();
7876 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7877 gen_qemu_st32(ctx, t0, addr);
7878 tcg_temp_free(t0);
7879 #else
7880 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7881 #endif
7882 gen_addr_add(ctx, addr, addr, 4);
7883 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7884 }
7885
7886 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7887 {
7888 TCGv t0 = tcg_temp_new();
7889 #if defined(TARGET_PPC64)
7890 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7891 #else
7892 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7893 #endif
7894 gen_qemu_st16(ctx, t0, addr);
7895 gen_addr_add(ctx, addr, addr, 2);
7896 #if defined(TARGET_PPC64)
7897 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7898 gen_qemu_st16(ctx, t0, addr);
7899 #else
7900 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7901 #endif
7902 gen_addr_add(ctx, addr, addr, 2);
7903 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7904 gen_qemu_st16(ctx, t0, addr);
7905 tcg_temp_free(t0);
7906 gen_addr_add(ctx, addr, addr, 2);
7907 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7908 }
7909
7910 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7911 {
7912 TCGv t0 = tcg_temp_new();
7913 #if defined(TARGET_PPC64)
7914 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7915 #else
7916 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7917 #endif
7918 gen_qemu_st16(ctx, t0, addr);
7919 gen_addr_add(ctx, addr, addr, 2);
7920 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7921 gen_qemu_st16(ctx, t0, addr);
7922 tcg_temp_free(t0);
7923 }
7924
7925 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7926 {
7927 #if defined(TARGET_PPC64)
7928 TCGv t0 = tcg_temp_new();
7929 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7930 gen_qemu_st16(ctx, t0, addr);
7931 tcg_temp_free(t0);
7932 #else
7933 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7934 #endif
7935 gen_addr_add(ctx, addr, addr, 2);
7936 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7937 }
7938
7939 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7940 {
7941 #if defined(TARGET_PPC64)
7942 TCGv t0 = tcg_temp_new();
7943 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7944 gen_qemu_st32(ctx, t0, addr);
7945 tcg_temp_free(t0);
7946 #else
7947 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7948 #endif
7949 }
7950
7951 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7952 {
7953 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7954 }
7955
7956 #define GEN_SPEOP_LDST(name, opc2, sh) \
7957 static void glue(gen_, name)(DisasContext *ctx) \
7958 { \
7959 TCGv t0; \
7960 if (unlikely(!ctx->spe_enabled)) { \
7961 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7962 return; \
7963 } \
7964 gen_set_access_type(ctx, ACCESS_INT); \
7965 t0 = tcg_temp_new(); \
7966 if (Rc(ctx->opcode)) { \
7967 gen_addr_spe_imm_index(ctx, t0, sh); \
7968 } else { \
7969 gen_addr_reg_index(ctx, t0); \
7970 } \
7971 gen_op_##name(ctx, t0); \
7972 tcg_temp_free(t0); \
7973 }
7974
7975 GEN_SPEOP_LDST(evldd, 0x00, 3);
7976 GEN_SPEOP_LDST(evldw, 0x01, 3);
7977 GEN_SPEOP_LDST(evldh, 0x02, 3);
7978 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7979 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7980 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7981 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7982 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7983 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7984 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7985 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7986
7987 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7988 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7989 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7990 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7991 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7992 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7993 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7994
7995 /* Multiply and add - TODO */
7996 #if 0
7997 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7998 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7999 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8000 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8001 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8002 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8003 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8004 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8005 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8006 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8007 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8008 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8009
8010 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8011 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8012 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8013 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8014 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8015 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8016 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8017 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8018 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8019 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8020 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8021 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8022
8023 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8024 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8025 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8026 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8027 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8028
8029 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8030 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8031 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8032 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8033 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8034 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8035 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8036 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8037 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8038 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8039 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8040 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8041
8042 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8043 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8044 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8045 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8046
8047 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8048 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8049 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8050 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8051 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8052 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8053 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8054 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8055 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8056 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8057 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8058 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8059
8060 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8061 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8062 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8063 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8064 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8065 #endif
8066
8067 /*** SPE floating-point extension ***/
8068 #if defined(TARGET_PPC64)
8069 #define GEN_SPEFPUOP_CONV_32_32(name) \
8070 static inline void gen_##name(DisasContext *ctx) \
8071 { \
8072 TCGv_i32 t0; \
8073 TCGv t1; \
8074 t0 = tcg_temp_new_i32(); \
8075 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8076 gen_helper_##name(t0, cpu_env, t0); \
8077 t1 = tcg_temp_new(); \
8078 tcg_gen_extu_i32_tl(t1, t0); \
8079 tcg_temp_free_i32(t0); \
8080 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8081 0xFFFFFFFF00000000ULL); \
8082 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8083 tcg_temp_free(t1); \
8084 }
8085 #define GEN_SPEFPUOP_CONV_32_64(name) \
8086 static inline void gen_##name(DisasContext *ctx) \
8087 { \
8088 TCGv_i32 t0; \
8089 TCGv t1; \
8090 t0 = tcg_temp_new_i32(); \
8091 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8092 t1 = tcg_temp_new(); \
8093 tcg_gen_extu_i32_tl(t1, t0); \
8094 tcg_temp_free_i32(t0); \
8095 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8096 0xFFFFFFFF00000000ULL); \
8097 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8098 tcg_temp_free(t1); \
8099 }
8100 #define GEN_SPEFPUOP_CONV_64_32(name) \
8101 static inline void gen_##name(DisasContext *ctx) \
8102 { \
8103 TCGv_i32 t0 = tcg_temp_new_i32(); \
8104 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8105 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8106 tcg_temp_free_i32(t0); \
8107 }
8108 #define GEN_SPEFPUOP_CONV_64_64(name) \
8109 static inline void gen_##name(DisasContext *ctx) \
8110 { \
8111 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8112 cpu_gpr[rB(ctx->opcode)]); \
8113 }
8114 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8115 static inline void gen_##name(DisasContext *ctx) \
8116 { \
8117 TCGv_i32 t0, t1; \
8118 TCGv_i64 t2; \
8119 if (unlikely(!ctx->spe_enabled)) { \
8120 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8121 return; \
8122 } \
8123 t0 = tcg_temp_new_i32(); \
8124 t1 = tcg_temp_new_i32(); \
8125 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8126 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8127 gen_helper_##name(t0, cpu_env, t0, t1); \
8128 tcg_temp_free_i32(t1); \
8129 t2 = tcg_temp_new(); \
8130 tcg_gen_extu_i32_tl(t2, t0); \
8131 tcg_temp_free_i32(t0); \
8132 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8133 0xFFFFFFFF00000000ULL); \
8134 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8135 tcg_temp_free(t2); \
8136 }
8137 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8138 static inline void gen_##name(DisasContext *ctx) \
8139 { \
8140 if (unlikely(!ctx->spe_enabled)) { \
8141 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8142 return; \
8143 } \
8144 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8145 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8146 }
8147 #define GEN_SPEFPUOP_COMP_32(name) \
8148 static inline void gen_##name(DisasContext *ctx) \
8149 { \
8150 TCGv_i32 t0, t1; \
8151 if (unlikely(!ctx->spe_enabled)) { \
8152 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8153 return; \
8154 } \
8155 t0 = tcg_temp_new_i32(); \
8156 t1 = tcg_temp_new_i32(); \
8157 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8158 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8159 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8160 tcg_temp_free_i32(t0); \
8161 tcg_temp_free_i32(t1); \
8162 }
8163 #define GEN_SPEFPUOP_COMP_64(name) \
8164 static inline void gen_##name(DisasContext *ctx) \
8165 { \
8166 if (unlikely(!ctx->spe_enabled)) { \
8167 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8168 return; \
8169 } \
8170 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8171 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8172 }
8173 #else
8174 #define GEN_SPEFPUOP_CONV_32_32(name) \
8175 static inline void gen_##name(DisasContext *ctx) \
8176 { \
8177 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8178 cpu_gpr[rB(ctx->opcode)]); \
8179 }
8180 #define GEN_SPEFPUOP_CONV_32_64(name) \
8181 static inline void gen_##name(DisasContext *ctx) \
8182 { \
8183 TCGv_i64 t0 = tcg_temp_new_i64(); \
8184 gen_load_gpr64(t0, rB(ctx->opcode)); \
8185 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8186 tcg_temp_free_i64(t0); \
8187 }
8188 #define GEN_SPEFPUOP_CONV_64_32(name) \
8189 static inline void gen_##name(DisasContext *ctx) \
8190 { \
8191 TCGv_i64 t0 = tcg_temp_new_i64(); \
8192 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8193 gen_store_gpr64(rD(ctx->opcode), t0); \
8194 tcg_temp_free_i64(t0); \
8195 }
8196 #define GEN_SPEFPUOP_CONV_64_64(name) \
8197 static inline void gen_##name(DisasContext *ctx) \
8198 { \
8199 TCGv_i64 t0 = tcg_temp_new_i64(); \
8200 gen_load_gpr64(t0, rB(ctx->opcode)); \
8201 gen_helper_##name(t0, cpu_env, t0); \
8202 gen_store_gpr64(rD(ctx->opcode), t0); \
8203 tcg_temp_free_i64(t0); \
8204 }
8205 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8206 static inline void gen_##name(DisasContext *ctx) \
8207 { \
8208 if (unlikely(!ctx->spe_enabled)) { \
8209 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8210 return; \
8211 } \
8212 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8213 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8214 }
8215 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8216 static inline void gen_##name(DisasContext *ctx) \
8217 { \
8218 TCGv_i64 t0, t1; \
8219 if (unlikely(!ctx->spe_enabled)) { \
8220 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8221 return; \
8222 } \
8223 t0 = tcg_temp_new_i64(); \
8224 t1 = tcg_temp_new_i64(); \
8225 gen_load_gpr64(t0, rA(ctx->opcode)); \
8226 gen_load_gpr64(t1, rB(ctx->opcode)); \
8227 gen_helper_##name(t0, cpu_env, t0, t1); \
8228 gen_store_gpr64(rD(ctx->opcode), t0); \
8229 tcg_temp_free_i64(t0); \
8230 tcg_temp_free_i64(t1); \
8231 }
8232 #define GEN_SPEFPUOP_COMP_32(name) \
8233 static inline void gen_##name(DisasContext *ctx) \
8234 { \
8235 if (unlikely(!ctx->spe_enabled)) { \
8236 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8237 return; \
8238 } \
8239 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8240 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8241 }
8242 #define GEN_SPEFPUOP_COMP_64(name) \
8243 static inline void gen_##name(DisasContext *ctx) \
8244 { \
8245 TCGv_i64 t0, t1; \
8246 if (unlikely(!ctx->spe_enabled)) { \
8247 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8248 return; \
8249 } \
8250 t0 = tcg_temp_new_i64(); \
8251 t1 = tcg_temp_new_i64(); \
8252 gen_load_gpr64(t0, rA(ctx->opcode)); \
8253 gen_load_gpr64(t1, rB(ctx->opcode)); \
8254 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8255 tcg_temp_free_i64(t0); \
8256 tcg_temp_free_i64(t1); \
8257 }
8258 #endif
8259
8260 /* Single precision floating-point vectors operations */
8261 /* Arithmetic */
8262 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8263 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8264 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8265 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8266 static inline void gen_evfsabs(DisasContext *ctx)
8267 {
8268 if (unlikely(!ctx->spe_enabled)) {
8269 gen_exception(ctx, POWERPC_EXCP_SPEU);
8270 return;
8271 }
8272 #if defined(TARGET_PPC64)
8273 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8274 #else
8275 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8276 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8277 #endif
8278 }
8279 static inline void gen_evfsnabs(DisasContext *ctx)
8280 {
8281 if (unlikely(!ctx->spe_enabled)) {
8282 gen_exception(ctx, POWERPC_EXCP_SPEU);
8283 return;
8284 }
8285 #if defined(TARGET_PPC64)
8286 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8287 #else
8288 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8289 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8290 #endif
8291 }
8292 static inline void gen_evfsneg(DisasContext *ctx)
8293 {
8294 if (unlikely(!ctx->spe_enabled)) {
8295 gen_exception(ctx, POWERPC_EXCP_SPEU);
8296 return;
8297 }
8298 #if defined(TARGET_PPC64)
8299 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8300 #else
8301 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8302 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8303 #endif
8304 }
8305
8306 /* Conversion */
8307 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8308 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8309 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8310 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8311 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8312 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8313 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8314 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8315 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8316 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8317
8318 /* Comparison */
8319 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8320 GEN_SPEFPUOP_COMP_64(evfscmplt);
8321 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8322 GEN_SPEFPUOP_COMP_64(evfststgt);
8323 GEN_SPEFPUOP_COMP_64(evfststlt);
8324 GEN_SPEFPUOP_COMP_64(evfststeq);
8325
8326 /* Opcodes definitions */
8327 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8328 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8329 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8330 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8331 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8332 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8333 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8334 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8335 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8336 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8337 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8338 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8339 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8340 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8341
8342 /* Single precision floating-point operations */
8343 /* Arithmetic */
8344 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8345 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8346 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8347 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8348 static inline void gen_efsabs(DisasContext *ctx)
8349 {
8350 if (unlikely(!ctx->spe_enabled)) {
8351 gen_exception(ctx, POWERPC_EXCP_SPEU);
8352 return;
8353 }
8354 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8355 }
8356 static inline void gen_efsnabs(DisasContext *ctx)
8357 {
8358 if (unlikely(!ctx->spe_enabled)) {
8359 gen_exception(ctx, POWERPC_EXCP_SPEU);
8360 return;
8361 }
8362 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8363 }
8364 static inline void gen_efsneg(DisasContext *ctx)
8365 {
8366 if (unlikely(!ctx->spe_enabled)) {
8367 gen_exception(ctx, POWERPC_EXCP_SPEU);
8368 return;
8369 }
8370 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8371 }
8372
8373 /* Conversion */
8374 GEN_SPEFPUOP_CONV_32_32(efscfui);
8375 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8376 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8377 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8378 GEN_SPEFPUOP_CONV_32_32(efsctui);
8379 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8380 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8381 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8382 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8383 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8384 GEN_SPEFPUOP_CONV_32_64(efscfd);
8385
8386 /* Comparison */
8387 GEN_SPEFPUOP_COMP_32(efscmpgt);
8388 GEN_SPEFPUOP_COMP_32(efscmplt);
8389 GEN_SPEFPUOP_COMP_32(efscmpeq);
8390 GEN_SPEFPUOP_COMP_32(efststgt);
8391 GEN_SPEFPUOP_COMP_32(efststlt);
8392 GEN_SPEFPUOP_COMP_32(efststeq);
8393
8394 /* Opcodes definitions */
8395 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8396 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8397 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8398 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8399 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8400 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8401 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8402 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8403 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8404 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8405 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8406 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8407 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8408 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8409
8410 /* Double precision floating-point operations */
8411 /* Arithmetic */
8412 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8413 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8414 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8415 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8416 static inline void gen_efdabs(DisasContext *ctx)
8417 {
8418 if (unlikely(!ctx->spe_enabled)) {
8419 gen_exception(ctx, POWERPC_EXCP_SPEU);
8420 return;
8421 }
8422 #if defined(TARGET_PPC64)
8423 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8424 #else
8425 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8426 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8427 #endif
8428 }
8429 static inline void gen_efdnabs(DisasContext *ctx)
8430 {
8431 if (unlikely(!ctx->spe_enabled)) {
8432 gen_exception(ctx, POWERPC_EXCP_SPEU);
8433 return;
8434 }
8435 #if defined(TARGET_PPC64)
8436 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8437 #else
8438 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8439 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8440 #endif
8441 }
8442 static inline void gen_efdneg(DisasContext *ctx)
8443 {
8444 if (unlikely(!ctx->spe_enabled)) {
8445 gen_exception(ctx, POWERPC_EXCP_SPEU);
8446 return;
8447 }
8448 #if defined(TARGET_PPC64)
8449 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8450 #else
8451 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8452 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8453 #endif
8454 }
8455
8456 /* Conversion */
8457 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8458 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8459 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8460 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8461 GEN_SPEFPUOP_CONV_32_64(efdctui);
8462 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8463 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8464 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8465 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8466 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8467 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8468 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8469 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8470 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8471 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8472
8473 /* Comparison */
8474 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8475 GEN_SPEFPUOP_COMP_64(efdcmplt);
8476 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8477 GEN_SPEFPUOP_COMP_64(efdtstgt);
8478 GEN_SPEFPUOP_COMP_64(efdtstlt);
8479 GEN_SPEFPUOP_COMP_64(efdtsteq);
8480
8481 /* Opcodes definitions */
8482 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8483 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8484 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8485 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8486 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8487 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8488 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8489 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8490 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8491 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8492 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8493 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8494 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8495 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8496 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8497 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8498
8499 static opcode_t opcodes[] = {
8500 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8501 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8502 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8503 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8504 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8505 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
8506 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8507 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8508 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8509 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8510 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8511 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8512 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8513 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8514 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8515 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8516 #if defined(TARGET_PPC64)
8517 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8518 #endif
8519 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8520 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8521 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8522 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8523 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8524 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8525 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8526 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8527 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8528 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8529 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8530 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8531 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8532 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8533 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
8534 #if defined(TARGET_PPC64)
8535 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8536 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8537 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
8538 #endif
8539 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8540 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8541 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8542 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8543 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8544 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8545 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8546 #if defined(TARGET_PPC64)
8547 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8548 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8549 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8550 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8551 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8552 #endif
8553 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8554 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8555 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8556 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8557 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8558 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
8559 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8560 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
8561 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
8562 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8563 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8564 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8565 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8566 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8567 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8568 #if defined(TARGET_PPC64)
8569 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8570 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8571 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8572 #endif
8573 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8574 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8575 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8576 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8577 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8578 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8579 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8580 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8581 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8582 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8583 #if defined(TARGET_PPC64)
8584 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8585 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8586 #endif
8587 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8588 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8589 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8590 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8591 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8592 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8593 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8594 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8595 #if defined(TARGET_PPC64)
8596 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8597 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8598 #endif
8599 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8600 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8601 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8602 #if defined(TARGET_PPC64)
8603 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8604 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8605 #endif
8606 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8607 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8608 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8609 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8610 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8611 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8612 #if defined(TARGET_PPC64)
8613 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8614 #endif
8615 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8616 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8617 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8618 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8619 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8620 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8621 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8622 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8623 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8624 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8625 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8626 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8627 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8628 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8629 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8630 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8631 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8632 #if defined(TARGET_PPC64)
8633 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8634 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8635 PPC_SEGMENT_64B),
8636 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8637 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8638 PPC_SEGMENT_64B),
8639 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8640 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8641 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8642 #endif
8643 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8644 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8645 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8646 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8647 #if defined(TARGET_PPC64)
8648 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8649 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8650 #endif
8651 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8652 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8653 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8654 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8655 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8656 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8657 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8658 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8659 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8660 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8661 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8662 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8663 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8664 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8665 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8666 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8667 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8668 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8669 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8670 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8671 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8672 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8673 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8674 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8675 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8676 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8677 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8678 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8679 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8680 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8681 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8682 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8683 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8684 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8685 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8686 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8687 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8688 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8689 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8690 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8691 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8692 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8693 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8694 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8695 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8696 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8697 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8698 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8699 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8700 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8701 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8702 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8703 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8704 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8705 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8706 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8707 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8708 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8709 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8710 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8711 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8712 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8713 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8714 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8715 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8716 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8717 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8718 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8719 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8720 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8721 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8722 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8723 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8724 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8725 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8726 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8727 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8728 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8729 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8730 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8731 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8732 PPC_NONE, PPC2_BOOKE206),
8733 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8734 PPC_NONE, PPC2_BOOKE206),
8735 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8736 PPC_NONE, PPC2_BOOKE206),
8737 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8738 PPC_NONE, PPC2_BOOKE206),
8739 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8740 PPC_NONE, PPC2_BOOKE206),
8741 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8742 PPC_NONE, PPC2_PRCNTL),
8743 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8744 PPC_NONE, PPC2_PRCNTL),
8745 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8746 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8747 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8748 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8749 PPC_BOOKE, PPC2_BOOKE206),
8750 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8751 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8752 PPC_BOOKE, PPC2_BOOKE206),
8753 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8754 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8755 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8756 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8757 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8758 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8759 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8760 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8761 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8762 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8763
8764 #undef GEN_INT_ARITH_ADD
8765 #undef GEN_INT_ARITH_ADD_CONST
8766 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8767 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8768 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8769 add_ca, compute_ca, compute_ov) \
8770 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8771 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8772 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8773 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8774 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8775 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8776 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8777 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8778 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8779 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8780 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8781
8782 #undef GEN_INT_ARITH_DIVW
8783 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8784 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8785 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8786 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8787 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8788 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8789
8790 #if defined(TARGET_PPC64)
8791 #undef GEN_INT_ARITH_DIVD
8792 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8793 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8794 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8795 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8796 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8797 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8798
8799 #undef GEN_INT_ARITH_MUL_HELPER
8800 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8801 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8802 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8803 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8804 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8805 #endif
8806
8807 #undef GEN_INT_ARITH_SUBF
8808 #undef GEN_INT_ARITH_SUBF_CONST
8809 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8810 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8811 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8812 add_ca, compute_ca, compute_ov) \
8813 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8814 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8815 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8816 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8817 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8818 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8819 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8820 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8821 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8822 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8823 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8824
8825 #undef GEN_LOGICAL1
8826 #undef GEN_LOGICAL2
8827 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8828 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8829 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8830 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8831 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8832 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8833 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8834 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8835 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8836 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8837 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8838 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8839 #if defined(TARGET_PPC64)
8840 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8841 #endif
8842
8843 #if defined(TARGET_PPC64)
8844 #undef GEN_PPC64_R2
8845 #undef GEN_PPC64_R4
8846 #define GEN_PPC64_R2(name, opc1, opc2) \
8847 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8848 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8849 PPC_64B)
8850 #define GEN_PPC64_R4(name, opc1, opc2) \
8851 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8852 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8853 PPC_64B), \
8854 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8855 PPC_64B), \
8856 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8857 PPC_64B)
8858 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8859 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8860 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8861 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8862 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8863 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8864 #endif
8865
8866 #undef _GEN_FLOAT_ACB
8867 #undef GEN_FLOAT_ACB
8868 #undef _GEN_FLOAT_AB
8869 #undef GEN_FLOAT_AB
8870 #undef _GEN_FLOAT_AC
8871 #undef GEN_FLOAT_AC
8872 #undef GEN_FLOAT_B
8873 #undef GEN_FLOAT_BS
8874 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8875 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8876 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8877 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8878 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8879 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8880 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8881 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8882 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8883 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8884 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8885 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8886 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8887 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8888 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8889 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8890 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8891 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8892 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8893
8894 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8895 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8896 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8897 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8898 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8899 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8900 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8901 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8902 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8903 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8904 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8905 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8906 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8907 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8908 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8909 #if defined(TARGET_PPC64)
8910 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8911 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8912 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8913 #endif
8914 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8915 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8916 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8917 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8918
8919 #undef GEN_LD
8920 #undef GEN_LDU
8921 #undef GEN_LDUX
8922 #undef GEN_LDX_E
8923 #undef GEN_LDS
8924 #define GEN_LD(name, ldop, opc, type) \
8925 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8926 #define GEN_LDU(name, ldop, opc, type) \
8927 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8928 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8929 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8930 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8931 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8932 #define GEN_LDS(name, ldop, op, type) \
8933 GEN_LD(name, ldop, op | 0x20, type) \
8934 GEN_LDU(name, ldop, op | 0x21, type) \
8935 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8936 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8937
8938 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8939 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8940 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8941 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8942 #if defined(TARGET_PPC64)
8943 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8944 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8945 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8946 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8947 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8948 #endif
8949 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8950 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8951
8952 #undef GEN_ST
8953 #undef GEN_STU
8954 #undef GEN_STUX
8955 #undef GEN_STX_E
8956 #undef GEN_STS
8957 #define GEN_ST(name, stop, opc, type) \
8958 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8959 #define GEN_STU(name, stop, opc, type) \
8960 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8961 #define GEN_STUX(name, stop, opc2, opc3, type) \
8962 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8963 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8964 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8965 #define GEN_STS(name, stop, op, type) \
8966 GEN_ST(name, stop, op | 0x20, type) \
8967 GEN_STU(name, stop, op | 0x21, type) \
8968 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8969 GEN_STX(name, stop, 0x17, op | 0x00, type)
8970
8971 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8972 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8973 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8974 #if defined(TARGET_PPC64)
8975 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8976 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8977 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8978 #endif
8979 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8980 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8981
8982 #undef GEN_LDF
8983 #undef GEN_LDUF
8984 #undef GEN_LDUXF
8985 #undef GEN_LDXF
8986 #undef GEN_LDFS
8987 #define GEN_LDF(name, ldop, opc, type) \
8988 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8989 #define GEN_LDUF(name, ldop, opc, type) \
8990 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8991 #define GEN_LDUXF(name, ldop, opc, type) \
8992 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8993 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8994 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8995 #define GEN_LDFS(name, ldop, op, type) \
8996 GEN_LDF(name, ldop, op | 0x20, type) \
8997 GEN_LDUF(name, ldop, op | 0x21, type) \
8998 GEN_LDUXF(name, ldop, op | 0x01, type) \
8999 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9000
9001 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
9002 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
9003
9004 #undef GEN_STF
9005 #undef GEN_STUF
9006 #undef GEN_STUXF
9007 #undef GEN_STXF
9008 #undef GEN_STFS
9009 #define GEN_STF(name, stop, opc, type) \
9010 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9011 #define GEN_STUF(name, stop, opc, type) \
9012 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9013 #define GEN_STUXF(name, stop, opc, type) \
9014 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9015 #define GEN_STXF(name, stop, opc2, opc3, type) \
9016 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9017 #define GEN_STFS(name, stop, op, type) \
9018 GEN_STF(name, stop, op | 0x20, type) \
9019 GEN_STUF(name, stop, op | 0x21, type) \
9020 GEN_STUXF(name, stop, op | 0x01, type) \
9021 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9022
9023 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
9024 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
9025 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
9026
9027 #undef GEN_CRLOGIC
9028 #define GEN_CRLOGIC(name, tcg_op, opc) \
9029 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9030 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
9031 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
9032 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
9033 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9034 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9035 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9036 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9037 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9038
9039 #undef GEN_MAC_HANDLER
9040 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9041 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9042 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9043 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9044 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9045 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9046 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9047 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9048 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9049 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9050 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9051 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9052 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9053 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9054 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9055 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9056 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9057 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9058 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9059 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9060 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9061 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9062 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9063 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9064 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9065 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9066 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9067 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9068 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9069 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9070 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9071 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9072 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9073 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9074 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9075 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9076 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9077 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9078 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9079 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9080 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9081 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9082 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9083 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9084
9085 #undef GEN_VR_LDX
9086 #undef GEN_VR_STX
9087 #undef GEN_VR_LVE
9088 #undef GEN_VR_STVE
9089 #define GEN_VR_LDX(name, opc2, opc3) \
9090 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9091 #define GEN_VR_STX(name, opc2, opc3) \
9092 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9093 #define GEN_VR_LVE(name, opc2, opc3) \
9094 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9095 #define GEN_VR_STVE(name, opc2, opc3) \
9096 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9097 GEN_VR_LDX(lvx, 0x07, 0x03),
9098 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9099 GEN_VR_LVE(bx, 0x07, 0x00),
9100 GEN_VR_LVE(hx, 0x07, 0x01),
9101 GEN_VR_LVE(wx, 0x07, 0x02),
9102 GEN_VR_STX(svx, 0x07, 0x07),
9103 GEN_VR_STX(svxl, 0x07, 0x0F),
9104 GEN_VR_STVE(bx, 0x07, 0x04),
9105 GEN_VR_STVE(hx, 0x07, 0x05),
9106 GEN_VR_STVE(wx, 0x07, 0x06),
9107
9108 #undef GEN_VX_LOGICAL
9109 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9110 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9111 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9112 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9113 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9114 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9115 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9116
9117 #undef GEN_VXFORM
9118 #define GEN_VXFORM(name, opc2, opc3) \
9119 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9120 GEN_VXFORM(vaddubm, 0, 0),
9121 GEN_VXFORM(vadduhm, 0, 1),
9122 GEN_VXFORM(vadduwm, 0, 2),
9123 GEN_VXFORM(vsububm, 0, 16),
9124 GEN_VXFORM(vsubuhm, 0, 17),
9125 GEN_VXFORM(vsubuwm, 0, 18),
9126 GEN_VXFORM(vmaxub, 1, 0),
9127 GEN_VXFORM(vmaxuh, 1, 1),
9128 GEN_VXFORM(vmaxuw, 1, 2),
9129 GEN_VXFORM(vmaxsb, 1, 4),
9130 GEN_VXFORM(vmaxsh, 1, 5),
9131 GEN_VXFORM(vmaxsw, 1, 6),
9132 GEN_VXFORM(vminub, 1, 8),
9133 GEN_VXFORM(vminuh, 1, 9),
9134 GEN_VXFORM(vminuw, 1, 10),
9135 GEN_VXFORM(vminsb, 1, 12),
9136 GEN_VXFORM(vminsh, 1, 13),
9137 GEN_VXFORM(vminsw, 1, 14),
9138 GEN_VXFORM(vavgub, 1, 16),
9139 GEN_VXFORM(vavguh, 1, 17),
9140 GEN_VXFORM(vavguw, 1, 18),
9141 GEN_VXFORM(vavgsb, 1, 20),
9142 GEN_VXFORM(vavgsh, 1, 21),
9143 GEN_VXFORM(vavgsw, 1, 22),
9144 GEN_VXFORM(vmrghb, 6, 0),
9145 GEN_VXFORM(vmrghh, 6, 1),
9146 GEN_VXFORM(vmrghw, 6, 2),
9147 GEN_VXFORM(vmrglb, 6, 4),
9148 GEN_VXFORM(vmrglh, 6, 5),
9149 GEN_VXFORM(vmrglw, 6, 6),
9150 GEN_VXFORM(vmuloub, 4, 0),
9151 GEN_VXFORM(vmulouh, 4, 1),
9152 GEN_VXFORM(vmulosb, 4, 4),
9153 GEN_VXFORM(vmulosh, 4, 5),
9154 GEN_VXFORM(vmuleub, 4, 8),
9155 GEN_VXFORM(vmuleuh, 4, 9),
9156 GEN_VXFORM(vmulesb, 4, 12),
9157 GEN_VXFORM(vmulesh, 4, 13),
9158 GEN_VXFORM(vslb, 2, 4),
9159 GEN_VXFORM(vslh, 2, 5),
9160 GEN_VXFORM(vslw, 2, 6),
9161 GEN_VXFORM(vsrb, 2, 8),
9162 GEN_VXFORM(vsrh, 2, 9),
9163 GEN_VXFORM(vsrw, 2, 10),
9164 GEN_VXFORM(vsrab, 2, 12),
9165 GEN_VXFORM(vsrah, 2, 13),
9166 GEN_VXFORM(vsraw, 2, 14),
9167 GEN_VXFORM(vslo, 6, 16),
9168 GEN_VXFORM(vsro, 6, 17),
9169 GEN_VXFORM(vaddcuw, 0, 6),
9170 GEN_VXFORM(vsubcuw, 0, 22),
9171 GEN_VXFORM(vaddubs, 0, 8),
9172 GEN_VXFORM(vadduhs, 0, 9),
9173 GEN_VXFORM(vadduws, 0, 10),
9174 GEN_VXFORM(vaddsbs, 0, 12),
9175 GEN_VXFORM(vaddshs, 0, 13),
9176 GEN_VXFORM(vaddsws, 0, 14),
9177 GEN_VXFORM(vsububs, 0, 24),
9178 GEN_VXFORM(vsubuhs, 0, 25),
9179 GEN_VXFORM(vsubuws, 0, 26),
9180 GEN_VXFORM(vsubsbs, 0, 28),
9181 GEN_VXFORM(vsubshs, 0, 29),
9182 GEN_VXFORM(vsubsws, 0, 30),
9183 GEN_VXFORM(vrlb, 2, 0),
9184 GEN_VXFORM(vrlh, 2, 1),
9185 GEN_VXFORM(vrlw, 2, 2),
9186 GEN_VXFORM(vsl, 2, 7),
9187 GEN_VXFORM(vsr, 2, 11),
9188 GEN_VXFORM(vpkuhum, 7, 0),
9189 GEN_VXFORM(vpkuwum, 7, 1),
9190 GEN_VXFORM(vpkuhus, 7, 2),
9191 GEN_VXFORM(vpkuwus, 7, 3),
9192 GEN_VXFORM(vpkshus, 7, 4),
9193 GEN_VXFORM(vpkswus, 7, 5),
9194 GEN_VXFORM(vpkshss, 7, 6),
9195 GEN_VXFORM(vpkswss, 7, 7),
9196 GEN_VXFORM(vpkpx, 7, 12),
9197 GEN_VXFORM(vsum4ubs, 4, 24),
9198 GEN_VXFORM(vsum4sbs, 4, 28),
9199 GEN_VXFORM(vsum4shs, 4, 25),
9200 GEN_VXFORM(vsum2sws, 4, 26),
9201 GEN_VXFORM(vsumsws, 4, 30),
9202 GEN_VXFORM(vaddfp, 5, 0),
9203 GEN_VXFORM(vsubfp, 5, 1),
9204 GEN_VXFORM(vmaxfp, 5, 16),
9205 GEN_VXFORM(vminfp, 5, 17),
9206
9207 #undef GEN_VXRFORM1
9208 #undef GEN_VXRFORM
9209 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9210 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9211 #define GEN_VXRFORM(name, opc2, opc3) \
9212 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9213 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9214 GEN_VXRFORM(vcmpequb, 3, 0)
9215 GEN_VXRFORM(vcmpequh, 3, 1)
9216 GEN_VXRFORM(vcmpequw, 3, 2)
9217 GEN_VXRFORM(vcmpgtsb, 3, 12)
9218 GEN_VXRFORM(vcmpgtsh, 3, 13)
9219 GEN_VXRFORM(vcmpgtsw, 3, 14)
9220 GEN_VXRFORM(vcmpgtub, 3, 8)
9221 GEN_VXRFORM(vcmpgtuh, 3, 9)
9222 GEN_VXRFORM(vcmpgtuw, 3, 10)
9223 GEN_VXRFORM(vcmpeqfp, 3, 3)
9224 GEN_VXRFORM(vcmpgefp, 3, 7)
9225 GEN_VXRFORM(vcmpgtfp, 3, 11)
9226 GEN_VXRFORM(vcmpbfp, 3, 15)
9227
9228 #undef GEN_VXFORM_SIMM
9229 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9230 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9231 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9232 GEN_VXFORM_SIMM(vspltish, 6, 13),
9233 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9234
9235 #undef GEN_VXFORM_NOA
9236 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9237 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9238 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9239 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9240 GEN_VXFORM_NOA(vupklsb, 7, 10),
9241 GEN_VXFORM_NOA(vupklsh, 7, 11),
9242 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9243 GEN_VXFORM_NOA(vupklpx, 7, 15),
9244 GEN_VXFORM_NOA(vrefp, 5, 4),
9245 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9246 GEN_VXFORM_NOA(vexptefp, 5, 6),
9247 GEN_VXFORM_NOA(vlogefp, 5, 7),
9248 GEN_VXFORM_NOA(vrfim, 5, 8),
9249 GEN_VXFORM_NOA(vrfin, 5, 9),
9250 GEN_VXFORM_NOA(vrfip, 5, 10),
9251 GEN_VXFORM_NOA(vrfiz, 5, 11),
9252
9253 #undef GEN_VXFORM_UIMM
9254 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9255 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9256 GEN_VXFORM_UIMM(vspltb, 6, 8),
9257 GEN_VXFORM_UIMM(vsplth, 6, 9),
9258 GEN_VXFORM_UIMM(vspltw, 6, 10),
9259 GEN_VXFORM_UIMM(vcfux, 5, 12),
9260 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9261 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9262 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9263
9264 #undef GEN_VAFORM_PAIRED
9265 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9266 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9267 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9268 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9269 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9270 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9271 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9272 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9273
9274 #undef GEN_SPE
9275 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9276 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9277 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9278 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9279 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9280 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9281 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9282 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9283 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9284 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9285 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9286 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9287 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9288 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9289 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9290 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9291 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9292 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9293 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9294 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9295 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9296 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9297 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9298 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9299 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9300 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9301 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9302 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9303 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9304 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9305 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9306
9307 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9308 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9309 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9310 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9311 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9312 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9313 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9314 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9315 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9316 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9317 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9318 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9319 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9320 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9321
9322 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9323 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9324 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9325 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9326 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9327 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9328 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9329 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9330 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9331 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9332 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9333 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9334 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9335 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9336
9337 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9338 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9339 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9340 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9341 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9342 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9343 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9344 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9345 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9346 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9347 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9348 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9349 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9350 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9351 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9352 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9353
9354 #undef GEN_SPEOP_LDST
9355 #define GEN_SPEOP_LDST(name, opc2, sh) \
9356 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9357 GEN_SPEOP_LDST(evldd, 0x00, 3),
9358 GEN_SPEOP_LDST(evldw, 0x01, 3),
9359 GEN_SPEOP_LDST(evldh, 0x02, 3),
9360 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9361 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9362 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9363 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9364 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9365 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9366 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9367 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9368
9369 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9370 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9371 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9372 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9373 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9374 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9375 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9376 };
9377
9378 #include "helper_regs.h"
9379 #include "translate_init.c"
9380
9381 /*****************************************************************************/
9382 /* Misc PowerPC helpers */
9383 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9384 int flags)
9385 {
9386 #define RGPL 4
9387 #define RFPL 4
9388
9389 int i;
9390
9391 cpu_synchronize_state(env);
9392
9393 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9394 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9395 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9396 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9397 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9398 env->hflags, env->mmu_idx);
9399 #if !defined(NO_TIMER_DUMP)
9400 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9401 #if !defined(CONFIG_USER_ONLY)
9402 " DECR %08" PRIu32
9403 #endif
9404 "\n",
9405 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9406 #if !defined(CONFIG_USER_ONLY)
9407 , cpu_ppc_load_decr(env)
9408 #endif
9409 );
9410 #endif
9411 for (i = 0; i < 32; i++) {
9412 if ((i & (RGPL - 1)) == 0)
9413 cpu_fprintf(f, "GPR%02d", i);
9414 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9415 if ((i & (RGPL - 1)) == (RGPL - 1))
9416 cpu_fprintf(f, "\n");
9417 }
9418 cpu_fprintf(f, "CR ");
9419 for (i = 0; i < 8; i++)
9420 cpu_fprintf(f, "%01x", env->crf[i]);
9421 cpu_fprintf(f, " [");
9422 for (i = 0; i < 8; i++) {
9423 char a = '-';
9424 if (env->crf[i] & 0x08)
9425 a = 'L';
9426 else if (env->crf[i] & 0x04)
9427 a = 'G';
9428 else if (env->crf[i] & 0x02)
9429 a = 'E';
9430 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9431 }
9432 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9433 env->reserve_addr);
9434 for (i = 0; i < 32; i++) {
9435 if ((i & (RFPL - 1)) == 0)
9436 cpu_fprintf(f, "FPR%02d", i);
9437 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9438 if ((i & (RFPL - 1)) == (RFPL - 1))
9439 cpu_fprintf(f, "\n");
9440 }
9441 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9442 #if !defined(CONFIG_USER_ONLY)
9443 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9444 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9445 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9446 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9447
9448 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9449 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9450 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9451 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9452
9453 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9454 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9455 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9456 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9457
9458 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9459 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9460 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9461 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9462 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9463
9464 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9465 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9466 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9467 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9468
9469 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9470 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9471 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9472 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9473
9474 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9475 " EPR " TARGET_FMT_lx "\n",
9476 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9477 env->spr[SPR_BOOKE_EPR]);
9478
9479 /* FSL-specific */
9480 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9481 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9482 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9483 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9484
9485 /*
9486 * IVORs are left out as they are large and do not change often --
9487 * they can be read with "p $ivor0", "p $ivor1", etc.
9488 */
9489 }
9490
9491 #if defined(TARGET_PPC64)
9492 if (env->flags & POWERPC_FLAG_CFAR) {
9493 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9494 }
9495 #endif
9496
9497 switch (env->mmu_model) {
9498 case POWERPC_MMU_32B:
9499 case POWERPC_MMU_601:
9500 case POWERPC_MMU_SOFT_6xx:
9501 case POWERPC_MMU_SOFT_74xx:
9502 #if defined(TARGET_PPC64)
9503 case POWERPC_MMU_64B:
9504 #endif
9505 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9506 break;
9507 case POWERPC_MMU_BOOKE206:
9508 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9509 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9510 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9511 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9512
9513 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9514 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9515 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9516 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9517
9518 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9519 " TLB1CFG " TARGET_FMT_lx "\n",
9520 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9521 env->spr[SPR_BOOKE_TLB1CFG]);
9522 break;
9523 default:
9524 break;
9525 }
9526 #endif
9527
9528 #undef RGPL
9529 #undef RFPL
9530 }
9531
9532 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9533 int flags)
9534 {
9535 #if defined(DO_PPC_STATISTICS)
9536 opc_handler_t **t1, **t2, **t3, *handler;
9537 int op1, op2, op3;
9538
9539 t1 = env->opcodes;
9540 for (op1 = 0; op1 < 64; op1++) {
9541 handler = t1[op1];
9542 if (is_indirect_opcode(handler)) {
9543 t2 = ind_table(handler);
9544 for (op2 = 0; op2 < 32; op2++) {
9545 handler = t2[op2];
9546 if (is_indirect_opcode(handler)) {
9547 t3 = ind_table(handler);
9548 for (op3 = 0; op3 < 32; op3++) {
9549 handler = t3[op3];
9550 if (handler->count == 0)
9551 continue;
9552 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9553 "%016" PRIx64 " %" PRId64 "\n",
9554 op1, op2, op3, op1, (op3 << 5) | op2,
9555 handler->oname,
9556 handler->count, handler->count);
9557 }
9558 } else {
9559 if (handler->count == 0)
9560 continue;
9561 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9562 "%016" PRIx64 " %" PRId64 "\n",
9563 op1, op2, op1, op2, handler->oname,
9564 handler->count, handler->count);
9565 }
9566 }
9567 } else {
9568 if (handler->count == 0)
9569 continue;
9570 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9571 " %" PRId64 "\n",
9572 op1, op1, handler->oname,
9573 handler->count, handler->count);
9574 }
9575 }
9576 #endif
9577 }
9578
9579 /*****************************************************************************/
9580 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9581 TranslationBlock *tb,
9582 int search_pc)
9583 {
9584 DisasContext ctx, *ctxp = &ctx;
9585 opc_handler_t **table, *handler;
9586 target_ulong pc_start;
9587 uint16_t *gen_opc_end;
9588 CPUBreakpoint *bp;
9589 int j, lj = -1;
9590 int num_insns;
9591 int max_insns;
9592
9593 pc_start = tb->pc;
9594 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9595 ctx.nip = pc_start;
9596 ctx.tb = tb;
9597 ctx.exception = POWERPC_EXCP_NONE;
9598 ctx.spr_cb = env->spr_cb;
9599 ctx.mem_idx = env->mmu_idx;
9600 ctx.access_type = -1;
9601 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9602 #if defined(TARGET_PPC64)
9603 ctx.sf_mode = msr_is_64bit(env, env->msr);
9604 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9605 #endif
9606 ctx.fpu_enabled = msr_fp;
9607 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9608 ctx.spe_enabled = msr_spe;
9609 else
9610 ctx.spe_enabled = 0;
9611 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9612 ctx.altivec_enabled = msr_vr;
9613 else
9614 ctx.altivec_enabled = 0;
9615 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9616 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9617 else
9618 ctx.singlestep_enabled = 0;
9619 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9620 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9621 if (unlikely(env->singlestep_enabled))
9622 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9623 #if defined (DO_SINGLE_STEP) && 0
9624 /* Single step trace mode */
9625 msr_se = 1;
9626 #endif
9627 num_insns = 0;
9628 max_insns = tb->cflags & CF_COUNT_MASK;
9629 if (max_insns == 0)
9630 max_insns = CF_COUNT_MASK;
9631
9632 gen_tb_start();
9633 /* Set env in case of segfault during code fetch */
9634 while (ctx.exception == POWERPC_EXCP_NONE
9635 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9636 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9637 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9638 if (bp->pc == ctx.nip) {
9639 gen_debug_exception(ctxp);
9640 break;
9641 }
9642 }
9643 }
9644 if (unlikely(search_pc)) {
9645 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9646 if (lj < j) {
9647 lj++;
9648 while (lj < j)
9649 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9650 }
9651 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9652 tcg_ctx.gen_opc_instr_start[lj] = 1;
9653 tcg_ctx.gen_opc_icount[lj] = num_insns;
9654 }
9655 LOG_DISAS("----------------\n");
9656 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9657 ctx.nip, ctx.mem_idx, (int)msr_ir);
9658 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9659 gen_io_start();
9660 if (unlikely(ctx.le_mode)) {
9661 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9662 } else {
9663 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9664 }
9665 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9666 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9667 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9668 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9669 tcg_gen_debug_insn_start(ctx.nip);
9670 }
9671 ctx.nip += 4;
9672 table = env->opcodes;
9673 num_insns++;
9674 handler = table[opc1(ctx.opcode)];
9675 if (is_indirect_opcode(handler)) {
9676 table = ind_table(handler);
9677 handler = table[opc2(ctx.opcode)];
9678 if (is_indirect_opcode(handler)) {
9679 table = ind_table(handler);
9680 handler = table[opc3(ctx.opcode)];
9681 }
9682 }
9683 /* Is opcode *REALLY* valid ? */
9684 if (unlikely(handler->handler == &gen_invalid)) {
9685 if (qemu_log_enabled()) {
9686 qemu_log("invalid/unsupported opcode: "
9687 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9688 opc1(ctx.opcode), opc2(ctx.opcode),
9689 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9690 }
9691 } else {
9692 uint32_t inval;
9693
9694 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9695 inval = handler->inval2;
9696 } else {
9697 inval = handler->inval1;
9698 }
9699
9700 if (unlikely((ctx.opcode & inval) != 0)) {
9701 if (qemu_log_enabled()) {
9702 qemu_log("invalid bits: %08x for opcode: "
9703 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9704 ctx.opcode & inval, opc1(ctx.opcode),
9705 opc2(ctx.opcode), opc3(ctx.opcode),
9706 ctx.opcode, ctx.nip - 4);
9707 }
9708 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9709 break;
9710 }
9711 }
9712 (*(handler->handler))(&ctx);
9713 #if defined(DO_PPC_STATISTICS)
9714 handler->count++;
9715 #endif
9716 /* Check trace mode exceptions */
9717 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9718 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9719 ctx.exception != POWERPC_SYSCALL &&
9720 ctx.exception != POWERPC_EXCP_TRAP &&
9721 ctx.exception != POWERPC_EXCP_BRANCH)) {
9722 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9723 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9724 (env->singlestep_enabled) ||
9725 singlestep ||
9726 num_insns >= max_insns)) {
9727 /* if we reach a page boundary or are single stepping, stop
9728 * generation
9729 */
9730 break;
9731 }
9732 }
9733 if (tb->cflags & CF_LAST_IO)
9734 gen_io_end();
9735 if (ctx.exception == POWERPC_EXCP_NONE) {
9736 gen_goto_tb(&ctx, 0, ctx.nip);
9737 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9738 if (unlikely(env->singlestep_enabled)) {
9739 gen_debug_exception(ctxp);
9740 }
9741 /* Generate the return instruction */
9742 tcg_gen_exit_tb(0);
9743 }
9744 gen_tb_end(tb, num_insns);
9745 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9746 if (unlikely(search_pc)) {
9747 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9748 lj++;
9749 while (lj <= j)
9750 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9751 } else {
9752 tb->size = ctx.nip - pc_start;
9753 tb->icount = num_insns;
9754 }
9755 #if defined(DEBUG_DISAS)
9756 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9757 int flags;
9758 flags = env->bfd_mach;
9759 flags |= ctx.le_mode << 16;
9760 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9761 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9762 qemu_log("\n");
9763 }
9764 #endif
9765 }
9766
9767 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9768 {
9769 gen_intermediate_code_internal(env, tb, 0);
9770 }
9771
9772 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9773 {
9774 gen_intermediate_code_internal(env, tb, 1);
9775 }
9776
9777 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9778 {
9779 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9780 }
Qemu copy for testing