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target-ppc: Fix narrow-mode add/sub carry output
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 /* True when active word size < size of target_long. */
208 #ifdef TARGET_PPC64
209 # define NARROW_MODE(C) (!(C)->sf_mode)
210 #else
211 # define NARROW_MODE(C) 0
212 #endif
213
214 struct opc_handler_t {
215 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
216 uint32_t inval1;
217 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
218 uint32_t inval2;
219 /* instruction type */
220 uint64_t type;
221 /* extended instruction type */
222 uint64_t type2;
223 /* handler */
224 void (*handler)(DisasContext *ctx);
225 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
226 const char *oname;
227 #endif
228 #if defined(DO_PPC_STATISTICS)
229 uint64_t count;
230 #endif
231 };
232
233 static inline void gen_reset_fpstatus(void)
234 {
235 gen_helper_reset_fpstatus(cpu_env);
236 }
237
238 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
239 {
240 TCGv_i32 t0 = tcg_temp_new_i32();
241
242 if (set_fprf != 0) {
243 /* This case might be optimized later */
244 tcg_gen_movi_i32(t0, 1);
245 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
246 if (unlikely(set_rc)) {
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249 gen_helper_float_check_status(cpu_env);
250 } else if (unlikely(set_rc)) {
251 /* We always need to compute fpcc */
252 tcg_gen_movi_i32(t0, 0);
253 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
254 tcg_gen_mov_i32(cpu_crf[1], t0);
255 }
256
257 tcg_temp_free_i32(t0);
258 }
259
260 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
261 {
262 if (ctx->access_type != access_type) {
263 tcg_gen_movi_i32(cpu_access_type, access_type);
264 ctx->access_type = access_type;
265 }
266 }
267
268 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
269 {
270 if (NARROW_MODE(ctx)) {
271 nip = (uint32_t)nip;
272 }
273 tcg_gen_movi_tl(cpu_nip, nip);
274 }
275
276 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
277 {
278 TCGv_i32 t0, t1;
279 if (ctx->exception == POWERPC_EXCP_NONE) {
280 gen_update_nip(ctx, ctx->nip);
281 }
282 t0 = tcg_const_i32(excp);
283 t1 = tcg_const_i32(error);
284 gen_helper_raise_exception_err(cpu_env, t0, t1);
285 tcg_temp_free_i32(t0);
286 tcg_temp_free_i32(t1);
287 ctx->exception = (excp);
288 }
289
290 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
291 {
292 TCGv_i32 t0;
293 if (ctx->exception == POWERPC_EXCP_NONE) {
294 gen_update_nip(ctx, ctx->nip);
295 }
296 t0 = tcg_const_i32(excp);
297 gen_helper_raise_exception(cpu_env, t0);
298 tcg_temp_free_i32(t0);
299 ctx->exception = (excp);
300 }
301
302 static inline void gen_debug_exception(DisasContext *ctx)
303 {
304 TCGv_i32 t0;
305
306 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
307 (ctx->exception != POWERPC_EXCP_SYNC)) {
308 gen_update_nip(ctx, ctx->nip);
309 }
310 t0 = tcg_const_i32(EXCP_DEBUG);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 }
314
315 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
316 {
317 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
318 }
319
320 /* Stop translation */
321 static inline void gen_stop_exception(DisasContext *ctx)
322 {
323 gen_update_nip(ctx, ctx->nip);
324 ctx->exception = POWERPC_EXCP_STOP;
325 }
326
327 /* No need to update nip here, as execution flow will change */
328 static inline void gen_sync_exception(DisasContext *ctx)
329 {
330 ctx->exception = POWERPC_EXCP_SYNC;
331 }
332
333 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
334 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
335
336 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
337 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
338
339 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
344
345 typedef struct opcode_t {
346 unsigned char opc1, opc2, opc3;
347 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
348 unsigned char pad[5];
349 #else
350 unsigned char pad[1];
351 #endif
352 opc_handler_t handler;
353 const char *oname;
354 } opcode_t;
355
356 /*****************************************************************************/
357 /*** Instruction decoding ***/
358 #define EXTRACT_HELPER(name, shift, nb) \
359 static inline uint32_t name(uint32_t opcode) \
360 { \
361 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
362 }
363
364 #define EXTRACT_SHELPER(name, shift, nb) \
365 static inline int32_t name(uint32_t opcode) \
366 { \
367 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
368 }
369
370 /* Opcode part 1 */
371 EXTRACT_HELPER(opc1, 26, 6);
372 /* Opcode part 2 */
373 EXTRACT_HELPER(opc2, 1, 5);
374 /* Opcode part 3 */
375 EXTRACT_HELPER(opc3, 6, 5);
376 /* Update Cr0 flags */
377 EXTRACT_HELPER(Rc, 0, 1);
378 /* Destination */
379 EXTRACT_HELPER(rD, 21, 5);
380 /* Source */
381 EXTRACT_HELPER(rS, 21, 5);
382 /* First operand */
383 EXTRACT_HELPER(rA, 16, 5);
384 /* Second operand */
385 EXTRACT_HELPER(rB, 11, 5);
386 /* Third operand */
387 EXTRACT_HELPER(rC, 6, 5);
388 /*** Get CRn ***/
389 EXTRACT_HELPER(crfD, 23, 3);
390 EXTRACT_HELPER(crfS, 18, 3);
391 EXTRACT_HELPER(crbD, 21, 5);
392 EXTRACT_HELPER(crbA, 16, 5);
393 EXTRACT_HELPER(crbB, 11, 5);
394 /* SPR / TBL */
395 EXTRACT_HELPER(_SPR, 11, 10);
396 static inline uint32_t SPR(uint32_t opcode)
397 {
398 uint32_t sprn = _SPR(opcode);
399
400 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
401 }
402 /*** Get constants ***/
403 EXTRACT_HELPER(IMM, 12, 8);
404 /* 16 bits signed immediate value */
405 EXTRACT_SHELPER(SIMM, 0, 16);
406 /* 16 bits unsigned immediate value */
407 EXTRACT_HELPER(UIMM, 0, 16);
408 /* 5 bits signed immediate value */
409 EXTRACT_HELPER(SIMM5, 16, 5);
410 /* 5 bits signed immediate value */
411 EXTRACT_HELPER(UIMM5, 16, 5);
412 /* Bit count */
413 EXTRACT_HELPER(NB, 11, 5);
414 /* Shift count */
415 EXTRACT_HELPER(SH, 11, 5);
416 /* Vector shift count */
417 EXTRACT_HELPER(VSH, 6, 4);
418 /* Mask start */
419 EXTRACT_HELPER(MB, 6, 5);
420 /* Mask end */
421 EXTRACT_HELPER(ME, 1, 5);
422 /* Trap operand */
423 EXTRACT_HELPER(TO, 21, 5);
424
425 EXTRACT_HELPER(CRM, 12, 8);
426 EXTRACT_HELPER(FM, 17, 8);
427 EXTRACT_HELPER(SR, 16, 4);
428 EXTRACT_HELPER(FPIMM, 12, 4);
429
430 /*** Jump target decoding ***/
431 /* Displacement */
432 EXTRACT_SHELPER(d, 0, 16);
433 /* Immediate address */
434 static inline target_ulong LI(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0x03FFFFFC;
437 }
438
439 static inline uint32_t BD(uint32_t opcode)
440 {
441 return (opcode >> 0) & 0xFFFC;
442 }
443
444 EXTRACT_HELPER(BO, 21, 5);
445 EXTRACT_HELPER(BI, 16, 5);
446 /* Absolute/relative address */
447 EXTRACT_HELPER(AA, 1, 1);
448 /* Link */
449 EXTRACT_HELPER(LK, 0, 1);
450
451 /* Create a mask between <start> and <end> bits */
452 static inline target_ulong MASK(uint32_t start, uint32_t end)
453 {
454 target_ulong ret;
455
456 #if defined(TARGET_PPC64)
457 if (likely(start == 0)) {
458 ret = UINT64_MAX << (63 - end);
459 } else if (likely(end == 63)) {
460 ret = UINT64_MAX >> start;
461 }
462 #else
463 if (likely(start == 0)) {
464 ret = UINT32_MAX << (31 - end);
465 } else if (likely(end == 31)) {
466 ret = UINT32_MAX >> start;
467 }
468 #endif
469 else {
470 ret = (((target_ulong)(-1ULL)) >> (start)) ^
471 (((target_ulong)(-1ULL) >> (end)) >> 1);
472 if (unlikely(start > end))
473 return ~ret;
474 }
475
476 return ret;
477 }
478
479 /*****************************************************************************/
480 /* PowerPC instructions table */
481
482 #if defined(DO_PPC_STATISTICS)
483 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
484 { \
485 .opc1 = op1, \
486 .opc2 = op2, \
487 .opc3 = op3, \
488 .pad = { 0, }, \
489 .handler = { \
490 .inval1 = invl, \
491 .type = _typ, \
492 .type2 = _typ2, \
493 .handler = &gen_##name, \
494 .oname = stringify(name), \
495 }, \
496 .oname = stringify(name), \
497 }
498 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
499 { \
500 .opc1 = op1, \
501 .opc2 = op2, \
502 .opc3 = op3, \
503 .pad = { 0, }, \
504 .handler = { \
505 .inval1 = invl1, \
506 .inval2 = invl2, \
507 .type = _typ, \
508 .type2 = _typ2, \
509 .handler = &gen_##name, \
510 .oname = stringify(name), \
511 }, \
512 .oname = stringify(name), \
513 }
514 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
515 { \
516 .opc1 = op1, \
517 .opc2 = op2, \
518 .opc3 = op3, \
519 .pad = { 0, }, \
520 .handler = { \
521 .inval1 = invl, \
522 .type = _typ, \
523 .type2 = _typ2, \
524 .handler = &gen_##name, \
525 .oname = onam, \
526 }, \
527 .oname = onam, \
528 }
529 #else
530 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
531 { \
532 .opc1 = op1, \
533 .opc2 = op2, \
534 .opc3 = op3, \
535 .pad = { 0, }, \
536 .handler = { \
537 .inval1 = invl, \
538 .type = _typ, \
539 .type2 = _typ2, \
540 .handler = &gen_##name, \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .pad = { 0, }, \
550 .handler = { \
551 .inval1 = invl1, \
552 .inval2 = invl2, \
553 .type = _typ, \
554 .type2 = _typ2, \
555 .handler = &gen_##name, \
556 }, \
557 .oname = stringify(name), \
558 }
559 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
560 { \
561 .opc1 = op1, \
562 .opc2 = op2, \
563 .opc3 = op3, \
564 .pad = { 0, }, \
565 .handler = { \
566 .inval1 = invl, \
567 .type = _typ, \
568 .type2 = _typ2, \
569 .handler = &gen_##name, \
570 }, \
571 .oname = onam, \
572 }
573 #endif
574
575 /* SPR load/store helpers */
576 static inline void gen_load_spr(TCGv t, int reg)
577 {
578 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 static inline void gen_store_spr(int reg, TCGv t)
582 {
583 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
584 }
585
586 /* Invalid instruction */
587 static void gen_invalid(DisasContext *ctx)
588 {
589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
590 }
591
592 static opc_handler_t invalid_handler = {
593 .inval1 = 0xFFFFFFFF,
594 .inval2 = 0xFFFFFFFF,
595 .type = PPC_NONE,
596 .type2 = PPC_NONE,
597 .handler = gen_invalid,
598 };
599
600 /*** Integer comparison ***/
601
602 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
603 {
604 TCGv t0 = tcg_temp_new();
605 TCGv_i32 t1 = tcg_temp_new_i32();
606
607 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_LT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_GT);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
620 tcg_gen_trunc_tl_i32(t1, t0);
621 tcg_gen_shli_i32(t1, t1, CRF_EQ);
622 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
623
624 tcg_temp_free(t0);
625 tcg_temp_free_i32(t1);
626 }
627
628 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
629 {
630 TCGv t0 = tcg_const_tl(arg1);
631 gen_op_cmp(arg0, t0, s, crf);
632 tcg_temp_free(t0);
633 }
634
635 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
636 {
637 TCGv t0, t1;
638 t0 = tcg_temp_new();
639 t1 = tcg_temp_new();
640 if (s) {
641 tcg_gen_ext32s_tl(t0, arg0);
642 tcg_gen_ext32s_tl(t1, arg1);
643 } else {
644 tcg_gen_ext32u_tl(t0, arg0);
645 tcg_gen_ext32u_tl(t1, arg1);
646 }
647 gen_op_cmp(t0, t1, s, crf);
648 tcg_temp_free(t1);
649 tcg_temp_free(t0);
650 }
651
652 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
653 {
654 TCGv t0 = tcg_const_tl(arg1);
655 gen_op_cmp32(arg0, t0, s, crf);
656 tcg_temp_free(t0);
657 }
658
659 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
660 {
661 if (NARROW_MODE(ctx)) {
662 gen_op_cmpi32(reg, 0, 1, 0);
663 } else {
664 gen_op_cmpi(reg, 0, 1, 0);
665 }
666 }
667
668 /* cmp */
669 static void gen_cmp(DisasContext *ctx)
670 {
671 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
672 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
673 1, crfD(ctx->opcode));
674 } else {
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678 }
679
680 /* cmpi */
681 static void gen_cmpi(DisasContext *ctx)
682 {
683 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 } else {
687 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
688 1, crfD(ctx->opcode));
689 }
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
696 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
697 0, crfD(ctx->opcode));
698 } else {
699 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
700 0, crfD(ctx->opcode));
701 }
702 }
703
704 /* cmpli */
705 static void gen_cmpli(DisasContext *ctx)
706 {
707 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
708 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
709 0, crfD(ctx->opcode));
710 } else {
711 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
712 0, crfD(ctx->opcode));
713 }
714 }
715
716 /* isel (PowerPC 2.03 specification) */
717 static void gen_isel(DisasContext *ctx)
718 {
719 int l1, l2;
720 uint32_t bi = rC(ctx->opcode);
721 uint32_t mask;
722 TCGv_i32 t0;
723
724 l1 = gen_new_label();
725 l2 = gen_new_label();
726
727 mask = 1 << (3 - (bi & 0x03));
728 t0 = tcg_temp_new_i32();
729 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
730 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
731 if (rA(ctx->opcode) == 0)
732 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
733 else
734 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
735 tcg_gen_br(l2);
736 gen_set_label(l1);
737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
738 gen_set_label(l2);
739 tcg_temp_free_i32(t0);
740 }
741
742 /*** Integer arithmetic ***/
743
744 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
745 TCGv arg1, TCGv arg2, int sub)
746 {
747 TCGv t0 = tcg_temp_new();
748
749 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
750 tcg_gen_xor_tl(t0, arg1, arg2);
751 if (sub) {
752 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
753 } else {
754 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
755 }
756 tcg_temp_free(t0);
757 if (NARROW_MODE(ctx)) {
758 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
759 }
760 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
761 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
762 }
763
764 /* Common add function */
765 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
766 TCGv arg2, bool add_ca, bool compute_ca,
767 bool compute_ov, bool compute_rc0)
768 {
769 TCGv t0 = ret;
770
771 if (compute_ca || compute_ov) {
772 t0 = tcg_temp_new();
773 }
774
775 if (compute_ca) {
776 if (NARROW_MODE(ctx)) {
777 /* Caution: a non-obvious corner case of the spec is that we
778 must produce the *entire* 64-bit addition, but produce the
779 carry into bit 32. */
780 TCGv t1 = tcg_temp_new();
781 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
782 tcg_gen_add_tl(t0, arg1, arg2);
783 if (add_ca) {
784 tcg_gen_add_tl(t0, t0, cpu_ca);
785 }
786 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
787 tcg_temp_free(t1);
788 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
789 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
790 } else {
791 TCGv zero = tcg_const_tl(0);
792 if (add_ca) {
793 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
794 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
795 } else {
796 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
797 }
798 tcg_temp_free(zero);
799 }
800 } else {
801 tcg_gen_add_tl(t0, arg1, arg2);
802 if (add_ca) {
803 tcg_gen_add_tl(t0, t0, cpu_ca);
804 }
805 }
806
807 if (compute_ov) {
808 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
809 }
810 if (unlikely(compute_rc0)) {
811 gen_set_Rc0(ctx, t0);
812 }
813
814 if (!TCGV_EQUAL(t0, ret)) {
815 tcg_gen_mov_tl(ret, t0);
816 tcg_temp_free(t0);
817 }
818 }
819 /* Add functions with two operands */
820 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
821 static void glue(gen_, name)(DisasContext *ctx) \
822 { \
823 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
824 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
825 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
826 }
827 /* Add functions with one operand and one immediate */
828 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
829 add_ca, compute_ca, compute_ov) \
830 static void glue(gen_, name)(DisasContext *ctx) \
831 { \
832 TCGv t0 = tcg_const_tl(const_val); \
833 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
834 cpu_gpr[rA(ctx->opcode)], t0, \
835 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
836 tcg_temp_free(t0); \
837 }
838
839 /* add add. addo addo. */
840 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
841 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
842 /* addc addc. addco addco. */
843 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
844 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
845 /* adde adde. addeo addeo. */
846 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
847 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
848 /* addme addme. addmeo addmeo. */
849 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
850 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
851 /* addze addze. addzeo addzeo.*/
852 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
853 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
854 /* addi */
855 static void gen_addi(DisasContext *ctx)
856 {
857 target_long simm = SIMM(ctx->opcode);
858
859 if (rA(ctx->opcode) == 0) {
860 /* li case */
861 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
862 } else {
863 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
864 cpu_gpr[rA(ctx->opcode)], simm);
865 }
866 }
867 /* addic addic.*/
868 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
869 {
870 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
871 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
872 c, 0, 1, 0, compute_rc0);
873 tcg_temp_free(c);
874 }
875
876 static void gen_addic(DisasContext *ctx)
877 {
878 gen_op_addic(ctx, 0);
879 }
880
881 static void gen_addic_(DisasContext *ctx)
882 {
883 gen_op_addic(ctx, 1);
884 }
885
886 /* addis */
887 static void gen_addis(DisasContext *ctx)
888 {
889 target_long simm = SIMM(ctx->opcode);
890
891 if (rA(ctx->opcode) == 0) {
892 /* lis case */
893 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
894 } else {
895 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
896 cpu_gpr[rA(ctx->opcode)], simm << 16);
897 }
898 }
899
900 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
901 TCGv arg2, int sign, int compute_ov)
902 {
903 int l1 = gen_new_label();
904 int l2 = gen_new_label();
905 TCGv_i32 t0 = tcg_temp_local_new_i32();
906 TCGv_i32 t1 = tcg_temp_local_new_i32();
907
908 tcg_gen_trunc_tl_i32(t0, arg1);
909 tcg_gen_trunc_tl_i32(t1, arg2);
910 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
911 if (sign) {
912 int l3 = gen_new_label();
913 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
914 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
915 gen_set_label(l3);
916 tcg_gen_div_i32(t0, t0, t1);
917 } else {
918 tcg_gen_divu_i32(t0, t0, t1);
919 }
920 if (compute_ov) {
921 tcg_gen_movi_tl(cpu_ov, 0);
922 }
923 tcg_gen_br(l2);
924 gen_set_label(l1);
925 if (sign) {
926 tcg_gen_sari_i32(t0, t0, 31);
927 } else {
928 tcg_gen_movi_i32(t0, 0);
929 }
930 if (compute_ov) {
931 tcg_gen_movi_tl(cpu_ov, 1);
932 tcg_gen_movi_tl(cpu_so, 1);
933 }
934 gen_set_label(l2);
935 tcg_gen_extu_i32_tl(ret, t0);
936 tcg_temp_free_i32(t0);
937 tcg_temp_free_i32(t1);
938 if (unlikely(Rc(ctx->opcode) != 0))
939 gen_set_Rc0(ctx, ret);
940 }
941 /* Div functions */
942 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
943 static void glue(gen_, name)(DisasContext *ctx) \
944 { \
945 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
946 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
947 sign, compute_ov); \
948 }
949 /* divwu divwu. divwuo divwuo. */
950 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
951 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
952 /* divw divw. divwo divwo. */
953 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
954 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
955 #if defined(TARGET_PPC64)
956 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
957 TCGv arg2, int sign, int compute_ov)
958 {
959 int l1 = gen_new_label();
960 int l2 = gen_new_label();
961
962 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
963 if (sign) {
964 int l3 = gen_new_label();
965 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
966 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
967 gen_set_label(l3);
968 tcg_gen_div_i64(ret, arg1, arg2);
969 } else {
970 tcg_gen_divu_i64(ret, arg1, arg2);
971 }
972 if (compute_ov) {
973 tcg_gen_movi_tl(cpu_ov, 0);
974 }
975 tcg_gen_br(l2);
976 gen_set_label(l1);
977 if (sign) {
978 tcg_gen_sari_i64(ret, arg1, 63);
979 } else {
980 tcg_gen_movi_i64(ret, 0);
981 }
982 if (compute_ov) {
983 tcg_gen_movi_tl(cpu_ov, 1);
984 tcg_gen_movi_tl(cpu_so, 1);
985 }
986 gen_set_label(l2);
987 if (unlikely(Rc(ctx->opcode) != 0))
988 gen_set_Rc0(ctx, ret);
989 }
990 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
991 static void glue(gen_, name)(DisasContext *ctx) \
992 { \
993 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
994 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
995 sign, compute_ov); \
996 }
997 /* divwu divwu. divwuo divwuo. */
998 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
999 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1000 /* divw divw. divwo divwo. */
1001 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1002 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1003 #endif
1004
1005 /* mulhw mulhw. */
1006 static void gen_mulhw(DisasContext *ctx)
1007 {
1008 TCGv_i32 t0 = tcg_temp_new_i32();
1009 TCGv_i32 t1 = tcg_temp_new_i32();
1010
1011 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1012 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1013 tcg_gen_muls2_i32(t0, t1, t0, t1);
1014 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1015 tcg_temp_free_i32(t0);
1016 tcg_temp_free_i32(t1);
1017 if (unlikely(Rc(ctx->opcode) != 0))
1018 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1019 }
1020
1021 /* mulhwu mulhwu. */
1022 static void gen_mulhwu(DisasContext *ctx)
1023 {
1024 TCGv_i32 t0 = tcg_temp_new_i32();
1025 TCGv_i32 t1 = tcg_temp_new_i32();
1026
1027 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1028 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1029 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1030 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1031 tcg_temp_free_i32(t0);
1032 tcg_temp_free_i32(t1);
1033 if (unlikely(Rc(ctx->opcode) != 0))
1034 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1035 }
1036
1037 /* mullw mullw. */
1038 static void gen_mullw(DisasContext *ctx)
1039 {
1040 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1041 cpu_gpr[rB(ctx->opcode)]);
1042 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1043 if (unlikely(Rc(ctx->opcode) != 0))
1044 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1045 }
1046
1047 /* mullwo mullwo. */
1048 static void gen_mullwo(DisasContext *ctx)
1049 {
1050 TCGv_i32 t0 = tcg_temp_new_i32();
1051 TCGv_i32 t1 = tcg_temp_new_i32();
1052
1053 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1054 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1055 tcg_gen_muls2_i32(t0, t1, t0, t1);
1056 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1057
1058 tcg_gen_sari_i32(t0, t0, 31);
1059 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1060 tcg_gen_extu_i32_tl(cpu_ov, t0);
1061 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1062
1063 tcg_temp_free_i32(t0);
1064 tcg_temp_free_i32(t1);
1065 if (unlikely(Rc(ctx->opcode) != 0))
1066 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1067 }
1068
1069 /* mulli */
1070 static void gen_mulli(DisasContext *ctx)
1071 {
1072 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1073 SIMM(ctx->opcode));
1074 }
1075
1076 #if defined(TARGET_PPC64)
1077 /* mulhd mulhd. */
1078 static void gen_mulhd(DisasContext *ctx)
1079 {
1080 TCGv lo = tcg_temp_new();
1081 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1082 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1083 tcg_temp_free(lo);
1084 if (unlikely(Rc(ctx->opcode) != 0)) {
1085 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1086 }
1087 }
1088
1089 /* mulhdu mulhdu. */
1090 static void gen_mulhdu(DisasContext *ctx)
1091 {
1092 TCGv lo = tcg_temp_new();
1093 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1094 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1095 tcg_temp_free(lo);
1096 if (unlikely(Rc(ctx->opcode) != 0)) {
1097 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1098 }
1099 }
1100
1101 /* mulld mulld. */
1102 static void gen_mulld(DisasContext *ctx)
1103 {
1104 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1105 cpu_gpr[rB(ctx->opcode)]);
1106 if (unlikely(Rc(ctx->opcode) != 0))
1107 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1108 }
1109
1110 /* mulldo mulldo. */
1111 static void gen_mulldo(DisasContext *ctx)
1112 {
1113 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1114 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1115 if (unlikely(Rc(ctx->opcode) != 0)) {
1116 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1117 }
1118 }
1119 #endif
1120
1121 /* Common subf function */
1122 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1123 TCGv arg2, bool add_ca, bool compute_ca,
1124 bool compute_ov, bool compute_rc0)
1125 {
1126 TCGv t0 = ret;
1127
1128 if (compute_ca || compute_ov) {
1129 t0 = tcg_temp_new();
1130 }
1131
1132 if (compute_ca) {
1133 /* dest = ~arg1 + arg2 [+ ca]. */
1134 if (NARROW_MODE(ctx)) {
1135 /* Caution: a non-obvious corner case of the spec is that we
1136 must produce the *entire* 64-bit addition, but produce the
1137 carry into bit 32. */
1138 TCGv inv1 = tcg_temp_new();
1139 TCGv t1 = tcg_temp_new();
1140 tcg_gen_not_tl(inv1, arg1);
1141 if (add_ca) {
1142 tcg_gen_add_tl(t0, arg2, cpu_ca);
1143 } else {
1144 tcg_gen_addi_tl(t0, arg2, 1);
1145 }
1146 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1147 tcg_gen_add_tl(t0, t0, inv1);
1148 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1149 tcg_temp_free(t1);
1150 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1151 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1152 } else if (add_ca) {
1153 TCGv zero, inv1 = tcg_temp_new();
1154 tcg_gen_not_tl(inv1, arg1);
1155 zero = tcg_const_tl(0);
1156 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1157 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1158 tcg_temp_free(zero);
1159 tcg_temp_free(inv1);
1160 } else {
1161 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1162 tcg_gen_sub_tl(t0, arg2, arg1);
1163 }
1164 } else if (add_ca) {
1165 /* Since we're ignoring carry-out, we can simplify the
1166 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1167 tcg_gen_sub_tl(t0, arg2, arg1);
1168 tcg_gen_add_tl(t0, t0, cpu_ca);
1169 tcg_gen_subi_tl(t0, t0, 1);
1170 } else {
1171 tcg_gen_sub_tl(t0, arg2, arg1);
1172 }
1173
1174 if (compute_ov) {
1175 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1176 }
1177 if (unlikely(compute_rc0)) {
1178 gen_set_Rc0(ctx, t0);
1179 }
1180
1181 if (!TCGV_EQUAL(t0, ret)) {
1182 tcg_gen_mov_tl(ret, t0);
1183 tcg_temp_free(t0);
1184 }
1185 }
1186 /* Sub functions with Two operands functions */
1187 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1188 static void glue(gen_, name)(DisasContext *ctx) \
1189 { \
1190 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1191 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1192 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1193 }
1194 /* Sub functions with one operand and one immediate */
1195 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1196 add_ca, compute_ca, compute_ov) \
1197 static void glue(gen_, name)(DisasContext *ctx) \
1198 { \
1199 TCGv t0 = tcg_const_tl(const_val); \
1200 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1201 cpu_gpr[rA(ctx->opcode)], t0, \
1202 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1203 tcg_temp_free(t0); \
1204 }
1205 /* subf subf. subfo subfo. */
1206 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1207 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1208 /* subfc subfc. subfco subfco. */
1209 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1210 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1211 /* subfe subfe. subfeo subfo. */
1212 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1213 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1214 /* subfme subfme. subfmeo subfmeo. */
1215 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1216 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1217 /* subfze subfze. subfzeo subfzeo.*/
1218 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1219 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1220
1221 /* subfic */
1222 static void gen_subfic(DisasContext *ctx)
1223 {
1224 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1225 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1226 c, 0, 1, 0, 0);
1227 tcg_temp_free(c);
1228 }
1229
1230 /* neg neg. nego nego. */
1231 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1232 {
1233 TCGv zero = tcg_const_tl(0);
1234 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1235 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1236 tcg_temp_free(zero);
1237 }
1238
1239 static void gen_neg(DisasContext *ctx)
1240 {
1241 gen_op_arith_neg(ctx, 0);
1242 }
1243
1244 static void gen_nego(DisasContext *ctx)
1245 {
1246 gen_op_arith_neg(ctx, 1);
1247 }
1248
1249 /*** Integer logical ***/
1250 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1251 static void glue(gen_, name)(DisasContext *ctx) \
1252 { \
1253 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1254 cpu_gpr[rB(ctx->opcode)]); \
1255 if (unlikely(Rc(ctx->opcode) != 0)) \
1256 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1257 }
1258
1259 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1260 static void glue(gen_, name)(DisasContext *ctx) \
1261 { \
1262 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1263 if (unlikely(Rc(ctx->opcode) != 0)) \
1264 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1265 }
1266
1267 /* and & and. */
1268 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1269 /* andc & andc. */
1270 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1271
1272 /* andi. */
1273 static void gen_andi_(DisasContext *ctx)
1274 {
1275 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1276 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1277 }
1278
1279 /* andis. */
1280 static void gen_andis_(DisasContext *ctx)
1281 {
1282 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1283 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1284 }
1285
1286 /* cntlzw */
1287 static void gen_cntlzw(DisasContext *ctx)
1288 {
1289 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1290 if (unlikely(Rc(ctx->opcode) != 0))
1291 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1292 }
1293 /* eqv & eqv. */
1294 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1295 /* extsb & extsb. */
1296 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1297 /* extsh & extsh. */
1298 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1299 /* nand & nand. */
1300 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1301 /* nor & nor. */
1302 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1303
1304 /* or & or. */
1305 static void gen_or(DisasContext *ctx)
1306 {
1307 int rs, ra, rb;
1308
1309 rs = rS(ctx->opcode);
1310 ra = rA(ctx->opcode);
1311 rb = rB(ctx->opcode);
1312 /* Optimisation for mr. ri case */
1313 if (rs != ra || rs != rb) {
1314 if (rs != rb)
1315 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1316 else
1317 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1318 if (unlikely(Rc(ctx->opcode) != 0))
1319 gen_set_Rc0(ctx, cpu_gpr[ra]);
1320 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1321 gen_set_Rc0(ctx, cpu_gpr[rs]);
1322 #if defined(TARGET_PPC64)
1323 } else {
1324 int prio = 0;
1325
1326 switch (rs) {
1327 case 1:
1328 /* Set process priority to low */
1329 prio = 2;
1330 break;
1331 case 6:
1332 /* Set process priority to medium-low */
1333 prio = 3;
1334 break;
1335 case 2:
1336 /* Set process priority to normal */
1337 prio = 4;
1338 break;
1339 #if !defined(CONFIG_USER_ONLY)
1340 case 31:
1341 if (ctx->mem_idx > 0) {
1342 /* Set process priority to very low */
1343 prio = 1;
1344 }
1345 break;
1346 case 5:
1347 if (ctx->mem_idx > 0) {
1348 /* Set process priority to medium-hight */
1349 prio = 5;
1350 }
1351 break;
1352 case 3:
1353 if (ctx->mem_idx > 0) {
1354 /* Set process priority to high */
1355 prio = 6;
1356 }
1357 break;
1358 case 7:
1359 if (ctx->mem_idx > 1) {
1360 /* Set process priority to very high */
1361 prio = 7;
1362 }
1363 break;
1364 #endif
1365 default:
1366 /* nop */
1367 break;
1368 }
1369 if (prio) {
1370 TCGv t0 = tcg_temp_new();
1371 gen_load_spr(t0, SPR_PPR);
1372 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1373 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1374 gen_store_spr(SPR_PPR, t0);
1375 tcg_temp_free(t0);
1376 }
1377 #endif
1378 }
1379 }
1380 /* orc & orc. */
1381 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1382
1383 /* xor & xor. */
1384 static void gen_xor(DisasContext *ctx)
1385 {
1386 /* Optimisation for "set to zero" case */
1387 if (rS(ctx->opcode) != rB(ctx->opcode))
1388 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1389 else
1390 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1391 if (unlikely(Rc(ctx->opcode) != 0))
1392 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1393 }
1394
1395 /* ori */
1396 static void gen_ori(DisasContext *ctx)
1397 {
1398 target_ulong uimm = UIMM(ctx->opcode);
1399
1400 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1401 /* NOP */
1402 /* XXX: should handle special NOPs for POWER series */
1403 return;
1404 }
1405 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1406 }
1407
1408 /* oris */
1409 static void gen_oris(DisasContext *ctx)
1410 {
1411 target_ulong uimm = UIMM(ctx->opcode);
1412
1413 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1414 /* NOP */
1415 return;
1416 }
1417 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1418 }
1419
1420 /* xori */
1421 static void gen_xori(DisasContext *ctx)
1422 {
1423 target_ulong uimm = UIMM(ctx->opcode);
1424
1425 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1426 /* NOP */
1427 return;
1428 }
1429 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1430 }
1431
1432 /* xoris */
1433 static void gen_xoris(DisasContext *ctx)
1434 {
1435 target_ulong uimm = UIMM(ctx->opcode);
1436
1437 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1438 /* NOP */
1439 return;
1440 }
1441 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1442 }
1443
1444 /* popcntb : PowerPC 2.03 specification */
1445 static void gen_popcntb(DisasContext *ctx)
1446 {
1447 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1448 }
1449
1450 static void gen_popcntw(DisasContext *ctx)
1451 {
1452 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1453 }
1454
1455 #if defined(TARGET_PPC64)
1456 /* popcntd: PowerPC 2.06 specification */
1457 static void gen_popcntd(DisasContext *ctx)
1458 {
1459 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1460 }
1461 #endif
1462
1463 #if defined(TARGET_PPC64)
1464 /* extsw & extsw. */
1465 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1466
1467 /* cntlzd */
1468 static void gen_cntlzd(DisasContext *ctx)
1469 {
1470 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1471 if (unlikely(Rc(ctx->opcode) != 0))
1472 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1473 }
1474 #endif
1475
1476 /*** Integer rotate ***/
1477
1478 /* rlwimi & rlwimi. */
1479 static void gen_rlwimi(DisasContext *ctx)
1480 {
1481 uint32_t mb, me, sh;
1482
1483 mb = MB(ctx->opcode);
1484 me = ME(ctx->opcode);
1485 sh = SH(ctx->opcode);
1486 if (likely(sh == 0 && mb == 0 && me == 31)) {
1487 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1488 } else {
1489 target_ulong mask;
1490 TCGv t1;
1491 TCGv t0 = tcg_temp_new();
1492 #if defined(TARGET_PPC64)
1493 TCGv_i32 t2 = tcg_temp_new_i32();
1494 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1495 tcg_gen_rotli_i32(t2, t2, sh);
1496 tcg_gen_extu_i32_i64(t0, t2);
1497 tcg_temp_free_i32(t2);
1498 #else
1499 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1500 #endif
1501 #if defined(TARGET_PPC64)
1502 mb += 32;
1503 me += 32;
1504 #endif
1505 mask = MASK(mb, me);
1506 t1 = tcg_temp_new();
1507 tcg_gen_andi_tl(t0, t0, mask);
1508 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1509 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1510 tcg_temp_free(t0);
1511 tcg_temp_free(t1);
1512 }
1513 if (unlikely(Rc(ctx->opcode) != 0))
1514 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1515 }
1516
1517 /* rlwinm & rlwinm. */
1518 static void gen_rlwinm(DisasContext *ctx)
1519 {
1520 uint32_t mb, me, sh;
1521
1522 sh = SH(ctx->opcode);
1523 mb = MB(ctx->opcode);
1524 me = ME(ctx->opcode);
1525
1526 if (likely(mb == 0 && me == (31 - sh))) {
1527 if (likely(sh == 0)) {
1528 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1529 } else {
1530 TCGv t0 = tcg_temp_new();
1531 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1532 tcg_gen_shli_tl(t0, t0, sh);
1533 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1534 tcg_temp_free(t0);
1535 }
1536 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1537 TCGv t0 = tcg_temp_new();
1538 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1539 tcg_gen_shri_tl(t0, t0, mb);
1540 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1541 tcg_temp_free(t0);
1542 } else {
1543 TCGv t0 = tcg_temp_new();
1544 #if defined(TARGET_PPC64)
1545 TCGv_i32 t1 = tcg_temp_new_i32();
1546 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1547 tcg_gen_rotli_i32(t1, t1, sh);
1548 tcg_gen_extu_i32_i64(t0, t1);
1549 tcg_temp_free_i32(t1);
1550 #else
1551 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1552 #endif
1553 #if defined(TARGET_PPC64)
1554 mb += 32;
1555 me += 32;
1556 #endif
1557 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1558 tcg_temp_free(t0);
1559 }
1560 if (unlikely(Rc(ctx->opcode) != 0))
1561 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1562 }
1563
1564 /* rlwnm & rlwnm. */
1565 static void gen_rlwnm(DisasContext *ctx)
1566 {
1567 uint32_t mb, me;
1568 TCGv t0;
1569 #if defined(TARGET_PPC64)
1570 TCGv_i32 t1, t2;
1571 #endif
1572
1573 mb = MB(ctx->opcode);
1574 me = ME(ctx->opcode);
1575 t0 = tcg_temp_new();
1576 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1577 #if defined(TARGET_PPC64)
1578 t1 = tcg_temp_new_i32();
1579 t2 = tcg_temp_new_i32();
1580 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1581 tcg_gen_trunc_i64_i32(t2, t0);
1582 tcg_gen_rotl_i32(t1, t1, t2);
1583 tcg_gen_extu_i32_i64(t0, t1);
1584 tcg_temp_free_i32(t1);
1585 tcg_temp_free_i32(t2);
1586 #else
1587 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1588 #endif
1589 if (unlikely(mb != 0 || me != 31)) {
1590 #if defined(TARGET_PPC64)
1591 mb += 32;
1592 me += 32;
1593 #endif
1594 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1595 } else {
1596 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1597 }
1598 tcg_temp_free(t0);
1599 if (unlikely(Rc(ctx->opcode) != 0))
1600 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1601 }
1602
1603 #if defined(TARGET_PPC64)
1604 #define GEN_PPC64_R2(name, opc1, opc2) \
1605 static void glue(gen_, name##0)(DisasContext *ctx) \
1606 { \
1607 gen_##name(ctx, 0); \
1608 } \
1609 \
1610 static void glue(gen_, name##1)(DisasContext *ctx) \
1611 { \
1612 gen_##name(ctx, 1); \
1613 }
1614 #define GEN_PPC64_R4(name, opc1, opc2) \
1615 static void glue(gen_, name##0)(DisasContext *ctx) \
1616 { \
1617 gen_##name(ctx, 0, 0); \
1618 } \
1619 \
1620 static void glue(gen_, name##1)(DisasContext *ctx) \
1621 { \
1622 gen_##name(ctx, 0, 1); \
1623 } \
1624 \
1625 static void glue(gen_, name##2)(DisasContext *ctx) \
1626 { \
1627 gen_##name(ctx, 1, 0); \
1628 } \
1629 \
1630 static void glue(gen_, name##3)(DisasContext *ctx) \
1631 { \
1632 gen_##name(ctx, 1, 1); \
1633 }
1634
1635 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1636 uint32_t sh)
1637 {
1638 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1639 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1640 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1641 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1642 } else {
1643 TCGv t0 = tcg_temp_new();
1644 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1645 if (likely(mb == 0 && me == 63)) {
1646 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1647 } else {
1648 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1649 }
1650 tcg_temp_free(t0);
1651 }
1652 if (unlikely(Rc(ctx->opcode) != 0))
1653 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1654 }
1655 /* rldicl - rldicl. */
1656 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1657 {
1658 uint32_t sh, mb;
1659
1660 sh = SH(ctx->opcode) | (shn << 5);
1661 mb = MB(ctx->opcode) | (mbn << 5);
1662 gen_rldinm(ctx, mb, 63, sh);
1663 }
1664 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1665 /* rldicr - rldicr. */
1666 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1667 {
1668 uint32_t sh, me;
1669
1670 sh = SH(ctx->opcode) | (shn << 5);
1671 me = MB(ctx->opcode) | (men << 5);
1672 gen_rldinm(ctx, 0, me, sh);
1673 }
1674 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1675 /* rldic - rldic. */
1676 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1677 {
1678 uint32_t sh, mb;
1679
1680 sh = SH(ctx->opcode) | (shn << 5);
1681 mb = MB(ctx->opcode) | (mbn << 5);
1682 gen_rldinm(ctx, mb, 63 - sh, sh);
1683 }
1684 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1685
1686 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1687 {
1688 TCGv t0;
1689
1690 mb = MB(ctx->opcode);
1691 me = ME(ctx->opcode);
1692 t0 = tcg_temp_new();
1693 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1694 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1695 if (unlikely(mb != 0 || me != 63)) {
1696 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1697 } else {
1698 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1699 }
1700 tcg_temp_free(t0);
1701 if (unlikely(Rc(ctx->opcode) != 0))
1702 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1703 }
1704
1705 /* rldcl - rldcl. */
1706 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1707 {
1708 uint32_t mb;
1709
1710 mb = MB(ctx->opcode) | (mbn << 5);
1711 gen_rldnm(ctx, mb, 63);
1712 }
1713 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1714 /* rldcr - rldcr. */
1715 static inline void gen_rldcr(DisasContext *ctx, int men)
1716 {
1717 uint32_t me;
1718
1719 me = MB(ctx->opcode) | (men << 5);
1720 gen_rldnm(ctx, 0, me);
1721 }
1722 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1723 /* rldimi - rldimi. */
1724 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1725 {
1726 uint32_t sh, mb, me;
1727
1728 sh = SH(ctx->opcode) | (shn << 5);
1729 mb = MB(ctx->opcode) | (mbn << 5);
1730 me = 63 - sh;
1731 if (unlikely(sh == 0 && mb == 0)) {
1732 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1733 } else {
1734 TCGv t0, t1;
1735 target_ulong mask;
1736
1737 t0 = tcg_temp_new();
1738 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1739 t1 = tcg_temp_new();
1740 mask = MASK(mb, me);
1741 tcg_gen_andi_tl(t0, t0, mask);
1742 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1743 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1744 tcg_temp_free(t0);
1745 tcg_temp_free(t1);
1746 }
1747 if (unlikely(Rc(ctx->opcode) != 0))
1748 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1749 }
1750 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1751 #endif
1752
1753 /*** Integer shift ***/
1754
1755 /* slw & slw. */
1756 static void gen_slw(DisasContext *ctx)
1757 {
1758 TCGv t0, t1;
1759
1760 t0 = tcg_temp_new();
1761 /* AND rS with a mask that is 0 when rB >= 0x20 */
1762 #if defined(TARGET_PPC64)
1763 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1764 tcg_gen_sari_tl(t0, t0, 0x3f);
1765 #else
1766 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1767 tcg_gen_sari_tl(t0, t0, 0x1f);
1768 #endif
1769 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1770 t1 = tcg_temp_new();
1771 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1772 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1773 tcg_temp_free(t1);
1774 tcg_temp_free(t0);
1775 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1776 if (unlikely(Rc(ctx->opcode) != 0))
1777 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1778 }
1779
1780 /* sraw & sraw. */
1781 static void gen_sraw(DisasContext *ctx)
1782 {
1783 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1784 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1785 if (unlikely(Rc(ctx->opcode) != 0))
1786 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1787 }
1788
1789 /* srawi & srawi. */
1790 static void gen_srawi(DisasContext *ctx)
1791 {
1792 int sh = SH(ctx->opcode);
1793 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1794 TCGv src = cpu_gpr[rS(ctx->opcode)];
1795 if (sh == 0) {
1796 tcg_gen_mov_tl(dst, src);
1797 tcg_gen_movi_tl(cpu_ca, 0);
1798 } else {
1799 TCGv t0;
1800 tcg_gen_ext32s_tl(dst, src);
1801 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1802 t0 = tcg_temp_new();
1803 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1804 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1805 tcg_temp_free(t0);
1806 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1807 tcg_gen_sari_tl(dst, dst, sh);
1808 }
1809 if (unlikely(Rc(ctx->opcode) != 0)) {
1810 gen_set_Rc0(ctx, dst);
1811 }
1812 }
1813
1814 /* srw & srw. */
1815 static void gen_srw(DisasContext *ctx)
1816 {
1817 TCGv t0, t1;
1818
1819 t0 = tcg_temp_new();
1820 /* AND rS with a mask that is 0 when rB >= 0x20 */
1821 #if defined(TARGET_PPC64)
1822 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1823 tcg_gen_sari_tl(t0, t0, 0x3f);
1824 #else
1825 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1826 tcg_gen_sari_tl(t0, t0, 0x1f);
1827 #endif
1828 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1829 tcg_gen_ext32u_tl(t0, t0);
1830 t1 = tcg_temp_new();
1831 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1832 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1833 tcg_temp_free(t1);
1834 tcg_temp_free(t0);
1835 if (unlikely(Rc(ctx->opcode) != 0))
1836 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1837 }
1838
1839 #if defined(TARGET_PPC64)
1840 /* sld & sld. */
1841 static void gen_sld(DisasContext *ctx)
1842 {
1843 TCGv t0, t1;
1844
1845 t0 = tcg_temp_new();
1846 /* AND rS with a mask that is 0 when rB >= 0x40 */
1847 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1848 tcg_gen_sari_tl(t0, t0, 0x3f);
1849 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1850 t1 = tcg_temp_new();
1851 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1852 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1853 tcg_temp_free(t1);
1854 tcg_temp_free(t0);
1855 if (unlikely(Rc(ctx->opcode) != 0))
1856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1857 }
1858
1859 /* srad & srad. */
1860 static void gen_srad(DisasContext *ctx)
1861 {
1862 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1863 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1864 if (unlikely(Rc(ctx->opcode) != 0))
1865 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1866 }
1867 /* sradi & sradi. */
1868 static inline void gen_sradi(DisasContext *ctx, int n)
1869 {
1870 int sh = SH(ctx->opcode) + (n << 5);
1871 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1872 TCGv src = cpu_gpr[rS(ctx->opcode)];
1873 if (sh == 0) {
1874 tcg_gen_mov_tl(dst, src);
1875 tcg_gen_movi_tl(cpu_ca, 0);
1876 } else {
1877 TCGv t0;
1878 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1879 t0 = tcg_temp_new();
1880 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1881 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1882 tcg_temp_free(t0);
1883 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1884 tcg_gen_sari_tl(dst, src, sh);
1885 }
1886 if (unlikely(Rc(ctx->opcode) != 0)) {
1887 gen_set_Rc0(ctx, dst);
1888 }
1889 }
1890
1891 static void gen_sradi0(DisasContext *ctx)
1892 {
1893 gen_sradi(ctx, 0);
1894 }
1895
1896 static void gen_sradi1(DisasContext *ctx)
1897 {
1898 gen_sradi(ctx, 1);
1899 }
1900
1901 /* srd & srd. */
1902 static void gen_srd(DisasContext *ctx)
1903 {
1904 TCGv t0, t1;
1905
1906 t0 = tcg_temp_new();
1907 /* AND rS with a mask that is 0 when rB >= 0x40 */
1908 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1909 tcg_gen_sari_tl(t0, t0, 0x3f);
1910 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1911 t1 = tcg_temp_new();
1912 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1913 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1914 tcg_temp_free(t1);
1915 tcg_temp_free(t0);
1916 if (unlikely(Rc(ctx->opcode) != 0))
1917 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1918 }
1919 #endif
1920
1921 /*** Floating-Point arithmetic ***/
1922 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1923 static void gen_f##name(DisasContext *ctx) \
1924 { \
1925 if (unlikely(!ctx->fpu_enabled)) { \
1926 gen_exception(ctx, POWERPC_EXCP_FPU); \
1927 return; \
1928 } \
1929 /* NIP cannot be restored if the memory exception comes from an helper */ \
1930 gen_update_nip(ctx, ctx->nip - 4); \
1931 gen_reset_fpstatus(); \
1932 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1933 cpu_fpr[rA(ctx->opcode)], \
1934 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1935 if (isfloat) { \
1936 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1937 cpu_fpr[rD(ctx->opcode)]); \
1938 } \
1939 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1940 Rc(ctx->opcode) != 0); \
1941 }
1942
1943 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1944 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1945 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1946
1947 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1948 static void gen_f##name(DisasContext *ctx) \
1949 { \
1950 if (unlikely(!ctx->fpu_enabled)) { \
1951 gen_exception(ctx, POWERPC_EXCP_FPU); \
1952 return; \
1953 } \
1954 /* NIP cannot be restored if the memory exception comes from an helper */ \
1955 gen_update_nip(ctx, ctx->nip - 4); \
1956 gen_reset_fpstatus(); \
1957 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1958 cpu_fpr[rA(ctx->opcode)], \
1959 cpu_fpr[rB(ctx->opcode)]); \
1960 if (isfloat) { \
1961 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1962 cpu_fpr[rD(ctx->opcode)]); \
1963 } \
1964 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1965 set_fprf, Rc(ctx->opcode) != 0); \
1966 }
1967 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1968 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1969 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1970
1971 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1972 static void gen_f##name(DisasContext *ctx) \
1973 { \
1974 if (unlikely(!ctx->fpu_enabled)) { \
1975 gen_exception(ctx, POWERPC_EXCP_FPU); \
1976 return; \
1977 } \
1978 /* NIP cannot be restored if the memory exception comes from an helper */ \
1979 gen_update_nip(ctx, ctx->nip - 4); \
1980 gen_reset_fpstatus(); \
1981 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1982 cpu_fpr[rA(ctx->opcode)], \
1983 cpu_fpr[rC(ctx->opcode)]); \
1984 if (isfloat) { \
1985 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1986 cpu_fpr[rD(ctx->opcode)]); \
1987 } \
1988 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1989 set_fprf, Rc(ctx->opcode) != 0); \
1990 }
1991 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1992 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1993 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1994
1995 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1996 static void gen_f##name(DisasContext *ctx) \
1997 { \
1998 if (unlikely(!ctx->fpu_enabled)) { \
1999 gen_exception(ctx, POWERPC_EXCP_FPU); \
2000 return; \
2001 } \
2002 /* NIP cannot be restored if the memory exception comes from an helper */ \
2003 gen_update_nip(ctx, ctx->nip - 4); \
2004 gen_reset_fpstatus(); \
2005 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2006 cpu_fpr[rB(ctx->opcode)]); \
2007 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2008 set_fprf, Rc(ctx->opcode) != 0); \
2009 }
2010
2011 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2012 static void gen_f##name(DisasContext *ctx) \
2013 { \
2014 if (unlikely(!ctx->fpu_enabled)) { \
2015 gen_exception(ctx, POWERPC_EXCP_FPU); \
2016 return; \
2017 } \
2018 /* NIP cannot be restored if the memory exception comes from an helper */ \
2019 gen_update_nip(ctx, ctx->nip - 4); \
2020 gen_reset_fpstatus(); \
2021 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2022 cpu_fpr[rB(ctx->opcode)]); \
2023 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2024 set_fprf, Rc(ctx->opcode) != 0); \
2025 }
2026
2027 /* fadd - fadds */
2028 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2029 /* fdiv - fdivs */
2030 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2031 /* fmul - fmuls */
2032 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2033
2034 /* fre */
2035 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2036
2037 /* fres */
2038 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2039
2040 /* frsqrte */
2041 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2042
2043 /* frsqrtes */
2044 static void gen_frsqrtes(DisasContext *ctx)
2045 {
2046 if (unlikely(!ctx->fpu_enabled)) {
2047 gen_exception(ctx, POWERPC_EXCP_FPU);
2048 return;
2049 }
2050 /* NIP cannot be restored if the memory exception comes from an helper */
2051 gen_update_nip(ctx, ctx->nip - 4);
2052 gen_reset_fpstatus();
2053 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2054 cpu_fpr[rB(ctx->opcode)]);
2055 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2056 cpu_fpr[rD(ctx->opcode)]);
2057 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2058 }
2059
2060 /* fsel */
2061 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2062 /* fsub - fsubs */
2063 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2064 /* Optional: */
2065
2066 /* fsqrt */
2067 static void gen_fsqrt(DisasContext *ctx)
2068 {
2069 if (unlikely(!ctx->fpu_enabled)) {
2070 gen_exception(ctx, POWERPC_EXCP_FPU);
2071 return;
2072 }
2073 /* NIP cannot be restored if the memory exception comes from an helper */
2074 gen_update_nip(ctx, ctx->nip - 4);
2075 gen_reset_fpstatus();
2076 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2077 cpu_fpr[rB(ctx->opcode)]);
2078 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2079 }
2080
2081 static void gen_fsqrts(DisasContext *ctx)
2082 {
2083 if (unlikely(!ctx->fpu_enabled)) {
2084 gen_exception(ctx, POWERPC_EXCP_FPU);
2085 return;
2086 }
2087 /* NIP cannot be restored if the memory exception comes from an helper */
2088 gen_update_nip(ctx, ctx->nip - 4);
2089 gen_reset_fpstatus();
2090 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2091 cpu_fpr[rB(ctx->opcode)]);
2092 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2093 cpu_fpr[rD(ctx->opcode)]);
2094 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2095 }
2096
2097 /*** Floating-Point multiply-and-add ***/
2098 /* fmadd - fmadds */
2099 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2100 /* fmsub - fmsubs */
2101 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2102 /* fnmadd - fnmadds */
2103 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2104 /* fnmsub - fnmsubs */
2105 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2106
2107 /*** Floating-Point round & convert ***/
2108 /* fctiw */
2109 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2110 /* fctiwz */
2111 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2112 /* frsp */
2113 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2114 #if defined(TARGET_PPC64)
2115 /* fcfid */
2116 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2117 /* fctid */
2118 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2119 /* fctidz */
2120 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2121 #endif
2122
2123 /* frin */
2124 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2125 /* friz */
2126 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2127 /* frip */
2128 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2129 /* frim */
2130 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2131
2132 /*** Floating-Point compare ***/
2133
2134 /* fcmpo */
2135 static void gen_fcmpo(DisasContext *ctx)
2136 {
2137 TCGv_i32 crf;
2138 if (unlikely(!ctx->fpu_enabled)) {
2139 gen_exception(ctx, POWERPC_EXCP_FPU);
2140 return;
2141 }
2142 /* NIP cannot be restored if the memory exception comes from an helper */
2143 gen_update_nip(ctx, ctx->nip - 4);
2144 gen_reset_fpstatus();
2145 crf = tcg_const_i32(crfD(ctx->opcode));
2146 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2147 cpu_fpr[rB(ctx->opcode)], crf);
2148 tcg_temp_free_i32(crf);
2149 gen_helper_float_check_status(cpu_env);
2150 }
2151
2152 /* fcmpu */
2153 static void gen_fcmpu(DisasContext *ctx)
2154 {
2155 TCGv_i32 crf;
2156 if (unlikely(!ctx->fpu_enabled)) {
2157 gen_exception(ctx, POWERPC_EXCP_FPU);
2158 return;
2159 }
2160 /* NIP cannot be restored if the memory exception comes from an helper */
2161 gen_update_nip(ctx, ctx->nip - 4);
2162 gen_reset_fpstatus();
2163 crf = tcg_const_i32(crfD(ctx->opcode));
2164 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2165 cpu_fpr[rB(ctx->opcode)], crf);
2166 tcg_temp_free_i32(crf);
2167 gen_helper_float_check_status(cpu_env);
2168 }
2169
2170 /*** Floating-point move ***/
2171 /* fabs */
2172 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2173 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2174
2175 /* fmr - fmr. */
2176 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2177 static void gen_fmr(DisasContext *ctx)
2178 {
2179 if (unlikely(!ctx->fpu_enabled)) {
2180 gen_exception(ctx, POWERPC_EXCP_FPU);
2181 return;
2182 }
2183 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2184 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2185 }
2186
2187 /* fnabs */
2188 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2189 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2190 /* fneg */
2191 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2192 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2193
2194 /*** Floating-Point status & ctrl register ***/
2195
2196 /* mcrfs */
2197 static void gen_mcrfs(DisasContext *ctx)
2198 {
2199 TCGv tmp = tcg_temp_new();
2200 int bfa;
2201
2202 if (unlikely(!ctx->fpu_enabled)) {
2203 gen_exception(ctx, POWERPC_EXCP_FPU);
2204 return;
2205 }
2206 bfa = 4 * (7 - crfS(ctx->opcode));
2207 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2208 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2209 tcg_temp_free(tmp);
2210 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2211 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2212 }
2213
2214 /* mffs */
2215 static void gen_mffs(DisasContext *ctx)
2216 {
2217 if (unlikely(!ctx->fpu_enabled)) {
2218 gen_exception(ctx, POWERPC_EXCP_FPU);
2219 return;
2220 }
2221 gen_reset_fpstatus();
2222 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2223 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2224 }
2225
2226 /* mtfsb0 */
2227 static void gen_mtfsb0(DisasContext *ctx)
2228 {
2229 uint8_t crb;
2230
2231 if (unlikely(!ctx->fpu_enabled)) {
2232 gen_exception(ctx, POWERPC_EXCP_FPU);
2233 return;
2234 }
2235 crb = 31 - crbD(ctx->opcode);
2236 gen_reset_fpstatus();
2237 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2238 TCGv_i32 t0;
2239 /* NIP cannot be restored if the memory exception comes from an helper */
2240 gen_update_nip(ctx, ctx->nip - 4);
2241 t0 = tcg_const_i32(crb);
2242 gen_helper_fpscr_clrbit(cpu_env, t0);
2243 tcg_temp_free_i32(t0);
2244 }
2245 if (unlikely(Rc(ctx->opcode) != 0)) {
2246 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2247 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2248 }
2249 }
2250
2251 /* mtfsb1 */
2252 static void gen_mtfsb1(DisasContext *ctx)
2253 {
2254 uint8_t crb;
2255
2256 if (unlikely(!ctx->fpu_enabled)) {
2257 gen_exception(ctx, POWERPC_EXCP_FPU);
2258 return;
2259 }
2260 crb = 31 - crbD(ctx->opcode);
2261 gen_reset_fpstatus();
2262 /* XXX: we pretend we can only do IEEE floating-point computations */
2263 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2264 TCGv_i32 t0;
2265 /* NIP cannot be restored if the memory exception comes from an helper */
2266 gen_update_nip(ctx, ctx->nip - 4);
2267 t0 = tcg_const_i32(crb);
2268 gen_helper_fpscr_setbit(cpu_env, t0);
2269 tcg_temp_free_i32(t0);
2270 }
2271 if (unlikely(Rc(ctx->opcode) != 0)) {
2272 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2273 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2274 }
2275 /* We can raise a differed exception */
2276 gen_helper_float_check_status(cpu_env);
2277 }
2278
2279 /* mtfsf */
2280 static void gen_mtfsf(DisasContext *ctx)
2281 {
2282 TCGv_i32 t0;
2283 int L = ctx->opcode & 0x02000000;
2284
2285 if (unlikely(!ctx->fpu_enabled)) {
2286 gen_exception(ctx, POWERPC_EXCP_FPU);
2287 return;
2288 }
2289 /* NIP cannot be restored if the memory exception comes from an helper */
2290 gen_update_nip(ctx, ctx->nip - 4);
2291 gen_reset_fpstatus();
2292 if (L)
2293 t0 = tcg_const_i32(0xff);
2294 else
2295 t0 = tcg_const_i32(FM(ctx->opcode));
2296 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2297 tcg_temp_free_i32(t0);
2298 if (unlikely(Rc(ctx->opcode) != 0)) {
2299 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2300 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2301 }
2302 /* We can raise a differed exception */
2303 gen_helper_float_check_status(cpu_env);
2304 }
2305
2306 /* mtfsfi */
2307 static void gen_mtfsfi(DisasContext *ctx)
2308 {
2309 int bf, sh;
2310 TCGv_i64 t0;
2311 TCGv_i32 t1;
2312
2313 if (unlikely(!ctx->fpu_enabled)) {
2314 gen_exception(ctx, POWERPC_EXCP_FPU);
2315 return;
2316 }
2317 bf = crbD(ctx->opcode) >> 2;
2318 sh = 7 - bf;
2319 /* NIP cannot be restored if the memory exception comes from an helper */
2320 gen_update_nip(ctx, ctx->nip - 4);
2321 gen_reset_fpstatus();
2322 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2323 t1 = tcg_const_i32(1 << sh);
2324 gen_helper_store_fpscr(cpu_env, t0, t1);
2325 tcg_temp_free_i64(t0);
2326 tcg_temp_free_i32(t1);
2327 if (unlikely(Rc(ctx->opcode) != 0)) {
2328 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2329 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2330 }
2331 /* We can raise a differed exception */
2332 gen_helper_float_check_status(cpu_env);
2333 }
2334
2335 /*** Addressing modes ***/
2336 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2337 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2338 target_long maskl)
2339 {
2340 target_long simm = SIMM(ctx->opcode);
2341
2342 simm &= ~maskl;
2343 if (rA(ctx->opcode) == 0) {
2344 if (NARROW_MODE(ctx)) {
2345 simm = (uint32_t)simm;
2346 }
2347 tcg_gen_movi_tl(EA, simm);
2348 } else if (likely(simm != 0)) {
2349 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2350 if (NARROW_MODE(ctx)) {
2351 tcg_gen_ext32u_tl(EA, EA);
2352 }
2353 } else {
2354 if (NARROW_MODE(ctx)) {
2355 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2356 } else {
2357 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2358 }
2359 }
2360 }
2361
2362 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2363 {
2364 if (rA(ctx->opcode) == 0) {
2365 if (NARROW_MODE(ctx)) {
2366 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2367 } else {
2368 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2369 }
2370 } else {
2371 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2372 if (NARROW_MODE(ctx)) {
2373 tcg_gen_ext32u_tl(EA, EA);
2374 }
2375 }
2376 }
2377
2378 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2379 {
2380 if (rA(ctx->opcode) == 0) {
2381 tcg_gen_movi_tl(EA, 0);
2382 } else if (NARROW_MODE(ctx)) {
2383 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2384 } else {
2385 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2386 }
2387 }
2388
2389 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2390 target_long val)
2391 {
2392 tcg_gen_addi_tl(ret, arg1, val);
2393 if (NARROW_MODE(ctx)) {
2394 tcg_gen_ext32u_tl(ret, ret);
2395 }
2396 }
2397
2398 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2399 {
2400 int l1 = gen_new_label();
2401 TCGv t0 = tcg_temp_new();
2402 TCGv_i32 t1, t2;
2403 /* NIP cannot be restored if the memory exception comes from an helper */
2404 gen_update_nip(ctx, ctx->nip - 4);
2405 tcg_gen_andi_tl(t0, EA, mask);
2406 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2407 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2408 t2 = tcg_const_i32(0);
2409 gen_helper_raise_exception_err(cpu_env, t1, t2);
2410 tcg_temp_free_i32(t1);
2411 tcg_temp_free_i32(t2);
2412 gen_set_label(l1);
2413 tcg_temp_free(t0);
2414 }
2415
2416 /*** Integer load ***/
2417 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2418 {
2419 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2420 }
2421
2422 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2423 {
2424 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2425 }
2426
2427 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2428 {
2429 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2430 if (unlikely(ctx->le_mode)) {
2431 tcg_gen_bswap16_tl(arg1, arg1);
2432 }
2433 }
2434
2435 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2436 {
2437 if (unlikely(ctx->le_mode)) {
2438 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2439 tcg_gen_bswap16_tl(arg1, arg1);
2440 tcg_gen_ext16s_tl(arg1, arg1);
2441 } else {
2442 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2443 }
2444 }
2445
2446 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2447 {
2448 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2449 if (unlikely(ctx->le_mode)) {
2450 tcg_gen_bswap32_tl(arg1, arg1);
2451 }
2452 }
2453
2454 #if defined(TARGET_PPC64)
2455 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2456 {
2457 if (unlikely(ctx->le_mode)) {
2458 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2459 tcg_gen_bswap32_tl(arg1, arg1);
2460 tcg_gen_ext32s_tl(arg1, arg1);
2461 } else
2462 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2463 }
2464 #endif
2465
2466 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2467 {
2468 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2469 if (unlikely(ctx->le_mode)) {
2470 tcg_gen_bswap64_i64(arg1, arg1);
2471 }
2472 }
2473
2474 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2475 {
2476 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2477 }
2478
2479 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2480 {
2481 if (unlikely(ctx->le_mode)) {
2482 TCGv t0 = tcg_temp_new();
2483 tcg_gen_ext16u_tl(t0, arg1);
2484 tcg_gen_bswap16_tl(t0, t0);
2485 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2486 tcg_temp_free(t0);
2487 } else {
2488 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2489 }
2490 }
2491
2492 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2493 {
2494 if (unlikely(ctx->le_mode)) {
2495 TCGv t0 = tcg_temp_new();
2496 tcg_gen_ext32u_tl(t0, arg1);
2497 tcg_gen_bswap32_tl(t0, t0);
2498 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2499 tcg_temp_free(t0);
2500 } else {
2501 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2502 }
2503 }
2504
2505 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2506 {
2507 if (unlikely(ctx->le_mode)) {
2508 TCGv_i64 t0 = tcg_temp_new_i64();
2509 tcg_gen_bswap64_i64(t0, arg1);
2510 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2511 tcg_temp_free_i64(t0);
2512 } else
2513 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2514 }
2515
2516 #define GEN_LD(name, ldop, opc, type) \
2517 static void glue(gen_, name)(DisasContext *ctx) \
2518 { \
2519 TCGv EA; \
2520 gen_set_access_type(ctx, ACCESS_INT); \
2521 EA = tcg_temp_new(); \
2522 gen_addr_imm_index(ctx, EA, 0); \
2523 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2524 tcg_temp_free(EA); \
2525 }
2526
2527 #define GEN_LDU(name, ldop, opc, type) \
2528 static void glue(gen_, name##u)(DisasContext *ctx) \
2529 { \
2530 TCGv EA; \
2531 if (unlikely(rA(ctx->opcode) == 0 || \
2532 rA(ctx->opcode) == rD(ctx->opcode))) { \
2533 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2534 return; \
2535 } \
2536 gen_set_access_type(ctx, ACCESS_INT); \
2537 EA = tcg_temp_new(); \
2538 if (type == PPC_64B) \
2539 gen_addr_imm_index(ctx, EA, 0x03); \
2540 else \
2541 gen_addr_imm_index(ctx, EA, 0); \
2542 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2543 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2544 tcg_temp_free(EA); \
2545 }
2546
2547 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2548 static void glue(gen_, name##ux)(DisasContext *ctx) \
2549 { \
2550 TCGv EA; \
2551 if (unlikely(rA(ctx->opcode) == 0 || \
2552 rA(ctx->opcode) == rD(ctx->opcode))) { \
2553 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2554 return; \
2555 } \
2556 gen_set_access_type(ctx, ACCESS_INT); \
2557 EA = tcg_temp_new(); \
2558 gen_addr_reg_index(ctx, EA); \
2559 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2560 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2561 tcg_temp_free(EA); \
2562 }
2563
2564 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2565 static void glue(gen_, name##x)(DisasContext *ctx) \
2566 { \
2567 TCGv EA; \
2568 gen_set_access_type(ctx, ACCESS_INT); \
2569 EA = tcg_temp_new(); \
2570 gen_addr_reg_index(ctx, EA); \
2571 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2572 tcg_temp_free(EA); \
2573 }
2574 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2575 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2576
2577 #define GEN_LDS(name, ldop, op, type) \
2578 GEN_LD(name, ldop, op | 0x20, type); \
2579 GEN_LDU(name, ldop, op | 0x21, type); \
2580 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2581 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2582
2583 /* lbz lbzu lbzux lbzx */
2584 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2585 /* lha lhau lhaux lhax */
2586 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2587 /* lhz lhzu lhzux lhzx */
2588 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2589 /* lwz lwzu lwzux lwzx */
2590 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2591 #if defined(TARGET_PPC64)
2592 /* lwaux */
2593 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2594 /* lwax */
2595 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2596 /* ldux */
2597 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2598 /* ldx */
2599 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2600
2601 static void gen_ld(DisasContext *ctx)
2602 {
2603 TCGv EA;
2604 if (Rc(ctx->opcode)) {
2605 if (unlikely(rA(ctx->opcode) == 0 ||
2606 rA(ctx->opcode) == rD(ctx->opcode))) {
2607 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2608 return;
2609 }
2610 }
2611 gen_set_access_type(ctx, ACCESS_INT);
2612 EA = tcg_temp_new();
2613 gen_addr_imm_index(ctx, EA, 0x03);
2614 if (ctx->opcode & 0x02) {
2615 /* lwa (lwau is undefined) */
2616 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2617 } else {
2618 /* ld - ldu */
2619 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2620 }
2621 if (Rc(ctx->opcode))
2622 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2623 tcg_temp_free(EA);
2624 }
2625
2626 /* lq */
2627 static void gen_lq(DisasContext *ctx)
2628 {
2629 #if defined(CONFIG_USER_ONLY)
2630 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2631 #else
2632 int ra, rd;
2633 TCGv EA;
2634
2635 /* Restore CPU state */
2636 if (unlikely(ctx->mem_idx == 0)) {
2637 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2638 return;
2639 }
2640 ra = rA(ctx->opcode);
2641 rd = rD(ctx->opcode);
2642 if (unlikely((rd & 1) || rd == ra)) {
2643 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2644 return;
2645 }
2646 if (unlikely(ctx->le_mode)) {
2647 /* Little-endian mode is not handled */
2648 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2649 return;
2650 }
2651 gen_set_access_type(ctx, ACCESS_INT);
2652 EA = tcg_temp_new();
2653 gen_addr_imm_index(ctx, EA, 0x0F);
2654 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2655 gen_addr_add(ctx, EA, EA, 8);
2656 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2657 tcg_temp_free(EA);
2658 #endif
2659 }
2660 #endif
2661
2662 /*** Integer store ***/
2663 #define GEN_ST(name, stop, opc, type) \
2664 static void glue(gen_, name)(DisasContext *ctx) \
2665 { \
2666 TCGv EA; \
2667 gen_set_access_type(ctx, ACCESS_INT); \
2668 EA = tcg_temp_new(); \
2669 gen_addr_imm_index(ctx, EA, 0); \
2670 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2671 tcg_temp_free(EA); \
2672 }
2673
2674 #define GEN_STU(name, stop, opc, type) \
2675 static void glue(gen_, stop##u)(DisasContext *ctx) \
2676 { \
2677 TCGv EA; \
2678 if (unlikely(rA(ctx->opcode) == 0)) { \
2679 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2680 return; \
2681 } \
2682 gen_set_access_type(ctx, ACCESS_INT); \
2683 EA = tcg_temp_new(); \
2684 if (type == PPC_64B) \
2685 gen_addr_imm_index(ctx, EA, 0x03); \
2686 else \
2687 gen_addr_imm_index(ctx, EA, 0); \
2688 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2689 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2690 tcg_temp_free(EA); \
2691 }
2692
2693 #define GEN_STUX(name, stop, opc2, opc3, type) \
2694 static void glue(gen_, name##ux)(DisasContext *ctx) \
2695 { \
2696 TCGv EA; \
2697 if (unlikely(rA(ctx->opcode) == 0)) { \
2698 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2699 return; \
2700 } \
2701 gen_set_access_type(ctx, ACCESS_INT); \
2702 EA = tcg_temp_new(); \
2703 gen_addr_reg_index(ctx, EA); \
2704 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2705 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2706 tcg_temp_free(EA); \
2707 }
2708
2709 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2710 static void glue(gen_, name##x)(DisasContext *ctx) \
2711 { \
2712 TCGv EA; \
2713 gen_set_access_type(ctx, ACCESS_INT); \
2714 EA = tcg_temp_new(); \
2715 gen_addr_reg_index(ctx, EA); \
2716 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2717 tcg_temp_free(EA); \
2718 }
2719 #define GEN_STX(name, stop, opc2, opc3, type) \
2720 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2721
2722 #define GEN_STS(name, stop, op, type) \
2723 GEN_ST(name, stop, op | 0x20, type); \
2724 GEN_STU(name, stop, op | 0x21, type); \
2725 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2726 GEN_STX(name, stop, 0x17, op | 0x00, type)
2727
2728 /* stb stbu stbux stbx */
2729 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2730 /* sth sthu sthux sthx */
2731 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2732 /* stw stwu stwux stwx */
2733 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2734 #if defined(TARGET_PPC64)
2735 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2736 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2737
2738 static void gen_std(DisasContext *ctx)
2739 {
2740 int rs;
2741 TCGv EA;
2742
2743 rs = rS(ctx->opcode);
2744 if ((ctx->opcode & 0x3) == 0x2) {
2745 #if defined(CONFIG_USER_ONLY)
2746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2747 #else
2748 /* stq */
2749 if (unlikely(ctx->mem_idx == 0)) {
2750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2751 return;
2752 }
2753 if (unlikely(rs & 1)) {
2754 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2755 return;
2756 }
2757 if (unlikely(ctx->le_mode)) {
2758 /* Little-endian mode is not handled */
2759 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2760 return;
2761 }
2762 gen_set_access_type(ctx, ACCESS_INT);
2763 EA = tcg_temp_new();
2764 gen_addr_imm_index(ctx, EA, 0x03);
2765 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2766 gen_addr_add(ctx, EA, EA, 8);
2767 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2768 tcg_temp_free(EA);
2769 #endif
2770 } else {
2771 /* std / stdu */
2772 if (Rc(ctx->opcode)) {
2773 if (unlikely(rA(ctx->opcode) == 0)) {
2774 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2775 return;
2776 }
2777 }
2778 gen_set_access_type(ctx, ACCESS_INT);
2779 EA = tcg_temp_new();
2780 gen_addr_imm_index(ctx, EA, 0x03);
2781 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2782 if (Rc(ctx->opcode))
2783 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2784 tcg_temp_free(EA);
2785 }
2786 }
2787 #endif
2788 /*** Integer load and store with byte reverse ***/
2789 /* lhbrx */
2790 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2791 {
2792 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2793 if (likely(!ctx->le_mode)) {
2794 tcg_gen_bswap16_tl(arg1, arg1);
2795 }
2796 }
2797 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2798
2799 /* lwbrx */
2800 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2801 {
2802 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2803 if (likely(!ctx->le_mode)) {
2804 tcg_gen_bswap32_tl(arg1, arg1);
2805 }
2806 }
2807 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2808
2809 #if defined(TARGET_PPC64)
2810 /* ldbrx */
2811 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2812 {
2813 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2814 if (likely(!ctx->le_mode)) {
2815 tcg_gen_bswap64_tl(arg1, arg1);
2816 }
2817 }
2818 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2819 #endif /* TARGET_PPC64 */
2820
2821 /* sthbrx */
2822 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2823 {
2824 if (likely(!ctx->le_mode)) {
2825 TCGv t0 = tcg_temp_new();
2826 tcg_gen_ext16u_tl(t0, arg1);
2827 tcg_gen_bswap16_tl(t0, t0);
2828 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2829 tcg_temp_free(t0);
2830 } else {
2831 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2832 }
2833 }
2834 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2835
2836 /* stwbrx */
2837 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2838 {
2839 if (likely(!ctx->le_mode)) {
2840 TCGv t0 = tcg_temp_new();
2841 tcg_gen_ext32u_tl(t0, arg1);
2842 tcg_gen_bswap32_tl(t0, t0);
2843 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2844 tcg_temp_free(t0);
2845 } else {
2846 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2847 }
2848 }
2849 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2850
2851 #if defined(TARGET_PPC64)
2852 /* stdbrx */
2853 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2854 {
2855 if (likely(!ctx->le_mode)) {
2856 TCGv t0 = tcg_temp_new();
2857 tcg_gen_bswap64_tl(t0, arg1);
2858 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2859 tcg_temp_free(t0);
2860 } else {
2861 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2862 }
2863 }
2864 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2865 #endif /* TARGET_PPC64 */
2866
2867 /*** Integer load and store multiple ***/
2868
2869 /* lmw */
2870 static void gen_lmw(DisasContext *ctx)
2871 {
2872 TCGv t0;
2873 TCGv_i32 t1;
2874 gen_set_access_type(ctx, ACCESS_INT);
2875 /* NIP cannot be restored if the memory exception comes from an helper */
2876 gen_update_nip(ctx, ctx->nip - 4);
2877 t0 = tcg_temp_new();
2878 t1 = tcg_const_i32(rD(ctx->opcode));
2879 gen_addr_imm_index(ctx, t0, 0);
2880 gen_helper_lmw(cpu_env, t0, t1);
2881 tcg_temp_free(t0);
2882 tcg_temp_free_i32(t1);
2883 }
2884
2885 /* stmw */
2886 static void gen_stmw(DisasContext *ctx)
2887 {
2888 TCGv t0;
2889 TCGv_i32 t1;
2890 gen_set_access_type(ctx, ACCESS_INT);
2891 /* NIP cannot be restored if the memory exception comes from an helper */
2892 gen_update_nip(ctx, ctx->nip - 4);
2893 t0 = tcg_temp_new();
2894 t1 = tcg_const_i32(rS(ctx->opcode));
2895 gen_addr_imm_index(ctx, t0, 0);
2896 gen_helper_stmw(cpu_env, t0, t1);
2897 tcg_temp_free(t0);
2898 tcg_temp_free_i32(t1);
2899 }
2900
2901 /*** Integer load and store strings ***/
2902
2903 /* lswi */
2904 /* PowerPC32 specification says we must generate an exception if
2905 * rA is in the range of registers to be loaded.
2906 * In an other hand, IBM says this is valid, but rA won't be loaded.
2907 * For now, I'll follow the spec...
2908 */
2909 static void gen_lswi(DisasContext *ctx)
2910 {
2911 TCGv t0;
2912 TCGv_i32 t1, t2;
2913 int nb = NB(ctx->opcode);
2914 int start = rD(ctx->opcode);
2915 int ra = rA(ctx->opcode);
2916 int nr;
2917
2918 if (nb == 0)
2919 nb = 32;
2920 nr = nb / 4;
2921 if (unlikely(((start + nr) > 32 &&
2922 start <= ra && (start + nr - 32) > ra) ||
2923 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2924 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2925 return;
2926 }
2927 gen_set_access_type(ctx, ACCESS_INT);
2928 /* NIP cannot be restored if the memory exception comes from an helper */
2929 gen_update_nip(ctx, ctx->nip - 4);
2930 t0 = tcg_temp_new();
2931 gen_addr_register(ctx, t0);
2932 t1 = tcg_const_i32(nb);
2933 t2 = tcg_const_i32(start);
2934 gen_helper_lsw(cpu_env, t0, t1, t2);
2935 tcg_temp_free(t0);
2936 tcg_temp_free_i32(t1);
2937 tcg_temp_free_i32(t2);
2938 }
2939
2940 /* lswx */
2941 static void gen_lswx(DisasContext *ctx)
2942 {
2943 TCGv t0;
2944 TCGv_i32 t1, t2, t3;
2945 gen_set_access_type(ctx, ACCESS_INT);
2946 /* NIP cannot be restored if the memory exception comes from an helper */
2947 gen_update_nip(ctx, ctx->nip - 4);
2948 t0 = tcg_temp_new();
2949 gen_addr_reg_index(ctx, t0);
2950 t1 = tcg_const_i32(rD(ctx->opcode));
2951 t2 = tcg_const_i32(rA(ctx->opcode));
2952 t3 = tcg_const_i32(rB(ctx->opcode));
2953 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2954 tcg_temp_free(t0);
2955 tcg_temp_free_i32(t1);
2956 tcg_temp_free_i32(t2);
2957 tcg_temp_free_i32(t3);
2958 }
2959
2960 /* stswi */
2961 static void gen_stswi(DisasContext *ctx)
2962 {
2963 TCGv t0;
2964 TCGv_i32 t1, t2;
2965 int nb = NB(ctx->opcode);
2966 gen_set_access_type(ctx, ACCESS_INT);
2967 /* NIP cannot be restored if the memory exception comes from an helper */
2968 gen_update_nip(ctx, ctx->nip - 4);
2969 t0 = tcg_temp_new();
2970 gen_addr_register(ctx, t0);
2971 if (nb == 0)
2972 nb = 32;
2973 t1 = tcg_const_i32(nb);
2974 t2 = tcg_const_i32(rS(ctx->opcode));
2975 gen_helper_stsw(cpu_env, t0, t1, t2);
2976 tcg_temp_free(t0);
2977 tcg_temp_free_i32(t1);
2978 tcg_temp_free_i32(t2);
2979 }
2980
2981 /* stswx */
2982 static void gen_stswx(DisasContext *ctx)
2983 {
2984 TCGv t0;
2985 TCGv_i32 t1, t2;
2986 gen_set_access_type(ctx, ACCESS_INT);
2987 /* NIP cannot be restored if the memory exception comes from an helper */
2988 gen_update_nip(ctx, ctx->nip - 4);
2989 t0 = tcg_temp_new();
2990 gen_addr_reg_index(ctx, t0);
2991 t1 = tcg_temp_new_i32();
2992 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2993 tcg_gen_andi_i32(t1, t1, 0x7F);
2994 t2 = tcg_const_i32(rS(ctx->opcode));
2995 gen_helper_stsw(cpu_env, t0, t1, t2);
2996 tcg_temp_free(t0);
2997 tcg_temp_free_i32(t1);
2998 tcg_temp_free_i32(t2);
2999 }
3000
3001 /*** Memory synchronisation ***/
3002 /* eieio */
3003 static void gen_eieio(DisasContext *ctx)
3004 {
3005 }
3006
3007 /* isync */
3008 static void gen_isync(DisasContext *ctx)
3009 {
3010 gen_stop_exception(ctx);
3011 }
3012
3013 /* lwarx */
3014 static void gen_lwarx(DisasContext *ctx)
3015 {
3016 TCGv t0;
3017 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3018 gen_set_access_type(ctx, ACCESS_RES);
3019 t0 = tcg_temp_local_new();
3020 gen_addr_reg_index(ctx, t0);
3021 gen_check_align(ctx, t0, 0x03);
3022 gen_qemu_ld32u(ctx, gpr, t0);
3023 tcg_gen_mov_tl(cpu_reserve, t0);
3024 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3025 tcg_temp_free(t0);
3026 }
3027
3028 #if defined(CONFIG_USER_ONLY)
3029 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3030 int reg, int size)
3031 {
3032 TCGv t0 = tcg_temp_new();
3033 uint32_t save_exception = ctx->exception;
3034
3035 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3036 tcg_gen_movi_tl(t0, (size << 5) | reg);
3037 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3038 tcg_temp_free(t0);
3039 gen_update_nip(ctx, ctx->nip-4);
3040 ctx->exception = POWERPC_EXCP_BRANCH;
3041 gen_exception(ctx, POWERPC_EXCP_STCX);
3042 ctx->exception = save_exception;
3043 }
3044 #endif
3045
3046 /* stwcx. */
3047 static void gen_stwcx_(DisasContext *ctx)
3048 {
3049 TCGv t0;
3050 gen_set_access_type(ctx, ACCESS_RES);
3051 t0 = tcg_temp_local_new();
3052 gen_addr_reg_index(ctx, t0);
3053 gen_check_align(ctx, t0, 0x03);
3054 #if defined(CONFIG_USER_ONLY)
3055 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3056 #else
3057 {
3058 int l1;
3059
3060 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3061 l1 = gen_new_label();
3062 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3063 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3064 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3065 gen_set_label(l1);
3066 tcg_gen_movi_tl(cpu_reserve, -1);
3067 }
3068 #endif
3069 tcg_temp_free(t0);
3070 }
3071
3072 #if defined(TARGET_PPC64)
3073 /* ldarx */
3074 static void gen_ldarx(DisasContext *ctx)
3075 {
3076 TCGv t0;
3077 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3078 gen_set_access_type(ctx, ACCESS_RES);
3079 t0 = tcg_temp_local_new();
3080 gen_addr_reg_index(ctx, t0);
3081 gen_check_align(ctx, t0, 0x07);
3082 gen_qemu_ld64(ctx, gpr, t0);
3083 tcg_gen_mov_tl(cpu_reserve, t0);
3084 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3085 tcg_temp_free(t0);
3086 }
3087
3088 /* stdcx. */
3089 static void gen_stdcx_(DisasContext *ctx)
3090 {
3091 TCGv t0;
3092 gen_set_access_type(ctx, ACCESS_RES);
3093 t0 = tcg_temp_local_new();
3094 gen_addr_reg_index(ctx, t0);
3095 gen_check_align(ctx, t0, 0x07);
3096 #if defined(CONFIG_USER_ONLY)
3097 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3098 #else
3099 {
3100 int l1;
3101 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3102 l1 = gen_new_label();
3103 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3104 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3105 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3106 gen_set_label(l1);
3107 tcg_gen_movi_tl(cpu_reserve, -1);
3108 }
3109 #endif
3110 tcg_temp_free(t0);
3111 }
3112 #endif /* defined(TARGET_PPC64) */
3113
3114 /* sync */
3115 static void gen_sync(DisasContext *ctx)
3116 {
3117 }
3118
3119 /* wait */
3120 static void gen_wait(DisasContext *ctx)
3121 {
3122 TCGv_i32 t0 = tcg_temp_new_i32();
3123 tcg_gen_st_i32(t0, cpu_env,
3124 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3125 tcg_temp_free_i32(t0);
3126 /* Stop translation, as the CPU is supposed to sleep from now */
3127 gen_exception_err(ctx, EXCP_HLT, 1);
3128 }
3129
3130 /*** Floating-point load ***/
3131 #define GEN_LDF(name, ldop, opc, type) \
3132 static void glue(gen_, name)(DisasContext *ctx) \
3133 { \
3134 TCGv EA; \
3135 if (unlikely(!ctx->fpu_enabled)) { \
3136 gen_exception(ctx, POWERPC_EXCP_FPU); \
3137 return; \
3138 } \
3139 gen_set_access_type(ctx, ACCESS_FLOAT); \
3140 EA = tcg_temp_new(); \
3141 gen_addr_imm_index(ctx, EA, 0); \
3142 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3143 tcg_temp_free(EA); \
3144 }
3145
3146 #define GEN_LDUF(name, ldop, opc, type) \
3147 static void glue(gen_, name##u)(DisasContext *ctx) \
3148 { \
3149 TCGv EA; \
3150 if (unlikely(!ctx->fpu_enabled)) { \
3151 gen_exception(ctx, POWERPC_EXCP_FPU); \
3152 return; \
3153 } \
3154 if (unlikely(rA(ctx->opcode) == 0)) { \
3155 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3156 return; \
3157 } \
3158 gen_set_access_type(ctx, ACCESS_FLOAT); \
3159 EA = tcg_temp_new(); \
3160 gen_addr_imm_index(ctx, EA, 0); \
3161 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3162 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3163 tcg_temp_free(EA); \
3164 }
3165
3166 #define GEN_LDUXF(name, ldop, opc, type) \
3167 static void glue(gen_, name##ux)(DisasContext *ctx) \
3168 { \
3169 TCGv EA; \
3170 if (unlikely(!ctx->fpu_enabled)) { \
3171 gen_exception(ctx, POWERPC_EXCP_FPU); \
3172 return; \
3173 } \
3174 if (unlikely(rA(ctx->opcode) == 0)) { \
3175 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3176 return; \
3177 } \
3178 gen_set_access_type(ctx, ACCESS_FLOAT); \
3179 EA = tcg_temp_new(); \
3180 gen_addr_reg_index(ctx, EA); \
3181 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3182 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3183 tcg_temp_free(EA); \
3184 }
3185
3186 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3187 static void glue(gen_, name##x)(DisasContext *ctx) \
3188 { \
3189 TCGv EA; \
3190 if (unlikely(!ctx->fpu_enabled)) { \
3191 gen_exception(ctx, POWERPC_EXCP_FPU); \
3192 return; \
3193 } \
3194 gen_set_access_type(ctx, ACCESS_FLOAT); \
3195 EA = tcg_temp_new(); \
3196 gen_addr_reg_index(ctx, EA); \
3197 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3198 tcg_temp_free(EA); \
3199 }
3200
3201 #define GEN_LDFS(name, ldop, op, type) \
3202 GEN_LDF(name, ldop, op | 0x20, type); \
3203 GEN_LDUF(name, ldop, op | 0x21, type); \
3204 GEN_LDUXF(name, ldop, op | 0x01, type); \
3205 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3206
3207 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3208 {
3209 TCGv t0 = tcg_temp_new();
3210 TCGv_i32 t1 = tcg_temp_new_i32();
3211 gen_qemu_ld32u(ctx, t0, arg2);
3212 tcg_gen_trunc_tl_i32(t1, t0);
3213 tcg_temp_free(t0);
3214 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3215 tcg_temp_free_i32(t1);
3216 }
3217
3218 /* lfd lfdu lfdux lfdx */
3219 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3220 /* lfs lfsu lfsux lfsx */
3221 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3222
3223 /*** Floating-point store ***/
3224 #define GEN_STF(name, stop, opc, type) \
3225 static void glue(gen_, name)(DisasContext *ctx) \
3226 { \
3227 TCGv EA; \
3228 if (unlikely(!ctx->fpu_enabled)) { \
3229 gen_exception(ctx, POWERPC_EXCP_FPU); \
3230 return; \
3231 } \
3232 gen_set_access_type(ctx, ACCESS_FLOAT); \
3233 EA = tcg_temp_new(); \
3234 gen_addr_imm_index(ctx, EA, 0); \
3235 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3236 tcg_temp_free(EA); \
3237 }
3238
3239 #define GEN_STUF(name, stop, opc, type) \
3240 static void glue(gen_, name##u)(DisasContext *ctx) \
3241 { \
3242 TCGv EA; \
3243 if (unlikely(!ctx->fpu_enabled)) { \
3244 gen_exception(ctx, POWERPC_EXCP_FPU); \
3245 return; \
3246 } \
3247 if (unlikely(rA(ctx->opcode) == 0)) { \
3248 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3249 return; \
3250 } \
3251 gen_set_access_type(ctx, ACCESS_FLOAT); \
3252 EA = tcg_temp_new(); \
3253 gen_addr_imm_index(ctx, EA, 0); \
3254 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3255 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3256 tcg_temp_free(EA); \
3257 }
3258
3259 #define GEN_STUXF(name, stop, opc, type) \
3260 static void glue(gen_, name##ux)(DisasContext *ctx) \
3261 { \
3262 TCGv EA; \
3263 if (unlikely(!ctx->fpu_enabled)) { \
3264 gen_exception(ctx, POWERPC_EXCP_FPU); \
3265 return; \
3266 } \
3267 if (unlikely(rA(ctx->opcode) == 0)) { \
3268 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3269 return; \
3270 } \
3271 gen_set_access_type(ctx, ACCESS_FLOAT); \
3272 EA = tcg_temp_new(); \
3273 gen_addr_reg_index(ctx, EA); \
3274 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3275 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3276 tcg_temp_free(EA); \
3277 }
3278
3279 #define GEN_STXF(name, stop, opc2, opc3, type) \
3280 static void glue(gen_, name##x)(DisasContext *ctx) \
3281 { \
3282 TCGv EA; \
3283 if (unlikely(!ctx->fpu_enabled)) { \
3284 gen_exception(ctx, POWERPC_EXCP_FPU); \
3285 return; \
3286 } \
3287 gen_set_access_type(ctx, ACCESS_FLOAT); \
3288 EA = tcg_temp_new(); \
3289 gen_addr_reg_index(ctx, EA); \
3290 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3291 tcg_temp_free(EA); \
3292 }
3293
3294 #define GEN_STFS(name, stop, op, type) \
3295 GEN_STF(name, stop, op | 0x20, type); \
3296 GEN_STUF(name, stop, op | 0x21, type); \
3297 GEN_STUXF(name, stop, op | 0x01, type); \
3298 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3299
3300 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3301 {
3302 TCGv_i32 t0 = tcg_temp_new_i32();
3303 TCGv t1 = tcg_temp_new();
3304 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3305 tcg_gen_extu_i32_tl(t1, t0);
3306 tcg_temp_free_i32(t0);
3307 gen_qemu_st32(ctx, t1, arg2);
3308 tcg_temp_free(t1);
3309 }
3310
3311 /* stfd stfdu stfdux stfdx */
3312 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3313 /* stfs stfsu stfsux stfsx */
3314 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3315
3316 /* Optional: */
3317 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3318 {
3319 TCGv t0 = tcg_temp_new();
3320 tcg_gen_trunc_i64_tl(t0, arg1),
3321 gen_qemu_st32(ctx, t0, arg2);
3322 tcg_temp_free(t0);
3323 }
3324 /* stfiwx */
3325 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3326
3327 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3328 {
3329 #if defined(TARGET_PPC64)
3330 if (ctx->has_cfar)
3331 tcg_gen_movi_tl(cpu_cfar, nip);
3332 #endif
3333 }
3334
3335 /*** Branch ***/
3336 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3337 {
3338 TranslationBlock *tb;
3339 tb = ctx->tb;
3340 if (NARROW_MODE(ctx)) {
3341 dest = (uint32_t) dest;
3342 }
3343 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3344 likely(!ctx->singlestep_enabled)) {
3345 tcg_gen_goto_tb(n);
3346 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3347 tcg_gen_exit_tb((tcg_target_long)tb + n);
3348 } else {
3349 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3350 if (unlikely(ctx->singlestep_enabled)) {
3351 if ((ctx->singlestep_enabled &
3352 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3353 (ctx->exception == POWERPC_EXCP_BRANCH ||
3354 ctx->exception == POWERPC_EXCP_TRACE)) {
3355 target_ulong tmp = ctx->nip;
3356 ctx->nip = dest;
3357 gen_exception(ctx, POWERPC_EXCP_TRACE);
3358 ctx->nip = tmp;
3359 }
3360 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3361 gen_debug_exception(ctx);
3362 }
3363 }
3364 tcg_gen_exit_tb(0);
3365 }
3366 }
3367
3368 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3369 {
3370 if (NARROW_MODE(ctx)) {
3371 nip = (uint32_t)nip;
3372 }
3373 tcg_gen_movi_tl(cpu_lr, nip);
3374 }
3375
3376 /* b ba bl bla */
3377 static void gen_b(DisasContext *ctx)
3378 {
3379 target_ulong li, target;
3380
3381 ctx->exception = POWERPC_EXCP_BRANCH;
3382 /* sign extend LI */
3383 li = LI(ctx->opcode);
3384 li = (li ^ 0x02000000) - 0x02000000;
3385 if (likely(AA(ctx->opcode) == 0)) {
3386 target = ctx->nip + li - 4;
3387 } else {
3388 target = li;
3389 }
3390 if (LK(ctx->opcode)) {
3391 gen_setlr(ctx, ctx->nip);
3392 }
3393 gen_update_cfar(ctx, ctx->nip);
3394 gen_goto_tb(ctx, 0, target);
3395 }
3396
3397 #define BCOND_IM 0
3398 #define BCOND_LR 1
3399 #define BCOND_CTR 2
3400
3401 static inline void gen_bcond(DisasContext *ctx, int type)
3402 {
3403 uint32_t bo = BO(ctx->opcode);
3404 int l1;
3405 TCGv target;
3406
3407 ctx->exception = POWERPC_EXCP_BRANCH;
3408 if (type == BCOND_LR || type == BCOND_CTR) {
3409 target = tcg_temp_local_new();
3410 if (type == BCOND_CTR)
3411 tcg_gen_mov_tl(target, cpu_ctr);
3412 else
3413 tcg_gen_mov_tl(target, cpu_lr);
3414 } else {
3415 TCGV_UNUSED(target);
3416 }
3417 if (LK(ctx->opcode))
3418 gen_setlr(ctx, ctx->nip);
3419 l1 = gen_new_label();
3420 if ((bo & 0x4) == 0) {
3421 /* Decrement and test CTR */
3422 TCGv temp = tcg_temp_new();
3423 if (unlikely(type == BCOND_CTR)) {
3424 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3425 return;
3426 }
3427 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3428 if (NARROW_MODE(ctx)) {
3429 tcg_gen_ext32u_tl(temp, cpu_ctr);
3430 } else {
3431 tcg_gen_mov_tl(temp, cpu_ctr);
3432 }
3433 if (bo & 0x2) {
3434 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3435 } else {
3436 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3437 }
3438 tcg_temp_free(temp);
3439 }
3440 if ((bo & 0x10) == 0) {
3441 /* Test CR */
3442 uint32_t bi = BI(ctx->opcode);
3443 uint32_t mask = 1 << (3 - (bi & 0x03));
3444 TCGv_i32 temp = tcg_temp_new_i32();
3445
3446 if (bo & 0x8) {
3447 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3448 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3449 } else {
3450 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3451 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3452 }
3453 tcg_temp_free_i32(temp);
3454 }
3455 gen_update_cfar(ctx, ctx->nip);
3456 if (type == BCOND_IM) {
3457 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3458 if (likely(AA(ctx->opcode) == 0)) {
3459 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3460 } else {
3461 gen_goto_tb(ctx, 0, li);
3462 }
3463 gen_set_label(l1);
3464 gen_goto_tb(ctx, 1, ctx->nip);
3465 } else {
3466 if (NARROW_MODE(ctx)) {
3467 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3468 } else {
3469 tcg_gen_andi_tl(cpu_nip, target, ~3);
3470 }
3471 tcg_gen_exit_tb(0);
3472 gen_set_label(l1);
3473 gen_update_nip(ctx, ctx->nip);
3474 tcg_gen_exit_tb(0);
3475 }
3476 }
3477
3478 static void gen_bc(DisasContext *ctx)
3479 {
3480 gen_bcond(ctx, BCOND_IM);
3481 }
3482
3483 static void gen_bcctr(DisasContext *ctx)
3484 {
3485 gen_bcond(ctx, BCOND_CTR);
3486 }
3487
3488 static void gen_bclr(DisasContext *ctx)
3489 {
3490 gen_bcond(ctx, BCOND_LR);
3491 }
3492
3493 /*** Condition register logical ***/
3494 #define GEN_CRLOGIC(name, tcg_op, opc) \
3495 static void glue(gen_, name)(DisasContext *ctx) \
3496 { \
3497 uint8_t bitmask; \
3498 int sh; \
3499 TCGv_i32 t0, t1; \
3500 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3501 t0 = tcg_temp_new_i32(); \
3502 if (sh > 0) \
3503 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3504 else if (sh < 0) \
3505 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3506 else \
3507 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3508 t1 = tcg_temp_new_i32(); \
3509 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3510 if (sh > 0) \
3511 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3512 else if (sh < 0) \
3513 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3514 else \
3515 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3516 tcg_op(t0, t0, t1); \
3517 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3518 tcg_gen_andi_i32(t0, t0, bitmask); \
3519 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3520 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3521 tcg_temp_free_i32(t0); \
3522 tcg_temp_free_i32(t1); \
3523 }
3524
3525 /* crand */
3526 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3527 /* crandc */
3528 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3529 /* creqv */
3530 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3531 /* crnand */
3532 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3533 /* crnor */
3534 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3535 /* cror */
3536 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3537 /* crorc */
3538 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3539 /* crxor */
3540 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3541
3542 /* mcrf */
3543 static void gen_mcrf(DisasContext *ctx)
3544 {
3545 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3546 }
3547
3548 /*** System linkage ***/
3549
3550 /* rfi (mem_idx only) */
3551 static void gen_rfi(DisasContext *ctx)
3552 {
3553 #if defined(CONFIG_USER_ONLY)
3554 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3555 #else
3556 /* Restore CPU state */
3557 if (unlikely(!ctx->mem_idx)) {
3558 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3559 return;
3560 }
3561 gen_update_cfar(ctx, ctx->nip);
3562 gen_helper_rfi(cpu_env);
3563 gen_sync_exception(ctx);
3564 #endif
3565 }
3566
3567 #if defined(TARGET_PPC64)
3568 static void gen_rfid(DisasContext *ctx)
3569 {
3570 #if defined(CONFIG_USER_ONLY)
3571 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3572 #else
3573 /* Restore CPU state */
3574 if (unlikely(!ctx->mem_idx)) {
3575 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3576 return;
3577 }
3578 gen_update_cfar(ctx, ctx->nip);
3579 gen_helper_rfid(cpu_env);
3580 gen_sync_exception(ctx);
3581 #endif
3582 }
3583
3584 static void gen_hrfid(DisasContext *ctx)
3585 {
3586 #if defined(CONFIG_USER_ONLY)
3587 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3588 #else
3589 /* Restore CPU state */
3590 if (unlikely(ctx->mem_idx <= 1)) {
3591 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3592 return;
3593 }
3594 gen_helper_hrfid(cpu_env);
3595 gen_sync_exception(ctx);
3596 #endif
3597 }
3598 #endif
3599
3600 /* sc */
3601 #if defined(CONFIG_USER_ONLY)
3602 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3603 #else
3604 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3605 #endif
3606 static void gen_sc(DisasContext *ctx)
3607 {
3608 uint32_t lev;
3609
3610 lev = (ctx->opcode >> 5) & 0x7F;
3611 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3612 }
3613
3614 /*** Trap ***/
3615
3616 /* tw */
3617 static void gen_tw(DisasContext *ctx)
3618 {
3619 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3620 /* Update the nip since this might generate a trap exception */
3621 gen_update_nip(ctx, ctx->nip);
3622 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3623 t0);
3624 tcg_temp_free_i32(t0);
3625 }
3626
3627 /* twi */
3628 static void gen_twi(DisasContext *ctx)
3629 {
3630 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3631 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3632 /* Update the nip since this might generate a trap exception */
3633 gen_update_nip(ctx, ctx->nip);
3634 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3635 tcg_temp_free(t0);
3636 tcg_temp_free_i32(t1);
3637 }
3638
3639 #if defined(TARGET_PPC64)
3640 /* td */
3641 static void gen_td(DisasContext *ctx)
3642 {
3643 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3644 /* Update the nip since this might generate a trap exception */
3645 gen_update_nip(ctx, ctx->nip);
3646 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3647 t0);
3648 tcg_temp_free_i32(t0);
3649 }
3650
3651 /* tdi */
3652 static void gen_tdi(DisasContext *ctx)
3653 {
3654 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3655 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3656 /* Update the nip since this might generate a trap exception */
3657 gen_update_nip(ctx, ctx->nip);
3658 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3659 tcg_temp_free(t0);
3660 tcg_temp_free_i32(t1);
3661 }
3662 #endif
3663
3664 /*** Processor control ***/
3665
3666 static void gen_read_xer(TCGv dst)
3667 {
3668 TCGv t0 = tcg_temp_new();
3669 TCGv t1 = tcg_temp_new();
3670 TCGv t2 = tcg_temp_new();
3671 tcg_gen_mov_tl(dst, cpu_xer);
3672 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3673 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3674 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3675 tcg_gen_or_tl(t0, t0, t1);
3676 tcg_gen_or_tl(dst, dst, t2);
3677 tcg_gen_or_tl(dst, dst, t0);
3678 tcg_temp_free(t0);
3679 tcg_temp_free(t1);
3680 tcg_temp_free(t2);
3681 }
3682
3683 static void gen_write_xer(TCGv src)
3684 {
3685 tcg_gen_andi_tl(cpu_xer, src,
3686 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3687 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3688 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3689 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3690 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3691 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3692 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3693 }
3694
3695 /* mcrxr */
3696 static void gen_mcrxr(DisasContext *ctx)
3697 {
3698 TCGv_i32 t0 = tcg_temp_new_i32();
3699 TCGv_i32 t1 = tcg_temp_new_i32();
3700 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3701
3702 tcg_gen_trunc_tl_i32(t0, cpu_so);
3703 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3704 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3705 tcg_gen_shri_i32(t0, t0, 2);
3706 tcg_gen_shri_i32(t1, t1, 1);
3707 tcg_gen_or_i32(dst, dst, t0);
3708 tcg_gen_or_i32(dst, dst, t1);
3709 tcg_temp_free_i32(t0);
3710 tcg_temp_free_i32(t1);
3711
3712 tcg_gen_movi_tl(cpu_so, 0);
3713 tcg_gen_movi_tl(cpu_ov, 0);
3714 tcg_gen_movi_tl(cpu_ca, 0);
3715 }
3716
3717 /* mfcr mfocrf */
3718 static void gen_mfcr(DisasContext *ctx)
3719 {
3720 uint32_t crm, crn;
3721
3722 if (likely(ctx->opcode & 0x00100000)) {
3723 crm = CRM(ctx->opcode);
3724 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3725 crn = ctz32 (crm);
3726 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3727 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3728 cpu_gpr[rD(ctx->opcode)], crn * 4);
3729 }
3730 } else {
3731 TCGv_i32 t0 = tcg_temp_new_i32();
3732 tcg_gen_mov_i32(t0, cpu_crf[0]);
3733 tcg_gen_shli_i32(t0, t0, 4);
3734 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3735 tcg_gen_shli_i32(t0, t0, 4);
3736 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3737 tcg_gen_shli_i32(t0, t0, 4);
3738 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3739 tcg_gen_shli_i32(t0, t0, 4);
3740 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3741 tcg_gen_shli_i32(t0, t0, 4);
3742 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3743 tcg_gen_shli_i32(t0, t0, 4);
3744 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3745 tcg_gen_shli_i32(t0, t0, 4);
3746 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3747 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3748 tcg_temp_free_i32(t0);
3749 }
3750 }
3751
3752 /* mfmsr */
3753 static void gen_mfmsr(DisasContext *ctx)
3754 {
3755 #if defined(CONFIG_USER_ONLY)
3756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3757 #else
3758 if (unlikely(!ctx->mem_idx)) {
3759 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3760 return;
3761 }
3762 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3763 #endif
3764 }
3765
3766 static void spr_noaccess(void *opaque, int gprn, int sprn)
3767 {
3768 #if 0
3769 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3770 printf("ERROR: try to access SPR %d !\n", sprn);
3771 #endif
3772 }
3773 #define SPR_NOACCESS (&spr_noaccess)
3774
3775 /* mfspr */
3776 static inline void gen_op_mfspr(DisasContext *ctx)
3777 {
3778 void (*read_cb)(void *opaque, int gprn, int sprn);
3779 uint32_t sprn = SPR(ctx->opcode);
3780
3781 #if !defined(CONFIG_USER_ONLY)
3782 if (ctx->mem_idx == 2)
3783 read_cb = ctx->spr_cb[sprn].hea_read;
3784 else if (ctx->mem_idx)
3785 read_cb = ctx->spr_cb[sprn].oea_read;
3786 else
3787 #endif
3788 read_cb = ctx->spr_cb[sprn].uea_read;
3789 if (likely(read_cb != NULL)) {
3790 if (likely(read_cb != SPR_NOACCESS)) {
3791 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3792 } else {
3793 /* Privilege exception */
3794 /* This is a hack to avoid warnings when running Linux:
3795 * this OS breaks the PowerPC virtualisation model,
3796 * allowing userland application to read the PVR
3797 */
3798 if (sprn != SPR_PVR) {
3799 qemu_log("Trying to read privileged spr %d %03x at "
3800 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3801 printf("Trying to read privileged spr %d %03x at "
3802 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3803 }
3804 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3805 }
3806 } else {
3807 /* Not defined */
3808 qemu_log("Trying to read invalid spr %d %03x at "
3809 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3810 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3811 sprn, sprn, ctx->nip);
3812 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3813 }
3814 }
3815
3816 static void gen_mfspr(DisasContext *ctx)
3817 {
3818 gen_op_mfspr(ctx);
3819 }
3820
3821 /* mftb */
3822 static void gen_mftb(DisasContext *ctx)
3823 {
3824 gen_op_mfspr(ctx);
3825 }
3826
3827 /* mtcrf mtocrf*/
3828 static void gen_mtcrf(DisasContext *ctx)
3829 {
3830 uint32_t crm, crn;
3831
3832 crm = CRM(ctx->opcode);
3833 if (likely((ctx->opcode & 0x00100000))) {
3834 if (crm && ((crm & (crm - 1)) == 0)) {
3835 TCGv_i32 temp = tcg_temp_new_i32();
3836 crn = ctz32 (crm);
3837 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3838 tcg_gen_shri_i32(temp, temp, crn * 4);
3839 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3840 tcg_temp_free_i32(temp);
3841 }
3842 } else {
3843 TCGv_i32 temp = tcg_temp_new_i32();
3844 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3845 for (crn = 0 ; crn < 8 ; crn++) {
3846 if (crm & (1 << crn)) {
3847 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3848 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3849 }
3850 }
3851 tcg_temp_free_i32(temp);
3852 }
3853 }
3854
3855 /* mtmsr */
3856 #if defined(TARGET_PPC64)
3857 static void gen_mtmsrd(DisasContext *ctx)
3858 {
3859 #if defined(CONFIG_USER_ONLY)
3860 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3861 #else
3862 if (unlikely(!ctx->mem_idx)) {
3863 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3864 return;
3865 }
3866 if (ctx->opcode & 0x00010000) {
3867 /* Special form that does not need any synchronisation */
3868 TCGv t0 = tcg_temp_new();
3869 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3870 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3871 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3872 tcg_temp_free(t0);
3873 } else {
3874 /* XXX: we need to update nip before the store
3875 * if we enter power saving mode, we will exit the loop
3876 * directly from ppc_store_msr
3877 */
3878 gen_update_nip(ctx, ctx->nip);
3879 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3880 /* Must stop the translation as machine state (may have) changed */
3881 /* Note that mtmsr is not always defined as context-synchronizing */
3882 gen_stop_exception(ctx);
3883 }
3884 #endif
3885 }
3886 #endif
3887
3888 static void gen_mtmsr(DisasContext *ctx)
3889 {
3890 #if defined(CONFIG_USER_ONLY)
3891 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3892 #else
3893 if (unlikely(!ctx->mem_idx)) {
3894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3895 return;
3896 }
3897 if (ctx->opcode & 0x00010000) {
3898 /* Special form that does not need any synchronisation */
3899 TCGv t0 = tcg_temp_new();
3900 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3901 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3902 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3903 tcg_temp_free(t0);
3904 } else {
3905 TCGv msr = tcg_temp_new();
3906
3907 /* XXX: we need to update nip before the store
3908 * if we enter power saving mode, we will exit the loop
3909 * directly from ppc_store_msr
3910 */
3911 gen_update_nip(ctx, ctx->nip);
3912 #if defined(TARGET_PPC64)
3913 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3914 #else
3915 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3916 #endif
3917 gen_helper_store_msr(cpu_env, msr);
3918 /* Must stop the translation as machine state (may have) changed */
3919 /* Note that mtmsr is not always defined as context-synchronizing */
3920 gen_stop_exception(ctx);
3921 }
3922 #endif
3923 }
3924
3925 /* mtspr */
3926 static void gen_mtspr(DisasContext *ctx)
3927 {
3928 void (*write_cb)(void *opaque, int sprn, int gprn);
3929 uint32_t sprn = SPR(ctx->opcode);
3930
3931 #if !defined(CONFIG_USER_ONLY)
3932 if (ctx->mem_idx == 2)
3933 write_cb = ctx->spr_cb[sprn].hea_write;
3934 else if (ctx->mem_idx)
3935 write_cb = ctx->spr_cb[sprn].oea_write;
3936 else
3937 #endif
3938 write_cb = ctx->spr_cb[sprn].uea_write;
3939 if (likely(write_cb != NULL)) {
3940 if (likely(write_cb != SPR_NOACCESS)) {
3941 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3942 } else {
3943 /* Privilege exception */
3944 qemu_log("Trying to write privileged spr %d %03x at "
3945 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3946 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3947 "\n", sprn, sprn, ctx->nip);
3948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3949 }
3950 } else {
3951 /* Not defined */
3952 qemu_log("Trying to write invalid spr %d %03x at "
3953 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3954 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3955 sprn, sprn, ctx->nip);
3956 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3957 }
3958 }
3959
3960 /*** Cache management ***/
3961
3962 /* dcbf */
3963 static void gen_dcbf(DisasContext *ctx)
3964 {
3965 /* XXX: specification says this is treated as a load by the MMU */
3966 TCGv t0;
3967 gen_set_access_type(ctx, ACCESS_CACHE);
3968 t0 = tcg_temp_new();
3969 gen_addr_reg_index(ctx, t0);
3970 gen_qemu_ld8u(ctx, t0, t0);
3971 tcg_temp_free(t0);
3972 }
3973
3974 /* dcbi (Supervisor only) */
3975 static void gen_dcbi(DisasContext *ctx)
3976 {
3977 #if defined(CONFIG_USER_ONLY)
3978 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3979 #else
3980 TCGv EA, val;
3981 if (unlikely(!ctx->mem_idx)) {
3982 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3983 return;
3984 }
3985 EA = tcg_temp_new();
3986 gen_set_access_type(ctx, ACCESS_CACHE);
3987 gen_addr_reg_index(ctx, EA);
3988 val = tcg_temp_new();
3989 /* XXX: specification says this should be treated as a store by the MMU */
3990 gen_qemu_ld8u(ctx, val, EA);
3991 gen_qemu_st8(ctx, val, EA);
3992 tcg_temp_free(val);
3993 tcg_temp_free(EA);
3994 #endif
3995 }
3996
3997 /* dcdst */
3998 static void gen_dcbst(DisasContext *ctx)
3999 {
4000 /* XXX: specification say this is treated as a load by the MMU */
4001 TCGv t0;
4002 gen_set_access_type(ctx, ACCESS_CACHE);
4003 t0 = tcg_temp_new();
4004 gen_addr_reg_index(ctx, t0);
4005 gen_qemu_ld8u(ctx, t0, t0);
4006 tcg_temp_free(t0);
4007 }
4008
4009 /* dcbt */
4010 static void gen_dcbt(DisasContext *ctx)
4011 {
4012 /* interpreted as no-op */
4013 /* XXX: specification say this is treated as a load by the MMU
4014 * but does not generate any exception
4015 */
4016 }
4017
4018 /* dcbtst */
4019 static void gen_dcbtst(DisasContext *ctx)
4020 {
4021 /* interpreted as no-op */
4022 /* XXX: specification say this is treated as a load by the MMU
4023 * but does not generate any exception
4024 */
4025 }
4026
4027 /* dcbz */
4028 static void gen_dcbz(DisasContext *ctx)
4029 {
4030 TCGv tcgv_addr;
4031 TCGv_i32 tcgv_is_dcbzl;
4032 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4033
4034 gen_set_access_type(ctx, ACCESS_CACHE);
4035 /* NIP cannot be restored if the memory exception comes from an helper */
4036 gen_update_nip(ctx, ctx->nip - 4);
4037 tcgv_addr = tcg_temp_new();
4038 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4039
4040 gen_addr_reg_index(ctx, tcgv_addr);
4041 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4042
4043 tcg_temp_free(tcgv_addr);
4044 tcg_temp_free_i32(tcgv_is_dcbzl);
4045 }
4046
4047 /* dst / dstt */
4048 static void gen_dst(DisasContext *ctx)
4049 {
4050 if (rA(ctx->opcode) == 0) {
4051 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4052 } else {
4053 /* interpreted as no-op */
4054 }
4055 }
4056
4057 /* dstst /dststt */
4058 static void gen_dstst(DisasContext *ctx)
4059 {
4060 if (rA(ctx->opcode) == 0) {
4061 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4062 } else {
4063 /* interpreted as no-op */
4064 }
4065
4066 }
4067
4068 /* dss / dssall */
4069 static void gen_dss(DisasContext *ctx)
4070 {
4071 /* interpreted as no-op */
4072 }
4073
4074 /* icbi */
4075 static void gen_icbi(DisasContext *ctx)
4076 {
4077 TCGv t0;
4078 gen_set_access_type(ctx, ACCESS_CACHE);
4079 /* NIP cannot be restored if the memory exception comes from an helper */
4080 gen_update_nip(ctx, ctx->nip - 4);
4081 t0 = tcg_temp_new();
4082 gen_addr_reg_index(ctx, t0);
4083 gen_helper_icbi(cpu_env, t0);
4084 tcg_temp_free(t0);
4085 }
4086
4087 /* Optional: */
4088 /* dcba */
4089 static void gen_dcba(DisasContext *ctx)
4090 {
4091 /* interpreted as no-op */
4092 /* XXX: specification say this is treated as a store by the MMU
4093 * but does not generate any exception
4094 */
4095 }
4096
4097 /*** Segment register manipulation ***/
4098 /* Supervisor only: */
4099
4100 /* mfsr */
4101 static void gen_mfsr(DisasContext *ctx)
4102 {
4103 #if defined(CONFIG_USER_ONLY)
4104 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4105 #else
4106 TCGv t0;
4107 if (unlikely(!ctx->mem_idx)) {
4108 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4109 return;
4110 }
4111 t0 = tcg_const_tl(SR(ctx->opcode));
4112 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4113 tcg_temp_free(t0);
4114 #endif
4115 }
4116
4117 /* mfsrin */
4118 static void gen_mfsrin(DisasContext *ctx)
4119 {
4120 #if defined(CONFIG_USER_ONLY)
4121 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4122 #else
4123 TCGv t0;
4124 if (unlikely(!ctx->mem_idx)) {
4125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4126 return;
4127 }
4128 t0 = tcg_temp_new();
4129 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4130 tcg_gen_andi_tl(t0, t0, 0xF);
4131 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4132 tcg_temp_free(t0);
4133 #endif
4134 }
4135
4136 /* mtsr */
4137 static void gen_mtsr(DisasContext *ctx)
4138 {
4139 #if defined(CONFIG_USER_ONLY)
4140 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4141 #else
4142 TCGv t0;
4143 if (unlikely(!ctx->mem_idx)) {
4144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4145 return;
4146 }
4147 t0 = tcg_const_tl(SR(ctx->opcode));
4148 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4149 tcg_temp_free(t0);
4150 #endif
4151 }
4152
4153 /* mtsrin */
4154 static void gen_mtsrin(DisasContext *ctx)
4155 {
4156 #if defined(CONFIG_USER_ONLY)
4157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4158 #else
4159 TCGv t0;
4160 if (unlikely(!ctx->mem_idx)) {
4161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4162 return;
4163 }
4164 t0 = tcg_temp_new();
4165 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4166 tcg_gen_andi_tl(t0, t0, 0xF);
4167 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4168 tcg_temp_free(t0);
4169 #endif
4170 }
4171
4172 #if defined(TARGET_PPC64)
4173 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4174
4175 /* mfsr */
4176 static void gen_mfsr_64b(DisasContext *ctx)
4177 {
4178 #if defined(CONFIG_USER_ONLY)
4179 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4180 #else
4181 TCGv t0;
4182 if (unlikely(!ctx->mem_idx)) {
4183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4184 return;
4185 }
4186 t0 = tcg_const_tl(SR(ctx->opcode));
4187 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4188 tcg_temp_free(t0);
4189 #endif
4190 }
4191
4192 /* mfsrin */
4193 static void gen_mfsrin_64b(DisasContext *ctx)
4194 {
4195 #if defined(CONFIG_USER_ONLY)
4196 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4197 #else
4198 TCGv t0;
4199 if (unlikely(!ctx->mem_idx)) {
4200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4201 return;
4202 }
4203 t0 = tcg_temp_new();
4204 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4205 tcg_gen_andi_tl(t0, t0, 0xF);
4206 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4207 tcg_temp_free(t0);
4208 #endif
4209 }
4210
4211 /* mtsr */
4212 static void gen_mtsr_64b(DisasContext *ctx)
4213 {
4214 #if defined(CONFIG_USER_ONLY)
4215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4216 #else
4217 TCGv t0;
4218 if (unlikely(!ctx->mem_idx)) {
4219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4220 return;
4221 }
4222 t0 = tcg_const_tl(SR(ctx->opcode));
4223 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4224 tcg_temp_free(t0);
4225 #endif
4226 }
4227
4228 /* mtsrin */
4229 static void gen_mtsrin_64b(DisasContext *ctx)
4230 {
4231 #if defined(CONFIG_USER_ONLY)
4232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4233 #else
4234 TCGv t0;
4235 if (unlikely(!ctx->mem_idx)) {
4236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4237 return;
4238 }
4239 t0 = tcg_temp_new();
4240 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4241 tcg_gen_andi_tl(t0, t0, 0xF);
4242 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4243 tcg_temp_free(t0);
4244 #endif
4245 }
4246
4247 /* slbmte */
4248 static void gen_slbmte(DisasContext *ctx)
4249 {
4250 #if defined(CONFIG_USER_ONLY)
4251 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4252 #else
4253 if (unlikely(!ctx->mem_idx)) {
4254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4255 return;
4256 }
4257 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4258 cpu_gpr[rS(ctx->opcode)]);
4259 #endif
4260 }
4261
4262 static void gen_slbmfee(DisasContext *ctx)
4263 {
4264 #if defined(CONFIG_USER_ONLY)
4265 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4266 #else
4267 if (unlikely(!ctx->mem_idx)) {
4268 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4269 return;
4270 }
4271 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4272 cpu_gpr[rB(ctx->opcode)]);
4273 #endif
4274 }
4275
4276 static void gen_slbmfev(DisasContext *ctx)
4277 {
4278 #if defined(CONFIG_USER_ONLY)
4279 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4280 #else
4281 if (unlikely(!ctx->mem_idx)) {
4282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4283 return;
4284 }
4285 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4286 cpu_gpr[rB(ctx->opcode)]);
4287 #endif
4288 }
4289 #endif /* defined(TARGET_PPC64) */
4290
4291 /*** Lookaside buffer management ***/
4292 /* Optional & mem_idx only: */
4293
4294 /* tlbia */
4295 static void gen_tlbia(DisasContext *ctx)
4296 {
4297 #if defined(CONFIG_USER_ONLY)
4298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4299 #else
4300 if (unlikely(!ctx->mem_idx)) {
4301 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4302 return;
4303 }
4304 gen_helper_tlbia(cpu_env);
4305 #endif
4306 }
4307
4308 /* tlbiel */
4309 static void gen_tlbiel(DisasContext *ctx)
4310 {
4311 #if defined(CONFIG_USER_ONLY)
4312 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4313 #else
4314 if (unlikely(!ctx->mem_idx)) {
4315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4316 return;
4317 }
4318 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4319 #endif
4320 }
4321
4322 /* tlbie */
4323 static void gen_tlbie(DisasContext *ctx)
4324 {
4325 #if defined(CONFIG_USER_ONLY)
4326 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4327 #else
4328 if (unlikely(!ctx->mem_idx)) {
4329 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4330 return;
4331 }
4332 if (NARROW_MODE(ctx)) {
4333 TCGv t0 = tcg_temp_new();
4334 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4335 gen_helper_tlbie(cpu_env, t0);
4336 tcg_temp_free(t0);
4337 } else {
4338 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4339 }
4340 #endif
4341 }
4342
4343 /* tlbsync */
4344 static void gen_tlbsync(DisasContext *ctx)
4345 {
4346 #if defined(CONFIG_USER_ONLY)
4347 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4348 #else
4349 if (unlikely(!ctx->mem_idx)) {
4350 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4351 return;
4352 }
4353 /* This has no effect: it should ensure that all previous
4354 * tlbie have completed
4355 */
4356 gen_stop_exception(ctx);
4357 #endif
4358 }
4359
4360 #if defined(TARGET_PPC64)
4361 /* slbia */
4362 static void gen_slbia(DisasContext *ctx)
4363 {
4364 #if defined(CONFIG_USER_ONLY)
4365 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4366 #else
4367 if (unlikely(!ctx->mem_idx)) {
4368 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4369 return;
4370 }
4371 gen_helper_slbia(cpu_env);
4372 #endif
4373 }
4374
4375 /* slbie */
4376 static void gen_slbie(DisasContext *ctx)
4377 {
4378 #if defined(CONFIG_USER_ONLY)
4379 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4380 #else
4381 if (unlikely(!ctx->mem_idx)) {
4382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4383 return;
4384 }
4385 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4386 #endif
4387 }
4388 #endif
4389
4390 /*** External control ***/
4391 /* Optional: */
4392
4393 /* eciwx */
4394 static void gen_eciwx(DisasContext *ctx)
4395 {
4396 TCGv t0;
4397 /* Should check EAR[E] ! */
4398 gen_set_access_type(ctx, ACCESS_EXT);
4399 t0 = tcg_temp_new();
4400 gen_addr_reg_index(ctx, t0);
4401 gen_check_align(ctx, t0, 0x03);
4402 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4403 tcg_temp_free(t0);
4404 }
4405
4406 /* ecowx */
4407 static void gen_ecowx(DisasContext *ctx)
4408 {
4409 TCGv t0;
4410 /* Should check EAR[E] ! */
4411 gen_set_access_type(ctx, ACCESS_EXT);
4412 t0 = tcg_temp_new();
4413 gen_addr_reg_index(ctx, t0);
4414 gen_check_align(ctx, t0, 0x03);
4415 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4416 tcg_temp_free(t0);
4417 }
4418
4419 /* PowerPC 601 specific instructions */
4420
4421 /* abs - abs. */
4422 static void gen_abs(DisasContext *ctx)
4423 {
4424 int l1 = gen_new_label();
4425 int l2 = gen_new_label();
4426 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4427 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4428 tcg_gen_br(l2);
4429 gen_set_label(l1);
4430 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4431 gen_set_label(l2);
4432 if (unlikely(Rc(ctx->opcode) != 0))
4433 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4434 }
4435
4436 /* abso - abso. */
4437 static void gen_abso(DisasContext *ctx)
4438 {
4439 int l1 = gen_new_label();
4440 int l2 = gen_new_label();
4441 int l3 = gen_new_label();
4442 /* Start with XER OV disabled, the most likely case */
4443 tcg_gen_movi_tl(cpu_ov, 0);
4444 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4445 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4446 tcg_gen_movi_tl(cpu_ov, 1);
4447 tcg_gen_movi_tl(cpu_so, 1);
4448 tcg_gen_br(l2);
4449 gen_set_label(l1);
4450 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4451 tcg_gen_br(l3);
4452 gen_set_label(l2);
4453 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4454 gen_set_label(l3);
4455 if (unlikely(Rc(ctx->opcode) != 0))
4456 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4457 }
4458
4459 /* clcs */
4460 static void gen_clcs(DisasContext *ctx)
4461 {
4462 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4463 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4464 tcg_temp_free_i32(t0);
4465 /* Rc=1 sets CR0 to an undefined state */
4466 }
4467
4468 /* div - div. */
4469 static void gen_div(DisasContext *ctx)
4470 {
4471 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4472 cpu_gpr[rB(ctx->opcode)]);
4473 if (unlikely(Rc(ctx->opcode) != 0))
4474 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4475 }
4476
4477 /* divo - divo. */
4478 static void gen_divo(DisasContext *ctx)
4479 {
4480 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4481 cpu_gpr[rB(ctx->opcode)]);
4482 if (unlikely(Rc(ctx->opcode) != 0))
4483 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4484 }
4485
4486 /* divs - divs. */
4487 static void gen_divs(DisasContext *ctx)
4488 {
4489 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4490 cpu_gpr[rB(ctx->opcode)]);
4491 if (unlikely(Rc(ctx->opcode) != 0))
4492 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4493 }
4494
4495 /* divso - divso. */
4496 static void gen_divso(DisasContext *ctx)
4497 {
4498 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4499 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4500 if (unlikely(Rc(ctx->opcode) != 0))
4501 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4502 }
4503
4504 /* doz - doz. */
4505 static void gen_doz(DisasContext *ctx)
4506 {
4507 int l1 = gen_new_label();
4508 int l2 = gen_new_label();
4509 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4510 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4511 tcg_gen_br(l2);
4512 gen_set_label(l1);
4513 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4514 gen_set_label(l2);
4515 if (unlikely(Rc(ctx->opcode) != 0))
4516 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4517 }
4518
4519 /* dozo - dozo. */
4520 static void gen_dozo(DisasContext *ctx)
4521 {
4522 int l1 = gen_new_label();
4523 int l2 = gen_new_label();
4524 TCGv t0 = tcg_temp_new();
4525 TCGv t1 = tcg_temp_new();
4526 TCGv t2 = tcg_temp_new();
4527 /* Start with XER OV disabled, the most likely case */
4528 tcg_gen_movi_tl(cpu_ov, 0);
4529 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4530 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4531 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4532 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4533 tcg_gen_andc_tl(t1, t1, t2);
4534 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4535 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4536 tcg_gen_movi_tl(cpu_ov, 1);
4537 tcg_gen_movi_tl(cpu_so, 1);
4538 tcg_gen_br(l2);
4539 gen_set_label(l1);
4540 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4541 gen_set_label(l2);
4542 tcg_temp_free(t0);
4543 tcg_temp_free(t1);
4544 tcg_temp_free(t2);
4545 if (unlikely(Rc(ctx->opcode) != 0))
4546 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4547 }
4548
4549 /* dozi */
4550 static void gen_dozi(DisasContext *ctx)
4551 {
4552 target_long simm = SIMM(ctx->opcode);
4553 int l1 = gen_new_label();
4554 int l2 = gen_new_label();
4555 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4556 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4557 tcg_gen_br(l2);
4558 gen_set_label(l1);
4559 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4560 gen_set_label(l2);
4561 if (unlikely(Rc(ctx->opcode) != 0))
4562 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4563 }
4564
4565 /* lscbx - lscbx. */
4566 static void gen_lscbx(DisasContext *ctx)
4567 {
4568 TCGv t0 = tcg_temp_new();
4569 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4570 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4571 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4572
4573 gen_addr_reg_index(ctx, t0);
4574 /* NIP cannot be restored if the memory exception comes from an helper */
4575 gen_update_nip(ctx, ctx->nip - 4);
4576 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4577 tcg_temp_free_i32(t1);
4578 tcg_temp_free_i32(t2);
4579 tcg_temp_free_i32(t3);
4580 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4581 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4582 if (unlikely(Rc(ctx->opcode) != 0))
4583 gen_set_Rc0(ctx, t0);
4584 tcg_temp_free(t0);
4585 }
4586
4587 /* maskg - maskg. */
4588 static void gen_maskg(DisasContext *ctx)
4589 {
4590 int l1 = gen_new_label();
4591 TCGv t0 = tcg_temp_new();
4592 TCGv t1 = tcg_temp_new();
4593 TCGv t2 = tcg_temp_new();
4594 TCGv t3 = tcg_temp_new();
4595 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4596 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4597 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4598 tcg_gen_addi_tl(t2, t0, 1);
4599 tcg_gen_shr_tl(t2, t3, t2);
4600 tcg_gen_shr_tl(t3, t3, t1);
4601 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4602 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4603 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4604 gen_set_label(l1);
4605 tcg_temp_free(t0);
4606 tcg_temp_free(t1);
4607 tcg_temp_free(t2);
4608 tcg_temp_free(t3);
4609 if (unlikely(Rc(ctx->opcode) != 0))
4610 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4611 }
4612
4613 /* maskir - maskir. */
4614 static void gen_maskir(DisasContext *ctx)
4615 {
4616 TCGv t0 = tcg_temp_new();
4617 TCGv t1 = tcg_temp_new();
4618 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4619 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4620 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4621 tcg_temp_free(t0);
4622 tcg_temp_free(t1);
4623 if (unlikely(Rc(ctx->opcode) != 0))
4624 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4625 }
4626
4627 /* mul - mul. */
4628 static void gen_mul(DisasContext *ctx)
4629 {
4630 TCGv_i64 t0 = tcg_temp_new_i64();
4631 TCGv_i64 t1 = tcg_temp_new_i64();
4632 TCGv t2 = tcg_temp_new();
4633 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4634 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4635 tcg_gen_mul_i64(t0, t0, t1);
4636 tcg_gen_trunc_i64_tl(t2, t0);
4637 gen_store_spr(SPR_MQ, t2);
4638 tcg_gen_shri_i64(t1, t0, 32);
4639 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4640 tcg_temp_free_i64(t0);
4641 tcg_temp_free_i64(t1);
4642 tcg_temp_free(t2);
4643 if (unlikely(Rc(ctx->opcode) != 0))
4644 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4645 }
4646
4647 /* mulo - mulo. */
4648 static void gen_mulo(DisasContext *ctx)
4649 {
4650 int l1 = gen_new_label();
4651 TCGv_i64 t0 = tcg_temp_new_i64();
4652 TCGv_i64 t1 = tcg_temp_new_i64();
4653 TCGv t2 = tcg_temp_new();
4654 /* Start with XER OV disabled, the most likely case */
4655 tcg_gen_movi_tl(cpu_ov, 0);
4656 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4657 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4658 tcg_gen_mul_i64(t0, t0, t1);
4659 tcg_gen_trunc_i64_tl(t2, t0);
4660 gen_store_spr(SPR_MQ, t2);
4661 tcg_gen_shri_i64(t1, t0, 32);
4662 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4663 tcg_gen_ext32s_i64(t1, t0);
4664 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4665 tcg_gen_movi_tl(cpu_ov, 1);
4666 tcg_gen_movi_tl(cpu_so, 1);
4667 gen_set_label(l1);
4668 tcg_temp_free_i64(t0);
4669 tcg_temp_free_i64(t1);
4670 tcg_temp_free(t2);
4671 if (unlikely(Rc(ctx->opcode) != 0))
4672 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4673 }
4674
4675 /* nabs - nabs. */
4676 static void gen_nabs(DisasContext *ctx)
4677 {
4678 int l1 = gen_new_label();
4679 int l2 = gen_new_label();
4680 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4681 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4682 tcg_gen_br(l2);
4683 gen_set_label(l1);
4684 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4685 gen_set_label(l2);
4686 if (unlikely(Rc(ctx->opcode) != 0))
4687 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4688 }
4689
4690 /* nabso - nabso. */
4691 static void gen_nabso(DisasContext *ctx)
4692 {
4693 int l1 = gen_new_label();
4694 int l2 = gen_new_label();
4695 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4696 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4697 tcg_gen_br(l2);
4698 gen_set_label(l1);
4699 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4700 gen_set_label(l2);
4701 /* nabs never overflows */
4702 tcg_gen_movi_tl(cpu_ov, 0);
4703 if (unlikely(Rc(ctx->opcode) != 0))
4704 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4705 }
4706
4707 /* rlmi - rlmi. */
4708 static void gen_rlmi(DisasContext *ctx)
4709 {
4710 uint32_t mb = MB(ctx->opcode);
4711 uint32_t me = ME(ctx->opcode);
4712 TCGv t0 = tcg_temp_new();
4713 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4714 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4715 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4716 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4717 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4718 tcg_temp_free(t0);
4719 if (unlikely(Rc(ctx->opcode) != 0))
4720 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4721 }
4722
4723 /* rrib - rrib. */
4724 static void gen_rrib(DisasContext *ctx)
4725 {
4726 TCGv t0 = tcg_temp_new();
4727 TCGv t1 = tcg_temp_new();
4728 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4729 tcg_gen_movi_tl(t1, 0x80000000);
4730 tcg_gen_shr_tl(t1, t1, t0);
4731 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4732 tcg_gen_and_tl(t0, t0, t1);
4733 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4734 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4735 tcg_temp_free(t0);
4736 tcg_temp_free(t1);
4737 if (unlikely(Rc(ctx->opcode) != 0))
4738 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4739 }
4740
4741 /* sle - sle. */
4742 static void gen_sle(DisasContext *ctx)
4743 {
4744 TCGv t0 = tcg_temp_new();
4745 TCGv t1 = tcg_temp_new();
4746 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4747 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4748 tcg_gen_subfi_tl(t1, 32, t1);
4749 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4750 tcg_gen_or_tl(t1, t0, t1);
4751 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4752 gen_store_spr(SPR_MQ, t1);
4753 tcg_temp_free(t0);
4754 tcg_temp_free(t1);
4755 if (unlikely(Rc(ctx->opcode) != 0))
4756 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4757 }
4758
4759 /* sleq - sleq. */
4760 static void gen_sleq(DisasContext *ctx)
4761 {
4762 TCGv t0 = tcg_temp_new();
4763 TCGv t1 = tcg_temp_new();
4764 TCGv t2 = tcg_temp_new();
4765 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4766 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4767 tcg_gen_shl_tl(t2, t2, t0);
4768 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4769 gen_load_spr(t1, SPR_MQ);
4770 gen_store_spr(SPR_MQ, t0);
4771 tcg_gen_and_tl(t0, t0, t2);
4772 tcg_gen_andc_tl(t1, t1, t2);
4773 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4774 tcg_temp_free(t0);
4775 tcg_temp_free(t1);
4776 tcg_temp_free(t2);
4777 if (unlikely(Rc(ctx->opcode) != 0))
4778 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4779 }
4780
4781 /* sliq - sliq. */
4782 static void gen_sliq(DisasContext *ctx)
4783 {
4784 int sh = SH(ctx->opcode);
4785 TCGv t0 = tcg_temp_new();
4786 TCGv t1 = tcg_temp_new();
4787 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4788 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4789 tcg_gen_or_tl(t1, t0, t1);
4790 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4791 gen_store_spr(SPR_MQ, t1);
4792 tcg_temp_free(t0);
4793 tcg_temp_free(t1);
4794 if (unlikely(Rc(ctx->opcode) != 0))
4795 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4796 }
4797
4798 /* slliq - slliq. */
4799 static void gen_slliq(DisasContext *ctx)
4800 {
4801 int sh = SH(ctx->opcode);
4802 TCGv t0 = tcg_temp_new();
4803 TCGv t1 = tcg_temp_new();
4804 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4805 gen_load_spr(t1, SPR_MQ);
4806 gen_store_spr(SPR_MQ, t0);
4807 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4808 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4809 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4810 tcg_temp_free(t0);
4811 tcg_temp_free(t1);
4812 if (unlikely(Rc(ctx->opcode) != 0))
4813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4814 }
4815
4816 /* sllq - sllq. */
4817 static void gen_sllq(DisasContext *ctx)
4818 {
4819 int l1 = gen_new_label();
4820 int l2 = gen_new_label();
4821 TCGv t0 = tcg_temp_local_new();
4822 TCGv t1 = tcg_temp_local_new();
4823 TCGv t2 = tcg_temp_local_new();
4824 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4825 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4826 tcg_gen_shl_tl(t1, t1, t2);
4827 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4828 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4829 gen_load_spr(t0, SPR_MQ);
4830 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4831 tcg_gen_br(l2);
4832 gen_set_label(l1);
4833 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4834 gen_load_spr(t2, SPR_MQ);
4835 tcg_gen_andc_tl(t1, t2, t1);
4836 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4837 gen_set_label(l2);
4838 tcg_temp_free(t0);
4839 tcg_temp_free(t1);
4840 tcg_temp_free(t2);
4841 if (unlikely(Rc(ctx->opcode) != 0))
4842 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4843 }
4844
4845 /* slq - slq. */
4846 static void gen_slq(DisasContext *ctx)
4847 {
4848 int l1 = gen_new_label();
4849 TCGv t0 = tcg_temp_new();
4850 TCGv t1 = tcg_temp_new();
4851 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4852 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4853 tcg_gen_subfi_tl(t1, 32, t1);
4854 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4855 tcg_gen_or_tl(t1, t0, t1);
4856 gen_store_spr(SPR_MQ, t1);
4857 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4858 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4859 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4860 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4861 gen_set_label(l1);
4862 tcg_temp_free(t0);
4863 tcg_temp_free(t1);
4864 if (unlikely(Rc(ctx->opcode) != 0))
4865 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4866 }
4867
4868 /* sraiq - sraiq. */
4869 static void gen_sraiq(DisasContext *ctx)
4870 {
4871 int sh = SH(ctx->opcode);
4872 int l1 = gen_new_label();
4873 TCGv t0 = tcg_temp_new();
4874 TCGv t1 = tcg_temp_new();
4875 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4876 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4877 tcg_gen_or_tl(t0, t0, t1);
4878 gen_store_spr(SPR_MQ, t0);
4879 tcg_gen_movi_tl(cpu_ca, 0);
4880 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4881 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4882 tcg_gen_movi_tl(cpu_ca, 1);
4883 gen_set_label(l1);
4884 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4885 tcg_temp_free(t0);
4886 tcg_temp_free(t1);
4887 if (unlikely(Rc(ctx->opcode) != 0))
4888 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4889 }
4890
4891 /* sraq - sraq. */
4892 static void gen_sraq(DisasContext *ctx)
4893 {
4894 int l1 = gen_new_label();
4895 int l2 = gen_new_label();
4896 TCGv t0 = tcg_temp_new();
4897 TCGv t1 = tcg_temp_local_new();
4898 TCGv t2 = tcg_temp_local_new();
4899 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4900 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4901 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4902 tcg_gen_subfi_tl(t2, 32, t2);
4903 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4904 tcg_gen_or_tl(t0, t0, t2);
4905 gen_store_spr(SPR_MQ, t0);
4906 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4907 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4908 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4909 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4910 gen_set_label(l1);
4911 tcg_temp_free(t0);
4912 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4913 tcg_gen_movi_tl(cpu_ca, 0);
4914 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4915 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4916 tcg_gen_movi_tl(cpu_ca, 1);
4917 gen_set_label(l2);
4918 tcg_temp_free(t1);
4919 tcg_temp_free(t2);
4920 if (unlikely(Rc(ctx->opcode) != 0))
4921 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4922 }
4923
4924 /* sre - sre. */
4925 static void gen_sre(DisasContext *ctx)
4926 {
4927 TCGv t0 = tcg_temp_new();
4928 TCGv t1 = tcg_temp_new();
4929 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4930 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4931 tcg_gen_subfi_tl(t1, 32, t1);
4932 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4933 tcg_gen_or_tl(t1, t0, t1);
4934 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4935 gen_store_spr(SPR_MQ, t1);
4936 tcg_temp_free(t0);
4937 tcg_temp_free(t1);
4938 if (unlikely(Rc(ctx->opcode) != 0))
4939 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4940 }
4941
4942 /* srea - srea. */
4943 static void gen_srea(DisasContext *ctx)
4944 {
4945 TCGv t0 = tcg_temp_new();
4946 TCGv t1 = tcg_temp_new();
4947 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4948 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4949 gen_store_spr(SPR_MQ, t0);
4950 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4951 tcg_temp_free(t0);
4952 tcg_temp_free(t1);
4953 if (unlikely(Rc(ctx->opcode) != 0))
4954 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4955 }
4956
4957 /* sreq */
4958 static void gen_sreq(DisasContext *ctx)
4959 {
4960 TCGv t0 = tcg_temp_new();
4961 TCGv t1 = tcg_temp_new();
4962 TCGv t2 = tcg_temp_new();
4963 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4964 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4965 tcg_gen_shr_tl(t1, t1, t0);
4966 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4967 gen_load_spr(t2, SPR_MQ);
4968 gen_store_spr(SPR_MQ, t0);
4969 tcg_gen_and_tl(t0, t0, t1);
4970 tcg_gen_andc_tl(t2, t2, t1);
4971 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4972 tcg_temp_free(t0);
4973 tcg_temp_free(t1);
4974 tcg_temp_free(t2);
4975 if (unlikely(Rc(ctx->opcode) != 0))
4976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4977 }
4978
4979 /* sriq */
4980 static void gen_sriq(DisasContext *ctx)
4981 {
4982 int sh = SH(ctx->opcode);
4983 TCGv t0 = tcg_temp_new();
4984 TCGv t1 = tcg_temp_new();
4985 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4986 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4987 tcg_gen_or_tl(t1, t0, t1);
4988 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4989 gen_store_spr(SPR_MQ, t1);
4990 tcg_temp_free(t0);
4991 tcg_temp_free(t1);
4992 if (unlikely(Rc(ctx->opcode) != 0))
4993 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4994 }
4995
4996 /* srliq */
4997 static void gen_srliq(DisasContext *ctx)
4998 {
4999 int sh = SH(ctx->opcode);
5000 TCGv t0 = tcg_temp_new();
5001 TCGv t1 = tcg_temp_new();
5002 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5003 gen_load_spr(t1, SPR_MQ);
5004 gen_store_spr(SPR_MQ, t0);
5005 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5006 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5007 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5008 tcg_temp_free(t0);
5009 tcg_temp_free(t1);
5010 if (unlikely(Rc(ctx->opcode) != 0))
5011 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5012 }
5013
5014 /* srlq */
5015 static void gen_srlq(DisasContext *ctx)
5016 {
5017 int l1 = gen_new_label();
5018 int l2 = gen_new_label();
5019 TCGv t0 = tcg_temp_local_new();
5020 TCGv t1 = tcg_temp_local_new();
5021 TCGv t2 = tcg_temp_local_new();
5022 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5023 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5024 tcg_gen_shr_tl(t2, t1, t2);
5025 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5026 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5027 gen_load_spr(t0, SPR_MQ);
5028 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5029 tcg_gen_br(l2);
5030 gen_set_label(l1);
5031 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5032 tcg_gen_and_tl(t0, t0, t2);
5033 gen_load_spr(t1, SPR_MQ);
5034 tcg_gen_andc_tl(t1, t1, t2);
5035 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5036 gen_set_label(l2);
5037 tcg_temp_free(t0);
5038 tcg_temp_free(t1);
5039 tcg_temp_free(t2);
5040 if (unlikely(Rc(ctx->opcode) != 0))
5041 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5042 }
5043
5044 /* srq */
5045 static void gen_srq(DisasContext *ctx)
5046 {
5047 int l1 = gen_new_label();
5048 TCGv t0 = tcg_temp_new();
5049 TCGv t1 = tcg_temp_new();
5050 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5051 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5052 tcg_gen_subfi_tl(t1, 32, t1);
5053 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5054 tcg_gen_or_tl(t1, t0, t1);
5055 gen_store_spr(SPR_MQ, t1);
5056 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5057 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5058 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5059 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5060 gen_set_label(l1);
5061 tcg_temp_free(t0);
5062 tcg_temp_free(t1);
5063 if (unlikely(Rc(ctx->opcode) != 0))
5064 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5065 }
5066
5067 /* PowerPC 602 specific instructions */
5068
5069 /* dsa */
5070 static void gen_dsa(DisasContext *ctx)
5071 {
5072 /* XXX: TODO */
5073 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5074 }
5075
5076 /* esa */
5077 static void gen_esa(DisasContext *ctx)
5078 {
5079 /* XXX: TODO */
5080 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5081 }
5082
5083 /* mfrom */
5084 static void gen_mfrom(DisasContext *ctx)
5085 {
5086 #if defined(CONFIG_USER_ONLY)
5087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5088 #else
5089 if (unlikely(!ctx->mem_idx)) {
5090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5091 return;
5092 }
5093 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5094 #endif
5095 }
5096
5097 /* 602 - 603 - G2 TLB management */
5098
5099 /* tlbld */
5100 static void gen_tlbld_6xx(DisasContext *ctx)
5101 {
5102 #if defined(CONFIG_USER_ONLY)
5103 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5104 #else
5105 if (unlikely(!ctx->mem_idx)) {
5106 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5107 return;
5108 }
5109 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5110 #endif
5111 }
5112
5113 /* tlbli */
5114 static void gen_tlbli_6xx(DisasContext *ctx)
5115 {
5116 #if defined(CONFIG_USER_ONLY)
5117 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5118 #else
5119 if (unlikely(!ctx->mem_idx)) {
5120 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5121 return;
5122 }
5123 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5124 #endif
5125 }
5126
5127 /* 74xx TLB management */
5128
5129 /* tlbld */
5130 static void gen_tlbld_74xx(DisasContext *ctx)
5131 {
5132 #if defined(CONFIG_USER_ONLY)
5133 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5134 #else
5135 if (unlikely(!ctx->mem_idx)) {
5136 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5137 return;
5138 }
5139 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5140 #endif
5141 }
5142
5143 /* tlbli */
5144 static void gen_tlbli_74xx(DisasContext *ctx)
5145 {
5146 #if defined(CONFIG_USER_ONLY)
5147 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5148 #else
5149 if (unlikely(!ctx->mem_idx)) {
5150 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5151 return;
5152 }
5153 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5154 #endif
5155 }
5156
5157 /* POWER instructions not in PowerPC 601 */
5158
5159 /* clf */
5160 static void gen_clf(DisasContext *ctx)
5161 {
5162 /* Cache line flush: implemented as no-op */
5163 }
5164
5165 /* cli */
5166 static void gen_cli(DisasContext *ctx)
5167 {
5168 /* Cache line invalidate: privileged and treated as no-op */
5169 #if defined(CONFIG_USER_ONLY)
5170 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5171 #else
5172 if (unlikely(!ctx->mem_idx)) {
5173 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5174 return;
5175 }
5176 #endif
5177 }
5178
5179 /* dclst */
5180 static void gen_dclst(DisasContext *ctx)
5181 {
5182 /* Data cache line store: treated as no-op */
5183 }
5184
5185 static void gen_mfsri(DisasContext *ctx)
5186 {
5187 #if defined(CONFIG_USER_ONLY)
5188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5189 #else
5190 int ra = rA(ctx->opcode);
5191 int rd = rD(ctx->opcode);
5192 TCGv t0;
5193 if (unlikely(!ctx->mem_idx)) {
5194 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5195 return;
5196 }
5197 t0 = tcg_temp_new();
5198 gen_addr_reg_index(ctx, t0);
5199 tcg_gen_shri_tl(t0, t0, 28);
5200 tcg_gen_andi_tl(t0, t0, 0xF);
5201 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5202 tcg_temp_free(t0);
5203 if (ra != 0 && ra != rd)
5204 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5205 #endif
5206 }
5207
5208 static void gen_rac(DisasContext *ctx)
5209 {
5210 #if defined(CONFIG_USER_ONLY)
5211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5212 #else
5213 TCGv t0;
5214 if (unlikely(!ctx->mem_idx)) {
5215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5216 return;
5217 }
5218 t0 = tcg_temp_new();
5219 gen_addr_reg_index(ctx, t0);
5220 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5221 tcg_temp_free(t0);
5222 #endif
5223 }
5224
5225 static void gen_rfsvc(DisasContext *ctx)
5226 {
5227 #if defined(CONFIG_USER_ONLY)
5228 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5229 #else
5230 if (unlikely(!ctx->mem_idx)) {
5231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5232 return;
5233 }
5234 gen_helper_rfsvc(cpu_env);
5235 gen_sync_exception(ctx);
5236 #endif
5237 }
5238
5239 /* svc is not implemented for now */
5240
5241 /* POWER2 specific instructions */
5242 /* Quad manipulation (load/store two floats at a time) */
5243
5244 /* lfq */
5245 static void gen_lfq(DisasContext *ctx)
5246 {
5247 int rd = rD(ctx->opcode);
5248 TCGv t0;
5249 gen_set_access_type(ctx, ACCESS_FLOAT);
5250 t0 = tcg_temp_new();
5251 gen_addr_imm_index(ctx, t0, 0);
5252 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5253 gen_addr_add(ctx, t0, t0, 8);
5254 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5255 tcg_temp_free(t0);
5256 }
5257
5258 /* lfqu */
5259 static void gen_lfqu(DisasContext *ctx)
5260 {
5261 int ra = rA(ctx->opcode);
5262 int rd = rD(ctx->opcode);
5263 TCGv t0, t1;
5264 gen_set_access_type(ctx, ACCESS_FLOAT);
5265 t0 = tcg_temp_new();
5266 t1 = tcg_temp_new();
5267 gen_addr_imm_index(ctx, t0, 0);
5268 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5269 gen_addr_add(ctx, t1, t0, 8);
5270 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5271 if (ra != 0)
5272 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5273 tcg_temp_free(t0);
5274 tcg_temp_free(t1);
5275 }
5276
5277 /* lfqux */
5278 static void gen_lfqux(DisasContext *ctx)
5279 {
5280 int ra = rA(ctx->opcode);
5281 int rd = rD(ctx->opcode);
5282 gen_set_access_type(ctx, ACCESS_FLOAT);
5283 TCGv t0, t1;
5284 t0 = tcg_temp_new();
5285 gen_addr_reg_index(ctx, t0);
5286 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5287 t1 = tcg_temp_new();
5288 gen_addr_add(ctx, t1, t0, 8);
5289 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5290 tcg_temp_free(t1);
5291 if (ra != 0)
5292 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5293 tcg_temp_free(t0);
5294 }
5295
5296 /* lfqx */
5297 static void gen_lfqx(DisasContext *ctx)
5298 {
5299 int rd = rD(ctx->opcode);
5300 TCGv t0;
5301 gen_set_access_type(ctx, ACCESS_FLOAT);
5302 t0 = tcg_temp_new();
5303 gen_addr_reg_index(ctx, t0);
5304 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5305 gen_addr_add(ctx, t0, t0, 8);
5306 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5307 tcg_temp_free(t0);
5308 }
5309
5310 /* stfq */
5311 static void gen_stfq(DisasContext *ctx)
5312 {
5313 int rd = rD(ctx->opcode);
5314 TCGv t0;
5315 gen_set_access_type(ctx, ACCESS_FLOAT);
5316 t0 = tcg_temp_new();
5317 gen_addr_imm_index(ctx, t0, 0);
5318 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5319 gen_addr_add(ctx, t0, t0, 8);
5320 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5321 tcg_temp_free(t0);
5322 }
5323
5324 /* stfqu */
5325 static void gen_stfqu(DisasContext *ctx)
5326 {
5327 int ra = rA(ctx->opcode);
5328 int rd = rD(ctx->opcode);
5329 TCGv t0, t1;
5330 gen_set_access_type(ctx, ACCESS_FLOAT);
5331 t0 = tcg_temp_new();
5332 gen_addr_imm_index(ctx, t0, 0);
5333 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5334 t1 = tcg_temp_new();
5335 gen_addr_add(ctx, t1, t0, 8);
5336 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5337 tcg_temp_free(t1);
5338 if (ra != 0)
5339 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5340 tcg_temp_free(t0);
5341 }
5342
5343 /* stfqux */
5344 static void gen_stfqux(DisasContext *ctx)
5345 {
5346 int ra = rA(ctx->opcode);
5347 int rd = rD(ctx->opcode);
5348 TCGv t0, t1;
5349 gen_set_access_type(ctx, ACCESS_FLOAT);
5350 t0 = tcg_temp_new();
5351 gen_addr_reg_index(ctx, t0);
5352 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5353 t1 = tcg_temp_new();
5354 gen_addr_add(ctx, t1, t0, 8);
5355 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5356 tcg_temp_free(t1);
5357 if (ra != 0)
5358 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5359 tcg_temp_free(t0);
5360 }
5361
5362 /* stfqx */
5363 static void gen_stfqx(DisasContext *ctx)
5364 {
5365 int rd = rD(ctx->opcode);
5366 TCGv t0;
5367 gen_set_access_type(ctx, ACCESS_FLOAT);
5368 t0 = tcg_temp_new();
5369 gen_addr_reg_index(ctx, t0);
5370 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5371 gen_addr_add(ctx, t0, t0, 8);
5372 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5373 tcg_temp_free(t0);
5374 }
5375
5376 /* BookE specific instructions */
5377
5378 /* XXX: not implemented on 440 ? */
5379 static void gen_mfapidi(DisasContext *ctx)
5380 {
5381 /* XXX: TODO */
5382 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5383 }
5384
5385 /* XXX: not implemented on 440 ? */
5386 static void gen_tlbiva(DisasContext *ctx)
5387 {
5388 #if defined(CONFIG_USER_ONLY)
5389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5390 #else
5391 TCGv t0;
5392 if (unlikely(!ctx->mem_idx)) {
5393 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5394 return;
5395 }
5396 t0 = tcg_temp_new();
5397 gen_addr_reg_index(ctx, t0);
5398 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5399 tcg_temp_free(t0);
5400 #endif
5401 }
5402
5403 /* All 405 MAC instructions are translated here */
5404 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5405 int ra, int rb, int rt, int Rc)
5406 {
5407 TCGv t0, t1;
5408
5409 t0 = tcg_temp_local_new();
5410 t1 = tcg_temp_local_new();
5411
5412 switch (opc3 & 0x0D) {
5413 case 0x05:
5414 /* macchw - macchw. - macchwo - macchwo. */
5415 /* macchws - macchws. - macchwso - macchwso. */
5416 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5417 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5418 /* mulchw - mulchw. */
5419 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5420 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5421 tcg_gen_ext16s_tl(t1, t1);
5422 break;
5423 case 0x04:
5424 /* macchwu - macchwu. - macchwuo - macchwuo. */
5425 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5426 /* mulchwu - mulchwu. */
5427 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5428 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5429 tcg_gen_ext16u_tl(t1, t1);
5430 break;
5431 case 0x01:
5432 /* machhw - machhw. - machhwo - machhwo. */
5433 /* machhws - machhws. - machhwso - machhwso. */
5434 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5435 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5436 /* mulhhw - mulhhw. */
5437 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5438 tcg_gen_ext16s_tl(t0, t0);
5439 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5440 tcg_gen_ext16s_tl(t1, t1);
5441 break;
5442 case 0x00:
5443 /* machhwu - machhwu. - machhwuo - machhwuo. */
5444 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5445 /* mulhhwu - mulhhwu. */
5446 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5447 tcg_gen_ext16u_tl(t0, t0);
5448 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5449 tcg_gen_ext16u_tl(t1, t1);
5450 break;
5451 case 0x0D:
5452 /* maclhw - maclhw. - maclhwo - maclhwo. */
5453 /* maclhws - maclhws. - maclhwso - maclhwso. */
5454 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5455 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5456 /* mullhw - mullhw. */
5457 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5458 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5459 break;
5460 case 0x0C:
5461 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5462 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5463 /* mullhwu - mullhwu. */
5464 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5465 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5466 break;
5467 }
5468 if (opc2 & 0x04) {
5469 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5470 tcg_gen_mul_tl(t1, t0, t1);
5471 if (opc2 & 0x02) {
5472 /* nmultiply-and-accumulate (0x0E) */
5473 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5474 } else {
5475 /* multiply-and-accumulate (0x0C) */
5476 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5477 }
5478
5479 if (opc3 & 0x12) {
5480 /* Check overflow and/or saturate */
5481 int l1 = gen_new_label();
5482
5483 if (opc3 & 0x10) {
5484 /* Start with XER OV disabled, the most likely case */
5485 tcg_gen_movi_tl(cpu_ov, 0);
5486 }
5487 if (opc3 & 0x01) {
5488 /* Signed */
5489 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5490 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5491 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5492 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5493 if (opc3 & 0x02) {
5494 /* Saturate */
5495 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5496 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5497 }
5498 } else {
5499 /* Unsigned */
5500 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5501 if (opc3 & 0x02) {
5502 /* Saturate */
5503 tcg_gen_movi_tl(t0, UINT32_MAX);
5504 }
5505 }
5506 if (opc3 & 0x10) {
5507 /* Check overflow */
5508 tcg_gen_movi_tl(cpu_ov, 1);
5509 tcg_gen_movi_tl(cpu_so, 1);
5510 }
5511 gen_set_label(l1);
5512 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5513 }
5514 } else {
5515 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5516 }
5517 tcg_temp_free(t0);
5518 tcg_temp_free(t1);
5519 if (unlikely(Rc) != 0) {
5520 /* Update Rc0 */
5521 gen_set_Rc0(ctx, cpu_gpr[rt]);
5522 }
5523 }
5524
5525 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5526 static void glue(gen_, name)(DisasContext *ctx) \
5527 { \
5528 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5529 rD(ctx->opcode), Rc(ctx->opcode)); \
5530 }
5531
5532 /* macchw - macchw. */
5533 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5534 /* macchwo - macchwo. */
5535 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5536 /* macchws - macchws. */
5537 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5538 /* macchwso - macchwso. */
5539 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5540 /* macchwsu - macchwsu. */
5541 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5542 /* macchwsuo - macchwsuo. */
5543 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5544 /* macchwu - macchwu. */
5545 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5546 /* macchwuo - macchwuo. */
5547 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5548 /* machhw - machhw. */
5549 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5550 /* machhwo - machhwo. */
5551 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5552 /* machhws - machhws. */
5553 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5554 /* machhwso - machhwso. */
5555 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5556 /* machhwsu - machhwsu. */
5557 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5558 /* machhwsuo - machhwsuo. */
5559 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5560 /* machhwu - machhwu. */
5561 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5562 /* machhwuo - machhwuo. */
5563 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5564 /* maclhw - maclhw. */
5565 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5566 /* maclhwo - maclhwo. */
5567 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5568 /* maclhws - maclhws. */
5569 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5570 /* maclhwso - maclhwso. */
5571 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5572 /* maclhwu - maclhwu. */
5573 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5574 /* maclhwuo - maclhwuo. */
5575 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5576 /* maclhwsu - maclhwsu. */
5577 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5578 /* maclhwsuo - maclhwsuo. */
5579 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5580 /* nmacchw - nmacchw. */
5581 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5582 /* nmacchwo - nmacchwo. */
5583 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5584 /* nmacchws - nmacchws. */
5585 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5586 /* nmacchwso - nmacchwso. */
5587 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5588 /* nmachhw - nmachhw. */
5589 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5590 /* nmachhwo - nmachhwo. */
5591 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5592 /* nmachhws - nmachhws. */
5593 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5594 /* nmachhwso - nmachhwso. */
5595 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5596 /* nmaclhw - nmaclhw. */
5597 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5598 /* nmaclhwo - nmaclhwo. */
5599 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5600 /* nmaclhws - nmaclhws. */
5601 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5602 /* nmaclhwso - nmaclhwso. */
5603 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5604
5605 /* mulchw - mulchw. */
5606 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5607 /* mulchwu - mulchwu. */
5608 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5609 /* mulhhw - mulhhw. */
5610 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5611 /* mulhhwu - mulhhwu. */
5612 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5613 /* mullhw - mullhw. */
5614 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5615 /* mullhwu - mullhwu. */
5616 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5617
5618 /* mfdcr */
5619 static void gen_mfdcr(DisasContext *ctx)
5620 {
5621 #if defined(CONFIG_USER_ONLY)
5622 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5623 #else
5624 TCGv dcrn;
5625 if (unlikely(!ctx->mem_idx)) {
5626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5627 return;
5628 }
5629 /* NIP cannot be restored if the memory exception comes from an helper */
5630 gen_update_nip(ctx, ctx->nip - 4);
5631 dcrn = tcg_const_tl(SPR(ctx->opcode));
5632 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5633 tcg_temp_free(dcrn);
5634 #endif
5635 }
5636
5637 /* mtdcr */
5638 static void gen_mtdcr(DisasContext *ctx)
5639 {
5640 #if defined(CONFIG_USER_ONLY)
5641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5642 #else
5643 TCGv dcrn;
5644 if (unlikely(!ctx->mem_idx)) {
5645 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5646 return;
5647 }
5648 /* NIP cannot be restored if the memory exception comes from an helper */
5649 gen_update_nip(ctx, ctx->nip - 4);
5650 dcrn = tcg_const_tl(SPR(ctx->opcode));
5651 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5652 tcg_temp_free(dcrn);
5653 #endif
5654 }
5655
5656 /* mfdcrx */
5657 /* XXX: not implemented on 440 ? */
5658 static void gen_mfdcrx(DisasContext *ctx)
5659 {
5660 #if defined(CONFIG_USER_ONLY)
5661 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5662 #else
5663 if (unlikely(!ctx->mem_idx)) {
5664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5665 return;
5666 }
5667 /* NIP cannot be restored if the memory exception comes from an helper */
5668 gen_update_nip(ctx, ctx->nip - 4);
5669 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5670 cpu_gpr[rA(ctx->opcode)]);
5671 /* Note: Rc update flag set leads to undefined state of Rc0 */
5672 #endif
5673 }
5674
5675 /* mtdcrx */
5676 /* XXX: not implemented on 440 ? */
5677 static void gen_mtdcrx(DisasContext *ctx)
5678 {
5679 #if defined(CONFIG_USER_ONLY)
5680 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5681 #else
5682 if (unlikely(!ctx->mem_idx)) {
5683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5684 return;
5685 }
5686 /* NIP cannot be restored if the memory exception comes from an helper */
5687 gen_update_nip(ctx, ctx->nip - 4);
5688 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5689 cpu_gpr[rS(ctx->opcode)]);
5690 /* Note: Rc update flag set leads to undefined state of Rc0 */
5691 #endif
5692 }
5693
5694 /* mfdcrux (PPC 460) : user-mode access to DCR */
5695 static void gen_mfdcrux(DisasContext *ctx)
5696 {
5697 /* NIP cannot be restored if the memory exception comes from an helper */
5698 gen_update_nip(ctx, ctx->nip - 4);
5699 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5700 cpu_gpr[rA(ctx->opcode)]);
5701 /* Note: Rc update flag set leads to undefined state of Rc0 */
5702 }
5703
5704 /* mtdcrux (PPC 460) : user-mode access to DCR */
5705 static void gen_mtdcrux(DisasContext *ctx)
5706 {
5707 /* NIP cannot be restored if the memory exception comes from an helper */
5708 gen_update_nip(ctx, ctx->nip - 4);
5709 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5710 cpu_gpr[rS(ctx->opcode)]);
5711 /* Note: Rc update flag set leads to undefined state of Rc0 */
5712 }
5713
5714 /* dccci */
5715 static void gen_dccci(DisasContext *ctx)
5716 {
5717 #if defined(CONFIG_USER_ONLY)
5718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5719 #else
5720 if (unlikely(!ctx->mem_idx)) {
5721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5722 return;
5723 }
5724 /* interpreted as no-op */
5725 #endif
5726 }
5727
5728 /* dcread */
5729 static void gen_dcread(DisasContext *ctx)
5730 {
5731 #if defined(CONFIG_USER_ONLY)
5732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5733 #else
5734 TCGv EA, val;
5735 if (unlikely(!ctx->mem_idx)) {
5736 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5737 return;
5738 }
5739 gen_set_access_type(ctx, ACCESS_CACHE);
5740 EA = tcg_temp_new();
5741 gen_addr_reg_index(ctx, EA);
5742 val = tcg_temp_new();
5743 gen_qemu_ld32u(ctx, val, EA);
5744 tcg_temp_free(val);
5745 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5746 tcg_temp_free(EA);
5747 #endif
5748 }
5749
5750 /* icbt */
5751 static void gen_icbt_40x(DisasContext *ctx)
5752 {
5753 /* interpreted as no-op */
5754 /* XXX: specification say this is treated as a load by the MMU
5755 * but does not generate any exception
5756 */
5757 }
5758
5759 /* iccci */
5760 static void gen_iccci(DisasContext *ctx)
5761 {
5762 #if defined(CONFIG_USER_ONLY)
5763 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5764 #else
5765 if (unlikely(!ctx->mem_idx)) {
5766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5767 return;
5768 }
5769 /* interpreted as no-op */
5770 #endif
5771 }
5772
5773 /* icread */
5774 static void gen_icread(DisasContext *ctx)
5775 {
5776 #if defined(CONFIG_USER_ONLY)
5777 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5778 #else
5779 if (unlikely(!ctx->mem_idx)) {
5780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5781 return;
5782 }
5783 /* interpreted as no-op */
5784 #endif
5785 }
5786
5787 /* rfci (mem_idx only) */
5788 static void gen_rfci_40x(DisasContext *ctx)
5789 {
5790 #if defined(CONFIG_USER_ONLY)
5791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5792 #else
5793 if (unlikely(!ctx->mem_idx)) {
5794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5795 return;
5796 }
5797 /* Restore CPU state */
5798 gen_helper_40x_rfci(cpu_env);
5799 gen_sync_exception(ctx);
5800 #endif
5801 }
5802
5803 static void gen_rfci(DisasContext *ctx)
5804 {
5805 #if defined(CONFIG_USER_ONLY)
5806 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5807 #else
5808 if (unlikely(!ctx->mem_idx)) {
5809 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5810 return;
5811 }
5812 /* Restore CPU state */
5813 gen_helper_rfci(cpu_env);
5814 gen_sync_exception(ctx);
5815 #endif
5816 }
5817
5818 /* BookE specific */
5819
5820 /* XXX: not implemented on 440 ? */
5821 static void gen_rfdi(DisasContext *ctx)
5822 {
5823 #if defined(CONFIG_USER_ONLY)
5824 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5825 #else
5826 if (unlikely(!ctx->mem_idx)) {
5827 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5828 return;
5829 }
5830 /* Restore CPU state */
5831 gen_helper_rfdi(cpu_env);
5832 gen_sync_exception(ctx);
5833 #endif
5834 }
5835
5836 /* XXX: not implemented on 440 ? */
5837 static void gen_rfmci(DisasContext *ctx)
5838 {
5839 #if defined(CONFIG_USER_ONLY)
5840 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5841 #else
5842 if (unlikely(!ctx->mem_idx)) {
5843 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5844 return;
5845 }
5846 /* Restore CPU state */
5847 gen_helper_rfmci(cpu_env);
5848 gen_sync_exception(ctx);
5849 #endif
5850 }
5851
5852 /* TLB management - PowerPC 405 implementation */
5853
5854 /* tlbre */
5855 static void gen_tlbre_40x(DisasContext *ctx)
5856 {
5857 #if defined(CONFIG_USER_ONLY)
5858 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5859 #else
5860 if (unlikely(!ctx->mem_idx)) {
5861 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5862 return;
5863 }
5864 switch (rB(ctx->opcode)) {
5865 case 0:
5866 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5867 cpu_gpr[rA(ctx->opcode)]);
5868 break;
5869 case 1:
5870 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5871 cpu_gpr[rA(ctx->opcode)]);
5872 break;
5873 default:
5874 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5875 break;
5876 }
5877 #endif
5878 }
5879
5880 /* tlbsx - tlbsx. */
5881 static void gen_tlbsx_40x(DisasContext *ctx)
5882 {
5883 #if defined(CONFIG_USER_ONLY)
5884 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5885 #else
5886 TCGv t0;
5887 if (unlikely(!ctx->mem_idx)) {
5888 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5889 return;
5890 }
5891 t0 = tcg_temp_new();
5892 gen_addr_reg_index(ctx, t0);
5893 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5894 tcg_temp_free(t0);
5895 if (Rc(ctx->opcode)) {
5896 int l1 = gen_new_label();
5897 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5898 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5899 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5900 gen_set_label(l1);
5901 }
5902 #endif
5903 }
5904
5905 /* tlbwe */
5906 static void gen_tlbwe_40x(DisasContext *ctx)
5907 {
5908 #if defined(CONFIG_USER_ONLY)
5909 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5910 #else
5911 if (unlikely(!ctx->mem_idx)) {
5912 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5913 return;
5914 }
5915 switch (rB(ctx->opcode)) {
5916 case 0:
5917 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5918 cpu_gpr[rS(ctx->opcode)]);
5919 break;
5920 case 1:
5921 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5922 cpu_gpr[rS(ctx->opcode)]);
5923 break;
5924 default:
5925 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5926 break;
5927 }
5928 #endif
5929 }
5930
5931 /* TLB management - PowerPC 440 implementation */
5932
5933 /* tlbre */
5934 static void gen_tlbre_440(DisasContext *ctx)
5935 {
5936 #if defined(CONFIG_USER_ONLY)
5937 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5938 #else
5939 if (unlikely(!ctx->mem_idx)) {
5940 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5941 return;
5942 }
5943 switch (rB(ctx->opcode)) {
5944 case 0:
5945 case 1:
5946 case 2:
5947 {
5948 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5949 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5950 t0, cpu_gpr[rA(ctx->opcode)]);
5951 tcg_temp_free_i32(t0);
5952 }
5953 break;
5954 default:
5955 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5956 break;
5957 }
5958 #endif
5959 }
5960
5961 /* tlbsx - tlbsx. */
5962 static void gen_tlbsx_440(DisasContext *ctx)
5963 {
5964 #if defined(CONFIG_USER_ONLY)
5965 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5966 #else
5967 TCGv t0;
5968 if (unlikely(!ctx->mem_idx)) {
5969 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5970 return;
5971 }
5972 t0 = tcg_temp_new();
5973 gen_addr_reg_index(ctx, t0);
5974 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5975 tcg_temp_free(t0);
5976 if (Rc(ctx->opcode)) {
5977 int l1 = gen_new_label();
5978 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5979 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5980 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5981 gen_set_label(l1);
5982 }
5983 #endif
5984 }
5985
5986 /* tlbwe */
5987 static void gen_tlbwe_440(DisasContext *ctx)
5988 {
5989 #if defined(CONFIG_USER_ONLY)
5990 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5991 #else
5992 if (unlikely(!ctx->mem_idx)) {
5993 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5994 return;
5995 }
5996 switch (rB(ctx->opcode)) {
5997 case 0:
5998 case 1:
5999 case 2:
6000 {
6001 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6002 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6003 cpu_gpr[rS(ctx->opcode)]);
6004 tcg_temp_free_i32(t0);
6005 }
6006 break;
6007 default:
6008 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6009 break;
6010 }
6011 #endif
6012 }
6013
6014 /* TLB management - PowerPC BookE 2.06 implementation */
6015
6016 /* tlbre */
6017 static void gen_tlbre_booke206(DisasContext *ctx)
6018 {
6019 #if defined(CONFIG_USER_ONLY)
6020 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6021 #else
6022 if (unlikely(!ctx->mem_idx)) {
6023 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6024 return;
6025 }
6026
6027 gen_helper_booke206_tlbre(cpu_env);
6028 #endif
6029 }
6030
6031 /* tlbsx - tlbsx. */
6032 static void gen_tlbsx_booke206(DisasContext *ctx)
6033 {
6034 #if defined(CONFIG_USER_ONLY)
6035 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6036 #else
6037 TCGv t0;
6038 if (unlikely(!ctx->mem_idx)) {
6039 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6040 return;
6041 }
6042
6043 if (rA(ctx->opcode)) {
6044 t0 = tcg_temp_new();
6045 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6046 } else {
6047 t0 = tcg_const_tl(0);
6048 }
6049
6050 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6051 gen_helper_booke206_tlbsx(cpu_env, t0);
6052 #endif
6053 }
6054
6055 /* tlbwe */
6056 static void gen_tlbwe_booke206(DisasContext *ctx)
6057 {
6058 #if defined(CONFIG_USER_ONLY)
6059 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6060 #else
6061 if (unlikely(!ctx->mem_idx)) {
6062 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6063 return;
6064 }
6065 gen_update_nip(ctx, ctx->nip - 4);
6066 gen_helper_booke206_tlbwe(cpu_env);
6067 #endif
6068 }
6069
6070 static void gen_tlbivax_booke206(DisasContext *ctx)
6071 {
6072 #if defined(CONFIG_USER_ONLY)
6073 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6074 #else
6075 TCGv t0;
6076 if (unlikely(!ctx->mem_idx)) {
6077 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6078 return;
6079 }
6080
6081 t0 = tcg_temp_new();
6082 gen_addr_reg_index(ctx, t0);
6083
6084 gen_helper_booke206_tlbivax(cpu_env, t0);
6085 #endif
6086 }
6087
6088 static void gen_tlbilx_booke206(DisasContext *ctx)
6089 {
6090 #if defined(CONFIG_USER_ONLY)
6091 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6092 #else
6093 TCGv t0;
6094 if (unlikely(!ctx->mem_idx)) {
6095 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6096 return;
6097 }
6098
6099 t0 = tcg_temp_new();
6100 gen_addr_reg_index(ctx, t0);
6101
6102 switch((ctx->opcode >> 21) & 0x3) {
6103 case 0:
6104 gen_helper_booke206_tlbilx0(cpu_env, t0);
6105 break;
6106 case 1:
6107 gen_helper_booke206_tlbilx1(cpu_env, t0);
6108 break;
6109 case 3:
6110 gen_helper_booke206_tlbilx3(cpu_env, t0);
6111 break;
6112 default:
6113 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6114 break;
6115 }
6116
6117 tcg_temp_free(t0);
6118 #endif
6119 }
6120
6121
6122 /* wrtee */
6123 static void gen_wrtee(DisasContext *ctx)
6124 {
6125 #if defined(CONFIG_USER_ONLY)
6126 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6127 #else
6128 TCGv t0;
6129 if (unlikely(!ctx->mem_idx)) {
6130 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6131 return;
6132 }
6133 t0 = tcg_temp_new();
6134 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6135 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6136 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6137 tcg_temp_free(t0);
6138 /* Stop translation to have a chance to raise an exception
6139 * if we just set msr_ee to 1
6140 */
6141 gen_stop_exception(ctx);
6142 #endif
6143 }
6144
6145 /* wrteei */
6146 static void gen_wrteei(DisasContext *ctx)
6147 {
6148 #if defined(CONFIG_USER_ONLY)
6149 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6150 #else
6151 if (unlikely(!ctx->mem_idx)) {
6152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6153 return;
6154 }
6155 if (ctx->opcode & 0x00008000) {
6156 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6157 /* Stop translation to have a chance to raise an exception */
6158 gen_stop_exception(ctx);
6159 } else {
6160 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6161 }
6162 #endif
6163 }
6164
6165 /* PowerPC 440 specific instructions */
6166
6167 /* dlmzb */
6168 static void gen_dlmzb(DisasContext *ctx)
6169 {
6170 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6171 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6172 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6173 tcg_temp_free_i32(t0);
6174 }
6175
6176 /* mbar replaces eieio on 440 */
6177 static void gen_mbar(DisasContext *ctx)
6178 {
6179 /* interpreted as no-op */
6180 }
6181
6182 /* msync replaces sync on 440 */
6183 static void gen_msync_4xx(DisasContext *ctx)
6184 {
6185 /* interpreted as no-op */
6186 }
6187
6188 /* icbt */
6189 static void gen_icbt_440(DisasContext *ctx)
6190 {
6191 /* interpreted as no-op */
6192 /* XXX: specification say this is treated as a load by the MMU
6193 * but does not generate any exception
6194 */
6195 }
6196
6197 /* Embedded.Processor Control */
6198
6199 static void gen_msgclr(DisasContext *ctx)
6200 {
6201 #if defined(CONFIG_USER_ONLY)
6202 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6203 #else
6204 if (unlikely(ctx->mem_idx == 0)) {
6205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6206 return;
6207 }
6208
6209 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6210 #endif
6211 }
6212
6213 static void gen_msgsnd(DisasContext *ctx)
6214 {
6215 #if defined(CONFIG_USER_ONLY)
6216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6217 #else
6218 if (unlikely(ctx->mem_idx == 0)) {
6219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6220 return;
6221 }
6222
6223 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6224 #endif
6225 }
6226
6227 /*** Altivec vector extension ***/
6228 /* Altivec registers moves */
6229
6230 static inline TCGv_ptr gen_avr_ptr(int reg)
6231 {
6232 TCGv_ptr r = tcg_temp_new_ptr();
6233 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6234 return r;
6235 }
6236
6237 #define GEN_VR_LDX(name, opc2, opc3) \
6238 static void glue(gen_, name)(DisasContext *ctx) \
6239 { \
6240 TCGv EA; \
6241 if (unlikely(!ctx->altivec_enabled)) { \
6242 gen_exception(ctx, POWERPC_EXCP_VPU); \
6243 return; \
6244 } \
6245 gen_set_access_type(ctx, ACCESS_INT); \
6246 EA = tcg_temp_new(); \
6247 gen_addr_reg_index(ctx, EA); \
6248 tcg_gen_andi_tl(EA, EA, ~0xf); \
6249 if (ctx->le_mode) { \
6250 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6251 tcg_gen_addi_tl(EA, EA, 8); \
6252 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6253 } else { \
6254 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6255 tcg_gen_addi_tl(EA, EA, 8); \
6256 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6257 } \
6258 tcg_temp_free(EA); \
6259 }
6260
6261 #define GEN_VR_STX(name, opc2, opc3) \
6262 static void gen_st##name(DisasContext *ctx) \
6263 { \
6264 TCGv EA; \
6265 if (unlikely(!ctx->altivec_enabled)) { \
6266 gen_exception(ctx, POWERPC_EXCP_VPU); \
6267 return; \
6268 } \
6269 gen_set_access_type(ctx, ACCESS_INT); \
6270 EA = tcg_temp_new(); \
6271 gen_addr_reg_index(ctx, EA); \
6272 tcg_gen_andi_tl(EA, EA, ~0xf); \
6273 if (ctx->le_mode) { \
6274 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6275 tcg_gen_addi_tl(EA, EA, 8); \
6276 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6277 } else { \
6278 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6279 tcg_gen_addi_tl(EA, EA, 8); \
6280 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6281 } \
6282 tcg_temp_free(EA); \
6283 }
6284
6285 #define GEN_VR_LVE(name, opc2, opc3) \
6286 static void gen_lve##name(DisasContext *ctx) \
6287 { \
6288 TCGv EA; \
6289 TCGv_ptr rs; \
6290 if (unlikely(!ctx->altivec_enabled)) { \
6291 gen_exception(ctx, POWERPC_EXCP_VPU); \
6292 return; \
6293 } \
6294 gen_set_access_type(ctx, ACCESS_INT); \
6295 EA = tcg_temp_new(); \
6296 gen_addr_reg_index(ctx, EA); \
6297 rs = gen_avr_ptr(rS(ctx->opcode)); \
6298 gen_helper_lve##name(cpu_env, rs, EA); \
6299 tcg_temp_free(EA); \
6300 tcg_temp_free_ptr(rs); \
6301 }
6302
6303 #define GEN_VR_STVE(name, opc2, opc3) \
6304 static void gen_stve##name(DisasContext *ctx) \
6305 { \
6306 TCGv EA; \
6307 TCGv_ptr rs; \
6308 if (unlikely(!ctx->altivec_enabled)) { \
6309 gen_exception(ctx, POWERPC_EXCP_VPU); \
6310 return; \
6311 } \
6312 gen_set_access_type(ctx, ACCESS_INT); \
6313 EA = tcg_temp_new(); \
6314 gen_addr_reg_index(ctx, EA); \
6315 rs = gen_avr_ptr(rS(ctx->opcode)); \
6316 gen_helper_stve##name(cpu_env, rs, EA); \
6317 tcg_temp_free(EA); \
6318 tcg_temp_free_ptr(rs); \
6319 }
6320
6321 GEN_VR_LDX(lvx, 0x07, 0x03);
6322 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6323 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6324
6325 GEN_VR_LVE(bx, 0x07, 0x00);
6326 GEN_VR_LVE(hx, 0x07, 0x01);
6327 GEN_VR_LVE(wx, 0x07, 0x02);
6328
6329 GEN_VR_STX(svx, 0x07, 0x07);
6330 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6331 GEN_VR_STX(svxl, 0x07, 0x0F);
6332
6333 GEN_VR_STVE(bx, 0x07, 0x04);
6334 GEN_VR_STVE(hx, 0x07, 0x05);
6335 GEN_VR_STVE(wx, 0x07, 0x06);
6336
6337 static void gen_lvsl(DisasContext *ctx)
6338 {
6339 TCGv_ptr rd;
6340 TCGv EA;
6341 if (unlikely(!ctx->altivec_enabled)) {
6342 gen_exception(ctx, POWERPC_EXCP_VPU);
6343 return;
6344 }
6345 EA = tcg_temp_new();
6346 gen_addr_reg_index(ctx, EA);
6347 rd = gen_avr_ptr(rD(ctx->opcode));
6348 gen_helper_lvsl(rd, EA);
6349 tcg_temp_free(EA);
6350 tcg_temp_free_ptr(rd);
6351 }
6352
6353 static void gen_lvsr(DisasContext *ctx)
6354 {
6355 TCGv_ptr rd;
6356 TCGv EA;
6357 if (unlikely(!ctx->altivec_enabled)) {
6358 gen_exception(ctx, POWERPC_EXCP_VPU);
6359 return;
6360 }
6361 EA = tcg_temp_new();
6362 gen_addr_reg_index(ctx, EA);
6363 rd = gen_avr_ptr(rD(ctx->opcode));
6364 gen_helper_lvsr(rd, EA);
6365 tcg_temp_free(EA);
6366 tcg_temp_free_ptr(rd);
6367 }
6368
6369 static void gen_mfvscr(DisasContext *ctx)
6370 {
6371 TCGv_i32 t;
6372 if (unlikely(!ctx->altivec_enabled)) {
6373 gen_exception(ctx, POWERPC_EXCP_VPU);
6374 return;
6375 }
6376 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6377 t = tcg_temp_new_i32();
6378 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6379 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6380 tcg_temp_free_i32(t);
6381 }
6382
6383 static void gen_mtvscr(DisasContext *ctx)
6384 {
6385 TCGv_ptr p;
6386 if (unlikely(!ctx->altivec_enabled)) {
6387 gen_exception(ctx, POWERPC_EXCP_VPU);
6388 return;
6389 }
6390 p = gen_avr_ptr(rD(ctx->opcode));
6391 gen_helper_mtvscr(cpu_env, p);
6392 tcg_temp_free_ptr(p);
6393 }
6394
6395 /* Logical operations */
6396 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6397 static void glue(gen_, name)(DisasContext *ctx) \
6398 { \
6399 if (unlikely(!ctx->altivec_enabled)) { \
6400 gen_exception(ctx, POWERPC_EXCP_VPU); \
6401 return; \
6402 } \
6403 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6404 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6405 }
6406
6407 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6408 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6409 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6410 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6411 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6412
6413 #define GEN_VXFORM(name, opc2, opc3) \
6414 static void glue(gen_, name)(DisasContext *ctx) \
6415 { \
6416 TCGv_ptr ra, rb, rd; \
6417 if (unlikely(!ctx->altivec_enabled)) { \
6418 gen_exception(ctx, POWERPC_EXCP_VPU); \
6419 return; \
6420 } \
6421 ra = gen_avr_ptr(rA(ctx->opcode)); \
6422 rb = gen_avr_ptr(rB(ctx->opcode)); \
6423 rd = gen_avr_ptr(rD(ctx->opcode)); \
6424 gen_helper_##name (rd, ra, rb); \
6425 tcg_temp_free_ptr(ra); \
6426 tcg_temp_free_ptr(rb); \
6427 tcg_temp_free_ptr(rd); \
6428 }
6429
6430 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6431 static void glue(gen_, name)(DisasContext *ctx) \
6432 { \
6433 TCGv_ptr ra, rb, rd; \
6434 if (unlikely(!ctx->altivec_enabled)) { \
6435 gen_exception(ctx, POWERPC_EXCP_VPU); \
6436 return; \
6437 } \
6438 ra = gen_avr_ptr(rA(ctx->opcode)); \
6439 rb = gen_avr_ptr(rB(ctx->opcode)); \
6440 rd = gen_avr_ptr(rD(ctx->opcode)); \
6441 gen_helper_##name(cpu_env, rd, ra, rb); \
6442 tcg_temp_free_ptr(ra); \
6443 tcg_temp_free_ptr(rb); \
6444 tcg_temp_free_ptr(rd); \
6445 }
6446
6447 GEN_VXFORM(vaddubm, 0, 0);
6448 GEN_VXFORM(vadduhm, 0, 1);
6449 GEN_VXFORM(vadduwm, 0, 2);
6450 GEN_VXFORM(vsububm, 0, 16);
6451 GEN_VXFORM(vsubuhm, 0, 17);
6452 GEN_VXFORM(vsubuwm, 0, 18);
6453 GEN_VXFORM(vmaxub, 1, 0);
6454 GEN_VXFORM(vmaxuh, 1, 1);
6455 GEN_VXFORM(vmaxuw, 1, 2);
6456 GEN_VXFORM(vmaxsb, 1, 4);
6457 GEN_VXFORM(vmaxsh, 1, 5);
6458 GEN_VXFORM(vmaxsw, 1, 6);
6459 GEN_VXFORM(vminub, 1, 8);
6460 GEN_VXFORM(vminuh, 1, 9);
6461 GEN_VXFORM(vminuw, 1, 10);
6462 GEN_VXFORM(vminsb, 1, 12);
6463 GEN_VXFORM(vminsh, 1, 13);
6464 GEN_VXFORM(vminsw, 1, 14);
6465 GEN_VXFORM(vavgub, 1, 16);
6466 GEN_VXFORM(vavguh, 1, 17);
6467 GEN_VXFORM(vavguw, 1, 18);
6468 GEN_VXFORM(vavgsb, 1, 20);
6469 GEN_VXFORM(vavgsh, 1, 21);
6470 GEN_VXFORM(vavgsw, 1, 22);
6471 GEN_VXFORM(vmrghb, 6, 0);
6472 GEN_VXFORM(vmrghh, 6, 1);
6473 GEN_VXFORM(vmrghw, 6, 2);
6474 GEN_VXFORM(vmrglb, 6, 4);
6475 GEN_VXFORM(vmrglh, 6, 5);
6476 GEN_VXFORM(vmrglw, 6, 6);
6477 GEN_VXFORM(vmuloub, 4, 0);
6478 GEN_VXFORM(vmulouh, 4, 1);
6479 GEN_VXFORM(vmulosb, 4, 4);
6480 GEN_VXFORM(vmulosh, 4, 5);
6481 GEN_VXFORM(vmuleub, 4, 8);
6482 GEN_VXFORM(vmuleuh, 4, 9);
6483 GEN_VXFORM(vmulesb, 4, 12);
6484 GEN_VXFORM(vmulesh, 4, 13);
6485 GEN_VXFORM(vslb, 2, 4);
6486 GEN_VXFORM(vslh, 2, 5);
6487 GEN_VXFORM(vslw, 2, 6);
6488 GEN_VXFORM(vsrb, 2, 8);
6489 GEN_VXFORM(vsrh, 2, 9);
6490 GEN_VXFORM(vsrw, 2, 10);
6491 GEN_VXFORM(vsrab, 2, 12);
6492 GEN_VXFORM(vsrah, 2, 13);
6493 GEN_VXFORM(vsraw, 2, 14);
6494 GEN_VXFORM(vslo, 6, 16);
6495 GEN_VXFORM(vsro, 6, 17);
6496 GEN_VXFORM(vaddcuw, 0, 6);
6497 GEN_VXFORM(vsubcuw, 0, 22);
6498 GEN_VXFORM_ENV(vaddubs, 0, 8);
6499 GEN_VXFORM_ENV(vadduhs, 0, 9);
6500 GEN_VXFORM_ENV(vadduws, 0, 10);
6501 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6502 GEN_VXFORM_ENV(vaddshs, 0, 13);
6503 GEN_VXFORM_ENV(vaddsws, 0, 14);
6504 GEN_VXFORM_ENV(vsububs, 0, 24);
6505 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6506 GEN_VXFORM_ENV(vsubuws, 0, 26);
6507 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6508 GEN_VXFORM_ENV(vsubshs, 0, 29);
6509 GEN_VXFORM_ENV(vsubsws, 0, 30);
6510 GEN_VXFORM(vrlb, 2, 0);
6511 GEN_VXFORM(vrlh, 2, 1);
6512 GEN_VXFORM(vrlw, 2, 2);
6513 GEN_VXFORM(vsl, 2, 7);
6514 GEN_VXFORM(vsr, 2, 11);
6515 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6516 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6517 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6518 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6519 GEN_VXFORM_ENV(vpkshus, 7, 4);
6520 GEN_VXFORM_ENV(vpkswus, 7, 5);
6521 GEN_VXFORM_ENV(vpkshss, 7, 6);
6522 GEN_VXFORM_ENV(vpkswss, 7, 7);
6523 GEN_VXFORM(vpkpx, 7, 12);
6524 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6525 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6526 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6527 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6528 GEN_VXFORM_ENV(vsumsws, 4, 30);
6529 GEN_VXFORM_ENV(vaddfp, 5, 0);
6530 GEN_VXFORM_ENV(vsubfp, 5, 1);
6531 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6532 GEN_VXFORM_ENV(vminfp, 5, 17);
6533
6534 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6535 static void glue(gen_, name)(DisasContext *ctx) \
6536 { \
6537 TCGv_ptr ra, rb, rd; \
6538 if (unlikely(!ctx->altivec_enabled)) { \
6539 gen_exception(ctx, POWERPC_EXCP_VPU); \
6540 return; \
6541 } \
6542 ra = gen_avr_ptr(rA(ctx->opcode)); \
6543 rb = gen_avr_ptr(rB(ctx->opcode)); \
6544 rd = gen_avr_ptr(rD(ctx->opcode)); \
6545 gen_helper_##opname(cpu_env, rd, ra, rb); \
6546 tcg_temp_free_ptr(ra); \
6547 tcg_temp_free_ptr(rb); \
6548 tcg_temp_free_ptr(rd); \
6549 }
6550
6551 #define GEN_VXRFORM(name, opc2, opc3) \
6552 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6553 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6554
6555 GEN_VXRFORM(vcmpequb, 3, 0)
6556 GEN_VXRFORM(vcmpequh, 3, 1)
6557 GEN_VXRFORM(vcmpequw, 3, 2)
6558 GEN_VXRFORM(vcmpgtsb, 3, 12)
6559 GEN_VXRFORM(vcmpgtsh, 3, 13)
6560 GEN_VXRFORM(vcmpgtsw, 3, 14)
6561 GEN_VXRFORM(vcmpgtub, 3, 8)
6562 GEN_VXRFORM(vcmpgtuh, 3, 9)
6563 GEN_VXRFORM(vcmpgtuw, 3, 10)
6564 GEN_VXRFORM(vcmpeqfp, 3, 3)
6565 GEN_VXRFORM(vcmpgefp, 3, 7)
6566 GEN_VXRFORM(vcmpgtfp, 3, 11)
6567 GEN_VXRFORM(vcmpbfp, 3, 15)
6568
6569 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6570 static void glue(gen_, name)(DisasContext *ctx) \
6571 { \
6572 TCGv_ptr rd; \
6573 TCGv_i32 simm; \
6574 if (unlikely(!ctx->altivec_enabled)) { \
6575 gen_exception(ctx, POWERPC_EXCP_VPU); \
6576 return; \
6577 } \
6578 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6579 rd = gen_avr_ptr(rD(ctx->opcode)); \
6580 gen_helper_##name (rd, simm); \
6581 tcg_temp_free_i32(simm); \
6582 tcg_temp_free_ptr(rd); \
6583 }
6584
6585 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6586 GEN_VXFORM_SIMM(vspltish, 6, 13);
6587 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6588
6589 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6590 static void glue(gen_, name)(DisasContext *ctx) \
6591 { \
6592 TCGv_ptr rb, rd; \
6593 if (unlikely(!ctx->altivec_enabled)) { \
6594 gen_exception(ctx, POWERPC_EXCP_VPU); \
6595 return; \
6596 } \
6597 rb = gen_avr_ptr(rB(ctx->opcode)); \
6598 rd = gen_avr_ptr(rD(ctx->opcode)); \
6599 gen_helper_##name (rd, rb); \
6600 tcg_temp_free_ptr(rb); \
6601 tcg_temp_free_ptr(rd); \
6602 }
6603
6604 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6605 static void glue(gen_, name)(DisasContext *ctx) \
6606 { \
6607 TCGv_ptr rb, rd; \
6608 \
6609 if (unlikely(!ctx->altivec_enabled)) { \
6610 gen_exception(ctx, POWERPC_EXCP_VPU); \
6611 return; \
6612 } \
6613 rb = gen_avr_ptr(rB(ctx->opcode)); \
6614 rd = gen_avr_ptr(rD(ctx->opcode)); \
6615 gen_helper_##name(cpu_env, rd, rb); \
6616 tcg_temp_free_ptr(rb); \
6617 tcg_temp_free_ptr(rd); \
6618 }
6619
6620 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6621 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6622 GEN_VXFORM_NOA(vupklsb, 7, 10);
6623 GEN_VXFORM_NOA(vupklsh, 7, 11);
6624 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6625 GEN_VXFORM_NOA(vupklpx, 7, 15);
6626 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6627 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6628 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6629 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6630 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6631 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6632 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6633 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6634
6635 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6636 static void glue(gen_, name)(DisasContext *ctx) \
6637 { \
6638 TCGv_ptr rd; \
6639 TCGv_i32 simm; \
6640 if (unlikely(!ctx->altivec_enabled)) { \
6641 gen_exception(ctx, POWERPC_EXCP_VPU); \
6642 return; \
6643 } \
6644 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6645 rd = gen_avr_ptr(rD(ctx->opcode)); \
6646 gen_helper_##name (rd, simm); \
6647 tcg_temp_free_i32(simm); \
6648 tcg_temp_free_ptr(rd); \
6649 }
6650
6651 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6652 static void glue(gen_, name)(DisasContext *ctx) \
6653 { \
6654 TCGv_ptr rb, rd; \
6655 TCGv_i32 uimm; \
6656 if (unlikely(!ctx->altivec_enabled)) { \
6657 gen_exception(ctx, POWERPC_EXCP_VPU); \
6658 return; \
6659 } \
6660 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6661 rb = gen_avr_ptr(rB(ctx->opcode)); \
6662 rd = gen_avr_ptr(rD(ctx->opcode)); \
6663 gen_helper_##name (rd, rb, uimm); \
6664 tcg_temp_free_i32(uimm); \
6665 tcg_temp_free_ptr(rb); \
6666 tcg_temp_free_ptr(rd); \
6667 }
6668
6669 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6670 static void glue(gen_, name)(DisasContext *ctx) \
6671 { \
6672 TCGv_ptr rb, rd; \
6673 TCGv_i32 uimm; \
6674 \
6675 if (unlikely(!ctx->altivec_enabled)) { \
6676 gen_exception(ctx, POWERPC_EXCP_VPU); \
6677 return; \
6678 } \
6679 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6680 rb = gen_avr_ptr(rB(ctx->opcode)); \
6681 rd = gen_avr_ptr(rD(ctx->opcode)); \
6682 gen_helper_##name(cpu_env, rd, rb, uimm); \
6683 tcg_temp_free_i32(uimm); \
6684 tcg_temp_free_ptr(rb); \
6685 tcg_temp_free_ptr(rd); \
6686 }
6687
6688 GEN_VXFORM_UIMM(vspltb, 6, 8);
6689 GEN_VXFORM_UIMM(vsplth, 6, 9);
6690 GEN_VXFORM_UIMM(vspltw, 6, 10);
6691 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6692 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6693 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6694 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6695
6696 static void gen_vsldoi(DisasContext *ctx)
6697 {
6698 TCGv_ptr ra, rb, rd;
6699 TCGv_i32 sh;
6700 if (unlikely(!ctx->altivec_enabled)) {
6701 gen_exception(ctx, POWERPC_EXCP_VPU);
6702 return;
6703 }
6704 ra = gen_avr_ptr(rA(ctx->opcode));
6705 rb = gen_avr_ptr(rB(ctx->opcode));
6706 rd = gen_avr_ptr(rD(ctx->opcode));
6707 sh = tcg_const_i32(VSH(ctx->opcode));
6708 gen_helper_vsldoi (rd, ra, rb, sh);
6709 tcg_temp_free_ptr(ra);
6710 tcg_temp_free_ptr(rb);
6711 tcg_temp_free_ptr(rd);
6712 tcg_temp_free_i32(sh);
6713 }
6714
6715 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6716 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6717 { \
6718 TCGv_ptr ra, rb, rc, rd; \
6719 if (unlikely(!ctx->altivec_enabled)) { \
6720 gen_exception(ctx, POWERPC_EXCP_VPU); \
6721 return; \
6722 } \
6723 ra = gen_avr_ptr(rA(ctx->opcode)); \
6724 rb = gen_avr_ptr(rB(ctx->opcode)); \
6725 rc = gen_avr_ptr(rC(ctx->opcode)); \
6726 rd = gen_avr_ptr(rD(ctx->opcode)); \
6727 if (Rc(ctx->opcode)) { \
6728 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6729 } else { \
6730 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6731 } \
6732 tcg_temp_free_ptr(ra); \
6733 tcg_temp_free_ptr(rb); \
6734 tcg_temp_free_ptr(rc); \
6735 tcg_temp_free_ptr(rd); \
6736 }
6737
6738 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6739
6740 static void gen_vmladduhm(DisasContext *ctx)
6741 {
6742 TCGv_ptr ra, rb, rc, rd;
6743 if (unlikely(!ctx->altivec_enabled)) {
6744 gen_exception(ctx, POWERPC_EXCP_VPU);
6745 return;
6746 }
6747 ra = gen_avr_ptr(rA(ctx->opcode));
6748 rb = gen_avr_ptr(rB(ctx->opcode));
6749 rc = gen_avr_ptr(rC(ctx->opcode));
6750 rd = gen_avr_ptr(rD(ctx->opcode));
6751 gen_helper_vmladduhm(rd, ra, rb, rc);
6752 tcg_temp_free_ptr(ra);
6753 tcg_temp_free_ptr(rb);
6754 tcg_temp_free_ptr(rc);
6755 tcg_temp_free_ptr(rd);
6756 }
6757
6758 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6759 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6760 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6761 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6762 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6763
6764 /*** SPE extension ***/
6765 /* Register moves */
6766
6767
6768 static inline void gen_evmra(DisasContext *ctx)
6769 {
6770
6771 if (unlikely(!ctx->spe_enabled)) {
6772 gen_exception(ctx, POWERPC_EXCP_SPEU);
6773 return;
6774 }
6775
6776 #if defined(TARGET_PPC64)
6777 /* rD := rA */
6778 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6779
6780 /* spe_acc := rA */
6781 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6782 cpu_env,
6783 offsetof(CPUPPCState, spe_acc));
6784 #else
6785 TCGv_i64 tmp = tcg_temp_new_i64();
6786
6787 /* tmp := rA_lo + rA_hi << 32 */
6788 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6789
6790 /* spe_acc := tmp */
6791 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6792 tcg_temp_free_i64(tmp);
6793
6794 /* rD := rA */
6795 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6796 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6797 #endif
6798 }
6799
6800 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6801 {
6802 #if defined(TARGET_PPC64)
6803 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6804 #else
6805 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6806 #endif
6807 }
6808
6809 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6810 {
6811 #if defined(TARGET_PPC64)
6812 tcg_gen_mov_i64(cpu_gpr[reg], t);
6813 #else
6814 TCGv_i64 tmp = tcg_temp_new_i64();
6815 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6816 tcg_gen_shri_i64(tmp, t, 32);
6817 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6818 tcg_temp_free_i64(tmp);
6819 #endif
6820 }
6821
6822 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6823 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6824 { \
6825 if (Rc(ctx->opcode)) \
6826 gen_##name1(ctx); \
6827 else \
6828 gen_##name0(ctx); \
6829 }
6830
6831 /* Handler for undefined SPE opcodes */
6832 static inline void gen_speundef(DisasContext *ctx)
6833 {
6834 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6835 }
6836
6837 /* SPE logic */
6838 #if defined(TARGET_PPC64)
6839 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6840 static inline void gen_##name(DisasContext *ctx) \
6841 { \
6842 if (unlikely(!ctx->spe_enabled)) { \
6843 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6844 return; \
6845 } \
6846 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6847 cpu_gpr[rB(ctx->opcode)]); \
6848 }
6849 #else
6850 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6851 static inline void gen_##name(DisasContext *ctx) \
6852 { \
6853 if (unlikely(!ctx->spe_enabled)) { \
6854 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6855 return; \
6856 } \
6857 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6858 cpu_gpr[rB(ctx->opcode)]); \
6859 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6860 cpu_gprh[rB(ctx->opcode)]); \
6861 }
6862 #endif
6863
6864 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6865 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6866 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6867 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6868 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6869 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6870 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6871 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6872
6873 /* SPE logic immediate */
6874 #if defined(TARGET_PPC64)
6875 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6876 static inline void gen_##name(DisasContext *ctx) \
6877 { \
6878 if (unlikely(!ctx->spe_enabled)) { \
6879 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6880 return; \
6881 } \
6882 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6883 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6884 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6885 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6886 tcg_opi(t0, t0, rB(ctx->opcode)); \
6887 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6888 tcg_gen_trunc_i64_i32(t1, t2); \
6889 tcg_temp_free_i64(t2); \
6890 tcg_opi(t1, t1, rB(ctx->opcode)); \
6891 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6892 tcg_temp_free_i32(t0); \
6893 tcg_temp_free_i32(t1); \
6894 }
6895 #else
6896 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6897 static inline void gen_##name(DisasContext *ctx) \
6898 { \
6899 if (unlikely(!ctx->spe_enabled)) { \
6900 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6901 return; \
6902 } \
6903 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6904 rB(ctx->opcode)); \
6905 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6906 rB(ctx->opcode)); \
6907 }
6908 #endif
6909 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6910 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6911 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6912 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6913
6914 /* SPE arithmetic */
6915 #if defined(TARGET_PPC64)
6916 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6917 static inline void gen_##name(DisasContext *ctx) \
6918 { \
6919 if (unlikely(!ctx->spe_enabled)) { \
6920 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6921 return; \
6922 } \
6923 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6924 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6925 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6926 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6927 tcg_op(t0, t0); \
6928 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6929 tcg_gen_trunc_i64_i32(t1, t2); \
6930 tcg_temp_free_i64(t2); \
6931 tcg_op(t1, t1); \
6932 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6933 tcg_temp_free_i32(t0); \
6934 tcg_temp_free_i32(t1); \
6935 }
6936 #else
6937 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6938 static inline void gen_##name(DisasContext *ctx) \
6939 { \
6940 if (unlikely(!ctx->spe_enabled)) { \
6941 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6942 return; \
6943 } \
6944 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6945 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6946 }
6947 #endif
6948
6949 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6950 {
6951 int l1 = gen_new_label();
6952 int l2 = gen_new_label();
6953
6954 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6955 tcg_gen_neg_i32(ret, arg1);
6956 tcg_gen_br(l2);
6957 gen_set_label(l1);
6958 tcg_gen_mov_i32(ret, arg1);
6959 gen_set_label(l2);
6960 }
6961 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6962 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6963 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6964 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6965 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6966 {
6967 tcg_gen_addi_i32(ret, arg1, 0x8000);
6968 tcg_gen_ext16u_i32(ret, ret);
6969 }
6970 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6971 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6972 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6973
6974 #if defined(TARGET_PPC64)
6975 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6976 static inline void gen_##name(DisasContext *ctx) \
6977 { \
6978 if (unlikely(!ctx->spe_enabled)) { \
6979 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6980 return; \
6981 } \
6982 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6983 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6984 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6985 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6986 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6987 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6988 tcg_op(t0, t0, t2); \
6989 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6990 tcg_gen_trunc_i64_i32(t1, t3); \
6991 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6992 tcg_gen_trunc_i64_i32(t2, t3); \
6993 tcg_temp_free_i64(t3); \
6994 tcg_op(t1, t1, t2); \
6995 tcg_temp_free_i32(t2); \
6996 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6997 tcg_temp_free_i32(t0); \
6998 tcg_temp_free_i32(t1); \
6999 }
7000 #else
7001 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7002 static inline void gen_##name(DisasContext *ctx) \
7003 { \
7004 if (unlikely(!ctx->spe_enabled)) { \
7005 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7006 return; \
7007 } \
7008 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7009 cpu_gpr[rB(ctx->opcode)]); \
7010 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7011 cpu_gprh[rB(ctx->opcode)]); \
7012 }
7013 #endif
7014
7015 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7016 {
7017 TCGv_i32 t0;
7018 int l1, l2;
7019
7020 l1 = gen_new_label();
7021 l2 = gen_new_label();
7022 t0 = tcg_temp_local_new_i32();
7023 /* No error here: 6 bits are used */
7024 tcg_gen_andi_i32(t0, arg2, 0x3F);
7025 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7026 tcg_gen_shr_i32(ret, arg1, t0);
7027 tcg_gen_br(l2);
7028 gen_set_label(l1);
7029 tcg_gen_movi_i32(ret, 0);
7030 gen_set_label(l2);
7031 tcg_temp_free_i32(t0);
7032 }
7033 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7034 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7035 {
7036 TCGv_i32 t0;
7037 int l1, l2;
7038
7039 l1 = gen_new_label();
7040 l2 = gen_new_label();
7041 t0 = tcg_temp_local_new_i32();
7042 /* No error here: 6 bits are used */
7043 tcg_gen_andi_i32(t0, arg2, 0x3F);
7044 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7045 tcg_gen_sar_i32(ret, arg1, t0);
7046 tcg_gen_br(l2);
7047 gen_set_label(l1);
7048 tcg_gen_movi_i32(ret, 0);
7049 gen_set_label(l2);
7050 tcg_temp_free_i32(t0);
7051 }
7052 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7053 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7054 {
7055 TCGv_i32 t0;
7056 int l1, l2;
7057
7058 l1 = gen_new_label();
7059 l2 = gen_new_label();
7060 t0 = tcg_temp_local_new_i32();
7061 /* No error here: 6 bits are used */
7062 tcg_gen_andi_i32(t0, arg2, 0x3F);
7063 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7064 tcg_gen_shl_i32(ret, arg1, t0);
7065 tcg_gen_br(l2);
7066 gen_set_label(l1);
7067 tcg_gen_movi_i32(ret, 0);
7068 gen_set_label(l2);
7069 tcg_temp_free_i32(t0);
7070 }
7071 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7072 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7073 {
7074 TCGv_i32 t0 = tcg_temp_new_i32();
7075 tcg_gen_andi_i32(t0, arg2, 0x1F);
7076 tcg_gen_rotl_i32(ret, arg1, t0);
7077 tcg_temp_free_i32(t0);
7078 }
7079 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7080 static inline void gen_evmergehi(DisasContext *ctx)
7081 {
7082 if (unlikely(!ctx->spe_enabled)) {
7083 gen_exception(ctx, POWERPC_EXCP_SPEU);
7084 return;
7085 }
7086 #if defined(TARGET_PPC64)
7087 TCGv t0 = tcg_temp_new();
7088 TCGv t1 = tcg_temp_new();
7089 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7090 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7091 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7092 tcg_temp_free(t0);
7093 tcg_temp_free(t1);
7094 #else
7095 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7096 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7097 #endif
7098 }
7099 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7100 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7101 {
7102 tcg_gen_sub_i32(ret, arg2, arg1);
7103 }
7104 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7105
7106 /* SPE arithmetic immediate */
7107 #if defined(TARGET_PPC64)
7108 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7109 static inline void gen_##name(DisasContext *ctx) \
7110 { \
7111 if (unlikely(!ctx->spe_enabled)) { \
7112 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7113 return; \
7114 } \
7115 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7116 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7117 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7118 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7119 tcg_op(t0, t0, rA(ctx->opcode)); \
7120 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7121 tcg_gen_trunc_i64_i32(t1, t2); \
7122 tcg_temp_free_i64(t2); \
7123 tcg_op(t1, t1, rA(ctx->opcode)); \
7124 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7125 tcg_temp_free_i32(t0); \
7126 tcg_temp_free_i32(t1); \
7127 }
7128 #else
7129 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7130 static inline void gen_##name(DisasContext *ctx) \
7131 { \
7132 if (unlikely(!ctx->spe_enabled)) { \
7133 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7134 return; \
7135 } \
7136 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7137 rA(ctx->opcode)); \
7138 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7139 rA(ctx->opcode)); \
7140 }
7141 #endif
7142 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7143 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7144
7145 /* SPE comparison */
7146 #if defined(TARGET_PPC64)
7147 #define GEN_SPEOP_COMP(name, tcg_cond) \
7148 static inline void gen_##name(DisasContext *ctx) \
7149 { \
7150 if (unlikely(!ctx->spe_enabled)) { \
7151 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7152 return; \
7153 } \
7154 int l1 = gen_new_label(); \
7155 int l2 = gen_new_label(); \
7156 int l3 = gen_new_label(); \
7157 int l4 = gen_new_label(); \
7158 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7159 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7160 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7161 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7162 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7163 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7164 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7165 tcg_gen_br(l2); \
7166 gen_set_label(l1); \
7167 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7168 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7169 gen_set_label(l2); \
7170 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7171 tcg_gen_trunc_i64_i32(t0, t2); \
7172 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7173 tcg_gen_trunc_i64_i32(t1, t2); \
7174 tcg_temp_free_i64(t2); \
7175 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7176 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7177 ~(CRF_CH | CRF_CH_AND_CL)); \
7178 tcg_gen_br(l4); \
7179 gen_set_label(l3); \
7180 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7181 CRF_CH | CRF_CH_OR_CL); \
7182 gen_set_label(l4); \
7183 tcg_temp_free_i32(t0); \
7184 tcg_temp_free_i32(t1); \
7185 }
7186 #else
7187 #define GEN_SPEOP_COMP(name, tcg_cond) \
7188 static inline void gen_##name(DisasContext *ctx) \
7189 { \
7190 if (unlikely(!ctx->spe_enabled)) { \
7191 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7192 return; \
7193 } \
7194 int l1 = gen_new_label(); \
7195 int l2 = gen_new_label(); \
7196 int l3 = gen_new_label(); \
7197 int l4 = gen_new_label(); \
7198 \
7199 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7200 cpu_gpr[rB(ctx->opcode)], l1); \
7201 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7202 tcg_gen_br(l2); \
7203 gen_set_label(l1); \
7204 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7205 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7206 gen_set_label(l2); \
7207 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7208 cpu_gprh[rB(ctx->opcode)], l3); \
7209 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7210 ~(CRF_CH | CRF_CH_AND_CL)); \
7211 tcg_gen_br(l4); \
7212 gen_set_label(l3); \
7213 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7214 CRF_CH | CRF_CH_OR_CL); \
7215 gen_set_label(l4); \
7216 }
7217 #endif
7218 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7219 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7220 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7221 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7222 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7223
7224 /* SPE misc */
7225 static inline void gen_brinc(DisasContext *ctx)
7226 {
7227 /* Note: brinc is usable even if SPE is disabled */
7228 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7229 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7230 }
7231 static inline void gen_evmergelo(DisasContext *ctx)
7232 {
7233 if (unlikely(!ctx->spe_enabled)) {
7234 gen_exception(ctx, POWERPC_EXCP_SPEU);
7235 return;
7236 }
7237 #if defined(TARGET_PPC64)
7238 TCGv t0 = tcg_temp_new();
7239 TCGv t1 = tcg_temp_new();
7240 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7241 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7242 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7243 tcg_temp_free(t0);
7244 tcg_temp_free(t1);
7245 #else
7246 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7247 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7248 #endif
7249 }
7250 static inline void gen_evmergehilo(DisasContext *ctx)
7251 {
7252 if (unlikely(!ctx->spe_enabled)) {
7253 gen_exception(ctx, POWERPC_EXCP_SPEU);
7254 return;
7255 }
7256 #if defined(TARGET_PPC64)
7257 TCGv t0 = tcg_temp_new();
7258 TCGv t1 = tcg_temp_new();
7259 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7260 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7261 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7262 tcg_temp_free(t0);
7263 tcg_temp_free(t1);
7264 #else
7265 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7266 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7267 #endif
7268 }
7269 static inline void gen_evmergelohi(DisasContext *ctx)
7270 {
7271 if (unlikely(!ctx->spe_enabled)) {
7272 gen_exception(ctx, POWERPC_EXCP_SPEU);
7273 return;
7274 }
7275 #if defined(TARGET_PPC64)
7276 TCGv t0 = tcg_temp_new();
7277 TCGv t1 = tcg_temp_new();
7278 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7279 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7280 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7281 tcg_temp_free(t0);
7282 tcg_temp_free(t1);
7283 #else
7284 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7285 TCGv_i32 tmp = tcg_temp_new_i32();
7286 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7287 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7288 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7289 tcg_temp_free_i32(tmp);
7290 } else {
7291 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7292 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7293 }
7294 #endif
7295 }
7296 static inline void gen_evsplati(DisasContext *ctx)
7297 {
7298 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7299
7300 #if defined(TARGET_PPC64)
7301 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7302 #else
7303 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7304 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7305 #endif
7306 }
7307 static inline void gen_evsplatfi(DisasContext *ctx)
7308 {
7309 uint64_t imm = rA(ctx->opcode) << 27;
7310
7311 #if defined(TARGET_PPC64)
7312 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7313 #else
7314 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7315 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7316 #endif
7317 }
7318
7319 static inline void gen_evsel(DisasContext *ctx)
7320 {
7321 int l1 = gen_new_label();
7322 int l2 = gen_new_label();
7323 int l3 = gen_new_label();
7324 int l4 = gen_new_label();
7325 TCGv_i32 t0 = tcg_temp_local_new_i32();
7326 #if defined(TARGET_PPC64)
7327 TCGv t1 = tcg_temp_local_new();
7328 TCGv t2 = tcg_temp_local_new();
7329 #endif
7330 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7331 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7332 #if defined(TARGET_PPC64)
7333 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7334 #else
7335 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7336 #endif
7337 tcg_gen_br(l2);
7338 gen_set_label(l1);
7339 #if defined(TARGET_PPC64)
7340 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7341 #else
7342 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7343 #endif
7344 gen_set_label(l2);
7345 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7346 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7347 #if defined(TARGET_PPC64)
7348 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7349 #else
7350 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7351 #endif
7352 tcg_gen_br(l4);
7353 gen_set_label(l3);
7354 #if defined(TARGET_PPC64)
7355 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7356 #else
7357 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7358 #endif
7359 gen_set_label(l4);
7360 tcg_temp_free_i32(t0);
7361 #if defined(TARGET_PPC64)
7362 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7363 tcg_temp_free(t1);
7364 tcg_temp_free(t2);
7365 #endif
7366 }
7367
7368 static void gen_evsel0(DisasContext *ctx)
7369 {
7370 gen_evsel(ctx);
7371 }
7372
7373 static void gen_evsel1(DisasContext *ctx)
7374 {
7375 gen_evsel(ctx);
7376 }
7377
7378 static void gen_evsel2(DisasContext *ctx)
7379 {
7380 gen_evsel(ctx);
7381 }
7382
7383 static void gen_evsel3(DisasContext *ctx)
7384 {
7385 gen_evsel(ctx);
7386 }
7387
7388 /* Multiply */
7389
7390 static inline void gen_evmwumi(DisasContext *ctx)
7391 {
7392 TCGv_i64 t0, t1;
7393
7394 if (unlikely(!ctx->spe_enabled)) {
7395 gen_exception(ctx, POWERPC_EXCP_SPEU);
7396 return;
7397 }
7398
7399 t0 = tcg_temp_new_i64();
7400 t1 = tcg_temp_new_i64();
7401
7402 /* t0 := rA; t1 := rB */
7403 #if defined(TARGET_PPC64)
7404 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7405 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7406 #else
7407 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7408 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7409 #endif
7410
7411 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7412
7413 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7414
7415 tcg_temp_free_i64(t0);
7416 tcg_temp_free_i64(t1);
7417 }
7418
7419 static inline void gen_evmwumia(DisasContext *ctx)
7420 {
7421 TCGv_i64 tmp;
7422
7423 if (unlikely(!ctx->spe_enabled)) {
7424 gen_exception(ctx, POWERPC_EXCP_SPEU);
7425 return;
7426 }
7427
7428 gen_evmwumi(ctx); /* rD := rA * rB */
7429
7430 tmp = tcg_temp_new_i64();
7431
7432 /* acc := rD */
7433 gen_load_gpr64(tmp, rD(ctx->opcode));
7434 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7435 tcg_temp_free_i64(tmp);
7436 }
7437
7438 static inline void gen_evmwumiaa(DisasContext *ctx)
7439 {
7440 TCGv_i64 acc;
7441 TCGv_i64 tmp;
7442
7443 if (unlikely(!ctx->spe_enabled)) {
7444 gen_exception(ctx, POWERPC_EXCP_SPEU);
7445 return;
7446 }
7447
7448 gen_evmwumi(ctx); /* rD := rA * rB */
7449
7450 acc = tcg_temp_new_i64();
7451 tmp = tcg_temp_new_i64();
7452
7453 /* tmp := rD */
7454 gen_load_gpr64(tmp, rD(ctx->opcode));
7455
7456 /* Load acc */
7457 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7458
7459 /* acc := tmp + acc */
7460 tcg_gen_add_i64(acc, acc, tmp);
7461
7462 /* Store acc */
7463 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7464
7465 /* rD := acc */
7466 gen_store_gpr64(rD(ctx->opcode), acc);
7467
7468 tcg_temp_free_i64(acc);
7469 tcg_temp_free_i64(tmp);
7470 }
7471
7472 static inline void gen_evmwsmi(DisasContext *ctx)
7473 {
7474 TCGv_i64 t0, t1;
7475
7476 if (unlikely(!ctx->spe_enabled)) {
7477 gen_exception(ctx, POWERPC_EXCP_SPEU);
7478 return;
7479 }
7480
7481 t0 = tcg_temp_new_i64();
7482 t1 = tcg_temp_new_i64();
7483
7484 /* t0 := rA; t1 := rB */
7485 #if defined(TARGET_PPC64)
7486 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7487 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7488 #else
7489 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7490 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7491 #endif
7492
7493 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7494
7495 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7496
7497 tcg_temp_free_i64(t0);
7498 tcg_temp_free_i64(t1);
7499 }
7500
7501 static inline void gen_evmwsmia(DisasContext *ctx)
7502 {
7503 TCGv_i64 tmp;
7504
7505 gen_evmwsmi(ctx); /* rD := rA * rB */
7506
7507 tmp = tcg_temp_new_i64();
7508
7509 /* acc := rD */
7510 gen_load_gpr64(tmp, rD(ctx->opcode));
7511 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7512
7513 tcg_temp_free_i64(tmp);
7514 }
7515
7516 static inline void gen_evmwsmiaa(DisasContext *ctx)
7517 {
7518 TCGv_i64 acc = tcg_temp_new_i64();
7519 TCGv_i64 tmp = tcg_temp_new_i64();
7520
7521 gen_evmwsmi(ctx); /* rD := rA * rB */
7522
7523 acc = tcg_temp_new_i64();
7524 tmp = tcg_temp_new_i64();
7525
7526 /* tmp := rD */
7527 gen_load_gpr64(tmp, rD(ctx->opcode));
7528
7529 /* Load acc */
7530 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7531
7532 /* acc := tmp + acc */
7533 tcg_gen_add_i64(acc, acc, tmp);
7534
7535 /* Store acc */
7536 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7537
7538 /* rD := acc */
7539 gen_store_gpr64(rD(ctx->opcode), acc);
7540
7541 tcg_temp_free_i64(acc);
7542 tcg_temp_free_i64(tmp);
7543 }
7544
7545 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7546 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7547 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7548 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7549 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7550 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7551 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7552 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7553 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7554 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7555 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7556 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7557 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7558 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7559 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7560 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7561 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7562 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7563 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7564 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7565 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7566 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7567 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7568 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7569 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7570 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7571 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7572 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7573 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7574
7575 /* SPE load and stores */
7576 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7577 {
7578 target_ulong uimm = rB(ctx->opcode);
7579
7580 if (rA(ctx->opcode) == 0) {
7581 tcg_gen_movi_tl(EA, uimm << sh);
7582 } else {
7583 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7584 if (NARROW_MODE(ctx)) {
7585 tcg_gen_ext32u_tl(EA, EA);
7586 }
7587 }
7588 }
7589
7590 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7591 {
7592 #if defined(TARGET_PPC64)
7593 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7594 #else
7595 TCGv_i64 t0 = tcg_temp_new_i64();
7596 gen_qemu_ld64(ctx, t0, addr);
7597 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7598 tcg_gen_shri_i64(t0, t0, 32);
7599 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7600 tcg_temp_free_i64(t0);
7601 #endif
7602 }
7603
7604 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7605 {
7606 #if defined(TARGET_PPC64)
7607 TCGv t0 = tcg_temp_new();
7608 gen_qemu_ld32u(ctx, t0, addr);
7609 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7610 gen_addr_add(ctx, addr, addr, 4);
7611 gen_qemu_ld32u(ctx, t0, addr);
7612 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7613 tcg_temp_free(t0);
7614 #else
7615 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7616 gen_addr_add(ctx, addr, addr, 4);
7617 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7618 #endif
7619 }
7620
7621 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7622 {
7623 TCGv t0 = tcg_temp_new();
7624 #if defined(TARGET_PPC64)
7625 gen_qemu_ld16u(ctx, t0, addr);
7626 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7627 gen_addr_add(ctx, addr, addr, 2);
7628 gen_qemu_ld16u(ctx, t0, addr);
7629 tcg_gen_shli_tl(t0, t0, 32);
7630 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7631 gen_addr_add(ctx, addr, addr, 2);
7632 gen_qemu_ld16u(ctx, t0, addr);
7633 tcg_gen_shli_tl(t0, t0, 16);
7634 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7635 gen_addr_add(ctx, addr, addr, 2);
7636 gen_qemu_ld16u(ctx, t0, addr);
7637 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7638 #else
7639 gen_qemu_ld16u(ctx, t0, addr);
7640 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7641 gen_addr_add(ctx, addr, addr, 2);
7642 gen_qemu_ld16u(ctx, t0, addr);
7643 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7644 gen_addr_add(ctx, addr, addr, 2);
7645 gen_qemu_ld16u(ctx, t0, addr);
7646 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7647 gen_addr_add(ctx, addr, addr, 2);
7648 gen_qemu_ld16u(ctx, t0, addr);
7649 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7650 #endif
7651 tcg_temp_free(t0);
7652 }
7653
7654 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7655 {
7656 TCGv t0 = tcg_temp_new();
7657 gen_qemu_ld16u(ctx, t0, addr);
7658 #if defined(TARGET_PPC64)
7659 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7660 tcg_gen_shli_tl(t0, t0, 16);
7661 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7662 #else
7663 tcg_gen_shli_tl(t0, t0, 16);
7664 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7665 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7666 #endif
7667 tcg_temp_free(t0);
7668 }
7669
7670 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7671 {
7672 TCGv t0 = tcg_temp_new();
7673 gen_qemu_ld16u(ctx, t0, addr);
7674 #if defined(TARGET_PPC64)
7675 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7676 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7677 #else
7678 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7679 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7680 #endif
7681 tcg_temp_free(t0);
7682 }
7683
7684 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7685 {
7686 TCGv t0 = tcg_temp_new();
7687 gen_qemu_ld16s(ctx, t0, addr);
7688 #if defined(TARGET_PPC64)
7689 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7690 tcg_gen_ext32u_tl(t0, t0);
7691 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7692 #else
7693 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7694 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7695 #endif
7696 tcg_temp_free(t0);
7697 }
7698
7699 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7700 {
7701 TCGv t0 = tcg_temp_new();
7702 #if defined(TARGET_PPC64)
7703 gen_qemu_ld16u(ctx, t0, addr);
7704 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7705 gen_addr_add(ctx, addr, addr, 2);
7706 gen_qemu_ld16u(ctx, t0, addr);
7707 tcg_gen_shli_tl(t0, t0, 16);
7708 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7709 #else
7710 gen_qemu_ld16u(ctx, t0, addr);
7711 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7712 gen_addr_add(ctx, addr, addr, 2);
7713 gen_qemu_ld16u(ctx, t0, addr);
7714 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7715 #endif
7716 tcg_temp_free(t0);
7717 }
7718
7719 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7720 {
7721 #if defined(TARGET_PPC64)
7722 TCGv t0 = tcg_temp_new();
7723 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7724 gen_addr_add(ctx, addr, addr, 2);
7725 gen_qemu_ld16u(ctx, t0, addr);
7726 tcg_gen_shli_tl(t0, t0, 32);
7727 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7728 tcg_temp_free(t0);
7729 #else
7730 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7731 gen_addr_add(ctx, addr, addr, 2);
7732 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7733 #endif
7734 }
7735
7736 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7737 {
7738 #if defined(TARGET_PPC64)
7739 TCGv t0 = tcg_temp_new();
7740 gen_qemu_ld16s(ctx, t0, addr);
7741 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7742 gen_addr_add(ctx, addr, addr, 2);
7743 gen_qemu_ld16s(ctx, t0, addr);
7744 tcg_gen_shli_tl(t0, t0, 32);
7745 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7746 tcg_temp_free(t0);
7747 #else
7748 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7749 gen_addr_add(ctx, addr, addr, 2);
7750 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7751 #endif
7752 }
7753
7754 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7755 {
7756 TCGv t0 = tcg_temp_new();
7757 gen_qemu_ld32u(ctx, t0, addr);
7758 #if defined(TARGET_PPC64)
7759 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7760 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7761 #else
7762 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7763 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7764 #endif
7765 tcg_temp_free(t0);
7766 }
7767
7768 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7769 {
7770 TCGv t0 = tcg_temp_new();
7771 #if defined(TARGET_PPC64)
7772 gen_qemu_ld16u(ctx, t0, addr);
7773 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7774 tcg_gen_shli_tl(t0, t0, 32);
7775 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7776 gen_addr_add(ctx, addr, addr, 2);
7777 gen_qemu_ld16u(ctx, t0, addr);
7778 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7779 tcg_gen_shli_tl(t0, t0, 16);
7780 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7781 #else
7782 gen_qemu_ld16u(ctx, t0, addr);
7783 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7784 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7785 gen_addr_add(ctx, addr, addr, 2);
7786 gen_qemu_ld16u(ctx, t0, addr);
7787 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7788 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7789 #endif
7790 tcg_temp_free(t0);
7791 }
7792
7793 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7794 {
7795 #if defined(TARGET_PPC64)
7796 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7797 #else
7798 TCGv_i64 t0 = tcg_temp_new_i64();
7799 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7800 gen_qemu_st64(ctx, t0, addr);
7801 tcg_temp_free_i64(t0);
7802 #endif
7803 }
7804
7805 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7806 {
7807 #if defined(TARGET_PPC64)
7808 TCGv t0 = tcg_temp_new();
7809 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7810 gen_qemu_st32(ctx, t0, addr);
7811 tcg_temp_free(t0);
7812 #else
7813 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7814 #endif
7815 gen_addr_add(ctx, addr, addr, 4);
7816 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7817 }
7818
7819 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7820 {
7821 TCGv t0 = tcg_temp_new();
7822 #if defined(TARGET_PPC64)
7823 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7824 #else
7825 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7826 #endif
7827 gen_qemu_st16(ctx, t0, addr);
7828 gen_addr_add(ctx, addr, addr, 2);
7829 #if defined(TARGET_PPC64)
7830 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7831 gen_qemu_st16(ctx, t0, addr);
7832 #else
7833 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7834 #endif
7835 gen_addr_add(ctx, addr, addr, 2);
7836 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7837 gen_qemu_st16(ctx, t0, addr);
7838 tcg_temp_free(t0);
7839 gen_addr_add(ctx, addr, addr, 2);
7840 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7841 }
7842
7843 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7844 {
7845 TCGv t0 = tcg_temp_new();
7846 #if defined(TARGET_PPC64)
7847 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7848 #else
7849 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7850 #endif
7851 gen_qemu_st16(ctx, t0, addr);
7852 gen_addr_add(ctx, addr, addr, 2);
7853 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7854 gen_qemu_st16(ctx, t0, addr);
7855 tcg_temp_free(t0);
7856 }
7857
7858 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7859 {
7860 #if defined(TARGET_PPC64)
7861 TCGv t0 = tcg_temp_new();
7862 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7863 gen_qemu_st16(ctx, t0, addr);
7864 tcg_temp_free(t0);
7865 #else
7866 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7867 #endif
7868 gen_addr_add(ctx, addr, addr, 2);
7869 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7870 }
7871
7872 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7873 {
7874 #if defined(TARGET_PPC64)
7875 TCGv t0 = tcg_temp_new();
7876 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7877 gen_qemu_st32(ctx, t0, addr);
7878 tcg_temp_free(t0);
7879 #else
7880 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7881 #endif
7882 }
7883
7884 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7885 {
7886 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7887 }
7888
7889 #define GEN_SPEOP_LDST(name, opc2, sh) \
7890 static void glue(gen_, name)(DisasContext *ctx) \
7891 { \
7892 TCGv t0; \
7893 if (unlikely(!ctx->spe_enabled)) { \
7894 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7895 return; \
7896 } \
7897 gen_set_access_type(ctx, ACCESS_INT); \
7898 t0 = tcg_temp_new(); \
7899 if (Rc(ctx->opcode)) { \
7900 gen_addr_spe_imm_index(ctx, t0, sh); \
7901 } else { \
7902 gen_addr_reg_index(ctx, t0); \
7903 } \
7904 gen_op_##name(ctx, t0); \
7905 tcg_temp_free(t0); \
7906 }
7907
7908 GEN_SPEOP_LDST(evldd, 0x00, 3);
7909 GEN_SPEOP_LDST(evldw, 0x01, 3);
7910 GEN_SPEOP_LDST(evldh, 0x02, 3);
7911 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7912 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7913 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7914 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7915 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7916 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7917 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7918 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7919
7920 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7921 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7922 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7923 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7924 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7925 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7926 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7927
7928 /* Multiply and add - TODO */
7929 #if 0
7930 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7931 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7932 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7933 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7934 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7935 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7936 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7937 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7938 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7939 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7940 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7941 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7942
7943 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7944 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7945 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7946 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7947 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7948 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7949 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7950 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7951 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7952 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7953 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7954 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7955
7956 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7957 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7958 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7959 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7960 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7961
7962 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7963 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7964 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7965 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7966 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7967 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7968 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7969 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7970 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7971 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7972 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7973 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7974
7975 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7976 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7977 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7978 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7979
7980 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7981 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7982 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7983 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7984 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7985 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7986 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7987 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7988 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7989 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7990 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7991 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7992
7993 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7994 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7995 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7996 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7997 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7998 #endif
7999
8000 /*** SPE floating-point extension ***/
8001 #if defined(TARGET_PPC64)
8002 #define GEN_SPEFPUOP_CONV_32_32(name) \
8003 static inline void gen_##name(DisasContext *ctx) \
8004 { \
8005 TCGv_i32 t0; \
8006 TCGv t1; \
8007 t0 = tcg_temp_new_i32(); \
8008 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8009 gen_helper_##name(t0, cpu_env, t0); \
8010 t1 = tcg_temp_new(); \
8011 tcg_gen_extu_i32_tl(t1, t0); \
8012 tcg_temp_free_i32(t0); \
8013 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8014 0xFFFFFFFF00000000ULL); \
8015 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8016 tcg_temp_free(t1); \
8017 }
8018 #define GEN_SPEFPUOP_CONV_32_64(name) \
8019 static inline void gen_##name(DisasContext *ctx) \
8020 { \
8021 TCGv_i32 t0; \
8022 TCGv t1; \
8023 t0 = tcg_temp_new_i32(); \
8024 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8025 t1 = tcg_temp_new(); \
8026 tcg_gen_extu_i32_tl(t1, t0); \
8027 tcg_temp_free_i32(t0); \
8028 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8029 0xFFFFFFFF00000000ULL); \
8030 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8031 tcg_temp_free(t1); \
8032 }
8033 #define GEN_SPEFPUOP_CONV_64_32(name) \
8034 static inline void gen_##name(DisasContext *ctx) \
8035 { \
8036 TCGv_i32 t0 = tcg_temp_new_i32(); \
8037 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8038 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8039 tcg_temp_free_i32(t0); \
8040 }
8041 #define GEN_SPEFPUOP_CONV_64_64(name) \
8042 static inline void gen_##name(DisasContext *ctx) \
8043 { \
8044 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8045 cpu_gpr[rB(ctx->opcode)]); \
8046 }
8047 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8048 static inline void gen_##name(DisasContext *ctx) \
8049 { \
8050 TCGv_i32 t0, t1; \
8051 TCGv_i64 t2; \
8052 if (unlikely(!ctx->spe_enabled)) { \
8053 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8054 return; \
8055 } \
8056 t0 = tcg_temp_new_i32(); \
8057 t1 = tcg_temp_new_i32(); \
8058 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8059 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8060 gen_helper_##name(t0, cpu_env, t0, t1); \
8061 tcg_temp_free_i32(t1); \
8062 t2 = tcg_temp_new(); \
8063 tcg_gen_extu_i32_tl(t2, t0); \
8064 tcg_temp_free_i32(t0); \
8065 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8066 0xFFFFFFFF00000000ULL); \
8067 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8068 tcg_temp_free(t2); \
8069 }
8070 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8071 static inline void gen_##name(DisasContext *ctx) \
8072 { \
8073 if (unlikely(!ctx->spe_enabled)) { \
8074 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8075 return; \
8076 } \
8077 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8078 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8079 }
8080 #define GEN_SPEFPUOP_COMP_32(name) \
8081 static inline void gen_##name(DisasContext *ctx) \
8082 { \
8083 TCGv_i32 t0, t1; \
8084 if (unlikely(!ctx->spe_enabled)) { \
8085 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8086 return; \
8087 } \
8088 t0 = tcg_temp_new_i32(); \
8089 t1 = tcg_temp_new_i32(); \
8090 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8091 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8092 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8093 tcg_temp_free_i32(t0); \
8094 tcg_temp_free_i32(t1); \
8095 }
8096 #define GEN_SPEFPUOP_COMP_64(name) \
8097 static inline void gen_##name(DisasContext *ctx) \
8098 { \
8099 if (unlikely(!ctx->spe_enabled)) { \
8100 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8101 return; \
8102 } \
8103 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8104 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8105 }
8106 #else
8107 #define GEN_SPEFPUOP_CONV_32_32(name) \
8108 static inline void gen_##name(DisasContext *ctx) \
8109 { \
8110 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8111 cpu_gpr[rB(ctx->opcode)]); \
8112 }
8113 #define GEN_SPEFPUOP_CONV_32_64(name) \
8114 static inline void gen_##name(DisasContext *ctx) \
8115 { \
8116 TCGv_i64 t0 = tcg_temp_new_i64(); \
8117 gen_load_gpr64(t0, rB(ctx->opcode)); \
8118 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8119 tcg_temp_free_i64(t0); \
8120 }
8121 #define GEN_SPEFPUOP_CONV_64_32(name) \
8122 static inline void gen_##name(DisasContext *ctx) \
8123 { \
8124 TCGv_i64 t0 = tcg_temp_new_i64(); \
8125 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8126 gen_store_gpr64(rD(ctx->opcode), t0); \
8127 tcg_temp_free_i64(t0); \
8128 }
8129 #define GEN_SPEFPUOP_CONV_64_64(name) \
8130 static inline void gen_##name(DisasContext *ctx) \
8131 { \
8132 TCGv_i64 t0 = tcg_temp_new_i64(); \
8133 gen_load_gpr64(t0, rB(ctx->opcode)); \
8134 gen_helper_##name(t0, cpu_env, t0); \
8135 gen_store_gpr64(rD(ctx->opcode), t0); \
8136 tcg_temp_free_i64(t0); \
8137 }
8138 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8139 static inline void gen_##name(DisasContext *ctx) \
8140 { \
8141 if (unlikely(!ctx->spe_enabled)) { \
8142 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8143 return; \
8144 } \
8145 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8146 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8147 }
8148 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8149 static inline void gen_##name(DisasContext *ctx) \
8150 { \
8151 TCGv_i64 t0, t1; \
8152 if (unlikely(!ctx->spe_enabled)) { \
8153 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8154 return; \
8155 } \
8156 t0 = tcg_temp_new_i64(); \
8157 t1 = tcg_temp_new_i64(); \
8158 gen_load_gpr64(t0, rA(ctx->opcode)); \
8159 gen_load_gpr64(t1, rB(ctx->opcode)); \
8160 gen_helper_##name(t0, cpu_env, t0, t1); \
8161 gen_store_gpr64(rD(ctx->opcode), t0); \
8162 tcg_temp_free_i64(t0); \
8163 tcg_temp_free_i64(t1); \
8164 }
8165 #define GEN_SPEFPUOP_COMP_32(name) \
8166 static inline void gen_##name(DisasContext *ctx) \
8167 { \
8168 if (unlikely(!ctx->spe_enabled)) { \
8169 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8170 return; \
8171 } \
8172 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8173 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8174 }
8175 #define GEN_SPEFPUOP_COMP_64(name) \
8176 static inline void gen_##name(DisasContext *ctx) \
8177 { \
8178 TCGv_i64 t0, t1; \
8179 if (unlikely(!ctx->spe_enabled)) { \
8180 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8181 return; \
8182 } \
8183 t0 = tcg_temp_new_i64(); \
8184 t1 = tcg_temp_new_i64(); \
8185 gen_load_gpr64(t0, rA(ctx->opcode)); \
8186 gen_load_gpr64(t1, rB(ctx->opcode)); \
8187 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8188 tcg_temp_free_i64(t0); \
8189 tcg_temp_free_i64(t1); \
8190 }
8191 #endif
8192
8193 /* Single precision floating-point vectors operations */
8194 /* Arithmetic */
8195 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8196 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8197 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8198 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8199 static inline void gen_evfsabs(DisasContext *ctx)
8200 {
8201 if (unlikely(!ctx->spe_enabled)) {
8202 gen_exception(ctx, POWERPC_EXCP_SPEU);
8203 return;
8204 }
8205 #if defined(TARGET_PPC64)
8206 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8207 #else
8208 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8209 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8210 #endif
8211 }
8212 static inline void gen_evfsnabs(DisasContext *ctx)
8213 {
8214 if (unlikely(!ctx->spe_enabled)) {
8215 gen_exception(ctx, POWERPC_EXCP_SPEU);
8216 return;
8217 }
8218 #if defined(TARGET_PPC64)
8219 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8220 #else
8221 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8222 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8223 #endif
8224 }
8225 static inline void gen_evfsneg(DisasContext *ctx)
8226 {
8227 if (unlikely(!ctx->spe_enabled)) {
8228 gen_exception(ctx, POWERPC_EXCP_SPEU);
8229 return;
8230 }
8231 #if defined(TARGET_PPC64)
8232 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8233 #else
8234 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8235 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8236 #endif
8237 }
8238
8239 /* Conversion */
8240 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8241 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8242 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8243 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8244 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8245 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8246 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8247 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8248 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8249 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8250
8251 /* Comparison */
8252 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8253 GEN_SPEFPUOP_COMP_64(evfscmplt);
8254 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8255 GEN_SPEFPUOP_COMP_64(evfststgt);
8256 GEN_SPEFPUOP_COMP_64(evfststlt);
8257 GEN_SPEFPUOP_COMP_64(evfststeq);
8258
8259 /* Opcodes definitions */
8260 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8261 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8262 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8263 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8264 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8265 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8266 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8267 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8268 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8269 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8270 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8271 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8272 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8273 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8274
8275 /* Single precision floating-point operations */
8276 /* Arithmetic */
8277 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8278 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8279 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8280 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8281 static inline void gen_efsabs(DisasContext *ctx)
8282 {
8283 if (unlikely(!ctx->spe_enabled)) {
8284 gen_exception(ctx, POWERPC_EXCP_SPEU);
8285 return;
8286 }
8287 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8288 }
8289 static inline void gen_efsnabs(DisasContext *ctx)
8290 {
8291 if (unlikely(!ctx->spe_enabled)) {
8292 gen_exception(ctx, POWERPC_EXCP_SPEU);
8293 return;
8294 }
8295 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8296 }
8297 static inline void gen_efsneg(DisasContext *ctx)
8298 {
8299 if (unlikely(!ctx->spe_enabled)) {
8300 gen_exception(ctx, POWERPC_EXCP_SPEU);
8301 return;
8302 }
8303 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8304 }
8305
8306 /* Conversion */
8307 GEN_SPEFPUOP_CONV_32_32(efscfui);
8308 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8309 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8310 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8311 GEN_SPEFPUOP_CONV_32_32(efsctui);
8312 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8313 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8314 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8315 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8316 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8317 GEN_SPEFPUOP_CONV_32_64(efscfd);
8318
8319 /* Comparison */
8320 GEN_SPEFPUOP_COMP_32(efscmpgt);
8321 GEN_SPEFPUOP_COMP_32(efscmplt);
8322 GEN_SPEFPUOP_COMP_32(efscmpeq);
8323 GEN_SPEFPUOP_COMP_32(efststgt);
8324 GEN_SPEFPUOP_COMP_32(efststlt);
8325 GEN_SPEFPUOP_COMP_32(efststeq);
8326
8327 /* Opcodes definitions */
8328 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8329 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8330 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8331 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8332 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8333 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8334 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8335 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8336 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8337 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8338 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8339 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8340 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8341 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8342
8343 /* Double precision floating-point operations */
8344 /* Arithmetic */
8345 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8346 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8347 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8348 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8349 static inline void gen_efdabs(DisasContext *ctx)
8350 {
8351 if (unlikely(!ctx->spe_enabled)) {
8352 gen_exception(ctx, POWERPC_EXCP_SPEU);
8353 return;
8354 }
8355 #if defined(TARGET_PPC64)
8356 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8357 #else
8358 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8359 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8360 #endif
8361 }
8362 static inline void gen_efdnabs(DisasContext *ctx)
8363 {
8364 if (unlikely(!ctx->spe_enabled)) {
8365 gen_exception(ctx, POWERPC_EXCP_SPEU);
8366 return;
8367 }
8368 #if defined(TARGET_PPC64)
8369 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8370 #else
8371 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8372 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8373 #endif
8374 }
8375 static inline void gen_efdneg(DisasContext *ctx)
8376 {
8377 if (unlikely(!ctx->spe_enabled)) {
8378 gen_exception(ctx, POWERPC_EXCP_SPEU);
8379 return;
8380 }
8381 #if defined(TARGET_PPC64)
8382 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8383 #else
8384 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8385 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8386 #endif
8387 }
8388
8389 /* Conversion */
8390 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8391 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8392 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8393 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8394 GEN_SPEFPUOP_CONV_32_64(efdctui);
8395 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8396 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8397 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8398 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8399 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8400 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8401 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8402 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8403 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8404 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8405
8406 /* Comparison */
8407 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8408 GEN_SPEFPUOP_COMP_64(efdcmplt);
8409 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8410 GEN_SPEFPUOP_COMP_64(efdtstgt);
8411 GEN_SPEFPUOP_COMP_64(efdtstlt);
8412 GEN_SPEFPUOP_COMP_64(efdtsteq);
8413
8414 /* Opcodes definitions */
8415 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8416 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8417 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8418 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8419 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8420 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8421 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8422 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8423 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8424 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8425 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8426 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8427 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8428 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8429 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8430 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8431
8432 static opcode_t opcodes[] = {
8433 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8434 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8435 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8436 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8437 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8438 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8439 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8440 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8441 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8442 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8443 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8444 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8445 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8446 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8447 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8448 #if defined(TARGET_PPC64)
8449 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8450 #endif
8451 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8452 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8453 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8454 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8455 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8456 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8457 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8458 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8459 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8460 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8461 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8462 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8463 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8464 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8465 #if defined(TARGET_PPC64)
8466 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8467 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8468 #endif
8469 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8470 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8471 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8472 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8473 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8474 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8475 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8476 #if defined(TARGET_PPC64)
8477 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8478 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8479 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8480 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8481 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8482 #endif
8483 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8484 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8485 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8486 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8487 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8488 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8489 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8490 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8491 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8492 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8493 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8494 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8495 #if defined(TARGET_PPC64)
8496 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8497 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8498 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8499 #endif
8500 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8501 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8502 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8503 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8504 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8505 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8506 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8507 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8508 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8509 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8510 #if defined(TARGET_PPC64)
8511 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8512 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8513 #endif
8514 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8515 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8516 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8517 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8518 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8519 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8520 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8521 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8522 #if defined(TARGET_PPC64)
8523 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8524 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8525 #endif
8526 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8527 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8528 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8529 #if defined(TARGET_PPC64)
8530 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8531 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8532 #endif
8533 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8534 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8535 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8536 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8537 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8538 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8539 #if defined(TARGET_PPC64)
8540 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8541 #endif
8542 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8543 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8544 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8545 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8546 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8547 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8548 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8549 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8550 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8551 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8552 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8553 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8554 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8555 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8556 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8557 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8558 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8559 #if defined(TARGET_PPC64)
8560 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8561 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8562 PPC_SEGMENT_64B),
8563 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8564 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8565 PPC_SEGMENT_64B),
8566 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8567 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8568 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8569 #endif
8570 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8571 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8572 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8573 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8574 #if defined(TARGET_PPC64)
8575 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8576 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8577 #endif
8578 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8579 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8580 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8581 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8582 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8583 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8584 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8585 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8586 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8587 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8588 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8589 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8590 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8591 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8592 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8593 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8594 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8595 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8596 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8597 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8598 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8599 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8600 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8601 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8602 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8603 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8604 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8605 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8606 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8607 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8608 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8609 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8610 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8611 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8612 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8613 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8614 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8615 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8616 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8617 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8618 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8619 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8620 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8621 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8622 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8623 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8624 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8625 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8626 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8627 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8628 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8629 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8630 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8631 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8632 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8633 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8634 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8635 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8636 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8637 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8638 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8639 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8640 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8641 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8642 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8643 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8644 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8645 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8646 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8647 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8648 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8649 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8650 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8651 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8652 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8653 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8654 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8655 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8656 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8657 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8658 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8659 PPC_NONE, PPC2_BOOKE206),
8660 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8661 PPC_NONE, PPC2_BOOKE206),
8662 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8663 PPC_NONE, PPC2_BOOKE206),
8664 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8665 PPC_NONE, PPC2_BOOKE206),
8666 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8667 PPC_NONE, PPC2_BOOKE206),
8668 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8669 PPC_NONE, PPC2_PRCNTL),
8670 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8671 PPC_NONE, PPC2_PRCNTL),
8672 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8673 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8674 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8675 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8676 PPC_BOOKE, PPC2_BOOKE206),
8677 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8678 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8679 PPC_BOOKE, PPC2_BOOKE206),
8680 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8681 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8682 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8683 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8684 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8685 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8686 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8687 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8688 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8689 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8690
8691 #undef GEN_INT_ARITH_ADD
8692 #undef GEN_INT_ARITH_ADD_CONST
8693 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8694 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8695 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8696 add_ca, compute_ca, compute_ov) \
8697 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8698 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8699 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8700 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8701 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8702 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8703 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8704 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8705 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8706 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8707 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8708
8709 #undef GEN_INT_ARITH_DIVW
8710 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8711 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8712 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8713 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8714 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8715 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8716
8717 #if defined(TARGET_PPC64)
8718 #undef GEN_INT_ARITH_DIVD
8719 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8720 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8721 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8722 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8723 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8724 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8725
8726 #undef GEN_INT_ARITH_MUL_HELPER
8727 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8728 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8729 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8730 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8731 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8732 #endif
8733
8734 #undef GEN_INT_ARITH_SUBF
8735 #undef GEN_INT_ARITH_SUBF_CONST
8736 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8737 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8738 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8739 add_ca, compute_ca, compute_ov) \
8740 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8741 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8742 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8743 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8744 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8745 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8746 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8747 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8748 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8749 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8750 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8751
8752 #undef GEN_LOGICAL1
8753 #undef GEN_LOGICAL2
8754 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8755 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8756 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8757 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8758 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8759 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8760 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8761 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8762 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8763 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8764 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8765 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8766 #if defined(TARGET_PPC64)
8767 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8768 #endif
8769
8770 #if defined(TARGET_PPC64)
8771 #undef GEN_PPC64_R2
8772 #undef GEN_PPC64_R4
8773 #define GEN_PPC64_R2(name, opc1, opc2) \
8774 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8775 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8776 PPC_64B)
8777 #define GEN_PPC64_R4(name, opc1, opc2) \
8778 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8779 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8780 PPC_64B), \
8781 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8782 PPC_64B), \
8783 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8784 PPC_64B)
8785 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8786 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8787 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8788 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8789 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8790 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8791 #endif
8792
8793 #undef _GEN_FLOAT_ACB
8794 #undef GEN_FLOAT_ACB
8795 #undef _GEN_FLOAT_AB
8796 #undef GEN_FLOAT_AB
8797 #undef _GEN_FLOAT_AC
8798 #undef GEN_FLOAT_AC
8799 #undef GEN_FLOAT_B
8800 #undef GEN_FLOAT_BS
8801 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8802 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8803 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8804 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8805 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8806 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8807 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8808 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8809 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8810 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8811 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8812 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8813 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8814 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8815 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8816 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8817 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8818 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8819 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8820
8821 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8822 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8823 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8824 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8825 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8826 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8827 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8828 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8829 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8830 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8831 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8832 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8833 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8834 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8835 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8836 #if defined(TARGET_PPC64)
8837 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8838 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8839 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8840 #endif
8841 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8842 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8843 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8844 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8845 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8846 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8847 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8848
8849 #undef GEN_LD
8850 #undef GEN_LDU
8851 #undef GEN_LDUX
8852 #undef GEN_LDX_E
8853 #undef GEN_LDS
8854 #define GEN_LD(name, ldop, opc, type) \
8855 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8856 #define GEN_LDU(name, ldop, opc, type) \
8857 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8858 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8859 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8860 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8861 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8862 #define GEN_LDS(name, ldop, op, type) \
8863 GEN_LD(name, ldop, op | 0x20, type) \
8864 GEN_LDU(name, ldop, op | 0x21, type) \
8865 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8866 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8867
8868 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8869 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8870 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8871 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8872 #if defined(TARGET_PPC64)
8873 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8874 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8875 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8876 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8877 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8878 #endif
8879 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8880 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8881
8882 #undef GEN_ST
8883 #undef GEN_STU
8884 #undef GEN_STUX
8885 #undef GEN_STX_E
8886 #undef GEN_STS
8887 #define GEN_ST(name, stop, opc, type) \
8888 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8889 #define GEN_STU(name, stop, opc, type) \
8890 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8891 #define GEN_STUX(name, stop, opc2, opc3, type) \
8892 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8893 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8894 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8895 #define GEN_STS(name, stop, op, type) \
8896 GEN_ST(name, stop, op | 0x20, type) \
8897 GEN_STU(name, stop, op | 0x21, type) \
8898 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8899 GEN_STX(name, stop, 0x17, op | 0x00, type)
8900
8901 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8902 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8903 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8904 #if defined(TARGET_PPC64)
8905 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8906 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8907 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8908 #endif
8909 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8910 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8911
8912 #undef GEN_LDF
8913 #undef GEN_LDUF
8914 #undef GEN_LDUXF
8915 #undef GEN_LDXF
8916 #undef GEN_LDFS
8917 #define GEN_LDF(name, ldop, opc, type) \
8918 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8919 #define GEN_LDUF(name, ldop, opc, type) \
8920 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8921 #define GEN_LDUXF(name, ldop, opc, type) \
8922 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8923 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8924 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8925 #define GEN_LDFS(name, ldop, op, type) \
8926 GEN_LDF(name, ldop, op | 0x20, type) \
8927 GEN_LDUF(name, ldop, op | 0x21, type) \
8928 GEN_LDUXF(name, ldop, op | 0x01, type) \
8929 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8930
8931 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8932 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8933
8934 #undef GEN_STF
8935 #undef GEN_STUF
8936 #undef GEN_STUXF
8937 #undef GEN_STXF
8938 #undef GEN_STFS
8939 #define GEN_STF(name, stop, opc, type) \
8940 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8941 #define GEN_STUF(name, stop, opc, type) \
8942 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8943 #define GEN_STUXF(name, stop, opc, type) \
8944 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8945 #define GEN_STXF(name, stop, opc2, opc3, type) \
8946 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8947 #define GEN_STFS(name, stop, op, type) \
8948 GEN_STF(name, stop, op | 0x20, type) \
8949 GEN_STUF(name, stop, op | 0x21, type) \
8950 GEN_STUXF(name, stop, op | 0x01, type) \
8951 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8952
8953 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8954 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8955 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8956
8957 #undef GEN_CRLOGIC
8958 #define GEN_CRLOGIC(name, tcg_op, opc) \
8959 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8960 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8961 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8962 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8963 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8964 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8965 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8966 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8967 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8968
8969 #undef GEN_MAC_HANDLER
8970 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8971 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8972 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8973 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8974 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8975 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8976 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8977 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8978 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8979 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8980 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8981 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8982 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8983 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8984 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8985 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8986 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8987 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8988 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8989 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8990 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8991 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8992 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8993 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8994 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8995 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8996 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8997 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8998 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8999 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9000 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9001 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9002 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9003 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9004 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9005 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9006 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9007 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9008 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9009 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9010 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9011 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9012 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9013 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9014
9015 #undef GEN_VR_LDX
9016 #undef GEN_VR_STX
9017 #undef GEN_VR_LVE
9018 #undef GEN_VR_STVE
9019 #define GEN_VR_LDX(name, opc2, opc3) \
9020 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9021 #define GEN_VR_STX(name, opc2, opc3) \
9022 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9023 #define GEN_VR_LVE(name, opc2, opc3) \
9024 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9025 #define GEN_VR_STVE(name, opc2, opc3) \
9026 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9027 GEN_VR_LDX(lvx, 0x07, 0x03),
9028 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9029 GEN_VR_LVE(bx, 0x07, 0x00),
9030 GEN_VR_LVE(hx, 0x07, 0x01),
9031 GEN_VR_LVE(wx, 0x07, 0x02),
9032 GEN_VR_STX(svx, 0x07, 0x07),
9033 GEN_VR_STX(svxl, 0x07, 0x0F),
9034 GEN_VR_STVE(bx, 0x07, 0x04),
9035 GEN_VR_STVE(hx, 0x07, 0x05),
9036 GEN_VR_STVE(wx, 0x07, 0x06),
9037
9038 #undef GEN_VX_LOGICAL
9039 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9040 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9041 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9042 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9043 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9044 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9045 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9046
9047 #undef GEN_VXFORM
9048 #define GEN_VXFORM(name, opc2, opc3) \
9049 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9050 GEN_VXFORM(vaddubm, 0, 0),
9051 GEN_VXFORM(vadduhm, 0, 1),
9052 GEN_VXFORM(vadduwm, 0, 2),
9053 GEN_VXFORM(vsububm, 0, 16),
9054 GEN_VXFORM(vsubuhm, 0, 17),
9055 GEN_VXFORM(vsubuwm, 0, 18),
9056 GEN_VXFORM(vmaxub, 1, 0),
9057 GEN_VXFORM(vmaxuh, 1, 1),
9058 GEN_VXFORM(vmaxuw, 1, 2),
9059 GEN_VXFORM(vmaxsb, 1, 4),
9060 GEN_VXFORM(vmaxsh, 1, 5),
9061 GEN_VXFORM(vmaxsw, 1, 6),
9062 GEN_VXFORM(vminub, 1, 8),
9063 GEN_VXFORM(vminuh, 1, 9),
9064 GEN_VXFORM(vminuw, 1, 10),
9065 GEN_VXFORM(vminsb, 1, 12),
9066 GEN_VXFORM(vminsh, 1, 13),
9067 GEN_VXFORM(vminsw, 1, 14),
9068 GEN_VXFORM(vavgub, 1, 16),
9069 GEN_VXFORM(vavguh, 1, 17),
9070 GEN_VXFORM(vavguw, 1, 18),
9071 GEN_VXFORM(vavgsb, 1, 20),
9072 GEN_VXFORM(vavgsh, 1, 21),
9073 GEN_VXFORM(vavgsw, 1, 22),
9074 GEN_VXFORM(vmrghb, 6, 0),
9075 GEN_VXFORM(vmrghh, 6, 1),
9076 GEN_VXFORM(vmrghw, 6, 2),
9077 GEN_VXFORM(vmrglb, 6, 4),
9078 GEN_VXFORM(vmrglh, 6, 5),
9079 GEN_VXFORM(vmrglw, 6, 6),
9080 GEN_VXFORM(vmuloub, 4, 0),
9081 GEN_VXFORM(vmulouh, 4, 1),
9082 GEN_VXFORM(vmulosb, 4, 4),
9083 GEN_VXFORM(vmulosh, 4, 5),
9084 GEN_VXFORM(vmuleub, 4, 8),
9085 GEN_VXFORM(vmuleuh, 4, 9),
9086 GEN_VXFORM(vmulesb, 4, 12),
9087 GEN_VXFORM(vmulesh, 4, 13),
9088 GEN_VXFORM(vslb, 2, 4),
9089 GEN_VXFORM(vslh, 2, 5),
9090 GEN_VXFORM(vslw, 2, 6),
9091 GEN_VXFORM(vsrb, 2, 8),
9092 GEN_VXFORM(vsrh, 2, 9),
9093 GEN_VXFORM(vsrw, 2, 10),
9094 GEN_VXFORM(vsrab, 2, 12),
9095 GEN_VXFORM(vsrah, 2, 13),
9096 GEN_VXFORM(vsraw, 2, 14),
9097 GEN_VXFORM(vslo, 6, 16),
9098 GEN_VXFORM(vsro, 6, 17),
9099 GEN_VXFORM(vaddcuw, 0, 6),
9100 GEN_VXFORM(vsubcuw, 0, 22),
9101 GEN_VXFORM(vaddubs, 0, 8),
9102 GEN_VXFORM(vadduhs, 0, 9),
9103 GEN_VXFORM(vadduws, 0, 10),
9104 GEN_VXFORM(vaddsbs, 0, 12),
9105 GEN_VXFORM(vaddshs, 0, 13),
9106 GEN_VXFORM(vaddsws, 0, 14),
9107 GEN_VXFORM(vsububs, 0, 24),
9108 GEN_VXFORM(vsubuhs, 0, 25),
9109 GEN_VXFORM(vsubuws, 0, 26),
9110 GEN_VXFORM(vsubsbs, 0, 28),
9111 GEN_VXFORM(vsubshs, 0, 29),
9112 GEN_VXFORM(vsubsws, 0, 30),
9113 GEN_VXFORM(vrlb, 2, 0),
9114 GEN_VXFORM(vrlh, 2, 1),
9115 GEN_VXFORM(vrlw, 2, 2),
9116 GEN_VXFORM(vsl, 2, 7),
9117 GEN_VXFORM(vsr, 2, 11),
9118 GEN_VXFORM(vpkuhum, 7, 0),
9119 GEN_VXFORM(vpkuwum, 7, 1),
9120 GEN_VXFORM(vpkuhus, 7, 2),
9121 GEN_VXFORM(vpkuwus, 7, 3),
9122 GEN_VXFORM(vpkshus, 7, 4),
9123 GEN_VXFORM(vpkswus, 7, 5),
9124 GEN_VXFORM(vpkshss, 7, 6),
9125 GEN_VXFORM(vpkswss, 7, 7),
9126 GEN_VXFORM(vpkpx, 7, 12),
9127 GEN_VXFORM(vsum4ubs, 4, 24),
9128 GEN_VXFORM(vsum4sbs, 4, 28),
9129 GEN_VXFORM(vsum4shs, 4, 25),
9130 GEN_VXFORM(vsum2sws, 4, 26),
9131 GEN_VXFORM(vsumsws, 4, 30),
9132 GEN_VXFORM(vaddfp, 5, 0),
9133 GEN_VXFORM(vsubfp, 5, 1),
9134 GEN_VXFORM(vmaxfp, 5, 16),
9135 GEN_VXFORM(vminfp, 5, 17),
9136
9137 #undef GEN_VXRFORM1
9138 #undef GEN_VXRFORM
9139 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9140 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9141 #define GEN_VXRFORM(name, opc2, opc3) \
9142 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9143 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9144 GEN_VXRFORM(vcmpequb, 3, 0)
9145 GEN_VXRFORM(vcmpequh, 3, 1)
9146 GEN_VXRFORM(vcmpequw, 3, 2)
9147 GEN_VXRFORM(vcmpgtsb, 3, 12)
9148 GEN_VXRFORM(vcmpgtsh, 3, 13)
9149 GEN_VXRFORM(vcmpgtsw, 3, 14)
9150 GEN_VXRFORM(vcmpgtub, 3, 8)
9151 GEN_VXRFORM(vcmpgtuh, 3, 9)
9152 GEN_VXRFORM(vcmpgtuw, 3, 10)
9153 GEN_VXRFORM(vcmpeqfp, 3, 3)
9154 GEN_VXRFORM(vcmpgefp, 3, 7)
9155 GEN_VXRFORM(vcmpgtfp, 3, 11)
9156 GEN_VXRFORM(vcmpbfp, 3, 15)
9157
9158 #undef GEN_VXFORM_SIMM
9159 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9160 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9161 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9162 GEN_VXFORM_SIMM(vspltish, 6, 13),
9163 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9164
9165 #undef GEN_VXFORM_NOA
9166 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9167 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9168 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9169 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9170 GEN_VXFORM_NOA(vupklsb, 7, 10),
9171 GEN_VXFORM_NOA(vupklsh, 7, 11),
9172 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9173 GEN_VXFORM_NOA(vupklpx, 7, 15),
9174 GEN_VXFORM_NOA(vrefp, 5, 4),
9175 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9176 GEN_VXFORM_NOA(vexptefp, 5, 6),
9177 GEN_VXFORM_NOA(vlogefp, 5, 7),
9178 GEN_VXFORM_NOA(vrfim, 5, 8),
9179 GEN_VXFORM_NOA(vrfin, 5, 9),
9180 GEN_VXFORM_NOA(vrfip, 5, 10),
9181 GEN_VXFORM_NOA(vrfiz, 5, 11),
9182
9183 #undef GEN_VXFORM_UIMM
9184 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9185 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9186 GEN_VXFORM_UIMM(vspltb, 6, 8),
9187 GEN_VXFORM_UIMM(vsplth, 6, 9),
9188 GEN_VXFORM_UIMM(vspltw, 6, 10),
9189 GEN_VXFORM_UIMM(vcfux, 5, 12),
9190 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9191 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9192 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9193
9194 #undef GEN_VAFORM_PAIRED
9195 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9196 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9197 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9198 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9199 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9200 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9201 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9202 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9203
9204 #undef GEN_SPE
9205 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9206 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9207 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9208 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9209 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9210 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9211 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9212 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9213 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9214 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9215 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9216 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9217 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9218 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9219 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9220 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9221 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9222 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9223 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9224 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9225 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9226 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9227 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9228 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9229 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9230 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9231 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9232 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9233 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9234 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9235 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9236
9237 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9238 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9239 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9240 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9241 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9242 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9243 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9244 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9245 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9246 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9247 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9248 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9249 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9250 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9251
9252 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9253 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9254 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9255 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9256 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9257 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9258 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9259 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9260 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9261 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9262 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9263 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9264 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9265 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9266
9267 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9268 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9269 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9270 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9271 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9272 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9273 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9274 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9275 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9276 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9277 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9278 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9279 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9280 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9281 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9282 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9283
9284 #undef GEN_SPEOP_LDST
9285 #define GEN_SPEOP_LDST(name, opc2, sh) \
9286 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9287 GEN_SPEOP_LDST(evldd, 0x00, 3),
9288 GEN_SPEOP_LDST(evldw, 0x01, 3),
9289 GEN_SPEOP_LDST(evldh, 0x02, 3),
9290 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9291 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9292 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9293 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9294 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9295 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9296 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9297 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9298
9299 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9300 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9301 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9302 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9303 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9304 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9305 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9306 };
9307
9308 #include "helper_regs.h"
9309 #include "translate_init.c"
9310
9311 /*****************************************************************************/
9312 /* Misc PowerPC helpers */
9313 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9314 int flags)
9315 {
9316 #define RGPL 4
9317 #define RFPL 4
9318
9319 int i;
9320
9321 cpu_synchronize_state(env);
9322
9323 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9324 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9325 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9326 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9327 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9328 env->hflags, env->mmu_idx);
9329 #if !defined(NO_TIMER_DUMP)
9330 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9331 #if !defined(CONFIG_USER_ONLY)
9332 " DECR %08" PRIu32
9333 #endif
9334 "\n",
9335 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9336 #if !defined(CONFIG_USER_ONLY)
9337 , cpu_ppc_load_decr(env)
9338 #endif
9339 );
9340 #endif
9341 for (i = 0; i < 32; i++) {
9342 if ((i & (RGPL - 1)) == 0)
9343 cpu_fprintf(f, "GPR%02d", i);
9344 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9345 if ((i & (RGPL - 1)) == (RGPL - 1))
9346 cpu_fprintf(f, "\n");
9347 }
9348 cpu_fprintf(f, "CR ");
9349 for (i = 0; i < 8; i++)
9350 cpu_fprintf(f, "%01x", env->crf[i]);
9351 cpu_fprintf(f, " [");
9352 for (i = 0; i < 8; i++) {
9353 char a = '-';
9354 if (env->crf[i] & 0x08)
9355 a = 'L';
9356 else if (env->crf[i] & 0x04)
9357 a = 'G';
9358 else if (env->crf[i] & 0x02)
9359 a = 'E';
9360 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9361 }
9362 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9363 env->reserve_addr);
9364 for (i = 0; i < 32; i++) {
9365 if ((i & (RFPL - 1)) == 0)
9366 cpu_fprintf(f, "FPR%02d", i);
9367 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9368 if ((i & (RFPL - 1)) == (RFPL - 1))
9369 cpu_fprintf(f, "\n");
9370 }
9371 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9372 #if !defined(CONFIG_USER_ONLY)
9373 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9374 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9375 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9376 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9377
9378 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9379 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9380 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9381 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9382
9383 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9384 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9385 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9386 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9387
9388 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9389 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9390 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9391 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9392 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9393
9394 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9395 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9396 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9397 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9398
9399 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9400 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9401 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9402 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9403
9404 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9405 " EPR " TARGET_FMT_lx "\n",
9406 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9407 env->spr[SPR_BOOKE_EPR]);
9408
9409 /* FSL-specific */
9410 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9411 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9412 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9413 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9414
9415 /*
9416 * IVORs are left out as they are large and do not change often --
9417 * they can be read with "p $ivor0", "p $ivor1", etc.
9418 */
9419 }
9420
9421 #if defined(TARGET_PPC64)
9422 if (env->flags & POWERPC_FLAG_CFAR) {
9423 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9424 }
9425 #endif
9426
9427 switch (env->mmu_model) {
9428 case POWERPC_MMU_32B:
9429 case POWERPC_MMU_601:
9430 case POWERPC_MMU_SOFT_6xx:
9431 case POWERPC_MMU_SOFT_74xx:
9432 #if defined(TARGET_PPC64)
9433 case POWERPC_MMU_64B:
9434 #endif
9435 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9436 break;
9437 case POWERPC_MMU_BOOKE206:
9438 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9439 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9440 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9441 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9442
9443 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9444 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9445 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9446 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9447
9448 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9449 " TLB1CFG " TARGET_FMT_lx "\n",
9450 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9451 env->spr[SPR_BOOKE_TLB1CFG]);
9452 break;
9453 default:
9454 break;
9455 }
9456 #endif
9457
9458 #undef RGPL
9459 #undef RFPL
9460 }
9461
9462 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9463 int flags)
9464 {
9465 #if defined(DO_PPC_STATISTICS)
9466 opc_handler_t **t1, **t2, **t3, *handler;
9467 int op1, op2, op3;
9468
9469 t1 = env->opcodes;
9470 for (op1 = 0; op1 < 64; op1++) {
9471 handler = t1[op1];
9472 if (is_indirect_opcode(handler)) {
9473 t2 = ind_table(handler);
9474 for (op2 = 0; op2 < 32; op2++) {
9475 handler = t2[op2];
9476 if (is_indirect_opcode(handler)) {
9477 t3 = ind_table(handler);
9478 for (op3 = 0; op3 < 32; op3++) {
9479 handler = t3[op3];
9480 if (handler->count == 0)
9481 continue;
9482 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9483 "%016" PRIx64 " %" PRId64 "\n",
9484 op1, op2, op3, op1, (op3 << 5) | op2,
9485 handler->oname,
9486 handler->count, handler->count);
9487 }
9488 } else {
9489 if (handler->count == 0)
9490 continue;
9491 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9492 "%016" PRIx64 " %" PRId64 "\n",
9493 op1, op2, op1, op2, handler->oname,
9494 handler->count, handler->count);
9495 }
9496 }
9497 } else {
9498 if (handler->count == 0)
9499 continue;
9500 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9501 " %" PRId64 "\n",
9502 op1, op1, handler->oname,
9503 handler->count, handler->count);
9504 }
9505 }
9506 #endif
9507 }
9508
9509 /*****************************************************************************/
9510 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9511 TranslationBlock *tb,
9512 int search_pc)
9513 {
9514 DisasContext ctx, *ctxp = &ctx;
9515 opc_handler_t **table, *handler;
9516 target_ulong pc_start;
9517 uint16_t *gen_opc_end;
9518 CPUBreakpoint *bp;
9519 int j, lj = -1;
9520 int num_insns;
9521 int max_insns;
9522
9523 pc_start = tb->pc;
9524 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9525 ctx.nip = pc_start;
9526 ctx.tb = tb;
9527 ctx.exception = POWERPC_EXCP_NONE;
9528 ctx.spr_cb = env->spr_cb;
9529 ctx.mem_idx = env->mmu_idx;
9530 ctx.access_type = -1;
9531 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9532 #if defined(TARGET_PPC64)
9533 ctx.sf_mode = msr_is_64bit(env, env->msr);
9534 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9535 #endif
9536 ctx.fpu_enabled = msr_fp;
9537 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9538 ctx.spe_enabled = msr_spe;
9539 else
9540 ctx.spe_enabled = 0;
9541 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9542 ctx.altivec_enabled = msr_vr;
9543 else
9544 ctx.altivec_enabled = 0;
9545 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9546 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9547 else
9548 ctx.singlestep_enabled = 0;
9549 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9550 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9551 if (unlikely(env->singlestep_enabled))
9552 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9553 #if defined (DO_SINGLE_STEP) && 0
9554 /* Single step trace mode */
9555 msr_se = 1;
9556 #endif
9557 num_insns = 0;
9558 max_insns = tb->cflags & CF_COUNT_MASK;
9559 if (max_insns == 0)
9560 max_insns = CF_COUNT_MASK;
9561
9562 gen_tb_start();
9563 /* Set env in case of segfault during code fetch */
9564 while (ctx.exception == POWERPC_EXCP_NONE
9565 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9566 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9567 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9568 if (bp->pc == ctx.nip) {
9569 gen_debug_exception(ctxp);
9570 break;
9571 }
9572 }
9573 }
9574 if (unlikely(search_pc)) {
9575 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9576 if (lj < j) {
9577 lj++;
9578 while (lj < j)
9579 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9580 }
9581 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9582 tcg_ctx.gen_opc_instr_start[lj] = 1;
9583 tcg_ctx.gen_opc_icount[lj] = num_insns;
9584 }
9585 LOG_DISAS("----------------\n");
9586 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9587 ctx.nip, ctx.mem_idx, (int)msr_ir);
9588 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9589 gen_io_start();
9590 if (unlikely(ctx.le_mode)) {
9591 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9592 } else {
9593 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9594 }
9595 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9596 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9597 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9598 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9599 tcg_gen_debug_insn_start(ctx.nip);
9600 }
9601 ctx.nip += 4;
9602 table = env->opcodes;
9603 num_insns++;
9604 handler = table[opc1(ctx.opcode)];
9605 if (is_indirect_opcode(handler)) {
9606 table = ind_table(handler);
9607 handler = table[opc2(ctx.opcode)];
9608 if (is_indirect_opcode(handler)) {
9609 table = ind_table(handler);
9610 handler = table[opc3(ctx.opcode)];
9611 }
9612 }
9613 /* Is opcode *REALLY* valid ? */
9614 if (unlikely(handler->handler == &gen_invalid)) {
9615 if (qemu_log_enabled()) {
9616 qemu_log("invalid/unsupported opcode: "
9617 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9618 opc1(ctx.opcode), opc2(ctx.opcode),
9619 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9620 }
9621 } else {
9622 uint32_t inval;
9623
9624 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9625 inval = handler->inval2;
9626 } else {
9627 inval = handler->inval1;
9628 }
9629
9630 if (unlikely((ctx.opcode & inval) != 0)) {
9631 if (qemu_log_enabled()) {
9632 qemu_log("invalid bits: %08x for opcode: "
9633 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9634 ctx.opcode & inval, opc1(ctx.opcode),
9635 opc2(ctx.opcode), opc3(ctx.opcode),
9636 ctx.opcode, ctx.nip - 4);
9637 }
9638 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9639 break;
9640 }
9641 }
9642 (*(handler->handler))(&ctx);
9643 #if defined(DO_PPC_STATISTICS)
9644 handler->count++;
9645 #endif
9646 /* Check trace mode exceptions */
9647 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9648 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9649 ctx.exception != POWERPC_SYSCALL &&
9650 ctx.exception != POWERPC_EXCP_TRAP &&
9651 ctx.exception != POWERPC_EXCP_BRANCH)) {
9652 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9653 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9654 (env->singlestep_enabled) ||
9655 singlestep ||
9656 num_insns >= max_insns)) {
9657 /* if we reach a page boundary or are single stepping, stop
9658 * generation
9659 */
9660 break;
9661 }
9662 }
9663 if (tb->cflags & CF_LAST_IO)
9664 gen_io_end();
9665 if (ctx.exception == POWERPC_EXCP_NONE) {
9666 gen_goto_tb(&ctx, 0, ctx.nip);
9667 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9668 if (unlikely(env->singlestep_enabled)) {
9669 gen_debug_exception(ctxp);
9670 }
9671 /* Generate the return instruction */
9672 tcg_gen_exit_tb(0);
9673 }
9674 gen_tb_end(tb, num_insns);
9675 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9676 if (unlikely(search_pc)) {
9677 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9678 lj++;
9679 while (lj <= j)
9680 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9681 } else {
9682 tb->size = ctx.nip - pc_start;
9683 tb->icount = num_insns;
9684 }
9685 #if defined(DEBUG_DISAS)
9686 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9687 int flags;
9688 flags = env->bfd_mach;
9689 flags |= ctx.le_mode << 16;
9690 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9691 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9692 qemu_log("\n");
9693 }
9694 #endif
9695 }
9696
9697 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9698 {
9699 gen_intermediate_code_internal(env, tb, 0);
9700 }
9701
9702 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9703 {
9704 gen_intermediate_code_internal(env, tb, 1);
9705 }
9706
9707 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9708 {
9709 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9710 }
Qemu copy for testing