2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
30 #include "qemu-common.h"
31 #include "host-utils.h"
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
41 /* Include definitions for instructions classes and implementations flags */
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
48 # define LOG_DISAS(...) do { } while (0)
50 /*****************************************************************************/
51 /* Code translation helpers */
53 /* global register indexes */
54 static TCGv_ptr cpu_env
;
55 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
56 #if !defined(TARGET_PPC64)
57 + 10*4 + 22*5 /* SPE GPRh */
59 + 10*4 + 22*5 /* FPR */
60 + 2*(10*6 + 22*7) /* AVRh, AVRl */
62 static TCGv cpu_gpr
[32];
63 #if !defined(TARGET_PPC64)
64 static TCGv cpu_gprh
[32];
66 static TCGv_i64 cpu_fpr
[32];
67 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
68 static TCGv_i32 cpu_crf
[8];
74 static TCGv cpu_reserve
;
75 static TCGv_i32 cpu_fpscr
;
76 static TCGv_i32 cpu_access_type
;
78 #include "gen-icount.h"
80 void ppc_translate_init(void)
84 size_t cpu_reg_names_size
;
85 static int done_init
= 0;
90 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
93 cpu_reg_names_size
= sizeof(cpu_reg_names
);
95 for (i
= 0; i
< 8; i
++) {
96 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
97 cpu_crf
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
98 offsetof(CPUState
, crf
[i
]), p
);
100 cpu_reg_names_size
-= 5;
103 for (i
= 0; i
< 32; i
++) {
104 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
105 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
106 offsetof(CPUState
, gpr
[i
]), p
);
107 p
+= (i
< 10) ? 3 : 4;
108 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
109 #if !defined(TARGET_PPC64)
110 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
111 cpu_gprh
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
112 offsetof(CPUState
, gprh
[i
]), p
);
113 p
+= (i
< 10) ? 4 : 5;
114 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
117 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
118 cpu_fpr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
119 offsetof(CPUState
, fpr
[i
]), p
);
120 p
+= (i
< 10) ? 4 : 5;
121 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
123 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
124 #ifdef WORDS_BIGENDIAN
125 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
126 offsetof(CPUState
, avr
[i
].u64
[0]), p
);
128 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
129 offsetof(CPUState
, avr
[i
].u64
[1]), p
);
131 p
+= (i
< 10) ? 6 : 7;
132 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
134 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
135 #ifdef WORDS_BIGENDIAN
136 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
137 offsetof(CPUState
, avr
[i
].u64
[1]), p
);
139 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
140 offsetof(CPUState
, avr
[i
].u64
[0]), p
);
142 p
+= (i
< 10) ? 6 : 7;
143 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
146 cpu_nip
= tcg_global_mem_new(TCG_AREG0
,
147 offsetof(CPUState
, nip
), "nip");
149 cpu_msr
= tcg_global_mem_new(TCG_AREG0
,
150 offsetof(CPUState
, msr
), "msr");
152 cpu_ctr
= tcg_global_mem_new(TCG_AREG0
,
153 offsetof(CPUState
, ctr
), "ctr");
155 cpu_lr
= tcg_global_mem_new(TCG_AREG0
,
156 offsetof(CPUState
, lr
), "lr");
158 cpu_xer
= tcg_global_mem_new(TCG_AREG0
,
159 offsetof(CPUState
, xer
), "xer");
161 cpu_reserve
= tcg_global_mem_new(TCG_AREG0
,
162 offsetof(CPUState
, reserve
), "reserve");
164 cpu_fpscr
= tcg_global_mem_new_i32(TCG_AREG0
,
165 offsetof(CPUState
, fpscr
), "fpscr");
167 cpu_access_type
= tcg_global_mem_new_i32(TCG_AREG0
,
168 offsetof(CPUState
, access_type
), "access_type");
170 /* register helpers */
177 /* internal defines */
178 typedef struct DisasContext
{
179 struct TranslationBlock
*tb
;
183 /* Routine used to access memory */
186 /* Translation flags */
188 #if defined(TARGET_PPC64)
194 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
195 int singlestep_enabled
;
198 struct opc_handler_t
{
201 /* instruction type */
204 void (*handler
)(DisasContext
*ctx
);
205 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
208 #if defined(DO_PPC_STATISTICS)
213 static always_inline
void gen_reset_fpstatus (void)
215 #ifdef CONFIG_SOFTFLOAT
216 gen_helper_reset_fpstatus();
220 static always_inline
void gen_compute_fprf (TCGv_i64 arg
, int set_fprf
, int set_rc
)
222 TCGv_i32 t0
= tcg_temp_new_i32();
225 /* This case might be optimized later */
226 tcg_gen_movi_i32(t0
, 1);
227 gen_helper_compute_fprf(t0
, arg
, t0
);
228 if (unlikely(set_rc
)) {
229 tcg_gen_mov_i32(cpu_crf
[1], t0
);
231 gen_helper_float_check_status();
232 } else if (unlikely(set_rc
)) {
233 /* We always need to compute fpcc */
234 tcg_gen_movi_i32(t0
, 0);
235 gen_helper_compute_fprf(t0
, arg
, t0
);
236 tcg_gen_mov_i32(cpu_crf
[1], t0
);
239 tcg_temp_free_i32(t0
);
242 static always_inline
void gen_set_access_type (DisasContext
*ctx
, int access_type
)
244 if (ctx
->access_type
!= access_type
) {
245 tcg_gen_movi_i32(cpu_access_type
, access_type
);
246 ctx
->access_type
= access_type
;
250 static always_inline
void gen_update_nip (DisasContext
*ctx
, target_ulong nip
)
252 #if defined(TARGET_PPC64)
254 tcg_gen_movi_tl(cpu_nip
, nip
);
257 tcg_gen_movi_tl(cpu_nip
, (uint32_t)nip
);
260 static always_inline
void gen_exception_err (DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
263 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
264 gen_update_nip(ctx
, ctx
->nip
);
266 t0
= tcg_const_i32(excp
);
267 t1
= tcg_const_i32(error
);
268 gen_helper_raise_exception_err(t0
, t1
);
269 tcg_temp_free_i32(t0
);
270 tcg_temp_free_i32(t1
);
271 ctx
->exception
= (excp
);
274 static always_inline
void gen_exception (DisasContext
*ctx
, uint32_t excp
)
277 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
278 gen_update_nip(ctx
, ctx
->nip
);
280 t0
= tcg_const_i32(excp
);
281 gen_helper_raise_exception(t0
);
282 tcg_temp_free_i32(t0
);
283 ctx
->exception
= (excp
);
286 static always_inline
void gen_debug_exception (DisasContext
*ctx
)
290 if (ctx
->exception
!= POWERPC_EXCP_BRANCH
)
291 gen_update_nip(ctx
, ctx
->nip
);
292 t0
= tcg_const_i32(EXCP_DEBUG
);
293 gen_helper_raise_exception(t0
);
294 tcg_temp_free_i32(t0
);
297 static always_inline
void gen_inval_exception (DisasContext
*ctx
, uint32_t error
)
299 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_INVAL
| error
);
302 /* Stop translation */
303 static always_inline
void gen_stop_exception (DisasContext
*ctx
)
305 gen_update_nip(ctx
, ctx
->nip
);
306 ctx
->exception
= POWERPC_EXCP_STOP
;
309 /* No need to update nip here, as execution flow will change */
310 static always_inline
void gen_sync_exception (DisasContext
*ctx
)
312 ctx
->exception
= POWERPC_EXCP_SYNC
;
315 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
316 static void gen_##name (DisasContext *ctx); \
317 GEN_OPCODE(name, opc1, opc2, opc3, inval, type);
319 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
320 static void gen_##name (DisasContext *ctx); \
321 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
322 static void gen_##name (DisasContext *ctx)
324 typedef struct opcode_t
{
325 unsigned char opc1
, opc2
, opc3
;
326 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
327 unsigned char pad
[5];
329 unsigned char pad
[1];
331 opc_handler_t handler
;
335 /*****************************************************************************/
336 /*** Instruction decoding ***/
337 #define EXTRACT_HELPER(name, shift, nb) \
338 static always_inline uint32_t name (uint32_t opcode) \
340 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
343 #define EXTRACT_SHELPER(name, shift, nb) \
344 static always_inline int32_t name (uint32_t opcode) \
346 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
350 EXTRACT_HELPER(opc1
, 26, 6);
352 EXTRACT_HELPER(opc2
, 1, 5);
354 EXTRACT_HELPER(opc3
, 6, 5);
355 /* Update Cr0 flags */
356 EXTRACT_HELPER(Rc
, 0, 1);
358 EXTRACT_HELPER(rD
, 21, 5);
360 EXTRACT_HELPER(rS
, 21, 5);
362 EXTRACT_HELPER(rA
, 16, 5);
364 EXTRACT_HELPER(rB
, 11, 5);
366 EXTRACT_HELPER(rC
, 6, 5);
368 EXTRACT_HELPER(crfD
, 23, 3);
369 EXTRACT_HELPER(crfS
, 18, 3);
370 EXTRACT_HELPER(crbD
, 21, 5);
371 EXTRACT_HELPER(crbA
, 16, 5);
372 EXTRACT_HELPER(crbB
, 11, 5);
374 EXTRACT_HELPER(_SPR
, 11, 10);
375 static always_inline
uint32_t SPR (uint32_t opcode
)
377 uint32_t sprn
= _SPR(opcode
);
379 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
381 /*** Get constants ***/
382 EXTRACT_HELPER(IMM
, 12, 8);
383 /* 16 bits signed immediate value */
384 EXTRACT_SHELPER(SIMM
, 0, 16);
385 /* 16 bits unsigned immediate value */
386 EXTRACT_HELPER(UIMM
, 0, 16);
387 /* 5 bits signed immediate value */
388 EXTRACT_HELPER(SIMM5
, 16, 5);
389 /* 5 bits signed immediate value */
390 EXTRACT_HELPER(UIMM5
, 16, 5);
392 EXTRACT_HELPER(NB
, 11, 5);
394 EXTRACT_HELPER(SH
, 11, 5);
395 /* Vector shift count */
396 EXTRACT_HELPER(VSH
, 6, 4);
398 EXTRACT_HELPER(MB
, 6, 5);
400 EXTRACT_HELPER(ME
, 1, 5);
402 EXTRACT_HELPER(TO
, 21, 5);
404 EXTRACT_HELPER(CRM
, 12, 8);
405 EXTRACT_HELPER(FM
, 17, 8);
406 EXTRACT_HELPER(SR
, 16, 4);
407 EXTRACT_HELPER(FPIMM
, 12, 4);
409 /*** Jump target decoding ***/
411 EXTRACT_SHELPER(d
, 0, 16);
412 /* Immediate address */
413 static always_inline target_ulong
LI (uint32_t opcode
)
415 return (opcode
>> 0) & 0x03FFFFFC;
418 static always_inline
uint32_t BD (uint32_t opcode
)
420 return (opcode
>> 0) & 0xFFFC;
423 EXTRACT_HELPER(BO
, 21, 5);
424 EXTRACT_HELPER(BI
, 16, 5);
425 /* Absolute/relative address */
426 EXTRACT_HELPER(AA
, 1, 1);
428 EXTRACT_HELPER(LK
, 0, 1);
430 /* Create a mask between <start> and <end> bits */
431 static always_inline target_ulong
MASK (uint32_t start
, uint32_t end
)
435 #if defined(TARGET_PPC64)
436 if (likely(start
== 0)) {
437 ret
= UINT64_MAX
<< (63 - end
);
438 } else if (likely(end
== 63)) {
439 ret
= UINT64_MAX
>> start
;
442 if (likely(start
== 0)) {
443 ret
= UINT32_MAX
<< (31 - end
);
444 } else if (likely(end
== 31)) {
445 ret
= UINT32_MAX
>> start
;
449 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
450 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
451 if (unlikely(start
> end
))
458 /*****************************************************************************/
459 /* PowerPC instructions table */
460 #if HOST_LONG_BITS == 64
465 #if defined(__APPLE__)
466 #define OPCODES_SECTION \
467 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
469 #define OPCODES_SECTION \
470 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
473 #if defined(DO_PPC_STATISTICS)
474 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
475 extern opcode_t opc_##name; \
476 OPCODES_SECTION opcode_t opc_##name = { \
484 .handler = &gen_##name, \
485 .oname = stringify(name), \
487 .oname = stringify(name), \
489 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
490 OPCODES_SECTION opcode_t opc_##name = { \
498 .handler = &gen_##name, \
504 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
505 extern opcode_t opc_##name; \
506 OPCODES_SECTION opcode_t opc_##name = { \
514 .handler = &gen_##name, \
516 .oname = stringify(name), \
518 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
519 extern opcode_t opc_##name; \
520 OPCODES_SECTION opcode_t opc_##name = { \
528 .handler = &gen_##name, \
534 #define GEN_OPCODE_MARK(name) \
535 extern opcode_t opc_##name; \
536 OPCODES_SECTION opcode_t opc_##name = { \
542 .inval = 0x00000000, \
546 .oname = stringify(name), \
549 /* SPR load/store helpers */
550 static always_inline
void gen_load_spr(TCGv t
, int reg
)
552 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUState
, spr
[reg
]));
555 static always_inline
void gen_store_spr(int reg
, TCGv t
)
557 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUState
, spr
[reg
]));
560 /* Start opcode list */
561 GEN_OPCODE_MARK(start
);
563 /* Invalid instruction */
564 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
);
566 static void gen_invalid(DisasContext
*ctx
)
568 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
571 static opc_handler_t invalid_handler
= {
574 .handler
= gen_invalid
,
577 /*** Integer comparison ***/
579 static always_inline
void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
583 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_xer
);
584 tcg_gen_shri_i32(cpu_crf
[crf
], cpu_crf
[crf
], XER_SO
);
585 tcg_gen_andi_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1);
587 l1
= gen_new_label();
588 l2
= gen_new_label();
589 l3
= gen_new_label();
591 tcg_gen_brcond_tl(TCG_COND_LT
, arg0
, arg1
, l1
);
592 tcg_gen_brcond_tl(TCG_COND_GT
, arg0
, arg1
, l2
);
594 tcg_gen_brcond_tl(TCG_COND_LTU
, arg0
, arg1
, l1
);
595 tcg_gen_brcond_tl(TCG_COND_GTU
, arg0
, arg1
, l2
);
597 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_EQ
);
600 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_LT
);
603 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_GT
);
607 static always_inline
void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
609 TCGv t0
= tcg_const_local_tl(arg1
);
610 gen_op_cmp(arg0
, t0
, s
, crf
);
614 #if defined(TARGET_PPC64)
615 static always_inline
void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
618 t0
= tcg_temp_local_new();
619 t1
= tcg_temp_local_new();
621 tcg_gen_ext32s_tl(t0
, arg0
);
622 tcg_gen_ext32s_tl(t1
, arg1
);
624 tcg_gen_ext32u_tl(t0
, arg0
);
625 tcg_gen_ext32u_tl(t1
, arg1
);
627 gen_op_cmp(t0
, t1
, s
, crf
);
632 static always_inline
void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
634 TCGv t0
= tcg_const_local_tl(arg1
);
635 gen_op_cmp32(arg0
, t0
, s
, crf
);
640 static always_inline
void gen_set_Rc0 (DisasContext
*ctx
, TCGv reg
)
642 #if defined(TARGET_PPC64)
644 gen_op_cmpi32(reg
, 0, 1, 0);
647 gen_op_cmpi(reg
, 0, 1, 0);
651 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
);
653 static void gen_cmp(DisasContext
*ctx
)
655 #if defined(TARGET_PPC64)
656 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
657 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
658 1, crfD(ctx
->opcode
));
661 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
662 1, crfD(ctx
->opcode
));
666 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
);
668 static void gen_cmpi(DisasContext
*ctx
)
670 #if defined(TARGET_PPC64)
671 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
672 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
673 1, crfD(ctx
->opcode
));
676 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
677 1, crfD(ctx
->opcode
));
681 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
);
683 static void gen_cmpl(DisasContext
*ctx
)
685 #if defined(TARGET_PPC64)
686 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
687 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
688 0, crfD(ctx
->opcode
));
691 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
692 0, crfD(ctx
->opcode
));
696 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
);
698 static void gen_cmpli(DisasContext
*ctx
)
700 #if defined(TARGET_PPC64)
701 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
702 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
703 0, crfD(ctx
->opcode
));
706 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
707 0, crfD(ctx
->opcode
));
710 /* isel (PowerPC 2.03 specification) */
711 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
);
713 static void gen_isel(DisasContext
*ctx
)
716 uint32_t bi
= rC(ctx
->opcode
);
720 l1
= gen_new_label();
721 l2
= gen_new_label();
723 mask
= 1 << (3 - (bi
& 0x03));
724 t0
= tcg_temp_new_i32();
725 tcg_gen_andi_i32(t0
, cpu_crf
[bi
>> 2], mask
);
726 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
727 if (rA(ctx
->opcode
) == 0)
728 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
730 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
733 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
735 tcg_temp_free_i32(t0
);
738 /*** Integer arithmetic ***/
740 static always_inline
void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
, TCGv arg1
, TCGv arg2
, int sub
)
745 l1
= gen_new_label();
746 /* Start with XER OV disabled, the most likely case */
747 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
748 t0
= tcg_temp_local_new();
749 tcg_gen_xor_tl(t0
, arg0
, arg1
);
750 #if defined(TARGET_PPC64)
752 tcg_gen_ext32s_tl(t0
, t0
);
755 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0, l1
);
757 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
758 tcg_gen_xor_tl(t0
, arg1
, arg2
);
759 #if defined(TARGET_PPC64)
761 tcg_gen_ext32s_tl(t0
, t0
);
764 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
766 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0, l1
);
767 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
772 static always_inline
void gen_op_arith_compute_ca(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
, int sub
)
774 int l1
= gen_new_label();
776 #if defined(TARGET_PPC64)
777 if (!(ctx
->sf_mode
)) {
782 tcg_gen_ext32u_tl(t0
, arg1
);
783 tcg_gen_ext32u_tl(t1
, arg2
);
785 tcg_gen_brcond_tl(TCG_COND_GTU
, t0
, t1
, l1
);
787 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
789 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
797 tcg_gen_brcond_tl(TCG_COND_GTU
, arg1
, arg2
, l1
);
799 tcg_gen_brcond_tl(TCG_COND_GEU
, arg1
, arg2
, l1
);
801 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
806 /* Common add function */
807 static always_inline
void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
, TCGv arg2
,
808 int add_ca
, int compute_ca
, int compute_ov
)
812 if ((!compute_ca
&& !compute_ov
) ||
813 (!TCGV_EQUAL(ret
,arg1
) && !TCGV_EQUAL(ret
, arg2
))) {
816 t0
= tcg_temp_local_new();
820 t1
= tcg_temp_local_new();
821 tcg_gen_andi_tl(t1
, cpu_xer
, (1 << XER_CA
));
822 tcg_gen_shri_tl(t1
, t1
, XER_CA
);
825 if (compute_ca
&& compute_ov
) {
826 /* Start with XER CA and OV disabled, the most likely case */
827 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~((1 << XER_CA
) | (1 << XER_OV
)));
828 } else if (compute_ca
) {
829 /* Start with XER CA disabled, the most likely case */
830 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
831 } else if (compute_ov
) {
832 /* Start with XER OV disabled, the most likely case */
833 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
836 tcg_gen_add_tl(t0
, arg1
, arg2
);
839 gen_op_arith_compute_ca(ctx
, t0
, arg1
, 0);
842 tcg_gen_add_tl(t0
, t0
, t1
);
843 gen_op_arith_compute_ca(ctx
, t0
, t1
, 0);
847 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
850 if (unlikely(Rc(ctx
->opcode
) != 0))
851 gen_set_Rc0(ctx
, t0
);
853 if (!TCGV_EQUAL(t0
, ret
)) {
854 tcg_gen_mov_tl(ret
, t0
);
858 /* Add functions with two operands */
859 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
860 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER); \
862 static void glue(gen_, name)(DisasContext *ctx) \
864 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
865 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
866 add_ca, compute_ca, compute_ov); \
868 /* Add functions with one operand and one immediate */
869 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
870 add_ca, compute_ca, compute_ov) \
871 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER); \
873 static void glue(gen_, name)(DisasContext *ctx) \
875 TCGv t0 = tcg_const_local_tl(const_val); \
876 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
877 cpu_gpr[rA(ctx->opcode)], t0, \
878 add_ca, compute_ca, compute_ov); \
882 /* add add. addo addo. */
883 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
884 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
885 /* addc addc. addco addco. */
886 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
887 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
888 /* adde adde. addeo addeo. */
889 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
890 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
891 /* addme addme. addmeo addmeo. */
892 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
893 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
894 /* addze addze. addzeo addzeo.*/
895 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
896 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
898 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
900 static void gen_addi(DisasContext
*ctx
)
902 target_long simm
= SIMM(ctx
->opcode
);
904 if (rA(ctx
->opcode
) == 0) {
906 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
908 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], simm
);
912 static always_inline
void gen_op_addic (DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
915 target_long simm
= SIMM(ctx
->opcode
);
917 /* Start with XER CA and OV disabled, the most likely case */
918 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
920 if (likely(simm
!= 0)) {
921 TCGv t0
= tcg_temp_local_new();
922 tcg_gen_addi_tl(t0
, arg1
, simm
);
923 gen_op_arith_compute_ca(ctx
, t0
, arg1
, 0);
924 tcg_gen_mov_tl(ret
, t0
);
927 tcg_gen_mov_tl(ret
, arg1
);
930 gen_set_Rc0(ctx
, ret
);
933 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
935 static void gen_addic(DisasContext
*ctx
)
937 gen_op_addic(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0);
939 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
941 gen_op_addic(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 1);
944 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
946 static void gen_addis(DisasContext
*ctx
)
948 target_long simm
= SIMM(ctx
->opcode
);
950 if (rA(ctx
->opcode
) == 0) {
952 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
954 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
958 static always_inline
void gen_op_arith_divw (DisasContext
*ctx
, TCGv ret
, TCGv arg1
, TCGv arg2
,
959 int sign
, int compute_ov
)
961 int l1
= gen_new_label();
962 int l2
= gen_new_label();
963 TCGv_i32 t0
= tcg_temp_local_new_i32();
964 TCGv_i32 t1
= tcg_temp_local_new_i32();
966 tcg_gen_trunc_tl_i32(t0
, arg1
);
967 tcg_gen_trunc_tl_i32(t1
, arg2
);
968 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
970 int l3
= gen_new_label();
971 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
972 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
974 tcg_gen_div_i32(t0
, t0
, t1
);
976 tcg_gen_divu_i32(t0
, t0
, t1
);
979 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
984 tcg_gen_sari_i32(t0
, t0
, 31);
986 tcg_gen_movi_i32(t0
, 0);
989 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
992 tcg_gen_extu_i32_tl(ret
, t0
);
993 tcg_temp_free_i32(t0
);
994 tcg_temp_free_i32(t1
);
995 if (unlikely(Rc(ctx
->opcode
) != 0))
996 gen_set_Rc0(ctx
, ret
);
999 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1000 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER); \
1002 static void glue(gen_, name)(DisasContext *ctx) \
1004 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1005 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1006 sign, compute_ov); \
1008 /* divwu divwu. divwuo divwuo. */
1009 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1010 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1011 /* divw divw. divwo divwo. */
1012 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1013 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1014 #if defined(TARGET_PPC64)
1015 static always_inline
void gen_op_arith_divd (DisasContext
*ctx
, TCGv ret
, TCGv arg1
, TCGv arg2
,
1016 int sign
, int compute_ov
)
1018 int l1
= gen_new_label();
1019 int l2
= gen_new_label();
1021 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
1023 int l3
= gen_new_label();
1024 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
1025 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
1027 tcg_gen_div_i64(ret
, arg1
, arg2
);
1029 tcg_gen_divu_i64(ret
, arg1
, arg2
);
1032 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1037 tcg_gen_sari_i64(ret
, arg1
, 63);
1039 tcg_gen_movi_i64(ret
, 0);
1042 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1045 if (unlikely(Rc(ctx
->opcode
) != 0))
1046 gen_set_Rc0(ctx
, ret
);
1048 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1049 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B); \
1051 static void glue(gen_, name)(DisasContext *ctx) \
1053 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1054 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1055 sign, compute_ov); \
1057 /* divwu divwu. divwuo divwuo. */
1058 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1059 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1060 /* divw divw. divwo divwo. */
1061 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1062 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1066 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
);
1068 static void gen_mulhw(DisasContext
*ctx
)
1072 t0
= tcg_temp_new_i64();
1073 t1
= tcg_temp_new_i64();
1074 #if defined(TARGET_PPC64)
1075 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1076 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1077 tcg_gen_mul_i64(t0
, t0
, t1
);
1078 tcg_gen_shri_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
1080 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1081 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1082 tcg_gen_mul_i64(t0
, t0
, t1
);
1083 tcg_gen_shri_i64(t0
, t0
, 32);
1084 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1086 tcg_temp_free_i64(t0
);
1087 tcg_temp_free_i64(t1
);
1088 if (unlikely(Rc(ctx
->opcode
) != 0))
1089 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1091 /* mulhwu mulhwu. */
1092 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
);
1094 static void gen_mulhwu(DisasContext
*ctx
)
1098 t0
= tcg_temp_new_i64();
1099 t1
= tcg_temp_new_i64();
1100 #if defined(TARGET_PPC64)
1101 tcg_gen_ext32u_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1102 tcg_gen_ext32u_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1103 tcg_gen_mul_i64(t0
, t0
, t1
);
1104 tcg_gen_shri_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
1106 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1107 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1108 tcg_gen_mul_i64(t0
, t0
, t1
);
1109 tcg_gen_shri_i64(t0
, t0
, 32);
1110 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1112 tcg_temp_free_i64(t0
);
1113 tcg_temp_free_i64(t1
);
1114 if (unlikely(Rc(ctx
->opcode
) != 0))
1115 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1118 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
);
1120 static void gen_mullw(DisasContext
*ctx
)
1122 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1123 cpu_gpr
[rB(ctx
->opcode
)]);
1124 tcg_gen_ext32s_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)]);
1125 if (unlikely(Rc(ctx
->opcode
) != 0))
1126 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1128 /* mullwo mullwo. */
1129 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
);
1131 static void gen_mullwo(DisasContext
*ctx
)
1136 t0
= tcg_temp_new_i64();
1137 t1
= tcg_temp_new_i64();
1138 l1
= gen_new_label();
1139 /* Start with XER OV disabled, the most likely case */
1140 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1141 #if defined(TARGET_PPC64)
1142 tcg_gen_ext32s_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1143 tcg_gen_ext32s_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1145 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1146 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1148 tcg_gen_mul_i64(t0
, t0
, t1
);
1149 #if defined(TARGET_PPC64)
1150 tcg_gen_ext32s_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1151 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, cpu_gpr
[rD(ctx
->opcode
)], l1
);
1153 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1154 tcg_gen_ext32s_i64(t1
, t0
);
1155 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
1157 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1159 tcg_temp_free_i64(t0
);
1160 tcg_temp_free_i64(t1
);
1161 if (unlikely(Rc(ctx
->opcode
) != 0))
1162 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1165 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
1167 static void gen_mulli(DisasContext
*ctx
)
1169 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1172 #if defined(TARGET_PPC64)
1173 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1174 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B); \
1176 static void glue(gen_, name)(DisasContext *ctx) \
1178 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1179 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1180 if (unlikely(Rc(ctx->opcode) != 0)) \
1181 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1184 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00);
1185 /* mulhdu mulhdu. */
1186 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02);
1188 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
);
1190 static void gen_mulld(DisasContext
*ctx
)
1192 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1193 cpu_gpr
[rB(ctx
->opcode
)]);
1194 if (unlikely(Rc(ctx
->opcode
) != 0))
1195 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1197 /* mulldo mulldo. */
1198 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17);
1201 /* neg neg. nego nego. */
1202 static always_inline
void gen_op_arith_neg (DisasContext
*ctx
, TCGv ret
, TCGv arg1
, int ov_check
)
1204 int l1
= gen_new_label();
1205 int l2
= gen_new_label();
1206 TCGv t0
= tcg_temp_local_new();
1207 #if defined(TARGET_PPC64)
1209 tcg_gen_mov_tl(t0
, arg1
);
1210 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, INT64_MIN
, l1
);
1214 tcg_gen_ext32s_tl(t0
, arg1
);
1215 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
1217 tcg_gen_neg_tl(ret
, arg1
);
1219 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1223 tcg_gen_mov_tl(ret
, t0
);
1225 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1229 if (unlikely(Rc(ctx
->opcode
) != 0))
1230 gen_set_Rc0(ctx
, ret
);
1232 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
);
1234 static void gen_neg(DisasContext
*ctx
)
1236 gen_op_arith_neg(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0);
1238 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
);
1240 static void gen_nego(DisasContext
*ctx
)
1242 gen_op_arith_neg(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 1);
1245 /* Common subf function */
1246 static always_inline
void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
, TCGv arg2
,
1247 int add_ca
, int compute_ca
, int compute_ov
)
1251 if ((!compute_ca
&& !compute_ov
) ||
1252 (!TCGV_EQUAL(ret
, arg1
) && !TCGV_EQUAL(ret
, arg2
))) {
1255 t0
= tcg_temp_local_new();
1259 t1
= tcg_temp_local_new();
1260 tcg_gen_andi_tl(t1
, cpu_xer
, (1 << XER_CA
));
1261 tcg_gen_shri_tl(t1
, t1
, XER_CA
);
1264 if (compute_ca
&& compute_ov
) {
1265 /* Start with XER CA and OV disabled, the most likely case */
1266 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~((1 << XER_CA
) | (1 << XER_OV
)));
1267 } else if (compute_ca
) {
1268 /* Start with XER CA disabled, the most likely case */
1269 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1270 } else if (compute_ov
) {
1271 /* Start with XER OV disabled, the most likely case */
1272 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1276 tcg_gen_not_tl(t0
, arg1
);
1277 tcg_gen_add_tl(t0
, t0
, arg2
);
1278 gen_op_arith_compute_ca(ctx
, t0
, arg2
, 0);
1279 tcg_gen_add_tl(t0
, t0
, t1
);
1280 gen_op_arith_compute_ca(ctx
, t0
, t1
, 0);
1283 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1285 gen_op_arith_compute_ca(ctx
, t0
, arg2
, 1);
1289 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1292 if (unlikely(Rc(ctx
->opcode
) != 0))
1293 gen_set_Rc0(ctx
, t0
);
1295 if (!TCGV_EQUAL(t0
, ret
)) {
1296 tcg_gen_mov_tl(ret
, t0
);
1300 /* Sub functions with Two operands functions */
1301 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1302 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER); \
1304 static void glue(gen_, name)(DisasContext *ctx) \
1306 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1307 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1308 add_ca, compute_ca, compute_ov); \
1310 /* Sub functions with one operand and one immediate */
1311 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1312 add_ca, compute_ca, compute_ov) \
1313 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER); \
1315 static void glue(gen_, name)(DisasContext *ctx) \
1317 TCGv t0 = tcg_const_local_tl(const_val); \
1318 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1319 cpu_gpr[rA(ctx->opcode)], t0, \
1320 add_ca, compute_ca, compute_ov); \
1321 tcg_temp_free(t0); \
1323 /* subf subf. subfo subfo. */
1324 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1325 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1326 /* subfc subfc. subfco subfco. */
1327 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1328 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1329 /* subfe subfe. subfeo subfo. */
1330 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1331 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1332 /* subfme subfme. subfmeo subfmeo. */
1333 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1334 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1335 /* subfze subfze. subfzeo subfzeo.*/
1336 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1337 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1339 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
1341 static void gen_subfic(DisasContext
*ctx
)
1343 /* Start with XER CA and OV disabled, the most likely case */
1344 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1345 TCGv t0
= tcg_temp_local_new();
1346 TCGv t1
= tcg_const_local_tl(SIMM(ctx
->opcode
));
1347 tcg_gen_sub_tl(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)]);
1348 gen_op_arith_compute_ca(ctx
, t0
, t1
, 1);
1350 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1354 /*** Integer logical ***/
1355 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1356 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type); \
1358 static void glue(gen_, name)(DisasContext *ctx) \
1360 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1361 cpu_gpr[rB(ctx->opcode)]); \
1362 if (unlikely(Rc(ctx->opcode) != 0)) \
1363 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1366 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1367 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type); \
1369 static void glue(gen_, name)(DisasContext *ctx) \
1371 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1372 if (unlikely(Rc(ctx->opcode) != 0)) \
1373 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1377 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1379 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1381 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1383 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1384 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1387 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
)
1389 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1390 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1393 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
);
1395 static void gen_cntlzw(DisasContext
*ctx
)
1397 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1398 if (unlikely(Rc(ctx
->opcode
) != 0))
1399 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1402 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1403 /* extsb & extsb. */
1404 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1405 /* extsh & extsh. */
1406 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1408 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1410 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1412 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
);
1414 static void gen_or(DisasContext
*ctx
)
1418 rs
= rS(ctx
->opcode
);
1419 ra
= rA(ctx
->opcode
);
1420 rb
= rB(ctx
->opcode
);
1421 /* Optimisation for mr. ri case */
1422 if (rs
!= ra
|| rs
!= rb
) {
1424 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1426 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1427 if (unlikely(Rc(ctx
->opcode
) != 0))
1428 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1429 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1430 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1431 #if defined(TARGET_PPC64)
1437 /* Set process priority to low */
1441 /* Set process priority to medium-low */
1445 /* Set process priority to normal */
1448 #if !defined(CONFIG_USER_ONLY)
1450 if (ctx
->mem_idx
> 0) {
1451 /* Set process priority to very low */
1456 if (ctx
->mem_idx
> 0) {
1457 /* Set process priority to medium-hight */
1462 if (ctx
->mem_idx
> 0) {
1463 /* Set process priority to high */
1468 if (ctx
->mem_idx
> 1) {
1469 /* Set process priority to very high */
1479 TCGv t0
= tcg_temp_new();
1480 gen_load_spr(t0
, SPR_PPR
);
1481 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1482 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1483 gen_store_spr(SPR_PPR
, t0
);
1490 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1492 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
);
1494 static void gen_xor(DisasContext
*ctx
)
1496 /* Optimisation for "set to zero" case */
1497 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1498 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1500 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1501 if (unlikely(Rc(ctx
->opcode
) != 0))
1502 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1505 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
1507 static void gen_ori(DisasContext
*ctx
)
1509 target_ulong uimm
= UIMM(ctx
->opcode
);
1511 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1513 /* XXX: should handle special NOPs for POWER series */
1516 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1519 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
1521 static void gen_oris(DisasContext
*ctx
)
1523 target_ulong uimm
= UIMM(ctx
->opcode
);
1525 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1529 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1532 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
1534 static void gen_xori(DisasContext
*ctx
)
1536 target_ulong uimm
= UIMM(ctx
->opcode
);
1538 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1542 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1545 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
1547 static void gen_xoris(DisasContext
*ctx
)
1549 target_ulong uimm
= UIMM(ctx
->opcode
);
1551 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1555 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1557 /* popcntb : PowerPC 2.03 specification */
1558 GEN_HANDLER(popcntb
, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB
);
1560 static void gen_popcntb(DisasContext
*ctx
)
1562 #if defined(TARGET_PPC64)
1564 gen_helper_popcntb_64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1567 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1570 #if defined(TARGET_PPC64)
1571 /* extsw & extsw. */
1572 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1574 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
);
1576 static void gen_cntlzd(DisasContext
*ctx
)
1578 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1579 if (unlikely(Rc(ctx
->opcode
) != 0))
1580 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1584 /*** Integer rotate ***/
1585 /* rlwimi & rlwimi. */
1586 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
1588 static void gen_rlwimi(DisasContext
*ctx
)
1590 uint32_t mb
, me
, sh
;
1592 mb
= MB(ctx
->opcode
);
1593 me
= ME(ctx
->opcode
);
1594 sh
= SH(ctx
->opcode
);
1595 if (likely(sh
== 0 && mb
== 0 && me
== 31)) {
1596 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1600 TCGv t0
= tcg_temp_new();
1601 #if defined(TARGET_PPC64)
1602 TCGv_i32 t2
= tcg_temp_new_i32();
1603 tcg_gen_trunc_i64_i32(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
1604 tcg_gen_rotli_i32(t2
, t2
, sh
);
1605 tcg_gen_extu_i32_i64(t0
, t2
);
1606 tcg_temp_free_i32(t2
);
1608 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1610 #if defined(TARGET_PPC64)
1614 mask
= MASK(mb
, me
);
1615 t1
= tcg_temp_new();
1616 tcg_gen_andi_tl(t0
, t0
, mask
);
1617 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1618 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1622 if (unlikely(Rc(ctx
->opcode
) != 0))
1623 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1625 /* rlwinm & rlwinm. */
1626 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
1628 static void gen_rlwinm(DisasContext
*ctx
)
1630 uint32_t mb
, me
, sh
;
1632 sh
= SH(ctx
->opcode
);
1633 mb
= MB(ctx
->opcode
);
1634 me
= ME(ctx
->opcode
);
1636 if (likely(mb
== 0 && me
== (31 - sh
))) {
1637 if (likely(sh
== 0)) {
1638 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1640 TCGv t0
= tcg_temp_new();
1641 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1642 tcg_gen_shli_tl(t0
, t0
, sh
);
1643 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1646 } else if (likely(sh
!= 0 && me
== 31 && sh
== (32 - mb
))) {
1647 TCGv t0
= tcg_temp_new();
1648 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1649 tcg_gen_shri_tl(t0
, t0
, mb
);
1650 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1653 TCGv t0
= tcg_temp_new();
1654 #if defined(TARGET_PPC64)
1655 TCGv_i32 t1
= tcg_temp_new_i32();
1656 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1657 tcg_gen_rotli_i32(t1
, t1
, sh
);
1658 tcg_gen_extu_i32_i64(t0
, t1
);
1659 tcg_temp_free_i32(t1
);
1661 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1663 #if defined(TARGET_PPC64)
1667 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1670 if (unlikely(Rc(ctx
->opcode
) != 0))
1671 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1673 /* rlwnm & rlwnm. */
1674 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
1676 static void gen_rlwnm(DisasContext
*ctx
)
1680 #if defined(TARGET_PPC64)
1684 mb
= MB(ctx
->opcode
);
1685 me
= ME(ctx
->opcode
);
1686 t0
= tcg_temp_new();
1687 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1688 #if defined(TARGET_PPC64)
1689 t1
= tcg_temp_new_i32();
1690 t2
= tcg_temp_new_i32();
1691 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1692 tcg_gen_trunc_i64_i32(t2
, t0
);
1693 tcg_gen_rotl_i32(t1
, t1
, t2
);
1694 tcg_gen_extu_i32_i64(t0
, t1
);
1695 tcg_temp_free_i32(t1
);
1696 tcg_temp_free_i32(t2
);
1698 tcg_gen_rotl_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1700 if (unlikely(mb
!= 0 || me
!= 31)) {
1701 #if defined(TARGET_PPC64)
1705 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1707 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1710 if (unlikely(Rc(ctx
->opcode
) != 0))
1711 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1714 #if defined(TARGET_PPC64)
1715 #define GEN_PPC64_R2(name, opc1, opc2) \
1716 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1718 gen_##name(ctx, 0); \
1720 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1723 gen_##name(ctx, 1); \
1725 #define GEN_PPC64_R4(name, opc1, opc2) \
1726 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1728 gen_##name(ctx, 0, 0); \
1730 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1733 gen_##name(ctx, 0, 1); \
1735 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1738 gen_##name(ctx, 1, 0); \
1740 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1743 gen_##name(ctx, 1, 1); \
1746 static always_inline
void gen_rldinm (DisasContext
*ctx
, uint32_t mb
,
1747 uint32_t me
, uint32_t sh
)
1749 if (likely(sh
!= 0 && mb
== 0 && me
== (63 - sh
))) {
1750 tcg_gen_shli_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
1751 } else if (likely(sh
!= 0 && me
== 63 && sh
== (64 - mb
))) {
1752 tcg_gen_shri_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], mb
);
1754 TCGv t0
= tcg_temp_new();
1755 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1756 if (likely(mb
== 0 && me
== 63)) {
1757 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1759 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1763 if (unlikely(Rc(ctx
->opcode
) != 0))
1764 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1766 /* rldicl - rldicl. */
1767 static always_inline
void gen_rldicl (DisasContext
*ctx
, int mbn
, int shn
)
1771 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1772 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1773 gen_rldinm(ctx
, mb
, 63, sh
);
1775 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1776 /* rldicr - rldicr. */
1777 static always_inline
void gen_rldicr (DisasContext
*ctx
, int men
, int shn
)
1781 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1782 me
= MB(ctx
->opcode
) | (men
<< 5);
1783 gen_rldinm(ctx
, 0, me
, sh
);
1785 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1786 /* rldic - rldic. */
1787 static always_inline
void gen_rldic (DisasContext
*ctx
, int mbn
, int shn
)
1791 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1792 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1793 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1795 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1797 static always_inline
void gen_rldnm (DisasContext
*ctx
, uint32_t mb
,
1802 mb
= MB(ctx
->opcode
);
1803 me
= ME(ctx
->opcode
);
1804 t0
= tcg_temp_new();
1805 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1806 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1807 if (unlikely(mb
!= 0 || me
!= 63)) {
1808 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1810 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1813 if (unlikely(Rc(ctx
->opcode
) != 0))
1814 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1817 /* rldcl - rldcl. */
1818 static always_inline
void gen_rldcl (DisasContext
*ctx
, int mbn
)
1822 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1823 gen_rldnm(ctx
, mb
, 63);
1825 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1826 /* rldcr - rldcr. */
1827 static always_inline
void gen_rldcr (DisasContext
*ctx
, int men
)
1831 me
= MB(ctx
->opcode
) | (men
<< 5);
1832 gen_rldnm(ctx
, 0, me
);
1834 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1835 /* rldimi - rldimi. */
1836 static always_inline
void gen_rldimi (DisasContext
*ctx
, int mbn
, int shn
)
1838 uint32_t sh
, mb
, me
;
1840 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1841 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1843 if (unlikely(sh
== 0 && mb
== 0)) {
1844 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1849 t0
= tcg_temp_new();
1850 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1851 t1
= tcg_temp_new();
1852 mask
= MASK(mb
, me
);
1853 tcg_gen_andi_tl(t0
, t0
, mask
);
1854 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1855 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1859 if (unlikely(Rc(ctx
->opcode
) != 0))
1860 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1862 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1865 /*** Integer shift ***/
1867 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
);
1869 static void gen_slw(DisasContext
*ctx
)
1873 l1
= gen_new_label();
1874 l2
= gen_new_label();
1876 t0
= tcg_temp_local_new();
1877 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1878 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0x20, l1
);
1879 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1882 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t0
);
1883 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1886 if (unlikely(Rc(ctx
->opcode
) != 0))
1887 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1890 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
);
1892 static void gen_sraw(DisasContext
*ctx
)
1894 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)],
1895 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1896 if (unlikely(Rc(ctx
->opcode
) != 0))
1897 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1899 /* srawi & srawi. */
1900 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
);
1902 static void gen_srawi(DisasContext
*ctx
)
1904 int sh
= SH(ctx
->opcode
);
1908 l1
= gen_new_label();
1909 l2
= gen_new_label();
1910 t0
= tcg_temp_local_new();
1911 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1912 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
1913 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1ULL << sh
) - 1);
1914 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1915 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
1918 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1920 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1921 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, sh
);
1924 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1925 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1927 if (unlikely(Rc(ctx
->opcode
) != 0))
1928 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1931 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
);
1933 static void gen_srw(DisasContext
*ctx
)
1937 l1
= gen_new_label();
1938 l2
= gen_new_label();
1940 t0
= tcg_temp_local_new();
1941 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1942 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0x20, l1
);
1943 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1946 t1
= tcg_temp_new();
1947 tcg_gen_ext32u_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1948 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
, t0
);
1952 if (unlikely(Rc(ctx
->opcode
) != 0))
1953 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1955 #if defined(TARGET_PPC64)
1957 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
);
1959 static void gen_sld(DisasContext
*ctx
)
1963 l1
= gen_new_label();
1964 l2
= gen_new_label();
1966 t0
= tcg_temp_local_new();
1967 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x7f);
1968 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0x40, l1
);
1969 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1972 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t0
);
1975 if (unlikely(Rc(ctx
->opcode
) != 0))
1976 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1979 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
);
1981 static void gen_srad(DisasContext
*ctx
)
1983 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)],
1984 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1985 if (unlikely(Rc(ctx
->opcode
) != 0))
1986 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1988 /* sradi & sradi. */
1989 static always_inline
void gen_sradi (DisasContext
*ctx
, int n
)
1991 int sh
= SH(ctx
->opcode
) + (n
<< 5);
1995 l1
= gen_new_label();
1996 l2
= gen_new_label();
1997 t0
= tcg_temp_local_new();
1998 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
1999 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1ULL << sh
) - 1);
2000 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2001 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
2004 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
2007 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
2009 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
2010 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
2012 if (unlikely(Rc(ctx
->opcode
) != 0))
2013 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2015 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
)
2019 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
)
2024 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
);
2026 static void gen_srd(DisasContext
*ctx
)
2030 l1
= gen_new_label();
2031 l2
= gen_new_label();
2033 t0
= tcg_temp_local_new();
2034 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x7f);
2035 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0x40, l1
);
2036 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
2039 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t0
);
2042 if (unlikely(Rc(ctx
->opcode
) != 0))
2043 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2047 /*** Floating-Point arithmetic ***/
2048 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2049 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type); \
2051 static void gen_f##name(DisasContext *ctx) \
2053 if (unlikely(!ctx->fpu_enabled)) { \
2054 gen_exception(ctx, POWERPC_EXCP_FPU); \
2057 /* NIP cannot be restored if the memory exception comes from an helper */ \
2058 gen_update_nip(ctx, ctx->nip - 4); \
2059 gen_reset_fpstatus(); \
2060 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2061 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2063 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2065 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2066 Rc(ctx->opcode) != 0); \
2069 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2070 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2071 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2073 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2074 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type); \
2076 static void gen_f##name(DisasContext *ctx) \
2078 if (unlikely(!ctx->fpu_enabled)) { \
2079 gen_exception(ctx, POWERPC_EXCP_FPU); \
2082 /* NIP cannot be restored if the memory exception comes from an helper */ \
2083 gen_update_nip(ctx, ctx->nip - 4); \
2084 gen_reset_fpstatus(); \
2085 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2086 cpu_fpr[rB(ctx->opcode)]); \
2088 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2090 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2091 set_fprf, Rc(ctx->opcode) != 0); \
2093 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2094 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2095 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2097 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2098 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type); \
2100 static void gen_f##name(DisasContext *ctx) \
2102 if (unlikely(!ctx->fpu_enabled)) { \
2103 gen_exception(ctx, POWERPC_EXCP_FPU); \
2106 /* NIP cannot be restored if the memory exception comes from an helper */ \
2107 gen_update_nip(ctx, ctx->nip - 4); \
2108 gen_reset_fpstatus(); \
2109 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2110 cpu_fpr[rC(ctx->opcode)]); \
2112 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2114 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2115 set_fprf, Rc(ctx->opcode) != 0); \
2117 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2118 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2119 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2121 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2122 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type); \
2124 static void gen_f##name(DisasContext *ctx) \
2126 if (unlikely(!ctx->fpu_enabled)) { \
2127 gen_exception(ctx, POWERPC_EXCP_FPU); \
2130 /* NIP cannot be restored if the memory exception comes from an helper */ \
2131 gen_update_nip(ctx, ctx->nip - 4); \
2132 gen_reset_fpstatus(); \
2133 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2134 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2135 set_fprf, Rc(ctx->opcode) != 0); \
2138 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2139 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type); \
2141 static void gen_f##name(DisasContext *ctx) \
2143 if (unlikely(!ctx->fpu_enabled)) { \
2144 gen_exception(ctx, POWERPC_EXCP_FPU); \
2147 /* NIP cannot be restored if the memory exception comes from an helper */ \
2148 gen_update_nip(ctx, ctx->nip - 4); \
2149 gen_reset_fpstatus(); \
2150 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2151 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2152 set_fprf, Rc(ctx->opcode) != 0); \
2156 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
2158 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
2160 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
2163 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
2166 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
2169 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
2172 GEN_HANDLER(frsqrtes
, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES
);
2174 static void gen_frsqrtes(DisasContext
*ctx
)
2176 if (unlikely(!ctx
->fpu_enabled
)) {
2177 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2180 /* NIP cannot be restored if the memory exception comes from an helper */
2181 gen_update_nip(ctx
, ctx
->nip
- 4);
2182 gen_reset_fpstatus();
2183 gen_helper_frsqrte(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2184 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rD(ctx
->opcode
)]);
2185 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2189 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
2191 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
2194 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
);
2196 static void gen_fsqrt(DisasContext
*ctx
)
2198 if (unlikely(!ctx
->fpu_enabled
)) {
2199 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2202 /* NIP cannot be restored if the memory exception comes from an helper */
2203 gen_update_nip(ctx
, ctx
->nip
- 4);
2204 gen_reset_fpstatus();
2205 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2206 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2209 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
);
2211 static void gen_fsqrts(DisasContext
*ctx
)
2213 if (unlikely(!ctx
->fpu_enabled
)) {
2214 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2217 /* NIP cannot be restored if the memory exception comes from an helper */
2218 gen_update_nip(ctx
, ctx
->nip
- 4);
2219 gen_reset_fpstatus();
2220 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2221 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rD(ctx
->opcode
)]);
2222 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2225 /*** Floating-Point multiply-and-add ***/
2226 /* fmadd - fmadds */
2227 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
2228 /* fmsub - fmsubs */
2229 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
2230 /* fnmadd - fnmadds */
2231 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
2232 /* fnmsub - fnmsubs */
2233 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
2235 /*** Floating-Point round & convert ***/
2237 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
2239 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
2241 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
2242 #if defined(TARGET_PPC64)
2244 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
);
2246 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
);
2248 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
);
2252 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
2254 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
2256 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
2258 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
2260 /*** Floating-Point compare ***/
2262 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
);
2264 static void gen_fcmpo(DisasContext
*ctx
)
2267 if (unlikely(!ctx
->fpu_enabled
)) {
2268 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2271 /* NIP cannot be restored if the memory exception comes from an helper */
2272 gen_update_nip(ctx
, ctx
->nip
- 4);
2273 gen_reset_fpstatus();
2274 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2275 gen_helper_fcmpo(cpu_fpr
[rA(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)], crf
);
2276 tcg_temp_free_i32(crf
);
2277 gen_helper_float_check_status();
2281 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
);
2283 static void gen_fcmpu(DisasContext
*ctx
)
2286 if (unlikely(!ctx
->fpu_enabled
)) {
2287 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2290 /* NIP cannot be restored if the memory exception comes from an helper */
2291 gen_update_nip(ctx
, ctx
->nip
- 4);
2292 gen_reset_fpstatus();
2293 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2294 gen_helper_fcmpu(cpu_fpr
[rA(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)], crf
);
2295 tcg_temp_free_i32(crf
);
2296 gen_helper_float_check_status();
2299 /*** Floating-point move ***/
2301 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2302 GEN_FLOAT_B(abs
, 0x08, 0x08, 0, PPC_FLOAT
);
2305 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2306 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
);
2308 static void gen_fmr(DisasContext
*ctx
)
2310 if (unlikely(!ctx
->fpu_enabled
)) {
2311 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2314 tcg_gen_mov_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2315 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2319 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2320 GEN_FLOAT_B(nabs
, 0x08, 0x04, 0, PPC_FLOAT
);
2322 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2323 GEN_FLOAT_B(neg
, 0x08, 0x01, 0, PPC_FLOAT
);
2325 /*** Floating-Point status & ctrl register ***/
2327 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
);
2329 static void gen_mcrfs(DisasContext
*ctx
)
2333 if (unlikely(!ctx
->fpu_enabled
)) {
2334 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2337 bfa
= 4 * (7 - crfS(ctx
->opcode
));
2338 tcg_gen_shri_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_fpscr
, bfa
);
2339 tcg_gen_andi_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], 0xf);
2340 tcg_gen_andi_i32(cpu_fpscr
, cpu_fpscr
, ~(0xF << bfa
));
2344 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
);
2346 static void gen_mffs(DisasContext
*ctx
)
2348 if (unlikely(!ctx
->fpu_enabled
)) {
2349 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2352 gen_reset_fpstatus();
2353 tcg_gen_extu_i32_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpscr
);
2354 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2358 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
);
2360 static void gen_mtfsb0(DisasContext
*ctx
)
2364 if (unlikely(!ctx
->fpu_enabled
)) {
2365 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2368 crb
= 31 - crbD(ctx
->opcode
);
2369 gen_reset_fpstatus();
2370 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
)) {
2372 /* NIP cannot be restored if the memory exception comes from an helper */
2373 gen_update_nip(ctx
, ctx
->nip
- 4);
2374 t0
= tcg_const_i32(crb
);
2375 gen_helper_fpscr_clrbit(t0
);
2376 tcg_temp_free_i32(t0
);
2378 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2379 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2384 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
);
2386 static void gen_mtfsb1(DisasContext
*ctx
)
2390 if (unlikely(!ctx
->fpu_enabled
)) {
2391 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2394 crb
= 31 - crbD(ctx
->opcode
);
2395 gen_reset_fpstatus();
2396 /* XXX: we pretend we can only do IEEE floating-point computations */
2397 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
)) {
2399 /* NIP cannot be restored if the memory exception comes from an helper */
2400 gen_update_nip(ctx
, ctx
->nip
- 4);
2401 t0
= tcg_const_i32(crb
);
2402 gen_helper_fpscr_setbit(t0
);
2403 tcg_temp_free_i32(t0
);
2405 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2406 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2408 /* We can raise a differed exception */
2409 gen_helper_float_check_status();
2413 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT
);
2415 static void gen_mtfsf(DisasContext
*ctx
)
2418 int L
= ctx
->opcode
& 0x02000000;
2420 if (unlikely(!ctx
->fpu_enabled
)) {
2421 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2424 /* NIP cannot be restored if the memory exception comes from an helper */
2425 gen_update_nip(ctx
, ctx
->nip
- 4);
2426 gen_reset_fpstatus();
2428 t0
= tcg_const_i32(0xff);
2430 t0
= tcg_const_i32(FM(ctx
->opcode
));
2431 gen_helper_store_fpscr(cpu_fpr
[rB(ctx
->opcode
)], t0
);
2432 tcg_temp_free_i32(t0
);
2433 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2434 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2436 /* We can raise a differed exception */
2437 gen_helper_float_check_status();
2441 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT
);
2443 static void gen_mtfsfi(DisasContext
*ctx
)
2449 if (unlikely(!ctx
->fpu_enabled
)) {
2450 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2453 bf
= crbD(ctx
->opcode
) >> 2;
2455 /* NIP cannot be restored if the memory exception comes from an helper */
2456 gen_update_nip(ctx
, ctx
->nip
- 4);
2457 gen_reset_fpstatus();
2458 t0
= tcg_const_i64(FPIMM(ctx
->opcode
) << (4 * sh
));
2459 t1
= tcg_const_i32(1 << sh
);
2460 gen_helper_store_fpscr(t0
, t1
);
2461 tcg_temp_free_i64(t0
);
2462 tcg_temp_free_i32(t1
);
2463 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2464 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2466 /* We can raise a differed exception */
2467 gen_helper_float_check_status();
2470 /*** Addressing modes ***/
2471 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2472 static always_inline
void gen_addr_imm_index (DisasContext
*ctx
, TCGv EA
, target_long maskl
)
2474 target_long simm
= SIMM(ctx
->opcode
);
2477 if (rA(ctx
->opcode
) == 0) {
2478 #if defined(TARGET_PPC64)
2479 if (!ctx
->sf_mode
) {
2480 tcg_gen_movi_tl(EA
, (uint32_t)simm
);
2483 tcg_gen_movi_tl(EA
, simm
);
2484 } else if (likely(simm
!= 0)) {
2485 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2486 #if defined(TARGET_PPC64)
2487 if (!ctx
->sf_mode
) {
2488 tcg_gen_ext32u_tl(EA
, EA
);
2492 #if defined(TARGET_PPC64)
2493 if (!ctx
->sf_mode
) {
2494 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2497 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2501 static always_inline
void gen_addr_reg_index (DisasContext
*ctx
, TCGv EA
)
2503 if (rA(ctx
->opcode
) == 0) {
2504 #if defined(TARGET_PPC64)
2505 if (!ctx
->sf_mode
) {
2506 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2509 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2511 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2512 #if defined(TARGET_PPC64)
2513 if (!ctx
->sf_mode
) {
2514 tcg_gen_ext32u_tl(EA
, EA
);
2520 static always_inline
void gen_addr_register (DisasContext
*ctx
, TCGv EA
)
2522 if (rA(ctx
->opcode
) == 0) {
2523 tcg_gen_movi_tl(EA
, 0);
2525 #if defined(TARGET_PPC64)
2526 if (!ctx
->sf_mode
) {
2527 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2530 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2534 static always_inline
void gen_addr_add (DisasContext
*ctx
, TCGv ret
, TCGv arg1
, target_long val
)
2536 tcg_gen_addi_tl(ret
, arg1
, val
);
2537 #if defined(TARGET_PPC64)
2538 if (!ctx
->sf_mode
) {
2539 tcg_gen_ext32u_tl(ret
, ret
);
2544 static always_inline
void gen_check_align (DisasContext
*ctx
, TCGv EA
, int mask
)
2546 int l1
= gen_new_label();
2547 TCGv t0
= tcg_temp_new();
2549 /* NIP cannot be restored if the memory exception comes from an helper */
2550 gen_update_nip(ctx
, ctx
->nip
- 4);
2551 tcg_gen_andi_tl(t0
, EA
, mask
);
2552 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2553 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2554 t2
= tcg_const_i32(0);
2555 gen_helper_raise_exception_err(t1
, t2
);
2556 tcg_temp_free_i32(t1
);
2557 tcg_temp_free_i32(t2
);
2562 /*** Integer load ***/
2563 static always_inline
void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2565 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2568 static always_inline
void gen_qemu_ld8s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2570 tcg_gen_qemu_ld8s(arg1
, arg2
, ctx
->mem_idx
);
2573 static always_inline
void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2575 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2576 if (unlikely(ctx
->le_mode
)) {
2577 tcg_gen_bswap16_tl(arg1
, arg1
);
2581 static always_inline
void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2583 if (unlikely(ctx
->le_mode
)) {
2584 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2585 tcg_gen_bswap16_tl(arg1
, arg1
);
2586 tcg_gen_ext16s_tl(arg1
, arg1
);
2588 tcg_gen_qemu_ld16s(arg1
, arg2
, ctx
->mem_idx
);
2592 static always_inline
void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2594 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2595 if (unlikely(ctx
->le_mode
)) {
2596 tcg_gen_bswap32_tl(arg1
, arg1
);
2600 #if defined(TARGET_PPC64)
2601 static always_inline
void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2603 if (unlikely(ctx
->le_mode
)) {
2604 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2605 tcg_gen_bswap32_tl(arg1
, arg1
);
2606 tcg_gen_ext32s_tl(arg1
, arg1
);
2608 tcg_gen_qemu_ld32s(arg1
, arg2
, ctx
->mem_idx
);
2612 static always_inline
void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2614 tcg_gen_qemu_ld64(arg1
, arg2
, ctx
->mem_idx
);
2615 if (unlikely(ctx
->le_mode
)) {
2616 tcg_gen_bswap64_i64(arg1
, arg1
);
2620 static always_inline
void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2622 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2625 static always_inline
void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2627 if (unlikely(ctx
->le_mode
)) {
2628 TCGv t0
= tcg_temp_new();
2629 tcg_gen_ext16u_tl(t0
, arg1
);
2630 tcg_gen_bswap16_tl(t0
, t0
);
2631 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2634 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
2638 static always_inline
void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2640 if (unlikely(ctx
->le_mode
)) {
2641 TCGv t0
= tcg_temp_new();
2642 tcg_gen_ext32u_tl(t0
, arg1
);
2643 tcg_gen_bswap32_tl(t0
, t0
);
2644 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
2647 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
2651 static always_inline
void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2653 if (unlikely(ctx
->le_mode
)) {
2654 TCGv_i64 t0
= tcg_temp_new_i64();
2655 tcg_gen_bswap64_i64(t0
, arg1
);
2656 tcg_gen_qemu_st64(t0
, arg2
, ctx
->mem_idx
);
2657 tcg_temp_free_i64(t0
);
2659 tcg_gen_qemu_st64(arg1
, arg2
, ctx
->mem_idx
);
2662 #define GEN_LD(name, ldop, opc, type) \
2663 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type); \
2665 static void glue(gen_, name)(DisasContext *ctx) \
2668 gen_set_access_type(ctx, ACCESS_INT); \
2669 EA = tcg_temp_new(); \
2670 gen_addr_imm_index(ctx, EA, 0); \
2671 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2672 tcg_temp_free(EA); \
2675 #define GEN_LDU(name, ldop, opc, type) \
2676 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type); \
2678 static void glue(gen_, name##u)(DisasContext *ctx) \
2681 if (unlikely(rA(ctx->opcode) == 0 || \
2682 rA(ctx->opcode) == rD(ctx->opcode))) { \
2683 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2686 gen_set_access_type(ctx, ACCESS_INT); \
2687 EA = tcg_temp_new(); \
2688 if (type == PPC_64B) \
2689 gen_addr_imm_index(ctx, EA, 0x03); \
2691 gen_addr_imm_index(ctx, EA, 0); \
2692 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2693 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2694 tcg_temp_free(EA); \
2697 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2698 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type); \
2700 static void glue(gen_, name##ux)(DisasContext *ctx) \
2703 if (unlikely(rA(ctx->opcode) == 0 || \
2704 rA(ctx->opcode) == rD(ctx->opcode))) { \
2705 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2708 gen_set_access_type(ctx, ACCESS_INT); \
2709 EA = tcg_temp_new(); \
2710 gen_addr_reg_index(ctx, EA); \
2711 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2712 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2713 tcg_temp_free(EA); \
2716 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2717 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type); \
2719 static void glue(gen_, name##x)(DisasContext *ctx) \
2722 gen_set_access_type(ctx, ACCESS_INT); \
2723 EA = tcg_temp_new(); \
2724 gen_addr_reg_index(ctx, EA); \
2725 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2726 tcg_temp_free(EA); \
2729 #define GEN_LDS(name, ldop, op, type) \
2730 GEN_LD(name, ldop, op | 0x20, type); \
2731 GEN_LDU(name, ldop, op | 0x21, type); \
2732 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2733 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2735 /* lbz lbzu lbzux lbzx */
2736 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2737 /* lha lhau lhaux lhax */
2738 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2739 /* lhz lhzu lhzux lhzx */
2740 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2741 /* lwz lwzu lwzux lwzx */
2742 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2743 #if defined(TARGET_PPC64)
2745 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2747 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2749 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2751 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2752 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
);
2754 static void gen_ld(DisasContext
*ctx
)
2757 if (Rc(ctx
->opcode
)) {
2758 if (unlikely(rA(ctx
->opcode
) == 0 ||
2759 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2760 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2764 gen_set_access_type(ctx
, ACCESS_INT
);
2765 EA
= tcg_temp_new();
2766 gen_addr_imm_index(ctx
, EA
, 0x03);
2767 if (ctx
->opcode
& 0x02) {
2768 /* lwa (lwau is undefined) */
2769 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2772 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2774 if (Rc(ctx
->opcode
))
2775 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2779 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
);
2781 static void gen_lq(DisasContext
*ctx
)
2783 #if defined(CONFIG_USER_ONLY)
2784 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2789 /* Restore CPU state */
2790 if (unlikely(ctx
->mem_idx
== 0)) {
2791 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2794 ra
= rA(ctx
->opcode
);
2795 rd
= rD(ctx
->opcode
);
2796 if (unlikely((rd
& 1) || rd
== ra
)) {
2797 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2800 if (unlikely(ctx
->le_mode
)) {
2801 /* Little-endian mode is not handled */
2802 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2805 gen_set_access_type(ctx
, ACCESS_INT
);
2806 EA
= tcg_temp_new();
2807 gen_addr_imm_index(ctx
, EA
, 0x0F);
2808 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2809 gen_addr_add(ctx
, EA
, EA
, 8);
2810 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2816 /*** Integer store ***/
2817 #define GEN_ST(name, stop, opc, type) \
2818 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type); \
2820 static void glue(gen_, name)(DisasContext *ctx) \
2823 gen_set_access_type(ctx, ACCESS_INT); \
2824 EA = tcg_temp_new(); \
2825 gen_addr_imm_index(ctx, EA, 0); \
2826 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2827 tcg_temp_free(EA); \
2830 #define GEN_STU(name, stop, opc, type) \
2831 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type); \
2833 static void glue(gen_, stop##u)(DisasContext *ctx) \
2836 if (unlikely(rA(ctx->opcode) == 0)) { \
2837 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2840 gen_set_access_type(ctx, ACCESS_INT); \
2841 EA = tcg_temp_new(); \
2842 if (type == PPC_64B) \
2843 gen_addr_imm_index(ctx, EA, 0x03); \
2845 gen_addr_imm_index(ctx, EA, 0); \
2846 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2847 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2848 tcg_temp_free(EA); \
2851 #define GEN_STUX(name, stop, opc2, opc3, type) \
2852 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type); \
2854 static void glue(gen_, name##ux)(DisasContext *ctx) \
2857 if (unlikely(rA(ctx->opcode) == 0)) { \
2858 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2861 gen_set_access_type(ctx, ACCESS_INT); \
2862 EA = tcg_temp_new(); \
2863 gen_addr_reg_index(ctx, EA); \
2864 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2865 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2866 tcg_temp_free(EA); \
2869 #define GEN_STX(name, stop, opc2, opc3, type) \
2870 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type); \
2872 static void glue(gen_, name##x)(DisasContext *ctx) \
2875 gen_set_access_type(ctx, ACCESS_INT); \
2876 EA = tcg_temp_new(); \
2877 gen_addr_reg_index(ctx, EA); \
2878 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2879 tcg_temp_free(EA); \
2882 #define GEN_STS(name, stop, op, type) \
2883 GEN_ST(name, stop, op | 0x20, type); \
2884 GEN_STU(name, stop, op | 0x21, type); \
2885 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2886 GEN_STX(name, stop, 0x17, op | 0x00, type)
2888 /* stb stbu stbux stbx */
2889 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2890 /* sth sthu sthux sthx */
2891 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2892 /* stw stwu stwux stwx */
2893 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2894 #if defined(TARGET_PPC64)
2895 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
2896 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
2897 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
);
2899 static void gen_std(DisasContext
*ctx
)
2904 rs
= rS(ctx
->opcode
);
2905 if ((ctx
->opcode
& 0x3) == 0x2) {
2906 #if defined(CONFIG_USER_ONLY)
2907 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2910 if (unlikely(ctx
->mem_idx
== 0)) {
2911 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2914 if (unlikely(rs
& 1)) {
2915 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2918 if (unlikely(ctx
->le_mode
)) {
2919 /* Little-endian mode is not handled */
2920 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2923 gen_set_access_type(ctx
, ACCESS_INT
);
2924 EA
= tcg_temp_new();
2925 gen_addr_imm_index(ctx
, EA
, 0x03);
2926 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2927 gen_addr_add(ctx
, EA
, EA
, 8);
2928 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
2933 if (Rc(ctx
->opcode
)) {
2934 if (unlikely(rA(ctx
->opcode
) == 0)) {
2935 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2939 gen_set_access_type(ctx
, ACCESS_INT
);
2940 EA
= tcg_temp_new();
2941 gen_addr_imm_index(ctx
, EA
, 0x03);
2942 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2943 if (Rc(ctx
->opcode
))
2944 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2949 /*** Integer load and store with byte reverse ***/
2951 static void always_inline
gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2953 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2954 if (likely(!ctx
->le_mode
)) {
2955 tcg_gen_bswap16_tl(arg1
, arg1
);
2958 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2961 static void always_inline
gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2963 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2964 if (likely(!ctx
->le_mode
)) {
2965 tcg_gen_bswap32_tl(arg1
, arg1
);
2968 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2971 static void always_inline
gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2973 if (likely(!ctx
->le_mode
)) {
2974 TCGv t0
= tcg_temp_new();
2975 tcg_gen_ext16u_tl(t0
, arg1
);
2976 tcg_gen_bswap16_tl(t0
, t0
);
2977 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2980 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
2983 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2986 static void always_inline
gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2988 if (likely(!ctx
->le_mode
)) {
2989 TCGv t0
= tcg_temp_new();
2990 tcg_gen_ext32u_tl(t0
, arg1
);
2991 tcg_gen_bswap32_tl(t0
, t0
);
2992 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
2995 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
2998 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
3000 /*** Integer load and store multiple ***/
3002 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
3004 static void gen_lmw(DisasContext
*ctx
)
3008 gen_set_access_type(ctx
, ACCESS_INT
);
3009 /* NIP cannot be restored if the memory exception comes from an helper */
3010 gen_update_nip(ctx
, ctx
->nip
- 4);
3011 t0
= tcg_temp_new();
3012 t1
= tcg_const_i32(rD(ctx
->opcode
));
3013 gen_addr_imm_index(ctx
, t0
, 0);
3014 gen_helper_lmw(t0
, t1
);
3016 tcg_temp_free_i32(t1
);
3020 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
);
3022 static void gen_stmw(DisasContext
*ctx
)
3026 gen_set_access_type(ctx
, ACCESS_INT
);
3027 /* NIP cannot be restored if the memory exception comes from an helper */
3028 gen_update_nip(ctx
, ctx
->nip
- 4);
3029 t0
= tcg_temp_new();
3030 t1
= tcg_const_i32(rS(ctx
->opcode
));
3031 gen_addr_imm_index(ctx
, t0
, 0);
3032 gen_helper_stmw(t0
, t1
);
3034 tcg_temp_free_i32(t1
);
3037 /*** Integer load and store strings ***/
3039 /* PowerPC32 specification says we must generate an exception if
3040 * rA is in the range of registers to be loaded.
3041 * In an other hand, IBM says this is valid, but rA won't be loaded.
3042 * For now, I'll follow the spec...
3044 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
);
3046 static void gen_lswi(DisasContext
*ctx
)
3050 int nb
= NB(ctx
->opcode
);
3051 int start
= rD(ctx
->opcode
);
3052 int ra
= rA(ctx
->opcode
);
3058 if (unlikely(((start
+ nr
) > 32 &&
3059 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
3060 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
3061 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
3064 gen_set_access_type(ctx
, ACCESS_INT
);
3065 /* NIP cannot be restored if the memory exception comes from an helper */
3066 gen_update_nip(ctx
, ctx
->nip
- 4);
3067 t0
= tcg_temp_new();
3068 gen_addr_register(ctx
, t0
);
3069 t1
= tcg_const_i32(nb
);
3070 t2
= tcg_const_i32(start
);
3071 gen_helper_lsw(t0
, t1
, t2
);
3073 tcg_temp_free_i32(t1
);
3074 tcg_temp_free_i32(t2
);
3078 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
);
3080 static void gen_lswx(DisasContext
*ctx
)
3083 TCGv_i32 t1
, t2
, t3
;
3084 gen_set_access_type(ctx
, ACCESS_INT
);
3085 /* NIP cannot be restored if the memory exception comes from an helper */
3086 gen_update_nip(ctx
, ctx
->nip
- 4);
3087 t0
= tcg_temp_new();
3088 gen_addr_reg_index(ctx
, t0
);
3089 t1
= tcg_const_i32(rD(ctx
->opcode
));
3090 t2
= tcg_const_i32(rA(ctx
->opcode
));
3091 t3
= tcg_const_i32(rB(ctx
->opcode
));
3092 gen_helper_lswx(t0
, t1
, t2
, t3
);
3094 tcg_temp_free_i32(t1
);
3095 tcg_temp_free_i32(t2
);
3096 tcg_temp_free_i32(t3
);
3100 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
);
3102 static void gen_stswi(DisasContext
*ctx
)
3106 int nb
= NB(ctx
->opcode
);
3107 gen_set_access_type(ctx
, ACCESS_INT
);
3108 /* NIP cannot be restored if the memory exception comes from an helper */
3109 gen_update_nip(ctx
, ctx
->nip
- 4);
3110 t0
= tcg_temp_new();
3111 gen_addr_register(ctx
, t0
);
3114 t1
= tcg_const_i32(nb
);
3115 t2
= tcg_const_i32(rS(ctx
->opcode
));
3116 gen_helper_stsw(t0
, t1
, t2
);
3118 tcg_temp_free_i32(t1
);
3119 tcg_temp_free_i32(t2
);
3123 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
);
3125 static void gen_stswx(DisasContext
*ctx
)
3129 gen_set_access_type(ctx
, ACCESS_INT
);
3130 /* NIP cannot be restored if the memory exception comes from an helper */
3131 gen_update_nip(ctx
, ctx
->nip
- 4);
3132 t0
= tcg_temp_new();
3133 gen_addr_reg_index(ctx
, t0
);
3134 t1
= tcg_temp_new_i32();
3135 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3136 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3137 t2
= tcg_const_i32(rS(ctx
->opcode
));
3138 gen_helper_stsw(t0
, t1
, t2
);
3140 tcg_temp_free_i32(t1
);
3141 tcg_temp_free_i32(t2
);
3144 /*** Memory synchronisation ***/
3146 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
);
3148 static void gen_eieio(DisasContext
*ctx
)
3153 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
);
3155 static void gen_isync(DisasContext
*ctx
)
3157 gen_stop_exception(ctx
);
3161 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES
);
3163 static void gen_lwarx(DisasContext
*ctx
)
3166 gen_set_access_type(ctx
, ACCESS_RES
);
3167 t0
= tcg_temp_local_new();
3168 gen_addr_reg_index(ctx
, t0
);
3169 gen_check_align(ctx
, t0
, 0x03);
3170 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
3171 tcg_gen_mov_tl(cpu_reserve
, t0
);
3176 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
)
3180 gen_set_access_type(ctx
, ACCESS_RES
);
3181 t0
= tcg_temp_local_new();
3182 gen_addr_reg_index(ctx
, t0
);
3183 gen_check_align(ctx
, t0
, 0x03);
3184 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
3185 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
3186 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
3187 l1
= gen_new_label();
3188 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3189 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3190 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3192 tcg_gen_movi_tl(cpu_reserve
, -1);
3196 #if defined(TARGET_PPC64)
3198 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B
);
3200 static void gen_ldarx(DisasContext
*ctx
)
3203 gen_set_access_type(ctx
, ACCESS_RES
);
3204 t0
= tcg_temp_local_new();
3205 gen_addr_reg_index(ctx
, t0
);
3206 gen_check_align(ctx
, t0
, 0x07);
3207 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
3208 tcg_gen_mov_tl(cpu_reserve
, t0
);
3213 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
)
3217 gen_set_access_type(ctx
, ACCESS_RES
);
3218 t0
= tcg_temp_local_new();
3219 gen_addr_reg_index(ctx
, t0
);
3220 gen_check_align(ctx
, t0
, 0x07);
3221 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
3222 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
3223 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
3224 l1
= gen_new_label();
3225 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3226 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3227 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3229 tcg_gen_movi_tl(cpu_reserve
, -1);
3232 #endif /* defined(TARGET_PPC64) */
3235 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
);
3237 static void gen_sync(DisasContext
*ctx
)
3242 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
);
3244 static void gen_wait(DisasContext
*ctx
)
3246 TCGv_i32 t0
= tcg_temp_new_i32();
3247 tcg_gen_st_i32(t0
, cpu_env
, offsetof(CPUState
, halted
));
3248 tcg_temp_free_i32(t0
);
3249 /* Stop translation, as the CPU is supposed to sleep from now */
3250 gen_exception_err(ctx
, EXCP_HLT
, 1);
3253 /*** Floating-point load ***/
3254 #define GEN_LDF(name, ldop, opc, type) \
3255 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type); \
3257 static void glue(gen_, name)(DisasContext *ctx) \
3260 if (unlikely(!ctx->fpu_enabled)) { \
3261 gen_exception(ctx, POWERPC_EXCP_FPU); \
3264 gen_set_access_type(ctx, ACCESS_FLOAT); \
3265 EA = tcg_temp_new(); \
3266 gen_addr_imm_index(ctx, EA, 0); \
3267 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3268 tcg_temp_free(EA); \
3271 #define GEN_LDUF(name, ldop, opc, type) \
3272 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type); \
3274 static void glue(gen_, name##u)(DisasContext *ctx) \
3277 if (unlikely(!ctx->fpu_enabled)) { \
3278 gen_exception(ctx, POWERPC_EXCP_FPU); \
3281 if (unlikely(rA(ctx->opcode) == 0)) { \
3282 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3285 gen_set_access_type(ctx, ACCESS_FLOAT); \
3286 EA = tcg_temp_new(); \
3287 gen_addr_imm_index(ctx, EA, 0); \
3288 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3289 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3290 tcg_temp_free(EA); \
3293 #define GEN_LDUXF(name, ldop, opc, type) \
3294 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type); \
3296 static void glue(gen_, name##ux)(DisasContext *ctx) \
3299 if (unlikely(!ctx->fpu_enabled)) { \
3300 gen_exception(ctx, POWERPC_EXCP_FPU); \
3303 if (unlikely(rA(ctx->opcode) == 0)) { \
3304 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3307 gen_set_access_type(ctx, ACCESS_FLOAT); \
3308 EA = tcg_temp_new(); \
3309 gen_addr_reg_index(ctx, EA); \
3310 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3311 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3312 tcg_temp_free(EA); \
3315 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3316 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type); \
3318 static void glue(gen_, name##x)(DisasContext *ctx) \
3321 if (unlikely(!ctx->fpu_enabled)) { \
3322 gen_exception(ctx, POWERPC_EXCP_FPU); \
3325 gen_set_access_type(ctx, ACCESS_FLOAT); \
3326 EA = tcg_temp_new(); \
3327 gen_addr_reg_index(ctx, EA); \
3328 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3329 tcg_temp_free(EA); \
3332 #define GEN_LDFS(name, ldop, op, type) \
3333 GEN_LDF(name, ldop, op | 0x20, type); \
3334 GEN_LDUF(name, ldop, op | 0x21, type); \
3335 GEN_LDUXF(name, ldop, op | 0x01, type); \
3336 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3338 static always_inline
void gen_qemu_ld32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3340 TCGv t0
= tcg_temp_new();
3341 TCGv_i32 t1
= tcg_temp_new_i32();
3342 gen_qemu_ld32u(ctx
, t0
, arg2
);
3343 tcg_gen_trunc_tl_i32(t1
, t0
);
3345 gen_helper_float32_to_float64(arg1
, t1
);
3346 tcg_temp_free_i32(t1
);
3349 /* lfd lfdu lfdux lfdx */
3350 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
);
3351 /* lfs lfsu lfsux lfsx */
3352 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
);
3354 /*** Floating-point store ***/
3355 #define GEN_STF(name, stop, opc, type) \
3356 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type); \
3358 static void glue(gen_, name)(DisasContext *ctx) \
3361 if (unlikely(!ctx->fpu_enabled)) { \
3362 gen_exception(ctx, POWERPC_EXCP_FPU); \
3365 gen_set_access_type(ctx, ACCESS_FLOAT); \
3366 EA = tcg_temp_new(); \
3367 gen_addr_imm_index(ctx, EA, 0); \
3368 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3369 tcg_temp_free(EA); \
3372 #define GEN_STUF(name, stop, opc, type) \
3373 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type); \
3375 static void glue(gen_, name##u)(DisasContext *ctx) \
3378 if (unlikely(!ctx->fpu_enabled)) { \
3379 gen_exception(ctx, POWERPC_EXCP_FPU); \
3382 if (unlikely(rA(ctx->opcode) == 0)) { \
3383 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3386 gen_set_access_type(ctx, ACCESS_FLOAT); \
3387 EA = tcg_temp_new(); \
3388 gen_addr_imm_index(ctx, EA, 0); \
3389 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3390 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3391 tcg_temp_free(EA); \
3394 #define GEN_STUXF(name, stop, opc, type) \
3395 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type); \
3397 static void glue(gen_, name##ux)(DisasContext *ctx) \
3400 if (unlikely(!ctx->fpu_enabled)) { \
3401 gen_exception(ctx, POWERPC_EXCP_FPU); \
3404 if (unlikely(rA(ctx->opcode) == 0)) { \
3405 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3408 gen_set_access_type(ctx, ACCESS_FLOAT); \
3409 EA = tcg_temp_new(); \
3410 gen_addr_reg_index(ctx, EA); \
3411 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3412 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3413 tcg_temp_free(EA); \
3416 #define GEN_STXF(name, stop, opc2, opc3, type) \
3417 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type); \
3419 static void glue(gen_, name##x)(DisasContext *ctx) \
3422 if (unlikely(!ctx->fpu_enabled)) { \
3423 gen_exception(ctx, POWERPC_EXCP_FPU); \
3426 gen_set_access_type(ctx, ACCESS_FLOAT); \
3427 EA = tcg_temp_new(); \
3428 gen_addr_reg_index(ctx, EA); \
3429 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3430 tcg_temp_free(EA); \
3433 #define GEN_STFS(name, stop, op, type) \
3434 GEN_STF(name, stop, op | 0x20, type); \
3435 GEN_STUF(name, stop, op | 0x21, type); \
3436 GEN_STUXF(name, stop, op | 0x01, type); \
3437 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3439 static always_inline
void gen_qemu_st32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3441 TCGv_i32 t0
= tcg_temp_new_i32();
3442 TCGv t1
= tcg_temp_new();
3443 gen_helper_float64_to_float32(t0
, arg1
);
3444 tcg_gen_extu_i32_tl(t1
, t0
);
3445 tcg_temp_free_i32(t0
);
3446 gen_qemu_st32(ctx
, t1
, arg2
);
3450 /* stfd stfdu stfdux stfdx */
3451 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
);
3452 /* stfs stfsu stfsux stfsx */
3453 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
);
3456 static always_inline
void gen_qemu_st32fiw(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3458 TCGv t0
= tcg_temp_new();
3459 tcg_gen_trunc_i64_tl(t0
, arg1
),
3460 gen_qemu_st32(ctx
, t0
, arg2
);
3464 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
3467 static always_inline
void gen_goto_tb (DisasContext
*ctx
, int n
,
3470 TranslationBlock
*tb
;
3472 #if defined(TARGET_PPC64)
3474 dest
= (uint32_t) dest
;
3476 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
3477 likely(!ctx
->singlestep_enabled
)) {
3479 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3480 tcg_gen_exit_tb((long)tb
+ n
);
3482 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3483 if (unlikely(ctx
->singlestep_enabled
)) {
3484 if ((ctx
->singlestep_enabled
&
3485 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3486 ctx
->exception
== POWERPC_EXCP_BRANCH
) {
3487 target_ulong tmp
= ctx
->nip
;
3489 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3492 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3493 gen_debug_exception(ctx
);
3500 static always_inline
void gen_setlr (DisasContext
*ctx
, target_ulong nip
)
3502 #if defined(TARGET_PPC64)
3503 if (ctx
->sf_mode
== 0)
3504 tcg_gen_movi_tl(cpu_lr
, (uint32_t)nip
);
3507 tcg_gen_movi_tl(cpu_lr
, nip
);
3511 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
);
3513 static void gen_b(DisasContext
*ctx
)
3515 target_ulong li
, target
;
3517 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3518 /* sign extend LI */
3519 #if defined(TARGET_PPC64)
3521 li
= ((int64_t)LI(ctx
->opcode
) << 38) >> 38;
3524 li
= ((int32_t)LI(ctx
->opcode
) << 6) >> 6;
3525 if (likely(AA(ctx
->opcode
) == 0))
3526 target
= ctx
->nip
+ li
- 4;
3529 if (LK(ctx
->opcode
))
3530 gen_setlr(ctx
, ctx
->nip
);
3531 gen_goto_tb(ctx
, 0, target
);
3538 static always_inline
void gen_bcond (DisasContext
*ctx
, int type
)
3540 uint32_t bo
= BO(ctx
->opcode
);
3541 int l1
= gen_new_label();
3544 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3545 if (type
== BCOND_LR
|| type
== BCOND_CTR
) {
3546 target
= tcg_temp_local_new();
3547 if (type
== BCOND_CTR
)
3548 tcg_gen_mov_tl(target
, cpu_ctr
);
3550 tcg_gen_mov_tl(target
, cpu_lr
);
3552 if (LK(ctx
->opcode
))
3553 gen_setlr(ctx
, ctx
->nip
);
3554 l1
= gen_new_label();
3555 if ((bo
& 0x4) == 0) {
3556 /* Decrement and test CTR */
3557 TCGv temp
= tcg_temp_new();
3558 if (unlikely(type
== BCOND_CTR
)) {
3559 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3562 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3563 #if defined(TARGET_PPC64)
3565 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3568 tcg_gen_mov_tl(temp
, cpu_ctr
);
3570 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3572 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3574 tcg_temp_free(temp
);
3576 if ((bo
& 0x10) == 0) {
3578 uint32_t bi
= BI(ctx
->opcode
);
3579 uint32_t mask
= 1 << (3 - (bi
& 0x03));
3580 TCGv_i32 temp
= tcg_temp_new_i32();
3583 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3584 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3586 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3587 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3589 tcg_temp_free_i32(temp
);
3591 if (type
== BCOND_IM
) {
3592 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3593 if (likely(AA(ctx
->opcode
) == 0)) {
3594 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3596 gen_goto_tb(ctx
, 0, li
);
3599 gen_goto_tb(ctx
, 1, ctx
->nip
);
3601 #if defined(TARGET_PPC64)
3602 if (!(ctx
->sf_mode
))
3603 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3606 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3609 #if defined(TARGET_PPC64)
3610 if (!(ctx
->sf_mode
))
3611 tcg_gen_movi_tl(cpu_nip
, (uint32_t)ctx
->nip
);
3614 tcg_gen_movi_tl(cpu_nip
, ctx
->nip
);
3619 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
);
3621 static void gen_bc(DisasContext
*ctx
)
3623 gen_bcond(ctx
, BCOND_IM
);
3626 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
);
3628 static void gen_bcctr(DisasContext
*ctx
)
3630 gen_bcond(ctx
, BCOND_CTR
);
3633 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
);
3635 static void gen_bclr(DisasContext
*ctx
)
3637 gen_bcond(ctx
, BCOND_LR
);
3640 /*** Condition register logical ***/
3641 #define GEN_CRLOGIC(name, tcg_op, opc) \
3642 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER); \
3644 static void glue(gen_, name)(DisasContext *ctx) \
3649 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3650 t0 = tcg_temp_new_i32(); \
3652 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3654 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3656 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3657 t1 = tcg_temp_new_i32(); \
3658 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3660 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3662 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3664 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3665 tcg_op(t0, t0, t1); \
3666 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3667 tcg_gen_andi_i32(t0, t0, bitmask); \
3668 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3669 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3670 tcg_temp_free_i32(t0); \
3671 tcg_temp_free_i32(t1); \
3675 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3677 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3679 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3681 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3683 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3685 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3687 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3689 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3691 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
);
3693 static void gen_mcrf(DisasContext
*ctx
)
3695 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3698 /*** System linkage ***/
3699 /* rfi (mem_idx only) */
3700 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
);
3702 static void gen_rfi(DisasContext
*ctx
)
3704 #if defined(CONFIG_USER_ONLY)
3705 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3707 /* Restore CPU state */
3708 if (unlikely(!ctx
->mem_idx
)) {
3709 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3713 gen_sync_exception(ctx
);
3717 #if defined(TARGET_PPC64)
3718 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
);
3720 static void gen_rfid(DisasContext
*ctx
)
3722 #if defined(CONFIG_USER_ONLY)
3723 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3725 /* Restore CPU state */
3726 if (unlikely(!ctx
->mem_idx
)) {
3727 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3731 gen_sync_exception(ctx
);
3735 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
);
3737 static void gen_hrfid(DisasContext
*ctx
)
3739 #if defined(CONFIG_USER_ONLY)
3740 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3742 /* Restore CPU state */
3743 if (unlikely(ctx
->mem_idx
<= 1)) {
3744 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3748 gen_sync_exception(ctx
);
3754 #if defined(CONFIG_USER_ONLY)
3755 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3757 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3759 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
);
3761 static void gen_sc(DisasContext
*ctx
)
3765 lev
= (ctx
->opcode
>> 5) & 0x7F;
3766 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3771 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
);
3773 static void gen_tw(DisasContext
*ctx
)
3775 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3776 /* Update the nip since this might generate a trap exception */
3777 gen_update_nip(ctx
, ctx
->nip
);
3778 gen_helper_tw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
3779 tcg_temp_free_i32(t0
);
3783 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
);
3785 static void gen_twi(DisasContext
*ctx
)
3787 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3788 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3789 /* Update the nip since this might generate a trap exception */
3790 gen_update_nip(ctx
, ctx
->nip
);
3791 gen_helper_tw(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3793 tcg_temp_free_i32(t1
);
3796 #if defined(TARGET_PPC64)
3798 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
);
3800 static void gen_td(DisasContext
*ctx
)
3802 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3803 /* Update the nip since this might generate a trap exception */
3804 gen_update_nip(ctx
, ctx
->nip
);
3805 gen_helper_td(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
3806 tcg_temp_free_i32(t0
);
3810 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
);
3812 static void gen_tdi(DisasContext
*ctx
)
3814 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3815 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3816 /* Update the nip since this might generate a trap exception */
3817 gen_update_nip(ctx
, ctx
->nip
);
3818 gen_helper_td(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3820 tcg_temp_free_i32(t1
);
3824 /*** Processor control ***/
3826 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
);
3828 static void gen_mcrxr(DisasContext
*ctx
)
3830 tcg_gen_trunc_tl_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_xer
);
3831 tcg_gen_shri_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], XER_CA
);
3832 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_SO
| 1 << XER_OV
| 1 << XER_CA
));
3836 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
);
3838 static void gen_mfcr(DisasContext
*ctx
)
3842 if (likely(ctx
->opcode
& 0x00100000)) {
3843 crm
= CRM(ctx
->opcode
);
3844 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
3846 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
3847 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
3848 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
3851 TCGv_i32 t0
= tcg_temp_new_i32();
3852 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
3853 tcg_gen_shli_i32(t0
, t0
, 4);
3854 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
3855 tcg_gen_shli_i32(t0
, t0
, 4);
3856 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
3857 tcg_gen_shli_i32(t0
, t0
, 4);
3858 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
3859 tcg_gen_shli_i32(t0
, t0
, 4);
3860 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
3861 tcg_gen_shli_i32(t0
, t0
, 4);
3862 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
3863 tcg_gen_shli_i32(t0
, t0
, 4);
3864 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
3865 tcg_gen_shli_i32(t0
, t0
, 4);
3866 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
3867 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
3868 tcg_temp_free_i32(t0
);
3873 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
);
3875 static void gen_mfmsr(DisasContext
*ctx
)
3877 #if defined(CONFIG_USER_ONLY)
3878 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3880 if (unlikely(!ctx
->mem_idx
)) {
3881 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3884 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
3889 #define SPR_NOACCESS ((void *)(-1UL))
3891 static void spr_noaccess (void *opaque
, int sprn
)
3893 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3894 printf("ERROR: try to access SPR %d !\n", sprn
);
3896 #define SPR_NOACCESS (&spr_noaccess)
3900 static always_inline
void gen_op_mfspr (DisasContext
*ctx
)
3902 void (*read_cb
)(void *opaque
, int gprn
, int sprn
);
3903 uint32_t sprn
= SPR(ctx
->opcode
);
3905 #if !defined(CONFIG_USER_ONLY)
3906 if (ctx
->mem_idx
== 2)
3907 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3908 else if (ctx
->mem_idx
)
3909 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3912 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3913 if (likely(read_cb
!= NULL
)) {
3914 if (likely(read_cb
!= SPR_NOACCESS
)) {
3915 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
3917 /* Privilege exception */
3918 /* This is a hack to avoid warnings when running Linux:
3919 * this OS breaks the PowerPC virtualisation model,
3920 * allowing userland application to read the PVR
3922 if (sprn
!= SPR_PVR
) {
3923 qemu_log("Trying to read privileged spr %d %03x at "
3924 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3925 printf("Trying to read privileged spr %d %03x at " ADDRX
"\n",
3926 sprn
, sprn
, ctx
->nip
);
3928 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3932 qemu_log("Trying to read invalid spr %d %03x at "
3933 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
3934 printf("Trying to read invalid spr %d %03x at " ADDRX
"\n",
3935 sprn
, sprn
, ctx
->nip
);
3936 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3940 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
);
3942 static void gen_mfspr(DisasContext
*ctx
)
3948 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
);
3950 static void gen_mftb(DisasContext
*ctx
)
3956 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
);
3958 static void gen_mtcrf(DisasContext
*ctx
)
3962 crm
= CRM(ctx
->opcode
);
3963 if (likely((ctx
->opcode
& 0x00100000))) {
3964 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
3965 TCGv_i32 temp
= tcg_temp_new_i32();
3967 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3968 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
3969 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
3970 tcg_temp_free_i32(temp
);
3973 TCGv_i32 temp
= tcg_temp_new_i32();
3974 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3975 for (crn
= 0 ; crn
< 8 ; crn
++) {
3976 if (crm
& (1 << crn
)) {
3977 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
3978 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
3981 tcg_temp_free_i32(temp
);
3986 #if defined(TARGET_PPC64)
3987 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
);
3989 static void gen_mtmsrd(DisasContext
*ctx
)
3991 #if defined(CONFIG_USER_ONLY)
3992 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3994 if (unlikely(!ctx
->mem_idx
)) {
3995 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3998 if (ctx
->opcode
& 0x00010000) {
3999 /* Special form that does not need any synchronisation */
4000 TCGv t0
= tcg_temp_new();
4001 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4002 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
4003 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4006 /* XXX: we need to update nip before the store
4007 * if we enter power saving mode, we will exit the loop
4008 * directly from ppc_store_msr
4010 gen_update_nip(ctx
, ctx
->nip
);
4011 gen_helper_store_msr(cpu_gpr
[rS(ctx
->opcode
)]);
4012 /* Must stop the translation as machine state (may have) changed */
4013 /* Note that mtmsr is not always defined as context-synchronizing */
4014 gen_stop_exception(ctx
);
4020 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
);
4022 static void gen_mtmsr(DisasContext
*ctx
)
4024 #if defined(CONFIG_USER_ONLY)
4025 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4027 if (unlikely(!ctx
->mem_idx
)) {
4028 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4031 if (ctx
->opcode
& 0x00010000) {
4032 /* Special form that does not need any synchronisation */
4033 TCGv t0
= tcg_temp_new();
4034 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4035 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
4036 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4039 /* XXX: we need to update nip before the store
4040 * if we enter power saving mode, we will exit the loop
4041 * directly from ppc_store_msr
4043 gen_update_nip(ctx
, ctx
->nip
);
4044 #if defined(TARGET_PPC64)
4045 if (!ctx
->sf_mode
) {
4046 TCGv t0
= tcg_temp_new();
4047 TCGv t1
= tcg_temp_new();
4048 tcg_gen_andi_tl(t0
, cpu_msr
, 0xFFFFFFFF00000000ULL
);
4049 tcg_gen_ext32u_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
4050 tcg_gen_or_tl(t0
, t0
, t1
);
4052 gen_helper_store_msr(t0
);
4056 gen_helper_store_msr(cpu_gpr
[rS(ctx
->opcode
)]);
4057 /* Must stop the translation as machine state (may have) changed */
4058 /* Note that mtmsr is not always defined as context-synchronizing */
4059 gen_stop_exception(ctx
);
4065 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
);
4067 static void gen_mtspr(DisasContext
*ctx
)
4069 void (*write_cb
)(void *opaque
, int sprn
, int gprn
);
4070 uint32_t sprn
= SPR(ctx
->opcode
);
4072 #if !defined(CONFIG_USER_ONLY)
4073 if (ctx
->mem_idx
== 2)
4074 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4075 else if (ctx
->mem_idx
)
4076 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4079 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4080 if (likely(write_cb
!= NULL
)) {
4081 if (likely(write_cb
!= SPR_NOACCESS
)) {
4082 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4084 /* Privilege exception */
4085 qemu_log("Trying to write privileged spr %d %03x at "
4086 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
4087 printf("Trying to write privileged spr %d %03x at " ADDRX
"\n",
4088 sprn
, sprn
, ctx
->nip
);
4089 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4093 qemu_log("Trying to write invalid spr %d %03x at "
4094 ADDRX
"\n", sprn
, sprn
, ctx
->nip
);
4095 printf("Trying to write invalid spr %d %03x at " ADDRX
"\n",
4096 sprn
, sprn
, ctx
->nip
);
4097 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4101 /*** Cache management ***/
4103 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
);
4105 static void gen_dcbf(DisasContext
*ctx
)
4107 /* XXX: specification says this is treated as a load by the MMU */
4109 gen_set_access_type(ctx
, ACCESS_CACHE
);
4110 t0
= tcg_temp_new();
4111 gen_addr_reg_index(ctx
, t0
);
4112 gen_qemu_ld8u(ctx
, t0
, t0
);
4116 /* dcbi (Supervisor only) */
4117 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
);
4119 static void gen_dcbi(DisasContext
*ctx
)
4121 #if defined(CONFIG_USER_ONLY)
4122 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4125 if (unlikely(!ctx
->mem_idx
)) {
4126 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4129 EA
= tcg_temp_new();
4130 gen_set_access_type(ctx
, ACCESS_CACHE
);
4131 gen_addr_reg_index(ctx
, EA
);
4132 val
= tcg_temp_new();
4133 /* XXX: specification says this should be treated as a store by the MMU */
4134 gen_qemu_ld8u(ctx
, val
, EA
);
4135 gen_qemu_st8(ctx
, val
, EA
);
4142 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
);
4144 static void gen_dcbst(DisasContext
*ctx
)
4146 /* XXX: specification say this is treated as a load by the MMU */
4148 gen_set_access_type(ctx
, ACCESS_CACHE
);
4149 t0
= tcg_temp_new();
4150 gen_addr_reg_index(ctx
, t0
);
4151 gen_qemu_ld8u(ctx
, t0
, t0
);
4156 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE
);
4158 static void gen_dcbt(DisasContext
*ctx
)
4160 /* interpreted as no-op */
4161 /* XXX: specification say this is treated as a load by the MMU
4162 * but does not generate any exception
4167 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE
);
4169 static void gen_dcbtst(DisasContext
*ctx
)
4171 /* interpreted as no-op */
4172 /* XXX: specification say this is treated as a load by the MMU
4173 * but does not generate any exception
4178 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ
);
4180 static void gen_dcbz(DisasContext
*ctx
)
4183 gen_set_access_type(ctx
, ACCESS_CACHE
);
4184 /* NIP cannot be restored if the memory exception comes from an helper */
4185 gen_update_nip(ctx
, ctx
->nip
- 4);
4186 t0
= tcg_temp_new();
4187 gen_addr_reg_index(ctx
, t0
);
4188 gen_helper_dcbz(t0
);
4192 GEN_HANDLER2(dcbz_970
, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT
)
4195 gen_set_access_type(ctx
, ACCESS_CACHE
);
4196 /* NIP cannot be restored if the memory exception comes from an helper */
4197 gen_update_nip(ctx
, ctx
->nip
- 4);
4198 t0
= tcg_temp_new();
4199 gen_addr_reg_index(ctx
, t0
);
4200 if (ctx
->opcode
& 0x00200000)
4201 gen_helper_dcbz(t0
);
4203 gen_helper_dcbz_970(t0
);
4208 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
);
4210 static void gen_dst(DisasContext
*ctx
)
4212 if (rA(ctx
->opcode
) == 0) {
4213 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4215 /* interpreted as no-op */
4220 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
);
4222 static void gen_dstst(DisasContext
*ctx
)
4224 if (rA(ctx
->opcode
) == 0) {
4225 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4227 /* interpreted as no-op */
4233 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
);
4235 static void gen_dss(DisasContext
*ctx
)
4237 /* interpreted as no-op */
4241 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
);
4243 static void gen_icbi(DisasContext
*ctx
)
4246 gen_set_access_type(ctx
, ACCESS_CACHE
);
4247 /* NIP cannot be restored if the memory exception comes from an helper */
4248 gen_update_nip(ctx
, ctx
->nip
- 4);
4249 t0
= tcg_temp_new();
4250 gen_addr_reg_index(ctx
, t0
);
4251 gen_helper_icbi(t0
);
4257 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
);
4259 static void gen_dcba(DisasContext
*ctx
)
4261 /* interpreted as no-op */
4262 /* XXX: specification say this is treated as a store by the MMU
4263 * but does not generate any exception
4267 /*** Segment register manipulation ***/
4268 /* Supervisor only: */
4270 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
);
4272 static void gen_mfsr(DisasContext
*ctx
)
4274 #if defined(CONFIG_USER_ONLY)
4275 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4278 if (unlikely(!ctx
->mem_idx
)) {
4279 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4282 t0
= tcg_const_tl(SR(ctx
->opcode
));
4283 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4289 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
);
4291 static void gen_mfsrin(DisasContext
*ctx
)
4293 #if defined(CONFIG_USER_ONLY)
4294 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4297 if (unlikely(!ctx
->mem_idx
)) {
4298 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4301 t0
= tcg_temp_new();
4302 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4303 tcg_gen_andi_tl(t0
, t0
, 0xF);
4304 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4310 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
);
4312 static void gen_mtsr(DisasContext
*ctx
)
4314 #if defined(CONFIG_USER_ONLY)
4315 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4318 if (unlikely(!ctx
->mem_idx
)) {
4319 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4322 t0
= tcg_const_tl(SR(ctx
->opcode
));
4323 gen_helper_store_sr(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4329 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
);
4331 static void gen_mtsrin(DisasContext
*ctx
)
4333 #if defined(CONFIG_USER_ONLY)
4334 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4337 if (unlikely(!ctx
->mem_idx
)) {
4338 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4341 t0
= tcg_temp_new();
4342 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4343 tcg_gen_andi_tl(t0
, t0
, 0xF);
4344 gen_helper_store_sr(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4349 #if defined(TARGET_PPC64)
4350 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4352 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
)
4354 #if defined(CONFIG_USER_ONLY)
4355 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4358 if (unlikely(!ctx
->mem_idx
)) {
4359 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4362 t0
= tcg_const_tl(SR(ctx
->opcode
));
4363 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4369 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4372 #if defined(CONFIG_USER_ONLY)
4373 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4376 if (unlikely(!ctx
->mem_idx
)) {
4377 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4380 t0
= tcg_temp_new();
4381 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4382 tcg_gen_andi_tl(t0
, t0
, 0xF);
4383 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4389 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
)
4391 #if defined(CONFIG_USER_ONLY)
4392 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4395 if (unlikely(!ctx
->mem_idx
)) {
4396 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4399 t0
= tcg_const_tl(SR(ctx
->opcode
));
4400 gen_helper_store_sr(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4406 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4409 #if defined(CONFIG_USER_ONLY)
4410 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4413 if (unlikely(!ctx
->mem_idx
)) {
4414 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4417 t0
= tcg_temp_new();
4418 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4419 tcg_gen_andi_tl(t0
, t0
, 0xF);
4420 gen_helper_store_sr(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4426 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B
)
4428 #if defined(CONFIG_USER_ONLY)
4429 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4431 if (unlikely(!ctx
->mem_idx
)) {
4432 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4435 gen_helper_store_slb(cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
4439 #endif /* defined(TARGET_PPC64) */
4441 /*** Lookaside buffer management ***/
4442 /* Optional & mem_idx only: */
4444 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
);
4446 static void gen_tlbia(DisasContext
*ctx
)
4448 #if defined(CONFIG_USER_ONLY)
4449 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4451 if (unlikely(!ctx
->mem_idx
)) {
4452 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4460 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE
);
4462 static void gen_tlbiel(DisasContext
*ctx
)
4464 #if defined(CONFIG_USER_ONLY)
4465 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4467 if (unlikely(!ctx
->mem_idx
)) {
4468 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4471 gen_helper_tlbie(cpu_gpr
[rB(ctx
->opcode
)]);
4476 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
);
4478 static void gen_tlbie(DisasContext
*ctx
)
4480 #if defined(CONFIG_USER_ONLY)
4481 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4483 if (unlikely(!ctx
->mem_idx
)) {
4484 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4487 #if defined(TARGET_PPC64)
4488 if (!ctx
->sf_mode
) {
4489 TCGv t0
= tcg_temp_new();
4490 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4491 gen_helper_tlbie(t0
);
4495 gen_helper_tlbie(cpu_gpr
[rB(ctx
->opcode
)]);
4500 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
);
4502 static void gen_tlbsync(DisasContext
*ctx
)
4504 #if defined(CONFIG_USER_ONLY)
4505 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4507 if (unlikely(!ctx
->mem_idx
)) {
4508 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4511 /* This has no effect: it should ensure that all previous
4512 * tlbie have completed
4514 gen_stop_exception(ctx
);
4518 #if defined(TARGET_PPC64)
4520 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
);
4522 static void gen_slbia(DisasContext
*ctx
)
4524 #if defined(CONFIG_USER_ONLY)
4525 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4527 if (unlikely(!ctx
->mem_idx
)) {
4528 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4536 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
);
4538 static void gen_slbie(DisasContext
*ctx
)
4540 #if defined(CONFIG_USER_ONLY)
4541 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4543 if (unlikely(!ctx
->mem_idx
)) {
4544 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4547 gen_helper_slbie(cpu_gpr
[rB(ctx
->opcode
)]);
4552 /*** External control ***/
4555 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
);
4557 static void gen_eciwx(DisasContext
*ctx
)
4560 /* Should check EAR[E] ! */
4561 gen_set_access_type(ctx
, ACCESS_EXT
);
4562 t0
= tcg_temp_new();
4563 gen_addr_reg_index(ctx
, t0
);
4564 gen_check_align(ctx
, t0
, 0x03);
4565 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4570 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
);
4572 static void gen_ecowx(DisasContext
*ctx
)
4575 /* Should check EAR[E] ! */
4576 gen_set_access_type(ctx
, ACCESS_EXT
);
4577 t0
= tcg_temp_new();
4578 gen_addr_reg_index(ctx
, t0
);
4579 gen_check_align(ctx
, t0
, 0x03);
4580 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4584 /* PowerPC 601 specific instructions */
4586 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
);
4588 static void gen_abs(DisasContext
*ctx
)
4590 int l1
= gen_new_label();
4591 int l2
= gen_new_label();
4592 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4593 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4596 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4598 if (unlikely(Rc(ctx
->opcode
) != 0))
4599 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4603 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
);
4605 static void gen_abso(DisasContext
*ctx
)
4607 int l1
= gen_new_label();
4608 int l2
= gen_new_label();
4609 int l3
= gen_new_label();
4610 /* Start with XER OV disabled, the most likely case */
4611 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4612 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4613 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4614 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4617 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4620 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4622 if (unlikely(Rc(ctx
->opcode
) != 0))
4623 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4627 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
);
4629 static void gen_clcs(DisasContext
*ctx
)
4631 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4632 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4633 tcg_temp_free_i32(t0
);
4634 /* Rc=1 sets CR0 to an undefined state */
4638 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
);
4640 static void gen_div(DisasContext
*ctx
)
4642 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4643 if (unlikely(Rc(ctx
->opcode
) != 0))
4644 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4648 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
);
4650 static void gen_divo(DisasContext
*ctx
)
4652 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4653 if (unlikely(Rc(ctx
->opcode
) != 0))
4654 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4658 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
);
4660 static void gen_divs(DisasContext
*ctx
)
4662 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4663 if (unlikely(Rc(ctx
->opcode
) != 0))
4664 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4667 /* divso - divso. */
4668 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
);
4670 static void gen_divso(DisasContext
*ctx
)
4672 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4673 if (unlikely(Rc(ctx
->opcode
) != 0))
4674 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4678 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
);
4680 static void gen_doz(DisasContext
*ctx
)
4682 int l1
= gen_new_label();
4683 int l2
= gen_new_label();
4684 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4685 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4688 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4690 if (unlikely(Rc(ctx
->opcode
) != 0))
4691 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4695 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
);
4697 static void gen_dozo(DisasContext
*ctx
)
4699 int l1
= gen_new_label();
4700 int l2
= gen_new_label();
4701 TCGv t0
= tcg_temp_new();
4702 TCGv t1
= tcg_temp_new();
4703 TCGv t2
= tcg_temp_new();
4704 /* Start with XER OV disabled, the most likely case */
4705 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4706 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4707 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4708 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4709 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
4710 tcg_gen_andc_tl(t1
, t1
, t2
);
4711 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4712 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4713 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4716 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4721 if (unlikely(Rc(ctx
->opcode
) != 0))
4722 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4726 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
);
4728 static void gen_dozi(DisasContext
*ctx
)
4730 target_long simm
= SIMM(ctx
->opcode
);
4731 int l1
= gen_new_label();
4732 int l2
= gen_new_label();
4733 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
4734 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
4737 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4739 if (unlikely(Rc(ctx
->opcode
) != 0))
4740 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4743 /* lscbx - lscbx. */
4744 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
);
4746 static void gen_lscbx(DisasContext
*ctx
)
4748 TCGv t0
= tcg_temp_new();
4749 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
4750 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
4751 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
4753 gen_addr_reg_index(ctx
, t0
);
4754 /* NIP cannot be restored if the memory exception comes from an helper */
4755 gen_update_nip(ctx
, ctx
->nip
- 4);
4756 gen_helper_lscbx(t0
, t0
, t1
, t2
, t3
);
4757 tcg_temp_free_i32(t1
);
4758 tcg_temp_free_i32(t2
);
4759 tcg_temp_free_i32(t3
);
4760 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
4761 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
4762 if (unlikely(Rc(ctx
->opcode
) != 0))
4763 gen_set_Rc0(ctx
, t0
);
4767 /* maskg - maskg. */
4768 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
);
4770 static void gen_maskg(DisasContext
*ctx
)
4772 int l1
= gen_new_label();
4773 TCGv t0
= tcg_temp_new();
4774 TCGv t1
= tcg_temp_new();
4775 TCGv t2
= tcg_temp_new();
4776 TCGv t3
= tcg_temp_new();
4777 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
4778 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4779 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
4780 tcg_gen_addi_tl(t2
, t0
, 1);
4781 tcg_gen_shr_tl(t2
, t3
, t2
);
4782 tcg_gen_shr_tl(t3
, t3
, t1
);
4783 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
4784 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4785 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4791 if (unlikely(Rc(ctx
->opcode
) != 0))
4792 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4795 /* maskir - maskir. */
4796 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
);
4798 static void gen_maskir(DisasContext
*ctx
)
4800 TCGv t0
= tcg_temp_new();
4801 TCGv t1
= tcg_temp_new();
4802 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4803 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4804 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4807 if (unlikely(Rc(ctx
->opcode
) != 0))
4808 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4812 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
);
4814 static void gen_mul(DisasContext
*ctx
)
4816 TCGv_i64 t0
= tcg_temp_new_i64();
4817 TCGv_i64 t1
= tcg_temp_new_i64();
4818 TCGv t2
= tcg_temp_new();
4819 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4820 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4821 tcg_gen_mul_i64(t0
, t0
, t1
);
4822 tcg_gen_trunc_i64_tl(t2
, t0
);
4823 gen_store_spr(SPR_MQ
, t2
);
4824 tcg_gen_shri_i64(t1
, t0
, 32);
4825 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4826 tcg_temp_free_i64(t0
);
4827 tcg_temp_free_i64(t1
);
4829 if (unlikely(Rc(ctx
->opcode
) != 0))
4830 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4834 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
);
4836 static void gen_mulo(DisasContext
*ctx
)
4838 int l1
= gen_new_label();
4839 TCGv_i64 t0
= tcg_temp_new_i64();
4840 TCGv_i64 t1
= tcg_temp_new_i64();
4841 TCGv t2
= tcg_temp_new();
4842 /* Start with XER OV disabled, the most likely case */
4843 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4844 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4845 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4846 tcg_gen_mul_i64(t0
, t0
, t1
);
4847 tcg_gen_trunc_i64_tl(t2
, t0
);
4848 gen_store_spr(SPR_MQ
, t2
);
4849 tcg_gen_shri_i64(t1
, t0
, 32);
4850 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4851 tcg_gen_ext32s_i64(t1
, t0
);
4852 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
4853 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4855 tcg_temp_free_i64(t0
);
4856 tcg_temp_free_i64(t1
);
4858 if (unlikely(Rc(ctx
->opcode
) != 0))
4859 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4863 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
);
4865 static void gen_nabs(DisasContext
*ctx
)
4867 int l1
= gen_new_label();
4868 int l2
= gen_new_label();
4869 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4870 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4873 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4875 if (unlikely(Rc(ctx
->opcode
) != 0))
4876 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4879 /* nabso - nabso. */
4880 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
);
4882 static void gen_nabso(DisasContext
*ctx
)
4884 int l1
= gen_new_label();
4885 int l2
= gen_new_label();
4886 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4887 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4890 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4892 /* nabs never overflows */
4893 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4894 if (unlikely(Rc(ctx
->opcode
) != 0))
4895 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4899 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
);
4901 static void gen_rlmi(DisasContext
*ctx
)
4903 uint32_t mb
= MB(ctx
->opcode
);
4904 uint32_t me
= ME(ctx
->opcode
);
4905 TCGv t0
= tcg_temp_new();
4906 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4907 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4908 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
4909 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
4910 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
4912 if (unlikely(Rc(ctx
->opcode
) != 0))
4913 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4917 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
);
4919 static void gen_rrib(DisasContext
*ctx
)
4921 TCGv t0
= tcg_temp_new();
4922 TCGv t1
= tcg_temp_new();
4923 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4924 tcg_gen_movi_tl(t1
, 0x80000000);
4925 tcg_gen_shr_tl(t1
, t1
, t0
);
4926 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4927 tcg_gen_and_tl(t0
, t0
, t1
);
4928 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
4929 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4932 if (unlikely(Rc(ctx
->opcode
) != 0))
4933 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4937 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
);
4939 static void gen_sle(DisasContext
*ctx
)
4941 TCGv t0
= tcg_temp_new();
4942 TCGv t1
= tcg_temp_new();
4943 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4944 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4945 tcg_gen_subfi_tl(t1
, 32, t1
);
4946 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4947 tcg_gen_or_tl(t1
, t0
, t1
);
4948 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4949 gen_store_spr(SPR_MQ
, t1
);
4952 if (unlikely(Rc(ctx
->opcode
) != 0))
4953 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4957 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
);
4959 static void gen_sleq(DisasContext
*ctx
)
4961 TCGv t0
= tcg_temp_new();
4962 TCGv t1
= tcg_temp_new();
4963 TCGv t2
= tcg_temp_new();
4964 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4965 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
4966 tcg_gen_shl_tl(t2
, t2
, t0
);
4967 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4968 gen_load_spr(t1
, SPR_MQ
);
4969 gen_store_spr(SPR_MQ
, t0
);
4970 tcg_gen_and_tl(t0
, t0
, t2
);
4971 tcg_gen_andc_tl(t1
, t1
, t2
);
4972 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4976 if (unlikely(Rc(ctx
->opcode
) != 0))
4977 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4981 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
);
4983 static void gen_sliq(DisasContext
*ctx
)
4985 int sh
= SH(ctx
->opcode
);
4986 TCGv t0
= tcg_temp_new();
4987 TCGv t1
= tcg_temp_new();
4988 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4989 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4990 tcg_gen_or_tl(t1
, t0
, t1
);
4991 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4992 gen_store_spr(SPR_MQ
, t1
);
4995 if (unlikely(Rc(ctx
->opcode
) != 0))
4996 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4999 /* slliq - slliq. */
5000 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
);
5002 static void gen_slliq(DisasContext
*ctx
)
5004 int sh
= SH(ctx
->opcode
);
5005 TCGv t0
= tcg_temp_new();
5006 TCGv t1
= tcg_temp_new();
5007 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5008 gen_load_spr(t1
, SPR_MQ
);
5009 gen_store_spr(SPR_MQ
, t0
);
5010 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
5011 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
5012 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5015 if (unlikely(Rc(ctx
->opcode
) != 0))
5016 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5020 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
);
5022 static void gen_sllq(DisasContext
*ctx
)
5024 int l1
= gen_new_label();
5025 int l2
= gen_new_label();
5026 TCGv t0
= tcg_temp_local_new();
5027 TCGv t1
= tcg_temp_local_new();
5028 TCGv t2
= tcg_temp_local_new();
5029 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5030 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5031 tcg_gen_shl_tl(t1
, t1
, t2
);
5032 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5033 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5034 gen_load_spr(t0
, SPR_MQ
);
5035 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5038 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5039 gen_load_spr(t2
, SPR_MQ
);
5040 tcg_gen_andc_tl(t1
, t2
, t1
);
5041 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5046 if (unlikely(Rc(ctx
->opcode
) != 0))
5047 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5051 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
);
5053 static void gen_slq(DisasContext
*ctx
)
5055 int l1
= gen_new_label();
5056 TCGv t0
= tcg_temp_new();
5057 TCGv t1
= tcg_temp_new();
5058 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5059 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5060 tcg_gen_subfi_tl(t1
, 32, t1
);
5061 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5062 tcg_gen_or_tl(t1
, t0
, t1
);
5063 gen_store_spr(SPR_MQ
, t1
);
5064 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5065 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5066 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5067 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5071 if (unlikely(Rc(ctx
->opcode
) != 0))
5072 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5075 /* sraiq - sraiq. */
5076 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
);
5078 static void gen_sraiq(DisasContext
*ctx
)
5080 int sh
= SH(ctx
->opcode
);
5081 int l1
= gen_new_label();
5082 TCGv t0
= tcg_temp_new();
5083 TCGv t1
= tcg_temp_new();
5084 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5085 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5086 tcg_gen_or_tl(t0
, t0
, t1
);
5087 gen_store_spr(SPR_MQ
, t0
);
5088 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
5089 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5090 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
5091 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_CA
));
5093 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
5096 if (unlikely(Rc(ctx
->opcode
) != 0))
5097 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5101 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
);
5103 static void gen_sraq(DisasContext
*ctx
)
5105 int l1
= gen_new_label();
5106 int l2
= gen_new_label();
5107 TCGv t0
= tcg_temp_new();
5108 TCGv t1
= tcg_temp_local_new();
5109 TCGv t2
= tcg_temp_local_new();
5110 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5111 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5112 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5113 tcg_gen_subfi_tl(t2
, 32, t2
);
5114 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5115 tcg_gen_or_tl(t0
, t0
, t2
);
5116 gen_store_spr(SPR_MQ
, t0
);
5117 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5118 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5119 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5120 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5123 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5124 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
5125 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5126 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5127 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_CA
));
5131 if (unlikely(Rc(ctx
->opcode
) != 0))
5132 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5136 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
);
5138 static void gen_sre(DisasContext
*ctx
)
5140 TCGv t0
= tcg_temp_new();
5141 TCGv t1
= tcg_temp_new();
5142 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5143 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5144 tcg_gen_subfi_tl(t1
, 32, t1
);
5145 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5146 tcg_gen_or_tl(t1
, t0
, t1
);
5147 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5148 gen_store_spr(SPR_MQ
, t1
);
5151 if (unlikely(Rc(ctx
->opcode
) != 0))
5152 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5156 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
);
5158 static void gen_srea(DisasContext
*ctx
)
5160 TCGv t0
= tcg_temp_new();
5161 TCGv t1
= tcg_temp_new();
5162 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5163 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5164 gen_store_spr(SPR_MQ
, t0
);
5165 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5168 if (unlikely(Rc(ctx
->opcode
) != 0))
5169 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5173 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
);
5175 static void gen_sreq(DisasContext
*ctx
)
5177 TCGv t0
= tcg_temp_new();
5178 TCGv t1
= tcg_temp_new();
5179 TCGv t2
= tcg_temp_new();
5180 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5181 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5182 tcg_gen_shr_tl(t1
, t1
, t0
);
5183 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5184 gen_load_spr(t2
, SPR_MQ
);
5185 gen_store_spr(SPR_MQ
, t0
);
5186 tcg_gen_and_tl(t0
, t0
, t1
);
5187 tcg_gen_andc_tl(t2
, t2
, t1
);
5188 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5192 if (unlikely(Rc(ctx
->opcode
) != 0))
5193 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5197 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
);
5199 static void gen_sriq(DisasContext
*ctx
)
5201 int sh
= SH(ctx
->opcode
);
5202 TCGv t0
= tcg_temp_new();
5203 TCGv t1
= tcg_temp_new();
5204 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5205 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5206 tcg_gen_or_tl(t1
, t0
, t1
);
5207 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5208 gen_store_spr(SPR_MQ
, t1
);
5211 if (unlikely(Rc(ctx
->opcode
) != 0))
5212 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5216 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
);
5218 static void gen_srliq(DisasContext
*ctx
)
5220 int sh
= SH(ctx
->opcode
);
5221 TCGv t0
= tcg_temp_new();
5222 TCGv t1
= tcg_temp_new();
5223 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5224 gen_load_spr(t1
, SPR_MQ
);
5225 gen_store_spr(SPR_MQ
, t0
);
5226 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5227 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5228 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5231 if (unlikely(Rc(ctx
->opcode
) != 0))
5232 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5236 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
);
5238 static void gen_srlq(DisasContext
*ctx
)
5240 int l1
= gen_new_label();
5241 int l2
= gen_new_label();
5242 TCGv t0
= tcg_temp_local_new();
5243 TCGv t1
= tcg_temp_local_new();
5244 TCGv t2
= tcg_temp_local_new();
5245 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5246 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5247 tcg_gen_shr_tl(t2
, t1
, t2
);
5248 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5249 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5250 gen_load_spr(t0
, SPR_MQ
);
5251 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5254 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5255 tcg_gen_and_tl(t0
, t0
, t2
);
5256 gen_load_spr(t1
, SPR_MQ
);
5257 tcg_gen_andc_tl(t1
, t1
, t2
);
5258 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5263 if (unlikely(Rc(ctx
->opcode
) != 0))
5264 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5268 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
);
5270 static void gen_srq(DisasContext
*ctx
)
5272 int l1
= gen_new_label();
5273 TCGv t0
= tcg_temp_new();
5274 TCGv t1
= tcg_temp_new();
5275 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5276 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5277 tcg_gen_subfi_tl(t1
, 32, t1
);
5278 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5279 tcg_gen_or_tl(t1
, t0
, t1
);
5280 gen_store_spr(SPR_MQ
, t1
);
5281 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5282 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5283 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5284 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5288 if (unlikely(Rc(ctx
->opcode
) != 0))
5289 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5292 /* PowerPC 602 specific instructions */
5294 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
);
5296 static void gen_dsa(DisasContext
*ctx
)
5299 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5303 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
);
5305 static void gen_esa(DisasContext
*ctx
)
5308 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5312 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
);
5314 static void gen_mfrom(DisasContext
*ctx
)
5316 #if defined(CONFIG_USER_ONLY)
5317 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5319 if (unlikely(!ctx
->mem_idx
)) {
5320 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5323 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5327 /* 602 - 603 - G2 TLB management */
5329 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
)
5331 #if defined(CONFIG_USER_ONLY)
5332 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5334 if (unlikely(!ctx
->mem_idx
)) {
5335 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5338 gen_helper_6xx_tlbd(cpu_gpr
[rB(ctx
->opcode
)]);
5343 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
)
5345 #if defined(CONFIG_USER_ONLY)
5346 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5348 if (unlikely(!ctx
->mem_idx
)) {
5349 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5352 gen_helper_6xx_tlbi(cpu_gpr
[rB(ctx
->opcode
)]);
5356 /* 74xx TLB management */
5358 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
)
5360 #if defined(CONFIG_USER_ONLY)
5361 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5363 if (unlikely(!ctx
->mem_idx
)) {
5364 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5367 gen_helper_74xx_tlbd(cpu_gpr
[rB(ctx
->opcode
)]);
5372 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
)
5374 #if defined(CONFIG_USER_ONLY)
5375 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5377 if (unlikely(!ctx
->mem_idx
)) {
5378 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5381 gen_helper_74xx_tlbi(cpu_gpr
[rB(ctx
->opcode
)]);
5385 /* POWER instructions not in PowerPC 601 */
5387 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
);
5389 static void gen_clf(DisasContext
*ctx
)
5391 /* Cache line flush: implemented as no-op */
5395 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
);
5397 static void gen_cli(DisasContext
*ctx
)
5399 /* Cache line invalidate: privileged and treated as no-op */
5400 #if defined(CONFIG_USER_ONLY)
5401 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5403 if (unlikely(!ctx
->mem_idx
)) {
5404 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5411 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
);
5413 static void gen_dclst(DisasContext
*ctx
)
5415 /* Data cache line store: treated as no-op */
5418 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
);
5420 static void gen_mfsri(DisasContext
*ctx
)
5422 #if defined(CONFIG_USER_ONLY)
5423 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5425 int ra
= rA(ctx
->opcode
);
5426 int rd
= rD(ctx
->opcode
);
5428 if (unlikely(!ctx
->mem_idx
)) {
5429 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5432 t0
= tcg_temp_new();
5433 gen_addr_reg_index(ctx
, t0
);
5434 tcg_gen_shri_tl(t0
, t0
, 28);
5435 tcg_gen_andi_tl(t0
, t0
, 0xF);
5436 gen_helper_load_sr(cpu_gpr
[rd
], t0
);
5438 if (ra
!= 0 && ra
!= rd
)
5439 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5443 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
);
5445 static void gen_rac(DisasContext
*ctx
)
5447 #if defined(CONFIG_USER_ONLY)
5448 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5451 if (unlikely(!ctx
->mem_idx
)) {
5452 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5455 t0
= tcg_temp_new();
5456 gen_addr_reg_index(ctx
, t0
);
5457 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5462 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
);
5464 static void gen_rfsvc(DisasContext
*ctx
)
5466 #if defined(CONFIG_USER_ONLY)
5467 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5469 if (unlikely(!ctx
->mem_idx
)) {
5470 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5474 gen_sync_exception(ctx
);
5478 /* svc is not implemented for now */
5480 /* POWER2 specific instructions */
5481 /* Quad manipulation (load/store two floats at a time) */
5484 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
);
5486 static void gen_lfq(DisasContext
*ctx
)
5488 int rd
= rD(ctx
->opcode
);
5490 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5491 t0
= tcg_temp_new();
5492 gen_addr_imm_index(ctx
, t0
, 0);
5493 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5494 gen_addr_add(ctx
, t0
, t0
, 8);
5495 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5500 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
);
5502 static void gen_lfqu(DisasContext
*ctx
)
5504 int ra
= rA(ctx
->opcode
);
5505 int rd
= rD(ctx
->opcode
);
5507 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5508 t0
= tcg_temp_new();
5509 t1
= tcg_temp_new();
5510 gen_addr_imm_index(ctx
, t0
, 0);
5511 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5512 gen_addr_add(ctx
, t1
, t0
, 8);
5513 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5515 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5521 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
);
5523 static void gen_lfqux(DisasContext
*ctx
)
5525 int ra
= rA(ctx
->opcode
);
5526 int rd
= rD(ctx
->opcode
);
5527 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5529 t0
= tcg_temp_new();
5530 gen_addr_reg_index(ctx
, t0
);
5531 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5532 t1
= tcg_temp_new();
5533 gen_addr_add(ctx
, t1
, t0
, 8);
5534 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5537 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5542 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
);
5544 static void gen_lfqx(DisasContext
*ctx
)
5546 int rd
= rD(ctx
->opcode
);
5548 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5549 t0
= tcg_temp_new();
5550 gen_addr_reg_index(ctx
, t0
);
5551 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5552 gen_addr_add(ctx
, t0
, t0
, 8);
5553 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5558 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
);
5560 static void gen_stfq(DisasContext
*ctx
)
5562 int rd
= rD(ctx
->opcode
);
5564 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5565 t0
= tcg_temp_new();
5566 gen_addr_imm_index(ctx
, t0
, 0);
5567 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5568 gen_addr_add(ctx
, t0
, t0
, 8);
5569 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5574 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
);
5576 static void gen_stfqu(DisasContext
*ctx
)
5578 int ra
= rA(ctx
->opcode
);
5579 int rd
= rD(ctx
->opcode
);
5581 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5582 t0
= tcg_temp_new();
5583 gen_addr_imm_index(ctx
, t0
, 0);
5584 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5585 t1
= tcg_temp_new();
5586 gen_addr_add(ctx
, t1
, t0
, 8);
5587 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5590 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5595 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
);
5597 static void gen_stfqux(DisasContext
*ctx
)
5599 int ra
= rA(ctx
->opcode
);
5600 int rd
= rD(ctx
->opcode
);
5602 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5603 t0
= tcg_temp_new();
5604 gen_addr_reg_index(ctx
, t0
);
5605 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5606 t1
= tcg_temp_new();
5607 gen_addr_add(ctx
, t1
, t0
, 8);
5608 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5611 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5616 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
);
5618 static void gen_stfqx(DisasContext
*ctx
)
5620 int rd
= rD(ctx
->opcode
);
5622 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5623 t0
= tcg_temp_new();
5624 gen_addr_reg_index(ctx
, t0
);
5625 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5626 gen_addr_add(ctx
, t0
, t0
, 8);
5627 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5631 /* BookE specific instructions */
5632 /* XXX: not implemented on 440 ? */
5633 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
);
5635 static void gen_mfapidi(DisasContext
*ctx
)
5638 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5641 /* XXX: not implemented on 440 ? */
5642 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
);
5644 static void gen_tlbiva(DisasContext
*ctx
)
5646 #if defined(CONFIG_USER_ONLY)
5647 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5650 if (unlikely(!ctx
->mem_idx
)) {
5651 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5654 t0
= tcg_temp_new();
5655 gen_addr_reg_index(ctx
, t0
);
5656 gen_helper_tlbie(cpu_gpr
[rB(ctx
->opcode
)]);
5661 /* All 405 MAC instructions are translated here */
5662 static always_inline
void gen_405_mulladd_insn (DisasContext
*ctx
,
5664 int ra
, int rb
, int rt
, int Rc
)
5668 t0
= tcg_temp_local_new();
5669 t1
= tcg_temp_local_new();
5671 switch (opc3
& 0x0D) {
5673 /* macchw - macchw. - macchwo - macchwo. */
5674 /* macchws - macchws. - macchwso - macchwso. */
5675 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5676 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5677 /* mulchw - mulchw. */
5678 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5679 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5680 tcg_gen_ext16s_tl(t1
, t1
);
5683 /* macchwu - macchwu. - macchwuo - macchwuo. */
5684 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5685 /* mulchwu - mulchwu. */
5686 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5687 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5688 tcg_gen_ext16u_tl(t1
, t1
);
5691 /* machhw - machhw. - machhwo - machhwo. */
5692 /* machhws - machhws. - machhwso - machhwso. */
5693 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5694 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5695 /* mulhhw - mulhhw. */
5696 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5697 tcg_gen_ext16s_tl(t0
, t0
);
5698 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5699 tcg_gen_ext16s_tl(t1
, t1
);
5702 /* machhwu - machhwu. - machhwuo - machhwuo. */
5703 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5704 /* mulhhwu - mulhhwu. */
5705 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5706 tcg_gen_ext16u_tl(t0
, t0
);
5707 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5708 tcg_gen_ext16u_tl(t1
, t1
);
5711 /* maclhw - maclhw. - maclhwo - maclhwo. */
5712 /* maclhws - maclhws. - maclhwso - maclhwso. */
5713 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5714 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5715 /* mullhw - mullhw. */
5716 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5717 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5720 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5721 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5722 /* mullhwu - mullhwu. */
5723 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5724 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5728 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5729 tcg_gen_mul_tl(t1
, t0
, t1
);
5731 /* nmultiply-and-accumulate (0x0E) */
5732 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5734 /* multiply-and-accumulate (0x0C) */
5735 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5739 /* Check overflow and/or saturate */
5740 int l1
= gen_new_label();
5743 /* Start with XER OV disabled, the most likely case */
5744 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
5748 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5749 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5750 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5751 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5754 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5755 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5759 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5762 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5766 /* Check overflow */
5767 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
5770 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5773 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5777 if (unlikely(Rc
) != 0) {
5779 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5783 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5784 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC); \
5786 static void glue(gen_, name)(DisasContext *ctx) \
5788 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5789 rD(ctx->opcode), Rc(ctx->opcode)); \
5792 /* macchw - macchw. */
5793 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5794 /* macchwo - macchwo. */
5795 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5796 /* macchws - macchws. */
5797 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5798 /* macchwso - macchwso. */
5799 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5800 /* macchwsu - macchwsu. */
5801 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5802 /* macchwsuo - macchwsuo. */
5803 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5804 /* macchwu - macchwu. */
5805 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5806 /* macchwuo - macchwuo. */
5807 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5808 /* machhw - machhw. */
5809 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5810 /* machhwo - machhwo. */
5811 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5812 /* machhws - machhws. */
5813 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5814 /* machhwso - machhwso. */
5815 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5816 /* machhwsu - machhwsu. */
5817 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5818 /* machhwsuo - machhwsuo. */
5819 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5820 /* machhwu - machhwu. */
5821 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5822 /* machhwuo - machhwuo. */
5823 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5824 /* maclhw - maclhw. */
5825 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5826 /* maclhwo - maclhwo. */
5827 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5828 /* maclhws - maclhws. */
5829 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5830 /* maclhwso - maclhwso. */
5831 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5832 /* maclhwu - maclhwu. */
5833 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5834 /* maclhwuo - maclhwuo. */
5835 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5836 /* maclhwsu - maclhwsu. */
5837 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5838 /* maclhwsuo - maclhwsuo. */
5839 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5840 /* nmacchw - nmacchw. */
5841 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5842 /* nmacchwo - nmacchwo. */
5843 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5844 /* nmacchws - nmacchws. */
5845 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5846 /* nmacchwso - nmacchwso. */
5847 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5848 /* nmachhw - nmachhw. */
5849 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5850 /* nmachhwo - nmachhwo. */
5851 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5852 /* nmachhws - nmachhws. */
5853 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5854 /* nmachhwso - nmachhwso. */
5855 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5856 /* nmaclhw - nmaclhw. */
5857 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5858 /* nmaclhwo - nmaclhwo. */
5859 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5860 /* nmaclhws - nmaclhws. */
5861 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5862 /* nmaclhwso - nmaclhwso. */
5863 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5865 /* mulchw - mulchw. */
5866 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5867 /* mulchwu - mulchwu. */
5868 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5869 /* mulhhw - mulhhw. */
5870 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5871 /* mulhhwu - mulhhwu. */
5872 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5873 /* mullhw - mullhw. */
5874 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5875 /* mullhwu - mullhwu. */
5876 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5879 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
);
5881 static void gen_mfdcr(DisasContext
*ctx
)
5883 #if defined(CONFIG_USER_ONLY)
5884 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5887 if (unlikely(!ctx
->mem_idx
)) {
5888 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5891 /* NIP cannot be restored if the memory exception comes from an helper */
5892 gen_update_nip(ctx
, ctx
->nip
- 4);
5893 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5894 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], dcrn
);
5895 tcg_temp_free(dcrn
);
5900 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
);
5902 static void gen_mtdcr(DisasContext
*ctx
)
5904 #if defined(CONFIG_USER_ONLY)
5905 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5908 if (unlikely(!ctx
->mem_idx
)) {
5909 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5912 /* NIP cannot be restored if the memory exception comes from an helper */
5913 gen_update_nip(ctx
, ctx
->nip
- 4);
5914 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5915 gen_helper_store_dcr(dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
5916 tcg_temp_free(dcrn
);
5921 /* XXX: not implemented on 440 ? */
5922 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
);
5924 static void gen_mfdcrx(DisasContext
*ctx
)
5926 #if defined(CONFIG_USER_ONLY)
5927 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5929 if (unlikely(!ctx
->mem_idx
)) {
5930 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5933 /* NIP cannot be restored if the memory exception comes from an helper */
5934 gen_update_nip(ctx
, ctx
->nip
- 4);
5935 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5936 /* Note: Rc update flag set leads to undefined state of Rc0 */
5941 /* XXX: not implemented on 440 ? */
5942 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
);
5944 static void gen_mtdcrx(DisasContext
*ctx
)
5946 #if defined(CONFIG_USER_ONLY)
5947 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5949 if (unlikely(!ctx
->mem_idx
)) {
5950 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5953 /* NIP cannot be restored if the memory exception comes from an helper */
5954 gen_update_nip(ctx
, ctx
->nip
- 4);
5955 gen_helper_store_dcr(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5956 /* Note: Rc update flag set leads to undefined state of Rc0 */
5960 /* mfdcrux (PPC 460) : user-mode access to DCR */
5961 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
);
5963 static void gen_mfdcrux(DisasContext
*ctx
)
5965 /* NIP cannot be restored if the memory exception comes from an helper */
5966 gen_update_nip(ctx
, ctx
->nip
- 4);
5967 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5968 /* Note: Rc update flag set leads to undefined state of Rc0 */
5971 /* mtdcrux (PPC 460) : user-mode access to DCR */
5972 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
);
5974 static void gen_mtdcrux(DisasContext
*ctx
)
5976 /* NIP cannot be restored if the memory exception comes from an helper */
5977 gen_update_nip(ctx
, ctx
->nip
- 4);
5978 gen_helper_store_dcr(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5979 /* Note: Rc update flag set leads to undefined state of Rc0 */
5983 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
);
5985 static void gen_dccci(DisasContext
*ctx
)
5987 #if defined(CONFIG_USER_ONLY)
5988 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5990 if (unlikely(!ctx
->mem_idx
)) {
5991 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5994 /* interpreted as no-op */
5999 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
);
6001 static void gen_dcread(DisasContext
*ctx
)
6003 #if defined(CONFIG_USER_ONLY)
6004 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6007 if (unlikely(!ctx
->mem_idx
)) {
6008 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6011 gen_set_access_type(ctx
, ACCESS_CACHE
);
6012 EA
= tcg_temp_new();
6013 gen_addr_reg_index(ctx
, EA
);
6014 val
= tcg_temp_new();
6015 gen_qemu_ld32u(ctx
, val
, EA
);
6017 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
6023 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
)
6025 /* interpreted as no-op */
6026 /* XXX: specification say this is treated as a load by the MMU
6027 * but does not generate any exception
6032 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
);
6034 static void gen_iccci(DisasContext
*ctx
)
6036 #if defined(CONFIG_USER_ONLY)
6037 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6039 if (unlikely(!ctx
->mem_idx
)) {
6040 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6043 /* interpreted as no-op */
6048 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
);
6050 static void gen_icread(DisasContext
*ctx
)
6052 #if defined(CONFIG_USER_ONLY)
6053 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6055 if (unlikely(!ctx
->mem_idx
)) {
6056 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6059 /* interpreted as no-op */
6063 /* rfci (mem_idx only) */
6064 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
)
6066 #if defined(CONFIG_USER_ONLY)
6067 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6069 if (unlikely(!ctx
->mem_idx
)) {
6070 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6073 /* Restore CPU state */
6074 gen_helper_40x_rfci();
6075 gen_sync_exception(ctx
);
6079 GEN_HANDLER(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
);
6081 static void gen_rfci(DisasContext
*ctx
)
6083 #if defined(CONFIG_USER_ONLY)
6084 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6086 if (unlikely(!ctx
->mem_idx
)) {
6087 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6090 /* Restore CPU state */
6092 gen_sync_exception(ctx
);
6096 /* BookE specific */
6097 /* XXX: not implemented on 440 ? */
6098 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
);
6100 static void gen_rfdi(DisasContext
*ctx
)
6102 #if defined(CONFIG_USER_ONLY)
6103 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6105 if (unlikely(!ctx
->mem_idx
)) {
6106 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6109 /* Restore CPU state */
6111 gen_sync_exception(ctx
);
6115 /* XXX: not implemented on 440 ? */
6116 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
);
6118 static void gen_rfmci(DisasContext
*ctx
)
6120 #if defined(CONFIG_USER_ONLY)
6121 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6123 if (unlikely(!ctx
->mem_idx
)) {
6124 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6127 /* Restore CPU state */
6129 gen_sync_exception(ctx
);
6133 /* TLB management - PowerPC 405 implementation */
6135 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
)
6137 #if defined(CONFIG_USER_ONLY)
6138 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6140 if (unlikely(!ctx
->mem_idx
)) {
6141 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6144 switch (rB(ctx
->opcode
)) {
6146 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6149 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6152 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6158 /* tlbsx - tlbsx. */
6159 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
)
6161 #if defined(CONFIG_USER_ONLY)
6162 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6165 if (unlikely(!ctx
->mem_idx
)) {
6166 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6169 t0
= tcg_temp_new();
6170 gen_addr_reg_index(ctx
, t0
);
6171 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], t0
);
6173 if (Rc(ctx
->opcode
)) {
6174 int l1
= gen_new_label();
6175 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
6176 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
6177 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
6178 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6179 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6186 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
)
6188 #if defined(CONFIG_USER_ONLY)
6189 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6191 if (unlikely(!ctx
->mem_idx
)) {
6192 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6195 switch (rB(ctx
->opcode
)) {
6197 gen_helper_4xx_tlbwe_hi(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
6200 gen_helper_4xx_tlbwe_lo(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
6203 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6209 /* TLB management - PowerPC 440 implementation */
6211 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
)
6213 #if defined(CONFIG_USER_ONLY)
6214 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6216 if (unlikely(!ctx
->mem_idx
)) {
6217 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6220 switch (rB(ctx
->opcode
)) {
6225 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6226 gen_helper_440_tlbwe(t0
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6227 tcg_temp_free_i32(t0
);
6231 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6237 /* tlbsx - tlbsx. */
6238 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
)
6240 #if defined(CONFIG_USER_ONLY)
6241 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6244 if (unlikely(!ctx
->mem_idx
)) {
6245 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6248 t0
= tcg_temp_new();
6249 gen_addr_reg_index(ctx
, t0
);
6250 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], t0
);
6252 if (Rc(ctx
->opcode
)) {
6253 int l1
= gen_new_label();
6254 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
6255 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
6256 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
6257 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6258 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6265 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
)
6267 #if defined(CONFIG_USER_ONLY)
6268 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6270 if (unlikely(!ctx
->mem_idx
)) {
6271 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6274 switch (rB(ctx
->opcode
)) {
6279 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6280 gen_helper_440_tlbwe(t0
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
6281 tcg_temp_free_i32(t0
);
6285 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6292 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
);
6294 static void gen_wrtee(DisasContext
*ctx
)
6296 #if defined(CONFIG_USER_ONLY)
6297 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6300 if (unlikely(!ctx
->mem_idx
)) {
6301 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6304 t0
= tcg_temp_new();
6305 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6306 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6307 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6309 /* Stop translation to have a chance to raise an exception
6310 * if we just set msr_ee to 1
6312 gen_stop_exception(ctx
);
6317 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE
);
6319 static void gen_wrteei(DisasContext
*ctx
)
6321 #if defined(CONFIG_USER_ONLY)
6322 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6324 if (unlikely(!ctx
->mem_idx
)) {
6325 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6328 if (ctx
->opcode
& 0x00010000) {
6329 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6330 /* Stop translation to have a chance to raise an exception */
6331 gen_stop_exception(ctx
);
6333 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6338 /* PowerPC 440 specific instructions */
6340 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
);
6342 static void gen_dlmzb(DisasContext
*ctx
)
6344 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6345 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
6346 cpu_gpr
[rB(ctx
->opcode
)], t0
);
6347 tcg_temp_free_i32(t0
);
6350 /* mbar replaces eieio on 440 */
6351 GEN_HANDLER(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE
);
6353 static void gen_mbar(DisasContext
*ctx
)
6355 /* interpreted as no-op */
6358 /* msync replaces sync on 440 */
6359 GEN_HANDLER(msync
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
);
6361 static void gen_msync(DisasContext
*ctx
)
6363 /* interpreted as no-op */
6367 GEN_HANDLER2(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE
)
6369 /* interpreted as no-op */
6370 /* XXX: specification say this is treated as a load by the MMU
6371 * but does not generate any exception
6375 /*** Altivec vector extension ***/
6376 /* Altivec registers moves */
6378 static always_inline TCGv_ptr
gen_avr_ptr(int reg
)
6380 TCGv_ptr r
= tcg_temp_new_ptr();
6381 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, avr
[reg
]));
6385 #define GEN_VR_LDX(name, opc2, opc3) \
6386 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC); \
6388 static void glue(gen_, name)(DisasContext *ctx) \
6391 if (unlikely(!ctx->altivec_enabled)) { \
6392 gen_exception(ctx, POWERPC_EXCP_VPU); \
6395 gen_set_access_type(ctx, ACCESS_INT); \
6396 EA = tcg_temp_new(); \
6397 gen_addr_reg_index(ctx, EA); \
6398 tcg_gen_andi_tl(EA, EA, ~0xf); \
6399 if (ctx->le_mode) { \
6400 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6401 tcg_gen_addi_tl(EA, EA, 8); \
6402 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6404 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6405 tcg_gen_addi_tl(EA, EA, 8); \
6406 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6408 tcg_temp_free(EA); \
6411 #define GEN_VR_STX(name, opc2, opc3) \
6412 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC); \
6414 static void gen_st##name(DisasContext *ctx) \
6417 if (unlikely(!ctx->altivec_enabled)) { \
6418 gen_exception(ctx, POWERPC_EXCP_VPU); \
6421 gen_set_access_type(ctx, ACCESS_INT); \
6422 EA = tcg_temp_new(); \
6423 gen_addr_reg_index(ctx, EA); \
6424 tcg_gen_andi_tl(EA, EA, ~0xf); \
6425 if (ctx->le_mode) { \
6426 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6427 tcg_gen_addi_tl(EA, EA, 8); \
6428 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6430 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6431 tcg_gen_addi_tl(EA, EA, 8); \
6432 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6434 tcg_temp_free(EA); \
6437 #define GEN_VR_LVE(name, opc2, opc3) \
6438 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC); \
6440 static void gen_lve##name(DisasContext *ctx) \
6444 if (unlikely(!ctx->altivec_enabled)) { \
6445 gen_exception(ctx, POWERPC_EXCP_VPU); \
6448 gen_set_access_type(ctx, ACCESS_INT); \
6449 EA = tcg_temp_new(); \
6450 gen_addr_reg_index(ctx, EA); \
6451 rs = gen_avr_ptr(rS(ctx->opcode)); \
6452 gen_helper_lve##name (rs, EA); \
6453 tcg_temp_free(EA); \
6454 tcg_temp_free_ptr(rs); \
6457 #define GEN_VR_STVE(name, opc2, opc3) \
6458 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC); \
6460 static void gen_stve##name(DisasContext *ctx) \
6464 if (unlikely(!ctx->altivec_enabled)) { \
6465 gen_exception(ctx, POWERPC_EXCP_VPU); \
6468 gen_set_access_type(ctx, ACCESS_INT); \
6469 EA = tcg_temp_new(); \
6470 gen_addr_reg_index(ctx, EA); \
6471 rs = gen_avr_ptr(rS(ctx->opcode)); \
6472 gen_helper_stve##name (rs, EA); \
6473 tcg_temp_free(EA); \
6474 tcg_temp_free_ptr(rs); \
6477 GEN_VR_LDX(lvx
, 0x07, 0x03);
6478 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6479 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
6481 GEN_VR_LVE(bx
, 0x07, 0x00);
6482 GEN_VR_LVE(hx
, 0x07, 0x01);
6483 GEN_VR_LVE(wx
, 0x07, 0x02);
6485 GEN_VR_STX(svx
, 0x07, 0x07);
6486 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6487 GEN_VR_STX(svxl
, 0x07, 0x0F);
6489 GEN_VR_STVE(bx
, 0x07, 0x04);
6490 GEN_VR_STVE(hx
, 0x07, 0x05);
6491 GEN_VR_STVE(wx
, 0x07, 0x06);
6493 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
);
6495 static void gen_lvsl(DisasContext
*ctx
)
6499 if (unlikely(!ctx
->altivec_enabled
)) {
6500 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6503 EA
= tcg_temp_new();
6504 gen_addr_reg_index(ctx
, EA
);
6505 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6506 gen_helper_lvsl(rd
, EA
);
6508 tcg_temp_free_ptr(rd
);
6511 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
);
6513 static void gen_lvsr(DisasContext
*ctx
)
6517 if (unlikely(!ctx
->altivec_enabled
)) {
6518 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6521 EA
= tcg_temp_new();
6522 gen_addr_reg_index(ctx
, EA
);
6523 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6524 gen_helper_lvsr(rd
, EA
);
6526 tcg_temp_free_ptr(rd
);
6529 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
);
6531 static void gen_mfvscr(DisasContext
*ctx
)
6534 if (unlikely(!ctx
->altivec_enabled
)) {
6535 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6538 tcg_gen_movi_i64(cpu_avrh
[rD(ctx
->opcode
)], 0);
6539 t
= tcg_temp_new_i32();
6540 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, vscr
));
6541 tcg_gen_extu_i32_i64(cpu_avrl
[rD(ctx
->opcode
)], t
);
6542 tcg_temp_free_i32(t
);
6545 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
);
6547 static void gen_mtvscr(DisasContext
*ctx
)
6550 if (unlikely(!ctx
->altivec_enabled
)) {
6551 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6554 p
= gen_avr_ptr(rD(ctx
->opcode
));
6555 gen_helper_mtvscr(p
);
6556 tcg_temp_free_ptr(p
);
6559 /* Logical operations */
6560 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6561 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC); \
6563 static void glue(gen_, name)(DisasContext *ctx) \
6565 if (unlikely(!ctx->altivec_enabled)) { \
6566 gen_exception(ctx, POWERPC_EXCP_VPU); \
6569 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6570 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6573 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16);
6574 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17);
6575 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18);
6576 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19);
6577 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20);
6579 #define GEN_VXFORM(name, opc2, opc3) \
6580 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC); \
6582 static void glue(gen_, name)(DisasContext *ctx) \
6584 TCGv_ptr ra, rb, rd; \
6585 if (unlikely(!ctx->altivec_enabled)) { \
6586 gen_exception(ctx, POWERPC_EXCP_VPU); \
6589 ra = gen_avr_ptr(rA(ctx->opcode)); \
6590 rb = gen_avr_ptr(rB(ctx->opcode)); \
6591 rd = gen_avr_ptr(rD(ctx->opcode)); \
6592 gen_helper_##name (rd, ra, rb); \
6593 tcg_temp_free_ptr(ra); \
6594 tcg_temp_free_ptr(rb); \
6595 tcg_temp_free_ptr(rd); \
6598 GEN_VXFORM(vaddubm
, 0, 0);
6599 GEN_VXFORM(vadduhm
, 0, 1);
6600 GEN_VXFORM(vadduwm
, 0, 2);
6601 GEN_VXFORM(vsububm
, 0, 16);
6602 GEN_VXFORM(vsubuhm
, 0, 17);
6603 GEN_VXFORM(vsubuwm
, 0, 18);
6604 GEN_VXFORM(vmaxub
, 1, 0);
6605 GEN_VXFORM(vmaxuh
, 1, 1);
6606 GEN_VXFORM(vmaxuw
, 1, 2);
6607 GEN_VXFORM(vmaxsb
, 1, 4);
6608 GEN_VXFORM(vmaxsh
, 1, 5);
6609 GEN_VXFORM(vmaxsw
, 1, 6);
6610 GEN_VXFORM(vminub
, 1, 8);
6611 GEN_VXFORM(vminuh
, 1, 9);
6612 GEN_VXFORM(vminuw
, 1, 10);
6613 GEN_VXFORM(vminsb
, 1, 12);
6614 GEN_VXFORM(vminsh
, 1, 13);
6615 GEN_VXFORM(vminsw
, 1, 14);
6616 GEN_VXFORM(vavgub
, 1, 16);
6617 GEN_VXFORM(vavguh
, 1, 17);
6618 GEN_VXFORM(vavguw
, 1, 18);
6619 GEN_VXFORM(vavgsb
, 1, 20);
6620 GEN_VXFORM(vavgsh
, 1, 21);
6621 GEN_VXFORM(vavgsw
, 1, 22);
6622 GEN_VXFORM(vmrghb
, 6, 0);
6623 GEN_VXFORM(vmrghh
, 6, 1);
6624 GEN_VXFORM(vmrghw
, 6, 2);
6625 GEN_VXFORM(vmrglb
, 6, 4);
6626 GEN_VXFORM(vmrglh
, 6, 5);
6627 GEN_VXFORM(vmrglw
, 6, 6);
6628 GEN_VXFORM(vmuloub
, 4, 0);
6629 GEN_VXFORM(vmulouh
, 4, 1);
6630 GEN_VXFORM(vmulosb
, 4, 4);
6631 GEN_VXFORM(vmulosh
, 4, 5);
6632 GEN_VXFORM(vmuleub
, 4, 8);
6633 GEN_VXFORM(vmuleuh
, 4, 9);
6634 GEN_VXFORM(vmulesb
, 4, 12);
6635 GEN_VXFORM(vmulesh
, 4, 13);
6636 GEN_VXFORM(vslb
, 2, 4);
6637 GEN_VXFORM(vslh
, 2, 5);
6638 GEN_VXFORM(vslw
, 2, 6);
6639 GEN_VXFORM(vsrb
, 2, 8);
6640 GEN_VXFORM(vsrh
, 2, 9);
6641 GEN_VXFORM(vsrw
, 2, 10);
6642 GEN_VXFORM(vsrab
, 2, 12);
6643 GEN_VXFORM(vsrah
, 2, 13);
6644 GEN_VXFORM(vsraw
, 2, 14);
6645 GEN_VXFORM(vslo
, 6, 16);
6646 GEN_VXFORM(vsro
, 6, 17);
6647 GEN_VXFORM(vaddcuw
, 0, 6);
6648 GEN_VXFORM(vsubcuw
, 0, 22);
6649 GEN_VXFORM(vaddubs
, 0, 8);
6650 GEN_VXFORM(vadduhs
, 0, 9);
6651 GEN_VXFORM(vadduws
, 0, 10);
6652 GEN_VXFORM(vaddsbs
, 0, 12);
6653 GEN_VXFORM(vaddshs
, 0, 13);
6654 GEN_VXFORM(vaddsws
, 0, 14);
6655 GEN_VXFORM(vsububs
, 0, 24);
6656 GEN_VXFORM(vsubuhs
, 0, 25);
6657 GEN_VXFORM(vsubuws
, 0, 26);
6658 GEN_VXFORM(vsubsbs
, 0, 28);
6659 GEN_VXFORM(vsubshs
, 0, 29);
6660 GEN_VXFORM(vsubsws
, 0, 30);
6661 GEN_VXFORM(vrlb
, 2, 0);
6662 GEN_VXFORM(vrlh
, 2, 1);
6663 GEN_VXFORM(vrlw
, 2, 2);
6664 GEN_VXFORM(vsl
, 2, 7);
6665 GEN_VXFORM(vsr
, 2, 11);
6666 GEN_VXFORM(vpkuhum
, 7, 0);
6667 GEN_VXFORM(vpkuwum
, 7, 1);
6668 GEN_VXFORM(vpkuhus
, 7, 2);
6669 GEN_VXFORM(vpkuwus
, 7, 3);
6670 GEN_VXFORM(vpkshus
, 7, 4);
6671 GEN_VXFORM(vpkswus
, 7, 5);
6672 GEN_VXFORM(vpkshss
, 7, 6);
6673 GEN_VXFORM(vpkswss
, 7, 7);
6674 GEN_VXFORM(vpkpx
, 7, 12);
6675 GEN_VXFORM(vsum4ubs
, 4, 24);
6676 GEN_VXFORM(vsum4sbs
, 4, 28);
6677 GEN_VXFORM(vsum4shs
, 4, 25);
6678 GEN_VXFORM(vsum2sws
, 4, 26);
6679 GEN_VXFORM(vsumsws
, 4, 30);
6680 GEN_VXFORM(vaddfp
, 5, 0);
6681 GEN_VXFORM(vsubfp
, 5, 1);
6682 GEN_VXFORM(vmaxfp
, 5, 16);
6683 GEN_VXFORM(vminfp
, 5, 17);
6685 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6686 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6688 TCGv_ptr ra, rb, rd; \
6689 if (unlikely(!ctx->altivec_enabled)) { \
6690 gen_exception(ctx, POWERPC_EXCP_VPU); \
6693 ra = gen_avr_ptr(rA(ctx->opcode)); \
6694 rb = gen_avr_ptr(rB(ctx->opcode)); \
6695 rd = gen_avr_ptr(rD(ctx->opcode)); \
6696 gen_helper_##opname (rd, ra, rb); \
6697 tcg_temp_free_ptr(ra); \
6698 tcg_temp_free_ptr(rb); \
6699 tcg_temp_free_ptr(rd); \
6702 #define GEN_VXRFORM(name, opc2, opc3) \
6703 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6704 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6706 GEN_VXRFORM(vcmpequb
, 3, 0)
6707 GEN_VXRFORM(vcmpequh
, 3, 1)
6708 GEN_VXRFORM(vcmpequw
, 3, 2)
6709 GEN_VXRFORM(vcmpgtsb
, 3, 12)
6710 GEN_VXRFORM(vcmpgtsh
, 3, 13)
6711 GEN_VXRFORM(vcmpgtsw
, 3, 14)
6712 GEN_VXRFORM(vcmpgtub
, 3, 8)
6713 GEN_VXRFORM(vcmpgtuh
, 3, 9)
6714 GEN_VXRFORM(vcmpgtuw
, 3, 10)
6715 GEN_VXRFORM(vcmpeqfp
, 3, 3)
6716 GEN_VXRFORM(vcmpgefp
, 3, 7)
6717 GEN_VXRFORM(vcmpgtfp
, 3, 11)
6718 GEN_VXRFORM(vcmpbfp
, 3, 15)
6720 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6721 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC); \
6723 static void glue(gen_, name)(DisasContext *ctx) \
6727 if (unlikely(!ctx->altivec_enabled)) { \
6728 gen_exception(ctx, POWERPC_EXCP_VPU); \
6731 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6732 rd = gen_avr_ptr(rD(ctx->opcode)); \
6733 gen_helper_##name (rd, simm); \
6734 tcg_temp_free_i32(simm); \
6735 tcg_temp_free_ptr(rd); \
6738 GEN_VXFORM_SIMM(vspltisb
, 6, 12);
6739 GEN_VXFORM_SIMM(vspltish
, 6, 13);
6740 GEN_VXFORM_SIMM(vspltisw
, 6, 14);
6742 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6743 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC); \
6745 static void glue(gen_, name)(DisasContext *ctx) \
6748 if (unlikely(!ctx->altivec_enabled)) { \
6749 gen_exception(ctx, POWERPC_EXCP_VPU); \
6752 rb = gen_avr_ptr(rB(ctx->opcode)); \
6753 rd = gen_avr_ptr(rD(ctx->opcode)); \
6754 gen_helper_##name (rd, rb); \
6755 tcg_temp_free_ptr(rb); \
6756 tcg_temp_free_ptr(rd); \
6759 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
6760 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
6761 GEN_VXFORM_NOA(vupklsb
, 7, 10);
6762 GEN_VXFORM_NOA(vupklsh
, 7, 11);
6763 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
6764 GEN_VXFORM_NOA(vupklpx
, 7, 15);
6765 GEN_VXFORM_NOA(vrefp
, 5, 4);
6766 GEN_VXFORM_NOA(vrsqrtefp
, 5, 5);
6767 GEN_VXFORM_NOA(vlogefp
, 5, 7);
6768 GEN_VXFORM_NOA(vrfim
, 5, 8);
6769 GEN_VXFORM_NOA(vrfin
, 5, 9);
6770 GEN_VXFORM_NOA(vrfip
, 5, 10);
6771 GEN_VXFORM_NOA(vrfiz
, 5, 11);
6773 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6774 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC); \
6776 static void glue(gen_, name)(DisasContext *ctx) \
6780 if (unlikely(!ctx->altivec_enabled)) { \
6781 gen_exception(ctx, POWERPC_EXCP_VPU); \
6784 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6785 rd = gen_avr_ptr(rD(ctx->opcode)); \
6786 gen_helper_##name (rd, simm); \
6787 tcg_temp_free_i32(simm); \
6788 tcg_temp_free_ptr(rd); \
6791 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6792 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC); \
6794 static void glue(gen_, name)(DisasContext *ctx) \
6798 if (unlikely(!ctx->altivec_enabled)) { \
6799 gen_exception(ctx, POWERPC_EXCP_VPU); \
6802 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6803 rb = gen_avr_ptr(rB(ctx->opcode)); \
6804 rd = gen_avr_ptr(rD(ctx->opcode)); \
6805 gen_helper_##name (rd, rb, uimm); \
6806 tcg_temp_free_i32(uimm); \
6807 tcg_temp_free_ptr(rb); \
6808 tcg_temp_free_ptr(rd); \
6811 GEN_VXFORM_UIMM(vspltb
, 6, 8);
6812 GEN_VXFORM_UIMM(vsplth
, 6, 9);
6813 GEN_VXFORM_UIMM(vspltw
, 6, 10);
6814 GEN_VXFORM_UIMM(vcfux
, 5, 12);
6815 GEN_VXFORM_UIMM(vcfsx
, 5, 13);
6816 GEN_VXFORM_UIMM(vctuxs
, 5, 14);
6817 GEN_VXFORM_UIMM(vctsxs
, 5, 15);
6819 GEN_HANDLER(vsldoi
, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC
);
6821 static void gen_vsldoi(DisasContext
*ctx
)
6823 TCGv_ptr ra
, rb
, rd
;
6825 if (unlikely(!ctx
->altivec_enabled
)) {
6826 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6829 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6830 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6831 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6832 sh
= tcg_const_i32(VSH(ctx
->opcode
));
6833 gen_helper_vsldoi (rd
, ra
, rb
, sh
);
6834 tcg_temp_free_ptr(ra
);
6835 tcg_temp_free_ptr(rb
);
6836 tcg_temp_free_ptr(rd
);
6837 tcg_temp_free_i32(sh
);
6840 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6841 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC);\
6843 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6845 TCGv_ptr ra, rb, rc, rd; \
6846 if (unlikely(!ctx->altivec_enabled)) { \
6847 gen_exception(ctx, POWERPC_EXCP_VPU); \
6850 ra = gen_avr_ptr(rA(ctx->opcode)); \
6851 rb = gen_avr_ptr(rB(ctx->opcode)); \
6852 rc = gen_avr_ptr(rC(ctx->opcode)); \
6853 rd = gen_avr_ptr(rD(ctx->opcode)); \
6854 if (Rc(ctx->opcode)) { \
6855 gen_helper_##name1 (rd, ra, rb, rc); \
6857 gen_helper_##name0 (rd, ra, rb, rc); \
6859 tcg_temp_free_ptr(ra); \
6860 tcg_temp_free_ptr(rb); \
6861 tcg_temp_free_ptr(rc); \
6862 tcg_temp_free_ptr(rd); \
6865 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
6867 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
);
6869 static void gen_vmladduhm(DisasContext
*ctx
)
6871 TCGv_ptr ra
, rb
, rc
, rd
;
6872 if (unlikely(!ctx
->altivec_enabled
)) {
6873 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6876 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6877 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6878 rc
= gen_avr_ptr(rC(ctx
->opcode
));
6879 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6880 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
6881 tcg_temp_free_ptr(ra
);
6882 tcg_temp_free_ptr(rb
);
6883 tcg_temp_free_ptr(rc
);
6884 tcg_temp_free_ptr(rd
);
6887 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
6888 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
6889 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
6890 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
6891 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
6893 /*** SPE extension ***/
6894 /* Register moves */
6896 static always_inline
void gen_load_gpr64(TCGv_i64 t
, int reg
) {
6897 #if defined(TARGET_PPC64)
6898 tcg_gen_mov_i64(t
, cpu_gpr
[reg
]);
6900 tcg_gen_concat_i32_i64(t
, cpu_gpr
[reg
], cpu_gprh
[reg
]);
6904 static always_inline
void gen_store_gpr64(int reg
, TCGv_i64 t
) {
6905 #if defined(TARGET_PPC64)
6906 tcg_gen_mov_i64(cpu_gpr
[reg
], t
);
6908 TCGv_i64 tmp
= tcg_temp_new_i64();
6909 tcg_gen_trunc_i64_i32(cpu_gpr
[reg
], t
);
6910 tcg_gen_shri_i64(tmp
, t
, 32);
6911 tcg_gen_trunc_i64_i32(cpu_gprh
[reg
], tmp
);
6912 tcg_temp_free_i64(tmp
);
6916 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6917 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type); \
6919 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6921 if (Rc(ctx->opcode)) \
6927 /* Handler for undefined SPE opcodes */
6928 static always_inline
void gen_speundef (DisasContext
*ctx
)
6930 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6934 #if defined(TARGET_PPC64)
6935 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6936 static always_inline void gen_##name (DisasContext *ctx) \
6938 if (unlikely(!ctx->spe_enabled)) { \
6939 gen_exception(ctx, POWERPC_EXCP_APU); \
6942 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6943 cpu_gpr[rB(ctx->opcode)]); \
6946 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6947 static always_inline void gen_##name (DisasContext *ctx) \
6949 if (unlikely(!ctx->spe_enabled)) { \
6950 gen_exception(ctx, POWERPC_EXCP_APU); \
6953 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6954 cpu_gpr[rB(ctx->opcode)]); \
6955 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6956 cpu_gprh[rB(ctx->opcode)]); \
6960 GEN_SPEOP_LOGIC2(evand
, tcg_gen_and_tl
);
6961 GEN_SPEOP_LOGIC2(evandc
, tcg_gen_andc_tl
);
6962 GEN_SPEOP_LOGIC2(evxor
, tcg_gen_xor_tl
);
6963 GEN_SPEOP_LOGIC2(evor
, tcg_gen_or_tl
);
6964 GEN_SPEOP_LOGIC2(evnor
, tcg_gen_nor_tl
);
6965 GEN_SPEOP_LOGIC2(eveqv
, tcg_gen_eqv_tl
);
6966 GEN_SPEOP_LOGIC2(evorc
, tcg_gen_orc_tl
);
6967 GEN_SPEOP_LOGIC2(evnand
, tcg_gen_nand_tl
);
6969 /* SPE logic immediate */
6970 #if defined(TARGET_PPC64)
6971 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6972 static always_inline void gen_##name (DisasContext *ctx) \
6974 if (unlikely(!ctx->spe_enabled)) { \
6975 gen_exception(ctx, POWERPC_EXCP_APU); \
6978 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6979 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6980 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6981 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6982 tcg_opi(t0, t0, rB(ctx->opcode)); \
6983 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6984 tcg_gen_trunc_i64_i32(t1, t2); \
6985 tcg_temp_free_i64(t2); \
6986 tcg_opi(t1, t1, rB(ctx->opcode)); \
6987 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6988 tcg_temp_free_i32(t0); \
6989 tcg_temp_free_i32(t1); \
6992 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6993 static always_inline void gen_##name (DisasContext *ctx) \
6995 if (unlikely(!ctx->spe_enabled)) { \
6996 gen_exception(ctx, POWERPC_EXCP_APU); \
6999 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7001 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7005 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi
, tcg_gen_shli_i32
);
7006 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu
, tcg_gen_shri_i32
);
7007 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis
, tcg_gen_sari_i32
);
7008 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi
, tcg_gen_rotli_i32
);
7010 /* SPE arithmetic */
7011 #if defined(TARGET_PPC64)
7012 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7013 static always_inline void gen_##name (DisasContext *ctx) \
7015 if (unlikely(!ctx->spe_enabled)) { \
7016 gen_exception(ctx, POWERPC_EXCP_APU); \
7019 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7020 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7021 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7022 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7024 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7025 tcg_gen_trunc_i64_i32(t1, t2); \
7026 tcg_temp_free_i64(t2); \
7028 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7029 tcg_temp_free_i32(t0); \
7030 tcg_temp_free_i32(t1); \
7033 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7034 static always_inline void gen_##name (DisasContext *ctx) \
7036 if (unlikely(!ctx->spe_enabled)) { \
7037 gen_exception(ctx, POWERPC_EXCP_APU); \
7040 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7041 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7045 static always_inline
void gen_op_evabs (TCGv_i32 ret
, TCGv_i32 arg1
)
7047 int l1
= gen_new_label();
7048 int l2
= gen_new_label();
7050 tcg_gen_brcondi_i32(TCG_COND_GE
, arg1
, 0, l1
);
7051 tcg_gen_neg_i32(ret
, arg1
);
7054 tcg_gen_mov_i32(ret
, arg1
);
7057 GEN_SPEOP_ARITH1(evabs
, gen_op_evabs
);
7058 GEN_SPEOP_ARITH1(evneg
, tcg_gen_neg_i32
);
7059 GEN_SPEOP_ARITH1(evextsb
, tcg_gen_ext8s_i32
);
7060 GEN_SPEOP_ARITH1(evextsh
, tcg_gen_ext16s_i32
);
7061 static always_inline
void gen_op_evrndw (TCGv_i32 ret
, TCGv_i32 arg1
)
7063 tcg_gen_addi_i32(ret
, arg1
, 0x8000);
7064 tcg_gen_ext16u_i32(ret
, ret
);
7066 GEN_SPEOP_ARITH1(evrndw
, gen_op_evrndw
);
7067 GEN_SPEOP_ARITH1(evcntlsw
, gen_helper_cntlsw32
);
7068 GEN_SPEOP_ARITH1(evcntlzw
, gen_helper_cntlzw32
);
7070 #if defined(TARGET_PPC64)
7071 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7072 static always_inline void gen_##name (DisasContext *ctx) \
7074 if (unlikely(!ctx->spe_enabled)) { \
7075 gen_exception(ctx, POWERPC_EXCP_APU); \
7078 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7079 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7080 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7081 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7082 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7083 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7084 tcg_op(t0, t0, t2); \
7085 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7086 tcg_gen_trunc_i64_i32(t1, t3); \
7087 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7088 tcg_gen_trunc_i64_i32(t2, t3); \
7089 tcg_temp_free_i64(t3); \
7090 tcg_op(t1, t1, t2); \
7091 tcg_temp_free_i32(t2); \
7092 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7093 tcg_temp_free_i32(t0); \
7094 tcg_temp_free_i32(t1); \
7097 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7098 static always_inline void gen_##name (DisasContext *ctx) \
7100 if (unlikely(!ctx->spe_enabled)) { \
7101 gen_exception(ctx, POWERPC_EXCP_APU); \
7104 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7105 cpu_gpr[rB(ctx->opcode)]); \
7106 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7107 cpu_gprh[rB(ctx->opcode)]); \
7111 static always_inline
void gen_op_evsrwu (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7116 l1
= gen_new_label();
7117 l2
= gen_new_label();
7118 t0
= tcg_temp_local_new_i32();
7119 /* No error here: 6 bits are used */
7120 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7121 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7122 tcg_gen_shr_i32(ret
, arg1
, t0
);
7125 tcg_gen_movi_i32(ret
, 0);
7127 tcg_temp_free_i32(t0
);
7129 GEN_SPEOP_ARITH2(evsrwu
, gen_op_evsrwu
);
7130 static always_inline
void gen_op_evsrws (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7135 l1
= gen_new_label();
7136 l2
= gen_new_label();
7137 t0
= tcg_temp_local_new_i32();
7138 /* No error here: 6 bits are used */
7139 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7140 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7141 tcg_gen_sar_i32(ret
, arg1
, t0
);
7144 tcg_gen_movi_i32(ret
, 0);
7146 tcg_temp_free_i32(t0
);
7148 GEN_SPEOP_ARITH2(evsrws
, gen_op_evsrws
);
7149 static always_inline
void gen_op_evslw (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7154 l1
= gen_new_label();
7155 l2
= gen_new_label();
7156 t0
= tcg_temp_local_new_i32();
7157 /* No error here: 6 bits are used */
7158 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7159 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7160 tcg_gen_shl_i32(ret
, arg1
, t0
);
7163 tcg_gen_movi_i32(ret
, 0);
7165 tcg_temp_free_i32(t0
);
7167 GEN_SPEOP_ARITH2(evslw
, gen_op_evslw
);
7168 static always_inline
void gen_op_evrlw (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7170 TCGv_i32 t0
= tcg_temp_new_i32();
7171 tcg_gen_andi_i32(t0
, arg2
, 0x1F);
7172 tcg_gen_rotl_i32(ret
, arg1
, t0
);
7173 tcg_temp_free_i32(t0
);
7175 GEN_SPEOP_ARITH2(evrlw
, gen_op_evrlw
);
7176 static always_inline
void gen_evmergehi (DisasContext
*ctx
)
7178 if (unlikely(!ctx
->spe_enabled
)) {
7179 gen_exception(ctx
, POWERPC_EXCP_APU
);
7182 #if defined(TARGET_PPC64)
7183 TCGv t0
= tcg_temp_new();
7184 TCGv t1
= tcg_temp_new();
7185 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
7186 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
7187 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7191 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7192 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7195 GEN_SPEOP_ARITH2(evaddw
, tcg_gen_add_i32
);
7196 static always_inline
void gen_op_evsubf (TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7198 tcg_gen_sub_i32(ret
, arg2
, arg1
);
7200 GEN_SPEOP_ARITH2(evsubfw
, gen_op_evsubf
);
7202 /* SPE arithmetic immediate */
7203 #if defined(TARGET_PPC64)
7204 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7205 static always_inline void gen_##name (DisasContext *ctx) \
7207 if (unlikely(!ctx->spe_enabled)) { \
7208 gen_exception(ctx, POWERPC_EXCP_APU); \
7211 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7212 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7213 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7214 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7215 tcg_op(t0, t0, rA(ctx->opcode)); \
7216 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7217 tcg_gen_trunc_i64_i32(t1, t2); \
7218 tcg_temp_free_i64(t2); \
7219 tcg_op(t1, t1, rA(ctx->opcode)); \
7220 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7221 tcg_temp_free_i32(t0); \
7222 tcg_temp_free_i32(t1); \
7225 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7226 static always_inline void gen_##name (DisasContext *ctx) \
7228 if (unlikely(!ctx->spe_enabled)) { \
7229 gen_exception(ctx, POWERPC_EXCP_APU); \
7232 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7234 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7238 GEN_SPEOP_ARITH_IMM2(evaddiw
, tcg_gen_addi_i32
);
7239 GEN_SPEOP_ARITH_IMM2(evsubifw
, tcg_gen_subi_i32
);
7241 /* SPE comparison */
7242 #if defined(TARGET_PPC64)
7243 #define GEN_SPEOP_COMP(name, tcg_cond) \
7244 static always_inline void gen_##name (DisasContext *ctx) \
7246 if (unlikely(!ctx->spe_enabled)) { \
7247 gen_exception(ctx, POWERPC_EXCP_APU); \
7250 int l1 = gen_new_label(); \
7251 int l2 = gen_new_label(); \
7252 int l3 = gen_new_label(); \
7253 int l4 = gen_new_label(); \
7254 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7255 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7256 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7257 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7258 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7259 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7260 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7262 gen_set_label(l1); \
7263 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7264 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7265 gen_set_label(l2); \
7266 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7267 tcg_gen_trunc_i64_i32(t0, t2); \
7268 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7269 tcg_gen_trunc_i64_i32(t1, t2); \
7270 tcg_temp_free_i64(t2); \
7271 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7272 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7273 ~(CRF_CH | CRF_CH_AND_CL)); \
7275 gen_set_label(l3); \
7276 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7277 CRF_CH | CRF_CH_OR_CL); \
7278 gen_set_label(l4); \
7279 tcg_temp_free_i32(t0); \
7280 tcg_temp_free_i32(t1); \
7283 #define GEN_SPEOP_COMP(name, tcg_cond) \
7284 static always_inline void gen_##name (DisasContext *ctx) \
7286 if (unlikely(!ctx->spe_enabled)) { \
7287 gen_exception(ctx, POWERPC_EXCP_APU); \
7290 int l1 = gen_new_label(); \
7291 int l2 = gen_new_label(); \
7292 int l3 = gen_new_label(); \
7293 int l4 = gen_new_label(); \
7295 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7296 cpu_gpr[rB(ctx->opcode)], l1); \
7297 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7299 gen_set_label(l1); \
7300 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7301 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7302 gen_set_label(l2); \
7303 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7304 cpu_gprh[rB(ctx->opcode)], l3); \
7305 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7306 ~(CRF_CH | CRF_CH_AND_CL)); \
7308 gen_set_label(l3); \
7309 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7310 CRF_CH | CRF_CH_OR_CL); \
7311 gen_set_label(l4); \
7314 GEN_SPEOP_COMP(evcmpgtu
, TCG_COND_GTU
);
7315 GEN_SPEOP_COMP(evcmpgts
, TCG_COND_GT
);
7316 GEN_SPEOP_COMP(evcmpltu
, TCG_COND_LTU
);
7317 GEN_SPEOP_COMP(evcmplts
, TCG_COND_LT
);
7318 GEN_SPEOP_COMP(evcmpeq
, TCG_COND_EQ
);
7321 static always_inline
void gen_brinc (DisasContext
*ctx
)
7323 /* Note: brinc is usable even if SPE is disabled */
7324 gen_helper_brinc(cpu_gpr
[rD(ctx
->opcode
)],
7325 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7327 static always_inline
void gen_evmergelo (DisasContext
*ctx
)
7329 if (unlikely(!ctx
->spe_enabled
)) {
7330 gen_exception(ctx
, POWERPC_EXCP_APU
);
7333 #if defined(TARGET_PPC64)
7334 TCGv t0
= tcg_temp_new();
7335 TCGv t1
= tcg_temp_new();
7336 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x00000000FFFFFFFFLL
);
7337 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
7338 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7342 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7343 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7346 static always_inline
void gen_evmergehilo (DisasContext
*ctx
)
7348 if (unlikely(!ctx
->spe_enabled
)) {
7349 gen_exception(ctx
, POWERPC_EXCP_APU
);
7352 #if defined(TARGET_PPC64)
7353 TCGv t0
= tcg_temp_new();
7354 TCGv t1
= tcg_temp_new();
7355 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x00000000FFFFFFFFLL
);
7356 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
7357 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7361 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7362 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7365 static always_inline
void gen_evmergelohi (DisasContext
*ctx
)
7367 if (unlikely(!ctx
->spe_enabled
)) {
7368 gen_exception(ctx
, POWERPC_EXCP_APU
);
7371 #if defined(TARGET_PPC64)
7372 TCGv t0
= tcg_temp_new();
7373 TCGv t1
= tcg_temp_new();
7374 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
7375 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
7376 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7380 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7381 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7384 static always_inline
void gen_evsplati (DisasContext
*ctx
)
7386 uint64_t imm
= ((int32_t)(rA(ctx
->opcode
) << 11)) >> 27;
7388 #if defined(TARGET_PPC64)
7389 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
7391 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
7392 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
7395 static always_inline
void gen_evsplatfi (DisasContext
*ctx
)
7397 uint64_t imm
= rA(ctx
->opcode
) << 11;
7399 #if defined(TARGET_PPC64)
7400 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
7402 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
7403 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
7407 static always_inline
void gen_evsel (DisasContext
*ctx
)
7409 int l1
= gen_new_label();
7410 int l2
= gen_new_label();
7411 int l3
= gen_new_label();
7412 int l4
= gen_new_label();
7413 TCGv_i32 t0
= tcg_temp_local_new_i32();
7414 #if defined(TARGET_PPC64)
7415 TCGv t1
= tcg_temp_local_new();
7416 TCGv t2
= tcg_temp_local_new();
7418 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 3);
7419 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
7420 #if defined(TARGET_PPC64)
7421 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
7423 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7427 #if defined(TARGET_PPC64)
7428 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
7430 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7433 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 2);
7434 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l3
);
7435 #if defined(TARGET_PPC64)
7436 tcg_gen_andi_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], 0x00000000FFFFFFFFULL
);
7438 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7442 #if defined(TARGET_PPC64)
7443 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x00000000FFFFFFFFULL
);
7445 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7448 tcg_temp_free_i32(t0
);
7449 #if defined(TARGET_PPC64)
7450 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
, t2
);
7455 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
)
7459 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
)
7463 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
)
7467 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
)
7472 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, PPC_SPE
); ////
7473 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, PPC_SPE
);
7474 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, PPC_SPE
); ////
7475 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, PPC_SPE
);
7476 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, PPC_SPE
); ////
7477 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, PPC_SPE
); ////
7478 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, PPC_SPE
); ////
7479 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x00000000, PPC_SPE
); //
7480 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0x00000000, PPC_SPE
); ////
7481 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, PPC_SPE
); ////
7482 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, PPC_SPE
); ////
7483 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, PPC_SPE
); ////
7484 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0x00000000, PPC_SPE
); ////
7485 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, PPC_SPE
); ////
7486 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, PPC_SPE
); ////
7487 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, PPC_SPE
);
7488 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, PPC_SPE
); ////
7489 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, PPC_SPE
);
7490 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, PPC_SPE
); //
7491 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, PPC_SPE
);
7492 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, PPC_SPE
); ////
7493 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, PPC_SPE
); ////
7494 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, PPC_SPE
); ////
7495 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, PPC_SPE
); ////
7496 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, PPC_SPE
); ////
7498 /* SPE load and stores */
7499 static always_inline
void gen_addr_spe_imm_index (DisasContext
*ctx
, TCGv EA
, int sh
)
7501 target_ulong uimm
= rB(ctx
->opcode
);
7503 if (rA(ctx
->opcode
) == 0) {
7504 tcg_gen_movi_tl(EA
, uimm
<< sh
);
7506 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], uimm
<< sh
);
7507 #if defined(TARGET_PPC64)
7508 if (!ctx
->sf_mode
) {
7509 tcg_gen_ext32u_tl(EA
, EA
);
7515 static always_inline
void gen_op_evldd(DisasContext
*ctx
, TCGv addr
)
7517 #if defined(TARGET_PPC64)
7518 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7520 TCGv_i64 t0
= tcg_temp_new_i64();
7521 gen_qemu_ld64(ctx
, t0
, addr
);
7522 tcg_gen_trunc_i64_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7523 tcg_gen_shri_i64(t0
, t0
, 32);
7524 tcg_gen_trunc_i64_i32(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7525 tcg_temp_free_i64(t0
);
7529 static always_inline
void gen_op_evldw(DisasContext
*ctx
, TCGv addr
)
7531 #if defined(TARGET_PPC64)
7532 TCGv t0
= tcg_temp_new();
7533 gen_qemu_ld32u(ctx
, t0
, addr
);
7534 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7535 gen_addr_add(ctx
, addr
, addr
, 4);
7536 gen_qemu_ld32u(ctx
, t0
, addr
);
7537 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7540 gen_qemu_ld32u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7541 gen_addr_add(ctx
, addr
, addr
, 4);
7542 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7546 static always_inline
void gen_op_evldh(DisasContext
*ctx
, TCGv addr
)
7548 TCGv t0
= tcg_temp_new();
7549 #if defined(TARGET_PPC64)
7550 gen_qemu_ld16u(ctx
, t0
, addr
);
7551 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7552 gen_addr_add(ctx
, addr
, addr
, 2);
7553 gen_qemu_ld16u(ctx
, t0
, addr
);
7554 tcg_gen_shli_tl(t0
, t0
, 32);
7555 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7556 gen_addr_add(ctx
, addr
, addr
, 2);
7557 gen_qemu_ld16u(ctx
, t0
, addr
);
7558 tcg_gen_shli_tl(t0
, t0
, 16);
7559 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7560 gen_addr_add(ctx
, addr
, addr
, 2);
7561 gen_qemu_ld16u(ctx
, t0
, addr
);
7562 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7564 gen_qemu_ld16u(ctx
, t0
, addr
);
7565 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7566 gen_addr_add(ctx
, addr
, addr
, 2);
7567 gen_qemu_ld16u(ctx
, t0
, addr
);
7568 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7569 gen_addr_add(ctx
, addr
, addr
, 2);
7570 gen_qemu_ld16u(ctx
, t0
, addr
);
7571 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7572 gen_addr_add(ctx
, addr
, addr
, 2);
7573 gen_qemu_ld16u(ctx
, t0
, addr
);
7574 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7579 static always_inline
void gen_op_evlhhesplat(DisasContext
*ctx
, TCGv addr
)
7581 TCGv t0
= tcg_temp_new();
7582 gen_qemu_ld16u(ctx
, t0
, addr
);
7583 #if defined(TARGET_PPC64)
7584 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7585 tcg_gen_shli_tl(t0
, t0
, 16);
7586 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7588 tcg_gen_shli_tl(t0
, t0
, 16);
7589 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7590 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7595 static always_inline
void gen_op_evlhhousplat(DisasContext
*ctx
, TCGv addr
)
7597 TCGv t0
= tcg_temp_new();
7598 gen_qemu_ld16u(ctx
, t0
, addr
);
7599 #if defined(TARGET_PPC64)
7600 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7601 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7603 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7604 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7609 static always_inline
void gen_op_evlhhossplat(DisasContext
*ctx
, TCGv addr
)
7611 TCGv t0
= tcg_temp_new();
7612 gen_qemu_ld16s(ctx
, t0
, addr
);
7613 #if defined(TARGET_PPC64)
7614 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7615 tcg_gen_ext32u_tl(t0
, t0
);
7616 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7618 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7619 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7624 static always_inline
void gen_op_evlwhe(DisasContext
*ctx
, TCGv addr
)
7626 TCGv t0
= tcg_temp_new();
7627 #if defined(TARGET_PPC64)
7628 gen_qemu_ld16u(ctx
, t0
, addr
);
7629 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7630 gen_addr_add(ctx
, addr
, addr
, 2);
7631 gen_qemu_ld16u(ctx
, t0
, addr
);
7632 tcg_gen_shli_tl(t0
, t0
, 16);
7633 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7635 gen_qemu_ld16u(ctx
, t0
, addr
);
7636 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7637 gen_addr_add(ctx
, addr
, addr
, 2);
7638 gen_qemu_ld16u(ctx
, t0
, addr
);
7639 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
7644 static always_inline
void gen_op_evlwhou(DisasContext
*ctx
, TCGv addr
)
7646 #if defined(TARGET_PPC64)
7647 TCGv t0
= tcg_temp_new();
7648 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7649 gen_addr_add(ctx
, addr
, addr
, 2);
7650 gen_qemu_ld16u(ctx
, t0
, addr
);
7651 tcg_gen_shli_tl(t0
, t0
, 32);
7652 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7655 gen_qemu_ld16u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7656 gen_addr_add(ctx
, addr
, addr
, 2);
7657 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7661 static always_inline
void gen_op_evlwhos(DisasContext
*ctx
, TCGv addr
)
7663 #if defined(TARGET_PPC64)
7664 TCGv t0
= tcg_temp_new();
7665 gen_qemu_ld16s(ctx
, t0
, addr
);
7666 tcg_gen_ext32u_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7667 gen_addr_add(ctx
, addr
, addr
, 2);
7668 gen_qemu_ld16s(ctx
, t0
, addr
);
7669 tcg_gen_shli_tl(t0
, t0
, 32);
7670 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7673 gen_qemu_ld16s(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7674 gen_addr_add(ctx
, addr
, addr
, 2);
7675 gen_qemu_ld16s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7679 static always_inline
void gen_op_evlwwsplat(DisasContext
*ctx
, TCGv addr
)
7681 TCGv t0
= tcg_temp_new();
7682 gen_qemu_ld32u(ctx
, t0
, addr
);
7683 #if defined(TARGET_PPC64)
7684 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7685 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7687 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7688 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7693 static always_inline
void gen_op_evlwhsplat(DisasContext
*ctx
, TCGv addr
)
7695 TCGv t0
= tcg_temp_new();
7696 #if defined(TARGET_PPC64)
7697 gen_qemu_ld16u(ctx
, t0
, addr
);
7698 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7699 tcg_gen_shli_tl(t0
, t0
, 32);
7700 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7701 gen_addr_add(ctx
, addr
, addr
, 2);
7702 gen_qemu_ld16u(ctx
, t0
, addr
);
7703 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7704 tcg_gen_shli_tl(t0
, t0
, 16);
7705 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7707 gen_qemu_ld16u(ctx
, t0
, addr
);
7708 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7709 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7710 gen_addr_add(ctx
, addr
, addr
, 2);
7711 gen_qemu_ld16u(ctx
, t0
, addr
);
7712 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
7713 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7718 static always_inline
void gen_op_evstdd(DisasContext
*ctx
, TCGv addr
)
7720 #if defined(TARGET_PPC64)
7721 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7723 TCGv_i64 t0
= tcg_temp_new_i64();
7724 tcg_gen_concat_i32_i64(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gprh
[rS(ctx
->opcode
)]);
7725 gen_qemu_st64(ctx
, t0
, addr
);
7726 tcg_temp_free_i64(t0
);
7730 static always_inline
void gen_op_evstdw(DisasContext
*ctx
, TCGv addr
)
7732 #if defined(TARGET_PPC64)
7733 TCGv t0
= tcg_temp_new();
7734 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7735 gen_qemu_st32(ctx
, t0
, addr
);
7738 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7740 gen_addr_add(ctx
, addr
, addr
, 4);
7741 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7744 static always_inline
void gen_op_evstdh(DisasContext
*ctx
, TCGv addr
)
7746 TCGv t0
= tcg_temp_new();
7747 #if defined(TARGET_PPC64)
7748 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
7750 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
7752 gen_qemu_st16(ctx
, t0
, addr
);
7753 gen_addr_add(ctx
, addr
, addr
, 2);
7754 #if defined(TARGET_PPC64)
7755 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7756 gen_qemu_st16(ctx
, t0
, addr
);
7758 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7760 gen_addr_add(ctx
, addr
, addr
, 2);
7761 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
7762 gen_qemu_st16(ctx
, t0
, addr
);
7764 gen_addr_add(ctx
, addr
, addr
, 2);
7765 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7768 static always_inline
void gen_op_evstwhe(DisasContext
*ctx
, TCGv addr
)
7770 TCGv t0
= tcg_temp_new();
7771 #if defined(TARGET_PPC64)
7772 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
7774 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
7776 gen_qemu_st16(ctx
, t0
, addr
);
7777 gen_addr_add(ctx
, addr
, addr
, 2);
7778 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
7779 gen_qemu_st16(ctx
, t0
, addr
);
7783 static always_inline
void gen_op_evstwho(DisasContext
*ctx
, TCGv addr
)
7785 #if defined(TARGET_PPC64)
7786 TCGv t0
= tcg_temp_new();
7787 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7788 gen_qemu_st16(ctx
, t0
, addr
);
7791 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7793 gen_addr_add(ctx
, addr
, addr
, 2);
7794 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7797 static always_inline
void gen_op_evstwwe(DisasContext
*ctx
, TCGv addr
)
7799 #if defined(TARGET_PPC64)
7800 TCGv t0
= tcg_temp_new();
7801 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7802 gen_qemu_st32(ctx
, t0
, addr
);
7805 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7809 static always_inline
void gen_op_evstwwo(DisasContext
*ctx
, TCGv addr
)
7811 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7814 #define GEN_SPEOP_LDST(name, opc2, sh) \
7815 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE); \
7817 static void glue(gen_, name)(DisasContext *ctx) \
7820 if (unlikely(!ctx->spe_enabled)) { \
7821 gen_exception(ctx, POWERPC_EXCP_APU); \
7824 gen_set_access_type(ctx, ACCESS_INT); \
7825 t0 = tcg_temp_new(); \
7826 if (Rc(ctx->opcode)) { \
7827 gen_addr_spe_imm_index(ctx, t0, sh); \
7829 gen_addr_reg_index(ctx, t0); \
7831 gen_op_##name(ctx, t0); \
7832 tcg_temp_free(t0); \
7835 GEN_SPEOP_LDST(evldd
, 0x00, 3);
7836 GEN_SPEOP_LDST(evldw
, 0x01, 3);
7837 GEN_SPEOP_LDST(evldh
, 0x02, 3);
7838 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1);
7839 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1);
7840 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1);
7841 GEN_SPEOP_LDST(evlwhe
, 0x08, 2);
7842 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2);
7843 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2);
7844 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2);
7845 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2);
7847 GEN_SPEOP_LDST(evstdd
, 0x10, 3);
7848 GEN_SPEOP_LDST(evstdw
, 0x11, 3);
7849 GEN_SPEOP_LDST(evstdh
, 0x12, 3);
7850 GEN_SPEOP_LDST(evstwhe
, 0x18, 2);
7851 GEN_SPEOP_LDST(evstwho
, 0x1A, 2);
7852 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2);
7853 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2);
7855 /* Multiply and add - TODO */
7857 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0x00000000, PPC_SPE
);
7858 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0x00000000, PPC_SPE
);
7859 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, PPC_SPE
);
7860 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0x00000000, PPC_SPE
);
7861 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, PPC_SPE
);
7862 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0x00000000, PPC_SPE
);
7863 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0x00000000, PPC_SPE
);
7864 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0x00000000, PPC_SPE
);
7865 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, PPC_SPE
);
7866 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0x00000000, PPC_SPE
);
7867 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, PPC_SPE
);
7868 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0x00000000, PPC_SPE
);
7870 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0x00000000, PPC_SPE
);
7871 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, PPC_SPE
);
7872 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, PPC_SPE
);
7873 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0x00000000, PPC_SPE
);
7874 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0x00000000, PPC_SPE
);
7875 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, PPC_SPE
);
7876 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0x00000000, PPC_SPE
);
7877 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0x00000000, PPC_SPE
);
7878 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, PPC_SPE
);
7879 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, PPC_SPE
);
7880 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0x00000000, PPC_SPE
);
7881 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0x00000000, PPC_SPE
);
7882 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, PPC_SPE
);
7883 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0x00000000, PPC_SPE
);
7885 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, PPC_SPE
);
7886 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, PPC_SPE
);
7887 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, PPC_SPE
);
7888 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, PPC_SPE
);
7889 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, PPC_SPE
);
7890 GEN_SPE(evmra
, speundef
, 0x07, 0x13, 0x0000F800, PPC_SPE
);
7892 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, PPC_SPE
);
7893 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0x00000000, PPC_SPE
);
7894 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, PPC_SPE
);
7895 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0x00000000, PPC_SPE
);
7896 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, PPC_SPE
);
7897 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0x00000000, PPC_SPE
);
7898 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, PPC_SPE
);
7899 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0x00000000, PPC_SPE
);
7900 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, PPC_SPE
);
7901 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0x00000000, PPC_SPE
);
7902 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, PPC_SPE
);
7903 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0x00000000, PPC_SPE
);
7905 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, PPC_SPE
);
7906 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, PPC_SPE
);
7907 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0x00000000, PPC_SPE
);
7908 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, PPC_SPE
);
7909 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0x00000000, PPC_SPE
);
7911 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, PPC_SPE
);
7912 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0x00000000, PPC_SPE
);
7913 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, PPC_SPE
);
7914 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0x00000000, PPC_SPE
);
7915 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, PPC_SPE
);
7916 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0x00000000, PPC_SPE
);
7917 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, PPC_SPE
);
7918 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0x00000000, PPC_SPE
);
7919 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, PPC_SPE
);
7920 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0x00000000, PPC_SPE
);
7921 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, PPC_SPE
);
7922 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0x00000000, PPC_SPE
);
7924 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, PPC_SPE
);
7925 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, PPC_SPE
);
7926 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0x00000000, PPC_SPE
);
7927 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, PPC_SPE
);
7928 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0x00000000, PPC_SPE
);
7931 /*** SPE floating-point extension ***/
7932 #if defined(TARGET_PPC64)
7933 #define GEN_SPEFPUOP_CONV_32_32(name) \
7934 static always_inline void gen_##name (DisasContext *ctx) \
7938 t0 = tcg_temp_new_i32(); \
7939 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7940 gen_helper_##name(t0, t0); \
7941 t1 = tcg_temp_new(); \
7942 tcg_gen_extu_i32_tl(t1, t0); \
7943 tcg_temp_free_i32(t0); \
7944 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7945 0xFFFFFFFF00000000ULL); \
7946 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7947 tcg_temp_free(t1); \
7949 #define GEN_SPEFPUOP_CONV_32_64(name) \
7950 static always_inline void gen_##name (DisasContext *ctx) \
7954 t0 = tcg_temp_new_i32(); \
7955 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7956 t1 = tcg_temp_new(); \
7957 tcg_gen_extu_i32_tl(t1, t0); \
7958 tcg_temp_free_i32(t0); \
7959 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7960 0xFFFFFFFF00000000ULL); \
7961 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7962 tcg_temp_free(t1); \
7964 #define GEN_SPEFPUOP_CONV_64_32(name) \
7965 static always_inline void gen_##name (DisasContext *ctx) \
7967 TCGv_i32 t0 = tcg_temp_new_i32(); \
7968 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7969 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7970 tcg_temp_free_i32(t0); \
7972 #define GEN_SPEFPUOP_CONV_64_64(name) \
7973 static always_inline void gen_##name (DisasContext *ctx) \
7975 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7977 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7978 static always_inline void gen_##name (DisasContext *ctx) \
7982 if (unlikely(!ctx->spe_enabled)) { \
7983 gen_exception(ctx, POWERPC_EXCP_APU); \
7986 t0 = tcg_temp_new_i32(); \
7987 t1 = tcg_temp_new_i32(); \
7988 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7989 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7990 gen_helper_##name(t0, t0, t1); \
7991 tcg_temp_free_i32(t1); \
7992 t2 = tcg_temp_new(); \
7993 tcg_gen_extu_i32_tl(t2, t0); \
7994 tcg_temp_free_i32(t0); \
7995 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7996 0xFFFFFFFF00000000ULL); \
7997 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7998 tcg_temp_free(t2); \
8000 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8001 static always_inline void gen_##name (DisasContext *ctx) \
8003 if (unlikely(!ctx->spe_enabled)) { \
8004 gen_exception(ctx, POWERPC_EXCP_APU); \
8007 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8008 cpu_gpr[rB(ctx->opcode)]); \
8010 #define GEN_SPEFPUOP_COMP_32(name) \
8011 static always_inline void gen_##name (DisasContext *ctx) \
8014 if (unlikely(!ctx->spe_enabled)) { \
8015 gen_exception(ctx, POWERPC_EXCP_APU); \
8018 t0 = tcg_temp_new_i32(); \
8019 t1 = tcg_temp_new_i32(); \
8020 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8021 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8022 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
8023 tcg_temp_free_i32(t0); \
8024 tcg_temp_free_i32(t1); \
8026 #define GEN_SPEFPUOP_COMP_64(name) \
8027 static always_inline void gen_##name (DisasContext *ctx) \
8029 if (unlikely(!ctx->spe_enabled)) { \
8030 gen_exception(ctx, POWERPC_EXCP_APU); \
8033 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8034 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8037 #define GEN_SPEFPUOP_CONV_32_32(name) \
8038 static always_inline void gen_##name (DisasContext *ctx) \
8040 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8042 #define GEN_SPEFPUOP_CONV_32_64(name) \
8043 static always_inline void gen_##name (DisasContext *ctx) \
8045 TCGv_i64 t0 = tcg_temp_new_i64(); \
8046 gen_load_gpr64(t0, rB(ctx->opcode)); \
8047 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
8048 tcg_temp_free_i64(t0); \
8050 #define GEN_SPEFPUOP_CONV_64_32(name) \
8051 static always_inline void gen_##name (DisasContext *ctx) \
8053 TCGv_i64 t0 = tcg_temp_new_i64(); \
8054 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
8055 gen_store_gpr64(rD(ctx->opcode), t0); \
8056 tcg_temp_free_i64(t0); \
8058 #define GEN_SPEFPUOP_CONV_64_64(name) \
8059 static always_inline void gen_##name (DisasContext *ctx) \
8061 TCGv_i64 t0 = tcg_temp_new_i64(); \
8062 gen_load_gpr64(t0, rB(ctx->opcode)); \
8063 gen_helper_##name(t0, t0); \
8064 gen_store_gpr64(rD(ctx->opcode), t0); \
8065 tcg_temp_free_i64(t0); \
8067 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8068 static always_inline void gen_##name (DisasContext *ctx) \
8070 if (unlikely(!ctx->spe_enabled)) { \
8071 gen_exception(ctx, POWERPC_EXCP_APU); \
8074 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
8075 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8077 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8078 static always_inline void gen_##name (DisasContext *ctx) \
8081 if (unlikely(!ctx->spe_enabled)) { \
8082 gen_exception(ctx, POWERPC_EXCP_APU); \
8085 t0 = tcg_temp_new_i64(); \
8086 t1 = tcg_temp_new_i64(); \
8087 gen_load_gpr64(t0, rA(ctx->opcode)); \
8088 gen_load_gpr64(t1, rB(ctx->opcode)); \
8089 gen_helper_##name(t0, t0, t1); \
8090 gen_store_gpr64(rD(ctx->opcode), t0); \
8091 tcg_temp_free_i64(t0); \
8092 tcg_temp_free_i64(t1); \
8094 #define GEN_SPEFPUOP_COMP_32(name) \
8095 static always_inline void gen_##name (DisasContext *ctx) \
8097 if (unlikely(!ctx->spe_enabled)) { \
8098 gen_exception(ctx, POWERPC_EXCP_APU); \
8101 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8102 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8104 #define GEN_SPEFPUOP_COMP_64(name) \
8105 static always_inline void gen_##name (DisasContext *ctx) \
8108 if (unlikely(!ctx->spe_enabled)) { \
8109 gen_exception(ctx, POWERPC_EXCP_APU); \
8112 t0 = tcg_temp_new_i64(); \
8113 t1 = tcg_temp_new_i64(); \
8114 gen_load_gpr64(t0, rA(ctx->opcode)); \
8115 gen_load_gpr64(t1, rB(ctx->opcode)); \
8116 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
8117 tcg_temp_free_i64(t0); \
8118 tcg_temp_free_i64(t1); \
8122 /* Single precision floating-point vectors operations */
8124 GEN_SPEFPUOP_ARITH2_64_64(evfsadd
);
8125 GEN_SPEFPUOP_ARITH2_64_64(evfssub
);
8126 GEN_SPEFPUOP_ARITH2_64_64(evfsmul
);
8127 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv
);
8128 static always_inline
void gen_evfsabs (DisasContext
*ctx
)
8130 if (unlikely(!ctx
->spe_enabled
)) {
8131 gen_exception(ctx
, POWERPC_EXCP_APU
);
8134 #if defined(TARGET_PPC64)
8135 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000080000000LL
);
8137 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x80000000);
8138 tcg_gen_andi_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
8141 static always_inline
void gen_evfsnabs (DisasContext
*ctx
)
8143 if (unlikely(!ctx
->spe_enabled
)) {
8144 gen_exception(ctx
, POWERPC_EXCP_APU
);
8147 #if defined(TARGET_PPC64)
8148 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
8150 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8151 tcg_gen_ori_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8154 static always_inline
void gen_evfsneg (DisasContext
*ctx
)
8156 if (unlikely(!ctx
->spe_enabled
)) {
8157 gen_exception(ctx
, POWERPC_EXCP_APU
);
8160 #if defined(TARGET_PPC64)
8161 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
8163 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8164 tcg_gen_xori_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8169 GEN_SPEFPUOP_CONV_64_64(evfscfui
);
8170 GEN_SPEFPUOP_CONV_64_64(evfscfsi
);
8171 GEN_SPEFPUOP_CONV_64_64(evfscfuf
);
8172 GEN_SPEFPUOP_CONV_64_64(evfscfsf
);
8173 GEN_SPEFPUOP_CONV_64_64(evfsctui
);
8174 GEN_SPEFPUOP_CONV_64_64(evfsctsi
);
8175 GEN_SPEFPUOP_CONV_64_64(evfsctuf
);
8176 GEN_SPEFPUOP_CONV_64_64(evfsctsf
);
8177 GEN_SPEFPUOP_CONV_64_64(evfsctuiz
);
8178 GEN_SPEFPUOP_CONV_64_64(evfsctsiz
);
8181 GEN_SPEFPUOP_COMP_64(evfscmpgt
);
8182 GEN_SPEFPUOP_COMP_64(evfscmplt
);
8183 GEN_SPEFPUOP_COMP_64(evfscmpeq
);
8184 GEN_SPEFPUOP_COMP_64(evfststgt
);
8185 GEN_SPEFPUOP_COMP_64(evfststlt
);
8186 GEN_SPEFPUOP_COMP_64(evfststeq
);
8188 /* Opcodes definitions */
8189 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE
); //
8190 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE
); //
8191 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE
); //
8192 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE
); //
8193 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE
); //
8194 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE
); //
8195 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE
); //
8196 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE
); //
8197 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE
); //
8198 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE
); //
8199 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE
); //
8200 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE
); //
8201 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE
); //
8202 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE
); //
8204 /* Single precision floating-point operations */
8206 GEN_SPEFPUOP_ARITH2_32_32(efsadd
);
8207 GEN_SPEFPUOP_ARITH2_32_32(efssub
);
8208 GEN_SPEFPUOP_ARITH2_32_32(efsmul
);
8209 GEN_SPEFPUOP_ARITH2_32_32(efsdiv
);
8210 static always_inline
void gen_efsabs (DisasContext
*ctx
)
8212 if (unlikely(!ctx
->spe_enabled
)) {
8213 gen_exception(ctx
, POWERPC_EXCP_APU
);
8216 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], (target_long
)~0x80000000LL
);
8218 static always_inline
void gen_efsnabs (DisasContext
*ctx
)
8220 if (unlikely(!ctx
->spe_enabled
)) {
8221 gen_exception(ctx
, POWERPC_EXCP_APU
);
8224 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8226 static always_inline
void gen_efsneg (DisasContext
*ctx
)
8228 if (unlikely(!ctx
->spe_enabled
)) {
8229 gen_exception(ctx
, POWERPC_EXCP_APU
);
8232 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8236 GEN_SPEFPUOP_CONV_32_32(efscfui
);
8237 GEN_SPEFPUOP_CONV_32_32(efscfsi
);
8238 GEN_SPEFPUOP_CONV_32_32(efscfuf
);
8239 GEN_SPEFPUOP_CONV_32_32(efscfsf
);
8240 GEN_SPEFPUOP_CONV_32_32(efsctui
);
8241 GEN_SPEFPUOP_CONV_32_32(efsctsi
);
8242 GEN_SPEFPUOP_CONV_32_32(efsctuf
);
8243 GEN_SPEFPUOP_CONV_32_32(efsctsf
);
8244 GEN_SPEFPUOP_CONV_32_32(efsctuiz
);
8245 GEN_SPEFPUOP_CONV_32_32(efsctsiz
);
8246 GEN_SPEFPUOP_CONV_32_64(efscfd
);
8249 GEN_SPEFPUOP_COMP_32(efscmpgt
);
8250 GEN_SPEFPUOP_COMP_32(efscmplt
);
8251 GEN_SPEFPUOP_COMP_32(efscmpeq
);
8252 GEN_SPEFPUOP_COMP_32(efststgt
);
8253 GEN_SPEFPUOP_COMP_32(efststlt
);
8254 GEN_SPEFPUOP_COMP_32(efststeq
);
8256 /* Opcodes definitions */
8257 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE
); //
8258 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE
); //
8259 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE
); //
8260 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE
); //
8261 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE
); //
8262 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE
); //
8263 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE
); //
8264 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE
); //
8265 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE
); //
8266 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE
); //
8267 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE
); //
8268 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE
); //
8269 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE
); //
8270 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE
); //
8272 /* Double precision floating-point operations */
8274 GEN_SPEFPUOP_ARITH2_64_64(efdadd
);
8275 GEN_SPEFPUOP_ARITH2_64_64(efdsub
);
8276 GEN_SPEFPUOP_ARITH2_64_64(efdmul
);
8277 GEN_SPEFPUOP_ARITH2_64_64(efddiv
);
8278 static always_inline
void gen_efdabs (DisasContext
*ctx
)
8280 if (unlikely(!ctx
->spe_enabled
)) {
8281 gen_exception(ctx
, POWERPC_EXCP_APU
);
8284 #if defined(TARGET_PPC64)
8285 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000000000000LL
);
8287 tcg_gen_andi_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
8290 static always_inline
void gen_efdnabs (DisasContext
*ctx
)
8292 if (unlikely(!ctx
->spe_enabled
)) {
8293 gen_exception(ctx
, POWERPC_EXCP_APU
);
8296 #if defined(TARGET_PPC64)
8297 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
8299 tcg_gen_ori_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8302 static always_inline
void gen_efdneg (DisasContext
*ctx
)
8304 if (unlikely(!ctx
->spe_enabled
)) {
8305 gen_exception(ctx
, POWERPC_EXCP_APU
);
8308 #if defined(TARGET_PPC64)
8309 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
8311 tcg_gen_xori_tl(cpu_gprh
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8316 GEN_SPEFPUOP_CONV_64_32(efdcfui
);
8317 GEN_SPEFPUOP_CONV_64_32(efdcfsi
);
8318 GEN_SPEFPUOP_CONV_64_32(efdcfuf
);
8319 GEN_SPEFPUOP_CONV_64_32(efdcfsf
);
8320 GEN_SPEFPUOP_CONV_32_64(efdctui
);
8321 GEN_SPEFPUOP_CONV_32_64(efdctsi
);
8322 GEN_SPEFPUOP_CONV_32_64(efdctuf
);
8323 GEN_SPEFPUOP_CONV_32_64(efdctsf
);
8324 GEN_SPEFPUOP_CONV_32_64(efdctuiz
);
8325 GEN_SPEFPUOP_CONV_32_64(efdctsiz
);
8326 GEN_SPEFPUOP_CONV_64_32(efdcfs
);
8327 GEN_SPEFPUOP_CONV_64_64(efdcfuid
);
8328 GEN_SPEFPUOP_CONV_64_64(efdcfsid
);
8329 GEN_SPEFPUOP_CONV_64_64(efdctuidz
);
8330 GEN_SPEFPUOP_CONV_64_64(efdctsidz
);
8333 GEN_SPEFPUOP_COMP_64(efdcmpgt
);
8334 GEN_SPEFPUOP_COMP_64(efdcmplt
);
8335 GEN_SPEFPUOP_COMP_64(efdcmpeq
);
8336 GEN_SPEFPUOP_COMP_64(efdtstgt
);
8337 GEN_SPEFPUOP_COMP_64(efdtstlt
);
8338 GEN_SPEFPUOP_COMP_64(efdtsteq
);
8340 /* Opcodes definitions */
8341 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE
); //
8342 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8343 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE
); //
8344 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE
); //
8345 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE
); //
8346 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8347 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE
); //
8348 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE
); //
8349 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8350 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8351 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8352 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8353 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8354 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE
); //
8355 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE
); //
8356 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE
); //
8358 /* End opcode list */
8359 GEN_OPCODE_MARK(end
);
8361 #include "translate_init.c"
8362 #include "helper_regs.h"
8364 /*****************************************************************************/
8365 /* Misc PowerPC helpers */
8366 void cpu_dump_state (CPUState
*env
, FILE *f
,
8367 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8375 cpu_fprintf(f
, "NIP " ADDRX
" LR " ADDRX
" CTR " ADDRX
" XER %08x\n",
8376 env
->nip
, env
->lr
, env
->ctr
, env
->xer
);
8377 cpu_fprintf(f
, "MSR " ADDRX
" HID0 " ADDRX
" HF " ADDRX
" idx %d\n",
8378 env
->msr
, env
->spr
[SPR_HID0
], env
->hflags
, env
->mmu_idx
);
8379 #if !defined(NO_TIMER_DUMP)
8380 cpu_fprintf(f
, "TB %08x %08x "
8381 #if !defined(CONFIG_USER_ONLY)
8385 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
8386 #if !defined(CONFIG_USER_ONLY)
8387 , cpu_ppc_load_decr(env
)
8391 for (i
= 0; i
< 32; i
++) {
8392 if ((i
& (RGPL
- 1)) == 0)
8393 cpu_fprintf(f
, "GPR%02d", i
);
8394 cpu_fprintf(f
, " " REGX
, ppc_dump_gpr(env
, i
));
8395 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
8396 cpu_fprintf(f
, "\n");
8398 cpu_fprintf(f
, "CR ");
8399 for (i
= 0; i
< 8; i
++)
8400 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
8401 cpu_fprintf(f
, " [");
8402 for (i
= 0; i
< 8; i
++) {
8404 if (env
->crf
[i
] & 0x08)
8406 else if (env
->crf
[i
] & 0x04)
8408 else if (env
->crf
[i
] & 0x02)
8410 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
8412 cpu_fprintf(f
, " ] RES " ADDRX
"\n", env
->reserve
);
8413 for (i
= 0; i
< 32; i
++) {
8414 if ((i
& (RFPL
- 1)) == 0)
8415 cpu_fprintf(f
, "FPR%02d", i
);
8416 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
8417 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
8418 cpu_fprintf(f
, "\n");
8420 cpu_fprintf(f
, "FPSCR %08x\n", env
->fpscr
);
8421 #if !defined(CONFIG_USER_ONLY)
8422 cpu_fprintf(f
, "SRR0 " ADDRX
" SRR1 " ADDRX
" SDR1 " ADDRX
"\n",
8423 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
], env
->sdr1
);
8430 void cpu_dump_statistics (CPUState
*env
, FILE*f
,
8431 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8434 #if defined(DO_PPC_STATISTICS)
8435 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
8439 for (op1
= 0; op1
< 64; op1
++) {
8441 if (is_indirect_opcode(handler
)) {
8442 t2
= ind_table(handler
);
8443 for (op2
= 0; op2
< 32; op2
++) {
8445 if (is_indirect_opcode(handler
)) {
8446 t3
= ind_table(handler
);
8447 for (op3
= 0; op3
< 32; op3
++) {
8449 if (handler
->count
== 0)
8451 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
8453 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
8455 handler
->count
, handler
->count
);
8458 if (handler
->count
== 0)
8460 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
8462 op1
, op2
, op1
, op2
, handler
->oname
,
8463 handler
->count
, handler
->count
);
8467 if (handler
->count
== 0)
8469 cpu_fprintf(f
, "%02x (%02x ) %16s: %016llx %lld\n",
8470 op1
, op1
, handler
->oname
,
8471 handler
->count
, handler
->count
);
8477 /*****************************************************************************/
8478 static always_inline
void gen_intermediate_code_internal (CPUState
*env
,
8479 TranslationBlock
*tb
,
8482 DisasContext ctx
, *ctxp
= &ctx
;
8483 opc_handler_t
**table
, *handler
;
8484 target_ulong pc_start
;
8485 uint16_t *gen_opc_end
;
8492 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
8495 ctx
.exception
= POWERPC_EXCP_NONE
;
8496 ctx
.spr_cb
= env
->spr_cb
;
8497 ctx
.mem_idx
= env
->mmu_idx
;
8498 ctx
.access_type
= -1;
8499 ctx
.le_mode
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
8500 #if defined(TARGET_PPC64)
8501 ctx
.sf_mode
= msr_sf
;
8503 ctx
.fpu_enabled
= msr_fp
;
8504 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
8505 ctx
.spe_enabled
= msr_spe
;
8507 ctx
.spe_enabled
= 0;
8508 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
8509 ctx
.altivec_enabled
= msr_vr
;
8511 ctx
.altivec_enabled
= 0;
8512 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
8513 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
8515 ctx
.singlestep_enabled
= 0;
8516 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
8517 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
8518 if (unlikely(env
->singlestep_enabled
))
8519 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
8520 #if defined (DO_SINGLE_STEP) && 0
8521 /* Single step trace mode */
8525 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8527 max_insns
= CF_COUNT_MASK
;
8530 /* Set env in case of segfault during code fetch */
8531 while (ctx
.exception
== POWERPC_EXCP_NONE
&& gen_opc_ptr
< gen_opc_end
) {
8532 if (unlikely(!TAILQ_EMPTY(&env
->breakpoints
))) {
8533 TAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
8534 if (bp
->pc
== ctx
.nip
) {
8535 gen_debug_exception(ctxp
);
8540 if (unlikely(search_pc
)) {
8541 j
= gen_opc_ptr
- gen_opc_buf
;
8545 gen_opc_instr_start
[lj
++] = 0;
8547 gen_opc_pc
[lj
] = ctx
.nip
;
8548 gen_opc_instr_start
[lj
] = 1;
8549 gen_opc_icount
[lj
] = num_insns
;
8551 LOG_DISAS("----------------\n");
8552 LOG_DISAS("nip=" ADDRX
" super=%d ir=%d\n",
8553 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
8554 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8556 if (unlikely(ctx
.le_mode
)) {
8557 ctx
.opcode
= bswap32(ldl_code(ctx
.nip
));
8559 ctx
.opcode
= ldl_code(ctx
.nip
);
8561 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
8562 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
8563 opc3(ctx
.opcode
), little_endian
? "little" : "big");
8565 table
= env
->opcodes
;
8567 handler
= table
[opc1(ctx
.opcode
)];
8568 if (is_indirect_opcode(handler
)) {
8569 table
= ind_table(handler
);
8570 handler
= table
[opc2(ctx
.opcode
)];
8571 if (is_indirect_opcode(handler
)) {
8572 table
= ind_table(handler
);
8573 handler
= table
[opc3(ctx
.opcode
)];
8576 /* Is opcode *REALLY* valid ? */
8577 if (unlikely(handler
->handler
== &gen_invalid
)) {
8578 if (qemu_log_enabled()) {
8579 qemu_log("invalid/unsupported opcode: "
8580 "%02x - %02x - %02x (%08x) " ADDRX
" %d\n",
8581 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
8582 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
8584 printf("invalid/unsupported opcode: "
8585 "%02x - %02x - %02x (%08x) " ADDRX
" %d\n",
8586 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
8587 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
8590 if (unlikely((ctx
.opcode
& handler
->inval
) != 0)) {
8591 if (qemu_log_enabled()) {
8592 qemu_log("invalid bits: %08x for opcode: "
8593 "%02x - %02x - %02x (%08x) " ADDRX
"\n",
8594 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
8595 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
8596 ctx
.opcode
, ctx
.nip
- 4);
8598 printf("invalid bits: %08x for opcode: "
8599 "%02x - %02x - %02x (%08x) " ADDRX
"\n",
8600 ctx
.opcode
& handler
->inval
, opc1(ctx
.opcode
),
8601 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
8602 ctx
.opcode
, ctx
.nip
- 4);
8604 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
8608 (*(handler
->handler
))(&ctx
);
8609 #if defined(DO_PPC_STATISTICS)
8612 /* Check trace mode exceptions */
8613 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
8614 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
8615 ctx
.exception
!= POWERPC_SYSCALL
&&
8616 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
8617 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
8618 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
8619 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
8620 (env
->singlestep_enabled
) ||
8622 num_insns
>= max_insns
)) {
8623 /* if we reach a page boundary or are single stepping, stop
8629 if (tb
->cflags
& CF_LAST_IO
)
8631 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
8632 gen_goto_tb(&ctx
, 0, ctx
.nip
);
8633 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
8634 if (unlikely(env
->singlestep_enabled
)) {
8635 gen_debug_exception(ctxp
);
8637 /* Generate the return instruction */
8640 gen_icount_end(tb
, num_insns
);
8641 *gen_opc_ptr
= INDEX_op_end
;
8642 if (unlikely(search_pc
)) {
8643 j
= gen_opc_ptr
- gen_opc_buf
;
8646 gen_opc_instr_start
[lj
++] = 0;
8648 tb
->size
= ctx
.nip
- pc_start
;
8649 tb
->icount
= num_insns
;
8651 #if defined(DEBUG_DISAS)
8652 qemu_log_mask(CPU_LOG_TB_CPU
, "---------------- excp: %04x\n", ctx
.exception
);
8653 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, 0);
8654 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8656 flags
= env
->bfd_mach
;
8657 flags
|= ctx
.le_mode
<< 16;
8658 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8659 log_target_disas(pc_start
, ctx
.nip
- pc_start
, flags
);
8665 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
8667 gen_intermediate_code_internal(env
, tb
, 0);
8670 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
8672 gen_intermediate_code_internal(env
, tb
, 1);
8675 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
8676 unsigned long searched_pc
, int pc_pos
, void *puc
)
8678 env
->nip
= gen_opc_pc
[pc_pos
];