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target-ppc: Use NARROW_MODE macro for tlbie
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 /* True when active word size < size of target_long. */
208 #ifdef TARGET_PPC64
209 # define NARROW_MODE(C) (!(C)->sf_mode)
210 #else
211 # define NARROW_MODE(C) 0
212 #endif
213
214 struct opc_handler_t {
215 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
216 uint32_t inval1;
217 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
218 uint32_t inval2;
219 /* instruction type */
220 uint64_t type;
221 /* extended instruction type */
222 uint64_t type2;
223 /* handler */
224 void (*handler)(DisasContext *ctx);
225 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
226 const char *oname;
227 #endif
228 #if defined(DO_PPC_STATISTICS)
229 uint64_t count;
230 #endif
231 };
232
233 static inline void gen_reset_fpstatus(void)
234 {
235 gen_helper_reset_fpstatus(cpu_env);
236 }
237
238 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
239 {
240 TCGv_i32 t0 = tcg_temp_new_i32();
241
242 if (set_fprf != 0) {
243 /* This case might be optimized later */
244 tcg_gen_movi_i32(t0, 1);
245 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
246 if (unlikely(set_rc)) {
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249 gen_helper_float_check_status(cpu_env);
250 } else if (unlikely(set_rc)) {
251 /* We always need to compute fpcc */
252 tcg_gen_movi_i32(t0, 0);
253 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
254 tcg_gen_mov_i32(cpu_crf[1], t0);
255 }
256
257 tcg_temp_free_i32(t0);
258 }
259
260 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
261 {
262 if (ctx->access_type != access_type) {
263 tcg_gen_movi_i32(cpu_access_type, access_type);
264 ctx->access_type = access_type;
265 }
266 }
267
268 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
269 {
270 if (NARROW_MODE(ctx)) {
271 nip = (uint32_t)nip;
272 }
273 tcg_gen_movi_tl(cpu_nip, nip);
274 }
275
276 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
277 {
278 TCGv_i32 t0, t1;
279 if (ctx->exception == POWERPC_EXCP_NONE) {
280 gen_update_nip(ctx, ctx->nip);
281 }
282 t0 = tcg_const_i32(excp);
283 t1 = tcg_const_i32(error);
284 gen_helper_raise_exception_err(cpu_env, t0, t1);
285 tcg_temp_free_i32(t0);
286 tcg_temp_free_i32(t1);
287 ctx->exception = (excp);
288 }
289
290 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
291 {
292 TCGv_i32 t0;
293 if (ctx->exception == POWERPC_EXCP_NONE) {
294 gen_update_nip(ctx, ctx->nip);
295 }
296 t0 = tcg_const_i32(excp);
297 gen_helper_raise_exception(cpu_env, t0);
298 tcg_temp_free_i32(t0);
299 ctx->exception = (excp);
300 }
301
302 static inline void gen_debug_exception(DisasContext *ctx)
303 {
304 TCGv_i32 t0;
305
306 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
307 (ctx->exception != POWERPC_EXCP_SYNC)) {
308 gen_update_nip(ctx, ctx->nip);
309 }
310 t0 = tcg_const_i32(EXCP_DEBUG);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 }
314
315 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
316 {
317 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
318 }
319
320 /* Stop translation */
321 static inline void gen_stop_exception(DisasContext *ctx)
322 {
323 gen_update_nip(ctx, ctx->nip);
324 ctx->exception = POWERPC_EXCP_STOP;
325 }
326
327 /* No need to update nip here, as execution flow will change */
328 static inline void gen_sync_exception(DisasContext *ctx)
329 {
330 ctx->exception = POWERPC_EXCP_SYNC;
331 }
332
333 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
334 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
335
336 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
337 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
338
339 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
344
345 typedef struct opcode_t {
346 unsigned char opc1, opc2, opc3;
347 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
348 unsigned char pad[5];
349 #else
350 unsigned char pad[1];
351 #endif
352 opc_handler_t handler;
353 const char *oname;
354 } opcode_t;
355
356 /*****************************************************************************/
357 /*** Instruction decoding ***/
358 #define EXTRACT_HELPER(name, shift, nb) \
359 static inline uint32_t name(uint32_t opcode) \
360 { \
361 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
362 }
363
364 #define EXTRACT_SHELPER(name, shift, nb) \
365 static inline int32_t name(uint32_t opcode) \
366 { \
367 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
368 }
369
370 /* Opcode part 1 */
371 EXTRACT_HELPER(opc1, 26, 6);
372 /* Opcode part 2 */
373 EXTRACT_HELPER(opc2, 1, 5);
374 /* Opcode part 3 */
375 EXTRACT_HELPER(opc3, 6, 5);
376 /* Update Cr0 flags */
377 EXTRACT_HELPER(Rc, 0, 1);
378 /* Destination */
379 EXTRACT_HELPER(rD, 21, 5);
380 /* Source */
381 EXTRACT_HELPER(rS, 21, 5);
382 /* First operand */
383 EXTRACT_HELPER(rA, 16, 5);
384 /* Second operand */
385 EXTRACT_HELPER(rB, 11, 5);
386 /* Third operand */
387 EXTRACT_HELPER(rC, 6, 5);
388 /*** Get CRn ***/
389 EXTRACT_HELPER(crfD, 23, 3);
390 EXTRACT_HELPER(crfS, 18, 3);
391 EXTRACT_HELPER(crbD, 21, 5);
392 EXTRACT_HELPER(crbA, 16, 5);
393 EXTRACT_HELPER(crbB, 11, 5);
394 /* SPR / TBL */
395 EXTRACT_HELPER(_SPR, 11, 10);
396 static inline uint32_t SPR(uint32_t opcode)
397 {
398 uint32_t sprn = _SPR(opcode);
399
400 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
401 }
402 /*** Get constants ***/
403 EXTRACT_HELPER(IMM, 12, 8);
404 /* 16 bits signed immediate value */
405 EXTRACT_SHELPER(SIMM, 0, 16);
406 /* 16 bits unsigned immediate value */
407 EXTRACT_HELPER(UIMM, 0, 16);
408 /* 5 bits signed immediate value */
409 EXTRACT_HELPER(SIMM5, 16, 5);
410 /* 5 bits signed immediate value */
411 EXTRACT_HELPER(UIMM5, 16, 5);
412 /* Bit count */
413 EXTRACT_HELPER(NB, 11, 5);
414 /* Shift count */
415 EXTRACT_HELPER(SH, 11, 5);
416 /* Vector shift count */
417 EXTRACT_HELPER(VSH, 6, 4);
418 /* Mask start */
419 EXTRACT_HELPER(MB, 6, 5);
420 /* Mask end */
421 EXTRACT_HELPER(ME, 1, 5);
422 /* Trap operand */
423 EXTRACT_HELPER(TO, 21, 5);
424
425 EXTRACT_HELPER(CRM, 12, 8);
426 EXTRACT_HELPER(FM, 17, 8);
427 EXTRACT_HELPER(SR, 16, 4);
428 EXTRACT_HELPER(FPIMM, 12, 4);
429
430 /*** Jump target decoding ***/
431 /* Displacement */
432 EXTRACT_SHELPER(d, 0, 16);
433 /* Immediate address */
434 static inline target_ulong LI(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0x03FFFFFC;
437 }
438
439 static inline uint32_t BD(uint32_t opcode)
440 {
441 return (opcode >> 0) & 0xFFFC;
442 }
443
444 EXTRACT_HELPER(BO, 21, 5);
445 EXTRACT_HELPER(BI, 16, 5);
446 /* Absolute/relative address */
447 EXTRACT_HELPER(AA, 1, 1);
448 /* Link */
449 EXTRACT_HELPER(LK, 0, 1);
450
451 /* Create a mask between <start> and <end> bits */
452 static inline target_ulong MASK(uint32_t start, uint32_t end)
453 {
454 target_ulong ret;
455
456 #if defined(TARGET_PPC64)
457 if (likely(start == 0)) {
458 ret = UINT64_MAX << (63 - end);
459 } else if (likely(end == 63)) {
460 ret = UINT64_MAX >> start;
461 }
462 #else
463 if (likely(start == 0)) {
464 ret = UINT32_MAX << (31 - end);
465 } else if (likely(end == 31)) {
466 ret = UINT32_MAX >> start;
467 }
468 #endif
469 else {
470 ret = (((target_ulong)(-1ULL)) >> (start)) ^
471 (((target_ulong)(-1ULL) >> (end)) >> 1);
472 if (unlikely(start > end))
473 return ~ret;
474 }
475
476 return ret;
477 }
478
479 /*****************************************************************************/
480 /* PowerPC instructions table */
481
482 #if defined(DO_PPC_STATISTICS)
483 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
484 { \
485 .opc1 = op1, \
486 .opc2 = op2, \
487 .opc3 = op3, \
488 .pad = { 0, }, \
489 .handler = { \
490 .inval1 = invl, \
491 .type = _typ, \
492 .type2 = _typ2, \
493 .handler = &gen_##name, \
494 .oname = stringify(name), \
495 }, \
496 .oname = stringify(name), \
497 }
498 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
499 { \
500 .opc1 = op1, \
501 .opc2 = op2, \
502 .opc3 = op3, \
503 .pad = { 0, }, \
504 .handler = { \
505 .inval1 = invl1, \
506 .inval2 = invl2, \
507 .type = _typ, \
508 .type2 = _typ2, \
509 .handler = &gen_##name, \
510 .oname = stringify(name), \
511 }, \
512 .oname = stringify(name), \
513 }
514 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
515 { \
516 .opc1 = op1, \
517 .opc2 = op2, \
518 .opc3 = op3, \
519 .pad = { 0, }, \
520 .handler = { \
521 .inval1 = invl, \
522 .type = _typ, \
523 .type2 = _typ2, \
524 .handler = &gen_##name, \
525 .oname = onam, \
526 }, \
527 .oname = onam, \
528 }
529 #else
530 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
531 { \
532 .opc1 = op1, \
533 .opc2 = op2, \
534 .opc3 = op3, \
535 .pad = { 0, }, \
536 .handler = { \
537 .inval1 = invl, \
538 .type = _typ, \
539 .type2 = _typ2, \
540 .handler = &gen_##name, \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .pad = { 0, }, \
550 .handler = { \
551 .inval1 = invl1, \
552 .inval2 = invl2, \
553 .type = _typ, \
554 .type2 = _typ2, \
555 .handler = &gen_##name, \
556 }, \
557 .oname = stringify(name), \
558 }
559 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
560 { \
561 .opc1 = op1, \
562 .opc2 = op2, \
563 .opc3 = op3, \
564 .pad = { 0, }, \
565 .handler = { \
566 .inval1 = invl, \
567 .type = _typ, \
568 .type2 = _typ2, \
569 .handler = &gen_##name, \
570 }, \
571 .oname = onam, \
572 }
573 #endif
574
575 /* SPR load/store helpers */
576 static inline void gen_load_spr(TCGv t, int reg)
577 {
578 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 static inline void gen_store_spr(int reg, TCGv t)
582 {
583 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
584 }
585
586 /* Invalid instruction */
587 static void gen_invalid(DisasContext *ctx)
588 {
589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
590 }
591
592 static opc_handler_t invalid_handler = {
593 .inval1 = 0xFFFFFFFF,
594 .inval2 = 0xFFFFFFFF,
595 .type = PPC_NONE,
596 .type2 = PPC_NONE,
597 .handler = gen_invalid,
598 };
599
600 /*** Integer comparison ***/
601
602 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
603 {
604 TCGv t0 = tcg_temp_new();
605 TCGv_i32 t1 = tcg_temp_new_i32();
606
607 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_LT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_GT);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
620 tcg_gen_trunc_tl_i32(t1, t0);
621 tcg_gen_shli_i32(t1, t1, CRF_EQ);
622 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
623
624 tcg_temp_free(t0);
625 tcg_temp_free_i32(t1);
626 }
627
628 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
629 {
630 TCGv t0 = tcg_const_tl(arg1);
631 gen_op_cmp(arg0, t0, s, crf);
632 tcg_temp_free(t0);
633 }
634
635 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
636 {
637 TCGv t0, t1;
638 t0 = tcg_temp_new();
639 t1 = tcg_temp_new();
640 if (s) {
641 tcg_gen_ext32s_tl(t0, arg0);
642 tcg_gen_ext32s_tl(t1, arg1);
643 } else {
644 tcg_gen_ext32u_tl(t0, arg0);
645 tcg_gen_ext32u_tl(t1, arg1);
646 }
647 gen_op_cmp(t0, t1, s, crf);
648 tcg_temp_free(t1);
649 tcg_temp_free(t0);
650 }
651
652 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
653 {
654 TCGv t0 = tcg_const_tl(arg1);
655 gen_op_cmp32(arg0, t0, s, crf);
656 tcg_temp_free(t0);
657 }
658
659 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
660 {
661 if (NARROW_MODE(ctx)) {
662 gen_op_cmpi32(reg, 0, 1, 0);
663 } else {
664 gen_op_cmpi(reg, 0, 1, 0);
665 }
666 }
667
668 /* cmp */
669 static void gen_cmp(DisasContext *ctx)
670 {
671 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
672 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
673 1, crfD(ctx->opcode));
674 } else {
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678 }
679
680 /* cmpi */
681 static void gen_cmpi(DisasContext *ctx)
682 {
683 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 } else {
687 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
688 1, crfD(ctx->opcode));
689 }
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
696 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
697 0, crfD(ctx->opcode));
698 } else {
699 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
700 0, crfD(ctx->opcode));
701 }
702 }
703
704 /* cmpli */
705 static void gen_cmpli(DisasContext *ctx)
706 {
707 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
708 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
709 0, crfD(ctx->opcode));
710 } else {
711 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
712 0, crfD(ctx->opcode));
713 }
714 }
715
716 /* isel (PowerPC 2.03 specification) */
717 static void gen_isel(DisasContext *ctx)
718 {
719 int l1, l2;
720 uint32_t bi = rC(ctx->opcode);
721 uint32_t mask;
722 TCGv_i32 t0;
723
724 l1 = gen_new_label();
725 l2 = gen_new_label();
726
727 mask = 1 << (3 - (bi & 0x03));
728 t0 = tcg_temp_new_i32();
729 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
730 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
731 if (rA(ctx->opcode) == 0)
732 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
733 else
734 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
735 tcg_gen_br(l2);
736 gen_set_label(l1);
737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
738 gen_set_label(l2);
739 tcg_temp_free_i32(t0);
740 }
741
742 /*** Integer arithmetic ***/
743
744 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
745 TCGv arg1, TCGv arg2, int sub)
746 {
747 TCGv t0 = tcg_temp_new();
748
749 tcg_gen_xor_tl(cpu_ov, arg0, arg1);
750 tcg_gen_xor_tl(t0, arg1, arg2);
751 if (sub) {
752 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
753 } else {
754 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
755 }
756 tcg_temp_free(t0);
757 if (NARROW_MODE(ctx)) {
758 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
759 }
760 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
761 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
762 }
763
764 /* Common add function */
765 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
766 TCGv arg2, bool add_ca, bool compute_ca,
767 bool compute_ov, bool compute_rc0)
768 {
769 TCGv t0 = ret;
770
771 if (((compute_ca && add_ca) || compute_ov)
772 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
773 t0 = tcg_temp_new();
774 }
775
776 if (compute_ca) {
777 if (NARROW_MODE(ctx)) {
778 TCGv t1 = tcg_temp_new();
779 tcg_gen_ext32u_tl(t1, arg2);
780 tcg_gen_ext32u_tl(t0, arg1);
781 tcg_gen_add_tl(t0, t0, t1);
782 tcg_temp_free(t1);
783 if (add_ca) {
784 tcg_gen_add_tl(t0, t0, cpu_ca);
785 }
786 tcg_gen_shri_tl(cpu_ca, t0, 32);
787 } else {
788 TCGv zero = tcg_const_tl(0);
789 if (add_ca) {
790 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
791 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
792 } else {
793 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
794 }
795 tcg_temp_free(zero);
796 }
797 } else {
798 tcg_gen_add_tl(t0, arg1, arg2);
799 if (add_ca) {
800 tcg_gen_add_tl(t0, t0, cpu_ca);
801 }
802 }
803
804 if (compute_ov) {
805 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
806 }
807 if (unlikely(compute_rc0)) {
808 gen_set_Rc0(ctx, t0);
809 }
810
811 if (!TCGV_EQUAL(t0, ret)) {
812 tcg_gen_mov_tl(ret, t0);
813 tcg_temp_free(t0);
814 }
815 }
816 /* Add functions with two operands */
817 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
818 static void glue(gen_, name)(DisasContext *ctx) \
819 { \
820 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
821 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
822 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
823 }
824 /* Add functions with one operand and one immediate */
825 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
826 add_ca, compute_ca, compute_ov) \
827 static void glue(gen_, name)(DisasContext *ctx) \
828 { \
829 TCGv t0 = tcg_const_tl(const_val); \
830 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
831 cpu_gpr[rA(ctx->opcode)], t0, \
832 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
833 tcg_temp_free(t0); \
834 }
835
836 /* add add. addo addo. */
837 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
838 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
839 /* addc addc. addco addco. */
840 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
841 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
842 /* adde adde. addeo addeo. */
843 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
844 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
845 /* addme addme. addmeo addmeo. */
846 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
847 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
848 /* addze addze. addzeo addzeo.*/
849 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
850 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
851 /* addi */
852 static void gen_addi(DisasContext *ctx)
853 {
854 target_long simm = SIMM(ctx->opcode);
855
856 if (rA(ctx->opcode) == 0) {
857 /* li case */
858 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
859 } else {
860 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
861 cpu_gpr[rA(ctx->opcode)], simm);
862 }
863 }
864 /* addic addic.*/
865 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
866 {
867 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
868 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
869 c, 0, 1, 0, compute_rc0);
870 tcg_temp_free(c);
871 }
872
873 static void gen_addic(DisasContext *ctx)
874 {
875 gen_op_addic(ctx, 0);
876 }
877
878 static void gen_addic_(DisasContext *ctx)
879 {
880 gen_op_addic(ctx, 1);
881 }
882
883 /* addis */
884 static void gen_addis(DisasContext *ctx)
885 {
886 target_long simm = SIMM(ctx->opcode);
887
888 if (rA(ctx->opcode) == 0) {
889 /* lis case */
890 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
891 } else {
892 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
893 cpu_gpr[rA(ctx->opcode)], simm << 16);
894 }
895 }
896
897 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
898 TCGv arg2, int sign, int compute_ov)
899 {
900 int l1 = gen_new_label();
901 int l2 = gen_new_label();
902 TCGv_i32 t0 = tcg_temp_local_new_i32();
903 TCGv_i32 t1 = tcg_temp_local_new_i32();
904
905 tcg_gen_trunc_tl_i32(t0, arg1);
906 tcg_gen_trunc_tl_i32(t1, arg2);
907 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
908 if (sign) {
909 int l3 = gen_new_label();
910 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
911 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
912 gen_set_label(l3);
913 tcg_gen_div_i32(t0, t0, t1);
914 } else {
915 tcg_gen_divu_i32(t0, t0, t1);
916 }
917 if (compute_ov) {
918 tcg_gen_movi_tl(cpu_ov, 0);
919 }
920 tcg_gen_br(l2);
921 gen_set_label(l1);
922 if (sign) {
923 tcg_gen_sari_i32(t0, t0, 31);
924 } else {
925 tcg_gen_movi_i32(t0, 0);
926 }
927 if (compute_ov) {
928 tcg_gen_movi_tl(cpu_ov, 1);
929 tcg_gen_movi_tl(cpu_so, 1);
930 }
931 gen_set_label(l2);
932 tcg_gen_extu_i32_tl(ret, t0);
933 tcg_temp_free_i32(t0);
934 tcg_temp_free_i32(t1);
935 if (unlikely(Rc(ctx->opcode) != 0))
936 gen_set_Rc0(ctx, ret);
937 }
938 /* Div functions */
939 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
940 static void glue(gen_, name)(DisasContext *ctx) \
941 { \
942 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
943 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
944 sign, compute_ov); \
945 }
946 /* divwu divwu. divwuo divwuo. */
947 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
948 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
949 /* divw divw. divwo divwo. */
950 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
951 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
952 #if defined(TARGET_PPC64)
953 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
954 TCGv arg2, int sign, int compute_ov)
955 {
956 int l1 = gen_new_label();
957 int l2 = gen_new_label();
958
959 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
960 if (sign) {
961 int l3 = gen_new_label();
962 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
963 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
964 gen_set_label(l3);
965 tcg_gen_div_i64(ret, arg1, arg2);
966 } else {
967 tcg_gen_divu_i64(ret, arg1, arg2);
968 }
969 if (compute_ov) {
970 tcg_gen_movi_tl(cpu_ov, 0);
971 }
972 tcg_gen_br(l2);
973 gen_set_label(l1);
974 if (sign) {
975 tcg_gen_sari_i64(ret, arg1, 63);
976 } else {
977 tcg_gen_movi_i64(ret, 0);
978 }
979 if (compute_ov) {
980 tcg_gen_movi_tl(cpu_ov, 1);
981 tcg_gen_movi_tl(cpu_so, 1);
982 }
983 gen_set_label(l2);
984 if (unlikely(Rc(ctx->opcode) != 0))
985 gen_set_Rc0(ctx, ret);
986 }
987 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
988 static void glue(gen_, name)(DisasContext *ctx) \
989 { \
990 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
991 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
992 sign, compute_ov); \
993 }
994 /* divwu divwu. divwuo divwuo. */
995 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
996 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
997 /* divw divw. divwo divwo. */
998 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
999 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1000 #endif
1001
1002 /* mulhw mulhw. */
1003 static void gen_mulhw(DisasContext *ctx)
1004 {
1005 TCGv_i32 t0 = tcg_temp_new_i32();
1006 TCGv_i32 t1 = tcg_temp_new_i32();
1007
1008 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1009 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1010 tcg_gen_muls2_i32(t0, t1, t0, t1);
1011 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1012 tcg_temp_free_i32(t0);
1013 tcg_temp_free_i32(t1);
1014 if (unlikely(Rc(ctx->opcode) != 0))
1015 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1016 }
1017
1018 /* mulhwu mulhwu. */
1019 static void gen_mulhwu(DisasContext *ctx)
1020 {
1021 TCGv_i32 t0 = tcg_temp_new_i32();
1022 TCGv_i32 t1 = tcg_temp_new_i32();
1023
1024 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1025 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1026 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1027 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1028 tcg_temp_free_i32(t0);
1029 tcg_temp_free_i32(t1);
1030 if (unlikely(Rc(ctx->opcode) != 0))
1031 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1032 }
1033
1034 /* mullw mullw. */
1035 static void gen_mullw(DisasContext *ctx)
1036 {
1037 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1038 cpu_gpr[rB(ctx->opcode)]);
1039 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1040 if (unlikely(Rc(ctx->opcode) != 0))
1041 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1042 }
1043
1044 /* mullwo mullwo. */
1045 static void gen_mullwo(DisasContext *ctx)
1046 {
1047 TCGv_i32 t0 = tcg_temp_new_i32();
1048 TCGv_i32 t1 = tcg_temp_new_i32();
1049
1050 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1051 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1052 tcg_gen_muls2_i32(t0, t1, t0, t1);
1053 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1054
1055 tcg_gen_sari_i32(t0, t0, 31);
1056 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1057 tcg_gen_extu_i32_tl(cpu_ov, t0);
1058 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1059
1060 tcg_temp_free_i32(t0);
1061 tcg_temp_free_i32(t1);
1062 if (unlikely(Rc(ctx->opcode) != 0))
1063 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1064 }
1065
1066 /* mulli */
1067 static void gen_mulli(DisasContext *ctx)
1068 {
1069 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1070 SIMM(ctx->opcode));
1071 }
1072
1073 #if defined(TARGET_PPC64)
1074 /* mulhd mulhd. */
1075 static void gen_mulhd(DisasContext *ctx)
1076 {
1077 TCGv lo = tcg_temp_new();
1078 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1079 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1080 tcg_temp_free(lo);
1081 if (unlikely(Rc(ctx->opcode) != 0)) {
1082 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1083 }
1084 }
1085
1086 /* mulhdu mulhdu. */
1087 static void gen_mulhdu(DisasContext *ctx)
1088 {
1089 TCGv lo = tcg_temp_new();
1090 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1091 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1092 tcg_temp_free(lo);
1093 if (unlikely(Rc(ctx->opcode) != 0)) {
1094 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1095 }
1096 }
1097
1098 /* mulld mulld. */
1099 static void gen_mulld(DisasContext *ctx)
1100 {
1101 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1102 cpu_gpr[rB(ctx->opcode)]);
1103 if (unlikely(Rc(ctx->opcode) != 0))
1104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1105 }
1106
1107 /* mulldo mulldo. */
1108 static void gen_mulldo(DisasContext *ctx)
1109 {
1110 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1111 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1112 if (unlikely(Rc(ctx->opcode) != 0)) {
1113 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1114 }
1115 }
1116 #endif
1117
1118 /* Common subf function */
1119 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1120 TCGv arg2, bool add_ca, bool compute_ca,
1121 bool compute_ov, bool compute_rc0)
1122 {
1123 TCGv t0 = ret;
1124
1125 if (compute_ov && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
1126 t0 = tcg_temp_new();
1127 }
1128
1129 if (compute_ca) {
1130 /* dest = ~arg1 + arg2 [+ ca]. */
1131 if (NARROW_MODE(ctx)) {
1132 TCGv inv1 = tcg_temp_new();
1133 tcg_gen_not_tl(inv1, arg1);
1134 tcg_gen_ext32u_tl(t0, arg2);
1135 tcg_gen_ext32u_tl(inv1, inv1);
1136 if (add_ca) {
1137 tcg_gen_add_tl(t0, t0, cpu_ca);
1138 } else {
1139 tcg_gen_addi_tl(t0, t0, 1);
1140 }
1141 tcg_gen_add_tl(t0, t0, inv1);
1142 tcg_gen_shri_tl(cpu_ca, t0, 32);
1143 } else if (add_ca) {
1144 TCGv zero, inv1 = tcg_temp_new();
1145 tcg_gen_not_tl(inv1, arg1);
1146 zero = tcg_const_tl(0);
1147 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1148 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1149 tcg_temp_free(zero);
1150 tcg_temp_free(inv1);
1151 } else {
1152 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1153 tcg_gen_sub_tl(t0, arg2, arg1);
1154 }
1155 } else if (add_ca) {
1156 /* Since we're ignoring carry-out, we can simplify the
1157 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1158 tcg_gen_sub_tl(t0, arg2, arg1);
1159 tcg_gen_add_tl(t0, t0, cpu_ca);
1160 tcg_gen_subi_tl(t0, t0, 1);
1161 } else {
1162 tcg_gen_sub_tl(t0, arg2, arg1);
1163 }
1164
1165 if (compute_ov) {
1166 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1167 }
1168 if (unlikely(compute_rc0)) {
1169 gen_set_Rc0(ctx, t0);
1170 }
1171
1172 if (!TCGV_EQUAL(t0, ret)) {
1173 tcg_gen_mov_tl(ret, t0);
1174 tcg_temp_free(t0);
1175 }
1176 }
1177 /* Sub functions with Two operands functions */
1178 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1179 static void glue(gen_, name)(DisasContext *ctx) \
1180 { \
1181 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1182 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1183 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1184 }
1185 /* Sub functions with one operand and one immediate */
1186 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1187 add_ca, compute_ca, compute_ov) \
1188 static void glue(gen_, name)(DisasContext *ctx) \
1189 { \
1190 TCGv t0 = tcg_const_tl(const_val); \
1191 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1192 cpu_gpr[rA(ctx->opcode)], t0, \
1193 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1194 tcg_temp_free(t0); \
1195 }
1196 /* subf subf. subfo subfo. */
1197 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1198 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1199 /* subfc subfc. subfco subfco. */
1200 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1201 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1202 /* subfe subfe. subfeo subfo. */
1203 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1204 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1205 /* subfme subfme. subfmeo subfmeo. */
1206 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1207 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1208 /* subfze subfze. subfzeo subfzeo.*/
1209 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1210 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1211
1212 /* subfic */
1213 static void gen_subfic(DisasContext *ctx)
1214 {
1215 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1216 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1217 c, 0, 1, 0, 0);
1218 tcg_temp_free(c);
1219 }
1220
1221 /* neg neg. nego nego. */
1222 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1223 {
1224 TCGv zero = tcg_const_tl(0);
1225 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1226 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1227 tcg_temp_free(zero);
1228 }
1229
1230 static void gen_neg(DisasContext *ctx)
1231 {
1232 gen_op_arith_neg(ctx, 0);
1233 }
1234
1235 static void gen_nego(DisasContext *ctx)
1236 {
1237 gen_op_arith_neg(ctx, 1);
1238 }
1239
1240 /*** Integer logical ***/
1241 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1242 static void glue(gen_, name)(DisasContext *ctx) \
1243 { \
1244 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1245 cpu_gpr[rB(ctx->opcode)]); \
1246 if (unlikely(Rc(ctx->opcode) != 0)) \
1247 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1248 }
1249
1250 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1251 static void glue(gen_, name)(DisasContext *ctx) \
1252 { \
1253 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1254 if (unlikely(Rc(ctx->opcode) != 0)) \
1255 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1256 }
1257
1258 /* and & and. */
1259 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1260 /* andc & andc. */
1261 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1262
1263 /* andi. */
1264 static void gen_andi_(DisasContext *ctx)
1265 {
1266 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1267 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1268 }
1269
1270 /* andis. */
1271 static void gen_andis_(DisasContext *ctx)
1272 {
1273 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1274 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1275 }
1276
1277 /* cntlzw */
1278 static void gen_cntlzw(DisasContext *ctx)
1279 {
1280 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1281 if (unlikely(Rc(ctx->opcode) != 0))
1282 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1283 }
1284 /* eqv & eqv. */
1285 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1286 /* extsb & extsb. */
1287 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1288 /* extsh & extsh. */
1289 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1290 /* nand & nand. */
1291 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1292 /* nor & nor. */
1293 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1294
1295 /* or & or. */
1296 static void gen_or(DisasContext *ctx)
1297 {
1298 int rs, ra, rb;
1299
1300 rs = rS(ctx->opcode);
1301 ra = rA(ctx->opcode);
1302 rb = rB(ctx->opcode);
1303 /* Optimisation for mr. ri case */
1304 if (rs != ra || rs != rb) {
1305 if (rs != rb)
1306 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1307 else
1308 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1309 if (unlikely(Rc(ctx->opcode) != 0))
1310 gen_set_Rc0(ctx, cpu_gpr[ra]);
1311 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1312 gen_set_Rc0(ctx, cpu_gpr[rs]);
1313 #if defined(TARGET_PPC64)
1314 } else {
1315 int prio = 0;
1316
1317 switch (rs) {
1318 case 1:
1319 /* Set process priority to low */
1320 prio = 2;
1321 break;
1322 case 6:
1323 /* Set process priority to medium-low */
1324 prio = 3;
1325 break;
1326 case 2:
1327 /* Set process priority to normal */
1328 prio = 4;
1329 break;
1330 #if !defined(CONFIG_USER_ONLY)
1331 case 31:
1332 if (ctx->mem_idx > 0) {
1333 /* Set process priority to very low */
1334 prio = 1;
1335 }
1336 break;
1337 case 5:
1338 if (ctx->mem_idx > 0) {
1339 /* Set process priority to medium-hight */
1340 prio = 5;
1341 }
1342 break;
1343 case 3:
1344 if (ctx->mem_idx > 0) {
1345 /* Set process priority to high */
1346 prio = 6;
1347 }
1348 break;
1349 case 7:
1350 if (ctx->mem_idx > 1) {
1351 /* Set process priority to very high */
1352 prio = 7;
1353 }
1354 break;
1355 #endif
1356 default:
1357 /* nop */
1358 break;
1359 }
1360 if (prio) {
1361 TCGv t0 = tcg_temp_new();
1362 gen_load_spr(t0, SPR_PPR);
1363 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1364 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1365 gen_store_spr(SPR_PPR, t0);
1366 tcg_temp_free(t0);
1367 }
1368 #endif
1369 }
1370 }
1371 /* orc & orc. */
1372 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1373
1374 /* xor & xor. */
1375 static void gen_xor(DisasContext *ctx)
1376 {
1377 /* Optimisation for "set to zero" case */
1378 if (rS(ctx->opcode) != rB(ctx->opcode))
1379 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1380 else
1381 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1382 if (unlikely(Rc(ctx->opcode) != 0))
1383 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1384 }
1385
1386 /* ori */
1387 static void gen_ori(DisasContext *ctx)
1388 {
1389 target_ulong uimm = UIMM(ctx->opcode);
1390
1391 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1392 /* NOP */
1393 /* XXX: should handle special NOPs for POWER series */
1394 return;
1395 }
1396 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1397 }
1398
1399 /* oris */
1400 static void gen_oris(DisasContext *ctx)
1401 {
1402 target_ulong uimm = UIMM(ctx->opcode);
1403
1404 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1405 /* NOP */
1406 return;
1407 }
1408 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1409 }
1410
1411 /* xori */
1412 static void gen_xori(DisasContext *ctx)
1413 {
1414 target_ulong uimm = UIMM(ctx->opcode);
1415
1416 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1417 /* NOP */
1418 return;
1419 }
1420 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1421 }
1422
1423 /* xoris */
1424 static void gen_xoris(DisasContext *ctx)
1425 {
1426 target_ulong uimm = UIMM(ctx->opcode);
1427
1428 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1429 /* NOP */
1430 return;
1431 }
1432 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1433 }
1434
1435 /* popcntb : PowerPC 2.03 specification */
1436 static void gen_popcntb(DisasContext *ctx)
1437 {
1438 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1439 }
1440
1441 static void gen_popcntw(DisasContext *ctx)
1442 {
1443 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1444 }
1445
1446 #if defined(TARGET_PPC64)
1447 /* popcntd: PowerPC 2.06 specification */
1448 static void gen_popcntd(DisasContext *ctx)
1449 {
1450 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1451 }
1452 #endif
1453
1454 #if defined(TARGET_PPC64)
1455 /* extsw & extsw. */
1456 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1457
1458 /* cntlzd */
1459 static void gen_cntlzd(DisasContext *ctx)
1460 {
1461 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1462 if (unlikely(Rc(ctx->opcode) != 0))
1463 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1464 }
1465 #endif
1466
1467 /*** Integer rotate ***/
1468
1469 /* rlwimi & rlwimi. */
1470 static void gen_rlwimi(DisasContext *ctx)
1471 {
1472 uint32_t mb, me, sh;
1473
1474 mb = MB(ctx->opcode);
1475 me = ME(ctx->opcode);
1476 sh = SH(ctx->opcode);
1477 if (likely(sh == 0 && mb == 0 && me == 31)) {
1478 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1479 } else {
1480 target_ulong mask;
1481 TCGv t1;
1482 TCGv t0 = tcg_temp_new();
1483 #if defined(TARGET_PPC64)
1484 TCGv_i32 t2 = tcg_temp_new_i32();
1485 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1486 tcg_gen_rotli_i32(t2, t2, sh);
1487 tcg_gen_extu_i32_i64(t0, t2);
1488 tcg_temp_free_i32(t2);
1489 #else
1490 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1491 #endif
1492 #if defined(TARGET_PPC64)
1493 mb += 32;
1494 me += 32;
1495 #endif
1496 mask = MASK(mb, me);
1497 t1 = tcg_temp_new();
1498 tcg_gen_andi_tl(t0, t0, mask);
1499 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1500 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1501 tcg_temp_free(t0);
1502 tcg_temp_free(t1);
1503 }
1504 if (unlikely(Rc(ctx->opcode) != 0))
1505 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1506 }
1507
1508 /* rlwinm & rlwinm. */
1509 static void gen_rlwinm(DisasContext *ctx)
1510 {
1511 uint32_t mb, me, sh;
1512
1513 sh = SH(ctx->opcode);
1514 mb = MB(ctx->opcode);
1515 me = ME(ctx->opcode);
1516
1517 if (likely(mb == 0 && me == (31 - sh))) {
1518 if (likely(sh == 0)) {
1519 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1520 } else {
1521 TCGv t0 = tcg_temp_new();
1522 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1523 tcg_gen_shli_tl(t0, t0, sh);
1524 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1525 tcg_temp_free(t0);
1526 }
1527 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1528 TCGv t0 = tcg_temp_new();
1529 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1530 tcg_gen_shri_tl(t0, t0, mb);
1531 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1532 tcg_temp_free(t0);
1533 } else {
1534 TCGv t0 = tcg_temp_new();
1535 #if defined(TARGET_PPC64)
1536 TCGv_i32 t1 = tcg_temp_new_i32();
1537 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1538 tcg_gen_rotli_i32(t1, t1, sh);
1539 tcg_gen_extu_i32_i64(t0, t1);
1540 tcg_temp_free_i32(t1);
1541 #else
1542 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1543 #endif
1544 #if defined(TARGET_PPC64)
1545 mb += 32;
1546 me += 32;
1547 #endif
1548 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1549 tcg_temp_free(t0);
1550 }
1551 if (unlikely(Rc(ctx->opcode) != 0))
1552 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1553 }
1554
1555 /* rlwnm & rlwnm. */
1556 static void gen_rlwnm(DisasContext *ctx)
1557 {
1558 uint32_t mb, me;
1559 TCGv t0;
1560 #if defined(TARGET_PPC64)
1561 TCGv_i32 t1, t2;
1562 #endif
1563
1564 mb = MB(ctx->opcode);
1565 me = ME(ctx->opcode);
1566 t0 = tcg_temp_new();
1567 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1568 #if defined(TARGET_PPC64)
1569 t1 = tcg_temp_new_i32();
1570 t2 = tcg_temp_new_i32();
1571 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1572 tcg_gen_trunc_i64_i32(t2, t0);
1573 tcg_gen_rotl_i32(t1, t1, t2);
1574 tcg_gen_extu_i32_i64(t0, t1);
1575 tcg_temp_free_i32(t1);
1576 tcg_temp_free_i32(t2);
1577 #else
1578 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1579 #endif
1580 if (unlikely(mb != 0 || me != 31)) {
1581 #if defined(TARGET_PPC64)
1582 mb += 32;
1583 me += 32;
1584 #endif
1585 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1586 } else {
1587 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1588 }
1589 tcg_temp_free(t0);
1590 if (unlikely(Rc(ctx->opcode) != 0))
1591 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1592 }
1593
1594 #if defined(TARGET_PPC64)
1595 #define GEN_PPC64_R2(name, opc1, opc2) \
1596 static void glue(gen_, name##0)(DisasContext *ctx) \
1597 { \
1598 gen_##name(ctx, 0); \
1599 } \
1600 \
1601 static void glue(gen_, name##1)(DisasContext *ctx) \
1602 { \
1603 gen_##name(ctx, 1); \
1604 }
1605 #define GEN_PPC64_R4(name, opc1, opc2) \
1606 static void glue(gen_, name##0)(DisasContext *ctx) \
1607 { \
1608 gen_##name(ctx, 0, 0); \
1609 } \
1610 \
1611 static void glue(gen_, name##1)(DisasContext *ctx) \
1612 { \
1613 gen_##name(ctx, 0, 1); \
1614 } \
1615 \
1616 static void glue(gen_, name##2)(DisasContext *ctx) \
1617 { \
1618 gen_##name(ctx, 1, 0); \
1619 } \
1620 \
1621 static void glue(gen_, name##3)(DisasContext *ctx) \
1622 { \
1623 gen_##name(ctx, 1, 1); \
1624 }
1625
1626 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1627 uint32_t sh)
1628 {
1629 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1630 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1631 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1632 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1633 } else {
1634 TCGv t0 = tcg_temp_new();
1635 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1636 if (likely(mb == 0 && me == 63)) {
1637 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1638 } else {
1639 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1640 }
1641 tcg_temp_free(t0);
1642 }
1643 if (unlikely(Rc(ctx->opcode) != 0))
1644 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1645 }
1646 /* rldicl - rldicl. */
1647 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1648 {
1649 uint32_t sh, mb;
1650
1651 sh = SH(ctx->opcode) | (shn << 5);
1652 mb = MB(ctx->opcode) | (mbn << 5);
1653 gen_rldinm(ctx, mb, 63, sh);
1654 }
1655 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1656 /* rldicr - rldicr. */
1657 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1658 {
1659 uint32_t sh, me;
1660
1661 sh = SH(ctx->opcode) | (shn << 5);
1662 me = MB(ctx->opcode) | (men << 5);
1663 gen_rldinm(ctx, 0, me, sh);
1664 }
1665 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1666 /* rldic - rldic. */
1667 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1668 {
1669 uint32_t sh, mb;
1670
1671 sh = SH(ctx->opcode) | (shn << 5);
1672 mb = MB(ctx->opcode) | (mbn << 5);
1673 gen_rldinm(ctx, mb, 63 - sh, sh);
1674 }
1675 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1676
1677 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1678 {
1679 TCGv t0;
1680
1681 mb = MB(ctx->opcode);
1682 me = ME(ctx->opcode);
1683 t0 = tcg_temp_new();
1684 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1685 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1686 if (unlikely(mb != 0 || me != 63)) {
1687 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1688 } else {
1689 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1690 }
1691 tcg_temp_free(t0);
1692 if (unlikely(Rc(ctx->opcode) != 0))
1693 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1694 }
1695
1696 /* rldcl - rldcl. */
1697 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1698 {
1699 uint32_t mb;
1700
1701 mb = MB(ctx->opcode) | (mbn << 5);
1702 gen_rldnm(ctx, mb, 63);
1703 }
1704 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1705 /* rldcr - rldcr. */
1706 static inline void gen_rldcr(DisasContext *ctx, int men)
1707 {
1708 uint32_t me;
1709
1710 me = MB(ctx->opcode) | (men << 5);
1711 gen_rldnm(ctx, 0, me);
1712 }
1713 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1714 /* rldimi - rldimi. */
1715 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1716 {
1717 uint32_t sh, mb, me;
1718
1719 sh = SH(ctx->opcode) | (shn << 5);
1720 mb = MB(ctx->opcode) | (mbn << 5);
1721 me = 63 - sh;
1722 if (unlikely(sh == 0 && mb == 0)) {
1723 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1724 } else {
1725 TCGv t0, t1;
1726 target_ulong mask;
1727
1728 t0 = tcg_temp_new();
1729 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1730 t1 = tcg_temp_new();
1731 mask = MASK(mb, me);
1732 tcg_gen_andi_tl(t0, t0, mask);
1733 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1734 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1735 tcg_temp_free(t0);
1736 tcg_temp_free(t1);
1737 }
1738 if (unlikely(Rc(ctx->opcode) != 0))
1739 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1740 }
1741 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1742 #endif
1743
1744 /*** Integer shift ***/
1745
1746 /* slw & slw. */
1747 static void gen_slw(DisasContext *ctx)
1748 {
1749 TCGv t0, t1;
1750
1751 t0 = tcg_temp_new();
1752 /* AND rS with a mask that is 0 when rB >= 0x20 */
1753 #if defined(TARGET_PPC64)
1754 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1755 tcg_gen_sari_tl(t0, t0, 0x3f);
1756 #else
1757 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1758 tcg_gen_sari_tl(t0, t0, 0x1f);
1759 #endif
1760 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1761 t1 = tcg_temp_new();
1762 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1763 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1764 tcg_temp_free(t1);
1765 tcg_temp_free(t0);
1766 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1767 if (unlikely(Rc(ctx->opcode) != 0))
1768 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1769 }
1770
1771 /* sraw & sraw. */
1772 static void gen_sraw(DisasContext *ctx)
1773 {
1774 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1775 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1776 if (unlikely(Rc(ctx->opcode) != 0))
1777 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1778 }
1779
1780 /* srawi & srawi. */
1781 static void gen_srawi(DisasContext *ctx)
1782 {
1783 int sh = SH(ctx->opcode);
1784 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1785 TCGv src = cpu_gpr[rS(ctx->opcode)];
1786 if (sh == 0) {
1787 tcg_gen_mov_tl(dst, src);
1788 tcg_gen_movi_tl(cpu_ca, 0);
1789 } else {
1790 TCGv t0;
1791 tcg_gen_ext32s_tl(dst, src);
1792 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1793 t0 = tcg_temp_new();
1794 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1795 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1796 tcg_temp_free(t0);
1797 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1798 tcg_gen_sari_tl(dst, dst, sh);
1799 }
1800 if (unlikely(Rc(ctx->opcode) != 0)) {
1801 gen_set_Rc0(ctx, dst);
1802 }
1803 }
1804
1805 /* srw & srw. */
1806 static void gen_srw(DisasContext *ctx)
1807 {
1808 TCGv t0, t1;
1809
1810 t0 = tcg_temp_new();
1811 /* AND rS with a mask that is 0 when rB >= 0x20 */
1812 #if defined(TARGET_PPC64)
1813 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1814 tcg_gen_sari_tl(t0, t0, 0x3f);
1815 #else
1816 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1817 tcg_gen_sari_tl(t0, t0, 0x1f);
1818 #endif
1819 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1820 tcg_gen_ext32u_tl(t0, t0);
1821 t1 = tcg_temp_new();
1822 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1823 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1824 tcg_temp_free(t1);
1825 tcg_temp_free(t0);
1826 if (unlikely(Rc(ctx->opcode) != 0))
1827 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1828 }
1829
1830 #if defined(TARGET_PPC64)
1831 /* sld & sld. */
1832 static void gen_sld(DisasContext *ctx)
1833 {
1834 TCGv t0, t1;
1835
1836 t0 = tcg_temp_new();
1837 /* AND rS with a mask that is 0 when rB >= 0x40 */
1838 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1839 tcg_gen_sari_tl(t0, t0, 0x3f);
1840 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1841 t1 = tcg_temp_new();
1842 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1843 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1844 tcg_temp_free(t1);
1845 tcg_temp_free(t0);
1846 if (unlikely(Rc(ctx->opcode) != 0))
1847 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1848 }
1849
1850 /* srad & srad. */
1851 static void gen_srad(DisasContext *ctx)
1852 {
1853 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1854 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1855 if (unlikely(Rc(ctx->opcode) != 0))
1856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1857 }
1858 /* sradi & sradi. */
1859 static inline void gen_sradi(DisasContext *ctx, int n)
1860 {
1861 int sh = SH(ctx->opcode) + (n << 5);
1862 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1863 TCGv src = cpu_gpr[rS(ctx->opcode)];
1864 if (sh == 0) {
1865 tcg_gen_mov_tl(dst, src);
1866 tcg_gen_movi_tl(cpu_ca, 0);
1867 } else {
1868 TCGv t0;
1869 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1870 t0 = tcg_temp_new();
1871 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1872 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1873 tcg_temp_free(t0);
1874 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1875 tcg_gen_sari_tl(dst, src, sh);
1876 }
1877 if (unlikely(Rc(ctx->opcode) != 0)) {
1878 gen_set_Rc0(ctx, dst);
1879 }
1880 }
1881
1882 static void gen_sradi0(DisasContext *ctx)
1883 {
1884 gen_sradi(ctx, 0);
1885 }
1886
1887 static void gen_sradi1(DisasContext *ctx)
1888 {
1889 gen_sradi(ctx, 1);
1890 }
1891
1892 /* srd & srd. */
1893 static void gen_srd(DisasContext *ctx)
1894 {
1895 TCGv t0, t1;
1896
1897 t0 = tcg_temp_new();
1898 /* AND rS with a mask that is 0 when rB >= 0x40 */
1899 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1900 tcg_gen_sari_tl(t0, t0, 0x3f);
1901 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1902 t1 = tcg_temp_new();
1903 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1904 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1905 tcg_temp_free(t1);
1906 tcg_temp_free(t0);
1907 if (unlikely(Rc(ctx->opcode) != 0))
1908 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1909 }
1910 #endif
1911
1912 /*** Floating-Point arithmetic ***/
1913 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1914 static void gen_f##name(DisasContext *ctx) \
1915 { \
1916 if (unlikely(!ctx->fpu_enabled)) { \
1917 gen_exception(ctx, POWERPC_EXCP_FPU); \
1918 return; \
1919 } \
1920 /* NIP cannot be restored if the memory exception comes from an helper */ \
1921 gen_update_nip(ctx, ctx->nip - 4); \
1922 gen_reset_fpstatus(); \
1923 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1924 cpu_fpr[rA(ctx->opcode)], \
1925 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1926 if (isfloat) { \
1927 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1928 cpu_fpr[rD(ctx->opcode)]); \
1929 } \
1930 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1931 Rc(ctx->opcode) != 0); \
1932 }
1933
1934 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1935 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1936 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1937
1938 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1939 static void gen_f##name(DisasContext *ctx) \
1940 { \
1941 if (unlikely(!ctx->fpu_enabled)) { \
1942 gen_exception(ctx, POWERPC_EXCP_FPU); \
1943 return; \
1944 } \
1945 /* NIP cannot be restored if the memory exception comes from an helper */ \
1946 gen_update_nip(ctx, ctx->nip - 4); \
1947 gen_reset_fpstatus(); \
1948 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1949 cpu_fpr[rA(ctx->opcode)], \
1950 cpu_fpr[rB(ctx->opcode)]); \
1951 if (isfloat) { \
1952 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1953 cpu_fpr[rD(ctx->opcode)]); \
1954 } \
1955 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1956 set_fprf, Rc(ctx->opcode) != 0); \
1957 }
1958 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1959 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1960 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1961
1962 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1963 static void gen_f##name(DisasContext *ctx) \
1964 { \
1965 if (unlikely(!ctx->fpu_enabled)) { \
1966 gen_exception(ctx, POWERPC_EXCP_FPU); \
1967 return; \
1968 } \
1969 /* NIP cannot be restored if the memory exception comes from an helper */ \
1970 gen_update_nip(ctx, ctx->nip - 4); \
1971 gen_reset_fpstatus(); \
1972 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1973 cpu_fpr[rA(ctx->opcode)], \
1974 cpu_fpr[rC(ctx->opcode)]); \
1975 if (isfloat) { \
1976 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1977 cpu_fpr[rD(ctx->opcode)]); \
1978 } \
1979 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1980 set_fprf, Rc(ctx->opcode) != 0); \
1981 }
1982 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1983 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1984 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1985
1986 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1987 static void gen_f##name(DisasContext *ctx) \
1988 { \
1989 if (unlikely(!ctx->fpu_enabled)) { \
1990 gen_exception(ctx, POWERPC_EXCP_FPU); \
1991 return; \
1992 } \
1993 /* NIP cannot be restored if the memory exception comes from an helper */ \
1994 gen_update_nip(ctx, ctx->nip - 4); \
1995 gen_reset_fpstatus(); \
1996 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1997 cpu_fpr[rB(ctx->opcode)]); \
1998 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1999 set_fprf, Rc(ctx->opcode) != 0); \
2000 }
2001
2002 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2003 static void gen_f##name(DisasContext *ctx) \
2004 { \
2005 if (unlikely(!ctx->fpu_enabled)) { \
2006 gen_exception(ctx, POWERPC_EXCP_FPU); \
2007 return; \
2008 } \
2009 /* NIP cannot be restored if the memory exception comes from an helper */ \
2010 gen_update_nip(ctx, ctx->nip - 4); \
2011 gen_reset_fpstatus(); \
2012 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2013 cpu_fpr[rB(ctx->opcode)]); \
2014 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2015 set_fprf, Rc(ctx->opcode) != 0); \
2016 }
2017
2018 /* fadd - fadds */
2019 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2020 /* fdiv - fdivs */
2021 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2022 /* fmul - fmuls */
2023 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2024
2025 /* fre */
2026 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2027
2028 /* fres */
2029 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2030
2031 /* frsqrte */
2032 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2033
2034 /* frsqrtes */
2035 static void gen_frsqrtes(DisasContext *ctx)
2036 {
2037 if (unlikely(!ctx->fpu_enabled)) {
2038 gen_exception(ctx, POWERPC_EXCP_FPU);
2039 return;
2040 }
2041 /* NIP cannot be restored if the memory exception comes from an helper */
2042 gen_update_nip(ctx, ctx->nip - 4);
2043 gen_reset_fpstatus();
2044 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2045 cpu_fpr[rB(ctx->opcode)]);
2046 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2047 cpu_fpr[rD(ctx->opcode)]);
2048 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2049 }
2050
2051 /* fsel */
2052 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2053 /* fsub - fsubs */
2054 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2055 /* Optional: */
2056
2057 /* fsqrt */
2058 static void gen_fsqrt(DisasContext *ctx)
2059 {
2060 if (unlikely(!ctx->fpu_enabled)) {
2061 gen_exception(ctx, POWERPC_EXCP_FPU);
2062 return;
2063 }
2064 /* NIP cannot be restored if the memory exception comes from an helper */
2065 gen_update_nip(ctx, ctx->nip - 4);
2066 gen_reset_fpstatus();
2067 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2068 cpu_fpr[rB(ctx->opcode)]);
2069 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2070 }
2071
2072 static void gen_fsqrts(DisasContext *ctx)
2073 {
2074 if (unlikely(!ctx->fpu_enabled)) {
2075 gen_exception(ctx, POWERPC_EXCP_FPU);
2076 return;
2077 }
2078 /* NIP cannot be restored if the memory exception comes from an helper */
2079 gen_update_nip(ctx, ctx->nip - 4);
2080 gen_reset_fpstatus();
2081 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2082 cpu_fpr[rB(ctx->opcode)]);
2083 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2084 cpu_fpr[rD(ctx->opcode)]);
2085 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2086 }
2087
2088 /*** Floating-Point multiply-and-add ***/
2089 /* fmadd - fmadds */
2090 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2091 /* fmsub - fmsubs */
2092 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2093 /* fnmadd - fnmadds */
2094 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2095 /* fnmsub - fnmsubs */
2096 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2097
2098 /*** Floating-Point round & convert ***/
2099 /* fctiw */
2100 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2101 /* fctiwz */
2102 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2103 /* frsp */
2104 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2105 #if defined(TARGET_PPC64)
2106 /* fcfid */
2107 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2108 /* fctid */
2109 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2110 /* fctidz */
2111 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2112 #endif
2113
2114 /* frin */
2115 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2116 /* friz */
2117 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2118 /* frip */
2119 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2120 /* frim */
2121 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2122
2123 /*** Floating-Point compare ***/
2124
2125 /* fcmpo */
2126 static void gen_fcmpo(DisasContext *ctx)
2127 {
2128 TCGv_i32 crf;
2129 if (unlikely(!ctx->fpu_enabled)) {
2130 gen_exception(ctx, POWERPC_EXCP_FPU);
2131 return;
2132 }
2133 /* NIP cannot be restored if the memory exception comes from an helper */
2134 gen_update_nip(ctx, ctx->nip - 4);
2135 gen_reset_fpstatus();
2136 crf = tcg_const_i32(crfD(ctx->opcode));
2137 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2138 cpu_fpr[rB(ctx->opcode)], crf);
2139 tcg_temp_free_i32(crf);
2140 gen_helper_float_check_status(cpu_env);
2141 }
2142
2143 /* fcmpu */
2144 static void gen_fcmpu(DisasContext *ctx)
2145 {
2146 TCGv_i32 crf;
2147 if (unlikely(!ctx->fpu_enabled)) {
2148 gen_exception(ctx, POWERPC_EXCP_FPU);
2149 return;
2150 }
2151 /* NIP cannot be restored if the memory exception comes from an helper */
2152 gen_update_nip(ctx, ctx->nip - 4);
2153 gen_reset_fpstatus();
2154 crf = tcg_const_i32(crfD(ctx->opcode));
2155 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2156 cpu_fpr[rB(ctx->opcode)], crf);
2157 tcg_temp_free_i32(crf);
2158 gen_helper_float_check_status(cpu_env);
2159 }
2160
2161 /*** Floating-point move ***/
2162 /* fabs */
2163 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2164 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2165
2166 /* fmr - fmr. */
2167 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2168 static void gen_fmr(DisasContext *ctx)
2169 {
2170 if (unlikely(!ctx->fpu_enabled)) {
2171 gen_exception(ctx, POWERPC_EXCP_FPU);
2172 return;
2173 }
2174 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2175 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2176 }
2177
2178 /* fnabs */
2179 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2180 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2181 /* fneg */
2182 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2183 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2184
2185 /*** Floating-Point status & ctrl register ***/
2186
2187 /* mcrfs */
2188 static void gen_mcrfs(DisasContext *ctx)
2189 {
2190 TCGv tmp = tcg_temp_new();
2191 int bfa;
2192
2193 if (unlikely(!ctx->fpu_enabled)) {
2194 gen_exception(ctx, POWERPC_EXCP_FPU);
2195 return;
2196 }
2197 bfa = 4 * (7 - crfS(ctx->opcode));
2198 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2199 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2200 tcg_temp_free(tmp);
2201 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2202 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2203 }
2204
2205 /* mffs */
2206 static void gen_mffs(DisasContext *ctx)
2207 {
2208 if (unlikely(!ctx->fpu_enabled)) {
2209 gen_exception(ctx, POWERPC_EXCP_FPU);
2210 return;
2211 }
2212 gen_reset_fpstatus();
2213 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2214 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2215 }
2216
2217 /* mtfsb0 */
2218 static void gen_mtfsb0(DisasContext *ctx)
2219 {
2220 uint8_t crb;
2221
2222 if (unlikely(!ctx->fpu_enabled)) {
2223 gen_exception(ctx, POWERPC_EXCP_FPU);
2224 return;
2225 }
2226 crb = 31 - crbD(ctx->opcode);
2227 gen_reset_fpstatus();
2228 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2229 TCGv_i32 t0;
2230 /* NIP cannot be restored if the memory exception comes from an helper */
2231 gen_update_nip(ctx, ctx->nip - 4);
2232 t0 = tcg_const_i32(crb);
2233 gen_helper_fpscr_clrbit(cpu_env, t0);
2234 tcg_temp_free_i32(t0);
2235 }
2236 if (unlikely(Rc(ctx->opcode) != 0)) {
2237 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2238 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2239 }
2240 }
2241
2242 /* mtfsb1 */
2243 static void gen_mtfsb1(DisasContext *ctx)
2244 {
2245 uint8_t crb;
2246
2247 if (unlikely(!ctx->fpu_enabled)) {
2248 gen_exception(ctx, POWERPC_EXCP_FPU);
2249 return;
2250 }
2251 crb = 31 - crbD(ctx->opcode);
2252 gen_reset_fpstatus();
2253 /* XXX: we pretend we can only do IEEE floating-point computations */
2254 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2255 TCGv_i32 t0;
2256 /* NIP cannot be restored if the memory exception comes from an helper */
2257 gen_update_nip(ctx, ctx->nip - 4);
2258 t0 = tcg_const_i32(crb);
2259 gen_helper_fpscr_setbit(cpu_env, t0);
2260 tcg_temp_free_i32(t0);
2261 }
2262 if (unlikely(Rc(ctx->opcode) != 0)) {
2263 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2264 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2265 }
2266 /* We can raise a differed exception */
2267 gen_helper_float_check_status(cpu_env);
2268 }
2269
2270 /* mtfsf */
2271 static void gen_mtfsf(DisasContext *ctx)
2272 {
2273 TCGv_i32 t0;
2274 int L = ctx->opcode & 0x02000000;
2275
2276 if (unlikely(!ctx->fpu_enabled)) {
2277 gen_exception(ctx, POWERPC_EXCP_FPU);
2278 return;
2279 }
2280 /* NIP cannot be restored if the memory exception comes from an helper */
2281 gen_update_nip(ctx, ctx->nip - 4);
2282 gen_reset_fpstatus();
2283 if (L)
2284 t0 = tcg_const_i32(0xff);
2285 else
2286 t0 = tcg_const_i32(FM(ctx->opcode));
2287 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2288 tcg_temp_free_i32(t0);
2289 if (unlikely(Rc(ctx->opcode) != 0)) {
2290 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2291 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2292 }
2293 /* We can raise a differed exception */
2294 gen_helper_float_check_status(cpu_env);
2295 }
2296
2297 /* mtfsfi */
2298 static void gen_mtfsfi(DisasContext *ctx)
2299 {
2300 int bf, sh;
2301 TCGv_i64 t0;
2302 TCGv_i32 t1;
2303
2304 if (unlikely(!ctx->fpu_enabled)) {
2305 gen_exception(ctx, POWERPC_EXCP_FPU);
2306 return;
2307 }
2308 bf = crbD(ctx->opcode) >> 2;
2309 sh = 7 - bf;
2310 /* NIP cannot be restored if the memory exception comes from an helper */
2311 gen_update_nip(ctx, ctx->nip - 4);
2312 gen_reset_fpstatus();
2313 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2314 t1 = tcg_const_i32(1 << sh);
2315 gen_helper_store_fpscr(cpu_env, t0, t1);
2316 tcg_temp_free_i64(t0);
2317 tcg_temp_free_i32(t1);
2318 if (unlikely(Rc(ctx->opcode) != 0)) {
2319 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2320 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2321 }
2322 /* We can raise a differed exception */
2323 gen_helper_float_check_status(cpu_env);
2324 }
2325
2326 /*** Addressing modes ***/
2327 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2328 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2329 target_long maskl)
2330 {
2331 target_long simm = SIMM(ctx->opcode);
2332
2333 simm &= ~maskl;
2334 if (rA(ctx->opcode) == 0) {
2335 if (NARROW_MODE(ctx)) {
2336 simm = (uint32_t)simm;
2337 }
2338 tcg_gen_movi_tl(EA, simm);
2339 } else if (likely(simm != 0)) {
2340 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2341 if (NARROW_MODE(ctx)) {
2342 tcg_gen_ext32u_tl(EA, EA);
2343 }
2344 } else {
2345 if (NARROW_MODE(ctx)) {
2346 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2347 } else {
2348 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2349 }
2350 }
2351 }
2352
2353 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2354 {
2355 if (rA(ctx->opcode) == 0) {
2356 if (NARROW_MODE(ctx)) {
2357 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2358 } else {
2359 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2360 }
2361 } else {
2362 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2363 if (NARROW_MODE(ctx)) {
2364 tcg_gen_ext32u_tl(EA, EA);
2365 }
2366 }
2367 }
2368
2369 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2370 {
2371 if (rA(ctx->opcode) == 0) {
2372 tcg_gen_movi_tl(EA, 0);
2373 } else if (NARROW_MODE(ctx)) {
2374 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2375 } else {
2376 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2377 }
2378 }
2379
2380 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2381 target_long val)
2382 {
2383 tcg_gen_addi_tl(ret, arg1, val);
2384 if (NARROW_MODE(ctx)) {
2385 tcg_gen_ext32u_tl(ret, ret);
2386 }
2387 }
2388
2389 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2390 {
2391 int l1 = gen_new_label();
2392 TCGv t0 = tcg_temp_new();
2393 TCGv_i32 t1, t2;
2394 /* NIP cannot be restored if the memory exception comes from an helper */
2395 gen_update_nip(ctx, ctx->nip - 4);
2396 tcg_gen_andi_tl(t0, EA, mask);
2397 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2398 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2399 t2 = tcg_const_i32(0);
2400 gen_helper_raise_exception_err(cpu_env, t1, t2);
2401 tcg_temp_free_i32(t1);
2402 tcg_temp_free_i32(t2);
2403 gen_set_label(l1);
2404 tcg_temp_free(t0);
2405 }
2406
2407 /*** Integer load ***/
2408 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2409 {
2410 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2411 }
2412
2413 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2414 {
2415 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2416 }
2417
2418 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2419 {
2420 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2421 if (unlikely(ctx->le_mode)) {
2422 tcg_gen_bswap16_tl(arg1, arg1);
2423 }
2424 }
2425
2426 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2427 {
2428 if (unlikely(ctx->le_mode)) {
2429 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2430 tcg_gen_bswap16_tl(arg1, arg1);
2431 tcg_gen_ext16s_tl(arg1, arg1);
2432 } else {
2433 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2434 }
2435 }
2436
2437 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2438 {
2439 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2440 if (unlikely(ctx->le_mode)) {
2441 tcg_gen_bswap32_tl(arg1, arg1);
2442 }
2443 }
2444
2445 #if defined(TARGET_PPC64)
2446 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2447 {
2448 if (unlikely(ctx->le_mode)) {
2449 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2450 tcg_gen_bswap32_tl(arg1, arg1);
2451 tcg_gen_ext32s_tl(arg1, arg1);
2452 } else
2453 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2454 }
2455 #endif
2456
2457 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2458 {
2459 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2460 if (unlikely(ctx->le_mode)) {
2461 tcg_gen_bswap64_i64(arg1, arg1);
2462 }
2463 }
2464
2465 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2466 {
2467 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2468 }
2469
2470 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2471 {
2472 if (unlikely(ctx->le_mode)) {
2473 TCGv t0 = tcg_temp_new();
2474 tcg_gen_ext16u_tl(t0, arg1);
2475 tcg_gen_bswap16_tl(t0, t0);
2476 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2477 tcg_temp_free(t0);
2478 } else {
2479 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2480 }
2481 }
2482
2483 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2484 {
2485 if (unlikely(ctx->le_mode)) {
2486 TCGv t0 = tcg_temp_new();
2487 tcg_gen_ext32u_tl(t0, arg1);
2488 tcg_gen_bswap32_tl(t0, t0);
2489 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2490 tcg_temp_free(t0);
2491 } else {
2492 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2493 }
2494 }
2495
2496 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2497 {
2498 if (unlikely(ctx->le_mode)) {
2499 TCGv_i64 t0 = tcg_temp_new_i64();
2500 tcg_gen_bswap64_i64(t0, arg1);
2501 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2502 tcg_temp_free_i64(t0);
2503 } else
2504 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2505 }
2506
2507 #define GEN_LD(name, ldop, opc, type) \
2508 static void glue(gen_, name)(DisasContext *ctx) \
2509 { \
2510 TCGv EA; \
2511 gen_set_access_type(ctx, ACCESS_INT); \
2512 EA = tcg_temp_new(); \
2513 gen_addr_imm_index(ctx, EA, 0); \
2514 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2515 tcg_temp_free(EA); \
2516 }
2517
2518 #define GEN_LDU(name, ldop, opc, type) \
2519 static void glue(gen_, name##u)(DisasContext *ctx) \
2520 { \
2521 TCGv EA; \
2522 if (unlikely(rA(ctx->opcode) == 0 || \
2523 rA(ctx->opcode) == rD(ctx->opcode))) { \
2524 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2525 return; \
2526 } \
2527 gen_set_access_type(ctx, ACCESS_INT); \
2528 EA = tcg_temp_new(); \
2529 if (type == PPC_64B) \
2530 gen_addr_imm_index(ctx, EA, 0x03); \
2531 else \
2532 gen_addr_imm_index(ctx, EA, 0); \
2533 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2534 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2535 tcg_temp_free(EA); \
2536 }
2537
2538 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2539 static void glue(gen_, name##ux)(DisasContext *ctx) \
2540 { \
2541 TCGv EA; \
2542 if (unlikely(rA(ctx->opcode) == 0 || \
2543 rA(ctx->opcode) == rD(ctx->opcode))) { \
2544 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2545 return; \
2546 } \
2547 gen_set_access_type(ctx, ACCESS_INT); \
2548 EA = tcg_temp_new(); \
2549 gen_addr_reg_index(ctx, EA); \
2550 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2551 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2552 tcg_temp_free(EA); \
2553 }
2554
2555 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2556 static void glue(gen_, name##x)(DisasContext *ctx) \
2557 { \
2558 TCGv EA; \
2559 gen_set_access_type(ctx, ACCESS_INT); \
2560 EA = tcg_temp_new(); \
2561 gen_addr_reg_index(ctx, EA); \
2562 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2563 tcg_temp_free(EA); \
2564 }
2565 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2566 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2567
2568 #define GEN_LDS(name, ldop, op, type) \
2569 GEN_LD(name, ldop, op | 0x20, type); \
2570 GEN_LDU(name, ldop, op | 0x21, type); \
2571 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2572 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2573
2574 /* lbz lbzu lbzux lbzx */
2575 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2576 /* lha lhau lhaux lhax */
2577 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2578 /* lhz lhzu lhzux lhzx */
2579 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2580 /* lwz lwzu lwzux lwzx */
2581 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2582 #if defined(TARGET_PPC64)
2583 /* lwaux */
2584 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2585 /* lwax */
2586 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2587 /* ldux */
2588 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2589 /* ldx */
2590 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2591
2592 static void gen_ld(DisasContext *ctx)
2593 {
2594 TCGv EA;
2595 if (Rc(ctx->opcode)) {
2596 if (unlikely(rA(ctx->opcode) == 0 ||
2597 rA(ctx->opcode) == rD(ctx->opcode))) {
2598 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2599 return;
2600 }
2601 }
2602 gen_set_access_type(ctx, ACCESS_INT);
2603 EA = tcg_temp_new();
2604 gen_addr_imm_index(ctx, EA, 0x03);
2605 if (ctx->opcode & 0x02) {
2606 /* lwa (lwau is undefined) */
2607 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2608 } else {
2609 /* ld - ldu */
2610 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2611 }
2612 if (Rc(ctx->opcode))
2613 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2614 tcg_temp_free(EA);
2615 }
2616
2617 /* lq */
2618 static void gen_lq(DisasContext *ctx)
2619 {
2620 #if defined(CONFIG_USER_ONLY)
2621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2622 #else
2623 int ra, rd;
2624 TCGv EA;
2625
2626 /* Restore CPU state */
2627 if (unlikely(ctx->mem_idx == 0)) {
2628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2629 return;
2630 }
2631 ra = rA(ctx->opcode);
2632 rd = rD(ctx->opcode);
2633 if (unlikely((rd & 1) || rd == ra)) {
2634 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2635 return;
2636 }
2637 if (unlikely(ctx->le_mode)) {
2638 /* Little-endian mode is not handled */
2639 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2640 return;
2641 }
2642 gen_set_access_type(ctx, ACCESS_INT);
2643 EA = tcg_temp_new();
2644 gen_addr_imm_index(ctx, EA, 0x0F);
2645 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2646 gen_addr_add(ctx, EA, EA, 8);
2647 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2648 tcg_temp_free(EA);
2649 #endif
2650 }
2651 #endif
2652
2653 /*** Integer store ***/
2654 #define GEN_ST(name, stop, opc, type) \
2655 static void glue(gen_, name)(DisasContext *ctx) \
2656 { \
2657 TCGv EA; \
2658 gen_set_access_type(ctx, ACCESS_INT); \
2659 EA = tcg_temp_new(); \
2660 gen_addr_imm_index(ctx, EA, 0); \
2661 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2662 tcg_temp_free(EA); \
2663 }
2664
2665 #define GEN_STU(name, stop, opc, type) \
2666 static void glue(gen_, stop##u)(DisasContext *ctx) \
2667 { \
2668 TCGv EA; \
2669 if (unlikely(rA(ctx->opcode) == 0)) { \
2670 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2671 return; \
2672 } \
2673 gen_set_access_type(ctx, ACCESS_INT); \
2674 EA = tcg_temp_new(); \
2675 if (type == PPC_64B) \
2676 gen_addr_imm_index(ctx, EA, 0x03); \
2677 else \
2678 gen_addr_imm_index(ctx, EA, 0); \
2679 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2680 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2681 tcg_temp_free(EA); \
2682 }
2683
2684 #define GEN_STUX(name, stop, opc2, opc3, type) \
2685 static void glue(gen_, name##ux)(DisasContext *ctx) \
2686 { \
2687 TCGv EA; \
2688 if (unlikely(rA(ctx->opcode) == 0)) { \
2689 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2690 return; \
2691 } \
2692 gen_set_access_type(ctx, ACCESS_INT); \
2693 EA = tcg_temp_new(); \
2694 gen_addr_reg_index(ctx, EA); \
2695 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2696 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2697 tcg_temp_free(EA); \
2698 }
2699
2700 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2701 static void glue(gen_, name##x)(DisasContext *ctx) \
2702 { \
2703 TCGv EA; \
2704 gen_set_access_type(ctx, ACCESS_INT); \
2705 EA = tcg_temp_new(); \
2706 gen_addr_reg_index(ctx, EA); \
2707 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2708 tcg_temp_free(EA); \
2709 }
2710 #define GEN_STX(name, stop, opc2, opc3, type) \
2711 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2712
2713 #define GEN_STS(name, stop, op, type) \
2714 GEN_ST(name, stop, op | 0x20, type); \
2715 GEN_STU(name, stop, op | 0x21, type); \
2716 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2717 GEN_STX(name, stop, 0x17, op | 0x00, type)
2718
2719 /* stb stbu stbux stbx */
2720 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2721 /* sth sthu sthux sthx */
2722 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2723 /* stw stwu stwux stwx */
2724 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2725 #if defined(TARGET_PPC64)
2726 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2727 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2728
2729 static void gen_std(DisasContext *ctx)
2730 {
2731 int rs;
2732 TCGv EA;
2733
2734 rs = rS(ctx->opcode);
2735 if ((ctx->opcode & 0x3) == 0x2) {
2736 #if defined(CONFIG_USER_ONLY)
2737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2738 #else
2739 /* stq */
2740 if (unlikely(ctx->mem_idx == 0)) {
2741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2742 return;
2743 }
2744 if (unlikely(rs & 1)) {
2745 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2746 return;
2747 }
2748 if (unlikely(ctx->le_mode)) {
2749 /* Little-endian mode is not handled */
2750 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2751 return;
2752 }
2753 gen_set_access_type(ctx, ACCESS_INT);
2754 EA = tcg_temp_new();
2755 gen_addr_imm_index(ctx, EA, 0x03);
2756 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2757 gen_addr_add(ctx, EA, EA, 8);
2758 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2759 tcg_temp_free(EA);
2760 #endif
2761 } else {
2762 /* std / stdu */
2763 if (Rc(ctx->opcode)) {
2764 if (unlikely(rA(ctx->opcode) == 0)) {
2765 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2766 return;
2767 }
2768 }
2769 gen_set_access_type(ctx, ACCESS_INT);
2770 EA = tcg_temp_new();
2771 gen_addr_imm_index(ctx, EA, 0x03);
2772 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2773 if (Rc(ctx->opcode))
2774 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2775 tcg_temp_free(EA);
2776 }
2777 }
2778 #endif
2779 /*** Integer load and store with byte reverse ***/
2780 /* lhbrx */
2781 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2782 {
2783 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2784 if (likely(!ctx->le_mode)) {
2785 tcg_gen_bswap16_tl(arg1, arg1);
2786 }
2787 }
2788 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2789
2790 /* lwbrx */
2791 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2792 {
2793 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2794 if (likely(!ctx->le_mode)) {
2795 tcg_gen_bswap32_tl(arg1, arg1);
2796 }
2797 }
2798 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2799
2800 #if defined(TARGET_PPC64)
2801 /* ldbrx */
2802 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2803 {
2804 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2805 if (likely(!ctx->le_mode)) {
2806 tcg_gen_bswap64_tl(arg1, arg1);
2807 }
2808 }
2809 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2810 #endif /* TARGET_PPC64 */
2811
2812 /* sthbrx */
2813 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2814 {
2815 if (likely(!ctx->le_mode)) {
2816 TCGv t0 = tcg_temp_new();
2817 tcg_gen_ext16u_tl(t0, arg1);
2818 tcg_gen_bswap16_tl(t0, t0);
2819 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2820 tcg_temp_free(t0);
2821 } else {
2822 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2823 }
2824 }
2825 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2826
2827 /* stwbrx */
2828 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2829 {
2830 if (likely(!ctx->le_mode)) {
2831 TCGv t0 = tcg_temp_new();
2832 tcg_gen_ext32u_tl(t0, arg1);
2833 tcg_gen_bswap32_tl(t0, t0);
2834 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2835 tcg_temp_free(t0);
2836 } else {
2837 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2838 }
2839 }
2840 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2841
2842 #if defined(TARGET_PPC64)
2843 /* stdbrx */
2844 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2845 {
2846 if (likely(!ctx->le_mode)) {
2847 TCGv t0 = tcg_temp_new();
2848 tcg_gen_bswap64_tl(t0, arg1);
2849 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2850 tcg_temp_free(t0);
2851 } else {
2852 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2853 }
2854 }
2855 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2856 #endif /* TARGET_PPC64 */
2857
2858 /*** Integer load and store multiple ***/
2859
2860 /* lmw */
2861 static void gen_lmw(DisasContext *ctx)
2862 {
2863 TCGv t0;
2864 TCGv_i32 t1;
2865 gen_set_access_type(ctx, ACCESS_INT);
2866 /* NIP cannot be restored if the memory exception comes from an helper */
2867 gen_update_nip(ctx, ctx->nip - 4);
2868 t0 = tcg_temp_new();
2869 t1 = tcg_const_i32(rD(ctx->opcode));
2870 gen_addr_imm_index(ctx, t0, 0);
2871 gen_helper_lmw(cpu_env, t0, t1);
2872 tcg_temp_free(t0);
2873 tcg_temp_free_i32(t1);
2874 }
2875
2876 /* stmw */
2877 static void gen_stmw(DisasContext *ctx)
2878 {
2879 TCGv t0;
2880 TCGv_i32 t1;
2881 gen_set_access_type(ctx, ACCESS_INT);
2882 /* NIP cannot be restored if the memory exception comes from an helper */
2883 gen_update_nip(ctx, ctx->nip - 4);
2884 t0 = tcg_temp_new();
2885 t1 = tcg_const_i32(rS(ctx->opcode));
2886 gen_addr_imm_index(ctx, t0, 0);
2887 gen_helper_stmw(cpu_env, t0, t1);
2888 tcg_temp_free(t0);
2889 tcg_temp_free_i32(t1);
2890 }
2891
2892 /*** Integer load and store strings ***/
2893
2894 /* lswi */
2895 /* PowerPC32 specification says we must generate an exception if
2896 * rA is in the range of registers to be loaded.
2897 * In an other hand, IBM says this is valid, but rA won't be loaded.
2898 * For now, I'll follow the spec...
2899 */
2900 static void gen_lswi(DisasContext *ctx)
2901 {
2902 TCGv t0;
2903 TCGv_i32 t1, t2;
2904 int nb = NB(ctx->opcode);
2905 int start = rD(ctx->opcode);
2906 int ra = rA(ctx->opcode);
2907 int nr;
2908
2909 if (nb == 0)
2910 nb = 32;
2911 nr = nb / 4;
2912 if (unlikely(((start + nr) > 32 &&
2913 start <= ra && (start + nr - 32) > ra) ||
2914 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2915 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2916 return;
2917 }
2918 gen_set_access_type(ctx, ACCESS_INT);
2919 /* NIP cannot be restored if the memory exception comes from an helper */
2920 gen_update_nip(ctx, ctx->nip - 4);
2921 t0 = tcg_temp_new();
2922 gen_addr_register(ctx, t0);
2923 t1 = tcg_const_i32(nb);
2924 t2 = tcg_const_i32(start);
2925 gen_helper_lsw(cpu_env, t0, t1, t2);
2926 tcg_temp_free(t0);
2927 tcg_temp_free_i32(t1);
2928 tcg_temp_free_i32(t2);
2929 }
2930
2931 /* lswx */
2932 static void gen_lswx(DisasContext *ctx)
2933 {
2934 TCGv t0;
2935 TCGv_i32 t1, t2, t3;
2936 gen_set_access_type(ctx, ACCESS_INT);
2937 /* NIP cannot be restored if the memory exception comes from an helper */
2938 gen_update_nip(ctx, ctx->nip - 4);
2939 t0 = tcg_temp_new();
2940 gen_addr_reg_index(ctx, t0);
2941 t1 = tcg_const_i32(rD(ctx->opcode));
2942 t2 = tcg_const_i32(rA(ctx->opcode));
2943 t3 = tcg_const_i32(rB(ctx->opcode));
2944 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2945 tcg_temp_free(t0);
2946 tcg_temp_free_i32(t1);
2947 tcg_temp_free_i32(t2);
2948 tcg_temp_free_i32(t3);
2949 }
2950
2951 /* stswi */
2952 static void gen_stswi(DisasContext *ctx)
2953 {
2954 TCGv t0;
2955 TCGv_i32 t1, t2;
2956 int nb = NB(ctx->opcode);
2957 gen_set_access_type(ctx, ACCESS_INT);
2958 /* NIP cannot be restored if the memory exception comes from an helper */
2959 gen_update_nip(ctx, ctx->nip - 4);
2960 t0 = tcg_temp_new();
2961 gen_addr_register(ctx, t0);
2962 if (nb == 0)
2963 nb = 32;
2964 t1 = tcg_const_i32(nb);
2965 t2 = tcg_const_i32(rS(ctx->opcode));
2966 gen_helper_stsw(cpu_env, t0, t1, t2);
2967 tcg_temp_free(t0);
2968 tcg_temp_free_i32(t1);
2969 tcg_temp_free_i32(t2);
2970 }
2971
2972 /* stswx */
2973 static void gen_stswx(DisasContext *ctx)
2974 {
2975 TCGv t0;
2976 TCGv_i32 t1, t2;
2977 gen_set_access_type(ctx, ACCESS_INT);
2978 /* NIP cannot be restored if the memory exception comes from an helper */
2979 gen_update_nip(ctx, ctx->nip - 4);
2980 t0 = tcg_temp_new();
2981 gen_addr_reg_index(ctx, t0);
2982 t1 = tcg_temp_new_i32();
2983 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2984 tcg_gen_andi_i32(t1, t1, 0x7F);
2985 t2 = tcg_const_i32(rS(ctx->opcode));
2986 gen_helper_stsw(cpu_env, t0, t1, t2);
2987 tcg_temp_free(t0);
2988 tcg_temp_free_i32(t1);
2989 tcg_temp_free_i32(t2);
2990 }
2991
2992 /*** Memory synchronisation ***/
2993 /* eieio */
2994 static void gen_eieio(DisasContext *ctx)
2995 {
2996 }
2997
2998 /* isync */
2999 static void gen_isync(DisasContext *ctx)
3000 {
3001 gen_stop_exception(ctx);
3002 }
3003
3004 /* lwarx */
3005 static void gen_lwarx(DisasContext *ctx)
3006 {
3007 TCGv t0;
3008 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3009 gen_set_access_type(ctx, ACCESS_RES);
3010 t0 = tcg_temp_local_new();
3011 gen_addr_reg_index(ctx, t0);
3012 gen_check_align(ctx, t0, 0x03);
3013 gen_qemu_ld32u(ctx, gpr, t0);
3014 tcg_gen_mov_tl(cpu_reserve, t0);
3015 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3016 tcg_temp_free(t0);
3017 }
3018
3019 #if defined(CONFIG_USER_ONLY)
3020 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3021 int reg, int size)
3022 {
3023 TCGv t0 = tcg_temp_new();
3024 uint32_t save_exception = ctx->exception;
3025
3026 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3027 tcg_gen_movi_tl(t0, (size << 5) | reg);
3028 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3029 tcg_temp_free(t0);
3030 gen_update_nip(ctx, ctx->nip-4);
3031 ctx->exception = POWERPC_EXCP_BRANCH;
3032 gen_exception(ctx, POWERPC_EXCP_STCX);
3033 ctx->exception = save_exception;
3034 }
3035 #endif
3036
3037 /* stwcx. */
3038 static void gen_stwcx_(DisasContext *ctx)
3039 {
3040 TCGv t0;
3041 gen_set_access_type(ctx, ACCESS_RES);
3042 t0 = tcg_temp_local_new();
3043 gen_addr_reg_index(ctx, t0);
3044 gen_check_align(ctx, t0, 0x03);
3045 #if defined(CONFIG_USER_ONLY)
3046 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3047 #else
3048 {
3049 int l1;
3050
3051 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3052 l1 = gen_new_label();
3053 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3054 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3055 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3056 gen_set_label(l1);
3057 tcg_gen_movi_tl(cpu_reserve, -1);
3058 }
3059 #endif
3060 tcg_temp_free(t0);
3061 }
3062
3063 #if defined(TARGET_PPC64)
3064 /* ldarx */
3065 static void gen_ldarx(DisasContext *ctx)
3066 {
3067 TCGv t0;
3068 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3069 gen_set_access_type(ctx, ACCESS_RES);
3070 t0 = tcg_temp_local_new();
3071 gen_addr_reg_index(ctx, t0);
3072 gen_check_align(ctx, t0, 0x07);
3073 gen_qemu_ld64(ctx, gpr, t0);
3074 tcg_gen_mov_tl(cpu_reserve, t0);
3075 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3076 tcg_temp_free(t0);
3077 }
3078
3079 /* stdcx. */
3080 static void gen_stdcx_(DisasContext *ctx)
3081 {
3082 TCGv t0;
3083 gen_set_access_type(ctx, ACCESS_RES);
3084 t0 = tcg_temp_local_new();
3085 gen_addr_reg_index(ctx, t0);
3086 gen_check_align(ctx, t0, 0x07);
3087 #if defined(CONFIG_USER_ONLY)
3088 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3089 #else
3090 {
3091 int l1;
3092 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3093 l1 = gen_new_label();
3094 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3095 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3096 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3097 gen_set_label(l1);
3098 tcg_gen_movi_tl(cpu_reserve, -1);
3099 }
3100 #endif
3101 tcg_temp_free(t0);
3102 }
3103 #endif /* defined(TARGET_PPC64) */
3104
3105 /* sync */
3106 static void gen_sync(DisasContext *ctx)
3107 {
3108 }
3109
3110 /* wait */
3111 static void gen_wait(DisasContext *ctx)
3112 {
3113 TCGv_i32 t0 = tcg_temp_new_i32();
3114 tcg_gen_st_i32(t0, cpu_env,
3115 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3116 tcg_temp_free_i32(t0);
3117 /* Stop translation, as the CPU is supposed to sleep from now */
3118 gen_exception_err(ctx, EXCP_HLT, 1);
3119 }
3120
3121 /*** Floating-point load ***/
3122 #define GEN_LDF(name, ldop, opc, type) \
3123 static void glue(gen_, name)(DisasContext *ctx) \
3124 { \
3125 TCGv EA; \
3126 if (unlikely(!ctx->fpu_enabled)) { \
3127 gen_exception(ctx, POWERPC_EXCP_FPU); \
3128 return; \
3129 } \
3130 gen_set_access_type(ctx, ACCESS_FLOAT); \
3131 EA = tcg_temp_new(); \
3132 gen_addr_imm_index(ctx, EA, 0); \
3133 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3134 tcg_temp_free(EA); \
3135 }
3136
3137 #define GEN_LDUF(name, ldop, opc, type) \
3138 static void glue(gen_, name##u)(DisasContext *ctx) \
3139 { \
3140 TCGv EA; \
3141 if (unlikely(!ctx->fpu_enabled)) { \
3142 gen_exception(ctx, POWERPC_EXCP_FPU); \
3143 return; \
3144 } \
3145 if (unlikely(rA(ctx->opcode) == 0)) { \
3146 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3147 return; \
3148 } \
3149 gen_set_access_type(ctx, ACCESS_FLOAT); \
3150 EA = tcg_temp_new(); \
3151 gen_addr_imm_index(ctx, EA, 0); \
3152 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3153 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3154 tcg_temp_free(EA); \
3155 }
3156
3157 #define GEN_LDUXF(name, ldop, opc, type) \
3158 static void glue(gen_, name##ux)(DisasContext *ctx) \
3159 { \
3160 TCGv EA; \
3161 if (unlikely(!ctx->fpu_enabled)) { \
3162 gen_exception(ctx, POWERPC_EXCP_FPU); \
3163 return; \
3164 } \
3165 if (unlikely(rA(ctx->opcode) == 0)) { \
3166 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3167 return; \
3168 } \
3169 gen_set_access_type(ctx, ACCESS_FLOAT); \
3170 EA = tcg_temp_new(); \
3171 gen_addr_reg_index(ctx, EA); \
3172 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3173 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3174 tcg_temp_free(EA); \
3175 }
3176
3177 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3178 static void glue(gen_, name##x)(DisasContext *ctx) \
3179 { \
3180 TCGv EA; \
3181 if (unlikely(!ctx->fpu_enabled)) { \
3182 gen_exception(ctx, POWERPC_EXCP_FPU); \
3183 return; \
3184 } \
3185 gen_set_access_type(ctx, ACCESS_FLOAT); \
3186 EA = tcg_temp_new(); \
3187 gen_addr_reg_index(ctx, EA); \
3188 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3189 tcg_temp_free(EA); \
3190 }
3191
3192 #define GEN_LDFS(name, ldop, op, type) \
3193 GEN_LDF(name, ldop, op | 0x20, type); \
3194 GEN_LDUF(name, ldop, op | 0x21, type); \
3195 GEN_LDUXF(name, ldop, op | 0x01, type); \
3196 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3197
3198 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3199 {
3200 TCGv t0 = tcg_temp_new();
3201 TCGv_i32 t1 = tcg_temp_new_i32();
3202 gen_qemu_ld32u(ctx, t0, arg2);
3203 tcg_gen_trunc_tl_i32(t1, t0);
3204 tcg_temp_free(t0);
3205 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3206 tcg_temp_free_i32(t1);
3207 }
3208
3209 /* lfd lfdu lfdux lfdx */
3210 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3211 /* lfs lfsu lfsux lfsx */
3212 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3213
3214 /*** Floating-point store ***/
3215 #define GEN_STF(name, stop, opc, type) \
3216 static void glue(gen_, name)(DisasContext *ctx) \
3217 { \
3218 TCGv EA; \
3219 if (unlikely(!ctx->fpu_enabled)) { \
3220 gen_exception(ctx, POWERPC_EXCP_FPU); \
3221 return; \
3222 } \
3223 gen_set_access_type(ctx, ACCESS_FLOAT); \
3224 EA = tcg_temp_new(); \
3225 gen_addr_imm_index(ctx, EA, 0); \
3226 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3227 tcg_temp_free(EA); \
3228 }
3229
3230 #define GEN_STUF(name, stop, opc, type) \
3231 static void glue(gen_, name##u)(DisasContext *ctx) \
3232 { \
3233 TCGv EA; \
3234 if (unlikely(!ctx->fpu_enabled)) { \
3235 gen_exception(ctx, POWERPC_EXCP_FPU); \
3236 return; \
3237 } \
3238 if (unlikely(rA(ctx->opcode) == 0)) { \
3239 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3240 return; \
3241 } \
3242 gen_set_access_type(ctx, ACCESS_FLOAT); \
3243 EA = tcg_temp_new(); \
3244 gen_addr_imm_index(ctx, EA, 0); \
3245 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3246 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3247 tcg_temp_free(EA); \
3248 }
3249
3250 #define GEN_STUXF(name, stop, opc, type) \
3251 static void glue(gen_, name##ux)(DisasContext *ctx) \
3252 { \
3253 TCGv EA; \
3254 if (unlikely(!ctx->fpu_enabled)) { \
3255 gen_exception(ctx, POWERPC_EXCP_FPU); \
3256 return; \
3257 } \
3258 if (unlikely(rA(ctx->opcode) == 0)) { \
3259 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3260 return; \
3261 } \
3262 gen_set_access_type(ctx, ACCESS_FLOAT); \
3263 EA = tcg_temp_new(); \
3264 gen_addr_reg_index(ctx, EA); \
3265 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3266 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3267 tcg_temp_free(EA); \
3268 }
3269
3270 #define GEN_STXF(name, stop, opc2, opc3, type) \
3271 static void glue(gen_, name##x)(DisasContext *ctx) \
3272 { \
3273 TCGv EA; \
3274 if (unlikely(!ctx->fpu_enabled)) { \
3275 gen_exception(ctx, POWERPC_EXCP_FPU); \
3276 return; \
3277 } \
3278 gen_set_access_type(ctx, ACCESS_FLOAT); \
3279 EA = tcg_temp_new(); \
3280 gen_addr_reg_index(ctx, EA); \
3281 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3282 tcg_temp_free(EA); \
3283 }
3284
3285 #define GEN_STFS(name, stop, op, type) \
3286 GEN_STF(name, stop, op | 0x20, type); \
3287 GEN_STUF(name, stop, op | 0x21, type); \
3288 GEN_STUXF(name, stop, op | 0x01, type); \
3289 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3290
3291 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3292 {
3293 TCGv_i32 t0 = tcg_temp_new_i32();
3294 TCGv t1 = tcg_temp_new();
3295 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3296 tcg_gen_extu_i32_tl(t1, t0);
3297 tcg_temp_free_i32(t0);
3298 gen_qemu_st32(ctx, t1, arg2);
3299 tcg_temp_free(t1);
3300 }
3301
3302 /* stfd stfdu stfdux stfdx */
3303 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3304 /* stfs stfsu stfsux stfsx */
3305 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3306
3307 /* Optional: */
3308 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3309 {
3310 TCGv t0 = tcg_temp_new();
3311 tcg_gen_trunc_i64_tl(t0, arg1),
3312 gen_qemu_st32(ctx, t0, arg2);
3313 tcg_temp_free(t0);
3314 }
3315 /* stfiwx */
3316 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3317
3318 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3319 {
3320 #if defined(TARGET_PPC64)
3321 if (ctx->has_cfar)
3322 tcg_gen_movi_tl(cpu_cfar, nip);
3323 #endif
3324 }
3325
3326 /*** Branch ***/
3327 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3328 {
3329 TranslationBlock *tb;
3330 tb = ctx->tb;
3331 if (NARROW_MODE(ctx)) {
3332 dest = (uint32_t) dest;
3333 }
3334 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3335 likely(!ctx->singlestep_enabled)) {
3336 tcg_gen_goto_tb(n);
3337 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3338 tcg_gen_exit_tb((tcg_target_long)tb + n);
3339 } else {
3340 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3341 if (unlikely(ctx->singlestep_enabled)) {
3342 if ((ctx->singlestep_enabled &
3343 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3344 (ctx->exception == POWERPC_EXCP_BRANCH ||
3345 ctx->exception == POWERPC_EXCP_TRACE)) {
3346 target_ulong tmp = ctx->nip;
3347 ctx->nip = dest;
3348 gen_exception(ctx, POWERPC_EXCP_TRACE);
3349 ctx->nip = tmp;
3350 }
3351 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3352 gen_debug_exception(ctx);
3353 }
3354 }
3355 tcg_gen_exit_tb(0);
3356 }
3357 }
3358
3359 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3360 {
3361 if (NARROW_MODE(ctx)) {
3362 nip = (uint32_t)nip;
3363 }
3364 tcg_gen_movi_tl(cpu_lr, nip);
3365 }
3366
3367 /* b ba bl bla */
3368 static void gen_b(DisasContext *ctx)
3369 {
3370 target_ulong li, target;
3371
3372 ctx->exception = POWERPC_EXCP_BRANCH;
3373 /* sign extend LI */
3374 li = LI(ctx->opcode);
3375 li = (li ^ 0x02000000) - 0x02000000;
3376 if (likely(AA(ctx->opcode) == 0)) {
3377 target = ctx->nip + li - 4;
3378 } else {
3379 target = li;
3380 }
3381 if (LK(ctx->opcode)) {
3382 gen_setlr(ctx, ctx->nip);
3383 }
3384 gen_update_cfar(ctx, ctx->nip);
3385 gen_goto_tb(ctx, 0, target);
3386 }
3387
3388 #define BCOND_IM 0
3389 #define BCOND_LR 1
3390 #define BCOND_CTR 2
3391
3392 static inline void gen_bcond(DisasContext *ctx, int type)
3393 {
3394 uint32_t bo = BO(ctx->opcode);
3395 int l1;
3396 TCGv target;
3397
3398 ctx->exception = POWERPC_EXCP_BRANCH;
3399 if (type == BCOND_LR || type == BCOND_CTR) {
3400 target = tcg_temp_local_new();
3401 if (type == BCOND_CTR)
3402 tcg_gen_mov_tl(target, cpu_ctr);
3403 else
3404 tcg_gen_mov_tl(target, cpu_lr);
3405 } else {
3406 TCGV_UNUSED(target);
3407 }
3408 if (LK(ctx->opcode))
3409 gen_setlr(ctx, ctx->nip);
3410 l1 = gen_new_label();
3411 if ((bo & 0x4) == 0) {
3412 /* Decrement and test CTR */
3413 TCGv temp = tcg_temp_new();
3414 if (unlikely(type == BCOND_CTR)) {
3415 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3416 return;
3417 }
3418 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3419 if (NARROW_MODE(ctx)) {
3420 tcg_gen_ext32u_tl(temp, cpu_ctr);
3421 } else {
3422 tcg_gen_mov_tl(temp, cpu_ctr);
3423 }
3424 if (bo & 0x2) {
3425 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3426 } else {
3427 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3428 }
3429 tcg_temp_free(temp);
3430 }
3431 if ((bo & 0x10) == 0) {
3432 /* Test CR */
3433 uint32_t bi = BI(ctx->opcode);
3434 uint32_t mask = 1 << (3 - (bi & 0x03));
3435 TCGv_i32 temp = tcg_temp_new_i32();
3436
3437 if (bo & 0x8) {
3438 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3439 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3440 } else {
3441 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3442 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3443 }
3444 tcg_temp_free_i32(temp);
3445 }
3446 gen_update_cfar(ctx, ctx->nip);
3447 if (type == BCOND_IM) {
3448 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3449 if (likely(AA(ctx->opcode) == 0)) {
3450 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3451 } else {
3452 gen_goto_tb(ctx, 0, li);
3453 }
3454 gen_set_label(l1);
3455 gen_goto_tb(ctx, 1, ctx->nip);
3456 } else {
3457 if (NARROW_MODE(ctx)) {
3458 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3459 } else {
3460 tcg_gen_andi_tl(cpu_nip, target, ~3);
3461 }
3462 tcg_gen_exit_tb(0);
3463 gen_set_label(l1);
3464 gen_update_nip(ctx, ctx->nip);
3465 tcg_gen_exit_tb(0);
3466 }
3467 }
3468
3469 static void gen_bc(DisasContext *ctx)
3470 {
3471 gen_bcond(ctx, BCOND_IM);
3472 }
3473
3474 static void gen_bcctr(DisasContext *ctx)
3475 {
3476 gen_bcond(ctx, BCOND_CTR);
3477 }
3478
3479 static void gen_bclr(DisasContext *ctx)
3480 {
3481 gen_bcond(ctx, BCOND_LR);
3482 }
3483
3484 /*** Condition register logical ***/
3485 #define GEN_CRLOGIC(name, tcg_op, opc) \
3486 static void glue(gen_, name)(DisasContext *ctx) \
3487 { \
3488 uint8_t bitmask; \
3489 int sh; \
3490 TCGv_i32 t0, t1; \
3491 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3492 t0 = tcg_temp_new_i32(); \
3493 if (sh > 0) \
3494 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3495 else if (sh < 0) \
3496 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3497 else \
3498 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3499 t1 = tcg_temp_new_i32(); \
3500 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3501 if (sh > 0) \
3502 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3503 else if (sh < 0) \
3504 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3505 else \
3506 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3507 tcg_op(t0, t0, t1); \
3508 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3509 tcg_gen_andi_i32(t0, t0, bitmask); \
3510 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3511 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3512 tcg_temp_free_i32(t0); \
3513 tcg_temp_free_i32(t1); \
3514 }
3515
3516 /* crand */
3517 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3518 /* crandc */
3519 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3520 /* creqv */
3521 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3522 /* crnand */
3523 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3524 /* crnor */
3525 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3526 /* cror */
3527 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3528 /* crorc */
3529 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3530 /* crxor */
3531 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3532
3533 /* mcrf */
3534 static void gen_mcrf(DisasContext *ctx)
3535 {
3536 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3537 }
3538
3539 /*** System linkage ***/
3540
3541 /* rfi (mem_idx only) */
3542 static void gen_rfi(DisasContext *ctx)
3543 {
3544 #if defined(CONFIG_USER_ONLY)
3545 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3546 #else
3547 /* Restore CPU state */
3548 if (unlikely(!ctx->mem_idx)) {
3549 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3550 return;
3551 }
3552 gen_update_cfar(ctx, ctx->nip);
3553 gen_helper_rfi(cpu_env);
3554 gen_sync_exception(ctx);
3555 #endif
3556 }
3557
3558 #if defined(TARGET_PPC64)
3559 static void gen_rfid(DisasContext *ctx)
3560 {
3561 #if defined(CONFIG_USER_ONLY)
3562 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3563 #else
3564 /* Restore CPU state */
3565 if (unlikely(!ctx->mem_idx)) {
3566 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3567 return;
3568 }
3569 gen_update_cfar(ctx, ctx->nip);
3570 gen_helper_rfid(cpu_env);
3571 gen_sync_exception(ctx);
3572 #endif
3573 }
3574
3575 static void gen_hrfid(DisasContext *ctx)
3576 {
3577 #if defined(CONFIG_USER_ONLY)
3578 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3579 #else
3580 /* Restore CPU state */
3581 if (unlikely(ctx->mem_idx <= 1)) {
3582 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3583 return;
3584 }
3585 gen_helper_hrfid(cpu_env);
3586 gen_sync_exception(ctx);
3587 #endif
3588 }
3589 #endif
3590
3591 /* sc */
3592 #if defined(CONFIG_USER_ONLY)
3593 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3594 #else
3595 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3596 #endif
3597 static void gen_sc(DisasContext *ctx)
3598 {
3599 uint32_t lev;
3600
3601 lev = (ctx->opcode >> 5) & 0x7F;
3602 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3603 }
3604
3605 /*** Trap ***/
3606
3607 /* tw */
3608 static void gen_tw(DisasContext *ctx)
3609 {
3610 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3611 /* Update the nip since this might generate a trap exception */
3612 gen_update_nip(ctx, ctx->nip);
3613 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3614 t0);
3615 tcg_temp_free_i32(t0);
3616 }
3617
3618 /* twi */
3619 static void gen_twi(DisasContext *ctx)
3620 {
3621 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3622 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3623 /* Update the nip since this might generate a trap exception */
3624 gen_update_nip(ctx, ctx->nip);
3625 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3626 tcg_temp_free(t0);
3627 tcg_temp_free_i32(t1);
3628 }
3629
3630 #if defined(TARGET_PPC64)
3631 /* td */
3632 static void gen_td(DisasContext *ctx)
3633 {
3634 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3635 /* Update the nip since this might generate a trap exception */
3636 gen_update_nip(ctx, ctx->nip);
3637 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3638 t0);
3639 tcg_temp_free_i32(t0);
3640 }
3641
3642 /* tdi */
3643 static void gen_tdi(DisasContext *ctx)
3644 {
3645 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3646 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3647 /* Update the nip since this might generate a trap exception */
3648 gen_update_nip(ctx, ctx->nip);
3649 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3650 tcg_temp_free(t0);
3651 tcg_temp_free_i32(t1);
3652 }
3653 #endif
3654
3655 /*** Processor control ***/
3656
3657 static void gen_read_xer(TCGv dst)
3658 {
3659 TCGv t0 = tcg_temp_new();
3660 TCGv t1 = tcg_temp_new();
3661 TCGv t2 = tcg_temp_new();
3662 tcg_gen_mov_tl(dst, cpu_xer);
3663 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3664 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3665 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3666 tcg_gen_or_tl(t0, t0, t1);
3667 tcg_gen_or_tl(dst, dst, t2);
3668 tcg_gen_or_tl(dst, dst, t0);
3669 tcg_temp_free(t0);
3670 tcg_temp_free(t1);
3671 tcg_temp_free(t2);
3672 }
3673
3674 static void gen_write_xer(TCGv src)
3675 {
3676 tcg_gen_andi_tl(cpu_xer, src,
3677 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3678 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3679 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3680 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3681 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3682 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3683 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3684 }
3685
3686 /* mcrxr */
3687 static void gen_mcrxr(DisasContext *ctx)
3688 {
3689 TCGv_i32 t0 = tcg_temp_new_i32();
3690 TCGv_i32 t1 = tcg_temp_new_i32();
3691 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3692
3693 tcg_gen_trunc_tl_i32(t0, cpu_so);
3694 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3695 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3696 tcg_gen_shri_i32(t0, t0, 2);
3697 tcg_gen_shri_i32(t1, t1, 1);
3698 tcg_gen_or_i32(dst, dst, t0);
3699 tcg_gen_or_i32(dst, dst, t1);
3700 tcg_temp_free_i32(t0);
3701 tcg_temp_free_i32(t1);
3702
3703 tcg_gen_movi_tl(cpu_so, 0);
3704 tcg_gen_movi_tl(cpu_ov, 0);
3705 tcg_gen_movi_tl(cpu_ca, 0);
3706 }
3707
3708 /* mfcr mfocrf */
3709 static void gen_mfcr(DisasContext *ctx)
3710 {
3711 uint32_t crm, crn;
3712
3713 if (likely(ctx->opcode & 0x00100000)) {
3714 crm = CRM(ctx->opcode);
3715 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3716 crn = ctz32 (crm);
3717 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3718 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3719 cpu_gpr[rD(ctx->opcode)], crn * 4);
3720 }
3721 } else {
3722 TCGv_i32 t0 = tcg_temp_new_i32();
3723 tcg_gen_mov_i32(t0, cpu_crf[0]);
3724 tcg_gen_shli_i32(t0, t0, 4);
3725 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3726 tcg_gen_shli_i32(t0, t0, 4);
3727 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3728 tcg_gen_shli_i32(t0, t0, 4);
3729 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3730 tcg_gen_shli_i32(t0, t0, 4);
3731 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3732 tcg_gen_shli_i32(t0, t0, 4);
3733 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3734 tcg_gen_shli_i32(t0, t0, 4);
3735 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3736 tcg_gen_shli_i32(t0, t0, 4);
3737 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3738 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3739 tcg_temp_free_i32(t0);
3740 }
3741 }
3742
3743 /* mfmsr */
3744 static void gen_mfmsr(DisasContext *ctx)
3745 {
3746 #if defined(CONFIG_USER_ONLY)
3747 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3748 #else
3749 if (unlikely(!ctx->mem_idx)) {
3750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3751 return;
3752 }
3753 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3754 #endif
3755 }
3756
3757 static void spr_noaccess(void *opaque, int gprn, int sprn)
3758 {
3759 #if 0
3760 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3761 printf("ERROR: try to access SPR %d !\n", sprn);
3762 #endif
3763 }
3764 #define SPR_NOACCESS (&spr_noaccess)
3765
3766 /* mfspr */
3767 static inline void gen_op_mfspr(DisasContext *ctx)
3768 {
3769 void (*read_cb)(void *opaque, int gprn, int sprn);
3770 uint32_t sprn = SPR(ctx->opcode);
3771
3772 #if !defined(CONFIG_USER_ONLY)
3773 if (ctx->mem_idx == 2)
3774 read_cb = ctx->spr_cb[sprn].hea_read;
3775 else if (ctx->mem_idx)
3776 read_cb = ctx->spr_cb[sprn].oea_read;
3777 else
3778 #endif
3779 read_cb = ctx->spr_cb[sprn].uea_read;
3780 if (likely(read_cb != NULL)) {
3781 if (likely(read_cb != SPR_NOACCESS)) {
3782 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3783 } else {
3784 /* Privilege exception */
3785 /* This is a hack to avoid warnings when running Linux:
3786 * this OS breaks the PowerPC virtualisation model,
3787 * allowing userland application to read the PVR
3788 */
3789 if (sprn != SPR_PVR) {
3790 qemu_log("Trying to read privileged spr %d %03x at "
3791 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3792 printf("Trying to read privileged spr %d %03x at "
3793 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3794 }
3795 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3796 }
3797 } else {
3798 /* Not defined */
3799 qemu_log("Trying to read invalid spr %d %03x at "
3800 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3801 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3802 sprn, sprn, ctx->nip);
3803 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3804 }
3805 }
3806
3807 static void gen_mfspr(DisasContext *ctx)
3808 {
3809 gen_op_mfspr(ctx);
3810 }
3811
3812 /* mftb */
3813 static void gen_mftb(DisasContext *ctx)
3814 {
3815 gen_op_mfspr(ctx);
3816 }
3817
3818 /* mtcrf mtocrf*/
3819 static void gen_mtcrf(DisasContext *ctx)
3820 {
3821 uint32_t crm, crn;
3822
3823 crm = CRM(ctx->opcode);
3824 if (likely((ctx->opcode & 0x00100000))) {
3825 if (crm && ((crm & (crm - 1)) == 0)) {
3826 TCGv_i32 temp = tcg_temp_new_i32();
3827 crn = ctz32 (crm);
3828 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3829 tcg_gen_shri_i32(temp, temp, crn * 4);
3830 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3831 tcg_temp_free_i32(temp);
3832 }
3833 } else {
3834 TCGv_i32 temp = tcg_temp_new_i32();
3835 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3836 for (crn = 0 ; crn < 8 ; crn++) {
3837 if (crm & (1 << crn)) {
3838 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3839 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3840 }
3841 }
3842 tcg_temp_free_i32(temp);
3843 }
3844 }
3845
3846 /* mtmsr */
3847 #if defined(TARGET_PPC64)
3848 static void gen_mtmsrd(DisasContext *ctx)
3849 {
3850 #if defined(CONFIG_USER_ONLY)
3851 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3852 #else
3853 if (unlikely(!ctx->mem_idx)) {
3854 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3855 return;
3856 }
3857 if (ctx->opcode & 0x00010000) {
3858 /* Special form that does not need any synchronisation */
3859 TCGv t0 = tcg_temp_new();
3860 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3861 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3862 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3863 tcg_temp_free(t0);
3864 } else {
3865 /* XXX: we need to update nip before the store
3866 * if we enter power saving mode, we will exit the loop
3867 * directly from ppc_store_msr
3868 */
3869 gen_update_nip(ctx, ctx->nip);
3870 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3871 /* Must stop the translation as machine state (may have) changed */
3872 /* Note that mtmsr is not always defined as context-synchronizing */
3873 gen_stop_exception(ctx);
3874 }
3875 #endif
3876 }
3877 #endif
3878
3879 static void gen_mtmsr(DisasContext *ctx)
3880 {
3881 #if defined(CONFIG_USER_ONLY)
3882 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3883 #else
3884 if (unlikely(!ctx->mem_idx)) {
3885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3886 return;
3887 }
3888 if (ctx->opcode & 0x00010000) {
3889 /* Special form that does not need any synchronisation */
3890 TCGv t0 = tcg_temp_new();
3891 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3892 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3893 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3894 tcg_temp_free(t0);
3895 } else {
3896 TCGv msr = tcg_temp_new();
3897
3898 /* XXX: we need to update nip before the store
3899 * if we enter power saving mode, we will exit the loop
3900 * directly from ppc_store_msr
3901 */
3902 gen_update_nip(ctx, ctx->nip);
3903 #if defined(TARGET_PPC64)
3904 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3905 #else
3906 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3907 #endif
3908 gen_helper_store_msr(cpu_env, msr);
3909 /* Must stop the translation as machine state (may have) changed */
3910 /* Note that mtmsr is not always defined as context-synchronizing */
3911 gen_stop_exception(ctx);
3912 }
3913 #endif
3914 }
3915
3916 /* mtspr */
3917 static void gen_mtspr(DisasContext *ctx)
3918 {
3919 void (*write_cb)(void *opaque, int sprn, int gprn);
3920 uint32_t sprn = SPR(ctx->opcode);
3921
3922 #if !defined(CONFIG_USER_ONLY)
3923 if (ctx->mem_idx == 2)
3924 write_cb = ctx->spr_cb[sprn].hea_write;
3925 else if (ctx->mem_idx)
3926 write_cb = ctx->spr_cb[sprn].oea_write;
3927 else
3928 #endif
3929 write_cb = ctx->spr_cb[sprn].uea_write;
3930 if (likely(write_cb != NULL)) {
3931 if (likely(write_cb != SPR_NOACCESS)) {
3932 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3933 } else {
3934 /* Privilege exception */
3935 qemu_log("Trying to write privileged spr %d %03x at "
3936 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3937 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3938 "\n", sprn, sprn, ctx->nip);
3939 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3940 }
3941 } else {
3942 /* Not defined */
3943 qemu_log("Trying to write invalid spr %d %03x at "
3944 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3945 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3946 sprn, sprn, ctx->nip);
3947 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3948 }
3949 }
3950
3951 /*** Cache management ***/
3952
3953 /* dcbf */
3954 static void gen_dcbf(DisasContext *ctx)
3955 {
3956 /* XXX: specification says this is treated as a load by the MMU */
3957 TCGv t0;
3958 gen_set_access_type(ctx, ACCESS_CACHE);
3959 t0 = tcg_temp_new();
3960 gen_addr_reg_index(ctx, t0);
3961 gen_qemu_ld8u(ctx, t0, t0);
3962 tcg_temp_free(t0);
3963 }
3964
3965 /* dcbi (Supervisor only) */
3966 static void gen_dcbi(DisasContext *ctx)
3967 {
3968 #if defined(CONFIG_USER_ONLY)
3969 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3970 #else
3971 TCGv EA, val;
3972 if (unlikely(!ctx->mem_idx)) {
3973 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3974 return;
3975 }
3976 EA = tcg_temp_new();
3977 gen_set_access_type(ctx, ACCESS_CACHE);
3978 gen_addr_reg_index(ctx, EA);
3979 val = tcg_temp_new();
3980 /* XXX: specification says this should be treated as a store by the MMU */
3981 gen_qemu_ld8u(ctx, val, EA);
3982 gen_qemu_st8(ctx, val, EA);
3983 tcg_temp_free(val);
3984 tcg_temp_free(EA);
3985 #endif
3986 }
3987
3988 /* dcdst */
3989 static void gen_dcbst(DisasContext *ctx)
3990 {
3991 /* XXX: specification say this is treated as a load by the MMU */
3992 TCGv t0;
3993 gen_set_access_type(ctx, ACCESS_CACHE);
3994 t0 = tcg_temp_new();
3995 gen_addr_reg_index(ctx, t0);
3996 gen_qemu_ld8u(ctx, t0, t0);
3997 tcg_temp_free(t0);
3998 }
3999
4000 /* dcbt */
4001 static void gen_dcbt(DisasContext *ctx)
4002 {
4003 /* interpreted as no-op */
4004 /* XXX: specification say this is treated as a load by the MMU
4005 * but does not generate any exception
4006 */
4007 }
4008
4009 /* dcbtst */
4010 static void gen_dcbtst(DisasContext *ctx)
4011 {
4012 /* interpreted as no-op */
4013 /* XXX: specification say this is treated as a load by the MMU
4014 * but does not generate any exception
4015 */
4016 }
4017
4018 /* dcbz */
4019 static void gen_dcbz(DisasContext *ctx)
4020 {
4021 TCGv tcgv_addr;
4022 TCGv_i32 tcgv_is_dcbzl;
4023 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4024
4025 gen_set_access_type(ctx, ACCESS_CACHE);
4026 /* NIP cannot be restored if the memory exception comes from an helper */
4027 gen_update_nip(ctx, ctx->nip - 4);
4028 tcgv_addr = tcg_temp_new();
4029 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4030
4031 gen_addr_reg_index(ctx, tcgv_addr);
4032 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4033
4034 tcg_temp_free(tcgv_addr);
4035 tcg_temp_free_i32(tcgv_is_dcbzl);
4036 }
4037
4038 /* dst / dstt */
4039 static void gen_dst(DisasContext *ctx)
4040 {
4041 if (rA(ctx->opcode) == 0) {
4042 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4043 } else {
4044 /* interpreted as no-op */
4045 }
4046 }
4047
4048 /* dstst /dststt */
4049 static void gen_dstst(DisasContext *ctx)
4050 {
4051 if (rA(ctx->opcode) == 0) {
4052 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4053 } else {
4054 /* interpreted as no-op */
4055 }
4056
4057 }
4058
4059 /* dss / dssall */
4060 static void gen_dss(DisasContext *ctx)
4061 {
4062 /* interpreted as no-op */
4063 }
4064
4065 /* icbi */
4066 static void gen_icbi(DisasContext *ctx)
4067 {
4068 TCGv t0;
4069 gen_set_access_type(ctx, ACCESS_CACHE);
4070 /* NIP cannot be restored if the memory exception comes from an helper */
4071 gen_update_nip(ctx, ctx->nip - 4);
4072 t0 = tcg_temp_new();
4073 gen_addr_reg_index(ctx, t0);
4074 gen_helper_icbi(cpu_env, t0);
4075 tcg_temp_free(t0);
4076 }
4077
4078 /* Optional: */
4079 /* dcba */
4080 static void gen_dcba(DisasContext *ctx)
4081 {
4082 /* interpreted as no-op */
4083 /* XXX: specification say this is treated as a store by the MMU
4084 * but does not generate any exception
4085 */
4086 }
4087
4088 /*** Segment register manipulation ***/
4089 /* Supervisor only: */
4090
4091 /* mfsr */
4092 static void gen_mfsr(DisasContext *ctx)
4093 {
4094 #if defined(CONFIG_USER_ONLY)
4095 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4096 #else
4097 TCGv t0;
4098 if (unlikely(!ctx->mem_idx)) {
4099 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4100 return;
4101 }
4102 t0 = tcg_const_tl(SR(ctx->opcode));
4103 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4104 tcg_temp_free(t0);
4105 #endif
4106 }
4107
4108 /* mfsrin */
4109 static void gen_mfsrin(DisasContext *ctx)
4110 {
4111 #if defined(CONFIG_USER_ONLY)
4112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4113 #else
4114 TCGv t0;
4115 if (unlikely(!ctx->mem_idx)) {
4116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4117 return;
4118 }
4119 t0 = tcg_temp_new();
4120 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4121 tcg_gen_andi_tl(t0, t0, 0xF);
4122 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4123 tcg_temp_free(t0);
4124 #endif
4125 }
4126
4127 /* mtsr */
4128 static void gen_mtsr(DisasContext *ctx)
4129 {
4130 #if defined(CONFIG_USER_ONLY)
4131 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4132 #else
4133 TCGv t0;
4134 if (unlikely(!ctx->mem_idx)) {
4135 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4136 return;
4137 }
4138 t0 = tcg_const_tl(SR(ctx->opcode));
4139 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4140 tcg_temp_free(t0);
4141 #endif
4142 }
4143
4144 /* mtsrin */
4145 static void gen_mtsrin(DisasContext *ctx)
4146 {
4147 #if defined(CONFIG_USER_ONLY)
4148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4149 #else
4150 TCGv t0;
4151 if (unlikely(!ctx->mem_idx)) {
4152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4153 return;
4154 }
4155 t0 = tcg_temp_new();
4156 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4157 tcg_gen_andi_tl(t0, t0, 0xF);
4158 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4159 tcg_temp_free(t0);
4160 #endif
4161 }
4162
4163 #if defined(TARGET_PPC64)
4164 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4165
4166 /* mfsr */
4167 static void gen_mfsr_64b(DisasContext *ctx)
4168 {
4169 #if defined(CONFIG_USER_ONLY)
4170 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4171 #else
4172 TCGv t0;
4173 if (unlikely(!ctx->mem_idx)) {
4174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4175 return;
4176 }
4177 t0 = tcg_const_tl(SR(ctx->opcode));
4178 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4179 tcg_temp_free(t0);
4180 #endif
4181 }
4182
4183 /* mfsrin */
4184 static void gen_mfsrin_64b(DisasContext *ctx)
4185 {
4186 #if defined(CONFIG_USER_ONLY)
4187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4188 #else
4189 TCGv t0;
4190 if (unlikely(!ctx->mem_idx)) {
4191 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4192 return;
4193 }
4194 t0 = tcg_temp_new();
4195 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4196 tcg_gen_andi_tl(t0, t0, 0xF);
4197 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4198 tcg_temp_free(t0);
4199 #endif
4200 }
4201
4202 /* mtsr */
4203 static void gen_mtsr_64b(DisasContext *ctx)
4204 {
4205 #if defined(CONFIG_USER_ONLY)
4206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4207 #else
4208 TCGv t0;
4209 if (unlikely(!ctx->mem_idx)) {
4210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4211 return;
4212 }
4213 t0 = tcg_const_tl(SR(ctx->opcode));
4214 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4215 tcg_temp_free(t0);
4216 #endif
4217 }
4218
4219 /* mtsrin */
4220 static void gen_mtsrin_64b(DisasContext *ctx)
4221 {
4222 #if defined(CONFIG_USER_ONLY)
4223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4224 #else
4225 TCGv t0;
4226 if (unlikely(!ctx->mem_idx)) {
4227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4228 return;
4229 }
4230 t0 = tcg_temp_new();
4231 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4232 tcg_gen_andi_tl(t0, t0, 0xF);
4233 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4234 tcg_temp_free(t0);
4235 #endif
4236 }
4237
4238 /* slbmte */
4239 static void gen_slbmte(DisasContext *ctx)
4240 {
4241 #if defined(CONFIG_USER_ONLY)
4242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4243 #else
4244 if (unlikely(!ctx->mem_idx)) {
4245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4246 return;
4247 }
4248 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4249 cpu_gpr[rS(ctx->opcode)]);
4250 #endif
4251 }
4252
4253 static void gen_slbmfee(DisasContext *ctx)
4254 {
4255 #if defined(CONFIG_USER_ONLY)
4256 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4257 #else
4258 if (unlikely(!ctx->mem_idx)) {
4259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4260 return;
4261 }
4262 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4263 cpu_gpr[rB(ctx->opcode)]);
4264 #endif
4265 }
4266
4267 static void gen_slbmfev(DisasContext *ctx)
4268 {
4269 #if defined(CONFIG_USER_ONLY)
4270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4271 #else
4272 if (unlikely(!ctx->mem_idx)) {
4273 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4274 return;
4275 }
4276 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4277 cpu_gpr[rB(ctx->opcode)]);
4278 #endif
4279 }
4280 #endif /* defined(TARGET_PPC64) */
4281
4282 /*** Lookaside buffer management ***/
4283 /* Optional & mem_idx only: */
4284
4285 /* tlbia */
4286 static void gen_tlbia(DisasContext *ctx)
4287 {
4288 #if defined(CONFIG_USER_ONLY)
4289 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4290 #else
4291 if (unlikely(!ctx->mem_idx)) {
4292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4293 return;
4294 }
4295 gen_helper_tlbia(cpu_env);
4296 #endif
4297 }
4298
4299 /* tlbiel */
4300 static void gen_tlbiel(DisasContext *ctx)
4301 {
4302 #if defined(CONFIG_USER_ONLY)
4303 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4304 #else
4305 if (unlikely(!ctx->mem_idx)) {
4306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4307 return;
4308 }
4309 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4310 #endif
4311 }
4312
4313 /* tlbie */
4314 static void gen_tlbie(DisasContext *ctx)
4315 {
4316 #if defined(CONFIG_USER_ONLY)
4317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4318 #else
4319 if (unlikely(!ctx->mem_idx)) {
4320 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4321 return;
4322 }
4323 if (NARROW_MODE(ctx)) {
4324 TCGv t0 = tcg_temp_new();
4325 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4326 gen_helper_tlbie(cpu_env, t0);
4327 tcg_temp_free(t0);
4328 } else {
4329 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4330 }
4331 #endif
4332 }
4333
4334 /* tlbsync */
4335 static void gen_tlbsync(DisasContext *ctx)
4336 {
4337 #if defined(CONFIG_USER_ONLY)
4338 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4339 #else
4340 if (unlikely(!ctx->mem_idx)) {
4341 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4342 return;
4343 }
4344 /* This has no effect: it should ensure that all previous
4345 * tlbie have completed
4346 */
4347 gen_stop_exception(ctx);
4348 #endif
4349 }
4350
4351 #if defined(TARGET_PPC64)
4352 /* slbia */
4353 static void gen_slbia(DisasContext *ctx)
4354 {
4355 #if defined(CONFIG_USER_ONLY)
4356 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4357 #else
4358 if (unlikely(!ctx->mem_idx)) {
4359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4360 return;
4361 }
4362 gen_helper_slbia(cpu_env);
4363 #endif
4364 }
4365
4366 /* slbie */
4367 static void gen_slbie(DisasContext *ctx)
4368 {
4369 #if defined(CONFIG_USER_ONLY)
4370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4371 #else
4372 if (unlikely(!ctx->mem_idx)) {
4373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4374 return;
4375 }
4376 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4377 #endif
4378 }
4379 #endif
4380
4381 /*** External control ***/
4382 /* Optional: */
4383
4384 /* eciwx */
4385 static void gen_eciwx(DisasContext *ctx)
4386 {
4387 TCGv t0;
4388 /* Should check EAR[E] ! */
4389 gen_set_access_type(ctx, ACCESS_EXT);
4390 t0 = tcg_temp_new();
4391 gen_addr_reg_index(ctx, t0);
4392 gen_check_align(ctx, t0, 0x03);
4393 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4394 tcg_temp_free(t0);
4395 }
4396
4397 /* ecowx */
4398 static void gen_ecowx(DisasContext *ctx)
4399 {
4400 TCGv t0;
4401 /* Should check EAR[E] ! */
4402 gen_set_access_type(ctx, ACCESS_EXT);
4403 t0 = tcg_temp_new();
4404 gen_addr_reg_index(ctx, t0);
4405 gen_check_align(ctx, t0, 0x03);
4406 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4407 tcg_temp_free(t0);
4408 }
4409
4410 /* PowerPC 601 specific instructions */
4411
4412 /* abs - abs. */
4413 static void gen_abs(DisasContext *ctx)
4414 {
4415 int l1 = gen_new_label();
4416 int l2 = gen_new_label();
4417 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4418 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4419 tcg_gen_br(l2);
4420 gen_set_label(l1);
4421 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4422 gen_set_label(l2);
4423 if (unlikely(Rc(ctx->opcode) != 0))
4424 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4425 }
4426
4427 /* abso - abso. */
4428 static void gen_abso(DisasContext *ctx)
4429 {
4430 int l1 = gen_new_label();
4431 int l2 = gen_new_label();
4432 int l3 = gen_new_label();
4433 /* Start with XER OV disabled, the most likely case */
4434 tcg_gen_movi_tl(cpu_ov, 0);
4435 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4436 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4437 tcg_gen_movi_tl(cpu_ov, 1);
4438 tcg_gen_movi_tl(cpu_so, 1);
4439 tcg_gen_br(l2);
4440 gen_set_label(l1);
4441 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4442 tcg_gen_br(l3);
4443 gen_set_label(l2);
4444 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4445 gen_set_label(l3);
4446 if (unlikely(Rc(ctx->opcode) != 0))
4447 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4448 }
4449
4450 /* clcs */
4451 static void gen_clcs(DisasContext *ctx)
4452 {
4453 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4454 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4455 tcg_temp_free_i32(t0);
4456 /* Rc=1 sets CR0 to an undefined state */
4457 }
4458
4459 /* div - div. */
4460 static void gen_div(DisasContext *ctx)
4461 {
4462 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4463 cpu_gpr[rB(ctx->opcode)]);
4464 if (unlikely(Rc(ctx->opcode) != 0))
4465 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4466 }
4467
4468 /* divo - divo. */
4469 static void gen_divo(DisasContext *ctx)
4470 {
4471 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4472 cpu_gpr[rB(ctx->opcode)]);
4473 if (unlikely(Rc(ctx->opcode) != 0))
4474 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4475 }
4476
4477 /* divs - divs. */
4478 static void gen_divs(DisasContext *ctx)
4479 {
4480 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4481 cpu_gpr[rB(ctx->opcode)]);
4482 if (unlikely(Rc(ctx->opcode) != 0))
4483 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4484 }
4485
4486 /* divso - divso. */
4487 static void gen_divso(DisasContext *ctx)
4488 {
4489 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4490 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4491 if (unlikely(Rc(ctx->opcode) != 0))
4492 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4493 }
4494
4495 /* doz - doz. */
4496 static void gen_doz(DisasContext *ctx)
4497 {
4498 int l1 = gen_new_label();
4499 int l2 = gen_new_label();
4500 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4501 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4502 tcg_gen_br(l2);
4503 gen_set_label(l1);
4504 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4505 gen_set_label(l2);
4506 if (unlikely(Rc(ctx->opcode) != 0))
4507 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4508 }
4509
4510 /* dozo - dozo. */
4511 static void gen_dozo(DisasContext *ctx)
4512 {
4513 int l1 = gen_new_label();
4514 int l2 = gen_new_label();
4515 TCGv t0 = tcg_temp_new();
4516 TCGv t1 = tcg_temp_new();
4517 TCGv t2 = tcg_temp_new();
4518 /* Start with XER OV disabled, the most likely case */
4519 tcg_gen_movi_tl(cpu_ov, 0);
4520 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4521 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4522 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4523 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4524 tcg_gen_andc_tl(t1, t1, t2);
4525 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4526 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4527 tcg_gen_movi_tl(cpu_ov, 1);
4528 tcg_gen_movi_tl(cpu_so, 1);
4529 tcg_gen_br(l2);
4530 gen_set_label(l1);
4531 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4532 gen_set_label(l2);
4533 tcg_temp_free(t0);
4534 tcg_temp_free(t1);
4535 tcg_temp_free(t2);
4536 if (unlikely(Rc(ctx->opcode) != 0))
4537 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4538 }
4539
4540 /* dozi */
4541 static void gen_dozi(DisasContext *ctx)
4542 {
4543 target_long simm = SIMM(ctx->opcode);
4544 int l1 = gen_new_label();
4545 int l2 = gen_new_label();
4546 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4547 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4548 tcg_gen_br(l2);
4549 gen_set_label(l1);
4550 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4551 gen_set_label(l2);
4552 if (unlikely(Rc(ctx->opcode) != 0))
4553 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4554 }
4555
4556 /* lscbx - lscbx. */
4557 static void gen_lscbx(DisasContext *ctx)
4558 {
4559 TCGv t0 = tcg_temp_new();
4560 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4561 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4562 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4563
4564 gen_addr_reg_index(ctx, t0);
4565 /* NIP cannot be restored if the memory exception comes from an helper */
4566 gen_update_nip(ctx, ctx->nip - 4);
4567 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4568 tcg_temp_free_i32(t1);
4569 tcg_temp_free_i32(t2);
4570 tcg_temp_free_i32(t3);
4571 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4572 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4573 if (unlikely(Rc(ctx->opcode) != 0))
4574 gen_set_Rc0(ctx, t0);
4575 tcg_temp_free(t0);
4576 }
4577
4578 /* maskg - maskg. */
4579 static void gen_maskg(DisasContext *ctx)
4580 {
4581 int l1 = gen_new_label();
4582 TCGv t0 = tcg_temp_new();
4583 TCGv t1 = tcg_temp_new();
4584 TCGv t2 = tcg_temp_new();
4585 TCGv t3 = tcg_temp_new();
4586 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4587 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4588 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4589 tcg_gen_addi_tl(t2, t0, 1);
4590 tcg_gen_shr_tl(t2, t3, t2);
4591 tcg_gen_shr_tl(t3, t3, t1);
4592 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4593 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4594 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4595 gen_set_label(l1);
4596 tcg_temp_free(t0);
4597 tcg_temp_free(t1);
4598 tcg_temp_free(t2);
4599 tcg_temp_free(t3);
4600 if (unlikely(Rc(ctx->opcode) != 0))
4601 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4602 }
4603
4604 /* maskir - maskir. */
4605 static void gen_maskir(DisasContext *ctx)
4606 {
4607 TCGv t0 = tcg_temp_new();
4608 TCGv t1 = tcg_temp_new();
4609 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4610 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4611 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4612 tcg_temp_free(t0);
4613 tcg_temp_free(t1);
4614 if (unlikely(Rc(ctx->opcode) != 0))
4615 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4616 }
4617
4618 /* mul - mul. */
4619 static void gen_mul(DisasContext *ctx)
4620 {
4621 TCGv_i64 t0 = tcg_temp_new_i64();
4622 TCGv_i64 t1 = tcg_temp_new_i64();
4623 TCGv t2 = tcg_temp_new();
4624 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4625 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4626 tcg_gen_mul_i64(t0, t0, t1);
4627 tcg_gen_trunc_i64_tl(t2, t0);
4628 gen_store_spr(SPR_MQ, t2);
4629 tcg_gen_shri_i64(t1, t0, 32);
4630 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4631 tcg_temp_free_i64(t0);
4632 tcg_temp_free_i64(t1);
4633 tcg_temp_free(t2);
4634 if (unlikely(Rc(ctx->opcode) != 0))
4635 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4636 }
4637
4638 /* mulo - mulo. */
4639 static void gen_mulo(DisasContext *ctx)
4640 {
4641 int l1 = gen_new_label();
4642 TCGv_i64 t0 = tcg_temp_new_i64();
4643 TCGv_i64 t1 = tcg_temp_new_i64();
4644 TCGv t2 = tcg_temp_new();
4645 /* Start with XER OV disabled, the most likely case */
4646 tcg_gen_movi_tl(cpu_ov, 0);
4647 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4648 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4649 tcg_gen_mul_i64(t0, t0, t1);
4650 tcg_gen_trunc_i64_tl(t2, t0);
4651 gen_store_spr(SPR_MQ, t2);
4652 tcg_gen_shri_i64(t1, t0, 32);
4653 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4654 tcg_gen_ext32s_i64(t1, t0);
4655 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4656 tcg_gen_movi_tl(cpu_ov, 1);
4657 tcg_gen_movi_tl(cpu_so, 1);
4658 gen_set_label(l1);
4659 tcg_temp_free_i64(t0);
4660 tcg_temp_free_i64(t1);
4661 tcg_temp_free(t2);
4662 if (unlikely(Rc(ctx->opcode) != 0))
4663 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4664 }
4665
4666 /* nabs - nabs. */
4667 static void gen_nabs(DisasContext *ctx)
4668 {
4669 int l1 = gen_new_label();
4670 int l2 = gen_new_label();
4671 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4672 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4673 tcg_gen_br(l2);
4674 gen_set_label(l1);
4675 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4676 gen_set_label(l2);
4677 if (unlikely(Rc(ctx->opcode) != 0))
4678 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4679 }
4680
4681 /* nabso - nabso. */
4682 static void gen_nabso(DisasContext *ctx)
4683 {
4684 int l1 = gen_new_label();
4685 int l2 = gen_new_label();
4686 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4687 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4688 tcg_gen_br(l2);
4689 gen_set_label(l1);
4690 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4691 gen_set_label(l2);
4692 /* nabs never overflows */
4693 tcg_gen_movi_tl(cpu_ov, 0);
4694 if (unlikely(Rc(ctx->opcode) != 0))
4695 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4696 }
4697
4698 /* rlmi - rlmi. */
4699 static void gen_rlmi(DisasContext *ctx)
4700 {
4701 uint32_t mb = MB(ctx->opcode);
4702 uint32_t me = ME(ctx->opcode);
4703 TCGv t0 = tcg_temp_new();
4704 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4705 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4706 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4707 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4708 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4709 tcg_temp_free(t0);
4710 if (unlikely(Rc(ctx->opcode) != 0))
4711 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4712 }
4713
4714 /* rrib - rrib. */
4715 static void gen_rrib(DisasContext *ctx)
4716 {
4717 TCGv t0 = tcg_temp_new();
4718 TCGv t1 = tcg_temp_new();
4719 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4720 tcg_gen_movi_tl(t1, 0x80000000);
4721 tcg_gen_shr_tl(t1, t1, t0);
4722 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4723 tcg_gen_and_tl(t0, t0, t1);
4724 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4725 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4726 tcg_temp_free(t0);
4727 tcg_temp_free(t1);
4728 if (unlikely(Rc(ctx->opcode) != 0))
4729 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4730 }
4731
4732 /* sle - sle. */
4733 static void gen_sle(DisasContext *ctx)
4734 {
4735 TCGv t0 = tcg_temp_new();
4736 TCGv t1 = tcg_temp_new();
4737 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4738 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4739 tcg_gen_subfi_tl(t1, 32, t1);
4740 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4741 tcg_gen_or_tl(t1, t0, t1);
4742 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4743 gen_store_spr(SPR_MQ, t1);
4744 tcg_temp_free(t0);
4745 tcg_temp_free(t1);
4746 if (unlikely(Rc(ctx->opcode) != 0))
4747 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4748 }
4749
4750 /* sleq - sleq. */
4751 static void gen_sleq(DisasContext *ctx)
4752 {
4753 TCGv t0 = tcg_temp_new();
4754 TCGv t1 = tcg_temp_new();
4755 TCGv t2 = tcg_temp_new();
4756 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4757 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4758 tcg_gen_shl_tl(t2, t2, t0);
4759 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4760 gen_load_spr(t1, SPR_MQ);
4761 gen_store_spr(SPR_MQ, t0);
4762 tcg_gen_and_tl(t0, t0, t2);
4763 tcg_gen_andc_tl(t1, t1, t2);
4764 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4765 tcg_temp_free(t0);
4766 tcg_temp_free(t1);
4767 tcg_temp_free(t2);
4768 if (unlikely(Rc(ctx->opcode) != 0))
4769 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4770 }
4771
4772 /* sliq - sliq. */
4773 static void gen_sliq(DisasContext *ctx)
4774 {
4775 int sh = SH(ctx->opcode);
4776 TCGv t0 = tcg_temp_new();
4777 TCGv t1 = tcg_temp_new();
4778 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4779 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4780 tcg_gen_or_tl(t1, t0, t1);
4781 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4782 gen_store_spr(SPR_MQ, t1);
4783 tcg_temp_free(t0);
4784 tcg_temp_free(t1);
4785 if (unlikely(Rc(ctx->opcode) != 0))
4786 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4787 }
4788
4789 /* slliq - slliq. */
4790 static void gen_slliq(DisasContext *ctx)
4791 {
4792 int sh = SH(ctx->opcode);
4793 TCGv t0 = tcg_temp_new();
4794 TCGv t1 = tcg_temp_new();
4795 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4796 gen_load_spr(t1, SPR_MQ);
4797 gen_store_spr(SPR_MQ, t0);
4798 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4799 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4800 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4801 tcg_temp_free(t0);
4802 tcg_temp_free(t1);
4803 if (unlikely(Rc(ctx->opcode) != 0))
4804 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4805 }
4806
4807 /* sllq - sllq. */
4808 static void gen_sllq(DisasContext *ctx)
4809 {
4810 int l1 = gen_new_label();
4811 int l2 = gen_new_label();
4812 TCGv t0 = tcg_temp_local_new();
4813 TCGv t1 = tcg_temp_local_new();
4814 TCGv t2 = tcg_temp_local_new();
4815 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4816 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4817 tcg_gen_shl_tl(t1, t1, t2);
4818 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4819 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4820 gen_load_spr(t0, SPR_MQ);
4821 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4822 tcg_gen_br(l2);
4823 gen_set_label(l1);
4824 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4825 gen_load_spr(t2, SPR_MQ);
4826 tcg_gen_andc_tl(t1, t2, t1);
4827 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4828 gen_set_label(l2);
4829 tcg_temp_free(t0);
4830 tcg_temp_free(t1);
4831 tcg_temp_free(t2);
4832 if (unlikely(Rc(ctx->opcode) != 0))
4833 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4834 }
4835
4836 /* slq - slq. */
4837 static void gen_slq(DisasContext *ctx)
4838 {
4839 int l1 = gen_new_label();
4840 TCGv t0 = tcg_temp_new();
4841 TCGv t1 = tcg_temp_new();
4842 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4843 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4844 tcg_gen_subfi_tl(t1, 32, t1);
4845 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4846 tcg_gen_or_tl(t1, t0, t1);
4847 gen_store_spr(SPR_MQ, t1);
4848 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4849 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4850 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4851 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4852 gen_set_label(l1);
4853 tcg_temp_free(t0);
4854 tcg_temp_free(t1);
4855 if (unlikely(Rc(ctx->opcode) != 0))
4856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4857 }
4858
4859 /* sraiq - sraiq. */
4860 static void gen_sraiq(DisasContext *ctx)
4861 {
4862 int sh = SH(ctx->opcode);
4863 int l1 = gen_new_label();
4864 TCGv t0 = tcg_temp_new();
4865 TCGv t1 = tcg_temp_new();
4866 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4867 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4868 tcg_gen_or_tl(t0, t0, t1);
4869 gen_store_spr(SPR_MQ, t0);
4870 tcg_gen_movi_tl(cpu_ca, 0);
4871 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4872 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4873 tcg_gen_movi_tl(cpu_ca, 1);
4874 gen_set_label(l1);
4875 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4876 tcg_temp_free(t0);
4877 tcg_temp_free(t1);
4878 if (unlikely(Rc(ctx->opcode) != 0))
4879 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4880 }
4881
4882 /* sraq - sraq. */
4883 static void gen_sraq(DisasContext *ctx)
4884 {
4885 int l1 = gen_new_label();
4886 int l2 = gen_new_label();
4887 TCGv t0 = tcg_temp_new();
4888 TCGv t1 = tcg_temp_local_new();
4889 TCGv t2 = tcg_temp_local_new();
4890 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4891 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4892 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4893 tcg_gen_subfi_tl(t2, 32, t2);
4894 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4895 tcg_gen_or_tl(t0, t0, t2);
4896 gen_store_spr(SPR_MQ, t0);
4897 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4898 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4899 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4900 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4901 gen_set_label(l1);
4902 tcg_temp_free(t0);
4903 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4904 tcg_gen_movi_tl(cpu_ca, 0);
4905 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4906 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4907 tcg_gen_movi_tl(cpu_ca, 1);
4908 gen_set_label(l2);
4909 tcg_temp_free(t1);
4910 tcg_temp_free(t2);
4911 if (unlikely(Rc(ctx->opcode) != 0))
4912 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4913 }
4914
4915 /* sre - sre. */
4916 static void gen_sre(DisasContext *ctx)
4917 {
4918 TCGv t0 = tcg_temp_new();
4919 TCGv t1 = tcg_temp_new();
4920 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4921 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4922 tcg_gen_subfi_tl(t1, 32, t1);
4923 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4924 tcg_gen_or_tl(t1, t0, t1);
4925 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4926 gen_store_spr(SPR_MQ, t1);
4927 tcg_temp_free(t0);
4928 tcg_temp_free(t1);
4929 if (unlikely(Rc(ctx->opcode) != 0))
4930 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4931 }
4932
4933 /* srea - srea. */
4934 static void gen_srea(DisasContext *ctx)
4935 {
4936 TCGv t0 = tcg_temp_new();
4937 TCGv t1 = tcg_temp_new();
4938 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4939 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4940 gen_store_spr(SPR_MQ, t0);
4941 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4942 tcg_temp_free(t0);
4943 tcg_temp_free(t1);
4944 if (unlikely(Rc(ctx->opcode) != 0))
4945 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4946 }
4947
4948 /* sreq */
4949 static void gen_sreq(DisasContext *ctx)
4950 {
4951 TCGv t0 = tcg_temp_new();
4952 TCGv t1 = tcg_temp_new();
4953 TCGv t2 = tcg_temp_new();
4954 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4955 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4956 tcg_gen_shr_tl(t1, t1, t0);
4957 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4958 gen_load_spr(t2, SPR_MQ);
4959 gen_store_spr(SPR_MQ, t0);
4960 tcg_gen_and_tl(t0, t0, t1);
4961 tcg_gen_andc_tl(t2, t2, t1);
4962 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4963 tcg_temp_free(t0);
4964 tcg_temp_free(t1);
4965 tcg_temp_free(t2);
4966 if (unlikely(Rc(ctx->opcode) != 0))
4967 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4968 }
4969
4970 /* sriq */
4971 static void gen_sriq(DisasContext *ctx)
4972 {
4973 int sh = SH(ctx->opcode);
4974 TCGv t0 = tcg_temp_new();
4975 TCGv t1 = tcg_temp_new();
4976 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4977 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4978 tcg_gen_or_tl(t1, t0, t1);
4979 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4980 gen_store_spr(SPR_MQ, t1);
4981 tcg_temp_free(t0);
4982 tcg_temp_free(t1);
4983 if (unlikely(Rc(ctx->opcode) != 0))
4984 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4985 }
4986
4987 /* srliq */
4988 static void gen_srliq(DisasContext *ctx)
4989 {
4990 int sh = SH(ctx->opcode);
4991 TCGv t0 = tcg_temp_new();
4992 TCGv t1 = tcg_temp_new();
4993 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4994 gen_load_spr(t1, SPR_MQ);
4995 gen_store_spr(SPR_MQ, t0);
4996 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
4997 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
4998 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4999 tcg_temp_free(t0);
5000 tcg_temp_free(t1);
5001 if (unlikely(Rc(ctx->opcode) != 0))
5002 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5003 }
5004
5005 /* srlq */
5006 static void gen_srlq(DisasContext *ctx)
5007 {
5008 int l1 = gen_new_label();
5009 int l2 = gen_new_label();
5010 TCGv t0 = tcg_temp_local_new();
5011 TCGv t1 = tcg_temp_local_new();
5012 TCGv t2 = tcg_temp_local_new();
5013 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5014 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5015 tcg_gen_shr_tl(t2, t1, t2);
5016 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5017 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5018 gen_load_spr(t0, SPR_MQ);
5019 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5020 tcg_gen_br(l2);
5021 gen_set_label(l1);
5022 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5023 tcg_gen_and_tl(t0, t0, t2);
5024 gen_load_spr(t1, SPR_MQ);
5025 tcg_gen_andc_tl(t1, t1, t2);
5026 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5027 gen_set_label(l2);
5028 tcg_temp_free(t0);
5029 tcg_temp_free(t1);
5030 tcg_temp_free(t2);
5031 if (unlikely(Rc(ctx->opcode) != 0))
5032 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5033 }
5034
5035 /* srq */
5036 static void gen_srq(DisasContext *ctx)
5037 {
5038 int l1 = gen_new_label();
5039 TCGv t0 = tcg_temp_new();
5040 TCGv t1 = tcg_temp_new();
5041 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5042 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5043 tcg_gen_subfi_tl(t1, 32, t1);
5044 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5045 tcg_gen_or_tl(t1, t0, t1);
5046 gen_store_spr(SPR_MQ, t1);
5047 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5048 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5049 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5050 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5051 gen_set_label(l1);
5052 tcg_temp_free(t0);
5053 tcg_temp_free(t1);
5054 if (unlikely(Rc(ctx->opcode) != 0))
5055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5056 }
5057
5058 /* PowerPC 602 specific instructions */
5059
5060 /* dsa */
5061 static void gen_dsa(DisasContext *ctx)
5062 {
5063 /* XXX: TODO */
5064 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5065 }
5066
5067 /* esa */
5068 static void gen_esa(DisasContext *ctx)
5069 {
5070 /* XXX: TODO */
5071 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5072 }
5073
5074 /* mfrom */
5075 static void gen_mfrom(DisasContext *ctx)
5076 {
5077 #if defined(CONFIG_USER_ONLY)
5078 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5079 #else
5080 if (unlikely(!ctx->mem_idx)) {
5081 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5082 return;
5083 }
5084 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5085 #endif
5086 }
5087
5088 /* 602 - 603 - G2 TLB management */
5089
5090 /* tlbld */
5091 static void gen_tlbld_6xx(DisasContext *ctx)
5092 {
5093 #if defined(CONFIG_USER_ONLY)
5094 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5095 #else
5096 if (unlikely(!ctx->mem_idx)) {
5097 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5098 return;
5099 }
5100 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5101 #endif
5102 }
5103
5104 /* tlbli */
5105 static void gen_tlbli_6xx(DisasContext *ctx)
5106 {
5107 #if defined(CONFIG_USER_ONLY)
5108 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5109 #else
5110 if (unlikely(!ctx->mem_idx)) {
5111 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5112 return;
5113 }
5114 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5115 #endif
5116 }
5117
5118 /* 74xx TLB management */
5119
5120 /* tlbld */
5121 static void gen_tlbld_74xx(DisasContext *ctx)
5122 {
5123 #if defined(CONFIG_USER_ONLY)
5124 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5125 #else
5126 if (unlikely(!ctx->mem_idx)) {
5127 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5128 return;
5129 }
5130 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5131 #endif
5132 }
5133
5134 /* tlbli */
5135 static void gen_tlbli_74xx(DisasContext *ctx)
5136 {
5137 #if defined(CONFIG_USER_ONLY)
5138 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5139 #else
5140 if (unlikely(!ctx->mem_idx)) {
5141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5142 return;
5143 }
5144 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5145 #endif
5146 }
5147
5148 /* POWER instructions not in PowerPC 601 */
5149
5150 /* clf */
5151 static void gen_clf(DisasContext *ctx)
5152 {
5153 /* Cache line flush: implemented as no-op */
5154 }
5155
5156 /* cli */
5157 static void gen_cli(DisasContext *ctx)
5158 {
5159 /* Cache line invalidate: privileged and treated as no-op */
5160 #if defined(CONFIG_USER_ONLY)
5161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5162 #else
5163 if (unlikely(!ctx->mem_idx)) {
5164 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5165 return;
5166 }
5167 #endif
5168 }
5169
5170 /* dclst */
5171 static void gen_dclst(DisasContext *ctx)
5172 {
5173 /* Data cache line store: treated as no-op */
5174 }
5175
5176 static void gen_mfsri(DisasContext *ctx)
5177 {
5178 #if defined(CONFIG_USER_ONLY)
5179 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5180 #else
5181 int ra = rA(ctx->opcode);
5182 int rd = rD(ctx->opcode);
5183 TCGv t0;
5184 if (unlikely(!ctx->mem_idx)) {
5185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5186 return;
5187 }
5188 t0 = tcg_temp_new();
5189 gen_addr_reg_index(ctx, t0);
5190 tcg_gen_shri_tl(t0, t0, 28);
5191 tcg_gen_andi_tl(t0, t0, 0xF);
5192 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5193 tcg_temp_free(t0);
5194 if (ra != 0 && ra != rd)
5195 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5196 #endif
5197 }
5198
5199 static void gen_rac(DisasContext *ctx)
5200 {
5201 #if defined(CONFIG_USER_ONLY)
5202 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5203 #else
5204 TCGv t0;
5205 if (unlikely(!ctx->mem_idx)) {
5206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5207 return;
5208 }
5209 t0 = tcg_temp_new();
5210 gen_addr_reg_index(ctx, t0);
5211 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5212 tcg_temp_free(t0);
5213 #endif
5214 }
5215
5216 static void gen_rfsvc(DisasContext *ctx)
5217 {
5218 #if defined(CONFIG_USER_ONLY)
5219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5220 #else
5221 if (unlikely(!ctx->mem_idx)) {
5222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5223 return;
5224 }
5225 gen_helper_rfsvc(cpu_env);
5226 gen_sync_exception(ctx);
5227 #endif
5228 }
5229
5230 /* svc is not implemented for now */
5231
5232 /* POWER2 specific instructions */
5233 /* Quad manipulation (load/store two floats at a time) */
5234
5235 /* lfq */
5236 static void gen_lfq(DisasContext *ctx)
5237 {
5238 int rd = rD(ctx->opcode);
5239 TCGv t0;
5240 gen_set_access_type(ctx, ACCESS_FLOAT);
5241 t0 = tcg_temp_new();
5242 gen_addr_imm_index(ctx, t0, 0);
5243 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5244 gen_addr_add(ctx, t0, t0, 8);
5245 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5246 tcg_temp_free(t0);
5247 }
5248
5249 /* lfqu */
5250 static void gen_lfqu(DisasContext *ctx)
5251 {
5252 int ra = rA(ctx->opcode);
5253 int rd = rD(ctx->opcode);
5254 TCGv t0, t1;
5255 gen_set_access_type(ctx, ACCESS_FLOAT);
5256 t0 = tcg_temp_new();
5257 t1 = tcg_temp_new();
5258 gen_addr_imm_index(ctx, t0, 0);
5259 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5260 gen_addr_add(ctx, t1, t0, 8);
5261 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5262 if (ra != 0)
5263 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5264 tcg_temp_free(t0);
5265 tcg_temp_free(t1);
5266 }
5267
5268 /* lfqux */
5269 static void gen_lfqux(DisasContext *ctx)
5270 {
5271 int ra = rA(ctx->opcode);
5272 int rd = rD(ctx->opcode);
5273 gen_set_access_type(ctx, ACCESS_FLOAT);
5274 TCGv t0, t1;
5275 t0 = tcg_temp_new();
5276 gen_addr_reg_index(ctx, t0);
5277 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5278 t1 = tcg_temp_new();
5279 gen_addr_add(ctx, t1, t0, 8);
5280 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5281 tcg_temp_free(t1);
5282 if (ra != 0)
5283 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5284 tcg_temp_free(t0);
5285 }
5286
5287 /* lfqx */
5288 static void gen_lfqx(DisasContext *ctx)
5289 {
5290 int rd = rD(ctx->opcode);
5291 TCGv t0;
5292 gen_set_access_type(ctx, ACCESS_FLOAT);
5293 t0 = tcg_temp_new();
5294 gen_addr_reg_index(ctx, t0);
5295 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5296 gen_addr_add(ctx, t0, t0, 8);
5297 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5298 tcg_temp_free(t0);
5299 }
5300
5301 /* stfq */
5302 static void gen_stfq(DisasContext *ctx)
5303 {
5304 int rd = rD(ctx->opcode);
5305 TCGv t0;
5306 gen_set_access_type(ctx, ACCESS_FLOAT);
5307 t0 = tcg_temp_new();
5308 gen_addr_imm_index(ctx, t0, 0);
5309 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5310 gen_addr_add(ctx, t0, t0, 8);
5311 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5312 tcg_temp_free(t0);
5313 }
5314
5315 /* stfqu */
5316 static void gen_stfqu(DisasContext *ctx)
5317 {
5318 int ra = rA(ctx->opcode);
5319 int rd = rD(ctx->opcode);
5320 TCGv t0, t1;
5321 gen_set_access_type(ctx, ACCESS_FLOAT);
5322 t0 = tcg_temp_new();
5323 gen_addr_imm_index(ctx, t0, 0);
5324 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5325 t1 = tcg_temp_new();
5326 gen_addr_add(ctx, t1, t0, 8);
5327 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5328 tcg_temp_free(t1);
5329 if (ra != 0)
5330 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5331 tcg_temp_free(t0);
5332 }
5333
5334 /* stfqux */
5335 static void gen_stfqux(DisasContext *ctx)
5336 {
5337 int ra = rA(ctx->opcode);
5338 int rd = rD(ctx->opcode);
5339 TCGv t0, t1;
5340 gen_set_access_type(ctx, ACCESS_FLOAT);
5341 t0 = tcg_temp_new();
5342 gen_addr_reg_index(ctx, t0);
5343 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5344 t1 = tcg_temp_new();
5345 gen_addr_add(ctx, t1, t0, 8);
5346 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5347 tcg_temp_free(t1);
5348 if (ra != 0)
5349 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5350 tcg_temp_free(t0);
5351 }
5352
5353 /* stfqx */
5354 static void gen_stfqx(DisasContext *ctx)
5355 {
5356 int rd = rD(ctx->opcode);
5357 TCGv t0;
5358 gen_set_access_type(ctx, ACCESS_FLOAT);
5359 t0 = tcg_temp_new();
5360 gen_addr_reg_index(ctx, t0);
5361 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5362 gen_addr_add(ctx, t0, t0, 8);
5363 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5364 tcg_temp_free(t0);
5365 }
5366
5367 /* BookE specific instructions */
5368
5369 /* XXX: not implemented on 440 ? */
5370 static void gen_mfapidi(DisasContext *ctx)
5371 {
5372 /* XXX: TODO */
5373 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5374 }
5375
5376 /* XXX: not implemented on 440 ? */
5377 static void gen_tlbiva(DisasContext *ctx)
5378 {
5379 #if defined(CONFIG_USER_ONLY)
5380 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5381 #else
5382 TCGv t0;
5383 if (unlikely(!ctx->mem_idx)) {
5384 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5385 return;
5386 }
5387 t0 = tcg_temp_new();
5388 gen_addr_reg_index(ctx, t0);
5389 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5390 tcg_temp_free(t0);
5391 #endif
5392 }
5393
5394 /* All 405 MAC instructions are translated here */
5395 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5396 int ra, int rb, int rt, int Rc)
5397 {
5398 TCGv t0, t1;
5399
5400 t0 = tcg_temp_local_new();
5401 t1 = tcg_temp_local_new();
5402
5403 switch (opc3 & 0x0D) {
5404 case 0x05:
5405 /* macchw - macchw. - macchwo - macchwo. */
5406 /* macchws - macchws. - macchwso - macchwso. */
5407 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5408 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5409 /* mulchw - mulchw. */
5410 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5411 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5412 tcg_gen_ext16s_tl(t1, t1);
5413 break;
5414 case 0x04:
5415 /* macchwu - macchwu. - macchwuo - macchwuo. */
5416 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5417 /* mulchwu - mulchwu. */
5418 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5419 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5420 tcg_gen_ext16u_tl(t1, t1);
5421 break;
5422 case 0x01:
5423 /* machhw - machhw. - machhwo - machhwo. */
5424 /* machhws - machhws. - machhwso - machhwso. */
5425 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5426 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5427 /* mulhhw - mulhhw. */
5428 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5429 tcg_gen_ext16s_tl(t0, t0);
5430 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5431 tcg_gen_ext16s_tl(t1, t1);
5432 break;
5433 case 0x00:
5434 /* machhwu - machhwu. - machhwuo - machhwuo. */
5435 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5436 /* mulhhwu - mulhhwu. */
5437 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5438 tcg_gen_ext16u_tl(t0, t0);
5439 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5440 tcg_gen_ext16u_tl(t1, t1);
5441 break;
5442 case 0x0D:
5443 /* maclhw - maclhw. - maclhwo - maclhwo. */
5444 /* maclhws - maclhws. - maclhwso - maclhwso. */
5445 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5446 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5447 /* mullhw - mullhw. */
5448 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5449 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5450 break;
5451 case 0x0C:
5452 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5453 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5454 /* mullhwu - mullhwu. */
5455 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5456 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5457 break;
5458 }
5459 if (opc2 & 0x04) {
5460 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5461 tcg_gen_mul_tl(t1, t0, t1);
5462 if (opc2 & 0x02) {
5463 /* nmultiply-and-accumulate (0x0E) */
5464 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5465 } else {
5466 /* multiply-and-accumulate (0x0C) */
5467 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5468 }
5469
5470 if (opc3 & 0x12) {
5471 /* Check overflow and/or saturate */
5472 int l1 = gen_new_label();
5473
5474 if (opc3 & 0x10) {
5475 /* Start with XER OV disabled, the most likely case */
5476 tcg_gen_movi_tl(cpu_ov, 0);
5477 }
5478 if (opc3 & 0x01) {
5479 /* Signed */
5480 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5481 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5482 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5483 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5484 if (opc3 & 0x02) {
5485 /* Saturate */
5486 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5487 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5488 }
5489 } else {
5490 /* Unsigned */
5491 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5492 if (opc3 & 0x02) {
5493 /* Saturate */
5494 tcg_gen_movi_tl(t0, UINT32_MAX);
5495 }
5496 }
5497 if (opc3 & 0x10) {
5498 /* Check overflow */
5499 tcg_gen_movi_tl(cpu_ov, 1);
5500 tcg_gen_movi_tl(cpu_so, 1);
5501 }
5502 gen_set_label(l1);
5503 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5504 }
5505 } else {
5506 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5507 }
5508 tcg_temp_free(t0);
5509 tcg_temp_free(t1);
5510 if (unlikely(Rc) != 0) {
5511 /* Update Rc0 */
5512 gen_set_Rc0(ctx, cpu_gpr[rt]);
5513 }
5514 }
5515
5516 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5517 static void glue(gen_, name)(DisasContext *ctx) \
5518 { \
5519 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5520 rD(ctx->opcode), Rc(ctx->opcode)); \
5521 }
5522
5523 /* macchw - macchw. */
5524 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5525 /* macchwo - macchwo. */
5526 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5527 /* macchws - macchws. */
5528 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5529 /* macchwso - macchwso. */
5530 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5531 /* macchwsu - macchwsu. */
5532 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5533 /* macchwsuo - macchwsuo. */
5534 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5535 /* macchwu - macchwu. */
5536 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5537 /* macchwuo - macchwuo. */
5538 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5539 /* machhw - machhw. */
5540 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5541 /* machhwo - machhwo. */
5542 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5543 /* machhws - machhws. */
5544 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5545 /* machhwso - machhwso. */
5546 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5547 /* machhwsu - machhwsu. */
5548 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5549 /* machhwsuo - machhwsuo. */
5550 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5551 /* machhwu - machhwu. */
5552 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5553 /* machhwuo - machhwuo. */
5554 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5555 /* maclhw - maclhw. */
5556 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5557 /* maclhwo - maclhwo. */
5558 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5559 /* maclhws - maclhws. */
5560 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5561 /* maclhwso - maclhwso. */
5562 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5563 /* maclhwu - maclhwu. */
5564 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5565 /* maclhwuo - maclhwuo. */
5566 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5567 /* maclhwsu - maclhwsu. */
5568 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5569 /* maclhwsuo - maclhwsuo. */
5570 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5571 /* nmacchw - nmacchw. */
5572 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5573 /* nmacchwo - nmacchwo. */
5574 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5575 /* nmacchws - nmacchws. */
5576 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5577 /* nmacchwso - nmacchwso. */
5578 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5579 /* nmachhw - nmachhw. */
5580 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5581 /* nmachhwo - nmachhwo. */
5582 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5583 /* nmachhws - nmachhws. */
5584 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5585 /* nmachhwso - nmachhwso. */
5586 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5587 /* nmaclhw - nmaclhw. */
5588 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5589 /* nmaclhwo - nmaclhwo. */
5590 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5591 /* nmaclhws - nmaclhws. */
5592 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5593 /* nmaclhwso - nmaclhwso. */
5594 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5595
5596 /* mulchw - mulchw. */
5597 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5598 /* mulchwu - mulchwu. */
5599 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5600 /* mulhhw - mulhhw. */
5601 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5602 /* mulhhwu - mulhhwu. */
5603 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5604 /* mullhw - mullhw. */
5605 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5606 /* mullhwu - mullhwu. */
5607 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5608
5609 /* mfdcr */
5610 static void gen_mfdcr(DisasContext *ctx)
5611 {
5612 #if defined(CONFIG_USER_ONLY)
5613 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5614 #else
5615 TCGv dcrn;
5616 if (unlikely(!ctx->mem_idx)) {
5617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5618 return;
5619 }
5620 /* NIP cannot be restored if the memory exception comes from an helper */
5621 gen_update_nip(ctx, ctx->nip - 4);
5622 dcrn = tcg_const_tl(SPR(ctx->opcode));
5623 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5624 tcg_temp_free(dcrn);
5625 #endif
5626 }
5627
5628 /* mtdcr */
5629 static void gen_mtdcr(DisasContext *ctx)
5630 {
5631 #if defined(CONFIG_USER_ONLY)
5632 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5633 #else
5634 TCGv dcrn;
5635 if (unlikely(!ctx->mem_idx)) {
5636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5637 return;
5638 }
5639 /* NIP cannot be restored if the memory exception comes from an helper */
5640 gen_update_nip(ctx, ctx->nip - 4);
5641 dcrn = tcg_const_tl(SPR(ctx->opcode));
5642 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5643 tcg_temp_free(dcrn);
5644 #endif
5645 }
5646
5647 /* mfdcrx */
5648 /* XXX: not implemented on 440 ? */
5649 static void gen_mfdcrx(DisasContext *ctx)
5650 {
5651 #if defined(CONFIG_USER_ONLY)
5652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5653 #else
5654 if (unlikely(!ctx->mem_idx)) {
5655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5656 return;
5657 }
5658 /* NIP cannot be restored if the memory exception comes from an helper */
5659 gen_update_nip(ctx, ctx->nip - 4);
5660 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5661 cpu_gpr[rA(ctx->opcode)]);
5662 /* Note: Rc update flag set leads to undefined state of Rc0 */
5663 #endif
5664 }
5665
5666 /* mtdcrx */
5667 /* XXX: not implemented on 440 ? */
5668 static void gen_mtdcrx(DisasContext *ctx)
5669 {
5670 #if defined(CONFIG_USER_ONLY)
5671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5672 #else
5673 if (unlikely(!ctx->mem_idx)) {
5674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5675 return;
5676 }
5677 /* NIP cannot be restored if the memory exception comes from an helper */
5678 gen_update_nip(ctx, ctx->nip - 4);
5679 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5680 cpu_gpr[rS(ctx->opcode)]);
5681 /* Note: Rc update flag set leads to undefined state of Rc0 */
5682 #endif
5683 }
5684
5685 /* mfdcrux (PPC 460) : user-mode access to DCR */
5686 static void gen_mfdcrux(DisasContext *ctx)
5687 {
5688 /* NIP cannot be restored if the memory exception comes from an helper */
5689 gen_update_nip(ctx, ctx->nip - 4);
5690 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5691 cpu_gpr[rA(ctx->opcode)]);
5692 /* Note: Rc update flag set leads to undefined state of Rc0 */
5693 }
5694
5695 /* mtdcrux (PPC 460) : user-mode access to DCR */
5696 static void gen_mtdcrux(DisasContext *ctx)
5697 {
5698 /* NIP cannot be restored if the memory exception comes from an helper */
5699 gen_update_nip(ctx, ctx->nip - 4);
5700 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5701 cpu_gpr[rS(ctx->opcode)]);
5702 /* Note: Rc update flag set leads to undefined state of Rc0 */
5703 }
5704
5705 /* dccci */
5706 static void gen_dccci(DisasContext *ctx)
5707 {
5708 #if defined(CONFIG_USER_ONLY)
5709 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5710 #else
5711 if (unlikely(!ctx->mem_idx)) {
5712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5713 return;
5714 }
5715 /* interpreted as no-op */
5716 #endif
5717 }
5718
5719 /* dcread */
5720 static void gen_dcread(DisasContext *ctx)
5721 {
5722 #if defined(CONFIG_USER_ONLY)
5723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5724 #else
5725 TCGv EA, val;
5726 if (unlikely(!ctx->mem_idx)) {
5727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5728 return;
5729 }
5730 gen_set_access_type(ctx, ACCESS_CACHE);
5731 EA = tcg_temp_new();
5732 gen_addr_reg_index(ctx, EA);
5733 val = tcg_temp_new();
5734 gen_qemu_ld32u(ctx, val, EA);
5735 tcg_temp_free(val);
5736 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5737 tcg_temp_free(EA);
5738 #endif
5739 }
5740
5741 /* icbt */
5742 static void gen_icbt_40x(DisasContext *ctx)
5743 {
5744 /* interpreted as no-op */
5745 /* XXX: specification say this is treated as a load by the MMU
5746 * but does not generate any exception
5747 */
5748 }
5749
5750 /* iccci */
5751 static void gen_iccci(DisasContext *ctx)
5752 {
5753 #if defined(CONFIG_USER_ONLY)
5754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5755 #else
5756 if (unlikely(!ctx->mem_idx)) {
5757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5758 return;
5759 }
5760 /* interpreted as no-op */
5761 #endif
5762 }
5763
5764 /* icread */
5765 static void gen_icread(DisasContext *ctx)
5766 {
5767 #if defined(CONFIG_USER_ONLY)
5768 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5769 #else
5770 if (unlikely(!ctx->mem_idx)) {
5771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5772 return;
5773 }
5774 /* interpreted as no-op */
5775 #endif
5776 }
5777
5778 /* rfci (mem_idx only) */
5779 static void gen_rfci_40x(DisasContext *ctx)
5780 {
5781 #if defined(CONFIG_USER_ONLY)
5782 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5783 #else
5784 if (unlikely(!ctx->mem_idx)) {
5785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5786 return;
5787 }
5788 /* Restore CPU state */
5789 gen_helper_40x_rfci(cpu_env);
5790 gen_sync_exception(ctx);
5791 #endif
5792 }
5793
5794 static void gen_rfci(DisasContext *ctx)
5795 {
5796 #if defined(CONFIG_USER_ONLY)
5797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5798 #else
5799 if (unlikely(!ctx->mem_idx)) {
5800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5801 return;
5802 }
5803 /* Restore CPU state */
5804 gen_helper_rfci(cpu_env);
5805 gen_sync_exception(ctx);
5806 #endif
5807 }
5808
5809 /* BookE specific */
5810
5811 /* XXX: not implemented on 440 ? */
5812 static void gen_rfdi(DisasContext *ctx)
5813 {
5814 #if defined(CONFIG_USER_ONLY)
5815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5816 #else
5817 if (unlikely(!ctx->mem_idx)) {
5818 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5819 return;
5820 }
5821 /* Restore CPU state */
5822 gen_helper_rfdi(cpu_env);
5823 gen_sync_exception(ctx);
5824 #endif
5825 }
5826
5827 /* XXX: not implemented on 440 ? */
5828 static void gen_rfmci(DisasContext *ctx)
5829 {
5830 #if defined(CONFIG_USER_ONLY)
5831 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5832 #else
5833 if (unlikely(!ctx->mem_idx)) {
5834 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5835 return;
5836 }
5837 /* Restore CPU state */
5838 gen_helper_rfmci(cpu_env);
5839 gen_sync_exception(ctx);
5840 #endif
5841 }
5842
5843 /* TLB management - PowerPC 405 implementation */
5844
5845 /* tlbre */
5846 static void gen_tlbre_40x(DisasContext *ctx)
5847 {
5848 #if defined(CONFIG_USER_ONLY)
5849 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5850 #else
5851 if (unlikely(!ctx->mem_idx)) {
5852 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5853 return;
5854 }
5855 switch (rB(ctx->opcode)) {
5856 case 0:
5857 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5858 cpu_gpr[rA(ctx->opcode)]);
5859 break;
5860 case 1:
5861 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5862 cpu_gpr[rA(ctx->opcode)]);
5863 break;
5864 default:
5865 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5866 break;
5867 }
5868 #endif
5869 }
5870
5871 /* tlbsx - tlbsx. */
5872 static void gen_tlbsx_40x(DisasContext *ctx)
5873 {
5874 #if defined(CONFIG_USER_ONLY)
5875 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5876 #else
5877 TCGv t0;
5878 if (unlikely(!ctx->mem_idx)) {
5879 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5880 return;
5881 }
5882 t0 = tcg_temp_new();
5883 gen_addr_reg_index(ctx, t0);
5884 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5885 tcg_temp_free(t0);
5886 if (Rc(ctx->opcode)) {
5887 int l1 = gen_new_label();
5888 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5889 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5890 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5891 gen_set_label(l1);
5892 }
5893 #endif
5894 }
5895
5896 /* tlbwe */
5897 static void gen_tlbwe_40x(DisasContext *ctx)
5898 {
5899 #if defined(CONFIG_USER_ONLY)
5900 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5901 #else
5902 if (unlikely(!ctx->mem_idx)) {
5903 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5904 return;
5905 }
5906 switch (rB(ctx->opcode)) {
5907 case 0:
5908 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5909 cpu_gpr[rS(ctx->opcode)]);
5910 break;
5911 case 1:
5912 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5913 cpu_gpr[rS(ctx->opcode)]);
5914 break;
5915 default:
5916 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5917 break;
5918 }
5919 #endif
5920 }
5921
5922 /* TLB management - PowerPC 440 implementation */
5923
5924 /* tlbre */
5925 static void gen_tlbre_440(DisasContext *ctx)
5926 {
5927 #if defined(CONFIG_USER_ONLY)
5928 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5929 #else
5930 if (unlikely(!ctx->mem_idx)) {
5931 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5932 return;
5933 }
5934 switch (rB(ctx->opcode)) {
5935 case 0:
5936 case 1:
5937 case 2:
5938 {
5939 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5940 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5941 t0, cpu_gpr[rA(ctx->opcode)]);
5942 tcg_temp_free_i32(t0);
5943 }
5944 break;
5945 default:
5946 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5947 break;
5948 }
5949 #endif
5950 }
5951
5952 /* tlbsx - tlbsx. */
5953 static void gen_tlbsx_440(DisasContext *ctx)
5954 {
5955 #if defined(CONFIG_USER_ONLY)
5956 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5957 #else
5958 TCGv t0;
5959 if (unlikely(!ctx->mem_idx)) {
5960 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5961 return;
5962 }
5963 t0 = tcg_temp_new();
5964 gen_addr_reg_index(ctx, t0);
5965 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5966 tcg_temp_free(t0);
5967 if (Rc(ctx->opcode)) {
5968 int l1 = gen_new_label();
5969 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5970 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5971 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5972 gen_set_label(l1);
5973 }
5974 #endif
5975 }
5976
5977 /* tlbwe */
5978 static void gen_tlbwe_440(DisasContext *ctx)
5979 {
5980 #if defined(CONFIG_USER_ONLY)
5981 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5982 #else
5983 if (unlikely(!ctx->mem_idx)) {
5984 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5985 return;
5986 }
5987 switch (rB(ctx->opcode)) {
5988 case 0:
5989 case 1:
5990 case 2:
5991 {
5992 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5993 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5994 cpu_gpr[rS(ctx->opcode)]);
5995 tcg_temp_free_i32(t0);
5996 }
5997 break;
5998 default:
5999 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6000 break;
6001 }
6002 #endif
6003 }
6004
6005 /* TLB management - PowerPC BookE 2.06 implementation */
6006
6007 /* tlbre */
6008 static void gen_tlbre_booke206(DisasContext *ctx)
6009 {
6010 #if defined(CONFIG_USER_ONLY)
6011 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6012 #else
6013 if (unlikely(!ctx->mem_idx)) {
6014 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6015 return;
6016 }
6017
6018 gen_helper_booke206_tlbre(cpu_env);
6019 #endif
6020 }
6021
6022 /* tlbsx - tlbsx. */
6023 static void gen_tlbsx_booke206(DisasContext *ctx)
6024 {
6025 #if defined(CONFIG_USER_ONLY)
6026 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6027 #else
6028 TCGv t0;
6029 if (unlikely(!ctx->mem_idx)) {
6030 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6031 return;
6032 }
6033
6034 if (rA(ctx->opcode)) {
6035 t0 = tcg_temp_new();
6036 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6037 } else {
6038 t0 = tcg_const_tl(0);
6039 }
6040
6041 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6042 gen_helper_booke206_tlbsx(cpu_env, t0);
6043 #endif
6044 }
6045
6046 /* tlbwe */
6047 static void gen_tlbwe_booke206(DisasContext *ctx)
6048 {
6049 #if defined(CONFIG_USER_ONLY)
6050 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6051 #else
6052 if (unlikely(!ctx->mem_idx)) {
6053 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6054 return;
6055 }
6056 gen_update_nip(ctx, ctx->nip - 4);
6057 gen_helper_booke206_tlbwe(cpu_env);
6058 #endif
6059 }
6060
6061 static void gen_tlbivax_booke206(DisasContext *ctx)
6062 {
6063 #if defined(CONFIG_USER_ONLY)
6064 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6065 #else
6066 TCGv t0;
6067 if (unlikely(!ctx->mem_idx)) {
6068 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6069 return;
6070 }
6071
6072 t0 = tcg_temp_new();
6073 gen_addr_reg_index(ctx, t0);
6074
6075 gen_helper_booke206_tlbivax(cpu_env, t0);
6076 #endif
6077 }
6078
6079 static void gen_tlbilx_booke206(DisasContext *ctx)
6080 {
6081 #if defined(CONFIG_USER_ONLY)
6082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6083 #else
6084 TCGv t0;
6085 if (unlikely(!ctx->mem_idx)) {
6086 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6087 return;
6088 }
6089
6090 t0 = tcg_temp_new();
6091 gen_addr_reg_index(ctx, t0);
6092
6093 switch((ctx->opcode >> 21) & 0x3) {
6094 case 0:
6095 gen_helper_booke206_tlbilx0(cpu_env, t0);
6096 break;
6097 case 1:
6098 gen_helper_booke206_tlbilx1(cpu_env, t0);
6099 break;
6100 case 3:
6101 gen_helper_booke206_tlbilx3(cpu_env, t0);
6102 break;
6103 default:
6104 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6105 break;
6106 }
6107
6108 tcg_temp_free(t0);
6109 #endif
6110 }
6111
6112
6113 /* wrtee */
6114 static void gen_wrtee(DisasContext *ctx)
6115 {
6116 #if defined(CONFIG_USER_ONLY)
6117 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6118 #else
6119 TCGv t0;
6120 if (unlikely(!ctx->mem_idx)) {
6121 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6122 return;
6123 }
6124 t0 = tcg_temp_new();
6125 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6126 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6127 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6128 tcg_temp_free(t0);
6129 /* Stop translation to have a chance to raise an exception
6130 * if we just set msr_ee to 1
6131 */
6132 gen_stop_exception(ctx);
6133 #endif
6134 }
6135
6136 /* wrteei */
6137 static void gen_wrteei(DisasContext *ctx)
6138 {
6139 #if defined(CONFIG_USER_ONLY)
6140 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6141 #else
6142 if (unlikely(!ctx->mem_idx)) {
6143 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6144 return;
6145 }
6146 if (ctx->opcode & 0x00008000) {
6147 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6148 /* Stop translation to have a chance to raise an exception */
6149 gen_stop_exception(ctx);
6150 } else {
6151 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6152 }
6153 #endif
6154 }
6155
6156 /* PowerPC 440 specific instructions */
6157
6158 /* dlmzb */
6159 static void gen_dlmzb(DisasContext *ctx)
6160 {
6161 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6162 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6163 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6164 tcg_temp_free_i32(t0);
6165 }
6166
6167 /* mbar replaces eieio on 440 */
6168 static void gen_mbar(DisasContext *ctx)
6169 {
6170 /* interpreted as no-op */
6171 }
6172
6173 /* msync replaces sync on 440 */
6174 static void gen_msync_4xx(DisasContext *ctx)
6175 {
6176 /* interpreted as no-op */
6177 }
6178
6179 /* icbt */
6180 static void gen_icbt_440(DisasContext *ctx)
6181 {
6182 /* interpreted as no-op */
6183 /* XXX: specification say this is treated as a load by the MMU
6184 * but does not generate any exception
6185 */
6186 }
6187
6188 /* Embedded.Processor Control */
6189
6190 static void gen_msgclr(DisasContext *ctx)
6191 {
6192 #if defined(CONFIG_USER_ONLY)
6193 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6194 #else
6195 if (unlikely(ctx->mem_idx == 0)) {
6196 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6197 return;
6198 }
6199
6200 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6201 #endif
6202 }
6203
6204 static void gen_msgsnd(DisasContext *ctx)
6205 {
6206 #if defined(CONFIG_USER_ONLY)
6207 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6208 #else
6209 if (unlikely(ctx->mem_idx == 0)) {
6210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6211 return;
6212 }
6213
6214 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6215 #endif
6216 }
6217
6218 /*** Altivec vector extension ***/
6219 /* Altivec registers moves */
6220
6221 static inline TCGv_ptr gen_avr_ptr(int reg)
6222 {
6223 TCGv_ptr r = tcg_temp_new_ptr();
6224 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6225 return r;
6226 }
6227
6228 #define GEN_VR_LDX(name, opc2, opc3) \
6229 static void glue(gen_, name)(DisasContext *ctx) \
6230 { \
6231 TCGv EA; \
6232 if (unlikely(!ctx->altivec_enabled)) { \
6233 gen_exception(ctx, POWERPC_EXCP_VPU); \
6234 return; \
6235 } \
6236 gen_set_access_type(ctx, ACCESS_INT); \
6237 EA = tcg_temp_new(); \
6238 gen_addr_reg_index(ctx, EA); \
6239 tcg_gen_andi_tl(EA, EA, ~0xf); \
6240 if (ctx->le_mode) { \
6241 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6242 tcg_gen_addi_tl(EA, EA, 8); \
6243 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6244 } else { \
6245 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6246 tcg_gen_addi_tl(EA, EA, 8); \
6247 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6248 } \
6249 tcg_temp_free(EA); \
6250 }
6251
6252 #define GEN_VR_STX(name, opc2, opc3) \
6253 static void gen_st##name(DisasContext *ctx) \
6254 { \
6255 TCGv EA; \
6256 if (unlikely(!ctx->altivec_enabled)) { \
6257 gen_exception(ctx, POWERPC_EXCP_VPU); \
6258 return; \
6259 } \
6260 gen_set_access_type(ctx, ACCESS_INT); \
6261 EA = tcg_temp_new(); \
6262 gen_addr_reg_index(ctx, EA); \
6263 tcg_gen_andi_tl(EA, EA, ~0xf); \
6264 if (ctx->le_mode) { \
6265 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6266 tcg_gen_addi_tl(EA, EA, 8); \
6267 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6268 } else { \
6269 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6270 tcg_gen_addi_tl(EA, EA, 8); \
6271 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6272 } \
6273 tcg_temp_free(EA); \
6274 }
6275
6276 #define GEN_VR_LVE(name, opc2, opc3) \
6277 static void gen_lve##name(DisasContext *ctx) \
6278 { \
6279 TCGv EA; \
6280 TCGv_ptr rs; \
6281 if (unlikely(!ctx->altivec_enabled)) { \
6282 gen_exception(ctx, POWERPC_EXCP_VPU); \
6283 return; \
6284 } \
6285 gen_set_access_type(ctx, ACCESS_INT); \
6286 EA = tcg_temp_new(); \
6287 gen_addr_reg_index(ctx, EA); \
6288 rs = gen_avr_ptr(rS(ctx->opcode)); \
6289 gen_helper_lve##name(cpu_env, rs, EA); \
6290 tcg_temp_free(EA); \
6291 tcg_temp_free_ptr(rs); \
6292 }
6293
6294 #define GEN_VR_STVE(name, opc2, opc3) \
6295 static void gen_stve##name(DisasContext *ctx) \
6296 { \
6297 TCGv EA; \
6298 TCGv_ptr rs; \
6299 if (unlikely(!ctx->altivec_enabled)) { \
6300 gen_exception(ctx, POWERPC_EXCP_VPU); \
6301 return; \
6302 } \
6303 gen_set_access_type(ctx, ACCESS_INT); \
6304 EA = tcg_temp_new(); \
6305 gen_addr_reg_index(ctx, EA); \
6306 rs = gen_avr_ptr(rS(ctx->opcode)); \
6307 gen_helper_stve##name(cpu_env, rs, EA); \
6308 tcg_temp_free(EA); \
6309 tcg_temp_free_ptr(rs); \
6310 }
6311
6312 GEN_VR_LDX(lvx, 0x07, 0x03);
6313 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6314 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6315
6316 GEN_VR_LVE(bx, 0x07, 0x00);
6317 GEN_VR_LVE(hx, 0x07, 0x01);
6318 GEN_VR_LVE(wx, 0x07, 0x02);
6319
6320 GEN_VR_STX(svx, 0x07, 0x07);
6321 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6322 GEN_VR_STX(svxl, 0x07, 0x0F);
6323
6324 GEN_VR_STVE(bx, 0x07, 0x04);
6325 GEN_VR_STVE(hx, 0x07, 0x05);
6326 GEN_VR_STVE(wx, 0x07, 0x06);
6327
6328 static void gen_lvsl(DisasContext *ctx)
6329 {
6330 TCGv_ptr rd;
6331 TCGv EA;
6332 if (unlikely(!ctx->altivec_enabled)) {
6333 gen_exception(ctx, POWERPC_EXCP_VPU);
6334 return;
6335 }
6336 EA = tcg_temp_new();
6337 gen_addr_reg_index(ctx, EA);
6338 rd = gen_avr_ptr(rD(ctx->opcode));
6339 gen_helper_lvsl(rd, EA);
6340 tcg_temp_free(EA);
6341 tcg_temp_free_ptr(rd);
6342 }
6343
6344 static void gen_lvsr(DisasContext *ctx)
6345 {
6346 TCGv_ptr rd;
6347 TCGv EA;
6348 if (unlikely(!ctx->altivec_enabled)) {
6349 gen_exception(ctx, POWERPC_EXCP_VPU);
6350 return;
6351 }
6352 EA = tcg_temp_new();
6353 gen_addr_reg_index(ctx, EA);
6354 rd = gen_avr_ptr(rD(ctx->opcode));
6355 gen_helper_lvsr(rd, EA);
6356 tcg_temp_free(EA);
6357 tcg_temp_free_ptr(rd);
6358 }
6359
6360 static void gen_mfvscr(DisasContext *ctx)
6361 {
6362 TCGv_i32 t;
6363 if (unlikely(!ctx->altivec_enabled)) {
6364 gen_exception(ctx, POWERPC_EXCP_VPU);
6365 return;
6366 }
6367 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6368 t = tcg_temp_new_i32();
6369 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6370 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6371 tcg_temp_free_i32(t);
6372 }
6373
6374 static void gen_mtvscr(DisasContext *ctx)
6375 {
6376 TCGv_ptr p;
6377 if (unlikely(!ctx->altivec_enabled)) {
6378 gen_exception(ctx, POWERPC_EXCP_VPU);
6379 return;
6380 }
6381 p = gen_avr_ptr(rD(ctx->opcode));
6382 gen_helper_mtvscr(cpu_env, p);
6383 tcg_temp_free_ptr(p);
6384 }
6385
6386 /* Logical operations */
6387 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6388 static void glue(gen_, name)(DisasContext *ctx) \
6389 { \
6390 if (unlikely(!ctx->altivec_enabled)) { \
6391 gen_exception(ctx, POWERPC_EXCP_VPU); \
6392 return; \
6393 } \
6394 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6395 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6396 }
6397
6398 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6399 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6400 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6401 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6402 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6403
6404 #define GEN_VXFORM(name, opc2, opc3) \
6405 static void glue(gen_, name)(DisasContext *ctx) \
6406 { \
6407 TCGv_ptr ra, rb, rd; \
6408 if (unlikely(!ctx->altivec_enabled)) { \
6409 gen_exception(ctx, POWERPC_EXCP_VPU); \
6410 return; \
6411 } \
6412 ra = gen_avr_ptr(rA(ctx->opcode)); \
6413 rb = gen_avr_ptr(rB(ctx->opcode)); \
6414 rd = gen_avr_ptr(rD(ctx->opcode)); \
6415 gen_helper_##name (rd, ra, rb); \
6416 tcg_temp_free_ptr(ra); \
6417 tcg_temp_free_ptr(rb); \
6418 tcg_temp_free_ptr(rd); \
6419 }
6420
6421 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6422 static void glue(gen_, name)(DisasContext *ctx) \
6423 { \
6424 TCGv_ptr ra, rb, rd; \
6425 if (unlikely(!ctx->altivec_enabled)) { \
6426 gen_exception(ctx, POWERPC_EXCP_VPU); \
6427 return; \
6428 } \
6429 ra = gen_avr_ptr(rA(ctx->opcode)); \
6430 rb = gen_avr_ptr(rB(ctx->opcode)); \
6431 rd = gen_avr_ptr(rD(ctx->opcode)); \
6432 gen_helper_##name(cpu_env, rd, ra, rb); \
6433 tcg_temp_free_ptr(ra); \
6434 tcg_temp_free_ptr(rb); \
6435 tcg_temp_free_ptr(rd); \
6436 }
6437
6438 GEN_VXFORM(vaddubm, 0, 0);
6439 GEN_VXFORM(vadduhm, 0, 1);
6440 GEN_VXFORM(vadduwm, 0, 2);
6441 GEN_VXFORM(vsububm, 0, 16);
6442 GEN_VXFORM(vsubuhm, 0, 17);
6443 GEN_VXFORM(vsubuwm, 0, 18);
6444 GEN_VXFORM(vmaxub, 1, 0);
6445 GEN_VXFORM(vmaxuh, 1, 1);
6446 GEN_VXFORM(vmaxuw, 1, 2);
6447 GEN_VXFORM(vmaxsb, 1, 4);
6448 GEN_VXFORM(vmaxsh, 1, 5);
6449 GEN_VXFORM(vmaxsw, 1, 6);
6450 GEN_VXFORM(vminub, 1, 8);
6451 GEN_VXFORM(vminuh, 1, 9);
6452 GEN_VXFORM(vminuw, 1, 10);
6453 GEN_VXFORM(vminsb, 1, 12);
6454 GEN_VXFORM(vminsh, 1, 13);
6455 GEN_VXFORM(vminsw, 1, 14);
6456 GEN_VXFORM(vavgub, 1, 16);
6457 GEN_VXFORM(vavguh, 1, 17);
6458 GEN_VXFORM(vavguw, 1, 18);
6459 GEN_VXFORM(vavgsb, 1, 20);
6460 GEN_VXFORM(vavgsh, 1, 21);
6461 GEN_VXFORM(vavgsw, 1, 22);
6462 GEN_VXFORM(vmrghb, 6, 0);
6463 GEN_VXFORM(vmrghh, 6, 1);
6464 GEN_VXFORM(vmrghw, 6, 2);
6465 GEN_VXFORM(vmrglb, 6, 4);
6466 GEN_VXFORM(vmrglh, 6, 5);
6467 GEN_VXFORM(vmrglw, 6, 6);
6468 GEN_VXFORM(vmuloub, 4, 0);
6469 GEN_VXFORM(vmulouh, 4, 1);
6470 GEN_VXFORM(vmulosb, 4, 4);
6471 GEN_VXFORM(vmulosh, 4, 5);
6472 GEN_VXFORM(vmuleub, 4, 8);
6473 GEN_VXFORM(vmuleuh, 4, 9);
6474 GEN_VXFORM(vmulesb, 4, 12);
6475 GEN_VXFORM(vmulesh, 4, 13);
6476 GEN_VXFORM(vslb, 2, 4);
6477 GEN_VXFORM(vslh, 2, 5);
6478 GEN_VXFORM(vslw, 2, 6);
6479 GEN_VXFORM(vsrb, 2, 8);
6480 GEN_VXFORM(vsrh, 2, 9);
6481 GEN_VXFORM(vsrw, 2, 10);
6482 GEN_VXFORM(vsrab, 2, 12);
6483 GEN_VXFORM(vsrah, 2, 13);
6484 GEN_VXFORM(vsraw, 2, 14);
6485 GEN_VXFORM(vslo, 6, 16);
6486 GEN_VXFORM(vsro, 6, 17);
6487 GEN_VXFORM(vaddcuw, 0, 6);
6488 GEN_VXFORM(vsubcuw, 0, 22);
6489 GEN_VXFORM_ENV(vaddubs, 0, 8);
6490 GEN_VXFORM_ENV(vadduhs, 0, 9);
6491 GEN_VXFORM_ENV(vadduws, 0, 10);
6492 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6493 GEN_VXFORM_ENV(vaddshs, 0, 13);
6494 GEN_VXFORM_ENV(vaddsws, 0, 14);
6495 GEN_VXFORM_ENV(vsububs, 0, 24);
6496 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6497 GEN_VXFORM_ENV(vsubuws, 0, 26);
6498 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6499 GEN_VXFORM_ENV(vsubshs, 0, 29);
6500 GEN_VXFORM_ENV(vsubsws, 0, 30);
6501 GEN_VXFORM(vrlb, 2, 0);
6502 GEN_VXFORM(vrlh, 2, 1);
6503 GEN_VXFORM(vrlw, 2, 2);
6504 GEN_VXFORM(vsl, 2, 7);
6505 GEN_VXFORM(vsr, 2, 11);
6506 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6507 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6508 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6509 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6510 GEN_VXFORM_ENV(vpkshus, 7, 4);
6511 GEN_VXFORM_ENV(vpkswus, 7, 5);
6512 GEN_VXFORM_ENV(vpkshss, 7, 6);
6513 GEN_VXFORM_ENV(vpkswss, 7, 7);
6514 GEN_VXFORM(vpkpx, 7, 12);
6515 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6516 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6517 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6518 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6519 GEN_VXFORM_ENV(vsumsws, 4, 30);
6520 GEN_VXFORM_ENV(vaddfp, 5, 0);
6521 GEN_VXFORM_ENV(vsubfp, 5, 1);
6522 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6523 GEN_VXFORM_ENV(vminfp, 5, 17);
6524
6525 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6526 static void glue(gen_, name)(DisasContext *ctx) \
6527 { \
6528 TCGv_ptr ra, rb, rd; \
6529 if (unlikely(!ctx->altivec_enabled)) { \
6530 gen_exception(ctx, POWERPC_EXCP_VPU); \
6531 return; \
6532 } \
6533 ra = gen_avr_ptr(rA(ctx->opcode)); \
6534 rb = gen_avr_ptr(rB(ctx->opcode)); \
6535 rd = gen_avr_ptr(rD(ctx->opcode)); \
6536 gen_helper_##opname(cpu_env, rd, ra, rb); \
6537 tcg_temp_free_ptr(ra); \
6538 tcg_temp_free_ptr(rb); \
6539 tcg_temp_free_ptr(rd); \
6540 }
6541
6542 #define GEN_VXRFORM(name, opc2, opc3) \
6543 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6544 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6545
6546 GEN_VXRFORM(vcmpequb, 3, 0)
6547 GEN_VXRFORM(vcmpequh, 3, 1)
6548 GEN_VXRFORM(vcmpequw, 3, 2)
6549 GEN_VXRFORM(vcmpgtsb, 3, 12)
6550 GEN_VXRFORM(vcmpgtsh, 3, 13)
6551 GEN_VXRFORM(vcmpgtsw, 3, 14)
6552 GEN_VXRFORM(vcmpgtub, 3, 8)
6553 GEN_VXRFORM(vcmpgtuh, 3, 9)
6554 GEN_VXRFORM(vcmpgtuw, 3, 10)
6555 GEN_VXRFORM(vcmpeqfp, 3, 3)
6556 GEN_VXRFORM(vcmpgefp, 3, 7)
6557 GEN_VXRFORM(vcmpgtfp, 3, 11)
6558 GEN_VXRFORM(vcmpbfp, 3, 15)
6559
6560 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6561 static void glue(gen_, name)(DisasContext *ctx) \
6562 { \
6563 TCGv_ptr rd; \
6564 TCGv_i32 simm; \
6565 if (unlikely(!ctx->altivec_enabled)) { \
6566 gen_exception(ctx, POWERPC_EXCP_VPU); \
6567 return; \
6568 } \
6569 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6570 rd = gen_avr_ptr(rD(ctx->opcode)); \
6571 gen_helper_##name (rd, simm); \
6572 tcg_temp_free_i32(simm); \
6573 tcg_temp_free_ptr(rd); \
6574 }
6575
6576 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6577 GEN_VXFORM_SIMM(vspltish, 6, 13);
6578 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6579
6580 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6581 static void glue(gen_, name)(DisasContext *ctx) \
6582 { \
6583 TCGv_ptr rb, rd; \
6584 if (unlikely(!ctx->altivec_enabled)) { \
6585 gen_exception(ctx, POWERPC_EXCP_VPU); \
6586 return; \
6587 } \
6588 rb = gen_avr_ptr(rB(ctx->opcode)); \
6589 rd = gen_avr_ptr(rD(ctx->opcode)); \
6590 gen_helper_##name (rd, rb); \
6591 tcg_temp_free_ptr(rb); \
6592 tcg_temp_free_ptr(rd); \
6593 }
6594
6595 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6596 static void glue(gen_, name)(DisasContext *ctx) \
6597 { \
6598 TCGv_ptr rb, rd; \
6599 \
6600 if (unlikely(!ctx->altivec_enabled)) { \
6601 gen_exception(ctx, POWERPC_EXCP_VPU); \
6602 return; \
6603 } \
6604 rb = gen_avr_ptr(rB(ctx->opcode)); \
6605 rd = gen_avr_ptr(rD(ctx->opcode)); \
6606 gen_helper_##name(cpu_env, rd, rb); \
6607 tcg_temp_free_ptr(rb); \
6608 tcg_temp_free_ptr(rd); \
6609 }
6610
6611 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6612 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6613 GEN_VXFORM_NOA(vupklsb, 7, 10);
6614 GEN_VXFORM_NOA(vupklsh, 7, 11);
6615 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6616 GEN_VXFORM_NOA(vupklpx, 7, 15);
6617 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6618 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6619 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6620 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6621 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6622 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6623 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6624 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6625
6626 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6627 static void glue(gen_, name)(DisasContext *ctx) \
6628 { \
6629 TCGv_ptr rd; \
6630 TCGv_i32 simm; \
6631 if (unlikely(!ctx->altivec_enabled)) { \
6632 gen_exception(ctx, POWERPC_EXCP_VPU); \
6633 return; \
6634 } \
6635 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6636 rd = gen_avr_ptr(rD(ctx->opcode)); \
6637 gen_helper_##name (rd, simm); \
6638 tcg_temp_free_i32(simm); \
6639 tcg_temp_free_ptr(rd); \
6640 }
6641
6642 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6643 static void glue(gen_, name)(DisasContext *ctx) \
6644 { \
6645 TCGv_ptr rb, rd; \
6646 TCGv_i32 uimm; \
6647 if (unlikely(!ctx->altivec_enabled)) { \
6648 gen_exception(ctx, POWERPC_EXCP_VPU); \
6649 return; \
6650 } \
6651 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6652 rb = gen_avr_ptr(rB(ctx->opcode)); \
6653 rd = gen_avr_ptr(rD(ctx->opcode)); \
6654 gen_helper_##name (rd, rb, uimm); \
6655 tcg_temp_free_i32(uimm); \
6656 tcg_temp_free_ptr(rb); \
6657 tcg_temp_free_ptr(rd); \
6658 }
6659
6660 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6661 static void glue(gen_, name)(DisasContext *ctx) \
6662 { \
6663 TCGv_ptr rb, rd; \
6664 TCGv_i32 uimm; \
6665 \
6666 if (unlikely(!ctx->altivec_enabled)) { \
6667 gen_exception(ctx, POWERPC_EXCP_VPU); \
6668 return; \
6669 } \
6670 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6671 rb = gen_avr_ptr(rB(ctx->opcode)); \
6672 rd = gen_avr_ptr(rD(ctx->opcode)); \
6673 gen_helper_##name(cpu_env, rd, rb, uimm); \
6674 tcg_temp_free_i32(uimm); \
6675 tcg_temp_free_ptr(rb); \
6676 tcg_temp_free_ptr(rd); \
6677 }
6678
6679 GEN_VXFORM_UIMM(vspltb, 6, 8);
6680 GEN_VXFORM_UIMM(vsplth, 6, 9);
6681 GEN_VXFORM_UIMM(vspltw, 6, 10);
6682 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6683 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6684 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6685 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6686
6687 static void gen_vsldoi(DisasContext *ctx)
6688 {
6689 TCGv_ptr ra, rb, rd;
6690 TCGv_i32 sh;
6691 if (unlikely(!ctx->altivec_enabled)) {
6692 gen_exception(ctx, POWERPC_EXCP_VPU);
6693 return;
6694 }
6695 ra = gen_avr_ptr(rA(ctx->opcode));
6696 rb = gen_avr_ptr(rB(ctx->opcode));
6697 rd = gen_avr_ptr(rD(ctx->opcode));
6698 sh = tcg_const_i32(VSH(ctx->opcode));
6699 gen_helper_vsldoi (rd, ra, rb, sh);
6700 tcg_temp_free_ptr(ra);
6701 tcg_temp_free_ptr(rb);
6702 tcg_temp_free_ptr(rd);
6703 tcg_temp_free_i32(sh);
6704 }
6705
6706 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6707 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6708 { \
6709 TCGv_ptr ra, rb, rc, rd; \
6710 if (unlikely(!ctx->altivec_enabled)) { \
6711 gen_exception(ctx, POWERPC_EXCP_VPU); \
6712 return; \
6713 } \
6714 ra = gen_avr_ptr(rA(ctx->opcode)); \
6715 rb = gen_avr_ptr(rB(ctx->opcode)); \
6716 rc = gen_avr_ptr(rC(ctx->opcode)); \
6717 rd = gen_avr_ptr(rD(ctx->opcode)); \
6718 if (Rc(ctx->opcode)) { \
6719 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6720 } else { \
6721 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6722 } \
6723 tcg_temp_free_ptr(ra); \
6724 tcg_temp_free_ptr(rb); \
6725 tcg_temp_free_ptr(rc); \
6726 tcg_temp_free_ptr(rd); \
6727 }
6728
6729 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6730
6731 static void gen_vmladduhm(DisasContext *ctx)
6732 {
6733 TCGv_ptr ra, rb, rc, rd;
6734 if (unlikely(!ctx->altivec_enabled)) {
6735 gen_exception(ctx, POWERPC_EXCP_VPU);
6736 return;
6737 }
6738 ra = gen_avr_ptr(rA(ctx->opcode));
6739 rb = gen_avr_ptr(rB(ctx->opcode));
6740 rc = gen_avr_ptr(rC(ctx->opcode));
6741 rd = gen_avr_ptr(rD(ctx->opcode));
6742 gen_helper_vmladduhm(rd, ra, rb, rc);
6743 tcg_temp_free_ptr(ra);
6744 tcg_temp_free_ptr(rb);
6745 tcg_temp_free_ptr(rc);
6746 tcg_temp_free_ptr(rd);
6747 }
6748
6749 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6750 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6751 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6752 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6753 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6754
6755 /*** SPE extension ***/
6756 /* Register moves */
6757
6758
6759 static inline void gen_evmra(DisasContext *ctx)
6760 {
6761
6762 if (unlikely(!ctx->spe_enabled)) {
6763 gen_exception(ctx, POWERPC_EXCP_SPEU);
6764 return;
6765 }
6766
6767 #if defined(TARGET_PPC64)
6768 /* rD := rA */
6769 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6770
6771 /* spe_acc := rA */
6772 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6773 cpu_env,
6774 offsetof(CPUPPCState, spe_acc));
6775 #else
6776 TCGv_i64 tmp = tcg_temp_new_i64();
6777
6778 /* tmp := rA_lo + rA_hi << 32 */
6779 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6780
6781 /* spe_acc := tmp */
6782 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6783 tcg_temp_free_i64(tmp);
6784
6785 /* rD := rA */
6786 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6787 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6788 #endif
6789 }
6790
6791 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6792 {
6793 #if defined(TARGET_PPC64)
6794 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6795 #else
6796 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6797 #endif
6798 }
6799
6800 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6801 {
6802 #if defined(TARGET_PPC64)
6803 tcg_gen_mov_i64(cpu_gpr[reg], t);
6804 #else
6805 TCGv_i64 tmp = tcg_temp_new_i64();
6806 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6807 tcg_gen_shri_i64(tmp, t, 32);
6808 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6809 tcg_temp_free_i64(tmp);
6810 #endif
6811 }
6812
6813 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6814 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6815 { \
6816 if (Rc(ctx->opcode)) \
6817 gen_##name1(ctx); \
6818 else \
6819 gen_##name0(ctx); \
6820 }
6821
6822 /* Handler for undefined SPE opcodes */
6823 static inline void gen_speundef(DisasContext *ctx)
6824 {
6825 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6826 }
6827
6828 /* SPE logic */
6829 #if defined(TARGET_PPC64)
6830 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6831 static inline void gen_##name(DisasContext *ctx) \
6832 { \
6833 if (unlikely(!ctx->spe_enabled)) { \
6834 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6835 return; \
6836 } \
6837 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6838 cpu_gpr[rB(ctx->opcode)]); \
6839 }
6840 #else
6841 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6842 static inline void gen_##name(DisasContext *ctx) \
6843 { \
6844 if (unlikely(!ctx->spe_enabled)) { \
6845 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6846 return; \
6847 } \
6848 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6849 cpu_gpr[rB(ctx->opcode)]); \
6850 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6851 cpu_gprh[rB(ctx->opcode)]); \
6852 }
6853 #endif
6854
6855 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6856 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6857 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6858 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6859 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6860 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6861 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6862 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6863
6864 /* SPE logic immediate */
6865 #if defined(TARGET_PPC64)
6866 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6867 static inline void gen_##name(DisasContext *ctx) \
6868 { \
6869 if (unlikely(!ctx->spe_enabled)) { \
6870 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6871 return; \
6872 } \
6873 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6874 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6875 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6876 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6877 tcg_opi(t0, t0, rB(ctx->opcode)); \
6878 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6879 tcg_gen_trunc_i64_i32(t1, t2); \
6880 tcg_temp_free_i64(t2); \
6881 tcg_opi(t1, t1, rB(ctx->opcode)); \
6882 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6883 tcg_temp_free_i32(t0); \
6884 tcg_temp_free_i32(t1); \
6885 }
6886 #else
6887 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6888 static inline void gen_##name(DisasContext *ctx) \
6889 { \
6890 if (unlikely(!ctx->spe_enabled)) { \
6891 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6892 return; \
6893 } \
6894 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6895 rB(ctx->opcode)); \
6896 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6897 rB(ctx->opcode)); \
6898 }
6899 #endif
6900 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6901 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6902 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6903 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6904
6905 /* SPE arithmetic */
6906 #if defined(TARGET_PPC64)
6907 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6908 static inline void gen_##name(DisasContext *ctx) \
6909 { \
6910 if (unlikely(!ctx->spe_enabled)) { \
6911 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6912 return; \
6913 } \
6914 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6915 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6916 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6917 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6918 tcg_op(t0, t0); \
6919 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6920 tcg_gen_trunc_i64_i32(t1, t2); \
6921 tcg_temp_free_i64(t2); \
6922 tcg_op(t1, t1); \
6923 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6924 tcg_temp_free_i32(t0); \
6925 tcg_temp_free_i32(t1); \
6926 }
6927 #else
6928 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6929 static inline void gen_##name(DisasContext *ctx) \
6930 { \
6931 if (unlikely(!ctx->spe_enabled)) { \
6932 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6933 return; \
6934 } \
6935 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6936 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6937 }
6938 #endif
6939
6940 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6941 {
6942 int l1 = gen_new_label();
6943 int l2 = gen_new_label();
6944
6945 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6946 tcg_gen_neg_i32(ret, arg1);
6947 tcg_gen_br(l2);
6948 gen_set_label(l1);
6949 tcg_gen_mov_i32(ret, arg1);
6950 gen_set_label(l2);
6951 }
6952 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6953 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6954 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6955 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6956 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6957 {
6958 tcg_gen_addi_i32(ret, arg1, 0x8000);
6959 tcg_gen_ext16u_i32(ret, ret);
6960 }
6961 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6962 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6963 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6964
6965 #if defined(TARGET_PPC64)
6966 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6967 static inline void gen_##name(DisasContext *ctx) \
6968 { \
6969 if (unlikely(!ctx->spe_enabled)) { \
6970 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6971 return; \
6972 } \
6973 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6974 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6975 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6976 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6977 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6978 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6979 tcg_op(t0, t0, t2); \
6980 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6981 tcg_gen_trunc_i64_i32(t1, t3); \
6982 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6983 tcg_gen_trunc_i64_i32(t2, t3); \
6984 tcg_temp_free_i64(t3); \
6985 tcg_op(t1, t1, t2); \
6986 tcg_temp_free_i32(t2); \
6987 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6988 tcg_temp_free_i32(t0); \
6989 tcg_temp_free_i32(t1); \
6990 }
6991 #else
6992 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6993 static inline void gen_##name(DisasContext *ctx) \
6994 { \
6995 if (unlikely(!ctx->spe_enabled)) { \
6996 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6997 return; \
6998 } \
6999 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7000 cpu_gpr[rB(ctx->opcode)]); \
7001 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7002 cpu_gprh[rB(ctx->opcode)]); \
7003 }
7004 #endif
7005
7006 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7007 {
7008 TCGv_i32 t0;
7009 int l1, l2;
7010
7011 l1 = gen_new_label();
7012 l2 = gen_new_label();
7013 t0 = tcg_temp_local_new_i32();
7014 /* No error here: 6 bits are used */
7015 tcg_gen_andi_i32(t0, arg2, 0x3F);
7016 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7017 tcg_gen_shr_i32(ret, arg1, t0);
7018 tcg_gen_br(l2);
7019 gen_set_label(l1);
7020 tcg_gen_movi_i32(ret, 0);
7021 gen_set_label(l2);
7022 tcg_temp_free_i32(t0);
7023 }
7024 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7025 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7026 {
7027 TCGv_i32 t0;
7028 int l1, l2;
7029
7030 l1 = gen_new_label();
7031 l2 = gen_new_label();
7032 t0 = tcg_temp_local_new_i32();
7033 /* No error here: 6 bits are used */
7034 tcg_gen_andi_i32(t0, arg2, 0x3F);
7035 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7036 tcg_gen_sar_i32(ret, arg1, t0);
7037 tcg_gen_br(l2);
7038 gen_set_label(l1);
7039 tcg_gen_movi_i32(ret, 0);
7040 gen_set_label(l2);
7041 tcg_temp_free_i32(t0);
7042 }
7043 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7044 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7045 {
7046 TCGv_i32 t0;
7047 int l1, l2;
7048
7049 l1 = gen_new_label();
7050 l2 = gen_new_label();
7051 t0 = tcg_temp_local_new_i32();
7052 /* No error here: 6 bits are used */
7053 tcg_gen_andi_i32(t0, arg2, 0x3F);
7054 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7055 tcg_gen_shl_i32(ret, arg1, t0);
7056 tcg_gen_br(l2);
7057 gen_set_label(l1);
7058 tcg_gen_movi_i32(ret, 0);
7059 gen_set_label(l2);
7060 tcg_temp_free_i32(t0);
7061 }
7062 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7063 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7064 {
7065 TCGv_i32 t0 = tcg_temp_new_i32();
7066 tcg_gen_andi_i32(t0, arg2, 0x1F);
7067 tcg_gen_rotl_i32(ret, arg1, t0);
7068 tcg_temp_free_i32(t0);
7069 }
7070 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7071 static inline void gen_evmergehi(DisasContext *ctx)
7072 {
7073 if (unlikely(!ctx->spe_enabled)) {
7074 gen_exception(ctx, POWERPC_EXCP_SPEU);
7075 return;
7076 }
7077 #if defined(TARGET_PPC64)
7078 TCGv t0 = tcg_temp_new();
7079 TCGv t1 = tcg_temp_new();
7080 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7081 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7082 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7083 tcg_temp_free(t0);
7084 tcg_temp_free(t1);
7085 #else
7086 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7087 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7088 #endif
7089 }
7090 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7091 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7092 {
7093 tcg_gen_sub_i32(ret, arg2, arg1);
7094 }
7095 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7096
7097 /* SPE arithmetic immediate */
7098 #if defined(TARGET_PPC64)
7099 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7100 static inline void gen_##name(DisasContext *ctx) \
7101 { \
7102 if (unlikely(!ctx->spe_enabled)) { \
7103 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7104 return; \
7105 } \
7106 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7107 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7108 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7109 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7110 tcg_op(t0, t0, rA(ctx->opcode)); \
7111 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7112 tcg_gen_trunc_i64_i32(t1, t2); \
7113 tcg_temp_free_i64(t2); \
7114 tcg_op(t1, t1, rA(ctx->opcode)); \
7115 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7116 tcg_temp_free_i32(t0); \
7117 tcg_temp_free_i32(t1); \
7118 }
7119 #else
7120 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7121 static inline void gen_##name(DisasContext *ctx) \
7122 { \
7123 if (unlikely(!ctx->spe_enabled)) { \
7124 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7125 return; \
7126 } \
7127 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7128 rA(ctx->opcode)); \
7129 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7130 rA(ctx->opcode)); \
7131 }
7132 #endif
7133 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7134 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7135
7136 /* SPE comparison */
7137 #if defined(TARGET_PPC64)
7138 #define GEN_SPEOP_COMP(name, tcg_cond) \
7139 static inline void gen_##name(DisasContext *ctx) \
7140 { \
7141 if (unlikely(!ctx->spe_enabled)) { \
7142 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7143 return; \
7144 } \
7145 int l1 = gen_new_label(); \
7146 int l2 = gen_new_label(); \
7147 int l3 = gen_new_label(); \
7148 int l4 = gen_new_label(); \
7149 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7150 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7151 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7152 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7153 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7154 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7155 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7156 tcg_gen_br(l2); \
7157 gen_set_label(l1); \
7158 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7159 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7160 gen_set_label(l2); \
7161 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7162 tcg_gen_trunc_i64_i32(t0, t2); \
7163 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7164 tcg_gen_trunc_i64_i32(t1, t2); \
7165 tcg_temp_free_i64(t2); \
7166 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7167 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7168 ~(CRF_CH | CRF_CH_AND_CL)); \
7169 tcg_gen_br(l4); \
7170 gen_set_label(l3); \
7171 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7172 CRF_CH | CRF_CH_OR_CL); \
7173 gen_set_label(l4); \
7174 tcg_temp_free_i32(t0); \
7175 tcg_temp_free_i32(t1); \
7176 }
7177 #else
7178 #define GEN_SPEOP_COMP(name, tcg_cond) \
7179 static inline void gen_##name(DisasContext *ctx) \
7180 { \
7181 if (unlikely(!ctx->spe_enabled)) { \
7182 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7183 return; \
7184 } \
7185 int l1 = gen_new_label(); \
7186 int l2 = gen_new_label(); \
7187 int l3 = gen_new_label(); \
7188 int l4 = gen_new_label(); \
7189 \
7190 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7191 cpu_gpr[rB(ctx->opcode)], l1); \
7192 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7193 tcg_gen_br(l2); \
7194 gen_set_label(l1); \
7195 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7196 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7197 gen_set_label(l2); \
7198 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7199 cpu_gprh[rB(ctx->opcode)], l3); \
7200 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7201 ~(CRF_CH | CRF_CH_AND_CL)); \
7202 tcg_gen_br(l4); \
7203 gen_set_label(l3); \
7204 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7205 CRF_CH | CRF_CH_OR_CL); \
7206 gen_set_label(l4); \
7207 }
7208 #endif
7209 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7210 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7211 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7212 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7213 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7214
7215 /* SPE misc */
7216 static inline void gen_brinc(DisasContext *ctx)
7217 {
7218 /* Note: brinc is usable even if SPE is disabled */
7219 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7220 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7221 }
7222 static inline void gen_evmergelo(DisasContext *ctx)
7223 {
7224 if (unlikely(!ctx->spe_enabled)) {
7225 gen_exception(ctx, POWERPC_EXCP_SPEU);
7226 return;
7227 }
7228 #if defined(TARGET_PPC64)
7229 TCGv t0 = tcg_temp_new();
7230 TCGv t1 = tcg_temp_new();
7231 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7232 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7233 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7234 tcg_temp_free(t0);
7235 tcg_temp_free(t1);
7236 #else
7237 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7238 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7239 #endif
7240 }
7241 static inline void gen_evmergehilo(DisasContext *ctx)
7242 {
7243 if (unlikely(!ctx->spe_enabled)) {
7244 gen_exception(ctx, POWERPC_EXCP_SPEU);
7245 return;
7246 }
7247 #if defined(TARGET_PPC64)
7248 TCGv t0 = tcg_temp_new();
7249 TCGv t1 = tcg_temp_new();
7250 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7251 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7252 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7253 tcg_temp_free(t0);
7254 tcg_temp_free(t1);
7255 #else
7256 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7257 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7258 #endif
7259 }
7260 static inline void gen_evmergelohi(DisasContext *ctx)
7261 {
7262 if (unlikely(!ctx->spe_enabled)) {
7263 gen_exception(ctx, POWERPC_EXCP_SPEU);
7264 return;
7265 }
7266 #if defined(TARGET_PPC64)
7267 TCGv t0 = tcg_temp_new();
7268 TCGv t1 = tcg_temp_new();
7269 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7270 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7271 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7272 tcg_temp_free(t0);
7273 tcg_temp_free(t1);
7274 #else
7275 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7276 TCGv_i32 tmp = tcg_temp_new_i32();
7277 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7278 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7279 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7280 tcg_temp_free_i32(tmp);
7281 } else {
7282 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7283 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7284 }
7285 #endif
7286 }
7287 static inline void gen_evsplati(DisasContext *ctx)
7288 {
7289 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7290
7291 #if defined(TARGET_PPC64)
7292 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7293 #else
7294 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7295 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7296 #endif
7297 }
7298 static inline void gen_evsplatfi(DisasContext *ctx)
7299 {
7300 uint64_t imm = rA(ctx->opcode) << 27;
7301
7302 #if defined(TARGET_PPC64)
7303 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7304 #else
7305 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7306 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7307 #endif
7308 }
7309
7310 static inline void gen_evsel(DisasContext *ctx)
7311 {
7312 int l1 = gen_new_label();
7313 int l2 = gen_new_label();
7314 int l3 = gen_new_label();
7315 int l4 = gen_new_label();
7316 TCGv_i32 t0 = tcg_temp_local_new_i32();
7317 #if defined(TARGET_PPC64)
7318 TCGv t1 = tcg_temp_local_new();
7319 TCGv t2 = tcg_temp_local_new();
7320 #endif
7321 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7322 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7323 #if defined(TARGET_PPC64)
7324 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7325 #else
7326 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7327 #endif
7328 tcg_gen_br(l2);
7329 gen_set_label(l1);
7330 #if defined(TARGET_PPC64)
7331 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7332 #else
7333 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7334 #endif
7335 gen_set_label(l2);
7336 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7337 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7338 #if defined(TARGET_PPC64)
7339 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7340 #else
7341 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7342 #endif
7343 tcg_gen_br(l4);
7344 gen_set_label(l3);
7345 #if defined(TARGET_PPC64)
7346 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7347 #else
7348 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7349 #endif
7350 gen_set_label(l4);
7351 tcg_temp_free_i32(t0);
7352 #if defined(TARGET_PPC64)
7353 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7354 tcg_temp_free(t1);
7355 tcg_temp_free(t2);
7356 #endif
7357 }
7358
7359 static void gen_evsel0(DisasContext *ctx)
7360 {
7361 gen_evsel(ctx);
7362 }
7363
7364 static void gen_evsel1(DisasContext *ctx)
7365 {
7366 gen_evsel(ctx);
7367 }
7368
7369 static void gen_evsel2(DisasContext *ctx)
7370 {
7371 gen_evsel(ctx);
7372 }
7373
7374 static void gen_evsel3(DisasContext *ctx)
7375 {
7376 gen_evsel(ctx);
7377 }
7378
7379 /* Multiply */
7380
7381 static inline void gen_evmwumi(DisasContext *ctx)
7382 {
7383 TCGv_i64 t0, t1;
7384
7385 if (unlikely(!ctx->spe_enabled)) {
7386 gen_exception(ctx, POWERPC_EXCP_SPEU);
7387 return;
7388 }
7389
7390 t0 = tcg_temp_new_i64();
7391 t1 = tcg_temp_new_i64();
7392
7393 /* t0 := rA; t1 := rB */
7394 #if defined(TARGET_PPC64)
7395 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7396 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7397 #else
7398 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7399 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7400 #endif
7401
7402 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7403
7404 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7405
7406 tcg_temp_free_i64(t0);
7407 tcg_temp_free_i64(t1);
7408 }
7409
7410 static inline void gen_evmwumia(DisasContext *ctx)
7411 {
7412 TCGv_i64 tmp;
7413
7414 if (unlikely(!ctx->spe_enabled)) {
7415 gen_exception(ctx, POWERPC_EXCP_SPEU);
7416 return;
7417 }
7418
7419 gen_evmwumi(ctx); /* rD := rA * rB */
7420
7421 tmp = tcg_temp_new_i64();
7422
7423 /* acc := rD */
7424 gen_load_gpr64(tmp, rD(ctx->opcode));
7425 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7426 tcg_temp_free_i64(tmp);
7427 }
7428
7429 static inline void gen_evmwumiaa(DisasContext *ctx)
7430 {
7431 TCGv_i64 acc;
7432 TCGv_i64 tmp;
7433
7434 if (unlikely(!ctx->spe_enabled)) {
7435 gen_exception(ctx, POWERPC_EXCP_SPEU);
7436 return;
7437 }
7438
7439 gen_evmwumi(ctx); /* rD := rA * rB */
7440
7441 acc = tcg_temp_new_i64();
7442 tmp = tcg_temp_new_i64();
7443
7444 /* tmp := rD */
7445 gen_load_gpr64(tmp, rD(ctx->opcode));
7446
7447 /* Load acc */
7448 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7449
7450 /* acc := tmp + acc */
7451 tcg_gen_add_i64(acc, acc, tmp);
7452
7453 /* Store acc */
7454 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7455
7456 /* rD := acc */
7457 gen_store_gpr64(rD(ctx->opcode), acc);
7458
7459 tcg_temp_free_i64(acc);
7460 tcg_temp_free_i64(tmp);
7461 }
7462
7463 static inline void gen_evmwsmi(DisasContext *ctx)
7464 {
7465 TCGv_i64 t0, t1;
7466
7467 if (unlikely(!ctx->spe_enabled)) {
7468 gen_exception(ctx, POWERPC_EXCP_SPEU);
7469 return;
7470 }
7471
7472 t0 = tcg_temp_new_i64();
7473 t1 = tcg_temp_new_i64();
7474
7475 /* t0 := rA; t1 := rB */
7476 #if defined(TARGET_PPC64)
7477 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7478 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7479 #else
7480 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7481 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7482 #endif
7483
7484 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7485
7486 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7487
7488 tcg_temp_free_i64(t0);
7489 tcg_temp_free_i64(t1);
7490 }
7491
7492 static inline void gen_evmwsmia(DisasContext *ctx)
7493 {
7494 TCGv_i64 tmp;
7495
7496 gen_evmwsmi(ctx); /* rD := rA * rB */
7497
7498 tmp = tcg_temp_new_i64();
7499
7500 /* acc := rD */
7501 gen_load_gpr64(tmp, rD(ctx->opcode));
7502 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7503
7504 tcg_temp_free_i64(tmp);
7505 }
7506
7507 static inline void gen_evmwsmiaa(DisasContext *ctx)
7508 {
7509 TCGv_i64 acc = tcg_temp_new_i64();
7510 TCGv_i64 tmp = tcg_temp_new_i64();
7511
7512 gen_evmwsmi(ctx); /* rD := rA * rB */
7513
7514 acc = tcg_temp_new_i64();
7515 tmp = tcg_temp_new_i64();
7516
7517 /* tmp := rD */
7518 gen_load_gpr64(tmp, rD(ctx->opcode));
7519
7520 /* Load acc */
7521 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7522
7523 /* acc := tmp + acc */
7524 tcg_gen_add_i64(acc, acc, tmp);
7525
7526 /* Store acc */
7527 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7528
7529 /* rD := acc */
7530 gen_store_gpr64(rD(ctx->opcode), acc);
7531
7532 tcg_temp_free_i64(acc);
7533 tcg_temp_free_i64(tmp);
7534 }
7535
7536 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7537 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7538 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7539 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7540 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7541 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7542 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7543 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7544 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7545 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7546 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7547 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7548 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7549 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7550 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7551 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7552 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7553 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7554 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7555 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7556 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7557 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7558 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7559 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7560 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7561 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7562 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7563 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7564 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7565
7566 /* SPE load and stores */
7567 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7568 {
7569 target_ulong uimm = rB(ctx->opcode);
7570
7571 if (rA(ctx->opcode) == 0) {
7572 tcg_gen_movi_tl(EA, uimm << sh);
7573 } else {
7574 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7575 if (NARROW_MODE(ctx)) {
7576 tcg_gen_ext32u_tl(EA, EA);
7577 }
7578 }
7579 }
7580
7581 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7582 {
7583 #if defined(TARGET_PPC64)
7584 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7585 #else
7586 TCGv_i64 t0 = tcg_temp_new_i64();
7587 gen_qemu_ld64(ctx, t0, addr);
7588 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7589 tcg_gen_shri_i64(t0, t0, 32);
7590 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7591 tcg_temp_free_i64(t0);
7592 #endif
7593 }
7594
7595 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7596 {
7597 #if defined(TARGET_PPC64)
7598 TCGv t0 = tcg_temp_new();
7599 gen_qemu_ld32u(ctx, t0, addr);
7600 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7601 gen_addr_add(ctx, addr, addr, 4);
7602 gen_qemu_ld32u(ctx, t0, addr);
7603 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7604 tcg_temp_free(t0);
7605 #else
7606 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7607 gen_addr_add(ctx, addr, addr, 4);
7608 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7609 #endif
7610 }
7611
7612 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7613 {
7614 TCGv t0 = tcg_temp_new();
7615 #if defined(TARGET_PPC64)
7616 gen_qemu_ld16u(ctx, t0, addr);
7617 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7618 gen_addr_add(ctx, addr, addr, 2);
7619 gen_qemu_ld16u(ctx, t0, addr);
7620 tcg_gen_shli_tl(t0, t0, 32);
7621 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7622 gen_addr_add(ctx, addr, addr, 2);
7623 gen_qemu_ld16u(ctx, t0, addr);
7624 tcg_gen_shli_tl(t0, t0, 16);
7625 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7626 gen_addr_add(ctx, addr, addr, 2);
7627 gen_qemu_ld16u(ctx, t0, addr);
7628 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7629 #else
7630 gen_qemu_ld16u(ctx, t0, addr);
7631 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7632 gen_addr_add(ctx, addr, addr, 2);
7633 gen_qemu_ld16u(ctx, t0, addr);
7634 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7635 gen_addr_add(ctx, addr, addr, 2);
7636 gen_qemu_ld16u(ctx, t0, addr);
7637 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7638 gen_addr_add(ctx, addr, addr, 2);
7639 gen_qemu_ld16u(ctx, t0, addr);
7640 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7641 #endif
7642 tcg_temp_free(t0);
7643 }
7644
7645 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7646 {
7647 TCGv t0 = tcg_temp_new();
7648 gen_qemu_ld16u(ctx, t0, addr);
7649 #if defined(TARGET_PPC64)
7650 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7651 tcg_gen_shli_tl(t0, t0, 16);
7652 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7653 #else
7654 tcg_gen_shli_tl(t0, t0, 16);
7655 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7656 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7657 #endif
7658 tcg_temp_free(t0);
7659 }
7660
7661 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7662 {
7663 TCGv t0 = tcg_temp_new();
7664 gen_qemu_ld16u(ctx, t0, addr);
7665 #if defined(TARGET_PPC64)
7666 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7667 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7668 #else
7669 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7670 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7671 #endif
7672 tcg_temp_free(t0);
7673 }
7674
7675 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7676 {
7677 TCGv t0 = tcg_temp_new();
7678 gen_qemu_ld16s(ctx, t0, addr);
7679 #if defined(TARGET_PPC64)
7680 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7681 tcg_gen_ext32u_tl(t0, t0);
7682 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7683 #else
7684 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7685 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7686 #endif
7687 tcg_temp_free(t0);
7688 }
7689
7690 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7691 {
7692 TCGv t0 = tcg_temp_new();
7693 #if defined(TARGET_PPC64)
7694 gen_qemu_ld16u(ctx, t0, addr);
7695 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7696 gen_addr_add(ctx, addr, addr, 2);
7697 gen_qemu_ld16u(ctx, t0, addr);
7698 tcg_gen_shli_tl(t0, t0, 16);
7699 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7700 #else
7701 gen_qemu_ld16u(ctx, t0, addr);
7702 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7703 gen_addr_add(ctx, addr, addr, 2);
7704 gen_qemu_ld16u(ctx, t0, addr);
7705 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7706 #endif
7707 tcg_temp_free(t0);
7708 }
7709
7710 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7711 {
7712 #if defined(TARGET_PPC64)
7713 TCGv t0 = tcg_temp_new();
7714 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7715 gen_addr_add(ctx, addr, addr, 2);
7716 gen_qemu_ld16u(ctx, t0, addr);
7717 tcg_gen_shli_tl(t0, t0, 32);
7718 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7719 tcg_temp_free(t0);
7720 #else
7721 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7722 gen_addr_add(ctx, addr, addr, 2);
7723 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7724 #endif
7725 }
7726
7727 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7728 {
7729 #if defined(TARGET_PPC64)
7730 TCGv t0 = tcg_temp_new();
7731 gen_qemu_ld16s(ctx, t0, addr);
7732 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7733 gen_addr_add(ctx, addr, addr, 2);
7734 gen_qemu_ld16s(ctx, t0, addr);
7735 tcg_gen_shli_tl(t0, t0, 32);
7736 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7737 tcg_temp_free(t0);
7738 #else
7739 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7740 gen_addr_add(ctx, addr, addr, 2);
7741 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7742 #endif
7743 }
7744
7745 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7746 {
7747 TCGv t0 = tcg_temp_new();
7748 gen_qemu_ld32u(ctx, t0, addr);
7749 #if defined(TARGET_PPC64)
7750 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7751 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7752 #else
7753 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7754 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7755 #endif
7756 tcg_temp_free(t0);
7757 }
7758
7759 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7760 {
7761 TCGv t0 = tcg_temp_new();
7762 #if defined(TARGET_PPC64)
7763 gen_qemu_ld16u(ctx, t0, addr);
7764 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7765 tcg_gen_shli_tl(t0, t0, 32);
7766 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7767 gen_addr_add(ctx, addr, addr, 2);
7768 gen_qemu_ld16u(ctx, t0, addr);
7769 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7770 tcg_gen_shli_tl(t0, t0, 16);
7771 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7772 #else
7773 gen_qemu_ld16u(ctx, t0, addr);
7774 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7775 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7776 gen_addr_add(ctx, addr, addr, 2);
7777 gen_qemu_ld16u(ctx, t0, addr);
7778 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7779 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7780 #endif
7781 tcg_temp_free(t0);
7782 }
7783
7784 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7785 {
7786 #if defined(TARGET_PPC64)
7787 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7788 #else
7789 TCGv_i64 t0 = tcg_temp_new_i64();
7790 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7791 gen_qemu_st64(ctx, t0, addr);
7792 tcg_temp_free_i64(t0);
7793 #endif
7794 }
7795
7796 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7797 {
7798 #if defined(TARGET_PPC64)
7799 TCGv t0 = tcg_temp_new();
7800 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7801 gen_qemu_st32(ctx, t0, addr);
7802 tcg_temp_free(t0);
7803 #else
7804 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7805 #endif
7806 gen_addr_add(ctx, addr, addr, 4);
7807 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7808 }
7809
7810 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7811 {
7812 TCGv t0 = tcg_temp_new();
7813 #if defined(TARGET_PPC64)
7814 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7815 #else
7816 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7817 #endif
7818 gen_qemu_st16(ctx, t0, addr);
7819 gen_addr_add(ctx, addr, addr, 2);
7820 #if defined(TARGET_PPC64)
7821 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7822 gen_qemu_st16(ctx, t0, addr);
7823 #else
7824 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7825 #endif
7826 gen_addr_add(ctx, addr, addr, 2);
7827 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7828 gen_qemu_st16(ctx, t0, addr);
7829 tcg_temp_free(t0);
7830 gen_addr_add(ctx, addr, addr, 2);
7831 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7832 }
7833
7834 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7835 {
7836 TCGv t0 = tcg_temp_new();
7837 #if defined(TARGET_PPC64)
7838 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7839 #else
7840 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7841 #endif
7842 gen_qemu_st16(ctx, t0, addr);
7843 gen_addr_add(ctx, addr, addr, 2);
7844 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7845 gen_qemu_st16(ctx, t0, addr);
7846 tcg_temp_free(t0);
7847 }
7848
7849 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7850 {
7851 #if defined(TARGET_PPC64)
7852 TCGv t0 = tcg_temp_new();
7853 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7854 gen_qemu_st16(ctx, t0, addr);
7855 tcg_temp_free(t0);
7856 #else
7857 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7858 #endif
7859 gen_addr_add(ctx, addr, addr, 2);
7860 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7861 }
7862
7863 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7864 {
7865 #if defined(TARGET_PPC64)
7866 TCGv t0 = tcg_temp_new();
7867 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7868 gen_qemu_st32(ctx, t0, addr);
7869 tcg_temp_free(t0);
7870 #else
7871 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7872 #endif
7873 }
7874
7875 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7876 {
7877 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7878 }
7879
7880 #define GEN_SPEOP_LDST(name, opc2, sh) \
7881 static void glue(gen_, name)(DisasContext *ctx) \
7882 { \
7883 TCGv t0; \
7884 if (unlikely(!ctx->spe_enabled)) { \
7885 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7886 return; \
7887 } \
7888 gen_set_access_type(ctx, ACCESS_INT); \
7889 t0 = tcg_temp_new(); \
7890 if (Rc(ctx->opcode)) { \
7891 gen_addr_spe_imm_index(ctx, t0, sh); \
7892 } else { \
7893 gen_addr_reg_index(ctx, t0); \
7894 } \
7895 gen_op_##name(ctx, t0); \
7896 tcg_temp_free(t0); \
7897 }
7898
7899 GEN_SPEOP_LDST(evldd, 0x00, 3);
7900 GEN_SPEOP_LDST(evldw, 0x01, 3);
7901 GEN_SPEOP_LDST(evldh, 0x02, 3);
7902 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7903 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7904 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7905 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7906 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7907 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7908 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7909 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7910
7911 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7912 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7913 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7914 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7915 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7916 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7917 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7918
7919 /* Multiply and add - TODO */
7920 #if 0
7921 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7922 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7923 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7924 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7925 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7926 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7927 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7928 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7929 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7930 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7931 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7932 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7933
7934 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7935 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7936 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7937 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7938 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7939 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7940 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7941 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7942 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7943 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7944 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7945 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7946
7947 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7948 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7949 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7950 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7951 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7952
7953 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7954 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7955 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7956 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7957 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7958 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7959 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7960 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7961 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7962 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7963 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7964 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7965
7966 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7967 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7968 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7969 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7970
7971 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7972 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7973 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7974 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7975 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7976 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7977 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7978 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7979 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7980 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7981 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7982 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7983
7984 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7985 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7986 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7987 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7988 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7989 #endif
7990
7991 /*** SPE floating-point extension ***/
7992 #if defined(TARGET_PPC64)
7993 #define GEN_SPEFPUOP_CONV_32_32(name) \
7994 static inline void gen_##name(DisasContext *ctx) \
7995 { \
7996 TCGv_i32 t0; \
7997 TCGv t1; \
7998 t0 = tcg_temp_new_i32(); \
7999 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8000 gen_helper_##name(t0, cpu_env, t0); \
8001 t1 = tcg_temp_new(); \
8002 tcg_gen_extu_i32_tl(t1, t0); \
8003 tcg_temp_free_i32(t0); \
8004 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8005 0xFFFFFFFF00000000ULL); \
8006 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8007 tcg_temp_free(t1); \
8008 }
8009 #define GEN_SPEFPUOP_CONV_32_64(name) \
8010 static inline void gen_##name(DisasContext *ctx) \
8011 { \
8012 TCGv_i32 t0; \
8013 TCGv t1; \
8014 t0 = tcg_temp_new_i32(); \
8015 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8016 t1 = tcg_temp_new(); \
8017 tcg_gen_extu_i32_tl(t1, t0); \
8018 tcg_temp_free_i32(t0); \
8019 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8020 0xFFFFFFFF00000000ULL); \
8021 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8022 tcg_temp_free(t1); \
8023 }
8024 #define GEN_SPEFPUOP_CONV_64_32(name) \
8025 static inline void gen_##name(DisasContext *ctx) \
8026 { \
8027 TCGv_i32 t0 = tcg_temp_new_i32(); \
8028 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8029 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8030 tcg_temp_free_i32(t0); \
8031 }
8032 #define GEN_SPEFPUOP_CONV_64_64(name) \
8033 static inline void gen_##name(DisasContext *ctx) \
8034 { \
8035 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8036 cpu_gpr[rB(ctx->opcode)]); \
8037 }
8038 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8039 static inline void gen_##name(DisasContext *ctx) \
8040 { \
8041 TCGv_i32 t0, t1; \
8042 TCGv_i64 t2; \
8043 if (unlikely(!ctx->spe_enabled)) { \
8044 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8045 return; \
8046 } \
8047 t0 = tcg_temp_new_i32(); \
8048 t1 = tcg_temp_new_i32(); \
8049 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8050 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8051 gen_helper_##name(t0, cpu_env, t0, t1); \
8052 tcg_temp_free_i32(t1); \
8053 t2 = tcg_temp_new(); \
8054 tcg_gen_extu_i32_tl(t2, t0); \
8055 tcg_temp_free_i32(t0); \
8056 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8057 0xFFFFFFFF00000000ULL); \
8058 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8059 tcg_temp_free(t2); \
8060 }
8061 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8062 static inline void gen_##name(DisasContext *ctx) \
8063 { \
8064 if (unlikely(!ctx->spe_enabled)) { \
8065 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8066 return; \
8067 } \
8068 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8069 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8070 }
8071 #define GEN_SPEFPUOP_COMP_32(name) \
8072 static inline void gen_##name(DisasContext *ctx) \
8073 { \
8074 TCGv_i32 t0, t1; \
8075 if (unlikely(!ctx->spe_enabled)) { \
8076 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8077 return; \
8078 } \
8079 t0 = tcg_temp_new_i32(); \
8080 t1 = tcg_temp_new_i32(); \
8081 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8082 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8083 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8084 tcg_temp_free_i32(t0); \
8085 tcg_temp_free_i32(t1); \
8086 }
8087 #define GEN_SPEFPUOP_COMP_64(name) \
8088 static inline void gen_##name(DisasContext *ctx) \
8089 { \
8090 if (unlikely(!ctx->spe_enabled)) { \
8091 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8092 return; \
8093 } \
8094 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8095 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8096 }
8097 #else
8098 #define GEN_SPEFPUOP_CONV_32_32(name) \
8099 static inline void gen_##name(DisasContext *ctx) \
8100 { \
8101 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8102 cpu_gpr[rB(ctx->opcode)]); \
8103 }
8104 #define GEN_SPEFPUOP_CONV_32_64(name) \
8105 static inline void gen_##name(DisasContext *ctx) \
8106 { \
8107 TCGv_i64 t0 = tcg_temp_new_i64(); \
8108 gen_load_gpr64(t0, rB(ctx->opcode)); \
8109 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8110 tcg_temp_free_i64(t0); \
8111 }
8112 #define GEN_SPEFPUOP_CONV_64_32(name) \
8113 static inline void gen_##name(DisasContext *ctx) \
8114 { \
8115 TCGv_i64 t0 = tcg_temp_new_i64(); \
8116 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8117 gen_store_gpr64(rD(ctx->opcode), t0); \
8118 tcg_temp_free_i64(t0); \
8119 }
8120 #define GEN_SPEFPUOP_CONV_64_64(name) \
8121 static inline void gen_##name(DisasContext *ctx) \
8122 { \
8123 TCGv_i64 t0 = tcg_temp_new_i64(); \
8124 gen_load_gpr64(t0, rB(ctx->opcode)); \
8125 gen_helper_##name(t0, cpu_env, t0); \
8126 gen_store_gpr64(rD(ctx->opcode), t0); \
8127 tcg_temp_free_i64(t0); \
8128 }
8129 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8130 static inline void gen_##name(DisasContext *ctx) \
8131 { \
8132 if (unlikely(!ctx->spe_enabled)) { \
8133 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8134 return; \
8135 } \
8136 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8137 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8138 }
8139 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8140 static inline void gen_##name(DisasContext *ctx) \
8141 { \
8142 TCGv_i64 t0, t1; \
8143 if (unlikely(!ctx->spe_enabled)) { \
8144 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8145 return; \
8146 } \
8147 t0 = tcg_temp_new_i64(); \
8148 t1 = tcg_temp_new_i64(); \
8149 gen_load_gpr64(t0, rA(ctx->opcode)); \
8150 gen_load_gpr64(t1, rB(ctx->opcode)); \
8151 gen_helper_##name(t0, cpu_env, t0, t1); \
8152 gen_store_gpr64(rD(ctx->opcode), t0); \
8153 tcg_temp_free_i64(t0); \
8154 tcg_temp_free_i64(t1); \
8155 }
8156 #define GEN_SPEFPUOP_COMP_32(name) \
8157 static inline void gen_##name(DisasContext *ctx) \
8158 { \
8159 if (unlikely(!ctx->spe_enabled)) { \
8160 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8161 return; \
8162 } \
8163 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8164 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8165 }
8166 #define GEN_SPEFPUOP_COMP_64(name) \
8167 static inline void gen_##name(DisasContext *ctx) \
8168 { \
8169 TCGv_i64 t0, t1; \
8170 if (unlikely(!ctx->spe_enabled)) { \
8171 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8172 return; \
8173 } \
8174 t0 = tcg_temp_new_i64(); \
8175 t1 = tcg_temp_new_i64(); \
8176 gen_load_gpr64(t0, rA(ctx->opcode)); \
8177 gen_load_gpr64(t1, rB(ctx->opcode)); \
8178 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8179 tcg_temp_free_i64(t0); \
8180 tcg_temp_free_i64(t1); \
8181 }
8182 #endif
8183
8184 /* Single precision floating-point vectors operations */
8185 /* Arithmetic */
8186 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8187 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8188 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8189 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8190 static inline void gen_evfsabs(DisasContext *ctx)
8191 {
8192 if (unlikely(!ctx->spe_enabled)) {
8193 gen_exception(ctx, POWERPC_EXCP_SPEU);
8194 return;
8195 }
8196 #if defined(TARGET_PPC64)
8197 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8198 #else
8199 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8200 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8201 #endif
8202 }
8203 static inline void gen_evfsnabs(DisasContext *ctx)
8204 {
8205 if (unlikely(!ctx->spe_enabled)) {
8206 gen_exception(ctx, POWERPC_EXCP_SPEU);
8207 return;
8208 }
8209 #if defined(TARGET_PPC64)
8210 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8211 #else
8212 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8213 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8214 #endif
8215 }
8216 static inline void gen_evfsneg(DisasContext *ctx)
8217 {
8218 if (unlikely(!ctx->spe_enabled)) {
8219 gen_exception(ctx, POWERPC_EXCP_SPEU);
8220 return;
8221 }
8222 #if defined(TARGET_PPC64)
8223 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8224 #else
8225 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8226 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8227 #endif
8228 }
8229
8230 /* Conversion */
8231 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8232 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8233 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8234 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8235 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8236 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8237 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8238 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8239 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8240 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8241
8242 /* Comparison */
8243 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8244 GEN_SPEFPUOP_COMP_64(evfscmplt);
8245 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8246 GEN_SPEFPUOP_COMP_64(evfststgt);
8247 GEN_SPEFPUOP_COMP_64(evfststlt);
8248 GEN_SPEFPUOP_COMP_64(evfststeq);
8249
8250 /* Opcodes definitions */
8251 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8252 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8253 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8254 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8255 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8256 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8257 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8258 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8259 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8260 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8261 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8262 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8263 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8264 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8265
8266 /* Single precision floating-point operations */
8267 /* Arithmetic */
8268 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8269 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8270 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8271 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8272 static inline void gen_efsabs(DisasContext *ctx)
8273 {
8274 if (unlikely(!ctx->spe_enabled)) {
8275 gen_exception(ctx, POWERPC_EXCP_SPEU);
8276 return;
8277 }
8278 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8279 }
8280 static inline void gen_efsnabs(DisasContext *ctx)
8281 {
8282 if (unlikely(!ctx->spe_enabled)) {
8283 gen_exception(ctx, POWERPC_EXCP_SPEU);
8284 return;
8285 }
8286 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8287 }
8288 static inline void gen_efsneg(DisasContext *ctx)
8289 {
8290 if (unlikely(!ctx->spe_enabled)) {
8291 gen_exception(ctx, POWERPC_EXCP_SPEU);
8292 return;
8293 }
8294 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8295 }
8296
8297 /* Conversion */
8298 GEN_SPEFPUOP_CONV_32_32(efscfui);
8299 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8300 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8301 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8302 GEN_SPEFPUOP_CONV_32_32(efsctui);
8303 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8304 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8305 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8306 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8307 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8308 GEN_SPEFPUOP_CONV_32_64(efscfd);
8309
8310 /* Comparison */
8311 GEN_SPEFPUOP_COMP_32(efscmpgt);
8312 GEN_SPEFPUOP_COMP_32(efscmplt);
8313 GEN_SPEFPUOP_COMP_32(efscmpeq);
8314 GEN_SPEFPUOP_COMP_32(efststgt);
8315 GEN_SPEFPUOP_COMP_32(efststlt);
8316 GEN_SPEFPUOP_COMP_32(efststeq);
8317
8318 /* Opcodes definitions */
8319 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8320 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8321 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8322 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8323 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8324 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8325 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8326 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8327 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8328 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8329 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8330 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8331 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8332 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8333
8334 /* Double precision floating-point operations */
8335 /* Arithmetic */
8336 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8337 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8338 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8339 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8340 static inline void gen_efdabs(DisasContext *ctx)
8341 {
8342 if (unlikely(!ctx->spe_enabled)) {
8343 gen_exception(ctx, POWERPC_EXCP_SPEU);
8344 return;
8345 }
8346 #if defined(TARGET_PPC64)
8347 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8348 #else
8349 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8350 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8351 #endif
8352 }
8353 static inline void gen_efdnabs(DisasContext *ctx)
8354 {
8355 if (unlikely(!ctx->spe_enabled)) {
8356 gen_exception(ctx, POWERPC_EXCP_SPEU);
8357 return;
8358 }
8359 #if defined(TARGET_PPC64)
8360 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8361 #else
8362 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8363 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8364 #endif
8365 }
8366 static inline void gen_efdneg(DisasContext *ctx)
8367 {
8368 if (unlikely(!ctx->spe_enabled)) {
8369 gen_exception(ctx, POWERPC_EXCP_SPEU);
8370 return;
8371 }
8372 #if defined(TARGET_PPC64)
8373 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8374 #else
8375 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8376 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8377 #endif
8378 }
8379
8380 /* Conversion */
8381 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8382 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8383 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8384 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8385 GEN_SPEFPUOP_CONV_32_64(efdctui);
8386 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8387 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8388 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8389 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8390 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8391 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8392 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8393 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8394 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8395 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8396
8397 /* Comparison */
8398 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8399 GEN_SPEFPUOP_COMP_64(efdcmplt);
8400 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8401 GEN_SPEFPUOP_COMP_64(efdtstgt);
8402 GEN_SPEFPUOP_COMP_64(efdtstlt);
8403 GEN_SPEFPUOP_COMP_64(efdtsteq);
8404
8405 /* Opcodes definitions */
8406 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8407 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8408 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8409 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8410 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8411 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8412 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8413 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8414 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8415 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8416 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8417 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8418 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8419 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8420 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8421 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8422
8423 static opcode_t opcodes[] = {
8424 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8425 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8426 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8427 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8428 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8429 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8430 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8431 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8432 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8433 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8434 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8435 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8436 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8437 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8438 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8439 #if defined(TARGET_PPC64)
8440 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8441 #endif
8442 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8443 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8444 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8445 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8446 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8447 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8448 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8449 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8450 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8451 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8452 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8453 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8454 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8455 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8456 #if defined(TARGET_PPC64)
8457 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8458 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8459 #endif
8460 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8461 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8462 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8463 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8464 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8465 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8466 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8467 #if defined(TARGET_PPC64)
8468 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8469 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8470 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8471 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8472 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8473 #endif
8474 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8475 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8476 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8477 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8478 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8479 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8480 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8481 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8482 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8483 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8484 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8485 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8486 #if defined(TARGET_PPC64)
8487 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8488 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8489 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8490 #endif
8491 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8492 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8493 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8494 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8495 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8496 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8497 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8498 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8499 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8500 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8501 #if defined(TARGET_PPC64)
8502 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8503 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8504 #endif
8505 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8506 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8507 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8508 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8509 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8510 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8511 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8512 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8513 #if defined(TARGET_PPC64)
8514 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8515 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8516 #endif
8517 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8518 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8519 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8520 #if defined(TARGET_PPC64)
8521 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8522 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8523 #endif
8524 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8525 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8526 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8527 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8528 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8529 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8530 #if defined(TARGET_PPC64)
8531 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8532 #endif
8533 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8534 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8535 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8536 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8537 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8538 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8539 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8540 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8541 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8542 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8543 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8544 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8545 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8546 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8547 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8548 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8549 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8550 #if defined(TARGET_PPC64)
8551 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8552 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8553 PPC_SEGMENT_64B),
8554 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8555 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8556 PPC_SEGMENT_64B),
8557 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8558 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8559 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8560 #endif
8561 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8562 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8563 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8564 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8565 #if defined(TARGET_PPC64)
8566 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8567 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8568 #endif
8569 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8570 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8571 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8572 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8573 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8574 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8575 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8576 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8577 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8578 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8579 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8580 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8581 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8582 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8583 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8584 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8585 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8586 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8587 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8588 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8589 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8590 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8591 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8592 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8593 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8594 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8595 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8596 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8597 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8598 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8599 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8600 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8601 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8602 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8603 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8604 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8605 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8606 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8607 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8608 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8609 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8610 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8611 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8612 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8613 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8614 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8615 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8616 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8617 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8618 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8619 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8620 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8621 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8622 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8623 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8624 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8625 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8626 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8627 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8628 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8629 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8630 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8631 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8632 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8633 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8634 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8635 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8636 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8637 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8638 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8639 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8640 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8641 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8642 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8643 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8644 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8645 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8646 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8647 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8648 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8649 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8650 PPC_NONE, PPC2_BOOKE206),
8651 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8652 PPC_NONE, PPC2_BOOKE206),
8653 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8654 PPC_NONE, PPC2_BOOKE206),
8655 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8656 PPC_NONE, PPC2_BOOKE206),
8657 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8658 PPC_NONE, PPC2_BOOKE206),
8659 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8660 PPC_NONE, PPC2_PRCNTL),
8661 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8662 PPC_NONE, PPC2_PRCNTL),
8663 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8664 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8665 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8666 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8667 PPC_BOOKE, PPC2_BOOKE206),
8668 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8669 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8670 PPC_BOOKE, PPC2_BOOKE206),
8671 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8672 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8673 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8674 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8675 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8676 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8677 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8678 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8679 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8680 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8681
8682 #undef GEN_INT_ARITH_ADD
8683 #undef GEN_INT_ARITH_ADD_CONST
8684 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8685 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8686 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8687 add_ca, compute_ca, compute_ov) \
8688 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8689 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8690 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8691 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8692 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8693 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8694 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8695 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8696 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8697 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8698 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8699
8700 #undef GEN_INT_ARITH_DIVW
8701 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8702 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8703 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8704 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8705 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8706 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8707
8708 #if defined(TARGET_PPC64)
8709 #undef GEN_INT_ARITH_DIVD
8710 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8711 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8712 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8713 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8714 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8715 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8716
8717 #undef GEN_INT_ARITH_MUL_HELPER
8718 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8719 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8720 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8721 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8722 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8723 #endif
8724
8725 #undef GEN_INT_ARITH_SUBF
8726 #undef GEN_INT_ARITH_SUBF_CONST
8727 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8728 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8729 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8730 add_ca, compute_ca, compute_ov) \
8731 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8732 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8733 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8734 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8735 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8736 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8737 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8738 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8739 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8740 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8741 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8742
8743 #undef GEN_LOGICAL1
8744 #undef GEN_LOGICAL2
8745 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8746 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8747 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8748 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8749 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8750 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8751 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8752 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8753 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8754 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8755 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8756 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8757 #if defined(TARGET_PPC64)
8758 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8759 #endif
8760
8761 #if defined(TARGET_PPC64)
8762 #undef GEN_PPC64_R2
8763 #undef GEN_PPC64_R4
8764 #define GEN_PPC64_R2(name, opc1, opc2) \
8765 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8766 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8767 PPC_64B)
8768 #define GEN_PPC64_R4(name, opc1, opc2) \
8769 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8770 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8771 PPC_64B), \
8772 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8773 PPC_64B), \
8774 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8775 PPC_64B)
8776 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8777 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8778 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8779 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8780 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8781 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8782 #endif
8783
8784 #undef _GEN_FLOAT_ACB
8785 #undef GEN_FLOAT_ACB
8786 #undef _GEN_FLOAT_AB
8787 #undef GEN_FLOAT_AB
8788 #undef _GEN_FLOAT_AC
8789 #undef GEN_FLOAT_AC
8790 #undef GEN_FLOAT_B
8791 #undef GEN_FLOAT_BS
8792 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8793 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8794 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8795 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8796 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8797 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8798 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8799 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8800 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8801 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8802 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8803 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8804 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8805 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8806 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8807 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8808 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8809 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8810 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8811
8812 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8813 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8814 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8815 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8816 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8817 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8818 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8819 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8820 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8821 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8822 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8823 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8824 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8825 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8826 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8827 #if defined(TARGET_PPC64)
8828 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8829 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8830 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8831 #endif
8832 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8833 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8834 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8835 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8836 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8837 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8838 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8839
8840 #undef GEN_LD
8841 #undef GEN_LDU
8842 #undef GEN_LDUX
8843 #undef GEN_LDX_E
8844 #undef GEN_LDS
8845 #define GEN_LD(name, ldop, opc, type) \
8846 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8847 #define GEN_LDU(name, ldop, opc, type) \
8848 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8849 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8850 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8851 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8852 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8853 #define GEN_LDS(name, ldop, op, type) \
8854 GEN_LD(name, ldop, op | 0x20, type) \
8855 GEN_LDU(name, ldop, op | 0x21, type) \
8856 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8857 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8858
8859 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8860 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8861 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8862 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8863 #if defined(TARGET_PPC64)
8864 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8865 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8866 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8867 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8868 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8869 #endif
8870 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8871 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8872
8873 #undef GEN_ST
8874 #undef GEN_STU
8875 #undef GEN_STUX
8876 #undef GEN_STX_E
8877 #undef GEN_STS
8878 #define GEN_ST(name, stop, opc, type) \
8879 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8880 #define GEN_STU(name, stop, opc, type) \
8881 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8882 #define GEN_STUX(name, stop, opc2, opc3, type) \
8883 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8884 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8885 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8886 #define GEN_STS(name, stop, op, type) \
8887 GEN_ST(name, stop, op | 0x20, type) \
8888 GEN_STU(name, stop, op | 0x21, type) \
8889 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8890 GEN_STX(name, stop, 0x17, op | 0x00, type)
8891
8892 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8893 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8894 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8895 #if defined(TARGET_PPC64)
8896 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8897 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8898 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8899 #endif
8900 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8901 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8902
8903 #undef GEN_LDF
8904 #undef GEN_LDUF
8905 #undef GEN_LDUXF
8906 #undef GEN_LDXF
8907 #undef GEN_LDFS
8908 #define GEN_LDF(name, ldop, opc, type) \
8909 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8910 #define GEN_LDUF(name, ldop, opc, type) \
8911 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8912 #define GEN_LDUXF(name, ldop, opc, type) \
8913 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8914 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8915 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8916 #define GEN_LDFS(name, ldop, op, type) \
8917 GEN_LDF(name, ldop, op | 0x20, type) \
8918 GEN_LDUF(name, ldop, op | 0x21, type) \
8919 GEN_LDUXF(name, ldop, op | 0x01, type) \
8920 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8921
8922 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8923 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8924
8925 #undef GEN_STF
8926 #undef GEN_STUF
8927 #undef GEN_STUXF
8928 #undef GEN_STXF
8929 #undef GEN_STFS
8930 #define GEN_STF(name, stop, opc, type) \
8931 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8932 #define GEN_STUF(name, stop, opc, type) \
8933 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8934 #define GEN_STUXF(name, stop, opc, type) \
8935 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8936 #define GEN_STXF(name, stop, opc2, opc3, type) \
8937 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8938 #define GEN_STFS(name, stop, op, type) \
8939 GEN_STF(name, stop, op | 0x20, type) \
8940 GEN_STUF(name, stop, op | 0x21, type) \
8941 GEN_STUXF(name, stop, op | 0x01, type) \
8942 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8943
8944 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8945 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8946 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8947
8948 #undef GEN_CRLOGIC
8949 #define GEN_CRLOGIC(name, tcg_op, opc) \
8950 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8951 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8952 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8953 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8954 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8955 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8956 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8957 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8958 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8959
8960 #undef GEN_MAC_HANDLER
8961 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8962 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8963 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8964 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8965 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8966 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8967 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8968 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8969 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8970 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8971 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8972 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8973 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8974 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8975 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8976 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8977 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8978 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8979 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8980 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8981 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8982 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8983 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8984 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8985 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8986 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8987 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8988 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8989 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8990 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8991 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8992 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8993 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8994 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
8995 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
8996 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
8997 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
8998 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
8999 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9000 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9001 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9002 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9003 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9004 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9005
9006 #undef GEN_VR_LDX
9007 #undef GEN_VR_STX
9008 #undef GEN_VR_LVE
9009 #undef GEN_VR_STVE
9010 #define GEN_VR_LDX(name, opc2, opc3) \
9011 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9012 #define GEN_VR_STX(name, opc2, opc3) \
9013 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9014 #define GEN_VR_LVE(name, opc2, opc3) \
9015 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9016 #define GEN_VR_STVE(name, opc2, opc3) \
9017 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9018 GEN_VR_LDX(lvx, 0x07, 0x03),
9019 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9020 GEN_VR_LVE(bx, 0x07, 0x00),
9021 GEN_VR_LVE(hx, 0x07, 0x01),
9022 GEN_VR_LVE(wx, 0x07, 0x02),
9023 GEN_VR_STX(svx, 0x07, 0x07),
9024 GEN_VR_STX(svxl, 0x07, 0x0F),
9025 GEN_VR_STVE(bx, 0x07, 0x04),
9026 GEN_VR_STVE(hx, 0x07, 0x05),
9027 GEN_VR_STVE(wx, 0x07, 0x06),
9028
9029 #undef GEN_VX_LOGICAL
9030 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9031 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9032 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9033 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9034 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9035 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9036 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9037
9038 #undef GEN_VXFORM
9039 #define GEN_VXFORM(name, opc2, opc3) \
9040 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9041 GEN_VXFORM(vaddubm, 0, 0),
9042 GEN_VXFORM(vadduhm, 0, 1),
9043 GEN_VXFORM(vadduwm, 0, 2),
9044 GEN_VXFORM(vsububm, 0, 16),
9045 GEN_VXFORM(vsubuhm, 0, 17),
9046 GEN_VXFORM(vsubuwm, 0, 18),
9047 GEN_VXFORM(vmaxub, 1, 0),
9048 GEN_VXFORM(vmaxuh, 1, 1),
9049 GEN_VXFORM(vmaxuw, 1, 2),
9050 GEN_VXFORM(vmaxsb, 1, 4),
9051 GEN_VXFORM(vmaxsh, 1, 5),
9052 GEN_VXFORM(vmaxsw, 1, 6),
9053 GEN_VXFORM(vminub, 1, 8),
9054 GEN_VXFORM(vminuh, 1, 9),
9055 GEN_VXFORM(vminuw, 1, 10),
9056 GEN_VXFORM(vminsb, 1, 12),
9057 GEN_VXFORM(vminsh, 1, 13),
9058 GEN_VXFORM(vminsw, 1, 14),
9059 GEN_VXFORM(vavgub, 1, 16),
9060 GEN_VXFORM(vavguh, 1, 17),
9061 GEN_VXFORM(vavguw, 1, 18),
9062 GEN_VXFORM(vavgsb, 1, 20),
9063 GEN_VXFORM(vavgsh, 1, 21),
9064 GEN_VXFORM(vavgsw, 1, 22),
9065 GEN_VXFORM(vmrghb, 6, 0),
9066 GEN_VXFORM(vmrghh, 6, 1),
9067 GEN_VXFORM(vmrghw, 6, 2),
9068 GEN_VXFORM(vmrglb, 6, 4),
9069 GEN_VXFORM(vmrglh, 6, 5),
9070 GEN_VXFORM(vmrglw, 6, 6),
9071 GEN_VXFORM(vmuloub, 4, 0),
9072 GEN_VXFORM(vmulouh, 4, 1),
9073 GEN_VXFORM(vmulosb, 4, 4),
9074 GEN_VXFORM(vmulosh, 4, 5),
9075 GEN_VXFORM(vmuleub, 4, 8),
9076 GEN_VXFORM(vmuleuh, 4, 9),
9077 GEN_VXFORM(vmulesb, 4, 12),
9078 GEN_VXFORM(vmulesh, 4, 13),
9079 GEN_VXFORM(vslb, 2, 4),
9080 GEN_VXFORM(vslh, 2, 5),
9081 GEN_VXFORM(vslw, 2, 6),
9082 GEN_VXFORM(vsrb, 2, 8),
9083 GEN_VXFORM(vsrh, 2, 9),
9084 GEN_VXFORM(vsrw, 2, 10),
9085 GEN_VXFORM(vsrab, 2, 12),
9086 GEN_VXFORM(vsrah, 2, 13),
9087 GEN_VXFORM(vsraw, 2, 14),
9088 GEN_VXFORM(vslo, 6, 16),
9089 GEN_VXFORM(vsro, 6, 17),
9090 GEN_VXFORM(vaddcuw, 0, 6),
9091 GEN_VXFORM(vsubcuw, 0, 22),
9092 GEN_VXFORM(vaddubs, 0, 8),
9093 GEN_VXFORM(vadduhs, 0, 9),
9094 GEN_VXFORM(vadduws, 0, 10),
9095 GEN_VXFORM(vaddsbs, 0, 12),
9096 GEN_VXFORM(vaddshs, 0, 13),
9097 GEN_VXFORM(vaddsws, 0, 14),
9098 GEN_VXFORM(vsububs, 0, 24),
9099 GEN_VXFORM(vsubuhs, 0, 25),
9100 GEN_VXFORM(vsubuws, 0, 26),
9101 GEN_VXFORM(vsubsbs, 0, 28),
9102 GEN_VXFORM(vsubshs, 0, 29),
9103 GEN_VXFORM(vsubsws, 0, 30),
9104 GEN_VXFORM(vrlb, 2, 0),
9105 GEN_VXFORM(vrlh, 2, 1),
9106 GEN_VXFORM(vrlw, 2, 2),
9107 GEN_VXFORM(vsl, 2, 7),
9108 GEN_VXFORM(vsr, 2, 11),
9109 GEN_VXFORM(vpkuhum, 7, 0),
9110 GEN_VXFORM(vpkuwum, 7, 1),
9111 GEN_VXFORM(vpkuhus, 7, 2),
9112 GEN_VXFORM(vpkuwus, 7, 3),
9113 GEN_VXFORM(vpkshus, 7, 4),
9114 GEN_VXFORM(vpkswus, 7, 5),
9115 GEN_VXFORM(vpkshss, 7, 6),
9116 GEN_VXFORM(vpkswss, 7, 7),
9117 GEN_VXFORM(vpkpx, 7, 12),
9118 GEN_VXFORM(vsum4ubs, 4, 24),
9119 GEN_VXFORM(vsum4sbs, 4, 28),
9120 GEN_VXFORM(vsum4shs, 4, 25),
9121 GEN_VXFORM(vsum2sws, 4, 26),
9122 GEN_VXFORM(vsumsws, 4, 30),
9123 GEN_VXFORM(vaddfp, 5, 0),
9124 GEN_VXFORM(vsubfp, 5, 1),
9125 GEN_VXFORM(vmaxfp, 5, 16),
9126 GEN_VXFORM(vminfp, 5, 17),
9127
9128 #undef GEN_VXRFORM1
9129 #undef GEN_VXRFORM
9130 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9131 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9132 #define GEN_VXRFORM(name, opc2, opc3) \
9133 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9134 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9135 GEN_VXRFORM(vcmpequb, 3, 0)
9136 GEN_VXRFORM(vcmpequh, 3, 1)
9137 GEN_VXRFORM(vcmpequw, 3, 2)
9138 GEN_VXRFORM(vcmpgtsb, 3, 12)
9139 GEN_VXRFORM(vcmpgtsh, 3, 13)
9140 GEN_VXRFORM(vcmpgtsw, 3, 14)
9141 GEN_VXRFORM(vcmpgtub, 3, 8)
9142 GEN_VXRFORM(vcmpgtuh, 3, 9)
9143 GEN_VXRFORM(vcmpgtuw, 3, 10)
9144 GEN_VXRFORM(vcmpeqfp, 3, 3)
9145 GEN_VXRFORM(vcmpgefp, 3, 7)
9146 GEN_VXRFORM(vcmpgtfp, 3, 11)
9147 GEN_VXRFORM(vcmpbfp, 3, 15)
9148
9149 #undef GEN_VXFORM_SIMM
9150 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9151 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9152 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9153 GEN_VXFORM_SIMM(vspltish, 6, 13),
9154 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9155
9156 #undef GEN_VXFORM_NOA
9157 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9158 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9159 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9160 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9161 GEN_VXFORM_NOA(vupklsb, 7, 10),
9162 GEN_VXFORM_NOA(vupklsh, 7, 11),
9163 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9164 GEN_VXFORM_NOA(vupklpx, 7, 15),
9165 GEN_VXFORM_NOA(vrefp, 5, 4),
9166 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9167 GEN_VXFORM_NOA(vexptefp, 5, 6),
9168 GEN_VXFORM_NOA(vlogefp, 5, 7),
9169 GEN_VXFORM_NOA(vrfim, 5, 8),
9170 GEN_VXFORM_NOA(vrfin, 5, 9),
9171 GEN_VXFORM_NOA(vrfip, 5, 10),
9172 GEN_VXFORM_NOA(vrfiz, 5, 11),
9173
9174 #undef GEN_VXFORM_UIMM
9175 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9176 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9177 GEN_VXFORM_UIMM(vspltb, 6, 8),
9178 GEN_VXFORM_UIMM(vsplth, 6, 9),
9179 GEN_VXFORM_UIMM(vspltw, 6, 10),
9180 GEN_VXFORM_UIMM(vcfux, 5, 12),
9181 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9182 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9183 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9184
9185 #undef GEN_VAFORM_PAIRED
9186 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9187 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9188 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9189 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9190 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9191 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9192 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9193 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9194
9195 #undef GEN_SPE
9196 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9197 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9198 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9199 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9200 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9201 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9202 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9203 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9204 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9205 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9206 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9207 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9208 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9209 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9210 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9211 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9212 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9213 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9214 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9215 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9216 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9217 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9218 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9219 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9220 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9221 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9222 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9223 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9224 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9225 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9226 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9227
9228 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9229 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9230 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9231 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9232 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9233 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9234 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9235 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9236 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9237 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9238 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9239 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9240 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9241 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9242
9243 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9244 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9245 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9246 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9247 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9248 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9249 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9250 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9251 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9252 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9253 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9254 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9255 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9256 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9257
9258 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9259 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9260 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9261 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9262 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9263 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9264 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9265 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9266 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9267 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9268 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9269 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9270 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9271 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9272 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9273 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9274
9275 #undef GEN_SPEOP_LDST
9276 #define GEN_SPEOP_LDST(name, opc2, sh) \
9277 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9278 GEN_SPEOP_LDST(evldd, 0x00, 3),
9279 GEN_SPEOP_LDST(evldw, 0x01, 3),
9280 GEN_SPEOP_LDST(evldh, 0x02, 3),
9281 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9282 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9283 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9284 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9285 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9286 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9287 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9288 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9289
9290 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9291 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9292 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9293 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9294 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9295 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9296 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9297 };
9298
9299 #include "helper_regs.h"
9300 #include "translate_init.c"
9301
9302 /*****************************************************************************/
9303 /* Misc PowerPC helpers */
9304 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9305 int flags)
9306 {
9307 #define RGPL 4
9308 #define RFPL 4
9309
9310 int i;
9311
9312 cpu_synchronize_state(env);
9313
9314 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9315 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9316 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9317 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9318 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9319 env->hflags, env->mmu_idx);
9320 #if !defined(NO_TIMER_DUMP)
9321 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9322 #if !defined(CONFIG_USER_ONLY)
9323 " DECR %08" PRIu32
9324 #endif
9325 "\n",
9326 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9327 #if !defined(CONFIG_USER_ONLY)
9328 , cpu_ppc_load_decr(env)
9329 #endif
9330 );
9331 #endif
9332 for (i = 0; i < 32; i++) {
9333 if ((i & (RGPL - 1)) == 0)
9334 cpu_fprintf(f, "GPR%02d", i);
9335 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9336 if ((i & (RGPL - 1)) == (RGPL - 1))
9337 cpu_fprintf(f, "\n");
9338 }
9339 cpu_fprintf(f, "CR ");
9340 for (i = 0; i < 8; i++)
9341 cpu_fprintf(f, "%01x", env->crf[i]);
9342 cpu_fprintf(f, " [");
9343 for (i = 0; i < 8; i++) {
9344 char a = '-';
9345 if (env->crf[i] & 0x08)
9346 a = 'L';
9347 else if (env->crf[i] & 0x04)
9348 a = 'G';
9349 else if (env->crf[i] & 0x02)
9350 a = 'E';
9351 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9352 }
9353 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9354 env->reserve_addr);
9355 for (i = 0; i < 32; i++) {
9356 if ((i & (RFPL - 1)) == 0)
9357 cpu_fprintf(f, "FPR%02d", i);
9358 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9359 if ((i & (RFPL - 1)) == (RFPL - 1))
9360 cpu_fprintf(f, "\n");
9361 }
9362 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9363 #if !defined(CONFIG_USER_ONLY)
9364 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9365 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9366 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9367 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9368
9369 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9370 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9371 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9372 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9373
9374 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9375 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9376 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9377 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9378
9379 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9380 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9381 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9382 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9383 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9384
9385 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9386 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9387 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9388 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9389
9390 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9391 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9392 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9393 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9394
9395 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9396 " EPR " TARGET_FMT_lx "\n",
9397 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9398 env->spr[SPR_BOOKE_EPR]);
9399
9400 /* FSL-specific */
9401 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9402 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9403 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9404 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9405
9406 /*
9407 * IVORs are left out as they are large and do not change often --
9408 * they can be read with "p $ivor0", "p $ivor1", etc.
9409 */
9410 }
9411
9412 #if defined(TARGET_PPC64)
9413 if (env->flags & POWERPC_FLAG_CFAR) {
9414 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9415 }
9416 #endif
9417
9418 switch (env->mmu_model) {
9419 case POWERPC_MMU_32B:
9420 case POWERPC_MMU_601:
9421 case POWERPC_MMU_SOFT_6xx:
9422 case POWERPC_MMU_SOFT_74xx:
9423 #if defined(TARGET_PPC64)
9424 case POWERPC_MMU_64B:
9425 #endif
9426 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9427 break;
9428 case POWERPC_MMU_BOOKE206:
9429 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9430 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9431 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9432 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9433
9434 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9435 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9436 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9437 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9438
9439 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9440 " TLB1CFG " TARGET_FMT_lx "\n",
9441 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9442 env->spr[SPR_BOOKE_TLB1CFG]);
9443 break;
9444 default:
9445 break;
9446 }
9447 #endif
9448
9449 #undef RGPL
9450 #undef RFPL
9451 }
9452
9453 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9454 int flags)
9455 {
9456 #if defined(DO_PPC_STATISTICS)
9457 opc_handler_t **t1, **t2, **t3, *handler;
9458 int op1, op2, op3;
9459
9460 t1 = env->opcodes;
9461 for (op1 = 0; op1 < 64; op1++) {
9462 handler = t1[op1];
9463 if (is_indirect_opcode(handler)) {
9464 t2 = ind_table(handler);
9465 for (op2 = 0; op2 < 32; op2++) {
9466 handler = t2[op2];
9467 if (is_indirect_opcode(handler)) {
9468 t3 = ind_table(handler);
9469 for (op3 = 0; op3 < 32; op3++) {
9470 handler = t3[op3];
9471 if (handler->count == 0)
9472 continue;
9473 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9474 "%016" PRIx64 " %" PRId64 "\n",
9475 op1, op2, op3, op1, (op3 << 5) | op2,
9476 handler->oname,
9477 handler->count, handler->count);
9478 }
9479 } else {
9480 if (handler->count == 0)
9481 continue;
9482 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9483 "%016" PRIx64 " %" PRId64 "\n",
9484 op1, op2, op1, op2, handler->oname,
9485 handler->count, handler->count);
9486 }
9487 }
9488 } else {
9489 if (handler->count == 0)
9490 continue;
9491 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9492 " %" PRId64 "\n",
9493 op1, op1, handler->oname,
9494 handler->count, handler->count);
9495 }
9496 }
9497 #endif
9498 }
9499
9500 /*****************************************************************************/
9501 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9502 TranslationBlock *tb,
9503 int search_pc)
9504 {
9505 DisasContext ctx, *ctxp = &ctx;
9506 opc_handler_t **table, *handler;
9507 target_ulong pc_start;
9508 uint16_t *gen_opc_end;
9509 CPUBreakpoint *bp;
9510 int j, lj = -1;
9511 int num_insns;
9512 int max_insns;
9513
9514 pc_start = tb->pc;
9515 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9516 ctx.nip = pc_start;
9517 ctx.tb = tb;
9518 ctx.exception = POWERPC_EXCP_NONE;
9519 ctx.spr_cb = env->spr_cb;
9520 ctx.mem_idx = env->mmu_idx;
9521 ctx.access_type = -1;
9522 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9523 #if defined(TARGET_PPC64)
9524 ctx.sf_mode = msr_is_64bit(env, env->msr);
9525 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9526 #endif
9527 ctx.fpu_enabled = msr_fp;
9528 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9529 ctx.spe_enabled = msr_spe;
9530 else
9531 ctx.spe_enabled = 0;
9532 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9533 ctx.altivec_enabled = msr_vr;
9534 else
9535 ctx.altivec_enabled = 0;
9536 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9537 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9538 else
9539 ctx.singlestep_enabled = 0;
9540 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9541 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9542 if (unlikely(env->singlestep_enabled))
9543 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9544 #if defined (DO_SINGLE_STEP) && 0
9545 /* Single step trace mode */
9546 msr_se = 1;
9547 #endif
9548 num_insns = 0;
9549 max_insns = tb->cflags & CF_COUNT_MASK;
9550 if (max_insns == 0)
9551 max_insns = CF_COUNT_MASK;
9552
9553 gen_tb_start();
9554 /* Set env in case of segfault during code fetch */
9555 while (ctx.exception == POWERPC_EXCP_NONE
9556 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9557 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9558 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9559 if (bp->pc == ctx.nip) {
9560 gen_debug_exception(ctxp);
9561 break;
9562 }
9563 }
9564 }
9565 if (unlikely(search_pc)) {
9566 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9567 if (lj < j) {
9568 lj++;
9569 while (lj < j)
9570 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9571 }
9572 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9573 tcg_ctx.gen_opc_instr_start[lj] = 1;
9574 tcg_ctx.gen_opc_icount[lj] = num_insns;
9575 }
9576 LOG_DISAS("----------------\n");
9577 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9578 ctx.nip, ctx.mem_idx, (int)msr_ir);
9579 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9580 gen_io_start();
9581 if (unlikely(ctx.le_mode)) {
9582 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9583 } else {
9584 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9585 }
9586 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9587 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9588 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9589 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9590 tcg_gen_debug_insn_start(ctx.nip);
9591 }
9592 ctx.nip += 4;
9593 table = env->opcodes;
9594 num_insns++;
9595 handler = table[opc1(ctx.opcode)];
9596 if (is_indirect_opcode(handler)) {
9597 table = ind_table(handler);
9598 handler = table[opc2(ctx.opcode)];
9599 if (is_indirect_opcode(handler)) {
9600 table = ind_table(handler);
9601 handler = table[opc3(ctx.opcode)];
9602 }
9603 }
9604 /* Is opcode *REALLY* valid ? */
9605 if (unlikely(handler->handler == &gen_invalid)) {
9606 if (qemu_log_enabled()) {
9607 qemu_log("invalid/unsupported opcode: "
9608 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9609 opc1(ctx.opcode), opc2(ctx.opcode),
9610 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9611 }
9612 } else {
9613 uint32_t inval;
9614
9615 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9616 inval = handler->inval2;
9617 } else {
9618 inval = handler->inval1;
9619 }
9620
9621 if (unlikely((ctx.opcode & inval) != 0)) {
9622 if (qemu_log_enabled()) {
9623 qemu_log("invalid bits: %08x for opcode: "
9624 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9625 ctx.opcode & inval, opc1(ctx.opcode),
9626 opc2(ctx.opcode), opc3(ctx.opcode),
9627 ctx.opcode, ctx.nip - 4);
9628 }
9629 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9630 break;
9631 }
9632 }
9633 (*(handler->handler))(&ctx);
9634 #if defined(DO_PPC_STATISTICS)
9635 handler->count++;
9636 #endif
9637 /* Check trace mode exceptions */
9638 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9639 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9640 ctx.exception != POWERPC_SYSCALL &&
9641 ctx.exception != POWERPC_EXCP_TRAP &&
9642 ctx.exception != POWERPC_EXCP_BRANCH)) {
9643 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9644 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9645 (env->singlestep_enabled) ||
9646 singlestep ||
9647 num_insns >= max_insns)) {
9648 /* if we reach a page boundary or are single stepping, stop
9649 * generation
9650 */
9651 break;
9652 }
9653 }
9654 if (tb->cflags & CF_LAST_IO)
9655 gen_io_end();
9656 if (ctx.exception == POWERPC_EXCP_NONE) {
9657 gen_goto_tb(&ctx, 0, ctx.nip);
9658 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9659 if (unlikely(env->singlestep_enabled)) {
9660 gen_debug_exception(ctxp);
9661 }
9662 /* Generate the return instruction */
9663 tcg_gen_exit_tb(0);
9664 }
9665 gen_tb_end(tb, num_insns);
9666 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9667 if (unlikely(search_pc)) {
9668 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9669 lj++;
9670 while (lj <= j)
9671 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9672 } else {
9673 tb->size = ctx.nip - pc_start;
9674 tb->icount = num_insns;
9675 }
9676 #if defined(DEBUG_DISAS)
9677 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9678 int flags;
9679 flags = env->bfd_mach;
9680 flags |= ctx.le_mode << 16;
9681 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9682 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9683 qemu_log("\n");
9684 }
9685 #endif
9686 }
9687
9688 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9689 {
9690 gen_intermediate_code_internal(env, tb, 0);
9691 }
9692
9693 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9694 {
9695 gen_intermediate_code_internal(env, tb, 1);
9696 }
9697
9698 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9699 {
9700 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9701 }
Qemu copy for testing