]> git.proxmox.com Git - qemu.git/blob - target-ppc/translate.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target-ppc: Use add2 for carry generation
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 struct opc_handler_t {
208 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
209 uint32_t inval1;
210 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
211 uint32_t inval2;
212 /* instruction type */
213 uint64_t type;
214 /* extended instruction type */
215 uint64_t type2;
216 /* handler */
217 void (*handler)(DisasContext *ctx);
218 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
219 const char *oname;
220 #endif
221 #if defined(DO_PPC_STATISTICS)
222 uint64_t count;
223 #endif
224 };
225
226 static inline void gen_reset_fpstatus(void)
227 {
228 gen_helper_reset_fpstatus(cpu_env);
229 }
230
231 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
232 {
233 TCGv_i32 t0 = tcg_temp_new_i32();
234
235 if (set_fprf != 0) {
236 /* This case might be optimized later */
237 tcg_gen_movi_i32(t0, 1);
238 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
239 if (unlikely(set_rc)) {
240 tcg_gen_mov_i32(cpu_crf[1], t0);
241 }
242 gen_helper_float_check_status(cpu_env);
243 } else if (unlikely(set_rc)) {
244 /* We always need to compute fpcc */
245 tcg_gen_movi_i32(t0, 0);
246 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249
250 tcg_temp_free_i32(t0);
251 }
252
253 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
254 {
255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
259 }
260
261 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
262 {
263 #if defined(TARGET_PPC64)
264 if (ctx->sf_mode)
265 tcg_gen_movi_tl(cpu_nip, nip);
266 else
267 #endif
268 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
269 }
270
271 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
272 {
273 TCGv_i32 t0, t1;
274 if (ctx->exception == POWERPC_EXCP_NONE) {
275 gen_update_nip(ctx, ctx->nip);
276 }
277 t0 = tcg_const_i32(excp);
278 t1 = tcg_const_i32(error);
279 gen_helper_raise_exception_err(cpu_env, t0, t1);
280 tcg_temp_free_i32(t0);
281 tcg_temp_free_i32(t1);
282 ctx->exception = (excp);
283 }
284
285 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
286 {
287 TCGv_i32 t0;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 gen_helper_raise_exception(cpu_env, t0);
293 tcg_temp_free_i32(t0);
294 ctx->exception = (excp);
295 }
296
297 static inline void gen_debug_exception(DisasContext *ctx)
298 {
299 TCGv_i32 t0;
300
301 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
302 (ctx->exception != POWERPC_EXCP_SYNC)) {
303 gen_update_nip(ctx, ctx->nip);
304 }
305 t0 = tcg_const_i32(EXCP_DEBUG);
306 gen_helper_raise_exception(cpu_env, t0);
307 tcg_temp_free_i32(t0);
308 }
309
310 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
311 {
312 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
313 }
314
315 /* Stop translation */
316 static inline void gen_stop_exception(DisasContext *ctx)
317 {
318 gen_update_nip(ctx, ctx->nip);
319 ctx->exception = POWERPC_EXCP_STOP;
320 }
321
322 /* No need to update nip here, as execution flow will change */
323 static inline void gen_sync_exception(DisasContext *ctx)
324 {
325 ctx->exception = POWERPC_EXCP_SYNC;
326 }
327
328 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
333
334 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
335 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
336
337 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
338 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
339
340 typedef struct opcode_t {
341 unsigned char opc1, opc2, opc3;
342 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
343 unsigned char pad[5];
344 #else
345 unsigned char pad[1];
346 #endif
347 opc_handler_t handler;
348 const char *oname;
349 } opcode_t;
350
351 /*****************************************************************************/
352 /*** Instruction decoding ***/
353 #define EXTRACT_HELPER(name, shift, nb) \
354 static inline uint32_t name(uint32_t opcode) \
355 { \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
357 }
358
359 #define EXTRACT_SHELPER(name, shift, nb) \
360 static inline int32_t name(uint32_t opcode) \
361 { \
362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
363 }
364
365 /* Opcode part 1 */
366 EXTRACT_HELPER(opc1, 26, 6);
367 /* Opcode part 2 */
368 EXTRACT_HELPER(opc2, 1, 5);
369 /* Opcode part 3 */
370 EXTRACT_HELPER(opc3, 6, 5);
371 /* Update Cr0 flags */
372 EXTRACT_HELPER(Rc, 0, 1);
373 /* Destination */
374 EXTRACT_HELPER(rD, 21, 5);
375 /* Source */
376 EXTRACT_HELPER(rS, 21, 5);
377 /* First operand */
378 EXTRACT_HELPER(rA, 16, 5);
379 /* Second operand */
380 EXTRACT_HELPER(rB, 11, 5);
381 /* Third operand */
382 EXTRACT_HELPER(rC, 6, 5);
383 /*** Get CRn ***/
384 EXTRACT_HELPER(crfD, 23, 3);
385 EXTRACT_HELPER(crfS, 18, 3);
386 EXTRACT_HELPER(crbD, 21, 5);
387 EXTRACT_HELPER(crbA, 16, 5);
388 EXTRACT_HELPER(crbB, 11, 5);
389 /* SPR / TBL */
390 EXTRACT_HELPER(_SPR, 11, 10);
391 static inline uint32_t SPR(uint32_t opcode)
392 {
393 uint32_t sprn = _SPR(opcode);
394
395 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
396 }
397 /*** Get constants ***/
398 EXTRACT_HELPER(IMM, 12, 8);
399 /* 16 bits signed immediate value */
400 EXTRACT_SHELPER(SIMM, 0, 16);
401 /* 16 bits unsigned immediate value */
402 EXTRACT_HELPER(UIMM, 0, 16);
403 /* 5 bits signed immediate value */
404 EXTRACT_HELPER(SIMM5, 16, 5);
405 /* 5 bits signed immediate value */
406 EXTRACT_HELPER(UIMM5, 16, 5);
407 /* Bit count */
408 EXTRACT_HELPER(NB, 11, 5);
409 /* Shift count */
410 EXTRACT_HELPER(SH, 11, 5);
411 /* Vector shift count */
412 EXTRACT_HELPER(VSH, 6, 4);
413 /* Mask start */
414 EXTRACT_HELPER(MB, 6, 5);
415 /* Mask end */
416 EXTRACT_HELPER(ME, 1, 5);
417 /* Trap operand */
418 EXTRACT_HELPER(TO, 21, 5);
419
420 EXTRACT_HELPER(CRM, 12, 8);
421 EXTRACT_HELPER(FM, 17, 8);
422 EXTRACT_HELPER(SR, 16, 4);
423 EXTRACT_HELPER(FPIMM, 12, 4);
424
425 /*** Jump target decoding ***/
426 /* Displacement */
427 EXTRACT_SHELPER(d, 0, 16);
428 /* Immediate address */
429 static inline target_ulong LI(uint32_t opcode)
430 {
431 return (opcode >> 0) & 0x03FFFFFC;
432 }
433
434 static inline uint32_t BD(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0xFFFC;
437 }
438
439 EXTRACT_HELPER(BO, 21, 5);
440 EXTRACT_HELPER(BI, 16, 5);
441 /* Absolute/relative address */
442 EXTRACT_HELPER(AA, 1, 1);
443 /* Link */
444 EXTRACT_HELPER(LK, 0, 1);
445
446 /* Create a mask between <start> and <end> bits */
447 static inline target_ulong MASK(uint32_t start, uint32_t end)
448 {
449 target_ulong ret;
450
451 #if defined(TARGET_PPC64)
452 if (likely(start == 0)) {
453 ret = UINT64_MAX << (63 - end);
454 } else if (likely(end == 63)) {
455 ret = UINT64_MAX >> start;
456 }
457 #else
458 if (likely(start == 0)) {
459 ret = UINT32_MAX << (31 - end);
460 } else if (likely(end == 31)) {
461 ret = UINT32_MAX >> start;
462 }
463 #endif
464 else {
465 ret = (((target_ulong)(-1ULL)) >> (start)) ^
466 (((target_ulong)(-1ULL) >> (end)) >> 1);
467 if (unlikely(start > end))
468 return ~ret;
469 }
470
471 return ret;
472 }
473
474 /*****************************************************************************/
475 /* PowerPC instructions table */
476
477 #if defined(DO_PPC_STATISTICS)
478 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
479 { \
480 .opc1 = op1, \
481 .opc2 = op2, \
482 .opc3 = op3, \
483 .pad = { 0, }, \
484 .handler = { \
485 .inval1 = invl, \
486 .type = _typ, \
487 .type2 = _typ2, \
488 .handler = &gen_##name, \
489 .oname = stringify(name), \
490 }, \
491 .oname = stringify(name), \
492 }
493 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
494 { \
495 .opc1 = op1, \
496 .opc2 = op2, \
497 .opc3 = op3, \
498 .pad = { 0, }, \
499 .handler = { \
500 .inval1 = invl1, \
501 .inval2 = invl2, \
502 .type = _typ, \
503 .type2 = _typ2, \
504 .handler = &gen_##name, \
505 .oname = stringify(name), \
506 }, \
507 .oname = stringify(name), \
508 }
509 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
510 { \
511 .opc1 = op1, \
512 .opc2 = op2, \
513 .opc3 = op3, \
514 .pad = { 0, }, \
515 .handler = { \
516 .inval1 = invl, \
517 .type = _typ, \
518 .type2 = _typ2, \
519 .handler = &gen_##name, \
520 .oname = onam, \
521 }, \
522 .oname = onam, \
523 }
524 #else
525 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
526 { \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl, \
533 .type = _typ, \
534 .type2 = _typ2, \
535 .handler = &gen_##name, \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
548 .type = _typ, \
549 .type2 = _typ2, \
550 .handler = &gen_##name, \
551 }, \
552 .oname = stringify(name), \
553 }
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555 { \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 }, \
566 .oname = onam, \
567 }
568 #endif
569
570 /* SPR load/store helpers */
571 static inline void gen_load_spr(TCGv t, int reg)
572 {
573 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
574 }
575
576 static inline void gen_store_spr(int reg, TCGv t)
577 {
578 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 /* Invalid instruction */
582 static void gen_invalid(DisasContext *ctx)
583 {
584 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
585 }
586
587 static opc_handler_t invalid_handler = {
588 .inval1 = 0xFFFFFFFF,
589 .inval2 = 0xFFFFFFFF,
590 .type = PPC_NONE,
591 .type2 = PPC_NONE,
592 .handler = gen_invalid,
593 };
594
595 /*** Integer comparison ***/
596
597 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
598 {
599 TCGv t0 = tcg_temp_new();
600 TCGv_i32 t1 = tcg_temp_new_i32();
601
602 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
603
604 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
605 tcg_gen_trunc_tl_i32(t1, t0);
606 tcg_gen_shli_i32(t1, t1, CRF_LT);
607 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_GT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_EQ);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_temp_free(t0);
620 tcg_temp_free_i32(t1);
621 }
622
623 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
624 {
625 TCGv t0 = tcg_const_tl(arg1);
626 gen_op_cmp(arg0, t0, s, crf);
627 tcg_temp_free(t0);
628 }
629
630 #if defined(TARGET_PPC64)
631 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
632 {
633 TCGv t0, t1;
634 t0 = tcg_temp_new();
635 t1 = tcg_temp_new();
636 if (s) {
637 tcg_gen_ext32s_tl(t0, arg0);
638 tcg_gen_ext32s_tl(t1, arg1);
639 } else {
640 tcg_gen_ext32u_tl(t0, arg0);
641 tcg_gen_ext32u_tl(t1, arg1);
642 }
643 gen_op_cmp(t0, t1, s, crf);
644 tcg_temp_free(t1);
645 tcg_temp_free(t0);
646 }
647
648 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
649 {
650 TCGv t0 = tcg_const_tl(arg1);
651 gen_op_cmp32(arg0, t0, s, crf);
652 tcg_temp_free(t0);
653 }
654 #endif
655
656 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
657 {
658 #if defined(TARGET_PPC64)
659 if (!(ctx->sf_mode))
660 gen_op_cmpi32(reg, 0, 1, 0);
661 else
662 #endif
663 gen_op_cmpi(reg, 0, 1, 0);
664 }
665
666 /* cmp */
667 static void gen_cmp(DisasContext *ctx)
668 {
669 #if defined(TARGET_PPC64)
670 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
671 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 else
674 #endif
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678
679 /* cmpi */
680 static void gen_cmpi(DisasContext *ctx)
681 {
682 #if defined(TARGET_PPC64)
683 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 else
687 #endif
688 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
689 1, crfD(ctx->opcode));
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 #if defined(TARGET_PPC64)
696 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 else
700 #endif
701 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
702 0, crfD(ctx->opcode));
703 }
704
705 /* cmpli */
706 static void gen_cmpli(DisasContext *ctx)
707 {
708 #if defined(TARGET_PPC64)
709 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
710 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712 else
713 #endif
714 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
715 0, crfD(ctx->opcode));
716 }
717
718 /* isel (PowerPC 2.03 specification) */
719 static void gen_isel(DisasContext *ctx)
720 {
721 int l1, l2;
722 uint32_t bi = rC(ctx->opcode);
723 uint32_t mask;
724 TCGv_i32 t0;
725
726 l1 = gen_new_label();
727 l2 = gen_new_label();
728
729 mask = 1 << (3 - (bi & 0x03));
730 t0 = tcg_temp_new_i32();
731 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
732 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
733 if (rA(ctx->opcode) == 0)
734 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
735 else
736 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
737 tcg_gen_br(l2);
738 gen_set_label(l1);
739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
740 gen_set_label(l2);
741 tcg_temp_free_i32(t0);
742 }
743
744 /*** Integer arithmetic ***/
745
746 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
747 TCGv arg1, TCGv arg2, int sub)
748 {
749 TCGv t0 = tcg_temp_new();
750
751 tcg_gen_xor_tl(cpu_ov, arg0, arg1);
752 tcg_gen_xor_tl(t0, arg1, arg2);
753 if (sub) {
754 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
755 } else {
756 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
757 }
758 tcg_temp_free(t0);
759 #if defined(TARGET_PPC64)
760 if (!ctx->sf_mode) {
761 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
762 }
763 #endif
764 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
765 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
766 }
767
768 /* Common add function */
769 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
770 TCGv arg2, bool add_ca, bool compute_ca,
771 bool compute_ov, bool compute_rc0)
772 {
773 TCGv t0 = ret;
774
775 if (((compute_ca && add_ca) || compute_ov)
776 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
777 t0 = tcg_temp_new();
778 }
779
780 if (compute_ca) {
781 TCGv zero = tcg_const_tl(0);
782 if (add_ca) {
783 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
784 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
785 } else {
786 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
787 }
788 tcg_temp_free(zero);
789 } else {
790 tcg_gen_add_tl(t0, arg1, arg2);
791 if (add_ca) {
792 tcg_gen_add_tl(t0, t0, cpu_ca);
793 }
794 }
795
796 if (compute_ov) {
797 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
798 }
799 if (unlikely(compute_rc0)) {
800 gen_set_Rc0(ctx, t0);
801 }
802
803 if (!TCGV_EQUAL(t0, ret)) {
804 tcg_gen_mov_tl(ret, t0);
805 tcg_temp_free(t0);
806 }
807 }
808 /* Add functions with two operands */
809 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
810 static void glue(gen_, name)(DisasContext *ctx) \
811 { \
812 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
813 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
814 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
815 }
816 /* Add functions with one operand and one immediate */
817 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
818 add_ca, compute_ca, compute_ov) \
819 static void glue(gen_, name)(DisasContext *ctx) \
820 { \
821 TCGv t0 = tcg_const_tl(const_val); \
822 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
823 cpu_gpr[rA(ctx->opcode)], t0, \
824 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
825 tcg_temp_free(t0); \
826 }
827
828 /* add add. addo addo. */
829 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
830 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
831 /* addc addc. addco addco. */
832 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
833 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
834 /* adde adde. addeo addeo. */
835 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
836 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
837 /* addme addme. addmeo addmeo. */
838 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
839 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
840 /* addze addze. addzeo addzeo.*/
841 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
842 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
843 /* addi */
844 static void gen_addi(DisasContext *ctx)
845 {
846 target_long simm = SIMM(ctx->opcode);
847
848 if (rA(ctx->opcode) == 0) {
849 /* li case */
850 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
851 } else {
852 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
853 cpu_gpr[rA(ctx->opcode)], simm);
854 }
855 }
856 /* addic addic.*/
857 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
858 {
859 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
860 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
861 c, 0, 1, 0, compute_rc0);
862 tcg_temp_free(c);
863 }
864
865 static void gen_addic(DisasContext *ctx)
866 {
867 gen_op_addic(ctx, 0);
868 }
869
870 static void gen_addic_(DisasContext *ctx)
871 {
872 gen_op_addic(ctx, 1);
873 }
874
875 /* addis */
876 static void gen_addis(DisasContext *ctx)
877 {
878 target_long simm = SIMM(ctx->opcode);
879
880 if (rA(ctx->opcode) == 0) {
881 /* lis case */
882 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
883 } else {
884 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
885 cpu_gpr[rA(ctx->opcode)], simm << 16);
886 }
887 }
888
889 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
890 TCGv arg2, int sign, int compute_ov)
891 {
892 int l1 = gen_new_label();
893 int l2 = gen_new_label();
894 TCGv_i32 t0 = tcg_temp_local_new_i32();
895 TCGv_i32 t1 = tcg_temp_local_new_i32();
896
897 tcg_gen_trunc_tl_i32(t0, arg1);
898 tcg_gen_trunc_tl_i32(t1, arg2);
899 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
900 if (sign) {
901 int l3 = gen_new_label();
902 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
903 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
904 gen_set_label(l3);
905 tcg_gen_div_i32(t0, t0, t1);
906 } else {
907 tcg_gen_divu_i32(t0, t0, t1);
908 }
909 if (compute_ov) {
910 tcg_gen_movi_tl(cpu_ov, 0);
911 }
912 tcg_gen_br(l2);
913 gen_set_label(l1);
914 if (sign) {
915 tcg_gen_sari_i32(t0, t0, 31);
916 } else {
917 tcg_gen_movi_i32(t0, 0);
918 }
919 if (compute_ov) {
920 tcg_gen_movi_tl(cpu_ov, 1);
921 tcg_gen_movi_tl(cpu_so, 1);
922 }
923 gen_set_label(l2);
924 tcg_gen_extu_i32_tl(ret, t0);
925 tcg_temp_free_i32(t0);
926 tcg_temp_free_i32(t1);
927 if (unlikely(Rc(ctx->opcode) != 0))
928 gen_set_Rc0(ctx, ret);
929 }
930 /* Div functions */
931 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
932 static void glue(gen_, name)(DisasContext *ctx) \
933 { \
934 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
935 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
936 sign, compute_ov); \
937 }
938 /* divwu divwu. divwuo divwuo. */
939 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
940 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
941 /* divw divw. divwo divwo. */
942 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
943 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
944 #if defined(TARGET_PPC64)
945 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
946 TCGv arg2, int sign, int compute_ov)
947 {
948 int l1 = gen_new_label();
949 int l2 = gen_new_label();
950
951 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
952 if (sign) {
953 int l3 = gen_new_label();
954 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
955 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
956 gen_set_label(l3);
957 tcg_gen_div_i64(ret, arg1, arg2);
958 } else {
959 tcg_gen_divu_i64(ret, arg1, arg2);
960 }
961 if (compute_ov) {
962 tcg_gen_movi_tl(cpu_ov, 0);
963 }
964 tcg_gen_br(l2);
965 gen_set_label(l1);
966 if (sign) {
967 tcg_gen_sari_i64(ret, arg1, 63);
968 } else {
969 tcg_gen_movi_i64(ret, 0);
970 }
971 if (compute_ov) {
972 tcg_gen_movi_tl(cpu_ov, 1);
973 tcg_gen_movi_tl(cpu_so, 1);
974 }
975 gen_set_label(l2);
976 if (unlikely(Rc(ctx->opcode) != 0))
977 gen_set_Rc0(ctx, ret);
978 }
979 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
980 static void glue(gen_, name)(DisasContext *ctx) \
981 { \
982 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
984 sign, compute_ov); \
985 }
986 /* divwu divwu. divwuo divwuo. */
987 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
988 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
989 /* divw divw. divwo divwo. */
990 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
991 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
992 #endif
993
994 /* mulhw mulhw. */
995 static void gen_mulhw(DisasContext *ctx)
996 {
997 TCGv_i32 t0 = tcg_temp_new_i32();
998 TCGv_i32 t1 = tcg_temp_new_i32();
999
1000 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1001 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1002 tcg_gen_muls2_i32(t0, t1, t0, t1);
1003 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1004 tcg_temp_free_i32(t0);
1005 tcg_temp_free_i32(t1);
1006 if (unlikely(Rc(ctx->opcode) != 0))
1007 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1008 }
1009
1010 /* mulhwu mulhwu. */
1011 static void gen_mulhwu(DisasContext *ctx)
1012 {
1013 TCGv_i32 t0 = tcg_temp_new_i32();
1014 TCGv_i32 t1 = tcg_temp_new_i32();
1015
1016 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1017 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1018 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1019 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1020 tcg_temp_free_i32(t0);
1021 tcg_temp_free_i32(t1);
1022 if (unlikely(Rc(ctx->opcode) != 0))
1023 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1024 }
1025
1026 /* mullw mullw. */
1027 static void gen_mullw(DisasContext *ctx)
1028 {
1029 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1030 cpu_gpr[rB(ctx->opcode)]);
1031 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1032 if (unlikely(Rc(ctx->opcode) != 0))
1033 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1034 }
1035
1036 /* mullwo mullwo. */
1037 static void gen_mullwo(DisasContext *ctx)
1038 {
1039 int l1;
1040 TCGv_i64 t0, t1;
1041
1042 t0 = tcg_temp_new_i64();
1043 t1 = tcg_temp_new_i64();
1044 l1 = gen_new_label();
1045 /* Start with XER OV disabled, the most likely case */
1046 tcg_gen_movi_tl(cpu_ov, 0);
1047 #if defined(TARGET_PPC64)
1048 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1049 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1050 #else
1051 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1052 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1053 #endif
1054 tcg_gen_mul_i64(t0, t0, t1);
1055 #if defined(TARGET_PPC64)
1056 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1057 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1058 #else
1059 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1060 tcg_gen_ext32s_i64(t1, t0);
1061 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1062 #endif
1063 tcg_gen_movi_tl(cpu_ov, 1);
1064 tcg_gen_movi_tl(cpu_so, 1);
1065 gen_set_label(l1);
1066 tcg_temp_free_i64(t0);
1067 tcg_temp_free_i64(t1);
1068 if (unlikely(Rc(ctx->opcode) != 0))
1069 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1070 }
1071
1072 /* mulli */
1073 static void gen_mulli(DisasContext *ctx)
1074 {
1075 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1076 SIMM(ctx->opcode));
1077 }
1078
1079 #if defined(TARGET_PPC64)
1080 /* mulhd mulhd. */
1081 static void gen_mulhd(DisasContext *ctx)
1082 {
1083 TCGv lo = tcg_temp_new();
1084 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1085 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1086 tcg_temp_free(lo);
1087 if (unlikely(Rc(ctx->opcode) != 0)) {
1088 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1089 }
1090 }
1091
1092 /* mulhdu mulhdu. */
1093 static void gen_mulhdu(DisasContext *ctx)
1094 {
1095 TCGv lo = tcg_temp_new();
1096 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1097 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1098 tcg_temp_free(lo);
1099 if (unlikely(Rc(ctx->opcode) != 0)) {
1100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1101 }
1102 }
1103
1104 /* mulld mulld. */
1105 static void gen_mulld(DisasContext *ctx)
1106 {
1107 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1108 cpu_gpr[rB(ctx->opcode)]);
1109 if (unlikely(Rc(ctx->opcode) != 0))
1110 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1111 }
1112
1113 /* mulldo mulldo. */
1114 static void gen_mulldo(DisasContext *ctx)
1115 {
1116 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1117 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1118 if (unlikely(Rc(ctx->opcode) != 0)) {
1119 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1120 }
1121 }
1122 #endif
1123
1124 /* neg neg. nego nego. */
1125 static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1126 int ov_check)
1127 {
1128 int l1 = gen_new_label();
1129 int l2 = gen_new_label();
1130 TCGv t0 = tcg_temp_local_new();
1131 #if defined(TARGET_PPC64)
1132 if (ctx->sf_mode) {
1133 tcg_gen_mov_tl(t0, arg1);
1134 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1135 } else
1136 #endif
1137 {
1138 tcg_gen_ext32s_tl(t0, arg1);
1139 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1140 }
1141 tcg_gen_neg_tl(ret, arg1);
1142 if (ov_check) {
1143 tcg_gen_movi_tl(cpu_ov, 0);
1144 }
1145 tcg_gen_br(l2);
1146 gen_set_label(l1);
1147 tcg_gen_mov_tl(ret, t0);
1148 if (ov_check) {
1149 tcg_gen_movi_tl(cpu_ov, 1);
1150 tcg_gen_movi_tl(cpu_so, 1);
1151 }
1152 gen_set_label(l2);
1153 tcg_temp_free(t0);
1154 if (unlikely(Rc(ctx->opcode) != 0))
1155 gen_set_Rc0(ctx, ret);
1156 }
1157
1158 static void gen_neg(DisasContext *ctx)
1159 {
1160 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1161 }
1162
1163 static void gen_nego(DisasContext *ctx)
1164 {
1165 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1166 }
1167
1168 /* Common subf function */
1169 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1170 TCGv arg2, bool add_ca, bool compute_ca,
1171 bool compute_ov, bool compute_rc0)
1172 {
1173 TCGv t0 = ret;
1174
1175 if (((add_ca && compute_ca) || compute_ov)
1176 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
1177 t0 = tcg_temp_new();
1178 }
1179
1180 if (add_ca) {
1181 /* dest = ~arg1 + arg2 + ca = arg2 - arg1 + ca - 1. */
1182 if (compute_ca) {
1183 TCGv zero;
1184 tcg_gen_subi_tl(cpu_ca, cpu_ca, 1);
1185 zero = tcg_const_tl(0);
1186 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1187 tcg_gen_sub2_tl(t0, cpu_ca, t0, cpu_ca, arg1, zero);
1188 tcg_temp_free(zero);
1189 } else {
1190 tcg_gen_sub_tl(t0, arg2, arg1);
1191 tcg_gen_add_tl(t0, t0, cpu_ca);
1192 tcg_gen_subi_tl(t0, t0, 1);
1193 }
1194 } else {
1195 if (compute_ca) {
1196 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1197 }
1198 tcg_gen_sub_tl(t0, arg2, arg1);
1199 }
1200
1201 if (compute_ov) {
1202 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1203 }
1204 if (unlikely(compute_rc0)) {
1205 gen_set_Rc0(ctx, t0);
1206 }
1207
1208 if (!TCGV_EQUAL(t0, ret)) {
1209 tcg_gen_mov_tl(ret, t0);
1210 tcg_temp_free(t0);
1211 }
1212 }
1213 /* Sub functions with Two operands functions */
1214 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1215 static void glue(gen_, name)(DisasContext *ctx) \
1216 { \
1217 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1218 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1219 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1220 }
1221 /* Sub functions with one operand and one immediate */
1222 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1223 add_ca, compute_ca, compute_ov) \
1224 static void glue(gen_, name)(DisasContext *ctx) \
1225 { \
1226 TCGv t0 = tcg_const_tl(const_val); \
1227 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1228 cpu_gpr[rA(ctx->opcode)], t0, \
1229 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1230 tcg_temp_free(t0); \
1231 }
1232 /* subf subf. subfo subfo. */
1233 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1234 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1235 /* subfc subfc. subfco subfco. */
1236 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1237 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1238 /* subfe subfe. subfeo subfo. */
1239 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1240 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1241 /* subfme subfme. subfmeo subfmeo. */
1242 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1243 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1244 /* subfze subfze. subfzeo subfzeo.*/
1245 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1246 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1247
1248 /* subfic */
1249 static void gen_subfic(DisasContext *ctx)
1250 {
1251 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1252 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1253 c, 0, 1, 0, 0);
1254 tcg_temp_free(c);
1255 }
1256
1257 /*** Integer logical ***/
1258 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1259 static void glue(gen_, name)(DisasContext *ctx) \
1260 { \
1261 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1262 cpu_gpr[rB(ctx->opcode)]); \
1263 if (unlikely(Rc(ctx->opcode) != 0)) \
1264 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1265 }
1266
1267 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1268 static void glue(gen_, name)(DisasContext *ctx) \
1269 { \
1270 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1271 if (unlikely(Rc(ctx->opcode) != 0)) \
1272 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1273 }
1274
1275 /* and & and. */
1276 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1277 /* andc & andc. */
1278 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1279
1280 /* andi. */
1281 static void gen_andi_(DisasContext *ctx)
1282 {
1283 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1284 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1285 }
1286
1287 /* andis. */
1288 static void gen_andis_(DisasContext *ctx)
1289 {
1290 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1291 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1292 }
1293
1294 /* cntlzw */
1295 static void gen_cntlzw(DisasContext *ctx)
1296 {
1297 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1298 if (unlikely(Rc(ctx->opcode) != 0))
1299 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1300 }
1301 /* eqv & eqv. */
1302 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1303 /* extsb & extsb. */
1304 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1305 /* extsh & extsh. */
1306 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1307 /* nand & nand. */
1308 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1309 /* nor & nor. */
1310 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1311
1312 /* or & or. */
1313 static void gen_or(DisasContext *ctx)
1314 {
1315 int rs, ra, rb;
1316
1317 rs = rS(ctx->opcode);
1318 ra = rA(ctx->opcode);
1319 rb = rB(ctx->opcode);
1320 /* Optimisation for mr. ri case */
1321 if (rs != ra || rs != rb) {
1322 if (rs != rb)
1323 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1324 else
1325 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1326 if (unlikely(Rc(ctx->opcode) != 0))
1327 gen_set_Rc0(ctx, cpu_gpr[ra]);
1328 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1329 gen_set_Rc0(ctx, cpu_gpr[rs]);
1330 #if defined(TARGET_PPC64)
1331 } else {
1332 int prio = 0;
1333
1334 switch (rs) {
1335 case 1:
1336 /* Set process priority to low */
1337 prio = 2;
1338 break;
1339 case 6:
1340 /* Set process priority to medium-low */
1341 prio = 3;
1342 break;
1343 case 2:
1344 /* Set process priority to normal */
1345 prio = 4;
1346 break;
1347 #if !defined(CONFIG_USER_ONLY)
1348 case 31:
1349 if (ctx->mem_idx > 0) {
1350 /* Set process priority to very low */
1351 prio = 1;
1352 }
1353 break;
1354 case 5:
1355 if (ctx->mem_idx > 0) {
1356 /* Set process priority to medium-hight */
1357 prio = 5;
1358 }
1359 break;
1360 case 3:
1361 if (ctx->mem_idx > 0) {
1362 /* Set process priority to high */
1363 prio = 6;
1364 }
1365 break;
1366 case 7:
1367 if (ctx->mem_idx > 1) {
1368 /* Set process priority to very high */
1369 prio = 7;
1370 }
1371 break;
1372 #endif
1373 default:
1374 /* nop */
1375 break;
1376 }
1377 if (prio) {
1378 TCGv t0 = tcg_temp_new();
1379 gen_load_spr(t0, SPR_PPR);
1380 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1381 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1382 gen_store_spr(SPR_PPR, t0);
1383 tcg_temp_free(t0);
1384 }
1385 #endif
1386 }
1387 }
1388 /* orc & orc. */
1389 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1390
1391 /* xor & xor. */
1392 static void gen_xor(DisasContext *ctx)
1393 {
1394 /* Optimisation for "set to zero" case */
1395 if (rS(ctx->opcode) != rB(ctx->opcode))
1396 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1397 else
1398 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1399 if (unlikely(Rc(ctx->opcode) != 0))
1400 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1401 }
1402
1403 /* ori */
1404 static void gen_ori(DisasContext *ctx)
1405 {
1406 target_ulong uimm = UIMM(ctx->opcode);
1407
1408 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1409 /* NOP */
1410 /* XXX: should handle special NOPs for POWER series */
1411 return;
1412 }
1413 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1414 }
1415
1416 /* oris */
1417 static void gen_oris(DisasContext *ctx)
1418 {
1419 target_ulong uimm = UIMM(ctx->opcode);
1420
1421 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1422 /* NOP */
1423 return;
1424 }
1425 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1426 }
1427
1428 /* xori */
1429 static void gen_xori(DisasContext *ctx)
1430 {
1431 target_ulong uimm = UIMM(ctx->opcode);
1432
1433 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1434 /* NOP */
1435 return;
1436 }
1437 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1438 }
1439
1440 /* xoris */
1441 static void gen_xoris(DisasContext *ctx)
1442 {
1443 target_ulong uimm = UIMM(ctx->opcode);
1444
1445 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1446 /* NOP */
1447 return;
1448 }
1449 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1450 }
1451
1452 /* popcntb : PowerPC 2.03 specification */
1453 static void gen_popcntb(DisasContext *ctx)
1454 {
1455 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1456 }
1457
1458 static void gen_popcntw(DisasContext *ctx)
1459 {
1460 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1461 }
1462
1463 #if defined(TARGET_PPC64)
1464 /* popcntd: PowerPC 2.06 specification */
1465 static void gen_popcntd(DisasContext *ctx)
1466 {
1467 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1468 }
1469 #endif
1470
1471 #if defined(TARGET_PPC64)
1472 /* extsw & extsw. */
1473 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1474
1475 /* cntlzd */
1476 static void gen_cntlzd(DisasContext *ctx)
1477 {
1478 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1479 if (unlikely(Rc(ctx->opcode) != 0))
1480 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1481 }
1482 #endif
1483
1484 /*** Integer rotate ***/
1485
1486 /* rlwimi & rlwimi. */
1487 static void gen_rlwimi(DisasContext *ctx)
1488 {
1489 uint32_t mb, me, sh;
1490
1491 mb = MB(ctx->opcode);
1492 me = ME(ctx->opcode);
1493 sh = SH(ctx->opcode);
1494 if (likely(sh == 0 && mb == 0 && me == 31)) {
1495 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1496 } else {
1497 target_ulong mask;
1498 TCGv t1;
1499 TCGv t0 = tcg_temp_new();
1500 #if defined(TARGET_PPC64)
1501 TCGv_i32 t2 = tcg_temp_new_i32();
1502 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1503 tcg_gen_rotli_i32(t2, t2, sh);
1504 tcg_gen_extu_i32_i64(t0, t2);
1505 tcg_temp_free_i32(t2);
1506 #else
1507 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1508 #endif
1509 #if defined(TARGET_PPC64)
1510 mb += 32;
1511 me += 32;
1512 #endif
1513 mask = MASK(mb, me);
1514 t1 = tcg_temp_new();
1515 tcg_gen_andi_tl(t0, t0, mask);
1516 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1517 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1518 tcg_temp_free(t0);
1519 tcg_temp_free(t1);
1520 }
1521 if (unlikely(Rc(ctx->opcode) != 0))
1522 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1523 }
1524
1525 /* rlwinm & rlwinm. */
1526 static void gen_rlwinm(DisasContext *ctx)
1527 {
1528 uint32_t mb, me, sh;
1529
1530 sh = SH(ctx->opcode);
1531 mb = MB(ctx->opcode);
1532 me = ME(ctx->opcode);
1533
1534 if (likely(mb == 0 && me == (31 - sh))) {
1535 if (likely(sh == 0)) {
1536 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1537 } else {
1538 TCGv t0 = tcg_temp_new();
1539 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1540 tcg_gen_shli_tl(t0, t0, sh);
1541 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1542 tcg_temp_free(t0);
1543 }
1544 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1545 TCGv t0 = tcg_temp_new();
1546 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1547 tcg_gen_shri_tl(t0, t0, mb);
1548 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1549 tcg_temp_free(t0);
1550 } else {
1551 TCGv t0 = tcg_temp_new();
1552 #if defined(TARGET_PPC64)
1553 TCGv_i32 t1 = tcg_temp_new_i32();
1554 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1555 tcg_gen_rotli_i32(t1, t1, sh);
1556 tcg_gen_extu_i32_i64(t0, t1);
1557 tcg_temp_free_i32(t1);
1558 #else
1559 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1560 #endif
1561 #if defined(TARGET_PPC64)
1562 mb += 32;
1563 me += 32;
1564 #endif
1565 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1566 tcg_temp_free(t0);
1567 }
1568 if (unlikely(Rc(ctx->opcode) != 0))
1569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1570 }
1571
1572 /* rlwnm & rlwnm. */
1573 static void gen_rlwnm(DisasContext *ctx)
1574 {
1575 uint32_t mb, me;
1576 TCGv t0;
1577 #if defined(TARGET_PPC64)
1578 TCGv_i32 t1, t2;
1579 #endif
1580
1581 mb = MB(ctx->opcode);
1582 me = ME(ctx->opcode);
1583 t0 = tcg_temp_new();
1584 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1585 #if defined(TARGET_PPC64)
1586 t1 = tcg_temp_new_i32();
1587 t2 = tcg_temp_new_i32();
1588 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1589 tcg_gen_trunc_i64_i32(t2, t0);
1590 tcg_gen_rotl_i32(t1, t1, t2);
1591 tcg_gen_extu_i32_i64(t0, t1);
1592 tcg_temp_free_i32(t1);
1593 tcg_temp_free_i32(t2);
1594 #else
1595 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1596 #endif
1597 if (unlikely(mb != 0 || me != 31)) {
1598 #if defined(TARGET_PPC64)
1599 mb += 32;
1600 me += 32;
1601 #endif
1602 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1603 } else {
1604 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1605 }
1606 tcg_temp_free(t0);
1607 if (unlikely(Rc(ctx->opcode) != 0))
1608 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1609 }
1610
1611 #if defined(TARGET_PPC64)
1612 #define GEN_PPC64_R2(name, opc1, opc2) \
1613 static void glue(gen_, name##0)(DisasContext *ctx) \
1614 { \
1615 gen_##name(ctx, 0); \
1616 } \
1617 \
1618 static void glue(gen_, name##1)(DisasContext *ctx) \
1619 { \
1620 gen_##name(ctx, 1); \
1621 }
1622 #define GEN_PPC64_R4(name, opc1, opc2) \
1623 static void glue(gen_, name##0)(DisasContext *ctx) \
1624 { \
1625 gen_##name(ctx, 0, 0); \
1626 } \
1627 \
1628 static void glue(gen_, name##1)(DisasContext *ctx) \
1629 { \
1630 gen_##name(ctx, 0, 1); \
1631 } \
1632 \
1633 static void glue(gen_, name##2)(DisasContext *ctx) \
1634 { \
1635 gen_##name(ctx, 1, 0); \
1636 } \
1637 \
1638 static void glue(gen_, name##3)(DisasContext *ctx) \
1639 { \
1640 gen_##name(ctx, 1, 1); \
1641 }
1642
1643 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1644 uint32_t sh)
1645 {
1646 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1647 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1648 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1649 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1650 } else {
1651 TCGv t0 = tcg_temp_new();
1652 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1653 if (likely(mb == 0 && me == 63)) {
1654 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1655 } else {
1656 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1657 }
1658 tcg_temp_free(t0);
1659 }
1660 if (unlikely(Rc(ctx->opcode) != 0))
1661 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1662 }
1663 /* rldicl - rldicl. */
1664 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1665 {
1666 uint32_t sh, mb;
1667
1668 sh = SH(ctx->opcode) | (shn << 5);
1669 mb = MB(ctx->opcode) | (mbn << 5);
1670 gen_rldinm(ctx, mb, 63, sh);
1671 }
1672 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1673 /* rldicr - rldicr. */
1674 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1675 {
1676 uint32_t sh, me;
1677
1678 sh = SH(ctx->opcode) | (shn << 5);
1679 me = MB(ctx->opcode) | (men << 5);
1680 gen_rldinm(ctx, 0, me, sh);
1681 }
1682 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1683 /* rldic - rldic. */
1684 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1685 {
1686 uint32_t sh, mb;
1687
1688 sh = SH(ctx->opcode) | (shn << 5);
1689 mb = MB(ctx->opcode) | (mbn << 5);
1690 gen_rldinm(ctx, mb, 63 - sh, sh);
1691 }
1692 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1693
1694 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1695 {
1696 TCGv t0;
1697
1698 mb = MB(ctx->opcode);
1699 me = ME(ctx->opcode);
1700 t0 = tcg_temp_new();
1701 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1702 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1703 if (unlikely(mb != 0 || me != 63)) {
1704 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1705 } else {
1706 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1707 }
1708 tcg_temp_free(t0);
1709 if (unlikely(Rc(ctx->opcode) != 0))
1710 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1711 }
1712
1713 /* rldcl - rldcl. */
1714 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1715 {
1716 uint32_t mb;
1717
1718 mb = MB(ctx->opcode) | (mbn << 5);
1719 gen_rldnm(ctx, mb, 63);
1720 }
1721 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1722 /* rldcr - rldcr. */
1723 static inline void gen_rldcr(DisasContext *ctx, int men)
1724 {
1725 uint32_t me;
1726
1727 me = MB(ctx->opcode) | (men << 5);
1728 gen_rldnm(ctx, 0, me);
1729 }
1730 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1731 /* rldimi - rldimi. */
1732 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1733 {
1734 uint32_t sh, mb, me;
1735
1736 sh = SH(ctx->opcode) | (shn << 5);
1737 mb = MB(ctx->opcode) | (mbn << 5);
1738 me = 63 - sh;
1739 if (unlikely(sh == 0 && mb == 0)) {
1740 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1741 } else {
1742 TCGv t0, t1;
1743 target_ulong mask;
1744
1745 t0 = tcg_temp_new();
1746 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1747 t1 = tcg_temp_new();
1748 mask = MASK(mb, me);
1749 tcg_gen_andi_tl(t0, t0, mask);
1750 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1751 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1752 tcg_temp_free(t0);
1753 tcg_temp_free(t1);
1754 }
1755 if (unlikely(Rc(ctx->opcode) != 0))
1756 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1757 }
1758 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1759 #endif
1760
1761 /*** Integer shift ***/
1762
1763 /* slw & slw. */
1764 static void gen_slw(DisasContext *ctx)
1765 {
1766 TCGv t0, t1;
1767
1768 t0 = tcg_temp_new();
1769 /* AND rS with a mask that is 0 when rB >= 0x20 */
1770 #if defined(TARGET_PPC64)
1771 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1772 tcg_gen_sari_tl(t0, t0, 0x3f);
1773 #else
1774 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1775 tcg_gen_sari_tl(t0, t0, 0x1f);
1776 #endif
1777 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1778 t1 = tcg_temp_new();
1779 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1780 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1781 tcg_temp_free(t1);
1782 tcg_temp_free(t0);
1783 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1784 if (unlikely(Rc(ctx->opcode) != 0))
1785 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1786 }
1787
1788 /* sraw & sraw. */
1789 static void gen_sraw(DisasContext *ctx)
1790 {
1791 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1792 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1793 if (unlikely(Rc(ctx->opcode) != 0))
1794 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1795 }
1796
1797 /* srawi & srawi. */
1798 static void gen_srawi(DisasContext *ctx)
1799 {
1800 int sh = SH(ctx->opcode);
1801 if (sh != 0) {
1802 int l1, l2;
1803 TCGv t0;
1804 l1 = gen_new_label();
1805 l2 = gen_new_label();
1806 t0 = tcg_temp_local_new();
1807 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1808 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1809 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1810 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1811 tcg_gen_movi_tl(cpu_ca, 1);
1812 tcg_gen_br(l2);
1813 gen_set_label(l1);
1814 tcg_gen_movi_tl(cpu_ca, 0);
1815 gen_set_label(l2);
1816 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1817 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1818 tcg_temp_free(t0);
1819 } else {
1820 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1821 tcg_gen_movi_tl(cpu_ca, 0);
1822 }
1823 if (unlikely(Rc(ctx->opcode) != 0))
1824 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1825 }
1826
1827 /* srw & srw. */
1828 static void gen_srw(DisasContext *ctx)
1829 {
1830 TCGv t0, t1;
1831
1832 t0 = tcg_temp_new();
1833 /* AND rS with a mask that is 0 when rB >= 0x20 */
1834 #if defined(TARGET_PPC64)
1835 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1836 tcg_gen_sari_tl(t0, t0, 0x3f);
1837 #else
1838 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1839 tcg_gen_sari_tl(t0, t0, 0x1f);
1840 #endif
1841 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1842 tcg_gen_ext32u_tl(t0, t0);
1843 t1 = tcg_temp_new();
1844 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1845 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1846 tcg_temp_free(t1);
1847 tcg_temp_free(t0);
1848 if (unlikely(Rc(ctx->opcode) != 0))
1849 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1850 }
1851
1852 #if defined(TARGET_PPC64)
1853 /* sld & sld. */
1854 static void gen_sld(DisasContext *ctx)
1855 {
1856 TCGv t0, t1;
1857
1858 t0 = tcg_temp_new();
1859 /* AND rS with a mask that is 0 when rB >= 0x40 */
1860 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1861 tcg_gen_sari_tl(t0, t0, 0x3f);
1862 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1863 t1 = tcg_temp_new();
1864 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1865 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1866 tcg_temp_free(t1);
1867 tcg_temp_free(t0);
1868 if (unlikely(Rc(ctx->opcode) != 0))
1869 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1870 }
1871
1872 /* srad & srad. */
1873 static void gen_srad(DisasContext *ctx)
1874 {
1875 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1876 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1877 if (unlikely(Rc(ctx->opcode) != 0))
1878 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1879 }
1880 /* sradi & sradi. */
1881 static inline void gen_sradi(DisasContext *ctx, int n)
1882 {
1883 int sh = SH(ctx->opcode) + (n << 5);
1884 if (sh != 0) {
1885 int l1, l2;
1886 TCGv t0;
1887 l1 = gen_new_label();
1888 l2 = gen_new_label();
1889 t0 = tcg_temp_local_new();
1890 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1891 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1892 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1893 tcg_gen_movi_tl(cpu_ca, 1);
1894 tcg_gen_br(l2);
1895 gen_set_label(l1);
1896 tcg_gen_movi_tl(cpu_ca, 0);
1897 gen_set_label(l2);
1898 tcg_temp_free(t0);
1899 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1900 } else {
1901 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1902 tcg_gen_movi_tl(cpu_ca, 0);
1903 }
1904 if (unlikely(Rc(ctx->opcode) != 0))
1905 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1906 }
1907
1908 static void gen_sradi0(DisasContext *ctx)
1909 {
1910 gen_sradi(ctx, 0);
1911 }
1912
1913 static void gen_sradi1(DisasContext *ctx)
1914 {
1915 gen_sradi(ctx, 1);
1916 }
1917
1918 /* srd & srd. */
1919 static void gen_srd(DisasContext *ctx)
1920 {
1921 TCGv t0, t1;
1922
1923 t0 = tcg_temp_new();
1924 /* AND rS with a mask that is 0 when rB >= 0x40 */
1925 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1926 tcg_gen_sari_tl(t0, t0, 0x3f);
1927 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1928 t1 = tcg_temp_new();
1929 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1930 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1931 tcg_temp_free(t1);
1932 tcg_temp_free(t0);
1933 if (unlikely(Rc(ctx->opcode) != 0))
1934 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1935 }
1936 #endif
1937
1938 /*** Floating-Point arithmetic ***/
1939 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1940 static void gen_f##name(DisasContext *ctx) \
1941 { \
1942 if (unlikely(!ctx->fpu_enabled)) { \
1943 gen_exception(ctx, POWERPC_EXCP_FPU); \
1944 return; \
1945 } \
1946 /* NIP cannot be restored if the memory exception comes from an helper */ \
1947 gen_update_nip(ctx, ctx->nip - 4); \
1948 gen_reset_fpstatus(); \
1949 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1950 cpu_fpr[rA(ctx->opcode)], \
1951 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1952 if (isfloat) { \
1953 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1954 cpu_fpr[rD(ctx->opcode)]); \
1955 } \
1956 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1957 Rc(ctx->opcode) != 0); \
1958 }
1959
1960 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1961 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1962 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1963
1964 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1965 static void gen_f##name(DisasContext *ctx) \
1966 { \
1967 if (unlikely(!ctx->fpu_enabled)) { \
1968 gen_exception(ctx, POWERPC_EXCP_FPU); \
1969 return; \
1970 } \
1971 /* NIP cannot be restored if the memory exception comes from an helper */ \
1972 gen_update_nip(ctx, ctx->nip - 4); \
1973 gen_reset_fpstatus(); \
1974 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1975 cpu_fpr[rA(ctx->opcode)], \
1976 cpu_fpr[rB(ctx->opcode)]); \
1977 if (isfloat) { \
1978 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1979 cpu_fpr[rD(ctx->opcode)]); \
1980 } \
1981 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1982 set_fprf, Rc(ctx->opcode) != 0); \
1983 }
1984 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1985 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1986 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1987
1988 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1989 static void gen_f##name(DisasContext *ctx) \
1990 { \
1991 if (unlikely(!ctx->fpu_enabled)) { \
1992 gen_exception(ctx, POWERPC_EXCP_FPU); \
1993 return; \
1994 } \
1995 /* NIP cannot be restored if the memory exception comes from an helper */ \
1996 gen_update_nip(ctx, ctx->nip - 4); \
1997 gen_reset_fpstatus(); \
1998 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1999 cpu_fpr[rA(ctx->opcode)], \
2000 cpu_fpr[rC(ctx->opcode)]); \
2001 if (isfloat) { \
2002 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2003 cpu_fpr[rD(ctx->opcode)]); \
2004 } \
2005 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2006 set_fprf, Rc(ctx->opcode) != 0); \
2007 }
2008 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2009 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2010 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2011
2012 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2013 static void gen_f##name(DisasContext *ctx) \
2014 { \
2015 if (unlikely(!ctx->fpu_enabled)) { \
2016 gen_exception(ctx, POWERPC_EXCP_FPU); \
2017 return; \
2018 } \
2019 /* NIP cannot be restored if the memory exception comes from an helper */ \
2020 gen_update_nip(ctx, ctx->nip - 4); \
2021 gen_reset_fpstatus(); \
2022 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2023 cpu_fpr[rB(ctx->opcode)]); \
2024 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2025 set_fprf, Rc(ctx->opcode) != 0); \
2026 }
2027
2028 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2029 static void gen_f##name(DisasContext *ctx) \
2030 { \
2031 if (unlikely(!ctx->fpu_enabled)) { \
2032 gen_exception(ctx, POWERPC_EXCP_FPU); \
2033 return; \
2034 } \
2035 /* NIP cannot be restored if the memory exception comes from an helper */ \
2036 gen_update_nip(ctx, ctx->nip - 4); \
2037 gen_reset_fpstatus(); \
2038 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2039 cpu_fpr[rB(ctx->opcode)]); \
2040 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2041 set_fprf, Rc(ctx->opcode) != 0); \
2042 }
2043
2044 /* fadd - fadds */
2045 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2046 /* fdiv - fdivs */
2047 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2048 /* fmul - fmuls */
2049 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2050
2051 /* fre */
2052 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2053
2054 /* fres */
2055 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2056
2057 /* frsqrte */
2058 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2059
2060 /* frsqrtes */
2061 static void gen_frsqrtes(DisasContext *ctx)
2062 {
2063 if (unlikely(!ctx->fpu_enabled)) {
2064 gen_exception(ctx, POWERPC_EXCP_FPU);
2065 return;
2066 }
2067 /* NIP cannot be restored if the memory exception comes from an helper */
2068 gen_update_nip(ctx, ctx->nip - 4);
2069 gen_reset_fpstatus();
2070 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2071 cpu_fpr[rB(ctx->opcode)]);
2072 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2073 cpu_fpr[rD(ctx->opcode)]);
2074 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2075 }
2076
2077 /* fsel */
2078 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2079 /* fsub - fsubs */
2080 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2081 /* Optional: */
2082
2083 /* fsqrt */
2084 static void gen_fsqrt(DisasContext *ctx)
2085 {
2086 if (unlikely(!ctx->fpu_enabled)) {
2087 gen_exception(ctx, POWERPC_EXCP_FPU);
2088 return;
2089 }
2090 /* NIP cannot be restored if the memory exception comes from an helper */
2091 gen_update_nip(ctx, ctx->nip - 4);
2092 gen_reset_fpstatus();
2093 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2094 cpu_fpr[rB(ctx->opcode)]);
2095 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2096 }
2097
2098 static void gen_fsqrts(DisasContext *ctx)
2099 {
2100 if (unlikely(!ctx->fpu_enabled)) {
2101 gen_exception(ctx, POWERPC_EXCP_FPU);
2102 return;
2103 }
2104 /* NIP cannot be restored if the memory exception comes from an helper */
2105 gen_update_nip(ctx, ctx->nip - 4);
2106 gen_reset_fpstatus();
2107 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2108 cpu_fpr[rB(ctx->opcode)]);
2109 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2110 cpu_fpr[rD(ctx->opcode)]);
2111 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2112 }
2113
2114 /*** Floating-Point multiply-and-add ***/
2115 /* fmadd - fmadds */
2116 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2117 /* fmsub - fmsubs */
2118 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2119 /* fnmadd - fnmadds */
2120 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2121 /* fnmsub - fnmsubs */
2122 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2123
2124 /*** Floating-Point round & convert ***/
2125 /* fctiw */
2126 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2127 /* fctiwz */
2128 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2129 /* frsp */
2130 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2131 #if defined(TARGET_PPC64)
2132 /* fcfid */
2133 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2134 /* fctid */
2135 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2136 /* fctidz */
2137 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2138 #endif
2139
2140 /* frin */
2141 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2142 /* friz */
2143 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2144 /* frip */
2145 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2146 /* frim */
2147 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2148
2149 /*** Floating-Point compare ***/
2150
2151 /* fcmpo */
2152 static void gen_fcmpo(DisasContext *ctx)
2153 {
2154 TCGv_i32 crf;
2155 if (unlikely(!ctx->fpu_enabled)) {
2156 gen_exception(ctx, POWERPC_EXCP_FPU);
2157 return;
2158 }
2159 /* NIP cannot be restored if the memory exception comes from an helper */
2160 gen_update_nip(ctx, ctx->nip - 4);
2161 gen_reset_fpstatus();
2162 crf = tcg_const_i32(crfD(ctx->opcode));
2163 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2164 cpu_fpr[rB(ctx->opcode)], crf);
2165 tcg_temp_free_i32(crf);
2166 gen_helper_float_check_status(cpu_env);
2167 }
2168
2169 /* fcmpu */
2170 static void gen_fcmpu(DisasContext *ctx)
2171 {
2172 TCGv_i32 crf;
2173 if (unlikely(!ctx->fpu_enabled)) {
2174 gen_exception(ctx, POWERPC_EXCP_FPU);
2175 return;
2176 }
2177 /* NIP cannot be restored if the memory exception comes from an helper */
2178 gen_update_nip(ctx, ctx->nip - 4);
2179 gen_reset_fpstatus();
2180 crf = tcg_const_i32(crfD(ctx->opcode));
2181 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2182 cpu_fpr[rB(ctx->opcode)], crf);
2183 tcg_temp_free_i32(crf);
2184 gen_helper_float_check_status(cpu_env);
2185 }
2186
2187 /*** Floating-point move ***/
2188 /* fabs */
2189 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2190 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2191
2192 /* fmr - fmr. */
2193 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2194 static void gen_fmr(DisasContext *ctx)
2195 {
2196 if (unlikely(!ctx->fpu_enabled)) {
2197 gen_exception(ctx, POWERPC_EXCP_FPU);
2198 return;
2199 }
2200 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2201 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2202 }
2203
2204 /* fnabs */
2205 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2206 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2207 /* fneg */
2208 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2209 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2210
2211 /*** Floating-Point status & ctrl register ***/
2212
2213 /* mcrfs */
2214 static void gen_mcrfs(DisasContext *ctx)
2215 {
2216 TCGv tmp = tcg_temp_new();
2217 int bfa;
2218
2219 if (unlikely(!ctx->fpu_enabled)) {
2220 gen_exception(ctx, POWERPC_EXCP_FPU);
2221 return;
2222 }
2223 bfa = 4 * (7 - crfS(ctx->opcode));
2224 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2225 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2226 tcg_temp_free(tmp);
2227 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2228 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2229 }
2230
2231 /* mffs */
2232 static void gen_mffs(DisasContext *ctx)
2233 {
2234 if (unlikely(!ctx->fpu_enabled)) {
2235 gen_exception(ctx, POWERPC_EXCP_FPU);
2236 return;
2237 }
2238 gen_reset_fpstatus();
2239 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2240 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2241 }
2242
2243 /* mtfsb0 */
2244 static void gen_mtfsb0(DisasContext *ctx)
2245 {
2246 uint8_t crb;
2247
2248 if (unlikely(!ctx->fpu_enabled)) {
2249 gen_exception(ctx, POWERPC_EXCP_FPU);
2250 return;
2251 }
2252 crb = 31 - crbD(ctx->opcode);
2253 gen_reset_fpstatus();
2254 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2255 TCGv_i32 t0;
2256 /* NIP cannot be restored if the memory exception comes from an helper */
2257 gen_update_nip(ctx, ctx->nip - 4);
2258 t0 = tcg_const_i32(crb);
2259 gen_helper_fpscr_clrbit(cpu_env, t0);
2260 tcg_temp_free_i32(t0);
2261 }
2262 if (unlikely(Rc(ctx->opcode) != 0)) {
2263 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2264 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2265 }
2266 }
2267
2268 /* mtfsb1 */
2269 static void gen_mtfsb1(DisasContext *ctx)
2270 {
2271 uint8_t crb;
2272
2273 if (unlikely(!ctx->fpu_enabled)) {
2274 gen_exception(ctx, POWERPC_EXCP_FPU);
2275 return;
2276 }
2277 crb = 31 - crbD(ctx->opcode);
2278 gen_reset_fpstatus();
2279 /* XXX: we pretend we can only do IEEE floating-point computations */
2280 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2281 TCGv_i32 t0;
2282 /* NIP cannot be restored if the memory exception comes from an helper */
2283 gen_update_nip(ctx, ctx->nip - 4);
2284 t0 = tcg_const_i32(crb);
2285 gen_helper_fpscr_setbit(cpu_env, t0);
2286 tcg_temp_free_i32(t0);
2287 }
2288 if (unlikely(Rc(ctx->opcode) != 0)) {
2289 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2290 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2291 }
2292 /* We can raise a differed exception */
2293 gen_helper_float_check_status(cpu_env);
2294 }
2295
2296 /* mtfsf */
2297 static void gen_mtfsf(DisasContext *ctx)
2298 {
2299 TCGv_i32 t0;
2300 int L = ctx->opcode & 0x02000000;
2301
2302 if (unlikely(!ctx->fpu_enabled)) {
2303 gen_exception(ctx, POWERPC_EXCP_FPU);
2304 return;
2305 }
2306 /* NIP cannot be restored if the memory exception comes from an helper */
2307 gen_update_nip(ctx, ctx->nip - 4);
2308 gen_reset_fpstatus();
2309 if (L)
2310 t0 = tcg_const_i32(0xff);
2311 else
2312 t0 = tcg_const_i32(FM(ctx->opcode));
2313 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2314 tcg_temp_free_i32(t0);
2315 if (unlikely(Rc(ctx->opcode) != 0)) {
2316 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2317 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2318 }
2319 /* We can raise a differed exception */
2320 gen_helper_float_check_status(cpu_env);
2321 }
2322
2323 /* mtfsfi */
2324 static void gen_mtfsfi(DisasContext *ctx)
2325 {
2326 int bf, sh;
2327 TCGv_i64 t0;
2328 TCGv_i32 t1;
2329
2330 if (unlikely(!ctx->fpu_enabled)) {
2331 gen_exception(ctx, POWERPC_EXCP_FPU);
2332 return;
2333 }
2334 bf = crbD(ctx->opcode) >> 2;
2335 sh = 7 - bf;
2336 /* NIP cannot be restored if the memory exception comes from an helper */
2337 gen_update_nip(ctx, ctx->nip - 4);
2338 gen_reset_fpstatus();
2339 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2340 t1 = tcg_const_i32(1 << sh);
2341 gen_helper_store_fpscr(cpu_env, t0, t1);
2342 tcg_temp_free_i64(t0);
2343 tcg_temp_free_i32(t1);
2344 if (unlikely(Rc(ctx->opcode) != 0)) {
2345 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2346 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2347 }
2348 /* We can raise a differed exception */
2349 gen_helper_float_check_status(cpu_env);
2350 }
2351
2352 /*** Addressing modes ***/
2353 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2354 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2355 target_long maskl)
2356 {
2357 target_long simm = SIMM(ctx->opcode);
2358
2359 simm &= ~maskl;
2360 if (rA(ctx->opcode) == 0) {
2361 #if defined(TARGET_PPC64)
2362 if (!ctx->sf_mode) {
2363 tcg_gen_movi_tl(EA, (uint32_t)simm);
2364 } else
2365 #endif
2366 tcg_gen_movi_tl(EA, simm);
2367 } else if (likely(simm != 0)) {
2368 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2369 #if defined(TARGET_PPC64)
2370 if (!ctx->sf_mode) {
2371 tcg_gen_ext32u_tl(EA, EA);
2372 }
2373 #endif
2374 } else {
2375 #if defined(TARGET_PPC64)
2376 if (!ctx->sf_mode) {
2377 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2378 } else
2379 #endif
2380 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2381 }
2382 }
2383
2384 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2385 {
2386 if (rA(ctx->opcode) == 0) {
2387 #if defined(TARGET_PPC64)
2388 if (!ctx->sf_mode) {
2389 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2390 } else
2391 #endif
2392 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2393 } else {
2394 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2395 #if defined(TARGET_PPC64)
2396 if (!ctx->sf_mode) {
2397 tcg_gen_ext32u_tl(EA, EA);
2398 }
2399 #endif
2400 }
2401 }
2402
2403 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2404 {
2405 if (rA(ctx->opcode) == 0) {
2406 tcg_gen_movi_tl(EA, 0);
2407 } else {
2408 #if defined(TARGET_PPC64)
2409 if (!ctx->sf_mode) {
2410 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2411 } else
2412 #endif
2413 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2414 }
2415 }
2416
2417 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2418 target_long val)
2419 {
2420 tcg_gen_addi_tl(ret, arg1, val);
2421 #if defined(TARGET_PPC64)
2422 if (!ctx->sf_mode) {
2423 tcg_gen_ext32u_tl(ret, ret);
2424 }
2425 #endif
2426 }
2427
2428 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2429 {
2430 int l1 = gen_new_label();
2431 TCGv t0 = tcg_temp_new();
2432 TCGv_i32 t1, t2;
2433 /* NIP cannot be restored if the memory exception comes from an helper */
2434 gen_update_nip(ctx, ctx->nip - 4);
2435 tcg_gen_andi_tl(t0, EA, mask);
2436 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2437 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2438 t2 = tcg_const_i32(0);
2439 gen_helper_raise_exception_err(cpu_env, t1, t2);
2440 tcg_temp_free_i32(t1);
2441 tcg_temp_free_i32(t2);
2442 gen_set_label(l1);
2443 tcg_temp_free(t0);
2444 }
2445
2446 /*** Integer load ***/
2447 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2448 {
2449 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2450 }
2451
2452 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2453 {
2454 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2455 }
2456
2457 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2458 {
2459 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2460 if (unlikely(ctx->le_mode)) {
2461 tcg_gen_bswap16_tl(arg1, arg1);
2462 }
2463 }
2464
2465 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2466 {
2467 if (unlikely(ctx->le_mode)) {
2468 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2469 tcg_gen_bswap16_tl(arg1, arg1);
2470 tcg_gen_ext16s_tl(arg1, arg1);
2471 } else {
2472 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2473 }
2474 }
2475
2476 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2477 {
2478 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2479 if (unlikely(ctx->le_mode)) {
2480 tcg_gen_bswap32_tl(arg1, arg1);
2481 }
2482 }
2483
2484 #if defined(TARGET_PPC64)
2485 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2486 {
2487 if (unlikely(ctx->le_mode)) {
2488 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2489 tcg_gen_bswap32_tl(arg1, arg1);
2490 tcg_gen_ext32s_tl(arg1, arg1);
2491 } else
2492 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2493 }
2494 #endif
2495
2496 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2497 {
2498 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2499 if (unlikely(ctx->le_mode)) {
2500 tcg_gen_bswap64_i64(arg1, arg1);
2501 }
2502 }
2503
2504 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2505 {
2506 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2507 }
2508
2509 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2510 {
2511 if (unlikely(ctx->le_mode)) {
2512 TCGv t0 = tcg_temp_new();
2513 tcg_gen_ext16u_tl(t0, arg1);
2514 tcg_gen_bswap16_tl(t0, t0);
2515 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2516 tcg_temp_free(t0);
2517 } else {
2518 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2519 }
2520 }
2521
2522 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2523 {
2524 if (unlikely(ctx->le_mode)) {
2525 TCGv t0 = tcg_temp_new();
2526 tcg_gen_ext32u_tl(t0, arg1);
2527 tcg_gen_bswap32_tl(t0, t0);
2528 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2529 tcg_temp_free(t0);
2530 } else {
2531 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2532 }
2533 }
2534
2535 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2536 {
2537 if (unlikely(ctx->le_mode)) {
2538 TCGv_i64 t0 = tcg_temp_new_i64();
2539 tcg_gen_bswap64_i64(t0, arg1);
2540 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2541 tcg_temp_free_i64(t0);
2542 } else
2543 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2544 }
2545
2546 #define GEN_LD(name, ldop, opc, type) \
2547 static void glue(gen_, name)(DisasContext *ctx) \
2548 { \
2549 TCGv EA; \
2550 gen_set_access_type(ctx, ACCESS_INT); \
2551 EA = tcg_temp_new(); \
2552 gen_addr_imm_index(ctx, EA, 0); \
2553 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2554 tcg_temp_free(EA); \
2555 }
2556
2557 #define GEN_LDU(name, ldop, opc, type) \
2558 static void glue(gen_, name##u)(DisasContext *ctx) \
2559 { \
2560 TCGv EA; \
2561 if (unlikely(rA(ctx->opcode) == 0 || \
2562 rA(ctx->opcode) == rD(ctx->opcode))) { \
2563 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2564 return; \
2565 } \
2566 gen_set_access_type(ctx, ACCESS_INT); \
2567 EA = tcg_temp_new(); \
2568 if (type == PPC_64B) \
2569 gen_addr_imm_index(ctx, EA, 0x03); \
2570 else \
2571 gen_addr_imm_index(ctx, EA, 0); \
2572 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2573 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2574 tcg_temp_free(EA); \
2575 }
2576
2577 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2578 static void glue(gen_, name##ux)(DisasContext *ctx) \
2579 { \
2580 TCGv EA; \
2581 if (unlikely(rA(ctx->opcode) == 0 || \
2582 rA(ctx->opcode) == rD(ctx->opcode))) { \
2583 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2584 return; \
2585 } \
2586 gen_set_access_type(ctx, ACCESS_INT); \
2587 EA = tcg_temp_new(); \
2588 gen_addr_reg_index(ctx, EA); \
2589 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2590 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2591 tcg_temp_free(EA); \
2592 }
2593
2594 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2595 static void glue(gen_, name##x)(DisasContext *ctx) \
2596 { \
2597 TCGv EA; \
2598 gen_set_access_type(ctx, ACCESS_INT); \
2599 EA = tcg_temp_new(); \
2600 gen_addr_reg_index(ctx, EA); \
2601 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2602 tcg_temp_free(EA); \
2603 }
2604 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2605 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2606
2607 #define GEN_LDS(name, ldop, op, type) \
2608 GEN_LD(name, ldop, op | 0x20, type); \
2609 GEN_LDU(name, ldop, op | 0x21, type); \
2610 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2611 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2612
2613 /* lbz lbzu lbzux lbzx */
2614 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2615 /* lha lhau lhaux lhax */
2616 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2617 /* lhz lhzu lhzux lhzx */
2618 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2619 /* lwz lwzu lwzux lwzx */
2620 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2621 #if defined(TARGET_PPC64)
2622 /* lwaux */
2623 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2624 /* lwax */
2625 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2626 /* ldux */
2627 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2628 /* ldx */
2629 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2630
2631 static void gen_ld(DisasContext *ctx)
2632 {
2633 TCGv EA;
2634 if (Rc(ctx->opcode)) {
2635 if (unlikely(rA(ctx->opcode) == 0 ||
2636 rA(ctx->opcode) == rD(ctx->opcode))) {
2637 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2638 return;
2639 }
2640 }
2641 gen_set_access_type(ctx, ACCESS_INT);
2642 EA = tcg_temp_new();
2643 gen_addr_imm_index(ctx, EA, 0x03);
2644 if (ctx->opcode & 0x02) {
2645 /* lwa (lwau is undefined) */
2646 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2647 } else {
2648 /* ld - ldu */
2649 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2650 }
2651 if (Rc(ctx->opcode))
2652 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2653 tcg_temp_free(EA);
2654 }
2655
2656 /* lq */
2657 static void gen_lq(DisasContext *ctx)
2658 {
2659 #if defined(CONFIG_USER_ONLY)
2660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2661 #else
2662 int ra, rd;
2663 TCGv EA;
2664
2665 /* Restore CPU state */
2666 if (unlikely(ctx->mem_idx == 0)) {
2667 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2668 return;
2669 }
2670 ra = rA(ctx->opcode);
2671 rd = rD(ctx->opcode);
2672 if (unlikely((rd & 1) || rd == ra)) {
2673 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2674 return;
2675 }
2676 if (unlikely(ctx->le_mode)) {
2677 /* Little-endian mode is not handled */
2678 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2679 return;
2680 }
2681 gen_set_access_type(ctx, ACCESS_INT);
2682 EA = tcg_temp_new();
2683 gen_addr_imm_index(ctx, EA, 0x0F);
2684 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2685 gen_addr_add(ctx, EA, EA, 8);
2686 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2687 tcg_temp_free(EA);
2688 #endif
2689 }
2690 #endif
2691
2692 /*** Integer store ***/
2693 #define GEN_ST(name, stop, opc, type) \
2694 static void glue(gen_, name)(DisasContext *ctx) \
2695 { \
2696 TCGv EA; \
2697 gen_set_access_type(ctx, ACCESS_INT); \
2698 EA = tcg_temp_new(); \
2699 gen_addr_imm_index(ctx, EA, 0); \
2700 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2701 tcg_temp_free(EA); \
2702 }
2703
2704 #define GEN_STU(name, stop, opc, type) \
2705 static void glue(gen_, stop##u)(DisasContext *ctx) \
2706 { \
2707 TCGv EA; \
2708 if (unlikely(rA(ctx->opcode) == 0)) { \
2709 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2710 return; \
2711 } \
2712 gen_set_access_type(ctx, ACCESS_INT); \
2713 EA = tcg_temp_new(); \
2714 if (type == PPC_64B) \
2715 gen_addr_imm_index(ctx, EA, 0x03); \
2716 else \
2717 gen_addr_imm_index(ctx, EA, 0); \
2718 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2719 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2720 tcg_temp_free(EA); \
2721 }
2722
2723 #define GEN_STUX(name, stop, opc2, opc3, type) \
2724 static void glue(gen_, name##ux)(DisasContext *ctx) \
2725 { \
2726 TCGv EA; \
2727 if (unlikely(rA(ctx->opcode) == 0)) { \
2728 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2729 return; \
2730 } \
2731 gen_set_access_type(ctx, ACCESS_INT); \
2732 EA = tcg_temp_new(); \
2733 gen_addr_reg_index(ctx, EA); \
2734 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2735 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2736 tcg_temp_free(EA); \
2737 }
2738
2739 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2740 static void glue(gen_, name##x)(DisasContext *ctx) \
2741 { \
2742 TCGv EA; \
2743 gen_set_access_type(ctx, ACCESS_INT); \
2744 EA = tcg_temp_new(); \
2745 gen_addr_reg_index(ctx, EA); \
2746 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2747 tcg_temp_free(EA); \
2748 }
2749 #define GEN_STX(name, stop, opc2, opc3, type) \
2750 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2751
2752 #define GEN_STS(name, stop, op, type) \
2753 GEN_ST(name, stop, op | 0x20, type); \
2754 GEN_STU(name, stop, op | 0x21, type); \
2755 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2756 GEN_STX(name, stop, 0x17, op | 0x00, type)
2757
2758 /* stb stbu stbux stbx */
2759 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2760 /* sth sthu sthux sthx */
2761 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2762 /* stw stwu stwux stwx */
2763 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2764 #if defined(TARGET_PPC64)
2765 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2766 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2767
2768 static void gen_std(DisasContext *ctx)
2769 {
2770 int rs;
2771 TCGv EA;
2772
2773 rs = rS(ctx->opcode);
2774 if ((ctx->opcode & 0x3) == 0x2) {
2775 #if defined(CONFIG_USER_ONLY)
2776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2777 #else
2778 /* stq */
2779 if (unlikely(ctx->mem_idx == 0)) {
2780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2781 return;
2782 }
2783 if (unlikely(rs & 1)) {
2784 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2785 return;
2786 }
2787 if (unlikely(ctx->le_mode)) {
2788 /* Little-endian mode is not handled */
2789 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2790 return;
2791 }
2792 gen_set_access_type(ctx, ACCESS_INT);
2793 EA = tcg_temp_new();
2794 gen_addr_imm_index(ctx, EA, 0x03);
2795 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2796 gen_addr_add(ctx, EA, EA, 8);
2797 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2798 tcg_temp_free(EA);
2799 #endif
2800 } else {
2801 /* std / stdu */
2802 if (Rc(ctx->opcode)) {
2803 if (unlikely(rA(ctx->opcode) == 0)) {
2804 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2805 return;
2806 }
2807 }
2808 gen_set_access_type(ctx, ACCESS_INT);
2809 EA = tcg_temp_new();
2810 gen_addr_imm_index(ctx, EA, 0x03);
2811 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2812 if (Rc(ctx->opcode))
2813 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2814 tcg_temp_free(EA);
2815 }
2816 }
2817 #endif
2818 /*** Integer load and store with byte reverse ***/
2819 /* lhbrx */
2820 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2821 {
2822 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2823 if (likely(!ctx->le_mode)) {
2824 tcg_gen_bswap16_tl(arg1, arg1);
2825 }
2826 }
2827 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2828
2829 /* lwbrx */
2830 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2831 {
2832 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2833 if (likely(!ctx->le_mode)) {
2834 tcg_gen_bswap32_tl(arg1, arg1);
2835 }
2836 }
2837 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2838
2839 #if defined(TARGET_PPC64)
2840 /* ldbrx */
2841 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2842 {
2843 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2844 if (likely(!ctx->le_mode)) {
2845 tcg_gen_bswap64_tl(arg1, arg1);
2846 }
2847 }
2848 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2849 #endif /* TARGET_PPC64 */
2850
2851 /* sthbrx */
2852 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2853 {
2854 if (likely(!ctx->le_mode)) {
2855 TCGv t0 = tcg_temp_new();
2856 tcg_gen_ext16u_tl(t0, arg1);
2857 tcg_gen_bswap16_tl(t0, t0);
2858 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2859 tcg_temp_free(t0);
2860 } else {
2861 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2862 }
2863 }
2864 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2865
2866 /* stwbrx */
2867 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2868 {
2869 if (likely(!ctx->le_mode)) {
2870 TCGv t0 = tcg_temp_new();
2871 tcg_gen_ext32u_tl(t0, arg1);
2872 tcg_gen_bswap32_tl(t0, t0);
2873 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2874 tcg_temp_free(t0);
2875 } else {
2876 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2877 }
2878 }
2879 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2880
2881 #if defined(TARGET_PPC64)
2882 /* stdbrx */
2883 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2884 {
2885 if (likely(!ctx->le_mode)) {
2886 TCGv t0 = tcg_temp_new();
2887 tcg_gen_bswap64_tl(t0, arg1);
2888 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2889 tcg_temp_free(t0);
2890 } else {
2891 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2892 }
2893 }
2894 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2895 #endif /* TARGET_PPC64 */
2896
2897 /*** Integer load and store multiple ***/
2898
2899 /* lmw */
2900 static void gen_lmw(DisasContext *ctx)
2901 {
2902 TCGv t0;
2903 TCGv_i32 t1;
2904 gen_set_access_type(ctx, ACCESS_INT);
2905 /* NIP cannot be restored if the memory exception comes from an helper */
2906 gen_update_nip(ctx, ctx->nip - 4);
2907 t0 = tcg_temp_new();
2908 t1 = tcg_const_i32(rD(ctx->opcode));
2909 gen_addr_imm_index(ctx, t0, 0);
2910 gen_helper_lmw(cpu_env, t0, t1);
2911 tcg_temp_free(t0);
2912 tcg_temp_free_i32(t1);
2913 }
2914
2915 /* stmw */
2916 static void gen_stmw(DisasContext *ctx)
2917 {
2918 TCGv t0;
2919 TCGv_i32 t1;
2920 gen_set_access_type(ctx, ACCESS_INT);
2921 /* NIP cannot be restored if the memory exception comes from an helper */
2922 gen_update_nip(ctx, ctx->nip - 4);
2923 t0 = tcg_temp_new();
2924 t1 = tcg_const_i32(rS(ctx->opcode));
2925 gen_addr_imm_index(ctx, t0, 0);
2926 gen_helper_stmw(cpu_env, t0, t1);
2927 tcg_temp_free(t0);
2928 tcg_temp_free_i32(t1);
2929 }
2930
2931 /*** Integer load and store strings ***/
2932
2933 /* lswi */
2934 /* PowerPC32 specification says we must generate an exception if
2935 * rA is in the range of registers to be loaded.
2936 * In an other hand, IBM says this is valid, but rA won't be loaded.
2937 * For now, I'll follow the spec...
2938 */
2939 static void gen_lswi(DisasContext *ctx)
2940 {
2941 TCGv t0;
2942 TCGv_i32 t1, t2;
2943 int nb = NB(ctx->opcode);
2944 int start = rD(ctx->opcode);
2945 int ra = rA(ctx->opcode);
2946 int nr;
2947
2948 if (nb == 0)
2949 nb = 32;
2950 nr = nb / 4;
2951 if (unlikely(((start + nr) > 32 &&
2952 start <= ra && (start + nr - 32) > ra) ||
2953 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2954 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2955 return;
2956 }
2957 gen_set_access_type(ctx, ACCESS_INT);
2958 /* NIP cannot be restored if the memory exception comes from an helper */
2959 gen_update_nip(ctx, ctx->nip - 4);
2960 t0 = tcg_temp_new();
2961 gen_addr_register(ctx, t0);
2962 t1 = tcg_const_i32(nb);
2963 t2 = tcg_const_i32(start);
2964 gen_helper_lsw(cpu_env, t0, t1, t2);
2965 tcg_temp_free(t0);
2966 tcg_temp_free_i32(t1);
2967 tcg_temp_free_i32(t2);
2968 }
2969
2970 /* lswx */
2971 static void gen_lswx(DisasContext *ctx)
2972 {
2973 TCGv t0;
2974 TCGv_i32 t1, t2, t3;
2975 gen_set_access_type(ctx, ACCESS_INT);
2976 /* NIP cannot be restored if the memory exception comes from an helper */
2977 gen_update_nip(ctx, ctx->nip - 4);
2978 t0 = tcg_temp_new();
2979 gen_addr_reg_index(ctx, t0);
2980 t1 = tcg_const_i32(rD(ctx->opcode));
2981 t2 = tcg_const_i32(rA(ctx->opcode));
2982 t3 = tcg_const_i32(rB(ctx->opcode));
2983 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2984 tcg_temp_free(t0);
2985 tcg_temp_free_i32(t1);
2986 tcg_temp_free_i32(t2);
2987 tcg_temp_free_i32(t3);
2988 }
2989
2990 /* stswi */
2991 static void gen_stswi(DisasContext *ctx)
2992 {
2993 TCGv t0;
2994 TCGv_i32 t1, t2;
2995 int nb = NB(ctx->opcode);
2996 gen_set_access_type(ctx, ACCESS_INT);
2997 /* NIP cannot be restored if the memory exception comes from an helper */
2998 gen_update_nip(ctx, ctx->nip - 4);
2999 t0 = tcg_temp_new();
3000 gen_addr_register(ctx, t0);
3001 if (nb == 0)
3002 nb = 32;
3003 t1 = tcg_const_i32(nb);
3004 t2 = tcg_const_i32(rS(ctx->opcode));
3005 gen_helper_stsw(cpu_env, t0, t1, t2);
3006 tcg_temp_free(t0);
3007 tcg_temp_free_i32(t1);
3008 tcg_temp_free_i32(t2);
3009 }
3010
3011 /* stswx */
3012 static void gen_stswx(DisasContext *ctx)
3013 {
3014 TCGv t0;
3015 TCGv_i32 t1, t2;
3016 gen_set_access_type(ctx, ACCESS_INT);
3017 /* NIP cannot be restored if the memory exception comes from an helper */
3018 gen_update_nip(ctx, ctx->nip - 4);
3019 t0 = tcg_temp_new();
3020 gen_addr_reg_index(ctx, t0);
3021 t1 = tcg_temp_new_i32();
3022 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3023 tcg_gen_andi_i32(t1, t1, 0x7F);
3024 t2 = tcg_const_i32(rS(ctx->opcode));
3025 gen_helper_stsw(cpu_env, t0, t1, t2);
3026 tcg_temp_free(t0);
3027 tcg_temp_free_i32(t1);
3028 tcg_temp_free_i32(t2);
3029 }
3030
3031 /*** Memory synchronisation ***/
3032 /* eieio */
3033 static void gen_eieio(DisasContext *ctx)
3034 {
3035 }
3036
3037 /* isync */
3038 static void gen_isync(DisasContext *ctx)
3039 {
3040 gen_stop_exception(ctx);
3041 }
3042
3043 /* lwarx */
3044 static void gen_lwarx(DisasContext *ctx)
3045 {
3046 TCGv t0;
3047 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3048 gen_set_access_type(ctx, ACCESS_RES);
3049 t0 = tcg_temp_local_new();
3050 gen_addr_reg_index(ctx, t0);
3051 gen_check_align(ctx, t0, 0x03);
3052 gen_qemu_ld32u(ctx, gpr, t0);
3053 tcg_gen_mov_tl(cpu_reserve, t0);
3054 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3055 tcg_temp_free(t0);
3056 }
3057
3058 #if defined(CONFIG_USER_ONLY)
3059 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3060 int reg, int size)
3061 {
3062 TCGv t0 = tcg_temp_new();
3063 uint32_t save_exception = ctx->exception;
3064
3065 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3066 tcg_gen_movi_tl(t0, (size << 5) | reg);
3067 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3068 tcg_temp_free(t0);
3069 gen_update_nip(ctx, ctx->nip-4);
3070 ctx->exception = POWERPC_EXCP_BRANCH;
3071 gen_exception(ctx, POWERPC_EXCP_STCX);
3072 ctx->exception = save_exception;
3073 }
3074 #endif
3075
3076 /* stwcx. */
3077 static void gen_stwcx_(DisasContext *ctx)
3078 {
3079 TCGv t0;
3080 gen_set_access_type(ctx, ACCESS_RES);
3081 t0 = tcg_temp_local_new();
3082 gen_addr_reg_index(ctx, t0);
3083 gen_check_align(ctx, t0, 0x03);
3084 #if defined(CONFIG_USER_ONLY)
3085 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3086 #else
3087 {
3088 int l1;
3089
3090 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3091 l1 = gen_new_label();
3092 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3093 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3094 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3095 gen_set_label(l1);
3096 tcg_gen_movi_tl(cpu_reserve, -1);
3097 }
3098 #endif
3099 tcg_temp_free(t0);
3100 }
3101
3102 #if defined(TARGET_PPC64)
3103 /* ldarx */
3104 static void gen_ldarx(DisasContext *ctx)
3105 {
3106 TCGv t0;
3107 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3108 gen_set_access_type(ctx, ACCESS_RES);
3109 t0 = tcg_temp_local_new();
3110 gen_addr_reg_index(ctx, t0);
3111 gen_check_align(ctx, t0, 0x07);
3112 gen_qemu_ld64(ctx, gpr, t0);
3113 tcg_gen_mov_tl(cpu_reserve, t0);
3114 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3115 tcg_temp_free(t0);
3116 }
3117
3118 /* stdcx. */
3119 static void gen_stdcx_(DisasContext *ctx)
3120 {
3121 TCGv t0;
3122 gen_set_access_type(ctx, ACCESS_RES);
3123 t0 = tcg_temp_local_new();
3124 gen_addr_reg_index(ctx, t0);
3125 gen_check_align(ctx, t0, 0x07);
3126 #if defined(CONFIG_USER_ONLY)
3127 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3128 #else
3129 {
3130 int l1;
3131 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3132 l1 = gen_new_label();
3133 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3134 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3135 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3136 gen_set_label(l1);
3137 tcg_gen_movi_tl(cpu_reserve, -1);
3138 }
3139 #endif
3140 tcg_temp_free(t0);
3141 }
3142 #endif /* defined(TARGET_PPC64) */
3143
3144 /* sync */
3145 static void gen_sync(DisasContext *ctx)
3146 {
3147 }
3148
3149 /* wait */
3150 static void gen_wait(DisasContext *ctx)
3151 {
3152 TCGv_i32 t0 = tcg_temp_new_i32();
3153 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
3154 tcg_temp_free_i32(t0);
3155 /* Stop translation, as the CPU is supposed to sleep from now */
3156 gen_exception_err(ctx, EXCP_HLT, 1);
3157 }
3158
3159 /*** Floating-point load ***/
3160 #define GEN_LDF(name, ldop, opc, type) \
3161 static void glue(gen_, name)(DisasContext *ctx) \
3162 { \
3163 TCGv EA; \
3164 if (unlikely(!ctx->fpu_enabled)) { \
3165 gen_exception(ctx, POWERPC_EXCP_FPU); \
3166 return; \
3167 } \
3168 gen_set_access_type(ctx, ACCESS_FLOAT); \
3169 EA = tcg_temp_new(); \
3170 gen_addr_imm_index(ctx, EA, 0); \
3171 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3172 tcg_temp_free(EA); \
3173 }
3174
3175 #define GEN_LDUF(name, ldop, opc, type) \
3176 static void glue(gen_, name##u)(DisasContext *ctx) \
3177 { \
3178 TCGv EA; \
3179 if (unlikely(!ctx->fpu_enabled)) { \
3180 gen_exception(ctx, POWERPC_EXCP_FPU); \
3181 return; \
3182 } \
3183 if (unlikely(rA(ctx->opcode) == 0)) { \
3184 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3185 return; \
3186 } \
3187 gen_set_access_type(ctx, ACCESS_FLOAT); \
3188 EA = tcg_temp_new(); \
3189 gen_addr_imm_index(ctx, EA, 0); \
3190 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3191 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3192 tcg_temp_free(EA); \
3193 }
3194
3195 #define GEN_LDUXF(name, ldop, opc, type) \
3196 static void glue(gen_, name##ux)(DisasContext *ctx) \
3197 { \
3198 TCGv EA; \
3199 if (unlikely(!ctx->fpu_enabled)) { \
3200 gen_exception(ctx, POWERPC_EXCP_FPU); \
3201 return; \
3202 } \
3203 if (unlikely(rA(ctx->opcode) == 0)) { \
3204 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3205 return; \
3206 } \
3207 gen_set_access_type(ctx, ACCESS_FLOAT); \
3208 EA = tcg_temp_new(); \
3209 gen_addr_reg_index(ctx, EA); \
3210 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3211 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3212 tcg_temp_free(EA); \
3213 }
3214
3215 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3216 static void glue(gen_, name##x)(DisasContext *ctx) \
3217 { \
3218 TCGv EA; \
3219 if (unlikely(!ctx->fpu_enabled)) { \
3220 gen_exception(ctx, POWERPC_EXCP_FPU); \
3221 return; \
3222 } \
3223 gen_set_access_type(ctx, ACCESS_FLOAT); \
3224 EA = tcg_temp_new(); \
3225 gen_addr_reg_index(ctx, EA); \
3226 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3227 tcg_temp_free(EA); \
3228 }
3229
3230 #define GEN_LDFS(name, ldop, op, type) \
3231 GEN_LDF(name, ldop, op | 0x20, type); \
3232 GEN_LDUF(name, ldop, op | 0x21, type); \
3233 GEN_LDUXF(name, ldop, op | 0x01, type); \
3234 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3235
3236 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3237 {
3238 TCGv t0 = tcg_temp_new();
3239 TCGv_i32 t1 = tcg_temp_new_i32();
3240 gen_qemu_ld32u(ctx, t0, arg2);
3241 tcg_gen_trunc_tl_i32(t1, t0);
3242 tcg_temp_free(t0);
3243 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3244 tcg_temp_free_i32(t1);
3245 }
3246
3247 /* lfd lfdu lfdux lfdx */
3248 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3249 /* lfs lfsu lfsux lfsx */
3250 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3251
3252 /*** Floating-point store ***/
3253 #define GEN_STF(name, stop, opc, type) \
3254 static void glue(gen_, name)(DisasContext *ctx) \
3255 { \
3256 TCGv EA; \
3257 if (unlikely(!ctx->fpu_enabled)) { \
3258 gen_exception(ctx, POWERPC_EXCP_FPU); \
3259 return; \
3260 } \
3261 gen_set_access_type(ctx, ACCESS_FLOAT); \
3262 EA = tcg_temp_new(); \
3263 gen_addr_imm_index(ctx, EA, 0); \
3264 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3265 tcg_temp_free(EA); \
3266 }
3267
3268 #define GEN_STUF(name, stop, opc, type) \
3269 static void glue(gen_, name##u)(DisasContext *ctx) \
3270 { \
3271 TCGv EA; \
3272 if (unlikely(!ctx->fpu_enabled)) { \
3273 gen_exception(ctx, POWERPC_EXCP_FPU); \
3274 return; \
3275 } \
3276 if (unlikely(rA(ctx->opcode) == 0)) { \
3277 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3278 return; \
3279 } \
3280 gen_set_access_type(ctx, ACCESS_FLOAT); \
3281 EA = tcg_temp_new(); \
3282 gen_addr_imm_index(ctx, EA, 0); \
3283 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3284 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3285 tcg_temp_free(EA); \
3286 }
3287
3288 #define GEN_STUXF(name, stop, opc, type) \
3289 static void glue(gen_, name##ux)(DisasContext *ctx) \
3290 { \
3291 TCGv EA; \
3292 if (unlikely(!ctx->fpu_enabled)) { \
3293 gen_exception(ctx, POWERPC_EXCP_FPU); \
3294 return; \
3295 } \
3296 if (unlikely(rA(ctx->opcode) == 0)) { \
3297 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3298 return; \
3299 } \
3300 gen_set_access_type(ctx, ACCESS_FLOAT); \
3301 EA = tcg_temp_new(); \
3302 gen_addr_reg_index(ctx, EA); \
3303 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3304 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3305 tcg_temp_free(EA); \
3306 }
3307
3308 #define GEN_STXF(name, stop, opc2, opc3, type) \
3309 static void glue(gen_, name##x)(DisasContext *ctx) \
3310 { \
3311 TCGv EA; \
3312 if (unlikely(!ctx->fpu_enabled)) { \
3313 gen_exception(ctx, POWERPC_EXCP_FPU); \
3314 return; \
3315 } \
3316 gen_set_access_type(ctx, ACCESS_FLOAT); \
3317 EA = tcg_temp_new(); \
3318 gen_addr_reg_index(ctx, EA); \
3319 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3320 tcg_temp_free(EA); \
3321 }
3322
3323 #define GEN_STFS(name, stop, op, type) \
3324 GEN_STF(name, stop, op | 0x20, type); \
3325 GEN_STUF(name, stop, op | 0x21, type); \
3326 GEN_STUXF(name, stop, op | 0x01, type); \
3327 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3328
3329 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3330 {
3331 TCGv_i32 t0 = tcg_temp_new_i32();
3332 TCGv t1 = tcg_temp_new();
3333 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3334 tcg_gen_extu_i32_tl(t1, t0);
3335 tcg_temp_free_i32(t0);
3336 gen_qemu_st32(ctx, t1, arg2);
3337 tcg_temp_free(t1);
3338 }
3339
3340 /* stfd stfdu stfdux stfdx */
3341 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3342 /* stfs stfsu stfsux stfsx */
3343 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3344
3345 /* Optional: */
3346 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3347 {
3348 TCGv t0 = tcg_temp_new();
3349 tcg_gen_trunc_i64_tl(t0, arg1),
3350 gen_qemu_st32(ctx, t0, arg2);
3351 tcg_temp_free(t0);
3352 }
3353 /* stfiwx */
3354 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3355
3356 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3357 {
3358 #if defined(TARGET_PPC64)
3359 if (ctx->has_cfar)
3360 tcg_gen_movi_tl(cpu_cfar, nip);
3361 #endif
3362 }
3363
3364 /*** Branch ***/
3365 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3366 {
3367 TranslationBlock *tb;
3368 tb = ctx->tb;
3369 #if defined(TARGET_PPC64)
3370 if (!ctx->sf_mode)
3371 dest = (uint32_t) dest;
3372 #endif
3373 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3374 likely(!ctx->singlestep_enabled)) {
3375 tcg_gen_goto_tb(n);
3376 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3377 tcg_gen_exit_tb((tcg_target_long)tb + n);
3378 } else {
3379 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3380 if (unlikely(ctx->singlestep_enabled)) {
3381 if ((ctx->singlestep_enabled &
3382 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3383 (ctx->exception == POWERPC_EXCP_BRANCH ||
3384 ctx->exception == POWERPC_EXCP_TRACE)) {
3385 target_ulong tmp = ctx->nip;
3386 ctx->nip = dest;
3387 gen_exception(ctx, POWERPC_EXCP_TRACE);
3388 ctx->nip = tmp;
3389 }
3390 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3391 gen_debug_exception(ctx);
3392 }
3393 }
3394 tcg_gen_exit_tb(0);
3395 }
3396 }
3397
3398 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3399 {
3400 #if defined(TARGET_PPC64)
3401 if (ctx->sf_mode == 0)
3402 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3403 else
3404 #endif
3405 tcg_gen_movi_tl(cpu_lr, nip);
3406 }
3407
3408 /* b ba bl bla */
3409 static void gen_b(DisasContext *ctx)
3410 {
3411 target_ulong li, target;
3412
3413 ctx->exception = POWERPC_EXCP_BRANCH;
3414 /* sign extend LI */
3415 #if defined(TARGET_PPC64)
3416 if (ctx->sf_mode)
3417 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3418 else
3419 #endif
3420 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3421 if (likely(AA(ctx->opcode) == 0))
3422 target = ctx->nip + li - 4;
3423 else
3424 target = li;
3425 if (LK(ctx->opcode))
3426 gen_setlr(ctx, ctx->nip);
3427 gen_update_cfar(ctx, ctx->nip);
3428 gen_goto_tb(ctx, 0, target);
3429 }
3430
3431 #define BCOND_IM 0
3432 #define BCOND_LR 1
3433 #define BCOND_CTR 2
3434
3435 static inline void gen_bcond(DisasContext *ctx, int type)
3436 {
3437 uint32_t bo = BO(ctx->opcode);
3438 int l1;
3439 TCGv target;
3440
3441 ctx->exception = POWERPC_EXCP_BRANCH;
3442 if (type == BCOND_LR || type == BCOND_CTR) {
3443 target = tcg_temp_local_new();
3444 if (type == BCOND_CTR)
3445 tcg_gen_mov_tl(target, cpu_ctr);
3446 else
3447 tcg_gen_mov_tl(target, cpu_lr);
3448 } else {
3449 TCGV_UNUSED(target);
3450 }
3451 if (LK(ctx->opcode))
3452 gen_setlr(ctx, ctx->nip);
3453 l1 = gen_new_label();
3454 if ((bo & 0x4) == 0) {
3455 /* Decrement and test CTR */
3456 TCGv temp = tcg_temp_new();
3457 if (unlikely(type == BCOND_CTR)) {
3458 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3459 return;
3460 }
3461 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3462 #if defined(TARGET_PPC64)
3463 if (!ctx->sf_mode)
3464 tcg_gen_ext32u_tl(temp, cpu_ctr);
3465 else
3466 #endif
3467 tcg_gen_mov_tl(temp, cpu_ctr);
3468 if (bo & 0x2) {
3469 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3470 } else {
3471 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3472 }
3473 tcg_temp_free(temp);
3474 }
3475 if ((bo & 0x10) == 0) {
3476 /* Test CR */
3477 uint32_t bi = BI(ctx->opcode);
3478 uint32_t mask = 1 << (3 - (bi & 0x03));
3479 TCGv_i32 temp = tcg_temp_new_i32();
3480
3481 if (bo & 0x8) {
3482 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3483 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3484 } else {
3485 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3486 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3487 }
3488 tcg_temp_free_i32(temp);
3489 }
3490 gen_update_cfar(ctx, ctx->nip);
3491 if (type == BCOND_IM) {
3492 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3493 if (likely(AA(ctx->opcode) == 0)) {
3494 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3495 } else {
3496 gen_goto_tb(ctx, 0, li);
3497 }
3498 gen_set_label(l1);
3499 gen_goto_tb(ctx, 1, ctx->nip);
3500 } else {
3501 #if defined(TARGET_PPC64)
3502 if (!(ctx->sf_mode))
3503 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3504 else
3505 #endif
3506 tcg_gen_andi_tl(cpu_nip, target, ~3);
3507 tcg_gen_exit_tb(0);
3508 gen_set_label(l1);
3509 #if defined(TARGET_PPC64)
3510 if (!(ctx->sf_mode))
3511 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3512 else
3513 #endif
3514 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3515 tcg_gen_exit_tb(0);
3516 }
3517 }
3518
3519 static void gen_bc(DisasContext *ctx)
3520 {
3521 gen_bcond(ctx, BCOND_IM);
3522 }
3523
3524 static void gen_bcctr(DisasContext *ctx)
3525 {
3526 gen_bcond(ctx, BCOND_CTR);
3527 }
3528
3529 static void gen_bclr(DisasContext *ctx)
3530 {
3531 gen_bcond(ctx, BCOND_LR);
3532 }
3533
3534 /*** Condition register logical ***/
3535 #define GEN_CRLOGIC(name, tcg_op, opc) \
3536 static void glue(gen_, name)(DisasContext *ctx) \
3537 { \
3538 uint8_t bitmask; \
3539 int sh; \
3540 TCGv_i32 t0, t1; \
3541 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3542 t0 = tcg_temp_new_i32(); \
3543 if (sh > 0) \
3544 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3545 else if (sh < 0) \
3546 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3547 else \
3548 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3549 t1 = tcg_temp_new_i32(); \
3550 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3551 if (sh > 0) \
3552 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3553 else if (sh < 0) \
3554 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3555 else \
3556 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3557 tcg_op(t0, t0, t1); \
3558 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3559 tcg_gen_andi_i32(t0, t0, bitmask); \
3560 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3561 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3562 tcg_temp_free_i32(t0); \
3563 tcg_temp_free_i32(t1); \
3564 }
3565
3566 /* crand */
3567 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3568 /* crandc */
3569 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3570 /* creqv */
3571 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3572 /* crnand */
3573 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3574 /* crnor */
3575 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3576 /* cror */
3577 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3578 /* crorc */
3579 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3580 /* crxor */
3581 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3582
3583 /* mcrf */
3584 static void gen_mcrf(DisasContext *ctx)
3585 {
3586 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3587 }
3588
3589 /*** System linkage ***/
3590
3591 /* rfi (mem_idx only) */
3592 static void gen_rfi(DisasContext *ctx)
3593 {
3594 #if defined(CONFIG_USER_ONLY)
3595 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3596 #else
3597 /* Restore CPU state */
3598 if (unlikely(!ctx->mem_idx)) {
3599 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3600 return;
3601 }
3602 gen_update_cfar(ctx, ctx->nip);
3603 gen_helper_rfi(cpu_env);
3604 gen_sync_exception(ctx);
3605 #endif
3606 }
3607
3608 #if defined(TARGET_PPC64)
3609 static void gen_rfid(DisasContext *ctx)
3610 {
3611 #if defined(CONFIG_USER_ONLY)
3612 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3613 #else
3614 /* Restore CPU state */
3615 if (unlikely(!ctx->mem_idx)) {
3616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3617 return;
3618 }
3619 gen_update_cfar(ctx, ctx->nip);
3620 gen_helper_rfid(cpu_env);
3621 gen_sync_exception(ctx);
3622 #endif
3623 }
3624
3625 static void gen_hrfid(DisasContext *ctx)
3626 {
3627 #if defined(CONFIG_USER_ONLY)
3628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3629 #else
3630 /* Restore CPU state */
3631 if (unlikely(ctx->mem_idx <= 1)) {
3632 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3633 return;
3634 }
3635 gen_helper_hrfid(cpu_env);
3636 gen_sync_exception(ctx);
3637 #endif
3638 }
3639 #endif
3640
3641 /* sc */
3642 #if defined(CONFIG_USER_ONLY)
3643 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3644 #else
3645 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3646 #endif
3647 static void gen_sc(DisasContext *ctx)
3648 {
3649 uint32_t lev;
3650
3651 lev = (ctx->opcode >> 5) & 0x7F;
3652 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3653 }
3654
3655 /*** Trap ***/
3656
3657 /* tw */
3658 static void gen_tw(DisasContext *ctx)
3659 {
3660 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3661 /* Update the nip since this might generate a trap exception */
3662 gen_update_nip(ctx, ctx->nip);
3663 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3664 t0);
3665 tcg_temp_free_i32(t0);
3666 }
3667
3668 /* twi */
3669 static void gen_twi(DisasContext *ctx)
3670 {
3671 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3672 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3673 /* Update the nip since this might generate a trap exception */
3674 gen_update_nip(ctx, ctx->nip);
3675 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3676 tcg_temp_free(t0);
3677 tcg_temp_free_i32(t1);
3678 }
3679
3680 #if defined(TARGET_PPC64)
3681 /* td */
3682 static void gen_td(DisasContext *ctx)
3683 {
3684 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3685 /* Update the nip since this might generate a trap exception */
3686 gen_update_nip(ctx, ctx->nip);
3687 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3688 t0);
3689 tcg_temp_free_i32(t0);
3690 }
3691
3692 /* tdi */
3693 static void gen_tdi(DisasContext *ctx)
3694 {
3695 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3696 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3697 /* Update the nip since this might generate a trap exception */
3698 gen_update_nip(ctx, ctx->nip);
3699 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3700 tcg_temp_free(t0);
3701 tcg_temp_free_i32(t1);
3702 }
3703 #endif
3704
3705 /*** Processor control ***/
3706
3707 static void gen_read_xer(TCGv dst)
3708 {
3709 TCGv t0 = tcg_temp_new();
3710 TCGv t1 = tcg_temp_new();
3711 TCGv t2 = tcg_temp_new();
3712 tcg_gen_mov_tl(dst, cpu_xer);
3713 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3714 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3715 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3716 tcg_gen_or_tl(t0, t0, t1);
3717 tcg_gen_or_tl(dst, dst, t2);
3718 tcg_gen_or_tl(dst, dst, t0);
3719 tcg_temp_free(t0);
3720 tcg_temp_free(t1);
3721 tcg_temp_free(t2);
3722 }
3723
3724 static void gen_write_xer(TCGv src)
3725 {
3726 tcg_gen_andi_tl(cpu_xer, src,
3727 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3728 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3729 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3730 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3731 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3732 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3733 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3734 }
3735
3736 /* mcrxr */
3737 static void gen_mcrxr(DisasContext *ctx)
3738 {
3739 TCGv_i32 t0 = tcg_temp_new_i32();
3740 TCGv_i32 t1 = tcg_temp_new_i32();
3741 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3742
3743 tcg_gen_trunc_tl_i32(t0, cpu_so);
3744 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3745 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3746 tcg_gen_shri_i32(t0, t0, 2);
3747 tcg_gen_shri_i32(t1, t1, 1);
3748 tcg_gen_or_i32(dst, dst, t0);
3749 tcg_gen_or_i32(dst, dst, t1);
3750 tcg_temp_free_i32(t0);
3751 tcg_temp_free_i32(t1);
3752
3753 tcg_gen_movi_tl(cpu_so, 0);
3754 tcg_gen_movi_tl(cpu_ov, 0);
3755 tcg_gen_movi_tl(cpu_ca, 0);
3756 }
3757
3758 /* mfcr mfocrf */
3759 static void gen_mfcr(DisasContext *ctx)
3760 {
3761 uint32_t crm, crn;
3762
3763 if (likely(ctx->opcode & 0x00100000)) {
3764 crm = CRM(ctx->opcode);
3765 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3766 crn = ctz32 (crm);
3767 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3768 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3769 cpu_gpr[rD(ctx->opcode)], crn * 4);
3770 }
3771 } else {
3772 TCGv_i32 t0 = tcg_temp_new_i32();
3773 tcg_gen_mov_i32(t0, cpu_crf[0]);
3774 tcg_gen_shli_i32(t0, t0, 4);
3775 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3776 tcg_gen_shli_i32(t0, t0, 4);
3777 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3778 tcg_gen_shli_i32(t0, t0, 4);
3779 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3780 tcg_gen_shli_i32(t0, t0, 4);
3781 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3782 tcg_gen_shli_i32(t0, t0, 4);
3783 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3784 tcg_gen_shli_i32(t0, t0, 4);
3785 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3786 tcg_gen_shli_i32(t0, t0, 4);
3787 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3788 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3789 tcg_temp_free_i32(t0);
3790 }
3791 }
3792
3793 /* mfmsr */
3794 static void gen_mfmsr(DisasContext *ctx)
3795 {
3796 #if defined(CONFIG_USER_ONLY)
3797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3798 #else
3799 if (unlikely(!ctx->mem_idx)) {
3800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3801 return;
3802 }
3803 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3804 #endif
3805 }
3806
3807 static void spr_noaccess(void *opaque, int gprn, int sprn)
3808 {
3809 #if 0
3810 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3811 printf("ERROR: try to access SPR %d !\n", sprn);
3812 #endif
3813 }
3814 #define SPR_NOACCESS (&spr_noaccess)
3815
3816 /* mfspr */
3817 static inline void gen_op_mfspr(DisasContext *ctx)
3818 {
3819 void (*read_cb)(void *opaque, int gprn, int sprn);
3820 uint32_t sprn = SPR(ctx->opcode);
3821
3822 #if !defined(CONFIG_USER_ONLY)
3823 if (ctx->mem_idx == 2)
3824 read_cb = ctx->spr_cb[sprn].hea_read;
3825 else if (ctx->mem_idx)
3826 read_cb = ctx->spr_cb[sprn].oea_read;
3827 else
3828 #endif
3829 read_cb = ctx->spr_cb[sprn].uea_read;
3830 if (likely(read_cb != NULL)) {
3831 if (likely(read_cb != SPR_NOACCESS)) {
3832 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3833 } else {
3834 /* Privilege exception */
3835 /* This is a hack to avoid warnings when running Linux:
3836 * this OS breaks the PowerPC virtualisation model,
3837 * allowing userland application to read the PVR
3838 */
3839 if (sprn != SPR_PVR) {
3840 qemu_log("Trying to read privileged spr %d %03x at "
3841 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3842 printf("Trying to read privileged spr %d %03x at "
3843 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3844 }
3845 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3846 }
3847 } else {
3848 /* Not defined */
3849 qemu_log("Trying to read invalid spr %d %03x at "
3850 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3851 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3852 sprn, sprn, ctx->nip);
3853 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3854 }
3855 }
3856
3857 static void gen_mfspr(DisasContext *ctx)
3858 {
3859 gen_op_mfspr(ctx);
3860 }
3861
3862 /* mftb */
3863 static void gen_mftb(DisasContext *ctx)
3864 {
3865 gen_op_mfspr(ctx);
3866 }
3867
3868 /* mtcrf mtocrf*/
3869 static void gen_mtcrf(DisasContext *ctx)
3870 {
3871 uint32_t crm, crn;
3872
3873 crm = CRM(ctx->opcode);
3874 if (likely((ctx->opcode & 0x00100000))) {
3875 if (crm && ((crm & (crm - 1)) == 0)) {
3876 TCGv_i32 temp = tcg_temp_new_i32();
3877 crn = ctz32 (crm);
3878 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3879 tcg_gen_shri_i32(temp, temp, crn * 4);
3880 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3881 tcg_temp_free_i32(temp);
3882 }
3883 } else {
3884 TCGv_i32 temp = tcg_temp_new_i32();
3885 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3886 for (crn = 0 ; crn < 8 ; crn++) {
3887 if (crm & (1 << crn)) {
3888 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3889 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3890 }
3891 }
3892 tcg_temp_free_i32(temp);
3893 }
3894 }
3895
3896 /* mtmsr */
3897 #if defined(TARGET_PPC64)
3898 static void gen_mtmsrd(DisasContext *ctx)
3899 {
3900 #if defined(CONFIG_USER_ONLY)
3901 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3902 #else
3903 if (unlikely(!ctx->mem_idx)) {
3904 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3905 return;
3906 }
3907 if (ctx->opcode & 0x00010000) {
3908 /* Special form that does not need any synchronisation */
3909 TCGv t0 = tcg_temp_new();
3910 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3911 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3912 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3913 tcg_temp_free(t0);
3914 } else {
3915 /* XXX: we need to update nip before the store
3916 * if we enter power saving mode, we will exit the loop
3917 * directly from ppc_store_msr
3918 */
3919 gen_update_nip(ctx, ctx->nip);
3920 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3921 /* Must stop the translation as machine state (may have) changed */
3922 /* Note that mtmsr is not always defined as context-synchronizing */
3923 gen_stop_exception(ctx);
3924 }
3925 #endif
3926 }
3927 #endif
3928
3929 static void gen_mtmsr(DisasContext *ctx)
3930 {
3931 #if defined(CONFIG_USER_ONLY)
3932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3933 #else
3934 if (unlikely(!ctx->mem_idx)) {
3935 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3936 return;
3937 }
3938 if (ctx->opcode & 0x00010000) {
3939 /* Special form that does not need any synchronisation */
3940 TCGv t0 = tcg_temp_new();
3941 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3942 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3943 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3944 tcg_temp_free(t0);
3945 } else {
3946 TCGv msr = tcg_temp_new();
3947
3948 /* XXX: we need to update nip before the store
3949 * if we enter power saving mode, we will exit the loop
3950 * directly from ppc_store_msr
3951 */
3952 gen_update_nip(ctx, ctx->nip);
3953 #if defined(TARGET_PPC64)
3954 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3955 #else
3956 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3957 #endif
3958 gen_helper_store_msr(cpu_env, msr);
3959 /* Must stop the translation as machine state (may have) changed */
3960 /* Note that mtmsr is not always defined as context-synchronizing */
3961 gen_stop_exception(ctx);
3962 }
3963 #endif
3964 }
3965
3966 /* mtspr */
3967 static void gen_mtspr(DisasContext *ctx)
3968 {
3969 void (*write_cb)(void *opaque, int sprn, int gprn);
3970 uint32_t sprn = SPR(ctx->opcode);
3971
3972 #if !defined(CONFIG_USER_ONLY)
3973 if (ctx->mem_idx == 2)
3974 write_cb = ctx->spr_cb[sprn].hea_write;
3975 else if (ctx->mem_idx)
3976 write_cb = ctx->spr_cb[sprn].oea_write;
3977 else
3978 #endif
3979 write_cb = ctx->spr_cb[sprn].uea_write;
3980 if (likely(write_cb != NULL)) {
3981 if (likely(write_cb != SPR_NOACCESS)) {
3982 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3983 } else {
3984 /* Privilege exception */
3985 qemu_log("Trying to write privileged spr %d %03x at "
3986 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3987 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3988 "\n", sprn, sprn, ctx->nip);
3989 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3990 }
3991 } else {
3992 /* Not defined */
3993 qemu_log("Trying to write invalid spr %d %03x at "
3994 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3995 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3996 sprn, sprn, ctx->nip);
3997 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3998 }
3999 }
4000
4001 /*** Cache management ***/
4002
4003 /* dcbf */
4004 static void gen_dcbf(DisasContext *ctx)
4005 {
4006 /* XXX: specification says this is treated as a load by the MMU */
4007 TCGv t0;
4008 gen_set_access_type(ctx, ACCESS_CACHE);
4009 t0 = tcg_temp_new();
4010 gen_addr_reg_index(ctx, t0);
4011 gen_qemu_ld8u(ctx, t0, t0);
4012 tcg_temp_free(t0);
4013 }
4014
4015 /* dcbi (Supervisor only) */
4016 static void gen_dcbi(DisasContext *ctx)
4017 {
4018 #if defined(CONFIG_USER_ONLY)
4019 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4020 #else
4021 TCGv EA, val;
4022 if (unlikely(!ctx->mem_idx)) {
4023 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4024 return;
4025 }
4026 EA = tcg_temp_new();
4027 gen_set_access_type(ctx, ACCESS_CACHE);
4028 gen_addr_reg_index(ctx, EA);
4029 val = tcg_temp_new();
4030 /* XXX: specification says this should be treated as a store by the MMU */
4031 gen_qemu_ld8u(ctx, val, EA);
4032 gen_qemu_st8(ctx, val, EA);
4033 tcg_temp_free(val);
4034 tcg_temp_free(EA);
4035 #endif
4036 }
4037
4038 /* dcdst */
4039 static void gen_dcbst(DisasContext *ctx)
4040 {
4041 /* XXX: specification say this is treated as a load by the MMU */
4042 TCGv t0;
4043 gen_set_access_type(ctx, ACCESS_CACHE);
4044 t0 = tcg_temp_new();
4045 gen_addr_reg_index(ctx, t0);
4046 gen_qemu_ld8u(ctx, t0, t0);
4047 tcg_temp_free(t0);
4048 }
4049
4050 /* dcbt */
4051 static void gen_dcbt(DisasContext *ctx)
4052 {
4053 /* interpreted as no-op */
4054 /* XXX: specification say this is treated as a load by the MMU
4055 * but does not generate any exception
4056 */
4057 }
4058
4059 /* dcbtst */
4060 static void gen_dcbtst(DisasContext *ctx)
4061 {
4062 /* interpreted as no-op */
4063 /* XXX: specification say this is treated as a load by the MMU
4064 * but does not generate any exception
4065 */
4066 }
4067
4068 /* dcbz */
4069 static void gen_dcbz(DisasContext *ctx)
4070 {
4071 TCGv tcgv_addr;
4072 TCGv_i32 tcgv_is_dcbzl;
4073 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4074
4075 gen_set_access_type(ctx, ACCESS_CACHE);
4076 /* NIP cannot be restored if the memory exception comes from an helper */
4077 gen_update_nip(ctx, ctx->nip - 4);
4078 tcgv_addr = tcg_temp_new();
4079 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4080
4081 gen_addr_reg_index(ctx, tcgv_addr);
4082 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4083
4084 tcg_temp_free(tcgv_addr);
4085 tcg_temp_free_i32(tcgv_is_dcbzl);
4086 }
4087
4088 /* dst / dstt */
4089 static void gen_dst(DisasContext *ctx)
4090 {
4091 if (rA(ctx->opcode) == 0) {
4092 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4093 } else {
4094 /* interpreted as no-op */
4095 }
4096 }
4097
4098 /* dstst /dststt */
4099 static void gen_dstst(DisasContext *ctx)
4100 {
4101 if (rA(ctx->opcode) == 0) {
4102 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4103 } else {
4104 /* interpreted as no-op */
4105 }
4106
4107 }
4108
4109 /* dss / dssall */
4110 static void gen_dss(DisasContext *ctx)
4111 {
4112 /* interpreted as no-op */
4113 }
4114
4115 /* icbi */
4116 static void gen_icbi(DisasContext *ctx)
4117 {
4118 TCGv t0;
4119 gen_set_access_type(ctx, ACCESS_CACHE);
4120 /* NIP cannot be restored if the memory exception comes from an helper */
4121 gen_update_nip(ctx, ctx->nip - 4);
4122 t0 = tcg_temp_new();
4123 gen_addr_reg_index(ctx, t0);
4124 gen_helper_icbi(cpu_env, t0);
4125 tcg_temp_free(t0);
4126 }
4127
4128 /* Optional: */
4129 /* dcba */
4130 static void gen_dcba(DisasContext *ctx)
4131 {
4132 /* interpreted as no-op */
4133 /* XXX: specification say this is treated as a store by the MMU
4134 * but does not generate any exception
4135 */
4136 }
4137
4138 /*** Segment register manipulation ***/
4139 /* Supervisor only: */
4140
4141 /* mfsr */
4142 static void gen_mfsr(DisasContext *ctx)
4143 {
4144 #if defined(CONFIG_USER_ONLY)
4145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4146 #else
4147 TCGv t0;
4148 if (unlikely(!ctx->mem_idx)) {
4149 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4150 return;
4151 }
4152 t0 = tcg_const_tl(SR(ctx->opcode));
4153 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4154 tcg_temp_free(t0);
4155 #endif
4156 }
4157
4158 /* mfsrin */
4159 static void gen_mfsrin(DisasContext *ctx)
4160 {
4161 #if defined(CONFIG_USER_ONLY)
4162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4163 #else
4164 TCGv t0;
4165 if (unlikely(!ctx->mem_idx)) {
4166 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4167 return;
4168 }
4169 t0 = tcg_temp_new();
4170 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4171 tcg_gen_andi_tl(t0, t0, 0xF);
4172 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4173 tcg_temp_free(t0);
4174 #endif
4175 }
4176
4177 /* mtsr */
4178 static void gen_mtsr(DisasContext *ctx)
4179 {
4180 #if defined(CONFIG_USER_ONLY)
4181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4182 #else
4183 TCGv t0;
4184 if (unlikely(!ctx->mem_idx)) {
4185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4186 return;
4187 }
4188 t0 = tcg_const_tl(SR(ctx->opcode));
4189 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4190 tcg_temp_free(t0);
4191 #endif
4192 }
4193
4194 /* mtsrin */
4195 static void gen_mtsrin(DisasContext *ctx)
4196 {
4197 #if defined(CONFIG_USER_ONLY)
4198 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4199 #else
4200 TCGv t0;
4201 if (unlikely(!ctx->mem_idx)) {
4202 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4203 return;
4204 }
4205 t0 = tcg_temp_new();
4206 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4207 tcg_gen_andi_tl(t0, t0, 0xF);
4208 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4209 tcg_temp_free(t0);
4210 #endif
4211 }
4212
4213 #if defined(TARGET_PPC64)
4214 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4215
4216 /* mfsr */
4217 static void gen_mfsr_64b(DisasContext *ctx)
4218 {
4219 #if defined(CONFIG_USER_ONLY)
4220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4221 #else
4222 TCGv t0;
4223 if (unlikely(!ctx->mem_idx)) {
4224 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4225 return;
4226 }
4227 t0 = tcg_const_tl(SR(ctx->opcode));
4228 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4229 tcg_temp_free(t0);
4230 #endif
4231 }
4232
4233 /* mfsrin */
4234 static void gen_mfsrin_64b(DisasContext *ctx)
4235 {
4236 #if defined(CONFIG_USER_ONLY)
4237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4238 #else
4239 TCGv t0;
4240 if (unlikely(!ctx->mem_idx)) {
4241 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4242 return;
4243 }
4244 t0 = tcg_temp_new();
4245 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4246 tcg_gen_andi_tl(t0, t0, 0xF);
4247 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4248 tcg_temp_free(t0);
4249 #endif
4250 }
4251
4252 /* mtsr */
4253 static void gen_mtsr_64b(DisasContext *ctx)
4254 {
4255 #if defined(CONFIG_USER_ONLY)
4256 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4257 #else
4258 TCGv t0;
4259 if (unlikely(!ctx->mem_idx)) {
4260 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4261 return;
4262 }
4263 t0 = tcg_const_tl(SR(ctx->opcode));
4264 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4265 tcg_temp_free(t0);
4266 #endif
4267 }
4268
4269 /* mtsrin */
4270 static void gen_mtsrin_64b(DisasContext *ctx)
4271 {
4272 #if defined(CONFIG_USER_ONLY)
4273 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4274 #else
4275 TCGv t0;
4276 if (unlikely(!ctx->mem_idx)) {
4277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4278 return;
4279 }
4280 t0 = tcg_temp_new();
4281 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4282 tcg_gen_andi_tl(t0, t0, 0xF);
4283 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4284 tcg_temp_free(t0);
4285 #endif
4286 }
4287
4288 /* slbmte */
4289 static void gen_slbmte(DisasContext *ctx)
4290 {
4291 #if defined(CONFIG_USER_ONLY)
4292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4293 #else
4294 if (unlikely(!ctx->mem_idx)) {
4295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4296 return;
4297 }
4298 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4299 cpu_gpr[rS(ctx->opcode)]);
4300 #endif
4301 }
4302
4303 static void gen_slbmfee(DisasContext *ctx)
4304 {
4305 #if defined(CONFIG_USER_ONLY)
4306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4307 #else
4308 if (unlikely(!ctx->mem_idx)) {
4309 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4310 return;
4311 }
4312 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4313 cpu_gpr[rB(ctx->opcode)]);
4314 #endif
4315 }
4316
4317 static void gen_slbmfev(DisasContext *ctx)
4318 {
4319 #if defined(CONFIG_USER_ONLY)
4320 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4321 #else
4322 if (unlikely(!ctx->mem_idx)) {
4323 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4324 return;
4325 }
4326 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4327 cpu_gpr[rB(ctx->opcode)]);
4328 #endif
4329 }
4330 #endif /* defined(TARGET_PPC64) */
4331
4332 /*** Lookaside buffer management ***/
4333 /* Optional & mem_idx only: */
4334
4335 /* tlbia */
4336 static void gen_tlbia(DisasContext *ctx)
4337 {
4338 #if defined(CONFIG_USER_ONLY)
4339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4340 #else
4341 if (unlikely(!ctx->mem_idx)) {
4342 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4343 return;
4344 }
4345 gen_helper_tlbia(cpu_env);
4346 #endif
4347 }
4348
4349 /* tlbiel */
4350 static void gen_tlbiel(DisasContext *ctx)
4351 {
4352 #if defined(CONFIG_USER_ONLY)
4353 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4354 #else
4355 if (unlikely(!ctx->mem_idx)) {
4356 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4357 return;
4358 }
4359 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4360 #endif
4361 }
4362
4363 /* tlbie */
4364 static void gen_tlbie(DisasContext *ctx)
4365 {
4366 #if defined(CONFIG_USER_ONLY)
4367 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4368 #else
4369 if (unlikely(!ctx->mem_idx)) {
4370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4371 return;
4372 }
4373 #if defined(TARGET_PPC64)
4374 if (!ctx->sf_mode) {
4375 TCGv t0 = tcg_temp_new();
4376 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4377 gen_helper_tlbie(cpu_env, t0);
4378 tcg_temp_free(t0);
4379 } else
4380 #endif
4381 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4382 #endif
4383 }
4384
4385 /* tlbsync */
4386 static void gen_tlbsync(DisasContext *ctx)
4387 {
4388 #if defined(CONFIG_USER_ONLY)
4389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4390 #else
4391 if (unlikely(!ctx->mem_idx)) {
4392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4393 return;
4394 }
4395 /* This has no effect: it should ensure that all previous
4396 * tlbie have completed
4397 */
4398 gen_stop_exception(ctx);
4399 #endif
4400 }
4401
4402 #if defined(TARGET_PPC64)
4403 /* slbia */
4404 static void gen_slbia(DisasContext *ctx)
4405 {
4406 #if defined(CONFIG_USER_ONLY)
4407 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4408 #else
4409 if (unlikely(!ctx->mem_idx)) {
4410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4411 return;
4412 }
4413 gen_helper_slbia(cpu_env);
4414 #endif
4415 }
4416
4417 /* slbie */
4418 static void gen_slbie(DisasContext *ctx)
4419 {
4420 #if defined(CONFIG_USER_ONLY)
4421 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4422 #else
4423 if (unlikely(!ctx->mem_idx)) {
4424 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4425 return;
4426 }
4427 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4428 #endif
4429 }
4430 #endif
4431
4432 /*** External control ***/
4433 /* Optional: */
4434
4435 /* eciwx */
4436 static void gen_eciwx(DisasContext *ctx)
4437 {
4438 TCGv t0;
4439 /* Should check EAR[E] ! */
4440 gen_set_access_type(ctx, ACCESS_EXT);
4441 t0 = tcg_temp_new();
4442 gen_addr_reg_index(ctx, t0);
4443 gen_check_align(ctx, t0, 0x03);
4444 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4445 tcg_temp_free(t0);
4446 }
4447
4448 /* ecowx */
4449 static void gen_ecowx(DisasContext *ctx)
4450 {
4451 TCGv t0;
4452 /* Should check EAR[E] ! */
4453 gen_set_access_type(ctx, ACCESS_EXT);
4454 t0 = tcg_temp_new();
4455 gen_addr_reg_index(ctx, t0);
4456 gen_check_align(ctx, t0, 0x03);
4457 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4458 tcg_temp_free(t0);
4459 }
4460
4461 /* PowerPC 601 specific instructions */
4462
4463 /* abs - abs. */
4464 static void gen_abs(DisasContext *ctx)
4465 {
4466 int l1 = gen_new_label();
4467 int l2 = gen_new_label();
4468 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4469 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4470 tcg_gen_br(l2);
4471 gen_set_label(l1);
4472 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4473 gen_set_label(l2);
4474 if (unlikely(Rc(ctx->opcode) != 0))
4475 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4476 }
4477
4478 /* abso - abso. */
4479 static void gen_abso(DisasContext *ctx)
4480 {
4481 int l1 = gen_new_label();
4482 int l2 = gen_new_label();
4483 int l3 = gen_new_label();
4484 /* Start with XER OV disabled, the most likely case */
4485 tcg_gen_movi_tl(cpu_ov, 0);
4486 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4487 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4488 tcg_gen_movi_tl(cpu_ov, 1);
4489 tcg_gen_movi_tl(cpu_so, 1);
4490 tcg_gen_br(l2);
4491 gen_set_label(l1);
4492 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4493 tcg_gen_br(l3);
4494 gen_set_label(l2);
4495 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4496 gen_set_label(l3);
4497 if (unlikely(Rc(ctx->opcode) != 0))
4498 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4499 }
4500
4501 /* clcs */
4502 static void gen_clcs(DisasContext *ctx)
4503 {
4504 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4505 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4506 tcg_temp_free_i32(t0);
4507 /* Rc=1 sets CR0 to an undefined state */
4508 }
4509
4510 /* div - div. */
4511 static void gen_div(DisasContext *ctx)
4512 {
4513 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4514 cpu_gpr[rB(ctx->opcode)]);
4515 if (unlikely(Rc(ctx->opcode) != 0))
4516 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4517 }
4518
4519 /* divo - divo. */
4520 static void gen_divo(DisasContext *ctx)
4521 {
4522 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4523 cpu_gpr[rB(ctx->opcode)]);
4524 if (unlikely(Rc(ctx->opcode) != 0))
4525 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4526 }
4527
4528 /* divs - divs. */
4529 static void gen_divs(DisasContext *ctx)
4530 {
4531 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4532 cpu_gpr[rB(ctx->opcode)]);
4533 if (unlikely(Rc(ctx->opcode) != 0))
4534 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4535 }
4536
4537 /* divso - divso. */
4538 static void gen_divso(DisasContext *ctx)
4539 {
4540 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4541 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4542 if (unlikely(Rc(ctx->opcode) != 0))
4543 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4544 }
4545
4546 /* doz - doz. */
4547 static void gen_doz(DisasContext *ctx)
4548 {
4549 int l1 = gen_new_label();
4550 int l2 = gen_new_label();
4551 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4552 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4553 tcg_gen_br(l2);
4554 gen_set_label(l1);
4555 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4556 gen_set_label(l2);
4557 if (unlikely(Rc(ctx->opcode) != 0))
4558 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4559 }
4560
4561 /* dozo - dozo. */
4562 static void gen_dozo(DisasContext *ctx)
4563 {
4564 int l1 = gen_new_label();
4565 int l2 = gen_new_label();
4566 TCGv t0 = tcg_temp_new();
4567 TCGv t1 = tcg_temp_new();
4568 TCGv t2 = tcg_temp_new();
4569 /* Start with XER OV disabled, the most likely case */
4570 tcg_gen_movi_tl(cpu_ov, 0);
4571 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4572 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4573 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4574 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4575 tcg_gen_andc_tl(t1, t1, t2);
4576 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4577 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4578 tcg_gen_movi_tl(cpu_ov, 1);
4579 tcg_gen_movi_tl(cpu_so, 1);
4580 tcg_gen_br(l2);
4581 gen_set_label(l1);
4582 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4583 gen_set_label(l2);
4584 tcg_temp_free(t0);
4585 tcg_temp_free(t1);
4586 tcg_temp_free(t2);
4587 if (unlikely(Rc(ctx->opcode) != 0))
4588 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4589 }
4590
4591 /* dozi */
4592 static void gen_dozi(DisasContext *ctx)
4593 {
4594 target_long simm = SIMM(ctx->opcode);
4595 int l1 = gen_new_label();
4596 int l2 = gen_new_label();
4597 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4598 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4599 tcg_gen_br(l2);
4600 gen_set_label(l1);
4601 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4602 gen_set_label(l2);
4603 if (unlikely(Rc(ctx->opcode) != 0))
4604 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4605 }
4606
4607 /* lscbx - lscbx. */
4608 static void gen_lscbx(DisasContext *ctx)
4609 {
4610 TCGv t0 = tcg_temp_new();
4611 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4612 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4613 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4614
4615 gen_addr_reg_index(ctx, t0);
4616 /* NIP cannot be restored if the memory exception comes from an helper */
4617 gen_update_nip(ctx, ctx->nip - 4);
4618 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4619 tcg_temp_free_i32(t1);
4620 tcg_temp_free_i32(t2);
4621 tcg_temp_free_i32(t3);
4622 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4623 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4624 if (unlikely(Rc(ctx->opcode) != 0))
4625 gen_set_Rc0(ctx, t0);
4626 tcg_temp_free(t0);
4627 }
4628
4629 /* maskg - maskg. */
4630 static void gen_maskg(DisasContext *ctx)
4631 {
4632 int l1 = gen_new_label();
4633 TCGv t0 = tcg_temp_new();
4634 TCGv t1 = tcg_temp_new();
4635 TCGv t2 = tcg_temp_new();
4636 TCGv t3 = tcg_temp_new();
4637 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4638 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4639 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4640 tcg_gen_addi_tl(t2, t0, 1);
4641 tcg_gen_shr_tl(t2, t3, t2);
4642 tcg_gen_shr_tl(t3, t3, t1);
4643 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4644 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4645 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4646 gen_set_label(l1);
4647 tcg_temp_free(t0);
4648 tcg_temp_free(t1);
4649 tcg_temp_free(t2);
4650 tcg_temp_free(t3);
4651 if (unlikely(Rc(ctx->opcode) != 0))
4652 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4653 }
4654
4655 /* maskir - maskir. */
4656 static void gen_maskir(DisasContext *ctx)
4657 {
4658 TCGv t0 = tcg_temp_new();
4659 TCGv t1 = tcg_temp_new();
4660 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4661 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4662 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4663 tcg_temp_free(t0);
4664 tcg_temp_free(t1);
4665 if (unlikely(Rc(ctx->opcode) != 0))
4666 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4667 }
4668
4669 /* mul - mul. */
4670 static void gen_mul(DisasContext *ctx)
4671 {
4672 TCGv_i64 t0 = tcg_temp_new_i64();
4673 TCGv_i64 t1 = tcg_temp_new_i64();
4674 TCGv t2 = tcg_temp_new();
4675 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4676 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4677 tcg_gen_mul_i64(t0, t0, t1);
4678 tcg_gen_trunc_i64_tl(t2, t0);
4679 gen_store_spr(SPR_MQ, t2);
4680 tcg_gen_shri_i64(t1, t0, 32);
4681 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4682 tcg_temp_free_i64(t0);
4683 tcg_temp_free_i64(t1);
4684 tcg_temp_free(t2);
4685 if (unlikely(Rc(ctx->opcode) != 0))
4686 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4687 }
4688
4689 /* mulo - mulo. */
4690 static void gen_mulo(DisasContext *ctx)
4691 {
4692 int l1 = gen_new_label();
4693 TCGv_i64 t0 = tcg_temp_new_i64();
4694 TCGv_i64 t1 = tcg_temp_new_i64();
4695 TCGv t2 = tcg_temp_new();
4696 /* Start with XER OV disabled, the most likely case */
4697 tcg_gen_movi_tl(cpu_ov, 0);
4698 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4699 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4700 tcg_gen_mul_i64(t0, t0, t1);
4701 tcg_gen_trunc_i64_tl(t2, t0);
4702 gen_store_spr(SPR_MQ, t2);
4703 tcg_gen_shri_i64(t1, t0, 32);
4704 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4705 tcg_gen_ext32s_i64(t1, t0);
4706 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4707 tcg_gen_movi_tl(cpu_ov, 1);
4708 tcg_gen_movi_tl(cpu_so, 1);
4709 gen_set_label(l1);
4710 tcg_temp_free_i64(t0);
4711 tcg_temp_free_i64(t1);
4712 tcg_temp_free(t2);
4713 if (unlikely(Rc(ctx->opcode) != 0))
4714 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4715 }
4716
4717 /* nabs - nabs. */
4718 static void gen_nabs(DisasContext *ctx)
4719 {
4720 int l1 = gen_new_label();
4721 int l2 = gen_new_label();
4722 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4723 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4724 tcg_gen_br(l2);
4725 gen_set_label(l1);
4726 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4727 gen_set_label(l2);
4728 if (unlikely(Rc(ctx->opcode) != 0))
4729 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4730 }
4731
4732 /* nabso - nabso. */
4733 static void gen_nabso(DisasContext *ctx)
4734 {
4735 int l1 = gen_new_label();
4736 int l2 = gen_new_label();
4737 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4738 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4739 tcg_gen_br(l2);
4740 gen_set_label(l1);
4741 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4742 gen_set_label(l2);
4743 /* nabs never overflows */
4744 tcg_gen_movi_tl(cpu_ov, 0);
4745 if (unlikely(Rc(ctx->opcode) != 0))
4746 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4747 }
4748
4749 /* rlmi - rlmi. */
4750 static void gen_rlmi(DisasContext *ctx)
4751 {
4752 uint32_t mb = MB(ctx->opcode);
4753 uint32_t me = ME(ctx->opcode);
4754 TCGv t0 = tcg_temp_new();
4755 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4756 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4757 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4758 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4759 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4760 tcg_temp_free(t0);
4761 if (unlikely(Rc(ctx->opcode) != 0))
4762 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4763 }
4764
4765 /* rrib - rrib. */
4766 static void gen_rrib(DisasContext *ctx)
4767 {
4768 TCGv t0 = tcg_temp_new();
4769 TCGv t1 = tcg_temp_new();
4770 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4771 tcg_gen_movi_tl(t1, 0x80000000);
4772 tcg_gen_shr_tl(t1, t1, t0);
4773 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4774 tcg_gen_and_tl(t0, t0, t1);
4775 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4776 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4777 tcg_temp_free(t0);
4778 tcg_temp_free(t1);
4779 if (unlikely(Rc(ctx->opcode) != 0))
4780 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4781 }
4782
4783 /* sle - sle. */
4784 static void gen_sle(DisasContext *ctx)
4785 {
4786 TCGv t0 = tcg_temp_new();
4787 TCGv t1 = tcg_temp_new();
4788 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4789 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4790 tcg_gen_subfi_tl(t1, 32, t1);
4791 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4792 tcg_gen_or_tl(t1, t0, t1);
4793 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4794 gen_store_spr(SPR_MQ, t1);
4795 tcg_temp_free(t0);
4796 tcg_temp_free(t1);
4797 if (unlikely(Rc(ctx->opcode) != 0))
4798 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4799 }
4800
4801 /* sleq - sleq. */
4802 static void gen_sleq(DisasContext *ctx)
4803 {
4804 TCGv t0 = tcg_temp_new();
4805 TCGv t1 = tcg_temp_new();
4806 TCGv t2 = tcg_temp_new();
4807 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4808 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4809 tcg_gen_shl_tl(t2, t2, t0);
4810 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4811 gen_load_spr(t1, SPR_MQ);
4812 gen_store_spr(SPR_MQ, t0);
4813 tcg_gen_and_tl(t0, t0, t2);
4814 tcg_gen_andc_tl(t1, t1, t2);
4815 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4816 tcg_temp_free(t0);
4817 tcg_temp_free(t1);
4818 tcg_temp_free(t2);
4819 if (unlikely(Rc(ctx->opcode) != 0))
4820 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4821 }
4822
4823 /* sliq - sliq. */
4824 static void gen_sliq(DisasContext *ctx)
4825 {
4826 int sh = SH(ctx->opcode);
4827 TCGv t0 = tcg_temp_new();
4828 TCGv t1 = tcg_temp_new();
4829 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4830 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4831 tcg_gen_or_tl(t1, t0, t1);
4832 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4833 gen_store_spr(SPR_MQ, t1);
4834 tcg_temp_free(t0);
4835 tcg_temp_free(t1);
4836 if (unlikely(Rc(ctx->opcode) != 0))
4837 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4838 }
4839
4840 /* slliq - slliq. */
4841 static void gen_slliq(DisasContext *ctx)
4842 {
4843 int sh = SH(ctx->opcode);
4844 TCGv t0 = tcg_temp_new();
4845 TCGv t1 = tcg_temp_new();
4846 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4847 gen_load_spr(t1, SPR_MQ);
4848 gen_store_spr(SPR_MQ, t0);
4849 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4850 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4851 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4852 tcg_temp_free(t0);
4853 tcg_temp_free(t1);
4854 if (unlikely(Rc(ctx->opcode) != 0))
4855 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4856 }
4857
4858 /* sllq - sllq. */
4859 static void gen_sllq(DisasContext *ctx)
4860 {
4861 int l1 = gen_new_label();
4862 int l2 = gen_new_label();
4863 TCGv t0 = tcg_temp_local_new();
4864 TCGv t1 = tcg_temp_local_new();
4865 TCGv t2 = tcg_temp_local_new();
4866 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4867 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4868 tcg_gen_shl_tl(t1, t1, t2);
4869 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4870 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4871 gen_load_spr(t0, SPR_MQ);
4872 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4873 tcg_gen_br(l2);
4874 gen_set_label(l1);
4875 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4876 gen_load_spr(t2, SPR_MQ);
4877 tcg_gen_andc_tl(t1, t2, t1);
4878 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4879 gen_set_label(l2);
4880 tcg_temp_free(t0);
4881 tcg_temp_free(t1);
4882 tcg_temp_free(t2);
4883 if (unlikely(Rc(ctx->opcode) != 0))
4884 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4885 }
4886
4887 /* slq - slq. */
4888 static void gen_slq(DisasContext *ctx)
4889 {
4890 int l1 = gen_new_label();
4891 TCGv t0 = tcg_temp_new();
4892 TCGv t1 = tcg_temp_new();
4893 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4894 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4895 tcg_gen_subfi_tl(t1, 32, t1);
4896 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4897 tcg_gen_or_tl(t1, t0, t1);
4898 gen_store_spr(SPR_MQ, t1);
4899 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4900 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4901 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4902 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4903 gen_set_label(l1);
4904 tcg_temp_free(t0);
4905 tcg_temp_free(t1);
4906 if (unlikely(Rc(ctx->opcode) != 0))
4907 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4908 }
4909
4910 /* sraiq - sraiq. */
4911 static void gen_sraiq(DisasContext *ctx)
4912 {
4913 int sh = SH(ctx->opcode);
4914 int l1 = gen_new_label();
4915 TCGv t0 = tcg_temp_new();
4916 TCGv t1 = tcg_temp_new();
4917 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4918 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4919 tcg_gen_or_tl(t0, t0, t1);
4920 gen_store_spr(SPR_MQ, t0);
4921 tcg_gen_movi_tl(cpu_ca, 0);
4922 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4923 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4924 tcg_gen_movi_tl(cpu_ca, 1);
4925 gen_set_label(l1);
4926 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4927 tcg_temp_free(t0);
4928 tcg_temp_free(t1);
4929 if (unlikely(Rc(ctx->opcode) != 0))
4930 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4931 }
4932
4933 /* sraq - sraq. */
4934 static void gen_sraq(DisasContext *ctx)
4935 {
4936 int l1 = gen_new_label();
4937 int l2 = gen_new_label();
4938 TCGv t0 = tcg_temp_new();
4939 TCGv t1 = tcg_temp_local_new();
4940 TCGv t2 = tcg_temp_local_new();
4941 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4942 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4943 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4944 tcg_gen_subfi_tl(t2, 32, t2);
4945 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4946 tcg_gen_or_tl(t0, t0, t2);
4947 gen_store_spr(SPR_MQ, t0);
4948 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4949 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4950 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4951 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4952 gen_set_label(l1);
4953 tcg_temp_free(t0);
4954 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4955 tcg_gen_movi_tl(cpu_ca, 0);
4956 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4957 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4958 tcg_gen_movi_tl(cpu_ca, 1);
4959 gen_set_label(l2);
4960 tcg_temp_free(t1);
4961 tcg_temp_free(t2);
4962 if (unlikely(Rc(ctx->opcode) != 0))
4963 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4964 }
4965
4966 /* sre - sre. */
4967 static void gen_sre(DisasContext *ctx)
4968 {
4969 TCGv t0 = tcg_temp_new();
4970 TCGv t1 = tcg_temp_new();
4971 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4972 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4973 tcg_gen_subfi_tl(t1, 32, t1);
4974 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4975 tcg_gen_or_tl(t1, t0, t1);
4976 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4977 gen_store_spr(SPR_MQ, t1);
4978 tcg_temp_free(t0);
4979 tcg_temp_free(t1);
4980 if (unlikely(Rc(ctx->opcode) != 0))
4981 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4982 }
4983
4984 /* srea - srea. */
4985 static void gen_srea(DisasContext *ctx)
4986 {
4987 TCGv t0 = tcg_temp_new();
4988 TCGv t1 = tcg_temp_new();
4989 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4990 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4991 gen_store_spr(SPR_MQ, t0);
4992 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4993 tcg_temp_free(t0);
4994 tcg_temp_free(t1);
4995 if (unlikely(Rc(ctx->opcode) != 0))
4996 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4997 }
4998
4999 /* sreq */
5000 static void gen_sreq(DisasContext *ctx)
5001 {
5002 TCGv t0 = tcg_temp_new();
5003 TCGv t1 = tcg_temp_new();
5004 TCGv t2 = tcg_temp_new();
5005 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5006 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5007 tcg_gen_shr_tl(t1, t1, t0);
5008 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5009 gen_load_spr(t2, SPR_MQ);
5010 gen_store_spr(SPR_MQ, t0);
5011 tcg_gen_and_tl(t0, t0, t1);
5012 tcg_gen_andc_tl(t2, t2, t1);
5013 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5014 tcg_temp_free(t0);
5015 tcg_temp_free(t1);
5016 tcg_temp_free(t2);
5017 if (unlikely(Rc(ctx->opcode) != 0))
5018 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5019 }
5020
5021 /* sriq */
5022 static void gen_sriq(DisasContext *ctx)
5023 {
5024 int sh = SH(ctx->opcode);
5025 TCGv t0 = tcg_temp_new();
5026 TCGv t1 = tcg_temp_new();
5027 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5028 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5029 tcg_gen_or_tl(t1, t0, t1);
5030 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5031 gen_store_spr(SPR_MQ, t1);
5032 tcg_temp_free(t0);
5033 tcg_temp_free(t1);
5034 if (unlikely(Rc(ctx->opcode) != 0))
5035 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5036 }
5037
5038 /* srliq */
5039 static void gen_srliq(DisasContext *ctx)
5040 {
5041 int sh = SH(ctx->opcode);
5042 TCGv t0 = tcg_temp_new();
5043 TCGv t1 = tcg_temp_new();
5044 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5045 gen_load_spr(t1, SPR_MQ);
5046 gen_store_spr(SPR_MQ, t0);
5047 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5048 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5049 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5050 tcg_temp_free(t0);
5051 tcg_temp_free(t1);
5052 if (unlikely(Rc(ctx->opcode) != 0))
5053 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5054 }
5055
5056 /* srlq */
5057 static void gen_srlq(DisasContext *ctx)
5058 {
5059 int l1 = gen_new_label();
5060 int l2 = gen_new_label();
5061 TCGv t0 = tcg_temp_local_new();
5062 TCGv t1 = tcg_temp_local_new();
5063 TCGv t2 = tcg_temp_local_new();
5064 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5065 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5066 tcg_gen_shr_tl(t2, t1, t2);
5067 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5068 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5069 gen_load_spr(t0, SPR_MQ);
5070 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5071 tcg_gen_br(l2);
5072 gen_set_label(l1);
5073 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5074 tcg_gen_and_tl(t0, t0, t2);
5075 gen_load_spr(t1, SPR_MQ);
5076 tcg_gen_andc_tl(t1, t1, t2);
5077 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5078 gen_set_label(l2);
5079 tcg_temp_free(t0);
5080 tcg_temp_free(t1);
5081 tcg_temp_free(t2);
5082 if (unlikely(Rc(ctx->opcode) != 0))
5083 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5084 }
5085
5086 /* srq */
5087 static void gen_srq(DisasContext *ctx)
5088 {
5089 int l1 = gen_new_label();
5090 TCGv t0 = tcg_temp_new();
5091 TCGv t1 = tcg_temp_new();
5092 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5093 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5094 tcg_gen_subfi_tl(t1, 32, t1);
5095 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5096 tcg_gen_or_tl(t1, t0, t1);
5097 gen_store_spr(SPR_MQ, t1);
5098 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5099 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5100 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5101 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5102 gen_set_label(l1);
5103 tcg_temp_free(t0);
5104 tcg_temp_free(t1);
5105 if (unlikely(Rc(ctx->opcode) != 0))
5106 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5107 }
5108
5109 /* PowerPC 602 specific instructions */
5110
5111 /* dsa */
5112 static void gen_dsa(DisasContext *ctx)
5113 {
5114 /* XXX: TODO */
5115 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5116 }
5117
5118 /* esa */
5119 static void gen_esa(DisasContext *ctx)
5120 {
5121 /* XXX: TODO */
5122 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5123 }
5124
5125 /* mfrom */
5126 static void gen_mfrom(DisasContext *ctx)
5127 {
5128 #if defined(CONFIG_USER_ONLY)
5129 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5130 #else
5131 if (unlikely(!ctx->mem_idx)) {
5132 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5133 return;
5134 }
5135 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5136 #endif
5137 }
5138
5139 /* 602 - 603 - G2 TLB management */
5140
5141 /* tlbld */
5142 static void gen_tlbld_6xx(DisasContext *ctx)
5143 {
5144 #if defined(CONFIG_USER_ONLY)
5145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5146 #else
5147 if (unlikely(!ctx->mem_idx)) {
5148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5149 return;
5150 }
5151 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5152 #endif
5153 }
5154
5155 /* tlbli */
5156 static void gen_tlbli_6xx(DisasContext *ctx)
5157 {
5158 #if defined(CONFIG_USER_ONLY)
5159 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5160 #else
5161 if (unlikely(!ctx->mem_idx)) {
5162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5163 return;
5164 }
5165 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5166 #endif
5167 }
5168
5169 /* 74xx TLB management */
5170
5171 /* tlbld */
5172 static void gen_tlbld_74xx(DisasContext *ctx)
5173 {
5174 #if defined(CONFIG_USER_ONLY)
5175 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5176 #else
5177 if (unlikely(!ctx->mem_idx)) {
5178 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5179 return;
5180 }
5181 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5182 #endif
5183 }
5184
5185 /* tlbli */
5186 static void gen_tlbli_74xx(DisasContext *ctx)
5187 {
5188 #if defined(CONFIG_USER_ONLY)
5189 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5190 #else
5191 if (unlikely(!ctx->mem_idx)) {
5192 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5193 return;
5194 }
5195 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5196 #endif
5197 }
5198
5199 /* POWER instructions not in PowerPC 601 */
5200
5201 /* clf */
5202 static void gen_clf(DisasContext *ctx)
5203 {
5204 /* Cache line flush: implemented as no-op */
5205 }
5206
5207 /* cli */
5208 static void gen_cli(DisasContext *ctx)
5209 {
5210 /* Cache line invalidate: privileged and treated as no-op */
5211 #if defined(CONFIG_USER_ONLY)
5212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5213 #else
5214 if (unlikely(!ctx->mem_idx)) {
5215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5216 return;
5217 }
5218 #endif
5219 }
5220
5221 /* dclst */
5222 static void gen_dclst(DisasContext *ctx)
5223 {
5224 /* Data cache line store: treated as no-op */
5225 }
5226
5227 static void gen_mfsri(DisasContext *ctx)
5228 {
5229 #if defined(CONFIG_USER_ONLY)
5230 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5231 #else
5232 int ra = rA(ctx->opcode);
5233 int rd = rD(ctx->opcode);
5234 TCGv t0;
5235 if (unlikely(!ctx->mem_idx)) {
5236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5237 return;
5238 }
5239 t0 = tcg_temp_new();
5240 gen_addr_reg_index(ctx, t0);
5241 tcg_gen_shri_tl(t0, t0, 28);
5242 tcg_gen_andi_tl(t0, t0, 0xF);
5243 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5244 tcg_temp_free(t0);
5245 if (ra != 0 && ra != rd)
5246 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5247 #endif
5248 }
5249
5250 static void gen_rac(DisasContext *ctx)
5251 {
5252 #if defined(CONFIG_USER_ONLY)
5253 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5254 #else
5255 TCGv t0;
5256 if (unlikely(!ctx->mem_idx)) {
5257 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5258 return;
5259 }
5260 t0 = tcg_temp_new();
5261 gen_addr_reg_index(ctx, t0);
5262 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5263 tcg_temp_free(t0);
5264 #endif
5265 }
5266
5267 static void gen_rfsvc(DisasContext *ctx)
5268 {
5269 #if defined(CONFIG_USER_ONLY)
5270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5271 #else
5272 if (unlikely(!ctx->mem_idx)) {
5273 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5274 return;
5275 }
5276 gen_helper_rfsvc(cpu_env);
5277 gen_sync_exception(ctx);
5278 #endif
5279 }
5280
5281 /* svc is not implemented for now */
5282
5283 /* POWER2 specific instructions */
5284 /* Quad manipulation (load/store two floats at a time) */
5285
5286 /* lfq */
5287 static void gen_lfq(DisasContext *ctx)
5288 {
5289 int rd = rD(ctx->opcode);
5290 TCGv t0;
5291 gen_set_access_type(ctx, ACCESS_FLOAT);
5292 t0 = tcg_temp_new();
5293 gen_addr_imm_index(ctx, t0, 0);
5294 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5295 gen_addr_add(ctx, t0, t0, 8);
5296 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5297 tcg_temp_free(t0);
5298 }
5299
5300 /* lfqu */
5301 static void gen_lfqu(DisasContext *ctx)
5302 {
5303 int ra = rA(ctx->opcode);
5304 int rd = rD(ctx->opcode);
5305 TCGv t0, t1;
5306 gen_set_access_type(ctx, ACCESS_FLOAT);
5307 t0 = tcg_temp_new();
5308 t1 = tcg_temp_new();
5309 gen_addr_imm_index(ctx, t0, 0);
5310 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5311 gen_addr_add(ctx, t1, t0, 8);
5312 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5313 if (ra != 0)
5314 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5315 tcg_temp_free(t0);
5316 tcg_temp_free(t1);
5317 }
5318
5319 /* lfqux */
5320 static void gen_lfqux(DisasContext *ctx)
5321 {
5322 int ra = rA(ctx->opcode);
5323 int rd = rD(ctx->opcode);
5324 gen_set_access_type(ctx, ACCESS_FLOAT);
5325 TCGv t0, t1;
5326 t0 = tcg_temp_new();
5327 gen_addr_reg_index(ctx, t0);
5328 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5329 t1 = tcg_temp_new();
5330 gen_addr_add(ctx, t1, t0, 8);
5331 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5332 tcg_temp_free(t1);
5333 if (ra != 0)
5334 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5335 tcg_temp_free(t0);
5336 }
5337
5338 /* lfqx */
5339 static void gen_lfqx(DisasContext *ctx)
5340 {
5341 int rd = rD(ctx->opcode);
5342 TCGv t0;
5343 gen_set_access_type(ctx, ACCESS_FLOAT);
5344 t0 = tcg_temp_new();
5345 gen_addr_reg_index(ctx, t0);
5346 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5347 gen_addr_add(ctx, t0, t0, 8);
5348 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5349 tcg_temp_free(t0);
5350 }
5351
5352 /* stfq */
5353 static void gen_stfq(DisasContext *ctx)
5354 {
5355 int rd = rD(ctx->opcode);
5356 TCGv t0;
5357 gen_set_access_type(ctx, ACCESS_FLOAT);
5358 t0 = tcg_temp_new();
5359 gen_addr_imm_index(ctx, t0, 0);
5360 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5361 gen_addr_add(ctx, t0, t0, 8);
5362 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5363 tcg_temp_free(t0);
5364 }
5365
5366 /* stfqu */
5367 static void gen_stfqu(DisasContext *ctx)
5368 {
5369 int ra = rA(ctx->opcode);
5370 int rd = rD(ctx->opcode);
5371 TCGv t0, t1;
5372 gen_set_access_type(ctx, ACCESS_FLOAT);
5373 t0 = tcg_temp_new();
5374 gen_addr_imm_index(ctx, t0, 0);
5375 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5376 t1 = tcg_temp_new();
5377 gen_addr_add(ctx, t1, t0, 8);
5378 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5379 tcg_temp_free(t1);
5380 if (ra != 0)
5381 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5382 tcg_temp_free(t0);
5383 }
5384
5385 /* stfqux */
5386 static void gen_stfqux(DisasContext *ctx)
5387 {
5388 int ra = rA(ctx->opcode);
5389 int rd = rD(ctx->opcode);
5390 TCGv t0, t1;
5391 gen_set_access_type(ctx, ACCESS_FLOAT);
5392 t0 = tcg_temp_new();
5393 gen_addr_reg_index(ctx, t0);
5394 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5395 t1 = tcg_temp_new();
5396 gen_addr_add(ctx, t1, t0, 8);
5397 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5398 tcg_temp_free(t1);
5399 if (ra != 0)
5400 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5401 tcg_temp_free(t0);
5402 }
5403
5404 /* stfqx */
5405 static void gen_stfqx(DisasContext *ctx)
5406 {
5407 int rd = rD(ctx->opcode);
5408 TCGv t0;
5409 gen_set_access_type(ctx, ACCESS_FLOAT);
5410 t0 = tcg_temp_new();
5411 gen_addr_reg_index(ctx, t0);
5412 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5413 gen_addr_add(ctx, t0, t0, 8);
5414 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5415 tcg_temp_free(t0);
5416 }
5417
5418 /* BookE specific instructions */
5419
5420 /* XXX: not implemented on 440 ? */
5421 static void gen_mfapidi(DisasContext *ctx)
5422 {
5423 /* XXX: TODO */
5424 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5425 }
5426
5427 /* XXX: not implemented on 440 ? */
5428 static void gen_tlbiva(DisasContext *ctx)
5429 {
5430 #if defined(CONFIG_USER_ONLY)
5431 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5432 #else
5433 TCGv t0;
5434 if (unlikely(!ctx->mem_idx)) {
5435 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5436 return;
5437 }
5438 t0 = tcg_temp_new();
5439 gen_addr_reg_index(ctx, t0);
5440 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5441 tcg_temp_free(t0);
5442 #endif
5443 }
5444
5445 /* All 405 MAC instructions are translated here */
5446 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5447 int ra, int rb, int rt, int Rc)
5448 {
5449 TCGv t0, t1;
5450
5451 t0 = tcg_temp_local_new();
5452 t1 = tcg_temp_local_new();
5453
5454 switch (opc3 & 0x0D) {
5455 case 0x05:
5456 /* macchw - macchw. - macchwo - macchwo. */
5457 /* macchws - macchws. - macchwso - macchwso. */
5458 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5459 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5460 /* mulchw - mulchw. */
5461 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5462 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5463 tcg_gen_ext16s_tl(t1, t1);
5464 break;
5465 case 0x04:
5466 /* macchwu - macchwu. - macchwuo - macchwuo. */
5467 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5468 /* mulchwu - mulchwu. */
5469 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5470 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5471 tcg_gen_ext16u_tl(t1, t1);
5472 break;
5473 case 0x01:
5474 /* machhw - machhw. - machhwo - machhwo. */
5475 /* machhws - machhws. - machhwso - machhwso. */
5476 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5477 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5478 /* mulhhw - mulhhw. */
5479 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5480 tcg_gen_ext16s_tl(t0, t0);
5481 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5482 tcg_gen_ext16s_tl(t1, t1);
5483 break;
5484 case 0x00:
5485 /* machhwu - machhwu. - machhwuo - machhwuo. */
5486 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5487 /* mulhhwu - mulhhwu. */
5488 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5489 tcg_gen_ext16u_tl(t0, t0);
5490 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5491 tcg_gen_ext16u_tl(t1, t1);
5492 break;
5493 case 0x0D:
5494 /* maclhw - maclhw. - maclhwo - maclhwo. */
5495 /* maclhws - maclhws. - maclhwso - maclhwso. */
5496 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5497 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5498 /* mullhw - mullhw. */
5499 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5500 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5501 break;
5502 case 0x0C:
5503 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5504 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5505 /* mullhwu - mullhwu. */
5506 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5507 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5508 break;
5509 }
5510 if (opc2 & 0x04) {
5511 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5512 tcg_gen_mul_tl(t1, t0, t1);
5513 if (opc2 & 0x02) {
5514 /* nmultiply-and-accumulate (0x0E) */
5515 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5516 } else {
5517 /* multiply-and-accumulate (0x0C) */
5518 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5519 }
5520
5521 if (opc3 & 0x12) {
5522 /* Check overflow and/or saturate */
5523 int l1 = gen_new_label();
5524
5525 if (opc3 & 0x10) {
5526 /* Start with XER OV disabled, the most likely case */
5527 tcg_gen_movi_tl(cpu_ov, 0);
5528 }
5529 if (opc3 & 0x01) {
5530 /* Signed */
5531 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5532 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5533 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5534 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5535 if (opc3 & 0x02) {
5536 /* Saturate */
5537 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5538 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5539 }
5540 } else {
5541 /* Unsigned */
5542 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5543 if (opc3 & 0x02) {
5544 /* Saturate */
5545 tcg_gen_movi_tl(t0, UINT32_MAX);
5546 }
5547 }
5548 if (opc3 & 0x10) {
5549 /* Check overflow */
5550 tcg_gen_movi_tl(cpu_ov, 1);
5551 tcg_gen_movi_tl(cpu_so, 1);
5552 }
5553 gen_set_label(l1);
5554 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5555 }
5556 } else {
5557 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5558 }
5559 tcg_temp_free(t0);
5560 tcg_temp_free(t1);
5561 if (unlikely(Rc) != 0) {
5562 /* Update Rc0 */
5563 gen_set_Rc0(ctx, cpu_gpr[rt]);
5564 }
5565 }
5566
5567 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5568 static void glue(gen_, name)(DisasContext *ctx) \
5569 { \
5570 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5571 rD(ctx->opcode), Rc(ctx->opcode)); \
5572 }
5573
5574 /* macchw - macchw. */
5575 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5576 /* macchwo - macchwo. */
5577 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5578 /* macchws - macchws. */
5579 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5580 /* macchwso - macchwso. */
5581 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5582 /* macchwsu - macchwsu. */
5583 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5584 /* macchwsuo - macchwsuo. */
5585 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5586 /* macchwu - macchwu. */
5587 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5588 /* macchwuo - macchwuo. */
5589 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5590 /* machhw - machhw. */
5591 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5592 /* machhwo - machhwo. */
5593 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5594 /* machhws - machhws. */
5595 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5596 /* machhwso - machhwso. */
5597 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5598 /* machhwsu - machhwsu. */
5599 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5600 /* machhwsuo - machhwsuo. */
5601 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5602 /* machhwu - machhwu. */
5603 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5604 /* machhwuo - machhwuo. */
5605 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5606 /* maclhw - maclhw. */
5607 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5608 /* maclhwo - maclhwo. */
5609 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5610 /* maclhws - maclhws. */
5611 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5612 /* maclhwso - maclhwso. */
5613 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5614 /* maclhwu - maclhwu. */
5615 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5616 /* maclhwuo - maclhwuo. */
5617 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5618 /* maclhwsu - maclhwsu. */
5619 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5620 /* maclhwsuo - maclhwsuo. */
5621 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5622 /* nmacchw - nmacchw. */
5623 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5624 /* nmacchwo - nmacchwo. */
5625 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5626 /* nmacchws - nmacchws. */
5627 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5628 /* nmacchwso - nmacchwso. */
5629 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5630 /* nmachhw - nmachhw. */
5631 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5632 /* nmachhwo - nmachhwo. */
5633 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5634 /* nmachhws - nmachhws. */
5635 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5636 /* nmachhwso - nmachhwso. */
5637 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5638 /* nmaclhw - nmaclhw. */
5639 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5640 /* nmaclhwo - nmaclhwo. */
5641 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5642 /* nmaclhws - nmaclhws. */
5643 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5644 /* nmaclhwso - nmaclhwso. */
5645 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5646
5647 /* mulchw - mulchw. */
5648 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5649 /* mulchwu - mulchwu. */
5650 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5651 /* mulhhw - mulhhw. */
5652 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5653 /* mulhhwu - mulhhwu. */
5654 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5655 /* mullhw - mullhw. */
5656 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5657 /* mullhwu - mullhwu. */
5658 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5659
5660 /* mfdcr */
5661 static void gen_mfdcr(DisasContext *ctx)
5662 {
5663 #if defined(CONFIG_USER_ONLY)
5664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5665 #else
5666 TCGv dcrn;
5667 if (unlikely(!ctx->mem_idx)) {
5668 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5669 return;
5670 }
5671 /* NIP cannot be restored if the memory exception comes from an helper */
5672 gen_update_nip(ctx, ctx->nip - 4);
5673 dcrn = tcg_const_tl(SPR(ctx->opcode));
5674 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5675 tcg_temp_free(dcrn);
5676 #endif
5677 }
5678
5679 /* mtdcr */
5680 static void gen_mtdcr(DisasContext *ctx)
5681 {
5682 #if defined(CONFIG_USER_ONLY)
5683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5684 #else
5685 TCGv dcrn;
5686 if (unlikely(!ctx->mem_idx)) {
5687 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5688 return;
5689 }
5690 /* NIP cannot be restored if the memory exception comes from an helper */
5691 gen_update_nip(ctx, ctx->nip - 4);
5692 dcrn = tcg_const_tl(SPR(ctx->opcode));
5693 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5694 tcg_temp_free(dcrn);
5695 #endif
5696 }
5697
5698 /* mfdcrx */
5699 /* XXX: not implemented on 440 ? */
5700 static void gen_mfdcrx(DisasContext *ctx)
5701 {
5702 #if defined(CONFIG_USER_ONLY)
5703 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5704 #else
5705 if (unlikely(!ctx->mem_idx)) {
5706 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5707 return;
5708 }
5709 /* NIP cannot be restored if the memory exception comes from an helper */
5710 gen_update_nip(ctx, ctx->nip - 4);
5711 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5712 cpu_gpr[rA(ctx->opcode)]);
5713 /* Note: Rc update flag set leads to undefined state of Rc0 */
5714 #endif
5715 }
5716
5717 /* mtdcrx */
5718 /* XXX: not implemented on 440 ? */
5719 static void gen_mtdcrx(DisasContext *ctx)
5720 {
5721 #if defined(CONFIG_USER_ONLY)
5722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5723 #else
5724 if (unlikely(!ctx->mem_idx)) {
5725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5726 return;
5727 }
5728 /* NIP cannot be restored if the memory exception comes from an helper */
5729 gen_update_nip(ctx, ctx->nip - 4);
5730 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5731 cpu_gpr[rS(ctx->opcode)]);
5732 /* Note: Rc update flag set leads to undefined state of Rc0 */
5733 #endif
5734 }
5735
5736 /* mfdcrux (PPC 460) : user-mode access to DCR */
5737 static void gen_mfdcrux(DisasContext *ctx)
5738 {
5739 /* NIP cannot be restored if the memory exception comes from an helper */
5740 gen_update_nip(ctx, ctx->nip - 4);
5741 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5742 cpu_gpr[rA(ctx->opcode)]);
5743 /* Note: Rc update flag set leads to undefined state of Rc0 */
5744 }
5745
5746 /* mtdcrux (PPC 460) : user-mode access to DCR */
5747 static void gen_mtdcrux(DisasContext *ctx)
5748 {
5749 /* NIP cannot be restored if the memory exception comes from an helper */
5750 gen_update_nip(ctx, ctx->nip - 4);
5751 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5752 cpu_gpr[rS(ctx->opcode)]);
5753 /* Note: Rc update flag set leads to undefined state of Rc0 */
5754 }
5755
5756 /* dccci */
5757 static void gen_dccci(DisasContext *ctx)
5758 {
5759 #if defined(CONFIG_USER_ONLY)
5760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5761 #else
5762 if (unlikely(!ctx->mem_idx)) {
5763 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5764 return;
5765 }
5766 /* interpreted as no-op */
5767 #endif
5768 }
5769
5770 /* dcread */
5771 static void gen_dcread(DisasContext *ctx)
5772 {
5773 #if defined(CONFIG_USER_ONLY)
5774 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5775 #else
5776 TCGv EA, val;
5777 if (unlikely(!ctx->mem_idx)) {
5778 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5779 return;
5780 }
5781 gen_set_access_type(ctx, ACCESS_CACHE);
5782 EA = tcg_temp_new();
5783 gen_addr_reg_index(ctx, EA);
5784 val = tcg_temp_new();
5785 gen_qemu_ld32u(ctx, val, EA);
5786 tcg_temp_free(val);
5787 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5788 tcg_temp_free(EA);
5789 #endif
5790 }
5791
5792 /* icbt */
5793 static void gen_icbt_40x(DisasContext *ctx)
5794 {
5795 /* interpreted as no-op */
5796 /* XXX: specification say this is treated as a load by the MMU
5797 * but does not generate any exception
5798 */
5799 }
5800
5801 /* iccci */
5802 static void gen_iccci(DisasContext *ctx)
5803 {
5804 #if defined(CONFIG_USER_ONLY)
5805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5806 #else
5807 if (unlikely(!ctx->mem_idx)) {
5808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5809 return;
5810 }
5811 /* interpreted as no-op */
5812 #endif
5813 }
5814
5815 /* icread */
5816 static void gen_icread(DisasContext *ctx)
5817 {
5818 #if defined(CONFIG_USER_ONLY)
5819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5820 #else
5821 if (unlikely(!ctx->mem_idx)) {
5822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5823 return;
5824 }
5825 /* interpreted as no-op */
5826 #endif
5827 }
5828
5829 /* rfci (mem_idx only) */
5830 static void gen_rfci_40x(DisasContext *ctx)
5831 {
5832 #if defined(CONFIG_USER_ONLY)
5833 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5834 #else
5835 if (unlikely(!ctx->mem_idx)) {
5836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5837 return;
5838 }
5839 /* Restore CPU state */
5840 gen_helper_40x_rfci(cpu_env);
5841 gen_sync_exception(ctx);
5842 #endif
5843 }
5844
5845 static void gen_rfci(DisasContext *ctx)
5846 {
5847 #if defined(CONFIG_USER_ONLY)
5848 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5849 #else
5850 if (unlikely(!ctx->mem_idx)) {
5851 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5852 return;
5853 }
5854 /* Restore CPU state */
5855 gen_helper_rfci(cpu_env);
5856 gen_sync_exception(ctx);
5857 #endif
5858 }
5859
5860 /* BookE specific */
5861
5862 /* XXX: not implemented on 440 ? */
5863 static void gen_rfdi(DisasContext *ctx)
5864 {
5865 #if defined(CONFIG_USER_ONLY)
5866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5867 #else
5868 if (unlikely(!ctx->mem_idx)) {
5869 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5870 return;
5871 }
5872 /* Restore CPU state */
5873 gen_helper_rfdi(cpu_env);
5874 gen_sync_exception(ctx);
5875 #endif
5876 }
5877
5878 /* XXX: not implemented on 440 ? */
5879 static void gen_rfmci(DisasContext *ctx)
5880 {
5881 #if defined(CONFIG_USER_ONLY)
5882 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5883 #else
5884 if (unlikely(!ctx->mem_idx)) {
5885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5886 return;
5887 }
5888 /* Restore CPU state */
5889 gen_helper_rfmci(cpu_env);
5890 gen_sync_exception(ctx);
5891 #endif
5892 }
5893
5894 /* TLB management - PowerPC 405 implementation */
5895
5896 /* tlbre */
5897 static void gen_tlbre_40x(DisasContext *ctx)
5898 {
5899 #if defined(CONFIG_USER_ONLY)
5900 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5901 #else
5902 if (unlikely(!ctx->mem_idx)) {
5903 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5904 return;
5905 }
5906 switch (rB(ctx->opcode)) {
5907 case 0:
5908 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5909 cpu_gpr[rA(ctx->opcode)]);
5910 break;
5911 case 1:
5912 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5913 cpu_gpr[rA(ctx->opcode)]);
5914 break;
5915 default:
5916 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5917 break;
5918 }
5919 #endif
5920 }
5921
5922 /* tlbsx - tlbsx. */
5923 static void gen_tlbsx_40x(DisasContext *ctx)
5924 {
5925 #if defined(CONFIG_USER_ONLY)
5926 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5927 #else
5928 TCGv t0;
5929 if (unlikely(!ctx->mem_idx)) {
5930 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5931 return;
5932 }
5933 t0 = tcg_temp_new();
5934 gen_addr_reg_index(ctx, t0);
5935 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5936 tcg_temp_free(t0);
5937 if (Rc(ctx->opcode)) {
5938 int l1 = gen_new_label();
5939 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5940 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5941 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5942 gen_set_label(l1);
5943 }
5944 #endif
5945 }
5946
5947 /* tlbwe */
5948 static void gen_tlbwe_40x(DisasContext *ctx)
5949 {
5950 #if defined(CONFIG_USER_ONLY)
5951 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5952 #else
5953 if (unlikely(!ctx->mem_idx)) {
5954 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5955 return;
5956 }
5957 switch (rB(ctx->opcode)) {
5958 case 0:
5959 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5960 cpu_gpr[rS(ctx->opcode)]);
5961 break;
5962 case 1:
5963 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5964 cpu_gpr[rS(ctx->opcode)]);
5965 break;
5966 default:
5967 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5968 break;
5969 }
5970 #endif
5971 }
5972
5973 /* TLB management - PowerPC 440 implementation */
5974
5975 /* tlbre */
5976 static void gen_tlbre_440(DisasContext *ctx)
5977 {
5978 #if defined(CONFIG_USER_ONLY)
5979 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5980 #else
5981 if (unlikely(!ctx->mem_idx)) {
5982 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5983 return;
5984 }
5985 switch (rB(ctx->opcode)) {
5986 case 0:
5987 case 1:
5988 case 2:
5989 {
5990 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5991 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5992 t0, cpu_gpr[rA(ctx->opcode)]);
5993 tcg_temp_free_i32(t0);
5994 }
5995 break;
5996 default:
5997 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5998 break;
5999 }
6000 #endif
6001 }
6002
6003 /* tlbsx - tlbsx. */
6004 static void gen_tlbsx_440(DisasContext *ctx)
6005 {
6006 #if defined(CONFIG_USER_ONLY)
6007 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6008 #else
6009 TCGv t0;
6010 if (unlikely(!ctx->mem_idx)) {
6011 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6012 return;
6013 }
6014 t0 = tcg_temp_new();
6015 gen_addr_reg_index(ctx, t0);
6016 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6017 tcg_temp_free(t0);
6018 if (Rc(ctx->opcode)) {
6019 int l1 = gen_new_label();
6020 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6021 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6022 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6023 gen_set_label(l1);
6024 }
6025 #endif
6026 }
6027
6028 /* tlbwe */
6029 static void gen_tlbwe_440(DisasContext *ctx)
6030 {
6031 #if defined(CONFIG_USER_ONLY)
6032 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6033 #else
6034 if (unlikely(!ctx->mem_idx)) {
6035 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6036 return;
6037 }
6038 switch (rB(ctx->opcode)) {
6039 case 0:
6040 case 1:
6041 case 2:
6042 {
6043 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6044 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6045 cpu_gpr[rS(ctx->opcode)]);
6046 tcg_temp_free_i32(t0);
6047 }
6048 break;
6049 default:
6050 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6051 break;
6052 }
6053 #endif
6054 }
6055
6056 /* TLB management - PowerPC BookE 2.06 implementation */
6057
6058 /* tlbre */
6059 static void gen_tlbre_booke206(DisasContext *ctx)
6060 {
6061 #if defined(CONFIG_USER_ONLY)
6062 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6063 #else
6064 if (unlikely(!ctx->mem_idx)) {
6065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6066 return;
6067 }
6068
6069 gen_helper_booke206_tlbre(cpu_env);
6070 #endif
6071 }
6072
6073 /* tlbsx - tlbsx. */
6074 static void gen_tlbsx_booke206(DisasContext *ctx)
6075 {
6076 #if defined(CONFIG_USER_ONLY)
6077 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6078 #else
6079 TCGv t0;
6080 if (unlikely(!ctx->mem_idx)) {
6081 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6082 return;
6083 }
6084
6085 if (rA(ctx->opcode)) {
6086 t0 = tcg_temp_new();
6087 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6088 } else {
6089 t0 = tcg_const_tl(0);
6090 }
6091
6092 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6093 gen_helper_booke206_tlbsx(cpu_env, t0);
6094 #endif
6095 }
6096
6097 /* tlbwe */
6098 static void gen_tlbwe_booke206(DisasContext *ctx)
6099 {
6100 #if defined(CONFIG_USER_ONLY)
6101 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6102 #else
6103 if (unlikely(!ctx->mem_idx)) {
6104 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6105 return;
6106 }
6107 gen_update_nip(ctx, ctx->nip - 4);
6108 gen_helper_booke206_tlbwe(cpu_env);
6109 #endif
6110 }
6111
6112 static void gen_tlbivax_booke206(DisasContext *ctx)
6113 {
6114 #if defined(CONFIG_USER_ONLY)
6115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6116 #else
6117 TCGv t0;
6118 if (unlikely(!ctx->mem_idx)) {
6119 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6120 return;
6121 }
6122
6123 t0 = tcg_temp_new();
6124 gen_addr_reg_index(ctx, t0);
6125
6126 gen_helper_booke206_tlbivax(cpu_env, t0);
6127 #endif
6128 }
6129
6130 static void gen_tlbilx_booke206(DisasContext *ctx)
6131 {
6132 #if defined(CONFIG_USER_ONLY)
6133 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6134 #else
6135 TCGv t0;
6136 if (unlikely(!ctx->mem_idx)) {
6137 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6138 return;
6139 }
6140
6141 t0 = tcg_temp_new();
6142 gen_addr_reg_index(ctx, t0);
6143
6144 switch((ctx->opcode >> 21) & 0x3) {
6145 case 0:
6146 gen_helper_booke206_tlbilx0(cpu_env, t0);
6147 break;
6148 case 1:
6149 gen_helper_booke206_tlbilx1(cpu_env, t0);
6150 break;
6151 case 3:
6152 gen_helper_booke206_tlbilx3(cpu_env, t0);
6153 break;
6154 default:
6155 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6156 break;
6157 }
6158
6159 tcg_temp_free(t0);
6160 #endif
6161 }
6162
6163
6164 /* wrtee */
6165 static void gen_wrtee(DisasContext *ctx)
6166 {
6167 #if defined(CONFIG_USER_ONLY)
6168 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6169 #else
6170 TCGv t0;
6171 if (unlikely(!ctx->mem_idx)) {
6172 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6173 return;
6174 }
6175 t0 = tcg_temp_new();
6176 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6177 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6178 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6179 tcg_temp_free(t0);
6180 /* Stop translation to have a chance to raise an exception
6181 * if we just set msr_ee to 1
6182 */
6183 gen_stop_exception(ctx);
6184 #endif
6185 }
6186
6187 /* wrteei */
6188 static void gen_wrteei(DisasContext *ctx)
6189 {
6190 #if defined(CONFIG_USER_ONLY)
6191 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6192 #else
6193 if (unlikely(!ctx->mem_idx)) {
6194 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6195 return;
6196 }
6197 if (ctx->opcode & 0x00008000) {
6198 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6199 /* Stop translation to have a chance to raise an exception */
6200 gen_stop_exception(ctx);
6201 } else {
6202 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6203 }
6204 #endif
6205 }
6206
6207 /* PowerPC 440 specific instructions */
6208
6209 /* dlmzb */
6210 static void gen_dlmzb(DisasContext *ctx)
6211 {
6212 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6213 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6214 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6215 tcg_temp_free_i32(t0);
6216 }
6217
6218 /* mbar replaces eieio on 440 */
6219 static void gen_mbar(DisasContext *ctx)
6220 {
6221 /* interpreted as no-op */
6222 }
6223
6224 /* msync replaces sync on 440 */
6225 static void gen_msync_4xx(DisasContext *ctx)
6226 {
6227 /* interpreted as no-op */
6228 }
6229
6230 /* icbt */
6231 static void gen_icbt_440(DisasContext *ctx)
6232 {
6233 /* interpreted as no-op */
6234 /* XXX: specification say this is treated as a load by the MMU
6235 * but does not generate any exception
6236 */
6237 }
6238
6239 /* Embedded.Processor Control */
6240
6241 static void gen_msgclr(DisasContext *ctx)
6242 {
6243 #if defined(CONFIG_USER_ONLY)
6244 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6245 #else
6246 if (unlikely(ctx->mem_idx == 0)) {
6247 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6248 return;
6249 }
6250
6251 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6252 #endif
6253 }
6254
6255 static void gen_msgsnd(DisasContext *ctx)
6256 {
6257 #if defined(CONFIG_USER_ONLY)
6258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6259 #else
6260 if (unlikely(ctx->mem_idx == 0)) {
6261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6262 return;
6263 }
6264
6265 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6266 #endif
6267 }
6268
6269 /*** Altivec vector extension ***/
6270 /* Altivec registers moves */
6271
6272 static inline TCGv_ptr gen_avr_ptr(int reg)
6273 {
6274 TCGv_ptr r = tcg_temp_new_ptr();
6275 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6276 return r;
6277 }
6278
6279 #define GEN_VR_LDX(name, opc2, opc3) \
6280 static void glue(gen_, name)(DisasContext *ctx) \
6281 { \
6282 TCGv EA; \
6283 if (unlikely(!ctx->altivec_enabled)) { \
6284 gen_exception(ctx, POWERPC_EXCP_VPU); \
6285 return; \
6286 } \
6287 gen_set_access_type(ctx, ACCESS_INT); \
6288 EA = tcg_temp_new(); \
6289 gen_addr_reg_index(ctx, EA); \
6290 tcg_gen_andi_tl(EA, EA, ~0xf); \
6291 if (ctx->le_mode) { \
6292 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6293 tcg_gen_addi_tl(EA, EA, 8); \
6294 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6295 } else { \
6296 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6297 tcg_gen_addi_tl(EA, EA, 8); \
6298 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6299 } \
6300 tcg_temp_free(EA); \
6301 }
6302
6303 #define GEN_VR_STX(name, opc2, opc3) \
6304 static void gen_st##name(DisasContext *ctx) \
6305 { \
6306 TCGv EA; \
6307 if (unlikely(!ctx->altivec_enabled)) { \
6308 gen_exception(ctx, POWERPC_EXCP_VPU); \
6309 return; \
6310 } \
6311 gen_set_access_type(ctx, ACCESS_INT); \
6312 EA = tcg_temp_new(); \
6313 gen_addr_reg_index(ctx, EA); \
6314 tcg_gen_andi_tl(EA, EA, ~0xf); \
6315 if (ctx->le_mode) { \
6316 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6317 tcg_gen_addi_tl(EA, EA, 8); \
6318 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6319 } else { \
6320 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6321 tcg_gen_addi_tl(EA, EA, 8); \
6322 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6323 } \
6324 tcg_temp_free(EA); \
6325 }
6326
6327 #define GEN_VR_LVE(name, opc2, opc3) \
6328 static void gen_lve##name(DisasContext *ctx) \
6329 { \
6330 TCGv EA; \
6331 TCGv_ptr rs; \
6332 if (unlikely(!ctx->altivec_enabled)) { \
6333 gen_exception(ctx, POWERPC_EXCP_VPU); \
6334 return; \
6335 } \
6336 gen_set_access_type(ctx, ACCESS_INT); \
6337 EA = tcg_temp_new(); \
6338 gen_addr_reg_index(ctx, EA); \
6339 rs = gen_avr_ptr(rS(ctx->opcode)); \
6340 gen_helper_lve##name(cpu_env, rs, EA); \
6341 tcg_temp_free(EA); \
6342 tcg_temp_free_ptr(rs); \
6343 }
6344
6345 #define GEN_VR_STVE(name, opc2, opc3) \
6346 static void gen_stve##name(DisasContext *ctx) \
6347 { \
6348 TCGv EA; \
6349 TCGv_ptr rs; \
6350 if (unlikely(!ctx->altivec_enabled)) { \
6351 gen_exception(ctx, POWERPC_EXCP_VPU); \
6352 return; \
6353 } \
6354 gen_set_access_type(ctx, ACCESS_INT); \
6355 EA = tcg_temp_new(); \
6356 gen_addr_reg_index(ctx, EA); \
6357 rs = gen_avr_ptr(rS(ctx->opcode)); \
6358 gen_helper_stve##name(cpu_env, rs, EA); \
6359 tcg_temp_free(EA); \
6360 tcg_temp_free_ptr(rs); \
6361 }
6362
6363 GEN_VR_LDX(lvx, 0x07, 0x03);
6364 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6365 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6366
6367 GEN_VR_LVE(bx, 0x07, 0x00);
6368 GEN_VR_LVE(hx, 0x07, 0x01);
6369 GEN_VR_LVE(wx, 0x07, 0x02);
6370
6371 GEN_VR_STX(svx, 0x07, 0x07);
6372 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6373 GEN_VR_STX(svxl, 0x07, 0x0F);
6374
6375 GEN_VR_STVE(bx, 0x07, 0x04);
6376 GEN_VR_STVE(hx, 0x07, 0x05);
6377 GEN_VR_STVE(wx, 0x07, 0x06);
6378
6379 static void gen_lvsl(DisasContext *ctx)
6380 {
6381 TCGv_ptr rd;
6382 TCGv EA;
6383 if (unlikely(!ctx->altivec_enabled)) {
6384 gen_exception(ctx, POWERPC_EXCP_VPU);
6385 return;
6386 }
6387 EA = tcg_temp_new();
6388 gen_addr_reg_index(ctx, EA);
6389 rd = gen_avr_ptr(rD(ctx->opcode));
6390 gen_helper_lvsl(rd, EA);
6391 tcg_temp_free(EA);
6392 tcg_temp_free_ptr(rd);
6393 }
6394
6395 static void gen_lvsr(DisasContext *ctx)
6396 {
6397 TCGv_ptr rd;
6398 TCGv EA;
6399 if (unlikely(!ctx->altivec_enabled)) {
6400 gen_exception(ctx, POWERPC_EXCP_VPU);
6401 return;
6402 }
6403 EA = tcg_temp_new();
6404 gen_addr_reg_index(ctx, EA);
6405 rd = gen_avr_ptr(rD(ctx->opcode));
6406 gen_helper_lvsr(rd, EA);
6407 tcg_temp_free(EA);
6408 tcg_temp_free_ptr(rd);
6409 }
6410
6411 static void gen_mfvscr(DisasContext *ctx)
6412 {
6413 TCGv_i32 t;
6414 if (unlikely(!ctx->altivec_enabled)) {
6415 gen_exception(ctx, POWERPC_EXCP_VPU);
6416 return;
6417 }
6418 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6419 t = tcg_temp_new_i32();
6420 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6421 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6422 tcg_temp_free_i32(t);
6423 }
6424
6425 static void gen_mtvscr(DisasContext *ctx)
6426 {
6427 TCGv_ptr p;
6428 if (unlikely(!ctx->altivec_enabled)) {
6429 gen_exception(ctx, POWERPC_EXCP_VPU);
6430 return;
6431 }
6432 p = gen_avr_ptr(rD(ctx->opcode));
6433 gen_helper_mtvscr(cpu_env, p);
6434 tcg_temp_free_ptr(p);
6435 }
6436
6437 /* Logical operations */
6438 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6439 static void glue(gen_, name)(DisasContext *ctx) \
6440 { \
6441 if (unlikely(!ctx->altivec_enabled)) { \
6442 gen_exception(ctx, POWERPC_EXCP_VPU); \
6443 return; \
6444 } \
6445 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6446 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6447 }
6448
6449 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6450 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6451 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6452 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6453 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6454
6455 #define GEN_VXFORM(name, opc2, opc3) \
6456 static void glue(gen_, name)(DisasContext *ctx) \
6457 { \
6458 TCGv_ptr ra, rb, rd; \
6459 if (unlikely(!ctx->altivec_enabled)) { \
6460 gen_exception(ctx, POWERPC_EXCP_VPU); \
6461 return; \
6462 } \
6463 ra = gen_avr_ptr(rA(ctx->opcode)); \
6464 rb = gen_avr_ptr(rB(ctx->opcode)); \
6465 rd = gen_avr_ptr(rD(ctx->opcode)); \
6466 gen_helper_##name (rd, ra, rb); \
6467 tcg_temp_free_ptr(ra); \
6468 tcg_temp_free_ptr(rb); \
6469 tcg_temp_free_ptr(rd); \
6470 }
6471
6472 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6473 static void glue(gen_, name)(DisasContext *ctx) \
6474 { \
6475 TCGv_ptr ra, rb, rd; \
6476 if (unlikely(!ctx->altivec_enabled)) { \
6477 gen_exception(ctx, POWERPC_EXCP_VPU); \
6478 return; \
6479 } \
6480 ra = gen_avr_ptr(rA(ctx->opcode)); \
6481 rb = gen_avr_ptr(rB(ctx->opcode)); \
6482 rd = gen_avr_ptr(rD(ctx->opcode)); \
6483 gen_helper_##name(cpu_env, rd, ra, rb); \
6484 tcg_temp_free_ptr(ra); \
6485 tcg_temp_free_ptr(rb); \
6486 tcg_temp_free_ptr(rd); \
6487 }
6488
6489 GEN_VXFORM(vaddubm, 0, 0);
6490 GEN_VXFORM(vadduhm, 0, 1);
6491 GEN_VXFORM(vadduwm, 0, 2);
6492 GEN_VXFORM(vsububm, 0, 16);
6493 GEN_VXFORM(vsubuhm, 0, 17);
6494 GEN_VXFORM(vsubuwm, 0, 18);
6495 GEN_VXFORM(vmaxub, 1, 0);
6496 GEN_VXFORM(vmaxuh, 1, 1);
6497 GEN_VXFORM(vmaxuw, 1, 2);
6498 GEN_VXFORM(vmaxsb, 1, 4);
6499 GEN_VXFORM(vmaxsh, 1, 5);
6500 GEN_VXFORM(vmaxsw, 1, 6);
6501 GEN_VXFORM(vminub, 1, 8);
6502 GEN_VXFORM(vminuh, 1, 9);
6503 GEN_VXFORM(vminuw, 1, 10);
6504 GEN_VXFORM(vminsb, 1, 12);
6505 GEN_VXFORM(vminsh, 1, 13);
6506 GEN_VXFORM(vminsw, 1, 14);
6507 GEN_VXFORM(vavgub, 1, 16);
6508 GEN_VXFORM(vavguh, 1, 17);
6509 GEN_VXFORM(vavguw, 1, 18);
6510 GEN_VXFORM(vavgsb, 1, 20);
6511 GEN_VXFORM(vavgsh, 1, 21);
6512 GEN_VXFORM(vavgsw, 1, 22);
6513 GEN_VXFORM(vmrghb, 6, 0);
6514 GEN_VXFORM(vmrghh, 6, 1);
6515 GEN_VXFORM(vmrghw, 6, 2);
6516 GEN_VXFORM(vmrglb, 6, 4);
6517 GEN_VXFORM(vmrglh, 6, 5);
6518 GEN_VXFORM(vmrglw, 6, 6);
6519 GEN_VXFORM(vmuloub, 4, 0);
6520 GEN_VXFORM(vmulouh, 4, 1);
6521 GEN_VXFORM(vmulosb, 4, 4);
6522 GEN_VXFORM(vmulosh, 4, 5);
6523 GEN_VXFORM(vmuleub, 4, 8);
6524 GEN_VXFORM(vmuleuh, 4, 9);
6525 GEN_VXFORM(vmulesb, 4, 12);
6526 GEN_VXFORM(vmulesh, 4, 13);
6527 GEN_VXFORM(vslb, 2, 4);
6528 GEN_VXFORM(vslh, 2, 5);
6529 GEN_VXFORM(vslw, 2, 6);
6530 GEN_VXFORM(vsrb, 2, 8);
6531 GEN_VXFORM(vsrh, 2, 9);
6532 GEN_VXFORM(vsrw, 2, 10);
6533 GEN_VXFORM(vsrab, 2, 12);
6534 GEN_VXFORM(vsrah, 2, 13);
6535 GEN_VXFORM(vsraw, 2, 14);
6536 GEN_VXFORM(vslo, 6, 16);
6537 GEN_VXFORM(vsro, 6, 17);
6538 GEN_VXFORM(vaddcuw, 0, 6);
6539 GEN_VXFORM(vsubcuw, 0, 22);
6540 GEN_VXFORM_ENV(vaddubs, 0, 8);
6541 GEN_VXFORM_ENV(vadduhs, 0, 9);
6542 GEN_VXFORM_ENV(vadduws, 0, 10);
6543 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6544 GEN_VXFORM_ENV(vaddshs, 0, 13);
6545 GEN_VXFORM_ENV(vaddsws, 0, 14);
6546 GEN_VXFORM_ENV(vsububs, 0, 24);
6547 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6548 GEN_VXFORM_ENV(vsubuws, 0, 26);
6549 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6550 GEN_VXFORM_ENV(vsubshs, 0, 29);
6551 GEN_VXFORM_ENV(vsubsws, 0, 30);
6552 GEN_VXFORM(vrlb, 2, 0);
6553 GEN_VXFORM(vrlh, 2, 1);
6554 GEN_VXFORM(vrlw, 2, 2);
6555 GEN_VXFORM(vsl, 2, 7);
6556 GEN_VXFORM(vsr, 2, 11);
6557 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6558 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6559 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6560 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6561 GEN_VXFORM_ENV(vpkshus, 7, 4);
6562 GEN_VXFORM_ENV(vpkswus, 7, 5);
6563 GEN_VXFORM_ENV(vpkshss, 7, 6);
6564 GEN_VXFORM_ENV(vpkswss, 7, 7);
6565 GEN_VXFORM(vpkpx, 7, 12);
6566 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6567 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6568 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6569 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6570 GEN_VXFORM_ENV(vsumsws, 4, 30);
6571 GEN_VXFORM_ENV(vaddfp, 5, 0);
6572 GEN_VXFORM_ENV(vsubfp, 5, 1);
6573 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6574 GEN_VXFORM_ENV(vminfp, 5, 17);
6575
6576 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6577 static void glue(gen_, name)(DisasContext *ctx) \
6578 { \
6579 TCGv_ptr ra, rb, rd; \
6580 if (unlikely(!ctx->altivec_enabled)) { \
6581 gen_exception(ctx, POWERPC_EXCP_VPU); \
6582 return; \
6583 } \
6584 ra = gen_avr_ptr(rA(ctx->opcode)); \
6585 rb = gen_avr_ptr(rB(ctx->opcode)); \
6586 rd = gen_avr_ptr(rD(ctx->opcode)); \
6587 gen_helper_##opname(cpu_env, rd, ra, rb); \
6588 tcg_temp_free_ptr(ra); \
6589 tcg_temp_free_ptr(rb); \
6590 tcg_temp_free_ptr(rd); \
6591 }
6592
6593 #define GEN_VXRFORM(name, opc2, opc3) \
6594 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6595 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6596
6597 GEN_VXRFORM(vcmpequb, 3, 0)
6598 GEN_VXRFORM(vcmpequh, 3, 1)
6599 GEN_VXRFORM(vcmpequw, 3, 2)
6600 GEN_VXRFORM(vcmpgtsb, 3, 12)
6601 GEN_VXRFORM(vcmpgtsh, 3, 13)
6602 GEN_VXRFORM(vcmpgtsw, 3, 14)
6603 GEN_VXRFORM(vcmpgtub, 3, 8)
6604 GEN_VXRFORM(vcmpgtuh, 3, 9)
6605 GEN_VXRFORM(vcmpgtuw, 3, 10)
6606 GEN_VXRFORM(vcmpeqfp, 3, 3)
6607 GEN_VXRFORM(vcmpgefp, 3, 7)
6608 GEN_VXRFORM(vcmpgtfp, 3, 11)
6609 GEN_VXRFORM(vcmpbfp, 3, 15)
6610
6611 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6612 static void glue(gen_, name)(DisasContext *ctx) \
6613 { \
6614 TCGv_ptr rd; \
6615 TCGv_i32 simm; \
6616 if (unlikely(!ctx->altivec_enabled)) { \
6617 gen_exception(ctx, POWERPC_EXCP_VPU); \
6618 return; \
6619 } \
6620 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6621 rd = gen_avr_ptr(rD(ctx->opcode)); \
6622 gen_helper_##name (rd, simm); \
6623 tcg_temp_free_i32(simm); \
6624 tcg_temp_free_ptr(rd); \
6625 }
6626
6627 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6628 GEN_VXFORM_SIMM(vspltish, 6, 13);
6629 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6630
6631 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6632 static void glue(gen_, name)(DisasContext *ctx) \
6633 { \
6634 TCGv_ptr rb, rd; \
6635 if (unlikely(!ctx->altivec_enabled)) { \
6636 gen_exception(ctx, POWERPC_EXCP_VPU); \
6637 return; \
6638 } \
6639 rb = gen_avr_ptr(rB(ctx->opcode)); \
6640 rd = gen_avr_ptr(rD(ctx->opcode)); \
6641 gen_helper_##name (rd, rb); \
6642 tcg_temp_free_ptr(rb); \
6643 tcg_temp_free_ptr(rd); \
6644 }
6645
6646 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6647 static void glue(gen_, name)(DisasContext *ctx) \
6648 { \
6649 TCGv_ptr rb, rd; \
6650 \
6651 if (unlikely(!ctx->altivec_enabled)) { \
6652 gen_exception(ctx, POWERPC_EXCP_VPU); \
6653 return; \
6654 } \
6655 rb = gen_avr_ptr(rB(ctx->opcode)); \
6656 rd = gen_avr_ptr(rD(ctx->opcode)); \
6657 gen_helper_##name(cpu_env, rd, rb); \
6658 tcg_temp_free_ptr(rb); \
6659 tcg_temp_free_ptr(rd); \
6660 }
6661
6662 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6663 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6664 GEN_VXFORM_NOA(vupklsb, 7, 10);
6665 GEN_VXFORM_NOA(vupklsh, 7, 11);
6666 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6667 GEN_VXFORM_NOA(vupklpx, 7, 15);
6668 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6669 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6670 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6671 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6672 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6673 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6674 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6675 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6676
6677 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6678 static void glue(gen_, name)(DisasContext *ctx) \
6679 { \
6680 TCGv_ptr rd; \
6681 TCGv_i32 simm; \
6682 if (unlikely(!ctx->altivec_enabled)) { \
6683 gen_exception(ctx, POWERPC_EXCP_VPU); \
6684 return; \
6685 } \
6686 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6687 rd = gen_avr_ptr(rD(ctx->opcode)); \
6688 gen_helper_##name (rd, simm); \
6689 tcg_temp_free_i32(simm); \
6690 tcg_temp_free_ptr(rd); \
6691 }
6692
6693 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6694 static void glue(gen_, name)(DisasContext *ctx) \
6695 { \
6696 TCGv_ptr rb, rd; \
6697 TCGv_i32 uimm; \
6698 if (unlikely(!ctx->altivec_enabled)) { \
6699 gen_exception(ctx, POWERPC_EXCP_VPU); \
6700 return; \
6701 } \
6702 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6703 rb = gen_avr_ptr(rB(ctx->opcode)); \
6704 rd = gen_avr_ptr(rD(ctx->opcode)); \
6705 gen_helper_##name (rd, rb, uimm); \
6706 tcg_temp_free_i32(uimm); \
6707 tcg_temp_free_ptr(rb); \
6708 tcg_temp_free_ptr(rd); \
6709 }
6710
6711 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6712 static void glue(gen_, name)(DisasContext *ctx) \
6713 { \
6714 TCGv_ptr rb, rd; \
6715 TCGv_i32 uimm; \
6716 \
6717 if (unlikely(!ctx->altivec_enabled)) { \
6718 gen_exception(ctx, POWERPC_EXCP_VPU); \
6719 return; \
6720 } \
6721 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6722 rb = gen_avr_ptr(rB(ctx->opcode)); \
6723 rd = gen_avr_ptr(rD(ctx->opcode)); \
6724 gen_helper_##name(cpu_env, rd, rb, uimm); \
6725 tcg_temp_free_i32(uimm); \
6726 tcg_temp_free_ptr(rb); \
6727 tcg_temp_free_ptr(rd); \
6728 }
6729
6730 GEN_VXFORM_UIMM(vspltb, 6, 8);
6731 GEN_VXFORM_UIMM(vsplth, 6, 9);
6732 GEN_VXFORM_UIMM(vspltw, 6, 10);
6733 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6734 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6735 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6736 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6737
6738 static void gen_vsldoi(DisasContext *ctx)
6739 {
6740 TCGv_ptr ra, rb, rd;
6741 TCGv_i32 sh;
6742 if (unlikely(!ctx->altivec_enabled)) {
6743 gen_exception(ctx, POWERPC_EXCP_VPU);
6744 return;
6745 }
6746 ra = gen_avr_ptr(rA(ctx->opcode));
6747 rb = gen_avr_ptr(rB(ctx->opcode));
6748 rd = gen_avr_ptr(rD(ctx->opcode));
6749 sh = tcg_const_i32(VSH(ctx->opcode));
6750 gen_helper_vsldoi (rd, ra, rb, sh);
6751 tcg_temp_free_ptr(ra);
6752 tcg_temp_free_ptr(rb);
6753 tcg_temp_free_ptr(rd);
6754 tcg_temp_free_i32(sh);
6755 }
6756
6757 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6758 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6759 { \
6760 TCGv_ptr ra, rb, rc, rd; \
6761 if (unlikely(!ctx->altivec_enabled)) { \
6762 gen_exception(ctx, POWERPC_EXCP_VPU); \
6763 return; \
6764 } \
6765 ra = gen_avr_ptr(rA(ctx->opcode)); \
6766 rb = gen_avr_ptr(rB(ctx->opcode)); \
6767 rc = gen_avr_ptr(rC(ctx->opcode)); \
6768 rd = gen_avr_ptr(rD(ctx->opcode)); \
6769 if (Rc(ctx->opcode)) { \
6770 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6771 } else { \
6772 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6773 } \
6774 tcg_temp_free_ptr(ra); \
6775 tcg_temp_free_ptr(rb); \
6776 tcg_temp_free_ptr(rc); \
6777 tcg_temp_free_ptr(rd); \
6778 }
6779
6780 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6781
6782 static void gen_vmladduhm(DisasContext *ctx)
6783 {
6784 TCGv_ptr ra, rb, rc, rd;
6785 if (unlikely(!ctx->altivec_enabled)) {
6786 gen_exception(ctx, POWERPC_EXCP_VPU);
6787 return;
6788 }
6789 ra = gen_avr_ptr(rA(ctx->opcode));
6790 rb = gen_avr_ptr(rB(ctx->opcode));
6791 rc = gen_avr_ptr(rC(ctx->opcode));
6792 rd = gen_avr_ptr(rD(ctx->opcode));
6793 gen_helper_vmladduhm(rd, ra, rb, rc);
6794 tcg_temp_free_ptr(ra);
6795 tcg_temp_free_ptr(rb);
6796 tcg_temp_free_ptr(rc);
6797 tcg_temp_free_ptr(rd);
6798 }
6799
6800 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6801 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6802 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6803 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6804 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6805
6806 /*** SPE extension ***/
6807 /* Register moves */
6808
6809
6810 static inline void gen_evmra(DisasContext *ctx)
6811 {
6812
6813 if (unlikely(!ctx->spe_enabled)) {
6814 gen_exception(ctx, POWERPC_EXCP_SPEU);
6815 return;
6816 }
6817
6818 #if defined(TARGET_PPC64)
6819 /* rD := rA */
6820 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6821
6822 /* spe_acc := rA */
6823 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6824 cpu_env,
6825 offsetof(CPUPPCState, spe_acc));
6826 #else
6827 TCGv_i64 tmp = tcg_temp_new_i64();
6828
6829 /* tmp := rA_lo + rA_hi << 32 */
6830 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6831
6832 /* spe_acc := tmp */
6833 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6834 tcg_temp_free_i64(tmp);
6835
6836 /* rD := rA */
6837 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6838 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6839 #endif
6840 }
6841
6842 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6843 {
6844 #if defined(TARGET_PPC64)
6845 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6846 #else
6847 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6848 #endif
6849 }
6850
6851 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6852 {
6853 #if defined(TARGET_PPC64)
6854 tcg_gen_mov_i64(cpu_gpr[reg], t);
6855 #else
6856 TCGv_i64 tmp = tcg_temp_new_i64();
6857 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6858 tcg_gen_shri_i64(tmp, t, 32);
6859 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6860 tcg_temp_free_i64(tmp);
6861 #endif
6862 }
6863
6864 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6865 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6866 { \
6867 if (Rc(ctx->opcode)) \
6868 gen_##name1(ctx); \
6869 else \
6870 gen_##name0(ctx); \
6871 }
6872
6873 /* Handler for undefined SPE opcodes */
6874 static inline void gen_speundef(DisasContext *ctx)
6875 {
6876 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6877 }
6878
6879 /* SPE logic */
6880 #if defined(TARGET_PPC64)
6881 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6882 static inline void gen_##name(DisasContext *ctx) \
6883 { \
6884 if (unlikely(!ctx->spe_enabled)) { \
6885 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6886 return; \
6887 } \
6888 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6889 cpu_gpr[rB(ctx->opcode)]); \
6890 }
6891 #else
6892 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6893 static inline void gen_##name(DisasContext *ctx) \
6894 { \
6895 if (unlikely(!ctx->spe_enabled)) { \
6896 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6897 return; \
6898 } \
6899 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6900 cpu_gpr[rB(ctx->opcode)]); \
6901 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6902 cpu_gprh[rB(ctx->opcode)]); \
6903 }
6904 #endif
6905
6906 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6907 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6908 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6909 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6910 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6911 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6912 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6913 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6914
6915 /* SPE logic immediate */
6916 #if defined(TARGET_PPC64)
6917 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6918 static inline void gen_##name(DisasContext *ctx) \
6919 { \
6920 if (unlikely(!ctx->spe_enabled)) { \
6921 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6922 return; \
6923 } \
6924 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6925 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6926 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6927 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6928 tcg_opi(t0, t0, rB(ctx->opcode)); \
6929 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6930 tcg_gen_trunc_i64_i32(t1, t2); \
6931 tcg_temp_free_i64(t2); \
6932 tcg_opi(t1, t1, rB(ctx->opcode)); \
6933 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6934 tcg_temp_free_i32(t0); \
6935 tcg_temp_free_i32(t1); \
6936 }
6937 #else
6938 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6939 static inline void gen_##name(DisasContext *ctx) \
6940 { \
6941 if (unlikely(!ctx->spe_enabled)) { \
6942 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6943 return; \
6944 } \
6945 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6946 rB(ctx->opcode)); \
6947 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6948 rB(ctx->opcode)); \
6949 }
6950 #endif
6951 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6952 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6953 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6954 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6955
6956 /* SPE arithmetic */
6957 #if defined(TARGET_PPC64)
6958 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6959 static inline void gen_##name(DisasContext *ctx) \
6960 { \
6961 if (unlikely(!ctx->spe_enabled)) { \
6962 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6963 return; \
6964 } \
6965 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6966 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6967 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6968 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6969 tcg_op(t0, t0); \
6970 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6971 tcg_gen_trunc_i64_i32(t1, t2); \
6972 tcg_temp_free_i64(t2); \
6973 tcg_op(t1, t1); \
6974 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6975 tcg_temp_free_i32(t0); \
6976 tcg_temp_free_i32(t1); \
6977 }
6978 #else
6979 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6980 static inline void gen_##name(DisasContext *ctx) \
6981 { \
6982 if (unlikely(!ctx->spe_enabled)) { \
6983 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6984 return; \
6985 } \
6986 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6987 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6988 }
6989 #endif
6990
6991 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6992 {
6993 int l1 = gen_new_label();
6994 int l2 = gen_new_label();
6995
6996 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6997 tcg_gen_neg_i32(ret, arg1);
6998 tcg_gen_br(l2);
6999 gen_set_label(l1);
7000 tcg_gen_mov_i32(ret, arg1);
7001 gen_set_label(l2);
7002 }
7003 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7004 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7005 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7006 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7007 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7008 {
7009 tcg_gen_addi_i32(ret, arg1, 0x8000);
7010 tcg_gen_ext16u_i32(ret, ret);
7011 }
7012 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7013 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7014 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7015
7016 #if defined(TARGET_PPC64)
7017 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7018 static inline void gen_##name(DisasContext *ctx) \
7019 { \
7020 if (unlikely(!ctx->spe_enabled)) { \
7021 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7022 return; \
7023 } \
7024 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7025 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7026 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7027 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7028 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7029 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7030 tcg_op(t0, t0, t2); \
7031 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7032 tcg_gen_trunc_i64_i32(t1, t3); \
7033 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7034 tcg_gen_trunc_i64_i32(t2, t3); \
7035 tcg_temp_free_i64(t3); \
7036 tcg_op(t1, t1, t2); \
7037 tcg_temp_free_i32(t2); \
7038 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7039 tcg_temp_free_i32(t0); \
7040 tcg_temp_free_i32(t1); \
7041 }
7042 #else
7043 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7044 static inline void gen_##name(DisasContext *ctx) \
7045 { \
7046 if (unlikely(!ctx->spe_enabled)) { \
7047 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7048 return; \
7049 } \
7050 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7051 cpu_gpr[rB(ctx->opcode)]); \
7052 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7053 cpu_gprh[rB(ctx->opcode)]); \
7054 }
7055 #endif
7056
7057 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7058 {
7059 TCGv_i32 t0;
7060 int l1, l2;
7061
7062 l1 = gen_new_label();
7063 l2 = gen_new_label();
7064 t0 = tcg_temp_local_new_i32();
7065 /* No error here: 6 bits are used */
7066 tcg_gen_andi_i32(t0, arg2, 0x3F);
7067 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7068 tcg_gen_shr_i32(ret, arg1, t0);
7069 tcg_gen_br(l2);
7070 gen_set_label(l1);
7071 tcg_gen_movi_i32(ret, 0);
7072 gen_set_label(l2);
7073 tcg_temp_free_i32(t0);
7074 }
7075 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7076 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7077 {
7078 TCGv_i32 t0;
7079 int l1, l2;
7080
7081 l1 = gen_new_label();
7082 l2 = gen_new_label();
7083 t0 = tcg_temp_local_new_i32();
7084 /* No error here: 6 bits are used */
7085 tcg_gen_andi_i32(t0, arg2, 0x3F);
7086 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7087 tcg_gen_sar_i32(ret, arg1, t0);
7088 tcg_gen_br(l2);
7089 gen_set_label(l1);
7090 tcg_gen_movi_i32(ret, 0);
7091 gen_set_label(l2);
7092 tcg_temp_free_i32(t0);
7093 }
7094 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7095 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7096 {
7097 TCGv_i32 t0;
7098 int l1, l2;
7099
7100 l1 = gen_new_label();
7101 l2 = gen_new_label();
7102 t0 = tcg_temp_local_new_i32();
7103 /* No error here: 6 bits are used */
7104 tcg_gen_andi_i32(t0, arg2, 0x3F);
7105 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7106 tcg_gen_shl_i32(ret, arg1, t0);
7107 tcg_gen_br(l2);
7108 gen_set_label(l1);
7109 tcg_gen_movi_i32(ret, 0);
7110 gen_set_label(l2);
7111 tcg_temp_free_i32(t0);
7112 }
7113 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7114 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7115 {
7116 TCGv_i32 t0 = tcg_temp_new_i32();
7117 tcg_gen_andi_i32(t0, arg2, 0x1F);
7118 tcg_gen_rotl_i32(ret, arg1, t0);
7119 tcg_temp_free_i32(t0);
7120 }
7121 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7122 static inline void gen_evmergehi(DisasContext *ctx)
7123 {
7124 if (unlikely(!ctx->spe_enabled)) {
7125 gen_exception(ctx, POWERPC_EXCP_SPEU);
7126 return;
7127 }
7128 #if defined(TARGET_PPC64)
7129 TCGv t0 = tcg_temp_new();
7130 TCGv t1 = tcg_temp_new();
7131 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7132 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7133 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7134 tcg_temp_free(t0);
7135 tcg_temp_free(t1);
7136 #else
7137 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7138 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7139 #endif
7140 }
7141 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7142 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7143 {
7144 tcg_gen_sub_i32(ret, arg2, arg1);
7145 }
7146 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7147
7148 /* SPE arithmetic immediate */
7149 #if defined(TARGET_PPC64)
7150 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7151 static inline void gen_##name(DisasContext *ctx) \
7152 { \
7153 if (unlikely(!ctx->spe_enabled)) { \
7154 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7155 return; \
7156 } \
7157 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7158 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7159 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7160 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7161 tcg_op(t0, t0, rA(ctx->opcode)); \
7162 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7163 tcg_gen_trunc_i64_i32(t1, t2); \
7164 tcg_temp_free_i64(t2); \
7165 tcg_op(t1, t1, rA(ctx->opcode)); \
7166 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7167 tcg_temp_free_i32(t0); \
7168 tcg_temp_free_i32(t1); \
7169 }
7170 #else
7171 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7172 static inline void gen_##name(DisasContext *ctx) \
7173 { \
7174 if (unlikely(!ctx->spe_enabled)) { \
7175 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7176 return; \
7177 } \
7178 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7179 rA(ctx->opcode)); \
7180 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7181 rA(ctx->opcode)); \
7182 }
7183 #endif
7184 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7185 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7186
7187 /* SPE comparison */
7188 #if defined(TARGET_PPC64)
7189 #define GEN_SPEOP_COMP(name, tcg_cond) \
7190 static inline void gen_##name(DisasContext *ctx) \
7191 { \
7192 if (unlikely(!ctx->spe_enabled)) { \
7193 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7194 return; \
7195 } \
7196 int l1 = gen_new_label(); \
7197 int l2 = gen_new_label(); \
7198 int l3 = gen_new_label(); \
7199 int l4 = gen_new_label(); \
7200 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7201 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7202 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7203 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7204 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7205 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7206 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7207 tcg_gen_br(l2); \
7208 gen_set_label(l1); \
7209 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7210 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7211 gen_set_label(l2); \
7212 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7213 tcg_gen_trunc_i64_i32(t0, t2); \
7214 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7215 tcg_gen_trunc_i64_i32(t1, t2); \
7216 tcg_temp_free_i64(t2); \
7217 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7218 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7219 ~(CRF_CH | CRF_CH_AND_CL)); \
7220 tcg_gen_br(l4); \
7221 gen_set_label(l3); \
7222 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7223 CRF_CH | CRF_CH_OR_CL); \
7224 gen_set_label(l4); \
7225 tcg_temp_free_i32(t0); \
7226 tcg_temp_free_i32(t1); \
7227 }
7228 #else
7229 #define GEN_SPEOP_COMP(name, tcg_cond) \
7230 static inline void gen_##name(DisasContext *ctx) \
7231 { \
7232 if (unlikely(!ctx->spe_enabled)) { \
7233 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7234 return; \
7235 } \
7236 int l1 = gen_new_label(); \
7237 int l2 = gen_new_label(); \
7238 int l3 = gen_new_label(); \
7239 int l4 = gen_new_label(); \
7240 \
7241 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7242 cpu_gpr[rB(ctx->opcode)], l1); \
7243 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7244 tcg_gen_br(l2); \
7245 gen_set_label(l1); \
7246 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7247 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7248 gen_set_label(l2); \
7249 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7250 cpu_gprh[rB(ctx->opcode)], l3); \
7251 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7252 ~(CRF_CH | CRF_CH_AND_CL)); \
7253 tcg_gen_br(l4); \
7254 gen_set_label(l3); \
7255 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7256 CRF_CH | CRF_CH_OR_CL); \
7257 gen_set_label(l4); \
7258 }
7259 #endif
7260 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7261 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7262 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7263 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7264 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7265
7266 /* SPE misc */
7267 static inline void gen_brinc(DisasContext *ctx)
7268 {
7269 /* Note: brinc is usable even if SPE is disabled */
7270 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7271 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7272 }
7273 static inline void gen_evmergelo(DisasContext *ctx)
7274 {
7275 if (unlikely(!ctx->spe_enabled)) {
7276 gen_exception(ctx, POWERPC_EXCP_SPEU);
7277 return;
7278 }
7279 #if defined(TARGET_PPC64)
7280 TCGv t0 = tcg_temp_new();
7281 TCGv t1 = tcg_temp_new();
7282 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7283 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7284 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7285 tcg_temp_free(t0);
7286 tcg_temp_free(t1);
7287 #else
7288 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7289 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7290 #endif
7291 }
7292 static inline void gen_evmergehilo(DisasContext *ctx)
7293 {
7294 if (unlikely(!ctx->spe_enabled)) {
7295 gen_exception(ctx, POWERPC_EXCP_SPEU);
7296 return;
7297 }
7298 #if defined(TARGET_PPC64)
7299 TCGv t0 = tcg_temp_new();
7300 TCGv t1 = tcg_temp_new();
7301 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7302 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7303 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7304 tcg_temp_free(t0);
7305 tcg_temp_free(t1);
7306 #else
7307 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7308 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7309 #endif
7310 }
7311 static inline void gen_evmergelohi(DisasContext *ctx)
7312 {
7313 if (unlikely(!ctx->spe_enabled)) {
7314 gen_exception(ctx, POWERPC_EXCP_SPEU);
7315 return;
7316 }
7317 #if defined(TARGET_PPC64)
7318 TCGv t0 = tcg_temp_new();
7319 TCGv t1 = tcg_temp_new();
7320 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7321 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7322 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7323 tcg_temp_free(t0);
7324 tcg_temp_free(t1);
7325 #else
7326 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7327 TCGv_i32 tmp = tcg_temp_new_i32();
7328 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7329 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7330 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7331 tcg_temp_free_i32(tmp);
7332 } else {
7333 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7334 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7335 }
7336 #endif
7337 }
7338 static inline void gen_evsplati(DisasContext *ctx)
7339 {
7340 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7341
7342 #if defined(TARGET_PPC64)
7343 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7344 #else
7345 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7346 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7347 #endif
7348 }
7349 static inline void gen_evsplatfi(DisasContext *ctx)
7350 {
7351 uint64_t imm = rA(ctx->opcode) << 27;
7352
7353 #if defined(TARGET_PPC64)
7354 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7355 #else
7356 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7357 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7358 #endif
7359 }
7360
7361 static inline void gen_evsel(DisasContext *ctx)
7362 {
7363 int l1 = gen_new_label();
7364 int l2 = gen_new_label();
7365 int l3 = gen_new_label();
7366 int l4 = gen_new_label();
7367 TCGv_i32 t0 = tcg_temp_local_new_i32();
7368 #if defined(TARGET_PPC64)
7369 TCGv t1 = tcg_temp_local_new();
7370 TCGv t2 = tcg_temp_local_new();
7371 #endif
7372 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7373 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7374 #if defined(TARGET_PPC64)
7375 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7376 #else
7377 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7378 #endif
7379 tcg_gen_br(l2);
7380 gen_set_label(l1);
7381 #if defined(TARGET_PPC64)
7382 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7383 #else
7384 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7385 #endif
7386 gen_set_label(l2);
7387 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7388 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7389 #if defined(TARGET_PPC64)
7390 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7391 #else
7392 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7393 #endif
7394 tcg_gen_br(l4);
7395 gen_set_label(l3);
7396 #if defined(TARGET_PPC64)
7397 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7398 #else
7399 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7400 #endif
7401 gen_set_label(l4);
7402 tcg_temp_free_i32(t0);
7403 #if defined(TARGET_PPC64)
7404 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7405 tcg_temp_free(t1);
7406 tcg_temp_free(t2);
7407 #endif
7408 }
7409
7410 static void gen_evsel0(DisasContext *ctx)
7411 {
7412 gen_evsel(ctx);
7413 }
7414
7415 static void gen_evsel1(DisasContext *ctx)
7416 {
7417 gen_evsel(ctx);
7418 }
7419
7420 static void gen_evsel2(DisasContext *ctx)
7421 {
7422 gen_evsel(ctx);
7423 }
7424
7425 static void gen_evsel3(DisasContext *ctx)
7426 {
7427 gen_evsel(ctx);
7428 }
7429
7430 /* Multiply */
7431
7432 static inline void gen_evmwumi(DisasContext *ctx)
7433 {
7434 TCGv_i64 t0, t1;
7435
7436 if (unlikely(!ctx->spe_enabled)) {
7437 gen_exception(ctx, POWERPC_EXCP_SPEU);
7438 return;
7439 }
7440
7441 t0 = tcg_temp_new_i64();
7442 t1 = tcg_temp_new_i64();
7443
7444 /* t0 := rA; t1 := rB */
7445 #if defined(TARGET_PPC64)
7446 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7447 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7448 #else
7449 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7450 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7451 #endif
7452
7453 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7454
7455 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7456
7457 tcg_temp_free_i64(t0);
7458 tcg_temp_free_i64(t1);
7459 }
7460
7461 static inline void gen_evmwumia(DisasContext *ctx)
7462 {
7463 TCGv_i64 tmp;
7464
7465 if (unlikely(!ctx->spe_enabled)) {
7466 gen_exception(ctx, POWERPC_EXCP_SPEU);
7467 return;
7468 }
7469
7470 gen_evmwumi(ctx); /* rD := rA * rB */
7471
7472 tmp = tcg_temp_new_i64();
7473
7474 /* acc := rD */
7475 gen_load_gpr64(tmp, rD(ctx->opcode));
7476 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7477 tcg_temp_free_i64(tmp);
7478 }
7479
7480 static inline void gen_evmwumiaa(DisasContext *ctx)
7481 {
7482 TCGv_i64 acc;
7483 TCGv_i64 tmp;
7484
7485 if (unlikely(!ctx->spe_enabled)) {
7486 gen_exception(ctx, POWERPC_EXCP_SPEU);
7487 return;
7488 }
7489
7490 gen_evmwumi(ctx); /* rD := rA * rB */
7491
7492 acc = tcg_temp_new_i64();
7493 tmp = tcg_temp_new_i64();
7494
7495 /* tmp := rD */
7496 gen_load_gpr64(tmp, rD(ctx->opcode));
7497
7498 /* Load acc */
7499 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7500
7501 /* acc := tmp + acc */
7502 tcg_gen_add_i64(acc, acc, tmp);
7503
7504 /* Store acc */
7505 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7506
7507 /* rD := acc */
7508 gen_store_gpr64(rD(ctx->opcode), acc);
7509
7510 tcg_temp_free_i64(acc);
7511 tcg_temp_free_i64(tmp);
7512 }
7513
7514 static inline void gen_evmwsmi(DisasContext *ctx)
7515 {
7516 TCGv_i64 t0, t1;
7517
7518 if (unlikely(!ctx->spe_enabled)) {
7519 gen_exception(ctx, POWERPC_EXCP_SPEU);
7520 return;
7521 }
7522
7523 t0 = tcg_temp_new_i64();
7524 t1 = tcg_temp_new_i64();
7525
7526 /* t0 := rA; t1 := rB */
7527 #if defined(TARGET_PPC64)
7528 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7529 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7530 #else
7531 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7532 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7533 #endif
7534
7535 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7536
7537 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7538
7539 tcg_temp_free_i64(t0);
7540 tcg_temp_free_i64(t1);
7541 }
7542
7543 static inline void gen_evmwsmia(DisasContext *ctx)
7544 {
7545 TCGv_i64 tmp;
7546
7547 gen_evmwsmi(ctx); /* rD := rA * rB */
7548
7549 tmp = tcg_temp_new_i64();
7550
7551 /* acc := rD */
7552 gen_load_gpr64(tmp, rD(ctx->opcode));
7553 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7554
7555 tcg_temp_free_i64(tmp);
7556 }
7557
7558 static inline void gen_evmwsmiaa(DisasContext *ctx)
7559 {
7560 TCGv_i64 acc = tcg_temp_new_i64();
7561 TCGv_i64 tmp = tcg_temp_new_i64();
7562
7563 gen_evmwsmi(ctx); /* rD := rA * rB */
7564
7565 acc = tcg_temp_new_i64();
7566 tmp = tcg_temp_new_i64();
7567
7568 /* tmp := rD */
7569 gen_load_gpr64(tmp, rD(ctx->opcode));
7570
7571 /* Load acc */
7572 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7573
7574 /* acc := tmp + acc */
7575 tcg_gen_add_i64(acc, acc, tmp);
7576
7577 /* Store acc */
7578 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7579
7580 /* rD := acc */
7581 gen_store_gpr64(rD(ctx->opcode), acc);
7582
7583 tcg_temp_free_i64(acc);
7584 tcg_temp_free_i64(tmp);
7585 }
7586
7587 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7588 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7589 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7590 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7591 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7592 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7593 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7594 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7595 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7596 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7597 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7598 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7599 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7600 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7601 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7602 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7603 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7604 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7605 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7606 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7607 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7608 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7609 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7610 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7611 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7612 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7613 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7614 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7615 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7616
7617 /* SPE load and stores */
7618 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7619 {
7620 target_ulong uimm = rB(ctx->opcode);
7621
7622 if (rA(ctx->opcode) == 0) {
7623 tcg_gen_movi_tl(EA, uimm << sh);
7624 } else {
7625 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7626 #if defined(TARGET_PPC64)
7627 if (!ctx->sf_mode) {
7628 tcg_gen_ext32u_tl(EA, EA);
7629 }
7630 #endif
7631 }
7632 }
7633
7634 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7635 {
7636 #if defined(TARGET_PPC64)
7637 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7638 #else
7639 TCGv_i64 t0 = tcg_temp_new_i64();
7640 gen_qemu_ld64(ctx, t0, addr);
7641 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7642 tcg_gen_shri_i64(t0, t0, 32);
7643 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7644 tcg_temp_free_i64(t0);
7645 #endif
7646 }
7647
7648 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7649 {
7650 #if defined(TARGET_PPC64)
7651 TCGv t0 = tcg_temp_new();
7652 gen_qemu_ld32u(ctx, t0, addr);
7653 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7654 gen_addr_add(ctx, addr, addr, 4);
7655 gen_qemu_ld32u(ctx, t0, addr);
7656 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7657 tcg_temp_free(t0);
7658 #else
7659 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7660 gen_addr_add(ctx, addr, addr, 4);
7661 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7662 #endif
7663 }
7664
7665 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7666 {
7667 TCGv t0 = tcg_temp_new();
7668 #if defined(TARGET_PPC64)
7669 gen_qemu_ld16u(ctx, t0, addr);
7670 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7671 gen_addr_add(ctx, addr, addr, 2);
7672 gen_qemu_ld16u(ctx, t0, addr);
7673 tcg_gen_shli_tl(t0, t0, 32);
7674 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7675 gen_addr_add(ctx, addr, addr, 2);
7676 gen_qemu_ld16u(ctx, t0, addr);
7677 tcg_gen_shli_tl(t0, t0, 16);
7678 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7679 gen_addr_add(ctx, addr, addr, 2);
7680 gen_qemu_ld16u(ctx, t0, addr);
7681 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7682 #else
7683 gen_qemu_ld16u(ctx, t0, addr);
7684 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7685 gen_addr_add(ctx, addr, addr, 2);
7686 gen_qemu_ld16u(ctx, t0, addr);
7687 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7688 gen_addr_add(ctx, addr, addr, 2);
7689 gen_qemu_ld16u(ctx, t0, addr);
7690 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7691 gen_addr_add(ctx, addr, addr, 2);
7692 gen_qemu_ld16u(ctx, t0, addr);
7693 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7694 #endif
7695 tcg_temp_free(t0);
7696 }
7697
7698 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7699 {
7700 TCGv t0 = tcg_temp_new();
7701 gen_qemu_ld16u(ctx, t0, addr);
7702 #if defined(TARGET_PPC64)
7703 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7704 tcg_gen_shli_tl(t0, t0, 16);
7705 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7706 #else
7707 tcg_gen_shli_tl(t0, t0, 16);
7708 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7709 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7710 #endif
7711 tcg_temp_free(t0);
7712 }
7713
7714 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7715 {
7716 TCGv t0 = tcg_temp_new();
7717 gen_qemu_ld16u(ctx, t0, addr);
7718 #if defined(TARGET_PPC64)
7719 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7720 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7721 #else
7722 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7723 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7724 #endif
7725 tcg_temp_free(t0);
7726 }
7727
7728 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7729 {
7730 TCGv t0 = tcg_temp_new();
7731 gen_qemu_ld16s(ctx, t0, addr);
7732 #if defined(TARGET_PPC64)
7733 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7734 tcg_gen_ext32u_tl(t0, t0);
7735 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7736 #else
7737 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7738 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7739 #endif
7740 tcg_temp_free(t0);
7741 }
7742
7743 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7744 {
7745 TCGv t0 = tcg_temp_new();
7746 #if defined(TARGET_PPC64)
7747 gen_qemu_ld16u(ctx, t0, addr);
7748 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7749 gen_addr_add(ctx, addr, addr, 2);
7750 gen_qemu_ld16u(ctx, t0, addr);
7751 tcg_gen_shli_tl(t0, t0, 16);
7752 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7753 #else
7754 gen_qemu_ld16u(ctx, t0, addr);
7755 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7756 gen_addr_add(ctx, addr, addr, 2);
7757 gen_qemu_ld16u(ctx, t0, addr);
7758 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7759 #endif
7760 tcg_temp_free(t0);
7761 }
7762
7763 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7764 {
7765 #if defined(TARGET_PPC64)
7766 TCGv t0 = tcg_temp_new();
7767 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7768 gen_addr_add(ctx, addr, addr, 2);
7769 gen_qemu_ld16u(ctx, t0, addr);
7770 tcg_gen_shli_tl(t0, t0, 32);
7771 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7772 tcg_temp_free(t0);
7773 #else
7774 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7775 gen_addr_add(ctx, addr, addr, 2);
7776 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7777 #endif
7778 }
7779
7780 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7781 {
7782 #if defined(TARGET_PPC64)
7783 TCGv t0 = tcg_temp_new();
7784 gen_qemu_ld16s(ctx, t0, addr);
7785 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7786 gen_addr_add(ctx, addr, addr, 2);
7787 gen_qemu_ld16s(ctx, t0, addr);
7788 tcg_gen_shli_tl(t0, t0, 32);
7789 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7790 tcg_temp_free(t0);
7791 #else
7792 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7793 gen_addr_add(ctx, addr, addr, 2);
7794 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7795 #endif
7796 }
7797
7798 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7799 {
7800 TCGv t0 = tcg_temp_new();
7801 gen_qemu_ld32u(ctx, t0, addr);
7802 #if defined(TARGET_PPC64)
7803 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7804 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7805 #else
7806 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7807 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7808 #endif
7809 tcg_temp_free(t0);
7810 }
7811
7812 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7813 {
7814 TCGv t0 = tcg_temp_new();
7815 #if defined(TARGET_PPC64)
7816 gen_qemu_ld16u(ctx, t0, addr);
7817 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7818 tcg_gen_shli_tl(t0, t0, 32);
7819 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7820 gen_addr_add(ctx, addr, addr, 2);
7821 gen_qemu_ld16u(ctx, t0, addr);
7822 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7823 tcg_gen_shli_tl(t0, t0, 16);
7824 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7825 #else
7826 gen_qemu_ld16u(ctx, t0, addr);
7827 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7828 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7829 gen_addr_add(ctx, addr, addr, 2);
7830 gen_qemu_ld16u(ctx, t0, addr);
7831 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7832 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7833 #endif
7834 tcg_temp_free(t0);
7835 }
7836
7837 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7838 {
7839 #if defined(TARGET_PPC64)
7840 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7841 #else
7842 TCGv_i64 t0 = tcg_temp_new_i64();
7843 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7844 gen_qemu_st64(ctx, t0, addr);
7845 tcg_temp_free_i64(t0);
7846 #endif
7847 }
7848
7849 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7850 {
7851 #if defined(TARGET_PPC64)
7852 TCGv t0 = tcg_temp_new();
7853 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7854 gen_qemu_st32(ctx, t0, addr);
7855 tcg_temp_free(t0);
7856 #else
7857 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7858 #endif
7859 gen_addr_add(ctx, addr, addr, 4);
7860 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7861 }
7862
7863 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7864 {
7865 TCGv t0 = tcg_temp_new();
7866 #if defined(TARGET_PPC64)
7867 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7868 #else
7869 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7870 #endif
7871 gen_qemu_st16(ctx, t0, addr);
7872 gen_addr_add(ctx, addr, addr, 2);
7873 #if defined(TARGET_PPC64)
7874 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7875 gen_qemu_st16(ctx, t0, addr);
7876 #else
7877 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7878 #endif
7879 gen_addr_add(ctx, addr, addr, 2);
7880 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7881 gen_qemu_st16(ctx, t0, addr);
7882 tcg_temp_free(t0);
7883 gen_addr_add(ctx, addr, addr, 2);
7884 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7885 }
7886
7887 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7888 {
7889 TCGv t0 = tcg_temp_new();
7890 #if defined(TARGET_PPC64)
7891 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7892 #else
7893 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7894 #endif
7895 gen_qemu_st16(ctx, t0, addr);
7896 gen_addr_add(ctx, addr, addr, 2);
7897 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7898 gen_qemu_st16(ctx, t0, addr);
7899 tcg_temp_free(t0);
7900 }
7901
7902 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7903 {
7904 #if defined(TARGET_PPC64)
7905 TCGv t0 = tcg_temp_new();
7906 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7907 gen_qemu_st16(ctx, t0, addr);
7908 tcg_temp_free(t0);
7909 #else
7910 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7911 #endif
7912 gen_addr_add(ctx, addr, addr, 2);
7913 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7914 }
7915
7916 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7917 {
7918 #if defined(TARGET_PPC64)
7919 TCGv t0 = tcg_temp_new();
7920 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7921 gen_qemu_st32(ctx, t0, addr);
7922 tcg_temp_free(t0);
7923 #else
7924 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7925 #endif
7926 }
7927
7928 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7929 {
7930 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7931 }
7932
7933 #define GEN_SPEOP_LDST(name, opc2, sh) \
7934 static void glue(gen_, name)(DisasContext *ctx) \
7935 { \
7936 TCGv t0; \
7937 if (unlikely(!ctx->spe_enabled)) { \
7938 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7939 return; \
7940 } \
7941 gen_set_access_type(ctx, ACCESS_INT); \
7942 t0 = tcg_temp_new(); \
7943 if (Rc(ctx->opcode)) { \
7944 gen_addr_spe_imm_index(ctx, t0, sh); \
7945 } else { \
7946 gen_addr_reg_index(ctx, t0); \
7947 } \
7948 gen_op_##name(ctx, t0); \
7949 tcg_temp_free(t0); \
7950 }
7951
7952 GEN_SPEOP_LDST(evldd, 0x00, 3);
7953 GEN_SPEOP_LDST(evldw, 0x01, 3);
7954 GEN_SPEOP_LDST(evldh, 0x02, 3);
7955 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7956 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7957 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7958 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7959 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7960 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7961 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7962 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7963
7964 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7965 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7966 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7967 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7968 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7969 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7970 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7971
7972 /* Multiply and add - TODO */
7973 #if 0
7974 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7975 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7976 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7977 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7978 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7979 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7980 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7981 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7982 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7983 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7984 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7985 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7986
7987 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7988 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7989 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7990 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7991 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7992 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7993 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7994 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7995 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7996 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7997 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7998 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7999
8000 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8001 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8002 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8003 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8004 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8005
8006 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8007 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8008 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8009 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8010 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8011 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8012 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8013 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8014 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8015 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8016 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8017 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8018
8019 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8020 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8021 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8022 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8023
8024 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8025 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8026 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8027 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8028 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8029 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8030 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8031 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8032 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8033 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8034 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8035 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8036
8037 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8038 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8039 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8040 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8041 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8042 #endif
8043
8044 /*** SPE floating-point extension ***/
8045 #if defined(TARGET_PPC64)
8046 #define GEN_SPEFPUOP_CONV_32_32(name) \
8047 static inline void gen_##name(DisasContext *ctx) \
8048 { \
8049 TCGv_i32 t0; \
8050 TCGv t1; \
8051 t0 = tcg_temp_new_i32(); \
8052 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8053 gen_helper_##name(t0, cpu_env, t0); \
8054 t1 = tcg_temp_new(); \
8055 tcg_gen_extu_i32_tl(t1, t0); \
8056 tcg_temp_free_i32(t0); \
8057 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8058 0xFFFFFFFF00000000ULL); \
8059 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8060 tcg_temp_free(t1); \
8061 }
8062 #define GEN_SPEFPUOP_CONV_32_64(name) \
8063 static inline void gen_##name(DisasContext *ctx) \
8064 { \
8065 TCGv_i32 t0; \
8066 TCGv t1; \
8067 t0 = tcg_temp_new_i32(); \
8068 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8069 t1 = tcg_temp_new(); \
8070 tcg_gen_extu_i32_tl(t1, t0); \
8071 tcg_temp_free_i32(t0); \
8072 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8073 0xFFFFFFFF00000000ULL); \
8074 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8075 tcg_temp_free(t1); \
8076 }
8077 #define GEN_SPEFPUOP_CONV_64_32(name) \
8078 static inline void gen_##name(DisasContext *ctx) \
8079 { \
8080 TCGv_i32 t0 = tcg_temp_new_i32(); \
8081 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8082 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8083 tcg_temp_free_i32(t0); \
8084 }
8085 #define GEN_SPEFPUOP_CONV_64_64(name) \
8086 static inline void gen_##name(DisasContext *ctx) \
8087 { \
8088 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8089 cpu_gpr[rB(ctx->opcode)]); \
8090 }
8091 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8092 static inline void gen_##name(DisasContext *ctx) \
8093 { \
8094 TCGv_i32 t0, t1; \
8095 TCGv_i64 t2; \
8096 if (unlikely(!ctx->spe_enabled)) { \
8097 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8098 return; \
8099 } \
8100 t0 = tcg_temp_new_i32(); \
8101 t1 = tcg_temp_new_i32(); \
8102 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8103 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8104 gen_helper_##name(t0, cpu_env, t0, t1); \
8105 tcg_temp_free_i32(t1); \
8106 t2 = tcg_temp_new(); \
8107 tcg_gen_extu_i32_tl(t2, t0); \
8108 tcg_temp_free_i32(t0); \
8109 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8110 0xFFFFFFFF00000000ULL); \
8111 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8112 tcg_temp_free(t2); \
8113 }
8114 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8115 static inline void gen_##name(DisasContext *ctx) \
8116 { \
8117 if (unlikely(!ctx->spe_enabled)) { \
8118 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8119 return; \
8120 } \
8121 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8122 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8123 }
8124 #define GEN_SPEFPUOP_COMP_32(name) \
8125 static inline void gen_##name(DisasContext *ctx) \
8126 { \
8127 TCGv_i32 t0, t1; \
8128 if (unlikely(!ctx->spe_enabled)) { \
8129 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8130 return; \
8131 } \
8132 t0 = tcg_temp_new_i32(); \
8133 t1 = tcg_temp_new_i32(); \
8134 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8135 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8136 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8137 tcg_temp_free_i32(t0); \
8138 tcg_temp_free_i32(t1); \
8139 }
8140 #define GEN_SPEFPUOP_COMP_64(name) \
8141 static inline void gen_##name(DisasContext *ctx) \
8142 { \
8143 if (unlikely(!ctx->spe_enabled)) { \
8144 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8145 return; \
8146 } \
8147 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8148 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8149 }
8150 #else
8151 #define GEN_SPEFPUOP_CONV_32_32(name) \
8152 static inline void gen_##name(DisasContext *ctx) \
8153 { \
8154 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8155 cpu_gpr[rB(ctx->opcode)]); \
8156 }
8157 #define GEN_SPEFPUOP_CONV_32_64(name) \
8158 static inline void gen_##name(DisasContext *ctx) \
8159 { \
8160 TCGv_i64 t0 = tcg_temp_new_i64(); \
8161 gen_load_gpr64(t0, rB(ctx->opcode)); \
8162 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8163 tcg_temp_free_i64(t0); \
8164 }
8165 #define GEN_SPEFPUOP_CONV_64_32(name) \
8166 static inline void gen_##name(DisasContext *ctx) \
8167 { \
8168 TCGv_i64 t0 = tcg_temp_new_i64(); \
8169 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8170 gen_store_gpr64(rD(ctx->opcode), t0); \
8171 tcg_temp_free_i64(t0); \
8172 }
8173 #define GEN_SPEFPUOP_CONV_64_64(name) \
8174 static inline void gen_##name(DisasContext *ctx) \
8175 { \
8176 TCGv_i64 t0 = tcg_temp_new_i64(); \
8177 gen_load_gpr64(t0, rB(ctx->opcode)); \
8178 gen_helper_##name(t0, cpu_env, t0); \
8179 gen_store_gpr64(rD(ctx->opcode), t0); \
8180 tcg_temp_free_i64(t0); \
8181 }
8182 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8183 static inline void gen_##name(DisasContext *ctx) \
8184 { \
8185 if (unlikely(!ctx->spe_enabled)) { \
8186 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8187 return; \
8188 } \
8189 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8190 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8191 }
8192 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8193 static inline void gen_##name(DisasContext *ctx) \
8194 { \
8195 TCGv_i64 t0, t1; \
8196 if (unlikely(!ctx->spe_enabled)) { \
8197 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8198 return; \
8199 } \
8200 t0 = tcg_temp_new_i64(); \
8201 t1 = tcg_temp_new_i64(); \
8202 gen_load_gpr64(t0, rA(ctx->opcode)); \
8203 gen_load_gpr64(t1, rB(ctx->opcode)); \
8204 gen_helper_##name(t0, cpu_env, t0, t1); \
8205 gen_store_gpr64(rD(ctx->opcode), t0); \
8206 tcg_temp_free_i64(t0); \
8207 tcg_temp_free_i64(t1); \
8208 }
8209 #define GEN_SPEFPUOP_COMP_32(name) \
8210 static inline void gen_##name(DisasContext *ctx) \
8211 { \
8212 if (unlikely(!ctx->spe_enabled)) { \
8213 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8214 return; \
8215 } \
8216 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8217 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8218 }
8219 #define GEN_SPEFPUOP_COMP_64(name) \
8220 static inline void gen_##name(DisasContext *ctx) \
8221 { \
8222 TCGv_i64 t0, t1; \
8223 if (unlikely(!ctx->spe_enabled)) { \
8224 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8225 return; \
8226 } \
8227 t0 = tcg_temp_new_i64(); \
8228 t1 = tcg_temp_new_i64(); \
8229 gen_load_gpr64(t0, rA(ctx->opcode)); \
8230 gen_load_gpr64(t1, rB(ctx->opcode)); \
8231 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8232 tcg_temp_free_i64(t0); \
8233 tcg_temp_free_i64(t1); \
8234 }
8235 #endif
8236
8237 /* Single precision floating-point vectors operations */
8238 /* Arithmetic */
8239 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8240 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8241 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8242 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8243 static inline void gen_evfsabs(DisasContext *ctx)
8244 {
8245 if (unlikely(!ctx->spe_enabled)) {
8246 gen_exception(ctx, POWERPC_EXCP_SPEU);
8247 return;
8248 }
8249 #if defined(TARGET_PPC64)
8250 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8251 #else
8252 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8253 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8254 #endif
8255 }
8256 static inline void gen_evfsnabs(DisasContext *ctx)
8257 {
8258 if (unlikely(!ctx->spe_enabled)) {
8259 gen_exception(ctx, POWERPC_EXCP_SPEU);
8260 return;
8261 }
8262 #if defined(TARGET_PPC64)
8263 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8264 #else
8265 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8266 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8267 #endif
8268 }
8269 static inline void gen_evfsneg(DisasContext *ctx)
8270 {
8271 if (unlikely(!ctx->spe_enabled)) {
8272 gen_exception(ctx, POWERPC_EXCP_SPEU);
8273 return;
8274 }
8275 #if defined(TARGET_PPC64)
8276 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8277 #else
8278 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8279 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8280 #endif
8281 }
8282
8283 /* Conversion */
8284 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8285 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8286 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8287 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8288 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8289 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8290 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8291 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8292 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8293 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8294
8295 /* Comparison */
8296 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8297 GEN_SPEFPUOP_COMP_64(evfscmplt);
8298 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8299 GEN_SPEFPUOP_COMP_64(evfststgt);
8300 GEN_SPEFPUOP_COMP_64(evfststlt);
8301 GEN_SPEFPUOP_COMP_64(evfststeq);
8302
8303 /* Opcodes definitions */
8304 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8305 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8306 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8307 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8308 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8309 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8310 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8311 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8312 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8313 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8314 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8315 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8316 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8317 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8318
8319 /* Single precision floating-point operations */
8320 /* Arithmetic */
8321 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8322 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8323 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8324 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8325 static inline void gen_efsabs(DisasContext *ctx)
8326 {
8327 if (unlikely(!ctx->spe_enabled)) {
8328 gen_exception(ctx, POWERPC_EXCP_SPEU);
8329 return;
8330 }
8331 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8332 }
8333 static inline void gen_efsnabs(DisasContext *ctx)
8334 {
8335 if (unlikely(!ctx->spe_enabled)) {
8336 gen_exception(ctx, POWERPC_EXCP_SPEU);
8337 return;
8338 }
8339 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8340 }
8341 static inline void gen_efsneg(DisasContext *ctx)
8342 {
8343 if (unlikely(!ctx->spe_enabled)) {
8344 gen_exception(ctx, POWERPC_EXCP_SPEU);
8345 return;
8346 }
8347 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8348 }
8349
8350 /* Conversion */
8351 GEN_SPEFPUOP_CONV_32_32(efscfui);
8352 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8353 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8354 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8355 GEN_SPEFPUOP_CONV_32_32(efsctui);
8356 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8357 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8358 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8359 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8360 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8361 GEN_SPEFPUOP_CONV_32_64(efscfd);
8362
8363 /* Comparison */
8364 GEN_SPEFPUOP_COMP_32(efscmpgt);
8365 GEN_SPEFPUOP_COMP_32(efscmplt);
8366 GEN_SPEFPUOP_COMP_32(efscmpeq);
8367 GEN_SPEFPUOP_COMP_32(efststgt);
8368 GEN_SPEFPUOP_COMP_32(efststlt);
8369 GEN_SPEFPUOP_COMP_32(efststeq);
8370
8371 /* Opcodes definitions */
8372 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8373 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8374 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8375 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8376 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8377 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8378 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8379 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8380 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8381 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8382 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8383 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8384 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8385 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8386
8387 /* Double precision floating-point operations */
8388 /* Arithmetic */
8389 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8390 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8391 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8392 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8393 static inline void gen_efdabs(DisasContext *ctx)
8394 {
8395 if (unlikely(!ctx->spe_enabled)) {
8396 gen_exception(ctx, POWERPC_EXCP_SPEU);
8397 return;
8398 }
8399 #if defined(TARGET_PPC64)
8400 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8401 #else
8402 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8403 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8404 #endif
8405 }
8406 static inline void gen_efdnabs(DisasContext *ctx)
8407 {
8408 if (unlikely(!ctx->spe_enabled)) {
8409 gen_exception(ctx, POWERPC_EXCP_SPEU);
8410 return;
8411 }
8412 #if defined(TARGET_PPC64)
8413 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8414 #else
8415 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8416 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8417 #endif
8418 }
8419 static inline void gen_efdneg(DisasContext *ctx)
8420 {
8421 if (unlikely(!ctx->spe_enabled)) {
8422 gen_exception(ctx, POWERPC_EXCP_SPEU);
8423 return;
8424 }
8425 #if defined(TARGET_PPC64)
8426 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8427 #else
8428 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8429 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8430 #endif
8431 }
8432
8433 /* Conversion */
8434 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8435 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8436 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8437 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8438 GEN_SPEFPUOP_CONV_32_64(efdctui);
8439 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8440 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8441 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8442 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8443 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8444 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8445 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8446 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8447 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8448 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8449
8450 /* Comparison */
8451 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8452 GEN_SPEFPUOP_COMP_64(efdcmplt);
8453 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8454 GEN_SPEFPUOP_COMP_64(efdtstgt);
8455 GEN_SPEFPUOP_COMP_64(efdtstlt);
8456 GEN_SPEFPUOP_COMP_64(efdtsteq);
8457
8458 /* Opcodes definitions */
8459 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8460 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8461 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8462 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8463 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8464 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8465 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8466 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8467 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8468 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8469 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8470 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8471 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8472 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8473 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8474 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8475
8476 static opcode_t opcodes[] = {
8477 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8478 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8479 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8480 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8481 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8482 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8483 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8484 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8485 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8486 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8487 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8488 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8489 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8490 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8491 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8492 #if defined(TARGET_PPC64)
8493 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8494 #endif
8495 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8496 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8497 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8498 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8499 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8500 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8501 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8502 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8503 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8504 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8505 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8506 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8507 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8508 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8509 #if defined(TARGET_PPC64)
8510 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8511 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8512 #endif
8513 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8514 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8515 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8516 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8517 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8518 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8519 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8520 #if defined(TARGET_PPC64)
8521 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8522 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8523 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8524 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8525 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8526 #endif
8527 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8528 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8529 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8530 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8531 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8532 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8533 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8534 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8535 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8536 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8537 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8538 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8539 #if defined(TARGET_PPC64)
8540 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8541 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8542 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8543 #endif
8544 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8545 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8546 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8547 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8548 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8549 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8550 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8551 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8552 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8553 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8554 #if defined(TARGET_PPC64)
8555 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8556 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8557 #endif
8558 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8559 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8560 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8561 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8562 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8563 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8564 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8565 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8566 #if defined(TARGET_PPC64)
8567 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8568 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8569 #endif
8570 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8571 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8572 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8573 #if defined(TARGET_PPC64)
8574 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8575 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8576 #endif
8577 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8578 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8579 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8580 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8581 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8582 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8583 #if defined(TARGET_PPC64)
8584 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8585 #endif
8586 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8587 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8588 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8589 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8590 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8591 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8592 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8593 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8594 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8595 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8596 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8597 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8598 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8599 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8600 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8601 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8602 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8603 #if defined(TARGET_PPC64)
8604 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8605 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8606 PPC_SEGMENT_64B),
8607 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8608 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8609 PPC_SEGMENT_64B),
8610 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8611 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8612 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8613 #endif
8614 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8615 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8616 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8617 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8618 #if defined(TARGET_PPC64)
8619 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8620 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8621 #endif
8622 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8623 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8624 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8625 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8626 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8627 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8628 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8629 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8630 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8631 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8632 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8633 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8634 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8635 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8636 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8637 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8638 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8639 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8640 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8641 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8642 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8643 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8644 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8645 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8646 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8647 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8648 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8649 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8650 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8651 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8652 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8653 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8654 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8655 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8656 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8657 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8658 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8659 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8660 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8661 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8662 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8663 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8664 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8665 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8666 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8667 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8668 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8669 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8670 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8671 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8672 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8673 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8674 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8675 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8676 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8677 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8678 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8679 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8680 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8681 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8682 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8683 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8684 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8685 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8686 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8687 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8688 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8689 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8690 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8691 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8692 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8693 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8694 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8695 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8696 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8697 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8698 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8699 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8700 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8701 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8702 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8703 PPC_NONE, PPC2_BOOKE206),
8704 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8705 PPC_NONE, PPC2_BOOKE206),
8706 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8707 PPC_NONE, PPC2_BOOKE206),
8708 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8709 PPC_NONE, PPC2_BOOKE206),
8710 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8711 PPC_NONE, PPC2_BOOKE206),
8712 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8713 PPC_NONE, PPC2_PRCNTL),
8714 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8715 PPC_NONE, PPC2_PRCNTL),
8716 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8717 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8718 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8719 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8720 PPC_BOOKE, PPC2_BOOKE206),
8721 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8722 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8723 PPC_BOOKE, PPC2_BOOKE206),
8724 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8725 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8726 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8727 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8728 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8729 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8730 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8731 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8732 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8733 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8734
8735 #undef GEN_INT_ARITH_ADD
8736 #undef GEN_INT_ARITH_ADD_CONST
8737 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8738 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8739 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8740 add_ca, compute_ca, compute_ov) \
8741 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8742 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8743 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8744 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8745 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8746 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8747 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8748 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8749 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8750 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8751 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8752
8753 #undef GEN_INT_ARITH_DIVW
8754 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8755 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8756 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8757 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8758 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8759 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8760
8761 #if defined(TARGET_PPC64)
8762 #undef GEN_INT_ARITH_DIVD
8763 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8764 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8765 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8766 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8767 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8768 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8769
8770 #undef GEN_INT_ARITH_MUL_HELPER
8771 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8772 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8773 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8774 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8775 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8776 #endif
8777
8778 #undef GEN_INT_ARITH_SUBF
8779 #undef GEN_INT_ARITH_SUBF_CONST
8780 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8781 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8782 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8783 add_ca, compute_ca, compute_ov) \
8784 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8785 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8786 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8787 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8788 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8789 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8790 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8791 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8792 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8793 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8794 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8795
8796 #undef GEN_LOGICAL1
8797 #undef GEN_LOGICAL2
8798 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8799 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8800 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8801 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8802 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8803 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8804 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8805 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8806 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8807 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8808 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8809 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8810 #if defined(TARGET_PPC64)
8811 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8812 #endif
8813
8814 #if defined(TARGET_PPC64)
8815 #undef GEN_PPC64_R2
8816 #undef GEN_PPC64_R4
8817 #define GEN_PPC64_R2(name, opc1, opc2) \
8818 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8819 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8820 PPC_64B)
8821 #define GEN_PPC64_R4(name, opc1, opc2) \
8822 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8823 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8824 PPC_64B), \
8825 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8826 PPC_64B), \
8827 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8828 PPC_64B)
8829 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8830 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8831 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8832 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8833 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8834 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8835 #endif
8836
8837 #undef _GEN_FLOAT_ACB
8838 #undef GEN_FLOAT_ACB
8839 #undef _GEN_FLOAT_AB
8840 #undef GEN_FLOAT_AB
8841 #undef _GEN_FLOAT_AC
8842 #undef GEN_FLOAT_AC
8843 #undef GEN_FLOAT_B
8844 #undef GEN_FLOAT_BS
8845 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8846 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8847 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8848 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8849 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8850 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8851 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8852 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8853 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8854 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8855 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8856 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8857 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8858 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8859 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8860 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8861 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8862 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8863 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8864
8865 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8866 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8867 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8868 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8869 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8870 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8871 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8872 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8873 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8874 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8875 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8876 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8877 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8878 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8879 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8880 #if defined(TARGET_PPC64)
8881 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8882 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8883 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8884 #endif
8885 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8886 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8887 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8888 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8889 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8890 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8891 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8892
8893 #undef GEN_LD
8894 #undef GEN_LDU
8895 #undef GEN_LDUX
8896 #undef GEN_LDX_E
8897 #undef GEN_LDS
8898 #define GEN_LD(name, ldop, opc, type) \
8899 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8900 #define GEN_LDU(name, ldop, opc, type) \
8901 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8902 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8903 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8904 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8905 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8906 #define GEN_LDS(name, ldop, op, type) \
8907 GEN_LD(name, ldop, op | 0x20, type) \
8908 GEN_LDU(name, ldop, op | 0x21, type) \
8909 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8910 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8911
8912 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8913 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8914 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8915 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8916 #if defined(TARGET_PPC64)
8917 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8918 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8919 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8920 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8921 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8922 #endif
8923 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8924 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8925
8926 #undef GEN_ST
8927 #undef GEN_STU
8928 #undef GEN_STUX
8929 #undef GEN_STX_E
8930 #undef GEN_STS
8931 #define GEN_ST(name, stop, opc, type) \
8932 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8933 #define GEN_STU(name, stop, opc, type) \
8934 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8935 #define GEN_STUX(name, stop, opc2, opc3, type) \
8936 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8937 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8938 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8939 #define GEN_STS(name, stop, op, type) \
8940 GEN_ST(name, stop, op | 0x20, type) \
8941 GEN_STU(name, stop, op | 0x21, type) \
8942 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8943 GEN_STX(name, stop, 0x17, op | 0x00, type)
8944
8945 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8946 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8947 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8948 #if defined(TARGET_PPC64)
8949 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8950 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8951 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8952 #endif
8953 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8954 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8955
8956 #undef GEN_LDF
8957 #undef GEN_LDUF
8958 #undef GEN_LDUXF
8959 #undef GEN_LDXF
8960 #undef GEN_LDFS
8961 #define GEN_LDF(name, ldop, opc, type) \
8962 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8963 #define GEN_LDUF(name, ldop, opc, type) \
8964 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8965 #define GEN_LDUXF(name, ldop, opc, type) \
8966 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8967 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8968 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8969 #define GEN_LDFS(name, ldop, op, type) \
8970 GEN_LDF(name, ldop, op | 0x20, type) \
8971 GEN_LDUF(name, ldop, op | 0x21, type) \
8972 GEN_LDUXF(name, ldop, op | 0x01, type) \
8973 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8974
8975 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8976 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8977
8978 #undef GEN_STF
8979 #undef GEN_STUF
8980 #undef GEN_STUXF
8981 #undef GEN_STXF
8982 #undef GEN_STFS
8983 #define GEN_STF(name, stop, opc, type) \
8984 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8985 #define GEN_STUF(name, stop, opc, type) \
8986 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8987 #define GEN_STUXF(name, stop, opc, type) \
8988 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8989 #define GEN_STXF(name, stop, opc2, opc3, type) \
8990 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8991 #define GEN_STFS(name, stop, op, type) \
8992 GEN_STF(name, stop, op | 0x20, type) \
8993 GEN_STUF(name, stop, op | 0x21, type) \
8994 GEN_STUXF(name, stop, op | 0x01, type) \
8995 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8996
8997 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8998 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8999 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
9000
9001 #undef GEN_CRLOGIC
9002 #define GEN_CRLOGIC(name, tcg_op, opc) \
9003 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9004 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
9005 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
9006 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
9007 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9008 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9009 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9010 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9011 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9012
9013 #undef GEN_MAC_HANDLER
9014 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9015 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9016 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9017 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9018 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9019 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9020 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9021 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9022 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9023 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9024 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9025 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9026 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9027 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9028 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9029 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9030 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9031 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9032 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9033 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9034 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9035 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9036 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9037 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9038 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9039 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9040 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9041 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9042 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9043 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9044 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9045 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9046 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9047 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9048 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9049 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9050 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9051 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9052 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9053 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9054 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9055 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9056 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9057 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9058
9059 #undef GEN_VR_LDX
9060 #undef GEN_VR_STX
9061 #undef GEN_VR_LVE
9062 #undef GEN_VR_STVE
9063 #define GEN_VR_LDX(name, opc2, opc3) \
9064 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9065 #define GEN_VR_STX(name, opc2, opc3) \
9066 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9067 #define GEN_VR_LVE(name, opc2, opc3) \
9068 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9069 #define GEN_VR_STVE(name, opc2, opc3) \
9070 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9071 GEN_VR_LDX(lvx, 0x07, 0x03),
9072 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9073 GEN_VR_LVE(bx, 0x07, 0x00),
9074 GEN_VR_LVE(hx, 0x07, 0x01),
9075 GEN_VR_LVE(wx, 0x07, 0x02),
9076 GEN_VR_STX(svx, 0x07, 0x07),
9077 GEN_VR_STX(svxl, 0x07, 0x0F),
9078 GEN_VR_STVE(bx, 0x07, 0x04),
9079 GEN_VR_STVE(hx, 0x07, 0x05),
9080 GEN_VR_STVE(wx, 0x07, 0x06),
9081
9082 #undef GEN_VX_LOGICAL
9083 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9084 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9085 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9086 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9087 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9088 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9089 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9090
9091 #undef GEN_VXFORM
9092 #define GEN_VXFORM(name, opc2, opc3) \
9093 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9094 GEN_VXFORM(vaddubm, 0, 0),
9095 GEN_VXFORM(vadduhm, 0, 1),
9096 GEN_VXFORM(vadduwm, 0, 2),
9097 GEN_VXFORM(vsububm, 0, 16),
9098 GEN_VXFORM(vsubuhm, 0, 17),
9099 GEN_VXFORM(vsubuwm, 0, 18),
9100 GEN_VXFORM(vmaxub, 1, 0),
9101 GEN_VXFORM(vmaxuh, 1, 1),
9102 GEN_VXFORM(vmaxuw, 1, 2),
9103 GEN_VXFORM(vmaxsb, 1, 4),
9104 GEN_VXFORM(vmaxsh, 1, 5),
9105 GEN_VXFORM(vmaxsw, 1, 6),
9106 GEN_VXFORM(vminub, 1, 8),
9107 GEN_VXFORM(vminuh, 1, 9),
9108 GEN_VXFORM(vminuw, 1, 10),
9109 GEN_VXFORM(vminsb, 1, 12),
9110 GEN_VXFORM(vminsh, 1, 13),
9111 GEN_VXFORM(vminsw, 1, 14),
9112 GEN_VXFORM(vavgub, 1, 16),
9113 GEN_VXFORM(vavguh, 1, 17),
9114 GEN_VXFORM(vavguw, 1, 18),
9115 GEN_VXFORM(vavgsb, 1, 20),
9116 GEN_VXFORM(vavgsh, 1, 21),
9117 GEN_VXFORM(vavgsw, 1, 22),
9118 GEN_VXFORM(vmrghb, 6, 0),
9119 GEN_VXFORM(vmrghh, 6, 1),
9120 GEN_VXFORM(vmrghw, 6, 2),
9121 GEN_VXFORM(vmrglb, 6, 4),
9122 GEN_VXFORM(vmrglh, 6, 5),
9123 GEN_VXFORM(vmrglw, 6, 6),
9124 GEN_VXFORM(vmuloub, 4, 0),
9125 GEN_VXFORM(vmulouh, 4, 1),
9126 GEN_VXFORM(vmulosb, 4, 4),
9127 GEN_VXFORM(vmulosh, 4, 5),
9128 GEN_VXFORM(vmuleub, 4, 8),
9129 GEN_VXFORM(vmuleuh, 4, 9),
9130 GEN_VXFORM(vmulesb, 4, 12),
9131 GEN_VXFORM(vmulesh, 4, 13),
9132 GEN_VXFORM(vslb, 2, 4),
9133 GEN_VXFORM(vslh, 2, 5),
9134 GEN_VXFORM(vslw, 2, 6),
9135 GEN_VXFORM(vsrb, 2, 8),
9136 GEN_VXFORM(vsrh, 2, 9),
9137 GEN_VXFORM(vsrw, 2, 10),
9138 GEN_VXFORM(vsrab, 2, 12),
9139 GEN_VXFORM(vsrah, 2, 13),
9140 GEN_VXFORM(vsraw, 2, 14),
9141 GEN_VXFORM(vslo, 6, 16),
9142 GEN_VXFORM(vsro, 6, 17),
9143 GEN_VXFORM(vaddcuw, 0, 6),
9144 GEN_VXFORM(vsubcuw, 0, 22),
9145 GEN_VXFORM(vaddubs, 0, 8),
9146 GEN_VXFORM(vadduhs, 0, 9),
9147 GEN_VXFORM(vadduws, 0, 10),
9148 GEN_VXFORM(vaddsbs, 0, 12),
9149 GEN_VXFORM(vaddshs, 0, 13),
9150 GEN_VXFORM(vaddsws, 0, 14),
9151 GEN_VXFORM(vsububs, 0, 24),
9152 GEN_VXFORM(vsubuhs, 0, 25),
9153 GEN_VXFORM(vsubuws, 0, 26),
9154 GEN_VXFORM(vsubsbs, 0, 28),
9155 GEN_VXFORM(vsubshs, 0, 29),
9156 GEN_VXFORM(vsubsws, 0, 30),
9157 GEN_VXFORM(vrlb, 2, 0),
9158 GEN_VXFORM(vrlh, 2, 1),
9159 GEN_VXFORM(vrlw, 2, 2),
9160 GEN_VXFORM(vsl, 2, 7),
9161 GEN_VXFORM(vsr, 2, 11),
9162 GEN_VXFORM(vpkuhum, 7, 0),
9163 GEN_VXFORM(vpkuwum, 7, 1),
9164 GEN_VXFORM(vpkuhus, 7, 2),
9165 GEN_VXFORM(vpkuwus, 7, 3),
9166 GEN_VXFORM(vpkshus, 7, 4),
9167 GEN_VXFORM(vpkswus, 7, 5),
9168 GEN_VXFORM(vpkshss, 7, 6),
9169 GEN_VXFORM(vpkswss, 7, 7),
9170 GEN_VXFORM(vpkpx, 7, 12),
9171 GEN_VXFORM(vsum4ubs, 4, 24),
9172 GEN_VXFORM(vsum4sbs, 4, 28),
9173 GEN_VXFORM(vsum4shs, 4, 25),
9174 GEN_VXFORM(vsum2sws, 4, 26),
9175 GEN_VXFORM(vsumsws, 4, 30),
9176 GEN_VXFORM(vaddfp, 5, 0),
9177 GEN_VXFORM(vsubfp, 5, 1),
9178 GEN_VXFORM(vmaxfp, 5, 16),
9179 GEN_VXFORM(vminfp, 5, 17),
9180
9181 #undef GEN_VXRFORM1
9182 #undef GEN_VXRFORM
9183 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9184 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9185 #define GEN_VXRFORM(name, opc2, opc3) \
9186 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9187 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9188 GEN_VXRFORM(vcmpequb, 3, 0)
9189 GEN_VXRFORM(vcmpequh, 3, 1)
9190 GEN_VXRFORM(vcmpequw, 3, 2)
9191 GEN_VXRFORM(vcmpgtsb, 3, 12)
9192 GEN_VXRFORM(vcmpgtsh, 3, 13)
9193 GEN_VXRFORM(vcmpgtsw, 3, 14)
9194 GEN_VXRFORM(vcmpgtub, 3, 8)
9195 GEN_VXRFORM(vcmpgtuh, 3, 9)
9196 GEN_VXRFORM(vcmpgtuw, 3, 10)
9197 GEN_VXRFORM(vcmpeqfp, 3, 3)
9198 GEN_VXRFORM(vcmpgefp, 3, 7)
9199 GEN_VXRFORM(vcmpgtfp, 3, 11)
9200 GEN_VXRFORM(vcmpbfp, 3, 15)
9201
9202 #undef GEN_VXFORM_SIMM
9203 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9204 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9205 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9206 GEN_VXFORM_SIMM(vspltish, 6, 13),
9207 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9208
9209 #undef GEN_VXFORM_NOA
9210 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9211 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9212 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9213 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9214 GEN_VXFORM_NOA(vupklsb, 7, 10),
9215 GEN_VXFORM_NOA(vupklsh, 7, 11),
9216 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9217 GEN_VXFORM_NOA(vupklpx, 7, 15),
9218 GEN_VXFORM_NOA(vrefp, 5, 4),
9219 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9220 GEN_VXFORM_NOA(vexptefp, 5, 6),
9221 GEN_VXFORM_NOA(vlogefp, 5, 7),
9222 GEN_VXFORM_NOA(vrfim, 5, 8),
9223 GEN_VXFORM_NOA(vrfin, 5, 9),
9224 GEN_VXFORM_NOA(vrfip, 5, 10),
9225 GEN_VXFORM_NOA(vrfiz, 5, 11),
9226
9227 #undef GEN_VXFORM_UIMM
9228 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9229 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9230 GEN_VXFORM_UIMM(vspltb, 6, 8),
9231 GEN_VXFORM_UIMM(vsplth, 6, 9),
9232 GEN_VXFORM_UIMM(vspltw, 6, 10),
9233 GEN_VXFORM_UIMM(vcfux, 5, 12),
9234 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9235 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9236 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9237
9238 #undef GEN_VAFORM_PAIRED
9239 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9240 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9241 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9242 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9243 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9244 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9245 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9246 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9247
9248 #undef GEN_SPE
9249 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9250 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9251 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9252 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9253 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9254 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9255 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9256 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9257 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9258 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9259 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9260 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9261 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9262 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9263 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9264 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9265 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9266 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9267 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9268 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9269 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9270 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9271 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9272 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9273 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9274 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9275 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9276 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9277 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9278 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9279 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9280
9281 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9282 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9283 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9284 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9285 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9286 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9287 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9288 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9289 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9290 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9291 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9292 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9293 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9294 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9295
9296 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9297 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9298 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9299 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9300 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9301 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9302 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9303 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9304 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9305 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9306 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9307 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9308 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9309 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9310
9311 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9312 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9313 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9314 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9315 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9316 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9317 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9318 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9319 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9320 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9321 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9322 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9323 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9324 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9325 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9326 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9327
9328 #undef GEN_SPEOP_LDST
9329 #define GEN_SPEOP_LDST(name, opc2, sh) \
9330 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9331 GEN_SPEOP_LDST(evldd, 0x00, 3),
9332 GEN_SPEOP_LDST(evldw, 0x01, 3),
9333 GEN_SPEOP_LDST(evldh, 0x02, 3),
9334 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9335 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9336 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9337 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9338 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9339 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9340 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9341 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9342
9343 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9344 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9345 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9346 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9347 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9348 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9349 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9350 };
9351
9352 #include "helper_regs.h"
9353 #include "translate_init.c"
9354
9355 /*****************************************************************************/
9356 /* Misc PowerPC helpers */
9357 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9358 int flags)
9359 {
9360 #define RGPL 4
9361 #define RFPL 4
9362
9363 int i;
9364
9365 cpu_synchronize_state(env);
9366
9367 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9368 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9369 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9370 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9371 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9372 env->hflags, env->mmu_idx);
9373 #if !defined(NO_TIMER_DUMP)
9374 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9375 #if !defined(CONFIG_USER_ONLY)
9376 " DECR %08" PRIu32
9377 #endif
9378 "\n",
9379 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9380 #if !defined(CONFIG_USER_ONLY)
9381 , cpu_ppc_load_decr(env)
9382 #endif
9383 );
9384 #endif
9385 for (i = 0; i < 32; i++) {
9386 if ((i & (RGPL - 1)) == 0)
9387 cpu_fprintf(f, "GPR%02d", i);
9388 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9389 if ((i & (RGPL - 1)) == (RGPL - 1))
9390 cpu_fprintf(f, "\n");
9391 }
9392 cpu_fprintf(f, "CR ");
9393 for (i = 0; i < 8; i++)
9394 cpu_fprintf(f, "%01x", env->crf[i]);
9395 cpu_fprintf(f, " [");
9396 for (i = 0; i < 8; i++) {
9397 char a = '-';
9398 if (env->crf[i] & 0x08)
9399 a = 'L';
9400 else if (env->crf[i] & 0x04)
9401 a = 'G';
9402 else if (env->crf[i] & 0x02)
9403 a = 'E';
9404 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9405 }
9406 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9407 env->reserve_addr);
9408 for (i = 0; i < 32; i++) {
9409 if ((i & (RFPL - 1)) == 0)
9410 cpu_fprintf(f, "FPR%02d", i);
9411 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9412 if ((i & (RFPL - 1)) == (RFPL - 1))
9413 cpu_fprintf(f, "\n");
9414 }
9415 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9416 #if !defined(CONFIG_USER_ONLY)
9417 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9418 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9419 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9420 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9421
9422 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9423 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9424 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9425 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9426
9427 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9428 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9429 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9430 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9431
9432 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9433 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9434 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9435 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9436 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9437
9438 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9439 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9440 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9441 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9442
9443 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9444 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9445 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9446 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9447
9448 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9449 " EPR " TARGET_FMT_lx "\n",
9450 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9451 env->spr[SPR_BOOKE_EPR]);
9452
9453 /* FSL-specific */
9454 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9455 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9456 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9457 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9458
9459 /*
9460 * IVORs are left out as they are large and do not change often --
9461 * they can be read with "p $ivor0", "p $ivor1", etc.
9462 */
9463 }
9464
9465 #if defined(TARGET_PPC64)
9466 if (env->flags & POWERPC_FLAG_CFAR) {
9467 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9468 }
9469 #endif
9470
9471 switch (env->mmu_model) {
9472 case POWERPC_MMU_32B:
9473 case POWERPC_MMU_601:
9474 case POWERPC_MMU_SOFT_6xx:
9475 case POWERPC_MMU_SOFT_74xx:
9476 #if defined(TARGET_PPC64)
9477 case POWERPC_MMU_620:
9478 case POWERPC_MMU_64B:
9479 #endif
9480 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9481 break;
9482 case POWERPC_MMU_BOOKE206:
9483 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9484 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9485 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9486 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9487
9488 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9489 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9490 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9491 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9492
9493 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9494 " TLB1CFG " TARGET_FMT_lx "\n",
9495 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9496 env->spr[SPR_BOOKE_TLB1CFG]);
9497 break;
9498 default:
9499 break;
9500 }
9501 #endif
9502
9503 #undef RGPL
9504 #undef RFPL
9505 }
9506
9507 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9508 int flags)
9509 {
9510 #if defined(DO_PPC_STATISTICS)
9511 opc_handler_t **t1, **t2, **t3, *handler;
9512 int op1, op2, op3;
9513
9514 t1 = env->opcodes;
9515 for (op1 = 0; op1 < 64; op1++) {
9516 handler = t1[op1];
9517 if (is_indirect_opcode(handler)) {
9518 t2 = ind_table(handler);
9519 for (op2 = 0; op2 < 32; op2++) {
9520 handler = t2[op2];
9521 if (is_indirect_opcode(handler)) {
9522 t3 = ind_table(handler);
9523 for (op3 = 0; op3 < 32; op3++) {
9524 handler = t3[op3];
9525 if (handler->count == 0)
9526 continue;
9527 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9528 "%016" PRIx64 " %" PRId64 "\n",
9529 op1, op2, op3, op1, (op3 << 5) | op2,
9530 handler->oname,
9531 handler->count, handler->count);
9532 }
9533 } else {
9534 if (handler->count == 0)
9535 continue;
9536 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9537 "%016" PRIx64 " %" PRId64 "\n",
9538 op1, op2, op1, op2, handler->oname,
9539 handler->count, handler->count);
9540 }
9541 }
9542 } else {
9543 if (handler->count == 0)
9544 continue;
9545 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9546 " %" PRId64 "\n",
9547 op1, op1, handler->oname,
9548 handler->count, handler->count);
9549 }
9550 }
9551 #endif
9552 }
9553
9554 /*****************************************************************************/
9555 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9556 TranslationBlock *tb,
9557 int search_pc)
9558 {
9559 DisasContext ctx, *ctxp = &ctx;
9560 opc_handler_t **table, *handler;
9561 target_ulong pc_start;
9562 uint16_t *gen_opc_end;
9563 CPUBreakpoint *bp;
9564 int j, lj = -1;
9565 int num_insns;
9566 int max_insns;
9567
9568 pc_start = tb->pc;
9569 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9570 ctx.nip = pc_start;
9571 ctx.tb = tb;
9572 ctx.exception = POWERPC_EXCP_NONE;
9573 ctx.spr_cb = env->spr_cb;
9574 ctx.mem_idx = env->mmu_idx;
9575 ctx.access_type = -1;
9576 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9577 #if defined(TARGET_PPC64)
9578 ctx.sf_mode = msr_is_64bit(env, env->msr);
9579 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9580 #endif
9581 ctx.fpu_enabled = msr_fp;
9582 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9583 ctx.spe_enabled = msr_spe;
9584 else
9585 ctx.spe_enabled = 0;
9586 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9587 ctx.altivec_enabled = msr_vr;
9588 else
9589 ctx.altivec_enabled = 0;
9590 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9591 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9592 else
9593 ctx.singlestep_enabled = 0;
9594 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9595 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9596 if (unlikely(env->singlestep_enabled))
9597 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9598 #if defined (DO_SINGLE_STEP) && 0
9599 /* Single step trace mode */
9600 msr_se = 1;
9601 #endif
9602 num_insns = 0;
9603 max_insns = tb->cflags & CF_COUNT_MASK;
9604 if (max_insns == 0)
9605 max_insns = CF_COUNT_MASK;
9606
9607 gen_icount_start();
9608 /* Set env in case of segfault during code fetch */
9609 while (ctx.exception == POWERPC_EXCP_NONE
9610 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9611 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9612 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9613 if (bp->pc == ctx.nip) {
9614 gen_debug_exception(ctxp);
9615 break;
9616 }
9617 }
9618 }
9619 if (unlikely(search_pc)) {
9620 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9621 if (lj < j) {
9622 lj++;
9623 while (lj < j)
9624 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9625 }
9626 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9627 tcg_ctx.gen_opc_instr_start[lj] = 1;
9628 tcg_ctx.gen_opc_icount[lj] = num_insns;
9629 }
9630 LOG_DISAS("----------------\n");
9631 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9632 ctx.nip, ctx.mem_idx, (int)msr_ir);
9633 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9634 gen_io_start();
9635 if (unlikely(ctx.le_mode)) {
9636 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9637 } else {
9638 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9639 }
9640 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9641 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9642 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9643 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9644 tcg_gen_debug_insn_start(ctx.nip);
9645 }
9646 ctx.nip += 4;
9647 table = env->opcodes;
9648 num_insns++;
9649 handler = table[opc1(ctx.opcode)];
9650 if (is_indirect_opcode(handler)) {
9651 table = ind_table(handler);
9652 handler = table[opc2(ctx.opcode)];
9653 if (is_indirect_opcode(handler)) {
9654 table = ind_table(handler);
9655 handler = table[opc3(ctx.opcode)];
9656 }
9657 }
9658 /* Is opcode *REALLY* valid ? */
9659 if (unlikely(handler->handler == &gen_invalid)) {
9660 if (qemu_log_enabled()) {
9661 qemu_log("invalid/unsupported opcode: "
9662 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9663 opc1(ctx.opcode), opc2(ctx.opcode),
9664 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9665 }
9666 } else {
9667 uint32_t inval;
9668
9669 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9670 inval = handler->inval2;
9671 } else {
9672 inval = handler->inval1;
9673 }
9674
9675 if (unlikely((ctx.opcode & inval) != 0)) {
9676 if (qemu_log_enabled()) {
9677 qemu_log("invalid bits: %08x for opcode: "
9678 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9679 ctx.opcode & inval, opc1(ctx.opcode),
9680 opc2(ctx.opcode), opc3(ctx.opcode),
9681 ctx.opcode, ctx.nip - 4);
9682 }
9683 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9684 break;
9685 }
9686 }
9687 (*(handler->handler))(&ctx);
9688 #if defined(DO_PPC_STATISTICS)
9689 handler->count++;
9690 #endif
9691 /* Check trace mode exceptions */
9692 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9693 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9694 ctx.exception != POWERPC_SYSCALL &&
9695 ctx.exception != POWERPC_EXCP_TRAP &&
9696 ctx.exception != POWERPC_EXCP_BRANCH)) {
9697 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9698 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9699 (env->singlestep_enabled) ||
9700 singlestep ||
9701 num_insns >= max_insns)) {
9702 /* if we reach a page boundary or are single stepping, stop
9703 * generation
9704 */
9705 break;
9706 }
9707 }
9708 if (tb->cflags & CF_LAST_IO)
9709 gen_io_end();
9710 if (ctx.exception == POWERPC_EXCP_NONE) {
9711 gen_goto_tb(&ctx, 0, ctx.nip);
9712 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9713 if (unlikely(env->singlestep_enabled)) {
9714 gen_debug_exception(ctxp);
9715 }
9716 /* Generate the return instruction */
9717 tcg_gen_exit_tb(0);
9718 }
9719 gen_icount_end(tb, num_insns);
9720 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9721 if (unlikely(search_pc)) {
9722 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9723 lj++;
9724 while (lj <= j)
9725 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9726 } else {
9727 tb->size = ctx.nip - pc_start;
9728 tb->icount = num_insns;
9729 }
9730 #if defined(DEBUG_DISAS)
9731 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9732 int flags;
9733 flags = env->bfd_mach;
9734 flags |= ctx.le_mode << 16;
9735 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9736 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9737 qemu_log("\n");
9738 }
9739 #endif
9740 }
9741
9742 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9743 {
9744 gen_intermediate_code_internal(env, tb, 0);
9745 }
9746
9747 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9748 {
9749 gen_intermediate_code_internal(env, tb, 1);
9750 }
9751
9752 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9753 {
9754 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9755 }
Qemu copy for testing