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[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 struct opc_handler_t {
208 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
209 uint32_t inval1;
210 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
211 uint32_t inval2;
212 /* instruction type */
213 uint64_t type;
214 /* extended instruction type */
215 uint64_t type2;
216 /* handler */
217 void (*handler)(DisasContext *ctx);
218 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
219 const char *oname;
220 #endif
221 #if defined(DO_PPC_STATISTICS)
222 uint64_t count;
223 #endif
224 };
225
226 static inline void gen_reset_fpstatus(void)
227 {
228 gen_helper_reset_fpstatus(cpu_env);
229 }
230
231 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
232 {
233 TCGv_i32 t0 = tcg_temp_new_i32();
234
235 if (set_fprf != 0) {
236 /* This case might be optimized later */
237 tcg_gen_movi_i32(t0, 1);
238 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
239 if (unlikely(set_rc)) {
240 tcg_gen_mov_i32(cpu_crf[1], t0);
241 }
242 gen_helper_float_check_status(cpu_env);
243 } else if (unlikely(set_rc)) {
244 /* We always need to compute fpcc */
245 tcg_gen_movi_i32(t0, 0);
246 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249
250 tcg_temp_free_i32(t0);
251 }
252
253 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
254 {
255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
259 }
260
261 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
262 {
263 #if defined(TARGET_PPC64)
264 if (ctx->sf_mode)
265 tcg_gen_movi_tl(cpu_nip, nip);
266 else
267 #endif
268 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
269 }
270
271 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
272 {
273 TCGv_i32 t0, t1;
274 if (ctx->exception == POWERPC_EXCP_NONE) {
275 gen_update_nip(ctx, ctx->nip);
276 }
277 t0 = tcg_const_i32(excp);
278 t1 = tcg_const_i32(error);
279 gen_helper_raise_exception_err(cpu_env, t0, t1);
280 tcg_temp_free_i32(t0);
281 tcg_temp_free_i32(t1);
282 ctx->exception = (excp);
283 }
284
285 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
286 {
287 TCGv_i32 t0;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 gen_helper_raise_exception(cpu_env, t0);
293 tcg_temp_free_i32(t0);
294 ctx->exception = (excp);
295 }
296
297 static inline void gen_debug_exception(DisasContext *ctx)
298 {
299 TCGv_i32 t0;
300
301 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
302 (ctx->exception != POWERPC_EXCP_SYNC)) {
303 gen_update_nip(ctx, ctx->nip);
304 }
305 t0 = tcg_const_i32(EXCP_DEBUG);
306 gen_helper_raise_exception(cpu_env, t0);
307 tcg_temp_free_i32(t0);
308 }
309
310 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
311 {
312 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
313 }
314
315 /* Stop translation */
316 static inline void gen_stop_exception(DisasContext *ctx)
317 {
318 gen_update_nip(ctx, ctx->nip);
319 ctx->exception = POWERPC_EXCP_STOP;
320 }
321
322 /* No need to update nip here, as execution flow will change */
323 static inline void gen_sync_exception(DisasContext *ctx)
324 {
325 ctx->exception = POWERPC_EXCP_SYNC;
326 }
327
328 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
333
334 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
335 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
336
337 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
338 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
339
340 typedef struct opcode_t {
341 unsigned char opc1, opc2, opc3;
342 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
343 unsigned char pad[5];
344 #else
345 unsigned char pad[1];
346 #endif
347 opc_handler_t handler;
348 const char *oname;
349 } opcode_t;
350
351 /*****************************************************************************/
352 /*** Instruction decoding ***/
353 #define EXTRACT_HELPER(name, shift, nb) \
354 static inline uint32_t name(uint32_t opcode) \
355 { \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
357 }
358
359 #define EXTRACT_SHELPER(name, shift, nb) \
360 static inline int32_t name(uint32_t opcode) \
361 { \
362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
363 }
364
365 /* Opcode part 1 */
366 EXTRACT_HELPER(opc1, 26, 6);
367 /* Opcode part 2 */
368 EXTRACT_HELPER(opc2, 1, 5);
369 /* Opcode part 3 */
370 EXTRACT_HELPER(opc3, 6, 5);
371 /* Update Cr0 flags */
372 EXTRACT_HELPER(Rc, 0, 1);
373 /* Destination */
374 EXTRACT_HELPER(rD, 21, 5);
375 /* Source */
376 EXTRACT_HELPER(rS, 21, 5);
377 /* First operand */
378 EXTRACT_HELPER(rA, 16, 5);
379 /* Second operand */
380 EXTRACT_HELPER(rB, 11, 5);
381 /* Third operand */
382 EXTRACT_HELPER(rC, 6, 5);
383 /*** Get CRn ***/
384 EXTRACT_HELPER(crfD, 23, 3);
385 EXTRACT_HELPER(crfS, 18, 3);
386 EXTRACT_HELPER(crbD, 21, 5);
387 EXTRACT_HELPER(crbA, 16, 5);
388 EXTRACT_HELPER(crbB, 11, 5);
389 /* SPR / TBL */
390 EXTRACT_HELPER(_SPR, 11, 10);
391 static inline uint32_t SPR(uint32_t opcode)
392 {
393 uint32_t sprn = _SPR(opcode);
394
395 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
396 }
397 /*** Get constants ***/
398 EXTRACT_HELPER(IMM, 12, 8);
399 /* 16 bits signed immediate value */
400 EXTRACT_SHELPER(SIMM, 0, 16);
401 /* 16 bits unsigned immediate value */
402 EXTRACT_HELPER(UIMM, 0, 16);
403 /* 5 bits signed immediate value */
404 EXTRACT_HELPER(SIMM5, 16, 5);
405 /* 5 bits signed immediate value */
406 EXTRACT_HELPER(UIMM5, 16, 5);
407 /* Bit count */
408 EXTRACT_HELPER(NB, 11, 5);
409 /* Shift count */
410 EXTRACT_HELPER(SH, 11, 5);
411 /* Vector shift count */
412 EXTRACT_HELPER(VSH, 6, 4);
413 /* Mask start */
414 EXTRACT_HELPER(MB, 6, 5);
415 /* Mask end */
416 EXTRACT_HELPER(ME, 1, 5);
417 /* Trap operand */
418 EXTRACT_HELPER(TO, 21, 5);
419
420 EXTRACT_HELPER(CRM, 12, 8);
421 EXTRACT_HELPER(FM, 17, 8);
422 EXTRACT_HELPER(SR, 16, 4);
423 EXTRACT_HELPER(FPIMM, 12, 4);
424
425 /*** Jump target decoding ***/
426 /* Displacement */
427 EXTRACT_SHELPER(d, 0, 16);
428 /* Immediate address */
429 static inline target_ulong LI(uint32_t opcode)
430 {
431 return (opcode >> 0) & 0x03FFFFFC;
432 }
433
434 static inline uint32_t BD(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0xFFFC;
437 }
438
439 EXTRACT_HELPER(BO, 21, 5);
440 EXTRACT_HELPER(BI, 16, 5);
441 /* Absolute/relative address */
442 EXTRACT_HELPER(AA, 1, 1);
443 /* Link */
444 EXTRACT_HELPER(LK, 0, 1);
445
446 /* Create a mask between <start> and <end> bits */
447 static inline target_ulong MASK(uint32_t start, uint32_t end)
448 {
449 target_ulong ret;
450
451 #if defined(TARGET_PPC64)
452 if (likely(start == 0)) {
453 ret = UINT64_MAX << (63 - end);
454 } else if (likely(end == 63)) {
455 ret = UINT64_MAX >> start;
456 }
457 #else
458 if (likely(start == 0)) {
459 ret = UINT32_MAX << (31 - end);
460 } else if (likely(end == 31)) {
461 ret = UINT32_MAX >> start;
462 }
463 #endif
464 else {
465 ret = (((target_ulong)(-1ULL)) >> (start)) ^
466 (((target_ulong)(-1ULL) >> (end)) >> 1);
467 if (unlikely(start > end))
468 return ~ret;
469 }
470
471 return ret;
472 }
473
474 /*****************************************************************************/
475 /* PowerPC instructions table */
476
477 #if defined(DO_PPC_STATISTICS)
478 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
479 { \
480 .opc1 = op1, \
481 .opc2 = op2, \
482 .opc3 = op3, \
483 .pad = { 0, }, \
484 .handler = { \
485 .inval1 = invl, \
486 .type = _typ, \
487 .type2 = _typ2, \
488 .handler = &gen_##name, \
489 .oname = stringify(name), \
490 }, \
491 .oname = stringify(name), \
492 }
493 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
494 { \
495 .opc1 = op1, \
496 .opc2 = op2, \
497 .opc3 = op3, \
498 .pad = { 0, }, \
499 .handler = { \
500 .inval1 = invl1, \
501 .inval2 = invl2, \
502 .type = _typ, \
503 .type2 = _typ2, \
504 .handler = &gen_##name, \
505 .oname = stringify(name), \
506 }, \
507 .oname = stringify(name), \
508 }
509 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
510 { \
511 .opc1 = op1, \
512 .opc2 = op2, \
513 .opc3 = op3, \
514 .pad = { 0, }, \
515 .handler = { \
516 .inval1 = invl, \
517 .type = _typ, \
518 .type2 = _typ2, \
519 .handler = &gen_##name, \
520 .oname = onam, \
521 }, \
522 .oname = onam, \
523 }
524 #else
525 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
526 { \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl, \
533 .type = _typ, \
534 .type2 = _typ2, \
535 .handler = &gen_##name, \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
548 .type = _typ, \
549 .type2 = _typ2, \
550 .handler = &gen_##name, \
551 }, \
552 .oname = stringify(name), \
553 }
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555 { \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 }, \
566 .oname = onam, \
567 }
568 #endif
569
570 /* SPR load/store helpers */
571 static inline void gen_load_spr(TCGv t, int reg)
572 {
573 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
574 }
575
576 static inline void gen_store_spr(int reg, TCGv t)
577 {
578 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 /* Invalid instruction */
582 static void gen_invalid(DisasContext *ctx)
583 {
584 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
585 }
586
587 static opc_handler_t invalid_handler = {
588 .inval1 = 0xFFFFFFFF,
589 .inval2 = 0xFFFFFFFF,
590 .type = PPC_NONE,
591 .type2 = PPC_NONE,
592 .handler = gen_invalid,
593 };
594
595 /*** Integer comparison ***/
596
597 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
598 {
599 TCGv t0 = tcg_temp_new();
600 TCGv_i32 t1 = tcg_temp_new_i32();
601
602 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
603
604 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
605 tcg_gen_trunc_tl_i32(t1, t0);
606 tcg_gen_shli_i32(t1, t1, CRF_LT);
607 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_GT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_EQ);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_temp_free(t0);
620 tcg_temp_free_i32(t1);
621 }
622
623 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
624 {
625 TCGv t0 = tcg_const_tl(arg1);
626 gen_op_cmp(arg0, t0, s, crf);
627 tcg_temp_free(t0);
628 }
629
630 #if defined(TARGET_PPC64)
631 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
632 {
633 TCGv t0, t1;
634 t0 = tcg_temp_new();
635 t1 = tcg_temp_new();
636 if (s) {
637 tcg_gen_ext32s_tl(t0, arg0);
638 tcg_gen_ext32s_tl(t1, arg1);
639 } else {
640 tcg_gen_ext32u_tl(t0, arg0);
641 tcg_gen_ext32u_tl(t1, arg1);
642 }
643 gen_op_cmp(t0, t1, s, crf);
644 tcg_temp_free(t1);
645 tcg_temp_free(t0);
646 }
647
648 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
649 {
650 TCGv t0 = tcg_const_tl(arg1);
651 gen_op_cmp32(arg0, t0, s, crf);
652 tcg_temp_free(t0);
653 }
654 #endif
655
656 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
657 {
658 #if defined(TARGET_PPC64)
659 if (!(ctx->sf_mode))
660 gen_op_cmpi32(reg, 0, 1, 0);
661 else
662 #endif
663 gen_op_cmpi(reg, 0, 1, 0);
664 }
665
666 /* cmp */
667 static void gen_cmp(DisasContext *ctx)
668 {
669 #if defined(TARGET_PPC64)
670 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
671 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 else
674 #endif
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678
679 /* cmpi */
680 static void gen_cmpi(DisasContext *ctx)
681 {
682 #if defined(TARGET_PPC64)
683 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 else
687 #endif
688 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
689 1, crfD(ctx->opcode));
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 #if defined(TARGET_PPC64)
696 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 else
700 #endif
701 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
702 0, crfD(ctx->opcode));
703 }
704
705 /* cmpli */
706 static void gen_cmpli(DisasContext *ctx)
707 {
708 #if defined(TARGET_PPC64)
709 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
710 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712 else
713 #endif
714 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
715 0, crfD(ctx->opcode));
716 }
717
718 /* isel (PowerPC 2.03 specification) */
719 static void gen_isel(DisasContext *ctx)
720 {
721 int l1, l2;
722 uint32_t bi = rC(ctx->opcode);
723 uint32_t mask;
724 TCGv_i32 t0;
725
726 l1 = gen_new_label();
727 l2 = gen_new_label();
728
729 mask = 1 << (3 - (bi & 0x03));
730 t0 = tcg_temp_new_i32();
731 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
732 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
733 if (rA(ctx->opcode) == 0)
734 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
735 else
736 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
737 tcg_gen_br(l2);
738 gen_set_label(l1);
739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
740 gen_set_label(l2);
741 tcg_temp_free_i32(t0);
742 }
743
744 /*** Integer arithmetic ***/
745
746 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
747 TCGv arg1, TCGv arg2, int sub)
748 {
749 TCGv t0 = tcg_temp_new();
750
751 tcg_gen_xor_tl(cpu_ov, arg0, arg1);
752 tcg_gen_xor_tl(t0, arg1, arg2);
753 if (sub) {
754 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
755 } else {
756 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
757 }
758 tcg_temp_free(t0);
759 #if defined(TARGET_PPC64)
760 if (!ctx->sf_mode) {
761 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
762 }
763 #endif
764 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
765 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
766 }
767
768 /* Common add function */
769 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
770 TCGv arg2, bool add_ca, bool compute_ca,
771 bool compute_ov, bool compute_rc0)
772 {
773 TCGv t0 = ret;
774
775 if (((compute_ca && add_ca) || compute_ov)
776 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
777 t0 = tcg_temp_new();
778 }
779
780 if (compute_ca) {
781 TCGv zero = tcg_const_tl(0);
782 if (add_ca) {
783 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
784 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
785 } else {
786 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
787 }
788 tcg_temp_free(zero);
789 } else {
790 tcg_gen_add_tl(t0, arg1, arg2);
791 if (add_ca) {
792 tcg_gen_add_tl(t0, t0, cpu_ca);
793 }
794 }
795
796 if (compute_ov) {
797 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
798 }
799 if (unlikely(compute_rc0)) {
800 gen_set_Rc0(ctx, t0);
801 }
802
803 if (!TCGV_EQUAL(t0, ret)) {
804 tcg_gen_mov_tl(ret, t0);
805 tcg_temp_free(t0);
806 }
807 }
808 /* Add functions with two operands */
809 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
810 static void glue(gen_, name)(DisasContext *ctx) \
811 { \
812 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
813 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
814 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
815 }
816 /* Add functions with one operand and one immediate */
817 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
818 add_ca, compute_ca, compute_ov) \
819 static void glue(gen_, name)(DisasContext *ctx) \
820 { \
821 TCGv t0 = tcg_const_tl(const_val); \
822 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
823 cpu_gpr[rA(ctx->opcode)], t0, \
824 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
825 tcg_temp_free(t0); \
826 }
827
828 /* add add. addo addo. */
829 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
830 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
831 /* addc addc. addco addco. */
832 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
833 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
834 /* adde adde. addeo addeo. */
835 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
836 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
837 /* addme addme. addmeo addmeo. */
838 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
839 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
840 /* addze addze. addzeo addzeo.*/
841 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
842 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
843 /* addi */
844 static void gen_addi(DisasContext *ctx)
845 {
846 target_long simm = SIMM(ctx->opcode);
847
848 if (rA(ctx->opcode) == 0) {
849 /* li case */
850 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
851 } else {
852 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
853 cpu_gpr[rA(ctx->opcode)], simm);
854 }
855 }
856 /* addic addic.*/
857 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
858 {
859 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
860 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
861 c, 0, 1, 0, compute_rc0);
862 tcg_temp_free(c);
863 }
864
865 static void gen_addic(DisasContext *ctx)
866 {
867 gen_op_addic(ctx, 0);
868 }
869
870 static void gen_addic_(DisasContext *ctx)
871 {
872 gen_op_addic(ctx, 1);
873 }
874
875 /* addis */
876 static void gen_addis(DisasContext *ctx)
877 {
878 target_long simm = SIMM(ctx->opcode);
879
880 if (rA(ctx->opcode) == 0) {
881 /* lis case */
882 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
883 } else {
884 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
885 cpu_gpr[rA(ctx->opcode)], simm << 16);
886 }
887 }
888
889 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
890 TCGv arg2, int sign, int compute_ov)
891 {
892 int l1 = gen_new_label();
893 int l2 = gen_new_label();
894 TCGv_i32 t0 = tcg_temp_local_new_i32();
895 TCGv_i32 t1 = tcg_temp_local_new_i32();
896
897 tcg_gen_trunc_tl_i32(t0, arg1);
898 tcg_gen_trunc_tl_i32(t1, arg2);
899 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
900 if (sign) {
901 int l3 = gen_new_label();
902 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
903 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
904 gen_set_label(l3);
905 tcg_gen_div_i32(t0, t0, t1);
906 } else {
907 tcg_gen_divu_i32(t0, t0, t1);
908 }
909 if (compute_ov) {
910 tcg_gen_movi_tl(cpu_ov, 0);
911 }
912 tcg_gen_br(l2);
913 gen_set_label(l1);
914 if (sign) {
915 tcg_gen_sari_i32(t0, t0, 31);
916 } else {
917 tcg_gen_movi_i32(t0, 0);
918 }
919 if (compute_ov) {
920 tcg_gen_movi_tl(cpu_ov, 1);
921 tcg_gen_movi_tl(cpu_so, 1);
922 }
923 gen_set_label(l2);
924 tcg_gen_extu_i32_tl(ret, t0);
925 tcg_temp_free_i32(t0);
926 tcg_temp_free_i32(t1);
927 if (unlikely(Rc(ctx->opcode) != 0))
928 gen_set_Rc0(ctx, ret);
929 }
930 /* Div functions */
931 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
932 static void glue(gen_, name)(DisasContext *ctx) \
933 { \
934 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
935 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
936 sign, compute_ov); \
937 }
938 /* divwu divwu. divwuo divwuo. */
939 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
940 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
941 /* divw divw. divwo divwo. */
942 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
943 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
944 #if defined(TARGET_PPC64)
945 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
946 TCGv arg2, int sign, int compute_ov)
947 {
948 int l1 = gen_new_label();
949 int l2 = gen_new_label();
950
951 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
952 if (sign) {
953 int l3 = gen_new_label();
954 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
955 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
956 gen_set_label(l3);
957 tcg_gen_div_i64(ret, arg1, arg2);
958 } else {
959 tcg_gen_divu_i64(ret, arg1, arg2);
960 }
961 if (compute_ov) {
962 tcg_gen_movi_tl(cpu_ov, 0);
963 }
964 tcg_gen_br(l2);
965 gen_set_label(l1);
966 if (sign) {
967 tcg_gen_sari_i64(ret, arg1, 63);
968 } else {
969 tcg_gen_movi_i64(ret, 0);
970 }
971 if (compute_ov) {
972 tcg_gen_movi_tl(cpu_ov, 1);
973 tcg_gen_movi_tl(cpu_so, 1);
974 }
975 gen_set_label(l2);
976 if (unlikely(Rc(ctx->opcode) != 0))
977 gen_set_Rc0(ctx, ret);
978 }
979 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
980 static void glue(gen_, name)(DisasContext *ctx) \
981 { \
982 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
984 sign, compute_ov); \
985 }
986 /* divwu divwu. divwuo divwuo. */
987 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
988 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
989 /* divw divw. divwo divwo. */
990 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
991 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
992 #endif
993
994 /* mulhw mulhw. */
995 static void gen_mulhw(DisasContext *ctx)
996 {
997 TCGv_i32 t0 = tcg_temp_new_i32();
998 TCGv_i32 t1 = tcg_temp_new_i32();
999
1000 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1001 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1002 tcg_gen_muls2_i32(t0, t1, t0, t1);
1003 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1004 tcg_temp_free_i32(t0);
1005 tcg_temp_free_i32(t1);
1006 if (unlikely(Rc(ctx->opcode) != 0))
1007 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1008 }
1009
1010 /* mulhwu mulhwu. */
1011 static void gen_mulhwu(DisasContext *ctx)
1012 {
1013 TCGv_i32 t0 = tcg_temp_new_i32();
1014 TCGv_i32 t1 = tcg_temp_new_i32();
1015
1016 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1017 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1018 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1019 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1020 tcg_temp_free_i32(t0);
1021 tcg_temp_free_i32(t1);
1022 if (unlikely(Rc(ctx->opcode) != 0))
1023 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1024 }
1025
1026 /* mullw mullw. */
1027 static void gen_mullw(DisasContext *ctx)
1028 {
1029 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1030 cpu_gpr[rB(ctx->opcode)]);
1031 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1032 if (unlikely(Rc(ctx->opcode) != 0))
1033 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1034 }
1035
1036 /* mullwo mullwo. */
1037 static void gen_mullwo(DisasContext *ctx)
1038 {
1039 int l1;
1040 TCGv_i64 t0, t1;
1041
1042 t0 = tcg_temp_new_i64();
1043 t1 = tcg_temp_new_i64();
1044 l1 = gen_new_label();
1045 /* Start with XER OV disabled, the most likely case */
1046 tcg_gen_movi_tl(cpu_ov, 0);
1047 #if defined(TARGET_PPC64)
1048 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1049 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1050 #else
1051 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1052 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1053 #endif
1054 tcg_gen_mul_i64(t0, t0, t1);
1055 #if defined(TARGET_PPC64)
1056 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1057 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1058 #else
1059 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1060 tcg_gen_ext32s_i64(t1, t0);
1061 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1062 #endif
1063 tcg_gen_movi_tl(cpu_ov, 1);
1064 tcg_gen_movi_tl(cpu_so, 1);
1065 gen_set_label(l1);
1066 tcg_temp_free_i64(t0);
1067 tcg_temp_free_i64(t1);
1068 if (unlikely(Rc(ctx->opcode) != 0))
1069 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1070 }
1071
1072 /* mulli */
1073 static void gen_mulli(DisasContext *ctx)
1074 {
1075 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1076 SIMM(ctx->opcode));
1077 }
1078
1079 #if defined(TARGET_PPC64)
1080 /* mulhd mulhd. */
1081 static void gen_mulhd(DisasContext *ctx)
1082 {
1083 TCGv lo = tcg_temp_new();
1084 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1085 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1086 tcg_temp_free(lo);
1087 if (unlikely(Rc(ctx->opcode) != 0)) {
1088 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1089 }
1090 }
1091
1092 /* mulhdu mulhdu. */
1093 static void gen_mulhdu(DisasContext *ctx)
1094 {
1095 TCGv lo = tcg_temp_new();
1096 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1097 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1098 tcg_temp_free(lo);
1099 if (unlikely(Rc(ctx->opcode) != 0)) {
1100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1101 }
1102 }
1103
1104 /* mulld mulld. */
1105 static void gen_mulld(DisasContext *ctx)
1106 {
1107 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1108 cpu_gpr[rB(ctx->opcode)]);
1109 if (unlikely(Rc(ctx->opcode) != 0))
1110 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1111 }
1112
1113 /* mulldo mulldo. */
1114 static void gen_mulldo(DisasContext *ctx)
1115 {
1116 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1117 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1118 if (unlikely(Rc(ctx->opcode) != 0)) {
1119 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1120 }
1121 }
1122 #endif
1123
1124 /* Common subf function */
1125 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1126 TCGv arg2, bool add_ca, bool compute_ca,
1127 bool compute_ov, bool compute_rc0)
1128 {
1129 TCGv t0 = ret;
1130
1131 if (((add_ca && compute_ca) || compute_ov)
1132 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
1133 t0 = tcg_temp_new();
1134 }
1135
1136 if (add_ca) {
1137 /* dest = ~arg1 + arg2 + ca = arg2 - arg1 + ca - 1. */
1138 if (compute_ca) {
1139 TCGv zero;
1140 tcg_gen_subi_tl(cpu_ca, cpu_ca, 1);
1141 zero = tcg_const_tl(0);
1142 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1143 tcg_gen_sub2_tl(t0, cpu_ca, t0, cpu_ca, arg1, zero);
1144 tcg_temp_free(zero);
1145 } else {
1146 tcg_gen_sub_tl(t0, arg2, arg1);
1147 tcg_gen_add_tl(t0, t0, cpu_ca);
1148 tcg_gen_subi_tl(t0, t0, 1);
1149 }
1150 } else {
1151 if (compute_ca) {
1152 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1153 }
1154 tcg_gen_sub_tl(t0, arg2, arg1);
1155 }
1156
1157 if (compute_ov) {
1158 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1159 }
1160 if (unlikely(compute_rc0)) {
1161 gen_set_Rc0(ctx, t0);
1162 }
1163
1164 if (!TCGV_EQUAL(t0, ret)) {
1165 tcg_gen_mov_tl(ret, t0);
1166 tcg_temp_free(t0);
1167 }
1168 }
1169 /* Sub functions with Two operands functions */
1170 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1171 static void glue(gen_, name)(DisasContext *ctx) \
1172 { \
1173 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1174 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1175 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1176 }
1177 /* Sub functions with one operand and one immediate */
1178 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1179 add_ca, compute_ca, compute_ov) \
1180 static void glue(gen_, name)(DisasContext *ctx) \
1181 { \
1182 TCGv t0 = tcg_const_tl(const_val); \
1183 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1184 cpu_gpr[rA(ctx->opcode)], t0, \
1185 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1186 tcg_temp_free(t0); \
1187 }
1188 /* subf subf. subfo subfo. */
1189 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1190 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1191 /* subfc subfc. subfco subfco. */
1192 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1193 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1194 /* subfe subfe. subfeo subfo. */
1195 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1196 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1197 /* subfme subfme. subfmeo subfmeo. */
1198 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1199 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1200 /* subfze subfze. subfzeo subfzeo.*/
1201 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1202 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1203
1204 /* subfic */
1205 static void gen_subfic(DisasContext *ctx)
1206 {
1207 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1208 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1209 c, 0, 1, 0, 0);
1210 tcg_temp_free(c);
1211 }
1212
1213 /* neg neg. nego nego. */
1214 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1215 {
1216 TCGv zero = tcg_const_tl(0);
1217 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1218 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1219 tcg_temp_free(zero);
1220 }
1221
1222 static void gen_neg(DisasContext *ctx)
1223 {
1224 gen_op_arith_neg(ctx, 0);
1225 }
1226
1227 static void gen_nego(DisasContext *ctx)
1228 {
1229 gen_op_arith_neg(ctx, 1);
1230 }
1231
1232 /*** Integer logical ***/
1233 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1234 static void glue(gen_, name)(DisasContext *ctx) \
1235 { \
1236 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1237 cpu_gpr[rB(ctx->opcode)]); \
1238 if (unlikely(Rc(ctx->opcode) != 0)) \
1239 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1240 }
1241
1242 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1243 static void glue(gen_, name)(DisasContext *ctx) \
1244 { \
1245 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1246 if (unlikely(Rc(ctx->opcode) != 0)) \
1247 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1248 }
1249
1250 /* and & and. */
1251 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1252 /* andc & andc. */
1253 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1254
1255 /* andi. */
1256 static void gen_andi_(DisasContext *ctx)
1257 {
1258 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1259 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1260 }
1261
1262 /* andis. */
1263 static void gen_andis_(DisasContext *ctx)
1264 {
1265 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1266 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1267 }
1268
1269 /* cntlzw */
1270 static void gen_cntlzw(DisasContext *ctx)
1271 {
1272 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1273 if (unlikely(Rc(ctx->opcode) != 0))
1274 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1275 }
1276 /* eqv & eqv. */
1277 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1278 /* extsb & extsb. */
1279 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1280 /* extsh & extsh. */
1281 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1282 /* nand & nand. */
1283 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1284 /* nor & nor. */
1285 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1286
1287 /* or & or. */
1288 static void gen_or(DisasContext *ctx)
1289 {
1290 int rs, ra, rb;
1291
1292 rs = rS(ctx->opcode);
1293 ra = rA(ctx->opcode);
1294 rb = rB(ctx->opcode);
1295 /* Optimisation for mr. ri case */
1296 if (rs != ra || rs != rb) {
1297 if (rs != rb)
1298 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1299 else
1300 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1301 if (unlikely(Rc(ctx->opcode) != 0))
1302 gen_set_Rc0(ctx, cpu_gpr[ra]);
1303 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1304 gen_set_Rc0(ctx, cpu_gpr[rs]);
1305 #if defined(TARGET_PPC64)
1306 } else {
1307 int prio = 0;
1308
1309 switch (rs) {
1310 case 1:
1311 /* Set process priority to low */
1312 prio = 2;
1313 break;
1314 case 6:
1315 /* Set process priority to medium-low */
1316 prio = 3;
1317 break;
1318 case 2:
1319 /* Set process priority to normal */
1320 prio = 4;
1321 break;
1322 #if !defined(CONFIG_USER_ONLY)
1323 case 31:
1324 if (ctx->mem_idx > 0) {
1325 /* Set process priority to very low */
1326 prio = 1;
1327 }
1328 break;
1329 case 5:
1330 if (ctx->mem_idx > 0) {
1331 /* Set process priority to medium-hight */
1332 prio = 5;
1333 }
1334 break;
1335 case 3:
1336 if (ctx->mem_idx > 0) {
1337 /* Set process priority to high */
1338 prio = 6;
1339 }
1340 break;
1341 case 7:
1342 if (ctx->mem_idx > 1) {
1343 /* Set process priority to very high */
1344 prio = 7;
1345 }
1346 break;
1347 #endif
1348 default:
1349 /* nop */
1350 break;
1351 }
1352 if (prio) {
1353 TCGv t0 = tcg_temp_new();
1354 gen_load_spr(t0, SPR_PPR);
1355 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1356 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1357 gen_store_spr(SPR_PPR, t0);
1358 tcg_temp_free(t0);
1359 }
1360 #endif
1361 }
1362 }
1363 /* orc & orc. */
1364 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1365
1366 /* xor & xor. */
1367 static void gen_xor(DisasContext *ctx)
1368 {
1369 /* Optimisation for "set to zero" case */
1370 if (rS(ctx->opcode) != rB(ctx->opcode))
1371 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1372 else
1373 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1374 if (unlikely(Rc(ctx->opcode) != 0))
1375 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1376 }
1377
1378 /* ori */
1379 static void gen_ori(DisasContext *ctx)
1380 {
1381 target_ulong uimm = UIMM(ctx->opcode);
1382
1383 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1384 /* NOP */
1385 /* XXX: should handle special NOPs for POWER series */
1386 return;
1387 }
1388 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1389 }
1390
1391 /* oris */
1392 static void gen_oris(DisasContext *ctx)
1393 {
1394 target_ulong uimm = UIMM(ctx->opcode);
1395
1396 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1397 /* NOP */
1398 return;
1399 }
1400 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1401 }
1402
1403 /* xori */
1404 static void gen_xori(DisasContext *ctx)
1405 {
1406 target_ulong uimm = UIMM(ctx->opcode);
1407
1408 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1409 /* NOP */
1410 return;
1411 }
1412 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1413 }
1414
1415 /* xoris */
1416 static void gen_xoris(DisasContext *ctx)
1417 {
1418 target_ulong uimm = UIMM(ctx->opcode);
1419
1420 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1421 /* NOP */
1422 return;
1423 }
1424 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1425 }
1426
1427 /* popcntb : PowerPC 2.03 specification */
1428 static void gen_popcntb(DisasContext *ctx)
1429 {
1430 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1431 }
1432
1433 static void gen_popcntw(DisasContext *ctx)
1434 {
1435 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1436 }
1437
1438 #if defined(TARGET_PPC64)
1439 /* popcntd: PowerPC 2.06 specification */
1440 static void gen_popcntd(DisasContext *ctx)
1441 {
1442 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1443 }
1444 #endif
1445
1446 #if defined(TARGET_PPC64)
1447 /* extsw & extsw. */
1448 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1449
1450 /* cntlzd */
1451 static void gen_cntlzd(DisasContext *ctx)
1452 {
1453 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1454 if (unlikely(Rc(ctx->opcode) != 0))
1455 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1456 }
1457 #endif
1458
1459 /*** Integer rotate ***/
1460
1461 /* rlwimi & rlwimi. */
1462 static void gen_rlwimi(DisasContext *ctx)
1463 {
1464 uint32_t mb, me, sh;
1465
1466 mb = MB(ctx->opcode);
1467 me = ME(ctx->opcode);
1468 sh = SH(ctx->opcode);
1469 if (likely(sh == 0 && mb == 0 && me == 31)) {
1470 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1471 } else {
1472 target_ulong mask;
1473 TCGv t1;
1474 TCGv t0 = tcg_temp_new();
1475 #if defined(TARGET_PPC64)
1476 TCGv_i32 t2 = tcg_temp_new_i32();
1477 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1478 tcg_gen_rotli_i32(t2, t2, sh);
1479 tcg_gen_extu_i32_i64(t0, t2);
1480 tcg_temp_free_i32(t2);
1481 #else
1482 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1483 #endif
1484 #if defined(TARGET_PPC64)
1485 mb += 32;
1486 me += 32;
1487 #endif
1488 mask = MASK(mb, me);
1489 t1 = tcg_temp_new();
1490 tcg_gen_andi_tl(t0, t0, mask);
1491 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1492 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1493 tcg_temp_free(t0);
1494 tcg_temp_free(t1);
1495 }
1496 if (unlikely(Rc(ctx->opcode) != 0))
1497 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1498 }
1499
1500 /* rlwinm & rlwinm. */
1501 static void gen_rlwinm(DisasContext *ctx)
1502 {
1503 uint32_t mb, me, sh;
1504
1505 sh = SH(ctx->opcode);
1506 mb = MB(ctx->opcode);
1507 me = ME(ctx->opcode);
1508
1509 if (likely(mb == 0 && me == (31 - sh))) {
1510 if (likely(sh == 0)) {
1511 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1512 } else {
1513 TCGv t0 = tcg_temp_new();
1514 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1515 tcg_gen_shli_tl(t0, t0, sh);
1516 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1517 tcg_temp_free(t0);
1518 }
1519 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1520 TCGv t0 = tcg_temp_new();
1521 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1522 tcg_gen_shri_tl(t0, t0, mb);
1523 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1524 tcg_temp_free(t0);
1525 } else {
1526 TCGv t0 = tcg_temp_new();
1527 #if defined(TARGET_PPC64)
1528 TCGv_i32 t1 = tcg_temp_new_i32();
1529 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1530 tcg_gen_rotli_i32(t1, t1, sh);
1531 tcg_gen_extu_i32_i64(t0, t1);
1532 tcg_temp_free_i32(t1);
1533 #else
1534 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1535 #endif
1536 #if defined(TARGET_PPC64)
1537 mb += 32;
1538 me += 32;
1539 #endif
1540 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1541 tcg_temp_free(t0);
1542 }
1543 if (unlikely(Rc(ctx->opcode) != 0))
1544 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1545 }
1546
1547 /* rlwnm & rlwnm. */
1548 static void gen_rlwnm(DisasContext *ctx)
1549 {
1550 uint32_t mb, me;
1551 TCGv t0;
1552 #if defined(TARGET_PPC64)
1553 TCGv_i32 t1, t2;
1554 #endif
1555
1556 mb = MB(ctx->opcode);
1557 me = ME(ctx->opcode);
1558 t0 = tcg_temp_new();
1559 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1560 #if defined(TARGET_PPC64)
1561 t1 = tcg_temp_new_i32();
1562 t2 = tcg_temp_new_i32();
1563 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1564 tcg_gen_trunc_i64_i32(t2, t0);
1565 tcg_gen_rotl_i32(t1, t1, t2);
1566 tcg_gen_extu_i32_i64(t0, t1);
1567 tcg_temp_free_i32(t1);
1568 tcg_temp_free_i32(t2);
1569 #else
1570 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1571 #endif
1572 if (unlikely(mb != 0 || me != 31)) {
1573 #if defined(TARGET_PPC64)
1574 mb += 32;
1575 me += 32;
1576 #endif
1577 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1578 } else {
1579 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1580 }
1581 tcg_temp_free(t0);
1582 if (unlikely(Rc(ctx->opcode) != 0))
1583 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1584 }
1585
1586 #if defined(TARGET_PPC64)
1587 #define GEN_PPC64_R2(name, opc1, opc2) \
1588 static void glue(gen_, name##0)(DisasContext *ctx) \
1589 { \
1590 gen_##name(ctx, 0); \
1591 } \
1592 \
1593 static void glue(gen_, name##1)(DisasContext *ctx) \
1594 { \
1595 gen_##name(ctx, 1); \
1596 }
1597 #define GEN_PPC64_R4(name, opc1, opc2) \
1598 static void glue(gen_, name##0)(DisasContext *ctx) \
1599 { \
1600 gen_##name(ctx, 0, 0); \
1601 } \
1602 \
1603 static void glue(gen_, name##1)(DisasContext *ctx) \
1604 { \
1605 gen_##name(ctx, 0, 1); \
1606 } \
1607 \
1608 static void glue(gen_, name##2)(DisasContext *ctx) \
1609 { \
1610 gen_##name(ctx, 1, 0); \
1611 } \
1612 \
1613 static void glue(gen_, name##3)(DisasContext *ctx) \
1614 { \
1615 gen_##name(ctx, 1, 1); \
1616 }
1617
1618 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1619 uint32_t sh)
1620 {
1621 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1622 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1623 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1624 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1625 } else {
1626 TCGv t0 = tcg_temp_new();
1627 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1628 if (likely(mb == 0 && me == 63)) {
1629 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1630 } else {
1631 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1632 }
1633 tcg_temp_free(t0);
1634 }
1635 if (unlikely(Rc(ctx->opcode) != 0))
1636 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1637 }
1638 /* rldicl - rldicl. */
1639 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1640 {
1641 uint32_t sh, mb;
1642
1643 sh = SH(ctx->opcode) | (shn << 5);
1644 mb = MB(ctx->opcode) | (mbn << 5);
1645 gen_rldinm(ctx, mb, 63, sh);
1646 }
1647 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1648 /* rldicr - rldicr. */
1649 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1650 {
1651 uint32_t sh, me;
1652
1653 sh = SH(ctx->opcode) | (shn << 5);
1654 me = MB(ctx->opcode) | (men << 5);
1655 gen_rldinm(ctx, 0, me, sh);
1656 }
1657 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1658 /* rldic - rldic. */
1659 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1660 {
1661 uint32_t sh, mb;
1662
1663 sh = SH(ctx->opcode) | (shn << 5);
1664 mb = MB(ctx->opcode) | (mbn << 5);
1665 gen_rldinm(ctx, mb, 63 - sh, sh);
1666 }
1667 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1668
1669 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1670 {
1671 TCGv t0;
1672
1673 mb = MB(ctx->opcode);
1674 me = ME(ctx->opcode);
1675 t0 = tcg_temp_new();
1676 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1677 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1678 if (unlikely(mb != 0 || me != 63)) {
1679 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1680 } else {
1681 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1682 }
1683 tcg_temp_free(t0);
1684 if (unlikely(Rc(ctx->opcode) != 0))
1685 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1686 }
1687
1688 /* rldcl - rldcl. */
1689 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1690 {
1691 uint32_t mb;
1692
1693 mb = MB(ctx->opcode) | (mbn << 5);
1694 gen_rldnm(ctx, mb, 63);
1695 }
1696 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1697 /* rldcr - rldcr. */
1698 static inline void gen_rldcr(DisasContext *ctx, int men)
1699 {
1700 uint32_t me;
1701
1702 me = MB(ctx->opcode) | (men << 5);
1703 gen_rldnm(ctx, 0, me);
1704 }
1705 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1706 /* rldimi - rldimi. */
1707 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1708 {
1709 uint32_t sh, mb, me;
1710
1711 sh = SH(ctx->opcode) | (shn << 5);
1712 mb = MB(ctx->opcode) | (mbn << 5);
1713 me = 63 - sh;
1714 if (unlikely(sh == 0 && mb == 0)) {
1715 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1716 } else {
1717 TCGv t0, t1;
1718 target_ulong mask;
1719
1720 t0 = tcg_temp_new();
1721 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1722 t1 = tcg_temp_new();
1723 mask = MASK(mb, me);
1724 tcg_gen_andi_tl(t0, t0, mask);
1725 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1726 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1727 tcg_temp_free(t0);
1728 tcg_temp_free(t1);
1729 }
1730 if (unlikely(Rc(ctx->opcode) != 0))
1731 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1732 }
1733 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1734 #endif
1735
1736 /*** Integer shift ***/
1737
1738 /* slw & slw. */
1739 static void gen_slw(DisasContext *ctx)
1740 {
1741 TCGv t0, t1;
1742
1743 t0 = tcg_temp_new();
1744 /* AND rS with a mask that is 0 when rB >= 0x20 */
1745 #if defined(TARGET_PPC64)
1746 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1747 tcg_gen_sari_tl(t0, t0, 0x3f);
1748 #else
1749 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1750 tcg_gen_sari_tl(t0, t0, 0x1f);
1751 #endif
1752 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1753 t1 = tcg_temp_new();
1754 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1755 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1756 tcg_temp_free(t1);
1757 tcg_temp_free(t0);
1758 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1759 if (unlikely(Rc(ctx->opcode) != 0))
1760 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1761 }
1762
1763 /* sraw & sraw. */
1764 static void gen_sraw(DisasContext *ctx)
1765 {
1766 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1767 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1768 if (unlikely(Rc(ctx->opcode) != 0))
1769 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1770 }
1771
1772 /* srawi & srawi. */
1773 static void gen_srawi(DisasContext *ctx)
1774 {
1775 int sh = SH(ctx->opcode);
1776 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1777 TCGv src = cpu_gpr[rS(ctx->opcode)];
1778 if (sh == 0) {
1779 tcg_gen_mov_tl(dst, src);
1780 tcg_gen_movi_tl(cpu_ca, 0);
1781 } else {
1782 TCGv t0;
1783 tcg_gen_ext32s_tl(dst, src);
1784 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1785 t0 = tcg_temp_new();
1786 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1787 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1788 tcg_temp_free(t0);
1789 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1790 tcg_gen_sari_tl(dst, dst, sh);
1791 }
1792 if (unlikely(Rc(ctx->opcode) != 0)) {
1793 gen_set_Rc0(ctx, dst);
1794 }
1795 }
1796
1797 /* srw & srw. */
1798 static void gen_srw(DisasContext *ctx)
1799 {
1800 TCGv t0, t1;
1801
1802 t0 = tcg_temp_new();
1803 /* AND rS with a mask that is 0 when rB >= 0x20 */
1804 #if defined(TARGET_PPC64)
1805 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1806 tcg_gen_sari_tl(t0, t0, 0x3f);
1807 #else
1808 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1809 tcg_gen_sari_tl(t0, t0, 0x1f);
1810 #endif
1811 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1812 tcg_gen_ext32u_tl(t0, t0);
1813 t1 = tcg_temp_new();
1814 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1815 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1816 tcg_temp_free(t1);
1817 tcg_temp_free(t0);
1818 if (unlikely(Rc(ctx->opcode) != 0))
1819 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1820 }
1821
1822 #if defined(TARGET_PPC64)
1823 /* sld & sld. */
1824 static void gen_sld(DisasContext *ctx)
1825 {
1826 TCGv t0, t1;
1827
1828 t0 = tcg_temp_new();
1829 /* AND rS with a mask that is 0 when rB >= 0x40 */
1830 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1831 tcg_gen_sari_tl(t0, t0, 0x3f);
1832 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1833 t1 = tcg_temp_new();
1834 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1835 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1836 tcg_temp_free(t1);
1837 tcg_temp_free(t0);
1838 if (unlikely(Rc(ctx->opcode) != 0))
1839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1840 }
1841
1842 /* srad & srad. */
1843 static void gen_srad(DisasContext *ctx)
1844 {
1845 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1846 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1847 if (unlikely(Rc(ctx->opcode) != 0))
1848 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1849 }
1850 /* sradi & sradi. */
1851 static inline void gen_sradi(DisasContext *ctx, int n)
1852 {
1853 int sh = SH(ctx->opcode) + (n << 5);
1854 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1855 TCGv src = cpu_gpr[rS(ctx->opcode)];
1856 if (sh == 0) {
1857 tcg_gen_mov_tl(dst, src);
1858 tcg_gen_movi_tl(cpu_ca, 0);
1859 } else {
1860 TCGv t0;
1861 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1862 t0 = tcg_temp_new();
1863 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1864 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1865 tcg_temp_free(t0);
1866 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1867 tcg_gen_sari_tl(dst, src, sh);
1868 }
1869 if (unlikely(Rc(ctx->opcode) != 0)) {
1870 gen_set_Rc0(ctx, dst);
1871 }
1872 }
1873
1874 static void gen_sradi0(DisasContext *ctx)
1875 {
1876 gen_sradi(ctx, 0);
1877 }
1878
1879 static void gen_sradi1(DisasContext *ctx)
1880 {
1881 gen_sradi(ctx, 1);
1882 }
1883
1884 /* srd & srd. */
1885 static void gen_srd(DisasContext *ctx)
1886 {
1887 TCGv t0, t1;
1888
1889 t0 = tcg_temp_new();
1890 /* AND rS with a mask that is 0 when rB >= 0x40 */
1891 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1892 tcg_gen_sari_tl(t0, t0, 0x3f);
1893 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1894 t1 = tcg_temp_new();
1895 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1896 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1897 tcg_temp_free(t1);
1898 tcg_temp_free(t0);
1899 if (unlikely(Rc(ctx->opcode) != 0))
1900 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1901 }
1902 #endif
1903
1904 /*** Floating-Point arithmetic ***/
1905 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1906 static void gen_f##name(DisasContext *ctx) \
1907 { \
1908 if (unlikely(!ctx->fpu_enabled)) { \
1909 gen_exception(ctx, POWERPC_EXCP_FPU); \
1910 return; \
1911 } \
1912 /* NIP cannot be restored if the memory exception comes from an helper */ \
1913 gen_update_nip(ctx, ctx->nip - 4); \
1914 gen_reset_fpstatus(); \
1915 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1916 cpu_fpr[rA(ctx->opcode)], \
1917 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1918 if (isfloat) { \
1919 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1920 cpu_fpr[rD(ctx->opcode)]); \
1921 } \
1922 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1923 Rc(ctx->opcode) != 0); \
1924 }
1925
1926 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1927 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1928 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1929
1930 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1931 static void gen_f##name(DisasContext *ctx) \
1932 { \
1933 if (unlikely(!ctx->fpu_enabled)) { \
1934 gen_exception(ctx, POWERPC_EXCP_FPU); \
1935 return; \
1936 } \
1937 /* NIP cannot be restored if the memory exception comes from an helper */ \
1938 gen_update_nip(ctx, ctx->nip - 4); \
1939 gen_reset_fpstatus(); \
1940 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1941 cpu_fpr[rA(ctx->opcode)], \
1942 cpu_fpr[rB(ctx->opcode)]); \
1943 if (isfloat) { \
1944 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1945 cpu_fpr[rD(ctx->opcode)]); \
1946 } \
1947 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1948 set_fprf, Rc(ctx->opcode) != 0); \
1949 }
1950 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1951 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1952 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1953
1954 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1955 static void gen_f##name(DisasContext *ctx) \
1956 { \
1957 if (unlikely(!ctx->fpu_enabled)) { \
1958 gen_exception(ctx, POWERPC_EXCP_FPU); \
1959 return; \
1960 } \
1961 /* NIP cannot be restored if the memory exception comes from an helper */ \
1962 gen_update_nip(ctx, ctx->nip - 4); \
1963 gen_reset_fpstatus(); \
1964 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1965 cpu_fpr[rA(ctx->opcode)], \
1966 cpu_fpr[rC(ctx->opcode)]); \
1967 if (isfloat) { \
1968 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1969 cpu_fpr[rD(ctx->opcode)]); \
1970 } \
1971 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1972 set_fprf, Rc(ctx->opcode) != 0); \
1973 }
1974 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1975 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1976 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1977
1978 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1979 static void gen_f##name(DisasContext *ctx) \
1980 { \
1981 if (unlikely(!ctx->fpu_enabled)) { \
1982 gen_exception(ctx, POWERPC_EXCP_FPU); \
1983 return; \
1984 } \
1985 /* NIP cannot be restored if the memory exception comes from an helper */ \
1986 gen_update_nip(ctx, ctx->nip - 4); \
1987 gen_reset_fpstatus(); \
1988 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1989 cpu_fpr[rB(ctx->opcode)]); \
1990 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1991 set_fprf, Rc(ctx->opcode) != 0); \
1992 }
1993
1994 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1995 static void gen_f##name(DisasContext *ctx) \
1996 { \
1997 if (unlikely(!ctx->fpu_enabled)) { \
1998 gen_exception(ctx, POWERPC_EXCP_FPU); \
1999 return; \
2000 } \
2001 /* NIP cannot be restored if the memory exception comes from an helper */ \
2002 gen_update_nip(ctx, ctx->nip - 4); \
2003 gen_reset_fpstatus(); \
2004 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2005 cpu_fpr[rB(ctx->opcode)]); \
2006 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2007 set_fprf, Rc(ctx->opcode) != 0); \
2008 }
2009
2010 /* fadd - fadds */
2011 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2012 /* fdiv - fdivs */
2013 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2014 /* fmul - fmuls */
2015 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2016
2017 /* fre */
2018 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2019
2020 /* fres */
2021 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2022
2023 /* frsqrte */
2024 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2025
2026 /* frsqrtes */
2027 static void gen_frsqrtes(DisasContext *ctx)
2028 {
2029 if (unlikely(!ctx->fpu_enabled)) {
2030 gen_exception(ctx, POWERPC_EXCP_FPU);
2031 return;
2032 }
2033 /* NIP cannot be restored if the memory exception comes from an helper */
2034 gen_update_nip(ctx, ctx->nip - 4);
2035 gen_reset_fpstatus();
2036 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2037 cpu_fpr[rB(ctx->opcode)]);
2038 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2039 cpu_fpr[rD(ctx->opcode)]);
2040 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2041 }
2042
2043 /* fsel */
2044 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2045 /* fsub - fsubs */
2046 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2047 /* Optional: */
2048
2049 /* fsqrt */
2050 static void gen_fsqrt(DisasContext *ctx)
2051 {
2052 if (unlikely(!ctx->fpu_enabled)) {
2053 gen_exception(ctx, POWERPC_EXCP_FPU);
2054 return;
2055 }
2056 /* NIP cannot be restored if the memory exception comes from an helper */
2057 gen_update_nip(ctx, ctx->nip - 4);
2058 gen_reset_fpstatus();
2059 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2060 cpu_fpr[rB(ctx->opcode)]);
2061 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2062 }
2063
2064 static void gen_fsqrts(DisasContext *ctx)
2065 {
2066 if (unlikely(!ctx->fpu_enabled)) {
2067 gen_exception(ctx, POWERPC_EXCP_FPU);
2068 return;
2069 }
2070 /* NIP cannot be restored if the memory exception comes from an helper */
2071 gen_update_nip(ctx, ctx->nip - 4);
2072 gen_reset_fpstatus();
2073 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2074 cpu_fpr[rB(ctx->opcode)]);
2075 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2076 cpu_fpr[rD(ctx->opcode)]);
2077 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2078 }
2079
2080 /*** Floating-Point multiply-and-add ***/
2081 /* fmadd - fmadds */
2082 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2083 /* fmsub - fmsubs */
2084 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2085 /* fnmadd - fnmadds */
2086 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2087 /* fnmsub - fnmsubs */
2088 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2089
2090 /*** Floating-Point round & convert ***/
2091 /* fctiw */
2092 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2093 /* fctiwz */
2094 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2095 /* frsp */
2096 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2097 #if defined(TARGET_PPC64)
2098 /* fcfid */
2099 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2100 /* fctid */
2101 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2102 /* fctidz */
2103 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2104 #endif
2105
2106 /* frin */
2107 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2108 /* friz */
2109 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2110 /* frip */
2111 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2112 /* frim */
2113 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2114
2115 /*** Floating-Point compare ***/
2116
2117 /* fcmpo */
2118 static void gen_fcmpo(DisasContext *ctx)
2119 {
2120 TCGv_i32 crf;
2121 if (unlikely(!ctx->fpu_enabled)) {
2122 gen_exception(ctx, POWERPC_EXCP_FPU);
2123 return;
2124 }
2125 /* NIP cannot be restored if the memory exception comes from an helper */
2126 gen_update_nip(ctx, ctx->nip - 4);
2127 gen_reset_fpstatus();
2128 crf = tcg_const_i32(crfD(ctx->opcode));
2129 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2130 cpu_fpr[rB(ctx->opcode)], crf);
2131 tcg_temp_free_i32(crf);
2132 gen_helper_float_check_status(cpu_env);
2133 }
2134
2135 /* fcmpu */
2136 static void gen_fcmpu(DisasContext *ctx)
2137 {
2138 TCGv_i32 crf;
2139 if (unlikely(!ctx->fpu_enabled)) {
2140 gen_exception(ctx, POWERPC_EXCP_FPU);
2141 return;
2142 }
2143 /* NIP cannot be restored if the memory exception comes from an helper */
2144 gen_update_nip(ctx, ctx->nip - 4);
2145 gen_reset_fpstatus();
2146 crf = tcg_const_i32(crfD(ctx->opcode));
2147 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2148 cpu_fpr[rB(ctx->opcode)], crf);
2149 tcg_temp_free_i32(crf);
2150 gen_helper_float_check_status(cpu_env);
2151 }
2152
2153 /*** Floating-point move ***/
2154 /* fabs */
2155 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2156 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2157
2158 /* fmr - fmr. */
2159 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2160 static void gen_fmr(DisasContext *ctx)
2161 {
2162 if (unlikely(!ctx->fpu_enabled)) {
2163 gen_exception(ctx, POWERPC_EXCP_FPU);
2164 return;
2165 }
2166 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2167 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2168 }
2169
2170 /* fnabs */
2171 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2172 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2173 /* fneg */
2174 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2175 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2176
2177 /*** Floating-Point status & ctrl register ***/
2178
2179 /* mcrfs */
2180 static void gen_mcrfs(DisasContext *ctx)
2181 {
2182 TCGv tmp = tcg_temp_new();
2183 int bfa;
2184
2185 if (unlikely(!ctx->fpu_enabled)) {
2186 gen_exception(ctx, POWERPC_EXCP_FPU);
2187 return;
2188 }
2189 bfa = 4 * (7 - crfS(ctx->opcode));
2190 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2191 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2192 tcg_temp_free(tmp);
2193 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2194 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2195 }
2196
2197 /* mffs */
2198 static void gen_mffs(DisasContext *ctx)
2199 {
2200 if (unlikely(!ctx->fpu_enabled)) {
2201 gen_exception(ctx, POWERPC_EXCP_FPU);
2202 return;
2203 }
2204 gen_reset_fpstatus();
2205 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2206 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2207 }
2208
2209 /* mtfsb0 */
2210 static void gen_mtfsb0(DisasContext *ctx)
2211 {
2212 uint8_t crb;
2213
2214 if (unlikely(!ctx->fpu_enabled)) {
2215 gen_exception(ctx, POWERPC_EXCP_FPU);
2216 return;
2217 }
2218 crb = 31 - crbD(ctx->opcode);
2219 gen_reset_fpstatus();
2220 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2221 TCGv_i32 t0;
2222 /* NIP cannot be restored if the memory exception comes from an helper */
2223 gen_update_nip(ctx, ctx->nip - 4);
2224 t0 = tcg_const_i32(crb);
2225 gen_helper_fpscr_clrbit(cpu_env, t0);
2226 tcg_temp_free_i32(t0);
2227 }
2228 if (unlikely(Rc(ctx->opcode) != 0)) {
2229 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2230 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2231 }
2232 }
2233
2234 /* mtfsb1 */
2235 static void gen_mtfsb1(DisasContext *ctx)
2236 {
2237 uint8_t crb;
2238
2239 if (unlikely(!ctx->fpu_enabled)) {
2240 gen_exception(ctx, POWERPC_EXCP_FPU);
2241 return;
2242 }
2243 crb = 31 - crbD(ctx->opcode);
2244 gen_reset_fpstatus();
2245 /* XXX: we pretend we can only do IEEE floating-point computations */
2246 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2247 TCGv_i32 t0;
2248 /* NIP cannot be restored if the memory exception comes from an helper */
2249 gen_update_nip(ctx, ctx->nip - 4);
2250 t0 = tcg_const_i32(crb);
2251 gen_helper_fpscr_setbit(cpu_env, t0);
2252 tcg_temp_free_i32(t0);
2253 }
2254 if (unlikely(Rc(ctx->opcode) != 0)) {
2255 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2256 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2257 }
2258 /* We can raise a differed exception */
2259 gen_helper_float_check_status(cpu_env);
2260 }
2261
2262 /* mtfsf */
2263 static void gen_mtfsf(DisasContext *ctx)
2264 {
2265 TCGv_i32 t0;
2266 int L = ctx->opcode & 0x02000000;
2267
2268 if (unlikely(!ctx->fpu_enabled)) {
2269 gen_exception(ctx, POWERPC_EXCP_FPU);
2270 return;
2271 }
2272 /* NIP cannot be restored if the memory exception comes from an helper */
2273 gen_update_nip(ctx, ctx->nip - 4);
2274 gen_reset_fpstatus();
2275 if (L)
2276 t0 = tcg_const_i32(0xff);
2277 else
2278 t0 = tcg_const_i32(FM(ctx->opcode));
2279 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2280 tcg_temp_free_i32(t0);
2281 if (unlikely(Rc(ctx->opcode) != 0)) {
2282 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2283 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2284 }
2285 /* We can raise a differed exception */
2286 gen_helper_float_check_status(cpu_env);
2287 }
2288
2289 /* mtfsfi */
2290 static void gen_mtfsfi(DisasContext *ctx)
2291 {
2292 int bf, sh;
2293 TCGv_i64 t0;
2294 TCGv_i32 t1;
2295
2296 if (unlikely(!ctx->fpu_enabled)) {
2297 gen_exception(ctx, POWERPC_EXCP_FPU);
2298 return;
2299 }
2300 bf = crbD(ctx->opcode) >> 2;
2301 sh = 7 - bf;
2302 /* NIP cannot be restored if the memory exception comes from an helper */
2303 gen_update_nip(ctx, ctx->nip - 4);
2304 gen_reset_fpstatus();
2305 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2306 t1 = tcg_const_i32(1 << sh);
2307 gen_helper_store_fpscr(cpu_env, t0, t1);
2308 tcg_temp_free_i64(t0);
2309 tcg_temp_free_i32(t1);
2310 if (unlikely(Rc(ctx->opcode) != 0)) {
2311 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2312 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2313 }
2314 /* We can raise a differed exception */
2315 gen_helper_float_check_status(cpu_env);
2316 }
2317
2318 /*** Addressing modes ***/
2319 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2320 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2321 target_long maskl)
2322 {
2323 target_long simm = SIMM(ctx->opcode);
2324
2325 simm &= ~maskl;
2326 if (rA(ctx->opcode) == 0) {
2327 #if defined(TARGET_PPC64)
2328 if (!ctx->sf_mode) {
2329 tcg_gen_movi_tl(EA, (uint32_t)simm);
2330 } else
2331 #endif
2332 tcg_gen_movi_tl(EA, simm);
2333 } else if (likely(simm != 0)) {
2334 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2335 #if defined(TARGET_PPC64)
2336 if (!ctx->sf_mode) {
2337 tcg_gen_ext32u_tl(EA, EA);
2338 }
2339 #endif
2340 } else {
2341 #if defined(TARGET_PPC64)
2342 if (!ctx->sf_mode) {
2343 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2344 } else
2345 #endif
2346 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2347 }
2348 }
2349
2350 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2351 {
2352 if (rA(ctx->opcode) == 0) {
2353 #if defined(TARGET_PPC64)
2354 if (!ctx->sf_mode) {
2355 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2356 } else
2357 #endif
2358 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2359 } else {
2360 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2361 #if defined(TARGET_PPC64)
2362 if (!ctx->sf_mode) {
2363 tcg_gen_ext32u_tl(EA, EA);
2364 }
2365 #endif
2366 }
2367 }
2368
2369 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2370 {
2371 if (rA(ctx->opcode) == 0) {
2372 tcg_gen_movi_tl(EA, 0);
2373 } else {
2374 #if defined(TARGET_PPC64)
2375 if (!ctx->sf_mode) {
2376 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2377 } else
2378 #endif
2379 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2380 }
2381 }
2382
2383 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2384 target_long val)
2385 {
2386 tcg_gen_addi_tl(ret, arg1, val);
2387 #if defined(TARGET_PPC64)
2388 if (!ctx->sf_mode) {
2389 tcg_gen_ext32u_tl(ret, ret);
2390 }
2391 #endif
2392 }
2393
2394 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2395 {
2396 int l1 = gen_new_label();
2397 TCGv t0 = tcg_temp_new();
2398 TCGv_i32 t1, t2;
2399 /* NIP cannot be restored if the memory exception comes from an helper */
2400 gen_update_nip(ctx, ctx->nip - 4);
2401 tcg_gen_andi_tl(t0, EA, mask);
2402 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2403 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2404 t2 = tcg_const_i32(0);
2405 gen_helper_raise_exception_err(cpu_env, t1, t2);
2406 tcg_temp_free_i32(t1);
2407 tcg_temp_free_i32(t2);
2408 gen_set_label(l1);
2409 tcg_temp_free(t0);
2410 }
2411
2412 /*** Integer load ***/
2413 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2414 {
2415 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2416 }
2417
2418 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2419 {
2420 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2421 }
2422
2423 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2424 {
2425 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2426 if (unlikely(ctx->le_mode)) {
2427 tcg_gen_bswap16_tl(arg1, arg1);
2428 }
2429 }
2430
2431 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2432 {
2433 if (unlikely(ctx->le_mode)) {
2434 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2435 tcg_gen_bswap16_tl(arg1, arg1);
2436 tcg_gen_ext16s_tl(arg1, arg1);
2437 } else {
2438 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2439 }
2440 }
2441
2442 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2443 {
2444 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2445 if (unlikely(ctx->le_mode)) {
2446 tcg_gen_bswap32_tl(arg1, arg1);
2447 }
2448 }
2449
2450 #if defined(TARGET_PPC64)
2451 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2452 {
2453 if (unlikely(ctx->le_mode)) {
2454 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2455 tcg_gen_bswap32_tl(arg1, arg1);
2456 tcg_gen_ext32s_tl(arg1, arg1);
2457 } else
2458 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2459 }
2460 #endif
2461
2462 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2463 {
2464 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2465 if (unlikely(ctx->le_mode)) {
2466 tcg_gen_bswap64_i64(arg1, arg1);
2467 }
2468 }
2469
2470 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2471 {
2472 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2473 }
2474
2475 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2476 {
2477 if (unlikely(ctx->le_mode)) {
2478 TCGv t0 = tcg_temp_new();
2479 tcg_gen_ext16u_tl(t0, arg1);
2480 tcg_gen_bswap16_tl(t0, t0);
2481 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2482 tcg_temp_free(t0);
2483 } else {
2484 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2485 }
2486 }
2487
2488 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2489 {
2490 if (unlikely(ctx->le_mode)) {
2491 TCGv t0 = tcg_temp_new();
2492 tcg_gen_ext32u_tl(t0, arg1);
2493 tcg_gen_bswap32_tl(t0, t0);
2494 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2495 tcg_temp_free(t0);
2496 } else {
2497 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2498 }
2499 }
2500
2501 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2502 {
2503 if (unlikely(ctx->le_mode)) {
2504 TCGv_i64 t0 = tcg_temp_new_i64();
2505 tcg_gen_bswap64_i64(t0, arg1);
2506 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2507 tcg_temp_free_i64(t0);
2508 } else
2509 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2510 }
2511
2512 #define GEN_LD(name, ldop, opc, type) \
2513 static void glue(gen_, name)(DisasContext *ctx) \
2514 { \
2515 TCGv EA; \
2516 gen_set_access_type(ctx, ACCESS_INT); \
2517 EA = tcg_temp_new(); \
2518 gen_addr_imm_index(ctx, EA, 0); \
2519 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2520 tcg_temp_free(EA); \
2521 }
2522
2523 #define GEN_LDU(name, ldop, opc, type) \
2524 static void glue(gen_, name##u)(DisasContext *ctx) \
2525 { \
2526 TCGv EA; \
2527 if (unlikely(rA(ctx->opcode) == 0 || \
2528 rA(ctx->opcode) == rD(ctx->opcode))) { \
2529 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2530 return; \
2531 } \
2532 gen_set_access_type(ctx, ACCESS_INT); \
2533 EA = tcg_temp_new(); \
2534 if (type == PPC_64B) \
2535 gen_addr_imm_index(ctx, EA, 0x03); \
2536 else \
2537 gen_addr_imm_index(ctx, EA, 0); \
2538 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2539 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2540 tcg_temp_free(EA); \
2541 }
2542
2543 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2544 static void glue(gen_, name##ux)(DisasContext *ctx) \
2545 { \
2546 TCGv EA; \
2547 if (unlikely(rA(ctx->opcode) == 0 || \
2548 rA(ctx->opcode) == rD(ctx->opcode))) { \
2549 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2550 return; \
2551 } \
2552 gen_set_access_type(ctx, ACCESS_INT); \
2553 EA = tcg_temp_new(); \
2554 gen_addr_reg_index(ctx, EA); \
2555 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2556 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2557 tcg_temp_free(EA); \
2558 }
2559
2560 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2561 static void glue(gen_, name##x)(DisasContext *ctx) \
2562 { \
2563 TCGv EA; \
2564 gen_set_access_type(ctx, ACCESS_INT); \
2565 EA = tcg_temp_new(); \
2566 gen_addr_reg_index(ctx, EA); \
2567 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2568 tcg_temp_free(EA); \
2569 }
2570 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2571 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2572
2573 #define GEN_LDS(name, ldop, op, type) \
2574 GEN_LD(name, ldop, op | 0x20, type); \
2575 GEN_LDU(name, ldop, op | 0x21, type); \
2576 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2577 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2578
2579 /* lbz lbzu lbzux lbzx */
2580 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2581 /* lha lhau lhaux lhax */
2582 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2583 /* lhz lhzu lhzux lhzx */
2584 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2585 /* lwz lwzu lwzux lwzx */
2586 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2587 #if defined(TARGET_PPC64)
2588 /* lwaux */
2589 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2590 /* lwax */
2591 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2592 /* ldux */
2593 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2594 /* ldx */
2595 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2596
2597 static void gen_ld(DisasContext *ctx)
2598 {
2599 TCGv EA;
2600 if (Rc(ctx->opcode)) {
2601 if (unlikely(rA(ctx->opcode) == 0 ||
2602 rA(ctx->opcode) == rD(ctx->opcode))) {
2603 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2604 return;
2605 }
2606 }
2607 gen_set_access_type(ctx, ACCESS_INT);
2608 EA = tcg_temp_new();
2609 gen_addr_imm_index(ctx, EA, 0x03);
2610 if (ctx->opcode & 0x02) {
2611 /* lwa (lwau is undefined) */
2612 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2613 } else {
2614 /* ld - ldu */
2615 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2616 }
2617 if (Rc(ctx->opcode))
2618 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2619 tcg_temp_free(EA);
2620 }
2621
2622 /* lq */
2623 static void gen_lq(DisasContext *ctx)
2624 {
2625 #if defined(CONFIG_USER_ONLY)
2626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2627 #else
2628 int ra, rd;
2629 TCGv EA;
2630
2631 /* Restore CPU state */
2632 if (unlikely(ctx->mem_idx == 0)) {
2633 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2634 return;
2635 }
2636 ra = rA(ctx->opcode);
2637 rd = rD(ctx->opcode);
2638 if (unlikely((rd & 1) || rd == ra)) {
2639 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2640 return;
2641 }
2642 if (unlikely(ctx->le_mode)) {
2643 /* Little-endian mode is not handled */
2644 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2645 return;
2646 }
2647 gen_set_access_type(ctx, ACCESS_INT);
2648 EA = tcg_temp_new();
2649 gen_addr_imm_index(ctx, EA, 0x0F);
2650 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2651 gen_addr_add(ctx, EA, EA, 8);
2652 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2653 tcg_temp_free(EA);
2654 #endif
2655 }
2656 #endif
2657
2658 /*** Integer store ***/
2659 #define GEN_ST(name, stop, opc, type) \
2660 static void glue(gen_, name)(DisasContext *ctx) \
2661 { \
2662 TCGv EA; \
2663 gen_set_access_type(ctx, ACCESS_INT); \
2664 EA = tcg_temp_new(); \
2665 gen_addr_imm_index(ctx, EA, 0); \
2666 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2667 tcg_temp_free(EA); \
2668 }
2669
2670 #define GEN_STU(name, stop, opc, type) \
2671 static void glue(gen_, stop##u)(DisasContext *ctx) \
2672 { \
2673 TCGv EA; \
2674 if (unlikely(rA(ctx->opcode) == 0)) { \
2675 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2676 return; \
2677 } \
2678 gen_set_access_type(ctx, ACCESS_INT); \
2679 EA = tcg_temp_new(); \
2680 if (type == PPC_64B) \
2681 gen_addr_imm_index(ctx, EA, 0x03); \
2682 else \
2683 gen_addr_imm_index(ctx, EA, 0); \
2684 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2685 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2686 tcg_temp_free(EA); \
2687 }
2688
2689 #define GEN_STUX(name, stop, opc2, opc3, type) \
2690 static void glue(gen_, name##ux)(DisasContext *ctx) \
2691 { \
2692 TCGv EA; \
2693 if (unlikely(rA(ctx->opcode) == 0)) { \
2694 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2695 return; \
2696 } \
2697 gen_set_access_type(ctx, ACCESS_INT); \
2698 EA = tcg_temp_new(); \
2699 gen_addr_reg_index(ctx, EA); \
2700 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2701 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2702 tcg_temp_free(EA); \
2703 }
2704
2705 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2706 static void glue(gen_, name##x)(DisasContext *ctx) \
2707 { \
2708 TCGv EA; \
2709 gen_set_access_type(ctx, ACCESS_INT); \
2710 EA = tcg_temp_new(); \
2711 gen_addr_reg_index(ctx, EA); \
2712 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2713 tcg_temp_free(EA); \
2714 }
2715 #define GEN_STX(name, stop, opc2, opc3, type) \
2716 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2717
2718 #define GEN_STS(name, stop, op, type) \
2719 GEN_ST(name, stop, op | 0x20, type); \
2720 GEN_STU(name, stop, op | 0x21, type); \
2721 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2722 GEN_STX(name, stop, 0x17, op | 0x00, type)
2723
2724 /* stb stbu stbux stbx */
2725 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2726 /* sth sthu sthux sthx */
2727 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2728 /* stw stwu stwux stwx */
2729 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2730 #if defined(TARGET_PPC64)
2731 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2732 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2733
2734 static void gen_std(DisasContext *ctx)
2735 {
2736 int rs;
2737 TCGv EA;
2738
2739 rs = rS(ctx->opcode);
2740 if ((ctx->opcode & 0x3) == 0x2) {
2741 #if defined(CONFIG_USER_ONLY)
2742 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2743 #else
2744 /* stq */
2745 if (unlikely(ctx->mem_idx == 0)) {
2746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2747 return;
2748 }
2749 if (unlikely(rs & 1)) {
2750 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2751 return;
2752 }
2753 if (unlikely(ctx->le_mode)) {
2754 /* Little-endian mode is not handled */
2755 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2756 return;
2757 }
2758 gen_set_access_type(ctx, ACCESS_INT);
2759 EA = tcg_temp_new();
2760 gen_addr_imm_index(ctx, EA, 0x03);
2761 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2762 gen_addr_add(ctx, EA, EA, 8);
2763 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2764 tcg_temp_free(EA);
2765 #endif
2766 } else {
2767 /* std / stdu */
2768 if (Rc(ctx->opcode)) {
2769 if (unlikely(rA(ctx->opcode) == 0)) {
2770 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2771 return;
2772 }
2773 }
2774 gen_set_access_type(ctx, ACCESS_INT);
2775 EA = tcg_temp_new();
2776 gen_addr_imm_index(ctx, EA, 0x03);
2777 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2778 if (Rc(ctx->opcode))
2779 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2780 tcg_temp_free(EA);
2781 }
2782 }
2783 #endif
2784 /*** Integer load and store with byte reverse ***/
2785 /* lhbrx */
2786 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2787 {
2788 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2789 if (likely(!ctx->le_mode)) {
2790 tcg_gen_bswap16_tl(arg1, arg1);
2791 }
2792 }
2793 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2794
2795 /* lwbrx */
2796 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2797 {
2798 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2799 if (likely(!ctx->le_mode)) {
2800 tcg_gen_bswap32_tl(arg1, arg1);
2801 }
2802 }
2803 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2804
2805 #if defined(TARGET_PPC64)
2806 /* ldbrx */
2807 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2808 {
2809 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2810 if (likely(!ctx->le_mode)) {
2811 tcg_gen_bswap64_tl(arg1, arg1);
2812 }
2813 }
2814 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2815 #endif /* TARGET_PPC64 */
2816
2817 /* sthbrx */
2818 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2819 {
2820 if (likely(!ctx->le_mode)) {
2821 TCGv t0 = tcg_temp_new();
2822 tcg_gen_ext16u_tl(t0, arg1);
2823 tcg_gen_bswap16_tl(t0, t0);
2824 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2825 tcg_temp_free(t0);
2826 } else {
2827 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2828 }
2829 }
2830 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2831
2832 /* stwbrx */
2833 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2834 {
2835 if (likely(!ctx->le_mode)) {
2836 TCGv t0 = tcg_temp_new();
2837 tcg_gen_ext32u_tl(t0, arg1);
2838 tcg_gen_bswap32_tl(t0, t0);
2839 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2840 tcg_temp_free(t0);
2841 } else {
2842 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2843 }
2844 }
2845 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2846
2847 #if defined(TARGET_PPC64)
2848 /* stdbrx */
2849 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2850 {
2851 if (likely(!ctx->le_mode)) {
2852 TCGv t0 = tcg_temp_new();
2853 tcg_gen_bswap64_tl(t0, arg1);
2854 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2855 tcg_temp_free(t0);
2856 } else {
2857 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2858 }
2859 }
2860 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2861 #endif /* TARGET_PPC64 */
2862
2863 /*** Integer load and store multiple ***/
2864
2865 /* lmw */
2866 static void gen_lmw(DisasContext *ctx)
2867 {
2868 TCGv t0;
2869 TCGv_i32 t1;
2870 gen_set_access_type(ctx, ACCESS_INT);
2871 /* NIP cannot be restored if the memory exception comes from an helper */
2872 gen_update_nip(ctx, ctx->nip - 4);
2873 t0 = tcg_temp_new();
2874 t1 = tcg_const_i32(rD(ctx->opcode));
2875 gen_addr_imm_index(ctx, t0, 0);
2876 gen_helper_lmw(cpu_env, t0, t1);
2877 tcg_temp_free(t0);
2878 tcg_temp_free_i32(t1);
2879 }
2880
2881 /* stmw */
2882 static void gen_stmw(DisasContext *ctx)
2883 {
2884 TCGv t0;
2885 TCGv_i32 t1;
2886 gen_set_access_type(ctx, ACCESS_INT);
2887 /* NIP cannot be restored if the memory exception comes from an helper */
2888 gen_update_nip(ctx, ctx->nip - 4);
2889 t0 = tcg_temp_new();
2890 t1 = tcg_const_i32(rS(ctx->opcode));
2891 gen_addr_imm_index(ctx, t0, 0);
2892 gen_helper_stmw(cpu_env, t0, t1);
2893 tcg_temp_free(t0);
2894 tcg_temp_free_i32(t1);
2895 }
2896
2897 /*** Integer load and store strings ***/
2898
2899 /* lswi */
2900 /* PowerPC32 specification says we must generate an exception if
2901 * rA is in the range of registers to be loaded.
2902 * In an other hand, IBM says this is valid, but rA won't be loaded.
2903 * For now, I'll follow the spec...
2904 */
2905 static void gen_lswi(DisasContext *ctx)
2906 {
2907 TCGv t0;
2908 TCGv_i32 t1, t2;
2909 int nb = NB(ctx->opcode);
2910 int start = rD(ctx->opcode);
2911 int ra = rA(ctx->opcode);
2912 int nr;
2913
2914 if (nb == 0)
2915 nb = 32;
2916 nr = nb / 4;
2917 if (unlikely(((start + nr) > 32 &&
2918 start <= ra && (start + nr - 32) > ra) ||
2919 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2920 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2921 return;
2922 }
2923 gen_set_access_type(ctx, ACCESS_INT);
2924 /* NIP cannot be restored if the memory exception comes from an helper */
2925 gen_update_nip(ctx, ctx->nip - 4);
2926 t0 = tcg_temp_new();
2927 gen_addr_register(ctx, t0);
2928 t1 = tcg_const_i32(nb);
2929 t2 = tcg_const_i32(start);
2930 gen_helper_lsw(cpu_env, t0, t1, t2);
2931 tcg_temp_free(t0);
2932 tcg_temp_free_i32(t1);
2933 tcg_temp_free_i32(t2);
2934 }
2935
2936 /* lswx */
2937 static void gen_lswx(DisasContext *ctx)
2938 {
2939 TCGv t0;
2940 TCGv_i32 t1, t2, t3;
2941 gen_set_access_type(ctx, ACCESS_INT);
2942 /* NIP cannot be restored if the memory exception comes from an helper */
2943 gen_update_nip(ctx, ctx->nip - 4);
2944 t0 = tcg_temp_new();
2945 gen_addr_reg_index(ctx, t0);
2946 t1 = tcg_const_i32(rD(ctx->opcode));
2947 t2 = tcg_const_i32(rA(ctx->opcode));
2948 t3 = tcg_const_i32(rB(ctx->opcode));
2949 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2950 tcg_temp_free(t0);
2951 tcg_temp_free_i32(t1);
2952 tcg_temp_free_i32(t2);
2953 tcg_temp_free_i32(t3);
2954 }
2955
2956 /* stswi */
2957 static void gen_stswi(DisasContext *ctx)
2958 {
2959 TCGv t0;
2960 TCGv_i32 t1, t2;
2961 int nb = NB(ctx->opcode);
2962 gen_set_access_type(ctx, ACCESS_INT);
2963 /* NIP cannot be restored if the memory exception comes from an helper */
2964 gen_update_nip(ctx, ctx->nip - 4);
2965 t0 = tcg_temp_new();
2966 gen_addr_register(ctx, t0);
2967 if (nb == 0)
2968 nb = 32;
2969 t1 = tcg_const_i32(nb);
2970 t2 = tcg_const_i32(rS(ctx->opcode));
2971 gen_helper_stsw(cpu_env, t0, t1, t2);
2972 tcg_temp_free(t0);
2973 tcg_temp_free_i32(t1);
2974 tcg_temp_free_i32(t2);
2975 }
2976
2977 /* stswx */
2978 static void gen_stswx(DisasContext *ctx)
2979 {
2980 TCGv t0;
2981 TCGv_i32 t1, t2;
2982 gen_set_access_type(ctx, ACCESS_INT);
2983 /* NIP cannot be restored if the memory exception comes from an helper */
2984 gen_update_nip(ctx, ctx->nip - 4);
2985 t0 = tcg_temp_new();
2986 gen_addr_reg_index(ctx, t0);
2987 t1 = tcg_temp_new_i32();
2988 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2989 tcg_gen_andi_i32(t1, t1, 0x7F);
2990 t2 = tcg_const_i32(rS(ctx->opcode));
2991 gen_helper_stsw(cpu_env, t0, t1, t2);
2992 tcg_temp_free(t0);
2993 tcg_temp_free_i32(t1);
2994 tcg_temp_free_i32(t2);
2995 }
2996
2997 /*** Memory synchronisation ***/
2998 /* eieio */
2999 static void gen_eieio(DisasContext *ctx)
3000 {
3001 }
3002
3003 /* isync */
3004 static void gen_isync(DisasContext *ctx)
3005 {
3006 gen_stop_exception(ctx);
3007 }
3008
3009 /* lwarx */
3010 static void gen_lwarx(DisasContext *ctx)
3011 {
3012 TCGv t0;
3013 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3014 gen_set_access_type(ctx, ACCESS_RES);
3015 t0 = tcg_temp_local_new();
3016 gen_addr_reg_index(ctx, t0);
3017 gen_check_align(ctx, t0, 0x03);
3018 gen_qemu_ld32u(ctx, gpr, t0);
3019 tcg_gen_mov_tl(cpu_reserve, t0);
3020 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3021 tcg_temp_free(t0);
3022 }
3023
3024 #if defined(CONFIG_USER_ONLY)
3025 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3026 int reg, int size)
3027 {
3028 TCGv t0 = tcg_temp_new();
3029 uint32_t save_exception = ctx->exception;
3030
3031 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3032 tcg_gen_movi_tl(t0, (size << 5) | reg);
3033 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3034 tcg_temp_free(t0);
3035 gen_update_nip(ctx, ctx->nip-4);
3036 ctx->exception = POWERPC_EXCP_BRANCH;
3037 gen_exception(ctx, POWERPC_EXCP_STCX);
3038 ctx->exception = save_exception;
3039 }
3040 #endif
3041
3042 /* stwcx. */
3043 static void gen_stwcx_(DisasContext *ctx)
3044 {
3045 TCGv t0;
3046 gen_set_access_type(ctx, ACCESS_RES);
3047 t0 = tcg_temp_local_new();
3048 gen_addr_reg_index(ctx, t0);
3049 gen_check_align(ctx, t0, 0x03);
3050 #if defined(CONFIG_USER_ONLY)
3051 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3052 #else
3053 {
3054 int l1;
3055
3056 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3057 l1 = gen_new_label();
3058 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3059 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3060 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3061 gen_set_label(l1);
3062 tcg_gen_movi_tl(cpu_reserve, -1);
3063 }
3064 #endif
3065 tcg_temp_free(t0);
3066 }
3067
3068 #if defined(TARGET_PPC64)
3069 /* ldarx */
3070 static void gen_ldarx(DisasContext *ctx)
3071 {
3072 TCGv t0;
3073 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3074 gen_set_access_type(ctx, ACCESS_RES);
3075 t0 = tcg_temp_local_new();
3076 gen_addr_reg_index(ctx, t0);
3077 gen_check_align(ctx, t0, 0x07);
3078 gen_qemu_ld64(ctx, gpr, t0);
3079 tcg_gen_mov_tl(cpu_reserve, t0);
3080 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3081 tcg_temp_free(t0);
3082 }
3083
3084 /* stdcx. */
3085 static void gen_stdcx_(DisasContext *ctx)
3086 {
3087 TCGv t0;
3088 gen_set_access_type(ctx, ACCESS_RES);
3089 t0 = tcg_temp_local_new();
3090 gen_addr_reg_index(ctx, t0);
3091 gen_check_align(ctx, t0, 0x07);
3092 #if defined(CONFIG_USER_ONLY)
3093 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3094 #else
3095 {
3096 int l1;
3097 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3098 l1 = gen_new_label();
3099 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3100 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3101 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3102 gen_set_label(l1);
3103 tcg_gen_movi_tl(cpu_reserve, -1);
3104 }
3105 #endif
3106 tcg_temp_free(t0);
3107 }
3108 #endif /* defined(TARGET_PPC64) */
3109
3110 /* sync */
3111 static void gen_sync(DisasContext *ctx)
3112 {
3113 }
3114
3115 /* wait */
3116 static void gen_wait(DisasContext *ctx)
3117 {
3118 TCGv_i32 t0 = tcg_temp_new_i32();
3119 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
3120 tcg_temp_free_i32(t0);
3121 /* Stop translation, as the CPU is supposed to sleep from now */
3122 gen_exception_err(ctx, EXCP_HLT, 1);
3123 }
3124
3125 /*** Floating-point load ***/
3126 #define GEN_LDF(name, ldop, opc, type) \
3127 static void glue(gen_, name)(DisasContext *ctx) \
3128 { \
3129 TCGv EA; \
3130 if (unlikely(!ctx->fpu_enabled)) { \
3131 gen_exception(ctx, POWERPC_EXCP_FPU); \
3132 return; \
3133 } \
3134 gen_set_access_type(ctx, ACCESS_FLOAT); \
3135 EA = tcg_temp_new(); \
3136 gen_addr_imm_index(ctx, EA, 0); \
3137 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3138 tcg_temp_free(EA); \
3139 }
3140
3141 #define GEN_LDUF(name, ldop, opc, type) \
3142 static void glue(gen_, name##u)(DisasContext *ctx) \
3143 { \
3144 TCGv EA; \
3145 if (unlikely(!ctx->fpu_enabled)) { \
3146 gen_exception(ctx, POWERPC_EXCP_FPU); \
3147 return; \
3148 } \
3149 if (unlikely(rA(ctx->opcode) == 0)) { \
3150 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3151 return; \
3152 } \
3153 gen_set_access_type(ctx, ACCESS_FLOAT); \
3154 EA = tcg_temp_new(); \
3155 gen_addr_imm_index(ctx, EA, 0); \
3156 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3157 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3158 tcg_temp_free(EA); \
3159 }
3160
3161 #define GEN_LDUXF(name, ldop, opc, type) \
3162 static void glue(gen_, name##ux)(DisasContext *ctx) \
3163 { \
3164 TCGv EA; \
3165 if (unlikely(!ctx->fpu_enabled)) { \
3166 gen_exception(ctx, POWERPC_EXCP_FPU); \
3167 return; \
3168 } \
3169 if (unlikely(rA(ctx->opcode) == 0)) { \
3170 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3171 return; \
3172 } \
3173 gen_set_access_type(ctx, ACCESS_FLOAT); \
3174 EA = tcg_temp_new(); \
3175 gen_addr_reg_index(ctx, EA); \
3176 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3177 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3178 tcg_temp_free(EA); \
3179 }
3180
3181 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3182 static void glue(gen_, name##x)(DisasContext *ctx) \
3183 { \
3184 TCGv EA; \
3185 if (unlikely(!ctx->fpu_enabled)) { \
3186 gen_exception(ctx, POWERPC_EXCP_FPU); \
3187 return; \
3188 } \
3189 gen_set_access_type(ctx, ACCESS_FLOAT); \
3190 EA = tcg_temp_new(); \
3191 gen_addr_reg_index(ctx, EA); \
3192 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3193 tcg_temp_free(EA); \
3194 }
3195
3196 #define GEN_LDFS(name, ldop, op, type) \
3197 GEN_LDF(name, ldop, op | 0x20, type); \
3198 GEN_LDUF(name, ldop, op | 0x21, type); \
3199 GEN_LDUXF(name, ldop, op | 0x01, type); \
3200 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3201
3202 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3203 {
3204 TCGv t0 = tcg_temp_new();
3205 TCGv_i32 t1 = tcg_temp_new_i32();
3206 gen_qemu_ld32u(ctx, t0, arg2);
3207 tcg_gen_trunc_tl_i32(t1, t0);
3208 tcg_temp_free(t0);
3209 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3210 tcg_temp_free_i32(t1);
3211 }
3212
3213 /* lfd lfdu lfdux lfdx */
3214 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3215 /* lfs lfsu lfsux lfsx */
3216 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3217
3218 /*** Floating-point store ***/
3219 #define GEN_STF(name, stop, opc, type) \
3220 static void glue(gen_, name)(DisasContext *ctx) \
3221 { \
3222 TCGv EA; \
3223 if (unlikely(!ctx->fpu_enabled)) { \
3224 gen_exception(ctx, POWERPC_EXCP_FPU); \
3225 return; \
3226 } \
3227 gen_set_access_type(ctx, ACCESS_FLOAT); \
3228 EA = tcg_temp_new(); \
3229 gen_addr_imm_index(ctx, EA, 0); \
3230 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3231 tcg_temp_free(EA); \
3232 }
3233
3234 #define GEN_STUF(name, stop, opc, type) \
3235 static void glue(gen_, name##u)(DisasContext *ctx) \
3236 { \
3237 TCGv EA; \
3238 if (unlikely(!ctx->fpu_enabled)) { \
3239 gen_exception(ctx, POWERPC_EXCP_FPU); \
3240 return; \
3241 } \
3242 if (unlikely(rA(ctx->opcode) == 0)) { \
3243 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3244 return; \
3245 } \
3246 gen_set_access_type(ctx, ACCESS_FLOAT); \
3247 EA = tcg_temp_new(); \
3248 gen_addr_imm_index(ctx, EA, 0); \
3249 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3250 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3251 tcg_temp_free(EA); \
3252 }
3253
3254 #define GEN_STUXF(name, stop, opc, type) \
3255 static void glue(gen_, name##ux)(DisasContext *ctx) \
3256 { \
3257 TCGv EA; \
3258 if (unlikely(!ctx->fpu_enabled)) { \
3259 gen_exception(ctx, POWERPC_EXCP_FPU); \
3260 return; \
3261 } \
3262 if (unlikely(rA(ctx->opcode) == 0)) { \
3263 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3264 return; \
3265 } \
3266 gen_set_access_type(ctx, ACCESS_FLOAT); \
3267 EA = tcg_temp_new(); \
3268 gen_addr_reg_index(ctx, EA); \
3269 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3270 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3271 tcg_temp_free(EA); \
3272 }
3273
3274 #define GEN_STXF(name, stop, opc2, opc3, type) \
3275 static void glue(gen_, name##x)(DisasContext *ctx) \
3276 { \
3277 TCGv EA; \
3278 if (unlikely(!ctx->fpu_enabled)) { \
3279 gen_exception(ctx, POWERPC_EXCP_FPU); \
3280 return; \
3281 } \
3282 gen_set_access_type(ctx, ACCESS_FLOAT); \
3283 EA = tcg_temp_new(); \
3284 gen_addr_reg_index(ctx, EA); \
3285 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3286 tcg_temp_free(EA); \
3287 }
3288
3289 #define GEN_STFS(name, stop, op, type) \
3290 GEN_STF(name, stop, op | 0x20, type); \
3291 GEN_STUF(name, stop, op | 0x21, type); \
3292 GEN_STUXF(name, stop, op | 0x01, type); \
3293 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3294
3295 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3296 {
3297 TCGv_i32 t0 = tcg_temp_new_i32();
3298 TCGv t1 = tcg_temp_new();
3299 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3300 tcg_gen_extu_i32_tl(t1, t0);
3301 tcg_temp_free_i32(t0);
3302 gen_qemu_st32(ctx, t1, arg2);
3303 tcg_temp_free(t1);
3304 }
3305
3306 /* stfd stfdu stfdux stfdx */
3307 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3308 /* stfs stfsu stfsux stfsx */
3309 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3310
3311 /* Optional: */
3312 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3313 {
3314 TCGv t0 = tcg_temp_new();
3315 tcg_gen_trunc_i64_tl(t0, arg1),
3316 gen_qemu_st32(ctx, t0, arg2);
3317 tcg_temp_free(t0);
3318 }
3319 /* stfiwx */
3320 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3321
3322 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3323 {
3324 #if defined(TARGET_PPC64)
3325 if (ctx->has_cfar)
3326 tcg_gen_movi_tl(cpu_cfar, nip);
3327 #endif
3328 }
3329
3330 /*** Branch ***/
3331 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3332 {
3333 TranslationBlock *tb;
3334 tb = ctx->tb;
3335 #if defined(TARGET_PPC64)
3336 if (!ctx->sf_mode)
3337 dest = (uint32_t) dest;
3338 #endif
3339 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3340 likely(!ctx->singlestep_enabled)) {
3341 tcg_gen_goto_tb(n);
3342 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3343 tcg_gen_exit_tb((tcg_target_long)tb + n);
3344 } else {
3345 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3346 if (unlikely(ctx->singlestep_enabled)) {
3347 if ((ctx->singlestep_enabled &
3348 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3349 (ctx->exception == POWERPC_EXCP_BRANCH ||
3350 ctx->exception == POWERPC_EXCP_TRACE)) {
3351 target_ulong tmp = ctx->nip;
3352 ctx->nip = dest;
3353 gen_exception(ctx, POWERPC_EXCP_TRACE);
3354 ctx->nip = tmp;
3355 }
3356 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3357 gen_debug_exception(ctx);
3358 }
3359 }
3360 tcg_gen_exit_tb(0);
3361 }
3362 }
3363
3364 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3365 {
3366 #if defined(TARGET_PPC64)
3367 if (ctx->sf_mode == 0)
3368 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3369 else
3370 #endif
3371 tcg_gen_movi_tl(cpu_lr, nip);
3372 }
3373
3374 /* b ba bl bla */
3375 static void gen_b(DisasContext *ctx)
3376 {
3377 target_ulong li, target;
3378
3379 ctx->exception = POWERPC_EXCP_BRANCH;
3380 /* sign extend LI */
3381 #if defined(TARGET_PPC64)
3382 if (ctx->sf_mode)
3383 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3384 else
3385 #endif
3386 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3387 if (likely(AA(ctx->opcode) == 0))
3388 target = ctx->nip + li - 4;
3389 else
3390 target = li;
3391 if (LK(ctx->opcode))
3392 gen_setlr(ctx, ctx->nip);
3393 gen_update_cfar(ctx, ctx->nip);
3394 gen_goto_tb(ctx, 0, target);
3395 }
3396
3397 #define BCOND_IM 0
3398 #define BCOND_LR 1
3399 #define BCOND_CTR 2
3400
3401 static inline void gen_bcond(DisasContext *ctx, int type)
3402 {
3403 uint32_t bo = BO(ctx->opcode);
3404 int l1;
3405 TCGv target;
3406
3407 ctx->exception = POWERPC_EXCP_BRANCH;
3408 if (type == BCOND_LR || type == BCOND_CTR) {
3409 target = tcg_temp_local_new();
3410 if (type == BCOND_CTR)
3411 tcg_gen_mov_tl(target, cpu_ctr);
3412 else
3413 tcg_gen_mov_tl(target, cpu_lr);
3414 } else {
3415 TCGV_UNUSED(target);
3416 }
3417 if (LK(ctx->opcode))
3418 gen_setlr(ctx, ctx->nip);
3419 l1 = gen_new_label();
3420 if ((bo & 0x4) == 0) {
3421 /* Decrement and test CTR */
3422 TCGv temp = tcg_temp_new();
3423 if (unlikely(type == BCOND_CTR)) {
3424 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3425 return;
3426 }
3427 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3428 #if defined(TARGET_PPC64)
3429 if (!ctx->sf_mode)
3430 tcg_gen_ext32u_tl(temp, cpu_ctr);
3431 else
3432 #endif
3433 tcg_gen_mov_tl(temp, cpu_ctr);
3434 if (bo & 0x2) {
3435 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3436 } else {
3437 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3438 }
3439 tcg_temp_free(temp);
3440 }
3441 if ((bo & 0x10) == 0) {
3442 /* Test CR */
3443 uint32_t bi = BI(ctx->opcode);
3444 uint32_t mask = 1 << (3 - (bi & 0x03));
3445 TCGv_i32 temp = tcg_temp_new_i32();
3446
3447 if (bo & 0x8) {
3448 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3449 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3450 } else {
3451 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3452 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3453 }
3454 tcg_temp_free_i32(temp);
3455 }
3456 gen_update_cfar(ctx, ctx->nip);
3457 if (type == BCOND_IM) {
3458 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3459 if (likely(AA(ctx->opcode) == 0)) {
3460 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3461 } else {
3462 gen_goto_tb(ctx, 0, li);
3463 }
3464 gen_set_label(l1);
3465 gen_goto_tb(ctx, 1, ctx->nip);
3466 } else {
3467 #if defined(TARGET_PPC64)
3468 if (!(ctx->sf_mode))
3469 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3470 else
3471 #endif
3472 tcg_gen_andi_tl(cpu_nip, target, ~3);
3473 tcg_gen_exit_tb(0);
3474 gen_set_label(l1);
3475 #if defined(TARGET_PPC64)
3476 if (!(ctx->sf_mode))
3477 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3478 else
3479 #endif
3480 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3481 tcg_gen_exit_tb(0);
3482 }
3483 }
3484
3485 static void gen_bc(DisasContext *ctx)
3486 {
3487 gen_bcond(ctx, BCOND_IM);
3488 }
3489
3490 static void gen_bcctr(DisasContext *ctx)
3491 {
3492 gen_bcond(ctx, BCOND_CTR);
3493 }
3494
3495 static void gen_bclr(DisasContext *ctx)
3496 {
3497 gen_bcond(ctx, BCOND_LR);
3498 }
3499
3500 /*** Condition register logical ***/
3501 #define GEN_CRLOGIC(name, tcg_op, opc) \
3502 static void glue(gen_, name)(DisasContext *ctx) \
3503 { \
3504 uint8_t bitmask; \
3505 int sh; \
3506 TCGv_i32 t0, t1; \
3507 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3508 t0 = tcg_temp_new_i32(); \
3509 if (sh > 0) \
3510 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3511 else if (sh < 0) \
3512 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3513 else \
3514 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3515 t1 = tcg_temp_new_i32(); \
3516 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3517 if (sh > 0) \
3518 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3519 else if (sh < 0) \
3520 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3521 else \
3522 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3523 tcg_op(t0, t0, t1); \
3524 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3525 tcg_gen_andi_i32(t0, t0, bitmask); \
3526 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3527 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3528 tcg_temp_free_i32(t0); \
3529 tcg_temp_free_i32(t1); \
3530 }
3531
3532 /* crand */
3533 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3534 /* crandc */
3535 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3536 /* creqv */
3537 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3538 /* crnand */
3539 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3540 /* crnor */
3541 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3542 /* cror */
3543 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3544 /* crorc */
3545 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3546 /* crxor */
3547 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3548
3549 /* mcrf */
3550 static void gen_mcrf(DisasContext *ctx)
3551 {
3552 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3553 }
3554
3555 /*** System linkage ***/
3556
3557 /* rfi (mem_idx only) */
3558 static void gen_rfi(DisasContext *ctx)
3559 {
3560 #if defined(CONFIG_USER_ONLY)
3561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3562 #else
3563 /* Restore CPU state */
3564 if (unlikely(!ctx->mem_idx)) {
3565 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3566 return;
3567 }
3568 gen_update_cfar(ctx, ctx->nip);
3569 gen_helper_rfi(cpu_env);
3570 gen_sync_exception(ctx);
3571 #endif
3572 }
3573
3574 #if defined(TARGET_PPC64)
3575 static void gen_rfid(DisasContext *ctx)
3576 {
3577 #if defined(CONFIG_USER_ONLY)
3578 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3579 #else
3580 /* Restore CPU state */
3581 if (unlikely(!ctx->mem_idx)) {
3582 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3583 return;
3584 }
3585 gen_update_cfar(ctx, ctx->nip);
3586 gen_helper_rfid(cpu_env);
3587 gen_sync_exception(ctx);
3588 #endif
3589 }
3590
3591 static void gen_hrfid(DisasContext *ctx)
3592 {
3593 #if defined(CONFIG_USER_ONLY)
3594 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3595 #else
3596 /* Restore CPU state */
3597 if (unlikely(ctx->mem_idx <= 1)) {
3598 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3599 return;
3600 }
3601 gen_helper_hrfid(cpu_env);
3602 gen_sync_exception(ctx);
3603 #endif
3604 }
3605 #endif
3606
3607 /* sc */
3608 #if defined(CONFIG_USER_ONLY)
3609 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3610 #else
3611 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3612 #endif
3613 static void gen_sc(DisasContext *ctx)
3614 {
3615 uint32_t lev;
3616
3617 lev = (ctx->opcode >> 5) & 0x7F;
3618 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3619 }
3620
3621 /*** Trap ***/
3622
3623 /* tw */
3624 static void gen_tw(DisasContext *ctx)
3625 {
3626 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3627 /* Update the nip since this might generate a trap exception */
3628 gen_update_nip(ctx, ctx->nip);
3629 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3630 t0);
3631 tcg_temp_free_i32(t0);
3632 }
3633
3634 /* twi */
3635 static void gen_twi(DisasContext *ctx)
3636 {
3637 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3638 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3639 /* Update the nip since this might generate a trap exception */
3640 gen_update_nip(ctx, ctx->nip);
3641 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3642 tcg_temp_free(t0);
3643 tcg_temp_free_i32(t1);
3644 }
3645
3646 #if defined(TARGET_PPC64)
3647 /* td */
3648 static void gen_td(DisasContext *ctx)
3649 {
3650 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3651 /* Update the nip since this might generate a trap exception */
3652 gen_update_nip(ctx, ctx->nip);
3653 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3654 t0);
3655 tcg_temp_free_i32(t0);
3656 }
3657
3658 /* tdi */
3659 static void gen_tdi(DisasContext *ctx)
3660 {
3661 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3662 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3663 /* Update the nip since this might generate a trap exception */
3664 gen_update_nip(ctx, ctx->nip);
3665 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3666 tcg_temp_free(t0);
3667 tcg_temp_free_i32(t1);
3668 }
3669 #endif
3670
3671 /*** Processor control ***/
3672
3673 static void gen_read_xer(TCGv dst)
3674 {
3675 TCGv t0 = tcg_temp_new();
3676 TCGv t1 = tcg_temp_new();
3677 TCGv t2 = tcg_temp_new();
3678 tcg_gen_mov_tl(dst, cpu_xer);
3679 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3680 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3681 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3682 tcg_gen_or_tl(t0, t0, t1);
3683 tcg_gen_or_tl(dst, dst, t2);
3684 tcg_gen_or_tl(dst, dst, t0);
3685 tcg_temp_free(t0);
3686 tcg_temp_free(t1);
3687 tcg_temp_free(t2);
3688 }
3689
3690 static void gen_write_xer(TCGv src)
3691 {
3692 tcg_gen_andi_tl(cpu_xer, src,
3693 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3694 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3695 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3696 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3697 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3698 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3699 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3700 }
3701
3702 /* mcrxr */
3703 static void gen_mcrxr(DisasContext *ctx)
3704 {
3705 TCGv_i32 t0 = tcg_temp_new_i32();
3706 TCGv_i32 t1 = tcg_temp_new_i32();
3707 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3708
3709 tcg_gen_trunc_tl_i32(t0, cpu_so);
3710 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3711 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3712 tcg_gen_shri_i32(t0, t0, 2);
3713 tcg_gen_shri_i32(t1, t1, 1);
3714 tcg_gen_or_i32(dst, dst, t0);
3715 tcg_gen_or_i32(dst, dst, t1);
3716 tcg_temp_free_i32(t0);
3717 tcg_temp_free_i32(t1);
3718
3719 tcg_gen_movi_tl(cpu_so, 0);
3720 tcg_gen_movi_tl(cpu_ov, 0);
3721 tcg_gen_movi_tl(cpu_ca, 0);
3722 }
3723
3724 /* mfcr mfocrf */
3725 static void gen_mfcr(DisasContext *ctx)
3726 {
3727 uint32_t crm, crn;
3728
3729 if (likely(ctx->opcode & 0x00100000)) {
3730 crm = CRM(ctx->opcode);
3731 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3732 crn = ctz32 (crm);
3733 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3734 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3735 cpu_gpr[rD(ctx->opcode)], crn * 4);
3736 }
3737 } else {
3738 TCGv_i32 t0 = tcg_temp_new_i32();
3739 tcg_gen_mov_i32(t0, cpu_crf[0]);
3740 tcg_gen_shli_i32(t0, t0, 4);
3741 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3742 tcg_gen_shli_i32(t0, t0, 4);
3743 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3744 tcg_gen_shli_i32(t0, t0, 4);
3745 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3746 tcg_gen_shli_i32(t0, t0, 4);
3747 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3748 tcg_gen_shli_i32(t0, t0, 4);
3749 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3750 tcg_gen_shli_i32(t0, t0, 4);
3751 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3752 tcg_gen_shli_i32(t0, t0, 4);
3753 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3754 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3755 tcg_temp_free_i32(t0);
3756 }
3757 }
3758
3759 /* mfmsr */
3760 static void gen_mfmsr(DisasContext *ctx)
3761 {
3762 #if defined(CONFIG_USER_ONLY)
3763 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3764 #else
3765 if (unlikely(!ctx->mem_idx)) {
3766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3767 return;
3768 }
3769 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3770 #endif
3771 }
3772
3773 static void spr_noaccess(void *opaque, int gprn, int sprn)
3774 {
3775 #if 0
3776 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3777 printf("ERROR: try to access SPR %d !\n", sprn);
3778 #endif
3779 }
3780 #define SPR_NOACCESS (&spr_noaccess)
3781
3782 /* mfspr */
3783 static inline void gen_op_mfspr(DisasContext *ctx)
3784 {
3785 void (*read_cb)(void *opaque, int gprn, int sprn);
3786 uint32_t sprn = SPR(ctx->opcode);
3787
3788 #if !defined(CONFIG_USER_ONLY)
3789 if (ctx->mem_idx == 2)
3790 read_cb = ctx->spr_cb[sprn].hea_read;
3791 else if (ctx->mem_idx)
3792 read_cb = ctx->spr_cb[sprn].oea_read;
3793 else
3794 #endif
3795 read_cb = ctx->spr_cb[sprn].uea_read;
3796 if (likely(read_cb != NULL)) {
3797 if (likely(read_cb != SPR_NOACCESS)) {
3798 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3799 } else {
3800 /* Privilege exception */
3801 /* This is a hack to avoid warnings when running Linux:
3802 * this OS breaks the PowerPC virtualisation model,
3803 * allowing userland application to read the PVR
3804 */
3805 if (sprn != SPR_PVR) {
3806 qemu_log("Trying to read privileged spr %d %03x at "
3807 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3808 printf("Trying to read privileged spr %d %03x at "
3809 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3810 }
3811 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3812 }
3813 } else {
3814 /* Not defined */
3815 qemu_log("Trying to read invalid spr %d %03x at "
3816 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3817 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3818 sprn, sprn, ctx->nip);
3819 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3820 }
3821 }
3822
3823 static void gen_mfspr(DisasContext *ctx)
3824 {
3825 gen_op_mfspr(ctx);
3826 }
3827
3828 /* mftb */
3829 static void gen_mftb(DisasContext *ctx)
3830 {
3831 gen_op_mfspr(ctx);
3832 }
3833
3834 /* mtcrf mtocrf*/
3835 static void gen_mtcrf(DisasContext *ctx)
3836 {
3837 uint32_t crm, crn;
3838
3839 crm = CRM(ctx->opcode);
3840 if (likely((ctx->opcode & 0x00100000))) {
3841 if (crm && ((crm & (crm - 1)) == 0)) {
3842 TCGv_i32 temp = tcg_temp_new_i32();
3843 crn = ctz32 (crm);
3844 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3845 tcg_gen_shri_i32(temp, temp, crn * 4);
3846 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3847 tcg_temp_free_i32(temp);
3848 }
3849 } else {
3850 TCGv_i32 temp = tcg_temp_new_i32();
3851 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3852 for (crn = 0 ; crn < 8 ; crn++) {
3853 if (crm & (1 << crn)) {
3854 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3855 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3856 }
3857 }
3858 tcg_temp_free_i32(temp);
3859 }
3860 }
3861
3862 /* mtmsr */
3863 #if defined(TARGET_PPC64)
3864 static void gen_mtmsrd(DisasContext *ctx)
3865 {
3866 #if defined(CONFIG_USER_ONLY)
3867 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3868 #else
3869 if (unlikely(!ctx->mem_idx)) {
3870 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3871 return;
3872 }
3873 if (ctx->opcode & 0x00010000) {
3874 /* Special form that does not need any synchronisation */
3875 TCGv t0 = tcg_temp_new();
3876 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3877 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3878 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3879 tcg_temp_free(t0);
3880 } else {
3881 /* XXX: we need to update nip before the store
3882 * if we enter power saving mode, we will exit the loop
3883 * directly from ppc_store_msr
3884 */
3885 gen_update_nip(ctx, ctx->nip);
3886 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3887 /* Must stop the translation as machine state (may have) changed */
3888 /* Note that mtmsr is not always defined as context-synchronizing */
3889 gen_stop_exception(ctx);
3890 }
3891 #endif
3892 }
3893 #endif
3894
3895 static void gen_mtmsr(DisasContext *ctx)
3896 {
3897 #if defined(CONFIG_USER_ONLY)
3898 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3899 #else
3900 if (unlikely(!ctx->mem_idx)) {
3901 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3902 return;
3903 }
3904 if (ctx->opcode & 0x00010000) {
3905 /* Special form that does not need any synchronisation */
3906 TCGv t0 = tcg_temp_new();
3907 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3908 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3909 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3910 tcg_temp_free(t0);
3911 } else {
3912 TCGv msr = tcg_temp_new();
3913
3914 /* XXX: we need to update nip before the store
3915 * if we enter power saving mode, we will exit the loop
3916 * directly from ppc_store_msr
3917 */
3918 gen_update_nip(ctx, ctx->nip);
3919 #if defined(TARGET_PPC64)
3920 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3921 #else
3922 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3923 #endif
3924 gen_helper_store_msr(cpu_env, msr);
3925 /* Must stop the translation as machine state (may have) changed */
3926 /* Note that mtmsr is not always defined as context-synchronizing */
3927 gen_stop_exception(ctx);
3928 }
3929 #endif
3930 }
3931
3932 /* mtspr */
3933 static void gen_mtspr(DisasContext *ctx)
3934 {
3935 void (*write_cb)(void *opaque, int sprn, int gprn);
3936 uint32_t sprn = SPR(ctx->opcode);
3937
3938 #if !defined(CONFIG_USER_ONLY)
3939 if (ctx->mem_idx == 2)
3940 write_cb = ctx->spr_cb[sprn].hea_write;
3941 else if (ctx->mem_idx)
3942 write_cb = ctx->spr_cb[sprn].oea_write;
3943 else
3944 #endif
3945 write_cb = ctx->spr_cb[sprn].uea_write;
3946 if (likely(write_cb != NULL)) {
3947 if (likely(write_cb != SPR_NOACCESS)) {
3948 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3949 } else {
3950 /* Privilege exception */
3951 qemu_log("Trying to write privileged spr %d %03x at "
3952 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3953 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3954 "\n", sprn, sprn, ctx->nip);
3955 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3956 }
3957 } else {
3958 /* Not defined */
3959 qemu_log("Trying to write invalid spr %d %03x at "
3960 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3961 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3962 sprn, sprn, ctx->nip);
3963 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3964 }
3965 }
3966
3967 /*** Cache management ***/
3968
3969 /* dcbf */
3970 static void gen_dcbf(DisasContext *ctx)
3971 {
3972 /* XXX: specification says this is treated as a load by the MMU */
3973 TCGv t0;
3974 gen_set_access_type(ctx, ACCESS_CACHE);
3975 t0 = tcg_temp_new();
3976 gen_addr_reg_index(ctx, t0);
3977 gen_qemu_ld8u(ctx, t0, t0);
3978 tcg_temp_free(t0);
3979 }
3980
3981 /* dcbi (Supervisor only) */
3982 static void gen_dcbi(DisasContext *ctx)
3983 {
3984 #if defined(CONFIG_USER_ONLY)
3985 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3986 #else
3987 TCGv EA, val;
3988 if (unlikely(!ctx->mem_idx)) {
3989 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3990 return;
3991 }
3992 EA = tcg_temp_new();
3993 gen_set_access_type(ctx, ACCESS_CACHE);
3994 gen_addr_reg_index(ctx, EA);
3995 val = tcg_temp_new();
3996 /* XXX: specification says this should be treated as a store by the MMU */
3997 gen_qemu_ld8u(ctx, val, EA);
3998 gen_qemu_st8(ctx, val, EA);
3999 tcg_temp_free(val);
4000 tcg_temp_free(EA);
4001 #endif
4002 }
4003
4004 /* dcdst */
4005 static void gen_dcbst(DisasContext *ctx)
4006 {
4007 /* XXX: specification say this is treated as a load by the MMU */
4008 TCGv t0;
4009 gen_set_access_type(ctx, ACCESS_CACHE);
4010 t0 = tcg_temp_new();
4011 gen_addr_reg_index(ctx, t0);
4012 gen_qemu_ld8u(ctx, t0, t0);
4013 tcg_temp_free(t0);
4014 }
4015
4016 /* dcbt */
4017 static void gen_dcbt(DisasContext *ctx)
4018 {
4019 /* interpreted as no-op */
4020 /* XXX: specification say this is treated as a load by the MMU
4021 * but does not generate any exception
4022 */
4023 }
4024
4025 /* dcbtst */
4026 static void gen_dcbtst(DisasContext *ctx)
4027 {
4028 /* interpreted as no-op */
4029 /* XXX: specification say this is treated as a load by the MMU
4030 * but does not generate any exception
4031 */
4032 }
4033
4034 /* dcbz */
4035 static void gen_dcbz(DisasContext *ctx)
4036 {
4037 TCGv tcgv_addr;
4038 TCGv_i32 tcgv_is_dcbzl;
4039 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4040
4041 gen_set_access_type(ctx, ACCESS_CACHE);
4042 /* NIP cannot be restored if the memory exception comes from an helper */
4043 gen_update_nip(ctx, ctx->nip - 4);
4044 tcgv_addr = tcg_temp_new();
4045 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4046
4047 gen_addr_reg_index(ctx, tcgv_addr);
4048 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4049
4050 tcg_temp_free(tcgv_addr);
4051 tcg_temp_free_i32(tcgv_is_dcbzl);
4052 }
4053
4054 /* dst / dstt */
4055 static void gen_dst(DisasContext *ctx)
4056 {
4057 if (rA(ctx->opcode) == 0) {
4058 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4059 } else {
4060 /* interpreted as no-op */
4061 }
4062 }
4063
4064 /* dstst /dststt */
4065 static void gen_dstst(DisasContext *ctx)
4066 {
4067 if (rA(ctx->opcode) == 0) {
4068 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4069 } else {
4070 /* interpreted as no-op */
4071 }
4072
4073 }
4074
4075 /* dss / dssall */
4076 static void gen_dss(DisasContext *ctx)
4077 {
4078 /* interpreted as no-op */
4079 }
4080
4081 /* icbi */
4082 static void gen_icbi(DisasContext *ctx)
4083 {
4084 TCGv t0;
4085 gen_set_access_type(ctx, ACCESS_CACHE);
4086 /* NIP cannot be restored if the memory exception comes from an helper */
4087 gen_update_nip(ctx, ctx->nip - 4);
4088 t0 = tcg_temp_new();
4089 gen_addr_reg_index(ctx, t0);
4090 gen_helper_icbi(cpu_env, t0);
4091 tcg_temp_free(t0);
4092 }
4093
4094 /* Optional: */
4095 /* dcba */
4096 static void gen_dcba(DisasContext *ctx)
4097 {
4098 /* interpreted as no-op */
4099 /* XXX: specification say this is treated as a store by the MMU
4100 * but does not generate any exception
4101 */
4102 }
4103
4104 /*** Segment register manipulation ***/
4105 /* Supervisor only: */
4106
4107 /* mfsr */
4108 static void gen_mfsr(DisasContext *ctx)
4109 {
4110 #if defined(CONFIG_USER_ONLY)
4111 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4112 #else
4113 TCGv t0;
4114 if (unlikely(!ctx->mem_idx)) {
4115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4116 return;
4117 }
4118 t0 = tcg_const_tl(SR(ctx->opcode));
4119 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4120 tcg_temp_free(t0);
4121 #endif
4122 }
4123
4124 /* mfsrin */
4125 static void gen_mfsrin(DisasContext *ctx)
4126 {
4127 #if defined(CONFIG_USER_ONLY)
4128 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4129 #else
4130 TCGv t0;
4131 if (unlikely(!ctx->mem_idx)) {
4132 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4133 return;
4134 }
4135 t0 = tcg_temp_new();
4136 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4137 tcg_gen_andi_tl(t0, t0, 0xF);
4138 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4139 tcg_temp_free(t0);
4140 #endif
4141 }
4142
4143 /* mtsr */
4144 static void gen_mtsr(DisasContext *ctx)
4145 {
4146 #if defined(CONFIG_USER_ONLY)
4147 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4148 #else
4149 TCGv t0;
4150 if (unlikely(!ctx->mem_idx)) {
4151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4152 return;
4153 }
4154 t0 = tcg_const_tl(SR(ctx->opcode));
4155 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4156 tcg_temp_free(t0);
4157 #endif
4158 }
4159
4160 /* mtsrin */
4161 static void gen_mtsrin(DisasContext *ctx)
4162 {
4163 #if defined(CONFIG_USER_ONLY)
4164 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4165 #else
4166 TCGv t0;
4167 if (unlikely(!ctx->mem_idx)) {
4168 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4169 return;
4170 }
4171 t0 = tcg_temp_new();
4172 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4173 tcg_gen_andi_tl(t0, t0, 0xF);
4174 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4175 tcg_temp_free(t0);
4176 #endif
4177 }
4178
4179 #if defined(TARGET_PPC64)
4180 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4181
4182 /* mfsr */
4183 static void gen_mfsr_64b(DisasContext *ctx)
4184 {
4185 #if defined(CONFIG_USER_ONLY)
4186 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4187 #else
4188 TCGv t0;
4189 if (unlikely(!ctx->mem_idx)) {
4190 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4191 return;
4192 }
4193 t0 = tcg_const_tl(SR(ctx->opcode));
4194 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4195 tcg_temp_free(t0);
4196 #endif
4197 }
4198
4199 /* mfsrin */
4200 static void gen_mfsrin_64b(DisasContext *ctx)
4201 {
4202 #if defined(CONFIG_USER_ONLY)
4203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4204 #else
4205 TCGv t0;
4206 if (unlikely(!ctx->mem_idx)) {
4207 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4208 return;
4209 }
4210 t0 = tcg_temp_new();
4211 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4212 tcg_gen_andi_tl(t0, t0, 0xF);
4213 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4214 tcg_temp_free(t0);
4215 #endif
4216 }
4217
4218 /* mtsr */
4219 static void gen_mtsr_64b(DisasContext *ctx)
4220 {
4221 #if defined(CONFIG_USER_ONLY)
4222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4223 #else
4224 TCGv t0;
4225 if (unlikely(!ctx->mem_idx)) {
4226 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4227 return;
4228 }
4229 t0 = tcg_const_tl(SR(ctx->opcode));
4230 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4231 tcg_temp_free(t0);
4232 #endif
4233 }
4234
4235 /* mtsrin */
4236 static void gen_mtsrin_64b(DisasContext *ctx)
4237 {
4238 #if defined(CONFIG_USER_ONLY)
4239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4240 #else
4241 TCGv t0;
4242 if (unlikely(!ctx->mem_idx)) {
4243 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4244 return;
4245 }
4246 t0 = tcg_temp_new();
4247 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4248 tcg_gen_andi_tl(t0, t0, 0xF);
4249 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4250 tcg_temp_free(t0);
4251 #endif
4252 }
4253
4254 /* slbmte */
4255 static void gen_slbmte(DisasContext *ctx)
4256 {
4257 #if defined(CONFIG_USER_ONLY)
4258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4259 #else
4260 if (unlikely(!ctx->mem_idx)) {
4261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4262 return;
4263 }
4264 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4265 cpu_gpr[rS(ctx->opcode)]);
4266 #endif
4267 }
4268
4269 static void gen_slbmfee(DisasContext *ctx)
4270 {
4271 #if defined(CONFIG_USER_ONLY)
4272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4273 #else
4274 if (unlikely(!ctx->mem_idx)) {
4275 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4276 return;
4277 }
4278 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4279 cpu_gpr[rB(ctx->opcode)]);
4280 #endif
4281 }
4282
4283 static void gen_slbmfev(DisasContext *ctx)
4284 {
4285 #if defined(CONFIG_USER_ONLY)
4286 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4287 #else
4288 if (unlikely(!ctx->mem_idx)) {
4289 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4290 return;
4291 }
4292 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4293 cpu_gpr[rB(ctx->opcode)]);
4294 #endif
4295 }
4296 #endif /* defined(TARGET_PPC64) */
4297
4298 /*** Lookaside buffer management ***/
4299 /* Optional & mem_idx only: */
4300
4301 /* tlbia */
4302 static void gen_tlbia(DisasContext *ctx)
4303 {
4304 #if defined(CONFIG_USER_ONLY)
4305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4306 #else
4307 if (unlikely(!ctx->mem_idx)) {
4308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4309 return;
4310 }
4311 gen_helper_tlbia(cpu_env);
4312 #endif
4313 }
4314
4315 /* tlbiel */
4316 static void gen_tlbiel(DisasContext *ctx)
4317 {
4318 #if defined(CONFIG_USER_ONLY)
4319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4320 #else
4321 if (unlikely(!ctx->mem_idx)) {
4322 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4323 return;
4324 }
4325 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4326 #endif
4327 }
4328
4329 /* tlbie */
4330 static void gen_tlbie(DisasContext *ctx)
4331 {
4332 #if defined(CONFIG_USER_ONLY)
4333 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4334 #else
4335 if (unlikely(!ctx->mem_idx)) {
4336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4337 return;
4338 }
4339 #if defined(TARGET_PPC64)
4340 if (!ctx->sf_mode) {
4341 TCGv t0 = tcg_temp_new();
4342 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4343 gen_helper_tlbie(cpu_env, t0);
4344 tcg_temp_free(t0);
4345 } else
4346 #endif
4347 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4348 #endif
4349 }
4350
4351 /* tlbsync */
4352 static void gen_tlbsync(DisasContext *ctx)
4353 {
4354 #if defined(CONFIG_USER_ONLY)
4355 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4356 #else
4357 if (unlikely(!ctx->mem_idx)) {
4358 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4359 return;
4360 }
4361 /* This has no effect: it should ensure that all previous
4362 * tlbie have completed
4363 */
4364 gen_stop_exception(ctx);
4365 #endif
4366 }
4367
4368 #if defined(TARGET_PPC64)
4369 /* slbia */
4370 static void gen_slbia(DisasContext *ctx)
4371 {
4372 #if defined(CONFIG_USER_ONLY)
4373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4374 #else
4375 if (unlikely(!ctx->mem_idx)) {
4376 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4377 return;
4378 }
4379 gen_helper_slbia(cpu_env);
4380 #endif
4381 }
4382
4383 /* slbie */
4384 static void gen_slbie(DisasContext *ctx)
4385 {
4386 #if defined(CONFIG_USER_ONLY)
4387 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4388 #else
4389 if (unlikely(!ctx->mem_idx)) {
4390 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4391 return;
4392 }
4393 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4394 #endif
4395 }
4396 #endif
4397
4398 /*** External control ***/
4399 /* Optional: */
4400
4401 /* eciwx */
4402 static void gen_eciwx(DisasContext *ctx)
4403 {
4404 TCGv t0;
4405 /* Should check EAR[E] ! */
4406 gen_set_access_type(ctx, ACCESS_EXT);
4407 t0 = tcg_temp_new();
4408 gen_addr_reg_index(ctx, t0);
4409 gen_check_align(ctx, t0, 0x03);
4410 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4411 tcg_temp_free(t0);
4412 }
4413
4414 /* ecowx */
4415 static void gen_ecowx(DisasContext *ctx)
4416 {
4417 TCGv t0;
4418 /* Should check EAR[E] ! */
4419 gen_set_access_type(ctx, ACCESS_EXT);
4420 t0 = tcg_temp_new();
4421 gen_addr_reg_index(ctx, t0);
4422 gen_check_align(ctx, t0, 0x03);
4423 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4424 tcg_temp_free(t0);
4425 }
4426
4427 /* PowerPC 601 specific instructions */
4428
4429 /* abs - abs. */
4430 static void gen_abs(DisasContext *ctx)
4431 {
4432 int l1 = gen_new_label();
4433 int l2 = gen_new_label();
4434 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4435 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4436 tcg_gen_br(l2);
4437 gen_set_label(l1);
4438 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4439 gen_set_label(l2);
4440 if (unlikely(Rc(ctx->opcode) != 0))
4441 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4442 }
4443
4444 /* abso - abso. */
4445 static void gen_abso(DisasContext *ctx)
4446 {
4447 int l1 = gen_new_label();
4448 int l2 = gen_new_label();
4449 int l3 = gen_new_label();
4450 /* Start with XER OV disabled, the most likely case */
4451 tcg_gen_movi_tl(cpu_ov, 0);
4452 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4453 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4454 tcg_gen_movi_tl(cpu_ov, 1);
4455 tcg_gen_movi_tl(cpu_so, 1);
4456 tcg_gen_br(l2);
4457 gen_set_label(l1);
4458 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4459 tcg_gen_br(l3);
4460 gen_set_label(l2);
4461 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4462 gen_set_label(l3);
4463 if (unlikely(Rc(ctx->opcode) != 0))
4464 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4465 }
4466
4467 /* clcs */
4468 static void gen_clcs(DisasContext *ctx)
4469 {
4470 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4471 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4472 tcg_temp_free_i32(t0);
4473 /* Rc=1 sets CR0 to an undefined state */
4474 }
4475
4476 /* div - div. */
4477 static void gen_div(DisasContext *ctx)
4478 {
4479 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4480 cpu_gpr[rB(ctx->opcode)]);
4481 if (unlikely(Rc(ctx->opcode) != 0))
4482 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4483 }
4484
4485 /* divo - divo. */
4486 static void gen_divo(DisasContext *ctx)
4487 {
4488 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4489 cpu_gpr[rB(ctx->opcode)]);
4490 if (unlikely(Rc(ctx->opcode) != 0))
4491 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4492 }
4493
4494 /* divs - divs. */
4495 static void gen_divs(DisasContext *ctx)
4496 {
4497 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4498 cpu_gpr[rB(ctx->opcode)]);
4499 if (unlikely(Rc(ctx->opcode) != 0))
4500 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4501 }
4502
4503 /* divso - divso. */
4504 static void gen_divso(DisasContext *ctx)
4505 {
4506 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4507 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4508 if (unlikely(Rc(ctx->opcode) != 0))
4509 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4510 }
4511
4512 /* doz - doz. */
4513 static void gen_doz(DisasContext *ctx)
4514 {
4515 int l1 = gen_new_label();
4516 int l2 = gen_new_label();
4517 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4518 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4519 tcg_gen_br(l2);
4520 gen_set_label(l1);
4521 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4522 gen_set_label(l2);
4523 if (unlikely(Rc(ctx->opcode) != 0))
4524 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4525 }
4526
4527 /* dozo - dozo. */
4528 static void gen_dozo(DisasContext *ctx)
4529 {
4530 int l1 = gen_new_label();
4531 int l2 = gen_new_label();
4532 TCGv t0 = tcg_temp_new();
4533 TCGv t1 = tcg_temp_new();
4534 TCGv t2 = tcg_temp_new();
4535 /* Start with XER OV disabled, the most likely case */
4536 tcg_gen_movi_tl(cpu_ov, 0);
4537 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4538 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4539 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4540 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4541 tcg_gen_andc_tl(t1, t1, t2);
4542 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4543 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4544 tcg_gen_movi_tl(cpu_ov, 1);
4545 tcg_gen_movi_tl(cpu_so, 1);
4546 tcg_gen_br(l2);
4547 gen_set_label(l1);
4548 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4549 gen_set_label(l2);
4550 tcg_temp_free(t0);
4551 tcg_temp_free(t1);
4552 tcg_temp_free(t2);
4553 if (unlikely(Rc(ctx->opcode) != 0))
4554 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4555 }
4556
4557 /* dozi */
4558 static void gen_dozi(DisasContext *ctx)
4559 {
4560 target_long simm = SIMM(ctx->opcode);
4561 int l1 = gen_new_label();
4562 int l2 = gen_new_label();
4563 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4564 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4565 tcg_gen_br(l2);
4566 gen_set_label(l1);
4567 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4568 gen_set_label(l2);
4569 if (unlikely(Rc(ctx->opcode) != 0))
4570 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4571 }
4572
4573 /* lscbx - lscbx. */
4574 static void gen_lscbx(DisasContext *ctx)
4575 {
4576 TCGv t0 = tcg_temp_new();
4577 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4578 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4579 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4580
4581 gen_addr_reg_index(ctx, t0);
4582 /* NIP cannot be restored if the memory exception comes from an helper */
4583 gen_update_nip(ctx, ctx->nip - 4);
4584 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4585 tcg_temp_free_i32(t1);
4586 tcg_temp_free_i32(t2);
4587 tcg_temp_free_i32(t3);
4588 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4589 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4590 if (unlikely(Rc(ctx->opcode) != 0))
4591 gen_set_Rc0(ctx, t0);
4592 tcg_temp_free(t0);
4593 }
4594
4595 /* maskg - maskg. */
4596 static void gen_maskg(DisasContext *ctx)
4597 {
4598 int l1 = gen_new_label();
4599 TCGv t0 = tcg_temp_new();
4600 TCGv t1 = tcg_temp_new();
4601 TCGv t2 = tcg_temp_new();
4602 TCGv t3 = tcg_temp_new();
4603 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4604 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4605 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4606 tcg_gen_addi_tl(t2, t0, 1);
4607 tcg_gen_shr_tl(t2, t3, t2);
4608 tcg_gen_shr_tl(t3, t3, t1);
4609 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4610 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4611 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4612 gen_set_label(l1);
4613 tcg_temp_free(t0);
4614 tcg_temp_free(t1);
4615 tcg_temp_free(t2);
4616 tcg_temp_free(t3);
4617 if (unlikely(Rc(ctx->opcode) != 0))
4618 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4619 }
4620
4621 /* maskir - maskir. */
4622 static void gen_maskir(DisasContext *ctx)
4623 {
4624 TCGv t0 = tcg_temp_new();
4625 TCGv t1 = tcg_temp_new();
4626 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4627 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4628 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4629 tcg_temp_free(t0);
4630 tcg_temp_free(t1);
4631 if (unlikely(Rc(ctx->opcode) != 0))
4632 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4633 }
4634
4635 /* mul - mul. */
4636 static void gen_mul(DisasContext *ctx)
4637 {
4638 TCGv_i64 t0 = tcg_temp_new_i64();
4639 TCGv_i64 t1 = tcg_temp_new_i64();
4640 TCGv t2 = tcg_temp_new();
4641 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4642 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4643 tcg_gen_mul_i64(t0, t0, t1);
4644 tcg_gen_trunc_i64_tl(t2, t0);
4645 gen_store_spr(SPR_MQ, t2);
4646 tcg_gen_shri_i64(t1, t0, 32);
4647 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4648 tcg_temp_free_i64(t0);
4649 tcg_temp_free_i64(t1);
4650 tcg_temp_free(t2);
4651 if (unlikely(Rc(ctx->opcode) != 0))
4652 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4653 }
4654
4655 /* mulo - mulo. */
4656 static void gen_mulo(DisasContext *ctx)
4657 {
4658 int l1 = gen_new_label();
4659 TCGv_i64 t0 = tcg_temp_new_i64();
4660 TCGv_i64 t1 = tcg_temp_new_i64();
4661 TCGv t2 = tcg_temp_new();
4662 /* Start with XER OV disabled, the most likely case */
4663 tcg_gen_movi_tl(cpu_ov, 0);
4664 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4665 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4666 tcg_gen_mul_i64(t0, t0, t1);
4667 tcg_gen_trunc_i64_tl(t2, t0);
4668 gen_store_spr(SPR_MQ, t2);
4669 tcg_gen_shri_i64(t1, t0, 32);
4670 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4671 tcg_gen_ext32s_i64(t1, t0);
4672 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4673 tcg_gen_movi_tl(cpu_ov, 1);
4674 tcg_gen_movi_tl(cpu_so, 1);
4675 gen_set_label(l1);
4676 tcg_temp_free_i64(t0);
4677 tcg_temp_free_i64(t1);
4678 tcg_temp_free(t2);
4679 if (unlikely(Rc(ctx->opcode) != 0))
4680 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4681 }
4682
4683 /* nabs - nabs. */
4684 static void gen_nabs(DisasContext *ctx)
4685 {
4686 int l1 = gen_new_label();
4687 int l2 = gen_new_label();
4688 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4689 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4690 tcg_gen_br(l2);
4691 gen_set_label(l1);
4692 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4693 gen_set_label(l2);
4694 if (unlikely(Rc(ctx->opcode) != 0))
4695 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4696 }
4697
4698 /* nabso - nabso. */
4699 static void gen_nabso(DisasContext *ctx)
4700 {
4701 int l1 = gen_new_label();
4702 int l2 = gen_new_label();
4703 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4704 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4705 tcg_gen_br(l2);
4706 gen_set_label(l1);
4707 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4708 gen_set_label(l2);
4709 /* nabs never overflows */
4710 tcg_gen_movi_tl(cpu_ov, 0);
4711 if (unlikely(Rc(ctx->opcode) != 0))
4712 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4713 }
4714
4715 /* rlmi - rlmi. */
4716 static void gen_rlmi(DisasContext *ctx)
4717 {
4718 uint32_t mb = MB(ctx->opcode);
4719 uint32_t me = ME(ctx->opcode);
4720 TCGv t0 = tcg_temp_new();
4721 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4722 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4723 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4724 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4725 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4726 tcg_temp_free(t0);
4727 if (unlikely(Rc(ctx->opcode) != 0))
4728 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4729 }
4730
4731 /* rrib - rrib. */
4732 static void gen_rrib(DisasContext *ctx)
4733 {
4734 TCGv t0 = tcg_temp_new();
4735 TCGv t1 = tcg_temp_new();
4736 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4737 tcg_gen_movi_tl(t1, 0x80000000);
4738 tcg_gen_shr_tl(t1, t1, t0);
4739 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4740 tcg_gen_and_tl(t0, t0, t1);
4741 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4742 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4743 tcg_temp_free(t0);
4744 tcg_temp_free(t1);
4745 if (unlikely(Rc(ctx->opcode) != 0))
4746 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4747 }
4748
4749 /* sle - sle. */
4750 static void gen_sle(DisasContext *ctx)
4751 {
4752 TCGv t0 = tcg_temp_new();
4753 TCGv t1 = tcg_temp_new();
4754 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4755 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4756 tcg_gen_subfi_tl(t1, 32, t1);
4757 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4758 tcg_gen_or_tl(t1, t0, t1);
4759 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4760 gen_store_spr(SPR_MQ, t1);
4761 tcg_temp_free(t0);
4762 tcg_temp_free(t1);
4763 if (unlikely(Rc(ctx->opcode) != 0))
4764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4765 }
4766
4767 /* sleq - sleq. */
4768 static void gen_sleq(DisasContext *ctx)
4769 {
4770 TCGv t0 = tcg_temp_new();
4771 TCGv t1 = tcg_temp_new();
4772 TCGv t2 = tcg_temp_new();
4773 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4774 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4775 tcg_gen_shl_tl(t2, t2, t0);
4776 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4777 gen_load_spr(t1, SPR_MQ);
4778 gen_store_spr(SPR_MQ, t0);
4779 tcg_gen_and_tl(t0, t0, t2);
4780 tcg_gen_andc_tl(t1, t1, t2);
4781 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4782 tcg_temp_free(t0);
4783 tcg_temp_free(t1);
4784 tcg_temp_free(t2);
4785 if (unlikely(Rc(ctx->opcode) != 0))
4786 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4787 }
4788
4789 /* sliq - sliq. */
4790 static void gen_sliq(DisasContext *ctx)
4791 {
4792 int sh = SH(ctx->opcode);
4793 TCGv t0 = tcg_temp_new();
4794 TCGv t1 = tcg_temp_new();
4795 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4796 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4797 tcg_gen_or_tl(t1, t0, t1);
4798 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4799 gen_store_spr(SPR_MQ, t1);
4800 tcg_temp_free(t0);
4801 tcg_temp_free(t1);
4802 if (unlikely(Rc(ctx->opcode) != 0))
4803 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4804 }
4805
4806 /* slliq - slliq. */
4807 static void gen_slliq(DisasContext *ctx)
4808 {
4809 int sh = SH(ctx->opcode);
4810 TCGv t0 = tcg_temp_new();
4811 TCGv t1 = tcg_temp_new();
4812 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4813 gen_load_spr(t1, SPR_MQ);
4814 gen_store_spr(SPR_MQ, t0);
4815 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4816 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4817 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4818 tcg_temp_free(t0);
4819 tcg_temp_free(t1);
4820 if (unlikely(Rc(ctx->opcode) != 0))
4821 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4822 }
4823
4824 /* sllq - sllq. */
4825 static void gen_sllq(DisasContext *ctx)
4826 {
4827 int l1 = gen_new_label();
4828 int l2 = gen_new_label();
4829 TCGv t0 = tcg_temp_local_new();
4830 TCGv t1 = tcg_temp_local_new();
4831 TCGv t2 = tcg_temp_local_new();
4832 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4833 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4834 tcg_gen_shl_tl(t1, t1, t2);
4835 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4836 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4837 gen_load_spr(t0, SPR_MQ);
4838 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4839 tcg_gen_br(l2);
4840 gen_set_label(l1);
4841 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4842 gen_load_spr(t2, SPR_MQ);
4843 tcg_gen_andc_tl(t1, t2, t1);
4844 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4845 gen_set_label(l2);
4846 tcg_temp_free(t0);
4847 tcg_temp_free(t1);
4848 tcg_temp_free(t2);
4849 if (unlikely(Rc(ctx->opcode) != 0))
4850 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4851 }
4852
4853 /* slq - slq. */
4854 static void gen_slq(DisasContext *ctx)
4855 {
4856 int l1 = gen_new_label();
4857 TCGv t0 = tcg_temp_new();
4858 TCGv t1 = tcg_temp_new();
4859 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4860 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4861 tcg_gen_subfi_tl(t1, 32, t1);
4862 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4863 tcg_gen_or_tl(t1, t0, t1);
4864 gen_store_spr(SPR_MQ, t1);
4865 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4866 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4867 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4868 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4869 gen_set_label(l1);
4870 tcg_temp_free(t0);
4871 tcg_temp_free(t1);
4872 if (unlikely(Rc(ctx->opcode) != 0))
4873 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4874 }
4875
4876 /* sraiq - sraiq. */
4877 static void gen_sraiq(DisasContext *ctx)
4878 {
4879 int sh = SH(ctx->opcode);
4880 int l1 = gen_new_label();
4881 TCGv t0 = tcg_temp_new();
4882 TCGv t1 = tcg_temp_new();
4883 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4884 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4885 tcg_gen_or_tl(t0, t0, t1);
4886 gen_store_spr(SPR_MQ, t0);
4887 tcg_gen_movi_tl(cpu_ca, 0);
4888 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4889 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4890 tcg_gen_movi_tl(cpu_ca, 1);
4891 gen_set_label(l1);
4892 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4893 tcg_temp_free(t0);
4894 tcg_temp_free(t1);
4895 if (unlikely(Rc(ctx->opcode) != 0))
4896 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4897 }
4898
4899 /* sraq - sraq. */
4900 static void gen_sraq(DisasContext *ctx)
4901 {
4902 int l1 = gen_new_label();
4903 int l2 = gen_new_label();
4904 TCGv t0 = tcg_temp_new();
4905 TCGv t1 = tcg_temp_local_new();
4906 TCGv t2 = tcg_temp_local_new();
4907 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4908 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4909 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4910 tcg_gen_subfi_tl(t2, 32, t2);
4911 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4912 tcg_gen_or_tl(t0, t0, t2);
4913 gen_store_spr(SPR_MQ, t0);
4914 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4915 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4916 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4917 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4918 gen_set_label(l1);
4919 tcg_temp_free(t0);
4920 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4921 tcg_gen_movi_tl(cpu_ca, 0);
4922 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4923 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4924 tcg_gen_movi_tl(cpu_ca, 1);
4925 gen_set_label(l2);
4926 tcg_temp_free(t1);
4927 tcg_temp_free(t2);
4928 if (unlikely(Rc(ctx->opcode) != 0))
4929 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4930 }
4931
4932 /* sre - sre. */
4933 static void gen_sre(DisasContext *ctx)
4934 {
4935 TCGv t0 = tcg_temp_new();
4936 TCGv t1 = tcg_temp_new();
4937 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4938 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4939 tcg_gen_subfi_tl(t1, 32, t1);
4940 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4941 tcg_gen_or_tl(t1, t0, t1);
4942 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4943 gen_store_spr(SPR_MQ, t1);
4944 tcg_temp_free(t0);
4945 tcg_temp_free(t1);
4946 if (unlikely(Rc(ctx->opcode) != 0))
4947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4948 }
4949
4950 /* srea - srea. */
4951 static void gen_srea(DisasContext *ctx)
4952 {
4953 TCGv t0 = tcg_temp_new();
4954 TCGv t1 = tcg_temp_new();
4955 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4956 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4957 gen_store_spr(SPR_MQ, t0);
4958 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4959 tcg_temp_free(t0);
4960 tcg_temp_free(t1);
4961 if (unlikely(Rc(ctx->opcode) != 0))
4962 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4963 }
4964
4965 /* sreq */
4966 static void gen_sreq(DisasContext *ctx)
4967 {
4968 TCGv t0 = tcg_temp_new();
4969 TCGv t1 = tcg_temp_new();
4970 TCGv t2 = tcg_temp_new();
4971 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4972 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4973 tcg_gen_shr_tl(t1, t1, t0);
4974 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4975 gen_load_spr(t2, SPR_MQ);
4976 gen_store_spr(SPR_MQ, t0);
4977 tcg_gen_and_tl(t0, t0, t1);
4978 tcg_gen_andc_tl(t2, t2, t1);
4979 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4980 tcg_temp_free(t0);
4981 tcg_temp_free(t1);
4982 tcg_temp_free(t2);
4983 if (unlikely(Rc(ctx->opcode) != 0))
4984 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4985 }
4986
4987 /* sriq */
4988 static void gen_sriq(DisasContext *ctx)
4989 {
4990 int sh = SH(ctx->opcode);
4991 TCGv t0 = tcg_temp_new();
4992 TCGv t1 = tcg_temp_new();
4993 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4994 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4995 tcg_gen_or_tl(t1, t0, t1);
4996 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4997 gen_store_spr(SPR_MQ, t1);
4998 tcg_temp_free(t0);
4999 tcg_temp_free(t1);
5000 if (unlikely(Rc(ctx->opcode) != 0))
5001 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5002 }
5003
5004 /* srliq */
5005 static void gen_srliq(DisasContext *ctx)
5006 {
5007 int sh = SH(ctx->opcode);
5008 TCGv t0 = tcg_temp_new();
5009 TCGv t1 = tcg_temp_new();
5010 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5011 gen_load_spr(t1, SPR_MQ);
5012 gen_store_spr(SPR_MQ, t0);
5013 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5014 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5015 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5016 tcg_temp_free(t0);
5017 tcg_temp_free(t1);
5018 if (unlikely(Rc(ctx->opcode) != 0))
5019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5020 }
5021
5022 /* srlq */
5023 static void gen_srlq(DisasContext *ctx)
5024 {
5025 int l1 = gen_new_label();
5026 int l2 = gen_new_label();
5027 TCGv t0 = tcg_temp_local_new();
5028 TCGv t1 = tcg_temp_local_new();
5029 TCGv t2 = tcg_temp_local_new();
5030 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5031 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5032 tcg_gen_shr_tl(t2, t1, t2);
5033 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5034 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5035 gen_load_spr(t0, SPR_MQ);
5036 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5037 tcg_gen_br(l2);
5038 gen_set_label(l1);
5039 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5040 tcg_gen_and_tl(t0, t0, t2);
5041 gen_load_spr(t1, SPR_MQ);
5042 tcg_gen_andc_tl(t1, t1, t2);
5043 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5044 gen_set_label(l2);
5045 tcg_temp_free(t0);
5046 tcg_temp_free(t1);
5047 tcg_temp_free(t2);
5048 if (unlikely(Rc(ctx->opcode) != 0))
5049 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5050 }
5051
5052 /* srq */
5053 static void gen_srq(DisasContext *ctx)
5054 {
5055 int l1 = gen_new_label();
5056 TCGv t0 = tcg_temp_new();
5057 TCGv t1 = tcg_temp_new();
5058 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5059 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5060 tcg_gen_subfi_tl(t1, 32, t1);
5061 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5062 tcg_gen_or_tl(t1, t0, t1);
5063 gen_store_spr(SPR_MQ, t1);
5064 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5065 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5066 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5067 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5068 gen_set_label(l1);
5069 tcg_temp_free(t0);
5070 tcg_temp_free(t1);
5071 if (unlikely(Rc(ctx->opcode) != 0))
5072 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5073 }
5074
5075 /* PowerPC 602 specific instructions */
5076
5077 /* dsa */
5078 static void gen_dsa(DisasContext *ctx)
5079 {
5080 /* XXX: TODO */
5081 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5082 }
5083
5084 /* esa */
5085 static void gen_esa(DisasContext *ctx)
5086 {
5087 /* XXX: TODO */
5088 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5089 }
5090
5091 /* mfrom */
5092 static void gen_mfrom(DisasContext *ctx)
5093 {
5094 #if defined(CONFIG_USER_ONLY)
5095 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5096 #else
5097 if (unlikely(!ctx->mem_idx)) {
5098 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5099 return;
5100 }
5101 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5102 #endif
5103 }
5104
5105 /* 602 - 603 - G2 TLB management */
5106
5107 /* tlbld */
5108 static void gen_tlbld_6xx(DisasContext *ctx)
5109 {
5110 #if defined(CONFIG_USER_ONLY)
5111 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5112 #else
5113 if (unlikely(!ctx->mem_idx)) {
5114 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5115 return;
5116 }
5117 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5118 #endif
5119 }
5120
5121 /* tlbli */
5122 static void gen_tlbli_6xx(DisasContext *ctx)
5123 {
5124 #if defined(CONFIG_USER_ONLY)
5125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5126 #else
5127 if (unlikely(!ctx->mem_idx)) {
5128 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5129 return;
5130 }
5131 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5132 #endif
5133 }
5134
5135 /* 74xx TLB management */
5136
5137 /* tlbld */
5138 static void gen_tlbld_74xx(DisasContext *ctx)
5139 {
5140 #if defined(CONFIG_USER_ONLY)
5141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5142 #else
5143 if (unlikely(!ctx->mem_idx)) {
5144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5145 return;
5146 }
5147 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5148 #endif
5149 }
5150
5151 /* tlbli */
5152 static void gen_tlbli_74xx(DisasContext *ctx)
5153 {
5154 #if defined(CONFIG_USER_ONLY)
5155 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5156 #else
5157 if (unlikely(!ctx->mem_idx)) {
5158 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5159 return;
5160 }
5161 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5162 #endif
5163 }
5164
5165 /* POWER instructions not in PowerPC 601 */
5166
5167 /* clf */
5168 static void gen_clf(DisasContext *ctx)
5169 {
5170 /* Cache line flush: implemented as no-op */
5171 }
5172
5173 /* cli */
5174 static void gen_cli(DisasContext *ctx)
5175 {
5176 /* Cache line invalidate: privileged and treated as no-op */
5177 #if defined(CONFIG_USER_ONLY)
5178 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5179 #else
5180 if (unlikely(!ctx->mem_idx)) {
5181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5182 return;
5183 }
5184 #endif
5185 }
5186
5187 /* dclst */
5188 static void gen_dclst(DisasContext *ctx)
5189 {
5190 /* Data cache line store: treated as no-op */
5191 }
5192
5193 static void gen_mfsri(DisasContext *ctx)
5194 {
5195 #if defined(CONFIG_USER_ONLY)
5196 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5197 #else
5198 int ra = rA(ctx->opcode);
5199 int rd = rD(ctx->opcode);
5200 TCGv t0;
5201 if (unlikely(!ctx->mem_idx)) {
5202 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5203 return;
5204 }
5205 t0 = tcg_temp_new();
5206 gen_addr_reg_index(ctx, t0);
5207 tcg_gen_shri_tl(t0, t0, 28);
5208 tcg_gen_andi_tl(t0, t0, 0xF);
5209 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5210 tcg_temp_free(t0);
5211 if (ra != 0 && ra != rd)
5212 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5213 #endif
5214 }
5215
5216 static void gen_rac(DisasContext *ctx)
5217 {
5218 #if defined(CONFIG_USER_ONLY)
5219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5220 #else
5221 TCGv t0;
5222 if (unlikely(!ctx->mem_idx)) {
5223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5224 return;
5225 }
5226 t0 = tcg_temp_new();
5227 gen_addr_reg_index(ctx, t0);
5228 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5229 tcg_temp_free(t0);
5230 #endif
5231 }
5232
5233 static void gen_rfsvc(DisasContext *ctx)
5234 {
5235 #if defined(CONFIG_USER_ONLY)
5236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5237 #else
5238 if (unlikely(!ctx->mem_idx)) {
5239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5240 return;
5241 }
5242 gen_helper_rfsvc(cpu_env);
5243 gen_sync_exception(ctx);
5244 #endif
5245 }
5246
5247 /* svc is not implemented for now */
5248
5249 /* POWER2 specific instructions */
5250 /* Quad manipulation (load/store two floats at a time) */
5251
5252 /* lfq */
5253 static void gen_lfq(DisasContext *ctx)
5254 {
5255 int rd = rD(ctx->opcode);
5256 TCGv t0;
5257 gen_set_access_type(ctx, ACCESS_FLOAT);
5258 t0 = tcg_temp_new();
5259 gen_addr_imm_index(ctx, t0, 0);
5260 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5261 gen_addr_add(ctx, t0, t0, 8);
5262 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5263 tcg_temp_free(t0);
5264 }
5265
5266 /* lfqu */
5267 static void gen_lfqu(DisasContext *ctx)
5268 {
5269 int ra = rA(ctx->opcode);
5270 int rd = rD(ctx->opcode);
5271 TCGv t0, t1;
5272 gen_set_access_type(ctx, ACCESS_FLOAT);
5273 t0 = tcg_temp_new();
5274 t1 = tcg_temp_new();
5275 gen_addr_imm_index(ctx, t0, 0);
5276 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5277 gen_addr_add(ctx, t1, t0, 8);
5278 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5279 if (ra != 0)
5280 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5281 tcg_temp_free(t0);
5282 tcg_temp_free(t1);
5283 }
5284
5285 /* lfqux */
5286 static void gen_lfqux(DisasContext *ctx)
5287 {
5288 int ra = rA(ctx->opcode);
5289 int rd = rD(ctx->opcode);
5290 gen_set_access_type(ctx, ACCESS_FLOAT);
5291 TCGv t0, t1;
5292 t0 = tcg_temp_new();
5293 gen_addr_reg_index(ctx, t0);
5294 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5295 t1 = tcg_temp_new();
5296 gen_addr_add(ctx, t1, t0, 8);
5297 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5298 tcg_temp_free(t1);
5299 if (ra != 0)
5300 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5301 tcg_temp_free(t0);
5302 }
5303
5304 /* lfqx */
5305 static void gen_lfqx(DisasContext *ctx)
5306 {
5307 int rd = rD(ctx->opcode);
5308 TCGv t0;
5309 gen_set_access_type(ctx, ACCESS_FLOAT);
5310 t0 = tcg_temp_new();
5311 gen_addr_reg_index(ctx, t0);
5312 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5313 gen_addr_add(ctx, t0, t0, 8);
5314 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5315 tcg_temp_free(t0);
5316 }
5317
5318 /* stfq */
5319 static void gen_stfq(DisasContext *ctx)
5320 {
5321 int rd = rD(ctx->opcode);
5322 TCGv t0;
5323 gen_set_access_type(ctx, ACCESS_FLOAT);
5324 t0 = tcg_temp_new();
5325 gen_addr_imm_index(ctx, t0, 0);
5326 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5327 gen_addr_add(ctx, t0, t0, 8);
5328 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5329 tcg_temp_free(t0);
5330 }
5331
5332 /* stfqu */
5333 static void gen_stfqu(DisasContext *ctx)
5334 {
5335 int ra = rA(ctx->opcode);
5336 int rd = rD(ctx->opcode);
5337 TCGv t0, t1;
5338 gen_set_access_type(ctx, ACCESS_FLOAT);
5339 t0 = tcg_temp_new();
5340 gen_addr_imm_index(ctx, t0, 0);
5341 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5342 t1 = tcg_temp_new();
5343 gen_addr_add(ctx, t1, t0, 8);
5344 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5345 tcg_temp_free(t1);
5346 if (ra != 0)
5347 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5348 tcg_temp_free(t0);
5349 }
5350
5351 /* stfqux */
5352 static void gen_stfqux(DisasContext *ctx)
5353 {
5354 int ra = rA(ctx->opcode);
5355 int rd = rD(ctx->opcode);
5356 TCGv t0, t1;
5357 gen_set_access_type(ctx, ACCESS_FLOAT);
5358 t0 = tcg_temp_new();
5359 gen_addr_reg_index(ctx, t0);
5360 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5361 t1 = tcg_temp_new();
5362 gen_addr_add(ctx, t1, t0, 8);
5363 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5364 tcg_temp_free(t1);
5365 if (ra != 0)
5366 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5367 tcg_temp_free(t0);
5368 }
5369
5370 /* stfqx */
5371 static void gen_stfqx(DisasContext *ctx)
5372 {
5373 int rd = rD(ctx->opcode);
5374 TCGv t0;
5375 gen_set_access_type(ctx, ACCESS_FLOAT);
5376 t0 = tcg_temp_new();
5377 gen_addr_reg_index(ctx, t0);
5378 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5379 gen_addr_add(ctx, t0, t0, 8);
5380 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5381 tcg_temp_free(t0);
5382 }
5383
5384 /* BookE specific instructions */
5385
5386 /* XXX: not implemented on 440 ? */
5387 static void gen_mfapidi(DisasContext *ctx)
5388 {
5389 /* XXX: TODO */
5390 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5391 }
5392
5393 /* XXX: not implemented on 440 ? */
5394 static void gen_tlbiva(DisasContext *ctx)
5395 {
5396 #if defined(CONFIG_USER_ONLY)
5397 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5398 #else
5399 TCGv t0;
5400 if (unlikely(!ctx->mem_idx)) {
5401 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5402 return;
5403 }
5404 t0 = tcg_temp_new();
5405 gen_addr_reg_index(ctx, t0);
5406 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5407 tcg_temp_free(t0);
5408 #endif
5409 }
5410
5411 /* All 405 MAC instructions are translated here */
5412 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5413 int ra, int rb, int rt, int Rc)
5414 {
5415 TCGv t0, t1;
5416
5417 t0 = tcg_temp_local_new();
5418 t1 = tcg_temp_local_new();
5419
5420 switch (opc3 & 0x0D) {
5421 case 0x05:
5422 /* macchw - macchw. - macchwo - macchwo. */
5423 /* macchws - macchws. - macchwso - macchwso. */
5424 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5425 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5426 /* mulchw - mulchw. */
5427 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5428 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5429 tcg_gen_ext16s_tl(t1, t1);
5430 break;
5431 case 0x04:
5432 /* macchwu - macchwu. - macchwuo - macchwuo. */
5433 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5434 /* mulchwu - mulchwu. */
5435 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5436 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5437 tcg_gen_ext16u_tl(t1, t1);
5438 break;
5439 case 0x01:
5440 /* machhw - machhw. - machhwo - machhwo. */
5441 /* machhws - machhws. - machhwso - machhwso. */
5442 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5443 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5444 /* mulhhw - mulhhw. */
5445 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5446 tcg_gen_ext16s_tl(t0, t0);
5447 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5448 tcg_gen_ext16s_tl(t1, t1);
5449 break;
5450 case 0x00:
5451 /* machhwu - machhwu. - machhwuo - machhwuo. */
5452 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5453 /* mulhhwu - mulhhwu. */
5454 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5455 tcg_gen_ext16u_tl(t0, t0);
5456 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5457 tcg_gen_ext16u_tl(t1, t1);
5458 break;
5459 case 0x0D:
5460 /* maclhw - maclhw. - maclhwo - maclhwo. */
5461 /* maclhws - maclhws. - maclhwso - maclhwso. */
5462 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5463 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5464 /* mullhw - mullhw. */
5465 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5466 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5467 break;
5468 case 0x0C:
5469 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5470 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5471 /* mullhwu - mullhwu. */
5472 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5473 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5474 break;
5475 }
5476 if (opc2 & 0x04) {
5477 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5478 tcg_gen_mul_tl(t1, t0, t1);
5479 if (opc2 & 0x02) {
5480 /* nmultiply-and-accumulate (0x0E) */
5481 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5482 } else {
5483 /* multiply-and-accumulate (0x0C) */
5484 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5485 }
5486
5487 if (opc3 & 0x12) {
5488 /* Check overflow and/or saturate */
5489 int l1 = gen_new_label();
5490
5491 if (opc3 & 0x10) {
5492 /* Start with XER OV disabled, the most likely case */
5493 tcg_gen_movi_tl(cpu_ov, 0);
5494 }
5495 if (opc3 & 0x01) {
5496 /* Signed */
5497 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5498 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5499 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5500 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5501 if (opc3 & 0x02) {
5502 /* Saturate */
5503 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5504 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5505 }
5506 } else {
5507 /* Unsigned */
5508 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5509 if (opc3 & 0x02) {
5510 /* Saturate */
5511 tcg_gen_movi_tl(t0, UINT32_MAX);
5512 }
5513 }
5514 if (opc3 & 0x10) {
5515 /* Check overflow */
5516 tcg_gen_movi_tl(cpu_ov, 1);
5517 tcg_gen_movi_tl(cpu_so, 1);
5518 }
5519 gen_set_label(l1);
5520 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5521 }
5522 } else {
5523 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5524 }
5525 tcg_temp_free(t0);
5526 tcg_temp_free(t1);
5527 if (unlikely(Rc) != 0) {
5528 /* Update Rc0 */
5529 gen_set_Rc0(ctx, cpu_gpr[rt]);
5530 }
5531 }
5532
5533 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5534 static void glue(gen_, name)(DisasContext *ctx) \
5535 { \
5536 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5537 rD(ctx->opcode), Rc(ctx->opcode)); \
5538 }
5539
5540 /* macchw - macchw. */
5541 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5542 /* macchwo - macchwo. */
5543 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5544 /* macchws - macchws. */
5545 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5546 /* macchwso - macchwso. */
5547 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5548 /* macchwsu - macchwsu. */
5549 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5550 /* macchwsuo - macchwsuo. */
5551 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5552 /* macchwu - macchwu. */
5553 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5554 /* macchwuo - macchwuo. */
5555 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5556 /* machhw - machhw. */
5557 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5558 /* machhwo - machhwo. */
5559 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5560 /* machhws - machhws. */
5561 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5562 /* machhwso - machhwso. */
5563 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5564 /* machhwsu - machhwsu. */
5565 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5566 /* machhwsuo - machhwsuo. */
5567 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5568 /* machhwu - machhwu. */
5569 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5570 /* machhwuo - machhwuo. */
5571 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5572 /* maclhw - maclhw. */
5573 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5574 /* maclhwo - maclhwo. */
5575 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5576 /* maclhws - maclhws. */
5577 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5578 /* maclhwso - maclhwso. */
5579 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5580 /* maclhwu - maclhwu. */
5581 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5582 /* maclhwuo - maclhwuo. */
5583 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5584 /* maclhwsu - maclhwsu. */
5585 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5586 /* maclhwsuo - maclhwsuo. */
5587 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5588 /* nmacchw - nmacchw. */
5589 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5590 /* nmacchwo - nmacchwo. */
5591 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5592 /* nmacchws - nmacchws. */
5593 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5594 /* nmacchwso - nmacchwso. */
5595 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5596 /* nmachhw - nmachhw. */
5597 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5598 /* nmachhwo - nmachhwo. */
5599 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5600 /* nmachhws - nmachhws. */
5601 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5602 /* nmachhwso - nmachhwso. */
5603 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5604 /* nmaclhw - nmaclhw. */
5605 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5606 /* nmaclhwo - nmaclhwo. */
5607 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5608 /* nmaclhws - nmaclhws. */
5609 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5610 /* nmaclhwso - nmaclhwso. */
5611 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5612
5613 /* mulchw - mulchw. */
5614 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5615 /* mulchwu - mulchwu. */
5616 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5617 /* mulhhw - mulhhw. */
5618 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5619 /* mulhhwu - mulhhwu. */
5620 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5621 /* mullhw - mullhw. */
5622 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5623 /* mullhwu - mullhwu. */
5624 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5625
5626 /* mfdcr */
5627 static void gen_mfdcr(DisasContext *ctx)
5628 {
5629 #if defined(CONFIG_USER_ONLY)
5630 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5631 #else
5632 TCGv dcrn;
5633 if (unlikely(!ctx->mem_idx)) {
5634 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5635 return;
5636 }
5637 /* NIP cannot be restored if the memory exception comes from an helper */
5638 gen_update_nip(ctx, ctx->nip - 4);
5639 dcrn = tcg_const_tl(SPR(ctx->opcode));
5640 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5641 tcg_temp_free(dcrn);
5642 #endif
5643 }
5644
5645 /* mtdcr */
5646 static void gen_mtdcr(DisasContext *ctx)
5647 {
5648 #if defined(CONFIG_USER_ONLY)
5649 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5650 #else
5651 TCGv dcrn;
5652 if (unlikely(!ctx->mem_idx)) {
5653 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5654 return;
5655 }
5656 /* NIP cannot be restored if the memory exception comes from an helper */
5657 gen_update_nip(ctx, ctx->nip - 4);
5658 dcrn = tcg_const_tl(SPR(ctx->opcode));
5659 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5660 tcg_temp_free(dcrn);
5661 #endif
5662 }
5663
5664 /* mfdcrx */
5665 /* XXX: not implemented on 440 ? */
5666 static void gen_mfdcrx(DisasContext *ctx)
5667 {
5668 #if defined(CONFIG_USER_ONLY)
5669 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5670 #else
5671 if (unlikely(!ctx->mem_idx)) {
5672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5673 return;
5674 }
5675 /* NIP cannot be restored if the memory exception comes from an helper */
5676 gen_update_nip(ctx, ctx->nip - 4);
5677 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5678 cpu_gpr[rA(ctx->opcode)]);
5679 /* Note: Rc update flag set leads to undefined state of Rc0 */
5680 #endif
5681 }
5682
5683 /* mtdcrx */
5684 /* XXX: not implemented on 440 ? */
5685 static void gen_mtdcrx(DisasContext *ctx)
5686 {
5687 #if defined(CONFIG_USER_ONLY)
5688 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5689 #else
5690 if (unlikely(!ctx->mem_idx)) {
5691 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5692 return;
5693 }
5694 /* NIP cannot be restored if the memory exception comes from an helper */
5695 gen_update_nip(ctx, ctx->nip - 4);
5696 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5697 cpu_gpr[rS(ctx->opcode)]);
5698 /* Note: Rc update flag set leads to undefined state of Rc0 */
5699 #endif
5700 }
5701
5702 /* mfdcrux (PPC 460) : user-mode access to DCR */
5703 static void gen_mfdcrux(DisasContext *ctx)
5704 {
5705 /* NIP cannot be restored if the memory exception comes from an helper */
5706 gen_update_nip(ctx, ctx->nip - 4);
5707 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5708 cpu_gpr[rA(ctx->opcode)]);
5709 /* Note: Rc update flag set leads to undefined state of Rc0 */
5710 }
5711
5712 /* mtdcrux (PPC 460) : user-mode access to DCR */
5713 static void gen_mtdcrux(DisasContext *ctx)
5714 {
5715 /* NIP cannot be restored if the memory exception comes from an helper */
5716 gen_update_nip(ctx, ctx->nip - 4);
5717 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5718 cpu_gpr[rS(ctx->opcode)]);
5719 /* Note: Rc update flag set leads to undefined state of Rc0 */
5720 }
5721
5722 /* dccci */
5723 static void gen_dccci(DisasContext *ctx)
5724 {
5725 #if defined(CONFIG_USER_ONLY)
5726 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5727 #else
5728 if (unlikely(!ctx->mem_idx)) {
5729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5730 return;
5731 }
5732 /* interpreted as no-op */
5733 #endif
5734 }
5735
5736 /* dcread */
5737 static void gen_dcread(DisasContext *ctx)
5738 {
5739 #if defined(CONFIG_USER_ONLY)
5740 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5741 #else
5742 TCGv EA, val;
5743 if (unlikely(!ctx->mem_idx)) {
5744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5745 return;
5746 }
5747 gen_set_access_type(ctx, ACCESS_CACHE);
5748 EA = tcg_temp_new();
5749 gen_addr_reg_index(ctx, EA);
5750 val = tcg_temp_new();
5751 gen_qemu_ld32u(ctx, val, EA);
5752 tcg_temp_free(val);
5753 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5754 tcg_temp_free(EA);
5755 #endif
5756 }
5757
5758 /* icbt */
5759 static void gen_icbt_40x(DisasContext *ctx)
5760 {
5761 /* interpreted as no-op */
5762 /* XXX: specification say this is treated as a load by the MMU
5763 * but does not generate any exception
5764 */
5765 }
5766
5767 /* iccci */
5768 static void gen_iccci(DisasContext *ctx)
5769 {
5770 #if defined(CONFIG_USER_ONLY)
5771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5772 #else
5773 if (unlikely(!ctx->mem_idx)) {
5774 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5775 return;
5776 }
5777 /* interpreted as no-op */
5778 #endif
5779 }
5780
5781 /* icread */
5782 static void gen_icread(DisasContext *ctx)
5783 {
5784 #if defined(CONFIG_USER_ONLY)
5785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5786 #else
5787 if (unlikely(!ctx->mem_idx)) {
5788 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5789 return;
5790 }
5791 /* interpreted as no-op */
5792 #endif
5793 }
5794
5795 /* rfci (mem_idx only) */
5796 static void gen_rfci_40x(DisasContext *ctx)
5797 {
5798 #if defined(CONFIG_USER_ONLY)
5799 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5800 #else
5801 if (unlikely(!ctx->mem_idx)) {
5802 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5803 return;
5804 }
5805 /* Restore CPU state */
5806 gen_helper_40x_rfci(cpu_env);
5807 gen_sync_exception(ctx);
5808 #endif
5809 }
5810
5811 static void gen_rfci(DisasContext *ctx)
5812 {
5813 #if defined(CONFIG_USER_ONLY)
5814 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5815 #else
5816 if (unlikely(!ctx->mem_idx)) {
5817 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5818 return;
5819 }
5820 /* Restore CPU state */
5821 gen_helper_rfci(cpu_env);
5822 gen_sync_exception(ctx);
5823 #endif
5824 }
5825
5826 /* BookE specific */
5827
5828 /* XXX: not implemented on 440 ? */
5829 static void gen_rfdi(DisasContext *ctx)
5830 {
5831 #if defined(CONFIG_USER_ONLY)
5832 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5833 #else
5834 if (unlikely(!ctx->mem_idx)) {
5835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5836 return;
5837 }
5838 /* Restore CPU state */
5839 gen_helper_rfdi(cpu_env);
5840 gen_sync_exception(ctx);
5841 #endif
5842 }
5843
5844 /* XXX: not implemented on 440 ? */
5845 static void gen_rfmci(DisasContext *ctx)
5846 {
5847 #if defined(CONFIG_USER_ONLY)
5848 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5849 #else
5850 if (unlikely(!ctx->mem_idx)) {
5851 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5852 return;
5853 }
5854 /* Restore CPU state */
5855 gen_helper_rfmci(cpu_env);
5856 gen_sync_exception(ctx);
5857 #endif
5858 }
5859
5860 /* TLB management - PowerPC 405 implementation */
5861
5862 /* tlbre */
5863 static void gen_tlbre_40x(DisasContext *ctx)
5864 {
5865 #if defined(CONFIG_USER_ONLY)
5866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5867 #else
5868 if (unlikely(!ctx->mem_idx)) {
5869 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5870 return;
5871 }
5872 switch (rB(ctx->opcode)) {
5873 case 0:
5874 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5875 cpu_gpr[rA(ctx->opcode)]);
5876 break;
5877 case 1:
5878 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5879 cpu_gpr[rA(ctx->opcode)]);
5880 break;
5881 default:
5882 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5883 break;
5884 }
5885 #endif
5886 }
5887
5888 /* tlbsx - tlbsx. */
5889 static void gen_tlbsx_40x(DisasContext *ctx)
5890 {
5891 #if defined(CONFIG_USER_ONLY)
5892 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5893 #else
5894 TCGv t0;
5895 if (unlikely(!ctx->mem_idx)) {
5896 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5897 return;
5898 }
5899 t0 = tcg_temp_new();
5900 gen_addr_reg_index(ctx, t0);
5901 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5902 tcg_temp_free(t0);
5903 if (Rc(ctx->opcode)) {
5904 int l1 = gen_new_label();
5905 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5906 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5907 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5908 gen_set_label(l1);
5909 }
5910 #endif
5911 }
5912
5913 /* tlbwe */
5914 static void gen_tlbwe_40x(DisasContext *ctx)
5915 {
5916 #if defined(CONFIG_USER_ONLY)
5917 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5918 #else
5919 if (unlikely(!ctx->mem_idx)) {
5920 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5921 return;
5922 }
5923 switch (rB(ctx->opcode)) {
5924 case 0:
5925 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5926 cpu_gpr[rS(ctx->opcode)]);
5927 break;
5928 case 1:
5929 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5930 cpu_gpr[rS(ctx->opcode)]);
5931 break;
5932 default:
5933 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5934 break;
5935 }
5936 #endif
5937 }
5938
5939 /* TLB management - PowerPC 440 implementation */
5940
5941 /* tlbre */
5942 static void gen_tlbre_440(DisasContext *ctx)
5943 {
5944 #if defined(CONFIG_USER_ONLY)
5945 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5946 #else
5947 if (unlikely(!ctx->mem_idx)) {
5948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5949 return;
5950 }
5951 switch (rB(ctx->opcode)) {
5952 case 0:
5953 case 1:
5954 case 2:
5955 {
5956 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5957 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5958 t0, cpu_gpr[rA(ctx->opcode)]);
5959 tcg_temp_free_i32(t0);
5960 }
5961 break;
5962 default:
5963 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5964 break;
5965 }
5966 #endif
5967 }
5968
5969 /* tlbsx - tlbsx. */
5970 static void gen_tlbsx_440(DisasContext *ctx)
5971 {
5972 #if defined(CONFIG_USER_ONLY)
5973 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5974 #else
5975 TCGv t0;
5976 if (unlikely(!ctx->mem_idx)) {
5977 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5978 return;
5979 }
5980 t0 = tcg_temp_new();
5981 gen_addr_reg_index(ctx, t0);
5982 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5983 tcg_temp_free(t0);
5984 if (Rc(ctx->opcode)) {
5985 int l1 = gen_new_label();
5986 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5987 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5988 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5989 gen_set_label(l1);
5990 }
5991 #endif
5992 }
5993
5994 /* tlbwe */
5995 static void gen_tlbwe_440(DisasContext *ctx)
5996 {
5997 #if defined(CONFIG_USER_ONLY)
5998 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5999 #else
6000 if (unlikely(!ctx->mem_idx)) {
6001 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6002 return;
6003 }
6004 switch (rB(ctx->opcode)) {
6005 case 0:
6006 case 1:
6007 case 2:
6008 {
6009 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6010 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6011 cpu_gpr[rS(ctx->opcode)]);
6012 tcg_temp_free_i32(t0);
6013 }
6014 break;
6015 default:
6016 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6017 break;
6018 }
6019 #endif
6020 }
6021
6022 /* TLB management - PowerPC BookE 2.06 implementation */
6023
6024 /* tlbre */
6025 static void gen_tlbre_booke206(DisasContext *ctx)
6026 {
6027 #if defined(CONFIG_USER_ONLY)
6028 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6029 #else
6030 if (unlikely(!ctx->mem_idx)) {
6031 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6032 return;
6033 }
6034
6035 gen_helper_booke206_tlbre(cpu_env);
6036 #endif
6037 }
6038
6039 /* tlbsx - tlbsx. */
6040 static void gen_tlbsx_booke206(DisasContext *ctx)
6041 {
6042 #if defined(CONFIG_USER_ONLY)
6043 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6044 #else
6045 TCGv t0;
6046 if (unlikely(!ctx->mem_idx)) {
6047 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6048 return;
6049 }
6050
6051 if (rA(ctx->opcode)) {
6052 t0 = tcg_temp_new();
6053 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6054 } else {
6055 t0 = tcg_const_tl(0);
6056 }
6057
6058 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6059 gen_helper_booke206_tlbsx(cpu_env, t0);
6060 #endif
6061 }
6062
6063 /* tlbwe */
6064 static void gen_tlbwe_booke206(DisasContext *ctx)
6065 {
6066 #if defined(CONFIG_USER_ONLY)
6067 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6068 #else
6069 if (unlikely(!ctx->mem_idx)) {
6070 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6071 return;
6072 }
6073 gen_update_nip(ctx, ctx->nip - 4);
6074 gen_helper_booke206_tlbwe(cpu_env);
6075 #endif
6076 }
6077
6078 static void gen_tlbivax_booke206(DisasContext *ctx)
6079 {
6080 #if defined(CONFIG_USER_ONLY)
6081 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6082 #else
6083 TCGv t0;
6084 if (unlikely(!ctx->mem_idx)) {
6085 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6086 return;
6087 }
6088
6089 t0 = tcg_temp_new();
6090 gen_addr_reg_index(ctx, t0);
6091
6092 gen_helper_booke206_tlbivax(cpu_env, t0);
6093 #endif
6094 }
6095
6096 static void gen_tlbilx_booke206(DisasContext *ctx)
6097 {
6098 #if defined(CONFIG_USER_ONLY)
6099 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6100 #else
6101 TCGv t0;
6102 if (unlikely(!ctx->mem_idx)) {
6103 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6104 return;
6105 }
6106
6107 t0 = tcg_temp_new();
6108 gen_addr_reg_index(ctx, t0);
6109
6110 switch((ctx->opcode >> 21) & 0x3) {
6111 case 0:
6112 gen_helper_booke206_tlbilx0(cpu_env, t0);
6113 break;
6114 case 1:
6115 gen_helper_booke206_tlbilx1(cpu_env, t0);
6116 break;
6117 case 3:
6118 gen_helper_booke206_tlbilx3(cpu_env, t0);
6119 break;
6120 default:
6121 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6122 break;
6123 }
6124
6125 tcg_temp_free(t0);
6126 #endif
6127 }
6128
6129
6130 /* wrtee */
6131 static void gen_wrtee(DisasContext *ctx)
6132 {
6133 #if defined(CONFIG_USER_ONLY)
6134 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6135 #else
6136 TCGv t0;
6137 if (unlikely(!ctx->mem_idx)) {
6138 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6139 return;
6140 }
6141 t0 = tcg_temp_new();
6142 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6143 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6144 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6145 tcg_temp_free(t0);
6146 /* Stop translation to have a chance to raise an exception
6147 * if we just set msr_ee to 1
6148 */
6149 gen_stop_exception(ctx);
6150 #endif
6151 }
6152
6153 /* wrteei */
6154 static void gen_wrteei(DisasContext *ctx)
6155 {
6156 #if defined(CONFIG_USER_ONLY)
6157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6158 #else
6159 if (unlikely(!ctx->mem_idx)) {
6160 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6161 return;
6162 }
6163 if (ctx->opcode & 0x00008000) {
6164 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6165 /* Stop translation to have a chance to raise an exception */
6166 gen_stop_exception(ctx);
6167 } else {
6168 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6169 }
6170 #endif
6171 }
6172
6173 /* PowerPC 440 specific instructions */
6174
6175 /* dlmzb */
6176 static void gen_dlmzb(DisasContext *ctx)
6177 {
6178 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6179 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6180 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6181 tcg_temp_free_i32(t0);
6182 }
6183
6184 /* mbar replaces eieio on 440 */
6185 static void gen_mbar(DisasContext *ctx)
6186 {
6187 /* interpreted as no-op */
6188 }
6189
6190 /* msync replaces sync on 440 */
6191 static void gen_msync_4xx(DisasContext *ctx)
6192 {
6193 /* interpreted as no-op */
6194 }
6195
6196 /* icbt */
6197 static void gen_icbt_440(DisasContext *ctx)
6198 {
6199 /* interpreted as no-op */
6200 /* XXX: specification say this is treated as a load by the MMU
6201 * but does not generate any exception
6202 */
6203 }
6204
6205 /* Embedded.Processor Control */
6206
6207 static void gen_msgclr(DisasContext *ctx)
6208 {
6209 #if defined(CONFIG_USER_ONLY)
6210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6211 #else
6212 if (unlikely(ctx->mem_idx == 0)) {
6213 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6214 return;
6215 }
6216
6217 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6218 #endif
6219 }
6220
6221 static void gen_msgsnd(DisasContext *ctx)
6222 {
6223 #if defined(CONFIG_USER_ONLY)
6224 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6225 #else
6226 if (unlikely(ctx->mem_idx == 0)) {
6227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6228 return;
6229 }
6230
6231 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6232 #endif
6233 }
6234
6235 /*** Altivec vector extension ***/
6236 /* Altivec registers moves */
6237
6238 static inline TCGv_ptr gen_avr_ptr(int reg)
6239 {
6240 TCGv_ptr r = tcg_temp_new_ptr();
6241 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6242 return r;
6243 }
6244
6245 #define GEN_VR_LDX(name, opc2, opc3) \
6246 static void glue(gen_, name)(DisasContext *ctx) \
6247 { \
6248 TCGv EA; \
6249 if (unlikely(!ctx->altivec_enabled)) { \
6250 gen_exception(ctx, POWERPC_EXCP_VPU); \
6251 return; \
6252 } \
6253 gen_set_access_type(ctx, ACCESS_INT); \
6254 EA = tcg_temp_new(); \
6255 gen_addr_reg_index(ctx, EA); \
6256 tcg_gen_andi_tl(EA, EA, ~0xf); \
6257 if (ctx->le_mode) { \
6258 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6259 tcg_gen_addi_tl(EA, EA, 8); \
6260 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6261 } else { \
6262 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6263 tcg_gen_addi_tl(EA, EA, 8); \
6264 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6265 } \
6266 tcg_temp_free(EA); \
6267 }
6268
6269 #define GEN_VR_STX(name, opc2, opc3) \
6270 static void gen_st##name(DisasContext *ctx) \
6271 { \
6272 TCGv EA; \
6273 if (unlikely(!ctx->altivec_enabled)) { \
6274 gen_exception(ctx, POWERPC_EXCP_VPU); \
6275 return; \
6276 } \
6277 gen_set_access_type(ctx, ACCESS_INT); \
6278 EA = tcg_temp_new(); \
6279 gen_addr_reg_index(ctx, EA); \
6280 tcg_gen_andi_tl(EA, EA, ~0xf); \
6281 if (ctx->le_mode) { \
6282 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6283 tcg_gen_addi_tl(EA, EA, 8); \
6284 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6285 } else { \
6286 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6287 tcg_gen_addi_tl(EA, EA, 8); \
6288 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6289 } \
6290 tcg_temp_free(EA); \
6291 }
6292
6293 #define GEN_VR_LVE(name, opc2, opc3) \
6294 static void gen_lve##name(DisasContext *ctx) \
6295 { \
6296 TCGv EA; \
6297 TCGv_ptr rs; \
6298 if (unlikely(!ctx->altivec_enabled)) { \
6299 gen_exception(ctx, POWERPC_EXCP_VPU); \
6300 return; \
6301 } \
6302 gen_set_access_type(ctx, ACCESS_INT); \
6303 EA = tcg_temp_new(); \
6304 gen_addr_reg_index(ctx, EA); \
6305 rs = gen_avr_ptr(rS(ctx->opcode)); \
6306 gen_helper_lve##name(cpu_env, rs, EA); \
6307 tcg_temp_free(EA); \
6308 tcg_temp_free_ptr(rs); \
6309 }
6310
6311 #define GEN_VR_STVE(name, opc2, opc3) \
6312 static void gen_stve##name(DisasContext *ctx) \
6313 { \
6314 TCGv EA; \
6315 TCGv_ptr rs; \
6316 if (unlikely(!ctx->altivec_enabled)) { \
6317 gen_exception(ctx, POWERPC_EXCP_VPU); \
6318 return; \
6319 } \
6320 gen_set_access_type(ctx, ACCESS_INT); \
6321 EA = tcg_temp_new(); \
6322 gen_addr_reg_index(ctx, EA); \
6323 rs = gen_avr_ptr(rS(ctx->opcode)); \
6324 gen_helper_stve##name(cpu_env, rs, EA); \
6325 tcg_temp_free(EA); \
6326 tcg_temp_free_ptr(rs); \
6327 }
6328
6329 GEN_VR_LDX(lvx, 0x07, 0x03);
6330 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6331 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6332
6333 GEN_VR_LVE(bx, 0x07, 0x00);
6334 GEN_VR_LVE(hx, 0x07, 0x01);
6335 GEN_VR_LVE(wx, 0x07, 0x02);
6336
6337 GEN_VR_STX(svx, 0x07, 0x07);
6338 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6339 GEN_VR_STX(svxl, 0x07, 0x0F);
6340
6341 GEN_VR_STVE(bx, 0x07, 0x04);
6342 GEN_VR_STVE(hx, 0x07, 0x05);
6343 GEN_VR_STVE(wx, 0x07, 0x06);
6344
6345 static void gen_lvsl(DisasContext *ctx)
6346 {
6347 TCGv_ptr rd;
6348 TCGv EA;
6349 if (unlikely(!ctx->altivec_enabled)) {
6350 gen_exception(ctx, POWERPC_EXCP_VPU);
6351 return;
6352 }
6353 EA = tcg_temp_new();
6354 gen_addr_reg_index(ctx, EA);
6355 rd = gen_avr_ptr(rD(ctx->opcode));
6356 gen_helper_lvsl(rd, EA);
6357 tcg_temp_free(EA);
6358 tcg_temp_free_ptr(rd);
6359 }
6360
6361 static void gen_lvsr(DisasContext *ctx)
6362 {
6363 TCGv_ptr rd;
6364 TCGv EA;
6365 if (unlikely(!ctx->altivec_enabled)) {
6366 gen_exception(ctx, POWERPC_EXCP_VPU);
6367 return;
6368 }
6369 EA = tcg_temp_new();
6370 gen_addr_reg_index(ctx, EA);
6371 rd = gen_avr_ptr(rD(ctx->opcode));
6372 gen_helper_lvsr(rd, EA);
6373 tcg_temp_free(EA);
6374 tcg_temp_free_ptr(rd);
6375 }
6376
6377 static void gen_mfvscr(DisasContext *ctx)
6378 {
6379 TCGv_i32 t;
6380 if (unlikely(!ctx->altivec_enabled)) {
6381 gen_exception(ctx, POWERPC_EXCP_VPU);
6382 return;
6383 }
6384 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6385 t = tcg_temp_new_i32();
6386 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6387 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6388 tcg_temp_free_i32(t);
6389 }
6390
6391 static void gen_mtvscr(DisasContext *ctx)
6392 {
6393 TCGv_ptr p;
6394 if (unlikely(!ctx->altivec_enabled)) {
6395 gen_exception(ctx, POWERPC_EXCP_VPU);
6396 return;
6397 }
6398 p = gen_avr_ptr(rD(ctx->opcode));
6399 gen_helper_mtvscr(cpu_env, p);
6400 tcg_temp_free_ptr(p);
6401 }
6402
6403 /* Logical operations */
6404 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6405 static void glue(gen_, name)(DisasContext *ctx) \
6406 { \
6407 if (unlikely(!ctx->altivec_enabled)) { \
6408 gen_exception(ctx, POWERPC_EXCP_VPU); \
6409 return; \
6410 } \
6411 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6412 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6413 }
6414
6415 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6416 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6417 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6418 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6419 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6420
6421 #define GEN_VXFORM(name, opc2, opc3) \
6422 static void glue(gen_, name)(DisasContext *ctx) \
6423 { \
6424 TCGv_ptr ra, rb, rd; \
6425 if (unlikely(!ctx->altivec_enabled)) { \
6426 gen_exception(ctx, POWERPC_EXCP_VPU); \
6427 return; \
6428 } \
6429 ra = gen_avr_ptr(rA(ctx->opcode)); \
6430 rb = gen_avr_ptr(rB(ctx->opcode)); \
6431 rd = gen_avr_ptr(rD(ctx->opcode)); \
6432 gen_helper_##name (rd, ra, rb); \
6433 tcg_temp_free_ptr(ra); \
6434 tcg_temp_free_ptr(rb); \
6435 tcg_temp_free_ptr(rd); \
6436 }
6437
6438 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6439 static void glue(gen_, name)(DisasContext *ctx) \
6440 { \
6441 TCGv_ptr ra, rb, rd; \
6442 if (unlikely(!ctx->altivec_enabled)) { \
6443 gen_exception(ctx, POWERPC_EXCP_VPU); \
6444 return; \
6445 } \
6446 ra = gen_avr_ptr(rA(ctx->opcode)); \
6447 rb = gen_avr_ptr(rB(ctx->opcode)); \
6448 rd = gen_avr_ptr(rD(ctx->opcode)); \
6449 gen_helper_##name(cpu_env, rd, ra, rb); \
6450 tcg_temp_free_ptr(ra); \
6451 tcg_temp_free_ptr(rb); \
6452 tcg_temp_free_ptr(rd); \
6453 }
6454
6455 GEN_VXFORM(vaddubm, 0, 0);
6456 GEN_VXFORM(vadduhm, 0, 1);
6457 GEN_VXFORM(vadduwm, 0, 2);
6458 GEN_VXFORM(vsububm, 0, 16);
6459 GEN_VXFORM(vsubuhm, 0, 17);
6460 GEN_VXFORM(vsubuwm, 0, 18);
6461 GEN_VXFORM(vmaxub, 1, 0);
6462 GEN_VXFORM(vmaxuh, 1, 1);
6463 GEN_VXFORM(vmaxuw, 1, 2);
6464 GEN_VXFORM(vmaxsb, 1, 4);
6465 GEN_VXFORM(vmaxsh, 1, 5);
6466 GEN_VXFORM(vmaxsw, 1, 6);
6467 GEN_VXFORM(vminub, 1, 8);
6468 GEN_VXFORM(vminuh, 1, 9);
6469 GEN_VXFORM(vminuw, 1, 10);
6470 GEN_VXFORM(vminsb, 1, 12);
6471 GEN_VXFORM(vminsh, 1, 13);
6472 GEN_VXFORM(vminsw, 1, 14);
6473 GEN_VXFORM(vavgub, 1, 16);
6474 GEN_VXFORM(vavguh, 1, 17);
6475 GEN_VXFORM(vavguw, 1, 18);
6476 GEN_VXFORM(vavgsb, 1, 20);
6477 GEN_VXFORM(vavgsh, 1, 21);
6478 GEN_VXFORM(vavgsw, 1, 22);
6479 GEN_VXFORM(vmrghb, 6, 0);
6480 GEN_VXFORM(vmrghh, 6, 1);
6481 GEN_VXFORM(vmrghw, 6, 2);
6482 GEN_VXFORM(vmrglb, 6, 4);
6483 GEN_VXFORM(vmrglh, 6, 5);
6484 GEN_VXFORM(vmrglw, 6, 6);
6485 GEN_VXFORM(vmuloub, 4, 0);
6486 GEN_VXFORM(vmulouh, 4, 1);
6487 GEN_VXFORM(vmulosb, 4, 4);
6488 GEN_VXFORM(vmulosh, 4, 5);
6489 GEN_VXFORM(vmuleub, 4, 8);
6490 GEN_VXFORM(vmuleuh, 4, 9);
6491 GEN_VXFORM(vmulesb, 4, 12);
6492 GEN_VXFORM(vmulesh, 4, 13);
6493 GEN_VXFORM(vslb, 2, 4);
6494 GEN_VXFORM(vslh, 2, 5);
6495 GEN_VXFORM(vslw, 2, 6);
6496 GEN_VXFORM(vsrb, 2, 8);
6497 GEN_VXFORM(vsrh, 2, 9);
6498 GEN_VXFORM(vsrw, 2, 10);
6499 GEN_VXFORM(vsrab, 2, 12);
6500 GEN_VXFORM(vsrah, 2, 13);
6501 GEN_VXFORM(vsraw, 2, 14);
6502 GEN_VXFORM(vslo, 6, 16);
6503 GEN_VXFORM(vsro, 6, 17);
6504 GEN_VXFORM(vaddcuw, 0, 6);
6505 GEN_VXFORM(vsubcuw, 0, 22);
6506 GEN_VXFORM_ENV(vaddubs, 0, 8);
6507 GEN_VXFORM_ENV(vadduhs, 0, 9);
6508 GEN_VXFORM_ENV(vadduws, 0, 10);
6509 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6510 GEN_VXFORM_ENV(vaddshs, 0, 13);
6511 GEN_VXFORM_ENV(vaddsws, 0, 14);
6512 GEN_VXFORM_ENV(vsububs, 0, 24);
6513 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6514 GEN_VXFORM_ENV(vsubuws, 0, 26);
6515 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6516 GEN_VXFORM_ENV(vsubshs, 0, 29);
6517 GEN_VXFORM_ENV(vsubsws, 0, 30);
6518 GEN_VXFORM(vrlb, 2, 0);
6519 GEN_VXFORM(vrlh, 2, 1);
6520 GEN_VXFORM(vrlw, 2, 2);
6521 GEN_VXFORM(vsl, 2, 7);
6522 GEN_VXFORM(vsr, 2, 11);
6523 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6524 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6525 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6526 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6527 GEN_VXFORM_ENV(vpkshus, 7, 4);
6528 GEN_VXFORM_ENV(vpkswus, 7, 5);
6529 GEN_VXFORM_ENV(vpkshss, 7, 6);
6530 GEN_VXFORM_ENV(vpkswss, 7, 7);
6531 GEN_VXFORM(vpkpx, 7, 12);
6532 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6533 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6534 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6535 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6536 GEN_VXFORM_ENV(vsumsws, 4, 30);
6537 GEN_VXFORM_ENV(vaddfp, 5, 0);
6538 GEN_VXFORM_ENV(vsubfp, 5, 1);
6539 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6540 GEN_VXFORM_ENV(vminfp, 5, 17);
6541
6542 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6543 static void glue(gen_, name)(DisasContext *ctx) \
6544 { \
6545 TCGv_ptr ra, rb, rd; \
6546 if (unlikely(!ctx->altivec_enabled)) { \
6547 gen_exception(ctx, POWERPC_EXCP_VPU); \
6548 return; \
6549 } \
6550 ra = gen_avr_ptr(rA(ctx->opcode)); \
6551 rb = gen_avr_ptr(rB(ctx->opcode)); \
6552 rd = gen_avr_ptr(rD(ctx->opcode)); \
6553 gen_helper_##opname(cpu_env, rd, ra, rb); \
6554 tcg_temp_free_ptr(ra); \
6555 tcg_temp_free_ptr(rb); \
6556 tcg_temp_free_ptr(rd); \
6557 }
6558
6559 #define GEN_VXRFORM(name, opc2, opc3) \
6560 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6561 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6562
6563 GEN_VXRFORM(vcmpequb, 3, 0)
6564 GEN_VXRFORM(vcmpequh, 3, 1)
6565 GEN_VXRFORM(vcmpequw, 3, 2)
6566 GEN_VXRFORM(vcmpgtsb, 3, 12)
6567 GEN_VXRFORM(vcmpgtsh, 3, 13)
6568 GEN_VXRFORM(vcmpgtsw, 3, 14)
6569 GEN_VXRFORM(vcmpgtub, 3, 8)
6570 GEN_VXRFORM(vcmpgtuh, 3, 9)
6571 GEN_VXRFORM(vcmpgtuw, 3, 10)
6572 GEN_VXRFORM(vcmpeqfp, 3, 3)
6573 GEN_VXRFORM(vcmpgefp, 3, 7)
6574 GEN_VXRFORM(vcmpgtfp, 3, 11)
6575 GEN_VXRFORM(vcmpbfp, 3, 15)
6576
6577 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6578 static void glue(gen_, name)(DisasContext *ctx) \
6579 { \
6580 TCGv_ptr rd; \
6581 TCGv_i32 simm; \
6582 if (unlikely(!ctx->altivec_enabled)) { \
6583 gen_exception(ctx, POWERPC_EXCP_VPU); \
6584 return; \
6585 } \
6586 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6587 rd = gen_avr_ptr(rD(ctx->opcode)); \
6588 gen_helper_##name (rd, simm); \
6589 tcg_temp_free_i32(simm); \
6590 tcg_temp_free_ptr(rd); \
6591 }
6592
6593 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6594 GEN_VXFORM_SIMM(vspltish, 6, 13);
6595 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6596
6597 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6598 static void glue(gen_, name)(DisasContext *ctx) \
6599 { \
6600 TCGv_ptr rb, rd; \
6601 if (unlikely(!ctx->altivec_enabled)) { \
6602 gen_exception(ctx, POWERPC_EXCP_VPU); \
6603 return; \
6604 } \
6605 rb = gen_avr_ptr(rB(ctx->opcode)); \
6606 rd = gen_avr_ptr(rD(ctx->opcode)); \
6607 gen_helper_##name (rd, rb); \
6608 tcg_temp_free_ptr(rb); \
6609 tcg_temp_free_ptr(rd); \
6610 }
6611
6612 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6613 static void glue(gen_, name)(DisasContext *ctx) \
6614 { \
6615 TCGv_ptr rb, rd; \
6616 \
6617 if (unlikely(!ctx->altivec_enabled)) { \
6618 gen_exception(ctx, POWERPC_EXCP_VPU); \
6619 return; \
6620 } \
6621 rb = gen_avr_ptr(rB(ctx->opcode)); \
6622 rd = gen_avr_ptr(rD(ctx->opcode)); \
6623 gen_helper_##name(cpu_env, rd, rb); \
6624 tcg_temp_free_ptr(rb); \
6625 tcg_temp_free_ptr(rd); \
6626 }
6627
6628 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6629 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6630 GEN_VXFORM_NOA(vupklsb, 7, 10);
6631 GEN_VXFORM_NOA(vupklsh, 7, 11);
6632 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6633 GEN_VXFORM_NOA(vupklpx, 7, 15);
6634 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6635 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6636 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6637 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6638 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6639 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6640 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6641 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6642
6643 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6644 static void glue(gen_, name)(DisasContext *ctx) \
6645 { \
6646 TCGv_ptr rd; \
6647 TCGv_i32 simm; \
6648 if (unlikely(!ctx->altivec_enabled)) { \
6649 gen_exception(ctx, POWERPC_EXCP_VPU); \
6650 return; \
6651 } \
6652 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6653 rd = gen_avr_ptr(rD(ctx->opcode)); \
6654 gen_helper_##name (rd, simm); \
6655 tcg_temp_free_i32(simm); \
6656 tcg_temp_free_ptr(rd); \
6657 }
6658
6659 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6660 static void glue(gen_, name)(DisasContext *ctx) \
6661 { \
6662 TCGv_ptr rb, rd; \
6663 TCGv_i32 uimm; \
6664 if (unlikely(!ctx->altivec_enabled)) { \
6665 gen_exception(ctx, POWERPC_EXCP_VPU); \
6666 return; \
6667 } \
6668 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6669 rb = gen_avr_ptr(rB(ctx->opcode)); \
6670 rd = gen_avr_ptr(rD(ctx->opcode)); \
6671 gen_helper_##name (rd, rb, uimm); \
6672 tcg_temp_free_i32(uimm); \
6673 tcg_temp_free_ptr(rb); \
6674 tcg_temp_free_ptr(rd); \
6675 }
6676
6677 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6678 static void glue(gen_, name)(DisasContext *ctx) \
6679 { \
6680 TCGv_ptr rb, rd; \
6681 TCGv_i32 uimm; \
6682 \
6683 if (unlikely(!ctx->altivec_enabled)) { \
6684 gen_exception(ctx, POWERPC_EXCP_VPU); \
6685 return; \
6686 } \
6687 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6688 rb = gen_avr_ptr(rB(ctx->opcode)); \
6689 rd = gen_avr_ptr(rD(ctx->opcode)); \
6690 gen_helper_##name(cpu_env, rd, rb, uimm); \
6691 tcg_temp_free_i32(uimm); \
6692 tcg_temp_free_ptr(rb); \
6693 tcg_temp_free_ptr(rd); \
6694 }
6695
6696 GEN_VXFORM_UIMM(vspltb, 6, 8);
6697 GEN_VXFORM_UIMM(vsplth, 6, 9);
6698 GEN_VXFORM_UIMM(vspltw, 6, 10);
6699 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6700 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6701 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6702 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6703
6704 static void gen_vsldoi(DisasContext *ctx)
6705 {
6706 TCGv_ptr ra, rb, rd;
6707 TCGv_i32 sh;
6708 if (unlikely(!ctx->altivec_enabled)) {
6709 gen_exception(ctx, POWERPC_EXCP_VPU);
6710 return;
6711 }
6712 ra = gen_avr_ptr(rA(ctx->opcode));
6713 rb = gen_avr_ptr(rB(ctx->opcode));
6714 rd = gen_avr_ptr(rD(ctx->opcode));
6715 sh = tcg_const_i32(VSH(ctx->opcode));
6716 gen_helper_vsldoi (rd, ra, rb, sh);
6717 tcg_temp_free_ptr(ra);
6718 tcg_temp_free_ptr(rb);
6719 tcg_temp_free_ptr(rd);
6720 tcg_temp_free_i32(sh);
6721 }
6722
6723 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6724 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6725 { \
6726 TCGv_ptr ra, rb, rc, rd; \
6727 if (unlikely(!ctx->altivec_enabled)) { \
6728 gen_exception(ctx, POWERPC_EXCP_VPU); \
6729 return; \
6730 } \
6731 ra = gen_avr_ptr(rA(ctx->opcode)); \
6732 rb = gen_avr_ptr(rB(ctx->opcode)); \
6733 rc = gen_avr_ptr(rC(ctx->opcode)); \
6734 rd = gen_avr_ptr(rD(ctx->opcode)); \
6735 if (Rc(ctx->opcode)) { \
6736 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6737 } else { \
6738 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6739 } \
6740 tcg_temp_free_ptr(ra); \
6741 tcg_temp_free_ptr(rb); \
6742 tcg_temp_free_ptr(rc); \
6743 tcg_temp_free_ptr(rd); \
6744 }
6745
6746 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6747
6748 static void gen_vmladduhm(DisasContext *ctx)
6749 {
6750 TCGv_ptr ra, rb, rc, rd;
6751 if (unlikely(!ctx->altivec_enabled)) {
6752 gen_exception(ctx, POWERPC_EXCP_VPU);
6753 return;
6754 }
6755 ra = gen_avr_ptr(rA(ctx->opcode));
6756 rb = gen_avr_ptr(rB(ctx->opcode));
6757 rc = gen_avr_ptr(rC(ctx->opcode));
6758 rd = gen_avr_ptr(rD(ctx->opcode));
6759 gen_helper_vmladduhm(rd, ra, rb, rc);
6760 tcg_temp_free_ptr(ra);
6761 tcg_temp_free_ptr(rb);
6762 tcg_temp_free_ptr(rc);
6763 tcg_temp_free_ptr(rd);
6764 }
6765
6766 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6767 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6768 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6769 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6770 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6771
6772 /*** SPE extension ***/
6773 /* Register moves */
6774
6775
6776 static inline void gen_evmra(DisasContext *ctx)
6777 {
6778
6779 if (unlikely(!ctx->spe_enabled)) {
6780 gen_exception(ctx, POWERPC_EXCP_SPEU);
6781 return;
6782 }
6783
6784 #if defined(TARGET_PPC64)
6785 /* rD := rA */
6786 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6787
6788 /* spe_acc := rA */
6789 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6790 cpu_env,
6791 offsetof(CPUPPCState, spe_acc));
6792 #else
6793 TCGv_i64 tmp = tcg_temp_new_i64();
6794
6795 /* tmp := rA_lo + rA_hi << 32 */
6796 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6797
6798 /* spe_acc := tmp */
6799 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6800 tcg_temp_free_i64(tmp);
6801
6802 /* rD := rA */
6803 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6804 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6805 #endif
6806 }
6807
6808 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6809 {
6810 #if defined(TARGET_PPC64)
6811 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6812 #else
6813 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6814 #endif
6815 }
6816
6817 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6818 {
6819 #if defined(TARGET_PPC64)
6820 tcg_gen_mov_i64(cpu_gpr[reg], t);
6821 #else
6822 TCGv_i64 tmp = tcg_temp_new_i64();
6823 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6824 tcg_gen_shri_i64(tmp, t, 32);
6825 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6826 tcg_temp_free_i64(tmp);
6827 #endif
6828 }
6829
6830 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6831 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6832 { \
6833 if (Rc(ctx->opcode)) \
6834 gen_##name1(ctx); \
6835 else \
6836 gen_##name0(ctx); \
6837 }
6838
6839 /* Handler for undefined SPE opcodes */
6840 static inline void gen_speundef(DisasContext *ctx)
6841 {
6842 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6843 }
6844
6845 /* SPE logic */
6846 #if defined(TARGET_PPC64)
6847 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6848 static inline void gen_##name(DisasContext *ctx) \
6849 { \
6850 if (unlikely(!ctx->spe_enabled)) { \
6851 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6852 return; \
6853 } \
6854 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6855 cpu_gpr[rB(ctx->opcode)]); \
6856 }
6857 #else
6858 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6859 static inline void gen_##name(DisasContext *ctx) \
6860 { \
6861 if (unlikely(!ctx->spe_enabled)) { \
6862 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6863 return; \
6864 } \
6865 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6866 cpu_gpr[rB(ctx->opcode)]); \
6867 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6868 cpu_gprh[rB(ctx->opcode)]); \
6869 }
6870 #endif
6871
6872 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6873 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6874 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6875 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6876 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6877 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6878 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6879 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6880
6881 /* SPE logic immediate */
6882 #if defined(TARGET_PPC64)
6883 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6884 static inline void gen_##name(DisasContext *ctx) \
6885 { \
6886 if (unlikely(!ctx->spe_enabled)) { \
6887 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6888 return; \
6889 } \
6890 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6891 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6892 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6893 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6894 tcg_opi(t0, t0, rB(ctx->opcode)); \
6895 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6896 tcg_gen_trunc_i64_i32(t1, t2); \
6897 tcg_temp_free_i64(t2); \
6898 tcg_opi(t1, t1, rB(ctx->opcode)); \
6899 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6900 tcg_temp_free_i32(t0); \
6901 tcg_temp_free_i32(t1); \
6902 }
6903 #else
6904 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6905 static inline void gen_##name(DisasContext *ctx) \
6906 { \
6907 if (unlikely(!ctx->spe_enabled)) { \
6908 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6909 return; \
6910 } \
6911 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6912 rB(ctx->opcode)); \
6913 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6914 rB(ctx->opcode)); \
6915 }
6916 #endif
6917 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6918 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6919 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6920 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6921
6922 /* SPE arithmetic */
6923 #if defined(TARGET_PPC64)
6924 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6925 static inline void gen_##name(DisasContext *ctx) \
6926 { \
6927 if (unlikely(!ctx->spe_enabled)) { \
6928 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6929 return; \
6930 } \
6931 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6932 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6933 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6934 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6935 tcg_op(t0, t0); \
6936 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6937 tcg_gen_trunc_i64_i32(t1, t2); \
6938 tcg_temp_free_i64(t2); \
6939 tcg_op(t1, t1); \
6940 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6941 tcg_temp_free_i32(t0); \
6942 tcg_temp_free_i32(t1); \
6943 }
6944 #else
6945 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6946 static inline void gen_##name(DisasContext *ctx) \
6947 { \
6948 if (unlikely(!ctx->spe_enabled)) { \
6949 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6950 return; \
6951 } \
6952 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6953 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6954 }
6955 #endif
6956
6957 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6958 {
6959 int l1 = gen_new_label();
6960 int l2 = gen_new_label();
6961
6962 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6963 tcg_gen_neg_i32(ret, arg1);
6964 tcg_gen_br(l2);
6965 gen_set_label(l1);
6966 tcg_gen_mov_i32(ret, arg1);
6967 gen_set_label(l2);
6968 }
6969 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6970 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6971 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6972 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6973 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6974 {
6975 tcg_gen_addi_i32(ret, arg1, 0x8000);
6976 tcg_gen_ext16u_i32(ret, ret);
6977 }
6978 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6979 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6980 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6981
6982 #if defined(TARGET_PPC64)
6983 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6984 static inline void gen_##name(DisasContext *ctx) \
6985 { \
6986 if (unlikely(!ctx->spe_enabled)) { \
6987 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6988 return; \
6989 } \
6990 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6991 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6992 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6993 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6994 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6995 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6996 tcg_op(t0, t0, t2); \
6997 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6998 tcg_gen_trunc_i64_i32(t1, t3); \
6999 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7000 tcg_gen_trunc_i64_i32(t2, t3); \
7001 tcg_temp_free_i64(t3); \
7002 tcg_op(t1, t1, t2); \
7003 tcg_temp_free_i32(t2); \
7004 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7005 tcg_temp_free_i32(t0); \
7006 tcg_temp_free_i32(t1); \
7007 }
7008 #else
7009 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7010 static inline void gen_##name(DisasContext *ctx) \
7011 { \
7012 if (unlikely(!ctx->spe_enabled)) { \
7013 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7014 return; \
7015 } \
7016 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7017 cpu_gpr[rB(ctx->opcode)]); \
7018 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7019 cpu_gprh[rB(ctx->opcode)]); \
7020 }
7021 #endif
7022
7023 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7024 {
7025 TCGv_i32 t0;
7026 int l1, l2;
7027
7028 l1 = gen_new_label();
7029 l2 = gen_new_label();
7030 t0 = tcg_temp_local_new_i32();
7031 /* No error here: 6 bits are used */
7032 tcg_gen_andi_i32(t0, arg2, 0x3F);
7033 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7034 tcg_gen_shr_i32(ret, arg1, t0);
7035 tcg_gen_br(l2);
7036 gen_set_label(l1);
7037 tcg_gen_movi_i32(ret, 0);
7038 gen_set_label(l2);
7039 tcg_temp_free_i32(t0);
7040 }
7041 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7042 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7043 {
7044 TCGv_i32 t0;
7045 int l1, l2;
7046
7047 l1 = gen_new_label();
7048 l2 = gen_new_label();
7049 t0 = tcg_temp_local_new_i32();
7050 /* No error here: 6 bits are used */
7051 tcg_gen_andi_i32(t0, arg2, 0x3F);
7052 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7053 tcg_gen_sar_i32(ret, arg1, t0);
7054 tcg_gen_br(l2);
7055 gen_set_label(l1);
7056 tcg_gen_movi_i32(ret, 0);
7057 gen_set_label(l2);
7058 tcg_temp_free_i32(t0);
7059 }
7060 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7061 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7062 {
7063 TCGv_i32 t0;
7064 int l1, l2;
7065
7066 l1 = gen_new_label();
7067 l2 = gen_new_label();
7068 t0 = tcg_temp_local_new_i32();
7069 /* No error here: 6 bits are used */
7070 tcg_gen_andi_i32(t0, arg2, 0x3F);
7071 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7072 tcg_gen_shl_i32(ret, arg1, t0);
7073 tcg_gen_br(l2);
7074 gen_set_label(l1);
7075 tcg_gen_movi_i32(ret, 0);
7076 gen_set_label(l2);
7077 tcg_temp_free_i32(t0);
7078 }
7079 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7080 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7081 {
7082 TCGv_i32 t0 = tcg_temp_new_i32();
7083 tcg_gen_andi_i32(t0, arg2, 0x1F);
7084 tcg_gen_rotl_i32(ret, arg1, t0);
7085 tcg_temp_free_i32(t0);
7086 }
7087 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7088 static inline void gen_evmergehi(DisasContext *ctx)
7089 {
7090 if (unlikely(!ctx->spe_enabled)) {
7091 gen_exception(ctx, POWERPC_EXCP_SPEU);
7092 return;
7093 }
7094 #if defined(TARGET_PPC64)
7095 TCGv t0 = tcg_temp_new();
7096 TCGv t1 = tcg_temp_new();
7097 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7098 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7099 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7100 tcg_temp_free(t0);
7101 tcg_temp_free(t1);
7102 #else
7103 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7104 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7105 #endif
7106 }
7107 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7108 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7109 {
7110 tcg_gen_sub_i32(ret, arg2, arg1);
7111 }
7112 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7113
7114 /* SPE arithmetic immediate */
7115 #if defined(TARGET_PPC64)
7116 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7117 static inline void gen_##name(DisasContext *ctx) \
7118 { \
7119 if (unlikely(!ctx->spe_enabled)) { \
7120 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7121 return; \
7122 } \
7123 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7124 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7125 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7126 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7127 tcg_op(t0, t0, rA(ctx->opcode)); \
7128 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7129 tcg_gen_trunc_i64_i32(t1, t2); \
7130 tcg_temp_free_i64(t2); \
7131 tcg_op(t1, t1, rA(ctx->opcode)); \
7132 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7133 tcg_temp_free_i32(t0); \
7134 tcg_temp_free_i32(t1); \
7135 }
7136 #else
7137 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7138 static inline void gen_##name(DisasContext *ctx) \
7139 { \
7140 if (unlikely(!ctx->spe_enabled)) { \
7141 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7142 return; \
7143 } \
7144 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7145 rA(ctx->opcode)); \
7146 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7147 rA(ctx->opcode)); \
7148 }
7149 #endif
7150 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7151 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7152
7153 /* SPE comparison */
7154 #if defined(TARGET_PPC64)
7155 #define GEN_SPEOP_COMP(name, tcg_cond) \
7156 static inline void gen_##name(DisasContext *ctx) \
7157 { \
7158 if (unlikely(!ctx->spe_enabled)) { \
7159 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7160 return; \
7161 } \
7162 int l1 = gen_new_label(); \
7163 int l2 = gen_new_label(); \
7164 int l3 = gen_new_label(); \
7165 int l4 = gen_new_label(); \
7166 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7167 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7168 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7169 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7170 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7171 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7172 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7173 tcg_gen_br(l2); \
7174 gen_set_label(l1); \
7175 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7176 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7177 gen_set_label(l2); \
7178 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7179 tcg_gen_trunc_i64_i32(t0, t2); \
7180 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7181 tcg_gen_trunc_i64_i32(t1, t2); \
7182 tcg_temp_free_i64(t2); \
7183 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7184 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7185 ~(CRF_CH | CRF_CH_AND_CL)); \
7186 tcg_gen_br(l4); \
7187 gen_set_label(l3); \
7188 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7189 CRF_CH | CRF_CH_OR_CL); \
7190 gen_set_label(l4); \
7191 tcg_temp_free_i32(t0); \
7192 tcg_temp_free_i32(t1); \
7193 }
7194 #else
7195 #define GEN_SPEOP_COMP(name, tcg_cond) \
7196 static inline void gen_##name(DisasContext *ctx) \
7197 { \
7198 if (unlikely(!ctx->spe_enabled)) { \
7199 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7200 return; \
7201 } \
7202 int l1 = gen_new_label(); \
7203 int l2 = gen_new_label(); \
7204 int l3 = gen_new_label(); \
7205 int l4 = gen_new_label(); \
7206 \
7207 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7208 cpu_gpr[rB(ctx->opcode)], l1); \
7209 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7210 tcg_gen_br(l2); \
7211 gen_set_label(l1); \
7212 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7213 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7214 gen_set_label(l2); \
7215 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7216 cpu_gprh[rB(ctx->opcode)], l3); \
7217 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7218 ~(CRF_CH | CRF_CH_AND_CL)); \
7219 tcg_gen_br(l4); \
7220 gen_set_label(l3); \
7221 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7222 CRF_CH | CRF_CH_OR_CL); \
7223 gen_set_label(l4); \
7224 }
7225 #endif
7226 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7227 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7228 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7229 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7230 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7231
7232 /* SPE misc */
7233 static inline void gen_brinc(DisasContext *ctx)
7234 {
7235 /* Note: brinc is usable even if SPE is disabled */
7236 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7237 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7238 }
7239 static inline void gen_evmergelo(DisasContext *ctx)
7240 {
7241 if (unlikely(!ctx->spe_enabled)) {
7242 gen_exception(ctx, POWERPC_EXCP_SPEU);
7243 return;
7244 }
7245 #if defined(TARGET_PPC64)
7246 TCGv t0 = tcg_temp_new();
7247 TCGv t1 = tcg_temp_new();
7248 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7249 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7250 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7251 tcg_temp_free(t0);
7252 tcg_temp_free(t1);
7253 #else
7254 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7255 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7256 #endif
7257 }
7258 static inline void gen_evmergehilo(DisasContext *ctx)
7259 {
7260 if (unlikely(!ctx->spe_enabled)) {
7261 gen_exception(ctx, POWERPC_EXCP_SPEU);
7262 return;
7263 }
7264 #if defined(TARGET_PPC64)
7265 TCGv t0 = tcg_temp_new();
7266 TCGv t1 = tcg_temp_new();
7267 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7268 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7269 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7270 tcg_temp_free(t0);
7271 tcg_temp_free(t1);
7272 #else
7273 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7274 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7275 #endif
7276 }
7277 static inline void gen_evmergelohi(DisasContext *ctx)
7278 {
7279 if (unlikely(!ctx->spe_enabled)) {
7280 gen_exception(ctx, POWERPC_EXCP_SPEU);
7281 return;
7282 }
7283 #if defined(TARGET_PPC64)
7284 TCGv t0 = tcg_temp_new();
7285 TCGv t1 = tcg_temp_new();
7286 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7287 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7288 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7289 tcg_temp_free(t0);
7290 tcg_temp_free(t1);
7291 #else
7292 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7293 TCGv_i32 tmp = tcg_temp_new_i32();
7294 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7295 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7296 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7297 tcg_temp_free_i32(tmp);
7298 } else {
7299 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7300 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7301 }
7302 #endif
7303 }
7304 static inline void gen_evsplati(DisasContext *ctx)
7305 {
7306 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7307
7308 #if defined(TARGET_PPC64)
7309 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7310 #else
7311 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7312 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7313 #endif
7314 }
7315 static inline void gen_evsplatfi(DisasContext *ctx)
7316 {
7317 uint64_t imm = rA(ctx->opcode) << 27;
7318
7319 #if defined(TARGET_PPC64)
7320 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7321 #else
7322 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7323 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7324 #endif
7325 }
7326
7327 static inline void gen_evsel(DisasContext *ctx)
7328 {
7329 int l1 = gen_new_label();
7330 int l2 = gen_new_label();
7331 int l3 = gen_new_label();
7332 int l4 = gen_new_label();
7333 TCGv_i32 t0 = tcg_temp_local_new_i32();
7334 #if defined(TARGET_PPC64)
7335 TCGv t1 = tcg_temp_local_new();
7336 TCGv t2 = tcg_temp_local_new();
7337 #endif
7338 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7339 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7340 #if defined(TARGET_PPC64)
7341 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7342 #else
7343 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7344 #endif
7345 tcg_gen_br(l2);
7346 gen_set_label(l1);
7347 #if defined(TARGET_PPC64)
7348 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7349 #else
7350 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7351 #endif
7352 gen_set_label(l2);
7353 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7354 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7355 #if defined(TARGET_PPC64)
7356 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7357 #else
7358 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7359 #endif
7360 tcg_gen_br(l4);
7361 gen_set_label(l3);
7362 #if defined(TARGET_PPC64)
7363 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7364 #else
7365 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7366 #endif
7367 gen_set_label(l4);
7368 tcg_temp_free_i32(t0);
7369 #if defined(TARGET_PPC64)
7370 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7371 tcg_temp_free(t1);
7372 tcg_temp_free(t2);
7373 #endif
7374 }
7375
7376 static void gen_evsel0(DisasContext *ctx)
7377 {
7378 gen_evsel(ctx);
7379 }
7380
7381 static void gen_evsel1(DisasContext *ctx)
7382 {
7383 gen_evsel(ctx);
7384 }
7385
7386 static void gen_evsel2(DisasContext *ctx)
7387 {
7388 gen_evsel(ctx);
7389 }
7390
7391 static void gen_evsel3(DisasContext *ctx)
7392 {
7393 gen_evsel(ctx);
7394 }
7395
7396 /* Multiply */
7397
7398 static inline void gen_evmwumi(DisasContext *ctx)
7399 {
7400 TCGv_i64 t0, t1;
7401
7402 if (unlikely(!ctx->spe_enabled)) {
7403 gen_exception(ctx, POWERPC_EXCP_SPEU);
7404 return;
7405 }
7406
7407 t0 = tcg_temp_new_i64();
7408 t1 = tcg_temp_new_i64();
7409
7410 /* t0 := rA; t1 := rB */
7411 #if defined(TARGET_PPC64)
7412 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7413 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7414 #else
7415 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7416 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7417 #endif
7418
7419 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7420
7421 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7422
7423 tcg_temp_free_i64(t0);
7424 tcg_temp_free_i64(t1);
7425 }
7426
7427 static inline void gen_evmwumia(DisasContext *ctx)
7428 {
7429 TCGv_i64 tmp;
7430
7431 if (unlikely(!ctx->spe_enabled)) {
7432 gen_exception(ctx, POWERPC_EXCP_SPEU);
7433 return;
7434 }
7435
7436 gen_evmwumi(ctx); /* rD := rA * rB */
7437
7438 tmp = tcg_temp_new_i64();
7439
7440 /* acc := rD */
7441 gen_load_gpr64(tmp, rD(ctx->opcode));
7442 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7443 tcg_temp_free_i64(tmp);
7444 }
7445
7446 static inline void gen_evmwumiaa(DisasContext *ctx)
7447 {
7448 TCGv_i64 acc;
7449 TCGv_i64 tmp;
7450
7451 if (unlikely(!ctx->spe_enabled)) {
7452 gen_exception(ctx, POWERPC_EXCP_SPEU);
7453 return;
7454 }
7455
7456 gen_evmwumi(ctx); /* rD := rA * rB */
7457
7458 acc = tcg_temp_new_i64();
7459 tmp = tcg_temp_new_i64();
7460
7461 /* tmp := rD */
7462 gen_load_gpr64(tmp, rD(ctx->opcode));
7463
7464 /* Load acc */
7465 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7466
7467 /* acc := tmp + acc */
7468 tcg_gen_add_i64(acc, acc, tmp);
7469
7470 /* Store acc */
7471 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7472
7473 /* rD := acc */
7474 gen_store_gpr64(rD(ctx->opcode), acc);
7475
7476 tcg_temp_free_i64(acc);
7477 tcg_temp_free_i64(tmp);
7478 }
7479
7480 static inline void gen_evmwsmi(DisasContext *ctx)
7481 {
7482 TCGv_i64 t0, t1;
7483
7484 if (unlikely(!ctx->spe_enabled)) {
7485 gen_exception(ctx, POWERPC_EXCP_SPEU);
7486 return;
7487 }
7488
7489 t0 = tcg_temp_new_i64();
7490 t1 = tcg_temp_new_i64();
7491
7492 /* t0 := rA; t1 := rB */
7493 #if defined(TARGET_PPC64)
7494 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7495 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7496 #else
7497 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7498 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7499 #endif
7500
7501 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7502
7503 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7504
7505 tcg_temp_free_i64(t0);
7506 tcg_temp_free_i64(t1);
7507 }
7508
7509 static inline void gen_evmwsmia(DisasContext *ctx)
7510 {
7511 TCGv_i64 tmp;
7512
7513 gen_evmwsmi(ctx); /* rD := rA * rB */
7514
7515 tmp = tcg_temp_new_i64();
7516
7517 /* acc := rD */
7518 gen_load_gpr64(tmp, rD(ctx->opcode));
7519 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7520
7521 tcg_temp_free_i64(tmp);
7522 }
7523
7524 static inline void gen_evmwsmiaa(DisasContext *ctx)
7525 {
7526 TCGv_i64 acc = tcg_temp_new_i64();
7527 TCGv_i64 tmp = tcg_temp_new_i64();
7528
7529 gen_evmwsmi(ctx); /* rD := rA * rB */
7530
7531 acc = tcg_temp_new_i64();
7532 tmp = tcg_temp_new_i64();
7533
7534 /* tmp := rD */
7535 gen_load_gpr64(tmp, rD(ctx->opcode));
7536
7537 /* Load acc */
7538 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7539
7540 /* acc := tmp + acc */
7541 tcg_gen_add_i64(acc, acc, tmp);
7542
7543 /* Store acc */
7544 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7545
7546 /* rD := acc */
7547 gen_store_gpr64(rD(ctx->opcode), acc);
7548
7549 tcg_temp_free_i64(acc);
7550 tcg_temp_free_i64(tmp);
7551 }
7552
7553 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7554 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7555 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7556 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7557 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7558 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7559 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7560 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7561 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7562 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7563 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7564 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7565 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7566 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7567 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7568 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7569 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7570 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7571 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7572 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7573 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7574 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7575 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7576 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7577 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7578 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7579 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7580 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7581 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7582
7583 /* SPE load and stores */
7584 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7585 {
7586 target_ulong uimm = rB(ctx->opcode);
7587
7588 if (rA(ctx->opcode) == 0) {
7589 tcg_gen_movi_tl(EA, uimm << sh);
7590 } else {
7591 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7592 #if defined(TARGET_PPC64)
7593 if (!ctx->sf_mode) {
7594 tcg_gen_ext32u_tl(EA, EA);
7595 }
7596 #endif
7597 }
7598 }
7599
7600 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7601 {
7602 #if defined(TARGET_PPC64)
7603 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7604 #else
7605 TCGv_i64 t0 = tcg_temp_new_i64();
7606 gen_qemu_ld64(ctx, t0, addr);
7607 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7608 tcg_gen_shri_i64(t0, t0, 32);
7609 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7610 tcg_temp_free_i64(t0);
7611 #endif
7612 }
7613
7614 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7615 {
7616 #if defined(TARGET_PPC64)
7617 TCGv t0 = tcg_temp_new();
7618 gen_qemu_ld32u(ctx, t0, addr);
7619 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7620 gen_addr_add(ctx, addr, addr, 4);
7621 gen_qemu_ld32u(ctx, t0, addr);
7622 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7623 tcg_temp_free(t0);
7624 #else
7625 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7626 gen_addr_add(ctx, addr, addr, 4);
7627 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7628 #endif
7629 }
7630
7631 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7632 {
7633 TCGv t0 = tcg_temp_new();
7634 #if defined(TARGET_PPC64)
7635 gen_qemu_ld16u(ctx, t0, addr);
7636 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7637 gen_addr_add(ctx, addr, addr, 2);
7638 gen_qemu_ld16u(ctx, t0, addr);
7639 tcg_gen_shli_tl(t0, t0, 32);
7640 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7641 gen_addr_add(ctx, addr, addr, 2);
7642 gen_qemu_ld16u(ctx, t0, addr);
7643 tcg_gen_shli_tl(t0, t0, 16);
7644 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7645 gen_addr_add(ctx, addr, addr, 2);
7646 gen_qemu_ld16u(ctx, t0, addr);
7647 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7648 #else
7649 gen_qemu_ld16u(ctx, t0, addr);
7650 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7651 gen_addr_add(ctx, addr, addr, 2);
7652 gen_qemu_ld16u(ctx, t0, addr);
7653 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7654 gen_addr_add(ctx, addr, addr, 2);
7655 gen_qemu_ld16u(ctx, t0, addr);
7656 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7657 gen_addr_add(ctx, addr, addr, 2);
7658 gen_qemu_ld16u(ctx, t0, addr);
7659 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7660 #endif
7661 tcg_temp_free(t0);
7662 }
7663
7664 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7665 {
7666 TCGv t0 = tcg_temp_new();
7667 gen_qemu_ld16u(ctx, t0, addr);
7668 #if defined(TARGET_PPC64)
7669 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7670 tcg_gen_shli_tl(t0, t0, 16);
7671 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7672 #else
7673 tcg_gen_shli_tl(t0, t0, 16);
7674 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7675 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7676 #endif
7677 tcg_temp_free(t0);
7678 }
7679
7680 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7681 {
7682 TCGv t0 = tcg_temp_new();
7683 gen_qemu_ld16u(ctx, t0, addr);
7684 #if defined(TARGET_PPC64)
7685 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7686 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7687 #else
7688 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7689 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7690 #endif
7691 tcg_temp_free(t0);
7692 }
7693
7694 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7695 {
7696 TCGv t0 = tcg_temp_new();
7697 gen_qemu_ld16s(ctx, t0, addr);
7698 #if defined(TARGET_PPC64)
7699 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7700 tcg_gen_ext32u_tl(t0, t0);
7701 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7702 #else
7703 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7704 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7705 #endif
7706 tcg_temp_free(t0);
7707 }
7708
7709 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7710 {
7711 TCGv t0 = tcg_temp_new();
7712 #if defined(TARGET_PPC64)
7713 gen_qemu_ld16u(ctx, t0, addr);
7714 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7715 gen_addr_add(ctx, addr, addr, 2);
7716 gen_qemu_ld16u(ctx, t0, addr);
7717 tcg_gen_shli_tl(t0, t0, 16);
7718 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7719 #else
7720 gen_qemu_ld16u(ctx, t0, addr);
7721 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7722 gen_addr_add(ctx, addr, addr, 2);
7723 gen_qemu_ld16u(ctx, t0, addr);
7724 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7725 #endif
7726 tcg_temp_free(t0);
7727 }
7728
7729 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7730 {
7731 #if defined(TARGET_PPC64)
7732 TCGv t0 = tcg_temp_new();
7733 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7734 gen_addr_add(ctx, addr, addr, 2);
7735 gen_qemu_ld16u(ctx, t0, addr);
7736 tcg_gen_shli_tl(t0, t0, 32);
7737 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7738 tcg_temp_free(t0);
7739 #else
7740 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7741 gen_addr_add(ctx, addr, addr, 2);
7742 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7743 #endif
7744 }
7745
7746 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7747 {
7748 #if defined(TARGET_PPC64)
7749 TCGv t0 = tcg_temp_new();
7750 gen_qemu_ld16s(ctx, t0, addr);
7751 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7752 gen_addr_add(ctx, addr, addr, 2);
7753 gen_qemu_ld16s(ctx, t0, addr);
7754 tcg_gen_shli_tl(t0, t0, 32);
7755 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7756 tcg_temp_free(t0);
7757 #else
7758 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7759 gen_addr_add(ctx, addr, addr, 2);
7760 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7761 #endif
7762 }
7763
7764 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7765 {
7766 TCGv t0 = tcg_temp_new();
7767 gen_qemu_ld32u(ctx, t0, addr);
7768 #if defined(TARGET_PPC64)
7769 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7770 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7771 #else
7772 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7773 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7774 #endif
7775 tcg_temp_free(t0);
7776 }
7777
7778 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7779 {
7780 TCGv t0 = tcg_temp_new();
7781 #if defined(TARGET_PPC64)
7782 gen_qemu_ld16u(ctx, t0, addr);
7783 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7784 tcg_gen_shli_tl(t0, t0, 32);
7785 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7786 gen_addr_add(ctx, addr, addr, 2);
7787 gen_qemu_ld16u(ctx, t0, addr);
7788 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7789 tcg_gen_shli_tl(t0, t0, 16);
7790 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7791 #else
7792 gen_qemu_ld16u(ctx, t0, addr);
7793 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7794 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7795 gen_addr_add(ctx, addr, addr, 2);
7796 gen_qemu_ld16u(ctx, t0, addr);
7797 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7798 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7799 #endif
7800 tcg_temp_free(t0);
7801 }
7802
7803 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7804 {
7805 #if defined(TARGET_PPC64)
7806 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7807 #else
7808 TCGv_i64 t0 = tcg_temp_new_i64();
7809 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7810 gen_qemu_st64(ctx, t0, addr);
7811 tcg_temp_free_i64(t0);
7812 #endif
7813 }
7814
7815 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7816 {
7817 #if defined(TARGET_PPC64)
7818 TCGv t0 = tcg_temp_new();
7819 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7820 gen_qemu_st32(ctx, t0, addr);
7821 tcg_temp_free(t0);
7822 #else
7823 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7824 #endif
7825 gen_addr_add(ctx, addr, addr, 4);
7826 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7827 }
7828
7829 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7830 {
7831 TCGv t0 = tcg_temp_new();
7832 #if defined(TARGET_PPC64)
7833 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7834 #else
7835 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7836 #endif
7837 gen_qemu_st16(ctx, t0, addr);
7838 gen_addr_add(ctx, addr, addr, 2);
7839 #if defined(TARGET_PPC64)
7840 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7841 gen_qemu_st16(ctx, t0, addr);
7842 #else
7843 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7844 #endif
7845 gen_addr_add(ctx, addr, addr, 2);
7846 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7847 gen_qemu_st16(ctx, t0, addr);
7848 tcg_temp_free(t0);
7849 gen_addr_add(ctx, addr, addr, 2);
7850 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7851 }
7852
7853 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7854 {
7855 TCGv t0 = tcg_temp_new();
7856 #if defined(TARGET_PPC64)
7857 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7858 #else
7859 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7860 #endif
7861 gen_qemu_st16(ctx, t0, addr);
7862 gen_addr_add(ctx, addr, addr, 2);
7863 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7864 gen_qemu_st16(ctx, t0, addr);
7865 tcg_temp_free(t0);
7866 }
7867
7868 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7869 {
7870 #if defined(TARGET_PPC64)
7871 TCGv t0 = tcg_temp_new();
7872 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7873 gen_qemu_st16(ctx, t0, addr);
7874 tcg_temp_free(t0);
7875 #else
7876 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7877 #endif
7878 gen_addr_add(ctx, addr, addr, 2);
7879 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7880 }
7881
7882 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7883 {
7884 #if defined(TARGET_PPC64)
7885 TCGv t0 = tcg_temp_new();
7886 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7887 gen_qemu_st32(ctx, t0, addr);
7888 tcg_temp_free(t0);
7889 #else
7890 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7891 #endif
7892 }
7893
7894 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7895 {
7896 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7897 }
7898
7899 #define GEN_SPEOP_LDST(name, opc2, sh) \
7900 static void glue(gen_, name)(DisasContext *ctx) \
7901 { \
7902 TCGv t0; \
7903 if (unlikely(!ctx->spe_enabled)) { \
7904 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7905 return; \
7906 } \
7907 gen_set_access_type(ctx, ACCESS_INT); \
7908 t0 = tcg_temp_new(); \
7909 if (Rc(ctx->opcode)) { \
7910 gen_addr_spe_imm_index(ctx, t0, sh); \
7911 } else { \
7912 gen_addr_reg_index(ctx, t0); \
7913 } \
7914 gen_op_##name(ctx, t0); \
7915 tcg_temp_free(t0); \
7916 }
7917
7918 GEN_SPEOP_LDST(evldd, 0x00, 3);
7919 GEN_SPEOP_LDST(evldw, 0x01, 3);
7920 GEN_SPEOP_LDST(evldh, 0x02, 3);
7921 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7922 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7923 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7924 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7925 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7926 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7927 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7928 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7929
7930 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7931 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7932 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7933 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7934 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7935 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7936 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7937
7938 /* Multiply and add - TODO */
7939 #if 0
7940 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7941 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7942 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7943 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7944 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7945 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7946 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7947 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7948 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7949 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7950 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7951 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7952
7953 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7954 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7955 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7956 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7957 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7958 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7959 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7960 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7961 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7962 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7963 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7964 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7965
7966 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7967 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7968 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7969 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7970 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7971
7972 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7973 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7974 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7975 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7976 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7977 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7978 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7979 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7980 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7981 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7982 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7983 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7984
7985 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7986 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7987 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7988 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7989
7990 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7991 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7992 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7993 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7994 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7995 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7996 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7997 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7998 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7999 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8000 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8001 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8002
8003 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8004 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8005 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8006 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8007 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8008 #endif
8009
8010 /*** SPE floating-point extension ***/
8011 #if defined(TARGET_PPC64)
8012 #define GEN_SPEFPUOP_CONV_32_32(name) \
8013 static inline void gen_##name(DisasContext *ctx) \
8014 { \
8015 TCGv_i32 t0; \
8016 TCGv t1; \
8017 t0 = tcg_temp_new_i32(); \
8018 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8019 gen_helper_##name(t0, cpu_env, t0); \
8020 t1 = tcg_temp_new(); \
8021 tcg_gen_extu_i32_tl(t1, t0); \
8022 tcg_temp_free_i32(t0); \
8023 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8024 0xFFFFFFFF00000000ULL); \
8025 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8026 tcg_temp_free(t1); \
8027 }
8028 #define GEN_SPEFPUOP_CONV_32_64(name) \
8029 static inline void gen_##name(DisasContext *ctx) \
8030 { \
8031 TCGv_i32 t0; \
8032 TCGv t1; \
8033 t0 = tcg_temp_new_i32(); \
8034 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8035 t1 = tcg_temp_new(); \
8036 tcg_gen_extu_i32_tl(t1, t0); \
8037 tcg_temp_free_i32(t0); \
8038 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8039 0xFFFFFFFF00000000ULL); \
8040 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8041 tcg_temp_free(t1); \
8042 }
8043 #define GEN_SPEFPUOP_CONV_64_32(name) \
8044 static inline void gen_##name(DisasContext *ctx) \
8045 { \
8046 TCGv_i32 t0 = tcg_temp_new_i32(); \
8047 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8048 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8049 tcg_temp_free_i32(t0); \
8050 }
8051 #define GEN_SPEFPUOP_CONV_64_64(name) \
8052 static inline void gen_##name(DisasContext *ctx) \
8053 { \
8054 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8055 cpu_gpr[rB(ctx->opcode)]); \
8056 }
8057 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8058 static inline void gen_##name(DisasContext *ctx) \
8059 { \
8060 TCGv_i32 t0, t1; \
8061 TCGv_i64 t2; \
8062 if (unlikely(!ctx->spe_enabled)) { \
8063 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8064 return; \
8065 } \
8066 t0 = tcg_temp_new_i32(); \
8067 t1 = tcg_temp_new_i32(); \
8068 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8069 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8070 gen_helper_##name(t0, cpu_env, t0, t1); \
8071 tcg_temp_free_i32(t1); \
8072 t2 = tcg_temp_new(); \
8073 tcg_gen_extu_i32_tl(t2, t0); \
8074 tcg_temp_free_i32(t0); \
8075 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8076 0xFFFFFFFF00000000ULL); \
8077 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8078 tcg_temp_free(t2); \
8079 }
8080 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8081 static inline void gen_##name(DisasContext *ctx) \
8082 { \
8083 if (unlikely(!ctx->spe_enabled)) { \
8084 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8085 return; \
8086 } \
8087 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8088 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8089 }
8090 #define GEN_SPEFPUOP_COMP_32(name) \
8091 static inline void gen_##name(DisasContext *ctx) \
8092 { \
8093 TCGv_i32 t0, t1; \
8094 if (unlikely(!ctx->spe_enabled)) { \
8095 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8096 return; \
8097 } \
8098 t0 = tcg_temp_new_i32(); \
8099 t1 = tcg_temp_new_i32(); \
8100 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8101 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8102 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8103 tcg_temp_free_i32(t0); \
8104 tcg_temp_free_i32(t1); \
8105 }
8106 #define GEN_SPEFPUOP_COMP_64(name) \
8107 static inline void gen_##name(DisasContext *ctx) \
8108 { \
8109 if (unlikely(!ctx->spe_enabled)) { \
8110 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8111 return; \
8112 } \
8113 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8114 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8115 }
8116 #else
8117 #define GEN_SPEFPUOP_CONV_32_32(name) \
8118 static inline void gen_##name(DisasContext *ctx) \
8119 { \
8120 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8121 cpu_gpr[rB(ctx->opcode)]); \
8122 }
8123 #define GEN_SPEFPUOP_CONV_32_64(name) \
8124 static inline void gen_##name(DisasContext *ctx) \
8125 { \
8126 TCGv_i64 t0 = tcg_temp_new_i64(); \
8127 gen_load_gpr64(t0, rB(ctx->opcode)); \
8128 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8129 tcg_temp_free_i64(t0); \
8130 }
8131 #define GEN_SPEFPUOP_CONV_64_32(name) \
8132 static inline void gen_##name(DisasContext *ctx) \
8133 { \
8134 TCGv_i64 t0 = tcg_temp_new_i64(); \
8135 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8136 gen_store_gpr64(rD(ctx->opcode), t0); \
8137 tcg_temp_free_i64(t0); \
8138 }
8139 #define GEN_SPEFPUOP_CONV_64_64(name) \
8140 static inline void gen_##name(DisasContext *ctx) \
8141 { \
8142 TCGv_i64 t0 = tcg_temp_new_i64(); \
8143 gen_load_gpr64(t0, rB(ctx->opcode)); \
8144 gen_helper_##name(t0, cpu_env, t0); \
8145 gen_store_gpr64(rD(ctx->opcode), t0); \
8146 tcg_temp_free_i64(t0); \
8147 }
8148 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8149 static inline void gen_##name(DisasContext *ctx) \
8150 { \
8151 if (unlikely(!ctx->spe_enabled)) { \
8152 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8153 return; \
8154 } \
8155 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8156 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8157 }
8158 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8159 static inline void gen_##name(DisasContext *ctx) \
8160 { \
8161 TCGv_i64 t0, t1; \
8162 if (unlikely(!ctx->spe_enabled)) { \
8163 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8164 return; \
8165 } \
8166 t0 = tcg_temp_new_i64(); \
8167 t1 = tcg_temp_new_i64(); \
8168 gen_load_gpr64(t0, rA(ctx->opcode)); \
8169 gen_load_gpr64(t1, rB(ctx->opcode)); \
8170 gen_helper_##name(t0, cpu_env, t0, t1); \
8171 gen_store_gpr64(rD(ctx->opcode), t0); \
8172 tcg_temp_free_i64(t0); \
8173 tcg_temp_free_i64(t1); \
8174 }
8175 #define GEN_SPEFPUOP_COMP_32(name) \
8176 static inline void gen_##name(DisasContext *ctx) \
8177 { \
8178 if (unlikely(!ctx->spe_enabled)) { \
8179 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8180 return; \
8181 } \
8182 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8183 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8184 }
8185 #define GEN_SPEFPUOP_COMP_64(name) \
8186 static inline void gen_##name(DisasContext *ctx) \
8187 { \
8188 TCGv_i64 t0, t1; \
8189 if (unlikely(!ctx->spe_enabled)) { \
8190 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8191 return; \
8192 } \
8193 t0 = tcg_temp_new_i64(); \
8194 t1 = tcg_temp_new_i64(); \
8195 gen_load_gpr64(t0, rA(ctx->opcode)); \
8196 gen_load_gpr64(t1, rB(ctx->opcode)); \
8197 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8198 tcg_temp_free_i64(t0); \
8199 tcg_temp_free_i64(t1); \
8200 }
8201 #endif
8202
8203 /* Single precision floating-point vectors operations */
8204 /* Arithmetic */
8205 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8206 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8207 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8208 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8209 static inline void gen_evfsabs(DisasContext *ctx)
8210 {
8211 if (unlikely(!ctx->spe_enabled)) {
8212 gen_exception(ctx, POWERPC_EXCP_SPEU);
8213 return;
8214 }
8215 #if defined(TARGET_PPC64)
8216 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8217 #else
8218 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8219 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8220 #endif
8221 }
8222 static inline void gen_evfsnabs(DisasContext *ctx)
8223 {
8224 if (unlikely(!ctx->spe_enabled)) {
8225 gen_exception(ctx, POWERPC_EXCP_SPEU);
8226 return;
8227 }
8228 #if defined(TARGET_PPC64)
8229 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8230 #else
8231 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8232 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8233 #endif
8234 }
8235 static inline void gen_evfsneg(DisasContext *ctx)
8236 {
8237 if (unlikely(!ctx->spe_enabled)) {
8238 gen_exception(ctx, POWERPC_EXCP_SPEU);
8239 return;
8240 }
8241 #if defined(TARGET_PPC64)
8242 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8243 #else
8244 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8245 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8246 #endif
8247 }
8248
8249 /* Conversion */
8250 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8251 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8252 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8253 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8254 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8255 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8256 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8257 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8258 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8259 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8260
8261 /* Comparison */
8262 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8263 GEN_SPEFPUOP_COMP_64(evfscmplt);
8264 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8265 GEN_SPEFPUOP_COMP_64(evfststgt);
8266 GEN_SPEFPUOP_COMP_64(evfststlt);
8267 GEN_SPEFPUOP_COMP_64(evfststeq);
8268
8269 /* Opcodes definitions */
8270 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8271 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8272 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8273 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8274 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8275 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8276 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8277 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8278 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8279 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8280 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8281 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8282 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8283 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8284
8285 /* Single precision floating-point operations */
8286 /* Arithmetic */
8287 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8288 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8289 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8290 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8291 static inline void gen_efsabs(DisasContext *ctx)
8292 {
8293 if (unlikely(!ctx->spe_enabled)) {
8294 gen_exception(ctx, POWERPC_EXCP_SPEU);
8295 return;
8296 }
8297 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8298 }
8299 static inline void gen_efsnabs(DisasContext *ctx)
8300 {
8301 if (unlikely(!ctx->spe_enabled)) {
8302 gen_exception(ctx, POWERPC_EXCP_SPEU);
8303 return;
8304 }
8305 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8306 }
8307 static inline void gen_efsneg(DisasContext *ctx)
8308 {
8309 if (unlikely(!ctx->spe_enabled)) {
8310 gen_exception(ctx, POWERPC_EXCP_SPEU);
8311 return;
8312 }
8313 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8314 }
8315
8316 /* Conversion */
8317 GEN_SPEFPUOP_CONV_32_32(efscfui);
8318 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8319 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8320 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8321 GEN_SPEFPUOP_CONV_32_32(efsctui);
8322 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8323 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8324 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8325 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8326 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8327 GEN_SPEFPUOP_CONV_32_64(efscfd);
8328
8329 /* Comparison */
8330 GEN_SPEFPUOP_COMP_32(efscmpgt);
8331 GEN_SPEFPUOP_COMP_32(efscmplt);
8332 GEN_SPEFPUOP_COMP_32(efscmpeq);
8333 GEN_SPEFPUOP_COMP_32(efststgt);
8334 GEN_SPEFPUOP_COMP_32(efststlt);
8335 GEN_SPEFPUOP_COMP_32(efststeq);
8336
8337 /* Opcodes definitions */
8338 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8339 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8340 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8341 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8342 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8343 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8344 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8345 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8346 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8347 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8348 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8349 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8350 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8351 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8352
8353 /* Double precision floating-point operations */
8354 /* Arithmetic */
8355 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8356 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8357 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8358 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8359 static inline void gen_efdabs(DisasContext *ctx)
8360 {
8361 if (unlikely(!ctx->spe_enabled)) {
8362 gen_exception(ctx, POWERPC_EXCP_SPEU);
8363 return;
8364 }
8365 #if defined(TARGET_PPC64)
8366 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8367 #else
8368 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8369 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8370 #endif
8371 }
8372 static inline void gen_efdnabs(DisasContext *ctx)
8373 {
8374 if (unlikely(!ctx->spe_enabled)) {
8375 gen_exception(ctx, POWERPC_EXCP_SPEU);
8376 return;
8377 }
8378 #if defined(TARGET_PPC64)
8379 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8380 #else
8381 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8382 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8383 #endif
8384 }
8385 static inline void gen_efdneg(DisasContext *ctx)
8386 {
8387 if (unlikely(!ctx->spe_enabled)) {
8388 gen_exception(ctx, POWERPC_EXCP_SPEU);
8389 return;
8390 }
8391 #if defined(TARGET_PPC64)
8392 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8393 #else
8394 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8395 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8396 #endif
8397 }
8398
8399 /* Conversion */
8400 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8401 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8402 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8403 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8404 GEN_SPEFPUOP_CONV_32_64(efdctui);
8405 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8406 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8407 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8408 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8409 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8410 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8411 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8412 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8413 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8414 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8415
8416 /* Comparison */
8417 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8418 GEN_SPEFPUOP_COMP_64(efdcmplt);
8419 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8420 GEN_SPEFPUOP_COMP_64(efdtstgt);
8421 GEN_SPEFPUOP_COMP_64(efdtstlt);
8422 GEN_SPEFPUOP_COMP_64(efdtsteq);
8423
8424 /* Opcodes definitions */
8425 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8426 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8427 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8428 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8429 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8430 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8431 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8432 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8433 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8434 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8435 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8436 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8437 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8438 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8439 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8440 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8441
8442 static opcode_t opcodes[] = {
8443 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8444 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8445 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8446 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8447 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8448 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8449 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8450 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8451 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8452 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8453 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8454 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8455 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8456 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8457 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8458 #if defined(TARGET_PPC64)
8459 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8460 #endif
8461 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8462 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8463 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8464 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8465 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8466 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8467 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8468 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8469 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8470 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8471 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8472 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8473 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8474 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8475 #if defined(TARGET_PPC64)
8476 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8477 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8478 #endif
8479 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8480 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8481 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8482 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8483 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8484 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8485 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8486 #if defined(TARGET_PPC64)
8487 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8488 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8489 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8490 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8491 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8492 #endif
8493 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8494 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8495 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8496 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8497 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8498 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8499 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8500 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8501 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8502 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8503 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8504 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8505 #if defined(TARGET_PPC64)
8506 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8507 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8508 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8509 #endif
8510 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8511 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8512 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8513 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8514 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8515 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8516 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8517 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8518 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8519 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8520 #if defined(TARGET_PPC64)
8521 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8522 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8523 #endif
8524 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8525 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8526 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8527 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8528 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8529 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8530 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8531 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8532 #if defined(TARGET_PPC64)
8533 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8534 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8535 #endif
8536 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8537 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8538 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8539 #if defined(TARGET_PPC64)
8540 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8541 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8542 #endif
8543 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8544 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8545 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8546 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8547 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8548 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8549 #if defined(TARGET_PPC64)
8550 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8551 #endif
8552 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8553 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8554 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8555 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8556 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8557 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8558 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8559 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8560 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8561 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8562 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8563 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8564 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8565 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8566 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8567 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8568 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8569 #if defined(TARGET_PPC64)
8570 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8571 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8572 PPC_SEGMENT_64B),
8573 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8574 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8575 PPC_SEGMENT_64B),
8576 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8577 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8578 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8579 #endif
8580 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8581 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8582 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8583 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8584 #if defined(TARGET_PPC64)
8585 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8586 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8587 #endif
8588 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8589 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8590 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8591 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8592 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8593 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8594 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8595 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8596 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8597 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8598 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8599 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8600 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8601 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8602 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8603 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8604 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8605 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8606 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8607 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8608 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8609 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8610 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8611 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8612 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8613 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8614 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8615 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8616 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8617 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8618 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8619 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8620 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8621 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8622 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8623 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8624 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8625 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8626 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8627 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8628 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8629 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8630 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8631 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8632 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8633 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8634 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8635 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8636 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8637 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8638 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8639 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8640 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8641 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8642 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8643 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8644 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8645 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8646 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8647 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8648 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8649 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8650 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8651 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8652 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8653 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8654 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8655 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8656 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8657 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8658 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8659 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8660 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8661 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8662 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8663 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8664 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8665 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8666 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8667 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8668 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8669 PPC_NONE, PPC2_BOOKE206),
8670 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8671 PPC_NONE, PPC2_BOOKE206),
8672 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8673 PPC_NONE, PPC2_BOOKE206),
8674 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8675 PPC_NONE, PPC2_BOOKE206),
8676 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8677 PPC_NONE, PPC2_BOOKE206),
8678 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8679 PPC_NONE, PPC2_PRCNTL),
8680 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8681 PPC_NONE, PPC2_PRCNTL),
8682 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8683 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8684 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8685 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8686 PPC_BOOKE, PPC2_BOOKE206),
8687 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8688 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8689 PPC_BOOKE, PPC2_BOOKE206),
8690 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8691 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8692 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8693 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8694 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8695 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8696 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8697 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8698 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8699 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8700
8701 #undef GEN_INT_ARITH_ADD
8702 #undef GEN_INT_ARITH_ADD_CONST
8703 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8704 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8705 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8706 add_ca, compute_ca, compute_ov) \
8707 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8708 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8709 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8710 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8711 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8712 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8713 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8714 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8715 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8716 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8717 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8718
8719 #undef GEN_INT_ARITH_DIVW
8720 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8721 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8722 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8723 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8724 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8725 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8726
8727 #if defined(TARGET_PPC64)
8728 #undef GEN_INT_ARITH_DIVD
8729 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8730 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8731 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8732 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8733 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8734 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8735
8736 #undef GEN_INT_ARITH_MUL_HELPER
8737 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8738 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8739 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8740 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8741 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8742 #endif
8743
8744 #undef GEN_INT_ARITH_SUBF
8745 #undef GEN_INT_ARITH_SUBF_CONST
8746 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8747 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8748 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8749 add_ca, compute_ca, compute_ov) \
8750 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8751 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8752 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8753 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8754 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8755 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8756 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8757 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8758 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8759 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8760 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8761
8762 #undef GEN_LOGICAL1
8763 #undef GEN_LOGICAL2
8764 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8765 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8766 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8767 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8768 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8769 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8770 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8771 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8772 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8773 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8774 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8775 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8776 #if defined(TARGET_PPC64)
8777 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8778 #endif
8779
8780 #if defined(TARGET_PPC64)
8781 #undef GEN_PPC64_R2
8782 #undef GEN_PPC64_R4
8783 #define GEN_PPC64_R2(name, opc1, opc2) \
8784 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8785 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8786 PPC_64B)
8787 #define GEN_PPC64_R4(name, opc1, opc2) \
8788 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8789 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8790 PPC_64B), \
8791 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8792 PPC_64B), \
8793 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8794 PPC_64B)
8795 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8796 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8797 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8798 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8799 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8800 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8801 #endif
8802
8803 #undef _GEN_FLOAT_ACB
8804 #undef GEN_FLOAT_ACB
8805 #undef _GEN_FLOAT_AB
8806 #undef GEN_FLOAT_AB
8807 #undef _GEN_FLOAT_AC
8808 #undef GEN_FLOAT_AC
8809 #undef GEN_FLOAT_B
8810 #undef GEN_FLOAT_BS
8811 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8812 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8813 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8814 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8815 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8816 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8817 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8818 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8819 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8820 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8821 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8822 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8823 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8824 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8825 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8826 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8827 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8828 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8829 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8830
8831 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8832 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8833 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8834 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8835 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8836 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8837 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8838 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8839 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8840 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8841 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8842 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8843 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8844 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8845 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8846 #if defined(TARGET_PPC64)
8847 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8848 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8849 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8850 #endif
8851 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8852 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8853 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8854 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8855 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8856 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8857 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8858
8859 #undef GEN_LD
8860 #undef GEN_LDU
8861 #undef GEN_LDUX
8862 #undef GEN_LDX_E
8863 #undef GEN_LDS
8864 #define GEN_LD(name, ldop, opc, type) \
8865 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8866 #define GEN_LDU(name, ldop, opc, type) \
8867 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8868 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8869 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8870 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8871 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8872 #define GEN_LDS(name, ldop, op, type) \
8873 GEN_LD(name, ldop, op | 0x20, type) \
8874 GEN_LDU(name, ldop, op | 0x21, type) \
8875 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8876 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8877
8878 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8879 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8880 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8881 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8882 #if defined(TARGET_PPC64)
8883 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8884 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8885 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8886 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8887 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8888 #endif
8889 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8890 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8891
8892 #undef GEN_ST
8893 #undef GEN_STU
8894 #undef GEN_STUX
8895 #undef GEN_STX_E
8896 #undef GEN_STS
8897 #define GEN_ST(name, stop, opc, type) \
8898 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8899 #define GEN_STU(name, stop, opc, type) \
8900 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8901 #define GEN_STUX(name, stop, opc2, opc3, type) \
8902 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8903 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8904 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8905 #define GEN_STS(name, stop, op, type) \
8906 GEN_ST(name, stop, op | 0x20, type) \
8907 GEN_STU(name, stop, op | 0x21, type) \
8908 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8909 GEN_STX(name, stop, 0x17, op | 0x00, type)
8910
8911 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8912 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8913 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8914 #if defined(TARGET_PPC64)
8915 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8916 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8917 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8918 #endif
8919 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8920 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8921
8922 #undef GEN_LDF
8923 #undef GEN_LDUF
8924 #undef GEN_LDUXF
8925 #undef GEN_LDXF
8926 #undef GEN_LDFS
8927 #define GEN_LDF(name, ldop, opc, type) \
8928 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8929 #define GEN_LDUF(name, ldop, opc, type) \
8930 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8931 #define GEN_LDUXF(name, ldop, opc, type) \
8932 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8933 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8934 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8935 #define GEN_LDFS(name, ldop, op, type) \
8936 GEN_LDF(name, ldop, op | 0x20, type) \
8937 GEN_LDUF(name, ldop, op | 0x21, type) \
8938 GEN_LDUXF(name, ldop, op | 0x01, type) \
8939 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8940
8941 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8942 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8943
8944 #undef GEN_STF
8945 #undef GEN_STUF
8946 #undef GEN_STUXF
8947 #undef GEN_STXF
8948 #undef GEN_STFS
8949 #define GEN_STF(name, stop, opc, type) \
8950 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8951 #define GEN_STUF(name, stop, opc, type) \
8952 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8953 #define GEN_STUXF(name, stop, opc, type) \
8954 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8955 #define GEN_STXF(name, stop, opc2, opc3, type) \
8956 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8957 #define GEN_STFS(name, stop, op, type) \
8958 GEN_STF(name, stop, op | 0x20, type) \
8959 GEN_STUF(name, stop, op | 0x21, type) \
8960 GEN_STUXF(name, stop, op | 0x01, type) \
8961 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8962
8963 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8964 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8965 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8966
8967 #undef GEN_CRLOGIC
8968 #define GEN_CRLOGIC(name, tcg_op, opc) \
8969 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8970 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8971 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8972 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8973 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8974 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8975 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8976 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8977 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8978
8979 #undef GEN_MAC_HANDLER
8980 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8981 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8982 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8983 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8984 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8985 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8986 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8987 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8988 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8989 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8990 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8991 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8992 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8993 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8994 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8995 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8996 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8997 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8998 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8999 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9000 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9001 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9002 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9003 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9004 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9005 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9006 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9007 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9008 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9009 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9010 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9011 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9012 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9013 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9014 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9015 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9016 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9017 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9018 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9019 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9020 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9021 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9022 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9023 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9024
9025 #undef GEN_VR_LDX
9026 #undef GEN_VR_STX
9027 #undef GEN_VR_LVE
9028 #undef GEN_VR_STVE
9029 #define GEN_VR_LDX(name, opc2, opc3) \
9030 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9031 #define GEN_VR_STX(name, opc2, opc3) \
9032 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9033 #define GEN_VR_LVE(name, opc2, opc3) \
9034 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9035 #define GEN_VR_STVE(name, opc2, opc3) \
9036 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9037 GEN_VR_LDX(lvx, 0x07, 0x03),
9038 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9039 GEN_VR_LVE(bx, 0x07, 0x00),
9040 GEN_VR_LVE(hx, 0x07, 0x01),
9041 GEN_VR_LVE(wx, 0x07, 0x02),
9042 GEN_VR_STX(svx, 0x07, 0x07),
9043 GEN_VR_STX(svxl, 0x07, 0x0F),
9044 GEN_VR_STVE(bx, 0x07, 0x04),
9045 GEN_VR_STVE(hx, 0x07, 0x05),
9046 GEN_VR_STVE(wx, 0x07, 0x06),
9047
9048 #undef GEN_VX_LOGICAL
9049 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9050 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9051 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9052 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9053 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9054 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9055 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9056
9057 #undef GEN_VXFORM
9058 #define GEN_VXFORM(name, opc2, opc3) \
9059 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9060 GEN_VXFORM(vaddubm, 0, 0),
9061 GEN_VXFORM(vadduhm, 0, 1),
9062 GEN_VXFORM(vadduwm, 0, 2),
9063 GEN_VXFORM(vsububm, 0, 16),
9064 GEN_VXFORM(vsubuhm, 0, 17),
9065 GEN_VXFORM(vsubuwm, 0, 18),
9066 GEN_VXFORM(vmaxub, 1, 0),
9067 GEN_VXFORM(vmaxuh, 1, 1),
9068 GEN_VXFORM(vmaxuw, 1, 2),
9069 GEN_VXFORM(vmaxsb, 1, 4),
9070 GEN_VXFORM(vmaxsh, 1, 5),
9071 GEN_VXFORM(vmaxsw, 1, 6),
9072 GEN_VXFORM(vminub, 1, 8),
9073 GEN_VXFORM(vminuh, 1, 9),
9074 GEN_VXFORM(vminuw, 1, 10),
9075 GEN_VXFORM(vminsb, 1, 12),
9076 GEN_VXFORM(vminsh, 1, 13),
9077 GEN_VXFORM(vminsw, 1, 14),
9078 GEN_VXFORM(vavgub, 1, 16),
9079 GEN_VXFORM(vavguh, 1, 17),
9080 GEN_VXFORM(vavguw, 1, 18),
9081 GEN_VXFORM(vavgsb, 1, 20),
9082 GEN_VXFORM(vavgsh, 1, 21),
9083 GEN_VXFORM(vavgsw, 1, 22),
9084 GEN_VXFORM(vmrghb, 6, 0),
9085 GEN_VXFORM(vmrghh, 6, 1),
9086 GEN_VXFORM(vmrghw, 6, 2),
9087 GEN_VXFORM(vmrglb, 6, 4),
9088 GEN_VXFORM(vmrglh, 6, 5),
9089 GEN_VXFORM(vmrglw, 6, 6),
9090 GEN_VXFORM(vmuloub, 4, 0),
9091 GEN_VXFORM(vmulouh, 4, 1),
9092 GEN_VXFORM(vmulosb, 4, 4),
9093 GEN_VXFORM(vmulosh, 4, 5),
9094 GEN_VXFORM(vmuleub, 4, 8),
9095 GEN_VXFORM(vmuleuh, 4, 9),
9096 GEN_VXFORM(vmulesb, 4, 12),
9097 GEN_VXFORM(vmulesh, 4, 13),
9098 GEN_VXFORM(vslb, 2, 4),
9099 GEN_VXFORM(vslh, 2, 5),
9100 GEN_VXFORM(vslw, 2, 6),
9101 GEN_VXFORM(vsrb, 2, 8),
9102 GEN_VXFORM(vsrh, 2, 9),
9103 GEN_VXFORM(vsrw, 2, 10),
9104 GEN_VXFORM(vsrab, 2, 12),
9105 GEN_VXFORM(vsrah, 2, 13),
9106 GEN_VXFORM(vsraw, 2, 14),
9107 GEN_VXFORM(vslo, 6, 16),
9108 GEN_VXFORM(vsro, 6, 17),
9109 GEN_VXFORM(vaddcuw, 0, 6),
9110 GEN_VXFORM(vsubcuw, 0, 22),
9111 GEN_VXFORM(vaddubs, 0, 8),
9112 GEN_VXFORM(vadduhs, 0, 9),
9113 GEN_VXFORM(vadduws, 0, 10),
9114 GEN_VXFORM(vaddsbs, 0, 12),
9115 GEN_VXFORM(vaddshs, 0, 13),
9116 GEN_VXFORM(vaddsws, 0, 14),
9117 GEN_VXFORM(vsububs, 0, 24),
9118 GEN_VXFORM(vsubuhs, 0, 25),
9119 GEN_VXFORM(vsubuws, 0, 26),
9120 GEN_VXFORM(vsubsbs, 0, 28),
9121 GEN_VXFORM(vsubshs, 0, 29),
9122 GEN_VXFORM(vsubsws, 0, 30),
9123 GEN_VXFORM(vrlb, 2, 0),
9124 GEN_VXFORM(vrlh, 2, 1),
9125 GEN_VXFORM(vrlw, 2, 2),
9126 GEN_VXFORM(vsl, 2, 7),
9127 GEN_VXFORM(vsr, 2, 11),
9128 GEN_VXFORM(vpkuhum, 7, 0),
9129 GEN_VXFORM(vpkuwum, 7, 1),
9130 GEN_VXFORM(vpkuhus, 7, 2),
9131 GEN_VXFORM(vpkuwus, 7, 3),
9132 GEN_VXFORM(vpkshus, 7, 4),
9133 GEN_VXFORM(vpkswus, 7, 5),
9134 GEN_VXFORM(vpkshss, 7, 6),
9135 GEN_VXFORM(vpkswss, 7, 7),
9136 GEN_VXFORM(vpkpx, 7, 12),
9137 GEN_VXFORM(vsum4ubs, 4, 24),
9138 GEN_VXFORM(vsum4sbs, 4, 28),
9139 GEN_VXFORM(vsum4shs, 4, 25),
9140 GEN_VXFORM(vsum2sws, 4, 26),
9141 GEN_VXFORM(vsumsws, 4, 30),
9142 GEN_VXFORM(vaddfp, 5, 0),
9143 GEN_VXFORM(vsubfp, 5, 1),
9144 GEN_VXFORM(vmaxfp, 5, 16),
9145 GEN_VXFORM(vminfp, 5, 17),
9146
9147 #undef GEN_VXRFORM1
9148 #undef GEN_VXRFORM
9149 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9150 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9151 #define GEN_VXRFORM(name, opc2, opc3) \
9152 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9153 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9154 GEN_VXRFORM(vcmpequb, 3, 0)
9155 GEN_VXRFORM(vcmpequh, 3, 1)
9156 GEN_VXRFORM(vcmpequw, 3, 2)
9157 GEN_VXRFORM(vcmpgtsb, 3, 12)
9158 GEN_VXRFORM(vcmpgtsh, 3, 13)
9159 GEN_VXRFORM(vcmpgtsw, 3, 14)
9160 GEN_VXRFORM(vcmpgtub, 3, 8)
9161 GEN_VXRFORM(vcmpgtuh, 3, 9)
9162 GEN_VXRFORM(vcmpgtuw, 3, 10)
9163 GEN_VXRFORM(vcmpeqfp, 3, 3)
9164 GEN_VXRFORM(vcmpgefp, 3, 7)
9165 GEN_VXRFORM(vcmpgtfp, 3, 11)
9166 GEN_VXRFORM(vcmpbfp, 3, 15)
9167
9168 #undef GEN_VXFORM_SIMM
9169 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9170 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9171 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9172 GEN_VXFORM_SIMM(vspltish, 6, 13),
9173 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9174
9175 #undef GEN_VXFORM_NOA
9176 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9177 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9178 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9179 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9180 GEN_VXFORM_NOA(vupklsb, 7, 10),
9181 GEN_VXFORM_NOA(vupklsh, 7, 11),
9182 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9183 GEN_VXFORM_NOA(vupklpx, 7, 15),
9184 GEN_VXFORM_NOA(vrefp, 5, 4),
9185 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9186 GEN_VXFORM_NOA(vexptefp, 5, 6),
9187 GEN_VXFORM_NOA(vlogefp, 5, 7),
9188 GEN_VXFORM_NOA(vrfim, 5, 8),
9189 GEN_VXFORM_NOA(vrfin, 5, 9),
9190 GEN_VXFORM_NOA(vrfip, 5, 10),
9191 GEN_VXFORM_NOA(vrfiz, 5, 11),
9192
9193 #undef GEN_VXFORM_UIMM
9194 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9195 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9196 GEN_VXFORM_UIMM(vspltb, 6, 8),
9197 GEN_VXFORM_UIMM(vsplth, 6, 9),
9198 GEN_VXFORM_UIMM(vspltw, 6, 10),
9199 GEN_VXFORM_UIMM(vcfux, 5, 12),
9200 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9201 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9202 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9203
9204 #undef GEN_VAFORM_PAIRED
9205 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9206 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9207 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9208 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9209 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9210 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9211 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9212 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9213
9214 #undef GEN_SPE
9215 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9216 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9217 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9218 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9219 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9220 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9221 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9222 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9223 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9224 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9225 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9226 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9227 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9228 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9229 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9230 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9231 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9232 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9233 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9234 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9235 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9236 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9237 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9238 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9239 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9240 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9241 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9242 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9243 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9244 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9245 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9246
9247 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9248 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9249 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9250 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9251 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9252 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9253 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9254 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9255 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9256 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9257 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9258 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9259 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9260 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9261
9262 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9263 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9264 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9265 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9266 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9267 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9268 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9269 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9270 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9271 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9272 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9273 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9274 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9275 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9276
9277 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9278 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9279 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9280 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9281 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9282 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9283 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9284 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9285 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9286 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9287 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9288 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9289 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9290 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9291 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9292 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9293
9294 #undef GEN_SPEOP_LDST
9295 #define GEN_SPEOP_LDST(name, opc2, sh) \
9296 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9297 GEN_SPEOP_LDST(evldd, 0x00, 3),
9298 GEN_SPEOP_LDST(evldw, 0x01, 3),
9299 GEN_SPEOP_LDST(evldh, 0x02, 3),
9300 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9301 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9302 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9303 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9304 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9305 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9306 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9307 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9308
9309 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9310 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9311 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9312 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9313 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9314 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9315 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9316 };
9317
9318 #include "helper_regs.h"
9319 #include "translate_init.c"
9320
9321 /*****************************************************************************/
9322 /* Misc PowerPC helpers */
9323 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9324 int flags)
9325 {
9326 #define RGPL 4
9327 #define RFPL 4
9328
9329 int i;
9330
9331 cpu_synchronize_state(env);
9332
9333 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9334 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9335 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9336 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9337 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9338 env->hflags, env->mmu_idx);
9339 #if !defined(NO_TIMER_DUMP)
9340 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9341 #if !defined(CONFIG_USER_ONLY)
9342 " DECR %08" PRIu32
9343 #endif
9344 "\n",
9345 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9346 #if !defined(CONFIG_USER_ONLY)
9347 , cpu_ppc_load_decr(env)
9348 #endif
9349 );
9350 #endif
9351 for (i = 0; i < 32; i++) {
9352 if ((i & (RGPL - 1)) == 0)
9353 cpu_fprintf(f, "GPR%02d", i);
9354 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9355 if ((i & (RGPL - 1)) == (RGPL - 1))
9356 cpu_fprintf(f, "\n");
9357 }
9358 cpu_fprintf(f, "CR ");
9359 for (i = 0; i < 8; i++)
9360 cpu_fprintf(f, "%01x", env->crf[i]);
9361 cpu_fprintf(f, " [");
9362 for (i = 0; i < 8; i++) {
9363 char a = '-';
9364 if (env->crf[i] & 0x08)
9365 a = 'L';
9366 else if (env->crf[i] & 0x04)
9367 a = 'G';
9368 else if (env->crf[i] & 0x02)
9369 a = 'E';
9370 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9371 }
9372 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9373 env->reserve_addr);
9374 for (i = 0; i < 32; i++) {
9375 if ((i & (RFPL - 1)) == 0)
9376 cpu_fprintf(f, "FPR%02d", i);
9377 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9378 if ((i & (RFPL - 1)) == (RFPL - 1))
9379 cpu_fprintf(f, "\n");
9380 }
9381 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9382 #if !defined(CONFIG_USER_ONLY)
9383 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9384 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9385 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9386 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9387
9388 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9389 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9390 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9391 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9392
9393 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9394 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9395 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9396 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9397
9398 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9399 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9400 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9401 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9402 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9403
9404 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9405 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9406 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9407 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9408
9409 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9410 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9411 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9412 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9413
9414 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9415 " EPR " TARGET_FMT_lx "\n",
9416 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9417 env->spr[SPR_BOOKE_EPR]);
9418
9419 /* FSL-specific */
9420 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9421 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9422 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9423 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9424
9425 /*
9426 * IVORs are left out as they are large and do not change often --
9427 * they can be read with "p $ivor0", "p $ivor1", etc.
9428 */
9429 }
9430
9431 #if defined(TARGET_PPC64)
9432 if (env->flags & POWERPC_FLAG_CFAR) {
9433 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9434 }
9435 #endif
9436
9437 switch (env->mmu_model) {
9438 case POWERPC_MMU_32B:
9439 case POWERPC_MMU_601:
9440 case POWERPC_MMU_SOFT_6xx:
9441 case POWERPC_MMU_SOFT_74xx:
9442 #if defined(TARGET_PPC64)
9443 case POWERPC_MMU_620:
9444 case POWERPC_MMU_64B:
9445 #endif
9446 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9447 break;
9448 case POWERPC_MMU_BOOKE206:
9449 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9450 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9451 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9452 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9453
9454 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9455 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9456 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9457 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9458
9459 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9460 " TLB1CFG " TARGET_FMT_lx "\n",
9461 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9462 env->spr[SPR_BOOKE_TLB1CFG]);
9463 break;
9464 default:
9465 break;
9466 }
9467 #endif
9468
9469 #undef RGPL
9470 #undef RFPL
9471 }
9472
9473 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9474 int flags)
9475 {
9476 #if defined(DO_PPC_STATISTICS)
9477 opc_handler_t **t1, **t2, **t3, *handler;
9478 int op1, op2, op3;
9479
9480 t1 = env->opcodes;
9481 for (op1 = 0; op1 < 64; op1++) {
9482 handler = t1[op1];
9483 if (is_indirect_opcode(handler)) {
9484 t2 = ind_table(handler);
9485 for (op2 = 0; op2 < 32; op2++) {
9486 handler = t2[op2];
9487 if (is_indirect_opcode(handler)) {
9488 t3 = ind_table(handler);
9489 for (op3 = 0; op3 < 32; op3++) {
9490 handler = t3[op3];
9491 if (handler->count == 0)
9492 continue;
9493 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9494 "%016" PRIx64 " %" PRId64 "\n",
9495 op1, op2, op3, op1, (op3 << 5) | op2,
9496 handler->oname,
9497 handler->count, handler->count);
9498 }
9499 } else {
9500 if (handler->count == 0)
9501 continue;
9502 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9503 "%016" PRIx64 " %" PRId64 "\n",
9504 op1, op2, op1, op2, handler->oname,
9505 handler->count, handler->count);
9506 }
9507 }
9508 } else {
9509 if (handler->count == 0)
9510 continue;
9511 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9512 " %" PRId64 "\n",
9513 op1, op1, handler->oname,
9514 handler->count, handler->count);
9515 }
9516 }
9517 #endif
9518 }
9519
9520 /*****************************************************************************/
9521 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9522 TranslationBlock *tb,
9523 int search_pc)
9524 {
9525 DisasContext ctx, *ctxp = &ctx;
9526 opc_handler_t **table, *handler;
9527 target_ulong pc_start;
9528 uint16_t *gen_opc_end;
9529 CPUBreakpoint *bp;
9530 int j, lj = -1;
9531 int num_insns;
9532 int max_insns;
9533
9534 pc_start = tb->pc;
9535 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9536 ctx.nip = pc_start;
9537 ctx.tb = tb;
9538 ctx.exception = POWERPC_EXCP_NONE;
9539 ctx.spr_cb = env->spr_cb;
9540 ctx.mem_idx = env->mmu_idx;
9541 ctx.access_type = -1;
9542 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9543 #if defined(TARGET_PPC64)
9544 ctx.sf_mode = msr_is_64bit(env, env->msr);
9545 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9546 #endif
9547 ctx.fpu_enabled = msr_fp;
9548 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9549 ctx.spe_enabled = msr_spe;
9550 else
9551 ctx.spe_enabled = 0;
9552 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9553 ctx.altivec_enabled = msr_vr;
9554 else
9555 ctx.altivec_enabled = 0;
9556 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9557 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9558 else
9559 ctx.singlestep_enabled = 0;
9560 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9561 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9562 if (unlikely(env->singlestep_enabled))
9563 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9564 #if defined (DO_SINGLE_STEP) && 0
9565 /* Single step trace mode */
9566 msr_se = 1;
9567 #endif
9568 num_insns = 0;
9569 max_insns = tb->cflags & CF_COUNT_MASK;
9570 if (max_insns == 0)
9571 max_insns = CF_COUNT_MASK;
9572
9573 gen_icount_start();
9574 /* Set env in case of segfault during code fetch */
9575 while (ctx.exception == POWERPC_EXCP_NONE
9576 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9577 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9578 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9579 if (bp->pc == ctx.nip) {
9580 gen_debug_exception(ctxp);
9581 break;
9582 }
9583 }
9584 }
9585 if (unlikely(search_pc)) {
9586 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9587 if (lj < j) {
9588 lj++;
9589 while (lj < j)
9590 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9591 }
9592 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9593 tcg_ctx.gen_opc_instr_start[lj] = 1;
9594 tcg_ctx.gen_opc_icount[lj] = num_insns;
9595 }
9596 LOG_DISAS("----------------\n");
9597 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9598 ctx.nip, ctx.mem_idx, (int)msr_ir);
9599 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9600 gen_io_start();
9601 if (unlikely(ctx.le_mode)) {
9602 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9603 } else {
9604 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9605 }
9606 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9607 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9608 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9609 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9610 tcg_gen_debug_insn_start(ctx.nip);
9611 }
9612 ctx.nip += 4;
9613 table = env->opcodes;
9614 num_insns++;
9615 handler = table[opc1(ctx.opcode)];
9616 if (is_indirect_opcode(handler)) {
9617 table = ind_table(handler);
9618 handler = table[opc2(ctx.opcode)];
9619 if (is_indirect_opcode(handler)) {
9620 table = ind_table(handler);
9621 handler = table[opc3(ctx.opcode)];
9622 }
9623 }
9624 /* Is opcode *REALLY* valid ? */
9625 if (unlikely(handler->handler == &gen_invalid)) {
9626 if (qemu_log_enabled()) {
9627 qemu_log("invalid/unsupported opcode: "
9628 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9629 opc1(ctx.opcode), opc2(ctx.opcode),
9630 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9631 }
9632 } else {
9633 uint32_t inval;
9634
9635 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9636 inval = handler->inval2;
9637 } else {
9638 inval = handler->inval1;
9639 }
9640
9641 if (unlikely((ctx.opcode & inval) != 0)) {
9642 if (qemu_log_enabled()) {
9643 qemu_log("invalid bits: %08x for opcode: "
9644 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9645 ctx.opcode & inval, opc1(ctx.opcode),
9646 opc2(ctx.opcode), opc3(ctx.opcode),
9647 ctx.opcode, ctx.nip - 4);
9648 }
9649 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9650 break;
9651 }
9652 }
9653 (*(handler->handler))(&ctx);
9654 #if defined(DO_PPC_STATISTICS)
9655 handler->count++;
9656 #endif
9657 /* Check trace mode exceptions */
9658 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9659 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9660 ctx.exception != POWERPC_SYSCALL &&
9661 ctx.exception != POWERPC_EXCP_TRAP &&
9662 ctx.exception != POWERPC_EXCP_BRANCH)) {
9663 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9664 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9665 (env->singlestep_enabled) ||
9666 singlestep ||
9667 num_insns >= max_insns)) {
9668 /* if we reach a page boundary or are single stepping, stop
9669 * generation
9670 */
9671 break;
9672 }
9673 }
9674 if (tb->cflags & CF_LAST_IO)
9675 gen_io_end();
9676 if (ctx.exception == POWERPC_EXCP_NONE) {
9677 gen_goto_tb(&ctx, 0, ctx.nip);
9678 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9679 if (unlikely(env->singlestep_enabled)) {
9680 gen_debug_exception(ctxp);
9681 }
9682 /* Generate the return instruction */
9683 tcg_gen_exit_tb(0);
9684 }
9685 gen_icount_end(tb, num_insns);
9686 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9687 if (unlikely(search_pc)) {
9688 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9689 lj++;
9690 while (lj <= j)
9691 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9692 } else {
9693 tb->size = ctx.nip - pc_start;
9694 tb->icount = num_insns;
9695 }
9696 #if defined(DEBUG_DISAS)
9697 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9698 int flags;
9699 flags = env->bfd_mach;
9700 flags |= ctx.le_mode << 16;
9701 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9702 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9703 qemu_log("\n");
9704 }
9705 #endif
9706 }
9707
9708 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9709 {
9710 gen_intermediate_code_internal(env, tb, 0);
9711 }
9712
9713 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9714 {
9715 gen_intermediate_code_internal(env, tb, 1);
9716 }
9717
9718 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9719 {
9720 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9721 }
Qemu copy for testing