2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "host-utils.h"
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
41 # define LOG_DISAS(...) do { } while (0)
43 /*****************************************************************************/
44 /* Code translation helpers */
46 /* global register indexes */
47 static TCGv_ptr cpu_env
;
48 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
55 static TCGv cpu_gpr
[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh
[32];
59 static TCGv_i64 cpu_fpr
[32];
60 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
61 static TCGv_i32 cpu_crf
[8];
66 #if defined(TARGET_PPC64)
70 static TCGv cpu_reserve
;
71 static TCGv_i32 cpu_fpscr
;
72 static TCGv_i32 cpu_access_type
;
74 #include "gen-icount.h"
76 void ppc_translate_init(void)
80 size_t cpu_reg_names_size
;
81 static int done_init
= 0;
86 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
89 cpu_reg_names_size
= sizeof(cpu_reg_names
);
91 for (i
= 0; i
< 8; i
++) {
92 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
93 cpu_crf
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
94 offsetof(CPUPPCState
, crf
[i
]), p
);
96 cpu_reg_names_size
-= 5;
99 for (i
= 0; i
< 32; i
++) {
100 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
101 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
102 offsetof(CPUPPCState
, gpr
[i
]), p
);
103 p
+= (i
< 10) ? 3 : 4;
104 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
107 cpu_gprh
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
108 offsetof(CPUPPCState
, gprh
[i
]), p
);
109 p
+= (i
< 10) ? 4 : 5;
110 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
113 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
114 cpu_fpr
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
115 offsetof(CPUPPCState
, fpr
[i
]), p
);
116 p
+= (i
< 10) ? 4 : 5;
117 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
119 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
122 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
124 cpu_avrh
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
125 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
127 p
+= (i
< 10) ? 6 : 7;
128 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
130 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
133 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
135 cpu_avrl
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
136 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
138 p
+= (i
< 10) ? 6 : 7;
139 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
142 cpu_nip
= tcg_global_mem_new(TCG_AREG0
,
143 offsetof(CPUPPCState
, nip
), "nip");
145 cpu_msr
= tcg_global_mem_new(TCG_AREG0
,
146 offsetof(CPUPPCState
, msr
), "msr");
148 cpu_ctr
= tcg_global_mem_new(TCG_AREG0
,
149 offsetof(CPUPPCState
, ctr
), "ctr");
151 cpu_lr
= tcg_global_mem_new(TCG_AREG0
,
152 offsetof(CPUPPCState
, lr
), "lr");
154 #if defined(TARGET_PPC64)
155 cpu_cfar
= tcg_global_mem_new(TCG_AREG0
,
156 offsetof(CPUPPCState
, cfar
), "cfar");
159 cpu_xer
= tcg_global_mem_new(TCG_AREG0
,
160 offsetof(CPUPPCState
, xer
), "xer");
162 cpu_reserve
= tcg_global_mem_new(TCG_AREG0
,
163 offsetof(CPUPPCState
, reserve_addr
),
166 cpu_fpscr
= tcg_global_mem_new_i32(TCG_AREG0
,
167 offsetof(CPUPPCState
, fpscr
), "fpscr");
169 cpu_access_type
= tcg_global_mem_new_i32(TCG_AREG0
,
170 offsetof(CPUPPCState
, access_type
), "access_type");
172 /* register helpers */
179 /* internal defines */
180 typedef struct DisasContext
{
181 struct TranslationBlock
*tb
;
185 /* Routine used to access memory */
188 /* Translation flags */
190 #if defined(TARGET_PPC64)
197 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
198 int singlestep_enabled
;
201 struct opc_handler_t
{
202 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
204 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
206 /* instruction type */
208 /* extended instruction type */
211 void (*handler
)(DisasContext
*ctx
);
212 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
215 #if defined(DO_PPC_STATISTICS)
220 static inline void gen_reset_fpstatus(void)
222 gen_helper_reset_fpstatus(cpu_env
);
225 static inline void gen_compute_fprf(TCGv_i64 arg
, int set_fprf
, int set_rc
)
227 TCGv_i32 t0
= tcg_temp_new_i32();
230 /* This case might be optimized later */
231 tcg_gen_movi_i32(t0
, 1);
232 gen_helper_compute_fprf(t0
, cpu_env
, arg
, t0
);
233 if (unlikely(set_rc
)) {
234 tcg_gen_mov_i32(cpu_crf
[1], t0
);
236 gen_helper_float_check_status(cpu_env
);
237 } else if (unlikely(set_rc
)) {
238 /* We always need to compute fpcc */
239 tcg_gen_movi_i32(t0
, 0);
240 gen_helper_compute_fprf(t0
, cpu_env
, arg
, t0
);
241 tcg_gen_mov_i32(cpu_crf
[1], t0
);
244 tcg_temp_free_i32(t0
);
247 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
249 if (ctx
->access_type
!= access_type
) {
250 tcg_gen_movi_i32(cpu_access_type
, access_type
);
251 ctx
->access_type
= access_type
;
255 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
257 #if defined(TARGET_PPC64)
259 tcg_gen_movi_tl(cpu_nip
, nip
);
262 tcg_gen_movi_tl(cpu_nip
, (uint32_t)nip
);
265 static inline void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
268 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
269 gen_update_nip(ctx
, ctx
->nip
);
271 t0
= tcg_const_i32(excp
);
272 t1
= tcg_const_i32(error
);
273 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
274 tcg_temp_free_i32(t0
);
275 tcg_temp_free_i32(t1
);
276 ctx
->exception
= (excp
);
279 static inline void gen_exception(DisasContext
*ctx
, uint32_t excp
)
282 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
283 gen_update_nip(ctx
, ctx
->nip
);
285 t0
= tcg_const_i32(excp
);
286 gen_helper_raise_exception(cpu_env
, t0
);
287 tcg_temp_free_i32(t0
);
288 ctx
->exception
= (excp
);
291 static inline void gen_debug_exception(DisasContext
*ctx
)
295 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
296 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
297 gen_update_nip(ctx
, ctx
->nip
);
299 t0
= tcg_const_i32(EXCP_DEBUG
);
300 gen_helper_raise_exception(cpu_env
, t0
);
301 tcg_temp_free_i32(t0
);
304 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
306 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_INVAL
| error
);
309 /* Stop translation */
310 static inline void gen_stop_exception(DisasContext
*ctx
)
312 gen_update_nip(ctx
, ctx
->nip
);
313 ctx
->exception
= POWERPC_EXCP_STOP
;
316 /* No need to update nip here, as execution flow will change */
317 static inline void gen_sync_exception(DisasContext
*ctx
)
319 ctx
->exception
= POWERPC_EXCP_SYNC
;
322 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
323 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
325 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
326 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
328 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
331 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
334 typedef struct opcode_t
{
335 unsigned char opc1
, opc2
, opc3
;
336 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
337 unsigned char pad
[5];
339 unsigned char pad
[1];
341 opc_handler_t handler
;
345 /*****************************************************************************/
346 /*** Instruction decoding ***/
347 #define EXTRACT_HELPER(name, shift, nb) \
348 static inline uint32_t name(uint32_t opcode) \
350 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
353 #define EXTRACT_SHELPER(name, shift, nb) \
354 static inline int32_t name(uint32_t opcode) \
356 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
360 EXTRACT_HELPER(opc1
, 26, 6);
362 EXTRACT_HELPER(opc2
, 1, 5);
364 EXTRACT_HELPER(opc3
, 6, 5);
365 /* Update Cr0 flags */
366 EXTRACT_HELPER(Rc
, 0, 1);
368 EXTRACT_HELPER(rD
, 21, 5);
370 EXTRACT_HELPER(rS
, 21, 5);
372 EXTRACT_HELPER(rA
, 16, 5);
374 EXTRACT_HELPER(rB
, 11, 5);
376 EXTRACT_HELPER(rC
, 6, 5);
378 EXTRACT_HELPER(crfD
, 23, 3);
379 EXTRACT_HELPER(crfS
, 18, 3);
380 EXTRACT_HELPER(crbD
, 21, 5);
381 EXTRACT_HELPER(crbA
, 16, 5);
382 EXTRACT_HELPER(crbB
, 11, 5);
384 EXTRACT_HELPER(_SPR
, 11, 10);
385 static inline uint32_t SPR(uint32_t opcode
)
387 uint32_t sprn
= _SPR(opcode
);
389 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
391 /*** Get constants ***/
392 EXTRACT_HELPER(IMM
, 12, 8);
393 /* 16 bits signed immediate value */
394 EXTRACT_SHELPER(SIMM
, 0, 16);
395 /* 16 bits unsigned immediate value */
396 EXTRACT_HELPER(UIMM
, 0, 16);
397 /* 5 bits signed immediate value */
398 EXTRACT_HELPER(SIMM5
, 16, 5);
399 /* 5 bits signed immediate value */
400 EXTRACT_HELPER(UIMM5
, 16, 5);
402 EXTRACT_HELPER(NB
, 11, 5);
404 EXTRACT_HELPER(SH
, 11, 5);
405 /* Vector shift count */
406 EXTRACT_HELPER(VSH
, 6, 4);
408 EXTRACT_HELPER(MB
, 6, 5);
410 EXTRACT_HELPER(ME
, 1, 5);
412 EXTRACT_HELPER(TO
, 21, 5);
414 EXTRACT_HELPER(CRM
, 12, 8);
415 EXTRACT_HELPER(FM
, 17, 8);
416 EXTRACT_HELPER(SR
, 16, 4);
417 EXTRACT_HELPER(FPIMM
, 12, 4);
419 /*** Jump target decoding ***/
421 EXTRACT_SHELPER(d
, 0, 16);
422 /* Immediate address */
423 static inline target_ulong
LI(uint32_t opcode
)
425 return (opcode
>> 0) & 0x03FFFFFC;
428 static inline uint32_t BD(uint32_t opcode
)
430 return (opcode
>> 0) & 0xFFFC;
433 EXTRACT_HELPER(BO
, 21, 5);
434 EXTRACT_HELPER(BI
, 16, 5);
435 /* Absolute/relative address */
436 EXTRACT_HELPER(AA
, 1, 1);
438 EXTRACT_HELPER(LK
, 0, 1);
440 /* Create a mask between <start> and <end> bits */
441 static inline target_ulong
MASK(uint32_t start
, uint32_t end
)
445 #if defined(TARGET_PPC64)
446 if (likely(start
== 0)) {
447 ret
= UINT64_MAX
<< (63 - end
);
448 } else if (likely(end
== 63)) {
449 ret
= UINT64_MAX
>> start
;
452 if (likely(start
== 0)) {
453 ret
= UINT32_MAX
<< (31 - end
);
454 } else if (likely(end
== 31)) {
455 ret
= UINT32_MAX
>> start
;
459 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
460 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
461 if (unlikely(start
> end
))
468 /*****************************************************************************/
469 /* PowerPC instructions table */
471 #if defined(DO_PPC_STATISTICS)
472 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
482 .handler = &gen_##name, \
483 .oname = stringify(name), \
485 .oname = stringify(name), \
487 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
498 .handler = &gen_##name, \
499 .oname = stringify(name), \
501 .oname = stringify(name), \
503 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
513 .handler = &gen_##name, \
519 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
529 .handler = &gen_##name, \
531 .oname = stringify(name), \
533 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
544 .handler = &gen_##name, \
546 .oname = stringify(name), \
548 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
558 .handler = &gen_##name, \
564 /* SPR load/store helpers */
565 static inline void gen_load_spr(TCGv t
, int reg
)
567 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
570 static inline void gen_store_spr(int reg
, TCGv t
)
572 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
575 /* Invalid instruction */
576 static void gen_invalid(DisasContext
*ctx
)
578 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
581 static opc_handler_t invalid_handler
= {
582 .inval1
= 0xFFFFFFFF,
583 .inval2
= 0xFFFFFFFF,
586 .handler
= gen_invalid
,
589 /*** Integer comparison ***/
591 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
595 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_xer
);
596 tcg_gen_shri_i32(cpu_crf
[crf
], cpu_crf
[crf
], XER_SO
);
597 tcg_gen_andi_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1);
599 l1
= gen_new_label();
600 l2
= gen_new_label();
601 l3
= gen_new_label();
603 tcg_gen_brcond_tl(TCG_COND_LT
, arg0
, arg1
, l1
);
604 tcg_gen_brcond_tl(TCG_COND_GT
, arg0
, arg1
, l2
);
606 tcg_gen_brcond_tl(TCG_COND_LTU
, arg0
, arg1
, l1
);
607 tcg_gen_brcond_tl(TCG_COND_GTU
, arg0
, arg1
, l2
);
609 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_EQ
);
612 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_LT
);
615 tcg_gen_ori_i32(cpu_crf
[crf
], cpu_crf
[crf
], 1 << CRF_GT
);
619 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
621 TCGv t0
= tcg_const_local_tl(arg1
);
622 gen_op_cmp(arg0
, t0
, s
, crf
);
626 #if defined(TARGET_PPC64)
627 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
630 t0
= tcg_temp_local_new();
631 t1
= tcg_temp_local_new();
633 tcg_gen_ext32s_tl(t0
, arg0
);
634 tcg_gen_ext32s_tl(t1
, arg1
);
636 tcg_gen_ext32u_tl(t0
, arg0
);
637 tcg_gen_ext32u_tl(t1
, arg1
);
639 gen_op_cmp(t0
, t1
, s
, crf
);
644 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
646 TCGv t0
= tcg_const_local_tl(arg1
);
647 gen_op_cmp32(arg0
, t0
, s
, crf
);
652 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
654 #if defined(TARGET_PPC64)
656 gen_op_cmpi32(reg
, 0, 1, 0);
659 gen_op_cmpi(reg
, 0, 1, 0);
663 static void gen_cmp(DisasContext
*ctx
)
665 #if defined(TARGET_PPC64)
666 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
667 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
668 1, crfD(ctx
->opcode
));
671 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
672 1, crfD(ctx
->opcode
));
676 static void gen_cmpi(DisasContext
*ctx
)
678 #if defined(TARGET_PPC64)
679 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
680 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
681 1, crfD(ctx
->opcode
));
684 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
685 1, crfD(ctx
->opcode
));
689 static void gen_cmpl(DisasContext
*ctx
)
691 #if defined(TARGET_PPC64)
692 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
693 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
694 0, crfD(ctx
->opcode
));
697 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
698 0, crfD(ctx
->opcode
));
702 static void gen_cmpli(DisasContext
*ctx
)
704 #if defined(TARGET_PPC64)
705 if (!(ctx
->sf_mode
&& (ctx
->opcode
& 0x00200000)))
706 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
707 0, crfD(ctx
->opcode
));
710 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
711 0, crfD(ctx
->opcode
));
714 /* isel (PowerPC 2.03 specification) */
715 static void gen_isel(DisasContext
*ctx
)
718 uint32_t bi
= rC(ctx
->opcode
);
722 l1
= gen_new_label();
723 l2
= gen_new_label();
725 mask
= 1 << (3 - (bi
& 0x03));
726 t0
= tcg_temp_new_i32();
727 tcg_gen_andi_i32(t0
, cpu_crf
[bi
>> 2], mask
);
728 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
729 if (rA(ctx
->opcode
) == 0)
730 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
732 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
735 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
737 tcg_temp_free_i32(t0
);
740 /*** Integer arithmetic ***/
742 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
743 TCGv arg1
, TCGv arg2
, int sub
)
748 l1
= gen_new_label();
749 /* Start with XER OV disabled, the most likely case */
750 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
751 t0
= tcg_temp_local_new();
752 tcg_gen_xor_tl(t0
, arg0
, arg1
);
753 #if defined(TARGET_PPC64)
755 tcg_gen_ext32s_tl(t0
, t0
);
758 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0, l1
);
760 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
761 tcg_gen_xor_tl(t0
, arg1
, arg2
);
762 #if defined(TARGET_PPC64)
764 tcg_gen_ext32s_tl(t0
, t0
);
767 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
769 tcg_gen_brcondi_tl(TCG_COND_LT
, t0
, 0, l1
);
770 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
775 static inline void gen_op_arith_compute_ca(DisasContext
*ctx
, TCGv arg1
,
778 int l1
= gen_new_label();
780 #if defined(TARGET_PPC64)
781 if (!(ctx
->sf_mode
)) {
786 tcg_gen_ext32u_tl(t0
, arg1
);
787 tcg_gen_ext32u_tl(t1
, arg2
);
789 tcg_gen_brcond_tl(TCG_COND_GTU
, t0
, t1
, l1
);
791 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
793 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
801 tcg_gen_brcond_tl(TCG_COND_GTU
, arg1
, arg2
, l1
);
803 tcg_gen_brcond_tl(TCG_COND_GEU
, arg1
, arg2
, l1
);
805 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
810 /* Common add function */
811 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
812 TCGv arg2
, int add_ca
, int compute_ca
,
817 if ((!compute_ca
&& !compute_ov
) ||
818 (!TCGV_EQUAL(ret
,arg1
) && !TCGV_EQUAL(ret
, arg2
))) {
821 t0
= tcg_temp_local_new();
825 t1
= tcg_temp_local_new();
826 tcg_gen_andi_tl(t1
, cpu_xer
, (1 << XER_CA
));
827 tcg_gen_shri_tl(t1
, t1
, XER_CA
);
832 if (compute_ca
&& compute_ov
) {
833 /* Start with XER CA and OV disabled, the most likely case */
834 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~((1 << XER_CA
) | (1 << XER_OV
)));
835 } else if (compute_ca
) {
836 /* Start with XER CA disabled, the most likely case */
837 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
838 } else if (compute_ov
) {
839 /* Start with XER OV disabled, the most likely case */
840 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
843 tcg_gen_add_tl(t0
, arg1
, arg2
);
846 gen_op_arith_compute_ca(ctx
, t0
, arg1
, 0);
849 tcg_gen_add_tl(t0
, t0
, t1
);
850 gen_op_arith_compute_ca(ctx
, t0
, t1
, 0);
854 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
857 if (unlikely(Rc(ctx
->opcode
) != 0))
858 gen_set_Rc0(ctx
, t0
);
860 if (!TCGV_EQUAL(t0
, ret
)) {
861 tcg_gen_mov_tl(ret
, t0
);
865 /* Add functions with two operands */
866 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
867 static void glue(gen_, name)(DisasContext *ctx) \
869 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
870 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
871 add_ca, compute_ca, compute_ov); \
873 /* Add functions with one operand and one immediate */
874 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
875 add_ca, compute_ca, compute_ov) \
876 static void glue(gen_, name)(DisasContext *ctx) \
878 TCGv t0 = tcg_const_local_tl(const_val); \
879 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
880 cpu_gpr[rA(ctx->opcode)], t0, \
881 add_ca, compute_ca, compute_ov); \
885 /* add add. addo addo. */
886 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
887 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
888 /* addc addc. addco addco. */
889 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
890 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
891 /* adde adde. addeo addeo. */
892 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
893 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
894 /* addme addme. addmeo addmeo. */
895 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
896 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
897 /* addze addze. addzeo addzeo.*/
898 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
899 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
901 static void gen_addi(DisasContext
*ctx
)
903 target_long simm
= SIMM(ctx
->opcode
);
905 if (rA(ctx
->opcode
) == 0) {
907 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
909 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], simm
);
913 static inline void gen_op_addic(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
916 target_long simm
= SIMM(ctx
->opcode
);
918 /* Start with XER CA and OV disabled, the most likely case */
919 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
921 if (likely(simm
!= 0)) {
922 TCGv t0
= tcg_temp_local_new();
923 tcg_gen_addi_tl(t0
, arg1
, simm
);
924 gen_op_arith_compute_ca(ctx
, t0
, arg1
, 0);
925 tcg_gen_mov_tl(ret
, t0
);
928 tcg_gen_mov_tl(ret
, arg1
);
931 gen_set_Rc0(ctx
, ret
);
935 static void gen_addic(DisasContext
*ctx
)
937 gen_op_addic(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0);
940 static void gen_addic_(DisasContext
*ctx
)
942 gen_op_addic(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 1);
946 static void gen_addis(DisasContext
*ctx
)
948 target_long simm
= SIMM(ctx
->opcode
);
950 if (rA(ctx
->opcode
) == 0) {
952 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
954 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
958 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
959 TCGv arg2
, int sign
, int compute_ov
)
961 int l1
= gen_new_label();
962 int l2
= gen_new_label();
963 TCGv_i32 t0
= tcg_temp_local_new_i32();
964 TCGv_i32 t1
= tcg_temp_local_new_i32();
966 tcg_gen_trunc_tl_i32(t0
, arg1
);
967 tcg_gen_trunc_tl_i32(t1
, arg2
);
968 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
970 int l3
= gen_new_label();
971 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
972 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
974 tcg_gen_div_i32(t0
, t0
, t1
);
976 tcg_gen_divu_i32(t0
, t0
, t1
);
979 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
984 tcg_gen_sari_i32(t0
, t0
, 31);
986 tcg_gen_movi_i32(t0
, 0);
989 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
992 tcg_gen_extu_i32_tl(ret
, t0
);
993 tcg_temp_free_i32(t0
);
994 tcg_temp_free_i32(t1
);
995 if (unlikely(Rc(ctx
->opcode
) != 0))
996 gen_set_Rc0(ctx
, ret
);
999 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1000 static void glue(gen_, name)(DisasContext *ctx) \
1002 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1004 sign, compute_ov); \
1006 /* divwu divwu. divwuo divwuo. */
1007 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1008 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1009 /* divw divw. divwo divwo. */
1010 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1011 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1012 #if defined(TARGET_PPC64)
1013 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1014 TCGv arg2
, int sign
, int compute_ov
)
1016 int l1
= gen_new_label();
1017 int l2
= gen_new_label();
1019 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
1021 int l3
= gen_new_label();
1022 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
1023 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
1025 tcg_gen_div_i64(ret
, arg1
, arg2
);
1027 tcg_gen_divu_i64(ret
, arg1
, arg2
);
1030 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1035 tcg_gen_sari_i64(ret
, arg1
, 63);
1037 tcg_gen_movi_i64(ret
, 0);
1040 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1043 if (unlikely(Rc(ctx
->opcode
) != 0))
1044 gen_set_Rc0(ctx
, ret
);
1046 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1047 static void glue(gen_, name)(DisasContext *ctx) \
1049 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1050 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1051 sign, compute_ov); \
1053 /* divwu divwu. divwuo divwuo. */
1054 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1055 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1056 /* divw divw. divwo divwo. */
1057 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1058 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1062 static void gen_mulhw(DisasContext
*ctx
)
1066 t0
= tcg_temp_new_i64();
1067 t1
= tcg_temp_new_i64();
1068 #if defined(TARGET_PPC64)
1069 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1070 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1071 tcg_gen_mul_i64(t0
, t0
, t1
);
1072 tcg_gen_shri_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
1074 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1075 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1076 tcg_gen_mul_i64(t0
, t0
, t1
);
1077 tcg_gen_shri_i64(t0
, t0
, 32);
1078 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1080 tcg_temp_free_i64(t0
);
1081 tcg_temp_free_i64(t1
);
1082 if (unlikely(Rc(ctx
->opcode
) != 0))
1083 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1086 /* mulhwu mulhwu. */
1087 static void gen_mulhwu(DisasContext
*ctx
)
1091 t0
= tcg_temp_new_i64();
1092 t1
= tcg_temp_new_i64();
1093 #if defined(TARGET_PPC64)
1094 tcg_gen_ext32u_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1095 tcg_gen_ext32u_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1096 tcg_gen_mul_i64(t0
, t0
, t1
);
1097 tcg_gen_shri_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
1099 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1100 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1101 tcg_gen_mul_i64(t0
, t0
, t1
);
1102 tcg_gen_shri_i64(t0
, t0
, 32);
1103 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1105 tcg_temp_free_i64(t0
);
1106 tcg_temp_free_i64(t1
);
1107 if (unlikely(Rc(ctx
->opcode
) != 0))
1108 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1112 static void gen_mullw(DisasContext
*ctx
)
1114 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1115 cpu_gpr
[rB(ctx
->opcode
)]);
1116 tcg_gen_ext32s_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)]);
1117 if (unlikely(Rc(ctx
->opcode
) != 0))
1118 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1121 /* mullwo mullwo. */
1122 static void gen_mullwo(DisasContext
*ctx
)
1127 t0
= tcg_temp_new_i64();
1128 t1
= tcg_temp_new_i64();
1129 l1
= gen_new_label();
1130 /* Start with XER OV disabled, the most likely case */
1131 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1132 #if defined(TARGET_PPC64)
1133 tcg_gen_ext32s_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1134 tcg_gen_ext32s_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1136 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1137 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1139 tcg_gen_mul_i64(t0
, t0
, t1
);
1140 #if defined(TARGET_PPC64)
1141 tcg_gen_ext32s_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1142 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, cpu_gpr
[rD(ctx
->opcode
)], l1
);
1144 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1145 tcg_gen_ext32s_i64(t1
, t0
);
1146 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
1148 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1150 tcg_temp_free_i64(t0
);
1151 tcg_temp_free_i64(t1
);
1152 if (unlikely(Rc(ctx
->opcode
) != 0))
1153 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1157 static void gen_mulli(DisasContext
*ctx
)
1159 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1162 #if defined(TARGET_PPC64)
1163 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1164 static void glue(gen_, name)(DisasContext *ctx) \
1166 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1167 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1168 if (unlikely(Rc(ctx->opcode) != 0)) \
1169 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1172 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00);
1173 /* mulhdu mulhdu. */
1174 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02);
1177 static void gen_mulld(DisasContext
*ctx
)
1179 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1180 cpu_gpr
[rB(ctx
->opcode
)]);
1181 if (unlikely(Rc(ctx
->opcode
) != 0))
1182 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1185 /* mulldo mulldo. */
1186 static void gen_mulldo(DisasContext
*ctx
)
1188 gen_helper_mulldo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
1189 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1190 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1191 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1196 /* neg neg. nego nego. */
1197 static inline void gen_op_arith_neg(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1200 int l1
= gen_new_label();
1201 int l2
= gen_new_label();
1202 TCGv t0
= tcg_temp_local_new();
1203 #if defined(TARGET_PPC64)
1205 tcg_gen_mov_tl(t0
, arg1
);
1206 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, INT64_MIN
, l1
);
1210 tcg_gen_ext32s_tl(t0
, arg1
);
1211 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
1213 tcg_gen_neg_tl(ret
, arg1
);
1215 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1219 tcg_gen_mov_tl(ret
, t0
);
1221 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
1225 if (unlikely(Rc(ctx
->opcode
) != 0))
1226 gen_set_Rc0(ctx
, ret
);
1229 static void gen_neg(DisasContext
*ctx
)
1231 gen_op_arith_neg(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0);
1234 static void gen_nego(DisasContext
*ctx
)
1236 gen_op_arith_neg(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 1);
1239 /* Common subf function */
1240 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1241 TCGv arg2
, int add_ca
, int compute_ca
,
1246 if ((!compute_ca
&& !compute_ov
) ||
1247 (!TCGV_EQUAL(ret
, arg1
) && !TCGV_EQUAL(ret
, arg2
))) {
1250 t0
= tcg_temp_local_new();
1254 t1
= tcg_temp_local_new();
1255 tcg_gen_andi_tl(t1
, cpu_xer
, (1 << XER_CA
));
1256 tcg_gen_shri_tl(t1
, t1
, XER_CA
);
1261 if (compute_ca
&& compute_ov
) {
1262 /* Start with XER CA and OV disabled, the most likely case */
1263 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~((1 << XER_CA
) | (1 << XER_OV
)));
1264 } else if (compute_ca
) {
1265 /* Start with XER CA disabled, the most likely case */
1266 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1267 } else if (compute_ov
) {
1268 /* Start with XER OV disabled, the most likely case */
1269 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
1273 tcg_gen_not_tl(t0
, arg1
);
1274 tcg_gen_add_tl(t0
, t0
, arg2
);
1275 gen_op_arith_compute_ca(ctx
, t0
, arg2
, 0);
1276 tcg_gen_add_tl(t0
, t0
, t1
);
1277 gen_op_arith_compute_ca(ctx
, t0
, t1
, 0);
1280 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1282 gen_op_arith_compute_ca(ctx
, t0
, arg2
, 1);
1286 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1289 if (unlikely(Rc(ctx
->opcode
) != 0))
1290 gen_set_Rc0(ctx
, t0
);
1292 if (!TCGV_EQUAL(t0
, ret
)) {
1293 tcg_gen_mov_tl(ret
, t0
);
1297 /* Sub functions with Two operands functions */
1298 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1299 static void glue(gen_, name)(DisasContext *ctx) \
1301 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1302 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1303 add_ca, compute_ca, compute_ov); \
1305 /* Sub functions with one operand and one immediate */
1306 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1307 add_ca, compute_ca, compute_ov) \
1308 static void glue(gen_, name)(DisasContext *ctx) \
1310 TCGv t0 = tcg_const_local_tl(const_val); \
1311 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1312 cpu_gpr[rA(ctx->opcode)], t0, \
1313 add_ca, compute_ca, compute_ov); \
1314 tcg_temp_free(t0); \
1316 /* subf subf. subfo subfo. */
1317 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1318 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1319 /* subfc subfc. subfco subfco. */
1320 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1321 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1322 /* subfe subfe. subfeo subfo. */
1323 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1324 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1325 /* subfme subfme. subfmeo subfmeo. */
1326 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1327 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1328 /* subfze subfze. subfzeo subfzeo.*/
1329 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1330 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1333 static void gen_subfic(DisasContext
*ctx
)
1335 /* Start with XER CA and OV disabled, the most likely case */
1336 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1337 TCGv t0
= tcg_temp_local_new();
1338 TCGv t1
= tcg_const_local_tl(SIMM(ctx
->opcode
));
1339 tcg_gen_sub_tl(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)]);
1340 gen_op_arith_compute_ca(ctx
, t0
, t1
, 1);
1342 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1346 /*** Integer logical ***/
1347 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1348 static void glue(gen_, name)(DisasContext *ctx) \
1350 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1351 cpu_gpr[rB(ctx->opcode)]); \
1352 if (unlikely(Rc(ctx->opcode) != 0)) \
1353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1356 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1357 static void glue(gen_, name)(DisasContext *ctx) \
1359 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1360 if (unlikely(Rc(ctx->opcode) != 0)) \
1361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1365 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1367 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1370 static void gen_andi_(DisasContext
*ctx
)
1372 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1373 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1377 static void gen_andis_(DisasContext
*ctx
)
1379 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1380 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1384 static void gen_cntlzw(DisasContext
*ctx
)
1386 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1387 if (unlikely(Rc(ctx
->opcode
) != 0))
1388 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1391 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1392 /* extsb & extsb. */
1393 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1394 /* extsh & extsh. */
1395 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1397 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1399 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1402 static void gen_or(DisasContext
*ctx
)
1406 rs
= rS(ctx
->opcode
);
1407 ra
= rA(ctx
->opcode
);
1408 rb
= rB(ctx
->opcode
);
1409 /* Optimisation for mr. ri case */
1410 if (rs
!= ra
|| rs
!= rb
) {
1412 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1414 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1415 if (unlikely(Rc(ctx
->opcode
) != 0))
1416 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1417 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1418 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1419 #if defined(TARGET_PPC64)
1425 /* Set process priority to low */
1429 /* Set process priority to medium-low */
1433 /* Set process priority to normal */
1436 #if !defined(CONFIG_USER_ONLY)
1438 if (ctx
->mem_idx
> 0) {
1439 /* Set process priority to very low */
1444 if (ctx
->mem_idx
> 0) {
1445 /* Set process priority to medium-hight */
1450 if (ctx
->mem_idx
> 0) {
1451 /* Set process priority to high */
1456 if (ctx
->mem_idx
> 1) {
1457 /* Set process priority to very high */
1467 TCGv t0
= tcg_temp_new();
1468 gen_load_spr(t0
, SPR_PPR
);
1469 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1470 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1471 gen_store_spr(SPR_PPR
, t0
);
1478 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1481 static void gen_xor(DisasContext
*ctx
)
1483 /* Optimisation for "set to zero" case */
1484 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1485 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1487 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1488 if (unlikely(Rc(ctx
->opcode
) != 0))
1489 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1493 static void gen_ori(DisasContext
*ctx
)
1495 target_ulong uimm
= UIMM(ctx
->opcode
);
1497 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1499 /* XXX: should handle special NOPs for POWER series */
1502 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1506 static void gen_oris(DisasContext
*ctx
)
1508 target_ulong uimm
= UIMM(ctx
->opcode
);
1510 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1514 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1518 static void gen_xori(DisasContext
*ctx
)
1520 target_ulong uimm
= UIMM(ctx
->opcode
);
1522 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1526 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1530 static void gen_xoris(DisasContext
*ctx
)
1532 target_ulong uimm
= UIMM(ctx
->opcode
);
1534 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1538 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1541 /* popcntb : PowerPC 2.03 specification */
1542 static void gen_popcntb(DisasContext
*ctx
)
1544 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1547 static void gen_popcntw(DisasContext
*ctx
)
1549 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1552 #if defined(TARGET_PPC64)
1553 /* popcntd: PowerPC 2.06 specification */
1554 static void gen_popcntd(DisasContext
*ctx
)
1556 gen_helper_popcntd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1560 #if defined(TARGET_PPC64)
1561 /* extsw & extsw. */
1562 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1565 static void gen_cntlzd(DisasContext
*ctx
)
1567 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1568 if (unlikely(Rc(ctx
->opcode
) != 0))
1569 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1573 /*** Integer rotate ***/
1575 /* rlwimi & rlwimi. */
1576 static void gen_rlwimi(DisasContext
*ctx
)
1578 uint32_t mb
, me
, sh
;
1580 mb
= MB(ctx
->opcode
);
1581 me
= ME(ctx
->opcode
);
1582 sh
= SH(ctx
->opcode
);
1583 if (likely(sh
== 0 && mb
== 0 && me
== 31)) {
1584 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1588 TCGv t0
= tcg_temp_new();
1589 #if defined(TARGET_PPC64)
1590 TCGv_i32 t2
= tcg_temp_new_i32();
1591 tcg_gen_trunc_i64_i32(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
1592 tcg_gen_rotli_i32(t2
, t2
, sh
);
1593 tcg_gen_extu_i32_i64(t0
, t2
);
1594 tcg_temp_free_i32(t2
);
1596 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1598 #if defined(TARGET_PPC64)
1602 mask
= MASK(mb
, me
);
1603 t1
= tcg_temp_new();
1604 tcg_gen_andi_tl(t0
, t0
, mask
);
1605 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1606 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1610 if (unlikely(Rc(ctx
->opcode
) != 0))
1611 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1614 /* rlwinm & rlwinm. */
1615 static void gen_rlwinm(DisasContext
*ctx
)
1617 uint32_t mb
, me
, sh
;
1619 sh
= SH(ctx
->opcode
);
1620 mb
= MB(ctx
->opcode
);
1621 me
= ME(ctx
->opcode
);
1623 if (likely(mb
== 0 && me
== (31 - sh
))) {
1624 if (likely(sh
== 0)) {
1625 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1627 TCGv t0
= tcg_temp_new();
1628 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1629 tcg_gen_shli_tl(t0
, t0
, sh
);
1630 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1633 } else if (likely(sh
!= 0 && me
== 31 && sh
== (32 - mb
))) {
1634 TCGv t0
= tcg_temp_new();
1635 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1636 tcg_gen_shri_tl(t0
, t0
, mb
);
1637 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1640 TCGv t0
= tcg_temp_new();
1641 #if defined(TARGET_PPC64)
1642 TCGv_i32 t1
= tcg_temp_new_i32();
1643 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1644 tcg_gen_rotli_i32(t1
, t1
, sh
);
1645 tcg_gen_extu_i32_i64(t0
, t1
);
1646 tcg_temp_free_i32(t1
);
1648 tcg_gen_rotli_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1650 #if defined(TARGET_PPC64)
1654 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1657 if (unlikely(Rc(ctx
->opcode
) != 0))
1658 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1661 /* rlwnm & rlwnm. */
1662 static void gen_rlwnm(DisasContext
*ctx
)
1666 #if defined(TARGET_PPC64)
1670 mb
= MB(ctx
->opcode
);
1671 me
= ME(ctx
->opcode
);
1672 t0
= tcg_temp_new();
1673 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1674 #if defined(TARGET_PPC64)
1675 t1
= tcg_temp_new_i32();
1676 t2
= tcg_temp_new_i32();
1677 tcg_gen_trunc_i64_i32(t1
, cpu_gpr
[rS(ctx
->opcode
)]);
1678 tcg_gen_trunc_i64_i32(t2
, t0
);
1679 tcg_gen_rotl_i32(t1
, t1
, t2
);
1680 tcg_gen_extu_i32_i64(t0
, t1
);
1681 tcg_temp_free_i32(t1
);
1682 tcg_temp_free_i32(t2
);
1684 tcg_gen_rotl_i32(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1686 if (unlikely(mb
!= 0 || me
!= 31)) {
1687 #if defined(TARGET_PPC64)
1691 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1693 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1696 if (unlikely(Rc(ctx
->opcode
) != 0))
1697 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1700 #if defined(TARGET_PPC64)
1701 #define GEN_PPC64_R2(name, opc1, opc2) \
1702 static void glue(gen_, name##0)(DisasContext *ctx) \
1704 gen_##name(ctx, 0); \
1707 static void glue(gen_, name##1)(DisasContext *ctx) \
1709 gen_##name(ctx, 1); \
1711 #define GEN_PPC64_R4(name, opc1, opc2) \
1712 static void glue(gen_, name##0)(DisasContext *ctx) \
1714 gen_##name(ctx, 0, 0); \
1717 static void glue(gen_, name##1)(DisasContext *ctx) \
1719 gen_##name(ctx, 0, 1); \
1722 static void glue(gen_, name##2)(DisasContext *ctx) \
1724 gen_##name(ctx, 1, 0); \
1727 static void glue(gen_, name##3)(DisasContext *ctx) \
1729 gen_##name(ctx, 1, 1); \
1732 static inline void gen_rldinm(DisasContext
*ctx
, uint32_t mb
, uint32_t me
,
1735 if (likely(sh
!= 0 && mb
== 0 && me
== (63 - sh
))) {
1736 tcg_gen_shli_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
1737 } else if (likely(sh
!= 0 && me
== 63 && sh
== (64 - mb
))) {
1738 tcg_gen_shri_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], mb
);
1740 TCGv t0
= tcg_temp_new();
1741 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1742 if (likely(mb
== 0 && me
== 63)) {
1743 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1745 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1749 if (unlikely(Rc(ctx
->opcode
) != 0))
1750 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1752 /* rldicl - rldicl. */
1753 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
1757 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1758 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1759 gen_rldinm(ctx
, mb
, 63, sh
);
1761 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1762 /* rldicr - rldicr. */
1763 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
1767 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1768 me
= MB(ctx
->opcode
) | (men
<< 5);
1769 gen_rldinm(ctx
, 0, me
, sh
);
1771 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1772 /* rldic - rldic. */
1773 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
1777 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1778 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1779 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1781 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1783 static inline void gen_rldnm(DisasContext
*ctx
, uint32_t mb
, uint32_t me
)
1787 mb
= MB(ctx
->opcode
);
1788 me
= ME(ctx
->opcode
);
1789 t0
= tcg_temp_new();
1790 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1791 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1792 if (unlikely(mb
!= 0 || me
!= 63)) {
1793 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, MASK(mb
, me
));
1795 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
1798 if (unlikely(Rc(ctx
->opcode
) != 0))
1799 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1802 /* rldcl - rldcl. */
1803 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
1807 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1808 gen_rldnm(ctx
, mb
, 63);
1810 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1811 /* rldcr - rldcr. */
1812 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
1816 me
= MB(ctx
->opcode
) | (men
<< 5);
1817 gen_rldnm(ctx
, 0, me
);
1819 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1820 /* rldimi - rldimi. */
1821 static inline void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
1823 uint32_t sh
, mb
, me
;
1825 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1826 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1828 if (unlikely(sh
== 0 && mb
== 0)) {
1829 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1834 t0
= tcg_temp_new();
1835 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
1836 t1
= tcg_temp_new();
1837 mask
= MASK(mb
, me
);
1838 tcg_gen_andi_tl(t0
, t0
, mask
);
1839 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], ~mask
);
1840 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1844 if (unlikely(Rc(ctx
->opcode
) != 0))
1845 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1847 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1850 /*** Integer shift ***/
1853 static void gen_slw(DisasContext
*ctx
)
1857 t0
= tcg_temp_new();
1858 /* AND rS with a mask that is 0 when rB >= 0x20 */
1859 #if defined(TARGET_PPC64)
1860 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1861 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1863 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1864 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1866 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1867 t1
= tcg_temp_new();
1868 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1869 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1872 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1873 if (unlikely(Rc(ctx
->opcode
) != 0))
1874 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1878 static void gen_sraw(DisasContext
*ctx
)
1880 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
1881 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1882 if (unlikely(Rc(ctx
->opcode
) != 0))
1883 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1886 /* srawi & srawi. */
1887 static void gen_srawi(DisasContext
*ctx
)
1889 int sh
= SH(ctx
->opcode
);
1893 l1
= gen_new_label();
1894 l2
= gen_new_label();
1895 t0
= tcg_temp_local_new();
1896 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1897 tcg_gen_brcondi_tl(TCG_COND_GE
, t0
, 0, l1
);
1898 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1ULL << sh
) - 1);
1899 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1900 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
1903 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1905 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
1906 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, sh
);
1909 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1910 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1912 if (unlikely(Rc(ctx
->opcode
) != 0))
1913 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1917 static void gen_srw(DisasContext
*ctx
)
1921 t0
= tcg_temp_new();
1922 /* AND rS with a mask that is 0 when rB >= 0x20 */
1923 #if defined(TARGET_PPC64)
1924 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1925 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1927 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1928 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1930 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1931 tcg_gen_ext32u_tl(t0
, t0
);
1932 t1
= tcg_temp_new();
1933 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1934 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1937 if (unlikely(Rc(ctx
->opcode
) != 0))
1938 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1941 #if defined(TARGET_PPC64)
1943 static void gen_sld(DisasContext
*ctx
)
1947 t0
= tcg_temp_new();
1948 /* AND rS with a mask that is 0 when rB >= 0x40 */
1949 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
1950 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1951 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1952 t1
= tcg_temp_new();
1953 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
1954 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1957 if (unlikely(Rc(ctx
->opcode
) != 0))
1958 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1962 static void gen_srad(DisasContext
*ctx
)
1964 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
1965 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1966 if (unlikely(Rc(ctx
->opcode
) != 0))
1967 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1969 /* sradi & sradi. */
1970 static inline void gen_sradi(DisasContext
*ctx
, int n
)
1972 int sh
= SH(ctx
->opcode
) + (n
<< 5);
1976 l1
= gen_new_label();
1977 l2
= gen_new_label();
1978 t0
= tcg_temp_local_new();
1979 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
1980 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1ULL << sh
) - 1);
1981 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
1982 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, 1 << XER_CA
);
1985 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1988 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
1990 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1991 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
1993 if (unlikely(Rc(ctx
->opcode
) != 0))
1994 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1997 static void gen_sradi0(DisasContext
*ctx
)
2002 static void gen_sradi1(DisasContext
*ctx
)
2008 static void gen_srd(DisasContext
*ctx
)
2012 t0
= tcg_temp_new();
2013 /* AND rS with a mask that is 0 when rB >= 0x40 */
2014 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2015 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2016 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2017 t1
= tcg_temp_new();
2018 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2019 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2022 if (unlikely(Rc(ctx
->opcode
) != 0))
2023 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2027 /*** Floating-Point arithmetic ***/
2028 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2029 static void gen_f##name(DisasContext *ctx) \
2031 if (unlikely(!ctx->fpu_enabled)) { \
2032 gen_exception(ctx, POWERPC_EXCP_FPU); \
2035 /* NIP cannot be restored if the memory exception comes from an helper */ \
2036 gen_update_nip(ctx, ctx->nip - 4); \
2037 gen_reset_fpstatus(); \
2038 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2039 cpu_fpr[rA(ctx->opcode)], \
2040 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2042 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2043 cpu_fpr[rD(ctx->opcode)]); \
2045 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2046 Rc(ctx->opcode) != 0); \
2049 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2050 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2051 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2053 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2054 static void gen_f##name(DisasContext *ctx) \
2056 if (unlikely(!ctx->fpu_enabled)) { \
2057 gen_exception(ctx, POWERPC_EXCP_FPU); \
2060 /* NIP cannot be restored if the memory exception comes from an helper */ \
2061 gen_update_nip(ctx, ctx->nip - 4); \
2062 gen_reset_fpstatus(); \
2063 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2064 cpu_fpr[rA(ctx->opcode)], \
2065 cpu_fpr[rB(ctx->opcode)]); \
2067 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2068 cpu_fpr[rD(ctx->opcode)]); \
2070 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2071 set_fprf, Rc(ctx->opcode) != 0); \
2073 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2074 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2075 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2077 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2078 static void gen_f##name(DisasContext *ctx) \
2080 if (unlikely(!ctx->fpu_enabled)) { \
2081 gen_exception(ctx, POWERPC_EXCP_FPU); \
2084 /* NIP cannot be restored if the memory exception comes from an helper */ \
2085 gen_update_nip(ctx, ctx->nip - 4); \
2086 gen_reset_fpstatus(); \
2087 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2088 cpu_fpr[rA(ctx->opcode)], \
2089 cpu_fpr[rC(ctx->opcode)]); \
2091 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2092 cpu_fpr[rD(ctx->opcode)]); \
2094 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2095 set_fprf, Rc(ctx->opcode) != 0); \
2097 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2098 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2099 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2101 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2102 static void gen_f##name(DisasContext *ctx) \
2104 if (unlikely(!ctx->fpu_enabled)) { \
2105 gen_exception(ctx, POWERPC_EXCP_FPU); \
2108 /* NIP cannot be restored if the memory exception comes from an helper */ \
2109 gen_update_nip(ctx, ctx->nip - 4); \
2110 gen_reset_fpstatus(); \
2111 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2112 cpu_fpr[rB(ctx->opcode)]); \
2113 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2114 set_fprf, Rc(ctx->opcode) != 0); \
2117 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2118 static void gen_f##name(DisasContext *ctx) \
2120 if (unlikely(!ctx->fpu_enabled)) { \
2121 gen_exception(ctx, POWERPC_EXCP_FPU); \
2124 /* NIP cannot be restored if the memory exception comes from an helper */ \
2125 gen_update_nip(ctx, ctx->nip - 4); \
2126 gen_reset_fpstatus(); \
2127 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2128 cpu_fpr[rB(ctx->opcode)]); \
2129 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2130 set_fprf, Rc(ctx->opcode) != 0); \
2134 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
2136 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
2138 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
2141 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
2144 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
2147 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
2150 static void gen_frsqrtes(DisasContext
*ctx
)
2152 if (unlikely(!ctx
->fpu_enabled
)) {
2153 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2156 /* NIP cannot be restored if the memory exception comes from an helper */
2157 gen_update_nip(ctx
, ctx
->nip
- 4);
2158 gen_reset_fpstatus();
2159 gen_helper_frsqrte(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2160 cpu_fpr
[rB(ctx
->opcode
)]);
2161 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2162 cpu_fpr
[rD(ctx
->opcode
)]);
2163 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2167 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
2169 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
2173 static void gen_fsqrt(DisasContext
*ctx
)
2175 if (unlikely(!ctx
->fpu_enabled
)) {
2176 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2179 /* NIP cannot be restored if the memory exception comes from an helper */
2180 gen_update_nip(ctx
, ctx
->nip
- 4);
2181 gen_reset_fpstatus();
2182 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2183 cpu_fpr
[rB(ctx
->opcode
)]);
2184 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2187 static void gen_fsqrts(DisasContext
*ctx
)
2189 if (unlikely(!ctx
->fpu_enabled
)) {
2190 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2193 /* NIP cannot be restored if the memory exception comes from an helper */
2194 gen_update_nip(ctx
, ctx
->nip
- 4);
2195 gen_reset_fpstatus();
2196 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2197 cpu_fpr
[rB(ctx
->opcode
)]);
2198 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2199 cpu_fpr
[rD(ctx
->opcode
)]);
2200 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 1, Rc(ctx
->opcode
) != 0);
2203 /*** Floating-Point multiply-and-add ***/
2204 /* fmadd - fmadds */
2205 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
2206 /* fmsub - fmsubs */
2207 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
2208 /* fnmadd - fnmadds */
2209 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
2210 /* fnmsub - fnmsubs */
2211 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
2213 /*** Floating-Point round & convert ***/
2215 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
2217 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
2219 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
2220 #if defined(TARGET_PPC64)
2222 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
);
2224 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
);
2226 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
);
2230 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
2232 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
2234 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
2236 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
2238 /*** Floating-Point compare ***/
2241 static void gen_fcmpo(DisasContext
*ctx
)
2244 if (unlikely(!ctx
->fpu_enabled
)) {
2245 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2248 /* NIP cannot be restored if the memory exception comes from an helper */
2249 gen_update_nip(ctx
, ctx
->nip
- 4);
2250 gen_reset_fpstatus();
2251 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2252 gen_helper_fcmpo(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2253 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2254 tcg_temp_free_i32(crf
);
2255 gen_helper_float_check_status(cpu_env
);
2259 static void gen_fcmpu(DisasContext
*ctx
)
2262 if (unlikely(!ctx
->fpu_enabled
)) {
2263 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2266 /* NIP cannot be restored if the memory exception comes from an helper */
2267 gen_update_nip(ctx
, ctx
->nip
- 4);
2268 gen_reset_fpstatus();
2269 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2270 gen_helper_fcmpu(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2271 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2272 tcg_temp_free_i32(crf
);
2273 gen_helper_float_check_status(cpu_env
);
2276 /*** Floating-point move ***/
2278 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2279 GEN_FLOAT_B(abs
, 0x08, 0x08, 0, PPC_FLOAT
);
2282 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2283 static void gen_fmr(DisasContext
*ctx
)
2285 if (unlikely(!ctx
->fpu_enabled
)) {
2286 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2289 tcg_gen_mov_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2290 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2294 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2295 GEN_FLOAT_B(nabs
, 0x08, 0x04, 0, PPC_FLOAT
);
2297 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2298 GEN_FLOAT_B(neg
, 0x08, 0x01, 0, PPC_FLOAT
);
2300 /*** Floating-Point status & ctrl register ***/
2303 static void gen_mcrfs(DisasContext
*ctx
)
2307 if (unlikely(!ctx
->fpu_enabled
)) {
2308 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2311 bfa
= 4 * (7 - crfS(ctx
->opcode
));
2312 tcg_gen_shri_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_fpscr
, bfa
);
2313 tcg_gen_andi_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], 0xf);
2314 tcg_gen_andi_i32(cpu_fpscr
, cpu_fpscr
, ~(0xF << bfa
));
2318 static void gen_mffs(DisasContext
*ctx
)
2320 if (unlikely(!ctx
->fpu_enabled
)) {
2321 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2324 gen_reset_fpstatus();
2325 tcg_gen_extu_i32_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpscr
);
2326 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)], 0, Rc(ctx
->opcode
) != 0);
2330 static void gen_mtfsb0(DisasContext
*ctx
)
2334 if (unlikely(!ctx
->fpu_enabled
)) {
2335 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2338 crb
= 31 - crbD(ctx
->opcode
);
2339 gen_reset_fpstatus();
2340 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
)) {
2342 /* NIP cannot be restored if the memory exception comes from an helper */
2343 gen_update_nip(ctx
, ctx
->nip
- 4);
2344 t0
= tcg_const_i32(crb
);
2345 gen_helper_fpscr_clrbit(cpu_env
, t0
);
2346 tcg_temp_free_i32(t0
);
2348 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2349 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2354 static void gen_mtfsb1(DisasContext
*ctx
)
2358 if (unlikely(!ctx
->fpu_enabled
)) {
2359 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2362 crb
= 31 - crbD(ctx
->opcode
);
2363 gen_reset_fpstatus();
2364 /* XXX: we pretend we can only do IEEE floating-point computations */
2365 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
)) {
2367 /* NIP cannot be restored if the memory exception comes from an helper */
2368 gen_update_nip(ctx
, ctx
->nip
- 4);
2369 t0
= tcg_const_i32(crb
);
2370 gen_helper_fpscr_setbit(cpu_env
, t0
);
2371 tcg_temp_free_i32(t0
);
2373 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2374 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2376 /* We can raise a differed exception */
2377 gen_helper_float_check_status(cpu_env
);
2381 static void gen_mtfsf(DisasContext
*ctx
)
2384 int L
= ctx
->opcode
& 0x02000000;
2386 if (unlikely(!ctx
->fpu_enabled
)) {
2387 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2390 /* NIP cannot be restored if the memory exception comes from an helper */
2391 gen_update_nip(ctx
, ctx
->nip
- 4);
2392 gen_reset_fpstatus();
2394 t0
= tcg_const_i32(0xff);
2396 t0
= tcg_const_i32(FM(ctx
->opcode
));
2397 gen_helper_store_fpscr(cpu_env
, cpu_fpr
[rB(ctx
->opcode
)], t0
);
2398 tcg_temp_free_i32(t0
);
2399 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2400 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2402 /* We can raise a differed exception */
2403 gen_helper_float_check_status(cpu_env
);
2407 static void gen_mtfsfi(DisasContext
*ctx
)
2413 if (unlikely(!ctx
->fpu_enabled
)) {
2414 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2417 bf
= crbD(ctx
->opcode
) >> 2;
2419 /* NIP cannot be restored if the memory exception comes from an helper */
2420 gen_update_nip(ctx
, ctx
->nip
- 4);
2421 gen_reset_fpstatus();
2422 t0
= tcg_const_i64(FPIMM(ctx
->opcode
) << (4 * sh
));
2423 t1
= tcg_const_i32(1 << sh
);
2424 gen_helper_store_fpscr(cpu_env
, t0
, t1
);
2425 tcg_temp_free_i64(t0
);
2426 tcg_temp_free_i32(t1
);
2427 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2428 tcg_gen_shri_i32(cpu_crf
[1], cpu_fpscr
, FPSCR_OX
);
2430 /* We can raise a differed exception */
2431 gen_helper_float_check_status(cpu_env
);
2434 /*** Addressing modes ***/
2435 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2436 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2439 target_long simm
= SIMM(ctx
->opcode
);
2442 if (rA(ctx
->opcode
) == 0) {
2443 #if defined(TARGET_PPC64)
2444 if (!ctx
->sf_mode
) {
2445 tcg_gen_movi_tl(EA
, (uint32_t)simm
);
2448 tcg_gen_movi_tl(EA
, simm
);
2449 } else if (likely(simm
!= 0)) {
2450 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2451 #if defined(TARGET_PPC64)
2452 if (!ctx
->sf_mode
) {
2453 tcg_gen_ext32u_tl(EA
, EA
);
2457 #if defined(TARGET_PPC64)
2458 if (!ctx
->sf_mode
) {
2459 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2462 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2466 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2468 if (rA(ctx
->opcode
) == 0) {
2469 #if defined(TARGET_PPC64)
2470 if (!ctx
->sf_mode
) {
2471 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2474 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2476 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2477 #if defined(TARGET_PPC64)
2478 if (!ctx
->sf_mode
) {
2479 tcg_gen_ext32u_tl(EA
, EA
);
2485 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2487 if (rA(ctx
->opcode
) == 0) {
2488 tcg_gen_movi_tl(EA
, 0);
2490 #if defined(TARGET_PPC64)
2491 if (!ctx
->sf_mode
) {
2492 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2495 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2499 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2502 tcg_gen_addi_tl(ret
, arg1
, val
);
2503 #if defined(TARGET_PPC64)
2504 if (!ctx
->sf_mode
) {
2505 tcg_gen_ext32u_tl(ret
, ret
);
2510 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2512 int l1
= gen_new_label();
2513 TCGv t0
= tcg_temp_new();
2515 /* NIP cannot be restored if the memory exception comes from an helper */
2516 gen_update_nip(ctx
, ctx
->nip
- 4);
2517 tcg_gen_andi_tl(t0
, EA
, mask
);
2518 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2519 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2520 t2
= tcg_const_i32(0);
2521 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2522 tcg_temp_free_i32(t1
);
2523 tcg_temp_free_i32(t2
);
2528 /*** Integer load ***/
2529 static inline void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2531 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2534 static inline void gen_qemu_ld8s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2536 tcg_gen_qemu_ld8s(arg1
, arg2
, ctx
->mem_idx
);
2539 static inline void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2541 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2542 if (unlikely(ctx
->le_mode
)) {
2543 tcg_gen_bswap16_tl(arg1
, arg1
);
2547 static inline void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2549 if (unlikely(ctx
->le_mode
)) {
2550 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2551 tcg_gen_bswap16_tl(arg1
, arg1
);
2552 tcg_gen_ext16s_tl(arg1
, arg1
);
2554 tcg_gen_qemu_ld16s(arg1
, arg2
, ctx
->mem_idx
);
2558 static inline void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2560 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2561 if (unlikely(ctx
->le_mode
)) {
2562 tcg_gen_bswap32_tl(arg1
, arg1
);
2566 #if defined(TARGET_PPC64)
2567 static inline void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2569 if (unlikely(ctx
->le_mode
)) {
2570 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2571 tcg_gen_bswap32_tl(arg1
, arg1
);
2572 tcg_gen_ext32s_tl(arg1
, arg1
);
2574 tcg_gen_qemu_ld32s(arg1
, arg2
, ctx
->mem_idx
);
2578 static inline void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2580 tcg_gen_qemu_ld64(arg1
, arg2
, ctx
->mem_idx
);
2581 if (unlikely(ctx
->le_mode
)) {
2582 tcg_gen_bswap64_i64(arg1
, arg1
);
2586 static inline void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2588 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2591 static inline void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2593 if (unlikely(ctx
->le_mode
)) {
2594 TCGv t0
= tcg_temp_new();
2595 tcg_gen_ext16u_tl(t0
, arg1
);
2596 tcg_gen_bswap16_tl(t0
, t0
);
2597 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2600 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
2604 static inline void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2606 if (unlikely(ctx
->le_mode
)) {
2607 TCGv t0
= tcg_temp_new();
2608 tcg_gen_ext32u_tl(t0
, arg1
);
2609 tcg_gen_bswap32_tl(t0
, t0
);
2610 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
2613 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
2617 static inline void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2619 if (unlikely(ctx
->le_mode
)) {
2620 TCGv_i64 t0
= tcg_temp_new_i64();
2621 tcg_gen_bswap64_i64(t0
, arg1
);
2622 tcg_gen_qemu_st64(t0
, arg2
, ctx
->mem_idx
);
2623 tcg_temp_free_i64(t0
);
2625 tcg_gen_qemu_st64(arg1
, arg2
, ctx
->mem_idx
);
2628 #define GEN_LD(name, ldop, opc, type) \
2629 static void glue(gen_, name)(DisasContext *ctx) \
2632 gen_set_access_type(ctx, ACCESS_INT); \
2633 EA = tcg_temp_new(); \
2634 gen_addr_imm_index(ctx, EA, 0); \
2635 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2636 tcg_temp_free(EA); \
2639 #define GEN_LDU(name, ldop, opc, type) \
2640 static void glue(gen_, name##u)(DisasContext *ctx) \
2643 if (unlikely(rA(ctx->opcode) == 0 || \
2644 rA(ctx->opcode) == rD(ctx->opcode))) { \
2645 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2648 gen_set_access_type(ctx, ACCESS_INT); \
2649 EA = tcg_temp_new(); \
2650 if (type == PPC_64B) \
2651 gen_addr_imm_index(ctx, EA, 0x03); \
2653 gen_addr_imm_index(ctx, EA, 0); \
2654 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2655 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2656 tcg_temp_free(EA); \
2659 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2660 static void glue(gen_, name##ux)(DisasContext *ctx) \
2663 if (unlikely(rA(ctx->opcode) == 0 || \
2664 rA(ctx->opcode) == rD(ctx->opcode))) { \
2665 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2668 gen_set_access_type(ctx, ACCESS_INT); \
2669 EA = tcg_temp_new(); \
2670 gen_addr_reg_index(ctx, EA); \
2671 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2672 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2673 tcg_temp_free(EA); \
2676 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2677 static void glue(gen_, name##x)(DisasContext *ctx) \
2680 gen_set_access_type(ctx, ACCESS_INT); \
2681 EA = tcg_temp_new(); \
2682 gen_addr_reg_index(ctx, EA); \
2683 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2684 tcg_temp_free(EA); \
2686 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2687 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2689 #define GEN_LDS(name, ldop, op, type) \
2690 GEN_LD(name, ldop, op | 0x20, type); \
2691 GEN_LDU(name, ldop, op | 0x21, type); \
2692 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2693 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2695 /* lbz lbzu lbzux lbzx */
2696 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2697 /* lha lhau lhaux lhax */
2698 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2699 /* lhz lhzu lhzux lhzx */
2700 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2701 /* lwz lwzu lwzux lwzx */
2702 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2703 #if defined(TARGET_PPC64)
2705 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2707 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2709 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2711 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2713 static void gen_ld(DisasContext
*ctx
)
2716 if (Rc(ctx
->opcode
)) {
2717 if (unlikely(rA(ctx
->opcode
) == 0 ||
2718 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2719 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2723 gen_set_access_type(ctx
, ACCESS_INT
);
2724 EA
= tcg_temp_new();
2725 gen_addr_imm_index(ctx
, EA
, 0x03);
2726 if (ctx
->opcode
& 0x02) {
2727 /* lwa (lwau is undefined) */
2728 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2731 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2733 if (Rc(ctx
->opcode
))
2734 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2739 static void gen_lq(DisasContext
*ctx
)
2741 #if defined(CONFIG_USER_ONLY)
2742 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2747 /* Restore CPU state */
2748 if (unlikely(ctx
->mem_idx
== 0)) {
2749 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2752 ra
= rA(ctx
->opcode
);
2753 rd
= rD(ctx
->opcode
);
2754 if (unlikely((rd
& 1) || rd
== ra
)) {
2755 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2758 if (unlikely(ctx
->le_mode
)) {
2759 /* Little-endian mode is not handled */
2760 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2763 gen_set_access_type(ctx
, ACCESS_INT
);
2764 EA
= tcg_temp_new();
2765 gen_addr_imm_index(ctx
, EA
, 0x0F);
2766 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2767 gen_addr_add(ctx
, EA
, EA
, 8);
2768 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2774 /*** Integer store ***/
2775 #define GEN_ST(name, stop, opc, type) \
2776 static void glue(gen_, name)(DisasContext *ctx) \
2779 gen_set_access_type(ctx, ACCESS_INT); \
2780 EA = tcg_temp_new(); \
2781 gen_addr_imm_index(ctx, EA, 0); \
2782 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2783 tcg_temp_free(EA); \
2786 #define GEN_STU(name, stop, opc, type) \
2787 static void glue(gen_, stop##u)(DisasContext *ctx) \
2790 if (unlikely(rA(ctx->opcode) == 0)) { \
2791 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2794 gen_set_access_type(ctx, ACCESS_INT); \
2795 EA = tcg_temp_new(); \
2796 if (type == PPC_64B) \
2797 gen_addr_imm_index(ctx, EA, 0x03); \
2799 gen_addr_imm_index(ctx, EA, 0); \
2800 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2801 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2802 tcg_temp_free(EA); \
2805 #define GEN_STUX(name, stop, opc2, opc3, type) \
2806 static void glue(gen_, name##ux)(DisasContext *ctx) \
2809 if (unlikely(rA(ctx->opcode) == 0)) { \
2810 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2813 gen_set_access_type(ctx, ACCESS_INT); \
2814 EA = tcg_temp_new(); \
2815 gen_addr_reg_index(ctx, EA); \
2816 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2817 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2818 tcg_temp_free(EA); \
2821 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2822 static void glue(gen_, name##x)(DisasContext *ctx) \
2825 gen_set_access_type(ctx, ACCESS_INT); \
2826 EA = tcg_temp_new(); \
2827 gen_addr_reg_index(ctx, EA); \
2828 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2829 tcg_temp_free(EA); \
2831 #define GEN_STX(name, stop, opc2, opc3, type) \
2832 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2834 #define GEN_STS(name, stop, op, type) \
2835 GEN_ST(name, stop, op | 0x20, type); \
2836 GEN_STU(name, stop, op | 0x21, type); \
2837 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2838 GEN_STX(name, stop, 0x17, op | 0x00, type)
2840 /* stb stbu stbux stbx */
2841 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2842 /* sth sthu sthux sthx */
2843 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2844 /* stw stwu stwux stwx */
2845 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2846 #if defined(TARGET_PPC64)
2847 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
2848 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
2850 static void gen_std(DisasContext
*ctx
)
2855 rs
= rS(ctx
->opcode
);
2856 if ((ctx
->opcode
& 0x3) == 0x2) {
2857 #if defined(CONFIG_USER_ONLY)
2858 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2861 if (unlikely(ctx
->mem_idx
== 0)) {
2862 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2865 if (unlikely(rs
& 1)) {
2866 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2869 if (unlikely(ctx
->le_mode
)) {
2870 /* Little-endian mode is not handled */
2871 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2874 gen_set_access_type(ctx
, ACCESS_INT
);
2875 EA
= tcg_temp_new();
2876 gen_addr_imm_index(ctx
, EA
, 0x03);
2877 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2878 gen_addr_add(ctx
, EA
, EA
, 8);
2879 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
2884 if (Rc(ctx
->opcode
)) {
2885 if (unlikely(rA(ctx
->opcode
) == 0)) {
2886 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2890 gen_set_access_type(ctx
, ACCESS_INT
);
2891 EA
= tcg_temp_new();
2892 gen_addr_imm_index(ctx
, EA
, 0x03);
2893 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
2894 if (Rc(ctx
->opcode
))
2895 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2900 /*** Integer load and store with byte reverse ***/
2902 static inline void gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2904 tcg_gen_qemu_ld16u(arg1
, arg2
, ctx
->mem_idx
);
2905 if (likely(!ctx
->le_mode
)) {
2906 tcg_gen_bswap16_tl(arg1
, arg1
);
2909 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2912 static inline void gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2914 tcg_gen_qemu_ld32u(arg1
, arg2
, ctx
->mem_idx
);
2915 if (likely(!ctx
->le_mode
)) {
2916 tcg_gen_bswap32_tl(arg1
, arg1
);
2919 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2921 #if defined(TARGET_PPC64)
2923 static inline void gen_qemu_ld64ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2925 tcg_gen_qemu_ld64(arg1
, arg2
, ctx
->mem_idx
);
2926 if (likely(!ctx
->le_mode
)) {
2927 tcg_gen_bswap64_tl(arg1
, arg1
);
2930 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
);
2931 #endif /* TARGET_PPC64 */
2934 static inline void gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2936 if (likely(!ctx
->le_mode
)) {
2937 TCGv t0
= tcg_temp_new();
2938 tcg_gen_ext16u_tl(t0
, arg1
);
2939 tcg_gen_bswap16_tl(t0
, t0
);
2940 tcg_gen_qemu_st16(t0
, arg2
, ctx
->mem_idx
);
2943 tcg_gen_qemu_st16(arg1
, arg2
, ctx
->mem_idx
);
2946 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2949 static inline void gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2951 if (likely(!ctx
->le_mode
)) {
2952 TCGv t0
= tcg_temp_new();
2953 tcg_gen_ext32u_tl(t0
, arg1
);
2954 tcg_gen_bswap32_tl(t0
, t0
);
2955 tcg_gen_qemu_st32(t0
, arg2
, ctx
->mem_idx
);
2958 tcg_gen_qemu_st32(arg1
, arg2
, ctx
->mem_idx
);
2961 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
2963 #if defined(TARGET_PPC64)
2965 static inline void gen_qemu_st64r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2967 if (likely(!ctx
->le_mode
)) {
2968 TCGv t0
= tcg_temp_new();
2969 tcg_gen_bswap64_tl(t0
, arg1
);
2970 tcg_gen_qemu_st64(t0
, arg2
, ctx
->mem_idx
);
2973 tcg_gen_qemu_st64(arg1
, arg2
, ctx
->mem_idx
);
2976 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
);
2977 #endif /* TARGET_PPC64 */
2979 /*** Integer load and store multiple ***/
2982 static void gen_lmw(DisasContext
*ctx
)
2986 gen_set_access_type(ctx
, ACCESS_INT
);
2987 /* NIP cannot be restored if the memory exception comes from an helper */
2988 gen_update_nip(ctx
, ctx
->nip
- 4);
2989 t0
= tcg_temp_new();
2990 t1
= tcg_const_i32(rD(ctx
->opcode
));
2991 gen_addr_imm_index(ctx
, t0
, 0);
2992 gen_helper_lmw(t0
, t1
);
2994 tcg_temp_free_i32(t1
);
2998 static void gen_stmw(DisasContext
*ctx
)
3002 gen_set_access_type(ctx
, ACCESS_INT
);
3003 /* NIP cannot be restored if the memory exception comes from an helper */
3004 gen_update_nip(ctx
, ctx
->nip
- 4);
3005 t0
= tcg_temp_new();
3006 t1
= tcg_const_i32(rS(ctx
->opcode
));
3007 gen_addr_imm_index(ctx
, t0
, 0);
3008 gen_helper_stmw(t0
, t1
);
3010 tcg_temp_free_i32(t1
);
3013 /*** Integer load and store strings ***/
3016 /* PowerPC32 specification says we must generate an exception if
3017 * rA is in the range of registers to be loaded.
3018 * In an other hand, IBM says this is valid, but rA won't be loaded.
3019 * For now, I'll follow the spec...
3021 static void gen_lswi(DisasContext
*ctx
)
3025 int nb
= NB(ctx
->opcode
);
3026 int start
= rD(ctx
->opcode
);
3027 int ra
= rA(ctx
->opcode
);
3033 if (unlikely(((start
+ nr
) > 32 &&
3034 start
<= ra
&& (start
+ nr
- 32) > ra
) ||
3035 ((start
+ nr
) <= 32 && start
<= ra
&& (start
+ nr
) > ra
))) {
3036 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
3039 gen_set_access_type(ctx
, ACCESS_INT
);
3040 /* NIP cannot be restored if the memory exception comes from an helper */
3041 gen_update_nip(ctx
, ctx
->nip
- 4);
3042 t0
= tcg_temp_new();
3043 gen_addr_register(ctx
, t0
);
3044 t1
= tcg_const_i32(nb
);
3045 t2
= tcg_const_i32(start
);
3046 gen_helper_lsw(t0
, t1
, t2
);
3048 tcg_temp_free_i32(t1
);
3049 tcg_temp_free_i32(t2
);
3053 static void gen_lswx(DisasContext
*ctx
)
3056 TCGv_i32 t1
, t2
, t3
;
3057 gen_set_access_type(ctx
, ACCESS_INT
);
3058 /* NIP cannot be restored if the memory exception comes from an helper */
3059 gen_update_nip(ctx
, ctx
->nip
- 4);
3060 t0
= tcg_temp_new();
3061 gen_addr_reg_index(ctx
, t0
);
3062 t1
= tcg_const_i32(rD(ctx
->opcode
));
3063 t2
= tcg_const_i32(rA(ctx
->opcode
));
3064 t3
= tcg_const_i32(rB(ctx
->opcode
));
3065 gen_helper_lswx(t0
, t1
, t2
, t3
);
3067 tcg_temp_free_i32(t1
);
3068 tcg_temp_free_i32(t2
);
3069 tcg_temp_free_i32(t3
);
3073 static void gen_stswi(DisasContext
*ctx
)
3077 int nb
= NB(ctx
->opcode
);
3078 gen_set_access_type(ctx
, ACCESS_INT
);
3079 /* NIP cannot be restored if the memory exception comes from an helper */
3080 gen_update_nip(ctx
, ctx
->nip
- 4);
3081 t0
= tcg_temp_new();
3082 gen_addr_register(ctx
, t0
);
3085 t1
= tcg_const_i32(nb
);
3086 t2
= tcg_const_i32(rS(ctx
->opcode
));
3087 gen_helper_stsw(t0
, t1
, t2
);
3089 tcg_temp_free_i32(t1
);
3090 tcg_temp_free_i32(t2
);
3094 static void gen_stswx(DisasContext
*ctx
)
3098 gen_set_access_type(ctx
, ACCESS_INT
);
3099 /* NIP cannot be restored if the memory exception comes from an helper */
3100 gen_update_nip(ctx
, ctx
->nip
- 4);
3101 t0
= tcg_temp_new();
3102 gen_addr_reg_index(ctx
, t0
);
3103 t1
= tcg_temp_new_i32();
3104 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3105 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3106 t2
= tcg_const_i32(rS(ctx
->opcode
));
3107 gen_helper_stsw(t0
, t1
, t2
);
3109 tcg_temp_free_i32(t1
);
3110 tcg_temp_free_i32(t2
);
3113 /*** Memory synchronisation ***/
3115 static void gen_eieio(DisasContext
*ctx
)
3120 static void gen_isync(DisasContext
*ctx
)
3122 gen_stop_exception(ctx
);
3126 static void gen_lwarx(DisasContext
*ctx
)
3129 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3130 gen_set_access_type(ctx
, ACCESS_RES
);
3131 t0
= tcg_temp_local_new();
3132 gen_addr_reg_index(ctx
, t0
);
3133 gen_check_align(ctx
, t0
, 0x03);
3134 gen_qemu_ld32u(ctx
, gpr
, t0
);
3135 tcg_gen_mov_tl(cpu_reserve
, t0
);
3136 tcg_gen_st_tl(gpr
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3140 #if defined(CONFIG_USER_ONLY)
3141 static void gen_conditional_store (DisasContext
*ctx
, TCGv EA
,
3144 TCGv t0
= tcg_temp_new();
3145 uint32_t save_exception
= ctx
->exception
;
3147 tcg_gen_st_tl(EA
, cpu_env
, offsetof(CPUPPCState
, reserve_ea
));
3148 tcg_gen_movi_tl(t0
, (size
<< 5) | reg
);
3149 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, reserve_info
));
3151 gen_update_nip(ctx
, ctx
->nip
-4);
3152 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3153 gen_exception(ctx
, POWERPC_EXCP_STCX
);
3154 ctx
->exception
= save_exception
;
3159 static void gen_stwcx_(DisasContext
*ctx
)
3162 gen_set_access_type(ctx
, ACCESS_RES
);
3163 t0
= tcg_temp_local_new();
3164 gen_addr_reg_index(ctx
, t0
);
3165 gen_check_align(ctx
, t0
, 0x03);
3166 #if defined(CONFIG_USER_ONLY)
3167 gen_conditional_store(ctx
, t0
, rS(ctx
->opcode
), 4);
3172 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
3173 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
3174 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
3175 l1
= gen_new_label();
3176 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3177 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3178 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3180 tcg_gen_movi_tl(cpu_reserve
, -1);
3186 #if defined(TARGET_PPC64)
3188 static void gen_ldarx(DisasContext
*ctx
)
3191 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3192 gen_set_access_type(ctx
, ACCESS_RES
);
3193 t0
= tcg_temp_local_new();
3194 gen_addr_reg_index(ctx
, t0
);
3195 gen_check_align(ctx
, t0
, 0x07);
3196 gen_qemu_ld64(ctx
, gpr
, t0
);
3197 tcg_gen_mov_tl(cpu_reserve
, t0
);
3198 tcg_gen_st_tl(gpr
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3203 static void gen_stdcx_(DisasContext
*ctx
)
3206 gen_set_access_type(ctx
, ACCESS_RES
);
3207 t0
= tcg_temp_local_new();
3208 gen_addr_reg_index(ctx
, t0
);
3209 gen_check_align(ctx
, t0
, 0x07);
3210 #if defined(CONFIG_USER_ONLY)
3211 gen_conditional_store(ctx
, t0
, rS(ctx
->opcode
), 8);
3215 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
3216 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
3217 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
3218 l1
= gen_new_label();
3219 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3220 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3221 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
3223 tcg_gen_movi_tl(cpu_reserve
, -1);
3228 #endif /* defined(TARGET_PPC64) */
3231 static void gen_sync(DisasContext
*ctx
)
3236 static void gen_wait(DisasContext
*ctx
)
3238 TCGv_i32 t0
= tcg_temp_new_i32();
3239 tcg_gen_st_i32(t0
, cpu_env
, offsetof(CPUPPCState
, halted
));
3240 tcg_temp_free_i32(t0
);
3241 /* Stop translation, as the CPU is supposed to sleep from now */
3242 gen_exception_err(ctx
, EXCP_HLT
, 1);
3245 /*** Floating-point load ***/
3246 #define GEN_LDF(name, ldop, opc, type) \
3247 static void glue(gen_, name)(DisasContext *ctx) \
3250 if (unlikely(!ctx->fpu_enabled)) { \
3251 gen_exception(ctx, POWERPC_EXCP_FPU); \
3254 gen_set_access_type(ctx, ACCESS_FLOAT); \
3255 EA = tcg_temp_new(); \
3256 gen_addr_imm_index(ctx, EA, 0); \
3257 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3258 tcg_temp_free(EA); \
3261 #define GEN_LDUF(name, ldop, opc, type) \
3262 static void glue(gen_, name##u)(DisasContext *ctx) \
3265 if (unlikely(!ctx->fpu_enabled)) { \
3266 gen_exception(ctx, POWERPC_EXCP_FPU); \
3269 if (unlikely(rA(ctx->opcode) == 0)) { \
3270 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3273 gen_set_access_type(ctx, ACCESS_FLOAT); \
3274 EA = tcg_temp_new(); \
3275 gen_addr_imm_index(ctx, EA, 0); \
3276 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3277 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3278 tcg_temp_free(EA); \
3281 #define GEN_LDUXF(name, ldop, opc, type) \
3282 static void glue(gen_, name##ux)(DisasContext *ctx) \
3285 if (unlikely(!ctx->fpu_enabled)) { \
3286 gen_exception(ctx, POWERPC_EXCP_FPU); \
3289 if (unlikely(rA(ctx->opcode) == 0)) { \
3290 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3293 gen_set_access_type(ctx, ACCESS_FLOAT); \
3294 EA = tcg_temp_new(); \
3295 gen_addr_reg_index(ctx, EA); \
3296 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3297 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3298 tcg_temp_free(EA); \
3301 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3302 static void glue(gen_, name##x)(DisasContext *ctx) \
3305 if (unlikely(!ctx->fpu_enabled)) { \
3306 gen_exception(ctx, POWERPC_EXCP_FPU); \
3309 gen_set_access_type(ctx, ACCESS_FLOAT); \
3310 EA = tcg_temp_new(); \
3311 gen_addr_reg_index(ctx, EA); \
3312 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3313 tcg_temp_free(EA); \
3316 #define GEN_LDFS(name, ldop, op, type) \
3317 GEN_LDF(name, ldop, op | 0x20, type); \
3318 GEN_LDUF(name, ldop, op | 0x21, type); \
3319 GEN_LDUXF(name, ldop, op | 0x01, type); \
3320 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3322 static inline void gen_qemu_ld32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3324 TCGv t0
= tcg_temp_new();
3325 TCGv_i32 t1
= tcg_temp_new_i32();
3326 gen_qemu_ld32u(ctx
, t0
, arg2
);
3327 tcg_gen_trunc_tl_i32(t1
, t0
);
3329 gen_helper_float32_to_float64(arg1
, cpu_env
, t1
);
3330 tcg_temp_free_i32(t1
);
3333 /* lfd lfdu lfdux lfdx */
3334 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
);
3335 /* lfs lfsu lfsux lfsx */
3336 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
);
3338 /*** Floating-point store ***/
3339 #define GEN_STF(name, stop, opc, type) \
3340 static void glue(gen_, name)(DisasContext *ctx) \
3343 if (unlikely(!ctx->fpu_enabled)) { \
3344 gen_exception(ctx, POWERPC_EXCP_FPU); \
3347 gen_set_access_type(ctx, ACCESS_FLOAT); \
3348 EA = tcg_temp_new(); \
3349 gen_addr_imm_index(ctx, EA, 0); \
3350 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3351 tcg_temp_free(EA); \
3354 #define GEN_STUF(name, stop, opc, type) \
3355 static void glue(gen_, name##u)(DisasContext *ctx) \
3358 if (unlikely(!ctx->fpu_enabled)) { \
3359 gen_exception(ctx, POWERPC_EXCP_FPU); \
3362 if (unlikely(rA(ctx->opcode) == 0)) { \
3363 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3366 gen_set_access_type(ctx, ACCESS_FLOAT); \
3367 EA = tcg_temp_new(); \
3368 gen_addr_imm_index(ctx, EA, 0); \
3369 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3370 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3371 tcg_temp_free(EA); \
3374 #define GEN_STUXF(name, stop, opc, type) \
3375 static void glue(gen_, name##ux)(DisasContext *ctx) \
3378 if (unlikely(!ctx->fpu_enabled)) { \
3379 gen_exception(ctx, POWERPC_EXCP_FPU); \
3382 if (unlikely(rA(ctx->opcode) == 0)) { \
3383 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3386 gen_set_access_type(ctx, ACCESS_FLOAT); \
3387 EA = tcg_temp_new(); \
3388 gen_addr_reg_index(ctx, EA); \
3389 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3390 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3391 tcg_temp_free(EA); \
3394 #define GEN_STXF(name, stop, opc2, opc3, type) \
3395 static void glue(gen_, name##x)(DisasContext *ctx) \
3398 if (unlikely(!ctx->fpu_enabled)) { \
3399 gen_exception(ctx, POWERPC_EXCP_FPU); \
3402 gen_set_access_type(ctx, ACCESS_FLOAT); \
3403 EA = tcg_temp_new(); \
3404 gen_addr_reg_index(ctx, EA); \
3405 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3406 tcg_temp_free(EA); \
3409 #define GEN_STFS(name, stop, op, type) \
3410 GEN_STF(name, stop, op | 0x20, type); \
3411 GEN_STUF(name, stop, op | 0x21, type); \
3412 GEN_STUXF(name, stop, op | 0x01, type); \
3413 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3415 static inline void gen_qemu_st32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3417 TCGv_i32 t0
= tcg_temp_new_i32();
3418 TCGv t1
= tcg_temp_new();
3419 gen_helper_float64_to_float32(t0
, cpu_env
, arg1
);
3420 tcg_gen_extu_i32_tl(t1
, t0
);
3421 tcg_temp_free_i32(t0
);
3422 gen_qemu_st32(ctx
, t1
, arg2
);
3426 /* stfd stfdu stfdux stfdx */
3427 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
);
3428 /* stfs stfsu stfsux stfsx */
3429 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
);
3432 static inline void gen_qemu_st32fiw(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3434 TCGv t0
= tcg_temp_new();
3435 tcg_gen_trunc_i64_tl(t0
, arg1
),
3436 gen_qemu_st32(ctx
, t0
, arg2
);
3440 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
3442 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3444 #if defined(TARGET_PPC64)
3446 tcg_gen_movi_tl(cpu_cfar
, nip
);
3451 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3453 TranslationBlock
*tb
;
3455 #if defined(TARGET_PPC64)
3457 dest
= (uint32_t) dest
;
3459 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
3460 likely(!ctx
->singlestep_enabled
)) {
3462 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3463 tcg_gen_exit_tb((tcg_target_long
)tb
+ n
);
3465 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3466 if (unlikely(ctx
->singlestep_enabled
)) {
3467 if ((ctx
->singlestep_enabled
&
3468 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3469 ctx
->exception
== POWERPC_EXCP_BRANCH
) {
3470 target_ulong tmp
= ctx
->nip
;
3472 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3475 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3476 gen_debug_exception(ctx
);
3483 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3485 #if defined(TARGET_PPC64)
3486 if (ctx
->sf_mode
== 0)
3487 tcg_gen_movi_tl(cpu_lr
, (uint32_t)nip
);
3490 tcg_gen_movi_tl(cpu_lr
, nip
);
3494 static void gen_b(DisasContext
*ctx
)
3496 target_ulong li
, target
;
3498 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3499 /* sign extend LI */
3500 #if defined(TARGET_PPC64)
3502 li
= ((int64_t)LI(ctx
->opcode
) << 38) >> 38;
3505 li
= ((int32_t)LI(ctx
->opcode
) << 6) >> 6;
3506 if (likely(AA(ctx
->opcode
) == 0))
3507 target
= ctx
->nip
+ li
- 4;
3510 if (LK(ctx
->opcode
))
3511 gen_setlr(ctx
, ctx
->nip
);
3512 gen_update_cfar(ctx
, ctx
->nip
);
3513 gen_goto_tb(ctx
, 0, target
);
3520 static inline void gen_bcond(DisasContext
*ctx
, int type
)
3522 uint32_t bo
= BO(ctx
->opcode
);
3526 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3527 if (type
== BCOND_LR
|| type
== BCOND_CTR
) {
3528 target
= tcg_temp_local_new();
3529 if (type
== BCOND_CTR
)
3530 tcg_gen_mov_tl(target
, cpu_ctr
);
3532 tcg_gen_mov_tl(target
, cpu_lr
);
3534 TCGV_UNUSED(target
);
3536 if (LK(ctx
->opcode
))
3537 gen_setlr(ctx
, ctx
->nip
);
3538 l1
= gen_new_label();
3539 if ((bo
& 0x4) == 0) {
3540 /* Decrement and test CTR */
3541 TCGv temp
= tcg_temp_new();
3542 if (unlikely(type
== BCOND_CTR
)) {
3543 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3546 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3547 #if defined(TARGET_PPC64)
3549 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3552 tcg_gen_mov_tl(temp
, cpu_ctr
);
3554 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3556 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3558 tcg_temp_free(temp
);
3560 if ((bo
& 0x10) == 0) {
3562 uint32_t bi
= BI(ctx
->opcode
);
3563 uint32_t mask
= 1 << (3 - (bi
& 0x03));
3564 TCGv_i32 temp
= tcg_temp_new_i32();
3567 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3568 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3570 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3571 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3573 tcg_temp_free_i32(temp
);
3575 gen_update_cfar(ctx
, ctx
->nip
);
3576 if (type
== BCOND_IM
) {
3577 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3578 if (likely(AA(ctx
->opcode
) == 0)) {
3579 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
3581 gen_goto_tb(ctx
, 0, li
);
3584 gen_goto_tb(ctx
, 1, ctx
->nip
);
3586 #if defined(TARGET_PPC64)
3587 if (!(ctx
->sf_mode
))
3588 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3591 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3594 #if defined(TARGET_PPC64)
3595 if (!(ctx
->sf_mode
))
3596 tcg_gen_movi_tl(cpu_nip
, (uint32_t)ctx
->nip
);
3599 tcg_gen_movi_tl(cpu_nip
, ctx
->nip
);
3604 static void gen_bc(DisasContext
*ctx
)
3606 gen_bcond(ctx
, BCOND_IM
);
3609 static void gen_bcctr(DisasContext
*ctx
)
3611 gen_bcond(ctx
, BCOND_CTR
);
3614 static void gen_bclr(DisasContext
*ctx
)
3616 gen_bcond(ctx
, BCOND_LR
);
3619 /*** Condition register logical ***/
3620 #define GEN_CRLOGIC(name, tcg_op, opc) \
3621 static void glue(gen_, name)(DisasContext *ctx) \
3626 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3627 t0 = tcg_temp_new_i32(); \
3629 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3631 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3633 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3634 t1 = tcg_temp_new_i32(); \
3635 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3637 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3639 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3641 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3642 tcg_op(t0, t0, t1); \
3643 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3644 tcg_gen_andi_i32(t0, t0, bitmask); \
3645 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3646 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3647 tcg_temp_free_i32(t0); \
3648 tcg_temp_free_i32(t1); \
3652 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3654 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3656 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3658 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3660 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3662 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3664 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3666 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3669 static void gen_mcrf(DisasContext
*ctx
)
3671 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3674 /*** System linkage ***/
3676 /* rfi (mem_idx only) */
3677 static void gen_rfi(DisasContext
*ctx
)
3679 #if defined(CONFIG_USER_ONLY)
3680 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3682 /* Restore CPU state */
3683 if (unlikely(!ctx
->mem_idx
)) {
3684 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3687 gen_update_cfar(ctx
, ctx
->nip
);
3688 gen_helper_rfi(cpu_env
);
3689 gen_sync_exception(ctx
);
3693 #if defined(TARGET_PPC64)
3694 static void gen_rfid(DisasContext
*ctx
)
3696 #if defined(CONFIG_USER_ONLY)
3697 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3699 /* Restore CPU state */
3700 if (unlikely(!ctx
->mem_idx
)) {
3701 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3704 gen_update_cfar(ctx
, ctx
->nip
);
3705 gen_helper_rfid(cpu_env
);
3706 gen_sync_exception(ctx
);
3710 static void gen_hrfid(DisasContext
*ctx
)
3712 #if defined(CONFIG_USER_ONLY)
3713 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3715 /* Restore CPU state */
3716 if (unlikely(ctx
->mem_idx
<= 1)) {
3717 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3720 gen_helper_hrfid(cpu_env
);
3721 gen_sync_exception(ctx
);
3727 #if defined(CONFIG_USER_ONLY)
3728 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3730 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3732 static void gen_sc(DisasContext
*ctx
)
3736 lev
= (ctx
->opcode
>> 5) & 0x7F;
3737 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3743 static void gen_tw(DisasContext
*ctx
)
3745 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3746 /* Update the nip since this might generate a trap exception */
3747 gen_update_nip(ctx
, ctx
->nip
);
3748 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3750 tcg_temp_free_i32(t0
);
3754 static void gen_twi(DisasContext
*ctx
)
3756 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3757 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3758 /* Update the nip since this might generate a trap exception */
3759 gen_update_nip(ctx
, ctx
->nip
);
3760 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3762 tcg_temp_free_i32(t1
);
3765 #if defined(TARGET_PPC64)
3767 static void gen_td(DisasContext
*ctx
)
3769 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
3770 /* Update the nip since this might generate a trap exception */
3771 gen_update_nip(ctx
, ctx
->nip
);
3772 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
3774 tcg_temp_free_i32(t0
);
3778 static void gen_tdi(DisasContext
*ctx
)
3780 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
3781 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
3782 /* Update the nip since this might generate a trap exception */
3783 gen_update_nip(ctx
, ctx
->nip
);
3784 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
3786 tcg_temp_free_i32(t1
);
3790 /*** Processor control ***/
3793 static void gen_mcrxr(DisasContext
*ctx
)
3795 tcg_gen_trunc_tl_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_xer
);
3796 tcg_gen_shri_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], XER_CA
);
3797 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_SO
| 1 << XER_OV
| 1 << XER_CA
));
3801 static void gen_mfcr(DisasContext
*ctx
)
3805 if (likely(ctx
->opcode
& 0x00100000)) {
3806 crm
= CRM(ctx
->opcode
);
3807 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
3809 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
3810 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
3811 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
3814 TCGv_i32 t0
= tcg_temp_new_i32();
3815 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
3816 tcg_gen_shli_i32(t0
, t0
, 4);
3817 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
3818 tcg_gen_shli_i32(t0
, t0
, 4);
3819 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
3820 tcg_gen_shli_i32(t0
, t0
, 4);
3821 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
3822 tcg_gen_shli_i32(t0
, t0
, 4);
3823 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
3824 tcg_gen_shli_i32(t0
, t0
, 4);
3825 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
3826 tcg_gen_shli_i32(t0
, t0
, 4);
3827 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
3828 tcg_gen_shli_i32(t0
, t0
, 4);
3829 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
3830 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
3831 tcg_temp_free_i32(t0
);
3836 static void gen_mfmsr(DisasContext
*ctx
)
3838 #if defined(CONFIG_USER_ONLY)
3839 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3841 if (unlikely(!ctx
->mem_idx
)) {
3842 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3845 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
3849 static void spr_noaccess(void *opaque
, int gprn
, int sprn
)
3852 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
3853 printf("ERROR: try to access SPR %d !\n", sprn
);
3856 #define SPR_NOACCESS (&spr_noaccess)
3859 static inline void gen_op_mfspr(DisasContext
*ctx
)
3861 void (*read_cb
)(void *opaque
, int gprn
, int sprn
);
3862 uint32_t sprn
= SPR(ctx
->opcode
);
3864 #if !defined(CONFIG_USER_ONLY)
3865 if (ctx
->mem_idx
== 2)
3866 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
3867 else if (ctx
->mem_idx
)
3868 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
3871 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
3872 if (likely(read_cb
!= NULL
)) {
3873 if (likely(read_cb
!= SPR_NOACCESS
)) {
3874 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
3876 /* Privilege exception */
3877 /* This is a hack to avoid warnings when running Linux:
3878 * this OS breaks the PowerPC virtualisation model,
3879 * allowing userland application to read the PVR
3881 if (sprn
!= SPR_PVR
) {
3882 qemu_log("Trying to read privileged spr %d %03x at "
3883 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3884 printf("Trying to read privileged spr %d %03x at "
3885 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3887 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3891 qemu_log("Trying to read invalid spr %d %03x at "
3892 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
3893 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx
"\n",
3894 sprn
, sprn
, ctx
->nip
);
3895 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
3899 static void gen_mfspr(DisasContext
*ctx
)
3905 static void gen_mftb(DisasContext
*ctx
)
3911 static void gen_mtcrf(DisasContext
*ctx
)
3915 crm
= CRM(ctx
->opcode
);
3916 if (likely((ctx
->opcode
& 0x00100000))) {
3917 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
3918 TCGv_i32 temp
= tcg_temp_new_i32();
3920 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3921 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
3922 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
3923 tcg_temp_free_i32(temp
);
3926 TCGv_i32 temp
= tcg_temp_new_i32();
3927 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
3928 for (crn
= 0 ; crn
< 8 ; crn
++) {
3929 if (crm
& (1 << crn
)) {
3930 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
3931 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
3934 tcg_temp_free_i32(temp
);
3939 #if defined(TARGET_PPC64)
3940 static void gen_mtmsrd(DisasContext
*ctx
)
3942 #if defined(CONFIG_USER_ONLY)
3943 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3945 if (unlikely(!ctx
->mem_idx
)) {
3946 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3949 if (ctx
->opcode
& 0x00010000) {
3950 /* Special form that does not need any synchronisation */
3951 TCGv t0
= tcg_temp_new();
3952 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3953 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
3954 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3957 /* XXX: we need to update nip before the store
3958 * if we enter power saving mode, we will exit the loop
3959 * directly from ppc_store_msr
3961 gen_update_nip(ctx
, ctx
->nip
);
3962 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
3963 /* Must stop the translation as machine state (may have) changed */
3964 /* Note that mtmsr is not always defined as context-synchronizing */
3965 gen_stop_exception(ctx
);
3971 static void gen_mtmsr(DisasContext
*ctx
)
3973 #if defined(CONFIG_USER_ONLY)
3974 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3976 if (unlikely(!ctx
->mem_idx
)) {
3977 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
3980 if (ctx
->opcode
& 0x00010000) {
3981 /* Special form that does not need any synchronisation */
3982 TCGv t0
= tcg_temp_new();
3983 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
3984 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~((1 << MSR_RI
) | (1 << MSR_EE
)));
3985 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
3988 TCGv msr
= tcg_temp_new();
3990 /* XXX: we need to update nip before the store
3991 * if we enter power saving mode, we will exit the loop
3992 * directly from ppc_store_msr
3994 gen_update_nip(ctx
, ctx
->nip
);
3995 #if defined(TARGET_PPC64)
3996 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
3998 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4000 gen_helper_store_msr(cpu_env
, msr
);
4001 /* Must stop the translation as machine state (may have) changed */
4002 /* Note that mtmsr is not always defined as context-synchronizing */
4003 gen_stop_exception(ctx
);
4009 static void gen_mtspr(DisasContext
*ctx
)
4011 void (*write_cb
)(void *opaque
, int sprn
, int gprn
);
4012 uint32_t sprn
= SPR(ctx
->opcode
);
4014 #if !defined(CONFIG_USER_ONLY)
4015 if (ctx
->mem_idx
== 2)
4016 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4017 else if (ctx
->mem_idx
)
4018 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4021 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4022 if (likely(write_cb
!= NULL
)) {
4023 if (likely(write_cb
!= SPR_NOACCESS
)) {
4024 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4026 /* Privilege exception */
4027 qemu_log("Trying to write privileged spr %d %03x at "
4028 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
4029 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
4030 "\n", sprn
, sprn
, ctx
->nip
);
4031 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4035 qemu_log("Trying to write invalid spr %d %03x at "
4036 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
);
4037 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx
"\n",
4038 sprn
, sprn
, ctx
->nip
);
4039 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4043 /*** Cache management ***/
4046 static void gen_dcbf(DisasContext
*ctx
)
4048 /* XXX: specification says this is treated as a load by the MMU */
4050 gen_set_access_type(ctx
, ACCESS_CACHE
);
4051 t0
= tcg_temp_new();
4052 gen_addr_reg_index(ctx
, t0
);
4053 gen_qemu_ld8u(ctx
, t0
, t0
);
4057 /* dcbi (Supervisor only) */
4058 static void gen_dcbi(DisasContext
*ctx
)
4060 #if defined(CONFIG_USER_ONLY)
4061 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4064 if (unlikely(!ctx
->mem_idx
)) {
4065 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4068 EA
= tcg_temp_new();
4069 gen_set_access_type(ctx
, ACCESS_CACHE
);
4070 gen_addr_reg_index(ctx
, EA
);
4071 val
= tcg_temp_new();
4072 /* XXX: specification says this should be treated as a store by the MMU */
4073 gen_qemu_ld8u(ctx
, val
, EA
);
4074 gen_qemu_st8(ctx
, val
, EA
);
4081 static void gen_dcbst(DisasContext
*ctx
)
4083 /* XXX: specification say this is treated as a load by the MMU */
4085 gen_set_access_type(ctx
, ACCESS_CACHE
);
4086 t0
= tcg_temp_new();
4087 gen_addr_reg_index(ctx
, t0
);
4088 gen_qemu_ld8u(ctx
, t0
, t0
);
4093 static void gen_dcbt(DisasContext
*ctx
)
4095 /* interpreted as no-op */
4096 /* XXX: specification say this is treated as a load by the MMU
4097 * but does not generate any exception
4102 static void gen_dcbtst(DisasContext
*ctx
)
4104 /* interpreted as no-op */
4105 /* XXX: specification say this is treated as a load by the MMU
4106 * but does not generate any exception
4111 static void gen_dcbz(DisasContext
*ctx
)
4114 gen_set_access_type(ctx
, ACCESS_CACHE
);
4115 /* NIP cannot be restored if the memory exception comes from an helper */
4116 gen_update_nip(ctx
, ctx
->nip
- 4);
4117 t0
= tcg_temp_new();
4118 gen_addr_reg_index(ctx
, t0
);
4119 gen_helper_dcbz(t0
);
4123 static void gen_dcbz_970(DisasContext
*ctx
)
4126 gen_set_access_type(ctx
, ACCESS_CACHE
);
4127 /* NIP cannot be restored if the memory exception comes from an helper */
4128 gen_update_nip(ctx
, ctx
->nip
- 4);
4129 t0
= tcg_temp_new();
4130 gen_addr_reg_index(ctx
, t0
);
4131 if (ctx
->opcode
& 0x00200000)
4132 gen_helper_dcbz(t0
);
4134 gen_helper_dcbz_970(t0
);
4139 static void gen_dst(DisasContext
*ctx
)
4141 if (rA(ctx
->opcode
) == 0) {
4142 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4144 /* interpreted as no-op */
4149 static void gen_dstst(DisasContext
*ctx
)
4151 if (rA(ctx
->opcode
) == 0) {
4152 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4154 /* interpreted as no-op */
4160 static void gen_dss(DisasContext
*ctx
)
4162 /* interpreted as no-op */
4166 static void gen_icbi(DisasContext
*ctx
)
4169 gen_set_access_type(ctx
, ACCESS_CACHE
);
4170 /* NIP cannot be restored if the memory exception comes from an helper */
4171 gen_update_nip(ctx
, ctx
->nip
- 4);
4172 t0
= tcg_temp_new();
4173 gen_addr_reg_index(ctx
, t0
);
4174 gen_helper_icbi(t0
);
4180 static void gen_dcba(DisasContext
*ctx
)
4182 /* interpreted as no-op */
4183 /* XXX: specification say this is treated as a store by the MMU
4184 * but does not generate any exception
4188 /*** Segment register manipulation ***/
4189 /* Supervisor only: */
4192 static void gen_mfsr(DisasContext
*ctx
)
4194 #if defined(CONFIG_USER_ONLY)
4195 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4198 if (unlikely(!ctx
->mem_idx
)) {
4199 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4202 t0
= tcg_const_tl(SR(ctx
->opcode
));
4203 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4209 static void gen_mfsrin(DisasContext
*ctx
)
4211 #if defined(CONFIG_USER_ONLY)
4212 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4215 if (unlikely(!ctx
->mem_idx
)) {
4216 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4219 t0
= tcg_temp_new();
4220 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4221 tcg_gen_andi_tl(t0
, t0
, 0xF);
4222 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4228 static void gen_mtsr(DisasContext
*ctx
)
4230 #if defined(CONFIG_USER_ONLY)
4231 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4234 if (unlikely(!ctx
->mem_idx
)) {
4235 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4238 t0
= tcg_const_tl(SR(ctx
->opcode
));
4239 gen_helper_store_sr(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4245 static void gen_mtsrin(DisasContext
*ctx
)
4247 #if defined(CONFIG_USER_ONLY)
4248 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4251 if (unlikely(!ctx
->mem_idx
)) {
4252 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4255 t0
= tcg_temp_new();
4256 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4257 tcg_gen_andi_tl(t0
, t0
, 0xF);
4258 gen_helper_store_sr(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4263 #if defined(TARGET_PPC64)
4264 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4267 static void gen_mfsr_64b(DisasContext
*ctx
)
4269 #if defined(CONFIG_USER_ONLY)
4270 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4273 if (unlikely(!ctx
->mem_idx
)) {
4274 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4277 t0
= tcg_const_tl(SR(ctx
->opcode
));
4278 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4284 static void gen_mfsrin_64b(DisasContext
*ctx
)
4286 #if defined(CONFIG_USER_ONLY)
4287 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4290 if (unlikely(!ctx
->mem_idx
)) {
4291 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4294 t0
= tcg_temp_new();
4295 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4296 tcg_gen_andi_tl(t0
, t0
, 0xF);
4297 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4303 static void gen_mtsr_64b(DisasContext
*ctx
)
4305 #if defined(CONFIG_USER_ONLY)
4306 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4309 if (unlikely(!ctx
->mem_idx
)) {
4310 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4313 t0
= tcg_const_tl(SR(ctx
->opcode
));
4314 gen_helper_store_sr(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4320 static void gen_mtsrin_64b(DisasContext
*ctx
)
4322 #if defined(CONFIG_USER_ONLY)
4323 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4326 if (unlikely(!ctx
->mem_idx
)) {
4327 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4330 t0
= tcg_temp_new();
4331 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4332 tcg_gen_andi_tl(t0
, t0
, 0xF);
4333 gen_helper_store_sr(t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4339 static void gen_slbmte(DisasContext
*ctx
)
4341 #if defined(CONFIG_USER_ONLY)
4342 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4344 if (unlikely(!ctx
->mem_idx
)) {
4345 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4348 gen_helper_store_slb(cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
4352 static void gen_slbmfee(DisasContext
*ctx
)
4354 #if defined(CONFIG_USER_ONLY)
4355 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4357 if (unlikely(!ctx
->mem_idx
)) {
4358 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4361 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)],
4362 cpu_gpr
[rB(ctx
->opcode
)]);
4366 static void gen_slbmfev(DisasContext
*ctx
)
4368 #if defined(CONFIG_USER_ONLY)
4369 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4371 if (unlikely(!ctx
->mem_idx
)) {
4372 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4375 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)],
4376 cpu_gpr
[rB(ctx
->opcode
)]);
4379 #endif /* defined(TARGET_PPC64) */
4381 /*** Lookaside buffer management ***/
4382 /* Optional & mem_idx only: */
4385 static void gen_tlbia(DisasContext
*ctx
)
4387 #if defined(CONFIG_USER_ONLY)
4388 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4390 if (unlikely(!ctx
->mem_idx
)) {
4391 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4399 static void gen_tlbiel(DisasContext
*ctx
)
4401 #if defined(CONFIG_USER_ONLY)
4402 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4404 if (unlikely(!ctx
->mem_idx
)) {
4405 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4408 gen_helper_tlbie(cpu_gpr
[rB(ctx
->opcode
)]);
4413 static void gen_tlbie(DisasContext
*ctx
)
4415 #if defined(CONFIG_USER_ONLY)
4416 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4418 if (unlikely(!ctx
->mem_idx
)) {
4419 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4422 #if defined(TARGET_PPC64)
4423 if (!ctx
->sf_mode
) {
4424 TCGv t0
= tcg_temp_new();
4425 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4426 gen_helper_tlbie(t0
);
4430 gen_helper_tlbie(cpu_gpr
[rB(ctx
->opcode
)]);
4435 static void gen_tlbsync(DisasContext
*ctx
)
4437 #if defined(CONFIG_USER_ONLY)
4438 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4440 if (unlikely(!ctx
->mem_idx
)) {
4441 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4444 /* This has no effect: it should ensure that all previous
4445 * tlbie have completed
4447 gen_stop_exception(ctx
);
4451 #if defined(TARGET_PPC64)
4453 static void gen_slbia(DisasContext
*ctx
)
4455 #if defined(CONFIG_USER_ONLY)
4456 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4458 if (unlikely(!ctx
->mem_idx
)) {
4459 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4467 static void gen_slbie(DisasContext
*ctx
)
4469 #if defined(CONFIG_USER_ONLY)
4470 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4472 if (unlikely(!ctx
->mem_idx
)) {
4473 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4476 gen_helper_slbie(cpu_gpr
[rB(ctx
->opcode
)]);
4481 /*** External control ***/
4485 static void gen_eciwx(DisasContext
*ctx
)
4488 /* Should check EAR[E] ! */
4489 gen_set_access_type(ctx
, ACCESS_EXT
);
4490 t0
= tcg_temp_new();
4491 gen_addr_reg_index(ctx
, t0
);
4492 gen_check_align(ctx
, t0
, 0x03);
4493 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4498 static void gen_ecowx(DisasContext
*ctx
)
4501 /* Should check EAR[E] ! */
4502 gen_set_access_type(ctx
, ACCESS_EXT
);
4503 t0
= tcg_temp_new();
4504 gen_addr_reg_index(ctx
, t0
);
4505 gen_check_align(ctx
, t0
, 0x03);
4506 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
4510 /* PowerPC 601 specific instructions */
4513 static void gen_abs(DisasContext
*ctx
)
4515 int l1
= gen_new_label();
4516 int l2
= gen_new_label();
4517 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4518 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4521 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4523 if (unlikely(Rc(ctx
->opcode
) != 0))
4524 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4528 static void gen_abso(DisasContext
*ctx
)
4530 int l1
= gen_new_label();
4531 int l2
= gen_new_label();
4532 int l3
= gen_new_label();
4533 /* Start with XER OV disabled, the most likely case */
4534 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4535 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
4536 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
4537 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4540 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4543 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4545 if (unlikely(Rc(ctx
->opcode
) != 0))
4546 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4550 static void gen_clcs(DisasContext
*ctx
)
4552 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
4553 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4554 tcg_temp_free_i32(t0
);
4555 /* Rc=1 sets CR0 to an undefined state */
4559 static void gen_div(DisasContext
*ctx
)
4561 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4562 cpu_gpr
[rB(ctx
->opcode
)]);
4563 if (unlikely(Rc(ctx
->opcode
) != 0))
4564 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4568 static void gen_divo(DisasContext
*ctx
)
4570 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4571 cpu_gpr
[rB(ctx
->opcode
)]);
4572 if (unlikely(Rc(ctx
->opcode
) != 0))
4573 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4577 static void gen_divs(DisasContext
*ctx
)
4579 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
4580 cpu_gpr
[rB(ctx
->opcode
)]);
4581 if (unlikely(Rc(ctx
->opcode
) != 0))
4582 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4585 /* divso - divso. */
4586 static void gen_divso(DisasContext
*ctx
)
4588 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
4589 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4590 if (unlikely(Rc(ctx
->opcode
) != 0))
4591 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4595 static void gen_doz(DisasContext
*ctx
)
4597 int l1
= gen_new_label();
4598 int l2
= gen_new_label();
4599 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4600 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4603 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4605 if (unlikely(Rc(ctx
->opcode
) != 0))
4606 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4610 static void gen_dozo(DisasContext
*ctx
)
4612 int l1
= gen_new_label();
4613 int l2
= gen_new_label();
4614 TCGv t0
= tcg_temp_new();
4615 TCGv t1
= tcg_temp_new();
4616 TCGv t2
= tcg_temp_new();
4617 /* Start with XER OV disabled, the most likely case */
4618 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4619 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
4620 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4621 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4622 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
4623 tcg_gen_andc_tl(t1
, t1
, t2
);
4624 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4625 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
4626 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4629 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4634 if (unlikely(Rc(ctx
->opcode
) != 0))
4635 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4639 static void gen_dozi(DisasContext
*ctx
)
4641 target_long simm
= SIMM(ctx
->opcode
);
4642 int l1
= gen_new_label();
4643 int l2
= gen_new_label();
4644 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
4645 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
4648 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
4650 if (unlikely(Rc(ctx
->opcode
) != 0))
4651 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4654 /* lscbx - lscbx. */
4655 static void gen_lscbx(DisasContext
*ctx
)
4657 TCGv t0
= tcg_temp_new();
4658 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
4659 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
4660 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
4662 gen_addr_reg_index(ctx
, t0
);
4663 /* NIP cannot be restored if the memory exception comes from an helper */
4664 gen_update_nip(ctx
, ctx
->nip
- 4);
4665 gen_helper_lscbx(t0
, t0
, t1
, t2
, t3
);
4666 tcg_temp_free_i32(t1
);
4667 tcg_temp_free_i32(t2
);
4668 tcg_temp_free_i32(t3
);
4669 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
4670 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
4671 if (unlikely(Rc(ctx
->opcode
) != 0))
4672 gen_set_Rc0(ctx
, t0
);
4676 /* maskg - maskg. */
4677 static void gen_maskg(DisasContext
*ctx
)
4679 int l1
= gen_new_label();
4680 TCGv t0
= tcg_temp_new();
4681 TCGv t1
= tcg_temp_new();
4682 TCGv t2
= tcg_temp_new();
4683 TCGv t3
= tcg_temp_new();
4684 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
4685 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4686 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
4687 tcg_gen_addi_tl(t2
, t0
, 1);
4688 tcg_gen_shr_tl(t2
, t3
, t2
);
4689 tcg_gen_shr_tl(t3
, t3
, t1
);
4690 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
4691 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
4692 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4698 if (unlikely(Rc(ctx
->opcode
) != 0))
4699 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4702 /* maskir - maskir. */
4703 static void gen_maskir(DisasContext
*ctx
)
4705 TCGv t0
= tcg_temp_new();
4706 TCGv t1
= tcg_temp_new();
4707 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4708 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
4709 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4712 if (unlikely(Rc(ctx
->opcode
) != 0))
4713 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4717 static void gen_mul(DisasContext
*ctx
)
4719 TCGv_i64 t0
= tcg_temp_new_i64();
4720 TCGv_i64 t1
= tcg_temp_new_i64();
4721 TCGv t2
= tcg_temp_new();
4722 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4723 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4724 tcg_gen_mul_i64(t0
, t0
, t1
);
4725 tcg_gen_trunc_i64_tl(t2
, t0
);
4726 gen_store_spr(SPR_MQ
, t2
);
4727 tcg_gen_shri_i64(t1
, t0
, 32);
4728 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4729 tcg_temp_free_i64(t0
);
4730 tcg_temp_free_i64(t1
);
4732 if (unlikely(Rc(ctx
->opcode
) != 0))
4733 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4737 static void gen_mulo(DisasContext
*ctx
)
4739 int l1
= gen_new_label();
4740 TCGv_i64 t0
= tcg_temp_new_i64();
4741 TCGv_i64 t1
= tcg_temp_new_i64();
4742 TCGv t2
= tcg_temp_new();
4743 /* Start with XER OV disabled, the most likely case */
4744 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4745 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
4746 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
4747 tcg_gen_mul_i64(t0
, t0
, t1
);
4748 tcg_gen_trunc_i64_tl(t2
, t0
);
4749 gen_store_spr(SPR_MQ
, t2
);
4750 tcg_gen_shri_i64(t1
, t0
, 32);
4751 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
4752 tcg_gen_ext32s_i64(t1
, t0
);
4753 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
4754 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
4756 tcg_temp_free_i64(t0
);
4757 tcg_temp_free_i64(t1
);
4759 if (unlikely(Rc(ctx
->opcode
) != 0))
4760 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4764 static void gen_nabs(DisasContext
*ctx
)
4766 int l1
= gen_new_label();
4767 int l2
= gen_new_label();
4768 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4769 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4772 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4774 if (unlikely(Rc(ctx
->opcode
) != 0))
4775 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4778 /* nabso - nabso. */
4779 static void gen_nabso(DisasContext
*ctx
)
4781 int l1
= gen_new_label();
4782 int l2
= gen_new_label();
4783 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
4784 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4787 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
4789 /* nabs never overflows */
4790 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
4791 if (unlikely(Rc(ctx
->opcode
) != 0))
4792 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
4796 static void gen_rlmi(DisasContext
*ctx
)
4798 uint32_t mb
= MB(ctx
->opcode
);
4799 uint32_t me
= ME(ctx
->opcode
);
4800 TCGv t0
= tcg_temp_new();
4801 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4802 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4803 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
4804 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
4805 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
4807 if (unlikely(Rc(ctx
->opcode
) != 0))
4808 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4812 static void gen_rrib(DisasContext
*ctx
)
4814 TCGv t0
= tcg_temp_new();
4815 TCGv t1
= tcg_temp_new();
4816 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4817 tcg_gen_movi_tl(t1
, 0x80000000);
4818 tcg_gen_shr_tl(t1
, t1
, t0
);
4819 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4820 tcg_gen_and_tl(t0
, t0
, t1
);
4821 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
4822 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4825 if (unlikely(Rc(ctx
->opcode
) != 0))
4826 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4830 static void gen_sle(DisasContext
*ctx
)
4832 TCGv t0
= tcg_temp_new();
4833 TCGv t1
= tcg_temp_new();
4834 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4835 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4836 tcg_gen_subfi_tl(t1
, 32, t1
);
4837 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4838 tcg_gen_or_tl(t1
, t0
, t1
);
4839 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4840 gen_store_spr(SPR_MQ
, t1
);
4843 if (unlikely(Rc(ctx
->opcode
) != 0))
4844 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4848 static void gen_sleq(DisasContext
*ctx
)
4850 TCGv t0
= tcg_temp_new();
4851 TCGv t1
= tcg_temp_new();
4852 TCGv t2
= tcg_temp_new();
4853 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4854 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
4855 tcg_gen_shl_tl(t2
, t2
, t0
);
4856 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
4857 gen_load_spr(t1
, SPR_MQ
);
4858 gen_store_spr(SPR_MQ
, t0
);
4859 tcg_gen_and_tl(t0
, t0
, t2
);
4860 tcg_gen_andc_tl(t1
, t1
, t2
);
4861 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4865 if (unlikely(Rc(ctx
->opcode
) != 0))
4866 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4870 static void gen_sliq(DisasContext
*ctx
)
4872 int sh
= SH(ctx
->opcode
);
4873 TCGv t0
= tcg_temp_new();
4874 TCGv t1
= tcg_temp_new();
4875 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4876 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4877 tcg_gen_or_tl(t1
, t0
, t1
);
4878 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4879 gen_store_spr(SPR_MQ
, t1
);
4882 if (unlikely(Rc(ctx
->opcode
) != 0))
4883 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4886 /* slliq - slliq. */
4887 static void gen_slliq(DisasContext
*ctx
)
4889 int sh
= SH(ctx
->opcode
);
4890 TCGv t0
= tcg_temp_new();
4891 TCGv t1
= tcg_temp_new();
4892 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4893 gen_load_spr(t1
, SPR_MQ
);
4894 gen_store_spr(SPR_MQ
, t0
);
4895 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
4896 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
4897 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4900 if (unlikely(Rc(ctx
->opcode
) != 0))
4901 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4905 static void gen_sllq(DisasContext
*ctx
)
4907 int l1
= gen_new_label();
4908 int l2
= gen_new_label();
4909 TCGv t0
= tcg_temp_local_new();
4910 TCGv t1
= tcg_temp_local_new();
4911 TCGv t2
= tcg_temp_local_new();
4912 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4913 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
4914 tcg_gen_shl_tl(t1
, t1
, t2
);
4915 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4916 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
4917 gen_load_spr(t0
, SPR_MQ
);
4918 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4921 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4922 gen_load_spr(t2
, SPR_MQ
);
4923 tcg_gen_andc_tl(t1
, t2
, t1
);
4924 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4929 if (unlikely(Rc(ctx
->opcode
) != 0))
4930 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4934 static void gen_slq(DisasContext
*ctx
)
4936 int l1
= gen_new_label();
4937 TCGv t0
= tcg_temp_new();
4938 TCGv t1
= tcg_temp_new();
4939 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4940 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4941 tcg_gen_subfi_tl(t1
, 32, t1
);
4942 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
4943 tcg_gen_or_tl(t1
, t0
, t1
);
4944 gen_store_spr(SPR_MQ
, t1
);
4945 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4946 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
4947 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4948 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
4952 if (unlikely(Rc(ctx
->opcode
) != 0))
4953 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4956 /* sraiq - sraiq. */
4957 static void gen_sraiq(DisasContext
*ctx
)
4959 int sh
= SH(ctx
->opcode
);
4960 int l1
= gen_new_label();
4961 TCGv t0
= tcg_temp_new();
4962 TCGv t1
= tcg_temp_new();
4963 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
4964 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
4965 tcg_gen_or_tl(t0
, t0
, t1
);
4966 gen_store_spr(SPR_MQ
, t0
);
4967 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
4968 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
4969 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
4970 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_CA
));
4972 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
4975 if (unlikely(Rc(ctx
->opcode
) != 0))
4976 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
4980 static void gen_sraq(DisasContext
*ctx
)
4982 int l1
= gen_new_label();
4983 int l2
= gen_new_label();
4984 TCGv t0
= tcg_temp_new();
4985 TCGv t1
= tcg_temp_local_new();
4986 TCGv t2
= tcg_temp_local_new();
4987 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
4988 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4989 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4990 tcg_gen_subfi_tl(t2
, 32, t2
);
4991 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
4992 tcg_gen_or_tl(t0
, t0
, t2
);
4993 gen_store_spr(SPR_MQ
, t0
);
4994 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
4995 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
4996 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
4997 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5000 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5001 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_CA
));
5002 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5003 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5004 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_CA
));
5008 if (unlikely(Rc(ctx
->opcode
) != 0))
5009 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5013 static void gen_sre(DisasContext
*ctx
)
5015 TCGv t0
= tcg_temp_new();
5016 TCGv t1
= tcg_temp_new();
5017 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5018 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5019 tcg_gen_subfi_tl(t1
, 32, t1
);
5020 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5021 tcg_gen_or_tl(t1
, t0
, t1
);
5022 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5023 gen_store_spr(SPR_MQ
, t1
);
5026 if (unlikely(Rc(ctx
->opcode
) != 0))
5027 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5031 static void gen_srea(DisasContext
*ctx
)
5033 TCGv t0
= tcg_temp_new();
5034 TCGv t1
= tcg_temp_new();
5035 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5036 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5037 gen_store_spr(SPR_MQ
, t0
);
5038 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5041 if (unlikely(Rc(ctx
->opcode
) != 0))
5042 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5046 static void gen_sreq(DisasContext
*ctx
)
5048 TCGv t0
= tcg_temp_new();
5049 TCGv t1
= tcg_temp_new();
5050 TCGv t2
= tcg_temp_new();
5051 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5052 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5053 tcg_gen_shr_tl(t1
, t1
, t0
);
5054 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5055 gen_load_spr(t2
, SPR_MQ
);
5056 gen_store_spr(SPR_MQ
, t0
);
5057 tcg_gen_and_tl(t0
, t0
, t1
);
5058 tcg_gen_andc_tl(t2
, t2
, t1
);
5059 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5063 if (unlikely(Rc(ctx
->opcode
) != 0))
5064 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5068 static void gen_sriq(DisasContext
*ctx
)
5070 int sh
= SH(ctx
->opcode
);
5071 TCGv t0
= tcg_temp_new();
5072 TCGv t1
= tcg_temp_new();
5073 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5074 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5075 tcg_gen_or_tl(t1
, t0
, t1
);
5076 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5077 gen_store_spr(SPR_MQ
, t1
);
5080 if (unlikely(Rc(ctx
->opcode
) != 0))
5081 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5085 static void gen_srliq(DisasContext
*ctx
)
5087 int sh
= SH(ctx
->opcode
);
5088 TCGv t0
= tcg_temp_new();
5089 TCGv t1
= tcg_temp_new();
5090 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5091 gen_load_spr(t1
, SPR_MQ
);
5092 gen_store_spr(SPR_MQ
, t0
);
5093 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5094 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5095 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5098 if (unlikely(Rc(ctx
->opcode
) != 0))
5099 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5103 static void gen_srlq(DisasContext
*ctx
)
5105 int l1
= gen_new_label();
5106 int l2
= gen_new_label();
5107 TCGv t0
= tcg_temp_local_new();
5108 TCGv t1
= tcg_temp_local_new();
5109 TCGv t2
= tcg_temp_local_new();
5110 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5111 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5112 tcg_gen_shr_tl(t2
, t1
, t2
);
5113 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5114 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5115 gen_load_spr(t0
, SPR_MQ
);
5116 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5119 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5120 tcg_gen_and_tl(t0
, t0
, t2
);
5121 gen_load_spr(t1
, SPR_MQ
);
5122 tcg_gen_andc_tl(t1
, t1
, t2
);
5123 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5128 if (unlikely(Rc(ctx
->opcode
) != 0))
5129 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5133 static void gen_srq(DisasContext
*ctx
)
5135 int l1
= gen_new_label();
5136 TCGv t0
= tcg_temp_new();
5137 TCGv t1
= tcg_temp_new();
5138 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5139 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5140 tcg_gen_subfi_tl(t1
, 32, t1
);
5141 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5142 tcg_gen_or_tl(t1
, t0
, t1
);
5143 gen_store_spr(SPR_MQ
, t1
);
5144 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5145 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5146 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5147 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5151 if (unlikely(Rc(ctx
->opcode
) != 0))
5152 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5155 /* PowerPC 602 specific instructions */
5158 static void gen_dsa(DisasContext
*ctx
)
5161 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5165 static void gen_esa(DisasContext
*ctx
)
5168 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5172 static void gen_mfrom(DisasContext
*ctx
)
5174 #if defined(CONFIG_USER_ONLY)
5175 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5177 if (unlikely(!ctx
->mem_idx
)) {
5178 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5181 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5185 /* 602 - 603 - G2 TLB management */
5188 static void gen_tlbld_6xx(DisasContext
*ctx
)
5190 #if defined(CONFIG_USER_ONLY)
5191 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5193 if (unlikely(!ctx
->mem_idx
)) {
5194 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5197 gen_helper_6xx_tlbd(cpu_gpr
[rB(ctx
->opcode
)]);
5202 static void gen_tlbli_6xx(DisasContext
*ctx
)
5204 #if defined(CONFIG_USER_ONLY)
5205 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5207 if (unlikely(!ctx
->mem_idx
)) {
5208 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5211 gen_helper_6xx_tlbi(cpu_gpr
[rB(ctx
->opcode
)]);
5215 /* 74xx TLB management */
5218 static void gen_tlbld_74xx(DisasContext
*ctx
)
5220 #if defined(CONFIG_USER_ONLY)
5221 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5223 if (unlikely(!ctx
->mem_idx
)) {
5224 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5227 gen_helper_74xx_tlbd(cpu_gpr
[rB(ctx
->opcode
)]);
5232 static void gen_tlbli_74xx(DisasContext
*ctx
)
5234 #if defined(CONFIG_USER_ONLY)
5235 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5237 if (unlikely(!ctx
->mem_idx
)) {
5238 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5241 gen_helper_74xx_tlbi(cpu_gpr
[rB(ctx
->opcode
)]);
5245 /* POWER instructions not in PowerPC 601 */
5248 static void gen_clf(DisasContext
*ctx
)
5250 /* Cache line flush: implemented as no-op */
5254 static void gen_cli(DisasContext
*ctx
)
5256 /* Cache line invalidate: privileged and treated as no-op */
5257 #if defined(CONFIG_USER_ONLY)
5258 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5260 if (unlikely(!ctx
->mem_idx
)) {
5261 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5268 static void gen_dclst(DisasContext
*ctx
)
5270 /* Data cache line store: treated as no-op */
5273 static void gen_mfsri(DisasContext
*ctx
)
5275 #if defined(CONFIG_USER_ONLY)
5276 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5278 int ra
= rA(ctx
->opcode
);
5279 int rd
= rD(ctx
->opcode
);
5281 if (unlikely(!ctx
->mem_idx
)) {
5282 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5285 t0
= tcg_temp_new();
5286 gen_addr_reg_index(ctx
, t0
);
5287 tcg_gen_shri_tl(t0
, t0
, 28);
5288 tcg_gen_andi_tl(t0
, t0
, 0xF);
5289 gen_helper_load_sr(cpu_gpr
[rd
], t0
);
5291 if (ra
!= 0 && ra
!= rd
)
5292 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5296 static void gen_rac(DisasContext
*ctx
)
5298 #if defined(CONFIG_USER_ONLY)
5299 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5302 if (unlikely(!ctx
->mem_idx
)) {
5303 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5306 t0
= tcg_temp_new();
5307 gen_addr_reg_index(ctx
, t0
);
5308 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5313 static void gen_rfsvc(DisasContext
*ctx
)
5315 #if defined(CONFIG_USER_ONLY)
5316 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5318 if (unlikely(!ctx
->mem_idx
)) {
5319 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5322 gen_helper_rfsvc(cpu_env
);
5323 gen_sync_exception(ctx
);
5327 /* svc is not implemented for now */
5329 /* POWER2 specific instructions */
5330 /* Quad manipulation (load/store two floats at a time) */
5333 static void gen_lfq(DisasContext
*ctx
)
5335 int rd
= rD(ctx
->opcode
);
5337 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5338 t0
= tcg_temp_new();
5339 gen_addr_imm_index(ctx
, t0
, 0);
5340 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5341 gen_addr_add(ctx
, t0
, t0
, 8);
5342 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5347 static void gen_lfqu(DisasContext
*ctx
)
5349 int ra
= rA(ctx
->opcode
);
5350 int rd
= rD(ctx
->opcode
);
5352 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5353 t0
= tcg_temp_new();
5354 t1
= tcg_temp_new();
5355 gen_addr_imm_index(ctx
, t0
, 0);
5356 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5357 gen_addr_add(ctx
, t1
, t0
, 8);
5358 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5360 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5366 static void gen_lfqux(DisasContext
*ctx
)
5368 int ra
= rA(ctx
->opcode
);
5369 int rd
= rD(ctx
->opcode
);
5370 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5372 t0
= tcg_temp_new();
5373 gen_addr_reg_index(ctx
, t0
);
5374 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5375 t1
= tcg_temp_new();
5376 gen_addr_add(ctx
, t1
, t0
, 8);
5377 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5380 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5385 static void gen_lfqx(DisasContext
*ctx
)
5387 int rd
= rD(ctx
->opcode
);
5389 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5390 t0
= tcg_temp_new();
5391 gen_addr_reg_index(ctx
, t0
);
5392 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5393 gen_addr_add(ctx
, t0
, t0
, 8);
5394 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5399 static void gen_stfq(DisasContext
*ctx
)
5401 int rd
= rD(ctx
->opcode
);
5403 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5404 t0
= tcg_temp_new();
5405 gen_addr_imm_index(ctx
, t0
, 0);
5406 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5407 gen_addr_add(ctx
, t0
, t0
, 8);
5408 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5413 static void gen_stfqu(DisasContext
*ctx
)
5415 int ra
= rA(ctx
->opcode
);
5416 int rd
= rD(ctx
->opcode
);
5418 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5419 t0
= tcg_temp_new();
5420 gen_addr_imm_index(ctx
, t0
, 0);
5421 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5422 t1
= tcg_temp_new();
5423 gen_addr_add(ctx
, t1
, t0
, 8);
5424 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5427 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5432 static void gen_stfqux(DisasContext
*ctx
)
5434 int ra
= rA(ctx
->opcode
);
5435 int rd
= rD(ctx
->opcode
);
5437 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5438 t0
= tcg_temp_new();
5439 gen_addr_reg_index(ctx
, t0
);
5440 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5441 t1
= tcg_temp_new();
5442 gen_addr_add(ctx
, t1
, t0
, 8);
5443 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5446 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5451 static void gen_stfqx(DisasContext
*ctx
)
5453 int rd
= rD(ctx
->opcode
);
5455 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5456 t0
= tcg_temp_new();
5457 gen_addr_reg_index(ctx
, t0
);
5458 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5459 gen_addr_add(ctx
, t0
, t0
, 8);
5460 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5464 /* BookE specific instructions */
5466 /* XXX: not implemented on 440 ? */
5467 static void gen_mfapidi(DisasContext
*ctx
)
5470 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5473 /* XXX: not implemented on 440 ? */
5474 static void gen_tlbiva(DisasContext
*ctx
)
5476 #if defined(CONFIG_USER_ONLY)
5477 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5480 if (unlikely(!ctx
->mem_idx
)) {
5481 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5484 t0
= tcg_temp_new();
5485 gen_addr_reg_index(ctx
, t0
);
5486 gen_helper_tlbie(cpu_gpr
[rB(ctx
->opcode
)]);
5491 /* All 405 MAC instructions are translated here */
5492 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5493 int ra
, int rb
, int rt
, int Rc
)
5497 t0
= tcg_temp_local_new();
5498 t1
= tcg_temp_local_new();
5500 switch (opc3
& 0x0D) {
5502 /* macchw - macchw. - macchwo - macchwo. */
5503 /* macchws - macchws. - macchwso - macchwso. */
5504 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5505 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5506 /* mulchw - mulchw. */
5507 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5508 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5509 tcg_gen_ext16s_tl(t1
, t1
);
5512 /* macchwu - macchwu. - macchwuo - macchwuo. */
5513 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5514 /* mulchwu - mulchwu. */
5515 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5516 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5517 tcg_gen_ext16u_tl(t1
, t1
);
5520 /* machhw - machhw. - machhwo - machhwo. */
5521 /* machhws - machhws. - machhwso - machhwso. */
5522 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5523 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5524 /* mulhhw - mulhhw. */
5525 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5526 tcg_gen_ext16s_tl(t0
, t0
);
5527 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5528 tcg_gen_ext16s_tl(t1
, t1
);
5531 /* machhwu - machhwu. - machhwuo - machhwuo. */
5532 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5533 /* mulhhwu - mulhhwu. */
5534 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5535 tcg_gen_ext16u_tl(t0
, t0
);
5536 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5537 tcg_gen_ext16u_tl(t1
, t1
);
5540 /* maclhw - maclhw. - maclhwo - maclhwo. */
5541 /* maclhws - maclhws. - maclhwso - maclhwso. */
5542 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5543 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5544 /* mullhw - mullhw. */
5545 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5546 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5549 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5550 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5551 /* mullhwu - mullhwu. */
5552 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5553 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5557 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5558 tcg_gen_mul_tl(t1
, t0
, t1
);
5560 /* nmultiply-and-accumulate (0x0E) */
5561 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5563 /* multiply-and-accumulate (0x0C) */
5564 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5568 /* Check overflow and/or saturate */
5569 int l1
= gen_new_label();
5572 /* Start with XER OV disabled, the most likely case */
5573 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~(1 << XER_OV
));
5577 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5578 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5579 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5580 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5583 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5584 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5588 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5591 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5595 /* Check overflow */
5596 tcg_gen_ori_tl(cpu_xer
, cpu_xer
, (1 << XER_OV
) | (1 << XER_SO
));
5599 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5602 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5606 if (unlikely(Rc
) != 0) {
5608 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5612 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5613 static void glue(gen_, name)(DisasContext *ctx) \
5615 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5616 rD(ctx->opcode), Rc(ctx->opcode)); \
5619 /* macchw - macchw. */
5620 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5621 /* macchwo - macchwo. */
5622 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5623 /* macchws - macchws. */
5624 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5625 /* macchwso - macchwso. */
5626 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5627 /* macchwsu - macchwsu. */
5628 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5629 /* macchwsuo - macchwsuo. */
5630 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5631 /* macchwu - macchwu. */
5632 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5633 /* macchwuo - macchwuo. */
5634 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5635 /* machhw - machhw. */
5636 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5637 /* machhwo - machhwo. */
5638 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5639 /* machhws - machhws. */
5640 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5641 /* machhwso - machhwso. */
5642 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5643 /* machhwsu - machhwsu. */
5644 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5645 /* machhwsuo - machhwsuo. */
5646 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5647 /* machhwu - machhwu. */
5648 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5649 /* machhwuo - machhwuo. */
5650 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5651 /* maclhw - maclhw. */
5652 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5653 /* maclhwo - maclhwo. */
5654 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5655 /* maclhws - maclhws. */
5656 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5657 /* maclhwso - maclhwso. */
5658 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5659 /* maclhwu - maclhwu. */
5660 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5661 /* maclhwuo - maclhwuo. */
5662 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5663 /* maclhwsu - maclhwsu. */
5664 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5665 /* maclhwsuo - maclhwsuo. */
5666 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
5667 /* nmacchw - nmacchw. */
5668 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
5669 /* nmacchwo - nmacchwo. */
5670 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
5671 /* nmacchws - nmacchws. */
5672 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
5673 /* nmacchwso - nmacchwso. */
5674 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
5675 /* nmachhw - nmachhw. */
5676 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
5677 /* nmachhwo - nmachhwo. */
5678 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
5679 /* nmachhws - nmachhws. */
5680 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
5681 /* nmachhwso - nmachhwso. */
5682 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
5683 /* nmaclhw - nmaclhw. */
5684 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
5685 /* nmaclhwo - nmaclhwo. */
5686 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
5687 /* nmaclhws - nmaclhws. */
5688 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
5689 /* nmaclhwso - nmaclhwso. */
5690 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
5692 /* mulchw - mulchw. */
5693 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
5694 /* mulchwu - mulchwu. */
5695 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
5696 /* mulhhw - mulhhw. */
5697 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
5698 /* mulhhwu - mulhhwu. */
5699 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
5700 /* mullhw - mullhw. */
5701 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
5702 /* mullhwu - mullhwu. */
5703 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
5706 static void gen_mfdcr(DisasContext
*ctx
)
5708 #if defined(CONFIG_USER_ONLY)
5709 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5712 if (unlikely(!ctx
->mem_idx
)) {
5713 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5716 /* NIP cannot be restored if the memory exception comes from an helper */
5717 gen_update_nip(ctx
, ctx
->nip
- 4);
5718 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5719 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], dcrn
);
5720 tcg_temp_free(dcrn
);
5725 static void gen_mtdcr(DisasContext
*ctx
)
5727 #if defined(CONFIG_USER_ONLY)
5728 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5731 if (unlikely(!ctx
->mem_idx
)) {
5732 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5735 /* NIP cannot be restored if the memory exception comes from an helper */
5736 gen_update_nip(ctx
, ctx
->nip
- 4);
5737 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
5738 gen_helper_store_dcr(dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
5739 tcg_temp_free(dcrn
);
5744 /* XXX: not implemented on 440 ? */
5745 static void gen_mfdcrx(DisasContext
*ctx
)
5747 #if defined(CONFIG_USER_ONLY)
5748 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5750 if (unlikely(!ctx
->mem_idx
)) {
5751 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5754 /* NIP cannot be restored if the memory exception comes from an helper */
5755 gen_update_nip(ctx
, ctx
->nip
- 4);
5756 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5757 /* Note: Rc update flag set leads to undefined state of Rc0 */
5762 /* XXX: not implemented on 440 ? */
5763 static void gen_mtdcrx(DisasContext
*ctx
)
5765 #if defined(CONFIG_USER_ONLY)
5766 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5768 if (unlikely(!ctx
->mem_idx
)) {
5769 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
5772 /* NIP cannot be restored if the memory exception comes from an helper */
5773 gen_update_nip(ctx
, ctx
->nip
- 4);
5774 gen_helper_store_dcr(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5775 /* Note: Rc update flag set leads to undefined state of Rc0 */
5779 /* mfdcrux (PPC 460) : user-mode access to DCR */
5780 static void gen_mfdcrux(DisasContext
*ctx
)
5782 /* NIP cannot be restored if the memory exception comes from an helper */
5783 gen_update_nip(ctx
, ctx
->nip
- 4);
5784 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5785 /* Note: Rc update flag set leads to undefined state of Rc0 */
5788 /* mtdcrux (PPC 460) : user-mode access to DCR */
5789 static void gen_mtdcrux(DisasContext
*ctx
)
5791 /* NIP cannot be restored if the memory exception comes from an helper */
5792 gen_update_nip(ctx
, ctx
->nip
- 4);
5793 gen_helper_store_dcr(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
5794 /* Note: Rc update flag set leads to undefined state of Rc0 */
5798 static void gen_dccci(DisasContext
*ctx
)
5800 #if defined(CONFIG_USER_ONLY)
5801 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5803 if (unlikely(!ctx
->mem_idx
)) {
5804 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5807 /* interpreted as no-op */
5812 static void gen_dcread(DisasContext
*ctx
)
5814 #if defined(CONFIG_USER_ONLY)
5815 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5818 if (unlikely(!ctx
->mem_idx
)) {
5819 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5822 gen_set_access_type(ctx
, ACCESS_CACHE
);
5823 EA
= tcg_temp_new();
5824 gen_addr_reg_index(ctx
, EA
);
5825 val
= tcg_temp_new();
5826 gen_qemu_ld32u(ctx
, val
, EA
);
5828 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
5834 static void gen_icbt_40x(DisasContext
*ctx
)
5836 /* interpreted as no-op */
5837 /* XXX: specification say this is treated as a load by the MMU
5838 * but does not generate any exception
5843 static void gen_iccci(DisasContext
*ctx
)
5845 #if defined(CONFIG_USER_ONLY)
5846 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5848 if (unlikely(!ctx
->mem_idx
)) {
5849 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5852 /* interpreted as no-op */
5857 static void gen_icread(DisasContext
*ctx
)
5859 #if defined(CONFIG_USER_ONLY)
5860 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5862 if (unlikely(!ctx
->mem_idx
)) {
5863 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5866 /* interpreted as no-op */
5870 /* rfci (mem_idx only) */
5871 static void gen_rfci_40x(DisasContext
*ctx
)
5873 #if defined(CONFIG_USER_ONLY)
5874 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5876 if (unlikely(!ctx
->mem_idx
)) {
5877 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5880 /* Restore CPU state */
5881 gen_helper_40x_rfci(cpu_env
);
5882 gen_sync_exception(ctx
);
5886 static void gen_rfci(DisasContext
*ctx
)
5888 #if defined(CONFIG_USER_ONLY)
5889 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5891 if (unlikely(!ctx
->mem_idx
)) {
5892 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5895 /* Restore CPU state */
5896 gen_helper_rfci(cpu_env
);
5897 gen_sync_exception(ctx
);
5901 /* BookE specific */
5903 /* XXX: not implemented on 440 ? */
5904 static void gen_rfdi(DisasContext
*ctx
)
5906 #if defined(CONFIG_USER_ONLY)
5907 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5909 if (unlikely(!ctx
->mem_idx
)) {
5910 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5913 /* Restore CPU state */
5914 gen_helper_rfdi(cpu_env
);
5915 gen_sync_exception(ctx
);
5919 /* XXX: not implemented on 440 ? */
5920 static void gen_rfmci(DisasContext
*ctx
)
5922 #if defined(CONFIG_USER_ONLY)
5923 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5925 if (unlikely(!ctx
->mem_idx
)) {
5926 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5929 /* Restore CPU state */
5930 gen_helper_rfmci(cpu_env
);
5931 gen_sync_exception(ctx
);
5935 /* TLB management - PowerPC 405 implementation */
5938 static void gen_tlbre_40x(DisasContext
*ctx
)
5940 #if defined(CONFIG_USER_ONLY)
5941 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5943 if (unlikely(!ctx
->mem_idx
)) {
5944 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5947 switch (rB(ctx
->opcode
)) {
5949 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5952 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5955 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5961 /* tlbsx - tlbsx. */
5962 static void gen_tlbsx_40x(DisasContext
*ctx
)
5964 #if defined(CONFIG_USER_ONLY)
5965 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5968 if (unlikely(!ctx
->mem_idx
)) {
5969 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5972 t0
= tcg_temp_new();
5973 gen_addr_reg_index(ctx
, t0
);
5974 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5976 if (Rc(ctx
->opcode
)) {
5977 int l1
= gen_new_label();
5978 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
5979 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
5980 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
5981 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
5982 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
5989 static void gen_tlbwe_40x(DisasContext
*ctx
)
5991 #if defined(CONFIG_USER_ONLY)
5992 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5994 if (unlikely(!ctx
->mem_idx
)) {
5995 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5998 switch (rB(ctx
->opcode
)) {
6000 gen_helper_4xx_tlbwe_hi(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
6003 gen_helper_4xx_tlbwe_lo(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
6006 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6012 /* TLB management - PowerPC 440 implementation */
6015 static void gen_tlbre_440(DisasContext
*ctx
)
6017 #if defined(CONFIG_USER_ONLY)
6018 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6020 if (unlikely(!ctx
->mem_idx
)) {
6021 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6024 switch (rB(ctx
->opcode
)) {
6029 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6030 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], t0
, cpu_gpr
[rA(ctx
->opcode
)]);
6031 tcg_temp_free_i32(t0
);
6035 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6041 /* tlbsx - tlbsx. */
6042 static void gen_tlbsx_440(DisasContext
*ctx
)
6044 #if defined(CONFIG_USER_ONLY)
6045 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6048 if (unlikely(!ctx
->mem_idx
)) {
6049 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6052 t0
= tcg_temp_new();
6053 gen_addr_reg_index(ctx
, t0
);
6054 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], t0
);
6056 if (Rc(ctx
->opcode
)) {
6057 int l1
= gen_new_label();
6058 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_xer
);
6059 tcg_gen_shri_i32(cpu_crf
[0], cpu_crf
[0], XER_SO
);
6060 tcg_gen_andi_i32(cpu_crf
[0], cpu_crf
[0], 1);
6061 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6062 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6069 static void gen_tlbwe_440(DisasContext
*ctx
)
6071 #if defined(CONFIG_USER_ONLY)
6072 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6074 if (unlikely(!ctx
->mem_idx
)) {
6075 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6078 switch (rB(ctx
->opcode
)) {
6083 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6084 gen_helper_440_tlbwe(t0
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
6085 tcg_temp_free_i32(t0
);
6089 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6095 /* TLB management - PowerPC BookE 2.06 implementation */
6098 static void gen_tlbre_booke206(DisasContext
*ctx
)
6100 #if defined(CONFIG_USER_ONLY)
6101 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6103 if (unlikely(!ctx
->mem_idx
)) {
6104 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6108 gen_helper_booke206_tlbre();
6112 /* tlbsx - tlbsx. */
6113 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6115 #if defined(CONFIG_USER_ONLY)
6116 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6119 if (unlikely(!ctx
->mem_idx
)) {
6120 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6124 if (rA(ctx
->opcode
)) {
6125 t0
= tcg_temp_new();
6126 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6128 t0
= tcg_const_tl(0);
6131 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6132 gen_helper_booke206_tlbsx(t0
);
6137 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6139 #if defined(CONFIG_USER_ONLY)
6140 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6142 if (unlikely(!ctx
->mem_idx
)) {
6143 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6146 gen_update_nip(ctx
, ctx
->nip
- 4);
6147 gen_helper_booke206_tlbwe();
6151 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6153 #if defined(CONFIG_USER_ONLY)
6154 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6157 if (unlikely(!ctx
->mem_idx
)) {
6158 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6162 t0
= tcg_temp_new();
6163 gen_addr_reg_index(ctx
, t0
);
6165 gen_helper_booke206_tlbivax(t0
);
6169 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6171 #if defined(CONFIG_USER_ONLY)
6172 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6175 if (unlikely(!ctx
->mem_idx
)) {
6176 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6180 t0
= tcg_temp_new();
6181 gen_addr_reg_index(ctx
, t0
);
6183 switch((ctx
->opcode
>> 21) & 0x3) {
6185 gen_helper_booke206_tlbilx0(t0
);
6188 gen_helper_booke206_tlbilx1(t0
);
6191 gen_helper_booke206_tlbilx3(t0
);
6194 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6204 static void gen_wrtee(DisasContext
*ctx
)
6206 #if defined(CONFIG_USER_ONLY)
6207 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6210 if (unlikely(!ctx
->mem_idx
)) {
6211 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6214 t0
= tcg_temp_new();
6215 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6216 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6217 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6219 /* Stop translation to have a chance to raise an exception
6220 * if we just set msr_ee to 1
6222 gen_stop_exception(ctx
);
6227 static void gen_wrteei(DisasContext
*ctx
)
6229 #if defined(CONFIG_USER_ONLY)
6230 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6232 if (unlikely(!ctx
->mem_idx
)) {
6233 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6236 if (ctx
->opcode
& 0x00008000) {
6237 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6238 /* Stop translation to have a chance to raise an exception */
6239 gen_stop_exception(ctx
);
6241 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6246 /* PowerPC 440 specific instructions */
6249 static void gen_dlmzb(DisasContext
*ctx
)
6251 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6252 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6253 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6254 tcg_temp_free_i32(t0
);
6257 /* mbar replaces eieio on 440 */
6258 static void gen_mbar(DisasContext
*ctx
)
6260 /* interpreted as no-op */
6263 /* msync replaces sync on 440 */
6264 static void gen_msync_4xx(DisasContext
*ctx
)
6266 /* interpreted as no-op */
6270 static void gen_icbt_440(DisasContext
*ctx
)
6272 /* interpreted as no-op */
6273 /* XXX: specification say this is treated as a load by the MMU
6274 * but does not generate any exception
6278 /* Embedded.Processor Control */
6280 static void gen_msgclr(DisasContext
*ctx
)
6282 #if defined(CONFIG_USER_ONLY)
6283 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6285 if (unlikely(ctx
->mem_idx
== 0)) {
6286 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6290 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6294 static void gen_msgsnd(DisasContext
*ctx
)
6296 #if defined(CONFIG_USER_ONLY)
6297 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6299 if (unlikely(ctx
->mem_idx
== 0)) {
6300 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6304 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6308 /*** Altivec vector extension ***/
6309 /* Altivec registers moves */
6311 static inline TCGv_ptr
gen_avr_ptr(int reg
)
6313 TCGv_ptr r
= tcg_temp_new_ptr();
6314 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, avr
[reg
]));
6318 #define GEN_VR_LDX(name, opc2, opc3) \
6319 static void glue(gen_, name)(DisasContext *ctx) \
6322 if (unlikely(!ctx->altivec_enabled)) { \
6323 gen_exception(ctx, POWERPC_EXCP_VPU); \
6326 gen_set_access_type(ctx, ACCESS_INT); \
6327 EA = tcg_temp_new(); \
6328 gen_addr_reg_index(ctx, EA); \
6329 tcg_gen_andi_tl(EA, EA, ~0xf); \
6330 if (ctx->le_mode) { \
6331 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6332 tcg_gen_addi_tl(EA, EA, 8); \
6333 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6335 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6336 tcg_gen_addi_tl(EA, EA, 8); \
6337 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6339 tcg_temp_free(EA); \
6342 #define GEN_VR_STX(name, opc2, opc3) \
6343 static void gen_st##name(DisasContext *ctx) \
6346 if (unlikely(!ctx->altivec_enabled)) { \
6347 gen_exception(ctx, POWERPC_EXCP_VPU); \
6350 gen_set_access_type(ctx, ACCESS_INT); \
6351 EA = tcg_temp_new(); \
6352 gen_addr_reg_index(ctx, EA); \
6353 tcg_gen_andi_tl(EA, EA, ~0xf); \
6354 if (ctx->le_mode) { \
6355 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6356 tcg_gen_addi_tl(EA, EA, 8); \
6357 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6359 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6360 tcg_gen_addi_tl(EA, EA, 8); \
6361 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6363 tcg_temp_free(EA); \
6366 #define GEN_VR_LVE(name, opc2, opc3) \
6367 static void gen_lve##name(DisasContext *ctx) \
6371 if (unlikely(!ctx->altivec_enabled)) { \
6372 gen_exception(ctx, POWERPC_EXCP_VPU); \
6375 gen_set_access_type(ctx, ACCESS_INT); \
6376 EA = tcg_temp_new(); \
6377 gen_addr_reg_index(ctx, EA); \
6378 rs = gen_avr_ptr(rS(ctx->opcode)); \
6379 gen_helper_lve##name (rs, EA); \
6380 tcg_temp_free(EA); \
6381 tcg_temp_free_ptr(rs); \
6384 #define GEN_VR_STVE(name, opc2, opc3) \
6385 static void gen_stve##name(DisasContext *ctx) \
6389 if (unlikely(!ctx->altivec_enabled)) { \
6390 gen_exception(ctx, POWERPC_EXCP_VPU); \
6393 gen_set_access_type(ctx, ACCESS_INT); \
6394 EA = tcg_temp_new(); \
6395 gen_addr_reg_index(ctx, EA); \
6396 rs = gen_avr_ptr(rS(ctx->opcode)); \
6397 gen_helper_stve##name (rs, EA); \
6398 tcg_temp_free(EA); \
6399 tcg_temp_free_ptr(rs); \
6402 GEN_VR_LDX(lvx
, 0x07, 0x03);
6403 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6404 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
6406 GEN_VR_LVE(bx
, 0x07, 0x00);
6407 GEN_VR_LVE(hx
, 0x07, 0x01);
6408 GEN_VR_LVE(wx
, 0x07, 0x02);
6410 GEN_VR_STX(svx
, 0x07, 0x07);
6411 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6412 GEN_VR_STX(svxl
, 0x07, 0x0F);
6414 GEN_VR_STVE(bx
, 0x07, 0x04);
6415 GEN_VR_STVE(hx
, 0x07, 0x05);
6416 GEN_VR_STVE(wx
, 0x07, 0x06);
6418 static void gen_lvsl(DisasContext
*ctx
)
6422 if (unlikely(!ctx
->altivec_enabled
)) {
6423 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6426 EA
= tcg_temp_new();
6427 gen_addr_reg_index(ctx
, EA
);
6428 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6429 gen_helper_lvsl(rd
, EA
);
6431 tcg_temp_free_ptr(rd
);
6434 static void gen_lvsr(DisasContext
*ctx
)
6438 if (unlikely(!ctx
->altivec_enabled
)) {
6439 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6442 EA
= tcg_temp_new();
6443 gen_addr_reg_index(ctx
, EA
);
6444 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6445 gen_helper_lvsr(rd
, EA
);
6447 tcg_temp_free_ptr(rd
);
6450 static void gen_mfvscr(DisasContext
*ctx
)
6453 if (unlikely(!ctx
->altivec_enabled
)) {
6454 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6457 tcg_gen_movi_i64(cpu_avrh
[rD(ctx
->opcode
)], 0);
6458 t
= tcg_temp_new_i32();
6459 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, vscr
));
6460 tcg_gen_extu_i32_i64(cpu_avrl
[rD(ctx
->opcode
)], t
);
6461 tcg_temp_free_i32(t
);
6464 static void gen_mtvscr(DisasContext
*ctx
)
6467 if (unlikely(!ctx
->altivec_enabled
)) {
6468 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6471 p
= gen_avr_ptr(rD(ctx
->opcode
));
6472 gen_helper_mtvscr(cpu_env
, p
);
6473 tcg_temp_free_ptr(p
);
6476 /* Logical operations */
6477 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6478 static void glue(gen_, name)(DisasContext *ctx) \
6480 if (unlikely(!ctx->altivec_enabled)) { \
6481 gen_exception(ctx, POWERPC_EXCP_VPU); \
6484 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6485 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6488 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16);
6489 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17);
6490 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18);
6491 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19);
6492 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20);
6494 #define GEN_VXFORM(name, opc2, opc3) \
6495 static void glue(gen_, name)(DisasContext *ctx) \
6497 TCGv_ptr ra, rb, rd; \
6498 if (unlikely(!ctx->altivec_enabled)) { \
6499 gen_exception(ctx, POWERPC_EXCP_VPU); \
6502 ra = gen_avr_ptr(rA(ctx->opcode)); \
6503 rb = gen_avr_ptr(rB(ctx->opcode)); \
6504 rd = gen_avr_ptr(rD(ctx->opcode)); \
6505 gen_helper_##name (rd, ra, rb); \
6506 tcg_temp_free_ptr(ra); \
6507 tcg_temp_free_ptr(rb); \
6508 tcg_temp_free_ptr(rd); \
6511 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6512 static void glue(gen_, name)(DisasContext *ctx) \
6514 TCGv_ptr ra, rb, rd; \
6515 if (unlikely(!ctx->altivec_enabled)) { \
6516 gen_exception(ctx, POWERPC_EXCP_VPU); \
6519 ra = gen_avr_ptr(rA(ctx->opcode)); \
6520 rb = gen_avr_ptr(rB(ctx->opcode)); \
6521 rd = gen_avr_ptr(rD(ctx->opcode)); \
6522 gen_helper_##name(rd, cpu_env, ra, rb); \
6523 tcg_temp_free_ptr(ra); \
6524 tcg_temp_free_ptr(rb); \
6525 tcg_temp_free_ptr(rd); \
6528 GEN_VXFORM(vaddubm
, 0, 0);
6529 GEN_VXFORM(vadduhm
, 0, 1);
6530 GEN_VXFORM(vadduwm
, 0, 2);
6531 GEN_VXFORM(vsububm
, 0, 16);
6532 GEN_VXFORM(vsubuhm
, 0, 17);
6533 GEN_VXFORM(vsubuwm
, 0, 18);
6534 GEN_VXFORM(vmaxub
, 1, 0);
6535 GEN_VXFORM(vmaxuh
, 1, 1);
6536 GEN_VXFORM(vmaxuw
, 1, 2);
6537 GEN_VXFORM(vmaxsb
, 1, 4);
6538 GEN_VXFORM(vmaxsh
, 1, 5);
6539 GEN_VXFORM(vmaxsw
, 1, 6);
6540 GEN_VXFORM(vminub
, 1, 8);
6541 GEN_VXFORM(vminuh
, 1, 9);
6542 GEN_VXFORM(vminuw
, 1, 10);
6543 GEN_VXFORM(vminsb
, 1, 12);
6544 GEN_VXFORM(vminsh
, 1, 13);
6545 GEN_VXFORM(vminsw
, 1, 14);
6546 GEN_VXFORM(vavgub
, 1, 16);
6547 GEN_VXFORM(vavguh
, 1, 17);
6548 GEN_VXFORM(vavguw
, 1, 18);
6549 GEN_VXFORM(vavgsb
, 1, 20);
6550 GEN_VXFORM(vavgsh
, 1, 21);
6551 GEN_VXFORM(vavgsw
, 1, 22);
6552 GEN_VXFORM(vmrghb
, 6, 0);
6553 GEN_VXFORM(vmrghh
, 6, 1);
6554 GEN_VXFORM(vmrghw
, 6, 2);
6555 GEN_VXFORM(vmrglb
, 6, 4);
6556 GEN_VXFORM(vmrglh
, 6, 5);
6557 GEN_VXFORM(vmrglw
, 6, 6);
6558 GEN_VXFORM(vmuloub
, 4, 0);
6559 GEN_VXFORM(vmulouh
, 4, 1);
6560 GEN_VXFORM(vmulosb
, 4, 4);
6561 GEN_VXFORM(vmulosh
, 4, 5);
6562 GEN_VXFORM(vmuleub
, 4, 8);
6563 GEN_VXFORM(vmuleuh
, 4, 9);
6564 GEN_VXFORM(vmulesb
, 4, 12);
6565 GEN_VXFORM(vmulesh
, 4, 13);
6566 GEN_VXFORM(vslb
, 2, 4);
6567 GEN_VXFORM(vslh
, 2, 5);
6568 GEN_VXFORM(vslw
, 2, 6);
6569 GEN_VXFORM(vsrb
, 2, 8);
6570 GEN_VXFORM(vsrh
, 2, 9);
6571 GEN_VXFORM(vsrw
, 2, 10);
6572 GEN_VXFORM(vsrab
, 2, 12);
6573 GEN_VXFORM(vsrah
, 2, 13);
6574 GEN_VXFORM(vsraw
, 2, 14);
6575 GEN_VXFORM(vslo
, 6, 16);
6576 GEN_VXFORM(vsro
, 6, 17);
6577 GEN_VXFORM(vaddcuw
, 0, 6);
6578 GEN_VXFORM(vsubcuw
, 0, 22);
6579 GEN_VXFORM_ENV(vaddubs
, 0, 8);
6580 GEN_VXFORM_ENV(vadduhs
, 0, 9);
6581 GEN_VXFORM_ENV(vadduws
, 0, 10);
6582 GEN_VXFORM_ENV(vaddsbs
, 0, 12);
6583 GEN_VXFORM_ENV(vaddshs
, 0, 13);
6584 GEN_VXFORM_ENV(vaddsws
, 0, 14);
6585 GEN_VXFORM_ENV(vsububs
, 0, 24);
6586 GEN_VXFORM_ENV(vsubuhs
, 0, 25);
6587 GEN_VXFORM_ENV(vsubuws
, 0, 26);
6588 GEN_VXFORM_ENV(vsubsbs
, 0, 28);
6589 GEN_VXFORM_ENV(vsubshs
, 0, 29);
6590 GEN_VXFORM_ENV(vsubsws
, 0, 30);
6591 GEN_VXFORM(vrlb
, 2, 0);
6592 GEN_VXFORM(vrlh
, 2, 1);
6593 GEN_VXFORM(vrlw
, 2, 2);
6594 GEN_VXFORM(vsl
, 2, 7);
6595 GEN_VXFORM(vsr
, 2, 11);
6596 GEN_VXFORM_ENV(vpkuhum
, 7, 0);
6597 GEN_VXFORM_ENV(vpkuwum
, 7, 1);
6598 GEN_VXFORM_ENV(vpkuhus
, 7, 2);
6599 GEN_VXFORM_ENV(vpkuwus
, 7, 3);
6600 GEN_VXFORM_ENV(vpkshus
, 7, 4);
6601 GEN_VXFORM_ENV(vpkswus
, 7, 5);
6602 GEN_VXFORM_ENV(vpkshss
, 7, 6);
6603 GEN_VXFORM_ENV(vpkswss
, 7, 7);
6604 GEN_VXFORM(vpkpx
, 7, 12);
6605 GEN_VXFORM_ENV(vsum4ubs
, 4, 24);
6606 GEN_VXFORM_ENV(vsum4sbs
, 4, 28);
6607 GEN_VXFORM_ENV(vsum4shs
, 4, 25);
6608 GEN_VXFORM_ENV(vsum2sws
, 4, 26);
6609 GEN_VXFORM_ENV(vsumsws
, 4, 30);
6610 GEN_VXFORM_ENV(vaddfp
, 5, 0);
6611 GEN_VXFORM_ENV(vsubfp
, 5, 1);
6612 GEN_VXFORM_ENV(vmaxfp
, 5, 16);
6613 GEN_VXFORM_ENV(vminfp
, 5, 17);
6615 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6616 static void glue(gen_, name)(DisasContext *ctx) \
6618 TCGv_ptr ra, rb, rd; \
6619 if (unlikely(!ctx->altivec_enabled)) { \
6620 gen_exception(ctx, POWERPC_EXCP_VPU); \
6623 ra = gen_avr_ptr(rA(ctx->opcode)); \
6624 rb = gen_avr_ptr(rB(ctx->opcode)); \
6625 rd = gen_avr_ptr(rD(ctx->opcode)); \
6626 gen_helper_##opname(cpu_env, rd, ra, rb); \
6627 tcg_temp_free_ptr(ra); \
6628 tcg_temp_free_ptr(rb); \
6629 tcg_temp_free_ptr(rd); \
6632 #define GEN_VXRFORM(name, opc2, opc3) \
6633 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6634 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6636 GEN_VXRFORM(vcmpequb
, 3, 0)
6637 GEN_VXRFORM(vcmpequh
, 3, 1)
6638 GEN_VXRFORM(vcmpequw
, 3, 2)
6639 GEN_VXRFORM(vcmpgtsb
, 3, 12)
6640 GEN_VXRFORM(vcmpgtsh
, 3, 13)
6641 GEN_VXRFORM(vcmpgtsw
, 3, 14)
6642 GEN_VXRFORM(vcmpgtub
, 3, 8)
6643 GEN_VXRFORM(vcmpgtuh
, 3, 9)
6644 GEN_VXRFORM(vcmpgtuw
, 3, 10)
6645 GEN_VXRFORM(vcmpeqfp
, 3, 3)
6646 GEN_VXRFORM(vcmpgefp
, 3, 7)
6647 GEN_VXRFORM(vcmpgtfp
, 3, 11)
6648 GEN_VXRFORM(vcmpbfp
, 3, 15)
6650 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6651 static void glue(gen_, name)(DisasContext *ctx) \
6655 if (unlikely(!ctx->altivec_enabled)) { \
6656 gen_exception(ctx, POWERPC_EXCP_VPU); \
6659 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6660 rd = gen_avr_ptr(rD(ctx->opcode)); \
6661 gen_helper_##name (rd, simm); \
6662 tcg_temp_free_i32(simm); \
6663 tcg_temp_free_ptr(rd); \
6666 GEN_VXFORM_SIMM(vspltisb
, 6, 12);
6667 GEN_VXFORM_SIMM(vspltish
, 6, 13);
6668 GEN_VXFORM_SIMM(vspltisw
, 6, 14);
6670 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6671 static void glue(gen_, name)(DisasContext *ctx) \
6674 if (unlikely(!ctx->altivec_enabled)) { \
6675 gen_exception(ctx, POWERPC_EXCP_VPU); \
6678 rb = gen_avr_ptr(rB(ctx->opcode)); \
6679 rd = gen_avr_ptr(rD(ctx->opcode)); \
6680 gen_helper_##name (rd, rb); \
6681 tcg_temp_free_ptr(rb); \
6682 tcg_temp_free_ptr(rd); \
6685 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6686 static void glue(gen_, name)(DisasContext *ctx) \
6690 if (unlikely(!ctx->altivec_enabled)) { \
6691 gen_exception(ctx, POWERPC_EXCP_VPU); \
6694 rb = gen_avr_ptr(rB(ctx->opcode)); \
6695 rd = gen_avr_ptr(rD(ctx->opcode)); \
6696 gen_helper_##name(cpu_env, rd, rb); \
6697 tcg_temp_free_ptr(rb); \
6698 tcg_temp_free_ptr(rd); \
6701 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
6702 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
6703 GEN_VXFORM_NOA(vupklsb
, 7, 10);
6704 GEN_VXFORM_NOA(vupklsh
, 7, 11);
6705 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
6706 GEN_VXFORM_NOA(vupklpx
, 7, 15);
6707 GEN_VXFORM_NOA_ENV(vrefp
, 5, 4);
6708 GEN_VXFORM_NOA_ENV(vrsqrtefp
, 5, 5);
6709 GEN_VXFORM_NOA_ENV(vexptefp
, 5, 6);
6710 GEN_VXFORM_NOA_ENV(vlogefp
, 5, 7);
6711 GEN_VXFORM_NOA_ENV(vrfim
, 5, 8);
6712 GEN_VXFORM_NOA_ENV(vrfin
, 5, 9);
6713 GEN_VXFORM_NOA_ENV(vrfip
, 5, 10);
6714 GEN_VXFORM_NOA_ENV(vrfiz
, 5, 11);
6716 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6717 static void glue(gen_, name)(DisasContext *ctx) \
6721 if (unlikely(!ctx->altivec_enabled)) { \
6722 gen_exception(ctx, POWERPC_EXCP_VPU); \
6725 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6726 rd = gen_avr_ptr(rD(ctx->opcode)); \
6727 gen_helper_##name (rd, simm); \
6728 tcg_temp_free_i32(simm); \
6729 tcg_temp_free_ptr(rd); \
6732 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6733 static void glue(gen_, name)(DisasContext *ctx) \
6737 if (unlikely(!ctx->altivec_enabled)) { \
6738 gen_exception(ctx, POWERPC_EXCP_VPU); \
6741 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6742 rb = gen_avr_ptr(rB(ctx->opcode)); \
6743 rd = gen_avr_ptr(rD(ctx->opcode)); \
6744 gen_helper_##name (rd, rb, uimm); \
6745 tcg_temp_free_i32(uimm); \
6746 tcg_temp_free_ptr(rb); \
6747 tcg_temp_free_ptr(rd); \
6750 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6751 static void glue(gen_, name)(DisasContext *ctx) \
6756 if (unlikely(!ctx->altivec_enabled)) { \
6757 gen_exception(ctx, POWERPC_EXCP_VPU); \
6760 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6761 rb = gen_avr_ptr(rB(ctx->opcode)); \
6762 rd = gen_avr_ptr(rD(ctx->opcode)); \
6763 gen_helper_##name(cpu_env, rd, rb, uimm); \
6764 tcg_temp_free_i32(uimm); \
6765 tcg_temp_free_ptr(rb); \
6766 tcg_temp_free_ptr(rd); \
6769 GEN_VXFORM_UIMM(vspltb
, 6, 8);
6770 GEN_VXFORM_UIMM(vsplth
, 6, 9);
6771 GEN_VXFORM_UIMM(vspltw
, 6, 10);
6772 GEN_VXFORM_UIMM_ENV(vcfux
, 5, 12);
6773 GEN_VXFORM_UIMM_ENV(vcfsx
, 5, 13);
6774 GEN_VXFORM_UIMM_ENV(vctuxs
, 5, 14);
6775 GEN_VXFORM_UIMM_ENV(vctsxs
, 5, 15);
6777 static void gen_vsldoi(DisasContext
*ctx
)
6779 TCGv_ptr ra
, rb
, rd
;
6781 if (unlikely(!ctx
->altivec_enabled
)) {
6782 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6785 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6786 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6787 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6788 sh
= tcg_const_i32(VSH(ctx
->opcode
));
6789 gen_helper_vsldoi (rd
, ra
, rb
, sh
);
6790 tcg_temp_free_ptr(ra
);
6791 tcg_temp_free_ptr(rb
);
6792 tcg_temp_free_ptr(rd
);
6793 tcg_temp_free_i32(sh
);
6796 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6797 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6799 TCGv_ptr ra, rb, rc, rd; \
6800 if (unlikely(!ctx->altivec_enabled)) { \
6801 gen_exception(ctx, POWERPC_EXCP_VPU); \
6804 ra = gen_avr_ptr(rA(ctx->opcode)); \
6805 rb = gen_avr_ptr(rB(ctx->opcode)); \
6806 rc = gen_avr_ptr(rC(ctx->opcode)); \
6807 rd = gen_avr_ptr(rD(ctx->opcode)); \
6808 if (Rc(ctx->opcode)) { \
6809 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6811 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6813 tcg_temp_free_ptr(ra); \
6814 tcg_temp_free_ptr(rb); \
6815 tcg_temp_free_ptr(rc); \
6816 tcg_temp_free_ptr(rd); \
6819 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
6821 static void gen_vmladduhm(DisasContext
*ctx
)
6823 TCGv_ptr ra
, rb
, rc
, rd
;
6824 if (unlikely(!ctx
->altivec_enabled
)) {
6825 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6828 ra
= gen_avr_ptr(rA(ctx
->opcode
));
6829 rb
= gen_avr_ptr(rB(ctx
->opcode
));
6830 rc
= gen_avr_ptr(rC(ctx
->opcode
));
6831 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6832 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
6833 tcg_temp_free_ptr(ra
);
6834 tcg_temp_free_ptr(rb
);
6835 tcg_temp_free_ptr(rc
);
6836 tcg_temp_free_ptr(rd
);
6839 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
6840 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
6841 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
6842 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
6843 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
6845 /*** SPE extension ***/
6846 /* Register moves */
6849 static inline void gen_evmra(DisasContext
*ctx
)
6852 if (unlikely(!ctx
->spe_enabled
)) {
6853 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
6857 #if defined(TARGET_PPC64)
6859 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6862 tcg_gen_st_i64(cpu_gpr
[rA(ctx
->opcode
)],
6864 offsetof(CPUPPCState
, spe_acc
));
6866 TCGv_i64 tmp
= tcg_temp_new_i64();
6868 /* tmp := rA_lo + rA_hi << 32 */
6869 tcg_gen_concat_i32_i64(tmp
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
6871 /* spe_acc := tmp */
6872 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
6873 tcg_temp_free_i64(tmp
);
6876 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
6877 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
6881 static inline void gen_load_gpr64(TCGv_i64 t
, int reg
)
6883 #if defined(TARGET_PPC64)
6884 tcg_gen_mov_i64(t
, cpu_gpr
[reg
]);
6886 tcg_gen_concat_i32_i64(t
, cpu_gpr
[reg
], cpu_gprh
[reg
]);
6890 static inline void gen_store_gpr64(int reg
, TCGv_i64 t
)
6892 #if defined(TARGET_PPC64)
6893 tcg_gen_mov_i64(cpu_gpr
[reg
], t
);
6895 TCGv_i64 tmp
= tcg_temp_new_i64();
6896 tcg_gen_trunc_i64_i32(cpu_gpr
[reg
], t
);
6897 tcg_gen_shri_i64(tmp
, t
, 32);
6898 tcg_gen_trunc_i64_i32(cpu_gprh
[reg
], tmp
);
6899 tcg_temp_free_i64(tmp
);
6903 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6904 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6906 if (Rc(ctx->opcode)) \
6912 /* Handler for undefined SPE opcodes */
6913 static inline void gen_speundef(DisasContext
*ctx
)
6915 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6919 #if defined(TARGET_PPC64)
6920 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6921 static inline void gen_##name(DisasContext *ctx) \
6923 if (unlikely(!ctx->spe_enabled)) { \
6924 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6927 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6928 cpu_gpr[rB(ctx->opcode)]); \
6931 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6932 static inline void gen_##name(DisasContext *ctx) \
6934 if (unlikely(!ctx->spe_enabled)) { \
6935 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6938 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6939 cpu_gpr[rB(ctx->opcode)]); \
6940 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6941 cpu_gprh[rB(ctx->opcode)]); \
6945 GEN_SPEOP_LOGIC2(evand
, tcg_gen_and_tl
);
6946 GEN_SPEOP_LOGIC2(evandc
, tcg_gen_andc_tl
);
6947 GEN_SPEOP_LOGIC2(evxor
, tcg_gen_xor_tl
);
6948 GEN_SPEOP_LOGIC2(evor
, tcg_gen_or_tl
);
6949 GEN_SPEOP_LOGIC2(evnor
, tcg_gen_nor_tl
);
6950 GEN_SPEOP_LOGIC2(eveqv
, tcg_gen_eqv_tl
);
6951 GEN_SPEOP_LOGIC2(evorc
, tcg_gen_orc_tl
);
6952 GEN_SPEOP_LOGIC2(evnand
, tcg_gen_nand_tl
);
6954 /* SPE logic immediate */
6955 #if defined(TARGET_PPC64)
6956 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6957 static inline void gen_##name(DisasContext *ctx) \
6959 if (unlikely(!ctx->spe_enabled)) { \
6960 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6963 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6964 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6965 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6966 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6967 tcg_opi(t0, t0, rB(ctx->opcode)); \
6968 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6969 tcg_gen_trunc_i64_i32(t1, t2); \
6970 tcg_temp_free_i64(t2); \
6971 tcg_opi(t1, t1, rB(ctx->opcode)); \
6972 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6973 tcg_temp_free_i32(t0); \
6974 tcg_temp_free_i32(t1); \
6977 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6978 static inline void gen_##name(DisasContext *ctx) \
6980 if (unlikely(!ctx->spe_enabled)) { \
6981 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6984 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6986 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6990 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi
, tcg_gen_shli_i32
);
6991 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu
, tcg_gen_shri_i32
);
6992 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis
, tcg_gen_sari_i32
);
6993 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi
, tcg_gen_rotli_i32
);
6995 /* SPE arithmetic */
6996 #if defined(TARGET_PPC64)
6997 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6998 static inline void gen_##name(DisasContext *ctx) \
7000 if (unlikely(!ctx->spe_enabled)) { \
7001 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7004 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7005 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7006 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7007 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7009 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7010 tcg_gen_trunc_i64_i32(t1, t2); \
7011 tcg_temp_free_i64(t2); \
7013 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7014 tcg_temp_free_i32(t0); \
7015 tcg_temp_free_i32(t1); \
7018 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7019 static inline void gen_##name(DisasContext *ctx) \
7021 if (unlikely(!ctx->spe_enabled)) { \
7022 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7025 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7026 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7030 static inline void gen_op_evabs(TCGv_i32 ret
, TCGv_i32 arg1
)
7032 int l1
= gen_new_label();
7033 int l2
= gen_new_label();
7035 tcg_gen_brcondi_i32(TCG_COND_GE
, arg1
, 0, l1
);
7036 tcg_gen_neg_i32(ret
, arg1
);
7039 tcg_gen_mov_i32(ret
, arg1
);
7042 GEN_SPEOP_ARITH1(evabs
, gen_op_evabs
);
7043 GEN_SPEOP_ARITH1(evneg
, tcg_gen_neg_i32
);
7044 GEN_SPEOP_ARITH1(evextsb
, tcg_gen_ext8s_i32
);
7045 GEN_SPEOP_ARITH1(evextsh
, tcg_gen_ext16s_i32
);
7046 static inline void gen_op_evrndw(TCGv_i32 ret
, TCGv_i32 arg1
)
7048 tcg_gen_addi_i32(ret
, arg1
, 0x8000);
7049 tcg_gen_ext16u_i32(ret
, ret
);
7051 GEN_SPEOP_ARITH1(evrndw
, gen_op_evrndw
);
7052 GEN_SPEOP_ARITH1(evcntlsw
, gen_helper_cntlsw32
);
7053 GEN_SPEOP_ARITH1(evcntlzw
, gen_helper_cntlzw32
);
7055 #if defined(TARGET_PPC64)
7056 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7057 static inline void gen_##name(DisasContext *ctx) \
7059 if (unlikely(!ctx->spe_enabled)) { \
7060 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7063 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7064 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7065 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7066 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7067 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7068 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7069 tcg_op(t0, t0, t2); \
7070 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7071 tcg_gen_trunc_i64_i32(t1, t3); \
7072 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7073 tcg_gen_trunc_i64_i32(t2, t3); \
7074 tcg_temp_free_i64(t3); \
7075 tcg_op(t1, t1, t2); \
7076 tcg_temp_free_i32(t2); \
7077 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7078 tcg_temp_free_i32(t0); \
7079 tcg_temp_free_i32(t1); \
7082 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7083 static inline void gen_##name(DisasContext *ctx) \
7085 if (unlikely(!ctx->spe_enabled)) { \
7086 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7089 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7090 cpu_gpr[rB(ctx->opcode)]); \
7091 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7092 cpu_gprh[rB(ctx->opcode)]); \
7096 static inline void gen_op_evsrwu(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7101 l1
= gen_new_label();
7102 l2
= gen_new_label();
7103 t0
= tcg_temp_local_new_i32();
7104 /* No error here: 6 bits are used */
7105 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7106 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7107 tcg_gen_shr_i32(ret
, arg1
, t0
);
7110 tcg_gen_movi_i32(ret
, 0);
7112 tcg_temp_free_i32(t0
);
7114 GEN_SPEOP_ARITH2(evsrwu
, gen_op_evsrwu
);
7115 static inline void gen_op_evsrws(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7120 l1
= gen_new_label();
7121 l2
= gen_new_label();
7122 t0
= tcg_temp_local_new_i32();
7123 /* No error here: 6 bits are used */
7124 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7125 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7126 tcg_gen_sar_i32(ret
, arg1
, t0
);
7129 tcg_gen_movi_i32(ret
, 0);
7131 tcg_temp_free_i32(t0
);
7133 GEN_SPEOP_ARITH2(evsrws
, gen_op_evsrws
);
7134 static inline void gen_op_evslw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7139 l1
= gen_new_label();
7140 l2
= gen_new_label();
7141 t0
= tcg_temp_local_new_i32();
7142 /* No error here: 6 bits are used */
7143 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
7144 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
7145 tcg_gen_shl_i32(ret
, arg1
, t0
);
7148 tcg_gen_movi_i32(ret
, 0);
7150 tcg_temp_free_i32(t0
);
7152 GEN_SPEOP_ARITH2(evslw
, gen_op_evslw
);
7153 static inline void gen_op_evrlw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7155 TCGv_i32 t0
= tcg_temp_new_i32();
7156 tcg_gen_andi_i32(t0
, arg2
, 0x1F);
7157 tcg_gen_rotl_i32(ret
, arg1
, t0
);
7158 tcg_temp_free_i32(t0
);
7160 GEN_SPEOP_ARITH2(evrlw
, gen_op_evrlw
);
7161 static inline void gen_evmergehi(DisasContext
*ctx
)
7163 if (unlikely(!ctx
->spe_enabled
)) {
7164 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7167 #if defined(TARGET_PPC64)
7168 TCGv t0
= tcg_temp_new();
7169 TCGv t1
= tcg_temp_new();
7170 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
7171 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
7172 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7176 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7177 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7180 GEN_SPEOP_ARITH2(evaddw
, tcg_gen_add_i32
);
7181 static inline void gen_op_evsubf(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
7183 tcg_gen_sub_i32(ret
, arg2
, arg1
);
7185 GEN_SPEOP_ARITH2(evsubfw
, gen_op_evsubf
);
7187 /* SPE arithmetic immediate */
7188 #if defined(TARGET_PPC64)
7189 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7190 static inline void gen_##name(DisasContext *ctx) \
7192 if (unlikely(!ctx->spe_enabled)) { \
7193 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7196 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7197 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7198 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7199 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7200 tcg_op(t0, t0, rA(ctx->opcode)); \
7201 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7202 tcg_gen_trunc_i64_i32(t1, t2); \
7203 tcg_temp_free_i64(t2); \
7204 tcg_op(t1, t1, rA(ctx->opcode)); \
7205 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7206 tcg_temp_free_i32(t0); \
7207 tcg_temp_free_i32(t1); \
7210 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7211 static inline void gen_##name(DisasContext *ctx) \
7213 if (unlikely(!ctx->spe_enabled)) { \
7214 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7217 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7219 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7223 GEN_SPEOP_ARITH_IMM2(evaddiw
, tcg_gen_addi_i32
);
7224 GEN_SPEOP_ARITH_IMM2(evsubifw
, tcg_gen_subi_i32
);
7226 /* SPE comparison */
7227 #if defined(TARGET_PPC64)
7228 #define GEN_SPEOP_COMP(name, tcg_cond) \
7229 static inline void gen_##name(DisasContext *ctx) \
7231 if (unlikely(!ctx->spe_enabled)) { \
7232 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7235 int l1 = gen_new_label(); \
7236 int l2 = gen_new_label(); \
7237 int l3 = gen_new_label(); \
7238 int l4 = gen_new_label(); \
7239 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7240 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7241 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7242 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7243 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7244 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7245 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7247 gen_set_label(l1); \
7248 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7249 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7250 gen_set_label(l2); \
7251 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7252 tcg_gen_trunc_i64_i32(t0, t2); \
7253 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7254 tcg_gen_trunc_i64_i32(t1, t2); \
7255 tcg_temp_free_i64(t2); \
7256 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7257 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7258 ~(CRF_CH | CRF_CH_AND_CL)); \
7260 gen_set_label(l3); \
7261 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7262 CRF_CH | CRF_CH_OR_CL); \
7263 gen_set_label(l4); \
7264 tcg_temp_free_i32(t0); \
7265 tcg_temp_free_i32(t1); \
7268 #define GEN_SPEOP_COMP(name, tcg_cond) \
7269 static inline void gen_##name(DisasContext *ctx) \
7271 if (unlikely(!ctx->spe_enabled)) { \
7272 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7275 int l1 = gen_new_label(); \
7276 int l2 = gen_new_label(); \
7277 int l3 = gen_new_label(); \
7278 int l4 = gen_new_label(); \
7280 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7281 cpu_gpr[rB(ctx->opcode)], l1); \
7282 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7284 gen_set_label(l1); \
7285 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7286 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7287 gen_set_label(l2); \
7288 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7289 cpu_gprh[rB(ctx->opcode)], l3); \
7290 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7291 ~(CRF_CH | CRF_CH_AND_CL)); \
7293 gen_set_label(l3); \
7294 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7295 CRF_CH | CRF_CH_OR_CL); \
7296 gen_set_label(l4); \
7299 GEN_SPEOP_COMP(evcmpgtu
, TCG_COND_GTU
);
7300 GEN_SPEOP_COMP(evcmpgts
, TCG_COND_GT
);
7301 GEN_SPEOP_COMP(evcmpltu
, TCG_COND_LTU
);
7302 GEN_SPEOP_COMP(evcmplts
, TCG_COND_LT
);
7303 GEN_SPEOP_COMP(evcmpeq
, TCG_COND_EQ
);
7306 static inline void gen_brinc(DisasContext
*ctx
)
7308 /* Note: brinc is usable even if SPE is disabled */
7309 gen_helper_brinc(cpu_gpr
[rD(ctx
->opcode
)],
7310 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7312 static inline void gen_evmergelo(DisasContext
*ctx
)
7314 if (unlikely(!ctx
->spe_enabled
)) {
7315 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7318 #if defined(TARGET_PPC64)
7319 TCGv t0
= tcg_temp_new();
7320 TCGv t1
= tcg_temp_new();
7321 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
7322 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
7323 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7327 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7328 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7331 static inline void gen_evmergehilo(DisasContext
*ctx
)
7333 if (unlikely(!ctx
->spe_enabled
)) {
7334 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7337 #if defined(TARGET_PPC64)
7338 TCGv t0
= tcg_temp_new();
7339 TCGv t1
= tcg_temp_new();
7340 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
7341 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF0000000ULL
);
7342 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7346 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7347 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7350 static inline void gen_evmergelohi(DisasContext
*ctx
)
7352 if (unlikely(!ctx
->spe_enabled
)) {
7353 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7356 #if defined(TARGET_PPC64)
7357 TCGv t0
= tcg_temp_new();
7358 TCGv t1
= tcg_temp_new();
7359 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 32);
7360 tcg_gen_shli_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 32);
7361 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
7365 if (rD(ctx
->opcode
) == rA(ctx
->opcode
)) {
7366 TCGv_i32 tmp
= tcg_temp_new_i32();
7367 tcg_gen_mov_i32(tmp
, cpu_gpr
[rA(ctx
->opcode
)]);
7368 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7369 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], tmp
);
7370 tcg_temp_free_i32(tmp
);
7372 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7373 tcg_gen_mov_i32(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7377 static inline void gen_evsplati(DisasContext
*ctx
)
7379 uint64_t imm
= ((int32_t)(rA(ctx
->opcode
) << 27)) >> 27;
7381 #if defined(TARGET_PPC64)
7382 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
7384 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
7385 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
7388 static inline void gen_evsplatfi(DisasContext
*ctx
)
7390 uint64_t imm
= rA(ctx
->opcode
) << 27;
7392 #if defined(TARGET_PPC64)
7393 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], (imm
<< 32) | imm
);
7395 tcg_gen_movi_i32(cpu_gpr
[rD(ctx
->opcode
)], imm
);
7396 tcg_gen_movi_i32(cpu_gprh
[rD(ctx
->opcode
)], imm
);
7400 static inline void gen_evsel(DisasContext
*ctx
)
7402 int l1
= gen_new_label();
7403 int l2
= gen_new_label();
7404 int l3
= gen_new_label();
7405 int l4
= gen_new_label();
7406 TCGv_i32 t0
= tcg_temp_local_new_i32();
7407 #if defined(TARGET_PPC64)
7408 TCGv t1
= tcg_temp_local_new();
7409 TCGv t2
= tcg_temp_local_new();
7411 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 3);
7412 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
7413 #if defined(TARGET_PPC64)
7414 tcg_gen_andi_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
7416 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
7420 #if defined(TARGET_PPC64)
7421 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0xFFFFFFFF00000000ULL
);
7423 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
7426 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 2);
7427 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l3
);
7428 #if defined(TARGET_PPC64)
7429 tcg_gen_ext32u_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)]);
7431 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
7435 #if defined(TARGET_PPC64)
7436 tcg_gen_ext32u_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)]);
7438 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
7441 tcg_temp_free_i32(t0
);
7442 #if defined(TARGET_PPC64)
7443 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
, t2
);
7449 static void gen_evsel0(DisasContext
*ctx
)
7454 static void gen_evsel1(DisasContext
*ctx
)
7459 static void gen_evsel2(DisasContext
*ctx
)
7464 static void gen_evsel3(DisasContext
*ctx
)
7471 static inline void gen_evmwumi(DisasContext
*ctx
)
7475 if (unlikely(!ctx
->spe_enabled
)) {
7476 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7480 t0
= tcg_temp_new_i64();
7481 t1
= tcg_temp_new_i64();
7483 /* t0 := rA; t1 := rB */
7484 #if defined(TARGET_PPC64)
7485 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7486 tcg_gen_ext32u_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7488 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7489 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7492 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
7494 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
7496 tcg_temp_free_i64(t0
);
7497 tcg_temp_free_i64(t1
);
7500 static inline void gen_evmwumia(DisasContext
*ctx
)
7504 if (unlikely(!ctx
->spe_enabled
)) {
7505 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7509 gen_evmwumi(ctx
); /* rD := rA * rB */
7511 tmp
= tcg_temp_new_i64();
7514 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7515 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7516 tcg_temp_free_i64(tmp
);
7519 static inline void gen_evmwumiaa(DisasContext
*ctx
)
7524 if (unlikely(!ctx
->spe_enabled
)) {
7525 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7529 gen_evmwumi(ctx
); /* rD := rA * rB */
7531 acc
= tcg_temp_new_i64();
7532 tmp
= tcg_temp_new_i64();
7535 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7538 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7540 /* acc := tmp + acc */
7541 tcg_gen_add_i64(acc
, acc
, tmp
);
7544 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7547 gen_store_gpr64(rD(ctx
->opcode
), acc
);
7549 tcg_temp_free_i64(acc
);
7550 tcg_temp_free_i64(tmp
);
7553 static inline void gen_evmwsmi(DisasContext
*ctx
)
7557 if (unlikely(!ctx
->spe_enabled
)) {
7558 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
7562 t0
= tcg_temp_new_i64();
7563 t1
= tcg_temp_new_i64();
7565 /* t0 := rA; t1 := rB */
7566 #if defined(TARGET_PPC64)
7567 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7568 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7570 tcg_gen_ext_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
7571 tcg_gen_ext_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
7574 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
7576 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
7578 tcg_temp_free_i64(t0
);
7579 tcg_temp_free_i64(t1
);
7582 static inline void gen_evmwsmia(DisasContext
*ctx
)
7586 gen_evmwsmi(ctx
); /* rD := rA * rB */
7588 tmp
= tcg_temp_new_i64();
7591 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7592 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7594 tcg_temp_free_i64(tmp
);
7597 static inline void gen_evmwsmiaa(DisasContext
*ctx
)
7599 TCGv_i64 acc
= tcg_temp_new_i64();
7600 TCGv_i64 tmp
= tcg_temp_new_i64();
7602 gen_evmwsmi(ctx
); /* rD := rA * rB */
7604 acc
= tcg_temp_new_i64();
7605 tmp
= tcg_temp_new_i64();
7608 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
7611 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7613 /* acc := tmp + acc */
7614 tcg_gen_add_i64(acc
, acc
, tmp
);
7617 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
7620 gen_store_gpr64(rD(ctx
->opcode
), acc
);
7622 tcg_temp_free_i64(acc
);
7623 tcg_temp_free_i64(tmp
);
7626 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7627 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7628 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7629 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7630 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
7631 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
7632 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
7633 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
); //
7634 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
);
7635 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
7636 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7637 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7638 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7639 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
7640 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
7641 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
7642 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
7643 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7644 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7645 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
);
7646 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
7647 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
7648 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
); //
7649 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
);
7650 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7651 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
7652 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
7653 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
7654 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
); ////
7656 /* SPE load and stores */
7657 static inline void gen_addr_spe_imm_index(DisasContext
*ctx
, TCGv EA
, int sh
)
7659 target_ulong uimm
= rB(ctx
->opcode
);
7661 if (rA(ctx
->opcode
) == 0) {
7662 tcg_gen_movi_tl(EA
, uimm
<< sh
);
7664 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], uimm
<< sh
);
7665 #if defined(TARGET_PPC64)
7666 if (!ctx
->sf_mode
) {
7667 tcg_gen_ext32u_tl(EA
, EA
);
7673 static inline void gen_op_evldd(DisasContext
*ctx
, TCGv addr
)
7675 #if defined(TARGET_PPC64)
7676 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7678 TCGv_i64 t0
= tcg_temp_new_i64();
7679 gen_qemu_ld64(ctx
, t0
, addr
);
7680 tcg_gen_trunc_i64_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7681 tcg_gen_shri_i64(t0
, t0
, 32);
7682 tcg_gen_trunc_i64_i32(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7683 tcg_temp_free_i64(t0
);
7687 static inline void gen_op_evldw(DisasContext
*ctx
, TCGv addr
)
7689 #if defined(TARGET_PPC64)
7690 TCGv t0
= tcg_temp_new();
7691 gen_qemu_ld32u(ctx
, t0
, addr
);
7692 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7693 gen_addr_add(ctx
, addr
, addr
, 4);
7694 gen_qemu_ld32u(ctx
, t0
, addr
);
7695 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7698 gen_qemu_ld32u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7699 gen_addr_add(ctx
, addr
, addr
, 4);
7700 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7704 static inline void gen_op_evldh(DisasContext
*ctx
, TCGv addr
)
7706 TCGv t0
= tcg_temp_new();
7707 #if defined(TARGET_PPC64)
7708 gen_qemu_ld16u(ctx
, t0
, addr
);
7709 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7710 gen_addr_add(ctx
, addr
, addr
, 2);
7711 gen_qemu_ld16u(ctx
, t0
, addr
);
7712 tcg_gen_shli_tl(t0
, t0
, 32);
7713 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7714 gen_addr_add(ctx
, addr
, addr
, 2);
7715 gen_qemu_ld16u(ctx
, t0
, addr
);
7716 tcg_gen_shli_tl(t0
, t0
, 16);
7717 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7718 gen_addr_add(ctx
, addr
, addr
, 2);
7719 gen_qemu_ld16u(ctx
, t0
, addr
);
7720 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7722 gen_qemu_ld16u(ctx
, t0
, addr
);
7723 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7724 gen_addr_add(ctx
, addr
, addr
, 2);
7725 gen_qemu_ld16u(ctx
, t0
, addr
);
7726 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7727 gen_addr_add(ctx
, addr
, addr
, 2);
7728 gen_qemu_ld16u(ctx
, t0
, addr
);
7729 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7730 gen_addr_add(ctx
, addr
, addr
, 2);
7731 gen_qemu_ld16u(ctx
, t0
, addr
);
7732 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7737 static inline void gen_op_evlhhesplat(DisasContext
*ctx
, TCGv addr
)
7739 TCGv t0
= tcg_temp_new();
7740 gen_qemu_ld16u(ctx
, t0
, addr
);
7741 #if defined(TARGET_PPC64)
7742 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7743 tcg_gen_shli_tl(t0
, t0
, 16);
7744 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7746 tcg_gen_shli_tl(t0
, t0
, 16);
7747 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7748 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7753 static inline void gen_op_evlhhousplat(DisasContext
*ctx
, TCGv addr
)
7755 TCGv t0
= tcg_temp_new();
7756 gen_qemu_ld16u(ctx
, t0
, addr
);
7757 #if defined(TARGET_PPC64)
7758 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7759 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7761 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7762 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7767 static inline void gen_op_evlhhossplat(DisasContext
*ctx
, TCGv addr
)
7769 TCGv t0
= tcg_temp_new();
7770 gen_qemu_ld16s(ctx
, t0
, addr
);
7771 #if defined(TARGET_PPC64)
7772 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7773 tcg_gen_ext32u_tl(t0
, t0
);
7774 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7776 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7777 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7782 static inline void gen_op_evlwhe(DisasContext
*ctx
, TCGv addr
)
7784 TCGv t0
= tcg_temp_new();
7785 #if defined(TARGET_PPC64)
7786 gen_qemu_ld16u(ctx
, t0
, addr
);
7787 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7788 gen_addr_add(ctx
, addr
, addr
, 2);
7789 gen_qemu_ld16u(ctx
, t0
, addr
);
7790 tcg_gen_shli_tl(t0
, t0
, 16);
7791 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7793 gen_qemu_ld16u(ctx
, t0
, addr
);
7794 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7795 gen_addr_add(ctx
, addr
, addr
, 2);
7796 gen_qemu_ld16u(ctx
, t0
, addr
);
7797 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
7802 static inline void gen_op_evlwhou(DisasContext
*ctx
, TCGv addr
)
7804 #if defined(TARGET_PPC64)
7805 TCGv t0
= tcg_temp_new();
7806 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7807 gen_addr_add(ctx
, addr
, addr
, 2);
7808 gen_qemu_ld16u(ctx
, t0
, addr
);
7809 tcg_gen_shli_tl(t0
, t0
, 32);
7810 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7813 gen_qemu_ld16u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7814 gen_addr_add(ctx
, addr
, addr
, 2);
7815 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7819 static inline void gen_op_evlwhos(DisasContext
*ctx
, TCGv addr
)
7821 #if defined(TARGET_PPC64)
7822 TCGv t0
= tcg_temp_new();
7823 gen_qemu_ld16s(ctx
, t0
, addr
);
7824 tcg_gen_ext32u_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7825 gen_addr_add(ctx
, addr
, addr
, 2);
7826 gen_qemu_ld16s(ctx
, t0
, addr
);
7827 tcg_gen_shli_tl(t0
, t0
, 32);
7828 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7831 gen_qemu_ld16s(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
7832 gen_addr_add(ctx
, addr
, addr
, 2);
7833 gen_qemu_ld16s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
7837 static inline void gen_op_evlwwsplat(DisasContext
*ctx
, TCGv addr
)
7839 TCGv t0
= tcg_temp_new();
7840 gen_qemu_ld32u(ctx
, t0
, addr
);
7841 #if defined(TARGET_PPC64)
7842 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 32);
7843 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7845 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
7846 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
7851 static inline void gen_op_evlwhsplat(DisasContext
*ctx
, TCGv addr
)
7853 TCGv t0
= tcg_temp_new();
7854 #if defined(TARGET_PPC64)
7855 gen_qemu_ld16u(ctx
, t0
, addr
);
7856 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 48);
7857 tcg_gen_shli_tl(t0
, t0
, 32);
7858 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7859 gen_addr_add(ctx
, addr
, addr
, 2);
7860 gen_qemu_ld16u(ctx
, t0
, addr
);
7861 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7862 tcg_gen_shli_tl(t0
, t0
, 16);
7863 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
7865 gen_qemu_ld16u(ctx
, t0
, addr
);
7866 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
7867 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7868 gen_addr_add(ctx
, addr
, addr
, 2);
7869 gen_qemu_ld16u(ctx
, t0
, addr
);
7870 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
7871 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
7876 static inline void gen_op_evstdd(DisasContext
*ctx
, TCGv addr
)
7878 #if defined(TARGET_PPC64)
7879 gen_qemu_st64(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7881 TCGv_i64 t0
= tcg_temp_new_i64();
7882 tcg_gen_concat_i32_i64(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gprh
[rS(ctx
->opcode
)]);
7883 gen_qemu_st64(ctx
, t0
, addr
);
7884 tcg_temp_free_i64(t0
);
7888 static inline void gen_op_evstdw(DisasContext
*ctx
, TCGv addr
)
7890 #if defined(TARGET_PPC64)
7891 TCGv t0
= tcg_temp_new();
7892 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7893 gen_qemu_st32(ctx
, t0
, addr
);
7896 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7898 gen_addr_add(ctx
, addr
, addr
, 4);
7899 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7902 static inline void gen_op_evstdh(DisasContext
*ctx
, TCGv addr
)
7904 TCGv t0
= tcg_temp_new();
7905 #if defined(TARGET_PPC64)
7906 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
7908 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
7910 gen_qemu_st16(ctx
, t0
, addr
);
7911 gen_addr_add(ctx
, addr
, addr
, 2);
7912 #if defined(TARGET_PPC64)
7913 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7914 gen_qemu_st16(ctx
, t0
, addr
);
7916 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7918 gen_addr_add(ctx
, addr
, addr
, 2);
7919 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
7920 gen_qemu_st16(ctx
, t0
, addr
);
7922 gen_addr_add(ctx
, addr
, addr
, 2);
7923 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7926 static inline void gen_op_evstwhe(DisasContext
*ctx
, TCGv addr
)
7928 TCGv t0
= tcg_temp_new();
7929 #if defined(TARGET_PPC64)
7930 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 48);
7932 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
7934 gen_qemu_st16(ctx
, t0
, addr
);
7935 gen_addr_add(ctx
, addr
, addr
, 2);
7936 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
7937 gen_qemu_st16(ctx
, t0
, addr
);
7941 static inline void gen_op_evstwho(DisasContext
*ctx
, TCGv addr
)
7943 #if defined(TARGET_PPC64)
7944 TCGv t0
= tcg_temp_new();
7945 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7946 gen_qemu_st16(ctx
, t0
, addr
);
7949 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7951 gen_addr_add(ctx
, addr
, addr
, 2);
7952 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7955 static inline void gen_op_evstwwe(DisasContext
*ctx
, TCGv addr
)
7957 #if defined(TARGET_PPC64)
7958 TCGv t0
= tcg_temp_new();
7959 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 32);
7960 gen_qemu_st32(ctx
, t0
, addr
);
7963 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
7967 static inline void gen_op_evstwwo(DisasContext
*ctx
, TCGv addr
)
7969 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
7972 #define GEN_SPEOP_LDST(name, opc2, sh) \
7973 static void glue(gen_, name)(DisasContext *ctx) \
7976 if (unlikely(!ctx->spe_enabled)) { \
7977 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7980 gen_set_access_type(ctx, ACCESS_INT); \
7981 t0 = tcg_temp_new(); \
7982 if (Rc(ctx->opcode)) { \
7983 gen_addr_spe_imm_index(ctx, t0, sh); \
7985 gen_addr_reg_index(ctx, t0); \
7987 gen_op_##name(ctx, t0); \
7988 tcg_temp_free(t0); \
7991 GEN_SPEOP_LDST(evldd
, 0x00, 3);
7992 GEN_SPEOP_LDST(evldw
, 0x01, 3);
7993 GEN_SPEOP_LDST(evldh
, 0x02, 3);
7994 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1);
7995 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1);
7996 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1);
7997 GEN_SPEOP_LDST(evlwhe
, 0x08, 2);
7998 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2);
7999 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2);
8000 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2);
8001 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2);
8003 GEN_SPEOP_LDST(evstdd
, 0x10, 3);
8004 GEN_SPEOP_LDST(evstdw
, 0x11, 3);
8005 GEN_SPEOP_LDST(evstdh
, 0x12, 3);
8006 GEN_SPEOP_LDST(evstwhe
, 0x18, 2);
8007 GEN_SPEOP_LDST(evstwho
, 0x1A, 2);
8008 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2);
8009 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2);
8011 /* Multiply and add - TODO */
8013 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);//
8014 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8015 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8016 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8017 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8018 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8019 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8020 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8021 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8022 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8023 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
8024 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8026 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8027 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
8028 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
8029 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8030 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8031 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8032 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8033 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
8034 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
8035 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8036 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8037 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8039 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8040 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8041 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8042 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
8043 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE
);
8045 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8046 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8047 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8048 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8049 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8050 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8051 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8052 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8053 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8054 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8055 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
8056 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8058 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
8059 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
8060 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8061 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8063 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8064 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8065 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8066 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8067 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8068 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8069 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8070 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8071 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8072 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8073 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
8074 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8076 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
8077 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
8078 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8079 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
8080 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
8083 /*** SPE floating-point extension ***/
8084 #if defined(TARGET_PPC64)
8085 #define GEN_SPEFPUOP_CONV_32_32(name) \
8086 static inline void gen_##name(DisasContext *ctx) \
8090 t0 = tcg_temp_new_i32(); \
8091 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8092 gen_helper_##name(t0, cpu_env, t0); \
8093 t1 = tcg_temp_new(); \
8094 tcg_gen_extu_i32_tl(t1, t0); \
8095 tcg_temp_free_i32(t0); \
8096 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8097 0xFFFFFFFF00000000ULL); \
8098 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8099 tcg_temp_free(t1); \
8101 #define GEN_SPEFPUOP_CONV_32_64(name) \
8102 static inline void gen_##name(DisasContext *ctx) \
8106 t0 = tcg_temp_new_i32(); \
8107 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8108 t1 = tcg_temp_new(); \
8109 tcg_gen_extu_i32_tl(t1, t0); \
8110 tcg_temp_free_i32(t0); \
8111 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8112 0xFFFFFFFF00000000ULL); \
8113 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8114 tcg_temp_free(t1); \
8116 #define GEN_SPEFPUOP_CONV_64_32(name) \
8117 static inline void gen_##name(DisasContext *ctx) \
8119 TCGv_i32 t0 = tcg_temp_new_i32(); \
8120 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8121 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8122 tcg_temp_free_i32(t0); \
8124 #define GEN_SPEFPUOP_CONV_64_64(name) \
8125 static inline void gen_##name(DisasContext *ctx) \
8127 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8128 cpu_gpr[rB(ctx->opcode)]); \
8130 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8131 static inline void gen_##name(DisasContext *ctx) \
8135 if (unlikely(!ctx->spe_enabled)) { \
8136 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8139 t0 = tcg_temp_new_i32(); \
8140 t1 = tcg_temp_new_i32(); \
8141 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8142 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8143 gen_helper_##name(t0, cpu_env, t0, t1); \
8144 tcg_temp_free_i32(t1); \
8145 t2 = tcg_temp_new(); \
8146 tcg_gen_extu_i32_tl(t2, t0); \
8147 tcg_temp_free_i32(t0); \
8148 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8149 0xFFFFFFFF00000000ULL); \
8150 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8151 tcg_temp_free(t2); \
8153 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8154 static inline void gen_##name(DisasContext *ctx) \
8156 if (unlikely(!ctx->spe_enabled)) { \
8157 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8160 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8161 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8163 #define GEN_SPEFPUOP_COMP_32(name) \
8164 static inline void gen_##name(DisasContext *ctx) \
8167 if (unlikely(!ctx->spe_enabled)) { \
8168 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8171 t0 = tcg_temp_new_i32(); \
8172 t1 = tcg_temp_new_i32(); \
8173 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8174 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8175 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8176 tcg_temp_free_i32(t0); \
8177 tcg_temp_free_i32(t1); \
8179 #define GEN_SPEFPUOP_COMP_64(name) \
8180 static inline void gen_##name(DisasContext *ctx) \
8182 if (unlikely(!ctx->spe_enabled)) { \
8183 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8186 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8187 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8190 #define GEN_SPEFPUOP_CONV_32_32(name) \
8191 static inline void gen_##name(DisasContext *ctx) \
8193 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8194 cpu_gpr[rB(ctx->opcode)]); \
8196 #define GEN_SPEFPUOP_CONV_32_64(name) \
8197 static inline void gen_##name(DisasContext *ctx) \
8199 TCGv_i64 t0 = tcg_temp_new_i64(); \
8200 gen_load_gpr64(t0, rB(ctx->opcode)); \
8201 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8202 tcg_temp_free_i64(t0); \
8204 #define GEN_SPEFPUOP_CONV_64_32(name) \
8205 static inline void gen_##name(DisasContext *ctx) \
8207 TCGv_i64 t0 = tcg_temp_new_i64(); \
8208 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8209 gen_store_gpr64(rD(ctx->opcode), t0); \
8210 tcg_temp_free_i64(t0); \
8212 #define GEN_SPEFPUOP_CONV_64_64(name) \
8213 static inline void gen_##name(DisasContext *ctx) \
8215 TCGv_i64 t0 = tcg_temp_new_i64(); \
8216 gen_load_gpr64(t0, rB(ctx->opcode)); \
8217 gen_helper_##name(t0, cpu_env, t0); \
8218 gen_store_gpr64(rD(ctx->opcode), t0); \
8219 tcg_temp_free_i64(t0); \
8221 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8222 static inline void gen_##name(DisasContext *ctx) \
8224 if (unlikely(!ctx->spe_enabled)) { \
8225 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8228 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8229 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8231 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8232 static inline void gen_##name(DisasContext *ctx) \
8235 if (unlikely(!ctx->spe_enabled)) { \
8236 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8239 t0 = tcg_temp_new_i64(); \
8240 t1 = tcg_temp_new_i64(); \
8241 gen_load_gpr64(t0, rA(ctx->opcode)); \
8242 gen_load_gpr64(t1, rB(ctx->opcode)); \
8243 gen_helper_##name(t0, cpu_env, t0, t1); \
8244 gen_store_gpr64(rD(ctx->opcode), t0); \
8245 tcg_temp_free_i64(t0); \
8246 tcg_temp_free_i64(t1); \
8248 #define GEN_SPEFPUOP_COMP_32(name) \
8249 static inline void gen_##name(DisasContext *ctx) \
8251 if (unlikely(!ctx->spe_enabled)) { \
8252 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8255 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8256 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8258 #define GEN_SPEFPUOP_COMP_64(name) \
8259 static inline void gen_##name(DisasContext *ctx) \
8262 if (unlikely(!ctx->spe_enabled)) { \
8263 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8266 t0 = tcg_temp_new_i64(); \
8267 t1 = tcg_temp_new_i64(); \
8268 gen_load_gpr64(t0, rA(ctx->opcode)); \
8269 gen_load_gpr64(t1, rB(ctx->opcode)); \
8270 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8271 tcg_temp_free_i64(t0); \
8272 tcg_temp_free_i64(t1); \
8276 /* Single precision floating-point vectors operations */
8278 GEN_SPEFPUOP_ARITH2_64_64(evfsadd
);
8279 GEN_SPEFPUOP_ARITH2_64_64(evfssub
);
8280 GEN_SPEFPUOP_ARITH2_64_64(evfsmul
);
8281 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv
);
8282 static inline void gen_evfsabs(DisasContext
*ctx
)
8284 if (unlikely(!ctx
->spe_enabled
)) {
8285 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8288 #if defined(TARGET_PPC64)
8289 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000080000000LL
);
8291 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x80000000);
8292 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
8295 static inline void gen_evfsnabs(DisasContext
*ctx
)
8297 if (unlikely(!ctx
->spe_enabled
)) {
8298 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8301 #if defined(TARGET_PPC64)
8302 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
8304 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8305 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8308 static inline void gen_evfsneg(DisasContext
*ctx
)
8310 if (unlikely(!ctx
->spe_enabled
)) {
8311 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8314 #if defined(TARGET_PPC64)
8315 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000080000000LL
);
8317 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8318 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8323 GEN_SPEFPUOP_CONV_64_64(evfscfui
);
8324 GEN_SPEFPUOP_CONV_64_64(evfscfsi
);
8325 GEN_SPEFPUOP_CONV_64_64(evfscfuf
);
8326 GEN_SPEFPUOP_CONV_64_64(evfscfsf
);
8327 GEN_SPEFPUOP_CONV_64_64(evfsctui
);
8328 GEN_SPEFPUOP_CONV_64_64(evfsctsi
);
8329 GEN_SPEFPUOP_CONV_64_64(evfsctuf
);
8330 GEN_SPEFPUOP_CONV_64_64(evfsctsf
);
8331 GEN_SPEFPUOP_CONV_64_64(evfsctuiz
);
8332 GEN_SPEFPUOP_CONV_64_64(evfsctsiz
);
8335 GEN_SPEFPUOP_COMP_64(evfscmpgt
);
8336 GEN_SPEFPUOP_COMP_64(evfscmplt
);
8337 GEN_SPEFPUOP_COMP_64(evfscmpeq
);
8338 GEN_SPEFPUOP_COMP_64(evfststgt
);
8339 GEN_SPEFPUOP_COMP_64(evfststlt
);
8340 GEN_SPEFPUOP_COMP_64(evfststeq
);
8342 /* Opcodes definitions */
8343 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8344 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
8345 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8346 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8347 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8348 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8349 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8350 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8351 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8352 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8353 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8354 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8355 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8356 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8358 /* Single precision floating-point operations */
8360 GEN_SPEFPUOP_ARITH2_32_32(efsadd
);
8361 GEN_SPEFPUOP_ARITH2_32_32(efssub
);
8362 GEN_SPEFPUOP_ARITH2_32_32(efsmul
);
8363 GEN_SPEFPUOP_ARITH2_32_32(efsdiv
);
8364 static inline void gen_efsabs(DisasContext
*ctx
)
8366 if (unlikely(!ctx
->spe_enabled
)) {
8367 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8370 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], (target_long
)~0x80000000LL
);
8372 static inline void gen_efsnabs(DisasContext
*ctx
)
8374 if (unlikely(!ctx
->spe_enabled
)) {
8375 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8378 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8380 static inline void gen_efsneg(DisasContext
*ctx
)
8382 if (unlikely(!ctx
->spe_enabled
)) {
8383 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8386 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
8390 GEN_SPEFPUOP_CONV_32_32(efscfui
);
8391 GEN_SPEFPUOP_CONV_32_32(efscfsi
);
8392 GEN_SPEFPUOP_CONV_32_32(efscfuf
);
8393 GEN_SPEFPUOP_CONV_32_32(efscfsf
);
8394 GEN_SPEFPUOP_CONV_32_32(efsctui
);
8395 GEN_SPEFPUOP_CONV_32_32(efsctsi
);
8396 GEN_SPEFPUOP_CONV_32_32(efsctuf
);
8397 GEN_SPEFPUOP_CONV_32_32(efsctsf
);
8398 GEN_SPEFPUOP_CONV_32_32(efsctuiz
);
8399 GEN_SPEFPUOP_CONV_32_32(efsctsiz
);
8400 GEN_SPEFPUOP_CONV_32_64(efscfd
);
8403 GEN_SPEFPUOP_COMP_32(efscmpgt
);
8404 GEN_SPEFPUOP_COMP_32(efscmplt
);
8405 GEN_SPEFPUOP_COMP_32(efscmpeq
);
8406 GEN_SPEFPUOP_COMP_32(efststgt
);
8407 GEN_SPEFPUOP_COMP_32(efststlt
);
8408 GEN_SPEFPUOP_COMP_32(efststeq
);
8410 /* Opcodes definitions */
8411 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8412 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
8413 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8414 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
8415 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8416 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
); //
8417 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8418 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8419 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8420 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
8421 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8422 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8423 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
8424 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
8426 /* Double precision floating-point operations */
8428 GEN_SPEFPUOP_ARITH2_64_64(efdadd
);
8429 GEN_SPEFPUOP_ARITH2_64_64(efdsub
);
8430 GEN_SPEFPUOP_ARITH2_64_64(efdmul
);
8431 GEN_SPEFPUOP_ARITH2_64_64(efddiv
);
8432 static inline void gen_efdabs(DisasContext
*ctx
)
8434 if (unlikely(!ctx
->spe_enabled
)) {
8435 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8438 #if defined(TARGET_PPC64)
8439 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~0x8000000000000000LL
);
8441 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8442 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], ~0x80000000);
8445 static inline void gen_efdnabs(DisasContext
*ctx
)
8447 if (unlikely(!ctx
->spe_enabled
)) {
8448 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8451 #if defined(TARGET_PPC64)
8452 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
8454 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8455 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8458 static inline void gen_efdneg(DisasContext
*ctx
)
8460 if (unlikely(!ctx
->spe_enabled
)) {
8461 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8464 #if defined(TARGET_PPC64)
8465 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x8000000000000000LL
);
8467 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8468 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)], 0x80000000);
8473 GEN_SPEFPUOP_CONV_64_32(efdcfui
);
8474 GEN_SPEFPUOP_CONV_64_32(efdcfsi
);
8475 GEN_SPEFPUOP_CONV_64_32(efdcfuf
);
8476 GEN_SPEFPUOP_CONV_64_32(efdcfsf
);
8477 GEN_SPEFPUOP_CONV_32_64(efdctui
);
8478 GEN_SPEFPUOP_CONV_32_64(efdctsi
);
8479 GEN_SPEFPUOP_CONV_32_64(efdctuf
);
8480 GEN_SPEFPUOP_CONV_32_64(efdctsf
);
8481 GEN_SPEFPUOP_CONV_32_64(efdctuiz
);
8482 GEN_SPEFPUOP_CONV_32_64(efdctsiz
);
8483 GEN_SPEFPUOP_CONV_64_32(efdcfs
);
8484 GEN_SPEFPUOP_CONV_64_64(efdcfuid
);
8485 GEN_SPEFPUOP_CONV_64_64(efdcfsid
);
8486 GEN_SPEFPUOP_CONV_64_64(efdctuidz
);
8487 GEN_SPEFPUOP_CONV_64_64(efdctsidz
);
8490 GEN_SPEFPUOP_COMP_64(efdcmpgt
);
8491 GEN_SPEFPUOP_COMP_64(efdcmplt
);
8492 GEN_SPEFPUOP_COMP_64(efdcmpeq
);
8493 GEN_SPEFPUOP_COMP_64(efdtstgt
);
8494 GEN_SPEFPUOP_COMP_64(efdtstlt
);
8495 GEN_SPEFPUOP_COMP_64(efdtsteq
);
8497 /* Opcodes definitions */
8498 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
8499 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8500 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
); //
8501 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8502 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
8503 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8504 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
8505 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
); //
8506 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8507 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8508 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8509 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
8510 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8511 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8512 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
8513 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
8515 static opcode_t opcodes
[] = {
8516 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
8517 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
8518 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
8519 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
),
8520 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
8521 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
8522 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8523 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8524 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8525 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8526 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
8527 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
8528 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
8529 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
8530 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8531 #if defined(TARGET_PPC64)
8532 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
8534 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
8535 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
8536 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8537 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8538 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8539 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
8540 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
8541 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
8542 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8543 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8544 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8545 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8546 GEN_HANDLER(popcntb
, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB
),
8547 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
8548 #if defined(TARGET_PPC64)
8549 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
8550 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
8552 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8553 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8554 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8555 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
8556 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
8557 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
8558 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
8559 #if defined(TARGET_PPC64)
8560 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
8561 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
8562 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
8563 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
8564 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
8566 GEN_HANDLER(frsqrtes
, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES
),
8567 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
8568 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
8569 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
),
8570 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
),
8571 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
),
8572 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
),
8573 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
),
8574 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
),
8575 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
),
8576 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT
),
8577 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT
),
8578 #if defined(TARGET_PPC64)
8579 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
8580 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
8581 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
8583 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8584 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
8585 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
8586 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
8587 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
8588 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
8589 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
),
8590 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
8591 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
8592 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
8593 #if defined(TARGET_PPC64)
8594 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
8595 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
8597 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
8598 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
8599 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
8600 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
8601 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
8602 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
8603 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
8604 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
8605 #if defined(TARGET_PPC64)
8606 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
8607 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
8609 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
8610 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
8611 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
8612 #if defined(TARGET_PPC64)
8613 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
8614 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
8616 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
8617 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
8618 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
8619 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
8620 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
8621 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
8622 #if defined(TARGET_PPC64)
8623 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
8625 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC
),
8626 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC
),
8627 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
8628 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
8629 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
8630 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE
),
8631 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE
),
8632 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ
),
8633 GEN_HANDLER2(dcbz_970
, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT
),
8634 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
8635 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
),
8636 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
8637 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
8638 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
8639 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
8640 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
8641 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
8642 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
8643 #if defined(TARGET_PPC64)
8644 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
8645 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8647 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
8648 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8650 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
8651 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
8652 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
8654 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
8655 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE
),
8656 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE
),
8657 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
8658 #if defined(TARGET_PPC64)
8659 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI
),
8660 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
8662 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
8663 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
8664 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
8665 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
8666 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
8667 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
8668 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
8669 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
8670 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
8671 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
8672 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
8673 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
8674 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
8675 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
8676 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
8677 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
8678 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
8679 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
8680 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
8681 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
8682 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
8683 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
8684 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
8685 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
8686 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
8687 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
8688 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
8689 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
8690 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
8691 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
8692 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
8693 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
8694 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
8695 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
8696 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
8697 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
8698 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
8699 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
8700 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
8701 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
8702 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
8703 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
8704 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
8705 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
8706 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
8707 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
8708 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
8709 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
8710 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
8711 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8712 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8713 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
8714 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
8715 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8716 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
8717 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
8718 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
8719 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
8720 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
8721 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
8722 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
8723 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
8724 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
8725 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
8726 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
8727 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
8728 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
8729 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
8730 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
8731 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
8732 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
8733 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
8734 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
8735 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
8736 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
8737 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
8738 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
8739 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
8740 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
8741 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
8742 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8743 PPC_NONE
, PPC2_BOOKE206
),
8744 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8745 PPC_NONE
, PPC2_BOOKE206
),
8746 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8747 PPC_NONE
, PPC2_BOOKE206
),
8748 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8749 PPC_NONE
, PPC2_BOOKE206
),
8750 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8751 PPC_NONE
, PPC2_BOOKE206
),
8752 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8753 PPC_NONE
, PPC2_PRCNTL
),
8754 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8755 PPC_NONE
, PPC2_PRCNTL
),
8756 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
8757 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
8758 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
8759 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
8760 PPC_BOOKE
, PPC2_BOOKE206
),
8761 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
8762 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8763 PPC_BOOKE
, PPC2_BOOKE206
),
8764 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
8765 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
8766 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
8767 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
8768 GEN_HANDLER(vsldoi
, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC
),
8769 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
8770 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
),
8771 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
),
8772 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
),
8773 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
),
8775 #undef GEN_INT_ARITH_ADD
8776 #undef GEN_INT_ARITH_ADD_CONST
8777 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8778 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8779 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8780 add_ca, compute_ca, compute_ov) \
8781 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8782 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
8783 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
8784 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
8785 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
8786 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
8787 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
8788 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
8789 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
8790 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
8791 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
8793 #undef GEN_INT_ARITH_DIVW
8794 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8795 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8796 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
8797 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
8798 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
8799 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
8801 #if defined(TARGET_PPC64)
8802 #undef GEN_INT_ARITH_DIVD
8803 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8804 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8805 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
8806 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
8807 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
8808 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
8810 #undef GEN_INT_ARITH_MUL_HELPER
8811 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8812 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8813 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
8814 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
8815 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
8818 #undef GEN_INT_ARITH_SUBF
8819 #undef GEN_INT_ARITH_SUBF_CONST
8820 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8821 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8822 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8823 add_ca, compute_ca, compute_ov) \
8824 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8825 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
8826 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
8827 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
8828 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
8829 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
8830 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
8831 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
8832 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
8833 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
8834 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
8838 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8839 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8840 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8841 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8842 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
8843 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
8844 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
8845 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
8846 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
8847 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
8848 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
8849 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
8850 #if defined(TARGET_PPC64)
8851 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
8854 #if defined(TARGET_PPC64)
8857 #define GEN_PPC64_R2(name, opc1, opc2) \
8858 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8859 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8861 #define GEN_PPC64_R4(name, opc1, opc2) \
8862 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8863 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8865 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8867 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8869 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
8870 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
8871 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
8872 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
8873 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
8874 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
8877 #undef _GEN_FLOAT_ACB
8878 #undef GEN_FLOAT_ACB
8879 #undef _GEN_FLOAT_AB
8881 #undef _GEN_FLOAT_AC
8885 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8886 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8887 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8888 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8889 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8890 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8891 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8892 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8893 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8894 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8895 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8896 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8897 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8898 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8899 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8900 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8901 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8902 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8903 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8905 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
),
8906 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
),
8907 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
),
8908 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
),
8909 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
),
8910 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
),
8911 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
),
8912 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
),
8913 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
),
8914 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
),
8915 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
),
8916 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
),
8917 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
),
8918 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
),
8919 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
),
8920 #if defined(TARGET_PPC64)
8921 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC_64B
),
8922 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC_64B
),
8923 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC_64B
),
8925 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
),
8926 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
),
8927 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
),
8928 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
),
8929 GEN_FLOAT_B(abs
, 0x08, 0x08, 0, PPC_FLOAT
),
8930 GEN_FLOAT_B(nabs
, 0x08, 0x04, 0, PPC_FLOAT
),
8931 GEN_FLOAT_B(neg
, 0x08, 0x01, 0, PPC_FLOAT
),
8938 #define GEN_LD(name, ldop, opc, type) \
8939 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8940 #define GEN_LDU(name, ldop, opc, type) \
8941 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8942 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8943 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8944 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8945 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8946 #define GEN_LDS(name, ldop, op, type) \
8947 GEN_LD(name, ldop, op | 0x20, type) \
8948 GEN_LDU(name, ldop, op | 0x21, type) \
8949 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8950 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8952 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
8953 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
8954 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
8955 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
8956 #if defined(TARGET_PPC64)
8957 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
8958 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
8959 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
)
8960 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
)
8961 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
)
8963 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
8964 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
8971 #define GEN_ST(name, stop, opc, type) \
8972 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8973 #define GEN_STU(name, stop, opc, type) \
8974 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8975 #define GEN_STUX(name, stop, opc2, opc3, type) \
8976 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8977 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8978 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8979 #define GEN_STS(name, stop, op, type) \
8980 GEN_ST(name, stop, op | 0x20, type) \
8981 GEN_STU(name, stop, op | 0x21, type) \
8982 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8983 GEN_STX(name, stop, 0x17, op | 0x00, type)
8985 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
8986 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
8987 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
8988 #if defined(TARGET_PPC64)
8989 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
)
8990 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
)
8991 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
)
8993 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
8994 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
9001 #define GEN_LDF(name, ldop, opc, type) \
9002 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9003 #define GEN_LDUF(name, ldop, opc, type) \
9004 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9005 #define GEN_LDUXF(name, ldop, opc, type) \
9006 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9007 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9008 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9009 #define GEN_LDFS(name, ldop, op, type) \
9010 GEN_LDF(name, ldop, op | 0x20, type) \
9011 GEN_LDUF(name, ldop, op | 0x21, type) \
9012 GEN_LDUXF(name, ldop, op | 0x01, type) \
9013 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9015 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
)
9016 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
)
9023 #define GEN_STF(name, stop, opc, type) \
9024 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9025 #define GEN_STUF(name, stop, opc, type) \
9026 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9027 #define GEN_STUXF(name, stop, opc, type) \
9028 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9029 #define GEN_STXF(name, stop, opc2, opc3, type) \
9030 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9031 #define GEN_STFS(name, stop, op, type) \
9032 GEN_STF(name, stop, op | 0x20, type) \
9033 GEN_STUF(name, stop, op | 0x21, type) \
9034 GEN_STUXF(name, stop, op | 0x01, type) \
9035 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9037 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
)
9038 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
)
9039 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
)
9042 #define GEN_CRLOGIC(name, tcg_op, opc) \
9043 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9044 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
9045 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
9046 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
9047 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
9048 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
9049 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
9050 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
9051 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
9053 #undef GEN_MAC_HANDLER
9054 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9055 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9056 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
9057 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
9058 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
9059 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
9060 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
9061 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
9062 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
9063 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
9064 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
9065 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
9066 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
9067 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
9068 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
9069 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
9070 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
9071 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
9072 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
9073 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
9074 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
9075 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
9076 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
9077 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
9078 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
9079 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
9080 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
9081 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
9082 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
9083 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
9084 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
9085 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
9086 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
9087 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
9088 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
9089 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
9090 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
9091 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
9092 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
9093 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
9094 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
9095 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
9096 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
9097 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
9103 #define GEN_VR_LDX(name, opc2, opc3) \
9104 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9105 #define GEN_VR_STX(name, opc2, opc3) \
9106 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9107 #define GEN_VR_LVE(name, opc2, opc3) \
9108 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9109 #define GEN_VR_STVE(name, opc2, opc3) \
9110 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9111 GEN_VR_LDX(lvx
, 0x07, 0x03),
9112 GEN_VR_LDX(lvxl
, 0x07, 0x0B),
9113 GEN_VR_LVE(bx
, 0x07, 0x00),
9114 GEN_VR_LVE(hx
, 0x07, 0x01),
9115 GEN_VR_LVE(wx
, 0x07, 0x02),
9116 GEN_VR_STX(svx
, 0x07, 0x07),
9117 GEN_VR_STX(svxl
, 0x07, 0x0F),
9118 GEN_VR_STVE(bx
, 0x07, 0x04),
9119 GEN_VR_STVE(hx
, 0x07, 0x05),
9120 GEN_VR_STVE(wx
, 0x07, 0x06),
9122 #undef GEN_VX_LOGICAL
9123 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9124 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9125 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16),
9126 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17),
9127 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18),
9128 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19),
9129 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20),
9132 #define GEN_VXFORM(name, opc2, opc3) \
9133 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9134 GEN_VXFORM(vaddubm
, 0, 0),
9135 GEN_VXFORM(vadduhm
, 0, 1),
9136 GEN_VXFORM(vadduwm
, 0, 2),
9137 GEN_VXFORM(vsububm
, 0, 16),
9138 GEN_VXFORM(vsubuhm
, 0, 17),
9139 GEN_VXFORM(vsubuwm
, 0, 18),
9140 GEN_VXFORM(vmaxub
, 1, 0),
9141 GEN_VXFORM(vmaxuh
, 1, 1),
9142 GEN_VXFORM(vmaxuw
, 1, 2),
9143 GEN_VXFORM(vmaxsb
, 1, 4),
9144 GEN_VXFORM(vmaxsh
, 1, 5),
9145 GEN_VXFORM(vmaxsw
, 1, 6),
9146 GEN_VXFORM(vminub
, 1, 8),
9147 GEN_VXFORM(vminuh
, 1, 9),
9148 GEN_VXFORM(vminuw
, 1, 10),
9149 GEN_VXFORM(vminsb
, 1, 12),
9150 GEN_VXFORM(vminsh
, 1, 13),
9151 GEN_VXFORM(vminsw
, 1, 14),
9152 GEN_VXFORM(vavgub
, 1, 16),
9153 GEN_VXFORM(vavguh
, 1, 17),
9154 GEN_VXFORM(vavguw
, 1, 18),
9155 GEN_VXFORM(vavgsb
, 1, 20),
9156 GEN_VXFORM(vavgsh
, 1, 21),
9157 GEN_VXFORM(vavgsw
, 1, 22),
9158 GEN_VXFORM(vmrghb
, 6, 0),
9159 GEN_VXFORM(vmrghh
, 6, 1),
9160 GEN_VXFORM(vmrghw
, 6, 2),
9161 GEN_VXFORM(vmrglb
, 6, 4),
9162 GEN_VXFORM(vmrglh
, 6, 5),
9163 GEN_VXFORM(vmrglw
, 6, 6),
9164 GEN_VXFORM(vmuloub
, 4, 0),
9165 GEN_VXFORM(vmulouh
, 4, 1),
9166 GEN_VXFORM(vmulosb
, 4, 4),
9167 GEN_VXFORM(vmulosh
, 4, 5),
9168 GEN_VXFORM(vmuleub
, 4, 8),
9169 GEN_VXFORM(vmuleuh
, 4, 9),
9170 GEN_VXFORM(vmulesb
, 4, 12),
9171 GEN_VXFORM(vmulesh
, 4, 13),
9172 GEN_VXFORM(vslb
, 2, 4),
9173 GEN_VXFORM(vslh
, 2, 5),
9174 GEN_VXFORM(vslw
, 2, 6),
9175 GEN_VXFORM(vsrb
, 2, 8),
9176 GEN_VXFORM(vsrh
, 2, 9),
9177 GEN_VXFORM(vsrw
, 2, 10),
9178 GEN_VXFORM(vsrab
, 2, 12),
9179 GEN_VXFORM(vsrah
, 2, 13),
9180 GEN_VXFORM(vsraw
, 2, 14),
9181 GEN_VXFORM(vslo
, 6, 16),
9182 GEN_VXFORM(vsro
, 6, 17),
9183 GEN_VXFORM(vaddcuw
, 0, 6),
9184 GEN_VXFORM(vsubcuw
, 0, 22),
9185 GEN_VXFORM(vaddubs
, 0, 8),
9186 GEN_VXFORM(vadduhs
, 0, 9),
9187 GEN_VXFORM(vadduws
, 0, 10),
9188 GEN_VXFORM(vaddsbs
, 0, 12),
9189 GEN_VXFORM(vaddshs
, 0, 13),
9190 GEN_VXFORM(vaddsws
, 0, 14),
9191 GEN_VXFORM(vsububs
, 0, 24),
9192 GEN_VXFORM(vsubuhs
, 0, 25),
9193 GEN_VXFORM(vsubuws
, 0, 26),
9194 GEN_VXFORM(vsubsbs
, 0, 28),
9195 GEN_VXFORM(vsubshs
, 0, 29),
9196 GEN_VXFORM(vsubsws
, 0, 30),
9197 GEN_VXFORM(vrlb
, 2, 0),
9198 GEN_VXFORM(vrlh
, 2, 1),
9199 GEN_VXFORM(vrlw
, 2, 2),
9200 GEN_VXFORM(vsl
, 2, 7),
9201 GEN_VXFORM(vsr
, 2, 11),
9202 GEN_VXFORM(vpkuhum
, 7, 0),
9203 GEN_VXFORM(vpkuwum
, 7, 1),
9204 GEN_VXFORM(vpkuhus
, 7, 2),
9205 GEN_VXFORM(vpkuwus
, 7, 3),
9206 GEN_VXFORM(vpkshus
, 7, 4),
9207 GEN_VXFORM(vpkswus
, 7, 5),
9208 GEN_VXFORM(vpkshss
, 7, 6),
9209 GEN_VXFORM(vpkswss
, 7, 7),
9210 GEN_VXFORM(vpkpx
, 7, 12),
9211 GEN_VXFORM(vsum4ubs
, 4, 24),
9212 GEN_VXFORM(vsum4sbs
, 4, 28),
9213 GEN_VXFORM(vsum4shs
, 4, 25),
9214 GEN_VXFORM(vsum2sws
, 4, 26),
9215 GEN_VXFORM(vsumsws
, 4, 30),
9216 GEN_VXFORM(vaddfp
, 5, 0),
9217 GEN_VXFORM(vsubfp
, 5, 1),
9218 GEN_VXFORM(vmaxfp
, 5, 16),
9219 GEN_VXFORM(vminfp
, 5, 17),
9223 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9224 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9225 #define GEN_VXRFORM(name, opc2, opc3) \
9226 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9227 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9228 GEN_VXRFORM(vcmpequb
, 3, 0)
9229 GEN_VXRFORM(vcmpequh
, 3, 1)
9230 GEN_VXRFORM(vcmpequw
, 3, 2)
9231 GEN_VXRFORM(vcmpgtsb
, 3, 12)
9232 GEN_VXRFORM(vcmpgtsh
, 3, 13)
9233 GEN_VXRFORM(vcmpgtsw
, 3, 14)
9234 GEN_VXRFORM(vcmpgtub
, 3, 8)
9235 GEN_VXRFORM(vcmpgtuh
, 3, 9)
9236 GEN_VXRFORM(vcmpgtuw
, 3, 10)
9237 GEN_VXRFORM(vcmpeqfp
, 3, 3)
9238 GEN_VXRFORM(vcmpgefp
, 3, 7)
9239 GEN_VXRFORM(vcmpgtfp
, 3, 11)
9240 GEN_VXRFORM(vcmpbfp
, 3, 15)
9242 #undef GEN_VXFORM_SIMM
9243 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9244 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9245 GEN_VXFORM_SIMM(vspltisb
, 6, 12),
9246 GEN_VXFORM_SIMM(vspltish
, 6, 13),
9247 GEN_VXFORM_SIMM(vspltisw
, 6, 14),
9249 #undef GEN_VXFORM_NOA
9250 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9251 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9252 GEN_VXFORM_NOA(vupkhsb
, 7, 8),
9253 GEN_VXFORM_NOA(vupkhsh
, 7, 9),
9254 GEN_VXFORM_NOA(vupklsb
, 7, 10),
9255 GEN_VXFORM_NOA(vupklsh
, 7, 11),
9256 GEN_VXFORM_NOA(vupkhpx
, 7, 13),
9257 GEN_VXFORM_NOA(vupklpx
, 7, 15),
9258 GEN_VXFORM_NOA(vrefp
, 5, 4),
9259 GEN_VXFORM_NOA(vrsqrtefp
, 5, 5),
9260 GEN_VXFORM_NOA(vexptefp
, 5, 6),
9261 GEN_VXFORM_NOA(vlogefp
, 5, 7),
9262 GEN_VXFORM_NOA(vrfim
, 5, 8),
9263 GEN_VXFORM_NOA(vrfin
, 5, 9),
9264 GEN_VXFORM_NOA(vrfip
, 5, 10),
9265 GEN_VXFORM_NOA(vrfiz
, 5, 11),
9267 #undef GEN_VXFORM_UIMM
9268 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9269 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9270 GEN_VXFORM_UIMM(vspltb
, 6, 8),
9271 GEN_VXFORM_UIMM(vsplth
, 6, 9),
9272 GEN_VXFORM_UIMM(vspltw
, 6, 10),
9273 GEN_VXFORM_UIMM(vcfux
, 5, 12),
9274 GEN_VXFORM_UIMM(vcfsx
, 5, 13),
9275 GEN_VXFORM_UIMM(vctuxs
, 5, 14),
9276 GEN_VXFORM_UIMM(vctsxs
, 5, 15),
9278 #undef GEN_VAFORM_PAIRED
9279 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9280 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9281 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16),
9282 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18),
9283 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19),
9284 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20),
9285 GEN_VAFORM_PAIRED(vsel
, vperm
, 21),
9286 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23),
9289 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9290 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9291 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9292 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9293 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9294 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9295 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
9296 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
9297 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
9298 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
),
9299 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
),
9300 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
9301 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9302 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9303 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9304 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
9305 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
9306 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
),
9307 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
9308 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9309 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9310 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9311 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9312 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
9313 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
9314 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
9315 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9316 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
9317 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
9318 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
9319 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
),
9321 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9322 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
9323 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9324 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9325 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9326 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9327 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9328 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9329 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9330 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9331 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9332 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9333 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9334 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9336 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9337 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
9338 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9339 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
9340 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9341 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
),
9342 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9343 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9344 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9345 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
9346 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9347 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9348 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
9349 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
9351 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
9352 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9353 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
),
9354 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9355 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
9356 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9357 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
9358 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
),
9359 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9360 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9361 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9362 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
9363 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9364 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9365 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
9366 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
9368 #undef GEN_SPEOP_LDST
9369 #define GEN_SPEOP_LDST(name, opc2, sh) \
9370 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9371 GEN_SPEOP_LDST(evldd
, 0x00, 3),
9372 GEN_SPEOP_LDST(evldw
, 0x01, 3),
9373 GEN_SPEOP_LDST(evldh
, 0x02, 3),
9374 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1),
9375 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1),
9376 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1),
9377 GEN_SPEOP_LDST(evlwhe
, 0x08, 2),
9378 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2),
9379 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2),
9380 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2),
9381 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2),
9383 GEN_SPEOP_LDST(evstdd
, 0x10, 3),
9384 GEN_SPEOP_LDST(evstdw
, 0x11, 3),
9385 GEN_SPEOP_LDST(evstdh
, 0x12, 3),
9386 GEN_SPEOP_LDST(evstwhe
, 0x18, 2),
9387 GEN_SPEOP_LDST(evstwho
, 0x1A, 2),
9388 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2),
9389 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2),
9392 #include "helper_regs.h"
9393 #include "translate_init.c"
9395 /*****************************************************************************/
9396 /* Misc PowerPC helpers */
9397 void cpu_dump_state (CPUPPCState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
9405 cpu_synchronize_state(env
);
9407 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
9408 TARGET_FMT_lx
" XER " TARGET_FMT_lx
"\n",
9409 env
->nip
, env
->lr
, env
->ctr
, env
->xer
);
9410 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
9411 TARGET_FMT_lx
" idx %d\n", env
->msr
, env
->spr
[SPR_HID0
],
9412 env
->hflags
, env
->mmu_idx
);
9413 #if !defined(NO_TIMER_DUMP)
9414 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
9415 #if !defined(CONFIG_USER_ONLY)
9419 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
9420 #if !defined(CONFIG_USER_ONLY)
9421 , cpu_ppc_load_decr(env
)
9425 for (i
= 0; i
< 32; i
++) {
9426 if ((i
& (RGPL
- 1)) == 0)
9427 cpu_fprintf(f
, "GPR%02d", i
);
9428 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
9429 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
9430 cpu_fprintf(f
, "\n");
9432 cpu_fprintf(f
, "CR ");
9433 for (i
= 0; i
< 8; i
++)
9434 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
9435 cpu_fprintf(f
, " [");
9436 for (i
= 0; i
< 8; i
++) {
9438 if (env
->crf
[i
] & 0x08)
9440 else if (env
->crf
[i
] & 0x04)
9442 else if (env
->crf
[i
] & 0x02)
9444 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
9446 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
9448 for (i
= 0; i
< 32; i
++) {
9449 if ((i
& (RFPL
- 1)) == 0)
9450 cpu_fprintf(f
, "FPR%02d", i
);
9451 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
9452 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
9453 cpu_fprintf(f
, "\n");
9455 cpu_fprintf(f
, "FPSCR %08x\n", env
->fpscr
);
9456 #if !defined(CONFIG_USER_ONLY)
9457 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
9458 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
9459 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
9460 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
9462 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
9463 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
9464 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
9465 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
9467 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
9468 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
9469 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
9470 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
9472 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
9473 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
9474 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
9475 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
9476 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
9478 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
9479 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
9480 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
9481 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
9483 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
9484 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
9485 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
9486 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
9488 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
9489 " EPR " TARGET_FMT_lx
"\n",
9490 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
9491 env
->spr
[SPR_BOOKE_EPR
]);
9494 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
9495 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
9496 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
9497 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
9500 * IVORs are left out as they are large and do not change often --
9501 * they can be read with "p $ivor0", "p $ivor1", etc.
9505 #if defined(TARGET_PPC64)
9506 if (env
->flags
& POWERPC_FLAG_CFAR
) {
9507 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
9511 switch (env
->mmu_model
) {
9512 case POWERPC_MMU_32B
:
9513 case POWERPC_MMU_601
:
9514 case POWERPC_MMU_SOFT_6xx
:
9515 case POWERPC_MMU_SOFT_74xx
:
9516 #if defined(TARGET_PPC64)
9517 case POWERPC_MMU_620
:
9518 case POWERPC_MMU_64B
:
9520 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
"\n", env
->spr
[SPR_SDR1
]);
9522 case POWERPC_MMU_BOOKE206
:
9523 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
9524 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
9525 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
9526 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
9528 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
9529 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
9530 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
9531 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
9533 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
9534 " TLB1CFG " TARGET_FMT_lx
"\n",
9535 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
9536 env
->spr
[SPR_BOOKE_TLB1CFG
]);
9547 void cpu_dump_statistics (CPUPPCState
*env
, FILE*f
, fprintf_function cpu_fprintf
,
9550 #if defined(DO_PPC_STATISTICS)
9551 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
9555 for (op1
= 0; op1
< 64; op1
++) {
9557 if (is_indirect_opcode(handler
)) {
9558 t2
= ind_table(handler
);
9559 for (op2
= 0; op2
< 32; op2
++) {
9561 if (is_indirect_opcode(handler
)) {
9562 t3
= ind_table(handler
);
9563 for (op3
= 0; op3
< 32; op3
++) {
9565 if (handler
->count
== 0)
9567 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
9568 "%016" PRIx64
" %" PRId64
"\n",
9569 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
9571 handler
->count
, handler
->count
);
9574 if (handler
->count
== 0)
9576 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
9577 "%016" PRIx64
" %" PRId64
"\n",
9578 op1
, op2
, op1
, op2
, handler
->oname
,
9579 handler
->count
, handler
->count
);
9583 if (handler
->count
== 0)
9585 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
9587 op1
, op1
, handler
->oname
,
9588 handler
->count
, handler
->count
);
9594 /*****************************************************************************/
9595 static inline void gen_intermediate_code_internal(CPUPPCState
*env
,
9596 TranslationBlock
*tb
,
9599 DisasContext ctx
, *ctxp
= &ctx
;
9600 opc_handler_t
**table
, *handler
;
9601 target_ulong pc_start
;
9602 uint16_t *gen_opc_end
;
9609 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
9612 ctx
.exception
= POWERPC_EXCP_NONE
;
9613 ctx
.spr_cb
= env
->spr_cb
;
9614 ctx
.mem_idx
= env
->mmu_idx
;
9615 ctx
.access_type
= -1;
9616 ctx
.le_mode
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
9617 #if defined(TARGET_PPC64)
9618 ctx
.sf_mode
= msr_sf
;
9619 ctx
.has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
9621 ctx
.fpu_enabled
= msr_fp
;
9622 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
9623 ctx
.spe_enabled
= msr_spe
;
9625 ctx
.spe_enabled
= 0;
9626 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
9627 ctx
.altivec_enabled
= msr_vr
;
9629 ctx
.altivec_enabled
= 0;
9630 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
9631 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
9633 ctx
.singlestep_enabled
= 0;
9634 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
9635 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
9636 if (unlikely(env
->singlestep_enabled
))
9637 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
9638 #if defined (DO_SINGLE_STEP) && 0
9639 /* Single step trace mode */
9643 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
9645 max_insns
= CF_COUNT_MASK
;
9648 /* Set env in case of segfault during code fetch */
9649 while (ctx
.exception
== POWERPC_EXCP_NONE
&& gen_opc_ptr
< gen_opc_end
) {
9650 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
9651 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
9652 if (bp
->pc
== ctx
.nip
) {
9653 gen_debug_exception(ctxp
);
9658 if (unlikely(search_pc
)) {
9659 j
= gen_opc_ptr
- gen_opc_buf
;
9663 gen_opc_instr_start
[lj
++] = 0;
9665 gen_opc_pc
[lj
] = ctx
.nip
;
9666 gen_opc_instr_start
[lj
] = 1;
9667 gen_opc_icount
[lj
] = num_insns
;
9669 LOG_DISAS("----------------\n");
9670 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
9671 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
9672 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
9674 if (unlikely(ctx
.le_mode
)) {
9675 ctx
.opcode
= bswap32(ldl_code(ctx
.nip
));
9677 ctx
.opcode
= ldl_code(ctx
.nip
);
9679 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9680 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
9681 opc3(ctx
.opcode
), little_endian
? "little" : "big");
9682 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
9683 tcg_gen_debug_insn_start(ctx
.nip
);
9685 table
= env
->opcodes
;
9687 handler
= table
[opc1(ctx
.opcode
)];
9688 if (is_indirect_opcode(handler
)) {
9689 table
= ind_table(handler
);
9690 handler
= table
[opc2(ctx
.opcode
)];
9691 if (is_indirect_opcode(handler
)) {
9692 table
= ind_table(handler
);
9693 handler
= table
[opc3(ctx
.opcode
)];
9696 /* Is opcode *REALLY* valid ? */
9697 if (unlikely(handler
->handler
== &gen_invalid
)) {
9698 if (qemu_log_enabled()) {
9699 qemu_log("invalid/unsupported opcode: "
9700 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
" %d\n",
9701 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
9702 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
9707 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
) && Rc(ctx
.opcode
))) {
9708 inval
= handler
->inval2
;
9710 inval
= handler
->inval1
;
9713 if (unlikely((ctx
.opcode
& inval
) != 0)) {
9714 if (qemu_log_enabled()) {
9715 qemu_log("invalid bits: %08x for opcode: "
9716 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
"\n",
9717 ctx
.opcode
& inval
, opc1(ctx
.opcode
),
9718 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
9719 ctx
.opcode
, ctx
.nip
- 4);
9721 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
9725 (*(handler
->handler
))(&ctx
);
9726 #if defined(DO_PPC_STATISTICS)
9729 /* Check trace mode exceptions */
9730 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
9731 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
9732 ctx
.exception
!= POWERPC_SYSCALL
&&
9733 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
9734 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
9735 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
9736 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
9737 (env
->singlestep_enabled
) ||
9739 num_insns
>= max_insns
)) {
9740 /* if we reach a page boundary or are single stepping, stop
9746 if (tb
->cflags
& CF_LAST_IO
)
9748 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
9749 gen_goto_tb(&ctx
, 0, ctx
.nip
);
9750 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
9751 if (unlikely(env
->singlestep_enabled
)) {
9752 gen_debug_exception(ctxp
);
9754 /* Generate the return instruction */
9757 gen_icount_end(tb
, num_insns
);
9758 *gen_opc_ptr
= INDEX_op_end
;
9759 if (unlikely(search_pc
)) {
9760 j
= gen_opc_ptr
- gen_opc_buf
;
9763 gen_opc_instr_start
[lj
++] = 0;
9765 tb
->size
= ctx
.nip
- pc_start
;
9766 tb
->icount
= num_insns
;
9768 #if defined(DEBUG_DISAS)
9769 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
9771 flags
= env
->bfd_mach
;
9772 flags
|= ctx
.le_mode
<< 16;
9773 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
9774 log_target_disas(pc_start
, ctx
.nip
- pc_start
, flags
);
9780 void gen_intermediate_code (CPUPPCState
*env
, struct TranslationBlock
*tb
)
9782 gen_intermediate_code_internal(env
, tb
, 0);
9785 void gen_intermediate_code_pc (CPUPPCState
*env
, struct TranslationBlock
*tb
)
9787 gen_intermediate_code_internal(env
, tb
, 1);
9790 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
, int pc_pos
)
9792 env
->nip
= gen_opc_pc
[pc_pos
];