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1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 /* True when active word size < size of target_long. */
208 #ifdef TARGET_PPC64
209 # define NARROW_MODE(C) (!(C)->sf_mode)
210 #else
211 # define NARROW_MODE(C) 0
212 #endif
213
214 struct opc_handler_t {
215 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
216 uint32_t inval1;
217 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
218 uint32_t inval2;
219 /* instruction type */
220 uint64_t type;
221 /* extended instruction type */
222 uint64_t type2;
223 /* handler */
224 void (*handler)(DisasContext *ctx);
225 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
226 const char *oname;
227 #endif
228 #if defined(DO_PPC_STATISTICS)
229 uint64_t count;
230 #endif
231 };
232
233 static inline void gen_reset_fpstatus(void)
234 {
235 gen_helper_reset_fpstatus(cpu_env);
236 }
237
238 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
239 {
240 TCGv_i32 t0 = tcg_temp_new_i32();
241
242 if (set_fprf != 0) {
243 /* This case might be optimized later */
244 tcg_gen_movi_i32(t0, 1);
245 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
246 if (unlikely(set_rc)) {
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249 gen_helper_float_check_status(cpu_env);
250 } else if (unlikely(set_rc)) {
251 /* We always need to compute fpcc */
252 tcg_gen_movi_i32(t0, 0);
253 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
254 tcg_gen_mov_i32(cpu_crf[1], t0);
255 }
256
257 tcg_temp_free_i32(t0);
258 }
259
260 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
261 {
262 if (ctx->access_type != access_type) {
263 tcg_gen_movi_i32(cpu_access_type, access_type);
264 ctx->access_type = access_type;
265 }
266 }
267
268 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
269 {
270 if (NARROW_MODE(ctx)) {
271 nip = (uint32_t)nip;
272 }
273 tcg_gen_movi_tl(cpu_nip, nip);
274 }
275
276 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
277 {
278 TCGv_i32 t0, t1;
279 if (ctx->exception == POWERPC_EXCP_NONE) {
280 gen_update_nip(ctx, ctx->nip);
281 }
282 t0 = tcg_const_i32(excp);
283 t1 = tcg_const_i32(error);
284 gen_helper_raise_exception_err(cpu_env, t0, t1);
285 tcg_temp_free_i32(t0);
286 tcg_temp_free_i32(t1);
287 ctx->exception = (excp);
288 }
289
290 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
291 {
292 TCGv_i32 t0;
293 if (ctx->exception == POWERPC_EXCP_NONE) {
294 gen_update_nip(ctx, ctx->nip);
295 }
296 t0 = tcg_const_i32(excp);
297 gen_helper_raise_exception(cpu_env, t0);
298 tcg_temp_free_i32(t0);
299 ctx->exception = (excp);
300 }
301
302 static inline void gen_debug_exception(DisasContext *ctx)
303 {
304 TCGv_i32 t0;
305
306 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
307 (ctx->exception != POWERPC_EXCP_SYNC)) {
308 gen_update_nip(ctx, ctx->nip);
309 }
310 t0 = tcg_const_i32(EXCP_DEBUG);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 }
314
315 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
316 {
317 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
318 }
319
320 /* Stop translation */
321 static inline void gen_stop_exception(DisasContext *ctx)
322 {
323 gen_update_nip(ctx, ctx->nip);
324 ctx->exception = POWERPC_EXCP_STOP;
325 }
326
327 /* No need to update nip here, as execution flow will change */
328 static inline void gen_sync_exception(DisasContext *ctx)
329 {
330 ctx->exception = POWERPC_EXCP_SYNC;
331 }
332
333 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
334 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
335
336 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
337 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
338
339 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
344
345 typedef struct opcode_t {
346 unsigned char opc1, opc2, opc3;
347 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
348 unsigned char pad[5];
349 #else
350 unsigned char pad[1];
351 #endif
352 opc_handler_t handler;
353 const char *oname;
354 } opcode_t;
355
356 /*****************************************************************************/
357 /*** Instruction decoding ***/
358 #define EXTRACT_HELPER(name, shift, nb) \
359 static inline uint32_t name(uint32_t opcode) \
360 { \
361 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
362 }
363
364 #define EXTRACT_SHELPER(name, shift, nb) \
365 static inline int32_t name(uint32_t opcode) \
366 { \
367 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
368 }
369
370 /* Opcode part 1 */
371 EXTRACT_HELPER(opc1, 26, 6);
372 /* Opcode part 2 */
373 EXTRACT_HELPER(opc2, 1, 5);
374 /* Opcode part 3 */
375 EXTRACT_HELPER(opc3, 6, 5);
376 /* Update Cr0 flags */
377 EXTRACT_HELPER(Rc, 0, 1);
378 /* Destination */
379 EXTRACT_HELPER(rD, 21, 5);
380 /* Source */
381 EXTRACT_HELPER(rS, 21, 5);
382 /* First operand */
383 EXTRACT_HELPER(rA, 16, 5);
384 /* Second operand */
385 EXTRACT_HELPER(rB, 11, 5);
386 /* Third operand */
387 EXTRACT_HELPER(rC, 6, 5);
388 /*** Get CRn ***/
389 EXTRACT_HELPER(crfD, 23, 3);
390 EXTRACT_HELPER(crfS, 18, 3);
391 EXTRACT_HELPER(crbD, 21, 5);
392 EXTRACT_HELPER(crbA, 16, 5);
393 EXTRACT_HELPER(crbB, 11, 5);
394 /* SPR / TBL */
395 EXTRACT_HELPER(_SPR, 11, 10);
396 static inline uint32_t SPR(uint32_t opcode)
397 {
398 uint32_t sprn = _SPR(opcode);
399
400 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
401 }
402 /*** Get constants ***/
403 EXTRACT_HELPER(IMM, 12, 8);
404 /* 16 bits signed immediate value */
405 EXTRACT_SHELPER(SIMM, 0, 16);
406 /* 16 bits unsigned immediate value */
407 EXTRACT_HELPER(UIMM, 0, 16);
408 /* 5 bits signed immediate value */
409 EXTRACT_HELPER(SIMM5, 16, 5);
410 /* 5 bits signed immediate value */
411 EXTRACT_HELPER(UIMM5, 16, 5);
412 /* Bit count */
413 EXTRACT_HELPER(NB, 11, 5);
414 /* Shift count */
415 EXTRACT_HELPER(SH, 11, 5);
416 /* Vector shift count */
417 EXTRACT_HELPER(VSH, 6, 4);
418 /* Mask start */
419 EXTRACT_HELPER(MB, 6, 5);
420 /* Mask end */
421 EXTRACT_HELPER(ME, 1, 5);
422 /* Trap operand */
423 EXTRACT_HELPER(TO, 21, 5);
424
425 EXTRACT_HELPER(CRM, 12, 8);
426 EXTRACT_HELPER(FM, 17, 8);
427 EXTRACT_HELPER(SR, 16, 4);
428 EXTRACT_HELPER(FPIMM, 12, 4);
429
430 /*** Jump target decoding ***/
431 /* Displacement */
432 EXTRACT_SHELPER(d, 0, 16);
433 /* Immediate address */
434 static inline target_ulong LI(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0x03FFFFFC;
437 }
438
439 static inline uint32_t BD(uint32_t opcode)
440 {
441 return (opcode >> 0) & 0xFFFC;
442 }
443
444 EXTRACT_HELPER(BO, 21, 5);
445 EXTRACT_HELPER(BI, 16, 5);
446 /* Absolute/relative address */
447 EXTRACT_HELPER(AA, 1, 1);
448 /* Link */
449 EXTRACT_HELPER(LK, 0, 1);
450
451 /* Create a mask between <start> and <end> bits */
452 static inline target_ulong MASK(uint32_t start, uint32_t end)
453 {
454 target_ulong ret;
455
456 #if defined(TARGET_PPC64)
457 if (likely(start == 0)) {
458 ret = UINT64_MAX << (63 - end);
459 } else if (likely(end == 63)) {
460 ret = UINT64_MAX >> start;
461 }
462 #else
463 if (likely(start == 0)) {
464 ret = UINT32_MAX << (31 - end);
465 } else if (likely(end == 31)) {
466 ret = UINT32_MAX >> start;
467 }
468 #endif
469 else {
470 ret = (((target_ulong)(-1ULL)) >> (start)) ^
471 (((target_ulong)(-1ULL) >> (end)) >> 1);
472 if (unlikely(start > end))
473 return ~ret;
474 }
475
476 return ret;
477 }
478
479 /*****************************************************************************/
480 /* PowerPC instructions table */
481
482 #if defined(DO_PPC_STATISTICS)
483 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
484 { \
485 .opc1 = op1, \
486 .opc2 = op2, \
487 .opc3 = op3, \
488 .pad = { 0, }, \
489 .handler = { \
490 .inval1 = invl, \
491 .type = _typ, \
492 .type2 = _typ2, \
493 .handler = &gen_##name, \
494 .oname = stringify(name), \
495 }, \
496 .oname = stringify(name), \
497 }
498 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
499 { \
500 .opc1 = op1, \
501 .opc2 = op2, \
502 .opc3 = op3, \
503 .pad = { 0, }, \
504 .handler = { \
505 .inval1 = invl1, \
506 .inval2 = invl2, \
507 .type = _typ, \
508 .type2 = _typ2, \
509 .handler = &gen_##name, \
510 .oname = stringify(name), \
511 }, \
512 .oname = stringify(name), \
513 }
514 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
515 { \
516 .opc1 = op1, \
517 .opc2 = op2, \
518 .opc3 = op3, \
519 .pad = { 0, }, \
520 .handler = { \
521 .inval1 = invl, \
522 .type = _typ, \
523 .type2 = _typ2, \
524 .handler = &gen_##name, \
525 .oname = onam, \
526 }, \
527 .oname = onam, \
528 }
529 #else
530 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
531 { \
532 .opc1 = op1, \
533 .opc2 = op2, \
534 .opc3 = op3, \
535 .pad = { 0, }, \
536 .handler = { \
537 .inval1 = invl, \
538 .type = _typ, \
539 .type2 = _typ2, \
540 .handler = &gen_##name, \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .pad = { 0, }, \
550 .handler = { \
551 .inval1 = invl1, \
552 .inval2 = invl2, \
553 .type = _typ, \
554 .type2 = _typ2, \
555 .handler = &gen_##name, \
556 }, \
557 .oname = stringify(name), \
558 }
559 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
560 { \
561 .opc1 = op1, \
562 .opc2 = op2, \
563 .opc3 = op3, \
564 .pad = { 0, }, \
565 .handler = { \
566 .inval1 = invl, \
567 .type = _typ, \
568 .type2 = _typ2, \
569 .handler = &gen_##name, \
570 }, \
571 .oname = onam, \
572 }
573 #endif
574
575 /* SPR load/store helpers */
576 static inline void gen_load_spr(TCGv t, int reg)
577 {
578 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 static inline void gen_store_spr(int reg, TCGv t)
582 {
583 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
584 }
585
586 /* Invalid instruction */
587 static void gen_invalid(DisasContext *ctx)
588 {
589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
590 }
591
592 static opc_handler_t invalid_handler = {
593 .inval1 = 0xFFFFFFFF,
594 .inval2 = 0xFFFFFFFF,
595 .type = PPC_NONE,
596 .type2 = PPC_NONE,
597 .handler = gen_invalid,
598 };
599
600 /*** Integer comparison ***/
601
602 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
603 {
604 TCGv t0 = tcg_temp_new();
605 TCGv_i32 t1 = tcg_temp_new_i32();
606
607 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_LT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_GT);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
620 tcg_gen_trunc_tl_i32(t1, t0);
621 tcg_gen_shli_i32(t1, t1, CRF_EQ);
622 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
623
624 tcg_temp_free(t0);
625 tcg_temp_free_i32(t1);
626 }
627
628 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
629 {
630 TCGv t0 = tcg_const_tl(arg1);
631 gen_op_cmp(arg0, t0, s, crf);
632 tcg_temp_free(t0);
633 }
634
635 #if defined(TARGET_PPC64)
636 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
637 {
638 TCGv t0, t1;
639 t0 = tcg_temp_new();
640 t1 = tcg_temp_new();
641 if (s) {
642 tcg_gen_ext32s_tl(t0, arg0);
643 tcg_gen_ext32s_tl(t1, arg1);
644 } else {
645 tcg_gen_ext32u_tl(t0, arg0);
646 tcg_gen_ext32u_tl(t1, arg1);
647 }
648 gen_op_cmp(t0, t1, s, crf);
649 tcg_temp_free(t1);
650 tcg_temp_free(t0);
651 }
652
653 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
654 {
655 TCGv t0 = tcg_const_tl(arg1);
656 gen_op_cmp32(arg0, t0, s, crf);
657 tcg_temp_free(t0);
658 }
659 #endif
660
661 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
662 {
663 #if defined(TARGET_PPC64)
664 if (!(ctx->sf_mode))
665 gen_op_cmpi32(reg, 0, 1, 0);
666 else
667 #endif
668 gen_op_cmpi(reg, 0, 1, 0);
669 }
670
671 /* cmp */
672 static void gen_cmp(DisasContext *ctx)
673 {
674 #if defined(TARGET_PPC64)
675 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
676 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
677 1, crfD(ctx->opcode));
678 else
679 #endif
680 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
681 1, crfD(ctx->opcode));
682 }
683
684 /* cmpi */
685 static void gen_cmpi(DisasContext *ctx)
686 {
687 #if defined(TARGET_PPC64)
688 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
689 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
690 1, crfD(ctx->opcode));
691 else
692 #endif
693 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
694 1, crfD(ctx->opcode));
695 }
696
697 /* cmpl */
698 static void gen_cmpl(DisasContext *ctx)
699 {
700 #if defined(TARGET_PPC64)
701 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
702 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
703 0, crfD(ctx->opcode));
704 else
705 #endif
706 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
707 0, crfD(ctx->opcode));
708 }
709
710 /* cmpli */
711 static void gen_cmpli(DisasContext *ctx)
712 {
713 #if defined(TARGET_PPC64)
714 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
715 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
716 0, crfD(ctx->opcode));
717 else
718 #endif
719 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
720 0, crfD(ctx->opcode));
721 }
722
723 /* isel (PowerPC 2.03 specification) */
724 static void gen_isel(DisasContext *ctx)
725 {
726 int l1, l2;
727 uint32_t bi = rC(ctx->opcode);
728 uint32_t mask;
729 TCGv_i32 t0;
730
731 l1 = gen_new_label();
732 l2 = gen_new_label();
733
734 mask = 1 << (3 - (bi & 0x03));
735 t0 = tcg_temp_new_i32();
736 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
737 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
738 if (rA(ctx->opcode) == 0)
739 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
740 else
741 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
742 tcg_gen_br(l2);
743 gen_set_label(l1);
744 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
745 gen_set_label(l2);
746 tcg_temp_free_i32(t0);
747 }
748
749 /*** Integer arithmetic ***/
750
751 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
752 TCGv arg1, TCGv arg2, int sub)
753 {
754 TCGv t0 = tcg_temp_new();
755
756 tcg_gen_xor_tl(cpu_ov, arg0, arg1);
757 tcg_gen_xor_tl(t0, arg1, arg2);
758 if (sub) {
759 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
760 } else {
761 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
762 }
763 tcg_temp_free(t0);
764 #if defined(TARGET_PPC64)
765 if (!ctx->sf_mode) {
766 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
767 }
768 #endif
769 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
770 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
771 }
772
773 /* Common add function */
774 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
775 TCGv arg2, bool add_ca, bool compute_ca,
776 bool compute_ov, bool compute_rc0)
777 {
778 TCGv t0 = ret;
779
780 if (((compute_ca && add_ca) || compute_ov)
781 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
782 t0 = tcg_temp_new();
783 }
784
785 if (compute_ca) {
786 if (NARROW_MODE(ctx)) {
787 TCGv t1 = tcg_temp_new();
788 tcg_gen_ext32u_tl(t1, arg2);
789 tcg_gen_ext32u_tl(t0, arg1);
790 tcg_gen_add_tl(t0, t0, t1);
791 tcg_temp_free(t1);
792 if (add_ca) {
793 tcg_gen_add_tl(t0, t0, cpu_ca);
794 }
795 tcg_gen_shri_tl(cpu_ca, t0, 32);
796 } else {
797 TCGv zero = tcg_const_tl(0);
798 if (add_ca) {
799 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
800 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
801 } else {
802 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
803 }
804 tcg_temp_free(zero);
805 }
806 } else {
807 tcg_gen_add_tl(t0, arg1, arg2);
808 if (add_ca) {
809 tcg_gen_add_tl(t0, t0, cpu_ca);
810 }
811 }
812
813 if (compute_ov) {
814 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
815 }
816 if (unlikely(compute_rc0)) {
817 gen_set_Rc0(ctx, t0);
818 }
819
820 if (!TCGV_EQUAL(t0, ret)) {
821 tcg_gen_mov_tl(ret, t0);
822 tcg_temp_free(t0);
823 }
824 }
825 /* Add functions with two operands */
826 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
827 static void glue(gen_, name)(DisasContext *ctx) \
828 { \
829 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
830 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
831 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
832 }
833 /* Add functions with one operand and one immediate */
834 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
835 add_ca, compute_ca, compute_ov) \
836 static void glue(gen_, name)(DisasContext *ctx) \
837 { \
838 TCGv t0 = tcg_const_tl(const_val); \
839 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
840 cpu_gpr[rA(ctx->opcode)], t0, \
841 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
842 tcg_temp_free(t0); \
843 }
844
845 /* add add. addo addo. */
846 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
847 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
848 /* addc addc. addco addco. */
849 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
850 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
851 /* adde adde. addeo addeo. */
852 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
853 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
854 /* addme addme. addmeo addmeo. */
855 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
856 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
857 /* addze addze. addzeo addzeo.*/
858 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
859 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
860 /* addi */
861 static void gen_addi(DisasContext *ctx)
862 {
863 target_long simm = SIMM(ctx->opcode);
864
865 if (rA(ctx->opcode) == 0) {
866 /* li case */
867 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
868 } else {
869 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
870 cpu_gpr[rA(ctx->opcode)], simm);
871 }
872 }
873 /* addic addic.*/
874 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
875 {
876 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
877 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
878 c, 0, 1, 0, compute_rc0);
879 tcg_temp_free(c);
880 }
881
882 static void gen_addic(DisasContext *ctx)
883 {
884 gen_op_addic(ctx, 0);
885 }
886
887 static void gen_addic_(DisasContext *ctx)
888 {
889 gen_op_addic(ctx, 1);
890 }
891
892 /* addis */
893 static void gen_addis(DisasContext *ctx)
894 {
895 target_long simm = SIMM(ctx->opcode);
896
897 if (rA(ctx->opcode) == 0) {
898 /* lis case */
899 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
900 } else {
901 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
902 cpu_gpr[rA(ctx->opcode)], simm << 16);
903 }
904 }
905
906 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
907 TCGv arg2, int sign, int compute_ov)
908 {
909 int l1 = gen_new_label();
910 int l2 = gen_new_label();
911 TCGv_i32 t0 = tcg_temp_local_new_i32();
912 TCGv_i32 t1 = tcg_temp_local_new_i32();
913
914 tcg_gen_trunc_tl_i32(t0, arg1);
915 tcg_gen_trunc_tl_i32(t1, arg2);
916 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
917 if (sign) {
918 int l3 = gen_new_label();
919 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
920 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
921 gen_set_label(l3);
922 tcg_gen_div_i32(t0, t0, t1);
923 } else {
924 tcg_gen_divu_i32(t0, t0, t1);
925 }
926 if (compute_ov) {
927 tcg_gen_movi_tl(cpu_ov, 0);
928 }
929 tcg_gen_br(l2);
930 gen_set_label(l1);
931 if (sign) {
932 tcg_gen_sari_i32(t0, t0, 31);
933 } else {
934 tcg_gen_movi_i32(t0, 0);
935 }
936 if (compute_ov) {
937 tcg_gen_movi_tl(cpu_ov, 1);
938 tcg_gen_movi_tl(cpu_so, 1);
939 }
940 gen_set_label(l2);
941 tcg_gen_extu_i32_tl(ret, t0);
942 tcg_temp_free_i32(t0);
943 tcg_temp_free_i32(t1);
944 if (unlikely(Rc(ctx->opcode) != 0))
945 gen_set_Rc0(ctx, ret);
946 }
947 /* Div functions */
948 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
949 static void glue(gen_, name)(DisasContext *ctx) \
950 { \
951 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
952 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
953 sign, compute_ov); \
954 }
955 /* divwu divwu. divwuo divwuo. */
956 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
957 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
958 /* divw divw. divwo divwo. */
959 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
960 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
961 #if defined(TARGET_PPC64)
962 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
963 TCGv arg2, int sign, int compute_ov)
964 {
965 int l1 = gen_new_label();
966 int l2 = gen_new_label();
967
968 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
969 if (sign) {
970 int l3 = gen_new_label();
971 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
972 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
973 gen_set_label(l3);
974 tcg_gen_div_i64(ret, arg1, arg2);
975 } else {
976 tcg_gen_divu_i64(ret, arg1, arg2);
977 }
978 if (compute_ov) {
979 tcg_gen_movi_tl(cpu_ov, 0);
980 }
981 tcg_gen_br(l2);
982 gen_set_label(l1);
983 if (sign) {
984 tcg_gen_sari_i64(ret, arg1, 63);
985 } else {
986 tcg_gen_movi_i64(ret, 0);
987 }
988 if (compute_ov) {
989 tcg_gen_movi_tl(cpu_ov, 1);
990 tcg_gen_movi_tl(cpu_so, 1);
991 }
992 gen_set_label(l2);
993 if (unlikely(Rc(ctx->opcode) != 0))
994 gen_set_Rc0(ctx, ret);
995 }
996 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
997 static void glue(gen_, name)(DisasContext *ctx) \
998 { \
999 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1000 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1001 sign, compute_ov); \
1002 }
1003 /* divwu divwu. divwuo divwuo. */
1004 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1005 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1006 /* divw divw. divwo divwo. */
1007 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1008 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1009 #endif
1010
1011 /* mulhw mulhw. */
1012 static void gen_mulhw(DisasContext *ctx)
1013 {
1014 TCGv_i32 t0 = tcg_temp_new_i32();
1015 TCGv_i32 t1 = tcg_temp_new_i32();
1016
1017 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1018 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1019 tcg_gen_muls2_i32(t0, t1, t0, t1);
1020 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1021 tcg_temp_free_i32(t0);
1022 tcg_temp_free_i32(t1);
1023 if (unlikely(Rc(ctx->opcode) != 0))
1024 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1025 }
1026
1027 /* mulhwu mulhwu. */
1028 static void gen_mulhwu(DisasContext *ctx)
1029 {
1030 TCGv_i32 t0 = tcg_temp_new_i32();
1031 TCGv_i32 t1 = tcg_temp_new_i32();
1032
1033 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1034 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1035 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1036 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1037 tcg_temp_free_i32(t0);
1038 tcg_temp_free_i32(t1);
1039 if (unlikely(Rc(ctx->opcode) != 0))
1040 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1041 }
1042
1043 /* mullw mullw. */
1044 static void gen_mullw(DisasContext *ctx)
1045 {
1046 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1047 cpu_gpr[rB(ctx->opcode)]);
1048 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1049 if (unlikely(Rc(ctx->opcode) != 0))
1050 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1051 }
1052
1053 /* mullwo mullwo. */
1054 static void gen_mullwo(DisasContext *ctx)
1055 {
1056 TCGv_i32 t0 = tcg_temp_new_i32();
1057 TCGv_i32 t1 = tcg_temp_new_i32();
1058
1059 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1060 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1061 tcg_gen_muls2_i32(t0, t1, t0, t1);
1062 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1063
1064 tcg_gen_sari_i32(t0, t0, 31);
1065 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1066 tcg_gen_extu_i32_tl(cpu_ov, t0);
1067 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1068
1069 tcg_temp_free_i32(t0);
1070 tcg_temp_free_i32(t1);
1071 if (unlikely(Rc(ctx->opcode) != 0))
1072 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1073 }
1074
1075 /* mulli */
1076 static void gen_mulli(DisasContext *ctx)
1077 {
1078 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1079 SIMM(ctx->opcode));
1080 }
1081
1082 #if defined(TARGET_PPC64)
1083 /* mulhd mulhd. */
1084 static void gen_mulhd(DisasContext *ctx)
1085 {
1086 TCGv lo = tcg_temp_new();
1087 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1088 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1089 tcg_temp_free(lo);
1090 if (unlikely(Rc(ctx->opcode) != 0)) {
1091 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1092 }
1093 }
1094
1095 /* mulhdu mulhdu. */
1096 static void gen_mulhdu(DisasContext *ctx)
1097 {
1098 TCGv lo = tcg_temp_new();
1099 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1100 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1101 tcg_temp_free(lo);
1102 if (unlikely(Rc(ctx->opcode) != 0)) {
1103 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1104 }
1105 }
1106
1107 /* mulld mulld. */
1108 static void gen_mulld(DisasContext *ctx)
1109 {
1110 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1111 cpu_gpr[rB(ctx->opcode)]);
1112 if (unlikely(Rc(ctx->opcode) != 0))
1113 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1114 }
1115
1116 /* mulldo mulldo. */
1117 static void gen_mulldo(DisasContext *ctx)
1118 {
1119 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1120 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1121 if (unlikely(Rc(ctx->opcode) != 0)) {
1122 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1123 }
1124 }
1125 #endif
1126
1127 /* Common subf function */
1128 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1129 TCGv arg2, bool add_ca, bool compute_ca,
1130 bool compute_ov, bool compute_rc0)
1131 {
1132 TCGv t0 = ret;
1133
1134 if (compute_ov && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
1135 t0 = tcg_temp_new();
1136 }
1137
1138 if (compute_ca) {
1139 /* dest = ~arg1 + arg2 [+ ca]. */
1140 if (NARROW_MODE(ctx)) {
1141 TCGv inv1 = tcg_temp_new();
1142 tcg_gen_not_tl(inv1, arg1);
1143 tcg_gen_ext32u_tl(t0, arg2);
1144 tcg_gen_ext32u_tl(inv1, inv1);
1145 if (add_ca) {
1146 tcg_gen_add_tl(t0, t0, cpu_ca);
1147 } else {
1148 tcg_gen_addi_tl(t0, t0, 1);
1149 }
1150 tcg_gen_add_tl(t0, t0, inv1);
1151 tcg_gen_shri_tl(cpu_ca, t0, 32);
1152 } else if (add_ca) {
1153 TCGv zero, inv1 = tcg_temp_new();
1154 tcg_gen_not_tl(inv1, arg1);
1155 zero = tcg_const_tl(0);
1156 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1157 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1158 tcg_temp_free(zero);
1159 tcg_temp_free(inv1);
1160 } else {
1161 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1162 tcg_gen_sub_tl(t0, arg2, arg1);
1163 }
1164 } else if (add_ca) {
1165 /* Since we're ignoring carry-out, we can simplify the
1166 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1167 tcg_gen_sub_tl(t0, arg2, arg1);
1168 tcg_gen_add_tl(t0, t0, cpu_ca);
1169 tcg_gen_subi_tl(t0, t0, 1);
1170 } else {
1171 tcg_gen_sub_tl(t0, arg2, arg1);
1172 }
1173
1174 if (compute_ov) {
1175 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1176 }
1177 if (unlikely(compute_rc0)) {
1178 gen_set_Rc0(ctx, t0);
1179 }
1180
1181 if (!TCGV_EQUAL(t0, ret)) {
1182 tcg_gen_mov_tl(ret, t0);
1183 tcg_temp_free(t0);
1184 }
1185 }
1186 /* Sub functions with Two operands functions */
1187 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1188 static void glue(gen_, name)(DisasContext *ctx) \
1189 { \
1190 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1191 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1192 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1193 }
1194 /* Sub functions with one operand and one immediate */
1195 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1196 add_ca, compute_ca, compute_ov) \
1197 static void glue(gen_, name)(DisasContext *ctx) \
1198 { \
1199 TCGv t0 = tcg_const_tl(const_val); \
1200 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1201 cpu_gpr[rA(ctx->opcode)], t0, \
1202 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1203 tcg_temp_free(t0); \
1204 }
1205 /* subf subf. subfo subfo. */
1206 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1207 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1208 /* subfc subfc. subfco subfco. */
1209 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1210 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1211 /* subfe subfe. subfeo subfo. */
1212 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1213 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1214 /* subfme subfme. subfmeo subfmeo. */
1215 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1216 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1217 /* subfze subfze. subfzeo subfzeo.*/
1218 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1219 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1220
1221 /* subfic */
1222 static void gen_subfic(DisasContext *ctx)
1223 {
1224 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1225 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1226 c, 0, 1, 0, 0);
1227 tcg_temp_free(c);
1228 }
1229
1230 /* neg neg. nego nego. */
1231 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1232 {
1233 TCGv zero = tcg_const_tl(0);
1234 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1235 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1236 tcg_temp_free(zero);
1237 }
1238
1239 static void gen_neg(DisasContext *ctx)
1240 {
1241 gen_op_arith_neg(ctx, 0);
1242 }
1243
1244 static void gen_nego(DisasContext *ctx)
1245 {
1246 gen_op_arith_neg(ctx, 1);
1247 }
1248
1249 /*** Integer logical ***/
1250 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1251 static void glue(gen_, name)(DisasContext *ctx) \
1252 { \
1253 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1254 cpu_gpr[rB(ctx->opcode)]); \
1255 if (unlikely(Rc(ctx->opcode) != 0)) \
1256 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1257 }
1258
1259 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1260 static void glue(gen_, name)(DisasContext *ctx) \
1261 { \
1262 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1263 if (unlikely(Rc(ctx->opcode) != 0)) \
1264 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1265 }
1266
1267 /* and & and. */
1268 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1269 /* andc & andc. */
1270 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1271
1272 /* andi. */
1273 static void gen_andi_(DisasContext *ctx)
1274 {
1275 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1276 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1277 }
1278
1279 /* andis. */
1280 static void gen_andis_(DisasContext *ctx)
1281 {
1282 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1283 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1284 }
1285
1286 /* cntlzw */
1287 static void gen_cntlzw(DisasContext *ctx)
1288 {
1289 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1290 if (unlikely(Rc(ctx->opcode) != 0))
1291 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1292 }
1293 /* eqv & eqv. */
1294 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1295 /* extsb & extsb. */
1296 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1297 /* extsh & extsh. */
1298 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1299 /* nand & nand. */
1300 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1301 /* nor & nor. */
1302 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1303
1304 /* or & or. */
1305 static void gen_or(DisasContext *ctx)
1306 {
1307 int rs, ra, rb;
1308
1309 rs = rS(ctx->opcode);
1310 ra = rA(ctx->opcode);
1311 rb = rB(ctx->opcode);
1312 /* Optimisation for mr. ri case */
1313 if (rs != ra || rs != rb) {
1314 if (rs != rb)
1315 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1316 else
1317 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1318 if (unlikely(Rc(ctx->opcode) != 0))
1319 gen_set_Rc0(ctx, cpu_gpr[ra]);
1320 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1321 gen_set_Rc0(ctx, cpu_gpr[rs]);
1322 #if defined(TARGET_PPC64)
1323 } else {
1324 int prio = 0;
1325
1326 switch (rs) {
1327 case 1:
1328 /* Set process priority to low */
1329 prio = 2;
1330 break;
1331 case 6:
1332 /* Set process priority to medium-low */
1333 prio = 3;
1334 break;
1335 case 2:
1336 /* Set process priority to normal */
1337 prio = 4;
1338 break;
1339 #if !defined(CONFIG_USER_ONLY)
1340 case 31:
1341 if (ctx->mem_idx > 0) {
1342 /* Set process priority to very low */
1343 prio = 1;
1344 }
1345 break;
1346 case 5:
1347 if (ctx->mem_idx > 0) {
1348 /* Set process priority to medium-hight */
1349 prio = 5;
1350 }
1351 break;
1352 case 3:
1353 if (ctx->mem_idx > 0) {
1354 /* Set process priority to high */
1355 prio = 6;
1356 }
1357 break;
1358 case 7:
1359 if (ctx->mem_idx > 1) {
1360 /* Set process priority to very high */
1361 prio = 7;
1362 }
1363 break;
1364 #endif
1365 default:
1366 /* nop */
1367 break;
1368 }
1369 if (prio) {
1370 TCGv t0 = tcg_temp_new();
1371 gen_load_spr(t0, SPR_PPR);
1372 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1373 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1374 gen_store_spr(SPR_PPR, t0);
1375 tcg_temp_free(t0);
1376 }
1377 #endif
1378 }
1379 }
1380 /* orc & orc. */
1381 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1382
1383 /* xor & xor. */
1384 static void gen_xor(DisasContext *ctx)
1385 {
1386 /* Optimisation for "set to zero" case */
1387 if (rS(ctx->opcode) != rB(ctx->opcode))
1388 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1389 else
1390 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1391 if (unlikely(Rc(ctx->opcode) != 0))
1392 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1393 }
1394
1395 /* ori */
1396 static void gen_ori(DisasContext *ctx)
1397 {
1398 target_ulong uimm = UIMM(ctx->opcode);
1399
1400 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1401 /* NOP */
1402 /* XXX: should handle special NOPs for POWER series */
1403 return;
1404 }
1405 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1406 }
1407
1408 /* oris */
1409 static void gen_oris(DisasContext *ctx)
1410 {
1411 target_ulong uimm = UIMM(ctx->opcode);
1412
1413 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1414 /* NOP */
1415 return;
1416 }
1417 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1418 }
1419
1420 /* xori */
1421 static void gen_xori(DisasContext *ctx)
1422 {
1423 target_ulong uimm = UIMM(ctx->opcode);
1424
1425 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1426 /* NOP */
1427 return;
1428 }
1429 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1430 }
1431
1432 /* xoris */
1433 static void gen_xoris(DisasContext *ctx)
1434 {
1435 target_ulong uimm = UIMM(ctx->opcode);
1436
1437 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1438 /* NOP */
1439 return;
1440 }
1441 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1442 }
1443
1444 /* popcntb : PowerPC 2.03 specification */
1445 static void gen_popcntb(DisasContext *ctx)
1446 {
1447 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1448 }
1449
1450 static void gen_popcntw(DisasContext *ctx)
1451 {
1452 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1453 }
1454
1455 #if defined(TARGET_PPC64)
1456 /* popcntd: PowerPC 2.06 specification */
1457 static void gen_popcntd(DisasContext *ctx)
1458 {
1459 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1460 }
1461 #endif
1462
1463 #if defined(TARGET_PPC64)
1464 /* extsw & extsw. */
1465 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1466
1467 /* cntlzd */
1468 static void gen_cntlzd(DisasContext *ctx)
1469 {
1470 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1471 if (unlikely(Rc(ctx->opcode) != 0))
1472 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1473 }
1474 #endif
1475
1476 /*** Integer rotate ***/
1477
1478 /* rlwimi & rlwimi. */
1479 static void gen_rlwimi(DisasContext *ctx)
1480 {
1481 uint32_t mb, me, sh;
1482
1483 mb = MB(ctx->opcode);
1484 me = ME(ctx->opcode);
1485 sh = SH(ctx->opcode);
1486 if (likely(sh == 0 && mb == 0 && me == 31)) {
1487 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1488 } else {
1489 target_ulong mask;
1490 TCGv t1;
1491 TCGv t0 = tcg_temp_new();
1492 #if defined(TARGET_PPC64)
1493 TCGv_i32 t2 = tcg_temp_new_i32();
1494 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1495 tcg_gen_rotli_i32(t2, t2, sh);
1496 tcg_gen_extu_i32_i64(t0, t2);
1497 tcg_temp_free_i32(t2);
1498 #else
1499 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1500 #endif
1501 #if defined(TARGET_PPC64)
1502 mb += 32;
1503 me += 32;
1504 #endif
1505 mask = MASK(mb, me);
1506 t1 = tcg_temp_new();
1507 tcg_gen_andi_tl(t0, t0, mask);
1508 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1509 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1510 tcg_temp_free(t0);
1511 tcg_temp_free(t1);
1512 }
1513 if (unlikely(Rc(ctx->opcode) != 0))
1514 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1515 }
1516
1517 /* rlwinm & rlwinm. */
1518 static void gen_rlwinm(DisasContext *ctx)
1519 {
1520 uint32_t mb, me, sh;
1521
1522 sh = SH(ctx->opcode);
1523 mb = MB(ctx->opcode);
1524 me = ME(ctx->opcode);
1525
1526 if (likely(mb == 0 && me == (31 - sh))) {
1527 if (likely(sh == 0)) {
1528 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1529 } else {
1530 TCGv t0 = tcg_temp_new();
1531 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1532 tcg_gen_shli_tl(t0, t0, sh);
1533 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1534 tcg_temp_free(t0);
1535 }
1536 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1537 TCGv t0 = tcg_temp_new();
1538 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1539 tcg_gen_shri_tl(t0, t0, mb);
1540 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1541 tcg_temp_free(t0);
1542 } else {
1543 TCGv t0 = tcg_temp_new();
1544 #if defined(TARGET_PPC64)
1545 TCGv_i32 t1 = tcg_temp_new_i32();
1546 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1547 tcg_gen_rotli_i32(t1, t1, sh);
1548 tcg_gen_extu_i32_i64(t0, t1);
1549 tcg_temp_free_i32(t1);
1550 #else
1551 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1552 #endif
1553 #if defined(TARGET_PPC64)
1554 mb += 32;
1555 me += 32;
1556 #endif
1557 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1558 tcg_temp_free(t0);
1559 }
1560 if (unlikely(Rc(ctx->opcode) != 0))
1561 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1562 }
1563
1564 /* rlwnm & rlwnm. */
1565 static void gen_rlwnm(DisasContext *ctx)
1566 {
1567 uint32_t mb, me;
1568 TCGv t0;
1569 #if defined(TARGET_PPC64)
1570 TCGv_i32 t1, t2;
1571 #endif
1572
1573 mb = MB(ctx->opcode);
1574 me = ME(ctx->opcode);
1575 t0 = tcg_temp_new();
1576 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1577 #if defined(TARGET_PPC64)
1578 t1 = tcg_temp_new_i32();
1579 t2 = tcg_temp_new_i32();
1580 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1581 tcg_gen_trunc_i64_i32(t2, t0);
1582 tcg_gen_rotl_i32(t1, t1, t2);
1583 tcg_gen_extu_i32_i64(t0, t1);
1584 tcg_temp_free_i32(t1);
1585 tcg_temp_free_i32(t2);
1586 #else
1587 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1588 #endif
1589 if (unlikely(mb != 0 || me != 31)) {
1590 #if defined(TARGET_PPC64)
1591 mb += 32;
1592 me += 32;
1593 #endif
1594 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1595 } else {
1596 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1597 }
1598 tcg_temp_free(t0);
1599 if (unlikely(Rc(ctx->opcode) != 0))
1600 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1601 }
1602
1603 #if defined(TARGET_PPC64)
1604 #define GEN_PPC64_R2(name, opc1, opc2) \
1605 static void glue(gen_, name##0)(DisasContext *ctx) \
1606 { \
1607 gen_##name(ctx, 0); \
1608 } \
1609 \
1610 static void glue(gen_, name##1)(DisasContext *ctx) \
1611 { \
1612 gen_##name(ctx, 1); \
1613 }
1614 #define GEN_PPC64_R4(name, opc1, opc2) \
1615 static void glue(gen_, name##0)(DisasContext *ctx) \
1616 { \
1617 gen_##name(ctx, 0, 0); \
1618 } \
1619 \
1620 static void glue(gen_, name##1)(DisasContext *ctx) \
1621 { \
1622 gen_##name(ctx, 0, 1); \
1623 } \
1624 \
1625 static void glue(gen_, name##2)(DisasContext *ctx) \
1626 { \
1627 gen_##name(ctx, 1, 0); \
1628 } \
1629 \
1630 static void glue(gen_, name##3)(DisasContext *ctx) \
1631 { \
1632 gen_##name(ctx, 1, 1); \
1633 }
1634
1635 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1636 uint32_t sh)
1637 {
1638 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1639 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1640 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1641 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1642 } else {
1643 TCGv t0 = tcg_temp_new();
1644 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1645 if (likely(mb == 0 && me == 63)) {
1646 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1647 } else {
1648 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1649 }
1650 tcg_temp_free(t0);
1651 }
1652 if (unlikely(Rc(ctx->opcode) != 0))
1653 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1654 }
1655 /* rldicl - rldicl. */
1656 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1657 {
1658 uint32_t sh, mb;
1659
1660 sh = SH(ctx->opcode) | (shn << 5);
1661 mb = MB(ctx->opcode) | (mbn << 5);
1662 gen_rldinm(ctx, mb, 63, sh);
1663 }
1664 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1665 /* rldicr - rldicr. */
1666 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1667 {
1668 uint32_t sh, me;
1669
1670 sh = SH(ctx->opcode) | (shn << 5);
1671 me = MB(ctx->opcode) | (men << 5);
1672 gen_rldinm(ctx, 0, me, sh);
1673 }
1674 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1675 /* rldic - rldic. */
1676 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1677 {
1678 uint32_t sh, mb;
1679
1680 sh = SH(ctx->opcode) | (shn << 5);
1681 mb = MB(ctx->opcode) | (mbn << 5);
1682 gen_rldinm(ctx, mb, 63 - sh, sh);
1683 }
1684 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1685
1686 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1687 {
1688 TCGv t0;
1689
1690 mb = MB(ctx->opcode);
1691 me = ME(ctx->opcode);
1692 t0 = tcg_temp_new();
1693 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1694 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1695 if (unlikely(mb != 0 || me != 63)) {
1696 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1697 } else {
1698 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1699 }
1700 tcg_temp_free(t0);
1701 if (unlikely(Rc(ctx->opcode) != 0))
1702 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1703 }
1704
1705 /* rldcl - rldcl. */
1706 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1707 {
1708 uint32_t mb;
1709
1710 mb = MB(ctx->opcode) | (mbn << 5);
1711 gen_rldnm(ctx, mb, 63);
1712 }
1713 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1714 /* rldcr - rldcr. */
1715 static inline void gen_rldcr(DisasContext *ctx, int men)
1716 {
1717 uint32_t me;
1718
1719 me = MB(ctx->opcode) | (men << 5);
1720 gen_rldnm(ctx, 0, me);
1721 }
1722 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1723 /* rldimi - rldimi. */
1724 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1725 {
1726 uint32_t sh, mb, me;
1727
1728 sh = SH(ctx->opcode) | (shn << 5);
1729 mb = MB(ctx->opcode) | (mbn << 5);
1730 me = 63 - sh;
1731 if (unlikely(sh == 0 && mb == 0)) {
1732 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1733 } else {
1734 TCGv t0, t1;
1735 target_ulong mask;
1736
1737 t0 = tcg_temp_new();
1738 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1739 t1 = tcg_temp_new();
1740 mask = MASK(mb, me);
1741 tcg_gen_andi_tl(t0, t0, mask);
1742 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1743 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1744 tcg_temp_free(t0);
1745 tcg_temp_free(t1);
1746 }
1747 if (unlikely(Rc(ctx->opcode) != 0))
1748 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1749 }
1750 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1751 #endif
1752
1753 /*** Integer shift ***/
1754
1755 /* slw & slw. */
1756 static void gen_slw(DisasContext *ctx)
1757 {
1758 TCGv t0, t1;
1759
1760 t0 = tcg_temp_new();
1761 /* AND rS with a mask that is 0 when rB >= 0x20 */
1762 #if defined(TARGET_PPC64)
1763 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1764 tcg_gen_sari_tl(t0, t0, 0x3f);
1765 #else
1766 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1767 tcg_gen_sari_tl(t0, t0, 0x1f);
1768 #endif
1769 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1770 t1 = tcg_temp_new();
1771 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1772 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1773 tcg_temp_free(t1);
1774 tcg_temp_free(t0);
1775 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1776 if (unlikely(Rc(ctx->opcode) != 0))
1777 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1778 }
1779
1780 /* sraw & sraw. */
1781 static void gen_sraw(DisasContext *ctx)
1782 {
1783 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1784 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1785 if (unlikely(Rc(ctx->opcode) != 0))
1786 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1787 }
1788
1789 /* srawi & srawi. */
1790 static void gen_srawi(DisasContext *ctx)
1791 {
1792 int sh = SH(ctx->opcode);
1793 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1794 TCGv src = cpu_gpr[rS(ctx->opcode)];
1795 if (sh == 0) {
1796 tcg_gen_mov_tl(dst, src);
1797 tcg_gen_movi_tl(cpu_ca, 0);
1798 } else {
1799 TCGv t0;
1800 tcg_gen_ext32s_tl(dst, src);
1801 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1802 t0 = tcg_temp_new();
1803 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1804 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1805 tcg_temp_free(t0);
1806 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1807 tcg_gen_sari_tl(dst, dst, sh);
1808 }
1809 if (unlikely(Rc(ctx->opcode) != 0)) {
1810 gen_set_Rc0(ctx, dst);
1811 }
1812 }
1813
1814 /* srw & srw. */
1815 static void gen_srw(DisasContext *ctx)
1816 {
1817 TCGv t0, t1;
1818
1819 t0 = tcg_temp_new();
1820 /* AND rS with a mask that is 0 when rB >= 0x20 */
1821 #if defined(TARGET_PPC64)
1822 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1823 tcg_gen_sari_tl(t0, t0, 0x3f);
1824 #else
1825 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1826 tcg_gen_sari_tl(t0, t0, 0x1f);
1827 #endif
1828 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1829 tcg_gen_ext32u_tl(t0, t0);
1830 t1 = tcg_temp_new();
1831 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1832 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1833 tcg_temp_free(t1);
1834 tcg_temp_free(t0);
1835 if (unlikely(Rc(ctx->opcode) != 0))
1836 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1837 }
1838
1839 #if defined(TARGET_PPC64)
1840 /* sld & sld. */
1841 static void gen_sld(DisasContext *ctx)
1842 {
1843 TCGv t0, t1;
1844
1845 t0 = tcg_temp_new();
1846 /* AND rS with a mask that is 0 when rB >= 0x40 */
1847 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1848 tcg_gen_sari_tl(t0, t0, 0x3f);
1849 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1850 t1 = tcg_temp_new();
1851 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1852 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1853 tcg_temp_free(t1);
1854 tcg_temp_free(t0);
1855 if (unlikely(Rc(ctx->opcode) != 0))
1856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1857 }
1858
1859 /* srad & srad. */
1860 static void gen_srad(DisasContext *ctx)
1861 {
1862 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1863 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1864 if (unlikely(Rc(ctx->opcode) != 0))
1865 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1866 }
1867 /* sradi & sradi. */
1868 static inline void gen_sradi(DisasContext *ctx, int n)
1869 {
1870 int sh = SH(ctx->opcode) + (n << 5);
1871 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1872 TCGv src = cpu_gpr[rS(ctx->opcode)];
1873 if (sh == 0) {
1874 tcg_gen_mov_tl(dst, src);
1875 tcg_gen_movi_tl(cpu_ca, 0);
1876 } else {
1877 TCGv t0;
1878 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1879 t0 = tcg_temp_new();
1880 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1881 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1882 tcg_temp_free(t0);
1883 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1884 tcg_gen_sari_tl(dst, src, sh);
1885 }
1886 if (unlikely(Rc(ctx->opcode) != 0)) {
1887 gen_set_Rc0(ctx, dst);
1888 }
1889 }
1890
1891 static void gen_sradi0(DisasContext *ctx)
1892 {
1893 gen_sradi(ctx, 0);
1894 }
1895
1896 static void gen_sradi1(DisasContext *ctx)
1897 {
1898 gen_sradi(ctx, 1);
1899 }
1900
1901 /* srd & srd. */
1902 static void gen_srd(DisasContext *ctx)
1903 {
1904 TCGv t0, t1;
1905
1906 t0 = tcg_temp_new();
1907 /* AND rS with a mask that is 0 when rB >= 0x40 */
1908 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1909 tcg_gen_sari_tl(t0, t0, 0x3f);
1910 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1911 t1 = tcg_temp_new();
1912 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1913 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1914 tcg_temp_free(t1);
1915 tcg_temp_free(t0);
1916 if (unlikely(Rc(ctx->opcode) != 0))
1917 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1918 }
1919 #endif
1920
1921 /*** Floating-Point arithmetic ***/
1922 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1923 static void gen_f##name(DisasContext *ctx) \
1924 { \
1925 if (unlikely(!ctx->fpu_enabled)) { \
1926 gen_exception(ctx, POWERPC_EXCP_FPU); \
1927 return; \
1928 } \
1929 /* NIP cannot be restored if the memory exception comes from an helper */ \
1930 gen_update_nip(ctx, ctx->nip - 4); \
1931 gen_reset_fpstatus(); \
1932 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1933 cpu_fpr[rA(ctx->opcode)], \
1934 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1935 if (isfloat) { \
1936 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1937 cpu_fpr[rD(ctx->opcode)]); \
1938 } \
1939 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1940 Rc(ctx->opcode) != 0); \
1941 }
1942
1943 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1944 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1945 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1946
1947 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1948 static void gen_f##name(DisasContext *ctx) \
1949 { \
1950 if (unlikely(!ctx->fpu_enabled)) { \
1951 gen_exception(ctx, POWERPC_EXCP_FPU); \
1952 return; \
1953 } \
1954 /* NIP cannot be restored if the memory exception comes from an helper */ \
1955 gen_update_nip(ctx, ctx->nip - 4); \
1956 gen_reset_fpstatus(); \
1957 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1958 cpu_fpr[rA(ctx->opcode)], \
1959 cpu_fpr[rB(ctx->opcode)]); \
1960 if (isfloat) { \
1961 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1962 cpu_fpr[rD(ctx->opcode)]); \
1963 } \
1964 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1965 set_fprf, Rc(ctx->opcode) != 0); \
1966 }
1967 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1968 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1969 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1970
1971 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1972 static void gen_f##name(DisasContext *ctx) \
1973 { \
1974 if (unlikely(!ctx->fpu_enabled)) { \
1975 gen_exception(ctx, POWERPC_EXCP_FPU); \
1976 return; \
1977 } \
1978 /* NIP cannot be restored if the memory exception comes from an helper */ \
1979 gen_update_nip(ctx, ctx->nip - 4); \
1980 gen_reset_fpstatus(); \
1981 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1982 cpu_fpr[rA(ctx->opcode)], \
1983 cpu_fpr[rC(ctx->opcode)]); \
1984 if (isfloat) { \
1985 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1986 cpu_fpr[rD(ctx->opcode)]); \
1987 } \
1988 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1989 set_fprf, Rc(ctx->opcode) != 0); \
1990 }
1991 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1992 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1993 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1994
1995 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1996 static void gen_f##name(DisasContext *ctx) \
1997 { \
1998 if (unlikely(!ctx->fpu_enabled)) { \
1999 gen_exception(ctx, POWERPC_EXCP_FPU); \
2000 return; \
2001 } \
2002 /* NIP cannot be restored if the memory exception comes from an helper */ \
2003 gen_update_nip(ctx, ctx->nip - 4); \
2004 gen_reset_fpstatus(); \
2005 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2006 cpu_fpr[rB(ctx->opcode)]); \
2007 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2008 set_fprf, Rc(ctx->opcode) != 0); \
2009 }
2010
2011 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2012 static void gen_f##name(DisasContext *ctx) \
2013 { \
2014 if (unlikely(!ctx->fpu_enabled)) { \
2015 gen_exception(ctx, POWERPC_EXCP_FPU); \
2016 return; \
2017 } \
2018 /* NIP cannot be restored if the memory exception comes from an helper */ \
2019 gen_update_nip(ctx, ctx->nip - 4); \
2020 gen_reset_fpstatus(); \
2021 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2022 cpu_fpr[rB(ctx->opcode)]); \
2023 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2024 set_fprf, Rc(ctx->opcode) != 0); \
2025 }
2026
2027 /* fadd - fadds */
2028 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2029 /* fdiv - fdivs */
2030 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2031 /* fmul - fmuls */
2032 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2033
2034 /* fre */
2035 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2036
2037 /* fres */
2038 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2039
2040 /* frsqrte */
2041 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2042
2043 /* frsqrtes */
2044 static void gen_frsqrtes(DisasContext *ctx)
2045 {
2046 if (unlikely(!ctx->fpu_enabled)) {
2047 gen_exception(ctx, POWERPC_EXCP_FPU);
2048 return;
2049 }
2050 /* NIP cannot be restored if the memory exception comes from an helper */
2051 gen_update_nip(ctx, ctx->nip - 4);
2052 gen_reset_fpstatus();
2053 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2054 cpu_fpr[rB(ctx->opcode)]);
2055 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2056 cpu_fpr[rD(ctx->opcode)]);
2057 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2058 }
2059
2060 /* fsel */
2061 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2062 /* fsub - fsubs */
2063 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2064 /* Optional: */
2065
2066 /* fsqrt */
2067 static void gen_fsqrt(DisasContext *ctx)
2068 {
2069 if (unlikely(!ctx->fpu_enabled)) {
2070 gen_exception(ctx, POWERPC_EXCP_FPU);
2071 return;
2072 }
2073 /* NIP cannot be restored if the memory exception comes from an helper */
2074 gen_update_nip(ctx, ctx->nip - 4);
2075 gen_reset_fpstatus();
2076 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2077 cpu_fpr[rB(ctx->opcode)]);
2078 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2079 }
2080
2081 static void gen_fsqrts(DisasContext *ctx)
2082 {
2083 if (unlikely(!ctx->fpu_enabled)) {
2084 gen_exception(ctx, POWERPC_EXCP_FPU);
2085 return;
2086 }
2087 /* NIP cannot be restored if the memory exception comes from an helper */
2088 gen_update_nip(ctx, ctx->nip - 4);
2089 gen_reset_fpstatus();
2090 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2091 cpu_fpr[rB(ctx->opcode)]);
2092 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2093 cpu_fpr[rD(ctx->opcode)]);
2094 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2095 }
2096
2097 /*** Floating-Point multiply-and-add ***/
2098 /* fmadd - fmadds */
2099 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2100 /* fmsub - fmsubs */
2101 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2102 /* fnmadd - fnmadds */
2103 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2104 /* fnmsub - fnmsubs */
2105 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2106
2107 /*** Floating-Point round & convert ***/
2108 /* fctiw */
2109 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2110 /* fctiwz */
2111 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2112 /* frsp */
2113 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2114 #if defined(TARGET_PPC64)
2115 /* fcfid */
2116 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2117 /* fctid */
2118 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2119 /* fctidz */
2120 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2121 #endif
2122
2123 /* frin */
2124 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2125 /* friz */
2126 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2127 /* frip */
2128 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2129 /* frim */
2130 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2131
2132 /*** Floating-Point compare ***/
2133
2134 /* fcmpo */
2135 static void gen_fcmpo(DisasContext *ctx)
2136 {
2137 TCGv_i32 crf;
2138 if (unlikely(!ctx->fpu_enabled)) {
2139 gen_exception(ctx, POWERPC_EXCP_FPU);
2140 return;
2141 }
2142 /* NIP cannot be restored if the memory exception comes from an helper */
2143 gen_update_nip(ctx, ctx->nip - 4);
2144 gen_reset_fpstatus();
2145 crf = tcg_const_i32(crfD(ctx->opcode));
2146 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2147 cpu_fpr[rB(ctx->opcode)], crf);
2148 tcg_temp_free_i32(crf);
2149 gen_helper_float_check_status(cpu_env);
2150 }
2151
2152 /* fcmpu */
2153 static void gen_fcmpu(DisasContext *ctx)
2154 {
2155 TCGv_i32 crf;
2156 if (unlikely(!ctx->fpu_enabled)) {
2157 gen_exception(ctx, POWERPC_EXCP_FPU);
2158 return;
2159 }
2160 /* NIP cannot be restored if the memory exception comes from an helper */
2161 gen_update_nip(ctx, ctx->nip - 4);
2162 gen_reset_fpstatus();
2163 crf = tcg_const_i32(crfD(ctx->opcode));
2164 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2165 cpu_fpr[rB(ctx->opcode)], crf);
2166 tcg_temp_free_i32(crf);
2167 gen_helper_float_check_status(cpu_env);
2168 }
2169
2170 /*** Floating-point move ***/
2171 /* fabs */
2172 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2173 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2174
2175 /* fmr - fmr. */
2176 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2177 static void gen_fmr(DisasContext *ctx)
2178 {
2179 if (unlikely(!ctx->fpu_enabled)) {
2180 gen_exception(ctx, POWERPC_EXCP_FPU);
2181 return;
2182 }
2183 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2184 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2185 }
2186
2187 /* fnabs */
2188 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2189 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2190 /* fneg */
2191 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2192 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2193
2194 /*** Floating-Point status & ctrl register ***/
2195
2196 /* mcrfs */
2197 static void gen_mcrfs(DisasContext *ctx)
2198 {
2199 TCGv tmp = tcg_temp_new();
2200 int bfa;
2201
2202 if (unlikely(!ctx->fpu_enabled)) {
2203 gen_exception(ctx, POWERPC_EXCP_FPU);
2204 return;
2205 }
2206 bfa = 4 * (7 - crfS(ctx->opcode));
2207 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2208 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2209 tcg_temp_free(tmp);
2210 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2211 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2212 }
2213
2214 /* mffs */
2215 static void gen_mffs(DisasContext *ctx)
2216 {
2217 if (unlikely(!ctx->fpu_enabled)) {
2218 gen_exception(ctx, POWERPC_EXCP_FPU);
2219 return;
2220 }
2221 gen_reset_fpstatus();
2222 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2223 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2224 }
2225
2226 /* mtfsb0 */
2227 static void gen_mtfsb0(DisasContext *ctx)
2228 {
2229 uint8_t crb;
2230
2231 if (unlikely(!ctx->fpu_enabled)) {
2232 gen_exception(ctx, POWERPC_EXCP_FPU);
2233 return;
2234 }
2235 crb = 31 - crbD(ctx->opcode);
2236 gen_reset_fpstatus();
2237 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2238 TCGv_i32 t0;
2239 /* NIP cannot be restored if the memory exception comes from an helper */
2240 gen_update_nip(ctx, ctx->nip - 4);
2241 t0 = tcg_const_i32(crb);
2242 gen_helper_fpscr_clrbit(cpu_env, t0);
2243 tcg_temp_free_i32(t0);
2244 }
2245 if (unlikely(Rc(ctx->opcode) != 0)) {
2246 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2247 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2248 }
2249 }
2250
2251 /* mtfsb1 */
2252 static void gen_mtfsb1(DisasContext *ctx)
2253 {
2254 uint8_t crb;
2255
2256 if (unlikely(!ctx->fpu_enabled)) {
2257 gen_exception(ctx, POWERPC_EXCP_FPU);
2258 return;
2259 }
2260 crb = 31 - crbD(ctx->opcode);
2261 gen_reset_fpstatus();
2262 /* XXX: we pretend we can only do IEEE floating-point computations */
2263 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2264 TCGv_i32 t0;
2265 /* NIP cannot be restored if the memory exception comes from an helper */
2266 gen_update_nip(ctx, ctx->nip - 4);
2267 t0 = tcg_const_i32(crb);
2268 gen_helper_fpscr_setbit(cpu_env, t0);
2269 tcg_temp_free_i32(t0);
2270 }
2271 if (unlikely(Rc(ctx->opcode) != 0)) {
2272 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2273 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2274 }
2275 /* We can raise a differed exception */
2276 gen_helper_float_check_status(cpu_env);
2277 }
2278
2279 /* mtfsf */
2280 static void gen_mtfsf(DisasContext *ctx)
2281 {
2282 TCGv_i32 t0;
2283 int L = ctx->opcode & 0x02000000;
2284
2285 if (unlikely(!ctx->fpu_enabled)) {
2286 gen_exception(ctx, POWERPC_EXCP_FPU);
2287 return;
2288 }
2289 /* NIP cannot be restored if the memory exception comes from an helper */
2290 gen_update_nip(ctx, ctx->nip - 4);
2291 gen_reset_fpstatus();
2292 if (L)
2293 t0 = tcg_const_i32(0xff);
2294 else
2295 t0 = tcg_const_i32(FM(ctx->opcode));
2296 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2297 tcg_temp_free_i32(t0);
2298 if (unlikely(Rc(ctx->opcode) != 0)) {
2299 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2300 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2301 }
2302 /* We can raise a differed exception */
2303 gen_helper_float_check_status(cpu_env);
2304 }
2305
2306 /* mtfsfi */
2307 static void gen_mtfsfi(DisasContext *ctx)
2308 {
2309 int bf, sh;
2310 TCGv_i64 t0;
2311 TCGv_i32 t1;
2312
2313 if (unlikely(!ctx->fpu_enabled)) {
2314 gen_exception(ctx, POWERPC_EXCP_FPU);
2315 return;
2316 }
2317 bf = crbD(ctx->opcode) >> 2;
2318 sh = 7 - bf;
2319 /* NIP cannot be restored if the memory exception comes from an helper */
2320 gen_update_nip(ctx, ctx->nip - 4);
2321 gen_reset_fpstatus();
2322 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2323 t1 = tcg_const_i32(1 << sh);
2324 gen_helper_store_fpscr(cpu_env, t0, t1);
2325 tcg_temp_free_i64(t0);
2326 tcg_temp_free_i32(t1);
2327 if (unlikely(Rc(ctx->opcode) != 0)) {
2328 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2329 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2330 }
2331 /* We can raise a differed exception */
2332 gen_helper_float_check_status(cpu_env);
2333 }
2334
2335 /*** Addressing modes ***/
2336 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2337 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2338 target_long maskl)
2339 {
2340 target_long simm = SIMM(ctx->opcode);
2341
2342 simm &= ~maskl;
2343 if (rA(ctx->opcode) == 0) {
2344 #if defined(TARGET_PPC64)
2345 if (!ctx->sf_mode) {
2346 tcg_gen_movi_tl(EA, (uint32_t)simm);
2347 } else
2348 #endif
2349 tcg_gen_movi_tl(EA, simm);
2350 } else if (likely(simm != 0)) {
2351 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2352 #if defined(TARGET_PPC64)
2353 if (!ctx->sf_mode) {
2354 tcg_gen_ext32u_tl(EA, EA);
2355 }
2356 #endif
2357 } else {
2358 #if defined(TARGET_PPC64)
2359 if (!ctx->sf_mode) {
2360 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2361 } else
2362 #endif
2363 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2364 }
2365 }
2366
2367 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2368 {
2369 if (rA(ctx->opcode) == 0) {
2370 #if defined(TARGET_PPC64)
2371 if (!ctx->sf_mode) {
2372 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2373 } else
2374 #endif
2375 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2376 } else {
2377 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2378 #if defined(TARGET_PPC64)
2379 if (!ctx->sf_mode) {
2380 tcg_gen_ext32u_tl(EA, EA);
2381 }
2382 #endif
2383 }
2384 }
2385
2386 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2387 {
2388 if (rA(ctx->opcode) == 0) {
2389 tcg_gen_movi_tl(EA, 0);
2390 } else {
2391 #if defined(TARGET_PPC64)
2392 if (!ctx->sf_mode) {
2393 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2394 } else
2395 #endif
2396 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2397 }
2398 }
2399
2400 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2401 target_long val)
2402 {
2403 tcg_gen_addi_tl(ret, arg1, val);
2404 #if defined(TARGET_PPC64)
2405 if (!ctx->sf_mode) {
2406 tcg_gen_ext32u_tl(ret, ret);
2407 }
2408 #endif
2409 }
2410
2411 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2412 {
2413 int l1 = gen_new_label();
2414 TCGv t0 = tcg_temp_new();
2415 TCGv_i32 t1, t2;
2416 /* NIP cannot be restored if the memory exception comes from an helper */
2417 gen_update_nip(ctx, ctx->nip - 4);
2418 tcg_gen_andi_tl(t0, EA, mask);
2419 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2420 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2421 t2 = tcg_const_i32(0);
2422 gen_helper_raise_exception_err(cpu_env, t1, t2);
2423 tcg_temp_free_i32(t1);
2424 tcg_temp_free_i32(t2);
2425 gen_set_label(l1);
2426 tcg_temp_free(t0);
2427 }
2428
2429 /*** Integer load ***/
2430 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2431 {
2432 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2433 }
2434
2435 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2436 {
2437 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2438 }
2439
2440 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2441 {
2442 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2443 if (unlikely(ctx->le_mode)) {
2444 tcg_gen_bswap16_tl(arg1, arg1);
2445 }
2446 }
2447
2448 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2449 {
2450 if (unlikely(ctx->le_mode)) {
2451 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2452 tcg_gen_bswap16_tl(arg1, arg1);
2453 tcg_gen_ext16s_tl(arg1, arg1);
2454 } else {
2455 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2456 }
2457 }
2458
2459 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2460 {
2461 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2462 if (unlikely(ctx->le_mode)) {
2463 tcg_gen_bswap32_tl(arg1, arg1);
2464 }
2465 }
2466
2467 #if defined(TARGET_PPC64)
2468 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2469 {
2470 if (unlikely(ctx->le_mode)) {
2471 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2472 tcg_gen_bswap32_tl(arg1, arg1);
2473 tcg_gen_ext32s_tl(arg1, arg1);
2474 } else
2475 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2476 }
2477 #endif
2478
2479 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2480 {
2481 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2482 if (unlikely(ctx->le_mode)) {
2483 tcg_gen_bswap64_i64(arg1, arg1);
2484 }
2485 }
2486
2487 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2488 {
2489 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2490 }
2491
2492 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2493 {
2494 if (unlikely(ctx->le_mode)) {
2495 TCGv t0 = tcg_temp_new();
2496 tcg_gen_ext16u_tl(t0, arg1);
2497 tcg_gen_bswap16_tl(t0, t0);
2498 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2499 tcg_temp_free(t0);
2500 } else {
2501 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2502 }
2503 }
2504
2505 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2506 {
2507 if (unlikely(ctx->le_mode)) {
2508 TCGv t0 = tcg_temp_new();
2509 tcg_gen_ext32u_tl(t0, arg1);
2510 tcg_gen_bswap32_tl(t0, t0);
2511 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2512 tcg_temp_free(t0);
2513 } else {
2514 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2515 }
2516 }
2517
2518 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2519 {
2520 if (unlikely(ctx->le_mode)) {
2521 TCGv_i64 t0 = tcg_temp_new_i64();
2522 tcg_gen_bswap64_i64(t0, arg1);
2523 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2524 tcg_temp_free_i64(t0);
2525 } else
2526 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2527 }
2528
2529 #define GEN_LD(name, ldop, opc, type) \
2530 static void glue(gen_, name)(DisasContext *ctx) \
2531 { \
2532 TCGv EA; \
2533 gen_set_access_type(ctx, ACCESS_INT); \
2534 EA = tcg_temp_new(); \
2535 gen_addr_imm_index(ctx, EA, 0); \
2536 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2537 tcg_temp_free(EA); \
2538 }
2539
2540 #define GEN_LDU(name, ldop, opc, type) \
2541 static void glue(gen_, name##u)(DisasContext *ctx) \
2542 { \
2543 TCGv EA; \
2544 if (unlikely(rA(ctx->opcode) == 0 || \
2545 rA(ctx->opcode) == rD(ctx->opcode))) { \
2546 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2547 return; \
2548 } \
2549 gen_set_access_type(ctx, ACCESS_INT); \
2550 EA = tcg_temp_new(); \
2551 if (type == PPC_64B) \
2552 gen_addr_imm_index(ctx, EA, 0x03); \
2553 else \
2554 gen_addr_imm_index(ctx, EA, 0); \
2555 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2556 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2557 tcg_temp_free(EA); \
2558 }
2559
2560 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2561 static void glue(gen_, name##ux)(DisasContext *ctx) \
2562 { \
2563 TCGv EA; \
2564 if (unlikely(rA(ctx->opcode) == 0 || \
2565 rA(ctx->opcode) == rD(ctx->opcode))) { \
2566 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2567 return; \
2568 } \
2569 gen_set_access_type(ctx, ACCESS_INT); \
2570 EA = tcg_temp_new(); \
2571 gen_addr_reg_index(ctx, EA); \
2572 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2573 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2574 tcg_temp_free(EA); \
2575 }
2576
2577 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2578 static void glue(gen_, name##x)(DisasContext *ctx) \
2579 { \
2580 TCGv EA; \
2581 gen_set_access_type(ctx, ACCESS_INT); \
2582 EA = tcg_temp_new(); \
2583 gen_addr_reg_index(ctx, EA); \
2584 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2585 tcg_temp_free(EA); \
2586 }
2587 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2588 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2589
2590 #define GEN_LDS(name, ldop, op, type) \
2591 GEN_LD(name, ldop, op | 0x20, type); \
2592 GEN_LDU(name, ldop, op | 0x21, type); \
2593 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2594 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2595
2596 /* lbz lbzu lbzux lbzx */
2597 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2598 /* lha lhau lhaux lhax */
2599 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2600 /* lhz lhzu lhzux lhzx */
2601 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2602 /* lwz lwzu lwzux lwzx */
2603 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2604 #if defined(TARGET_PPC64)
2605 /* lwaux */
2606 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2607 /* lwax */
2608 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2609 /* ldux */
2610 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2611 /* ldx */
2612 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2613
2614 static void gen_ld(DisasContext *ctx)
2615 {
2616 TCGv EA;
2617 if (Rc(ctx->opcode)) {
2618 if (unlikely(rA(ctx->opcode) == 0 ||
2619 rA(ctx->opcode) == rD(ctx->opcode))) {
2620 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2621 return;
2622 }
2623 }
2624 gen_set_access_type(ctx, ACCESS_INT);
2625 EA = tcg_temp_new();
2626 gen_addr_imm_index(ctx, EA, 0x03);
2627 if (ctx->opcode & 0x02) {
2628 /* lwa (lwau is undefined) */
2629 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2630 } else {
2631 /* ld - ldu */
2632 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2633 }
2634 if (Rc(ctx->opcode))
2635 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2636 tcg_temp_free(EA);
2637 }
2638
2639 /* lq */
2640 static void gen_lq(DisasContext *ctx)
2641 {
2642 #if defined(CONFIG_USER_ONLY)
2643 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2644 #else
2645 int ra, rd;
2646 TCGv EA;
2647
2648 /* Restore CPU state */
2649 if (unlikely(ctx->mem_idx == 0)) {
2650 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2651 return;
2652 }
2653 ra = rA(ctx->opcode);
2654 rd = rD(ctx->opcode);
2655 if (unlikely((rd & 1) || rd == ra)) {
2656 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2657 return;
2658 }
2659 if (unlikely(ctx->le_mode)) {
2660 /* Little-endian mode is not handled */
2661 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2662 return;
2663 }
2664 gen_set_access_type(ctx, ACCESS_INT);
2665 EA = tcg_temp_new();
2666 gen_addr_imm_index(ctx, EA, 0x0F);
2667 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2668 gen_addr_add(ctx, EA, EA, 8);
2669 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2670 tcg_temp_free(EA);
2671 #endif
2672 }
2673 #endif
2674
2675 /*** Integer store ***/
2676 #define GEN_ST(name, stop, opc, type) \
2677 static void glue(gen_, name)(DisasContext *ctx) \
2678 { \
2679 TCGv EA; \
2680 gen_set_access_type(ctx, ACCESS_INT); \
2681 EA = tcg_temp_new(); \
2682 gen_addr_imm_index(ctx, EA, 0); \
2683 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2684 tcg_temp_free(EA); \
2685 }
2686
2687 #define GEN_STU(name, stop, opc, type) \
2688 static void glue(gen_, stop##u)(DisasContext *ctx) \
2689 { \
2690 TCGv EA; \
2691 if (unlikely(rA(ctx->opcode) == 0)) { \
2692 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2693 return; \
2694 } \
2695 gen_set_access_type(ctx, ACCESS_INT); \
2696 EA = tcg_temp_new(); \
2697 if (type == PPC_64B) \
2698 gen_addr_imm_index(ctx, EA, 0x03); \
2699 else \
2700 gen_addr_imm_index(ctx, EA, 0); \
2701 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2702 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2703 tcg_temp_free(EA); \
2704 }
2705
2706 #define GEN_STUX(name, stop, opc2, opc3, type) \
2707 static void glue(gen_, name##ux)(DisasContext *ctx) \
2708 { \
2709 TCGv EA; \
2710 if (unlikely(rA(ctx->opcode) == 0)) { \
2711 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2712 return; \
2713 } \
2714 gen_set_access_type(ctx, ACCESS_INT); \
2715 EA = tcg_temp_new(); \
2716 gen_addr_reg_index(ctx, EA); \
2717 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2718 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2719 tcg_temp_free(EA); \
2720 }
2721
2722 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2723 static void glue(gen_, name##x)(DisasContext *ctx) \
2724 { \
2725 TCGv EA; \
2726 gen_set_access_type(ctx, ACCESS_INT); \
2727 EA = tcg_temp_new(); \
2728 gen_addr_reg_index(ctx, EA); \
2729 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2730 tcg_temp_free(EA); \
2731 }
2732 #define GEN_STX(name, stop, opc2, opc3, type) \
2733 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2734
2735 #define GEN_STS(name, stop, op, type) \
2736 GEN_ST(name, stop, op | 0x20, type); \
2737 GEN_STU(name, stop, op | 0x21, type); \
2738 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2739 GEN_STX(name, stop, 0x17, op | 0x00, type)
2740
2741 /* stb stbu stbux stbx */
2742 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2743 /* sth sthu sthux sthx */
2744 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2745 /* stw stwu stwux stwx */
2746 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2747 #if defined(TARGET_PPC64)
2748 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2749 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2750
2751 static void gen_std(DisasContext *ctx)
2752 {
2753 int rs;
2754 TCGv EA;
2755
2756 rs = rS(ctx->opcode);
2757 if ((ctx->opcode & 0x3) == 0x2) {
2758 #if defined(CONFIG_USER_ONLY)
2759 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2760 #else
2761 /* stq */
2762 if (unlikely(ctx->mem_idx == 0)) {
2763 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2764 return;
2765 }
2766 if (unlikely(rs & 1)) {
2767 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2768 return;
2769 }
2770 if (unlikely(ctx->le_mode)) {
2771 /* Little-endian mode is not handled */
2772 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2773 return;
2774 }
2775 gen_set_access_type(ctx, ACCESS_INT);
2776 EA = tcg_temp_new();
2777 gen_addr_imm_index(ctx, EA, 0x03);
2778 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2779 gen_addr_add(ctx, EA, EA, 8);
2780 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2781 tcg_temp_free(EA);
2782 #endif
2783 } else {
2784 /* std / stdu */
2785 if (Rc(ctx->opcode)) {
2786 if (unlikely(rA(ctx->opcode) == 0)) {
2787 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2788 return;
2789 }
2790 }
2791 gen_set_access_type(ctx, ACCESS_INT);
2792 EA = tcg_temp_new();
2793 gen_addr_imm_index(ctx, EA, 0x03);
2794 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2795 if (Rc(ctx->opcode))
2796 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2797 tcg_temp_free(EA);
2798 }
2799 }
2800 #endif
2801 /*** Integer load and store with byte reverse ***/
2802 /* lhbrx */
2803 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2804 {
2805 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2806 if (likely(!ctx->le_mode)) {
2807 tcg_gen_bswap16_tl(arg1, arg1);
2808 }
2809 }
2810 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2811
2812 /* lwbrx */
2813 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2814 {
2815 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2816 if (likely(!ctx->le_mode)) {
2817 tcg_gen_bswap32_tl(arg1, arg1);
2818 }
2819 }
2820 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2821
2822 #if defined(TARGET_PPC64)
2823 /* ldbrx */
2824 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2825 {
2826 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2827 if (likely(!ctx->le_mode)) {
2828 tcg_gen_bswap64_tl(arg1, arg1);
2829 }
2830 }
2831 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2832 #endif /* TARGET_PPC64 */
2833
2834 /* sthbrx */
2835 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2836 {
2837 if (likely(!ctx->le_mode)) {
2838 TCGv t0 = tcg_temp_new();
2839 tcg_gen_ext16u_tl(t0, arg1);
2840 tcg_gen_bswap16_tl(t0, t0);
2841 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2842 tcg_temp_free(t0);
2843 } else {
2844 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2845 }
2846 }
2847 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2848
2849 /* stwbrx */
2850 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2851 {
2852 if (likely(!ctx->le_mode)) {
2853 TCGv t0 = tcg_temp_new();
2854 tcg_gen_ext32u_tl(t0, arg1);
2855 tcg_gen_bswap32_tl(t0, t0);
2856 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2857 tcg_temp_free(t0);
2858 } else {
2859 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2860 }
2861 }
2862 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2863
2864 #if defined(TARGET_PPC64)
2865 /* stdbrx */
2866 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2867 {
2868 if (likely(!ctx->le_mode)) {
2869 TCGv t0 = tcg_temp_new();
2870 tcg_gen_bswap64_tl(t0, arg1);
2871 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2872 tcg_temp_free(t0);
2873 } else {
2874 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2875 }
2876 }
2877 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2878 #endif /* TARGET_PPC64 */
2879
2880 /*** Integer load and store multiple ***/
2881
2882 /* lmw */
2883 static void gen_lmw(DisasContext *ctx)
2884 {
2885 TCGv t0;
2886 TCGv_i32 t1;
2887 gen_set_access_type(ctx, ACCESS_INT);
2888 /* NIP cannot be restored if the memory exception comes from an helper */
2889 gen_update_nip(ctx, ctx->nip - 4);
2890 t0 = tcg_temp_new();
2891 t1 = tcg_const_i32(rD(ctx->opcode));
2892 gen_addr_imm_index(ctx, t0, 0);
2893 gen_helper_lmw(cpu_env, t0, t1);
2894 tcg_temp_free(t0);
2895 tcg_temp_free_i32(t1);
2896 }
2897
2898 /* stmw */
2899 static void gen_stmw(DisasContext *ctx)
2900 {
2901 TCGv t0;
2902 TCGv_i32 t1;
2903 gen_set_access_type(ctx, ACCESS_INT);
2904 /* NIP cannot be restored if the memory exception comes from an helper */
2905 gen_update_nip(ctx, ctx->nip - 4);
2906 t0 = tcg_temp_new();
2907 t1 = tcg_const_i32(rS(ctx->opcode));
2908 gen_addr_imm_index(ctx, t0, 0);
2909 gen_helper_stmw(cpu_env, t0, t1);
2910 tcg_temp_free(t0);
2911 tcg_temp_free_i32(t1);
2912 }
2913
2914 /*** Integer load and store strings ***/
2915
2916 /* lswi */
2917 /* PowerPC32 specification says we must generate an exception if
2918 * rA is in the range of registers to be loaded.
2919 * In an other hand, IBM says this is valid, but rA won't be loaded.
2920 * For now, I'll follow the spec...
2921 */
2922 static void gen_lswi(DisasContext *ctx)
2923 {
2924 TCGv t0;
2925 TCGv_i32 t1, t2;
2926 int nb = NB(ctx->opcode);
2927 int start = rD(ctx->opcode);
2928 int ra = rA(ctx->opcode);
2929 int nr;
2930
2931 if (nb == 0)
2932 nb = 32;
2933 nr = nb / 4;
2934 if (unlikely(((start + nr) > 32 &&
2935 start <= ra && (start + nr - 32) > ra) ||
2936 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2937 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2938 return;
2939 }
2940 gen_set_access_type(ctx, ACCESS_INT);
2941 /* NIP cannot be restored if the memory exception comes from an helper */
2942 gen_update_nip(ctx, ctx->nip - 4);
2943 t0 = tcg_temp_new();
2944 gen_addr_register(ctx, t0);
2945 t1 = tcg_const_i32(nb);
2946 t2 = tcg_const_i32(start);
2947 gen_helper_lsw(cpu_env, t0, t1, t2);
2948 tcg_temp_free(t0);
2949 tcg_temp_free_i32(t1);
2950 tcg_temp_free_i32(t2);
2951 }
2952
2953 /* lswx */
2954 static void gen_lswx(DisasContext *ctx)
2955 {
2956 TCGv t0;
2957 TCGv_i32 t1, t2, t3;
2958 gen_set_access_type(ctx, ACCESS_INT);
2959 /* NIP cannot be restored if the memory exception comes from an helper */
2960 gen_update_nip(ctx, ctx->nip - 4);
2961 t0 = tcg_temp_new();
2962 gen_addr_reg_index(ctx, t0);
2963 t1 = tcg_const_i32(rD(ctx->opcode));
2964 t2 = tcg_const_i32(rA(ctx->opcode));
2965 t3 = tcg_const_i32(rB(ctx->opcode));
2966 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2967 tcg_temp_free(t0);
2968 tcg_temp_free_i32(t1);
2969 tcg_temp_free_i32(t2);
2970 tcg_temp_free_i32(t3);
2971 }
2972
2973 /* stswi */
2974 static void gen_stswi(DisasContext *ctx)
2975 {
2976 TCGv t0;
2977 TCGv_i32 t1, t2;
2978 int nb = NB(ctx->opcode);
2979 gen_set_access_type(ctx, ACCESS_INT);
2980 /* NIP cannot be restored if the memory exception comes from an helper */
2981 gen_update_nip(ctx, ctx->nip - 4);
2982 t0 = tcg_temp_new();
2983 gen_addr_register(ctx, t0);
2984 if (nb == 0)
2985 nb = 32;
2986 t1 = tcg_const_i32(nb);
2987 t2 = tcg_const_i32(rS(ctx->opcode));
2988 gen_helper_stsw(cpu_env, t0, t1, t2);
2989 tcg_temp_free(t0);
2990 tcg_temp_free_i32(t1);
2991 tcg_temp_free_i32(t2);
2992 }
2993
2994 /* stswx */
2995 static void gen_stswx(DisasContext *ctx)
2996 {
2997 TCGv t0;
2998 TCGv_i32 t1, t2;
2999 gen_set_access_type(ctx, ACCESS_INT);
3000 /* NIP cannot be restored if the memory exception comes from an helper */
3001 gen_update_nip(ctx, ctx->nip - 4);
3002 t0 = tcg_temp_new();
3003 gen_addr_reg_index(ctx, t0);
3004 t1 = tcg_temp_new_i32();
3005 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3006 tcg_gen_andi_i32(t1, t1, 0x7F);
3007 t2 = tcg_const_i32(rS(ctx->opcode));
3008 gen_helper_stsw(cpu_env, t0, t1, t2);
3009 tcg_temp_free(t0);
3010 tcg_temp_free_i32(t1);
3011 tcg_temp_free_i32(t2);
3012 }
3013
3014 /*** Memory synchronisation ***/
3015 /* eieio */
3016 static void gen_eieio(DisasContext *ctx)
3017 {
3018 }
3019
3020 /* isync */
3021 static void gen_isync(DisasContext *ctx)
3022 {
3023 gen_stop_exception(ctx);
3024 }
3025
3026 /* lwarx */
3027 static void gen_lwarx(DisasContext *ctx)
3028 {
3029 TCGv t0;
3030 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3031 gen_set_access_type(ctx, ACCESS_RES);
3032 t0 = tcg_temp_local_new();
3033 gen_addr_reg_index(ctx, t0);
3034 gen_check_align(ctx, t0, 0x03);
3035 gen_qemu_ld32u(ctx, gpr, t0);
3036 tcg_gen_mov_tl(cpu_reserve, t0);
3037 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3038 tcg_temp_free(t0);
3039 }
3040
3041 #if defined(CONFIG_USER_ONLY)
3042 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3043 int reg, int size)
3044 {
3045 TCGv t0 = tcg_temp_new();
3046 uint32_t save_exception = ctx->exception;
3047
3048 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3049 tcg_gen_movi_tl(t0, (size << 5) | reg);
3050 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3051 tcg_temp_free(t0);
3052 gen_update_nip(ctx, ctx->nip-4);
3053 ctx->exception = POWERPC_EXCP_BRANCH;
3054 gen_exception(ctx, POWERPC_EXCP_STCX);
3055 ctx->exception = save_exception;
3056 }
3057 #endif
3058
3059 /* stwcx. */
3060 static void gen_stwcx_(DisasContext *ctx)
3061 {
3062 TCGv t0;
3063 gen_set_access_type(ctx, ACCESS_RES);
3064 t0 = tcg_temp_local_new();
3065 gen_addr_reg_index(ctx, t0);
3066 gen_check_align(ctx, t0, 0x03);
3067 #if defined(CONFIG_USER_ONLY)
3068 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3069 #else
3070 {
3071 int l1;
3072
3073 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3074 l1 = gen_new_label();
3075 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3076 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3077 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3078 gen_set_label(l1);
3079 tcg_gen_movi_tl(cpu_reserve, -1);
3080 }
3081 #endif
3082 tcg_temp_free(t0);
3083 }
3084
3085 #if defined(TARGET_PPC64)
3086 /* ldarx */
3087 static void gen_ldarx(DisasContext *ctx)
3088 {
3089 TCGv t0;
3090 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3091 gen_set_access_type(ctx, ACCESS_RES);
3092 t0 = tcg_temp_local_new();
3093 gen_addr_reg_index(ctx, t0);
3094 gen_check_align(ctx, t0, 0x07);
3095 gen_qemu_ld64(ctx, gpr, t0);
3096 tcg_gen_mov_tl(cpu_reserve, t0);
3097 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3098 tcg_temp_free(t0);
3099 }
3100
3101 /* stdcx. */
3102 static void gen_stdcx_(DisasContext *ctx)
3103 {
3104 TCGv t0;
3105 gen_set_access_type(ctx, ACCESS_RES);
3106 t0 = tcg_temp_local_new();
3107 gen_addr_reg_index(ctx, t0);
3108 gen_check_align(ctx, t0, 0x07);
3109 #if defined(CONFIG_USER_ONLY)
3110 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3111 #else
3112 {
3113 int l1;
3114 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3115 l1 = gen_new_label();
3116 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3117 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3118 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3119 gen_set_label(l1);
3120 tcg_gen_movi_tl(cpu_reserve, -1);
3121 }
3122 #endif
3123 tcg_temp_free(t0);
3124 }
3125 #endif /* defined(TARGET_PPC64) */
3126
3127 /* sync */
3128 static void gen_sync(DisasContext *ctx)
3129 {
3130 }
3131
3132 /* wait */
3133 static void gen_wait(DisasContext *ctx)
3134 {
3135 TCGv_i32 t0 = tcg_temp_new_i32();
3136 tcg_gen_st_i32(t0, cpu_env,
3137 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3138 tcg_temp_free_i32(t0);
3139 /* Stop translation, as the CPU is supposed to sleep from now */
3140 gen_exception_err(ctx, EXCP_HLT, 1);
3141 }
3142
3143 /*** Floating-point load ***/
3144 #define GEN_LDF(name, ldop, opc, type) \
3145 static void glue(gen_, name)(DisasContext *ctx) \
3146 { \
3147 TCGv EA; \
3148 if (unlikely(!ctx->fpu_enabled)) { \
3149 gen_exception(ctx, POWERPC_EXCP_FPU); \
3150 return; \
3151 } \
3152 gen_set_access_type(ctx, ACCESS_FLOAT); \
3153 EA = tcg_temp_new(); \
3154 gen_addr_imm_index(ctx, EA, 0); \
3155 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3156 tcg_temp_free(EA); \
3157 }
3158
3159 #define GEN_LDUF(name, ldop, opc, type) \
3160 static void glue(gen_, name##u)(DisasContext *ctx) \
3161 { \
3162 TCGv EA; \
3163 if (unlikely(!ctx->fpu_enabled)) { \
3164 gen_exception(ctx, POWERPC_EXCP_FPU); \
3165 return; \
3166 } \
3167 if (unlikely(rA(ctx->opcode) == 0)) { \
3168 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3169 return; \
3170 } \
3171 gen_set_access_type(ctx, ACCESS_FLOAT); \
3172 EA = tcg_temp_new(); \
3173 gen_addr_imm_index(ctx, EA, 0); \
3174 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3175 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3176 tcg_temp_free(EA); \
3177 }
3178
3179 #define GEN_LDUXF(name, ldop, opc, type) \
3180 static void glue(gen_, name##ux)(DisasContext *ctx) \
3181 { \
3182 TCGv EA; \
3183 if (unlikely(!ctx->fpu_enabled)) { \
3184 gen_exception(ctx, POWERPC_EXCP_FPU); \
3185 return; \
3186 } \
3187 if (unlikely(rA(ctx->opcode) == 0)) { \
3188 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3189 return; \
3190 } \
3191 gen_set_access_type(ctx, ACCESS_FLOAT); \
3192 EA = tcg_temp_new(); \
3193 gen_addr_reg_index(ctx, EA); \
3194 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3195 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3196 tcg_temp_free(EA); \
3197 }
3198
3199 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3200 static void glue(gen_, name##x)(DisasContext *ctx) \
3201 { \
3202 TCGv EA; \
3203 if (unlikely(!ctx->fpu_enabled)) { \
3204 gen_exception(ctx, POWERPC_EXCP_FPU); \
3205 return; \
3206 } \
3207 gen_set_access_type(ctx, ACCESS_FLOAT); \
3208 EA = tcg_temp_new(); \
3209 gen_addr_reg_index(ctx, EA); \
3210 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3211 tcg_temp_free(EA); \
3212 }
3213
3214 #define GEN_LDFS(name, ldop, op, type) \
3215 GEN_LDF(name, ldop, op | 0x20, type); \
3216 GEN_LDUF(name, ldop, op | 0x21, type); \
3217 GEN_LDUXF(name, ldop, op | 0x01, type); \
3218 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3219
3220 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3221 {
3222 TCGv t0 = tcg_temp_new();
3223 TCGv_i32 t1 = tcg_temp_new_i32();
3224 gen_qemu_ld32u(ctx, t0, arg2);
3225 tcg_gen_trunc_tl_i32(t1, t0);
3226 tcg_temp_free(t0);
3227 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3228 tcg_temp_free_i32(t1);
3229 }
3230
3231 /* lfd lfdu lfdux lfdx */
3232 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3233 /* lfs lfsu lfsux lfsx */
3234 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3235
3236 /*** Floating-point store ***/
3237 #define GEN_STF(name, stop, opc, type) \
3238 static void glue(gen_, name)(DisasContext *ctx) \
3239 { \
3240 TCGv EA; \
3241 if (unlikely(!ctx->fpu_enabled)) { \
3242 gen_exception(ctx, POWERPC_EXCP_FPU); \
3243 return; \
3244 } \
3245 gen_set_access_type(ctx, ACCESS_FLOAT); \
3246 EA = tcg_temp_new(); \
3247 gen_addr_imm_index(ctx, EA, 0); \
3248 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3249 tcg_temp_free(EA); \
3250 }
3251
3252 #define GEN_STUF(name, stop, opc, type) \
3253 static void glue(gen_, name##u)(DisasContext *ctx) \
3254 { \
3255 TCGv EA; \
3256 if (unlikely(!ctx->fpu_enabled)) { \
3257 gen_exception(ctx, POWERPC_EXCP_FPU); \
3258 return; \
3259 } \
3260 if (unlikely(rA(ctx->opcode) == 0)) { \
3261 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3262 return; \
3263 } \
3264 gen_set_access_type(ctx, ACCESS_FLOAT); \
3265 EA = tcg_temp_new(); \
3266 gen_addr_imm_index(ctx, EA, 0); \
3267 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3268 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3269 tcg_temp_free(EA); \
3270 }
3271
3272 #define GEN_STUXF(name, stop, opc, type) \
3273 static void glue(gen_, name##ux)(DisasContext *ctx) \
3274 { \
3275 TCGv EA; \
3276 if (unlikely(!ctx->fpu_enabled)) { \
3277 gen_exception(ctx, POWERPC_EXCP_FPU); \
3278 return; \
3279 } \
3280 if (unlikely(rA(ctx->opcode) == 0)) { \
3281 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3282 return; \
3283 } \
3284 gen_set_access_type(ctx, ACCESS_FLOAT); \
3285 EA = tcg_temp_new(); \
3286 gen_addr_reg_index(ctx, EA); \
3287 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3288 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3289 tcg_temp_free(EA); \
3290 }
3291
3292 #define GEN_STXF(name, stop, opc2, opc3, type) \
3293 static void glue(gen_, name##x)(DisasContext *ctx) \
3294 { \
3295 TCGv EA; \
3296 if (unlikely(!ctx->fpu_enabled)) { \
3297 gen_exception(ctx, POWERPC_EXCP_FPU); \
3298 return; \
3299 } \
3300 gen_set_access_type(ctx, ACCESS_FLOAT); \
3301 EA = tcg_temp_new(); \
3302 gen_addr_reg_index(ctx, EA); \
3303 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3304 tcg_temp_free(EA); \
3305 }
3306
3307 #define GEN_STFS(name, stop, op, type) \
3308 GEN_STF(name, stop, op | 0x20, type); \
3309 GEN_STUF(name, stop, op | 0x21, type); \
3310 GEN_STUXF(name, stop, op | 0x01, type); \
3311 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3312
3313 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3314 {
3315 TCGv_i32 t0 = tcg_temp_new_i32();
3316 TCGv t1 = tcg_temp_new();
3317 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3318 tcg_gen_extu_i32_tl(t1, t0);
3319 tcg_temp_free_i32(t0);
3320 gen_qemu_st32(ctx, t1, arg2);
3321 tcg_temp_free(t1);
3322 }
3323
3324 /* stfd stfdu stfdux stfdx */
3325 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3326 /* stfs stfsu stfsux stfsx */
3327 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3328
3329 /* Optional: */
3330 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3331 {
3332 TCGv t0 = tcg_temp_new();
3333 tcg_gen_trunc_i64_tl(t0, arg1),
3334 gen_qemu_st32(ctx, t0, arg2);
3335 tcg_temp_free(t0);
3336 }
3337 /* stfiwx */
3338 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3339
3340 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3341 {
3342 #if defined(TARGET_PPC64)
3343 if (ctx->has_cfar)
3344 tcg_gen_movi_tl(cpu_cfar, nip);
3345 #endif
3346 }
3347
3348 /*** Branch ***/
3349 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3350 {
3351 TranslationBlock *tb;
3352 tb = ctx->tb;
3353 if (NARROW_MODE(ctx)) {
3354 dest = (uint32_t) dest;
3355 }
3356 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3357 likely(!ctx->singlestep_enabled)) {
3358 tcg_gen_goto_tb(n);
3359 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3360 tcg_gen_exit_tb((tcg_target_long)tb + n);
3361 } else {
3362 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3363 if (unlikely(ctx->singlestep_enabled)) {
3364 if ((ctx->singlestep_enabled &
3365 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3366 (ctx->exception == POWERPC_EXCP_BRANCH ||
3367 ctx->exception == POWERPC_EXCP_TRACE)) {
3368 target_ulong tmp = ctx->nip;
3369 ctx->nip = dest;
3370 gen_exception(ctx, POWERPC_EXCP_TRACE);
3371 ctx->nip = tmp;
3372 }
3373 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3374 gen_debug_exception(ctx);
3375 }
3376 }
3377 tcg_gen_exit_tb(0);
3378 }
3379 }
3380
3381 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3382 {
3383 if (NARROW_MODE(ctx)) {
3384 nip = (uint32_t)nip;
3385 }
3386 tcg_gen_movi_tl(cpu_lr, nip);
3387 }
3388
3389 /* b ba bl bla */
3390 static void gen_b(DisasContext *ctx)
3391 {
3392 target_ulong li, target;
3393
3394 ctx->exception = POWERPC_EXCP_BRANCH;
3395 /* sign extend LI */
3396 li = LI(ctx->opcode);
3397 li = (li ^ 0x02000000) - 0x02000000;
3398 if (likely(AA(ctx->opcode) == 0)) {
3399 target = ctx->nip + li - 4;
3400 } else {
3401 target = li;
3402 }
3403 if (LK(ctx->opcode)) {
3404 gen_setlr(ctx, ctx->nip);
3405 }
3406 gen_update_cfar(ctx, ctx->nip);
3407 gen_goto_tb(ctx, 0, target);
3408 }
3409
3410 #define BCOND_IM 0
3411 #define BCOND_LR 1
3412 #define BCOND_CTR 2
3413
3414 static inline void gen_bcond(DisasContext *ctx, int type)
3415 {
3416 uint32_t bo = BO(ctx->opcode);
3417 int l1;
3418 TCGv target;
3419
3420 ctx->exception = POWERPC_EXCP_BRANCH;
3421 if (type == BCOND_LR || type == BCOND_CTR) {
3422 target = tcg_temp_local_new();
3423 if (type == BCOND_CTR)
3424 tcg_gen_mov_tl(target, cpu_ctr);
3425 else
3426 tcg_gen_mov_tl(target, cpu_lr);
3427 } else {
3428 TCGV_UNUSED(target);
3429 }
3430 if (LK(ctx->opcode))
3431 gen_setlr(ctx, ctx->nip);
3432 l1 = gen_new_label();
3433 if ((bo & 0x4) == 0) {
3434 /* Decrement and test CTR */
3435 TCGv temp = tcg_temp_new();
3436 if (unlikely(type == BCOND_CTR)) {
3437 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3438 return;
3439 }
3440 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3441 if (NARROW_MODE(ctx)) {
3442 tcg_gen_ext32u_tl(temp, cpu_ctr);
3443 } else {
3444 tcg_gen_mov_tl(temp, cpu_ctr);
3445 }
3446 if (bo & 0x2) {
3447 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3448 } else {
3449 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3450 }
3451 tcg_temp_free(temp);
3452 }
3453 if ((bo & 0x10) == 0) {
3454 /* Test CR */
3455 uint32_t bi = BI(ctx->opcode);
3456 uint32_t mask = 1 << (3 - (bi & 0x03));
3457 TCGv_i32 temp = tcg_temp_new_i32();
3458
3459 if (bo & 0x8) {
3460 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3461 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3462 } else {
3463 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3464 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3465 }
3466 tcg_temp_free_i32(temp);
3467 }
3468 gen_update_cfar(ctx, ctx->nip);
3469 if (type == BCOND_IM) {
3470 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3471 if (likely(AA(ctx->opcode) == 0)) {
3472 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3473 } else {
3474 gen_goto_tb(ctx, 0, li);
3475 }
3476 gen_set_label(l1);
3477 gen_goto_tb(ctx, 1, ctx->nip);
3478 } else {
3479 if (NARROW_MODE(ctx)) {
3480 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3481 } else {
3482 tcg_gen_andi_tl(cpu_nip, target, ~3);
3483 }
3484 tcg_gen_exit_tb(0);
3485 gen_set_label(l1);
3486 gen_update_nip(ctx, ctx->nip);
3487 tcg_gen_exit_tb(0);
3488 }
3489 }
3490
3491 static void gen_bc(DisasContext *ctx)
3492 {
3493 gen_bcond(ctx, BCOND_IM);
3494 }
3495
3496 static void gen_bcctr(DisasContext *ctx)
3497 {
3498 gen_bcond(ctx, BCOND_CTR);
3499 }
3500
3501 static void gen_bclr(DisasContext *ctx)
3502 {
3503 gen_bcond(ctx, BCOND_LR);
3504 }
3505
3506 /*** Condition register logical ***/
3507 #define GEN_CRLOGIC(name, tcg_op, opc) \
3508 static void glue(gen_, name)(DisasContext *ctx) \
3509 { \
3510 uint8_t bitmask; \
3511 int sh; \
3512 TCGv_i32 t0, t1; \
3513 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3514 t0 = tcg_temp_new_i32(); \
3515 if (sh > 0) \
3516 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3517 else if (sh < 0) \
3518 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3519 else \
3520 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3521 t1 = tcg_temp_new_i32(); \
3522 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3523 if (sh > 0) \
3524 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3525 else if (sh < 0) \
3526 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3527 else \
3528 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3529 tcg_op(t0, t0, t1); \
3530 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3531 tcg_gen_andi_i32(t0, t0, bitmask); \
3532 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3533 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3534 tcg_temp_free_i32(t0); \
3535 tcg_temp_free_i32(t1); \
3536 }
3537
3538 /* crand */
3539 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3540 /* crandc */
3541 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3542 /* creqv */
3543 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3544 /* crnand */
3545 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3546 /* crnor */
3547 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3548 /* cror */
3549 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3550 /* crorc */
3551 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3552 /* crxor */
3553 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3554
3555 /* mcrf */
3556 static void gen_mcrf(DisasContext *ctx)
3557 {
3558 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3559 }
3560
3561 /*** System linkage ***/
3562
3563 /* rfi (mem_idx only) */
3564 static void gen_rfi(DisasContext *ctx)
3565 {
3566 #if defined(CONFIG_USER_ONLY)
3567 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3568 #else
3569 /* Restore CPU state */
3570 if (unlikely(!ctx->mem_idx)) {
3571 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3572 return;
3573 }
3574 gen_update_cfar(ctx, ctx->nip);
3575 gen_helper_rfi(cpu_env);
3576 gen_sync_exception(ctx);
3577 #endif
3578 }
3579
3580 #if defined(TARGET_PPC64)
3581 static void gen_rfid(DisasContext *ctx)
3582 {
3583 #if defined(CONFIG_USER_ONLY)
3584 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3585 #else
3586 /* Restore CPU state */
3587 if (unlikely(!ctx->mem_idx)) {
3588 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3589 return;
3590 }
3591 gen_update_cfar(ctx, ctx->nip);
3592 gen_helper_rfid(cpu_env);
3593 gen_sync_exception(ctx);
3594 #endif
3595 }
3596
3597 static void gen_hrfid(DisasContext *ctx)
3598 {
3599 #if defined(CONFIG_USER_ONLY)
3600 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3601 #else
3602 /* Restore CPU state */
3603 if (unlikely(ctx->mem_idx <= 1)) {
3604 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3605 return;
3606 }
3607 gen_helper_hrfid(cpu_env);
3608 gen_sync_exception(ctx);
3609 #endif
3610 }
3611 #endif
3612
3613 /* sc */
3614 #if defined(CONFIG_USER_ONLY)
3615 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3616 #else
3617 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3618 #endif
3619 static void gen_sc(DisasContext *ctx)
3620 {
3621 uint32_t lev;
3622
3623 lev = (ctx->opcode >> 5) & 0x7F;
3624 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3625 }
3626
3627 /*** Trap ***/
3628
3629 /* tw */
3630 static void gen_tw(DisasContext *ctx)
3631 {
3632 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3633 /* Update the nip since this might generate a trap exception */
3634 gen_update_nip(ctx, ctx->nip);
3635 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3636 t0);
3637 tcg_temp_free_i32(t0);
3638 }
3639
3640 /* twi */
3641 static void gen_twi(DisasContext *ctx)
3642 {
3643 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3644 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3645 /* Update the nip since this might generate a trap exception */
3646 gen_update_nip(ctx, ctx->nip);
3647 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3648 tcg_temp_free(t0);
3649 tcg_temp_free_i32(t1);
3650 }
3651
3652 #if defined(TARGET_PPC64)
3653 /* td */
3654 static void gen_td(DisasContext *ctx)
3655 {
3656 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3657 /* Update the nip since this might generate a trap exception */
3658 gen_update_nip(ctx, ctx->nip);
3659 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3660 t0);
3661 tcg_temp_free_i32(t0);
3662 }
3663
3664 /* tdi */
3665 static void gen_tdi(DisasContext *ctx)
3666 {
3667 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3668 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3669 /* Update the nip since this might generate a trap exception */
3670 gen_update_nip(ctx, ctx->nip);
3671 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3672 tcg_temp_free(t0);
3673 tcg_temp_free_i32(t1);
3674 }
3675 #endif
3676
3677 /*** Processor control ***/
3678
3679 static void gen_read_xer(TCGv dst)
3680 {
3681 TCGv t0 = tcg_temp_new();
3682 TCGv t1 = tcg_temp_new();
3683 TCGv t2 = tcg_temp_new();
3684 tcg_gen_mov_tl(dst, cpu_xer);
3685 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3686 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3687 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3688 tcg_gen_or_tl(t0, t0, t1);
3689 tcg_gen_or_tl(dst, dst, t2);
3690 tcg_gen_or_tl(dst, dst, t0);
3691 tcg_temp_free(t0);
3692 tcg_temp_free(t1);
3693 tcg_temp_free(t2);
3694 }
3695
3696 static void gen_write_xer(TCGv src)
3697 {
3698 tcg_gen_andi_tl(cpu_xer, src,
3699 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3700 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3701 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3702 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3703 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3704 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3705 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3706 }
3707
3708 /* mcrxr */
3709 static void gen_mcrxr(DisasContext *ctx)
3710 {
3711 TCGv_i32 t0 = tcg_temp_new_i32();
3712 TCGv_i32 t1 = tcg_temp_new_i32();
3713 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3714
3715 tcg_gen_trunc_tl_i32(t0, cpu_so);
3716 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3717 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3718 tcg_gen_shri_i32(t0, t0, 2);
3719 tcg_gen_shri_i32(t1, t1, 1);
3720 tcg_gen_or_i32(dst, dst, t0);
3721 tcg_gen_or_i32(dst, dst, t1);
3722 tcg_temp_free_i32(t0);
3723 tcg_temp_free_i32(t1);
3724
3725 tcg_gen_movi_tl(cpu_so, 0);
3726 tcg_gen_movi_tl(cpu_ov, 0);
3727 tcg_gen_movi_tl(cpu_ca, 0);
3728 }
3729
3730 /* mfcr mfocrf */
3731 static void gen_mfcr(DisasContext *ctx)
3732 {
3733 uint32_t crm, crn;
3734
3735 if (likely(ctx->opcode & 0x00100000)) {
3736 crm = CRM(ctx->opcode);
3737 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3738 crn = ctz32 (crm);
3739 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3740 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3741 cpu_gpr[rD(ctx->opcode)], crn * 4);
3742 }
3743 } else {
3744 TCGv_i32 t0 = tcg_temp_new_i32();
3745 tcg_gen_mov_i32(t0, cpu_crf[0]);
3746 tcg_gen_shli_i32(t0, t0, 4);
3747 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3748 tcg_gen_shli_i32(t0, t0, 4);
3749 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3750 tcg_gen_shli_i32(t0, t0, 4);
3751 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3752 tcg_gen_shli_i32(t0, t0, 4);
3753 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3754 tcg_gen_shli_i32(t0, t0, 4);
3755 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3756 tcg_gen_shli_i32(t0, t0, 4);
3757 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3758 tcg_gen_shli_i32(t0, t0, 4);
3759 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3760 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3761 tcg_temp_free_i32(t0);
3762 }
3763 }
3764
3765 /* mfmsr */
3766 static void gen_mfmsr(DisasContext *ctx)
3767 {
3768 #if defined(CONFIG_USER_ONLY)
3769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3770 #else
3771 if (unlikely(!ctx->mem_idx)) {
3772 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3773 return;
3774 }
3775 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3776 #endif
3777 }
3778
3779 static void spr_noaccess(void *opaque, int gprn, int sprn)
3780 {
3781 #if 0
3782 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3783 printf("ERROR: try to access SPR %d !\n", sprn);
3784 #endif
3785 }
3786 #define SPR_NOACCESS (&spr_noaccess)
3787
3788 /* mfspr */
3789 static inline void gen_op_mfspr(DisasContext *ctx)
3790 {
3791 void (*read_cb)(void *opaque, int gprn, int sprn);
3792 uint32_t sprn = SPR(ctx->opcode);
3793
3794 #if !defined(CONFIG_USER_ONLY)
3795 if (ctx->mem_idx == 2)
3796 read_cb = ctx->spr_cb[sprn].hea_read;
3797 else if (ctx->mem_idx)
3798 read_cb = ctx->spr_cb[sprn].oea_read;
3799 else
3800 #endif
3801 read_cb = ctx->spr_cb[sprn].uea_read;
3802 if (likely(read_cb != NULL)) {
3803 if (likely(read_cb != SPR_NOACCESS)) {
3804 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3805 } else {
3806 /* Privilege exception */
3807 /* This is a hack to avoid warnings when running Linux:
3808 * this OS breaks the PowerPC virtualisation model,
3809 * allowing userland application to read the PVR
3810 */
3811 if (sprn != SPR_PVR) {
3812 qemu_log("Trying to read privileged spr %d %03x at "
3813 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3814 printf("Trying to read privileged spr %d %03x at "
3815 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3816 }
3817 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3818 }
3819 } else {
3820 /* Not defined */
3821 qemu_log("Trying to read invalid spr %d %03x at "
3822 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3823 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3824 sprn, sprn, ctx->nip);
3825 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3826 }
3827 }
3828
3829 static void gen_mfspr(DisasContext *ctx)
3830 {
3831 gen_op_mfspr(ctx);
3832 }
3833
3834 /* mftb */
3835 static void gen_mftb(DisasContext *ctx)
3836 {
3837 gen_op_mfspr(ctx);
3838 }
3839
3840 /* mtcrf mtocrf*/
3841 static void gen_mtcrf(DisasContext *ctx)
3842 {
3843 uint32_t crm, crn;
3844
3845 crm = CRM(ctx->opcode);
3846 if (likely((ctx->opcode & 0x00100000))) {
3847 if (crm && ((crm & (crm - 1)) == 0)) {
3848 TCGv_i32 temp = tcg_temp_new_i32();
3849 crn = ctz32 (crm);
3850 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3851 tcg_gen_shri_i32(temp, temp, crn * 4);
3852 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3853 tcg_temp_free_i32(temp);
3854 }
3855 } else {
3856 TCGv_i32 temp = tcg_temp_new_i32();
3857 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3858 for (crn = 0 ; crn < 8 ; crn++) {
3859 if (crm & (1 << crn)) {
3860 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3861 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3862 }
3863 }
3864 tcg_temp_free_i32(temp);
3865 }
3866 }
3867
3868 /* mtmsr */
3869 #if defined(TARGET_PPC64)
3870 static void gen_mtmsrd(DisasContext *ctx)
3871 {
3872 #if defined(CONFIG_USER_ONLY)
3873 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3874 #else
3875 if (unlikely(!ctx->mem_idx)) {
3876 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3877 return;
3878 }
3879 if (ctx->opcode & 0x00010000) {
3880 /* Special form that does not need any synchronisation */
3881 TCGv t0 = tcg_temp_new();
3882 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3883 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3884 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3885 tcg_temp_free(t0);
3886 } else {
3887 /* XXX: we need to update nip before the store
3888 * if we enter power saving mode, we will exit the loop
3889 * directly from ppc_store_msr
3890 */
3891 gen_update_nip(ctx, ctx->nip);
3892 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3893 /* Must stop the translation as machine state (may have) changed */
3894 /* Note that mtmsr is not always defined as context-synchronizing */
3895 gen_stop_exception(ctx);
3896 }
3897 #endif
3898 }
3899 #endif
3900
3901 static void gen_mtmsr(DisasContext *ctx)
3902 {
3903 #if defined(CONFIG_USER_ONLY)
3904 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3905 #else
3906 if (unlikely(!ctx->mem_idx)) {
3907 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3908 return;
3909 }
3910 if (ctx->opcode & 0x00010000) {
3911 /* Special form that does not need any synchronisation */
3912 TCGv t0 = tcg_temp_new();
3913 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3914 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3915 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3916 tcg_temp_free(t0);
3917 } else {
3918 TCGv msr = tcg_temp_new();
3919
3920 /* XXX: we need to update nip before the store
3921 * if we enter power saving mode, we will exit the loop
3922 * directly from ppc_store_msr
3923 */
3924 gen_update_nip(ctx, ctx->nip);
3925 #if defined(TARGET_PPC64)
3926 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3927 #else
3928 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3929 #endif
3930 gen_helper_store_msr(cpu_env, msr);
3931 /* Must stop the translation as machine state (may have) changed */
3932 /* Note that mtmsr is not always defined as context-synchronizing */
3933 gen_stop_exception(ctx);
3934 }
3935 #endif
3936 }
3937
3938 /* mtspr */
3939 static void gen_mtspr(DisasContext *ctx)
3940 {
3941 void (*write_cb)(void *opaque, int sprn, int gprn);
3942 uint32_t sprn = SPR(ctx->opcode);
3943
3944 #if !defined(CONFIG_USER_ONLY)
3945 if (ctx->mem_idx == 2)
3946 write_cb = ctx->spr_cb[sprn].hea_write;
3947 else if (ctx->mem_idx)
3948 write_cb = ctx->spr_cb[sprn].oea_write;
3949 else
3950 #endif
3951 write_cb = ctx->spr_cb[sprn].uea_write;
3952 if (likely(write_cb != NULL)) {
3953 if (likely(write_cb != SPR_NOACCESS)) {
3954 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3955 } else {
3956 /* Privilege exception */
3957 qemu_log("Trying to write privileged spr %d %03x at "
3958 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3959 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3960 "\n", sprn, sprn, ctx->nip);
3961 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3962 }
3963 } else {
3964 /* Not defined */
3965 qemu_log("Trying to write invalid spr %d %03x at "
3966 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3967 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3968 sprn, sprn, ctx->nip);
3969 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3970 }
3971 }
3972
3973 /*** Cache management ***/
3974
3975 /* dcbf */
3976 static void gen_dcbf(DisasContext *ctx)
3977 {
3978 /* XXX: specification says this is treated as a load by the MMU */
3979 TCGv t0;
3980 gen_set_access_type(ctx, ACCESS_CACHE);
3981 t0 = tcg_temp_new();
3982 gen_addr_reg_index(ctx, t0);
3983 gen_qemu_ld8u(ctx, t0, t0);
3984 tcg_temp_free(t0);
3985 }
3986
3987 /* dcbi (Supervisor only) */
3988 static void gen_dcbi(DisasContext *ctx)
3989 {
3990 #if defined(CONFIG_USER_ONLY)
3991 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3992 #else
3993 TCGv EA, val;
3994 if (unlikely(!ctx->mem_idx)) {
3995 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3996 return;
3997 }
3998 EA = tcg_temp_new();
3999 gen_set_access_type(ctx, ACCESS_CACHE);
4000 gen_addr_reg_index(ctx, EA);
4001 val = tcg_temp_new();
4002 /* XXX: specification says this should be treated as a store by the MMU */
4003 gen_qemu_ld8u(ctx, val, EA);
4004 gen_qemu_st8(ctx, val, EA);
4005 tcg_temp_free(val);
4006 tcg_temp_free(EA);
4007 #endif
4008 }
4009
4010 /* dcdst */
4011 static void gen_dcbst(DisasContext *ctx)
4012 {
4013 /* XXX: specification say this is treated as a load by the MMU */
4014 TCGv t0;
4015 gen_set_access_type(ctx, ACCESS_CACHE);
4016 t0 = tcg_temp_new();
4017 gen_addr_reg_index(ctx, t0);
4018 gen_qemu_ld8u(ctx, t0, t0);
4019 tcg_temp_free(t0);
4020 }
4021
4022 /* dcbt */
4023 static void gen_dcbt(DisasContext *ctx)
4024 {
4025 /* interpreted as no-op */
4026 /* XXX: specification say this is treated as a load by the MMU
4027 * but does not generate any exception
4028 */
4029 }
4030
4031 /* dcbtst */
4032 static void gen_dcbtst(DisasContext *ctx)
4033 {
4034 /* interpreted as no-op */
4035 /* XXX: specification say this is treated as a load by the MMU
4036 * but does not generate any exception
4037 */
4038 }
4039
4040 /* dcbz */
4041 static void gen_dcbz(DisasContext *ctx)
4042 {
4043 TCGv tcgv_addr;
4044 TCGv_i32 tcgv_is_dcbzl;
4045 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4046
4047 gen_set_access_type(ctx, ACCESS_CACHE);
4048 /* NIP cannot be restored if the memory exception comes from an helper */
4049 gen_update_nip(ctx, ctx->nip - 4);
4050 tcgv_addr = tcg_temp_new();
4051 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4052
4053 gen_addr_reg_index(ctx, tcgv_addr);
4054 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4055
4056 tcg_temp_free(tcgv_addr);
4057 tcg_temp_free_i32(tcgv_is_dcbzl);
4058 }
4059
4060 /* dst / dstt */
4061 static void gen_dst(DisasContext *ctx)
4062 {
4063 if (rA(ctx->opcode) == 0) {
4064 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4065 } else {
4066 /* interpreted as no-op */
4067 }
4068 }
4069
4070 /* dstst /dststt */
4071 static void gen_dstst(DisasContext *ctx)
4072 {
4073 if (rA(ctx->opcode) == 0) {
4074 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4075 } else {
4076 /* interpreted as no-op */
4077 }
4078
4079 }
4080
4081 /* dss / dssall */
4082 static void gen_dss(DisasContext *ctx)
4083 {
4084 /* interpreted as no-op */
4085 }
4086
4087 /* icbi */
4088 static void gen_icbi(DisasContext *ctx)
4089 {
4090 TCGv t0;
4091 gen_set_access_type(ctx, ACCESS_CACHE);
4092 /* NIP cannot be restored if the memory exception comes from an helper */
4093 gen_update_nip(ctx, ctx->nip - 4);
4094 t0 = tcg_temp_new();
4095 gen_addr_reg_index(ctx, t0);
4096 gen_helper_icbi(cpu_env, t0);
4097 tcg_temp_free(t0);
4098 }
4099
4100 /* Optional: */
4101 /* dcba */
4102 static void gen_dcba(DisasContext *ctx)
4103 {
4104 /* interpreted as no-op */
4105 /* XXX: specification say this is treated as a store by the MMU
4106 * but does not generate any exception
4107 */
4108 }
4109
4110 /*** Segment register manipulation ***/
4111 /* Supervisor only: */
4112
4113 /* mfsr */
4114 static void gen_mfsr(DisasContext *ctx)
4115 {
4116 #if defined(CONFIG_USER_ONLY)
4117 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4118 #else
4119 TCGv t0;
4120 if (unlikely(!ctx->mem_idx)) {
4121 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4122 return;
4123 }
4124 t0 = tcg_const_tl(SR(ctx->opcode));
4125 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4126 tcg_temp_free(t0);
4127 #endif
4128 }
4129
4130 /* mfsrin */
4131 static void gen_mfsrin(DisasContext *ctx)
4132 {
4133 #if defined(CONFIG_USER_ONLY)
4134 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4135 #else
4136 TCGv t0;
4137 if (unlikely(!ctx->mem_idx)) {
4138 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4139 return;
4140 }
4141 t0 = tcg_temp_new();
4142 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4143 tcg_gen_andi_tl(t0, t0, 0xF);
4144 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4145 tcg_temp_free(t0);
4146 #endif
4147 }
4148
4149 /* mtsr */
4150 static void gen_mtsr(DisasContext *ctx)
4151 {
4152 #if defined(CONFIG_USER_ONLY)
4153 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4154 #else
4155 TCGv t0;
4156 if (unlikely(!ctx->mem_idx)) {
4157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4158 return;
4159 }
4160 t0 = tcg_const_tl(SR(ctx->opcode));
4161 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4162 tcg_temp_free(t0);
4163 #endif
4164 }
4165
4166 /* mtsrin */
4167 static void gen_mtsrin(DisasContext *ctx)
4168 {
4169 #if defined(CONFIG_USER_ONLY)
4170 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4171 #else
4172 TCGv t0;
4173 if (unlikely(!ctx->mem_idx)) {
4174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4175 return;
4176 }
4177 t0 = tcg_temp_new();
4178 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4179 tcg_gen_andi_tl(t0, t0, 0xF);
4180 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4181 tcg_temp_free(t0);
4182 #endif
4183 }
4184
4185 #if defined(TARGET_PPC64)
4186 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4187
4188 /* mfsr */
4189 static void gen_mfsr_64b(DisasContext *ctx)
4190 {
4191 #if defined(CONFIG_USER_ONLY)
4192 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4193 #else
4194 TCGv t0;
4195 if (unlikely(!ctx->mem_idx)) {
4196 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4197 return;
4198 }
4199 t0 = tcg_const_tl(SR(ctx->opcode));
4200 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4201 tcg_temp_free(t0);
4202 #endif
4203 }
4204
4205 /* mfsrin */
4206 static void gen_mfsrin_64b(DisasContext *ctx)
4207 {
4208 #if defined(CONFIG_USER_ONLY)
4209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4210 #else
4211 TCGv t0;
4212 if (unlikely(!ctx->mem_idx)) {
4213 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4214 return;
4215 }
4216 t0 = tcg_temp_new();
4217 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4218 tcg_gen_andi_tl(t0, t0, 0xF);
4219 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4220 tcg_temp_free(t0);
4221 #endif
4222 }
4223
4224 /* mtsr */
4225 static void gen_mtsr_64b(DisasContext *ctx)
4226 {
4227 #if defined(CONFIG_USER_ONLY)
4228 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4229 #else
4230 TCGv t0;
4231 if (unlikely(!ctx->mem_idx)) {
4232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4233 return;
4234 }
4235 t0 = tcg_const_tl(SR(ctx->opcode));
4236 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4237 tcg_temp_free(t0);
4238 #endif
4239 }
4240
4241 /* mtsrin */
4242 static void gen_mtsrin_64b(DisasContext *ctx)
4243 {
4244 #if defined(CONFIG_USER_ONLY)
4245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4246 #else
4247 TCGv t0;
4248 if (unlikely(!ctx->mem_idx)) {
4249 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4250 return;
4251 }
4252 t0 = tcg_temp_new();
4253 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4254 tcg_gen_andi_tl(t0, t0, 0xF);
4255 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4256 tcg_temp_free(t0);
4257 #endif
4258 }
4259
4260 /* slbmte */
4261 static void gen_slbmte(DisasContext *ctx)
4262 {
4263 #if defined(CONFIG_USER_ONLY)
4264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4265 #else
4266 if (unlikely(!ctx->mem_idx)) {
4267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4268 return;
4269 }
4270 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4271 cpu_gpr[rS(ctx->opcode)]);
4272 #endif
4273 }
4274
4275 static void gen_slbmfee(DisasContext *ctx)
4276 {
4277 #if defined(CONFIG_USER_ONLY)
4278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4279 #else
4280 if (unlikely(!ctx->mem_idx)) {
4281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4282 return;
4283 }
4284 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4285 cpu_gpr[rB(ctx->opcode)]);
4286 #endif
4287 }
4288
4289 static void gen_slbmfev(DisasContext *ctx)
4290 {
4291 #if defined(CONFIG_USER_ONLY)
4292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4293 #else
4294 if (unlikely(!ctx->mem_idx)) {
4295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4296 return;
4297 }
4298 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4299 cpu_gpr[rB(ctx->opcode)]);
4300 #endif
4301 }
4302 #endif /* defined(TARGET_PPC64) */
4303
4304 /*** Lookaside buffer management ***/
4305 /* Optional & mem_idx only: */
4306
4307 /* tlbia */
4308 static void gen_tlbia(DisasContext *ctx)
4309 {
4310 #if defined(CONFIG_USER_ONLY)
4311 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4312 #else
4313 if (unlikely(!ctx->mem_idx)) {
4314 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4315 return;
4316 }
4317 gen_helper_tlbia(cpu_env);
4318 #endif
4319 }
4320
4321 /* tlbiel */
4322 static void gen_tlbiel(DisasContext *ctx)
4323 {
4324 #if defined(CONFIG_USER_ONLY)
4325 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4326 #else
4327 if (unlikely(!ctx->mem_idx)) {
4328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4329 return;
4330 }
4331 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4332 #endif
4333 }
4334
4335 /* tlbie */
4336 static void gen_tlbie(DisasContext *ctx)
4337 {
4338 #if defined(CONFIG_USER_ONLY)
4339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4340 #else
4341 if (unlikely(!ctx->mem_idx)) {
4342 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4343 return;
4344 }
4345 #if defined(TARGET_PPC64)
4346 if (!ctx->sf_mode) {
4347 TCGv t0 = tcg_temp_new();
4348 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4349 gen_helper_tlbie(cpu_env, t0);
4350 tcg_temp_free(t0);
4351 } else
4352 #endif
4353 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4354 #endif
4355 }
4356
4357 /* tlbsync */
4358 static void gen_tlbsync(DisasContext *ctx)
4359 {
4360 #if defined(CONFIG_USER_ONLY)
4361 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4362 #else
4363 if (unlikely(!ctx->mem_idx)) {
4364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4365 return;
4366 }
4367 /* This has no effect: it should ensure that all previous
4368 * tlbie have completed
4369 */
4370 gen_stop_exception(ctx);
4371 #endif
4372 }
4373
4374 #if defined(TARGET_PPC64)
4375 /* slbia */
4376 static void gen_slbia(DisasContext *ctx)
4377 {
4378 #if defined(CONFIG_USER_ONLY)
4379 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4380 #else
4381 if (unlikely(!ctx->mem_idx)) {
4382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4383 return;
4384 }
4385 gen_helper_slbia(cpu_env);
4386 #endif
4387 }
4388
4389 /* slbie */
4390 static void gen_slbie(DisasContext *ctx)
4391 {
4392 #if defined(CONFIG_USER_ONLY)
4393 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4394 #else
4395 if (unlikely(!ctx->mem_idx)) {
4396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4397 return;
4398 }
4399 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4400 #endif
4401 }
4402 #endif
4403
4404 /*** External control ***/
4405 /* Optional: */
4406
4407 /* eciwx */
4408 static void gen_eciwx(DisasContext *ctx)
4409 {
4410 TCGv t0;
4411 /* Should check EAR[E] ! */
4412 gen_set_access_type(ctx, ACCESS_EXT);
4413 t0 = tcg_temp_new();
4414 gen_addr_reg_index(ctx, t0);
4415 gen_check_align(ctx, t0, 0x03);
4416 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4417 tcg_temp_free(t0);
4418 }
4419
4420 /* ecowx */
4421 static void gen_ecowx(DisasContext *ctx)
4422 {
4423 TCGv t0;
4424 /* Should check EAR[E] ! */
4425 gen_set_access_type(ctx, ACCESS_EXT);
4426 t0 = tcg_temp_new();
4427 gen_addr_reg_index(ctx, t0);
4428 gen_check_align(ctx, t0, 0x03);
4429 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4430 tcg_temp_free(t0);
4431 }
4432
4433 /* PowerPC 601 specific instructions */
4434
4435 /* abs - abs. */
4436 static void gen_abs(DisasContext *ctx)
4437 {
4438 int l1 = gen_new_label();
4439 int l2 = gen_new_label();
4440 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4441 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4442 tcg_gen_br(l2);
4443 gen_set_label(l1);
4444 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4445 gen_set_label(l2);
4446 if (unlikely(Rc(ctx->opcode) != 0))
4447 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4448 }
4449
4450 /* abso - abso. */
4451 static void gen_abso(DisasContext *ctx)
4452 {
4453 int l1 = gen_new_label();
4454 int l2 = gen_new_label();
4455 int l3 = gen_new_label();
4456 /* Start with XER OV disabled, the most likely case */
4457 tcg_gen_movi_tl(cpu_ov, 0);
4458 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4459 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4460 tcg_gen_movi_tl(cpu_ov, 1);
4461 tcg_gen_movi_tl(cpu_so, 1);
4462 tcg_gen_br(l2);
4463 gen_set_label(l1);
4464 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4465 tcg_gen_br(l3);
4466 gen_set_label(l2);
4467 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4468 gen_set_label(l3);
4469 if (unlikely(Rc(ctx->opcode) != 0))
4470 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4471 }
4472
4473 /* clcs */
4474 static void gen_clcs(DisasContext *ctx)
4475 {
4476 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4477 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4478 tcg_temp_free_i32(t0);
4479 /* Rc=1 sets CR0 to an undefined state */
4480 }
4481
4482 /* div - div. */
4483 static void gen_div(DisasContext *ctx)
4484 {
4485 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4486 cpu_gpr[rB(ctx->opcode)]);
4487 if (unlikely(Rc(ctx->opcode) != 0))
4488 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4489 }
4490
4491 /* divo - divo. */
4492 static void gen_divo(DisasContext *ctx)
4493 {
4494 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4495 cpu_gpr[rB(ctx->opcode)]);
4496 if (unlikely(Rc(ctx->opcode) != 0))
4497 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4498 }
4499
4500 /* divs - divs. */
4501 static void gen_divs(DisasContext *ctx)
4502 {
4503 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4504 cpu_gpr[rB(ctx->opcode)]);
4505 if (unlikely(Rc(ctx->opcode) != 0))
4506 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4507 }
4508
4509 /* divso - divso. */
4510 static void gen_divso(DisasContext *ctx)
4511 {
4512 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4513 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4514 if (unlikely(Rc(ctx->opcode) != 0))
4515 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4516 }
4517
4518 /* doz - doz. */
4519 static void gen_doz(DisasContext *ctx)
4520 {
4521 int l1 = gen_new_label();
4522 int l2 = gen_new_label();
4523 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4524 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4525 tcg_gen_br(l2);
4526 gen_set_label(l1);
4527 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4528 gen_set_label(l2);
4529 if (unlikely(Rc(ctx->opcode) != 0))
4530 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4531 }
4532
4533 /* dozo - dozo. */
4534 static void gen_dozo(DisasContext *ctx)
4535 {
4536 int l1 = gen_new_label();
4537 int l2 = gen_new_label();
4538 TCGv t0 = tcg_temp_new();
4539 TCGv t1 = tcg_temp_new();
4540 TCGv t2 = tcg_temp_new();
4541 /* Start with XER OV disabled, the most likely case */
4542 tcg_gen_movi_tl(cpu_ov, 0);
4543 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4544 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4545 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4546 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4547 tcg_gen_andc_tl(t1, t1, t2);
4548 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4549 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4550 tcg_gen_movi_tl(cpu_ov, 1);
4551 tcg_gen_movi_tl(cpu_so, 1);
4552 tcg_gen_br(l2);
4553 gen_set_label(l1);
4554 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4555 gen_set_label(l2);
4556 tcg_temp_free(t0);
4557 tcg_temp_free(t1);
4558 tcg_temp_free(t2);
4559 if (unlikely(Rc(ctx->opcode) != 0))
4560 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4561 }
4562
4563 /* dozi */
4564 static void gen_dozi(DisasContext *ctx)
4565 {
4566 target_long simm = SIMM(ctx->opcode);
4567 int l1 = gen_new_label();
4568 int l2 = gen_new_label();
4569 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4570 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4571 tcg_gen_br(l2);
4572 gen_set_label(l1);
4573 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4574 gen_set_label(l2);
4575 if (unlikely(Rc(ctx->opcode) != 0))
4576 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4577 }
4578
4579 /* lscbx - lscbx. */
4580 static void gen_lscbx(DisasContext *ctx)
4581 {
4582 TCGv t0 = tcg_temp_new();
4583 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4584 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4585 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4586
4587 gen_addr_reg_index(ctx, t0);
4588 /* NIP cannot be restored if the memory exception comes from an helper */
4589 gen_update_nip(ctx, ctx->nip - 4);
4590 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4591 tcg_temp_free_i32(t1);
4592 tcg_temp_free_i32(t2);
4593 tcg_temp_free_i32(t3);
4594 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4595 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4596 if (unlikely(Rc(ctx->opcode) != 0))
4597 gen_set_Rc0(ctx, t0);
4598 tcg_temp_free(t0);
4599 }
4600
4601 /* maskg - maskg. */
4602 static void gen_maskg(DisasContext *ctx)
4603 {
4604 int l1 = gen_new_label();
4605 TCGv t0 = tcg_temp_new();
4606 TCGv t1 = tcg_temp_new();
4607 TCGv t2 = tcg_temp_new();
4608 TCGv t3 = tcg_temp_new();
4609 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4610 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4611 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4612 tcg_gen_addi_tl(t2, t0, 1);
4613 tcg_gen_shr_tl(t2, t3, t2);
4614 tcg_gen_shr_tl(t3, t3, t1);
4615 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4616 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4617 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4618 gen_set_label(l1);
4619 tcg_temp_free(t0);
4620 tcg_temp_free(t1);
4621 tcg_temp_free(t2);
4622 tcg_temp_free(t3);
4623 if (unlikely(Rc(ctx->opcode) != 0))
4624 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4625 }
4626
4627 /* maskir - maskir. */
4628 static void gen_maskir(DisasContext *ctx)
4629 {
4630 TCGv t0 = tcg_temp_new();
4631 TCGv t1 = tcg_temp_new();
4632 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4633 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4634 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4635 tcg_temp_free(t0);
4636 tcg_temp_free(t1);
4637 if (unlikely(Rc(ctx->opcode) != 0))
4638 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4639 }
4640
4641 /* mul - mul. */
4642 static void gen_mul(DisasContext *ctx)
4643 {
4644 TCGv_i64 t0 = tcg_temp_new_i64();
4645 TCGv_i64 t1 = tcg_temp_new_i64();
4646 TCGv t2 = tcg_temp_new();
4647 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4648 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4649 tcg_gen_mul_i64(t0, t0, t1);
4650 tcg_gen_trunc_i64_tl(t2, t0);
4651 gen_store_spr(SPR_MQ, t2);
4652 tcg_gen_shri_i64(t1, t0, 32);
4653 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4654 tcg_temp_free_i64(t0);
4655 tcg_temp_free_i64(t1);
4656 tcg_temp_free(t2);
4657 if (unlikely(Rc(ctx->opcode) != 0))
4658 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4659 }
4660
4661 /* mulo - mulo. */
4662 static void gen_mulo(DisasContext *ctx)
4663 {
4664 int l1 = gen_new_label();
4665 TCGv_i64 t0 = tcg_temp_new_i64();
4666 TCGv_i64 t1 = tcg_temp_new_i64();
4667 TCGv t2 = tcg_temp_new();
4668 /* Start with XER OV disabled, the most likely case */
4669 tcg_gen_movi_tl(cpu_ov, 0);
4670 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4671 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4672 tcg_gen_mul_i64(t0, t0, t1);
4673 tcg_gen_trunc_i64_tl(t2, t0);
4674 gen_store_spr(SPR_MQ, t2);
4675 tcg_gen_shri_i64(t1, t0, 32);
4676 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4677 tcg_gen_ext32s_i64(t1, t0);
4678 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4679 tcg_gen_movi_tl(cpu_ov, 1);
4680 tcg_gen_movi_tl(cpu_so, 1);
4681 gen_set_label(l1);
4682 tcg_temp_free_i64(t0);
4683 tcg_temp_free_i64(t1);
4684 tcg_temp_free(t2);
4685 if (unlikely(Rc(ctx->opcode) != 0))
4686 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4687 }
4688
4689 /* nabs - nabs. */
4690 static void gen_nabs(DisasContext *ctx)
4691 {
4692 int l1 = gen_new_label();
4693 int l2 = gen_new_label();
4694 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4695 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4696 tcg_gen_br(l2);
4697 gen_set_label(l1);
4698 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4699 gen_set_label(l2);
4700 if (unlikely(Rc(ctx->opcode) != 0))
4701 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4702 }
4703
4704 /* nabso - nabso. */
4705 static void gen_nabso(DisasContext *ctx)
4706 {
4707 int l1 = gen_new_label();
4708 int l2 = gen_new_label();
4709 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4710 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4711 tcg_gen_br(l2);
4712 gen_set_label(l1);
4713 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4714 gen_set_label(l2);
4715 /* nabs never overflows */
4716 tcg_gen_movi_tl(cpu_ov, 0);
4717 if (unlikely(Rc(ctx->opcode) != 0))
4718 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4719 }
4720
4721 /* rlmi - rlmi. */
4722 static void gen_rlmi(DisasContext *ctx)
4723 {
4724 uint32_t mb = MB(ctx->opcode);
4725 uint32_t me = ME(ctx->opcode);
4726 TCGv t0 = tcg_temp_new();
4727 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4728 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4729 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4730 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4731 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4732 tcg_temp_free(t0);
4733 if (unlikely(Rc(ctx->opcode) != 0))
4734 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4735 }
4736
4737 /* rrib - rrib. */
4738 static void gen_rrib(DisasContext *ctx)
4739 {
4740 TCGv t0 = tcg_temp_new();
4741 TCGv t1 = tcg_temp_new();
4742 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4743 tcg_gen_movi_tl(t1, 0x80000000);
4744 tcg_gen_shr_tl(t1, t1, t0);
4745 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4746 tcg_gen_and_tl(t0, t0, t1);
4747 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4748 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4749 tcg_temp_free(t0);
4750 tcg_temp_free(t1);
4751 if (unlikely(Rc(ctx->opcode) != 0))
4752 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4753 }
4754
4755 /* sle - sle. */
4756 static void gen_sle(DisasContext *ctx)
4757 {
4758 TCGv t0 = tcg_temp_new();
4759 TCGv t1 = tcg_temp_new();
4760 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4761 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4762 tcg_gen_subfi_tl(t1, 32, t1);
4763 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4764 tcg_gen_or_tl(t1, t0, t1);
4765 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4766 gen_store_spr(SPR_MQ, t1);
4767 tcg_temp_free(t0);
4768 tcg_temp_free(t1);
4769 if (unlikely(Rc(ctx->opcode) != 0))
4770 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4771 }
4772
4773 /* sleq - sleq. */
4774 static void gen_sleq(DisasContext *ctx)
4775 {
4776 TCGv t0 = tcg_temp_new();
4777 TCGv t1 = tcg_temp_new();
4778 TCGv t2 = tcg_temp_new();
4779 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4780 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4781 tcg_gen_shl_tl(t2, t2, t0);
4782 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4783 gen_load_spr(t1, SPR_MQ);
4784 gen_store_spr(SPR_MQ, t0);
4785 tcg_gen_and_tl(t0, t0, t2);
4786 tcg_gen_andc_tl(t1, t1, t2);
4787 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4788 tcg_temp_free(t0);
4789 tcg_temp_free(t1);
4790 tcg_temp_free(t2);
4791 if (unlikely(Rc(ctx->opcode) != 0))
4792 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4793 }
4794
4795 /* sliq - sliq. */
4796 static void gen_sliq(DisasContext *ctx)
4797 {
4798 int sh = SH(ctx->opcode);
4799 TCGv t0 = tcg_temp_new();
4800 TCGv t1 = tcg_temp_new();
4801 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4802 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4803 tcg_gen_or_tl(t1, t0, t1);
4804 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4805 gen_store_spr(SPR_MQ, t1);
4806 tcg_temp_free(t0);
4807 tcg_temp_free(t1);
4808 if (unlikely(Rc(ctx->opcode) != 0))
4809 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4810 }
4811
4812 /* slliq - slliq. */
4813 static void gen_slliq(DisasContext *ctx)
4814 {
4815 int sh = SH(ctx->opcode);
4816 TCGv t0 = tcg_temp_new();
4817 TCGv t1 = tcg_temp_new();
4818 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4819 gen_load_spr(t1, SPR_MQ);
4820 gen_store_spr(SPR_MQ, t0);
4821 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4822 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4823 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4824 tcg_temp_free(t0);
4825 tcg_temp_free(t1);
4826 if (unlikely(Rc(ctx->opcode) != 0))
4827 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4828 }
4829
4830 /* sllq - sllq. */
4831 static void gen_sllq(DisasContext *ctx)
4832 {
4833 int l1 = gen_new_label();
4834 int l2 = gen_new_label();
4835 TCGv t0 = tcg_temp_local_new();
4836 TCGv t1 = tcg_temp_local_new();
4837 TCGv t2 = tcg_temp_local_new();
4838 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4839 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4840 tcg_gen_shl_tl(t1, t1, t2);
4841 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4842 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4843 gen_load_spr(t0, SPR_MQ);
4844 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4845 tcg_gen_br(l2);
4846 gen_set_label(l1);
4847 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4848 gen_load_spr(t2, SPR_MQ);
4849 tcg_gen_andc_tl(t1, t2, t1);
4850 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4851 gen_set_label(l2);
4852 tcg_temp_free(t0);
4853 tcg_temp_free(t1);
4854 tcg_temp_free(t2);
4855 if (unlikely(Rc(ctx->opcode) != 0))
4856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4857 }
4858
4859 /* slq - slq. */
4860 static void gen_slq(DisasContext *ctx)
4861 {
4862 int l1 = gen_new_label();
4863 TCGv t0 = tcg_temp_new();
4864 TCGv t1 = tcg_temp_new();
4865 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4866 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4867 tcg_gen_subfi_tl(t1, 32, t1);
4868 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4869 tcg_gen_or_tl(t1, t0, t1);
4870 gen_store_spr(SPR_MQ, t1);
4871 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4872 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4873 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4874 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4875 gen_set_label(l1);
4876 tcg_temp_free(t0);
4877 tcg_temp_free(t1);
4878 if (unlikely(Rc(ctx->opcode) != 0))
4879 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4880 }
4881
4882 /* sraiq - sraiq. */
4883 static void gen_sraiq(DisasContext *ctx)
4884 {
4885 int sh = SH(ctx->opcode);
4886 int l1 = gen_new_label();
4887 TCGv t0 = tcg_temp_new();
4888 TCGv t1 = tcg_temp_new();
4889 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4890 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4891 tcg_gen_or_tl(t0, t0, t1);
4892 gen_store_spr(SPR_MQ, t0);
4893 tcg_gen_movi_tl(cpu_ca, 0);
4894 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4895 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4896 tcg_gen_movi_tl(cpu_ca, 1);
4897 gen_set_label(l1);
4898 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4899 tcg_temp_free(t0);
4900 tcg_temp_free(t1);
4901 if (unlikely(Rc(ctx->opcode) != 0))
4902 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4903 }
4904
4905 /* sraq - sraq. */
4906 static void gen_sraq(DisasContext *ctx)
4907 {
4908 int l1 = gen_new_label();
4909 int l2 = gen_new_label();
4910 TCGv t0 = tcg_temp_new();
4911 TCGv t1 = tcg_temp_local_new();
4912 TCGv t2 = tcg_temp_local_new();
4913 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4914 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4915 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4916 tcg_gen_subfi_tl(t2, 32, t2);
4917 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4918 tcg_gen_or_tl(t0, t0, t2);
4919 gen_store_spr(SPR_MQ, t0);
4920 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4921 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4922 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4923 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4924 gen_set_label(l1);
4925 tcg_temp_free(t0);
4926 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4927 tcg_gen_movi_tl(cpu_ca, 0);
4928 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4929 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4930 tcg_gen_movi_tl(cpu_ca, 1);
4931 gen_set_label(l2);
4932 tcg_temp_free(t1);
4933 tcg_temp_free(t2);
4934 if (unlikely(Rc(ctx->opcode) != 0))
4935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4936 }
4937
4938 /* sre - sre. */
4939 static void gen_sre(DisasContext *ctx)
4940 {
4941 TCGv t0 = tcg_temp_new();
4942 TCGv t1 = tcg_temp_new();
4943 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4944 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4945 tcg_gen_subfi_tl(t1, 32, t1);
4946 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4947 tcg_gen_or_tl(t1, t0, t1);
4948 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4949 gen_store_spr(SPR_MQ, t1);
4950 tcg_temp_free(t0);
4951 tcg_temp_free(t1);
4952 if (unlikely(Rc(ctx->opcode) != 0))
4953 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4954 }
4955
4956 /* srea - srea. */
4957 static void gen_srea(DisasContext *ctx)
4958 {
4959 TCGv t0 = tcg_temp_new();
4960 TCGv t1 = tcg_temp_new();
4961 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4962 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4963 gen_store_spr(SPR_MQ, t0);
4964 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4965 tcg_temp_free(t0);
4966 tcg_temp_free(t1);
4967 if (unlikely(Rc(ctx->opcode) != 0))
4968 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4969 }
4970
4971 /* sreq */
4972 static void gen_sreq(DisasContext *ctx)
4973 {
4974 TCGv t0 = tcg_temp_new();
4975 TCGv t1 = tcg_temp_new();
4976 TCGv t2 = tcg_temp_new();
4977 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4978 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4979 tcg_gen_shr_tl(t1, t1, t0);
4980 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4981 gen_load_spr(t2, SPR_MQ);
4982 gen_store_spr(SPR_MQ, t0);
4983 tcg_gen_and_tl(t0, t0, t1);
4984 tcg_gen_andc_tl(t2, t2, t1);
4985 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4986 tcg_temp_free(t0);
4987 tcg_temp_free(t1);
4988 tcg_temp_free(t2);
4989 if (unlikely(Rc(ctx->opcode) != 0))
4990 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4991 }
4992
4993 /* sriq */
4994 static void gen_sriq(DisasContext *ctx)
4995 {
4996 int sh = SH(ctx->opcode);
4997 TCGv t0 = tcg_temp_new();
4998 TCGv t1 = tcg_temp_new();
4999 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5000 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5001 tcg_gen_or_tl(t1, t0, t1);
5002 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5003 gen_store_spr(SPR_MQ, t1);
5004 tcg_temp_free(t0);
5005 tcg_temp_free(t1);
5006 if (unlikely(Rc(ctx->opcode) != 0))
5007 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5008 }
5009
5010 /* srliq */
5011 static void gen_srliq(DisasContext *ctx)
5012 {
5013 int sh = SH(ctx->opcode);
5014 TCGv t0 = tcg_temp_new();
5015 TCGv t1 = tcg_temp_new();
5016 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5017 gen_load_spr(t1, SPR_MQ);
5018 gen_store_spr(SPR_MQ, t0);
5019 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5020 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5021 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5022 tcg_temp_free(t0);
5023 tcg_temp_free(t1);
5024 if (unlikely(Rc(ctx->opcode) != 0))
5025 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5026 }
5027
5028 /* srlq */
5029 static void gen_srlq(DisasContext *ctx)
5030 {
5031 int l1 = gen_new_label();
5032 int l2 = gen_new_label();
5033 TCGv t0 = tcg_temp_local_new();
5034 TCGv t1 = tcg_temp_local_new();
5035 TCGv t2 = tcg_temp_local_new();
5036 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5037 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5038 tcg_gen_shr_tl(t2, t1, t2);
5039 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5040 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5041 gen_load_spr(t0, SPR_MQ);
5042 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5043 tcg_gen_br(l2);
5044 gen_set_label(l1);
5045 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5046 tcg_gen_and_tl(t0, t0, t2);
5047 gen_load_spr(t1, SPR_MQ);
5048 tcg_gen_andc_tl(t1, t1, t2);
5049 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5050 gen_set_label(l2);
5051 tcg_temp_free(t0);
5052 tcg_temp_free(t1);
5053 tcg_temp_free(t2);
5054 if (unlikely(Rc(ctx->opcode) != 0))
5055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5056 }
5057
5058 /* srq */
5059 static void gen_srq(DisasContext *ctx)
5060 {
5061 int l1 = gen_new_label();
5062 TCGv t0 = tcg_temp_new();
5063 TCGv t1 = tcg_temp_new();
5064 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5065 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5066 tcg_gen_subfi_tl(t1, 32, t1);
5067 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5068 tcg_gen_or_tl(t1, t0, t1);
5069 gen_store_spr(SPR_MQ, t1);
5070 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5071 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5072 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5073 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5074 gen_set_label(l1);
5075 tcg_temp_free(t0);
5076 tcg_temp_free(t1);
5077 if (unlikely(Rc(ctx->opcode) != 0))
5078 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5079 }
5080
5081 /* PowerPC 602 specific instructions */
5082
5083 /* dsa */
5084 static void gen_dsa(DisasContext *ctx)
5085 {
5086 /* XXX: TODO */
5087 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5088 }
5089
5090 /* esa */
5091 static void gen_esa(DisasContext *ctx)
5092 {
5093 /* XXX: TODO */
5094 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5095 }
5096
5097 /* mfrom */
5098 static void gen_mfrom(DisasContext *ctx)
5099 {
5100 #if defined(CONFIG_USER_ONLY)
5101 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5102 #else
5103 if (unlikely(!ctx->mem_idx)) {
5104 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5105 return;
5106 }
5107 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5108 #endif
5109 }
5110
5111 /* 602 - 603 - G2 TLB management */
5112
5113 /* tlbld */
5114 static void gen_tlbld_6xx(DisasContext *ctx)
5115 {
5116 #if defined(CONFIG_USER_ONLY)
5117 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5118 #else
5119 if (unlikely(!ctx->mem_idx)) {
5120 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5121 return;
5122 }
5123 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5124 #endif
5125 }
5126
5127 /* tlbli */
5128 static void gen_tlbli_6xx(DisasContext *ctx)
5129 {
5130 #if defined(CONFIG_USER_ONLY)
5131 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5132 #else
5133 if (unlikely(!ctx->mem_idx)) {
5134 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5135 return;
5136 }
5137 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5138 #endif
5139 }
5140
5141 /* 74xx TLB management */
5142
5143 /* tlbld */
5144 static void gen_tlbld_74xx(DisasContext *ctx)
5145 {
5146 #if defined(CONFIG_USER_ONLY)
5147 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5148 #else
5149 if (unlikely(!ctx->mem_idx)) {
5150 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5151 return;
5152 }
5153 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5154 #endif
5155 }
5156
5157 /* tlbli */
5158 static void gen_tlbli_74xx(DisasContext *ctx)
5159 {
5160 #if defined(CONFIG_USER_ONLY)
5161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5162 #else
5163 if (unlikely(!ctx->mem_idx)) {
5164 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5165 return;
5166 }
5167 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5168 #endif
5169 }
5170
5171 /* POWER instructions not in PowerPC 601 */
5172
5173 /* clf */
5174 static void gen_clf(DisasContext *ctx)
5175 {
5176 /* Cache line flush: implemented as no-op */
5177 }
5178
5179 /* cli */
5180 static void gen_cli(DisasContext *ctx)
5181 {
5182 /* Cache line invalidate: privileged and treated as no-op */
5183 #if defined(CONFIG_USER_ONLY)
5184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5185 #else
5186 if (unlikely(!ctx->mem_idx)) {
5187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5188 return;
5189 }
5190 #endif
5191 }
5192
5193 /* dclst */
5194 static void gen_dclst(DisasContext *ctx)
5195 {
5196 /* Data cache line store: treated as no-op */
5197 }
5198
5199 static void gen_mfsri(DisasContext *ctx)
5200 {
5201 #if defined(CONFIG_USER_ONLY)
5202 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5203 #else
5204 int ra = rA(ctx->opcode);
5205 int rd = rD(ctx->opcode);
5206 TCGv t0;
5207 if (unlikely(!ctx->mem_idx)) {
5208 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5209 return;
5210 }
5211 t0 = tcg_temp_new();
5212 gen_addr_reg_index(ctx, t0);
5213 tcg_gen_shri_tl(t0, t0, 28);
5214 tcg_gen_andi_tl(t0, t0, 0xF);
5215 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5216 tcg_temp_free(t0);
5217 if (ra != 0 && ra != rd)
5218 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5219 #endif
5220 }
5221
5222 static void gen_rac(DisasContext *ctx)
5223 {
5224 #if defined(CONFIG_USER_ONLY)
5225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5226 #else
5227 TCGv t0;
5228 if (unlikely(!ctx->mem_idx)) {
5229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5230 return;
5231 }
5232 t0 = tcg_temp_new();
5233 gen_addr_reg_index(ctx, t0);
5234 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5235 tcg_temp_free(t0);
5236 #endif
5237 }
5238
5239 static void gen_rfsvc(DisasContext *ctx)
5240 {
5241 #if defined(CONFIG_USER_ONLY)
5242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5243 #else
5244 if (unlikely(!ctx->mem_idx)) {
5245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5246 return;
5247 }
5248 gen_helper_rfsvc(cpu_env);
5249 gen_sync_exception(ctx);
5250 #endif
5251 }
5252
5253 /* svc is not implemented for now */
5254
5255 /* POWER2 specific instructions */
5256 /* Quad manipulation (load/store two floats at a time) */
5257
5258 /* lfq */
5259 static void gen_lfq(DisasContext *ctx)
5260 {
5261 int rd = rD(ctx->opcode);
5262 TCGv t0;
5263 gen_set_access_type(ctx, ACCESS_FLOAT);
5264 t0 = tcg_temp_new();
5265 gen_addr_imm_index(ctx, t0, 0);
5266 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5267 gen_addr_add(ctx, t0, t0, 8);
5268 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5269 tcg_temp_free(t0);
5270 }
5271
5272 /* lfqu */
5273 static void gen_lfqu(DisasContext *ctx)
5274 {
5275 int ra = rA(ctx->opcode);
5276 int rd = rD(ctx->opcode);
5277 TCGv t0, t1;
5278 gen_set_access_type(ctx, ACCESS_FLOAT);
5279 t0 = tcg_temp_new();
5280 t1 = tcg_temp_new();
5281 gen_addr_imm_index(ctx, t0, 0);
5282 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5283 gen_addr_add(ctx, t1, t0, 8);
5284 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5285 if (ra != 0)
5286 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5287 tcg_temp_free(t0);
5288 tcg_temp_free(t1);
5289 }
5290
5291 /* lfqux */
5292 static void gen_lfqux(DisasContext *ctx)
5293 {
5294 int ra = rA(ctx->opcode);
5295 int rd = rD(ctx->opcode);
5296 gen_set_access_type(ctx, ACCESS_FLOAT);
5297 TCGv t0, t1;
5298 t0 = tcg_temp_new();
5299 gen_addr_reg_index(ctx, t0);
5300 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5301 t1 = tcg_temp_new();
5302 gen_addr_add(ctx, t1, t0, 8);
5303 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5304 tcg_temp_free(t1);
5305 if (ra != 0)
5306 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5307 tcg_temp_free(t0);
5308 }
5309
5310 /* lfqx */
5311 static void gen_lfqx(DisasContext *ctx)
5312 {
5313 int rd = rD(ctx->opcode);
5314 TCGv t0;
5315 gen_set_access_type(ctx, ACCESS_FLOAT);
5316 t0 = tcg_temp_new();
5317 gen_addr_reg_index(ctx, t0);
5318 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5319 gen_addr_add(ctx, t0, t0, 8);
5320 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5321 tcg_temp_free(t0);
5322 }
5323
5324 /* stfq */
5325 static void gen_stfq(DisasContext *ctx)
5326 {
5327 int rd = rD(ctx->opcode);
5328 TCGv t0;
5329 gen_set_access_type(ctx, ACCESS_FLOAT);
5330 t0 = tcg_temp_new();
5331 gen_addr_imm_index(ctx, t0, 0);
5332 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5333 gen_addr_add(ctx, t0, t0, 8);
5334 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5335 tcg_temp_free(t0);
5336 }
5337
5338 /* stfqu */
5339 static void gen_stfqu(DisasContext *ctx)
5340 {
5341 int ra = rA(ctx->opcode);
5342 int rd = rD(ctx->opcode);
5343 TCGv t0, t1;
5344 gen_set_access_type(ctx, ACCESS_FLOAT);
5345 t0 = tcg_temp_new();
5346 gen_addr_imm_index(ctx, t0, 0);
5347 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5348 t1 = tcg_temp_new();
5349 gen_addr_add(ctx, t1, t0, 8);
5350 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5351 tcg_temp_free(t1);
5352 if (ra != 0)
5353 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5354 tcg_temp_free(t0);
5355 }
5356
5357 /* stfqux */
5358 static void gen_stfqux(DisasContext *ctx)
5359 {
5360 int ra = rA(ctx->opcode);
5361 int rd = rD(ctx->opcode);
5362 TCGv t0, t1;
5363 gen_set_access_type(ctx, ACCESS_FLOAT);
5364 t0 = tcg_temp_new();
5365 gen_addr_reg_index(ctx, t0);
5366 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5367 t1 = tcg_temp_new();
5368 gen_addr_add(ctx, t1, t0, 8);
5369 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5370 tcg_temp_free(t1);
5371 if (ra != 0)
5372 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5373 tcg_temp_free(t0);
5374 }
5375
5376 /* stfqx */
5377 static void gen_stfqx(DisasContext *ctx)
5378 {
5379 int rd = rD(ctx->opcode);
5380 TCGv t0;
5381 gen_set_access_type(ctx, ACCESS_FLOAT);
5382 t0 = tcg_temp_new();
5383 gen_addr_reg_index(ctx, t0);
5384 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5385 gen_addr_add(ctx, t0, t0, 8);
5386 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5387 tcg_temp_free(t0);
5388 }
5389
5390 /* BookE specific instructions */
5391
5392 /* XXX: not implemented on 440 ? */
5393 static void gen_mfapidi(DisasContext *ctx)
5394 {
5395 /* XXX: TODO */
5396 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5397 }
5398
5399 /* XXX: not implemented on 440 ? */
5400 static void gen_tlbiva(DisasContext *ctx)
5401 {
5402 #if defined(CONFIG_USER_ONLY)
5403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5404 #else
5405 TCGv t0;
5406 if (unlikely(!ctx->mem_idx)) {
5407 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5408 return;
5409 }
5410 t0 = tcg_temp_new();
5411 gen_addr_reg_index(ctx, t0);
5412 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5413 tcg_temp_free(t0);
5414 #endif
5415 }
5416
5417 /* All 405 MAC instructions are translated here */
5418 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5419 int ra, int rb, int rt, int Rc)
5420 {
5421 TCGv t0, t1;
5422
5423 t0 = tcg_temp_local_new();
5424 t1 = tcg_temp_local_new();
5425
5426 switch (opc3 & 0x0D) {
5427 case 0x05:
5428 /* macchw - macchw. - macchwo - macchwo. */
5429 /* macchws - macchws. - macchwso - macchwso. */
5430 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5431 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5432 /* mulchw - mulchw. */
5433 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5434 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5435 tcg_gen_ext16s_tl(t1, t1);
5436 break;
5437 case 0x04:
5438 /* macchwu - macchwu. - macchwuo - macchwuo. */
5439 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5440 /* mulchwu - mulchwu. */
5441 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5442 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5443 tcg_gen_ext16u_tl(t1, t1);
5444 break;
5445 case 0x01:
5446 /* machhw - machhw. - machhwo - machhwo. */
5447 /* machhws - machhws. - machhwso - machhwso. */
5448 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5449 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5450 /* mulhhw - mulhhw. */
5451 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5452 tcg_gen_ext16s_tl(t0, t0);
5453 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5454 tcg_gen_ext16s_tl(t1, t1);
5455 break;
5456 case 0x00:
5457 /* machhwu - machhwu. - machhwuo - machhwuo. */
5458 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5459 /* mulhhwu - mulhhwu. */
5460 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5461 tcg_gen_ext16u_tl(t0, t0);
5462 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5463 tcg_gen_ext16u_tl(t1, t1);
5464 break;
5465 case 0x0D:
5466 /* maclhw - maclhw. - maclhwo - maclhwo. */
5467 /* maclhws - maclhws. - maclhwso - maclhwso. */
5468 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5469 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5470 /* mullhw - mullhw. */
5471 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5472 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5473 break;
5474 case 0x0C:
5475 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5476 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5477 /* mullhwu - mullhwu. */
5478 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5479 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5480 break;
5481 }
5482 if (opc2 & 0x04) {
5483 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5484 tcg_gen_mul_tl(t1, t0, t1);
5485 if (opc2 & 0x02) {
5486 /* nmultiply-and-accumulate (0x0E) */
5487 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5488 } else {
5489 /* multiply-and-accumulate (0x0C) */
5490 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5491 }
5492
5493 if (opc3 & 0x12) {
5494 /* Check overflow and/or saturate */
5495 int l1 = gen_new_label();
5496
5497 if (opc3 & 0x10) {
5498 /* Start with XER OV disabled, the most likely case */
5499 tcg_gen_movi_tl(cpu_ov, 0);
5500 }
5501 if (opc3 & 0x01) {
5502 /* Signed */
5503 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5504 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5505 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5506 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5507 if (opc3 & 0x02) {
5508 /* Saturate */
5509 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5510 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5511 }
5512 } else {
5513 /* Unsigned */
5514 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5515 if (opc3 & 0x02) {
5516 /* Saturate */
5517 tcg_gen_movi_tl(t0, UINT32_MAX);
5518 }
5519 }
5520 if (opc3 & 0x10) {
5521 /* Check overflow */
5522 tcg_gen_movi_tl(cpu_ov, 1);
5523 tcg_gen_movi_tl(cpu_so, 1);
5524 }
5525 gen_set_label(l1);
5526 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5527 }
5528 } else {
5529 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5530 }
5531 tcg_temp_free(t0);
5532 tcg_temp_free(t1);
5533 if (unlikely(Rc) != 0) {
5534 /* Update Rc0 */
5535 gen_set_Rc0(ctx, cpu_gpr[rt]);
5536 }
5537 }
5538
5539 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5540 static void glue(gen_, name)(DisasContext *ctx) \
5541 { \
5542 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5543 rD(ctx->opcode), Rc(ctx->opcode)); \
5544 }
5545
5546 /* macchw - macchw. */
5547 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5548 /* macchwo - macchwo. */
5549 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5550 /* macchws - macchws. */
5551 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5552 /* macchwso - macchwso. */
5553 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5554 /* macchwsu - macchwsu. */
5555 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5556 /* macchwsuo - macchwsuo. */
5557 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5558 /* macchwu - macchwu. */
5559 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5560 /* macchwuo - macchwuo. */
5561 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5562 /* machhw - machhw. */
5563 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5564 /* machhwo - machhwo. */
5565 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5566 /* machhws - machhws. */
5567 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5568 /* machhwso - machhwso. */
5569 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5570 /* machhwsu - machhwsu. */
5571 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5572 /* machhwsuo - machhwsuo. */
5573 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5574 /* machhwu - machhwu. */
5575 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5576 /* machhwuo - machhwuo. */
5577 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5578 /* maclhw - maclhw. */
5579 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5580 /* maclhwo - maclhwo. */
5581 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5582 /* maclhws - maclhws. */
5583 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5584 /* maclhwso - maclhwso. */
5585 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5586 /* maclhwu - maclhwu. */
5587 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5588 /* maclhwuo - maclhwuo. */
5589 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5590 /* maclhwsu - maclhwsu. */
5591 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5592 /* maclhwsuo - maclhwsuo. */
5593 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5594 /* nmacchw - nmacchw. */
5595 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5596 /* nmacchwo - nmacchwo. */
5597 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5598 /* nmacchws - nmacchws. */
5599 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5600 /* nmacchwso - nmacchwso. */
5601 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5602 /* nmachhw - nmachhw. */
5603 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5604 /* nmachhwo - nmachhwo. */
5605 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5606 /* nmachhws - nmachhws. */
5607 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5608 /* nmachhwso - nmachhwso. */
5609 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5610 /* nmaclhw - nmaclhw. */
5611 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5612 /* nmaclhwo - nmaclhwo. */
5613 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5614 /* nmaclhws - nmaclhws. */
5615 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5616 /* nmaclhwso - nmaclhwso. */
5617 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5618
5619 /* mulchw - mulchw. */
5620 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5621 /* mulchwu - mulchwu. */
5622 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5623 /* mulhhw - mulhhw. */
5624 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5625 /* mulhhwu - mulhhwu. */
5626 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5627 /* mullhw - mullhw. */
5628 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5629 /* mullhwu - mullhwu. */
5630 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5631
5632 /* mfdcr */
5633 static void gen_mfdcr(DisasContext *ctx)
5634 {
5635 #if defined(CONFIG_USER_ONLY)
5636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5637 #else
5638 TCGv dcrn;
5639 if (unlikely(!ctx->mem_idx)) {
5640 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5641 return;
5642 }
5643 /* NIP cannot be restored if the memory exception comes from an helper */
5644 gen_update_nip(ctx, ctx->nip - 4);
5645 dcrn = tcg_const_tl(SPR(ctx->opcode));
5646 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5647 tcg_temp_free(dcrn);
5648 #endif
5649 }
5650
5651 /* mtdcr */
5652 static void gen_mtdcr(DisasContext *ctx)
5653 {
5654 #if defined(CONFIG_USER_ONLY)
5655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5656 #else
5657 TCGv dcrn;
5658 if (unlikely(!ctx->mem_idx)) {
5659 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5660 return;
5661 }
5662 /* NIP cannot be restored if the memory exception comes from an helper */
5663 gen_update_nip(ctx, ctx->nip - 4);
5664 dcrn = tcg_const_tl(SPR(ctx->opcode));
5665 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5666 tcg_temp_free(dcrn);
5667 #endif
5668 }
5669
5670 /* mfdcrx */
5671 /* XXX: not implemented on 440 ? */
5672 static void gen_mfdcrx(DisasContext *ctx)
5673 {
5674 #if defined(CONFIG_USER_ONLY)
5675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5676 #else
5677 if (unlikely(!ctx->mem_idx)) {
5678 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5679 return;
5680 }
5681 /* NIP cannot be restored if the memory exception comes from an helper */
5682 gen_update_nip(ctx, ctx->nip - 4);
5683 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5684 cpu_gpr[rA(ctx->opcode)]);
5685 /* Note: Rc update flag set leads to undefined state of Rc0 */
5686 #endif
5687 }
5688
5689 /* mtdcrx */
5690 /* XXX: not implemented on 440 ? */
5691 static void gen_mtdcrx(DisasContext *ctx)
5692 {
5693 #if defined(CONFIG_USER_ONLY)
5694 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5695 #else
5696 if (unlikely(!ctx->mem_idx)) {
5697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5698 return;
5699 }
5700 /* NIP cannot be restored if the memory exception comes from an helper */
5701 gen_update_nip(ctx, ctx->nip - 4);
5702 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5703 cpu_gpr[rS(ctx->opcode)]);
5704 /* Note: Rc update flag set leads to undefined state of Rc0 */
5705 #endif
5706 }
5707
5708 /* mfdcrux (PPC 460) : user-mode access to DCR */
5709 static void gen_mfdcrux(DisasContext *ctx)
5710 {
5711 /* NIP cannot be restored if the memory exception comes from an helper */
5712 gen_update_nip(ctx, ctx->nip - 4);
5713 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5714 cpu_gpr[rA(ctx->opcode)]);
5715 /* Note: Rc update flag set leads to undefined state of Rc0 */
5716 }
5717
5718 /* mtdcrux (PPC 460) : user-mode access to DCR */
5719 static void gen_mtdcrux(DisasContext *ctx)
5720 {
5721 /* NIP cannot be restored if the memory exception comes from an helper */
5722 gen_update_nip(ctx, ctx->nip - 4);
5723 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5724 cpu_gpr[rS(ctx->opcode)]);
5725 /* Note: Rc update flag set leads to undefined state of Rc0 */
5726 }
5727
5728 /* dccci */
5729 static void gen_dccci(DisasContext *ctx)
5730 {
5731 #if defined(CONFIG_USER_ONLY)
5732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5733 #else
5734 if (unlikely(!ctx->mem_idx)) {
5735 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5736 return;
5737 }
5738 /* interpreted as no-op */
5739 #endif
5740 }
5741
5742 /* dcread */
5743 static void gen_dcread(DisasContext *ctx)
5744 {
5745 #if defined(CONFIG_USER_ONLY)
5746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5747 #else
5748 TCGv EA, val;
5749 if (unlikely(!ctx->mem_idx)) {
5750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5751 return;
5752 }
5753 gen_set_access_type(ctx, ACCESS_CACHE);
5754 EA = tcg_temp_new();
5755 gen_addr_reg_index(ctx, EA);
5756 val = tcg_temp_new();
5757 gen_qemu_ld32u(ctx, val, EA);
5758 tcg_temp_free(val);
5759 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5760 tcg_temp_free(EA);
5761 #endif
5762 }
5763
5764 /* icbt */
5765 static void gen_icbt_40x(DisasContext *ctx)
5766 {
5767 /* interpreted as no-op */
5768 /* XXX: specification say this is treated as a load by the MMU
5769 * but does not generate any exception
5770 */
5771 }
5772
5773 /* iccci */
5774 static void gen_iccci(DisasContext *ctx)
5775 {
5776 #if defined(CONFIG_USER_ONLY)
5777 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5778 #else
5779 if (unlikely(!ctx->mem_idx)) {
5780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5781 return;
5782 }
5783 /* interpreted as no-op */
5784 #endif
5785 }
5786
5787 /* icread */
5788 static void gen_icread(DisasContext *ctx)
5789 {
5790 #if defined(CONFIG_USER_ONLY)
5791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5792 #else
5793 if (unlikely(!ctx->mem_idx)) {
5794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5795 return;
5796 }
5797 /* interpreted as no-op */
5798 #endif
5799 }
5800
5801 /* rfci (mem_idx only) */
5802 static void gen_rfci_40x(DisasContext *ctx)
5803 {
5804 #if defined(CONFIG_USER_ONLY)
5805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5806 #else
5807 if (unlikely(!ctx->mem_idx)) {
5808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5809 return;
5810 }
5811 /* Restore CPU state */
5812 gen_helper_40x_rfci(cpu_env);
5813 gen_sync_exception(ctx);
5814 #endif
5815 }
5816
5817 static void gen_rfci(DisasContext *ctx)
5818 {
5819 #if defined(CONFIG_USER_ONLY)
5820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5821 #else
5822 if (unlikely(!ctx->mem_idx)) {
5823 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5824 return;
5825 }
5826 /* Restore CPU state */
5827 gen_helper_rfci(cpu_env);
5828 gen_sync_exception(ctx);
5829 #endif
5830 }
5831
5832 /* BookE specific */
5833
5834 /* XXX: not implemented on 440 ? */
5835 static void gen_rfdi(DisasContext *ctx)
5836 {
5837 #if defined(CONFIG_USER_ONLY)
5838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5839 #else
5840 if (unlikely(!ctx->mem_idx)) {
5841 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5842 return;
5843 }
5844 /* Restore CPU state */
5845 gen_helper_rfdi(cpu_env);
5846 gen_sync_exception(ctx);
5847 #endif
5848 }
5849
5850 /* XXX: not implemented on 440 ? */
5851 static void gen_rfmci(DisasContext *ctx)
5852 {
5853 #if defined(CONFIG_USER_ONLY)
5854 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5855 #else
5856 if (unlikely(!ctx->mem_idx)) {
5857 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5858 return;
5859 }
5860 /* Restore CPU state */
5861 gen_helper_rfmci(cpu_env);
5862 gen_sync_exception(ctx);
5863 #endif
5864 }
5865
5866 /* TLB management - PowerPC 405 implementation */
5867
5868 /* tlbre */
5869 static void gen_tlbre_40x(DisasContext *ctx)
5870 {
5871 #if defined(CONFIG_USER_ONLY)
5872 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5873 #else
5874 if (unlikely(!ctx->mem_idx)) {
5875 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5876 return;
5877 }
5878 switch (rB(ctx->opcode)) {
5879 case 0:
5880 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5881 cpu_gpr[rA(ctx->opcode)]);
5882 break;
5883 case 1:
5884 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5885 cpu_gpr[rA(ctx->opcode)]);
5886 break;
5887 default:
5888 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5889 break;
5890 }
5891 #endif
5892 }
5893
5894 /* tlbsx - tlbsx. */
5895 static void gen_tlbsx_40x(DisasContext *ctx)
5896 {
5897 #if defined(CONFIG_USER_ONLY)
5898 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5899 #else
5900 TCGv t0;
5901 if (unlikely(!ctx->mem_idx)) {
5902 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5903 return;
5904 }
5905 t0 = tcg_temp_new();
5906 gen_addr_reg_index(ctx, t0);
5907 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5908 tcg_temp_free(t0);
5909 if (Rc(ctx->opcode)) {
5910 int l1 = gen_new_label();
5911 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5912 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5913 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5914 gen_set_label(l1);
5915 }
5916 #endif
5917 }
5918
5919 /* tlbwe */
5920 static void gen_tlbwe_40x(DisasContext *ctx)
5921 {
5922 #if defined(CONFIG_USER_ONLY)
5923 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5924 #else
5925 if (unlikely(!ctx->mem_idx)) {
5926 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5927 return;
5928 }
5929 switch (rB(ctx->opcode)) {
5930 case 0:
5931 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5932 cpu_gpr[rS(ctx->opcode)]);
5933 break;
5934 case 1:
5935 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5936 cpu_gpr[rS(ctx->opcode)]);
5937 break;
5938 default:
5939 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5940 break;
5941 }
5942 #endif
5943 }
5944
5945 /* TLB management - PowerPC 440 implementation */
5946
5947 /* tlbre */
5948 static void gen_tlbre_440(DisasContext *ctx)
5949 {
5950 #if defined(CONFIG_USER_ONLY)
5951 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5952 #else
5953 if (unlikely(!ctx->mem_idx)) {
5954 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5955 return;
5956 }
5957 switch (rB(ctx->opcode)) {
5958 case 0:
5959 case 1:
5960 case 2:
5961 {
5962 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5963 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5964 t0, cpu_gpr[rA(ctx->opcode)]);
5965 tcg_temp_free_i32(t0);
5966 }
5967 break;
5968 default:
5969 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5970 break;
5971 }
5972 #endif
5973 }
5974
5975 /* tlbsx - tlbsx. */
5976 static void gen_tlbsx_440(DisasContext *ctx)
5977 {
5978 #if defined(CONFIG_USER_ONLY)
5979 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5980 #else
5981 TCGv t0;
5982 if (unlikely(!ctx->mem_idx)) {
5983 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5984 return;
5985 }
5986 t0 = tcg_temp_new();
5987 gen_addr_reg_index(ctx, t0);
5988 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5989 tcg_temp_free(t0);
5990 if (Rc(ctx->opcode)) {
5991 int l1 = gen_new_label();
5992 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5993 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5994 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5995 gen_set_label(l1);
5996 }
5997 #endif
5998 }
5999
6000 /* tlbwe */
6001 static void gen_tlbwe_440(DisasContext *ctx)
6002 {
6003 #if defined(CONFIG_USER_ONLY)
6004 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6005 #else
6006 if (unlikely(!ctx->mem_idx)) {
6007 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6008 return;
6009 }
6010 switch (rB(ctx->opcode)) {
6011 case 0:
6012 case 1:
6013 case 2:
6014 {
6015 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6016 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6017 cpu_gpr[rS(ctx->opcode)]);
6018 tcg_temp_free_i32(t0);
6019 }
6020 break;
6021 default:
6022 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6023 break;
6024 }
6025 #endif
6026 }
6027
6028 /* TLB management - PowerPC BookE 2.06 implementation */
6029
6030 /* tlbre */
6031 static void gen_tlbre_booke206(DisasContext *ctx)
6032 {
6033 #if defined(CONFIG_USER_ONLY)
6034 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6035 #else
6036 if (unlikely(!ctx->mem_idx)) {
6037 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6038 return;
6039 }
6040
6041 gen_helper_booke206_tlbre(cpu_env);
6042 #endif
6043 }
6044
6045 /* tlbsx - tlbsx. */
6046 static void gen_tlbsx_booke206(DisasContext *ctx)
6047 {
6048 #if defined(CONFIG_USER_ONLY)
6049 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6050 #else
6051 TCGv t0;
6052 if (unlikely(!ctx->mem_idx)) {
6053 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6054 return;
6055 }
6056
6057 if (rA(ctx->opcode)) {
6058 t0 = tcg_temp_new();
6059 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6060 } else {
6061 t0 = tcg_const_tl(0);
6062 }
6063
6064 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6065 gen_helper_booke206_tlbsx(cpu_env, t0);
6066 #endif
6067 }
6068
6069 /* tlbwe */
6070 static void gen_tlbwe_booke206(DisasContext *ctx)
6071 {
6072 #if defined(CONFIG_USER_ONLY)
6073 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6074 #else
6075 if (unlikely(!ctx->mem_idx)) {
6076 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6077 return;
6078 }
6079 gen_update_nip(ctx, ctx->nip - 4);
6080 gen_helper_booke206_tlbwe(cpu_env);
6081 #endif
6082 }
6083
6084 static void gen_tlbivax_booke206(DisasContext *ctx)
6085 {
6086 #if defined(CONFIG_USER_ONLY)
6087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6088 #else
6089 TCGv t0;
6090 if (unlikely(!ctx->mem_idx)) {
6091 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6092 return;
6093 }
6094
6095 t0 = tcg_temp_new();
6096 gen_addr_reg_index(ctx, t0);
6097
6098 gen_helper_booke206_tlbivax(cpu_env, t0);
6099 #endif
6100 }
6101
6102 static void gen_tlbilx_booke206(DisasContext *ctx)
6103 {
6104 #if defined(CONFIG_USER_ONLY)
6105 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6106 #else
6107 TCGv t0;
6108 if (unlikely(!ctx->mem_idx)) {
6109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6110 return;
6111 }
6112
6113 t0 = tcg_temp_new();
6114 gen_addr_reg_index(ctx, t0);
6115
6116 switch((ctx->opcode >> 21) & 0x3) {
6117 case 0:
6118 gen_helper_booke206_tlbilx0(cpu_env, t0);
6119 break;
6120 case 1:
6121 gen_helper_booke206_tlbilx1(cpu_env, t0);
6122 break;
6123 case 3:
6124 gen_helper_booke206_tlbilx3(cpu_env, t0);
6125 break;
6126 default:
6127 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6128 break;
6129 }
6130
6131 tcg_temp_free(t0);
6132 #endif
6133 }
6134
6135
6136 /* wrtee */
6137 static void gen_wrtee(DisasContext *ctx)
6138 {
6139 #if defined(CONFIG_USER_ONLY)
6140 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6141 #else
6142 TCGv t0;
6143 if (unlikely(!ctx->mem_idx)) {
6144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6145 return;
6146 }
6147 t0 = tcg_temp_new();
6148 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6149 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6150 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6151 tcg_temp_free(t0);
6152 /* Stop translation to have a chance to raise an exception
6153 * if we just set msr_ee to 1
6154 */
6155 gen_stop_exception(ctx);
6156 #endif
6157 }
6158
6159 /* wrteei */
6160 static void gen_wrteei(DisasContext *ctx)
6161 {
6162 #if defined(CONFIG_USER_ONLY)
6163 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6164 #else
6165 if (unlikely(!ctx->mem_idx)) {
6166 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6167 return;
6168 }
6169 if (ctx->opcode & 0x00008000) {
6170 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6171 /* Stop translation to have a chance to raise an exception */
6172 gen_stop_exception(ctx);
6173 } else {
6174 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6175 }
6176 #endif
6177 }
6178
6179 /* PowerPC 440 specific instructions */
6180
6181 /* dlmzb */
6182 static void gen_dlmzb(DisasContext *ctx)
6183 {
6184 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6185 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6186 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6187 tcg_temp_free_i32(t0);
6188 }
6189
6190 /* mbar replaces eieio on 440 */
6191 static void gen_mbar(DisasContext *ctx)
6192 {
6193 /* interpreted as no-op */
6194 }
6195
6196 /* msync replaces sync on 440 */
6197 static void gen_msync_4xx(DisasContext *ctx)
6198 {
6199 /* interpreted as no-op */
6200 }
6201
6202 /* icbt */
6203 static void gen_icbt_440(DisasContext *ctx)
6204 {
6205 /* interpreted as no-op */
6206 /* XXX: specification say this is treated as a load by the MMU
6207 * but does not generate any exception
6208 */
6209 }
6210
6211 /* Embedded.Processor Control */
6212
6213 static void gen_msgclr(DisasContext *ctx)
6214 {
6215 #if defined(CONFIG_USER_ONLY)
6216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6217 #else
6218 if (unlikely(ctx->mem_idx == 0)) {
6219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6220 return;
6221 }
6222
6223 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6224 #endif
6225 }
6226
6227 static void gen_msgsnd(DisasContext *ctx)
6228 {
6229 #if defined(CONFIG_USER_ONLY)
6230 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6231 #else
6232 if (unlikely(ctx->mem_idx == 0)) {
6233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6234 return;
6235 }
6236
6237 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6238 #endif
6239 }
6240
6241 /*** Altivec vector extension ***/
6242 /* Altivec registers moves */
6243
6244 static inline TCGv_ptr gen_avr_ptr(int reg)
6245 {
6246 TCGv_ptr r = tcg_temp_new_ptr();
6247 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6248 return r;
6249 }
6250
6251 #define GEN_VR_LDX(name, opc2, opc3) \
6252 static void glue(gen_, name)(DisasContext *ctx) \
6253 { \
6254 TCGv EA; \
6255 if (unlikely(!ctx->altivec_enabled)) { \
6256 gen_exception(ctx, POWERPC_EXCP_VPU); \
6257 return; \
6258 } \
6259 gen_set_access_type(ctx, ACCESS_INT); \
6260 EA = tcg_temp_new(); \
6261 gen_addr_reg_index(ctx, EA); \
6262 tcg_gen_andi_tl(EA, EA, ~0xf); \
6263 if (ctx->le_mode) { \
6264 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6265 tcg_gen_addi_tl(EA, EA, 8); \
6266 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6267 } else { \
6268 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6269 tcg_gen_addi_tl(EA, EA, 8); \
6270 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6271 } \
6272 tcg_temp_free(EA); \
6273 }
6274
6275 #define GEN_VR_STX(name, opc2, opc3) \
6276 static void gen_st##name(DisasContext *ctx) \
6277 { \
6278 TCGv EA; \
6279 if (unlikely(!ctx->altivec_enabled)) { \
6280 gen_exception(ctx, POWERPC_EXCP_VPU); \
6281 return; \
6282 } \
6283 gen_set_access_type(ctx, ACCESS_INT); \
6284 EA = tcg_temp_new(); \
6285 gen_addr_reg_index(ctx, EA); \
6286 tcg_gen_andi_tl(EA, EA, ~0xf); \
6287 if (ctx->le_mode) { \
6288 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6289 tcg_gen_addi_tl(EA, EA, 8); \
6290 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6291 } else { \
6292 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6293 tcg_gen_addi_tl(EA, EA, 8); \
6294 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6295 } \
6296 tcg_temp_free(EA); \
6297 }
6298
6299 #define GEN_VR_LVE(name, opc2, opc3) \
6300 static void gen_lve##name(DisasContext *ctx) \
6301 { \
6302 TCGv EA; \
6303 TCGv_ptr rs; \
6304 if (unlikely(!ctx->altivec_enabled)) { \
6305 gen_exception(ctx, POWERPC_EXCP_VPU); \
6306 return; \
6307 } \
6308 gen_set_access_type(ctx, ACCESS_INT); \
6309 EA = tcg_temp_new(); \
6310 gen_addr_reg_index(ctx, EA); \
6311 rs = gen_avr_ptr(rS(ctx->opcode)); \
6312 gen_helper_lve##name(cpu_env, rs, EA); \
6313 tcg_temp_free(EA); \
6314 tcg_temp_free_ptr(rs); \
6315 }
6316
6317 #define GEN_VR_STVE(name, opc2, opc3) \
6318 static void gen_stve##name(DisasContext *ctx) \
6319 { \
6320 TCGv EA; \
6321 TCGv_ptr rs; \
6322 if (unlikely(!ctx->altivec_enabled)) { \
6323 gen_exception(ctx, POWERPC_EXCP_VPU); \
6324 return; \
6325 } \
6326 gen_set_access_type(ctx, ACCESS_INT); \
6327 EA = tcg_temp_new(); \
6328 gen_addr_reg_index(ctx, EA); \
6329 rs = gen_avr_ptr(rS(ctx->opcode)); \
6330 gen_helper_stve##name(cpu_env, rs, EA); \
6331 tcg_temp_free(EA); \
6332 tcg_temp_free_ptr(rs); \
6333 }
6334
6335 GEN_VR_LDX(lvx, 0x07, 0x03);
6336 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6337 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6338
6339 GEN_VR_LVE(bx, 0x07, 0x00);
6340 GEN_VR_LVE(hx, 0x07, 0x01);
6341 GEN_VR_LVE(wx, 0x07, 0x02);
6342
6343 GEN_VR_STX(svx, 0x07, 0x07);
6344 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6345 GEN_VR_STX(svxl, 0x07, 0x0F);
6346
6347 GEN_VR_STVE(bx, 0x07, 0x04);
6348 GEN_VR_STVE(hx, 0x07, 0x05);
6349 GEN_VR_STVE(wx, 0x07, 0x06);
6350
6351 static void gen_lvsl(DisasContext *ctx)
6352 {
6353 TCGv_ptr rd;
6354 TCGv EA;
6355 if (unlikely(!ctx->altivec_enabled)) {
6356 gen_exception(ctx, POWERPC_EXCP_VPU);
6357 return;
6358 }
6359 EA = tcg_temp_new();
6360 gen_addr_reg_index(ctx, EA);
6361 rd = gen_avr_ptr(rD(ctx->opcode));
6362 gen_helper_lvsl(rd, EA);
6363 tcg_temp_free(EA);
6364 tcg_temp_free_ptr(rd);
6365 }
6366
6367 static void gen_lvsr(DisasContext *ctx)
6368 {
6369 TCGv_ptr rd;
6370 TCGv EA;
6371 if (unlikely(!ctx->altivec_enabled)) {
6372 gen_exception(ctx, POWERPC_EXCP_VPU);
6373 return;
6374 }
6375 EA = tcg_temp_new();
6376 gen_addr_reg_index(ctx, EA);
6377 rd = gen_avr_ptr(rD(ctx->opcode));
6378 gen_helper_lvsr(rd, EA);
6379 tcg_temp_free(EA);
6380 tcg_temp_free_ptr(rd);
6381 }
6382
6383 static void gen_mfvscr(DisasContext *ctx)
6384 {
6385 TCGv_i32 t;
6386 if (unlikely(!ctx->altivec_enabled)) {
6387 gen_exception(ctx, POWERPC_EXCP_VPU);
6388 return;
6389 }
6390 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6391 t = tcg_temp_new_i32();
6392 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6393 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6394 tcg_temp_free_i32(t);
6395 }
6396
6397 static void gen_mtvscr(DisasContext *ctx)
6398 {
6399 TCGv_ptr p;
6400 if (unlikely(!ctx->altivec_enabled)) {
6401 gen_exception(ctx, POWERPC_EXCP_VPU);
6402 return;
6403 }
6404 p = gen_avr_ptr(rD(ctx->opcode));
6405 gen_helper_mtvscr(cpu_env, p);
6406 tcg_temp_free_ptr(p);
6407 }
6408
6409 /* Logical operations */
6410 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6411 static void glue(gen_, name)(DisasContext *ctx) \
6412 { \
6413 if (unlikely(!ctx->altivec_enabled)) { \
6414 gen_exception(ctx, POWERPC_EXCP_VPU); \
6415 return; \
6416 } \
6417 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6418 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6419 }
6420
6421 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6422 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6423 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6424 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6425 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6426
6427 #define GEN_VXFORM(name, opc2, opc3) \
6428 static void glue(gen_, name)(DisasContext *ctx) \
6429 { \
6430 TCGv_ptr ra, rb, rd; \
6431 if (unlikely(!ctx->altivec_enabled)) { \
6432 gen_exception(ctx, POWERPC_EXCP_VPU); \
6433 return; \
6434 } \
6435 ra = gen_avr_ptr(rA(ctx->opcode)); \
6436 rb = gen_avr_ptr(rB(ctx->opcode)); \
6437 rd = gen_avr_ptr(rD(ctx->opcode)); \
6438 gen_helper_##name (rd, ra, rb); \
6439 tcg_temp_free_ptr(ra); \
6440 tcg_temp_free_ptr(rb); \
6441 tcg_temp_free_ptr(rd); \
6442 }
6443
6444 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6445 static void glue(gen_, name)(DisasContext *ctx) \
6446 { \
6447 TCGv_ptr ra, rb, rd; \
6448 if (unlikely(!ctx->altivec_enabled)) { \
6449 gen_exception(ctx, POWERPC_EXCP_VPU); \
6450 return; \
6451 } \
6452 ra = gen_avr_ptr(rA(ctx->opcode)); \
6453 rb = gen_avr_ptr(rB(ctx->opcode)); \
6454 rd = gen_avr_ptr(rD(ctx->opcode)); \
6455 gen_helper_##name(cpu_env, rd, ra, rb); \
6456 tcg_temp_free_ptr(ra); \
6457 tcg_temp_free_ptr(rb); \
6458 tcg_temp_free_ptr(rd); \
6459 }
6460
6461 GEN_VXFORM(vaddubm, 0, 0);
6462 GEN_VXFORM(vadduhm, 0, 1);
6463 GEN_VXFORM(vadduwm, 0, 2);
6464 GEN_VXFORM(vsububm, 0, 16);
6465 GEN_VXFORM(vsubuhm, 0, 17);
6466 GEN_VXFORM(vsubuwm, 0, 18);
6467 GEN_VXFORM(vmaxub, 1, 0);
6468 GEN_VXFORM(vmaxuh, 1, 1);
6469 GEN_VXFORM(vmaxuw, 1, 2);
6470 GEN_VXFORM(vmaxsb, 1, 4);
6471 GEN_VXFORM(vmaxsh, 1, 5);
6472 GEN_VXFORM(vmaxsw, 1, 6);
6473 GEN_VXFORM(vminub, 1, 8);
6474 GEN_VXFORM(vminuh, 1, 9);
6475 GEN_VXFORM(vminuw, 1, 10);
6476 GEN_VXFORM(vminsb, 1, 12);
6477 GEN_VXFORM(vminsh, 1, 13);
6478 GEN_VXFORM(vminsw, 1, 14);
6479 GEN_VXFORM(vavgub, 1, 16);
6480 GEN_VXFORM(vavguh, 1, 17);
6481 GEN_VXFORM(vavguw, 1, 18);
6482 GEN_VXFORM(vavgsb, 1, 20);
6483 GEN_VXFORM(vavgsh, 1, 21);
6484 GEN_VXFORM(vavgsw, 1, 22);
6485 GEN_VXFORM(vmrghb, 6, 0);
6486 GEN_VXFORM(vmrghh, 6, 1);
6487 GEN_VXFORM(vmrghw, 6, 2);
6488 GEN_VXFORM(vmrglb, 6, 4);
6489 GEN_VXFORM(vmrglh, 6, 5);
6490 GEN_VXFORM(vmrglw, 6, 6);
6491 GEN_VXFORM(vmuloub, 4, 0);
6492 GEN_VXFORM(vmulouh, 4, 1);
6493 GEN_VXFORM(vmulosb, 4, 4);
6494 GEN_VXFORM(vmulosh, 4, 5);
6495 GEN_VXFORM(vmuleub, 4, 8);
6496 GEN_VXFORM(vmuleuh, 4, 9);
6497 GEN_VXFORM(vmulesb, 4, 12);
6498 GEN_VXFORM(vmulesh, 4, 13);
6499 GEN_VXFORM(vslb, 2, 4);
6500 GEN_VXFORM(vslh, 2, 5);
6501 GEN_VXFORM(vslw, 2, 6);
6502 GEN_VXFORM(vsrb, 2, 8);
6503 GEN_VXFORM(vsrh, 2, 9);
6504 GEN_VXFORM(vsrw, 2, 10);
6505 GEN_VXFORM(vsrab, 2, 12);
6506 GEN_VXFORM(vsrah, 2, 13);
6507 GEN_VXFORM(vsraw, 2, 14);
6508 GEN_VXFORM(vslo, 6, 16);
6509 GEN_VXFORM(vsro, 6, 17);
6510 GEN_VXFORM(vaddcuw, 0, 6);
6511 GEN_VXFORM(vsubcuw, 0, 22);
6512 GEN_VXFORM_ENV(vaddubs, 0, 8);
6513 GEN_VXFORM_ENV(vadduhs, 0, 9);
6514 GEN_VXFORM_ENV(vadduws, 0, 10);
6515 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6516 GEN_VXFORM_ENV(vaddshs, 0, 13);
6517 GEN_VXFORM_ENV(vaddsws, 0, 14);
6518 GEN_VXFORM_ENV(vsububs, 0, 24);
6519 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6520 GEN_VXFORM_ENV(vsubuws, 0, 26);
6521 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6522 GEN_VXFORM_ENV(vsubshs, 0, 29);
6523 GEN_VXFORM_ENV(vsubsws, 0, 30);
6524 GEN_VXFORM(vrlb, 2, 0);
6525 GEN_VXFORM(vrlh, 2, 1);
6526 GEN_VXFORM(vrlw, 2, 2);
6527 GEN_VXFORM(vsl, 2, 7);
6528 GEN_VXFORM(vsr, 2, 11);
6529 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6530 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6531 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6532 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6533 GEN_VXFORM_ENV(vpkshus, 7, 4);
6534 GEN_VXFORM_ENV(vpkswus, 7, 5);
6535 GEN_VXFORM_ENV(vpkshss, 7, 6);
6536 GEN_VXFORM_ENV(vpkswss, 7, 7);
6537 GEN_VXFORM(vpkpx, 7, 12);
6538 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6539 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6540 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6541 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6542 GEN_VXFORM_ENV(vsumsws, 4, 30);
6543 GEN_VXFORM_ENV(vaddfp, 5, 0);
6544 GEN_VXFORM_ENV(vsubfp, 5, 1);
6545 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6546 GEN_VXFORM_ENV(vminfp, 5, 17);
6547
6548 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6549 static void glue(gen_, name)(DisasContext *ctx) \
6550 { \
6551 TCGv_ptr ra, rb, rd; \
6552 if (unlikely(!ctx->altivec_enabled)) { \
6553 gen_exception(ctx, POWERPC_EXCP_VPU); \
6554 return; \
6555 } \
6556 ra = gen_avr_ptr(rA(ctx->opcode)); \
6557 rb = gen_avr_ptr(rB(ctx->opcode)); \
6558 rd = gen_avr_ptr(rD(ctx->opcode)); \
6559 gen_helper_##opname(cpu_env, rd, ra, rb); \
6560 tcg_temp_free_ptr(ra); \
6561 tcg_temp_free_ptr(rb); \
6562 tcg_temp_free_ptr(rd); \
6563 }
6564
6565 #define GEN_VXRFORM(name, opc2, opc3) \
6566 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6567 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6568
6569 GEN_VXRFORM(vcmpequb, 3, 0)
6570 GEN_VXRFORM(vcmpequh, 3, 1)
6571 GEN_VXRFORM(vcmpequw, 3, 2)
6572 GEN_VXRFORM(vcmpgtsb, 3, 12)
6573 GEN_VXRFORM(vcmpgtsh, 3, 13)
6574 GEN_VXRFORM(vcmpgtsw, 3, 14)
6575 GEN_VXRFORM(vcmpgtub, 3, 8)
6576 GEN_VXRFORM(vcmpgtuh, 3, 9)
6577 GEN_VXRFORM(vcmpgtuw, 3, 10)
6578 GEN_VXRFORM(vcmpeqfp, 3, 3)
6579 GEN_VXRFORM(vcmpgefp, 3, 7)
6580 GEN_VXRFORM(vcmpgtfp, 3, 11)
6581 GEN_VXRFORM(vcmpbfp, 3, 15)
6582
6583 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6584 static void glue(gen_, name)(DisasContext *ctx) \
6585 { \
6586 TCGv_ptr rd; \
6587 TCGv_i32 simm; \
6588 if (unlikely(!ctx->altivec_enabled)) { \
6589 gen_exception(ctx, POWERPC_EXCP_VPU); \
6590 return; \
6591 } \
6592 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6593 rd = gen_avr_ptr(rD(ctx->opcode)); \
6594 gen_helper_##name (rd, simm); \
6595 tcg_temp_free_i32(simm); \
6596 tcg_temp_free_ptr(rd); \
6597 }
6598
6599 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6600 GEN_VXFORM_SIMM(vspltish, 6, 13);
6601 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6602
6603 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6604 static void glue(gen_, name)(DisasContext *ctx) \
6605 { \
6606 TCGv_ptr rb, rd; \
6607 if (unlikely(!ctx->altivec_enabled)) { \
6608 gen_exception(ctx, POWERPC_EXCP_VPU); \
6609 return; \
6610 } \
6611 rb = gen_avr_ptr(rB(ctx->opcode)); \
6612 rd = gen_avr_ptr(rD(ctx->opcode)); \
6613 gen_helper_##name (rd, rb); \
6614 tcg_temp_free_ptr(rb); \
6615 tcg_temp_free_ptr(rd); \
6616 }
6617
6618 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6619 static void glue(gen_, name)(DisasContext *ctx) \
6620 { \
6621 TCGv_ptr rb, rd; \
6622 \
6623 if (unlikely(!ctx->altivec_enabled)) { \
6624 gen_exception(ctx, POWERPC_EXCP_VPU); \
6625 return; \
6626 } \
6627 rb = gen_avr_ptr(rB(ctx->opcode)); \
6628 rd = gen_avr_ptr(rD(ctx->opcode)); \
6629 gen_helper_##name(cpu_env, rd, rb); \
6630 tcg_temp_free_ptr(rb); \
6631 tcg_temp_free_ptr(rd); \
6632 }
6633
6634 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6635 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6636 GEN_VXFORM_NOA(vupklsb, 7, 10);
6637 GEN_VXFORM_NOA(vupklsh, 7, 11);
6638 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6639 GEN_VXFORM_NOA(vupklpx, 7, 15);
6640 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6641 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6642 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6643 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6644 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6645 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6646 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6647 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6648
6649 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6650 static void glue(gen_, name)(DisasContext *ctx) \
6651 { \
6652 TCGv_ptr rd; \
6653 TCGv_i32 simm; \
6654 if (unlikely(!ctx->altivec_enabled)) { \
6655 gen_exception(ctx, POWERPC_EXCP_VPU); \
6656 return; \
6657 } \
6658 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6659 rd = gen_avr_ptr(rD(ctx->opcode)); \
6660 gen_helper_##name (rd, simm); \
6661 tcg_temp_free_i32(simm); \
6662 tcg_temp_free_ptr(rd); \
6663 }
6664
6665 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6666 static void glue(gen_, name)(DisasContext *ctx) \
6667 { \
6668 TCGv_ptr rb, rd; \
6669 TCGv_i32 uimm; \
6670 if (unlikely(!ctx->altivec_enabled)) { \
6671 gen_exception(ctx, POWERPC_EXCP_VPU); \
6672 return; \
6673 } \
6674 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6675 rb = gen_avr_ptr(rB(ctx->opcode)); \
6676 rd = gen_avr_ptr(rD(ctx->opcode)); \
6677 gen_helper_##name (rd, rb, uimm); \
6678 tcg_temp_free_i32(uimm); \
6679 tcg_temp_free_ptr(rb); \
6680 tcg_temp_free_ptr(rd); \
6681 }
6682
6683 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6684 static void glue(gen_, name)(DisasContext *ctx) \
6685 { \
6686 TCGv_ptr rb, rd; \
6687 TCGv_i32 uimm; \
6688 \
6689 if (unlikely(!ctx->altivec_enabled)) { \
6690 gen_exception(ctx, POWERPC_EXCP_VPU); \
6691 return; \
6692 } \
6693 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6694 rb = gen_avr_ptr(rB(ctx->opcode)); \
6695 rd = gen_avr_ptr(rD(ctx->opcode)); \
6696 gen_helper_##name(cpu_env, rd, rb, uimm); \
6697 tcg_temp_free_i32(uimm); \
6698 tcg_temp_free_ptr(rb); \
6699 tcg_temp_free_ptr(rd); \
6700 }
6701
6702 GEN_VXFORM_UIMM(vspltb, 6, 8);
6703 GEN_VXFORM_UIMM(vsplth, 6, 9);
6704 GEN_VXFORM_UIMM(vspltw, 6, 10);
6705 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6706 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6707 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6708 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6709
6710 static void gen_vsldoi(DisasContext *ctx)
6711 {
6712 TCGv_ptr ra, rb, rd;
6713 TCGv_i32 sh;
6714 if (unlikely(!ctx->altivec_enabled)) {
6715 gen_exception(ctx, POWERPC_EXCP_VPU);
6716 return;
6717 }
6718 ra = gen_avr_ptr(rA(ctx->opcode));
6719 rb = gen_avr_ptr(rB(ctx->opcode));
6720 rd = gen_avr_ptr(rD(ctx->opcode));
6721 sh = tcg_const_i32(VSH(ctx->opcode));
6722 gen_helper_vsldoi (rd, ra, rb, sh);
6723 tcg_temp_free_ptr(ra);
6724 tcg_temp_free_ptr(rb);
6725 tcg_temp_free_ptr(rd);
6726 tcg_temp_free_i32(sh);
6727 }
6728
6729 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6730 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6731 { \
6732 TCGv_ptr ra, rb, rc, rd; \
6733 if (unlikely(!ctx->altivec_enabled)) { \
6734 gen_exception(ctx, POWERPC_EXCP_VPU); \
6735 return; \
6736 } \
6737 ra = gen_avr_ptr(rA(ctx->opcode)); \
6738 rb = gen_avr_ptr(rB(ctx->opcode)); \
6739 rc = gen_avr_ptr(rC(ctx->opcode)); \
6740 rd = gen_avr_ptr(rD(ctx->opcode)); \
6741 if (Rc(ctx->opcode)) { \
6742 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6743 } else { \
6744 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6745 } \
6746 tcg_temp_free_ptr(ra); \
6747 tcg_temp_free_ptr(rb); \
6748 tcg_temp_free_ptr(rc); \
6749 tcg_temp_free_ptr(rd); \
6750 }
6751
6752 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6753
6754 static void gen_vmladduhm(DisasContext *ctx)
6755 {
6756 TCGv_ptr ra, rb, rc, rd;
6757 if (unlikely(!ctx->altivec_enabled)) {
6758 gen_exception(ctx, POWERPC_EXCP_VPU);
6759 return;
6760 }
6761 ra = gen_avr_ptr(rA(ctx->opcode));
6762 rb = gen_avr_ptr(rB(ctx->opcode));
6763 rc = gen_avr_ptr(rC(ctx->opcode));
6764 rd = gen_avr_ptr(rD(ctx->opcode));
6765 gen_helper_vmladduhm(rd, ra, rb, rc);
6766 tcg_temp_free_ptr(ra);
6767 tcg_temp_free_ptr(rb);
6768 tcg_temp_free_ptr(rc);
6769 tcg_temp_free_ptr(rd);
6770 }
6771
6772 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6773 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6774 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6775 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6776 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6777
6778 /*** SPE extension ***/
6779 /* Register moves */
6780
6781
6782 static inline void gen_evmra(DisasContext *ctx)
6783 {
6784
6785 if (unlikely(!ctx->spe_enabled)) {
6786 gen_exception(ctx, POWERPC_EXCP_SPEU);
6787 return;
6788 }
6789
6790 #if defined(TARGET_PPC64)
6791 /* rD := rA */
6792 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6793
6794 /* spe_acc := rA */
6795 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6796 cpu_env,
6797 offsetof(CPUPPCState, spe_acc));
6798 #else
6799 TCGv_i64 tmp = tcg_temp_new_i64();
6800
6801 /* tmp := rA_lo + rA_hi << 32 */
6802 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6803
6804 /* spe_acc := tmp */
6805 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6806 tcg_temp_free_i64(tmp);
6807
6808 /* rD := rA */
6809 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6810 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6811 #endif
6812 }
6813
6814 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6815 {
6816 #if defined(TARGET_PPC64)
6817 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6818 #else
6819 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6820 #endif
6821 }
6822
6823 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6824 {
6825 #if defined(TARGET_PPC64)
6826 tcg_gen_mov_i64(cpu_gpr[reg], t);
6827 #else
6828 TCGv_i64 tmp = tcg_temp_new_i64();
6829 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6830 tcg_gen_shri_i64(tmp, t, 32);
6831 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6832 tcg_temp_free_i64(tmp);
6833 #endif
6834 }
6835
6836 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6837 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6838 { \
6839 if (Rc(ctx->opcode)) \
6840 gen_##name1(ctx); \
6841 else \
6842 gen_##name0(ctx); \
6843 }
6844
6845 /* Handler for undefined SPE opcodes */
6846 static inline void gen_speundef(DisasContext *ctx)
6847 {
6848 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6849 }
6850
6851 /* SPE logic */
6852 #if defined(TARGET_PPC64)
6853 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6854 static inline void gen_##name(DisasContext *ctx) \
6855 { \
6856 if (unlikely(!ctx->spe_enabled)) { \
6857 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6858 return; \
6859 } \
6860 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6861 cpu_gpr[rB(ctx->opcode)]); \
6862 }
6863 #else
6864 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6865 static inline void gen_##name(DisasContext *ctx) \
6866 { \
6867 if (unlikely(!ctx->spe_enabled)) { \
6868 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6869 return; \
6870 } \
6871 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6872 cpu_gpr[rB(ctx->opcode)]); \
6873 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6874 cpu_gprh[rB(ctx->opcode)]); \
6875 }
6876 #endif
6877
6878 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6879 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6880 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6881 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6882 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6883 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6884 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6885 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6886
6887 /* SPE logic immediate */
6888 #if defined(TARGET_PPC64)
6889 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6890 static inline void gen_##name(DisasContext *ctx) \
6891 { \
6892 if (unlikely(!ctx->spe_enabled)) { \
6893 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6894 return; \
6895 } \
6896 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6897 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6898 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6899 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6900 tcg_opi(t0, t0, rB(ctx->opcode)); \
6901 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6902 tcg_gen_trunc_i64_i32(t1, t2); \
6903 tcg_temp_free_i64(t2); \
6904 tcg_opi(t1, t1, rB(ctx->opcode)); \
6905 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6906 tcg_temp_free_i32(t0); \
6907 tcg_temp_free_i32(t1); \
6908 }
6909 #else
6910 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6911 static inline void gen_##name(DisasContext *ctx) \
6912 { \
6913 if (unlikely(!ctx->spe_enabled)) { \
6914 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6915 return; \
6916 } \
6917 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6918 rB(ctx->opcode)); \
6919 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6920 rB(ctx->opcode)); \
6921 }
6922 #endif
6923 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6924 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6925 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6926 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6927
6928 /* SPE arithmetic */
6929 #if defined(TARGET_PPC64)
6930 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6931 static inline void gen_##name(DisasContext *ctx) \
6932 { \
6933 if (unlikely(!ctx->spe_enabled)) { \
6934 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6935 return; \
6936 } \
6937 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6938 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6939 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6940 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6941 tcg_op(t0, t0); \
6942 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6943 tcg_gen_trunc_i64_i32(t1, t2); \
6944 tcg_temp_free_i64(t2); \
6945 tcg_op(t1, t1); \
6946 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6947 tcg_temp_free_i32(t0); \
6948 tcg_temp_free_i32(t1); \
6949 }
6950 #else
6951 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6952 static inline void gen_##name(DisasContext *ctx) \
6953 { \
6954 if (unlikely(!ctx->spe_enabled)) { \
6955 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6956 return; \
6957 } \
6958 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6959 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6960 }
6961 #endif
6962
6963 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6964 {
6965 int l1 = gen_new_label();
6966 int l2 = gen_new_label();
6967
6968 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6969 tcg_gen_neg_i32(ret, arg1);
6970 tcg_gen_br(l2);
6971 gen_set_label(l1);
6972 tcg_gen_mov_i32(ret, arg1);
6973 gen_set_label(l2);
6974 }
6975 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6976 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6977 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6978 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6979 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6980 {
6981 tcg_gen_addi_i32(ret, arg1, 0x8000);
6982 tcg_gen_ext16u_i32(ret, ret);
6983 }
6984 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6985 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6986 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6987
6988 #if defined(TARGET_PPC64)
6989 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6990 static inline void gen_##name(DisasContext *ctx) \
6991 { \
6992 if (unlikely(!ctx->spe_enabled)) { \
6993 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6994 return; \
6995 } \
6996 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6997 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6998 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6999 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7000 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7001 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7002 tcg_op(t0, t0, t2); \
7003 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7004 tcg_gen_trunc_i64_i32(t1, t3); \
7005 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7006 tcg_gen_trunc_i64_i32(t2, t3); \
7007 tcg_temp_free_i64(t3); \
7008 tcg_op(t1, t1, t2); \
7009 tcg_temp_free_i32(t2); \
7010 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7011 tcg_temp_free_i32(t0); \
7012 tcg_temp_free_i32(t1); \
7013 }
7014 #else
7015 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7016 static inline void gen_##name(DisasContext *ctx) \
7017 { \
7018 if (unlikely(!ctx->spe_enabled)) { \
7019 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7020 return; \
7021 } \
7022 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7023 cpu_gpr[rB(ctx->opcode)]); \
7024 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7025 cpu_gprh[rB(ctx->opcode)]); \
7026 }
7027 #endif
7028
7029 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7030 {
7031 TCGv_i32 t0;
7032 int l1, l2;
7033
7034 l1 = gen_new_label();
7035 l2 = gen_new_label();
7036 t0 = tcg_temp_local_new_i32();
7037 /* No error here: 6 bits are used */
7038 tcg_gen_andi_i32(t0, arg2, 0x3F);
7039 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7040 tcg_gen_shr_i32(ret, arg1, t0);
7041 tcg_gen_br(l2);
7042 gen_set_label(l1);
7043 tcg_gen_movi_i32(ret, 0);
7044 gen_set_label(l2);
7045 tcg_temp_free_i32(t0);
7046 }
7047 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7048 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7049 {
7050 TCGv_i32 t0;
7051 int l1, l2;
7052
7053 l1 = gen_new_label();
7054 l2 = gen_new_label();
7055 t0 = tcg_temp_local_new_i32();
7056 /* No error here: 6 bits are used */
7057 tcg_gen_andi_i32(t0, arg2, 0x3F);
7058 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7059 tcg_gen_sar_i32(ret, arg1, t0);
7060 tcg_gen_br(l2);
7061 gen_set_label(l1);
7062 tcg_gen_movi_i32(ret, 0);
7063 gen_set_label(l2);
7064 tcg_temp_free_i32(t0);
7065 }
7066 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7067 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7068 {
7069 TCGv_i32 t0;
7070 int l1, l2;
7071
7072 l1 = gen_new_label();
7073 l2 = gen_new_label();
7074 t0 = tcg_temp_local_new_i32();
7075 /* No error here: 6 bits are used */
7076 tcg_gen_andi_i32(t0, arg2, 0x3F);
7077 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7078 tcg_gen_shl_i32(ret, arg1, t0);
7079 tcg_gen_br(l2);
7080 gen_set_label(l1);
7081 tcg_gen_movi_i32(ret, 0);
7082 gen_set_label(l2);
7083 tcg_temp_free_i32(t0);
7084 }
7085 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7086 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7087 {
7088 TCGv_i32 t0 = tcg_temp_new_i32();
7089 tcg_gen_andi_i32(t0, arg2, 0x1F);
7090 tcg_gen_rotl_i32(ret, arg1, t0);
7091 tcg_temp_free_i32(t0);
7092 }
7093 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7094 static inline void gen_evmergehi(DisasContext *ctx)
7095 {
7096 if (unlikely(!ctx->spe_enabled)) {
7097 gen_exception(ctx, POWERPC_EXCP_SPEU);
7098 return;
7099 }
7100 #if defined(TARGET_PPC64)
7101 TCGv t0 = tcg_temp_new();
7102 TCGv t1 = tcg_temp_new();
7103 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7104 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7105 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7106 tcg_temp_free(t0);
7107 tcg_temp_free(t1);
7108 #else
7109 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7110 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7111 #endif
7112 }
7113 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7114 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7115 {
7116 tcg_gen_sub_i32(ret, arg2, arg1);
7117 }
7118 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7119
7120 /* SPE arithmetic immediate */
7121 #if defined(TARGET_PPC64)
7122 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7123 static inline void gen_##name(DisasContext *ctx) \
7124 { \
7125 if (unlikely(!ctx->spe_enabled)) { \
7126 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7127 return; \
7128 } \
7129 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7130 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7131 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7132 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7133 tcg_op(t0, t0, rA(ctx->opcode)); \
7134 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7135 tcg_gen_trunc_i64_i32(t1, t2); \
7136 tcg_temp_free_i64(t2); \
7137 tcg_op(t1, t1, rA(ctx->opcode)); \
7138 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7139 tcg_temp_free_i32(t0); \
7140 tcg_temp_free_i32(t1); \
7141 }
7142 #else
7143 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7144 static inline void gen_##name(DisasContext *ctx) \
7145 { \
7146 if (unlikely(!ctx->spe_enabled)) { \
7147 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7148 return; \
7149 } \
7150 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7151 rA(ctx->opcode)); \
7152 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7153 rA(ctx->opcode)); \
7154 }
7155 #endif
7156 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7157 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7158
7159 /* SPE comparison */
7160 #if defined(TARGET_PPC64)
7161 #define GEN_SPEOP_COMP(name, tcg_cond) \
7162 static inline void gen_##name(DisasContext *ctx) \
7163 { \
7164 if (unlikely(!ctx->spe_enabled)) { \
7165 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7166 return; \
7167 } \
7168 int l1 = gen_new_label(); \
7169 int l2 = gen_new_label(); \
7170 int l3 = gen_new_label(); \
7171 int l4 = gen_new_label(); \
7172 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7173 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7174 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7175 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7176 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7177 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7178 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7179 tcg_gen_br(l2); \
7180 gen_set_label(l1); \
7181 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7182 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7183 gen_set_label(l2); \
7184 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7185 tcg_gen_trunc_i64_i32(t0, t2); \
7186 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7187 tcg_gen_trunc_i64_i32(t1, t2); \
7188 tcg_temp_free_i64(t2); \
7189 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7190 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7191 ~(CRF_CH | CRF_CH_AND_CL)); \
7192 tcg_gen_br(l4); \
7193 gen_set_label(l3); \
7194 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7195 CRF_CH | CRF_CH_OR_CL); \
7196 gen_set_label(l4); \
7197 tcg_temp_free_i32(t0); \
7198 tcg_temp_free_i32(t1); \
7199 }
7200 #else
7201 #define GEN_SPEOP_COMP(name, tcg_cond) \
7202 static inline void gen_##name(DisasContext *ctx) \
7203 { \
7204 if (unlikely(!ctx->spe_enabled)) { \
7205 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7206 return; \
7207 } \
7208 int l1 = gen_new_label(); \
7209 int l2 = gen_new_label(); \
7210 int l3 = gen_new_label(); \
7211 int l4 = gen_new_label(); \
7212 \
7213 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7214 cpu_gpr[rB(ctx->opcode)], l1); \
7215 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7216 tcg_gen_br(l2); \
7217 gen_set_label(l1); \
7218 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7219 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7220 gen_set_label(l2); \
7221 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7222 cpu_gprh[rB(ctx->opcode)], l3); \
7223 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7224 ~(CRF_CH | CRF_CH_AND_CL)); \
7225 tcg_gen_br(l4); \
7226 gen_set_label(l3); \
7227 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7228 CRF_CH | CRF_CH_OR_CL); \
7229 gen_set_label(l4); \
7230 }
7231 #endif
7232 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7233 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7234 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7235 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7236 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7237
7238 /* SPE misc */
7239 static inline void gen_brinc(DisasContext *ctx)
7240 {
7241 /* Note: brinc is usable even if SPE is disabled */
7242 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7243 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7244 }
7245 static inline void gen_evmergelo(DisasContext *ctx)
7246 {
7247 if (unlikely(!ctx->spe_enabled)) {
7248 gen_exception(ctx, POWERPC_EXCP_SPEU);
7249 return;
7250 }
7251 #if defined(TARGET_PPC64)
7252 TCGv t0 = tcg_temp_new();
7253 TCGv t1 = tcg_temp_new();
7254 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7255 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7256 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7257 tcg_temp_free(t0);
7258 tcg_temp_free(t1);
7259 #else
7260 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7261 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7262 #endif
7263 }
7264 static inline void gen_evmergehilo(DisasContext *ctx)
7265 {
7266 if (unlikely(!ctx->spe_enabled)) {
7267 gen_exception(ctx, POWERPC_EXCP_SPEU);
7268 return;
7269 }
7270 #if defined(TARGET_PPC64)
7271 TCGv t0 = tcg_temp_new();
7272 TCGv t1 = tcg_temp_new();
7273 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7274 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7275 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7276 tcg_temp_free(t0);
7277 tcg_temp_free(t1);
7278 #else
7279 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7280 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7281 #endif
7282 }
7283 static inline void gen_evmergelohi(DisasContext *ctx)
7284 {
7285 if (unlikely(!ctx->spe_enabled)) {
7286 gen_exception(ctx, POWERPC_EXCP_SPEU);
7287 return;
7288 }
7289 #if defined(TARGET_PPC64)
7290 TCGv t0 = tcg_temp_new();
7291 TCGv t1 = tcg_temp_new();
7292 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7293 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7294 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7295 tcg_temp_free(t0);
7296 tcg_temp_free(t1);
7297 #else
7298 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7299 TCGv_i32 tmp = tcg_temp_new_i32();
7300 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7301 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7302 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7303 tcg_temp_free_i32(tmp);
7304 } else {
7305 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7306 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7307 }
7308 #endif
7309 }
7310 static inline void gen_evsplati(DisasContext *ctx)
7311 {
7312 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7313
7314 #if defined(TARGET_PPC64)
7315 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7316 #else
7317 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7318 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7319 #endif
7320 }
7321 static inline void gen_evsplatfi(DisasContext *ctx)
7322 {
7323 uint64_t imm = rA(ctx->opcode) << 27;
7324
7325 #if defined(TARGET_PPC64)
7326 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7327 #else
7328 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7329 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7330 #endif
7331 }
7332
7333 static inline void gen_evsel(DisasContext *ctx)
7334 {
7335 int l1 = gen_new_label();
7336 int l2 = gen_new_label();
7337 int l3 = gen_new_label();
7338 int l4 = gen_new_label();
7339 TCGv_i32 t0 = tcg_temp_local_new_i32();
7340 #if defined(TARGET_PPC64)
7341 TCGv t1 = tcg_temp_local_new();
7342 TCGv t2 = tcg_temp_local_new();
7343 #endif
7344 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7345 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7346 #if defined(TARGET_PPC64)
7347 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7348 #else
7349 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7350 #endif
7351 tcg_gen_br(l2);
7352 gen_set_label(l1);
7353 #if defined(TARGET_PPC64)
7354 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7355 #else
7356 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7357 #endif
7358 gen_set_label(l2);
7359 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7360 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7361 #if defined(TARGET_PPC64)
7362 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7363 #else
7364 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7365 #endif
7366 tcg_gen_br(l4);
7367 gen_set_label(l3);
7368 #if defined(TARGET_PPC64)
7369 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7370 #else
7371 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7372 #endif
7373 gen_set_label(l4);
7374 tcg_temp_free_i32(t0);
7375 #if defined(TARGET_PPC64)
7376 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7377 tcg_temp_free(t1);
7378 tcg_temp_free(t2);
7379 #endif
7380 }
7381
7382 static void gen_evsel0(DisasContext *ctx)
7383 {
7384 gen_evsel(ctx);
7385 }
7386
7387 static void gen_evsel1(DisasContext *ctx)
7388 {
7389 gen_evsel(ctx);
7390 }
7391
7392 static void gen_evsel2(DisasContext *ctx)
7393 {
7394 gen_evsel(ctx);
7395 }
7396
7397 static void gen_evsel3(DisasContext *ctx)
7398 {
7399 gen_evsel(ctx);
7400 }
7401
7402 /* Multiply */
7403
7404 static inline void gen_evmwumi(DisasContext *ctx)
7405 {
7406 TCGv_i64 t0, t1;
7407
7408 if (unlikely(!ctx->spe_enabled)) {
7409 gen_exception(ctx, POWERPC_EXCP_SPEU);
7410 return;
7411 }
7412
7413 t0 = tcg_temp_new_i64();
7414 t1 = tcg_temp_new_i64();
7415
7416 /* t0 := rA; t1 := rB */
7417 #if defined(TARGET_PPC64)
7418 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7419 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7420 #else
7421 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7422 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7423 #endif
7424
7425 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7426
7427 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7428
7429 tcg_temp_free_i64(t0);
7430 tcg_temp_free_i64(t1);
7431 }
7432
7433 static inline void gen_evmwumia(DisasContext *ctx)
7434 {
7435 TCGv_i64 tmp;
7436
7437 if (unlikely(!ctx->spe_enabled)) {
7438 gen_exception(ctx, POWERPC_EXCP_SPEU);
7439 return;
7440 }
7441
7442 gen_evmwumi(ctx); /* rD := rA * rB */
7443
7444 tmp = tcg_temp_new_i64();
7445
7446 /* acc := rD */
7447 gen_load_gpr64(tmp, rD(ctx->opcode));
7448 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7449 tcg_temp_free_i64(tmp);
7450 }
7451
7452 static inline void gen_evmwumiaa(DisasContext *ctx)
7453 {
7454 TCGv_i64 acc;
7455 TCGv_i64 tmp;
7456
7457 if (unlikely(!ctx->spe_enabled)) {
7458 gen_exception(ctx, POWERPC_EXCP_SPEU);
7459 return;
7460 }
7461
7462 gen_evmwumi(ctx); /* rD := rA * rB */
7463
7464 acc = tcg_temp_new_i64();
7465 tmp = tcg_temp_new_i64();
7466
7467 /* tmp := rD */
7468 gen_load_gpr64(tmp, rD(ctx->opcode));
7469
7470 /* Load acc */
7471 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7472
7473 /* acc := tmp + acc */
7474 tcg_gen_add_i64(acc, acc, tmp);
7475
7476 /* Store acc */
7477 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7478
7479 /* rD := acc */
7480 gen_store_gpr64(rD(ctx->opcode), acc);
7481
7482 tcg_temp_free_i64(acc);
7483 tcg_temp_free_i64(tmp);
7484 }
7485
7486 static inline void gen_evmwsmi(DisasContext *ctx)
7487 {
7488 TCGv_i64 t0, t1;
7489
7490 if (unlikely(!ctx->spe_enabled)) {
7491 gen_exception(ctx, POWERPC_EXCP_SPEU);
7492 return;
7493 }
7494
7495 t0 = tcg_temp_new_i64();
7496 t1 = tcg_temp_new_i64();
7497
7498 /* t0 := rA; t1 := rB */
7499 #if defined(TARGET_PPC64)
7500 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7501 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7502 #else
7503 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7504 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7505 #endif
7506
7507 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7508
7509 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7510
7511 tcg_temp_free_i64(t0);
7512 tcg_temp_free_i64(t1);
7513 }
7514
7515 static inline void gen_evmwsmia(DisasContext *ctx)
7516 {
7517 TCGv_i64 tmp;
7518
7519 gen_evmwsmi(ctx); /* rD := rA * rB */
7520
7521 tmp = tcg_temp_new_i64();
7522
7523 /* acc := rD */
7524 gen_load_gpr64(tmp, rD(ctx->opcode));
7525 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7526
7527 tcg_temp_free_i64(tmp);
7528 }
7529
7530 static inline void gen_evmwsmiaa(DisasContext *ctx)
7531 {
7532 TCGv_i64 acc = tcg_temp_new_i64();
7533 TCGv_i64 tmp = tcg_temp_new_i64();
7534
7535 gen_evmwsmi(ctx); /* rD := rA * rB */
7536
7537 acc = tcg_temp_new_i64();
7538 tmp = tcg_temp_new_i64();
7539
7540 /* tmp := rD */
7541 gen_load_gpr64(tmp, rD(ctx->opcode));
7542
7543 /* Load acc */
7544 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7545
7546 /* acc := tmp + acc */
7547 tcg_gen_add_i64(acc, acc, tmp);
7548
7549 /* Store acc */
7550 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7551
7552 /* rD := acc */
7553 gen_store_gpr64(rD(ctx->opcode), acc);
7554
7555 tcg_temp_free_i64(acc);
7556 tcg_temp_free_i64(tmp);
7557 }
7558
7559 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7560 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7561 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7562 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7563 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7564 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7565 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7566 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7567 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7568 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7569 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7570 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7571 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7572 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7573 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7574 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7575 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7576 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7577 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7578 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7579 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7580 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7581 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7582 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7583 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7584 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7585 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7586 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7587 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7588
7589 /* SPE load and stores */
7590 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7591 {
7592 target_ulong uimm = rB(ctx->opcode);
7593
7594 if (rA(ctx->opcode) == 0) {
7595 tcg_gen_movi_tl(EA, uimm << sh);
7596 } else {
7597 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7598 #if defined(TARGET_PPC64)
7599 if (!ctx->sf_mode) {
7600 tcg_gen_ext32u_tl(EA, EA);
7601 }
7602 #endif
7603 }
7604 }
7605
7606 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7607 {
7608 #if defined(TARGET_PPC64)
7609 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7610 #else
7611 TCGv_i64 t0 = tcg_temp_new_i64();
7612 gen_qemu_ld64(ctx, t0, addr);
7613 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7614 tcg_gen_shri_i64(t0, t0, 32);
7615 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7616 tcg_temp_free_i64(t0);
7617 #endif
7618 }
7619
7620 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7621 {
7622 #if defined(TARGET_PPC64)
7623 TCGv t0 = tcg_temp_new();
7624 gen_qemu_ld32u(ctx, t0, addr);
7625 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7626 gen_addr_add(ctx, addr, addr, 4);
7627 gen_qemu_ld32u(ctx, t0, addr);
7628 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7629 tcg_temp_free(t0);
7630 #else
7631 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7632 gen_addr_add(ctx, addr, addr, 4);
7633 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7634 #endif
7635 }
7636
7637 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7638 {
7639 TCGv t0 = tcg_temp_new();
7640 #if defined(TARGET_PPC64)
7641 gen_qemu_ld16u(ctx, t0, addr);
7642 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7643 gen_addr_add(ctx, addr, addr, 2);
7644 gen_qemu_ld16u(ctx, t0, addr);
7645 tcg_gen_shli_tl(t0, t0, 32);
7646 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7647 gen_addr_add(ctx, addr, addr, 2);
7648 gen_qemu_ld16u(ctx, t0, addr);
7649 tcg_gen_shli_tl(t0, t0, 16);
7650 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7651 gen_addr_add(ctx, addr, addr, 2);
7652 gen_qemu_ld16u(ctx, t0, addr);
7653 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7654 #else
7655 gen_qemu_ld16u(ctx, t0, addr);
7656 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7657 gen_addr_add(ctx, addr, addr, 2);
7658 gen_qemu_ld16u(ctx, t0, addr);
7659 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7660 gen_addr_add(ctx, addr, addr, 2);
7661 gen_qemu_ld16u(ctx, t0, addr);
7662 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7663 gen_addr_add(ctx, addr, addr, 2);
7664 gen_qemu_ld16u(ctx, t0, addr);
7665 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7666 #endif
7667 tcg_temp_free(t0);
7668 }
7669
7670 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7671 {
7672 TCGv t0 = tcg_temp_new();
7673 gen_qemu_ld16u(ctx, t0, addr);
7674 #if defined(TARGET_PPC64)
7675 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7676 tcg_gen_shli_tl(t0, t0, 16);
7677 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7678 #else
7679 tcg_gen_shli_tl(t0, t0, 16);
7680 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7681 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7682 #endif
7683 tcg_temp_free(t0);
7684 }
7685
7686 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7687 {
7688 TCGv t0 = tcg_temp_new();
7689 gen_qemu_ld16u(ctx, t0, addr);
7690 #if defined(TARGET_PPC64)
7691 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7692 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7693 #else
7694 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7695 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7696 #endif
7697 tcg_temp_free(t0);
7698 }
7699
7700 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7701 {
7702 TCGv t0 = tcg_temp_new();
7703 gen_qemu_ld16s(ctx, t0, addr);
7704 #if defined(TARGET_PPC64)
7705 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7706 tcg_gen_ext32u_tl(t0, t0);
7707 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7708 #else
7709 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7710 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7711 #endif
7712 tcg_temp_free(t0);
7713 }
7714
7715 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7716 {
7717 TCGv t0 = tcg_temp_new();
7718 #if defined(TARGET_PPC64)
7719 gen_qemu_ld16u(ctx, t0, addr);
7720 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7721 gen_addr_add(ctx, addr, addr, 2);
7722 gen_qemu_ld16u(ctx, t0, addr);
7723 tcg_gen_shli_tl(t0, t0, 16);
7724 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7725 #else
7726 gen_qemu_ld16u(ctx, t0, addr);
7727 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7728 gen_addr_add(ctx, addr, addr, 2);
7729 gen_qemu_ld16u(ctx, t0, addr);
7730 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7731 #endif
7732 tcg_temp_free(t0);
7733 }
7734
7735 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7736 {
7737 #if defined(TARGET_PPC64)
7738 TCGv t0 = tcg_temp_new();
7739 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7740 gen_addr_add(ctx, addr, addr, 2);
7741 gen_qemu_ld16u(ctx, t0, addr);
7742 tcg_gen_shli_tl(t0, t0, 32);
7743 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7744 tcg_temp_free(t0);
7745 #else
7746 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7747 gen_addr_add(ctx, addr, addr, 2);
7748 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7749 #endif
7750 }
7751
7752 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7753 {
7754 #if defined(TARGET_PPC64)
7755 TCGv t0 = tcg_temp_new();
7756 gen_qemu_ld16s(ctx, t0, addr);
7757 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7758 gen_addr_add(ctx, addr, addr, 2);
7759 gen_qemu_ld16s(ctx, t0, addr);
7760 tcg_gen_shli_tl(t0, t0, 32);
7761 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7762 tcg_temp_free(t0);
7763 #else
7764 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7765 gen_addr_add(ctx, addr, addr, 2);
7766 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7767 #endif
7768 }
7769
7770 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7771 {
7772 TCGv t0 = tcg_temp_new();
7773 gen_qemu_ld32u(ctx, t0, addr);
7774 #if defined(TARGET_PPC64)
7775 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7776 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7777 #else
7778 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7779 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7780 #endif
7781 tcg_temp_free(t0);
7782 }
7783
7784 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7785 {
7786 TCGv t0 = tcg_temp_new();
7787 #if defined(TARGET_PPC64)
7788 gen_qemu_ld16u(ctx, t0, addr);
7789 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7790 tcg_gen_shli_tl(t0, t0, 32);
7791 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7792 gen_addr_add(ctx, addr, addr, 2);
7793 gen_qemu_ld16u(ctx, t0, addr);
7794 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7795 tcg_gen_shli_tl(t0, t0, 16);
7796 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7797 #else
7798 gen_qemu_ld16u(ctx, t0, addr);
7799 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7800 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7801 gen_addr_add(ctx, addr, addr, 2);
7802 gen_qemu_ld16u(ctx, t0, addr);
7803 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7804 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7805 #endif
7806 tcg_temp_free(t0);
7807 }
7808
7809 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7810 {
7811 #if defined(TARGET_PPC64)
7812 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7813 #else
7814 TCGv_i64 t0 = tcg_temp_new_i64();
7815 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7816 gen_qemu_st64(ctx, t0, addr);
7817 tcg_temp_free_i64(t0);
7818 #endif
7819 }
7820
7821 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7822 {
7823 #if defined(TARGET_PPC64)
7824 TCGv t0 = tcg_temp_new();
7825 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7826 gen_qemu_st32(ctx, t0, addr);
7827 tcg_temp_free(t0);
7828 #else
7829 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7830 #endif
7831 gen_addr_add(ctx, addr, addr, 4);
7832 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7833 }
7834
7835 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7836 {
7837 TCGv t0 = tcg_temp_new();
7838 #if defined(TARGET_PPC64)
7839 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7840 #else
7841 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7842 #endif
7843 gen_qemu_st16(ctx, t0, addr);
7844 gen_addr_add(ctx, addr, addr, 2);
7845 #if defined(TARGET_PPC64)
7846 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7847 gen_qemu_st16(ctx, t0, addr);
7848 #else
7849 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7850 #endif
7851 gen_addr_add(ctx, addr, addr, 2);
7852 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7853 gen_qemu_st16(ctx, t0, addr);
7854 tcg_temp_free(t0);
7855 gen_addr_add(ctx, addr, addr, 2);
7856 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7857 }
7858
7859 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7860 {
7861 TCGv t0 = tcg_temp_new();
7862 #if defined(TARGET_PPC64)
7863 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7864 #else
7865 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7866 #endif
7867 gen_qemu_st16(ctx, t0, addr);
7868 gen_addr_add(ctx, addr, addr, 2);
7869 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7870 gen_qemu_st16(ctx, t0, addr);
7871 tcg_temp_free(t0);
7872 }
7873
7874 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7875 {
7876 #if defined(TARGET_PPC64)
7877 TCGv t0 = tcg_temp_new();
7878 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7879 gen_qemu_st16(ctx, t0, addr);
7880 tcg_temp_free(t0);
7881 #else
7882 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7883 #endif
7884 gen_addr_add(ctx, addr, addr, 2);
7885 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7886 }
7887
7888 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7889 {
7890 #if defined(TARGET_PPC64)
7891 TCGv t0 = tcg_temp_new();
7892 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7893 gen_qemu_st32(ctx, t0, addr);
7894 tcg_temp_free(t0);
7895 #else
7896 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7897 #endif
7898 }
7899
7900 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7901 {
7902 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7903 }
7904
7905 #define GEN_SPEOP_LDST(name, opc2, sh) \
7906 static void glue(gen_, name)(DisasContext *ctx) \
7907 { \
7908 TCGv t0; \
7909 if (unlikely(!ctx->spe_enabled)) { \
7910 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7911 return; \
7912 } \
7913 gen_set_access_type(ctx, ACCESS_INT); \
7914 t0 = tcg_temp_new(); \
7915 if (Rc(ctx->opcode)) { \
7916 gen_addr_spe_imm_index(ctx, t0, sh); \
7917 } else { \
7918 gen_addr_reg_index(ctx, t0); \
7919 } \
7920 gen_op_##name(ctx, t0); \
7921 tcg_temp_free(t0); \
7922 }
7923
7924 GEN_SPEOP_LDST(evldd, 0x00, 3);
7925 GEN_SPEOP_LDST(evldw, 0x01, 3);
7926 GEN_SPEOP_LDST(evldh, 0x02, 3);
7927 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7928 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7929 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7930 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7931 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7932 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7933 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7934 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7935
7936 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7937 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7938 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7939 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7940 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7941 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7942 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7943
7944 /* Multiply and add - TODO */
7945 #if 0
7946 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7947 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7948 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7949 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7950 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7951 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7952 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7953 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7954 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7955 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7956 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7957 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7958
7959 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7960 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7961 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7962 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7963 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7964 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7965 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7966 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7967 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7968 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7969 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7970 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7971
7972 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7973 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7974 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7975 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7976 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7977
7978 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7979 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7980 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7981 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7982 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7983 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7984 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7985 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7986 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7987 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7988 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7989 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7990
7991 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7992 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7993 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7994 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7995
7996 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7997 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7998 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7999 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8000 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8001 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8002 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8003 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8004 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8005 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8006 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8007 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8008
8009 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8010 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8011 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8012 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8013 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8014 #endif
8015
8016 /*** SPE floating-point extension ***/
8017 #if defined(TARGET_PPC64)
8018 #define GEN_SPEFPUOP_CONV_32_32(name) \
8019 static inline void gen_##name(DisasContext *ctx) \
8020 { \
8021 TCGv_i32 t0; \
8022 TCGv t1; \
8023 t0 = tcg_temp_new_i32(); \
8024 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8025 gen_helper_##name(t0, cpu_env, t0); \
8026 t1 = tcg_temp_new(); \
8027 tcg_gen_extu_i32_tl(t1, t0); \
8028 tcg_temp_free_i32(t0); \
8029 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8030 0xFFFFFFFF00000000ULL); \
8031 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8032 tcg_temp_free(t1); \
8033 }
8034 #define GEN_SPEFPUOP_CONV_32_64(name) \
8035 static inline void gen_##name(DisasContext *ctx) \
8036 { \
8037 TCGv_i32 t0; \
8038 TCGv t1; \
8039 t0 = tcg_temp_new_i32(); \
8040 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8041 t1 = tcg_temp_new(); \
8042 tcg_gen_extu_i32_tl(t1, t0); \
8043 tcg_temp_free_i32(t0); \
8044 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8045 0xFFFFFFFF00000000ULL); \
8046 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8047 tcg_temp_free(t1); \
8048 }
8049 #define GEN_SPEFPUOP_CONV_64_32(name) \
8050 static inline void gen_##name(DisasContext *ctx) \
8051 { \
8052 TCGv_i32 t0 = tcg_temp_new_i32(); \
8053 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8054 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8055 tcg_temp_free_i32(t0); \
8056 }
8057 #define GEN_SPEFPUOP_CONV_64_64(name) \
8058 static inline void gen_##name(DisasContext *ctx) \
8059 { \
8060 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8061 cpu_gpr[rB(ctx->opcode)]); \
8062 }
8063 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8064 static inline void gen_##name(DisasContext *ctx) \
8065 { \
8066 TCGv_i32 t0, t1; \
8067 TCGv_i64 t2; \
8068 if (unlikely(!ctx->spe_enabled)) { \
8069 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8070 return; \
8071 } \
8072 t0 = tcg_temp_new_i32(); \
8073 t1 = tcg_temp_new_i32(); \
8074 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8075 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8076 gen_helper_##name(t0, cpu_env, t0, t1); \
8077 tcg_temp_free_i32(t1); \
8078 t2 = tcg_temp_new(); \
8079 tcg_gen_extu_i32_tl(t2, t0); \
8080 tcg_temp_free_i32(t0); \
8081 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8082 0xFFFFFFFF00000000ULL); \
8083 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8084 tcg_temp_free(t2); \
8085 }
8086 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8087 static inline void gen_##name(DisasContext *ctx) \
8088 { \
8089 if (unlikely(!ctx->spe_enabled)) { \
8090 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8091 return; \
8092 } \
8093 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8094 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8095 }
8096 #define GEN_SPEFPUOP_COMP_32(name) \
8097 static inline void gen_##name(DisasContext *ctx) \
8098 { \
8099 TCGv_i32 t0, t1; \
8100 if (unlikely(!ctx->spe_enabled)) { \
8101 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8102 return; \
8103 } \
8104 t0 = tcg_temp_new_i32(); \
8105 t1 = tcg_temp_new_i32(); \
8106 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8107 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8108 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8109 tcg_temp_free_i32(t0); \
8110 tcg_temp_free_i32(t1); \
8111 }
8112 #define GEN_SPEFPUOP_COMP_64(name) \
8113 static inline void gen_##name(DisasContext *ctx) \
8114 { \
8115 if (unlikely(!ctx->spe_enabled)) { \
8116 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8117 return; \
8118 } \
8119 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8120 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8121 }
8122 #else
8123 #define GEN_SPEFPUOP_CONV_32_32(name) \
8124 static inline void gen_##name(DisasContext *ctx) \
8125 { \
8126 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8127 cpu_gpr[rB(ctx->opcode)]); \
8128 }
8129 #define GEN_SPEFPUOP_CONV_32_64(name) \
8130 static inline void gen_##name(DisasContext *ctx) \
8131 { \
8132 TCGv_i64 t0 = tcg_temp_new_i64(); \
8133 gen_load_gpr64(t0, rB(ctx->opcode)); \
8134 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8135 tcg_temp_free_i64(t0); \
8136 }
8137 #define GEN_SPEFPUOP_CONV_64_32(name) \
8138 static inline void gen_##name(DisasContext *ctx) \
8139 { \
8140 TCGv_i64 t0 = tcg_temp_new_i64(); \
8141 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8142 gen_store_gpr64(rD(ctx->opcode), t0); \
8143 tcg_temp_free_i64(t0); \
8144 }
8145 #define GEN_SPEFPUOP_CONV_64_64(name) \
8146 static inline void gen_##name(DisasContext *ctx) \
8147 { \
8148 TCGv_i64 t0 = tcg_temp_new_i64(); \
8149 gen_load_gpr64(t0, rB(ctx->opcode)); \
8150 gen_helper_##name(t0, cpu_env, t0); \
8151 gen_store_gpr64(rD(ctx->opcode), t0); \
8152 tcg_temp_free_i64(t0); \
8153 }
8154 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8155 static inline void gen_##name(DisasContext *ctx) \
8156 { \
8157 if (unlikely(!ctx->spe_enabled)) { \
8158 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8159 return; \
8160 } \
8161 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8162 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8163 }
8164 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8165 static inline void gen_##name(DisasContext *ctx) \
8166 { \
8167 TCGv_i64 t0, t1; \
8168 if (unlikely(!ctx->spe_enabled)) { \
8169 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8170 return; \
8171 } \
8172 t0 = tcg_temp_new_i64(); \
8173 t1 = tcg_temp_new_i64(); \
8174 gen_load_gpr64(t0, rA(ctx->opcode)); \
8175 gen_load_gpr64(t1, rB(ctx->opcode)); \
8176 gen_helper_##name(t0, cpu_env, t0, t1); \
8177 gen_store_gpr64(rD(ctx->opcode), t0); \
8178 tcg_temp_free_i64(t0); \
8179 tcg_temp_free_i64(t1); \
8180 }
8181 #define GEN_SPEFPUOP_COMP_32(name) \
8182 static inline void gen_##name(DisasContext *ctx) \
8183 { \
8184 if (unlikely(!ctx->spe_enabled)) { \
8185 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8186 return; \
8187 } \
8188 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8189 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8190 }
8191 #define GEN_SPEFPUOP_COMP_64(name) \
8192 static inline void gen_##name(DisasContext *ctx) \
8193 { \
8194 TCGv_i64 t0, t1; \
8195 if (unlikely(!ctx->spe_enabled)) { \
8196 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8197 return; \
8198 } \
8199 t0 = tcg_temp_new_i64(); \
8200 t1 = tcg_temp_new_i64(); \
8201 gen_load_gpr64(t0, rA(ctx->opcode)); \
8202 gen_load_gpr64(t1, rB(ctx->opcode)); \
8203 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8204 tcg_temp_free_i64(t0); \
8205 tcg_temp_free_i64(t1); \
8206 }
8207 #endif
8208
8209 /* Single precision floating-point vectors operations */
8210 /* Arithmetic */
8211 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8212 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8213 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8214 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8215 static inline void gen_evfsabs(DisasContext *ctx)
8216 {
8217 if (unlikely(!ctx->spe_enabled)) {
8218 gen_exception(ctx, POWERPC_EXCP_SPEU);
8219 return;
8220 }
8221 #if defined(TARGET_PPC64)
8222 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8223 #else
8224 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8225 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8226 #endif
8227 }
8228 static inline void gen_evfsnabs(DisasContext *ctx)
8229 {
8230 if (unlikely(!ctx->spe_enabled)) {
8231 gen_exception(ctx, POWERPC_EXCP_SPEU);
8232 return;
8233 }
8234 #if defined(TARGET_PPC64)
8235 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8236 #else
8237 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8238 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8239 #endif
8240 }
8241 static inline void gen_evfsneg(DisasContext *ctx)
8242 {
8243 if (unlikely(!ctx->spe_enabled)) {
8244 gen_exception(ctx, POWERPC_EXCP_SPEU);
8245 return;
8246 }
8247 #if defined(TARGET_PPC64)
8248 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8249 #else
8250 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8251 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8252 #endif
8253 }
8254
8255 /* Conversion */
8256 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8257 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8258 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8259 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8260 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8261 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8262 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8263 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8264 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8265 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8266
8267 /* Comparison */
8268 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8269 GEN_SPEFPUOP_COMP_64(evfscmplt);
8270 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8271 GEN_SPEFPUOP_COMP_64(evfststgt);
8272 GEN_SPEFPUOP_COMP_64(evfststlt);
8273 GEN_SPEFPUOP_COMP_64(evfststeq);
8274
8275 /* Opcodes definitions */
8276 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8277 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8278 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8279 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8280 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8281 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8282 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8283 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8284 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8285 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8286 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8287 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8288 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8289 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8290
8291 /* Single precision floating-point operations */
8292 /* Arithmetic */
8293 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8294 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8295 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8296 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8297 static inline void gen_efsabs(DisasContext *ctx)
8298 {
8299 if (unlikely(!ctx->spe_enabled)) {
8300 gen_exception(ctx, POWERPC_EXCP_SPEU);
8301 return;
8302 }
8303 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8304 }
8305 static inline void gen_efsnabs(DisasContext *ctx)
8306 {
8307 if (unlikely(!ctx->spe_enabled)) {
8308 gen_exception(ctx, POWERPC_EXCP_SPEU);
8309 return;
8310 }
8311 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8312 }
8313 static inline void gen_efsneg(DisasContext *ctx)
8314 {
8315 if (unlikely(!ctx->spe_enabled)) {
8316 gen_exception(ctx, POWERPC_EXCP_SPEU);
8317 return;
8318 }
8319 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8320 }
8321
8322 /* Conversion */
8323 GEN_SPEFPUOP_CONV_32_32(efscfui);
8324 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8325 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8326 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8327 GEN_SPEFPUOP_CONV_32_32(efsctui);
8328 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8329 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8330 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8331 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8332 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8333 GEN_SPEFPUOP_CONV_32_64(efscfd);
8334
8335 /* Comparison */
8336 GEN_SPEFPUOP_COMP_32(efscmpgt);
8337 GEN_SPEFPUOP_COMP_32(efscmplt);
8338 GEN_SPEFPUOP_COMP_32(efscmpeq);
8339 GEN_SPEFPUOP_COMP_32(efststgt);
8340 GEN_SPEFPUOP_COMP_32(efststlt);
8341 GEN_SPEFPUOP_COMP_32(efststeq);
8342
8343 /* Opcodes definitions */
8344 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8345 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8346 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8347 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8348 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8349 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8350 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8351 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8352 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8353 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8354 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8355 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8356 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8357 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8358
8359 /* Double precision floating-point operations */
8360 /* Arithmetic */
8361 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8362 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8363 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8364 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8365 static inline void gen_efdabs(DisasContext *ctx)
8366 {
8367 if (unlikely(!ctx->spe_enabled)) {
8368 gen_exception(ctx, POWERPC_EXCP_SPEU);
8369 return;
8370 }
8371 #if defined(TARGET_PPC64)
8372 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8373 #else
8374 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8375 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8376 #endif
8377 }
8378 static inline void gen_efdnabs(DisasContext *ctx)
8379 {
8380 if (unlikely(!ctx->spe_enabled)) {
8381 gen_exception(ctx, POWERPC_EXCP_SPEU);
8382 return;
8383 }
8384 #if defined(TARGET_PPC64)
8385 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8386 #else
8387 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8388 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8389 #endif
8390 }
8391 static inline void gen_efdneg(DisasContext *ctx)
8392 {
8393 if (unlikely(!ctx->spe_enabled)) {
8394 gen_exception(ctx, POWERPC_EXCP_SPEU);
8395 return;
8396 }
8397 #if defined(TARGET_PPC64)
8398 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8399 #else
8400 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8401 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8402 #endif
8403 }
8404
8405 /* Conversion */
8406 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8407 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8408 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8409 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8410 GEN_SPEFPUOP_CONV_32_64(efdctui);
8411 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8412 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8413 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8414 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8415 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8416 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8417 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8418 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8419 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8420 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8421
8422 /* Comparison */
8423 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8424 GEN_SPEFPUOP_COMP_64(efdcmplt);
8425 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8426 GEN_SPEFPUOP_COMP_64(efdtstgt);
8427 GEN_SPEFPUOP_COMP_64(efdtstlt);
8428 GEN_SPEFPUOP_COMP_64(efdtsteq);
8429
8430 /* Opcodes definitions */
8431 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8432 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8433 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8434 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8435 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8436 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8437 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8438 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8439 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8440 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8441 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8442 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8443 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8444 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8445 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8446 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8447
8448 static opcode_t opcodes[] = {
8449 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8450 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8451 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8452 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8453 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8454 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8455 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8456 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8457 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8458 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8459 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8460 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8461 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8462 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8463 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8464 #if defined(TARGET_PPC64)
8465 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8466 #endif
8467 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8468 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8469 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8470 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8471 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8472 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8473 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8474 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8475 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8476 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8477 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8478 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8479 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8480 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8481 #if defined(TARGET_PPC64)
8482 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8483 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8484 #endif
8485 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8486 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8487 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8488 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8489 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8490 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8491 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8492 #if defined(TARGET_PPC64)
8493 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8494 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8495 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8496 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8497 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8498 #endif
8499 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8500 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8501 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8502 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8503 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8504 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8505 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8506 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8507 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8508 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8509 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8510 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8511 #if defined(TARGET_PPC64)
8512 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8513 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8514 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8515 #endif
8516 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8517 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8518 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8519 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8520 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8521 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8522 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8523 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8524 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8525 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8526 #if defined(TARGET_PPC64)
8527 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8528 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8529 #endif
8530 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8531 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8532 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8533 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8534 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8535 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8536 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8537 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8538 #if defined(TARGET_PPC64)
8539 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8540 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8541 #endif
8542 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8543 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8544 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8545 #if defined(TARGET_PPC64)
8546 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8547 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8548 #endif
8549 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8550 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8551 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8552 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8553 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8554 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8555 #if defined(TARGET_PPC64)
8556 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8557 #endif
8558 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8559 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8560 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8561 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8562 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8563 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8564 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8565 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8566 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8567 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8568 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8569 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8570 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8571 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8572 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8573 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8574 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8575 #if defined(TARGET_PPC64)
8576 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8577 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8578 PPC_SEGMENT_64B),
8579 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8580 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8581 PPC_SEGMENT_64B),
8582 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8583 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8584 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8585 #endif
8586 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8587 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8588 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8589 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8590 #if defined(TARGET_PPC64)
8591 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8592 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8593 #endif
8594 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8595 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8596 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8597 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8598 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8599 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8600 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8601 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8602 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8603 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8604 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8605 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8606 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8607 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8608 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8609 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8610 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8611 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8612 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8613 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8614 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8615 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8616 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8617 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8618 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8619 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8620 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8621 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8622 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8623 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8624 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8625 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8626 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8627 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8628 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8629 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8630 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8631 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8632 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8633 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8634 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8635 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8636 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8637 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8638 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8639 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8640 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8641 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8642 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8643 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8644 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8645 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8646 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8647 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8648 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8649 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8650 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8651 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8652 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8653 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8654 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8655 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8656 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8657 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8658 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8659 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8660 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8661 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8662 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8663 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8664 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8665 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8666 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8667 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8668 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8669 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8670 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8671 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8672 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8673 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8674 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8675 PPC_NONE, PPC2_BOOKE206),
8676 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8677 PPC_NONE, PPC2_BOOKE206),
8678 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8679 PPC_NONE, PPC2_BOOKE206),
8680 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8681 PPC_NONE, PPC2_BOOKE206),
8682 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8683 PPC_NONE, PPC2_BOOKE206),
8684 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8685 PPC_NONE, PPC2_PRCNTL),
8686 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8687 PPC_NONE, PPC2_PRCNTL),
8688 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8689 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8690 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8691 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8692 PPC_BOOKE, PPC2_BOOKE206),
8693 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8694 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8695 PPC_BOOKE, PPC2_BOOKE206),
8696 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8697 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8698 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8699 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8700 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8701 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8702 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8703 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8704 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8705 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8706
8707 #undef GEN_INT_ARITH_ADD
8708 #undef GEN_INT_ARITH_ADD_CONST
8709 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8710 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8711 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8712 add_ca, compute_ca, compute_ov) \
8713 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8714 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8715 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8716 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8717 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8718 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8719 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8720 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8721 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8722 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8723 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8724
8725 #undef GEN_INT_ARITH_DIVW
8726 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8727 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8728 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8729 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8730 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8731 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8732
8733 #if defined(TARGET_PPC64)
8734 #undef GEN_INT_ARITH_DIVD
8735 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8736 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8737 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8738 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8739 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8740 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8741
8742 #undef GEN_INT_ARITH_MUL_HELPER
8743 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8744 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8745 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8746 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8747 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8748 #endif
8749
8750 #undef GEN_INT_ARITH_SUBF
8751 #undef GEN_INT_ARITH_SUBF_CONST
8752 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8753 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8754 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8755 add_ca, compute_ca, compute_ov) \
8756 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8757 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8758 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8759 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8760 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8761 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8762 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8763 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8764 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8765 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8766 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8767
8768 #undef GEN_LOGICAL1
8769 #undef GEN_LOGICAL2
8770 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8771 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8772 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8773 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8774 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8775 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8776 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8777 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8778 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8779 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8780 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8781 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8782 #if defined(TARGET_PPC64)
8783 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8784 #endif
8785
8786 #if defined(TARGET_PPC64)
8787 #undef GEN_PPC64_R2
8788 #undef GEN_PPC64_R4
8789 #define GEN_PPC64_R2(name, opc1, opc2) \
8790 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8791 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8792 PPC_64B)
8793 #define GEN_PPC64_R4(name, opc1, opc2) \
8794 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8795 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8796 PPC_64B), \
8797 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8798 PPC_64B), \
8799 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8800 PPC_64B)
8801 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8802 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8803 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8804 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8805 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8806 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8807 #endif
8808
8809 #undef _GEN_FLOAT_ACB
8810 #undef GEN_FLOAT_ACB
8811 #undef _GEN_FLOAT_AB
8812 #undef GEN_FLOAT_AB
8813 #undef _GEN_FLOAT_AC
8814 #undef GEN_FLOAT_AC
8815 #undef GEN_FLOAT_B
8816 #undef GEN_FLOAT_BS
8817 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8818 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8819 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8820 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8821 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8822 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8823 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8824 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8825 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8826 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8827 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8828 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8829 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8830 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8831 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8832 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8833 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8834 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8835 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8836
8837 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8838 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8839 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8840 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8841 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8842 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8843 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8844 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8845 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8846 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8847 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8848 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8849 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8850 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8851 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8852 #if defined(TARGET_PPC64)
8853 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8854 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8855 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8856 #endif
8857 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8858 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8859 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8860 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8861 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8862 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8863 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8864
8865 #undef GEN_LD
8866 #undef GEN_LDU
8867 #undef GEN_LDUX
8868 #undef GEN_LDX_E
8869 #undef GEN_LDS
8870 #define GEN_LD(name, ldop, opc, type) \
8871 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8872 #define GEN_LDU(name, ldop, opc, type) \
8873 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8874 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8875 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8876 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8877 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8878 #define GEN_LDS(name, ldop, op, type) \
8879 GEN_LD(name, ldop, op | 0x20, type) \
8880 GEN_LDU(name, ldop, op | 0x21, type) \
8881 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8882 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8883
8884 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8885 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8886 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8887 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8888 #if defined(TARGET_PPC64)
8889 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8890 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8891 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8892 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8893 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8894 #endif
8895 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8896 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8897
8898 #undef GEN_ST
8899 #undef GEN_STU
8900 #undef GEN_STUX
8901 #undef GEN_STX_E
8902 #undef GEN_STS
8903 #define GEN_ST(name, stop, opc, type) \
8904 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8905 #define GEN_STU(name, stop, opc, type) \
8906 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8907 #define GEN_STUX(name, stop, opc2, opc3, type) \
8908 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8909 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8910 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8911 #define GEN_STS(name, stop, op, type) \
8912 GEN_ST(name, stop, op | 0x20, type) \
8913 GEN_STU(name, stop, op | 0x21, type) \
8914 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8915 GEN_STX(name, stop, 0x17, op | 0x00, type)
8916
8917 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8918 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8919 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8920 #if defined(TARGET_PPC64)
8921 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8922 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8923 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8924 #endif
8925 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8926 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8927
8928 #undef GEN_LDF
8929 #undef GEN_LDUF
8930 #undef GEN_LDUXF
8931 #undef GEN_LDXF
8932 #undef GEN_LDFS
8933 #define GEN_LDF(name, ldop, opc, type) \
8934 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8935 #define GEN_LDUF(name, ldop, opc, type) \
8936 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8937 #define GEN_LDUXF(name, ldop, opc, type) \
8938 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8939 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8940 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8941 #define GEN_LDFS(name, ldop, op, type) \
8942 GEN_LDF(name, ldop, op | 0x20, type) \
8943 GEN_LDUF(name, ldop, op | 0x21, type) \
8944 GEN_LDUXF(name, ldop, op | 0x01, type) \
8945 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8946
8947 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8948 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8949
8950 #undef GEN_STF
8951 #undef GEN_STUF
8952 #undef GEN_STUXF
8953 #undef GEN_STXF
8954 #undef GEN_STFS
8955 #define GEN_STF(name, stop, opc, type) \
8956 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8957 #define GEN_STUF(name, stop, opc, type) \
8958 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8959 #define GEN_STUXF(name, stop, opc, type) \
8960 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8961 #define GEN_STXF(name, stop, opc2, opc3, type) \
8962 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8963 #define GEN_STFS(name, stop, op, type) \
8964 GEN_STF(name, stop, op | 0x20, type) \
8965 GEN_STUF(name, stop, op | 0x21, type) \
8966 GEN_STUXF(name, stop, op | 0x01, type) \
8967 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8968
8969 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8970 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8971 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8972
8973 #undef GEN_CRLOGIC
8974 #define GEN_CRLOGIC(name, tcg_op, opc) \
8975 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8976 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8977 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8978 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8979 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8980 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8981 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8982 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8983 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8984
8985 #undef GEN_MAC_HANDLER
8986 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8987 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8988 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8989 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8990 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8991 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8992 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8993 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8994 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8995 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8996 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8997 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8998 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8999 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9000 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9001 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9002 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9003 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9004 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9005 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9006 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9007 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9008 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9009 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9010 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9011 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9012 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9013 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9014 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9015 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9016 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9017 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9018 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9019 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9020 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9021 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9022 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9023 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9024 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9025 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9026 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9027 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9028 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9029 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9030
9031 #undef GEN_VR_LDX
9032 #undef GEN_VR_STX
9033 #undef GEN_VR_LVE
9034 #undef GEN_VR_STVE
9035 #define GEN_VR_LDX(name, opc2, opc3) \
9036 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9037 #define GEN_VR_STX(name, opc2, opc3) \
9038 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9039 #define GEN_VR_LVE(name, opc2, opc3) \
9040 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9041 #define GEN_VR_STVE(name, opc2, opc3) \
9042 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9043 GEN_VR_LDX(lvx, 0x07, 0x03),
9044 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9045 GEN_VR_LVE(bx, 0x07, 0x00),
9046 GEN_VR_LVE(hx, 0x07, 0x01),
9047 GEN_VR_LVE(wx, 0x07, 0x02),
9048 GEN_VR_STX(svx, 0x07, 0x07),
9049 GEN_VR_STX(svxl, 0x07, 0x0F),
9050 GEN_VR_STVE(bx, 0x07, 0x04),
9051 GEN_VR_STVE(hx, 0x07, 0x05),
9052 GEN_VR_STVE(wx, 0x07, 0x06),
9053
9054 #undef GEN_VX_LOGICAL
9055 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9056 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9057 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9058 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9059 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9060 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9061 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9062
9063 #undef GEN_VXFORM
9064 #define GEN_VXFORM(name, opc2, opc3) \
9065 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9066 GEN_VXFORM(vaddubm, 0, 0),
9067 GEN_VXFORM(vadduhm, 0, 1),
9068 GEN_VXFORM(vadduwm, 0, 2),
9069 GEN_VXFORM(vsububm, 0, 16),
9070 GEN_VXFORM(vsubuhm, 0, 17),
9071 GEN_VXFORM(vsubuwm, 0, 18),
9072 GEN_VXFORM(vmaxub, 1, 0),
9073 GEN_VXFORM(vmaxuh, 1, 1),
9074 GEN_VXFORM(vmaxuw, 1, 2),
9075 GEN_VXFORM(vmaxsb, 1, 4),
9076 GEN_VXFORM(vmaxsh, 1, 5),
9077 GEN_VXFORM(vmaxsw, 1, 6),
9078 GEN_VXFORM(vminub, 1, 8),
9079 GEN_VXFORM(vminuh, 1, 9),
9080 GEN_VXFORM(vminuw, 1, 10),
9081 GEN_VXFORM(vminsb, 1, 12),
9082 GEN_VXFORM(vminsh, 1, 13),
9083 GEN_VXFORM(vminsw, 1, 14),
9084 GEN_VXFORM(vavgub, 1, 16),
9085 GEN_VXFORM(vavguh, 1, 17),
9086 GEN_VXFORM(vavguw, 1, 18),
9087 GEN_VXFORM(vavgsb, 1, 20),
9088 GEN_VXFORM(vavgsh, 1, 21),
9089 GEN_VXFORM(vavgsw, 1, 22),
9090 GEN_VXFORM(vmrghb, 6, 0),
9091 GEN_VXFORM(vmrghh, 6, 1),
9092 GEN_VXFORM(vmrghw, 6, 2),
9093 GEN_VXFORM(vmrglb, 6, 4),
9094 GEN_VXFORM(vmrglh, 6, 5),
9095 GEN_VXFORM(vmrglw, 6, 6),
9096 GEN_VXFORM(vmuloub, 4, 0),
9097 GEN_VXFORM(vmulouh, 4, 1),
9098 GEN_VXFORM(vmulosb, 4, 4),
9099 GEN_VXFORM(vmulosh, 4, 5),
9100 GEN_VXFORM(vmuleub, 4, 8),
9101 GEN_VXFORM(vmuleuh, 4, 9),
9102 GEN_VXFORM(vmulesb, 4, 12),
9103 GEN_VXFORM(vmulesh, 4, 13),
9104 GEN_VXFORM(vslb, 2, 4),
9105 GEN_VXFORM(vslh, 2, 5),
9106 GEN_VXFORM(vslw, 2, 6),
9107 GEN_VXFORM(vsrb, 2, 8),
9108 GEN_VXFORM(vsrh, 2, 9),
9109 GEN_VXFORM(vsrw, 2, 10),
9110 GEN_VXFORM(vsrab, 2, 12),
9111 GEN_VXFORM(vsrah, 2, 13),
9112 GEN_VXFORM(vsraw, 2, 14),
9113 GEN_VXFORM(vslo, 6, 16),
9114 GEN_VXFORM(vsro, 6, 17),
9115 GEN_VXFORM(vaddcuw, 0, 6),
9116 GEN_VXFORM(vsubcuw, 0, 22),
9117 GEN_VXFORM(vaddubs, 0, 8),
9118 GEN_VXFORM(vadduhs, 0, 9),
9119 GEN_VXFORM(vadduws, 0, 10),
9120 GEN_VXFORM(vaddsbs, 0, 12),
9121 GEN_VXFORM(vaddshs, 0, 13),
9122 GEN_VXFORM(vaddsws, 0, 14),
9123 GEN_VXFORM(vsububs, 0, 24),
9124 GEN_VXFORM(vsubuhs, 0, 25),
9125 GEN_VXFORM(vsubuws, 0, 26),
9126 GEN_VXFORM(vsubsbs, 0, 28),
9127 GEN_VXFORM(vsubshs, 0, 29),
9128 GEN_VXFORM(vsubsws, 0, 30),
9129 GEN_VXFORM(vrlb, 2, 0),
9130 GEN_VXFORM(vrlh, 2, 1),
9131 GEN_VXFORM(vrlw, 2, 2),
9132 GEN_VXFORM(vsl, 2, 7),
9133 GEN_VXFORM(vsr, 2, 11),
9134 GEN_VXFORM(vpkuhum, 7, 0),
9135 GEN_VXFORM(vpkuwum, 7, 1),
9136 GEN_VXFORM(vpkuhus, 7, 2),
9137 GEN_VXFORM(vpkuwus, 7, 3),
9138 GEN_VXFORM(vpkshus, 7, 4),
9139 GEN_VXFORM(vpkswus, 7, 5),
9140 GEN_VXFORM(vpkshss, 7, 6),
9141 GEN_VXFORM(vpkswss, 7, 7),
9142 GEN_VXFORM(vpkpx, 7, 12),
9143 GEN_VXFORM(vsum4ubs, 4, 24),
9144 GEN_VXFORM(vsum4sbs, 4, 28),
9145 GEN_VXFORM(vsum4shs, 4, 25),
9146 GEN_VXFORM(vsum2sws, 4, 26),
9147 GEN_VXFORM(vsumsws, 4, 30),
9148 GEN_VXFORM(vaddfp, 5, 0),
9149 GEN_VXFORM(vsubfp, 5, 1),
9150 GEN_VXFORM(vmaxfp, 5, 16),
9151 GEN_VXFORM(vminfp, 5, 17),
9152
9153 #undef GEN_VXRFORM1
9154 #undef GEN_VXRFORM
9155 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9156 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9157 #define GEN_VXRFORM(name, opc2, opc3) \
9158 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9159 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9160 GEN_VXRFORM(vcmpequb, 3, 0)
9161 GEN_VXRFORM(vcmpequh, 3, 1)
9162 GEN_VXRFORM(vcmpequw, 3, 2)
9163 GEN_VXRFORM(vcmpgtsb, 3, 12)
9164 GEN_VXRFORM(vcmpgtsh, 3, 13)
9165 GEN_VXRFORM(vcmpgtsw, 3, 14)
9166 GEN_VXRFORM(vcmpgtub, 3, 8)
9167 GEN_VXRFORM(vcmpgtuh, 3, 9)
9168 GEN_VXRFORM(vcmpgtuw, 3, 10)
9169 GEN_VXRFORM(vcmpeqfp, 3, 3)
9170 GEN_VXRFORM(vcmpgefp, 3, 7)
9171 GEN_VXRFORM(vcmpgtfp, 3, 11)
9172 GEN_VXRFORM(vcmpbfp, 3, 15)
9173
9174 #undef GEN_VXFORM_SIMM
9175 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9176 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9177 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9178 GEN_VXFORM_SIMM(vspltish, 6, 13),
9179 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9180
9181 #undef GEN_VXFORM_NOA
9182 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9183 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9184 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9185 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9186 GEN_VXFORM_NOA(vupklsb, 7, 10),
9187 GEN_VXFORM_NOA(vupklsh, 7, 11),
9188 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9189 GEN_VXFORM_NOA(vupklpx, 7, 15),
9190 GEN_VXFORM_NOA(vrefp, 5, 4),
9191 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9192 GEN_VXFORM_NOA(vexptefp, 5, 6),
9193 GEN_VXFORM_NOA(vlogefp, 5, 7),
9194 GEN_VXFORM_NOA(vrfim, 5, 8),
9195 GEN_VXFORM_NOA(vrfin, 5, 9),
9196 GEN_VXFORM_NOA(vrfip, 5, 10),
9197 GEN_VXFORM_NOA(vrfiz, 5, 11),
9198
9199 #undef GEN_VXFORM_UIMM
9200 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9201 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9202 GEN_VXFORM_UIMM(vspltb, 6, 8),
9203 GEN_VXFORM_UIMM(vsplth, 6, 9),
9204 GEN_VXFORM_UIMM(vspltw, 6, 10),
9205 GEN_VXFORM_UIMM(vcfux, 5, 12),
9206 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9207 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9208 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9209
9210 #undef GEN_VAFORM_PAIRED
9211 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9212 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9213 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9214 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9215 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9216 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9217 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9218 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9219
9220 #undef GEN_SPE
9221 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9222 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9223 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9224 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9225 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9226 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9227 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9228 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9229 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9230 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9231 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9232 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9233 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9234 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9235 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9236 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9237 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9238 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9239 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9240 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9241 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9242 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9243 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9244 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9245 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9246 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9247 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9248 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9249 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9250 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9251 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9252
9253 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9254 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9255 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9256 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9257 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9258 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9259 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9260 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9261 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9262 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9263 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9264 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9265 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9266 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9267
9268 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9269 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9270 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9271 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9272 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9273 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9274 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9275 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9276 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9277 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9278 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9279 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9280 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9281 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9282
9283 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9284 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9285 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9286 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9287 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9288 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9289 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9290 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9291 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9292 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9293 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9294 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9295 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9296 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9297 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9298 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9299
9300 #undef GEN_SPEOP_LDST
9301 #define GEN_SPEOP_LDST(name, opc2, sh) \
9302 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9303 GEN_SPEOP_LDST(evldd, 0x00, 3),
9304 GEN_SPEOP_LDST(evldw, 0x01, 3),
9305 GEN_SPEOP_LDST(evldh, 0x02, 3),
9306 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9307 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9308 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9309 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9310 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9311 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9312 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9313 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9314
9315 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9316 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9317 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9318 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9319 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9320 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9321 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9322 };
9323
9324 #include "helper_regs.h"
9325 #include "translate_init.c"
9326
9327 /*****************************************************************************/
9328 /* Misc PowerPC helpers */
9329 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9330 int flags)
9331 {
9332 #define RGPL 4
9333 #define RFPL 4
9334
9335 int i;
9336
9337 cpu_synchronize_state(env);
9338
9339 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9340 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9341 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9342 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9343 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9344 env->hflags, env->mmu_idx);
9345 #if !defined(NO_TIMER_DUMP)
9346 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9347 #if !defined(CONFIG_USER_ONLY)
9348 " DECR %08" PRIu32
9349 #endif
9350 "\n",
9351 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9352 #if !defined(CONFIG_USER_ONLY)
9353 , cpu_ppc_load_decr(env)
9354 #endif
9355 );
9356 #endif
9357 for (i = 0; i < 32; i++) {
9358 if ((i & (RGPL - 1)) == 0)
9359 cpu_fprintf(f, "GPR%02d", i);
9360 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9361 if ((i & (RGPL - 1)) == (RGPL - 1))
9362 cpu_fprintf(f, "\n");
9363 }
9364 cpu_fprintf(f, "CR ");
9365 for (i = 0; i < 8; i++)
9366 cpu_fprintf(f, "%01x", env->crf[i]);
9367 cpu_fprintf(f, " [");
9368 for (i = 0; i < 8; i++) {
9369 char a = '-';
9370 if (env->crf[i] & 0x08)
9371 a = 'L';
9372 else if (env->crf[i] & 0x04)
9373 a = 'G';
9374 else if (env->crf[i] & 0x02)
9375 a = 'E';
9376 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9377 }
9378 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9379 env->reserve_addr);
9380 for (i = 0; i < 32; i++) {
9381 if ((i & (RFPL - 1)) == 0)
9382 cpu_fprintf(f, "FPR%02d", i);
9383 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9384 if ((i & (RFPL - 1)) == (RFPL - 1))
9385 cpu_fprintf(f, "\n");
9386 }
9387 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9388 #if !defined(CONFIG_USER_ONLY)
9389 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9390 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9391 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9392 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9393
9394 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9395 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9396 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9397 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9398
9399 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9400 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9401 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9402 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9403
9404 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9405 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9406 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9407 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9408 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9409
9410 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9411 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9412 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9413 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9414
9415 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9416 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9417 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9418 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9419
9420 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9421 " EPR " TARGET_FMT_lx "\n",
9422 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9423 env->spr[SPR_BOOKE_EPR]);
9424
9425 /* FSL-specific */
9426 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9427 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9428 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9429 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9430
9431 /*
9432 * IVORs are left out as they are large and do not change often --
9433 * they can be read with "p $ivor0", "p $ivor1", etc.
9434 */
9435 }
9436
9437 #if defined(TARGET_PPC64)
9438 if (env->flags & POWERPC_FLAG_CFAR) {
9439 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9440 }
9441 #endif
9442
9443 switch (env->mmu_model) {
9444 case POWERPC_MMU_32B:
9445 case POWERPC_MMU_601:
9446 case POWERPC_MMU_SOFT_6xx:
9447 case POWERPC_MMU_SOFT_74xx:
9448 #if defined(TARGET_PPC64)
9449 case POWERPC_MMU_64B:
9450 #endif
9451 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9452 break;
9453 case POWERPC_MMU_BOOKE206:
9454 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9455 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9456 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9457 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9458
9459 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9460 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9461 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9462 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9463
9464 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9465 " TLB1CFG " TARGET_FMT_lx "\n",
9466 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9467 env->spr[SPR_BOOKE_TLB1CFG]);
9468 break;
9469 default:
9470 break;
9471 }
9472 #endif
9473
9474 #undef RGPL
9475 #undef RFPL
9476 }
9477
9478 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9479 int flags)
9480 {
9481 #if defined(DO_PPC_STATISTICS)
9482 opc_handler_t **t1, **t2, **t3, *handler;
9483 int op1, op2, op3;
9484
9485 t1 = env->opcodes;
9486 for (op1 = 0; op1 < 64; op1++) {
9487 handler = t1[op1];
9488 if (is_indirect_opcode(handler)) {
9489 t2 = ind_table(handler);
9490 for (op2 = 0; op2 < 32; op2++) {
9491 handler = t2[op2];
9492 if (is_indirect_opcode(handler)) {
9493 t3 = ind_table(handler);
9494 for (op3 = 0; op3 < 32; op3++) {
9495 handler = t3[op3];
9496 if (handler->count == 0)
9497 continue;
9498 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9499 "%016" PRIx64 " %" PRId64 "\n",
9500 op1, op2, op3, op1, (op3 << 5) | op2,
9501 handler->oname,
9502 handler->count, handler->count);
9503 }
9504 } else {
9505 if (handler->count == 0)
9506 continue;
9507 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9508 "%016" PRIx64 " %" PRId64 "\n",
9509 op1, op2, op1, op2, handler->oname,
9510 handler->count, handler->count);
9511 }
9512 }
9513 } else {
9514 if (handler->count == 0)
9515 continue;
9516 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9517 " %" PRId64 "\n",
9518 op1, op1, handler->oname,
9519 handler->count, handler->count);
9520 }
9521 }
9522 #endif
9523 }
9524
9525 /*****************************************************************************/
9526 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9527 TranslationBlock *tb,
9528 int search_pc)
9529 {
9530 DisasContext ctx, *ctxp = &ctx;
9531 opc_handler_t **table, *handler;
9532 target_ulong pc_start;
9533 uint16_t *gen_opc_end;
9534 CPUBreakpoint *bp;
9535 int j, lj = -1;
9536 int num_insns;
9537 int max_insns;
9538
9539 pc_start = tb->pc;
9540 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9541 ctx.nip = pc_start;
9542 ctx.tb = tb;
9543 ctx.exception = POWERPC_EXCP_NONE;
9544 ctx.spr_cb = env->spr_cb;
9545 ctx.mem_idx = env->mmu_idx;
9546 ctx.access_type = -1;
9547 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9548 #if defined(TARGET_PPC64)
9549 ctx.sf_mode = msr_is_64bit(env, env->msr);
9550 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9551 #endif
9552 ctx.fpu_enabled = msr_fp;
9553 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9554 ctx.spe_enabled = msr_spe;
9555 else
9556 ctx.spe_enabled = 0;
9557 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9558 ctx.altivec_enabled = msr_vr;
9559 else
9560 ctx.altivec_enabled = 0;
9561 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9562 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9563 else
9564 ctx.singlestep_enabled = 0;
9565 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9566 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9567 if (unlikely(env->singlestep_enabled))
9568 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9569 #if defined (DO_SINGLE_STEP) && 0
9570 /* Single step trace mode */
9571 msr_se = 1;
9572 #endif
9573 num_insns = 0;
9574 max_insns = tb->cflags & CF_COUNT_MASK;
9575 if (max_insns == 0)
9576 max_insns = CF_COUNT_MASK;
9577
9578 gen_tb_start();
9579 /* Set env in case of segfault during code fetch */
9580 while (ctx.exception == POWERPC_EXCP_NONE
9581 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9582 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9583 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9584 if (bp->pc == ctx.nip) {
9585 gen_debug_exception(ctxp);
9586 break;
9587 }
9588 }
9589 }
9590 if (unlikely(search_pc)) {
9591 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9592 if (lj < j) {
9593 lj++;
9594 while (lj < j)
9595 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9596 }
9597 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9598 tcg_ctx.gen_opc_instr_start[lj] = 1;
9599 tcg_ctx.gen_opc_icount[lj] = num_insns;
9600 }
9601 LOG_DISAS("----------------\n");
9602 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9603 ctx.nip, ctx.mem_idx, (int)msr_ir);
9604 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9605 gen_io_start();
9606 if (unlikely(ctx.le_mode)) {
9607 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9608 } else {
9609 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9610 }
9611 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9612 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9613 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9614 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9615 tcg_gen_debug_insn_start(ctx.nip);
9616 }
9617 ctx.nip += 4;
9618 table = env->opcodes;
9619 num_insns++;
9620 handler = table[opc1(ctx.opcode)];
9621 if (is_indirect_opcode(handler)) {
9622 table = ind_table(handler);
9623 handler = table[opc2(ctx.opcode)];
9624 if (is_indirect_opcode(handler)) {
9625 table = ind_table(handler);
9626 handler = table[opc3(ctx.opcode)];
9627 }
9628 }
9629 /* Is opcode *REALLY* valid ? */
9630 if (unlikely(handler->handler == &gen_invalid)) {
9631 if (qemu_log_enabled()) {
9632 qemu_log("invalid/unsupported opcode: "
9633 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9634 opc1(ctx.opcode), opc2(ctx.opcode),
9635 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9636 }
9637 } else {
9638 uint32_t inval;
9639
9640 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9641 inval = handler->inval2;
9642 } else {
9643 inval = handler->inval1;
9644 }
9645
9646 if (unlikely((ctx.opcode & inval) != 0)) {
9647 if (qemu_log_enabled()) {
9648 qemu_log("invalid bits: %08x for opcode: "
9649 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9650 ctx.opcode & inval, opc1(ctx.opcode),
9651 opc2(ctx.opcode), opc3(ctx.opcode),
9652 ctx.opcode, ctx.nip - 4);
9653 }
9654 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9655 break;
9656 }
9657 }
9658 (*(handler->handler))(&ctx);
9659 #if defined(DO_PPC_STATISTICS)
9660 handler->count++;
9661 #endif
9662 /* Check trace mode exceptions */
9663 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9664 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9665 ctx.exception != POWERPC_SYSCALL &&
9666 ctx.exception != POWERPC_EXCP_TRAP &&
9667 ctx.exception != POWERPC_EXCP_BRANCH)) {
9668 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9669 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9670 (env->singlestep_enabled) ||
9671 singlestep ||
9672 num_insns >= max_insns)) {
9673 /* if we reach a page boundary or are single stepping, stop
9674 * generation
9675 */
9676 break;
9677 }
9678 }
9679 if (tb->cflags & CF_LAST_IO)
9680 gen_io_end();
9681 if (ctx.exception == POWERPC_EXCP_NONE) {
9682 gen_goto_tb(&ctx, 0, ctx.nip);
9683 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9684 if (unlikely(env->singlestep_enabled)) {
9685 gen_debug_exception(ctxp);
9686 }
9687 /* Generate the return instruction */
9688 tcg_gen_exit_tb(0);
9689 }
9690 gen_tb_end(tb, num_insns);
9691 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9692 if (unlikely(search_pc)) {
9693 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9694 lj++;
9695 while (lj <= j)
9696 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9697 } else {
9698 tb->size = ctx.nip - pc_start;
9699 tb->icount = num_insns;
9700 }
9701 #if defined(DEBUG_DISAS)
9702 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9703 int flags;
9704 flags = env->bfd_mach;
9705 flags |= ctx.le_mode << 16;
9706 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9707 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9708 qemu_log("\n");
9709 }
9710 #endif
9711 }
9712
9713 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9714 {
9715 gen_intermediate_code_internal(env, tb, 0);
9716 }
9717
9718 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9719 {
9720 gen_intermediate_code_internal(env, tb, 1);
9721 }
9722
9723 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9724 {
9725 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9726 }
Qemu copy for testing