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1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 struct opc_handler_t {
208 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
209 uint32_t inval1;
210 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
211 uint32_t inval2;
212 /* instruction type */
213 uint64_t type;
214 /* extended instruction type */
215 uint64_t type2;
216 /* handler */
217 void (*handler)(DisasContext *ctx);
218 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
219 const char *oname;
220 #endif
221 #if defined(DO_PPC_STATISTICS)
222 uint64_t count;
223 #endif
224 };
225
226 static inline void gen_reset_fpstatus(void)
227 {
228 gen_helper_reset_fpstatus(cpu_env);
229 }
230
231 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
232 {
233 TCGv_i32 t0 = tcg_temp_new_i32();
234
235 if (set_fprf != 0) {
236 /* This case might be optimized later */
237 tcg_gen_movi_i32(t0, 1);
238 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
239 if (unlikely(set_rc)) {
240 tcg_gen_mov_i32(cpu_crf[1], t0);
241 }
242 gen_helper_float_check_status(cpu_env);
243 } else if (unlikely(set_rc)) {
244 /* We always need to compute fpcc */
245 tcg_gen_movi_i32(t0, 0);
246 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249
250 tcg_temp_free_i32(t0);
251 }
252
253 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
254 {
255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
259 }
260
261 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
262 {
263 #if defined(TARGET_PPC64)
264 if (ctx->sf_mode)
265 tcg_gen_movi_tl(cpu_nip, nip);
266 else
267 #endif
268 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
269 }
270
271 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
272 {
273 TCGv_i32 t0, t1;
274 if (ctx->exception == POWERPC_EXCP_NONE) {
275 gen_update_nip(ctx, ctx->nip);
276 }
277 t0 = tcg_const_i32(excp);
278 t1 = tcg_const_i32(error);
279 gen_helper_raise_exception_err(cpu_env, t0, t1);
280 tcg_temp_free_i32(t0);
281 tcg_temp_free_i32(t1);
282 ctx->exception = (excp);
283 }
284
285 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
286 {
287 TCGv_i32 t0;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 gen_helper_raise_exception(cpu_env, t0);
293 tcg_temp_free_i32(t0);
294 ctx->exception = (excp);
295 }
296
297 static inline void gen_debug_exception(DisasContext *ctx)
298 {
299 TCGv_i32 t0;
300
301 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
302 (ctx->exception != POWERPC_EXCP_SYNC)) {
303 gen_update_nip(ctx, ctx->nip);
304 }
305 t0 = tcg_const_i32(EXCP_DEBUG);
306 gen_helper_raise_exception(cpu_env, t0);
307 tcg_temp_free_i32(t0);
308 }
309
310 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
311 {
312 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
313 }
314
315 /* Stop translation */
316 static inline void gen_stop_exception(DisasContext *ctx)
317 {
318 gen_update_nip(ctx, ctx->nip);
319 ctx->exception = POWERPC_EXCP_STOP;
320 }
321
322 /* No need to update nip here, as execution flow will change */
323 static inline void gen_sync_exception(DisasContext *ctx)
324 {
325 ctx->exception = POWERPC_EXCP_SYNC;
326 }
327
328 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
333
334 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
335 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
336
337 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
338 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
339
340 typedef struct opcode_t {
341 unsigned char opc1, opc2, opc3;
342 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
343 unsigned char pad[5];
344 #else
345 unsigned char pad[1];
346 #endif
347 opc_handler_t handler;
348 const char *oname;
349 } opcode_t;
350
351 /*****************************************************************************/
352 /*** Instruction decoding ***/
353 #define EXTRACT_HELPER(name, shift, nb) \
354 static inline uint32_t name(uint32_t opcode) \
355 { \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
357 }
358
359 #define EXTRACT_SHELPER(name, shift, nb) \
360 static inline int32_t name(uint32_t opcode) \
361 { \
362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
363 }
364
365 /* Opcode part 1 */
366 EXTRACT_HELPER(opc1, 26, 6);
367 /* Opcode part 2 */
368 EXTRACT_HELPER(opc2, 1, 5);
369 /* Opcode part 3 */
370 EXTRACT_HELPER(opc3, 6, 5);
371 /* Update Cr0 flags */
372 EXTRACT_HELPER(Rc, 0, 1);
373 /* Destination */
374 EXTRACT_HELPER(rD, 21, 5);
375 /* Source */
376 EXTRACT_HELPER(rS, 21, 5);
377 /* First operand */
378 EXTRACT_HELPER(rA, 16, 5);
379 /* Second operand */
380 EXTRACT_HELPER(rB, 11, 5);
381 /* Third operand */
382 EXTRACT_HELPER(rC, 6, 5);
383 /*** Get CRn ***/
384 EXTRACT_HELPER(crfD, 23, 3);
385 EXTRACT_HELPER(crfS, 18, 3);
386 EXTRACT_HELPER(crbD, 21, 5);
387 EXTRACT_HELPER(crbA, 16, 5);
388 EXTRACT_HELPER(crbB, 11, 5);
389 /* SPR / TBL */
390 EXTRACT_HELPER(_SPR, 11, 10);
391 static inline uint32_t SPR(uint32_t opcode)
392 {
393 uint32_t sprn = _SPR(opcode);
394
395 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
396 }
397 /*** Get constants ***/
398 EXTRACT_HELPER(IMM, 12, 8);
399 /* 16 bits signed immediate value */
400 EXTRACT_SHELPER(SIMM, 0, 16);
401 /* 16 bits unsigned immediate value */
402 EXTRACT_HELPER(UIMM, 0, 16);
403 /* 5 bits signed immediate value */
404 EXTRACT_HELPER(SIMM5, 16, 5);
405 /* 5 bits signed immediate value */
406 EXTRACT_HELPER(UIMM5, 16, 5);
407 /* Bit count */
408 EXTRACT_HELPER(NB, 11, 5);
409 /* Shift count */
410 EXTRACT_HELPER(SH, 11, 5);
411 /* Vector shift count */
412 EXTRACT_HELPER(VSH, 6, 4);
413 /* Mask start */
414 EXTRACT_HELPER(MB, 6, 5);
415 /* Mask end */
416 EXTRACT_HELPER(ME, 1, 5);
417 /* Trap operand */
418 EXTRACT_HELPER(TO, 21, 5);
419
420 EXTRACT_HELPER(CRM, 12, 8);
421 EXTRACT_HELPER(FM, 17, 8);
422 EXTRACT_HELPER(SR, 16, 4);
423 EXTRACT_HELPER(FPIMM, 12, 4);
424
425 /*** Jump target decoding ***/
426 /* Displacement */
427 EXTRACT_SHELPER(d, 0, 16);
428 /* Immediate address */
429 static inline target_ulong LI(uint32_t opcode)
430 {
431 return (opcode >> 0) & 0x03FFFFFC;
432 }
433
434 static inline uint32_t BD(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0xFFFC;
437 }
438
439 EXTRACT_HELPER(BO, 21, 5);
440 EXTRACT_HELPER(BI, 16, 5);
441 /* Absolute/relative address */
442 EXTRACT_HELPER(AA, 1, 1);
443 /* Link */
444 EXTRACT_HELPER(LK, 0, 1);
445
446 /* Create a mask between <start> and <end> bits */
447 static inline target_ulong MASK(uint32_t start, uint32_t end)
448 {
449 target_ulong ret;
450
451 #if defined(TARGET_PPC64)
452 if (likely(start == 0)) {
453 ret = UINT64_MAX << (63 - end);
454 } else if (likely(end == 63)) {
455 ret = UINT64_MAX >> start;
456 }
457 #else
458 if (likely(start == 0)) {
459 ret = UINT32_MAX << (31 - end);
460 } else if (likely(end == 31)) {
461 ret = UINT32_MAX >> start;
462 }
463 #endif
464 else {
465 ret = (((target_ulong)(-1ULL)) >> (start)) ^
466 (((target_ulong)(-1ULL) >> (end)) >> 1);
467 if (unlikely(start > end))
468 return ~ret;
469 }
470
471 return ret;
472 }
473
474 /*****************************************************************************/
475 /* PowerPC instructions table */
476
477 #if defined(DO_PPC_STATISTICS)
478 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
479 { \
480 .opc1 = op1, \
481 .opc2 = op2, \
482 .opc3 = op3, \
483 .pad = { 0, }, \
484 .handler = { \
485 .inval1 = invl, \
486 .type = _typ, \
487 .type2 = _typ2, \
488 .handler = &gen_##name, \
489 .oname = stringify(name), \
490 }, \
491 .oname = stringify(name), \
492 }
493 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
494 { \
495 .opc1 = op1, \
496 .opc2 = op2, \
497 .opc3 = op3, \
498 .pad = { 0, }, \
499 .handler = { \
500 .inval1 = invl1, \
501 .inval2 = invl2, \
502 .type = _typ, \
503 .type2 = _typ2, \
504 .handler = &gen_##name, \
505 .oname = stringify(name), \
506 }, \
507 .oname = stringify(name), \
508 }
509 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
510 { \
511 .opc1 = op1, \
512 .opc2 = op2, \
513 .opc3 = op3, \
514 .pad = { 0, }, \
515 .handler = { \
516 .inval1 = invl, \
517 .type = _typ, \
518 .type2 = _typ2, \
519 .handler = &gen_##name, \
520 .oname = onam, \
521 }, \
522 .oname = onam, \
523 }
524 #else
525 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
526 { \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl, \
533 .type = _typ, \
534 .type2 = _typ2, \
535 .handler = &gen_##name, \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
548 .type = _typ, \
549 .type2 = _typ2, \
550 .handler = &gen_##name, \
551 }, \
552 .oname = stringify(name), \
553 }
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555 { \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 }, \
566 .oname = onam, \
567 }
568 #endif
569
570 /* SPR load/store helpers */
571 static inline void gen_load_spr(TCGv t, int reg)
572 {
573 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
574 }
575
576 static inline void gen_store_spr(int reg, TCGv t)
577 {
578 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 /* Invalid instruction */
582 static void gen_invalid(DisasContext *ctx)
583 {
584 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
585 }
586
587 static opc_handler_t invalid_handler = {
588 .inval1 = 0xFFFFFFFF,
589 .inval2 = 0xFFFFFFFF,
590 .type = PPC_NONE,
591 .type2 = PPC_NONE,
592 .handler = gen_invalid,
593 };
594
595 /*** Integer comparison ***/
596
597 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
598 {
599 TCGv t0 = tcg_temp_new();
600 TCGv_i32 t1 = tcg_temp_new_i32();
601
602 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
603
604 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
605 tcg_gen_trunc_tl_i32(t1, t0);
606 tcg_gen_shli_i32(t1, t1, CRF_LT);
607 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_GT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_EQ);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_temp_free(t0);
620 tcg_temp_free_i32(t1);
621 }
622
623 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
624 {
625 TCGv t0 = tcg_const_tl(arg1);
626 gen_op_cmp(arg0, t0, s, crf);
627 tcg_temp_free(t0);
628 }
629
630 #if defined(TARGET_PPC64)
631 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
632 {
633 TCGv t0, t1;
634 t0 = tcg_temp_new();
635 t1 = tcg_temp_new();
636 if (s) {
637 tcg_gen_ext32s_tl(t0, arg0);
638 tcg_gen_ext32s_tl(t1, arg1);
639 } else {
640 tcg_gen_ext32u_tl(t0, arg0);
641 tcg_gen_ext32u_tl(t1, arg1);
642 }
643 gen_op_cmp(t0, t1, s, crf);
644 tcg_temp_free(t1);
645 tcg_temp_free(t0);
646 }
647
648 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
649 {
650 TCGv t0 = tcg_const_tl(arg1);
651 gen_op_cmp32(arg0, t0, s, crf);
652 tcg_temp_free(t0);
653 }
654 #endif
655
656 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
657 {
658 #if defined(TARGET_PPC64)
659 if (!(ctx->sf_mode))
660 gen_op_cmpi32(reg, 0, 1, 0);
661 else
662 #endif
663 gen_op_cmpi(reg, 0, 1, 0);
664 }
665
666 /* cmp */
667 static void gen_cmp(DisasContext *ctx)
668 {
669 #if defined(TARGET_PPC64)
670 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
671 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 else
674 #endif
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678
679 /* cmpi */
680 static void gen_cmpi(DisasContext *ctx)
681 {
682 #if defined(TARGET_PPC64)
683 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 else
687 #endif
688 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
689 1, crfD(ctx->opcode));
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 #if defined(TARGET_PPC64)
696 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 else
700 #endif
701 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
702 0, crfD(ctx->opcode));
703 }
704
705 /* cmpli */
706 static void gen_cmpli(DisasContext *ctx)
707 {
708 #if defined(TARGET_PPC64)
709 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
710 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712 else
713 #endif
714 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
715 0, crfD(ctx->opcode));
716 }
717
718 /* isel (PowerPC 2.03 specification) */
719 static void gen_isel(DisasContext *ctx)
720 {
721 int l1, l2;
722 uint32_t bi = rC(ctx->opcode);
723 uint32_t mask;
724 TCGv_i32 t0;
725
726 l1 = gen_new_label();
727 l2 = gen_new_label();
728
729 mask = 1 << (3 - (bi & 0x03));
730 t0 = tcg_temp_new_i32();
731 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
732 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
733 if (rA(ctx->opcode) == 0)
734 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
735 else
736 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
737 tcg_gen_br(l2);
738 gen_set_label(l1);
739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
740 gen_set_label(l2);
741 tcg_temp_free_i32(t0);
742 }
743
744 /*** Integer arithmetic ***/
745
746 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
747 TCGv arg1, TCGv arg2, int sub)
748 {
749 TCGv t0 = tcg_temp_new();
750
751 tcg_gen_xor_tl(cpu_ov, arg0, arg1);
752 tcg_gen_xor_tl(t0, arg1, arg2);
753 if (sub) {
754 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
755 } else {
756 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
757 }
758 tcg_temp_free(t0);
759 #if defined(TARGET_PPC64)
760 if (!ctx->sf_mode) {
761 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
762 }
763 #endif
764 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
765 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
766 }
767
768 /* Common add function */
769 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
770 TCGv arg2, bool add_ca, bool compute_ca,
771 bool compute_ov, bool compute_rc0)
772 {
773 TCGv t0 = ret;
774
775 if (((compute_ca && add_ca) || compute_ov)
776 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
777 t0 = tcg_temp_new();
778 }
779
780 if (compute_ca) {
781 TCGv zero = tcg_const_tl(0);
782 if (add_ca) {
783 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
784 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
785 } else {
786 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
787 }
788 tcg_temp_free(zero);
789 } else {
790 tcg_gen_add_tl(t0, arg1, arg2);
791 if (add_ca) {
792 tcg_gen_add_tl(t0, t0, cpu_ca);
793 }
794 }
795
796 if (compute_ov) {
797 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
798 }
799 if (unlikely(compute_rc0)) {
800 gen_set_Rc0(ctx, t0);
801 }
802
803 if (!TCGV_EQUAL(t0, ret)) {
804 tcg_gen_mov_tl(ret, t0);
805 tcg_temp_free(t0);
806 }
807 }
808 /* Add functions with two operands */
809 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
810 static void glue(gen_, name)(DisasContext *ctx) \
811 { \
812 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
813 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
814 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
815 }
816 /* Add functions with one operand and one immediate */
817 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
818 add_ca, compute_ca, compute_ov) \
819 static void glue(gen_, name)(DisasContext *ctx) \
820 { \
821 TCGv t0 = tcg_const_tl(const_val); \
822 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
823 cpu_gpr[rA(ctx->opcode)], t0, \
824 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
825 tcg_temp_free(t0); \
826 }
827
828 /* add add. addo addo. */
829 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
830 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
831 /* addc addc. addco addco. */
832 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
833 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
834 /* adde adde. addeo addeo. */
835 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
836 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
837 /* addme addme. addmeo addmeo. */
838 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
839 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
840 /* addze addze. addzeo addzeo.*/
841 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
842 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
843 /* addi */
844 static void gen_addi(DisasContext *ctx)
845 {
846 target_long simm = SIMM(ctx->opcode);
847
848 if (rA(ctx->opcode) == 0) {
849 /* li case */
850 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
851 } else {
852 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
853 cpu_gpr[rA(ctx->opcode)], simm);
854 }
855 }
856 /* addic addic.*/
857 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
858 {
859 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
860 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
861 c, 0, 1, 0, compute_rc0);
862 tcg_temp_free(c);
863 }
864
865 static void gen_addic(DisasContext *ctx)
866 {
867 gen_op_addic(ctx, 0);
868 }
869
870 static void gen_addic_(DisasContext *ctx)
871 {
872 gen_op_addic(ctx, 1);
873 }
874
875 /* addis */
876 static void gen_addis(DisasContext *ctx)
877 {
878 target_long simm = SIMM(ctx->opcode);
879
880 if (rA(ctx->opcode) == 0) {
881 /* lis case */
882 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
883 } else {
884 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
885 cpu_gpr[rA(ctx->opcode)], simm << 16);
886 }
887 }
888
889 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
890 TCGv arg2, int sign, int compute_ov)
891 {
892 int l1 = gen_new_label();
893 int l2 = gen_new_label();
894 TCGv_i32 t0 = tcg_temp_local_new_i32();
895 TCGv_i32 t1 = tcg_temp_local_new_i32();
896
897 tcg_gen_trunc_tl_i32(t0, arg1);
898 tcg_gen_trunc_tl_i32(t1, arg2);
899 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
900 if (sign) {
901 int l3 = gen_new_label();
902 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
903 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
904 gen_set_label(l3);
905 tcg_gen_div_i32(t0, t0, t1);
906 } else {
907 tcg_gen_divu_i32(t0, t0, t1);
908 }
909 if (compute_ov) {
910 tcg_gen_movi_tl(cpu_ov, 0);
911 }
912 tcg_gen_br(l2);
913 gen_set_label(l1);
914 if (sign) {
915 tcg_gen_sari_i32(t0, t0, 31);
916 } else {
917 tcg_gen_movi_i32(t0, 0);
918 }
919 if (compute_ov) {
920 tcg_gen_movi_tl(cpu_ov, 1);
921 tcg_gen_movi_tl(cpu_so, 1);
922 }
923 gen_set_label(l2);
924 tcg_gen_extu_i32_tl(ret, t0);
925 tcg_temp_free_i32(t0);
926 tcg_temp_free_i32(t1);
927 if (unlikely(Rc(ctx->opcode) != 0))
928 gen_set_Rc0(ctx, ret);
929 }
930 /* Div functions */
931 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
932 static void glue(gen_, name)(DisasContext *ctx) \
933 { \
934 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
935 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
936 sign, compute_ov); \
937 }
938 /* divwu divwu. divwuo divwuo. */
939 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
940 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
941 /* divw divw. divwo divwo. */
942 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
943 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
944 #if defined(TARGET_PPC64)
945 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
946 TCGv arg2, int sign, int compute_ov)
947 {
948 int l1 = gen_new_label();
949 int l2 = gen_new_label();
950
951 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
952 if (sign) {
953 int l3 = gen_new_label();
954 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
955 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
956 gen_set_label(l3);
957 tcg_gen_div_i64(ret, arg1, arg2);
958 } else {
959 tcg_gen_divu_i64(ret, arg1, arg2);
960 }
961 if (compute_ov) {
962 tcg_gen_movi_tl(cpu_ov, 0);
963 }
964 tcg_gen_br(l2);
965 gen_set_label(l1);
966 if (sign) {
967 tcg_gen_sari_i64(ret, arg1, 63);
968 } else {
969 tcg_gen_movi_i64(ret, 0);
970 }
971 if (compute_ov) {
972 tcg_gen_movi_tl(cpu_ov, 1);
973 tcg_gen_movi_tl(cpu_so, 1);
974 }
975 gen_set_label(l2);
976 if (unlikely(Rc(ctx->opcode) != 0))
977 gen_set_Rc0(ctx, ret);
978 }
979 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
980 static void glue(gen_, name)(DisasContext *ctx) \
981 { \
982 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
984 sign, compute_ov); \
985 }
986 /* divwu divwu. divwuo divwuo. */
987 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
988 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
989 /* divw divw. divwo divwo. */
990 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
991 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
992 #endif
993
994 /* mulhw mulhw. */
995 static void gen_mulhw(DisasContext *ctx)
996 {
997 TCGv_i32 t0 = tcg_temp_new_i32();
998 TCGv_i32 t1 = tcg_temp_new_i32();
999
1000 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1001 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1002 tcg_gen_muls2_i32(t0, t1, t0, t1);
1003 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1004 tcg_temp_free_i32(t0);
1005 tcg_temp_free_i32(t1);
1006 if (unlikely(Rc(ctx->opcode) != 0))
1007 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1008 }
1009
1010 /* mulhwu mulhwu. */
1011 static void gen_mulhwu(DisasContext *ctx)
1012 {
1013 TCGv_i32 t0 = tcg_temp_new_i32();
1014 TCGv_i32 t1 = tcg_temp_new_i32();
1015
1016 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1017 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1018 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1019 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1020 tcg_temp_free_i32(t0);
1021 tcg_temp_free_i32(t1);
1022 if (unlikely(Rc(ctx->opcode) != 0))
1023 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1024 }
1025
1026 /* mullw mullw. */
1027 static void gen_mullw(DisasContext *ctx)
1028 {
1029 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1030 cpu_gpr[rB(ctx->opcode)]);
1031 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1032 if (unlikely(Rc(ctx->opcode) != 0))
1033 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1034 }
1035
1036 /* mullwo mullwo. */
1037 static void gen_mullwo(DisasContext *ctx)
1038 {
1039 TCGv_i32 t0 = tcg_temp_new_i32();
1040 TCGv_i32 t1 = tcg_temp_new_i32();
1041
1042 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1043 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1044 tcg_gen_muls2_i32(t0, t1, t0, t1);
1045 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1046
1047 tcg_gen_sari_i32(t0, t0, 31);
1048 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1049 tcg_gen_extu_i32_tl(cpu_ov, t0);
1050 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1051
1052 tcg_temp_free_i32(t0);
1053 tcg_temp_free_i32(t1);
1054 if (unlikely(Rc(ctx->opcode) != 0))
1055 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1056 }
1057
1058 /* mulli */
1059 static void gen_mulli(DisasContext *ctx)
1060 {
1061 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1062 SIMM(ctx->opcode));
1063 }
1064
1065 #if defined(TARGET_PPC64)
1066 /* mulhd mulhd. */
1067 static void gen_mulhd(DisasContext *ctx)
1068 {
1069 TCGv lo = tcg_temp_new();
1070 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1071 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1072 tcg_temp_free(lo);
1073 if (unlikely(Rc(ctx->opcode) != 0)) {
1074 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1075 }
1076 }
1077
1078 /* mulhdu mulhdu. */
1079 static void gen_mulhdu(DisasContext *ctx)
1080 {
1081 TCGv lo = tcg_temp_new();
1082 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1083 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1084 tcg_temp_free(lo);
1085 if (unlikely(Rc(ctx->opcode) != 0)) {
1086 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1087 }
1088 }
1089
1090 /* mulld mulld. */
1091 static void gen_mulld(DisasContext *ctx)
1092 {
1093 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1094 cpu_gpr[rB(ctx->opcode)]);
1095 if (unlikely(Rc(ctx->opcode) != 0))
1096 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1097 }
1098
1099 /* mulldo mulldo. */
1100 static void gen_mulldo(DisasContext *ctx)
1101 {
1102 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1103 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1104 if (unlikely(Rc(ctx->opcode) != 0)) {
1105 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1106 }
1107 }
1108 #endif
1109
1110 /* Common subf function */
1111 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1112 TCGv arg2, bool add_ca, bool compute_ca,
1113 bool compute_ov, bool compute_rc0)
1114 {
1115 TCGv t0 = ret;
1116
1117 if (((add_ca && compute_ca) || compute_ov)
1118 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
1119 t0 = tcg_temp_new();
1120 }
1121
1122 if (add_ca) {
1123 /* dest = ~arg1 + arg2 + ca = arg2 - arg1 + ca - 1. */
1124 if (compute_ca) {
1125 TCGv zero;
1126 tcg_gen_subi_tl(cpu_ca, cpu_ca, 1);
1127 zero = tcg_const_tl(0);
1128 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1129 tcg_gen_sub2_tl(t0, cpu_ca, t0, cpu_ca, arg1, zero);
1130 tcg_temp_free(zero);
1131 } else {
1132 tcg_gen_sub_tl(t0, arg2, arg1);
1133 tcg_gen_add_tl(t0, t0, cpu_ca);
1134 tcg_gen_subi_tl(t0, t0, 1);
1135 }
1136 } else {
1137 if (compute_ca) {
1138 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1139 }
1140 tcg_gen_sub_tl(t0, arg2, arg1);
1141 }
1142
1143 if (compute_ov) {
1144 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1145 }
1146 if (unlikely(compute_rc0)) {
1147 gen_set_Rc0(ctx, t0);
1148 }
1149
1150 if (!TCGV_EQUAL(t0, ret)) {
1151 tcg_gen_mov_tl(ret, t0);
1152 tcg_temp_free(t0);
1153 }
1154 }
1155 /* Sub functions with Two operands functions */
1156 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1157 static void glue(gen_, name)(DisasContext *ctx) \
1158 { \
1159 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1161 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1162 }
1163 /* Sub functions with one operand and one immediate */
1164 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1165 add_ca, compute_ca, compute_ov) \
1166 static void glue(gen_, name)(DisasContext *ctx) \
1167 { \
1168 TCGv t0 = tcg_const_tl(const_val); \
1169 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1170 cpu_gpr[rA(ctx->opcode)], t0, \
1171 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1172 tcg_temp_free(t0); \
1173 }
1174 /* subf subf. subfo subfo. */
1175 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1176 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1177 /* subfc subfc. subfco subfco. */
1178 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1179 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1180 /* subfe subfe. subfeo subfo. */
1181 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1182 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1183 /* subfme subfme. subfmeo subfmeo. */
1184 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1185 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1186 /* subfze subfze. subfzeo subfzeo.*/
1187 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1188 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1189
1190 /* subfic */
1191 static void gen_subfic(DisasContext *ctx)
1192 {
1193 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1194 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1195 c, 0, 1, 0, 0);
1196 tcg_temp_free(c);
1197 }
1198
1199 /* neg neg. nego nego. */
1200 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1201 {
1202 TCGv zero = tcg_const_tl(0);
1203 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1204 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1205 tcg_temp_free(zero);
1206 }
1207
1208 static void gen_neg(DisasContext *ctx)
1209 {
1210 gen_op_arith_neg(ctx, 0);
1211 }
1212
1213 static void gen_nego(DisasContext *ctx)
1214 {
1215 gen_op_arith_neg(ctx, 1);
1216 }
1217
1218 /*** Integer logical ***/
1219 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1220 static void glue(gen_, name)(DisasContext *ctx) \
1221 { \
1222 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1223 cpu_gpr[rB(ctx->opcode)]); \
1224 if (unlikely(Rc(ctx->opcode) != 0)) \
1225 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1226 }
1227
1228 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1229 static void glue(gen_, name)(DisasContext *ctx) \
1230 { \
1231 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1232 if (unlikely(Rc(ctx->opcode) != 0)) \
1233 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1234 }
1235
1236 /* and & and. */
1237 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1238 /* andc & andc. */
1239 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1240
1241 /* andi. */
1242 static void gen_andi_(DisasContext *ctx)
1243 {
1244 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1245 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1246 }
1247
1248 /* andis. */
1249 static void gen_andis_(DisasContext *ctx)
1250 {
1251 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1252 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1253 }
1254
1255 /* cntlzw */
1256 static void gen_cntlzw(DisasContext *ctx)
1257 {
1258 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1259 if (unlikely(Rc(ctx->opcode) != 0))
1260 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1261 }
1262 /* eqv & eqv. */
1263 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1264 /* extsb & extsb. */
1265 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1266 /* extsh & extsh. */
1267 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1268 /* nand & nand. */
1269 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1270 /* nor & nor. */
1271 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1272
1273 /* or & or. */
1274 static void gen_or(DisasContext *ctx)
1275 {
1276 int rs, ra, rb;
1277
1278 rs = rS(ctx->opcode);
1279 ra = rA(ctx->opcode);
1280 rb = rB(ctx->opcode);
1281 /* Optimisation for mr. ri case */
1282 if (rs != ra || rs != rb) {
1283 if (rs != rb)
1284 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1285 else
1286 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1287 if (unlikely(Rc(ctx->opcode) != 0))
1288 gen_set_Rc0(ctx, cpu_gpr[ra]);
1289 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1290 gen_set_Rc0(ctx, cpu_gpr[rs]);
1291 #if defined(TARGET_PPC64)
1292 } else {
1293 int prio = 0;
1294
1295 switch (rs) {
1296 case 1:
1297 /* Set process priority to low */
1298 prio = 2;
1299 break;
1300 case 6:
1301 /* Set process priority to medium-low */
1302 prio = 3;
1303 break;
1304 case 2:
1305 /* Set process priority to normal */
1306 prio = 4;
1307 break;
1308 #if !defined(CONFIG_USER_ONLY)
1309 case 31:
1310 if (ctx->mem_idx > 0) {
1311 /* Set process priority to very low */
1312 prio = 1;
1313 }
1314 break;
1315 case 5:
1316 if (ctx->mem_idx > 0) {
1317 /* Set process priority to medium-hight */
1318 prio = 5;
1319 }
1320 break;
1321 case 3:
1322 if (ctx->mem_idx > 0) {
1323 /* Set process priority to high */
1324 prio = 6;
1325 }
1326 break;
1327 case 7:
1328 if (ctx->mem_idx > 1) {
1329 /* Set process priority to very high */
1330 prio = 7;
1331 }
1332 break;
1333 #endif
1334 default:
1335 /* nop */
1336 break;
1337 }
1338 if (prio) {
1339 TCGv t0 = tcg_temp_new();
1340 gen_load_spr(t0, SPR_PPR);
1341 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1342 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1343 gen_store_spr(SPR_PPR, t0);
1344 tcg_temp_free(t0);
1345 }
1346 #endif
1347 }
1348 }
1349 /* orc & orc. */
1350 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1351
1352 /* xor & xor. */
1353 static void gen_xor(DisasContext *ctx)
1354 {
1355 /* Optimisation for "set to zero" case */
1356 if (rS(ctx->opcode) != rB(ctx->opcode))
1357 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1358 else
1359 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1360 if (unlikely(Rc(ctx->opcode) != 0))
1361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1362 }
1363
1364 /* ori */
1365 static void gen_ori(DisasContext *ctx)
1366 {
1367 target_ulong uimm = UIMM(ctx->opcode);
1368
1369 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1370 /* NOP */
1371 /* XXX: should handle special NOPs for POWER series */
1372 return;
1373 }
1374 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1375 }
1376
1377 /* oris */
1378 static void gen_oris(DisasContext *ctx)
1379 {
1380 target_ulong uimm = UIMM(ctx->opcode);
1381
1382 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1383 /* NOP */
1384 return;
1385 }
1386 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1387 }
1388
1389 /* xori */
1390 static void gen_xori(DisasContext *ctx)
1391 {
1392 target_ulong uimm = UIMM(ctx->opcode);
1393
1394 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1395 /* NOP */
1396 return;
1397 }
1398 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1399 }
1400
1401 /* xoris */
1402 static void gen_xoris(DisasContext *ctx)
1403 {
1404 target_ulong uimm = UIMM(ctx->opcode);
1405
1406 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1407 /* NOP */
1408 return;
1409 }
1410 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1411 }
1412
1413 /* popcntb : PowerPC 2.03 specification */
1414 static void gen_popcntb(DisasContext *ctx)
1415 {
1416 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1417 }
1418
1419 static void gen_popcntw(DisasContext *ctx)
1420 {
1421 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1422 }
1423
1424 #if defined(TARGET_PPC64)
1425 /* popcntd: PowerPC 2.06 specification */
1426 static void gen_popcntd(DisasContext *ctx)
1427 {
1428 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1429 }
1430 #endif
1431
1432 #if defined(TARGET_PPC64)
1433 /* extsw & extsw. */
1434 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1435
1436 /* cntlzd */
1437 static void gen_cntlzd(DisasContext *ctx)
1438 {
1439 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1440 if (unlikely(Rc(ctx->opcode) != 0))
1441 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1442 }
1443 #endif
1444
1445 /*** Integer rotate ***/
1446
1447 /* rlwimi & rlwimi. */
1448 static void gen_rlwimi(DisasContext *ctx)
1449 {
1450 uint32_t mb, me, sh;
1451
1452 mb = MB(ctx->opcode);
1453 me = ME(ctx->opcode);
1454 sh = SH(ctx->opcode);
1455 if (likely(sh == 0 && mb == 0 && me == 31)) {
1456 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1457 } else {
1458 target_ulong mask;
1459 TCGv t1;
1460 TCGv t0 = tcg_temp_new();
1461 #if defined(TARGET_PPC64)
1462 TCGv_i32 t2 = tcg_temp_new_i32();
1463 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1464 tcg_gen_rotli_i32(t2, t2, sh);
1465 tcg_gen_extu_i32_i64(t0, t2);
1466 tcg_temp_free_i32(t2);
1467 #else
1468 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1469 #endif
1470 #if defined(TARGET_PPC64)
1471 mb += 32;
1472 me += 32;
1473 #endif
1474 mask = MASK(mb, me);
1475 t1 = tcg_temp_new();
1476 tcg_gen_andi_tl(t0, t0, mask);
1477 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1478 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1479 tcg_temp_free(t0);
1480 tcg_temp_free(t1);
1481 }
1482 if (unlikely(Rc(ctx->opcode) != 0))
1483 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1484 }
1485
1486 /* rlwinm & rlwinm. */
1487 static void gen_rlwinm(DisasContext *ctx)
1488 {
1489 uint32_t mb, me, sh;
1490
1491 sh = SH(ctx->opcode);
1492 mb = MB(ctx->opcode);
1493 me = ME(ctx->opcode);
1494
1495 if (likely(mb == 0 && me == (31 - sh))) {
1496 if (likely(sh == 0)) {
1497 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1498 } else {
1499 TCGv t0 = tcg_temp_new();
1500 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1501 tcg_gen_shli_tl(t0, t0, sh);
1502 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1503 tcg_temp_free(t0);
1504 }
1505 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1506 TCGv t0 = tcg_temp_new();
1507 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1508 tcg_gen_shri_tl(t0, t0, mb);
1509 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1510 tcg_temp_free(t0);
1511 } else {
1512 TCGv t0 = tcg_temp_new();
1513 #if defined(TARGET_PPC64)
1514 TCGv_i32 t1 = tcg_temp_new_i32();
1515 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1516 tcg_gen_rotli_i32(t1, t1, sh);
1517 tcg_gen_extu_i32_i64(t0, t1);
1518 tcg_temp_free_i32(t1);
1519 #else
1520 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1521 #endif
1522 #if defined(TARGET_PPC64)
1523 mb += 32;
1524 me += 32;
1525 #endif
1526 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1527 tcg_temp_free(t0);
1528 }
1529 if (unlikely(Rc(ctx->opcode) != 0))
1530 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1531 }
1532
1533 /* rlwnm & rlwnm. */
1534 static void gen_rlwnm(DisasContext *ctx)
1535 {
1536 uint32_t mb, me;
1537 TCGv t0;
1538 #if defined(TARGET_PPC64)
1539 TCGv_i32 t1, t2;
1540 #endif
1541
1542 mb = MB(ctx->opcode);
1543 me = ME(ctx->opcode);
1544 t0 = tcg_temp_new();
1545 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1546 #if defined(TARGET_PPC64)
1547 t1 = tcg_temp_new_i32();
1548 t2 = tcg_temp_new_i32();
1549 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1550 tcg_gen_trunc_i64_i32(t2, t0);
1551 tcg_gen_rotl_i32(t1, t1, t2);
1552 tcg_gen_extu_i32_i64(t0, t1);
1553 tcg_temp_free_i32(t1);
1554 tcg_temp_free_i32(t2);
1555 #else
1556 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1557 #endif
1558 if (unlikely(mb != 0 || me != 31)) {
1559 #if defined(TARGET_PPC64)
1560 mb += 32;
1561 me += 32;
1562 #endif
1563 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1564 } else {
1565 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1566 }
1567 tcg_temp_free(t0);
1568 if (unlikely(Rc(ctx->opcode) != 0))
1569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1570 }
1571
1572 #if defined(TARGET_PPC64)
1573 #define GEN_PPC64_R2(name, opc1, opc2) \
1574 static void glue(gen_, name##0)(DisasContext *ctx) \
1575 { \
1576 gen_##name(ctx, 0); \
1577 } \
1578 \
1579 static void glue(gen_, name##1)(DisasContext *ctx) \
1580 { \
1581 gen_##name(ctx, 1); \
1582 }
1583 #define GEN_PPC64_R4(name, opc1, opc2) \
1584 static void glue(gen_, name##0)(DisasContext *ctx) \
1585 { \
1586 gen_##name(ctx, 0, 0); \
1587 } \
1588 \
1589 static void glue(gen_, name##1)(DisasContext *ctx) \
1590 { \
1591 gen_##name(ctx, 0, 1); \
1592 } \
1593 \
1594 static void glue(gen_, name##2)(DisasContext *ctx) \
1595 { \
1596 gen_##name(ctx, 1, 0); \
1597 } \
1598 \
1599 static void glue(gen_, name##3)(DisasContext *ctx) \
1600 { \
1601 gen_##name(ctx, 1, 1); \
1602 }
1603
1604 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1605 uint32_t sh)
1606 {
1607 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1608 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1609 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1610 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1611 } else {
1612 TCGv t0 = tcg_temp_new();
1613 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1614 if (likely(mb == 0 && me == 63)) {
1615 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1616 } else {
1617 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1618 }
1619 tcg_temp_free(t0);
1620 }
1621 if (unlikely(Rc(ctx->opcode) != 0))
1622 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1623 }
1624 /* rldicl - rldicl. */
1625 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1626 {
1627 uint32_t sh, mb;
1628
1629 sh = SH(ctx->opcode) | (shn << 5);
1630 mb = MB(ctx->opcode) | (mbn << 5);
1631 gen_rldinm(ctx, mb, 63, sh);
1632 }
1633 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1634 /* rldicr - rldicr. */
1635 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1636 {
1637 uint32_t sh, me;
1638
1639 sh = SH(ctx->opcode) | (shn << 5);
1640 me = MB(ctx->opcode) | (men << 5);
1641 gen_rldinm(ctx, 0, me, sh);
1642 }
1643 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1644 /* rldic - rldic. */
1645 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1646 {
1647 uint32_t sh, mb;
1648
1649 sh = SH(ctx->opcode) | (shn << 5);
1650 mb = MB(ctx->opcode) | (mbn << 5);
1651 gen_rldinm(ctx, mb, 63 - sh, sh);
1652 }
1653 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1654
1655 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1656 {
1657 TCGv t0;
1658
1659 mb = MB(ctx->opcode);
1660 me = ME(ctx->opcode);
1661 t0 = tcg_temp_new();
1662 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1663 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1664 if (unlikely(mb != 0 || me != 63)) {
1665 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1666 } else {
1667 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1668 }
1669 tcg_temp_free(t0);
1670 if (unlikely(Rc(ctx->opcode) != 0))
1671 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1672 }
1673
1674 /* rldcl - rldcl. */
1675 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1676 {
1677 uint32_t mb;
1678
1679 mb = MB(ctx->opcode) | (mbn << 5);
1680 gen_rldnm(ctx, mb, 63);
1681 }
1682 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1683 /* rldcr - rldcr. */
1684 static inline void gen_rldcr(DisasContext *ctx, int men)
1685 {
1686 uint32_t me;
1687
1688 me = MB(ctx->opcode) | (men << 5);
1689 gen_rldnm(ctx, 0, me);
1690 }
1691 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1692 /* rldimi - rldimi. */
1693 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1694 {
1695 uint32_t sh, mb, me;
1696
1697 sh = SH(ctx->opcode) | (shn << 5);
1698 mb = MB(ctx->opcode) | (mbn << 5);
1699 me = 63 - sh;
1700 if (unlikely(sh == 0 && mb == 0)) {
1701 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1702 } else {
1703 TCGv t0, t1;
1704 target_ulong mask;
1705
1706 t0 = tcg_temp_new();
1707 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1708 t1 = tcg_temp_new();
1709 mask = MASK(mb, me);
1710 tcg_gen_andi_tl(t0, t0, mask);
1711 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1712 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1713 tcg_temp_free(t0);
1714 tcg_temp_free(t1);
1715 }
1716 if (unlikely(Rc(ctx->opcode) != 0))
1717 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1718 }
1719 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1720 #endif
1721
1722 /*** Integer shift ***/
1723
1724 /* slw & slw. */
1725 static void gen_slw(DisasContext *ctx)
1726 {
1727 TCGv t0, t1;
1728
1729 t0 = tcg_temp_new();
1730 /* AND rS with a mask that is 0 when rB >= 0x20 */
1731 #if defined(TARGET_PPC64)
1732 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1733 tcg_gen_sari_tl(t0, t0, 0x3f);
1734 #else
1735 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1736 tcg_gen_sari_tl(t0, t0, 0x1f);
1737 #endif
1738 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1739 t1 = tcg_temp_new();
1740 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1741 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1742 tcg_temp_free(t1);
1743 tcg_temp_free(t0);
1744 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1745 if (unlikely(Rc(ctx->opcode) != 0))
1746 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1747 }
1748
1749 /* sraw & sraw. */
1750 static void gen_sraw(DisasContext *ctx)
1751 {
1752 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1753 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1754 if (unlikely(Rc(ctx->opcode) != 0))
1755 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1756 }
1757
1758 /* srawi & srawi. */
1759 static void gen_srawi(DisasContext *ctx)
1760 {
1761 int sh = SH(ctx->opcode);
1762 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1763 TCGv src = cpu_gpr[rS(ctx->opcode)];
1764 if (sh == 0) {
1765 tcg_gen_mov_tl(dst, src);
1766 tcg_gen_movi_tl(cpu_ca, 0);
1767 } else {
1768 TCGv t0;
1769 tcg_gen_ext32s_tl(dst, src);
1770 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1771 t0 = tcg_temp_new();
1772 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1773 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1774 tcg_temp_free(t0);
1775 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1776 tcg_gen_sari_tl(dst, dst, sh);
1777 }
1778 if (unlikely(Rc(ctx->opcode) != 0)) {
1779 gen_set_Rc0(ctx, dst);
1780 }
1781 }
1782
1783 /* srw & srw. */
1784 static void gen_srw(DisasContext *ctx)
1785 {
1786 TCGv t0, t1;
1787
1788 t0 = tcg_temp_new();
1789 /* AND rS with a mask that is 0 when rB >= 0x20 */
1790 #if defined(TARGET_PPC64)
1791 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1792 tcg_gen_sari_tl(t0, t0, 0x3f);
1793 #else
1794 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1795 tcg_gen_sari_tl(t0, t0, 0x1f);
1796 #endif
1797 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1798 tcg_gen_ext32u_tl(t0, t0);
1799 t1 = tcg_temp_new();
1800 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1801 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1802 tcg_temp_free(t1);
1803 tcg_temp_free(t0);
1804 if (unlikely(Rc(ctx->opcode) != 0))
1805 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1806 }
1807
1808 #if defined(TARGET_PPC64)
1809 /* sld & sld. */
1810 static void gen_sld(DisasContext *ctx)
1811 {
1812 TCGv t0, t1;
1813
1814 t0 = tcg_temp_new();
1815 /* AND rS with a mask that is 0 when rB >= 0x40 */
1816 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1817 tcg_gen_sari_tl(t0, t0, 0x3f);
1818 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1819 t1 = tcg_temp_new();
1820 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1821 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1822 tcg_temp_free(t1);
1823 tcg_temp_free(t0);
1824 if (unlikely(Rc(ctx->opcode) != 0))
1825 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1826 }
1827
1828 /* srad & srad. */
1829 static void gen_srad(DisasContext *ctx)
1830 {
1831 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1832 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1833 if (unlikely(Rc(ctx->opcode) != 0))
1834 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1835 }
1836 /* sradi & sradi. */
1837 static inline void gen_sradi(DisasContext *ctx, int n)
1838 {
1839 int sh = SH(ctx->opcode) + (n << 5);
1840 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1841 TCGv src = cpu_gpr[rS(ctx->opcode)];
1842 if (sh == 0) {
1843 tcg_gen_mov_tl(dst, src);
1844 tcg_gen_movi_tl(cpu_ca, 0);
1845 } else {
1846 TCGv t0;
1847 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1848 t0 = tcg_temp_new();
1849 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1850 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1851 tcg_temp_free(t0);
1852 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1853 tcg_gen_sari_tl(dst, src, sh);
1854 }
1855 if (unlikely(Rc(ctx->opcode) != 0)) {
1856 gen_set_Rc0(ctx, dst);
1857 }
1858 }
1859
1860 static void gen_sradi0(DisasContext *ctx)
1861 {
1862 gen_sradi(ctx, 0);
1863 }
1864
1865 static void gen_sradi1(DisasContext *ctx)
1866 {
1867 gen_sradi(ctx, 1);
1868 }
1869
1870 /* srd & srd. */
1871 static void gen_srd(DisasContext *ctx)
1872 {
1873 TCGv t0, t1;
1874
1875 t0 = tcg_temp_new();
1876 /* AND rS with a mask that is 0 when rB >= 0x40 */
1877 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1878 tcg_gen_sari_tl(t0, t0, 0x3f);
1879 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1880 t1 = tcg_temp_new();
1881 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1882 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1883 tcg_temp_free(t1);
1884 tcg_temp_free(t0);
1885 if (unlikely(Rc(ctx->opcode) != 0))
1886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1887 }
1888 #endif
1889
1890 /*** Floating-Point arithmetic ***/
1891 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1892 static void gen_f##name(DisasContext *ctx) \
1893 { \
1894 if (unlikely(!ctx->fpu_enabled)) { \
1895 gen_exception(ctx, POWERPC_EXCP_FPU); \
1896 return; \
1897 } \
1898 /* NIP cannot be restored if the memory exception comes from an helper */ \
1899 gen_update_nip(ctx, ctx->nip - 4); \
1900 gen_reset_fpstatus(); \
1901 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1902 cpu_fpr[rA(ctx->opcode)], \
1903 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1904 if (isfloat) { \
1905 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1906 cpu_fpr[rD(ctx->opcode)]); \
1907 } \
1908 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1909 Rc(ctx->opcode) != 0); \
1910 }
1911
1912 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1913 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1914 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1915
1916 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1917 static void gen_f##name(DisasContext *ctx) \
1918 { \
1919 if (unlikely(!ctx->fpu_enabled)) { \
1920 gen_exception(ctx, POWERPC_EXCP_FPU); \
1921 return; \
1922 } \
1923 /* NIP cannot be restored if the memory exception comes from an helper */ \
1924 gen_update_nip(ctx, ctx->nip - 4); \
1925 gen_reset_fpstatus(); \
1926 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1927 cpu_fpr[rA(ctx->opcode)], \
1928 cpu_fpr[rB(ctx->opcode)]); \
1929 if (isfloat) { \
1930 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1931 cpu_fpr[rD(ctx->opcode)]); \
1932 } \
1933 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1934 set_fprf, Rc(ctx->opcode) != 0); \
1935 }
1936 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1937 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1938 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1939
1940 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1941 static void gen_f##name(DisasContext *ctx) \
1942 { \
1943 if (unlikely(!ctx->fpu_enabled)) { \
1944 gen_exception(ctx, POWERPC_EXCP_FPU); \
1945 return; \
1946 } \
1947 /* NIP cannot be restored if the memory exception comes from an helper */ \
1948 gen_update_nip(ctx, ctx->nip - 4); \
1949 gen_reset_fpstatus(); \
1950 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1951 cpu_fpr[rA(ctx->opcode)], \
1952 cpu_fpr[rC(ctx->opcode)]); \
1953 if (isfloat) { \
1954 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1955 cpu_fpr[rD(ctx->opcode)]); \
1956 } \
1957 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1958 set_fprf, Rc(ctx->opcode) != 0); \
1959 }
1960 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1961 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1962 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1963
1964 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1965 static void gen_f##name(DisasContext *ctx) \
1966 { \
1967 if (unlikely(!ctx->fpu_enabled)) { \
1968 gen_exception(ctx, POWERPC_EXCP_FPU); \
1969 return; \
1970 } \
1971 /* NIP cannot be restored if the memory exception comes from an helper */ \
1972 gen_update_nip(ctx, ctx->nip - 4); \
1973 gen_reset_fpstatus(); \
1974 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1975 cpu_fpr[rB(ctx->opcode)]); \
1976 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1977 set_fprf, Rc(ctx->opcode) != 0); \
1978 }
1979
1980 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1981 static void gen_f##name(DisasContext *ctx) \
1982 { \
1983 if (unlikely(!ctx->fpu_enabled)) { \
1984 gen_exception(ctx, POWERPC_EXCP_FPU); \
1985 return; \
1986 } \
1987 /* NIP cannot be restored if the memory exception comes from an helper */ \
1988 gen_update_nip(ctx, ctx->nip - 4); \
1989 gen_reset_fpstatus(); \
1990 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1991 cpu_fpr[rB(ctx->opcode)]); \
1992 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1993 set_fprf, Rc(ctx->opcode) != 0); \
1994 }
1995
1996 /* fadd - fadds */
1997 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
1998 /* fdiv - fdivs */
1999 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2000 /* fmul - fmuls */
2001 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2002
2003 /* fre */
2004 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2005
2006 /* fres */
2007 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2008
2009 /* frsqrte */
2010 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2011
2012 /* frsqrtes */
2013 static void gen_frsqrtes(DisasContext *ctx)
2014 {
2015 if (unlikely(!ctx->fpu_enabled)) {
2016 gen_exception(ctx, POWERPC_EXCP_FPU);
2017 return;
2018 }
2019 /* NIP cannot be restored if the memory exception comes from an helper */
2020 gen_update_nip(ctx, ctx->nip - 4);
2021 gen_reset_fpstatus();
2022 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2023 cpu_fpr[rB(ctx->opcode)]);
2024 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2025 cpu_fpr[rD(ctx->opcode)]);
2026 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2027 }
2028
2029 /* fsel */
2030 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2031 /* fsub - fsubs */
2032 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2033 /* Optional: */
2034
2035 /* fsqrt */
2036 static void gen_fsqrt(DisasContext *ctx)
2037 {
2038 if (unlikely(!ctx->fpu_enabled)) {
2039 gen_exception(ctx, POWERPC_EXCP_FPU);
2040 return;
2041 }
2042 /* NIP cannot be restored if the memory exception comes from an helper */
2043 gen_update_nip(ctx, ctx->nip - 4);
2044 gen_reset_fpstatus();
2045 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2046 cpu_fpr[rB(ctx->opcode)]);
2047 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2048 }
2049
2050 static void gen_fsqrts(DisasContext *ctx)
2051 {
2052 if (unlikely(!ctx->fpu_enabled)) {
2053 gen_exception(ctx, POWERPC_EXCP_FPU);
2054 return;
2055 }
2056 /* NIP cannot be restored if the memory exception comes from an helper */
2057 gen_update_nip(ctx, ctx->nip - 4);
2058 gen_reset_fpstatus();
2059 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2060 cpu_fpr[rB(ctx->opcode)]);
2061 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2062 cpu_fpr[rD(ctx->opcode)]);
2063 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2064 }
2065
2066 /*** Floating-Point multiply-and-add ***/
2067 /* fmadd - fmadds */
2068 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2069 /* fmsub - fmsubs */
2070 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2071 /* fnmadd - fnmadds */
2072 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2073 /* fnmsub - fnmsubs */
2074 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2075
2076 /*** Floating-Point round & convert ***/
2077 /* fctiw */
2078 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2079 /* fctiwz */
2080 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2081 /* frsp */
2082 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2083 #if defined(TARGET_PPC64)
2084 /* fcfid */
2085 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2086 /* fctid */
2087 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2088 /* fctidz */
2089 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2090 #endif
2091
2092 /* frin */
2093 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2094 /* friz */
2095 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2096 /* frip */
2097 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2098 /* frim */
2099 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2100
2101 /*** Floating-Point compare ***/
2102
2103 /* fcmpo */
2104 static void gen_fcmpo(DisasContext *ctx)
2105 {
2106 TCGv_i32 crf;
2107 if (unlikely(!ctx->fpu_enabled)) {
2108 gen_exception(ctx, POWERPC_EXCP_FPU);
2109 return;
2110 }
2111 /* NIP cannot be restored if the memory exception comes from an helper */
2112 gen_update_nip(ctx, ctx->nip - 4);
2113 gen_reset_fpstatus();
2114 crf = tcg_const_i32(crfD(ctx->opcode));
2115 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2116 cpu_fpr[rB(ctx->opcode)], crf);
2117 tcg_temp_free_i32(crf);
2118 gen_helper_float_check_status(cpu_env);
2119 }
2120
2121 /* fcmpu */
2122 static void gen_fcmpu(DisasContext *ctx)
2123 {
2124 TCGv_i32 crf;
2125 if (unlikely(!ctx->fpu_enabled)) {
2126 gen_exception(ctx, POWERPC_EXCP_FPU);
2127 return;
2128 }
2129 /* NIP cannot be restored if the memory exception comes from an helper */
2130 gen_update_nip(ctx, ctx->nip - 4);
2131 gen_reset_fpstatus();
2132 crf = tcg_const_i32(crfD(ctx->opcode));
2133 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2134 cpu_fpr[rB(ctx->opcode)], crf);
2135 tcg_temp_free_i32(crf);
2136 gen_helper_float_check_status(cpu_env);
2137 }
2138
2139 /*** Floating-point move ***/
2140 /* fabs */
2141 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2142 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2143
2144 /* fmr - fmr. */
2145 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2146 static void gen_fmr(DisasContext *ctx)
2147 {
2148 if (unlikely(!ctx->fpu_enabled)) {
2149 gen_exception(ctx, POWERPC_EXCP_FPU);
2150 return;
2151 }
2152 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2153 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2154 }
2155
2156 /* fnabs */
2157 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2158 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2159 /* fneg */
2160 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2161 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2162
2163 /*** Floating-Point status & ctrl register ***/
2164
2165 /* mcrfs */
2166 static void gen_mcrfs(DisasContext *ctx)
2167 {
2168 TCGv tmp = tcg_temp_new();
2169 int bfa;
2170
2171 if (unlikely(!ctx->fpu_enabled)) {
2172 gen_exception(ctx, POWERPC_EXCP_FPU);
2173 return;
2174 }
2175 bfa = 4 * (7 - crfS(ctx->opcode));
2176 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2177 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2178 tcg_temp_free(tmp);
2179 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2180 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2181 }
2182
2183 /* mffs */
2184 static void gen_mffs(DisasContext *ctx)
2185 {
2186 if (unlikely(!ctx->fpu_enabled)) {
2187 gen_exception(ctx, POWERPC_EXCP_FPU);
2188 return;
2189 }
2190 gen_reset_fpstatus();
2191 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2192 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2193 }
2194
2195 /* mtfsb0 */
2196 static void gen_mtfsb0(DisasContext *ctx)
2197 {
2198 uint8_t crb;
2199
2200 if (unlikely(!ctx->fpu_enabled)) {
2201 gen_exception(ctx, POWERPC_EXCP_FPU);
2202 return;
2203 }
2204 crb = 31 - crbD(ctx->opcode);
2205 gen_reset_fpstatus();
2206 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2207 TCGv_i32 t0;
2208 /* NIP cannot be restored if the memory exception comes from an helper */
2209 gen_update_nip(ctx, ctx->nip - 4);
2210 t0 = tcg_const_i32(crb);
2211 gen_helper_fpscr_clrbit(cpu_env, t0);
2212 tcg_temp_free_i32(t0);
2213 }
2214 if (unlikely(Rc(ctx->opcode) != 0)) {
2215 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2216 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2217 }
2218 }
2219
2220 /* mtfsb1 */
2221 static void gen_mtfsb1(DisasContext *ctx)
2222 {
2223 uint8_t crb;
2224
2225 if (unlikely(!ctx->fpu_enabled)) {
2226 gen_exception(ctx, POWERPC_EXCP_FPU);
2227 return;
2228 }
2229 crb = 31 - crbD(ctx->opcode);
2230 gen_reset_fpstatus();
2231 /* XXX: we pretend we can only do IEEE floating-point computations */
2232 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2233 TCGv_i32 t0;
2234 /* NIP cannot be restored if the memory exception comes from an helper */
2235 gen_update_nip(ctx, ctx->nip - 4);
2236 t0 = tcg_const_i32(crb);
2237 gen_helper_fpscr_setbit(cpu_env, t0);
2238 tcg_temp_free_i32(t0);
2239 }
2240 if (unlikely(Rc(ctx->opcode) != 0)) {
2241 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2242 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2243 }
2244 /* We can raise a differed exception */
2245 gen_helper_float_check_status(cpu_env);
2246 }
2247
2248 /* mtfsf */
2249 static void gen_mtfsf(DisasContext *ctx)
2250 {
2251 TCGv_i32 t0;
2252 int L = ctx->opcode & 0x02000000;
2253
2254 if (unlikely(!ctx->fpu_enabled)) {
2255 gen_exception(ctx, POWERPC_EXCP_FPU);
2256 return;
2257 }
2258 /* NIP cannot be restored if the memory exception comes from an helper */
2259 gen_update_nip(ctx, ctx->nip - 4);
2260 gen_reset_fpstatus();
2261 if (L)
2262 t0 = tcg_const_i32(0xff);
2263 else
2264 t0 = tcg_const_i32(FM(ctx->opcode));
2265 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2266 tcg_temp_free_i32(t0);
2267 if (unlikely(Rc(ctx->opcode) != 0)) {
2268 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2269 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2270 }
2271 /* We can raise a differed exception */
2272 gen_helper_float_check_status(cpu_env);
2273 }
2274
2275 /* mtfsfi */
2276 static void gen_mtfsfi(DisasContext *ctx)
2277 {
2278 int bf, sh;
2279 TCGv_i64 t0;
2280 TCGv_i32 t1;
2281
2282 if (unlikely(!ctx->fpu_enabled)) {
2283 gen_exception(ctx, POWERPC_EXCP_FPU);
2284 return;
2285 }
2286 bf = crbD(ctx->opcode) >> 2;
2287 sh = 7 - bf;
2288 /* NIP cannot be restored if the memory exception comes from an helper */
2289 gen_update_nip(ctx, ctx->nip - 4);
2290 gen_reset_fpstatus();
2291 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2292 t1 = tcg_const_i32(1 << sh);
2293 gen_helper_store_fpscr(cpu_env, t0, t1);
2294 tcg_temp_free_i64(t0);
2295 tcg_temp_free_i32(t1);
2296 if (unlikely(Rc(ctx->opcode) != 0)) {
2297 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2298 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2299 }
2300 /* We can raise a differed exception */
2301 gen_helper_float_check_status(cpu_env);
2302 }
2303
2304 /*** Addressing modes ***/
2305 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2306 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2307 target_long maskl)
2308 {
2309 target_long simm = SIMM(ctx->opcode);
2310
2311 simm &= ~maskl;
2312 if (rA(ctx->opcode) == 0) {
2313 #if defined(TARGET_PPC64)
2314 if (!ctx->sf_mode) {
2315 tcg_gen_movi_tl(EA, (uint32_t)simm);
2316 } else
2317 #endif
2318 tcg_gen_movi_tl(EA, simm);
2319 } else if (likely(simm != 0)) {
2320 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2321 #if defined(TARGET_PPC64)
2322 if (!ctx->sf_mode) {
2323 tcg_gen_ext32u_tl(EA, EA);
2324 }
2325 #endif
2326 } else {
2327 #if defined(TARGET_PPC64)
2328 if (!ctx->sf_mode) {
2329 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2330 } else
2331 #endif
2332 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2333 }
2334 }
2335
2336 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2337 {
2338 if (rA(ctx->opcode) == 0) {
2339 #if defined(TARGET_PPC64)
2340 if (!ctx->sf_mode) {
2341 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2342 } else
2343 #endif
2344 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2345 } else {
2346 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2347 #if defined(TARGET_PPC64)
2348 if (!ctx->sf_mode) {
2349 tcg_gen_ext32u_tl(EA, EA);
2350 }
2351 #endif
2352 }
2353 }
2354
2355 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2356 {
2357 if (rA(ctx->opcode) == 0) {
2358 tcg_gen_movi_tl(EA, 0);
2359 } else {
2360 #if defined(TARGET_PPC64)
2361 if (!ctx->sf_mode) {
2362 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2363 } else
2364 #endif
2365 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2366 }
2367 }
2368
2369 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2370 target_long val)
2371 {
2372 tcg_gen_addi_tl(ret, arg1, val);
2373 #if defined(TARGET_PPC64)
2374 if (!ctx->sf_mode) {
2375 tcg_gen_ext32u_tl(ret, ret);
2376 }
2377 #endif
2378 }
2379
2380 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2381 {
2382 int l1 = gen_new_label();
2383 TCGv t0 = tcg_temp_new();
2384 TCGv_i32 t1, t2;
2385 /* NIP cannot be restored if the memory exception comes from an helper */
2386 gen_update_nip(ctx, ctx->nip - 4);
2387 tcg_gen_andi_tl(t0, EA, mask);
2388 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2389 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2390 t2 = tcg_const_i32(0);
2391 gen_helper_raise_exception_err(cpu_env, t1, t2);
2392 tcg_temp_free_i32(t1);
2393 tcg_temp_free_i32(t2);
2394 gen_set_label(l1);
2395 tcg_temp_free(t0);
2396 }
2397
2398 /*** Integer load ***/
2399 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2400 {
2401 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2402 }
2403
2404 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2405 {
2406 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2407 }
2408
2409 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2410 {
2411 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2412 if (unlikely(ctx->le_mode)) {
2413 tcg_gen_bswap16_tl(arg1, arg1);
2414 }
2415 }
2416
2417 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2418 {
2419 if (unlikely(ctx->le_mode)) {
2420 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2421 tcg_gen_bswap16_tl(arg1, arg1);
2422 tcg_gen_ext16s_tl(arg1, arg1);
2423 } else {
2424 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2425 }
2426 }
2427
2428 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2429 {
2430 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2431 if (unlikely(ctx->le_mode)) {
2432 tcg_gen_bswap32_tl(arg1, arg1);
2433 }
2434 }
2435
2436 #if defined(TARGET_PPC64)
2437 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2438 {
2439 if (unlikely(ctx->le_mode)) {
2440 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2441 tcg_gen_bswap32_tl(arg1, arg1);
2442 tcg_gen_ext32s_tl(arg1, arg1);
2443 } else
2444 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2445 }
2446 #endif
2447
2448 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2449 {
2450 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2451 if (unlikely(ctx->le_mode)) {
2452 tcg_gen_bswap64_i64(arg1, arg1);
2453 }
2454 }
2455
2456 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2457 {
2458 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2459 }
2460
2461 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2462 {
2463 if (unlikely(ctx->le_mode)) {
2464 TCGv t0 = tcg_temp_new();
2465 tcg_gen_ext16u_tl(t0, arg1);
2466 tcg_gen_bswap16_tl(t0, t0);
2467 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2468 tcg_temp_free(t0);
2469 } else {
2470 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2471 }
2472 }
2473
2474 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2475 {
2476 if (unlikely(ctx->le_mode)) {
2477 TCGv t0 = tcg_temp_new();
2478 tcg_gen_ext32u_tl(t0, arg1);
2479 tcg_gen_bswap32_tl(t0, t0);
2480 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2481 tcg_temp_free(t0);
2482 } else {
2483 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2484 }
2485 }
2486
2487 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2488 {
2489 if (unlikely(ctx->le_mode)) {
2490 TCGv_i64 t0 = tcg_temp_new_i64();
2491 tcg_gen_bswap64_i64(t0, arg1);
2492 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2493 tcg_temp_free_i64(t0);
2494 } else
2495 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2496 }
2497
2498 #define GEN_LD(name, ldop, opc, type) \
2499 static void glue(gen_, name)(DisasContext *ctx) \
2500 { \
2501 TCGv EA; \
2502 gen_set_access_type(ctx, ACCESS_INT); \
2503 EA = tcg_temp_new(); \
2504 gen_addr_imm_index(ctx, EA, 0); \
2505 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2506 tcg_temp_free(EA); \
2507 }
2508
2509 #define GEN_LDU(name, ldop, opc, type) \
2510 static void glue(gen_, name##u)(DisasContext *ctx) \
2511 { \
2512 TCGv EA; \
2513 if (unlikely(rA(ctx->opcode) == 0 || \
2514 rA(ctx->opcode) == rD(ctx->opcode))) { \
2515 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2516 return; \
2517 } \
2518 gen_set_access_type(ctx, ACCESS_INT); \
2519 EA = tcg_temp_new(); \
2520 if (type == PPC_64B) \
2521 gen_addr_imm_index(ctx, EA, 0x03); \
2522 else \
2523 gen_addr_imm_index(ctx, EA, 0); \
2524 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2525 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2526 tcg_temp_free(EA); \
2527 }
2528
2529 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2530 static void glue(gen_, name##ux)(DisasContext *ctx) \
2531 { \
2532 TCGv EA; \
2533 if (unlikely(rA(ctx->opcode) == 0 || \
2534 rA(ctx->opcode) == rD(ctx->opcode))) { \
2535 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2536 return; \
2537 } \
2538 gen_set_access_type(ctx, ACCESS_INT); \
2539 EA = tcg_temp_new(); \
2540 gen_addr_reg_index(ctx, EA); \
2541 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2542 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2543 tcg_temp_free(EA); \
2544 }
2545
2546 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2547 static void glue(gen_, name##x)(DisasContext *ctx) \
2548 { \
2549 TCGv EA; \
2550 gen_set_access_type(ctx, ACCESS_INT); \
2551 EA = tcg_temp_new(); \
2552 gen_addr_reg_index(ctx, EA); \
2553 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2554 tcg_temp_free(EA); \
2555 }
2556 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2557 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2558
2559 #define GEN_LDS(name, ldop, op, type) \
2560 GEN_LD(name, ldop, op | 0x20, type); \
2561 GEN_LDU(name, ldop, op | 0x21, type); \
2562 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2563 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2564
2565 /* lbz lbzu lbzux lbzx */
2566 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2567 /* lha lhau lhaux lhax */
2568 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2569 /* lhz lhzu lhzux lhzx */
2570 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2571 /* lwz lwzu lwzux lwzx */
2572 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2573 #if defined(TARGET_PPC64)
2574 /* lwaux */
2575 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2576 /* lwax */
2577 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2578 /* ldux */
2579 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2580 /* ldx */
2581 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2582
2583 static void gen_ld(DisasContext *ctx)
2584 {
2585 TCGv EA;
2586 if (Rc(ctx->opcode)) {
2587 if (unlikely(rA(ctx->opcode) == 0 ||
2588 rA(ctx->opcode) == rD(ctx->opcode))) {
2589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2590 return;
2591 }
2592 }
2593 gen_set_access_type(ctx, ACCESS_INT);
2594 EA = tcg_temp_new();
2595 gen_addr_imm_index(ctx, EA, 0x03);
2596 if (ctx->opcode & 0x02) {
2597 /* lwa (lwau is undefined) */
2598 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2599 } else {
2600 /* ld - ldu */
2601 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2602 }
2603 if (Rc(ctx->opcode))
2604 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2605 tcg_temp_free(EA);
2606 }
2607
2608 /* lq */
2609 static void gen_lq(DisasContext *ctx)
2610 {
2611 #if defined(CONFIG_USER_ONLY)
2612 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2613 #else
2614 int ra, rd;
2615 TCGv EA;
2616
2617 /* Restore CPU state */
2618 if (unlikely(ctx->mem_idx == 0)) {
2619 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2620 return;
2621 }
2622 ra = rA(ctx->opcode);
2623 rd = rD(ctx->opcode);
2624 if (unlikely((rd & 1) || rd == ra)) {
2625 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2626 return;
2627 }
2628 if (unlikely(ctx->le_mode)) {
2629 /* Little-endian mode is not handled */
2630 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2631 return;
2632 }
2633 gen_set_access_type(ctx, ACCESS_INT);
2634 EA = tcg_temp_new();
2635 gen_addr_imm_index(ctx, EA, 0x0F);
2636 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2637 gen_addr_add(ctx, EA, EA, 8);
2638 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2639 tcg_temp_free(EA);
2640 #endif
2641 }
2642 #endif
2643
2644 /*** Integer store ***/
2645 #define GEN_ST(name, stop, opc, type) \
2646 static void glue(gen_, name)(DisasContext *ctx) \
2647 { \
2648 TCGv EA; \
2649 gen_set_access_type(ctx, ACCESS_INT); \
2650 EA = tcg_temp_new(); \
2651 gen_addr_imm_index(ctx, EA, 0); \
2652 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2653 tcg_temp_free(EA); \
2654 }
2655
2656 #define GEN_STU(name, stop, opc, type) \
2657 static void glue(gen_, stop##u)(DisasContext *ctx) \
2658 { \
2659 TCGv EA; \
2660 if (unlikely(rA(ctx->opcode) == 0)) { \
2661 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2662 return; \
2663 } \
2664 gen_set_access_type(ctx, ACCESS_INT); \
2665 EA = tcg_temp_new(); \
2666 if (type == PPC_64B) \
2667 gen_addr_imm_index(ctx, EA, 0x03); \
2668 else \
2669 gen_addr_imm_index(ctx, EA, 0); \
2670 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2671 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2672 tcg_temp_free(EA); \
2673 }
2674
2675 #define GEN_STUX(name, stop, opc2, opc3, type) \
2676 static void glue(gen_, name##ux)(DisasContext *ctx) \
2677 { \
2678 TCGv EA; \
2679 if (unlikely(rA(ctx->opcode) == 0)) { \
2680 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2681 return; \
2682 } \
2683 gen_set_access_type(ctx, ACCESS_INT); \
2684 EA = tcg_temp_new(); \
2685 gen_addr_reg_index(ctx, EA); \
2686 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2687 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2688 tcg_temp_free(EA); \
2689 }
2690
2691 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2692 static void glue(gen_, name##x)(DisasContext *ctx) \
2693 { \
2694 TCGv EA; \
2695 gen_set_access_type(ctx, ACCESS_INT); \
2696 EA = tcg_temp_new(); \
2697 gen_addr_reg_index(ctx, EA); \
2698 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2699 tcg_temp_free(EA); \
2700 }
2701 #define GEN_STX(name, stop, opc2, opc3, type) \
2702 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2703
2704 #define GEN_STS(name, stop, op, type) \
2705 GEN_ST(name, stop, op | 0x20, type); \
2706 GEN_STU(name, stop, op | 0x21, type); \
2707 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2708 GEN_STX(name, stop, 0x17, op | 0x00, type)
2709
2710 /* stb stbu stbux stbx */
2711 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2712 /* sth sthu sthux sthx */
2713 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2714 /* stw stwu stwux stwx */
2715 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2716 #if defined(TARGET_PPC64)
2717 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2718 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2719
2720 static void gen_std(DisasContext *ctx)
2721 {
2722 int rs;
2723 TCGv EA;
2724
2725 rs = rS(ctx->opcode);
2726 if ((ctx->opcode & 0x3) == 0x2) {
2727 #if defined(CONFIG_USER_ONLY)
2728 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2729 #else
2730 /* stq */
2731 if (unlikely(ctx->mem_idx == 0)) {
2732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2733 return;
2734 }
2735 if (unlikely(rs & 1)) {
2736 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2737 return;
2738 }
2739 if (unlikely(ctx->le_mode)) {
2740 /* Little-endian mode is not handled */
2741 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2742 return;
2743 }
2744 gen_set_access_type(ctx, ACCESS_INT);
2745 EA = tcg_temp_new();
2746 gen_addr_imm_index(ctx, EA, 0x03);
2747 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2748 gen_addr_add(ctx, EA, EA, 8);
2749 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2750 tcg_temp_free(EA);
2751 #endif
2752 } else {
2753 /* std / stdu */
2754 if (Rc(ctx->opcode)) {
2755 if (unlikely(rA(ctx->opcode) == 0)) {
2756 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2757 return;
2758 }
2759 }
2760 gen_set_access_type(ctx, ACCESS_INT);
2761 EA = tcg_temp_new();
2762 gen_addr_imm_index(ctx, EA, 0x03);
2763 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2764 if (Rc(ctx->opcode))
2765 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2766 tcg_temp_free(EA);
2767 }
2768 }
2769 #endif
2770 /*** Integer load and store with byte reverse ***/
2771 /* lhbrx */
2772 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2773 {
2774 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2775 if (likely(!ctx->le_mode)) {
2776 tcg_gen_bswap16_tl(arg1, arg1);
2777 }
2778 }
2779 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2780
2781 /* lwbrx */
2782 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2783 {
2784 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2785 if (likely(!ctx->le_mode)) {
2786 tcg_gen_bswap32_tl(arg1, arg1);
2787 }
2788 }
2789 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2790
2791 #if defined(TARGET_PPC64)
2792 /* ldbrx */
2793 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2794 {
2795 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2796 if (likely(!ctx->le_mode)) {
2797 tcg_gen_bswap64_tl(arg1, arg1);
2798 }
2799 }
2800 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2801 #endif /* TARGET_PPC64 */
2802
2803 /* sthbrx */
2804 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2805 {
2806 if (likely(!ctx->le_mode)) {
2807 TCGv t0 = tcg_temp_new();
2808 tcg_gen_ext16u_tl(t0, arg1);
2809 tcg_gen_bswap16_tl(t0, t0);
2810 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2811 tcg_temp_free(t0);
2812 } else {
2813 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2814 }
2815 }
2816 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2817
2818 /* stwbrx */
2819 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2820 {
2821 if (likely(!ctx->le_mode)) {
2822 TCGv t0 = tcg_temp_new();
2823 tcg_gen_ext32u_tl(t0, arg1);
2824 tcg_gen_bswap32_tl(t0, t0);
2825 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2826 tcg_temp_free(t0);
2827 } else {
2828 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2829 }
2830 }
2831 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2832
2833 #if defined(TARGET_PPC64)
2834 /* stdbrx */
2835 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2836 {
2837 if (likely(!ctx->le_mode)) {
2838 TCGv t0 = tcg_temp_new();
2839 tcg_gen_bswap64_tl(t0, arg1);
2840 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2841 tcg_temp_free(t0);
2842 } else {
2843 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2844 }
2845 }
2846 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2847 #endif /* TARGET_PPC64 */
2848
2849 /*** Integer load and store multiple ***/
2850
2851 /* lmw */
2852 static void gen_lmw(DisasContext *ctx)
2853 {
2854 TCGv t0;
2855 TCGv_i32 t1;
2856 gen_set_access_type(ctx, ACCESS_INT);
2857 /* NIP cannot be restored if the memory exception comes from an helper */
2858 gen_update_nip(ctx, ctx->nip - 4);
2859 t0 = tcg_temp_new();
2860 t1 = tcg_const_i32(rD(ctx->opcode));
2861 gen_addr_imm_index(ctx, t0, 0);
2862 gen_helper_lmw(cpu_env, t0, t1);
2863 tcg_temp_free(t0);
2864 tcg_temp_free_i32(t1);
2865 }
2866
2867 /* stmw */
2868 static void gen_stmw(DisasContext *ctx)
2869 {
2870 TCGv t0;
2871 TCGv_i32 t1;
2872 gen_set_access_type(ctx, ACCESS_INT);
2873 /* NIP cannot be restored if the memory exception comes from an helper */
2874 gen_update_nip(ctx, ctx->nip - 4);
2875 t0 = tcg_temp_new();
2876 t1 = tcg_const_i32(rS(ctx->opcode));
2877 gen_addr_imm_index(ctx, t0, 0);
2878 gen_helper_stmw(cpu_env, t0, t1);
2879 tcg_temp_free(t0);
2880 tcg_temp_free_i32(t1);
2881 }
2882
2883 /*** Integer load and store strings ***/
2884
2885 /* lswi */
2886 /* PowerPC32 specification says we must generate an exception if
2887 * rA is in the range of registers to be loaded.
2888 * In an other hand, IBM says this is valid, but rA won't be loaded.
2889 * For now, I'll follow the spec...
2890 */
2891 static void gen_lswi(DisasContext *ctx)
2892 {
2893 TCGv t0;
2894 TCGv_i32 t1, t2;
2895 int nb = NB(ctx->opcode);
2896 int start = rD(ctx->opcode);
2897 int ra = rA(ctx->opcode);
2898 int nr;
2899
2900 if (nb == 0)
2901 nb = 32;
2902 nr = nb / 4;
2903 if (unlikely(((start + nr) > 32 &&
2904 start <= ra && (start + nr - 32) > ra) ||
2905 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2906 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2907 return;
2908 }
2909 gen_set_access_type(ctx, ACCESS_INT);
2910 /* NIP cannot be restored if the memory exception comes from an helper */
2911 gen_update_nip(ctx, ctx->nip - 4);
2912 t0 = tcg_temp_new();
2913 gen_addr_register(ctx, t0);
2914 t1 = tcg_const_i32(nb);
2915 t2 = tcg_const_i32(start);
2916 gen_helper_lsw(cpu_env, t0, t1, t2);
2917 tcg_temp_free(t0);
2918 tcg_temp_free_i32(t1);
2919 tcg_temp_free_i32(t2);
2920 }
2921
2922 /* lswx */
2923 static void gen_lswx(DisasContext *ctx)
2924 {
2925 TCGv t0;
2926 TCGv_i32 t1, t2, t3;
2927 gen_set_access_type(ctx, ACCESS_INT);
2928 /* NIP cannot be restored if the memory exception comes from an helper */
2929 gen_update_nip(ctx, ctx->nip - 4);
2930 t0 = tcg_temp_new();
2931 gen_addr_reg_index(ctx, t0);
2932 t1 = tcg_const_i32(rD(ctx->opcode));
2933 t2 = tcg_const_i32(rA(ctx->opcode));
2934 t3 = tcg_const_i32(rB(ctx->opcode));
2935 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2936 tcg_temp_free(t0);
2937 tcg_temp_free_i32(t1);
2938 tcg_temp_free_i32(t2);
2939 tcg_temp_free_i32(t3);
2940 }
2941
2942 /* stswi */
2943 static void gen_stswi(DisasContext *ctx)
2944 {
2945 TCGv t0;
2946 TCGv_i32 t1, t2;
2947 int nb = NB(ctx->opcode);
2948 gen_set_access_type(ctx, ACCESS_INT);
2949 /* NIP cannot be restored if the memory exception comes from an helper */
2950 gen_update_nip(ctx, ctx->nip - 4);
2951 t0 = tcg_temp_new();
2952 gen_addr_register(ctx, t0);
2953 if (nb == 0)
2954 nb = 32;
2955 t1 = tcg_const_i32(nb);
2956 t2 = tcg_const_i32(rS(ctx->opcode));
2957 gen_helper_stsw(cpu_env, t0, t1, t2);
2958 tcg_temp_free(t0);
2959 tcg_temp_free_i32(t1);
2960 tcg_temp_free_i32(t2);
2961 }
2962
2963 /* stswx */
2964 static void gen_stswx(DisasContext *ctx)
2965 {
2966 TCGv t0;
2967 TCGv_i32 t1, t2;
2968 gen_set_access_type(ctx, ACCESS_INT);
2969 /* NIP cannot be restored if the memory exception comes from an helper */
2970 gen_update_nip(ctx, ctx->nip - 4);
2971 t0 = tcg_temp_new();
2972 gen_addr_reg_index(ctx, t0);
2973 t1 = tcg_temp_new_i32();
2974 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2975 tcg_gen_andi_i32(t1, t1, 0x7F);
2976 t2 = tcg_const_i32(rS(ctx->opcode));
2977 gen_helper_stsw(cpu_env, t0, t1, t2);
2978 tcg_temp_free(t0);
2979 tcg_temp_free_i32(t1);
2980 tcg_temp_free_i32(t2);
2981 }
2982
2983 /*** Memory synchronisation ***/
2984 /* eieio */
2985 static void gen_eieio(DisasContext *ctx)
2986 {
2987 }
2988
2989 /* isync */
2990 static void gen_isync(DisasContext *ctx)
2991 {
2992 gen_stop_exception(ctx);
2993 }
2994
2995 /* lwarx */
2996 static void gen_lwarx(DisasContext *ctx)
2997 {
2998 TCGv t0;
2999 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3000 gen_set_access_type(ctx, ACCESS_RES);
3001 t0 = tcg_temp_local_new();
3002 gen_addr_reg_index(ctx, t0);
3003 gen_check_align(ctx, t0, 0x03);
3004 gen_qemu_ld32u(ctx, gpr, t0);
3005 tcg_gen_mov_tl(cpu_reserve, t0);
3006 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3007 tcg_temp_free(t0);
3008 }
3009
3010 #if defined(CONFIG_USER_ONLY)
3011 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3012 int reg, int size)
3013 {
3014 TCGv t0 = tcg_temp_new();
3015 uint32_t save_exception = ctx->exception;
3016
3017 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3018 tcg_gen_movi_tl(t0, (size << 5) | reg);
3019 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3020 tcg_temp_free(t0);
3021 gen_update_nip(ctx, ctx->nip-4);
3022 ctx->exception = POWERPC_EXCP_BRANCH;
3023 gen_exception(ctx, POWERPC_EXCP_STCX);
3024 ctx->exception = save_exception;
3025 }
3026 #endif
3027
3028 /* stwcx. */
3029 static void gen_stwcx_(DisasContext *ctx)
3030 {
3031 TCGv t0;
3032 gen_set_access_type(ctx, ACCESS_RES);
3033 t0 = tcg_temp_local_new();
3034 gen_addr_reg_index(ctx, t0);
3035 gen_check_align(ctx, t0, 0x03);
3036 #if defined(CONFIG_USER_ONLY)
3037 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3038 #else
3039 {
3040 int l1;
3041
3042 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3043 l1 = gen_new_label();
3044 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3045 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3046 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3047 gen_set_label(l1);
3048 tcg_gen_movi_tl(cpu_reserve, -1);
3049 }
3050 #endif
3051 tcg_temp_free(t0);
3052 }
3053
3054 #if defined(TARGET_PPC64)
3055 /* ldarx */
3056 static void gen_ldarx(DisasContext *ctx)
3057 {
3058 TCGv t0;
3059 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3060 gen_set_access_type(ctx, ACCESS_RES);
3061 t0 = tcg_temp_local_new();
3062 gen_addr_reg_index(ctx, t0);
3063 gen_check_align(ctx, t0, 0x07);
3064 gen_qemu_ld64(ctx, gpr, t0);
3065 tcg_gen_mov_tl(cpu_reserve, t0);
3066 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3067 tcg_temp_free(t0);
3068 }
3069
3070 /* stdcx. */
3071 static void gen_stdcx_(DisasContext *ctx)
3072 {
3073 TCGv t0;
3074 gen_set_access_type(ctx, ACCESS_RES);
3075 t0 = tcg_temp_local_new();
3076 gen_addr_reg_index(ctx, t0);
3077 gen_check_align(ctx, t0, 0x07);
3078 #if defined(CONFIG_USER_ONLY)
3079 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3080 #else
3081 {
3082 int l1;
3083 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3084 l1 = gen_new_label();
3085 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3086 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3087 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3088 gen_set_label(l1);
3089 tcg_gen_movi_tl(cpu_reserve, -1);
3090 }
3091 #endif
3092 tcg_temp_free(t0);
3093 }
3094 #endif /* defined(TARGET_PPC64) */
3095
3096 /* sync */
3097 static void gen_sync(DisasContext *ctx)
3098 {
3099 }
3100
3101 /* wait */
3102 static void gen_wait(DisasContext *ctx)
3103 {
3104 TCGv_i32 t0 = tcg_temp_new_i32();
3105 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
3106 tcg_temp_free_i32(t0);
3107 /* Stop translation, as the CPU is supposed to sleep from now */
3108 gen_exception_err(ctx, EXCP_HLT, 1);
3109 }
3110
3111 /*** Floating-point load ***/
3112 #define GEN_LDF(name, ldop, opc, type) \
3113 static void glue(gen_, name)(DisasContext *ctx) \
3114 { \
3115 TCGv EA; \
3116 if (unlikely(!ctx->fpu_enabled)) { \
3117 gen_exception(ctx, POWERPC_EXCP_FPU); \
3118 return; \
3119 } \
3120 gen_set_access_type(ctx, ACCESS_FLOAT); \
3121 EA = tcg_temp_new(); \
3122 gen_addr_imm_index(ctx, EA, 0); \
3123 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3124 tcg_temp_free(EA); \
3125 }
3126
3127 #define GEN_LDUF(name, ldop, opc, type) \
3128 static void glue(gen_, name##u)(DisasContext *ctx) \
3129 { \
3130 TCGv EA; \
3131 if (unlikely(!ctx->fpu_enabled)) { \
3132 gen_exception(ctx, POWERPC_EXCP_FPU); \
3133 return; \
3134 } \
3135 if (unlikely(rA(ctx->opcode) == 0)) { \
3136 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3137 return; \
3138 } \
3139 gen_set_access_type(ctx, ACCESS_FLOAT); \
3140 EA = tcg_temp_new(); \
3141 gen_addr_imm_index(ctx, EA, 0); \
3142 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3143 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3144 tcg_temp_free(EA); \
3145 }
3146
3147 #define GEN_LDUXF(name, ldop, opc, type) \
3148 static void glue(gen_, name##ux)(DisasContext *ctx) \
3149 { \
3150 TCGv EA; \
3151 if (unlikely(!ctx->fpu_enabled)) { \
3152 gen_exception(ctx, POWERPC_EXCP_FPU); \
3153 return; \
3154 } \
3155 if (unlikely(rA(ctx->opcode) == 0)) { \
3156 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3157 return; \
3158 } \
3159 gen_set_access_type(ctx, ACCESS_FLOAT); \
3160 EA = tcg_temp_new(); \
3161 gen_addr_reg_index(ctx, EA); \
3162 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3163 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3164 tcg_temp_free(EA); \
3165 }
3166
3167 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3168 static void glue(gen_, name##x)(DisasContext *ctx) \
3169 { \
3170 TCGv EA; \
3171 if (unlikely(!ctx->fpu_enabled)) { \
3172 gen_exception(ctx, POWERPC_EXCP_FPU); \
3173 return; \
3174 } \
3175 gen_set_access_type(ctx, ACCESS_FLOAT); \
3176 EA = tcg_temp_new(); \
3177 gen_addr_reg_index(ctx, EA); \
3178 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3179 tcg_temp_free(EA); \
3180 }
3181
3182 #define GEN_LDFS(name, ldop, op, type) \
3183 GEN_LDF(name, ldop, op | 0x20, type); \
3184 GEN_LDUF(name, ldop, op | 0x21, type); \
3185 GEN_LDUXF(name, ldop, op | 0x01, type); \
3186 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3187
3188 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3189 {
3190 TCGv t0 = tcg_temp_new();
3191 TCGv_i32 t1 = tcg_temp_new_i32();
3192 gen_qemu_ld32u(ctx, t0, arg2);
3193 tcg_gen_trunc_tl_i32(t1, t0);
3194 tcg_temp_free(t0);
3195 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3196 tcg_temp_free_i32(t1);
3197 }
3198
3199 /* lfd lfdu lfdux lfdx */
3200 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3201 /* lfs lfsu lfsux lfsx */
3202 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3203
3204 /*** Floating-point store ***/
3205 #define GEN_STF(name, stop, opc, type) \
3206 static void glue(gen_, name)(DisasContext *ctx) \
3207 { \
3208 TCGv EA; \
3209 if (unlikely(!ctx->fpu_enabled)) { \
3210 gen_exception(ctx, POWERPC_EXCP_FPU); \
3211 return; \
3212 } \
3213 gen_set_access_type(ctx, ACCESS_FLOAT); \
3214 EA = tcg_temp_new(); \
3215 gen_addr_imm_index(ctx, EA, 0); \
3216 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3217 tcg_temp_free(EA); \
3218 }
3219
3220 #define GEN_STUF(name, stop, opc, type) \
3221 static void glue(gen_, name##u)(DisasContext *ctx) \
3222 { \
3223 TCGv EA; \
3224 if (unlikely(!ctx->fpu_enabled)) { \
3225 gen_exception(ctx, POWERPC_EXCP_FPU); \
3226 return; \
3227 } \
3228 if (unlikely(rA(ctx->opcode) == 0)) { \
3229 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3230 return; \
3231 } \
3232 gen_set_access_type(ctx, ACCESS_FLOAT); \
3233 EA = tcg_temp_new(); \
3234 gen_addr_imm_index(ctx, EA, 0); \
3235 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3236 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3237 tcg_temp_free(EA); \
3238 }
3239
3240 #define GEN_STUXF(name, stop, opc, type) \
3241 static void glue(gen_, name##ux)(DisasContext *ctx) \
3242 { \
3243 TCGv EA; \
3244 if (unlikely(!ctx->fpu_enabled)) { \
3245 gen_exception(ctx, POWERPC_EXCP_FPU); \
3246 return; \
3247 } \
3248 if (unlikely(rA(ctx->opcode) == 0)) { \
3249 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3250 return; \
3251 } \
3252 gen_set_access_type(ctx, ACCESS_FLOAT); \
3253 EA = tcg_temp_new(); \
3254 gen_addr_reg_index(ctx, EA); \
3255 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3256 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3257 tcg_temp_free(EA); \
3258 }
3259
3260 #define GEN_STXF(name, stop, opc2, opc3, type) \
3261 static void glue(gen_, name##x)(DisasContext *ctx) \
3262 { \
3263 TCGv EA; \
3264 if (unlikely(!ctx->fpu_enabled)) { \
3265 gen_exception(ctx, POWERPC_EXCP_FPU); \
3266 return; \
3267 } \
3268 gen_set_access_type(ctx, ACCESS_FLOAT); \
3269 EA = tcg_temp_new(); \
3270 gen_addr_reg_index(ctx, EA); \
3271 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3272 tcg_temp_free(EA); \
3273 }
3274
3275 #define GEN_STFS(name, stop, op, type) \
3276 GEN_STF(name, stop, op | 0x20, type); \
3277 GEN_STUF(name, stop, op | 0x21, type); \
3278 GEN_STUXF(name, stop, op | 0x01, type); \
3279 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3280
3281 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3282 {
3283 TCGv_i32 t0 = tcg_temp_new_i32();
3284 TCGv t1 = tcg_temp_new();
3285 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3286 tcg_gen_extu_i32_tl(t1, t0);
3287 tcg_temp_free_i32(t0);
3288 gen_qemu_st32(ctx, t1, arg2);
3289 tcg_temp_free(t1);
3290 }
3291
3292 /* stfd stfdu stfdux stfdx */
3293 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3294 /* stfs stfsu stfsux stfsx */
3295 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3296
3297 /* Optional: */
3298 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3299 {
3300 TCGv t0 = tcg_temp_new();
3301 tcg_gen_trunc_i64_tl(t0, arg1),
3302 gen_qemu_st32(ctx, t0, arg2);
3303 tcg_temp_free(t0);
3304 }
3305 /* stfiwx */
3306 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3307
3308 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3309 {
3310 #if defined(TARGET_PPC64)
3311 if (ctx->has_cfar)
3312 tcg_gen_movi_tl(cpu_cfar, nip);
3313 #endif
3314 }
3315
3316 /*** Branch ***/
3317 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3318 {
3319 TranslationBlock *tb;
3320 tb = ctx->tb;
3321 #if defined(TARGET_PPC64)
3322 if (!ctx->sf_mode)
3323 dest = (uint32_t) dest;
3324 #endif
3325 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3326 likely(!ctx->singlestep_enabled)) {
3327 tcg_gen_goto_tb(n);
3328 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3329 tcg_gen_exit_tb((tcg_target_long)tb + n);
3330 } else {
3331 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3332 if (unlikely(ctx->singlestep_enabled)) {
3333 if ((ctx->singlestep_enabled &
3334 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3335 (ctx->exception == POWERPC_EXCP_BRANCH ||
3336 ctx->exception == POWERPC_EXCP_TRACE)) {
3337 target_ulong tmp = ctx->nip;
3338 ctx->nip = dest;
3339 gen_exception(ctx, POWERPC_EXCP_TRACE);
3340 ctx->nip = tmp;
3341 }
3342 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3343 gen_debug_exception(ctx);
3344 }
3345 }
3346 tcg_gen_exit_tb(0);
3347 }
3348 }
3349
3350 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3351 {
3352 #if defined(TARGET_PPC64)
3353 if (ctx->sf_mode == 0)
3354 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3355 else
3356 #endif
3357 tcg_gen_movi_tl(cpu_lr, nip);
3358 }
3359
3360 /* b ba bl bla */
3361 static void gen_b(DisasContext *ctx)
3362 {
3363 target_ulong li, target;
3364
3365 ctx->exception = POWERPC_EXCP_BRANCH;
3366 /* sign extend LI */
3367 #if defined(TARGET_PPC64)
3368 if (ctx->sf_mode)
3369 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3370 else
3371 #endif
3372 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3373 if (likely(AA(ctx->opcode) == 0))
3374 target = ctx->nip + li - 4;
3375 else
3376 target = li;
3377 if (LK(ctx->opcode))
3378 gen_setlr(ctx, ctx->nip);
3379 gen_update_cfar(ctx, ctx->nip);
3380 gen_goto_tb(ctx, 0, target);
3381 }
3382
3383 #define BCOND_IM 0
3384 #define BCOND_LR 1
3385 #define BCOND_CTR 2
3386
3387 static inline void gen_bcond(DisasContext *ctx, int type)
3388 {
3389 uint32_t bo = BO(ctx->opcode);
3390 int l1;
3391 TCGv target;
3392
3393 ctx->exception = POWERPC_EXCP_BRANCH;
3394 if (type == BCOND_LR || type == BCOND_CTR) {
3395 target = tcg_temp_local_new();
3396 if (type == BCOND_CTR)
3397 tcg_gen_mov_tl(target, cpu_ctr);
3398 else
3399 tcg_gen_mov_tl(target, cpu_lr);
3400 } else {
3401 TCGV_UNUSED(target);
3402 }
3403 if (LK(ctx->opcode))
3404 gen_setlr(ctx, ctx->nip);
3405 l1 = gen_new_label();
3406 if ((bo & 0x4) == 0) {
3407 /* Decrement and test CTR */
3408 TCGv temp = tcg_temp_new();
3409 if (unlikely(type == BCOND_CTR)) {
3410 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3411 return;
3412 }
3413 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3414 #if defined(TARGET_PPC64)
3415 if (!ctx->sf_mode)
3416 tcg_gen_ext32u_tl(temp, cpu_ctr);
3417 else
3418 #endif
3419 tcg_gen_mov_tl(temp, cpu_ctr);
3420 if (bo & 0x2) {
3421 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3422 } else {
3423 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3424 }
3425 tcg_temp_free(temp);
3426 }
3427 if ((bo & 0x10) == 0) {
3428 /* Test CR */
3429 uint32_t bi = BI(ctx->opcode);
3430 uint32_t mask = 1 << (3 - (bi & 0x03));
3431 TCGv_i32 temp = tcg_temp_new_i32();
3432
3433 if (bo & 0x8) {
3434 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3435 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3436 } else {
3437 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3438 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3439 }
3440 tcg_temp_free_i32(temp);
3441 }
3442 gen_update_cfar(ctx, ctx->nip);
3443 if (type == BCOND_IM) {
3444 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3445 if (likely(AA(ctx->opcode) == 0)) {
3446 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3447 } else {
3448 gen_goto_tb(ctx, 0, li);
3449 }
3450 gen_set_label(l1);
3451 gen_goto_tb(ctx, 1, ctx->nip);
3452 } else {
3453 #if defined(TARGET_PPC64)
3454 if (!(ctx->sf_mode))
3455 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3456 else
3457 #endif
3458 tcg_gen_andi_tl(cpu_nip, target, ~3);
3459 tcg_gen_exit_tb(0);
3460 gen_set_label(l1);
3461 #if defined(TARGET_PPC64)
3462 if (!(ctx->sf_mode))
3463 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3464 else
3465 #endif
3466 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3467 tcg_gen_exit_tb(0);
3468 }
3469 }
3470
3471 static void gen_bc(DisasContext *ctx)
3472 {
3473 gen_bcond(ctx, BCOND_IM);
3474 }
3475
3476 static void gen_bcctr(DisasContext *ctx)
3477 {
3478 gen_bcond(ctx, BCOND_CTR);
3479 }
3480
3481 static void gen_bclr(DisasContext *ctx)
3482 {
3483 gen_bcond(ctx, BCOND_LR);
3484 }
3485
3486 /*** Condition register logical ***/
3487 #define GEN_CRLOGIC(name, tcg_op, opc) \
3488 static void glue(gen_, name)(DisasContext *ctx) \
3489 { \
3490 uint8_t bitmask; \
3491 int sh; \
3492 TCGv_i32 t0, t1; \
3493 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3494 t0 = tcg_temp_new_i32(); \
3495 if (sh > 0) \
3496 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3497 else if (sh < 0) \
3498 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3499 else \
3500 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3501 t1 = tcg_temp_new_i32(); \
3502 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3503 if (sh > 0) \
3504 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3505 else if (sh < 0) \
3506 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3507 else \
3508 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3509 tcg_op(t0, t0, t1); \
3510 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3511 tcg_gen_andi_i32(t0, t0, bitmask); \
3512 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3513 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3514 tcg_temp_free_i32(t0); \
3515 tcg_temp_free_i32(t1); \
3516 }
3517
3518 /* crand */
3519 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3520 /* crandc */
3521 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3522 /* creqv */
3523 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3524 /* crnand */
3525 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3526 /* crnor */
3527 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3528 /* cror */
3529 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3530 /* crorc */
3531 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3532 /* crxor */
3533 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3534
3535 /* mcrf */
3536 static void gen_mcrf(DisasContext *ctx)
3537 {
3538 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3539 }
3540
3541 /*** System linkage ***/
3542
3543 /* rfi (mem_idx only) */
3544 static void gen_rfi(DisasContext *ctx)
3545 {
3546 #if defined(CONFIG_USER_ONLY)
3547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3548 #else
3549 /* Restore CPU state */
3550 if (unlikely(!ctx->mem_idx)) {
3551 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3552 return;
3553 }
3554 gen_update_cfar(ctx, ctx->nip);
3555 gen_helper_rfi(cpu_env);
3556 gen_sync_exception(ctx);
3557 #endif
3558 }
3559
3560 #if defined(TARGET_PPC64)
3561 static void gen_rfid(DisasContext *ctx)
3562 {
3563 #if defined(CONFIG_USER_ONLY)
3564 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3565 #else
3566 /* Restore CPU state */
3567 if (unlikely(!ctx->mem_idx)) {
3568 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3569 return;
3570 }
3571 gen_update_cfar(ctx, ctx->nip);
3572 gen_helper_rfid(cpu_env);
3573 gen_sync_exception(ctx);
3574 #endif
3575 }
3576
3577 static void gen_hrfid(DisasContext *ctx)
3578 {
3579 #if defined(CONFIG_USER_ONLY)
3580 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3581 #else
3582 /* Restore CPU state */
3583 if (unlikely(ctx->mem_idx <= 1)) {
3584 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3585 return;
3586 }
3587 gen_helper_hrfid(cpu_env);
3588 gen_sync_exception(ctx);
3589 #endif
3590 }
3591 #endif
3592
3593 /* sc */
3594 #if defined(CONFIG_USER_ONLY)
3595 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3596 #else
3597 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3598 #endif
3599 static void gen_sc(DisasContext *ctx)
3600 {
3601 uint32_t lev;
3602
3603 lev = (ctx->opcode >> 5) & 0x7F;
3604 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3605 }
3606
3607 /*** Trap ***/
3608
3609 /* tw */
3610 static void gen_tw(DisasContext *ctx)
3611 {
3612 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3613 /* Update the nip since this might generate a trap exception */
3614 gen_update_nip(ctx, ctx->nip);
3615 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3616 t0);
3617 tcg_temp_free_i32(t0);
3618 }
3619
3620 /* twi */
3621 static void gen_twi(DisasContext *ctx)
3622 {
3623 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3624 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3625 /* Update the nip since this might generate a trap exception */
3626 gen_update_nip(ctx, ctx->nip);
3627 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3628 tcg_temp_free(t0);
3629 tcg_temp_free_i32(t1);
3630 }
3631
3632 #if defined(TARGET_PPC64)
3633 /* td */
3634 static void gen_td(DisasContext *ctx)
3635 {
3636 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3637 /* Update the nip since this might generate a trap exception */
3638 gen_update_nip(ctx, ctx->nip);
3639 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3640 t0);
3641 tcg_temp_free_i32(t0);
3642 }
3643
3644 /* tdi */
3645 static void gen_tdi(DisasContext *ctx)
3646 {
3647 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3648 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3649 /* Update the nip since this might generate a trap exception */
3650 gen_update_nip(ctx, ctx->nip);
3651 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3652 tcg_temp_free(t0);
3653 tcg_temp_free_i32(t1);
3654 }
3655 #endif
3656
3657 /*** Processor control ***/
3658
3659 static void gen_read_xer(TCGv dst)
3660 {
3661 TCGv t0 = tcg_temp_new();
3662 TCGv t1 = tcg_temp_new();
3663 TCGv t2 = tcg_temp_new();
3664 tcg_gen_mov_tl(dst, cpu_xer);
3665 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3666 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3667 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3668 tcg_gen_or_tl(t0, t0, t1);
3669 tcg_gen_or_tl(dst, dst, t2);
3670 tcg_gen_or_tl(dst, dst, t0);
3671 tcg_temp_free(t0);
3672 tcg_temp_free(t1);
3673 tcg_temp_free(t2);
3674 }
3675
3676 static void gen_write_xer(TCGv src)
3677 {
3678 tcg_gen_andi_tl(cpu_xer, src,
3679 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3680 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3681 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3682 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3683 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3684 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3685 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3686 }
3687
3688 /* mcrxr */
3689 static void gen_mcrxr(DisasContext *ctx)
3690 {
3691 TCGv_i32 t0 = tcg_temp_new_i32();
3692 TCGv_i32 t1 = tcg_temp_new_i32();
3693 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3694
3695 tcg_gen_trunc_tl_i32(t0, cpu_so);
3696 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3697 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3698 tcg_gen_shri_i32(t0, t0, 2);
3699 tcg_gen_shri_i32(t1, t1, 1);
3700 tcg_gen_or_i32(dst, dst, t0);
3701 tcg_gen_or_i32(dst, dst, t1);
3702 tcg_temp_free_i32(t0);
3703 tcg_temp_free_i32(t1);
3704
3705 tcg_gen_movi_tl(cpu_so, 0);
3706 tcg_gen_movi_tl(cpu_ov, 0);
3707 tcg_gen_movi_tl(cpu_ca, 0);
3708 }
3709
3710 /* mfcr mfocrf */
3711 static void gen_mfcr(DisasContext *ctx)
3712 {
3713 uint32_t crm, crn;
3714
3715 if (likely(ctx->opcode & 0x00100000)) {
3716 crm = CRM(ctx->opcode);
3717 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3718 crn = ctz32 (crm);
3719 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3720 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3721 cpu_gpr[rD(ctx->opcode)], crn * 4);
3722 }
3723 } else {
3724 TCGv_i32 t0 = tcg_temp_new_i32();
3725 tcg_gen_mov_i32(t0, cpu_crf[0]);
3726 tcg_gen_shli_i32(t0, t0, 4);
3727 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3728 tcg_gen_shli_i32(t0, t0, 4);
3729 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3730 tcg_gen_shli_i32(t0, t0, 4);
3731 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3732 tcg_gen_shli_i32(t0, t0, 4);
3733 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3734 tcg_gen_shli_i32(t0, t0, 4);
3735 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3736 tcg_gen_shli_i32(t0, t0, 4);
3737 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3738 tcg_gen_shli_i32(t0, t0, 4);
3739 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3740 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3741 tcg_temp_free_i32(t0);
3742 }
3743 }
3744
3745 /* mfmsr */
3746 static void gen_mfmsr(DisasContext *ctx)
3747 {
3748 #if defined(CONFIG_USER_ONLY)
3749 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3750 #else
3751 if (unlikely(!ctx->mem_idx)) {
3752 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3753 return;
3754 }
3755 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3756 #endif
3757 }
3758
3759 static void spr_noaccess(void *opaque, int gprn, int sprn)
3760 {
3761 #if 0
3762 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3763 printf("ERROR: try to access SPR %d !\n", sprn);
3764 #endif
3765 }
3766 #define SPR_NOACCESS (&spr_noaccess)
3767
3768 /* mfspr */
3769 static inline void gen_op_mfspr(DisasContext *ctx)
3770 {
3771 void (*read_cb)(void *opaque, int gprn, int sprn);
3772 uint32_t sprn = SPR(ctx->opcode);
3773
3774 #if !defined(CONFIG_USER_ONLY)
3775 if (ctx->mem_idx == 2)
3776 read_cb = ctx->spr_cb[sprn].hea_read;
3777 else if (ctx->mem_idx)
3778 read_cb = ctx->spr_cb[sprn].oea_read;
3779 else
3780 #endif
3781 read_cb = ctx->spr_cb[sprn].uea_read;
3782 if (likely(read_cb != NULL)) {
3783 if (likely(read_cb != SPR_NOACCESS)) {
3784 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3785 } else {
3786 /* Privilege exception */
3787 /* This is a hack to avoid warnings when running Linux:
3788 * this OS breaks the PowerPC virtualisation model,
3789 * allowing userland application to read the PVR
3790 */
3791 if (sprn != SPR_PVR) {
3792 qemu_log("Trying to read privileged spr %d %03x at "
3793 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3794 printf("Trying to read privileged spr %d %03x at "
3795 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3796 }
3797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3798 }
3799 } else {
3800 /* Not defined */
3801 qemu_log("Trying to read invalid spr %d %03x at "
3802 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3803 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3804 sprn, sprn, ctx->nip);
3805 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3806 }
3807 }
3808
3809 static void gen_mfspr(DisasContext *ctx)
3810 {
3811 gen_op_mfspr(ctx);
3812 }
3813
3814 /* mftb */
3815 static void gen_mftb(DisasContext *ctx)
3816 {
3817 gen_op_mfspr(ctx);
3818 }
3819
3820 /* mtcrf mtocrf*/
3821 static void gen_mtcrf(DisasContext *ctx)
3822 {
3823 uint32_t crm, crn;
3824
3825 crm = CRM(ctx->opcode);
3826 if (likely((ctx->opcode & 0x00100000))) {
3827 if (crm && ((crm & (crm - 1)) == 0)) {
3828 TCGv_i32 temp = tcg_temp_new_i32();
3829 crn = ctz32 (crm);
3830 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3831 tcg_gen_shri_i32(temp, temp, crn * 4);
3832 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3833 tcg_temp_free_i32(temp);
3834 }
3835 } else {
3836 TCGv_i32 temp = tcg_temp_new_i32();
3837 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3838 for (crn = 0 ; crn < 8 ; crn++) {
3839 if (crm & (1 << crn)) {
3840 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3841 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3842 }
3843 }
3844 tcg_temp_free_i32(temp);
3845 }
3846 }
3847
3848 /* mtmsr */
3849 #if defined(TARGET_PPC64)
3850 static void gen_mtmsrd(DisasContext *ctx)
3851 {
3852 #if defined(CONFIG_USER_ONLY)
3853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3854 #else
3855 if (unlikely(!ctx->mem_idx)) {
3856 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3857 return;
3858 }
3859 if (ctx->opcode & 0x00010000) {
3860 /* Special form that does not need any synchronisation */
3861 TCGv t0 = tcg_temp_new();
3862 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3863 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3864 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3865 tcg_temp_free(t0);
3866 } else {
3867 /* XXX: we need to update nip before the store
3868 * if we enter power saving mode, we will exit the loop
3869 * directly from ppc_store_msr
3870 */
3871 gen_update_nip(ctx, ctx->nip);
3872 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3873 /* Must stop the translation as machine state (may have) changed */
3874 /* Note that mtmsr is not always defined as context-synchronizing */
3875 gen_stop_exception(ctx);
3876 }
3877 #endif
3878 }
3879 #endif
3880
3881 static void gen_mtmsr(DisasContext *ctx)
3882 {
3883 #if defined(CONFIG_USER_ONLY)
3884 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3885 #else
3886 if (unlikely(!ctx->mem_idx)) {
3887 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3888 return;
3889 }
3890 if (ctx->opcode & 0x00010000) {
3891 /* Special form that does not need any synchronisation */
3892 TCGv t0 = tcg_temp_new();
3893 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3894 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3895 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3896 tcg_temp_free(t0);
3897 } else {
3898 TCGv msr = tcg_temp_new();
3899
3900 /* XXX: we need to update nip before the store
3901 * if we enter power saving mode, we will exit the loop
3902 * directly from ppc_store_msr
3903 */
3904 gen_update_nip(ctx, ctx->nip);
3905 #if defined(TARGET_PPC64)
3906 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3907 #else
3908 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3909 #endif
3910 gen_helper_store_msr(cpu_env, msr);
3911 /* Must stop the translation as machine state (may have) changed */
3912 /* Note that mtmsr is not always defined as context-synchronizing */
3913 gen_stop_exception(ctx);
3914 }
3915 #endif
3916 }
3917
3918 /* mtspr */
3919 static void gen_mtspr(DisasContext *ctx)
3920 {
3921 void (*write_cb)(void *opaque, int sprn, int gprn);
3922 uint32_t sprn = SPR(ctx->opcode);
3923
3924 #if !defined(CONFIG_USER_ONLY)
3925 if (ctx->mem_idx == 2)
3926 write_cb = ctx->spr_cb[sprn].hea_write;
3927 else if (ctx->mem_idx)
3928 write_cb = ctx->spr_cb[sprn].oea_write;
3929 else
3930 #endif
3931 write_cb = ctx->spr_cb[sprn].uea_write;
3932 if (likely(write_cb != NULL)) {
3933 if (likely(write_cb != SPR_NOACCESS)) {
3934 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3935 } else {
3936 /* Privilege exception */
3937 qemu_log("Trying to write privileged spr %d %03x at "
3938 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3939 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3940 "\n", sprn, sprn, ctx->nip);
3941 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3942 }
3943 } else {
3944 /* Not defined */
3945 qemu_log("Trying to write invalid spr %d %03x at "
3946 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3947 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3948 sprn, sprn, ctx->nip);
3949 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3950 }
3951 }
3952
3953 /*** Cache management ***/
3954
3955 /* dcbf */
3956 static void gen_dcbf(DisasContext *ctx)
3957 {
3958 /* XXX: specification says this is treated as a load by the MMU */
3959 TCGv t0;
3960 gen_set_access_type(ctx, ACCESS_CACHE);
3961 t0 = tcg_temp_new();
3962 gen_addr_reg_index(ctx, t0);
3963 gen_qemu_ld8u(ctx, t0, t0);
3964 tcg_temp_free(t0);
3965 }
3966
3967 /* dcbi (Supervisor only) */
3968 static void gen_dcbi(DisasContext *ctx)
3969 {
3970 #if defined(CONFIG_USER_ONLY)
3971 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3972 #else
3973 TCGv EA, val;
3974 if (unlikely(!ctx->mem_idx)) {
3975 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3976 return;
3977 }
3978 EA = tcg_temp_new();
3979 gen_set_access_type(ctx, ACCESS_CACHE);
3980 gen_addr_reg_index(ctx, EA);
3981 val = tcg_temp_new();
3982 /* XXX: specification says this should be treated as a store by the MMU */
3983 gen_qemu_ld8u(ctx, val, EA);
3984 gen_qemu_st8(ctx, val, EA);
3985 tcg_temp_free(val);
3986 tcg_temp_free(EA);
3987 #endif
3988 }
3989
3990 /* dcdst */
3991 static void gen_dcbst(DisasContext *ctx)
3992 {
3993 /* XXX: specification say this is treated as a load by the MMU */
3994 TCGv t0;
3995 gen_set_access_type(ctx, ACCESS_CACHE);
3996 t0 = tcg_temp_new();
3997 gen_addr_reg_index(ctx, t0);
3998 gen_qemu_ld8u(ctx, t0, t0);
3999 tcg_temp_free(t0);
4000 }
4001
4002 /* dcbt */
4003 static void gen_dcbt(DisasContext *ctx)
4004 {
4005 /* interpreted as no-op */
4006 /* XXX: specification say this is treated as a load by the MMU
4007 * but does not generate any exception
4008 */
4009 }
4010
4011 /* dcbtst */
4012 static void gen_dcbtst(DisasContext *ctx)
4013 {
4014 /* interpreted as no-op */
4015 /* XXX: specification say this is treated as a load by the MMU
4016 * but does not generate any exception
4017 */
4018 }
4019
4020 /* dcbz */
4021 static void gen_dcbz(DisasContext *ctx)
4022 {
4023 TCGv tcgv_addr;
4024 TCGv_i32 tcgv_is_dcbzl;
4025 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4026
4027 gen_set_access_type(ctx, ACCESS_CACHE);
4028 /* NIP cannot be restored if the memory exception comes from an helper */
4029 gen_update_nip(ctx, ctx->nip - 4);
4030 tcgv_addr = tcg_temp_new();
4031 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4032
4033 gen_addr_reg_index(ctx, tcgv_addr);
4034 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4035
4036 tcg_temp_free(tcgv_addr);
4037 tcg_temp_free_i32(tcgv_is_dcbzl);
4038 }
4039
4040 /* dst / dstt */
4041 static void gen_dst(DisasContext *ctx)
4042 {
4043 if (rA(ctx->opcode) == 0) {
4044 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4045 } else {
4046 /* interpreted as no-op */
4047 }
4048 }
4049
4050 /* dstst /dststt */
4051 static void gen_dstst(DisasContext *ctx)
4052 {
4053 if (rA(ctx->opcode) == 0) {
4054 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4055 } else {
4056 /* interpreted as no-op */
4057 }
4058
4059 }
4060
4061 /* dss / dssall */
4062 static void gen_dss(DisasContext *ctx)
4063 {
4064 /* interpreted as no-op */
4065 }
4066
4067 /* icbi */
4068 static void gen_icbi(DisasContext *ctx)
4069 {
4070 TCGv t0;
4071 gen_set_access_type(ctx, ACCESS_CACHE);
4072 /* NIP cannot be restored if the memory exception comes from an helper */
4073 gen_update_nip(ctx, ctx->nip - 4);
4074 t0 = tcg_temp_new();
4075 gen_addr_reg_index(ctx, t0);
4076 gen_helper_icbi(cpu_env, t0);
4077 tcg_temp_free(t0);
4078 }
4079
4080 /* Optional: */
4081 /* dcba */
4082 static void gen_dcba(DisasContext *ctx)
4083 {
4084 /* interpreted as no-op */
4085 /* XXX: specification say this is treated as a store by the MMU
4086 * but does not generate any exception
4087 */
4088 }
4089
4090 /*** Segment register manipulation ***/
4091 /* Supervisor only: */
4092
4093 /* mfsr */
4094 static void gen_mfsr(DisasContext *ctx)
4095 {
4096 #if defined(CONFIG_USER_ONLY)
4097 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4098 #else
4099 TCGv t0;
4100 if (unlikely(!ctx->mem_idx)) {
4101 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4102 return;
4103 }
4104 t0 = tcg_const_tl(SR(ctx->opcode));
4105 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4106 tcg_temp_free(t0);
4107 #endif
4108 }
4109
4110 /* mfsrin */
4111 static void gen_mfsrin(DisasContext *ctx)
4112 {
4113 #if defined(CONFIG_USER_ONLY)
4114 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4115 #else
4116 TCGv t0;
4117 if (unlikely(!ctx->mem_idx)) {
4118 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4119 return;
4120 }
4121 t0 = tcg_temp_new();
4122 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4123 tcg_gen_andi_tl(t0, t0, 0xF);
4124 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4125 tcg_temp_free(t0);
4126 #endif
4127 }
4128
4129 /* mtsr */
4130 static void gen_mtsr(DisasContext *ctx)
4131 {
4132 #if defined(CONFIG_USER_ONLY)
4133 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4134 #else
4135 TCGv t0;
4136 if (unlikely(!ctx->mem_idx)) {
4137 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4138 return;
4139 }
4140 t0 = tcg_const_tl(SR(ctx->opcode));
4141 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4142 tcg_temp_free(t0);
4143 #endif
4144 }
4145
4146 /* mtsrin */
4147 static void gen_mtsrin(DisasContext *ctx)
4148 {
4149 #if defined(CONFIG_USER_ONLY)
4150 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4151 #else
4152 TCGv t0;
4153 if (unlikely(!ctx->mem_idx)) {
4154 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4155 return;
4156 }
4157 t0 = tcg_temp_new();
4158 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4159 tcg_gen_andi_tl(t0, t0, 0xF);
4160 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4161 tcg_temp_free(t0);
4162 #endif
4163 }
4164
4165 #if defined(TARGET_PPC64)
4166 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4167
4168 /* mfsr */
4169 static void gen_mfsr_64b(DisasContext *ctx)
4170 {
4171 #if defined(CONFIG_USER_ONLY)
4172 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4173 #else
4174 TCGv t0;
4175 if (unlikely(!ctx->mem_idx)) {
4176 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4177 return;
4178 }
4179 t0 = tcg_const_tl(SR(ctx->opcode));
4180 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4181 tcg_temp_free(t0);
4182 #endif
4183 }
4184
4185 /* mfsrin */
4186 static void gen_mfsrin_64b(DisasContext *ctx)
4187 {
4188 #if defined(CONFIG_USER_ONLY)
4189 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4190 #else
4191 TCGv t0;
4192 if (unlikely(!ctx->mem_idx)) {
4193 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4194 return;
4195 }
4196 t0 = tcg_temp_new();
4197 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4198 tcg_gen_andi_tl(t0, t0, 0xF);
4199 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4200 tcg_temp_free(t0);
4201 #endif
4202 }
4203
4204 /* mtsr */
4205 static void gen_mtsr_64b(DisasContext *ctx)
4206 {
4207 #if defined(CONFIG_USER_ONLY)
4208 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4209 #else
4210 TCGv t0;
4211 if (unlikely(!ctx->mem_idx)) {
4212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4213 return;
4214 }
4215 t0 = tcg_const_tl(SR(ctx->opcode));
4216 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4217 tcg_temp_free(t0);
4218 #endif
4219 }
4220
4221 /* mtsrin */
4222 static void gen_mtsrin_64b(DisasContext *ctx)
4223 {
4224 #if defined(CONFIG_USER_ONLY)
4225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4226 #else
4227 TCGv t0;
4228 if (unlikely(!ctx->mem_idx)) {
4229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4230 return;
4231 }
4232 t0 = tcg_temp_new();
4233 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4234 tcg_gen_andi_tl(t0, t0, 0xF);
4235 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4236 tcg_temp_free(t0);
4237 #endif
4238 }
4239
4240 /* slbmte */
4241 static void gen_slbmte(DisasContext *ctx)
4242 {
4243 #if defined(CONFIG_USER_ONLY)
4244 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4245 #else
4246 if (unlikely(!ctx->mem_idx)) {
4247 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4248 return;
4249 }
4250 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4251 cpu_gpr[rS(ctx->opcode)]);
4252 #endif
4253 }
4254
4255 static void gen_slbmfee(DisasContext *ctx)
4256 {
4257 #if defined(CONFIG_USER_ONLY)
4258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4259 #else
4260 if (unlikely(!ctx->mem_idx)) {
4261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4262 return;
4263 }
4264 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4265 cpu_gpr[rB(ctx->opcode)]);
4266 #endif
4267 }
4268
4269 static void gen_slbmfev(DisasContext *ctx)
4270 {
4271 #if defined(CONFIG_USER_ONLY)
4272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4273 #else
4274 if (unlikely(!ctx->mem_idx)) {
4275 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4276 return;
4277 }
4278 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4279 cpu_gpr[rB(ctx->opcode)]);
4280 #endif
4281 }
4282 #endif /* defined(TARGET_PPC64) */
4283
4284 /*** Lookaside buffer management ***/
4285 /* Optional & mem_idx only: */
4286
4287 /* tlbia */
4288 static void gen_tlbia(DisasContext *ctx)
4289 {
4290 #if defined(CONFIG_USER_ONLY)
4291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4292 #else
4293 if (unlikely(!ctx->mem_idx)) {
4294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4295 return;
4296 }
4297 gen_helper_tlbia(cpu_env);
4298 #endif
4299 }
4300
4301 /* tlbiel */
4302 static void gen_tlbiel(DisasContext *ctx)
4303 {
4304 #if defined(CONFIG_USER_ONLY)
4305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4306 #else
4307 if (unlikely(!ctx->mem_idx)) {
4308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4309 return;
4310 }
4311 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4312 #endif
4313 }
4314
4315 /* tlbie */
4316 static void gen_tlbie(DisasContext *ctx)
4317 {
4318 #if defined(CONFIG_USER_ONLY)
4319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4320 #else
4321 if (unlikely(!ctx->mem_idx)) {
4322 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4323 return;
4324 }
4325 #if defined(TARGET_PPC64)
4326 if (!ctx->sf_mode) {
4327 TCGv t0 = tcg_temp_new();
4328 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4329 gen_helper_tlbie(cpu_env, t0);
4330 tcg_temp_free(t0);
4331 } else
4332 #endif
4333 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4334 #endif
4335 }
4336
4337 /* tlbsync */
4338 static void gen_tlbsync(DisasContext *ctx)
4339 {
4340 #if defined(CONFIG_USER_ONLY)
4341 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4342 #else
4343 if (unlikely(!ctx->mem_idx)) {
4344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4345 return;
4346 }
4347 /* This has no effect: it should ensure that all previous
4348 * tlbie have completed
4349 */
4350 gen_stop_exception(ctx);
4351 #endif
4352 }
4353
4354 #if defined(TARGET_PPC64)
4355 /* slbia */
4356 static void gen_slbia(DisasContext *ctx)
4357 {
4358 #if defined(CONFIG_USER_ONLY)
4359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4360 #else
4361 if (unlikely(!ctx->mem_idx)) {
4362 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4363 return;
4364 }
4365 gen_helper_slbia(cpu_env);
4366 #endif
4367 }
4368
4369 /* slbie */
4370 static void gen_slbie(DisasContext *ctx)
4371 {
4372 #if defined(CONFIG_USER_ONLY)
4373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4374 #else
4375 if (unlikely(!ctx->mem_idx)) {
4376 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4377 return;
4378 }
4379 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4380 #endif
4381 }
4382 #endif
4383
4384 /*** External control ***/
4385 /* Optional: */
4386
4387 /* eciwx */
4388 static void gen_eciwx(DisasContext *ctx)
4389 {
4390 TCGv t0;
4391 /* Should check EAR[E] ! */
4392 gen_set_access_type(ctx, ACCESS_EXT);
4393 t0 = tcg_temp_new();
4394 gen_addr_reg_index(ctx, t0);
4395 gen_check_align(ctx, t0, 0x03);
4396 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4397 tcg_temp_free(t0);
4398 }
4399
4400 /* ecowx */
4401 static void gen_ecowx(DisasContext *ctx)
4402 {
4403 TCGv t0;
4404 /* Should check EAR[E] ! */
4405 gen_set_access_type(ctx, ACCESS_EXT);
4406 t0 = tcg_temp_new();
4407 gen_addr_reg_index(ctx, t0);
4408 gen_check_align(ctx, t0, 0x03);
4409 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4410 tcg_temp_free(t0);
4411 }
4412
4413 /* PowerPC 601 specific instructions */
4414
4415 /* abs - abs. */
4416 static void gen_abs(DisasContext *ctx)
4417 {
4418 int l1 = gen_new_label();
4419 int l2 = gen_new_label();
4420 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4421 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4422 tcg_gen_br(l2);
4423 gen_set_label(l1);
4424 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4425 gen_set_label(l2);
4426 if (unlikely(Rc(ctx->opcode) != 0))
4427 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4428 }
4429
4430 /* abso - abso. */
4431 static void gen_abso(DisasContext *ctx)
4432 {
4433 int l1 = gen_new_label();
4434 int l2 = gen_new_label();
4435 int l3 = gen_new_label();
4436 /* Start with XER OV disabled, the most likely case */
4437 tcg_gen_movi_tl(cpu_ov, 0);
4438 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4439 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4440 tcg_gen_movi_tl(cpu_ov, 1);
4441 tcg_gen_movi_tl(cpu_so, 1);
4442 tcg_gen_br(l2);
4443 gen_set_label(l1);
4444 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4445 tcg_gen_br(l3);
4446 gen_set_label(l2);
4447 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4448 gen_set_label(l3);
4449 if (unlikely(Rc(ctx->opcode) != 0))
4450 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4451 }
4452
4453 /* clcs */
4454 static void gen_clcs(DisasContext *ctx)
4455 {
4456 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4457 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4458 tcg_temp_free_i32(t0);
4459 /* Rc=1 sets CR0 to an undefined state */
4460 }
4461
4462 /* div - div. */
4463 static void gen_div(DisasContext *ctx)
4464 {
4465 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4466 cpu_gpr[rB(ctx->opcode)]);
4467 if (unlikely(Rc(ctx->opcode) != 0))
4468 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4469 }
4470
4471 /* divo - divo. */
4472 static void gen_divo(DisasContext *ctx)
4473 {
4474 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4475 cpu_gpr[rB(ctx->opcode)]);
4476 if (unlikely(Rc(ctx->opcode) != 0))
4477 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4478 }
4479
4480 /* divs - divs. */
4481 static void gen_divs(DisasContext *ctx)
4482 {
4483 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4484 cpu_gpr[rB(ctx->opcode)]);
4485 if (unlikely(Rc(ctx->opcode) != 0))
4486 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4487 }
4488
4489 /* divso - divso. */
4490 static void gen_divso(DisasContext *ctx)
4491 {
4492 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4493 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4494 if (unlikely(Rc(ctx->opcode) != 0))
4495 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4496 }
4497
4498 /* doz - doz. */
4499 static void gen_doz(DisasContext *ctx)
4500 {
4501 int l1 = gen_new_label();
4502 int l2 = gen_new_label();
4503 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4504 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4505 tcg_gen_br(l2);
4506 gen_set_label(l1);
4507 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4508 gen_set_label(l2);
4509 if (unlikely(Rc(ctx->opcode) != 0))
4510 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4511 }
4512
4513 /* dozo - dozo. */
4514 static void gen_dozo(DisasContext *ctx)
4515 {
4516 int l1 = gen_new_label();
4517 int l2 = gen_new_label();
4518 TCGv t0 = tcg_temp_new();
4519 TCGv t1 = tcg_temp_new();
4520 TCGv t2 = tcg_temp_new();
4521 /* Start with XER OV disabled, the most likely case */
4522 tcg_gen_movi_tl(cpu_ov, 0);
4523 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4524 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4525 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4526 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4527 tcg_gen_andc_tl(t1, t1, t2);
4528 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4529 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4530 tcg_gen_movi_tl(cpu_ov, 1);
4531 tcg_gen_movi_tl(cpu_so, 1);
4532 tcg_gen_br(l2);
4533 gen_set_label(l1);
4534 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4535 gen_set_label(l2);
4536 tcg_temp_free(t0);
4537 tcg_temp_free(t1);
4538 tcg_temp_free(t2);
4539 if (unlikely(Rc(ctx->opcode) != 0))
4540 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4541 }
4542
4543 /* dozi */
4544 static void gen_dozi(DisasContext *ctx)
4545 {
4546 target_long simm = SIMM(ctx->opcode);
4547 int l1 = gen_new_label();
4548 int l2 = gen_new_label();
4549 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4550 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4551 tcg_gen_br(l2);
4552 gen_set_label(l1);
4553 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4554 gen_set_label(l2);
4555 if (unlikely(Rc(ctx->opcode) != 0))
4556 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4557 }
4558
4559 /* lscbx - lscbx. */
4560 static void gen_lscbx(DisasContext *ctx)
4561 {
4562 TCGv t0 = tcg_temp_new();
4563 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4564 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4565 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4566
4567 gen_addr_reg_index(ctx, t0);
4568 /* NIP cannot be restored if the memory exception comes from an helper */
4569 gen_update_nip(ctx, ctx->nip - 4);
4570 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4571 tcg_temp_free_i32(t1);
4572 tcg_temp_free_i32(t2);
4573 tcg_temp_free_i32(t3);
4574 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4575 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4576 if (unlikely(Rc(ctx->opcode) != 0))
4577 gen_set_Rc0(ctx, t0);
4578 tcg_temp_free(t0);
4579 }
4580
4581 /* maskg - maskg. */
4582 static void gen_maskg(DisasContext *ctx)
4583 {
4584 int l1 = gen_new_label();
4585 TCGv t0 = tcg_temp_new();
4586 TCGv t1 = tcg_temp_new();
4587 TCGv t2 = tcg_temp_new();
4588 TCGv t3 = tcg_temp_new();
4589 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4590 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4591 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4592 tcg_gen_addi_tl(t2, t0, 1);
4593 tcg_gen_shr_tl(t2, t3, t2);
4594 tcg_gen_shr_tl(t3, t3, t1);
4595 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4596 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4597 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4598 gen_set_label(l1);
4599 tcg_temp_free(t0);
4600 tcg_temp_free(t1);
4601 tcg_temp_free(t2);
4602 tcg_temp_free(t3);
4603 if (unlikely(Rc(ctx->opcode) != 0))
4604 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4605 }
4606
4607 /* maskir - maskir. */
4608 static void gen_maskir(DisasContext *ctx)
4609 {
4610 TCGv t0 = tcg_temp_new();
4611 TCGv t1 = tcg_temp_new();
4612 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4613 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4614 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4615 tcg_temp_free(t0);
4616 tcg_temp_free(t1);
4617 if (unlikely(Rc(ctx->opcode) != 0))
4618 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4619 }
4620
4621 /* mul - mul. */
4622 static void gen_mul(DisasContext *ctx)
4623 {
4624 TCGv_i64 t0 = tcg_temp_new_i64();
4625 TCGv_i64 t1 = tcg_temp_new_i64();
4626 TCGv t2 = tcg_temp_new();
4627 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4628 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4629 tcg_gen_mul_i64(t0, t0, t1);
4630 tcg_gen_trunc_i64_tl(t2, t0);
4631 gen_store_spr(SPR_MQ, t2);
4632 tcg_gen_shri_i64(t1, t0, 32);
4633 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4634 tcg_temp_free_i64(t0);
4635 tcg_temp_free_i64(t1);
4636 tcg_temp_free(t2);
4637 if (unlikely(Rc(ctx->opcode) != 0))
4638 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4639 }
4640
4641 /* mulo - mulo. */
4642 static void gen_mulo(DisasContext *ctx)
4643 {
4644 int l1 = gen_new_label();
4645 TCGv_i64 t0 = tcg_temp_new_i64();
4646 TCGv_i64 t1 = tcg_temp_new_i64();
4647 TCGv t2 = tcg_temp_new();
4648 /* Start with XER OV disabled, the most likely case */
4649 tcg_gen_movi_tl(cpu_ov, 0);
4650 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4651 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4652 tcg_gen_mul_i64(t0, t0, t1);
4653 tcg_gen_trunc_i64_tl(t2, t0);
4654 gen_store_spr(SPR_MQ, t2);
4655 tcg_gen_shri_i64(t1, t0, 32);
4656 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4657 tcg_gen_ext32s_i64(t1, t0);
4658 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4659 tcg_gen_movi_tl(cpu_ov, 1);
4660 tcg_gen_movi_tl(cpu_so, 1);
4661 gen_set_label(l1);
4662 tcg_temp_free_i64(t0);
4663 tcg_temp_free_i64(t1);
4664 tcg_temp_free(t2);
4665 if (unlikely(Rc(ctx->opcode) != 0))
4666 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4667 }
4668
4669 /* nabs - nabs. */
4670 static void gen_nabs(DisasContext *ctx)
4671 {
4672 int l1 = gen_new_label();
4673 int l2 = gen_new_label();
4674 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4675 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4676 tcg_gen_br(l2);
4677 gen_set_label(l1);
4678 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4679 gen_set_label(l2);
4680 if (unlikely(Rc(ctx->opcode) != 0))
4681 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4682 }
4683
4684 /* nabso - nabso. */
4685 static void gen_nabso(DisasContext *ctx)
4686 {
4687 int l1 = gen_new_label();
4688 int l2 = gen_new_label();
4689 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4690 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4691 tcg_gen_br(l2);
4692 gen_set_label(l1);
4693 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4694 gen_set_label(l2);
4695 /* nabs never overflows */
4696 tcg_gen_movi_tl(cpu_ov, 0);
4697 if (unlikely(Rc(ctx->opcode) != 0))
4698 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4699 }
4700
4701 /* rlmi - rlmi. */
4702 static void gen_rlmi(DisasContext *ctx)
4703 {
4704 uint32_t mb = MB(ctx->opcode);
4705 uint32_t me = ME(ctx->opcode);
4706 TCGv t0 = tcg_temp_new();
4707 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4708 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4709 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4710 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4711 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4712 tcg_temp_free(t0);
4713 if (unlikely(Rc(ctx->opcode) != 0))
4714 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4715 }
4716
4717 /* rrib - rrib. */
4718 static void gen_rrib(DisasContext *ctx)
4719 {
4720 TCGv t0 = tcg_temp_new();
4721 TCGv t1 = tcg_temp_new();
4722 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4723 tcg_gen_movi_tl(t1, 0x80000000);
4724 tcg_gen_shr_tl(t1, t1, t0);
4725 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4726 tcg_gen_and_tl(t0, t0, t1);
4727 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4728 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4729 tcg_temp_free(t0);
4730 tcg_temp_free(t1);
4731 if (unlikely(Rc(ctx->opcode) != 0))
4732 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4733 }
4734
4735 /* sle - sle. */
4736 static void gen_sle(DisasContext *ctx)
4737 {
4738 TCGv t0 = tcg_temp_new();
4739 TCGv t1 = tcg_temp_new();
4740 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4741 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4742 tcg_gen_subfi_tl(t1, 32, t1);
4743 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4744 tcg_gen_or_tl(t1, t0, t1);
4745 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4746 gen_store_spr(SPR_MQ, t1);
4747 tcg_temp_free(t0);
4748 tcg_temp_free(t1);
4749 if (unlikely(Rc(ctx->opcode) != 0))
4750 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4751 }
4752
4753 /* sleq - sleq. */
4754 static void gen_sleq(DisasContext *ctx)
4755 {
4756 TCGv t0 = tcg_temp_new();
4757 TCGv t1 = tcg_temp_new();
4758 TCGv t2 = tcg_temp_new();
4759 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4760 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4761 tcg_gen_shl_tl(t2, t2, t0);
4762 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4763 gen_load_spr(t1, SPR_MQ);
4764 gen_store_spr(SPR_MQ, t0);
4765 tcg_gen_and_tl(t0, t0, t2);
4766 tcg_gen_andc_tl(t1, t1, t2);
4767 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4768 tcg_temp_free(t0);
4769 tcg_temp_free(t1);
4770 tcg_temp_free(t2);
4771 if (unlikely(Rc(ctx->opcode) != 0))
4772 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4773 }
4774
4775 /* sliq - sliq. */
4776 static void gen_sliq(DisasContext *ctx)
4777 {
4778 int sh = SH(ctx->opcode);
4779 TCGv t0 = tcg_temp_new();
4780 TCGv t1 = tcg_temp_new();
4781 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4782 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4783 tcg_gen_or_tl(t1, t0, t1);
4784 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4785 gen_store_spr(SPR_MQ, t1);
4786 tcg_temp_free(t0);
4787 tcg_temp_free(t1);
4788 if (unlikely(Rc(ctx->opcode) != 0))
4789 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4790 }
4791
4792 /* slliq - slliq. */
4793 static void gen_slliq(DisasContext *ctx)
4794 {
4795 int sh = SH(ctx->opcode);
4796 TCGv t0 = tcg_temp_new();
4797 TCGv t1 = tcg_temp_new();
4798 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4799 gen_load_spr(t1, SPR_MQ);
4800 gen_store_spr(SPR_MQ, t0);
4801 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4802 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4803 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4804 tcg_temp_free(t0);
4805 tcg_temp_free(t1);
4806 if (unlikely(Rc(ctx->opcode) != 0))
4807 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4808 }
4809
4810 /* sllq - sllq. */
4811 static void gen_sllq(DisasContext *ctx)
4812 {
4813 int l1 = gen_new_label();
4814 int l2 = gen_new_label();
4815 TCGv t0 = tcg_temp_local_new();
4816 TCGv t1 = tcg_temp_local_new();
4817 TCGv t2 = tcg_temp_local_new();
4818 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4819 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4820 tcg_gen_shl_tl(t1, t1, t2);
4821 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4822 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4823 gen_load_spr(t0, SPR_MQ);
4824 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4825 tcg_gen_br(l2);
4826 gen_set_label(l1);
4827 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4828 gen_load_spr(t2, SPR_MQ);
4829 tcg_gen_andc_tl(t1, t2, t1);
4830 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4831 gen_set_label(l2);
4832 tcg_temp_free(t0);
4833 tcg_temp_free(t1);
4834 tcg_temp_free(t2);
4835 if (unlikely(Rc(ctx->opcode) != 0))
4836 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4837 }
4838
4839 /* slq - slq. */
4840 static void gen_slq(DisasContext *ctx)
4841 {
4842 int l1 = gen_new_label();
4843 TCGv t0 = tcg_temp_new();
4844 TCGv t1 = tcg_temp_new();
4845 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4846 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4847 tcg_gen_subfi_tl(t1, 32, t1);
4848 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4849 tcg_gen_or_tl(t1, t0, t1);
4850 gen_store_spr(SPR_MQ, t1);
4851 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4852 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4853 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4854 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4855 gen_set_label(l1);
4856 tcg_temp_free(t0);
4857 tcg_temp_free(t1);
4858 if (unlikely(Rc(ctx->opcode) != 0))
4859 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4860 }
4861
4862 /* sraiq - sraiq. */
4863 static void gen_sraiq(DisasContext *ctx)
4864 {
4865 int sh = SH(ctx->opcode);
4866 int l1 = gen_new_label();
4867 TCGv t0 = tcg_temp_new();
4868 TCGv t1 = tcg_temp_new();
4869 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4870 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4871 tcg_gen_or_tl(t0, t0, t1);
4872 gen_store_spr(SPR_MQ, t0);
4873 tcg_gen_movi_tl(cpu_ca, 0);
4874 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4875 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4876 tcg_gen_movi_tl(cpu_ca, 1);
4877 gen_set_label(l1);
4878 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4879 tcg_temp_free(t0);
4880 tcg_temp_free(t1);
4881 if (unlikely(Rc(ctx->opcode) != 0))
4882 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4883 }
4884
4885 /* sraq - sraq. */
4886 static void gen_sraq(DisasContext *ctx)
4887 {
4888 int l1 = gen_new_label();
4889 int l2 = gen_new_label();
4890 TCGv t0 = tcg_temp_new();
4891 TCGv t1 = tcg_temp_local_new();
4892 TCGv t2 = tcg_temp_local_new();
4893 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4894 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4895 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4896 tcg_gen_subfi_tl(t2, 32, t2);
4897 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4898 tcg_gen_or_tl(t0, t0, t2);
4899 gen_store_spr(SPR_MQ, t0);
4900 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4901 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4902 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4903 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4904 gen_set_label(l1);
4905 tcg_temp_free(t0);
4906 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4907 tcg_gen_movi_tl(cpu_ca, 0);
4908 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4909 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4910 tcg_gen_movi_tl(cpu_ca, 1);
4911 gen_set_label(l2);
4912 tcg_temp_free(t1);
4913 tcg_temp_free(t2);
4914 if (unlikely(Rc(ctx->opcode) != 0))
4915 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4916 }
4917
4918 /* sre - sre. */
4919 static void gen_sre(DisasContext *ctx)
4920 {
4921 TCGv t0 = tcg_temp_new();
4922 TCGv t1 = tcg_temp_new();
4923 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4924 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4925 tcg_gen_subfi_tl(t1, 32, t1);
4926 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4927 tcg_gen_or_tl(t1, t0, t1);
4928 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4929 gen_store_spr(SPR_MQ, t1);
4930 tcg_temp_free(t0);
4931 tcg_temp_free(t1);
4932 if (unlikely(Rc(ctx->opcode) != 0))
4933 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4934 }
4935
4936 /* srea - srea. */
4937 static void gen_srea(DisasContext *ctx)
4938 {
4939 TCGv t0 = tcg_temp_new();
4940 TCGv t1 = tcg_temp_new();
4941 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4942 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4943 gen_store_spr(SPR_MQ, t0);
4944 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4945 tcg_temp_free(t0);
4946 tcg_temp_free(t1);
4947 if (unlikely(Rc(ctx->opcode) != 0))
4948 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4949 }
4950
4951 /* sreq */
4952 static void gen_sreq(DisasContext *ctx)
4953 {
4954 TCGv t0 = tcg_temp_new();
4955 TCGv t1 = tcg_temp_new();
4956 TCGv t2 = tcg_temp_new();
4957 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4958 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4959 tcg_gen_shr_tl(t1, t1, t0);
4960 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4961 gen_load_spr(t2, SPR_MQ);
4962 gen_store_spr(SPR_MQ, t0);
4963 tcg_gen_and_tl(t0, t0, t1);
4964 tcg_gen_andc_tl(t2, t2, t1);
4965 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4966 tcg_temp_free(t0);
4967 tcg_temp_free(t1);
4968 tcg_temp_free(t2);
4969 if (unlikely(Rc(ctx->opcode) != 0))
4970 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4971 }
4972
4973 /* sriq */
4974 static void gen_sriq(DisasContext *ctx)
4975 {
4976 int sh = SH(ctx->opcode);
4977 TCGv t0 = tcg_temp_new();
4978 TCGv t1 = tcg_temp_new();
4979 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4980 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4981 tcg_gen_or_tl(t1, t0, t1);
4982 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4983 gen_store_spr(SPR_MQ, t1);
4984 tcg_temp_free(t0);
4985 tcg_temp_free(t1);
4986 if (unlikely(Rc(ctx->opcode) != 0))
4987 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4988 }
4989
4990 /* srliq */
4991 static void gen_srliq(DisasContext *ctx)
4992 {
4993 int sh = SH(ctx->opcode);
4994 TCGv t0 = tcg_temp_new();
4995 TCGv t1 = tcg_temp_new();
4996 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4997 gen_load_spr(t1, SPR_MQ);
4998 gen_store_spr(SPR_MQ, t0);
4999 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5000 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5001 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5002 tcg_temp_free(t0);
5003 tcg_temp_free(t1);
5004 if (unlikely(Rc(ctx->opcode) != 0))
5005 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5006 }
5007
5008 /* srlq */
5009 static void gen_srlq(DisasContext *ctx)
5010 {
5011 int l1 = gen_new_label();
5012 int l2 = gen_new_label();
5013 TCGv t0 = tcg_temp_local_new();
5014 TCGv t1 = tcg_temp_local_new();
5015 TCGv t2 = tcg_temp_local_new();
5016 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5017 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5018 tcg_gen_shr_tl(t2, t1, t2);
5019 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5020 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5021 gen_load_spr(t0, SPR_MQ);
5022 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5023 tcg_gen_br(l2);
5024 gen_set_label(l1);
5025 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5026 tcg_gen_and_tl(t0, t0, t2);
5027 gen_load_spr(t1, SPR_MQ);
5028 tcg_gen_andc_tl(t1, t1, t2);
5029 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5030 gen_set_label(l2);
5031 tcg_temp_free(t0);
5032 tcg_temp_free(t1);
5033 tcg_temp_free(t2);
5034 if (unlikely(Rc(ctx->opcode) != 0))
5035 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5036 }
5037
5038 /* srq */
5039 static void gen_srq(DisasContext *ctx)
5040 {
5041 int l1 = gen_new_label();
5042 TCGv t0 = tcg_temp_new();
5043 TCGv t1 = tcg_temp_new();
5044 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5045 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5046 tcg_gen_subfi_tl(t1, 32, t1);
5047 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5048 tcg_gen_or_tl(t1, t0, t1);
5049 gen_store_spr(SPR_MQ, t1);
5050 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5051 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5052 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5053 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5054 gen_set_label(l1);
5055 tcg_temp_free(t0);
5056 tcg_temp_free(t1);
5057 if (unlikely(Rc(ctx->opcode) != 0))
5058 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5059 }
5060
5061 /* PowerPC 602 specific instructions */
5062
5063 /* dsa */
5064 static void gen_dsa(DisasContext *ctx)
5065 {
5066 /* XXX: TODO */
5067 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5068 }
5069
5070 /* esa */
5071 static void gen_esa(DisasContext *ctx)
5072 {
5073 /* XXX: TODO */
5074 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5075 }
5076
5077 /* mfrom */
5078 static void gen_mfrom(DisasContext *ctx)
5079 {
5080 #if defined(CONFIG_USER_ONLY)
5081 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5082 #else
5083 if (unlikely(!ctx->mem_idx)) {
5084 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5085 return;
5086 }
5087 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5088 #endif
5089 }
5090
5091 /* 602 - 603 - G2 TLB management */
5092
5093 /* tlbld */
5094 static void gen_tlbld_6xx(DisasContext *ctx)
5095 {
5096 #if defined(CONFIG_USER_ONLY)
5097 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5098 #else
5099 if (unlikely(!ctx->mem_idx)) {
5100 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5101 return;
5102 }
5103 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5104 #endif
5105 }
5106
5107 /* tlbli */
5108 static void gen_tlbli_6xx(DisasContext *ctx)
5109 {
5110 #if defined(CONFIG_USER_ONLY)
5111 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5112 #else
5113 if (unlikely(!ctx->mem_idx)) {
5114 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5115 return;
5116 }
5117 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5118 #endif
5119 }
5120
5121 /* 74xx TLB management */
5122
5123 /* tlbld */
5124 static void gen_tlbld_74xx(DisasContext *ctx)
5125 {
5126 #if defined(CONFIG_USER_ONLY)
5127 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5128 #else
5129 if (unlikely(!ctx->mem_idx)) {
5130 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5131 return;
5132 }
5133 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5134 #endif
5135 }
5136
5137 /* tlbli */
5138 static void gen_tlbli_74xx(DisasContext *ctx)
5139 {
5140 #if defined(CONFIG_USER_ONLY)
5141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5142 #else
5143 if (unlikely(!ctx->mem_idx)) {
5144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5145 return;
5146 }
5147 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5148 #endif
5149 }
5150
5151 /* POWER instructions not in PowerPC 601 */
5152
5153 /* clf */
5154 static void gen_clf(DisasContext *ctx)
5155 {
5156 /* Cache line flush: implemented as no-op */
5157 }
5158
5159 /* cli */
5160 static void gen_cli(DisasContext *ctx)
5161 {
5162 /* Cache line invalidate: privileged and treated as no-op */
5163 #if defined(CONFIG_USER_ONLY)
5164 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5165 #else
5166 if (unlikely(!ctx->mem_idx)) {
5167 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5168 return;
5169 }
5170 #endif
5171 }
5172
5173 /* dclst */
5174 static void gen_dclst(DisasContext *ctx)
5175 {
5176 /* Data cache line store: treated as no-op */
5177 }
5178
5179 static void gen_mfsri(DisasContext *ctx)
5180 {
5181 #if defined(CONFIG_USER_ONLY)
5182 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5183 #else
5184 int ra = rA(ctx->opcode);
5185 int rd = rD(ctx->opcode);
5186 TCGv t0;
5187 if (unlikely(!ctx->mem_idx)) {
5188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5189 return;
5190 }
5191 t0 = tcg_temp_new();
5192 gen_addr_reg_index(ctx, t0);
5193 tcg_gen_shri_tl(t0, t0, 28);
5194 tcg_gen_andi_tl(t0, t0, 0xF);
5195 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5196 tcg_temp_free(t0);
5197 if (ra != 0 && ra != rd)
5198 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5199 #endif
5200 }
5201
5202 static void gen_rac(DisasContext *ctx)
5203 {
5204 #if defined(CONFIG_USER_ONLY)
5205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5206 #else
5207 TCGv t0;
5208 if (unlikely(!ctx->mem_idx)) {
5209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5210 return;
5211 }
5212 t0 = tcg_temp_new();
5213 gen_addr_reg_index(ctx, t0);
5214 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5215 tcg_temp_free(t0);
5216 #endif
5217 }
5218
5219 static void gen_rfsvc(DisasContext *ctx)
5220 {
5221 #if defined(CONFIG_USER_ONLY)
5222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5223 #else
5224 if (unlikely(!ctx->mem_idx)) {
5225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5226 return;
5227 }
5228 gen_helper_rfsvc(cpu_env);
5229 gen_sync_exception(ctx);
5230 #endif
5231 }
5232
5233 /* svc is not implemented for now */
5234
5235 /* POWER2 specific instructions */
5236 /* Quad manipulation (load/store two floats at a time) */
5237
5238 /* lfq */
5239 static void gen_lfq(DisasContext *ctx)
5240 {
5241 int rd = rD(ctx->opcode);
5242 TCGv t0;
5243 gen_set_access_type(ctx, ACCESS_FLOAT);
5244 t0 = tcg_temp_new();
5245 gen_addr_imm_index(ctx, t0, 0);
5246 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5247 gen_addr_add(ctx, t0, t0, 8);
5248 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5249 tcg_temp_free(t0);
5250 }
5251
5252 /* lfqu */
5253 static void gen_lfqu(DisasContext *ctx)
5254 {
5255 int ra = rA(ctx->opcode);
5256 int rd = rD(ctx->opcode);
5257 TCGv t0, t1;
5258 gen_set_access_type(ctx, ACCESS_FLOAT);
5259 t0 = tcg_temp_new();
5260 t1 = tcg_temp_new();
5261 gen_addr_imm_index(ctx, t0, 0);
5262 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5263 gen_addr_add(ctx, t1, t0, 8);
5264 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5265 if (ra != 0)
5266 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5267 tcg_temp_free(t0);
5268 tcg_temp_free(t1);
5269 }
5270
5271 /* lfqux */
5272 static void gen_lfqux(DisasContext *ctx)
5273 {
5274 int ra = rA(ctx->opcode);
5275 int rd = rD(ctx->opcode);
5276 gen_set_access_type(ctx, ACCESS_FLOAT);
5277 TCGv t0, t1;
5278 t0 = tcg_temp_new();
5279 gen_addr_reg_index(ctx, t0);
5280 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5281 t1 = tcg_temp_new();
5282 gen_addr_add(ctx, t1, t0, 8);
5283 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5284 tcg_temp_free(t1);
5285 if (ra != 0)
5286 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5287 tcg_temp_free(t0);
5288 }
5289
5290 /* lfqx */
5291 static void gen_lfqx(DisasContext *ctx)
5292 {
5293 int rd = rD(ctx->opcode);
5294 TCGv t0;
5295 gen_set_access_type(ctx, ACCESS_FLOAT);
5296 t0 = tcg_temp_new();
5297 gen_addr_reg_index(ctx, t0);
5298 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5299 gen_addr_add(ctx, t0, t0, 8);
5300 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5301 tcg_temp_free(t0);
5302 }
5303
5304 /* stfq */
5305 static void gen_stfq(DisasContext *ctx)
5306 {
5307 int rd = rD(ctx->opcode);
5308 TCGv t0;
5309 gen_set_access_type(ctx, ACCESS_FLOAT);
5310 t0 = tcg_temp_new();
5311 gen_addr_imm_index(ctx, t0, 0);
5312 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5313 gen_addr_add(ctx, t0, t0, 8);
5314 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5315 tcg_temp_free(t0);
5316 }
5317
5318 /* stfqu */
5319 static void gen_stfqu(DisasContext *ctx)
5320 {
5321 int ra = rA(ctx->opcode);
5322 int rd = rD(ctx->opcode);
5323 TCGv t0, t1;
5324 gen_set_access_type(ctx, ACCESS_FLOAT);
5325 t0 = tcg_temp_new();
5326 gen_addr_imm_index(ctx, t0, 0);
5327 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5328 t1 = tcg_temp_new();
5329 gen_addr_add(ctx, t1, t0, 8);
5330 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5331 tcg_temp_free(t1);
5332 if (ra != 0)
5333 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5334 tcg_temp_free(t0);
5335 }
5336
5337 /* stfqux */
5338 static void gen_stfqux(DisasContext *ctx)
5339 {
5340 int ra = rA(ctx->opcode);
5341 int rd = rD(ctx->opcode);
5342 TCGv t0, t1;
5343 gen_set_access_type(ctx, ACCESS_FLOAT);
5344 t0 = tcg_temp_new();
5345 gen_addr_reg_index(ctx, t0);
5346 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5347 t1 = tcg_temp_new();
5348 gen_addr_add(ctx, t1, t0, 8);
5349 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5350 tcg_temp_free(t1);
5351 if (ra != 0)
5352 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5353 tcg_temp_free(t0);
5354 }
5355
5356 /* stfqx */
5357 static void gen_stfqx(DisasContext *ctx)
5358 {
5359 int rd = rD(ctx->opcode);
5360 TCGv t0;
5361 gen_set_access_type(ctx, ACCESS_FLOAT);
5362 t0 = tcg_temp_new();
5363 gen_addr_reg_index(ctx, t0);
5364 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5365 gen_addr_add(ctx, t0, t0, 8);
5366 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5367 tcg_temp_free(t0);
5368 }
5369
5370 /* BookE specific instructions */
5371
5372 /* XXX: not implemented on 440 ? */
5373 static void gen_mfapidi(DisasContext *ctx)
5374 {
5375 /* XXX: TODO */
5376 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5377 }
5378
5379 /* XXX: not implemented on 440 ? */
5380 static void gen_tlbiva(DisasContext *ctx)
5381 {
5382 #if defined(CONFIG_USER_ONLY)
5383 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5384 #else
5385 TCGv t0;
5386 if (unlikely(!ctx->mem_idx)) {
5387 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5388 return;
5389 }
5390 t0 = tcg_temp_new();
5391 gen_addr_reg_index(ctx, t0);
5392 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5393 tcg_temp_free(t0);
5394 #endif
5395 }
5396
5397 /* All 405 MAC instructions are translated here */
5398 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5399 int ra, int rb, int rt, int Rc)
5400 {
5401 TCGv t0, t1;
5402
5403 t0 = tcg_temp_local_new();
5404 t1 = tcg_temp_local_new();
5405
5406 switch (opc3 & 0x0D) {
5407 case 0x05:
5408 /* macchw - macchw. - macchwo - macchwo. */
5409 /* macchws - macchws. - macchwso - macchwso. */
5410 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5411 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5412 /* mulchw - mulchw. */
5413 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5414 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5415 tcg_gen_ext16s_tl(t1, t1);
5416 break;
5417 case 0x04:
5418 /* macchwu - macchwu. - macchwuo - macchwuo. */
5419 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5420 /* mulchwu - mulchwu. */
5421 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5422 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5423 tcg_gen_ext16u_tl(t1, t1);
5424 break;
5425 case 0x01:
5426 /* machhw - machhw. - machhwo - machhwo. */
5427 /* machhws - machhws. - machhwso - machhwso. */
5428 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5429 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5430 /* mulhhw - mulhhw. */
5431 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5432 tcg_gen_ext16s_tl(t0, t0);
5433 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5434 tcg_gen_ext16s_tl(t1, t1);
5435 break;
5436 case 0x00:
5437 /* machhwu - machhwu. - machhwuo - machhwuo. */
5438 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5439 /* mulhhwu - mulhhwu. */
5440 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5441 tcg_gen_ext16u_tl(t0, t0);
5442 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5443 tcg_gen_ext16u_tl(t1, t1);
5444 break;
5445 case 0x0D:
5446 /* maclhw - maclhw. - maclhwo - maclhwo. */
5447 /* maclhws - maclhws. - maclhwso - maclhwso. */
5448 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5449 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5450 /* mullhw - mullhw. */
5451 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5452 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5453 break;
5454 case 0x0C:
5455 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5456 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5457 /* mullhwu - mullhwu. */
5458 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5459 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5460 break;
5461 }
5462 if (opc2 & 0x04) {
5463 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5464 tcg_gen_mul_tl(t1, t0, t1);
5465 if (opc2 & 0x02) {
5466 /* nmultiply-and-accumulate (0x0E) */
5467 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5468 } else {
5469 /* multiply-and-accumulate (0x0C) */
5470 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5471 }
5472
5473 if (opc3 & 0x12) {
5474 /* Check overflow and/or saturate */
5475 int l1 = gen_new_label();
5476
5477 if (opc3 & 0x10) {
5478 /* Start with XER OV disabled, the most likely case */
5479 tcg_gen_movi_tl(cpu_ov, 0);
5480 }
5481 if (opc3 & 0x01) {
5482 /* Signed */
5483 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5484 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5485 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5486 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5487 if (opc3 & 0x02) {
5488 /* Saturate */
5489 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5490 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5491 }
5492 } else {
5493 /* Unsigned */
5494 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5495 if (opc3 & 0x02) {
5496 /* Saturate */
5497 tcg_gen_movi_tl(t0, UINT32_MAX);
5498 }
5499 }
5500 if (opc3 & 0x10) {
5501 /* Check overflow */
5502 tcg_gen_movi_tl(cpu_ov, 1);
5503 tcg_gen_movi_tl(cpu_so, 1);
5504 }
5505 gen_set_label(l1);
5506 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5507 }
5508 } else {
5509 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5510 }
5511 tcg_temp_free(t0);
5512 tcg_temp_free(t1);
5513 if (unlikely(Rc) != 0) {
5514 /* Update Rc0 */
5515 gen_set_Rc0(ctx, cpu_gpr[rt]);
5516 }
5517 }
5518
5519 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5520 static void glue(gen_, name)(DisasContext *ctx) \
5521 { \
5522 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5523 rD(ctx->opcode), Rc(ctx->opcode)); \
5524 }
5525
5526 /* macchw - macchw. */
5527 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5528 /* macchwo - macchwo. */
5529 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5530 /* macchws - macchws. */
5531 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5532 /* macchwso - macchwso. */
5533 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5534 /* macchwsu - macchwsu. */
5535 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5536 /* macchwsuo - macchwsuo. */
5537 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5538 /* macchwu - macchwu. */
5539 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5540 /* macchwuo - macchwuo. */
5541 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5542 /* machhw - machhw. */
5543 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5544 /* machhwo - machhwo. */
5545 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5546 /* machhws - machhws. */
5547 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5548 /* machhwso - machhwso. */
5549 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5550 /* machhwsu - machhwsu. */
5551 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5552 /* machhwsuo - machhwsuo. */
5553 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5554 /* machhwu - machhwu. */
5555 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5556 /* machhwuo - machhwuo. */
5557 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5558 /* maclhw - maclhw. */
5559 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5560 /* maclhwo - maclhwo. */
5561 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5562 /* maclhws - maclhws. */
5563 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5564 /* maclhwso - maclhwso. */
5565 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5566 /* maclhwu - maclhwu. */
5567 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5568 /* maclhwuo - maclhwuo. */
5569 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5570 /* maclhwsu - maclhwsu. */
5571 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5572 /* maclhwsuo - maclhwsuo. */
5573 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5574 /* nmacchw - nmacchw. */
5575 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5576 /* nmacchwo - nmacchwo. */
5577 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5578 /* nmacchws - nmacchws. */
5579 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5580 /* nmacchwso - nmacchwso. */
5581 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5582 /* nmachhw - nmachhw. */
5583 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5584 /* nmachhwo - nmachhwo. */
5585 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5586 /* nmachhws - nmachhws. */
5587 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5588 /* nmachhwso - nmachhwso. */
5589 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5590 /* nmaclhw - nmaclhw. */
5591 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5592 /* nmaclhwo - nmaclhwo. */
5593 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5594 /* nmaclhws - nmaclhws. */
5595 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5596 /* nmaclhwso - nmaclhwso. */
5597 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5598
5599 /* mulchw - mulchw. */
5600 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5601 /* mulchwu - mulchwu. */
5602 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5603 /* mulhhw - mulhhw. */
5604 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5605 /* mulhhwu - mulhhwu. */
5606 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5607 /* mullhw - mullhw. */
5608 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5609 /* mullhwu - mullhwu. */
5610 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5611
5612 /* mfdcr */
5613 static void gen_mfdcr(DisasContext *ctx)
5614 {
5615 #if defined(CONFIG_USER_ONLY)
5616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5617 #else
5618 TCGv dcrn;
5619 if (unlikely(!ctx->mem_idx)) {
5620 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5621 return;
5622 }
5623 /* NIP cannot be restored if the memory exception comes from an helper */
5624 gen_update_nip(ctx, ctx->nip - 4);
5625 dcrn = tcg_const_tl(SPR(ctx->opcode));
5626 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5627 tcg_temp_free(dcrn);
5628 #endif
5629 }
5630
5631 /* mtdcr */
5632 static void gen_mtdcr(DisasContext *ctx)
5633 {
5634 #if defined(CONFIG_USER_ONLY)
5635 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5636 #else
5637 TCGv dcrn;
5638 if (unlikely(!ctx->mem_idx)) {
5639 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5640 return;
5641 }
5642 /* NIP cannot be restored if the memory exception comes from an helper */
5643 gen_update_nip(ctx, ctx->nip - 4);
5644 dcrn = tcg_const_tl(SPR(ctx->opcode));
5645 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5646 tcg_temp_free(dcrn);
5647 #endif
5648 }
5649
5650 /* mfdcrx */
5651 /* XXX: not implemented on 440 ? */
5652 static void gen_mfdcrx(DisasContext *ctx)
5653 {
5654 #if defined(CONFIG_USER_ONLY)
5655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5656 #else
5657 if (unlikely(!ctx->mem_idx)) {
5658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5659 return;
5660 }
5661 /* NIP cannot be restored if the memory exception comes from an helper */
5662 gen_update_nip(ctx, ctx->nip - 4);
5663 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5664 cpu_gpr[rA(ctx->opcode)]);
5665 /* Note: Rc update flag set leads to undefined state of Rc0 */
5666 #endif
5667 }
5668
5669 /* mtdcrx */
5670 /* XXX: not implemented on 440 ? */
5671 static void gen_mtdcrx(DisasContext *ctx)
5672 {
5673 #if defined(CONFIG_USER_ONLY)
5674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5675 #else
5676 if (unlikely(!ctx->mem_idx)) {
5677 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5678 return;
5679 }
5680 /* NIP cannot be restored if the memory exception comes from an helper */
5681 gen_update_nip(ctx, ctx->nip - 4);
5682 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5683 cpu_gpr[rS(ctx->opcode)]);
5684 /* Note: Rc update flag set leads to undefined state of Rc0 */
5685 #endif
5686 }
5687
5688 /* mfdcrux (PPC 460) : user-mode access to DCR */
5689 static void gen_mfdcrux(DisasContext *ctx)
5690 {
5691 /* NIP cannot be restored if the memory exception comes from an helper */
5692 gen_update_nip(ctx, ctx->nip - 4);
5693 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5694 cpu_gpr[rA(ctx->opcode)]);
5695 /* Note: Rc update flag set leads to undefined state of Rc0 */
5696 }
5697
5698 /* mtdcrux (PPC 460) : user-mode access to DCR */
5699 static void gen_mtdcrux(DisasContext *ctx)
5700 {
5701 /* NIP cannot be restored if the memory exception comes from an helper */
5702 gen_update_nip(ctx, ctx->nip - 4);
5703 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5704 cpu_gpr[rS(ctx->opcode)]);
5705 /* Note: Rc update flag set leads to undefined state of Rc0 */
5706 }
5707
5708 /* dccci */
5709 static void gen_dccci(DisasContext *ctx)
5710 {
5711 #if defined(CONFIG_USER_ONLY)
5712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5713 #else
5714 if (unlikely(!ctx->mem_idx)) {
5715 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5716 return;
5717 }
5718 /* interpreted as no-op */
5719 #endif
5720 }
5721
5722 /* dcread */
5723 static void gen_dcread(DisasContext *ctx)
5724 {
5725 #if defined(CONFIG_USER_ONLY)
5726 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5727 #else
5728 TCGv EA, val;
5729 if (unlikely(!ctx->mem_idx)) {
5730 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5731 return;
5732 }
5733 gen_set_access_type(ctx, ACCESS_CACHE);
5734 EA = tcg_temp_new();
5735 gen_addr_reg_index(ctx, EA);
5736 val = tcg_temp_new();
5737 gen_qemu_ld32u(ctx, val, EA);
5738 tcg_temp_free(val);
5739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5740 tcg_temp_free(EA);
5741 #endif
5742 }
5743
5744 /* icbt */
5745 static void gen_icbt_40x(DisasContext *ctx)
5746 {
5747 /* interpreted as no-op */
5748 /* XXX: specification say this is treated as a load by the MMU
5749 * but does not generate any exception
5750 */
5751 }
5752
5753 /* iccci */
5754 static void gen_iccci(DisasContext *ctx)
5755 {
5756 #if defined(CONFIG_USER_ONLY)
5757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5758 #else
5759 if (unlikely(!ctx->mem_idx)) {
5760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5761 return;
5762 }
5763 /* interpreted as no-op */
5764 #endif
5765 }
5766
5767 /* icread */
5768 static void gen_icread(DisasContext *ctx)
5769 {
5770 #if defined(CONFIG_USER_ONLY)
5771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5772 #else
5773 if (unlikely(!ctx->mem_idx)) {
5774 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5775 return;
5776 }
5777 /* interpreted as no-op */
5778 #endif
5779 }
5780
5781 /* rfci (mem_idx only) */
5782 static void gen_rfci_40x(DisasContext *ctx)
5783 {
5784 #if defined(CONFIG_USER_ONLY)
5785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5786 #else
5787 if (unlikely(!ctx->mem_idx)) {
5788 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5789 return;
5790 }
5791 /* Restore CPU state */
5792 gen_helper_40x_rfci(cpu_env);
5793 gen_sync_exception(ctx);
5794 #endif
5795 }
5796
5797 static void gen_rfci(DisasContext *ctx)
5798 {
5799 #if defined(CONFIG_USER_ONLY)
5800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5801 #else
5802 if (unlikely(!ctx->mem_idx)) {
5803 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5804 return;
5805 }
5806 /* Restore CPU state */
5807 gen_helper_rfci(cpu_env);
5808 gen_sync_exception(ctx);
5809 #endif
5810 }
5811
5812 /* BookE specific */
5813
5814 /* XXX: not implemented on 440 ? */
5815 static void gen_rfdi(DisasContext *ctx)
5816 {
5817 #if defined(CONFIG_USER_ONLY)
5818 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5819 #else
5820 if (unlikely(!ctx->mem_idx)) {
5821 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5822 return;
5823 }
5824 /* Restore CPU state */
5825 gen_helper_rfdi(cpu_env);
5826 gen_sync_exception(ctx);
5827 #endif
5828 }
5829
5830 /* XXX: not implemented on 440 ? */
5831 static void gen_rfmci(DisasContext *ctx)
5832 {
5833 #if defined(CONFIG_USER_ONLY)
5834 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5835 #else
5836 if (unlikely(!ctx->mem_idx)) {
5837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5838 return;
5839 }
5840 /* Restore CPU state */
5841 gen_helper_rfmci(cpu_env);
5842 gen_sync_exception(ctx);
5843 #endif
5844 }
5845
5846 /* TLB management - PowerPC 405 implementation */
5847
5848 /* tlbre */
5849 static void gen_tlbre_40x(DisasContext *ctx)
5850 {
5851 #if defined(CONFIG_USER_ONLY)
5852 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5853 #else
5854 if (unlikely(!ctx->mem_idx)) {
5855 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5856 return;
5857 }
5858 switch (rB(ctx->opcode)) {
5859 case 0:
5860 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5861 cpu_gpr[rA(ctx->opcode)]);
5862 break;
5863 case 1:
5864 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5865 cpu_gpr[rA(ctx->opcode)]);
5866 break;
5867 default:
5868 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5869 break;
5870 }
5871 #endif
5872 }
5873
5874 /* tlbsx - tlbsx. */
5875 static void gen_tlbsx_40x(DisasContext *ctx)
5876 {
5877 #if defined(CONFIG_USER_ONLY)
5878 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5879 #else
5880 TCGv t0;
5881 if (unlikely(!ctx->mem_idx)) {
5882 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5883 return;
5884 }
5885 t0 = tcg_temp_new();
5886 gen_addr_reg_index(ctx, t0);
5887 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5888 tcg_temp_free(t0);
5889 if (Rc(ctx->opcode)) {
5890 int l1 = gen_new_label();
5891 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5892 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5893 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5894 gen_set_label(l1);
5895 }
5896 #endif
5897 }
5898
5899 /* tlbwe */
5900 static void gen_tlbwe_40x(DisasContext *ctx)
5901 {
5902 #if defined(CONFIG_USER_ONLY)
5903 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5904 #else
5905 if (unlikely(!ctx->mem_idx)) {
5906 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5907 return;
5908 }
5909 switch (rB(ctx->opcode)) {
5910 case 0:
5911 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5912 cpu_gpr[rS(ctx->opcode)]);
5913 break;
5914 case 1:
5915 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5916 cpu_gpr[rS(ctx->opcode)]);
5917 break;
5918 default:
5919 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5920 break;
5921 }
5922 #endif
5923 }
5924
5925 /* TLB management - PowerPC 440 implementation */
5926
5927 /* tlbre */
5928 static void gen_tlbre_440(DisasContext *ctx)
5929 {
5930 #if defined(CONFIG_USER_ONLY)
5931 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5932 #else
5933 if (unlikely(!ctx->mem_idx)) {
5934 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5935 return;
5936 }
5937 switch (rB(ctx->opcode)) {
5938 case 0:
5939 case 1:
5940 case 2:
5941 {
5942 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5943 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5944 t0, cpu_gpr[rA(ctx->opcode)]);
5945 tcg_temp_free_i32(t0);
5946 }
5947 break;
5948 default:
5949 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5950 break;
5951 }
5952 #endif
5953 }
5954
5955 /* tlbsx - tlbsx. */
5956 static void gen_tlbsx_440(DisasContext *ctx)
5957 {
5958 #if defined(CONFIG_USER_ONLY)
5959 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5960 #else
5961 TCGv t0;
5962 if (unlikely(!ctx->mem_idx)) {
5963 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5964 return;
5965 }
5966 t0 = tcg_temp_new();
5967 gen_addr_reg_index(ctx, t0);
5968 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5969 tcg_temp_free(t0);
5970 if (Rc(ctx->opcode)) {
5971 int l1 = gen_new_label();
5972 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5973 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5974 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5975 gen_set_label(l1);
5976 }
5977 #endif
5978 }
5979
5980 /* tlbwe */
5981 static void gen_tlbwe_440(DisasContext *ctx)
5982 {
5983 #if defined(CONFIG_USER_ONLY)
5984 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5985 #else
5986 if (unlikely(!ctx->mem_idx)) {
5987 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5988 return;
5989 }
5990 switch (rB(ctx->opcode)) {
5991 case 0:
5992 case 1:
5993 case 2:
5994 {
5995 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5996 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5997 cpu_gpr[rS(ctx->opcode)]);
5998 tcg_temp_free_i32(t0);
5999 }
6000 break;
6001 default:
6002 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6003 break;
6004 }
6005 #endif
6006 }
6007
6008 /* TLB management - PowerPC BookE 2.06 implementation */
6009
6010 /* tlbre */
6011 static void gen_tlbre_booke206(DisasContext *ctx)
6012 {
6013 #if defined(CONFIG_USER_ONLY)
6014 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6015 #else
6016 if (unlikely(!ctx->mem_idx)) {
6017 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6018 return;
6019 }
6020
6021 gen_helper_booke206_tlbre(cpu_env);
6022 #endif
6023 }
6024
6025 /* tlbsx - tlbsx. */
6026 static void gen_tlbsx_booke206(DisasContext *ctx)
6027 {
6028 #if defined(CONFIG_USER_ONLY)
6029 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6030 #else
6031 TCGv t0;
6032 if (unlikely(!ctx->mem_idx)) {
6033 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6034 return;
6035 }
6036
6037 if (rA(ctx->opcode)) {
6038 t0 = tcg_temp_new();
6039 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6040 } else {
6041 t0 = tcg_const_tl(0);
6042 }
6043
6044 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6045 gen_helper_booke206_tlbsx(cpu_env, t0);
6046 #endif
6047 }
6048
6049 /* tlbwe */
6050 static void gen_tlbwe_booke206(DisasContext *ctx)
6051 {
6052 #if defined(CONFIG_USER_ONLY)
6053 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6054 #else
6055 if (unlikely(!ctx->mem_idx)) {
6056 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6057 return;
6058 }
6059 gen_update_nip(ctx, ctx->nip - 4);
6060 gen_helper_booke206_tlbwe(cpu_env);
6061 #endif
6062 }
6063
6064 static void gen_tlbivax_booke206(DisasContext *ctx)
6065 {
6066 #if defined(CONFIG_USER_ONLY)
6067 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6068 #else
6069 TCGv t0;
6070 if (unlikely(!ctx->mem_idx)) {
6071 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6072 return;
6073 }
6074
6075 t0 = tcg_temp_new();
6076 gen_addr_reg_index(ctx, t0);
6077
6078 gen_helper_booke206_tlbivax(cpu_env, t0);
6079 #endif
6080 }
6081
6082 static void gen_tlbilx_booke206(DisasContext *ctx)
6083 {
6084 #if defined(CONFIG_USER_ONLY)
6085 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6086 #else
6087 TCGv t0;
6088 if (unlikely(!ctx->mem_idx)) {
6089 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6090 return;
6091 }
6092
6093 t0 = tcg_temp_new();
6094 gen_addr_reg_index(ctx, t0);
6095
6096 switch((ctx->opcode >> 21) & 0x3) {
6097 case 0:
6098 gen_helper_booke206_tlbilx0(cpu_env, t0);
6099 break;
6100 case 1:
6101 gen_helper_booke206_tlbilx1(cpu_env, t0);
6102 break;
6103 case 3:
6104 gen_helper_booke206_tlbilx3(cpu_env, t0);
6105 break;
6106 default:
6107 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6108 break;
6109 }
6110
6111 tcg_temp_free(t0);
6112 #endif
6113 }
6114
6115
6116 /* wrtee */
6117 static void gen_wrtee(DisasContext *ctx)
6118 {
6119 #if defined(CONFIG_USER_ONLY)
6120 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6121 #else
6122 TCGv t0;
6123 if (unlikely(!ctx->mem_idx)) {
6124 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6125 return;
6126 }
6127 t0 = tcg_temp_new();
6128 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6129 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6130 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6131 tcg_temp_free(t0);
6132 /* Stop translation to have a chance to raise an exception
6133 * if we just set msr_ee to 1
6134 */
6135 gen_stop_exception(ctx);
6136 #endif
6137 }
6138
6139 /* wrteei */
6140 static void gen_wrteei(DisasContext *ctx)
6141 {
6142 #if defined(CONFIG_USER_ONLY)
6143 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6144 #else
6145 if (unlikely(!ctx->mem_idx)) {
6146 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6147 return;
6148 }
6149 if (ctx->opcode & 0x00008000) {
6150 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6151 /* Stop translation to have a chance to raise an exception */
6152 gen_stop_exception(ctx);
6153 } else {
6154 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6155 }
6156 #endif
6157 }
6158
6159 /* PowerPC 440 specific instructions */
6160
6161 /* dlmzb */
6162 static void gen_dlmzb(DisasContext *ctx)
6163 {
6164 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6165 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6166 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6167 tcg_temp_free_i32(t0);
6168 }
6169
6170 /* mbar replaces eieio on 440 */
6171 static void gen_mbar(DisasContext *ctx)
6172 {
6173 /* interpreted as no-op */
6174 }
6175
6176 /* msync replaces sync on 440 */
6177 static void gen_msync_4xx(DisasContext *ctx)
6178 {
6179 /* interpreted as no-op */
6180 }
6181
6182 /* icbt */
6183 static void gen_icbt_440(DisasContext *ctx)
6184 {
6185 /* interpreted as no-op */
6186 /* XXX: specification say this is treated as a load by the MMU
6187 * but does not generate any exception
6188 */
6189 }
6190
6191 /* Embedded.Processor Control */
6192
6193 static void gen_msgclr(DisasContext *ctx)
6194 {
6195 #if defined(CONFIG_USER_ONLY)
6196 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6197 #else
6198 if (unlikely(ctx->mem_idx == 0)) {
6199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6200 return;
6201 }
6202
6203 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6204 #endif
6205 }
6206
6207 static void gen_msgsnd(DisasContext *ctx)
6208 {
6209 #if defined(CONFIG_USER_ONLY)
6210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6211 #else
6212 if (unlikely(ctx->mem_idx == 0)) {
6213 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6214 return;
6215 }
6216
6217 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6218 #endif
6219 }
6220
6221 /*** Altivec vector extension ***/
6222 /* Altivec registers moves */
6223
6224 static inline TCGv_ptr gen_avr_ptr(int reg)
6225 {
6226 TCGv_ptr r = tcg_temp_new_ptr();
6227 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6228 return r;
6229 }
6230
6231 #define GEN_VR_LDX(name, opc2, opc3) \
6232 static void glue(gen_, name)(DisasContext *ctx) \
6233 { \
6234 TCGv EA; \
6235 if (unlikely(!ctx->altivec_enabled)) { \
6236 gen_exception(ctx, POWERPC_EXCP_VPU); \
6237 return; \
6238 } \
6239 gen_set_access_type(ctx, ACCESS_INT); \
6240 EA = tcg_temp_new(); \
6241 gen_addr_reg_index(ctx, EA); \
6242 tcg_gen_andi_tl(EA, EA, ~0xf); \
6243 if (ctx->le_mode) { \
6244 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6245 tcg_gen_addi_tl(EA, EA, 8); \
6246 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6247 } else { \
6248 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6249 tcg_gen_addi_tl(EA, EA, 8); \
6250 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6251 } \
6252 tcg_temp_free(EA); \
6253 }
6254
6255 #define GEN_VR_STX(name, opc2, opc3) \
6256 static void gen_st##name(DisasContext *ctx) \
6257 { \
6258 TCGv EA; \
6259 if (unlikely(!ctx->altivec_enabled)) { \
6260 gen_exception(ctx, POWERPC_EXCP_VPU); \
6261 return; \
6262 } \
6263 gen_set_access_type(ctx, ACCESS_INT); \
6264 EA = tcg_temp_new(); \
6265 gen_addr_reg_index(ctx, EA); \
6266 tcg_gen_andi_tl(EA, EA, ~0xf); \
6267 if (ctx->le_mode) { \
6268 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6269 tcg_gen_addi_tl(EA, EA, 8); \
6270 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6271 } else { \
6272 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6273 tcg_gen_addi_tl(EA, EA, 8); \
6274 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6275 } \
6276 tcg_temp_free(EA); \
6277 }
6278
6279 #define GEN_VR_LVE(name, opc2, opc3) \
6280 static void gen_lve##name(DisasContext *ctx) \
6281 { \
6282 TCGv EA; \
6283 TCGv_ptr rs; \
6284 if (unlikely(!ctx->altivec_enabled)) { \
6285 gen_exception(ctx, POWERPC_EXCP_VPU); \
6286 return; \
6287 } \
6288 gen_set_access_type(ctx, ACCESS_INT); \
6289 EA = tcg_temp_new(); \
6290 gen_addr_reg_index(ctx, EA); \
6291 rs = gen_avr_ptr(rS(ctx->opcode)); \
6292 gen_helper_lve##name(cpu_env, rs, EA); \
6293 tcg_temp_free(EA); \
6294 tcg_temp_free_ptr(rs); \
6295 }
6296
6297 #define GEN_VR_STVE(name, opc2, opc3) \
6298 static void gen_stve##name(DisasContext *ctx) \
6299 { \
6300 TCGv EA; \
6301 TCGv_ptr rs; \
6302 if (unlikely(!ctx->altivec_enabled)) { \
6303 gen_exception(ctx, POWERPC_EXCP_VPU); \
6304 return; \
6305 } \
6306 gen_set_access_type(ctx, ACCESS_INT); \
6307 EA = tcg_temp_new(); \
6308 gen_addr_reg_index(ctx, EA); \
6309 rs = gen_avr_ptr(rS(ctx->opcode)); \
6310 gen_helper_stve##name(cpu_env, rs, EA); \
6311 tcg_temp_free(EA); \
6312 tcg_temp_free_ptr(rs); \
6313 }
6314
6315 GEN_VR_LDX(lvx, 0x07, 0x03);
6316 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6317 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6318
6319 GEN_VR_LVE(bx, 0x07, 0x00);
6320 GEN_VR_LVE(hx, 0x07, 0x01);
6321 GEN_VR_LVE(wx, 0x07, 0x02);
6322
6323 GEN_VR_STX(svx, 0x07, 0x07);
6324 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6325 GEN_VR_STX(svxl, 0x07, 0x0F);
6326
6327 GEN_VR_STVE(bx, 0x07, 0x04);
6328 GEN_VR_STVE(hx, 0x07, 0x05);
6329 GEN_VR_STVE(wx, 0x07, 0x06);
6330
6331 static void gen_lvsl(DisasContext *ctx)
6332 {
6333 TCGv_ptr rd;
6334 TCGv EA;
6335 if (unlikely(!ctx->altivec_enabled)) {
6336 gen_exception(ctx, POWERPC_EXCP_VPU);
6337 return;
6338 }
6339 EA = tcg_temp_new();
6340 gen_addr_reg_index(ctx, EA);
6341 rd = gen_avr_ptr(rD(ctx->opcode));
6342 gen_helper_lvsl(rd, EA);
6343 tcg_temp_free(EA);
6344 tcg_temp_free_ptr(rd);
6345 }
6346
6347 static void gen_lvsr(DisasContext *ctx)
6348 {
6349 TCGv_ptr rd;
6350 TCGv EA;
6351 if (unlikely(!ctx->altivec_enabled)) {
6352 gen_exception(ctx, POWERPC_EXCP_VPU);
6353 return;
6354 }
6355 EA = tcg_temp_new();
6356 gen_addr_reg_index(ctx, EA);
6357 rd = gen_avr_ptr(rD(ctx->opcode));
6358 gen_helper_lvsr(rd, EA);
6359 tcg_temp_free(EA);
6360 tcg_temp_free_ptr(rd);
6361 }
6362
6363 static void gen_mfvscr(DisasContext *ctx)
6364 {
6365 TCGv_i32 t;
6366 if (unlikely(!ctx->altivec_enabled)) {
6367 gen_exception(ctx, POWERPC_EXCP_VPU);
6368 return;
6369 }
6370 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6371 t = tcg_temp_new_i32();
6372 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6373 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6374 tcg_temp_free_i32(t);
6375 }
6376
6377 static void gen_mtvscr(DisasContext *ctx)
6378 {
6379 TCGv_ptr p;
6380 if (unlikely(!ctx->altivec_enabled)) {
6381 gen_exception(ctx, POWERPC_EXCP_VPU);
6382 return;
6383 }
6384 p = gen_avr_ptr(rD(ctx->opcode));
6385 gen_helper_mtvscr(cpu_env, p);
6386 tcg_temp_free_ptr(p);
6387 }
6388
6389 /* Logical operations */
6390 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6391 static void glue(gen_, name)(DisasContext *ctx) \
6392 { \
6393 if (unlikely(!ctx->altivec_enabled)) { \
6394 gen_exception(ctx, POWERPC_EXCP_VPU); \
6395 return; \
6396 } \
6397 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6398 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6399 }
6400
6401 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6402 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6403 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6404 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6405 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6406
6407 #define GEN_VXFORM(name, opc2, opc3) \
6408 static void glue(gen_, name)(DisasContext *ctx) \
6409 { \
6410 TCGv_ptr ra, rb, rd; \
6411 if (unlikely(!ctx->altivec_enabled)) { \
6412 gen_exception(ctx, POWERPC_EXCP_VPU); \
6413 return; \
6414 } \
6415 ra = gen_avr_ptr(rA(ctx->opcode)); \
6416 rb = gen_avr_ptr(rB(ctx->opcode)); \
6417 rd = gen_avr_ptr(rD(ctx->opcode)); \
6418 gen_helper_##name (rd, ra, rb); \
6419 tcg_temp_free_ptr(ra); \
6420 tcg_temp_free_ptr(rb); \
6421 tcg_temp_free_ptr(rd); \
6422 }
6423
6424 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6425 static void glue(gen_, name)(DisasContext *ctx) \
6426 { \
6427 TCGv_ptr ra, rb, rd; \
6428 if (unlikely(!ctx->altivec_enabled)) { \
6429 gen_exception(ctx, POWERPC_EXCP_VPU); \
6430 return; \
6431 } \
6432 ra = gen_avr_ptr(rA(ctx->opcode)); \
6433 rb = gen_avr_ptr(rB(ctx->opcode)); \
6434 rd = gen_avr_ptr(rD(ctx->opcode)); \
6435 gen_helper_##name(cpu_env, rd, ra, rb); \
6436 tcg_temp_free_ptr(ra); \
6437 tcg_temp_free_ptr(rb); \
6438 tcg_temp_free_ptr(rd); \
6439 }
6440
6441 GEN_VXFORM(vaddubm, 0, 0);
6442 GEN_VXFORM(vadduhm, 0, 1);
6443 GEN_VXFORM(vadduwm, 0, 2);
6444 GEN_VXFORM(vsububm, 0, 16);
6445 GEN_VXFORM(vsubuhm, 0, 17);
6446 GEN_VXFORM(vsubuwm, 0, 18);
6447 GEN_VXFORM(vmaxub, 1, 0);
6448 GEN_VXFORM(vmaxuh, 1, 1);
6449 GEN_VXFORM(vmaxuw, 1, 2);
6450 GEN_VXFORM(vmaxsb, 1, 4);
6451 GEN_VXFORM(vmaxsh, 1, 5);
6452 GEN_VXFORM(vmaxsw, 1, 6);
6453 GEN_VXFORM(vminub, 1, 8);
6454 GEN_VXFORM(vminuh, 1, 9);
6455 GEN_VXFORM(vminuw, 1, 10);
6456 GEN_VXFORM(vminsb, 1, 12);
6457 GEN_VXFORM(vminsh, 1, 13);
6458 GEN_VXFORM(vminsw, 1, 14);
6459 GEN_VXFORM(vavgub, 1, 16);
6460 GEN_VXFORM(vavguh, 1, 17);
6461 GEN_VXFORM(vavguw, 1, 18);
6462 GEN_VXFORM(vavgsb, 1, 20);
6463 GEN_VXFORM(vavgsh, 1, 21);
6464 GEN_VXFORM(vavgsw, 1, 22);
6465 GEN_VXFORM(vmrghb, 6, 0);
6466 GEN_VXFORM(vmrghh, 6, 1);
6467 GEN_VXFORM(vmrghw, 6, 2);
6468 GEN_VXFORM(vmrglb, 6, 4);
6469 GEN_VXFORM(vmrglh, 6, 5);
6470 GEN_VXFORM(vmrglw, 6, 6);
6471 GEN_VXFORM(vmuloub, 4, 0);
6472 GEN_VXFORM(vmulouh, 4, 1);
6473 GEN_VXFORM(vmulosb, 4, 4);
6474 GEN_VXFORM(vmulosh, 4, 5);
6475 GEN_VXFORM(vmuleub, 4, 8);
6476 GEN_VXFORM(vmuleuh, 4, 9);
6477 GEN_VXFORM(vmulesb, 4, 12);
6478 GEN_VXFORM(vmulesh, 4, 13);
6479 GEN_VXFORM(vslb, 2, 4);
6480 GEN_VXFORM(vslh, 2, 5);
6481 GEN_VXFORM(vslw, 2, 6);
6482 GEN_VXFORM(vsrb, 2, 8);
6483 GEN_VXFORM(vsrh, 2, 9);
6484 GEN_VXFORM(vsrw, 2, 10);
6485 GEN_VXFORM(vsrab, 2, 12);
6486 GEN_VXFORM(vsrah, 2, 13);
6487 GEN_VXFORM(vsraw, 2, 14);
6488 GEN_VXFORM(vslo, 6, 16);
6489 GEN_VXFORM(vsro, 6, 17);
6490 GEN_VXFORM(vaddcuw, 0, 6);
6491 GEN_VXFORM(vsubcuw, 0, 22);
6492 GEN_VXFORM_ENV(vaddubs, 0, 8);
6493 GEN_VXFORM_ENV(vadduhs, 0, 9);
6494 GEN_VXFORM_ENV(vadduws, 0, 10);
6495 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6496 GEN_VXFORM_ENV(vaddshs, 0, 13);
6497 GEN_VXFORM_ENV(vaddsws, 0, 14);
6498 GEN_VXFORM_ENV(vsububs, 0, 24);
6499 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6500 GEN_VXFORM_ENV(vsubuws, 0, 26);
6501 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6502 GEN_VXFORM_ENV(vsubshs, 0, 29);
6503 GEN_VXFORM_ENV(vsubsws, 0, 30);
6504 GEN_VXFORM(vrlb, 2, 0);
6505 GEN_VXFORM(vrlh, 2, 1);
6506 GEN_VXFORM(vrlw, 2, 2);
6507 GEN_VXFORM(vsl, 2, 7);
6508 GEN_VXFORM(vsr, 2, 11);
6509 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6510 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6511 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6512 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6513 GEN_VXFORM_ENV(vpkshus, 7, 4);
6514 GEN_VXFORM_ENV(vpkswus, 7, 5);
6515 GEN_VXFORM_ENV(vpkshss, 7, 6);
6516 GEN_VXFORM_ENV(vpkswss, 7, 7);
6517 GEN_VXFORM(vpkpx, 7, 12);
6518 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6519 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6520 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6521 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6522 GEN_VXFORM_ENV(vsumsws, 4, 30);
6523 GEN_VXFORM_ENV(vaddfp, 5, 0);
6524 GEN_VXFORM_ENV(vsubfp, 5, 1);
6525 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6526 GEN_VXFORM_ENV(vminfp, 5, 17);
6527
6528 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6529 static void glue(gen_, name)(DisasContext *ctx) \
6530 { \
6531 TCGv_ptr ra, rb, rd; \
6532 if (unlikely(!ctx->altivec_enabled)) { \
6533 gen_exception(ctx, POWERPC_EXCP_VPU); \
6534 return; \
6535 } \
6536 ra = gen_avr_ptr(rA(ctx->opcode)); \
6537 rb = gen_avr_ptr(rB(ctx->opcode)); \
6538 rd = gen_avr_ptr(rD(ctx->opcode)); \
6539 gen_helper_##opname(cpu_env, rd, ra, rb); \
6540 tcg_temp_free_ptr(ra); \
6541 tcg_temp_free_ptr(rb); \
6542 tcg_temp_free_ptr(rd); \
6543 }
6544
6545 #define GEN_VXRFORM(name, opc2, opc3) \
6546 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6547 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6548
6549 GEN_VXRFORM(vcmpequb, 3, 0)
6550 GEN_VXRFORM(vcmpequh, 3, 1)
6551 GEN_VXRFORM(vcmpequw, 3, 2)
6552 GEN_VXRFORM(vcmpgtsb, 3, 12)
6553 GEN_VXRFORM(vcmpgtsh, 3, 13)
6554 GEN_VXRFORM(vcmpgtsw, 3, 14)
6555 GEN_VXRFORM(vcmpgtub, 3, 8)
6556 GEN_VXRFORM(vcmpgtuh, 3, 9)
6557 GEN_VXRFORM(vcmpgtuw, 3, 10)
6558 GEN_VXRFORM(vcmpeqfp, 3, 3)
6559 GEN_VXRFORM(vcmpgefp, 3, 7)
6560 GEN_VXRFORM(vcmpgtfp, 3, 11)
6561 GEN_VXRFORM(vcmpbfp, 3, 15)
6562
6563 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6564 static void glue(gen_, name)(DisasContext *ctx) \
6565 { \
6566 TCGv_ptr rd; \
6567 TCGv_i32 simm; \
6568 if (unlikely(!ctx->altivec_enabled)) { \
6569 gen_exception(ctx, POWERPC_EXCP_VPU); \
6570 return; \
6571 } \
6572 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6573 rd = gen_avr_ptr(rD(ctx->opcode)); \
6574 gen_helper_##name (rd, simm); \
6575 tcg_temp_free_i32(simm); \
6576 tcg_temp_free_ptr(rd); \
6577 }
6578
6579 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6580 GEN_VXFORM_SIMM(vspltish, 6, 13);
6581 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6582
6583 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6584 static void glue(gen_, name)(DisasContext *ctx) \
6585 { \
6586 TCGv_ptr rb, rd; \
6587 if (unlikely(!ctx->altivec_enabled)) { \
6588 gen_exception(ctx, POWERPC_EXCP_VPU); \
6589 return; \
6590 } \
6591 rb = gen_avr_ptr(rB(ctx->opcode)); \
6592 rd = gen_avr_ptr(rD(ctx->opcode)); \
6593 gen_helper_##name (rd, rb); \
6594 tcg_temp_free_ptr(rb); \
6595 tcg_temp_free_ptr(rd); \
6596 }
6597
6598 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6599 static void glue(gen_, name)(DisasContext *ctx) \
6600 { \
6601 TCGv_ptr rb, rd; \
6602 \
6603 if (unlikely(!ctx->altivec_enabled)) { \
6604 gen_exception(ctx, POWERPC_EXCP_VPU); \
6605 return; \
6606 } \
6607 rb = gen_avr_ptr(rB(ctx->opcode)); \
6608 rd = gen_avr_ptr(rD(ctx->opcode)); \
6609 gen_helper_##name(cpu_env, rd, rb); \
6610 tcg_temp_free_ptr(rb); \
6611 tcg_temp_free_ptr(rd); \
6612 }
6613
6614 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6615 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6616 GEN_VXFORM_NOA(vupklsb, 7, 10);
6617 GEN_VXFORM_NOA(vupklsh, 7, 11);
6618 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6619 GEN_VXFORM_NOA(vupklpx, 7, 15);
6620 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6621 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6622 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6623 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6624 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6625 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6626 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6627 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6628
6629 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6630 static void glue(gen_, name)(DisasContext *ctx) \
6631 { \
6632 TCGv_ptr rd; \
6633 TCGv_i32 simm; \
6634 if (unlikely(!ctx->altivec_enabled)) { \
6635 gen_exception(ctx, POWERPC_EXCP_VPU); \
6636 return; \
6637 } \
6638 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6639 rd = gen_avr_ptr(rD(ctx->opcode)); \
6640 gen_helper_##name (rd, simm); \
6641 tcg_temp_free_i32(simm); \
6642 tcg_temp_free_ptr(rd); \
6643 }
6644
6645 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6646 static void glue(gen_, name)(DisasContext *ctx) \
6647 { \
6648 TCGv_ptr rb, rd; \
6649 TCGv_i32 uimm; \
6650 if (unlikely(!ctx->altivec_enabled)) { \
6651 gen_exception(ctx, POWERPC_EXCP_VPU); \
6652 return; \
6653 } \
6654 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6655 rb = gen_avr_ptr(rB(ctx->opcode)); \
6656 rd = gen_avr_ptr(rD(ctx->opcode)); \
6657 gen_helper_##name (rd, rb, uimm); \
6658 tcg_temp_free_i32(uimm); \
6659 tcg_temp_free_ptr(rb); \
6660 tcg_temp_free_ptr(rd); \
6661 }
6662
6663 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6664 static void glue(gen_, name)(DisasContext *ctx) \
6665 { \
6666 TCGv_ptr rb, rd; \
6667 TCGv_i32 uimm; \
6668 \
6669 if (unlikely(!ctx->altivec_enabled)) { \
6670 gen_exception(ctx, POWERPC_EXCP_VPU); \
6671 return; \
6672 } \
6673 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6674 rb = gen_avr_ptr(rB(ctx->opcode)); \
6675 rd = gen_avr_ptr(rD(ctx->opcode)); \
6676 gen_helper_##name(cpu_env, rd, rb, uimm); \
6677 tcg_temp_free_i32(uimm); \
6678 tcg_temp_free_ptr(rb); \
6679 tcg_temp_free_ptr(rd); \
6680 }
6681
6682 GEN_VXFORM_UIMM(vspltb, 6, 8);
6683 GEN_VXFORM_UIMM(vsplth, 6, 9);
6684 GEN_VXFORM_UIMM(vspltw, 6, 10);
6685 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6686 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6687 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6688 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6689
6690 static void gen_vsldoi(DisasContext *ctx)
6691 {
6692 TCGv_ptr ra, rb, rd;
6693 TCGv_i32 sh;
6694 if (unlikely(!ctx->altivec_enabled)) {
6695 gen_exception(ctx, POWERPC_EXCP_VPU);
6696 return;
6697 }
6698 ra = gen_avr_ptr(rA(ctx->opcode));
6699 rb = gen_avr_ptr(rB(ctx->opcode));
6700 rd = gen_avr_ptr(rD(ctx->opcode));
6701 sh = tcg_const_i32(VSH(ctx->opcode));
6702 gen_helper_vsldoi (rd, ra, rb, sh);
6703 tcg_temp_free_ptr(ra);
6704 tcg_temp_free_ptr(rb);
6705 tcg_temp_free_ptr(rd);
6706 tcg_temp_free_i32(sh);
6707 }
6708
6709 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6710 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6711 { \
6712 TCGv_ptr ra, rb, rc, rd; \
6713 if (unlikely(!ctx->altivec_enabled)) { \
6714 gen_exception(ctx, POWERPC_EXCP_VPU); \
6715 return; \
6716 } \
6717 ra = gen_avr_ptr(rA(ctx->opcode)); \
6718 rb = gen_avr_ptr(rB(ctx->opcode)); \
6719 rc = gen_avr_ptr(rC(ctx->opcode)); \
6720 rd = gen_avr_ptr(rD(ctx->opcode)); \
6721 if (Rc(ctx->opcode)) { \
6722 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6723 } else { \
6724 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6725 } \
6726 tcg_temp_free_ptr(ra); \
6727 tcg_temp_free_ptr(rb); \
6728 tcg_temp_free_ptr(rc); \
6729 tcg_temp_free_ptr(rd); \
6730 }
6731
6732 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6733
6734 static void gen_vmladduhm(DisasContext *ctx)
6735 {
6736 TCGv_ptr ra, rb, rc, rd;
6737 if (unlikely(!ctx->altivec_enabled)) {
6738 gen_exception(ctx, POWERPC_EXCP_VPU);
6739 return;
6740 }
6741 ra = gen_avr_ptr(rA(ctx->opcode));
6742 rb = gen_avr_ptr(rB(ctx->opcode));
6743 rc = gen_avr_ptr(rC(ctx->opcode));
6744 rd = gen_avr_ptr(rD(ctx->opcode));
6745 gen_helper_vmladduhm(rd, ra, rb, rc);
6746 tcg_temp_free_ptr(ra);
6747 tcg_temp_free_ptr(rb);
6748 tcg_temp_free_ptr(rc);
6749 tcg_temp_free_ptr(rd);
6750 }
6751
6752 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6753 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6754 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6755 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6756 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6757
6758 /*** SPE extension ***/
6759 /* Register moves */
6760
6761
6762 static inline void gen_evmra(DisasContext *ctx)
6763 {
6764
6765 if (unlikely(!ctx->spe_enabled)) {
6766 gen_exception(ctx, POWERPC_EXCP_SPEU);
6767 return;
6768 }
6769
6770 #if defined(TARGET_PPC64)
6771 /* rD := rA */
6772 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6773
6774 /* spe_acc := rA */
6775 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6776 cpu_env,
6777 offsetof(CPUPPCState, spe_acc));
6778 #else
6779 TCGv_i64 tmp = tcg_temp_new_i64();
6780
6781 /* tmp := rA_lo + rA_hi << 32 */
6782 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6783
6784 /* spe_acc := tmp */
6785 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6786 tcg_temp_free_i64(tmp);
6787
6788 /* rD := rA */
6789 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6790 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6791 #endif
6792 }
6793
6794 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6795 {
6796 #if defined(TARGET_PPC64)
6797 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6798 #else
6799 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6800 #endif
6801 }
6802
6803 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6804 {
6805 #if defined(TARGET_PPC64)
6806 tcg_gen_mov_i64(cpu_gpr[reg], t);
6807 #else
6808 TCGv_i64 tmp = tcg_temp_new_i64();
6809 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6810 tcg_gen_shri_i64(tmp, t, 32);
6811 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6812 tcg_temp_free_i64(tmp);
6813 #endif
6814 }
6815
6816 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6817 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6818 { \
6819 if (Rc(ctx->opcode)) \
6820 gen_##name1(ctx); \
6821 else \
6822 gen_##name0(ctx); \
6823 }
6824
6825 /* Handler for undefined SPE opcodes */
6826 static inline void gen_speundef(DisasContext *ctx)
6827 {
6828 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6829 }
6830
6831 /* SPE logic */
6832 #if defined(TARGET_PPC64)
6833 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6834 static inline void gen_##name(DisasContext *ctx) \
6835 { \
6836 if (unlikely(!ctx->spe_enabled)) { \
6837 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6838 return; \
6839 } \
6840 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6841 cpu_gpr[rB(ctx->opcode)]); \
6842 }
6843 #else
6844 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6845 static inline void gen_##name(DisasContext *ctx) \
6846 { \
6847 if (unlikely(!ctx->spe_enabled)) { \
6848 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6849 return; \
6850 } \
6851 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6852 cpu_gpr[rB(ctx->opcode)]); \
6853 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6854 cpu_gprh[rB(ctx->opcode)]); \
6855 }
6856 #endif
6857
6858 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6859 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6860 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6861 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6862 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6863 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6864 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6865 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6866
6867 /* SPE logic immediate */
6868 #if defined(TARGET_PPC64)
6869 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6870 static inline void gen_##name(DisasContext *ctx) \
6871 { \
6872 if (unlikely(!ctx->spe_enabled)) { \
6873 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6874 return; \
6875 } \
6876 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6877 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6878 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6879 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6880 tcg_opi(t0, t0, rB(ctx->opcode)); \
6881 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6882 tcg_gen_trunc_i64_i32(t1, t2); \
6883 tcg_temp_free_i64(t2); \
6884 tcg_opi(t1, t1, rB(ctx->opcode)); \
6885 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6886 tcg_temp_free_i32(t0); \
6887 tcg_temp_free_i32(t1); \
6888 }
6889 #else
6890 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6891 static inline void gen_##name(DisasContext *ctx) \
6892 { \
6893 if (unlikely(!ctx->spe_enabled)) { \
6894 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6895 return; \
6896 } \
6897 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6898 rB(ctx->opcode)); \
6899 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6900 rB(ctx->opcode)); \
6901 }
6902 #endif
6903 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6904 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6905 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6906 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6907
6908 /* SPE arithmetic */
6909 #if defined(TARGET_PPC64)
6910 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6911 static inline void gen_##name(DisasContext *ctx) \
6912 { \
6913 if (unlikely(!ctx->spe_enabled)) { \
6914 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6915 return; \
6916 } \
6917 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6918 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6919 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6920 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6921 tcg_op(t0, t0); \
6922 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6923 tcg_gen_trunc_i64_i32(t1, t2); \
6924 tcg_temp_free_i64(t2); \
6925 tcg_op(t1, t1); \
6926 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6927 tcg_temp_free_i32(t0); \
6928 tcg_temp_free_i32(t1); \
6929 }
6930 #else
6931 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6932 static inline void gen_##name(DisasContext *ctx) \
6933 { \
6934 if (unlikely(!ctx->spe_enabled)) { \
6935 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6936 return; \
6937 } \
6938 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6939 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6940 }
6941 #endif
6942
6943 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6944 {
6945 int l1 = gen_new_label();
6946 int l2 = gen_new_label();
6947
6948 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6949 tcg_gen_neg_i32(ret, arg1);
6950 tcg_gen_br(l2);
6951 gen_set_label(l1);
6952 tcg_gen_mov_i32(ret, arg1);
6953 gen_set_label(l2);
6954 }
6955 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6956 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6957 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6958 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6959 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6960 {
6961 tcg_gen_addi_i32(ret, arg1, 0x8000);
6962 tcg_gen_ext16u_i32(ret, ret);
6963 }
6964 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6965 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6966 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6967
6968 #if defined(TARGET_PPC64)
6969 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6970 static inline void gen_##name(DisasContext *ctx) \
6971 { \
6972 if (unlikely(!ctx->spe_enabled)) { \
6973 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6974 return; \
6975 } \
6976 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6977 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6978 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6979 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6980 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6981 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6982 tcg_op(t0, t0, t2); \
6983 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6984 tcg_gen_trunc_i64_i32(t1, t3); \
6985 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6986 tcg_gen_trunc_i64_i32(t2, t3); \
6987 tcg_temp_free_i64(t3); \
6988 tcg_op(t1, t1, t2); \
6989 tcg_temp_free_i32(t2); \
6990 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6991 tcg_temp_free_i32(t0); \
6992 tcg_temp_free_i32(t1); \
6993 }
6994 #else
6995 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6996 static inline void gen_##name(DisasContext *ctx) \
6997 { \
6998 if (unlikely(!ctx->spe_enabled)) { \
6999 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7000 return; \
7001 } \
7002 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7003 cpu_gpr[rB(ctx->opcode)]); \
7004 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7005 cpu_gprh[rB(ctx->opcode)]); \
7006 }
7007 #endif
7008
7009 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7010 {
7011 TCGv_i32 t0;
7012 int l1, l2;
7013
7014 l1 = gen_new_label();
7015 l2 = gen_new_label();
7016 t0 = tcg_temp_local_new_i32();
7017 /* No error here: 6 bits are used */
7018 tcg_gen_andi_i32(t0, arg2, 0x3F);
7019 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7020 tcg_gen_shr_i32(ret, arg1, t0);
7021 tcg_gen_br(l2);
7022 gen_set_label(l1);
7023 tcg_gen_movi_i32(ret, 0);
7024 gen_set_label(l2);
7025 tcg_temp_free_i32(t0);
7026 }
7027 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7028 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7029 {
7030 TCGv_i32 t0;
7031 int l1, l2;
7032
7033 l1 = gen_new_label();
7034 l2 = gen_new_label();
7035 t0 = tcg_temp_local_new_i32();
7036 /* No error here: 6 bits are used */
7037 tcg_gen_andi_i32(t0, arg2, 0x3F);
7038 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7039 tcg_gen_sar_i32(ret, arg1, t0);
7040 tcg_gen_br(l2);
7041 gen_set_label(l1);
7042 tcg_gen_movi_i32(ret, 0);
7043 gen_set_label(l2);
7044 tcg_temp_free_i32(t0);
7045 }
7046 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7047 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7048 {
7049 TCGv_i32 t0;
7050 int l1, l2;
7051
7052 l1 = gen_new_label();
7053 l2 = gen_new_label();
7054 t0 = tcg_temp_local_new_i32();
7055 /* No error here: 6 bits are used */
7056 tcg_gen_andi_i32(t0, arg2, 0x3F);
7057 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7058 tcg_gen_shl_i32(ret, arg1, t0);
7059 tcg_gen_br(l2);
7060 gen_set_label(l1);
7061 tcg_gen_movi_i32(ret, 0);
7062 gen_set_label(l2);
7063 tcg_temp_free_i32(t0);
7064 }
7065 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7066 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7067 {
7068 TCGv_i32 t0 = tcg_temp_new_i32();
7069 tcg_gen_andi_i32(t0, arg2, 0x1F);
7070 tcg_gen_rotl_i32(ret, arg1, t0);
7071 tcg_temp_free_i32(t0);
7072 }
7073 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7074 static inline void gen_evmergehi(DisasContext *ctx)
7075 {
7076 if (unlikely(!ctx->spe_enabled)) {
7077 gen_exception(ctx, POWERPC_EXCP_SPEU);
7078 return;
7079 }
7080 #if defined(TARGET_PPC64)
7081 TCGv t0 = tcg_temp_new();
7082 TCGv t1 = tcg_temp_new();
7083 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7084 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7085 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7086 tcg_temp_free(t0);
7087 tcg_temp_free(t1);
7088 #else
7089 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7090 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7091 #endif
7092 }
7093 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7094 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7095 {
7096 tcg_gen_sub_i32(ret, arg2, arg1);
7097 }
7098 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7099
7100 /* SPE arithmetic immediate */
7101 #if defined(TARGET_PPC64)
7102 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7103 static inline void gen_##name(DisasContext *ctx) \
7104 { \
7105 if (unlikely(!ctx->spe_enabled)) { \
7106 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7107 return; \
7108 } \
7109 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7110 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7111 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7112 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7113 tcg_op(t0, t0, rA(ctx->opcode)); \
7114 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7115 tcg_gen_trunc_i64_i32(t1, t2); \
7116 tcg_temp_free_i64(t2); \
7117 tcg_op(t1, t1, rA(ctx->opcode)); \
7118 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7119 tcg_temp_free_i32(t0); \
7120 tcg_temp_free_i32(t1); \
7121 }
7122 #else
7123 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7124 static inline void gen_##name(DisasContext *ctx) \
7125 { \
7126 if (unlikely(!ctx->spe_enabled)) { \
7127 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7128 return; \
7129 } \
7130 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7131 rA(ctx->opcode)); \
7132 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7133 rA(ctx->opcode)); \
7134 }
7135 #endif
7136 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7137 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7138
7139 /* SPE comparison */
7140 #if defined(TARGET_PPC64)
7141 #define GEN_SPEOP_COMP(name, tcg_cond) \
7142 static inline void gen_##name(DisasContext *ctx) \
7143 { \
7144 if (unlikely(!ctx->spe_enabled)) { \
7145 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7146 return; \
7147 } \
7148 int l1 = gen_new_label(); \
7149 int l2 = gen_new_label(); \
7150 int l3 = gen_new_label(); \
7151 int l4 = gen_new_label(); \
7152 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7153 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7154 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7155 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7156 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7157 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7158 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7159 tcg_gen_br(l2); \
7160 gen_set_label(l1); \
7161 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7162 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7163 gen_set_label(l2); \
7164 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7165 tcg_gen_trunc_i64_i32(t0, t2); \
7166 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7167 tcg_gen_trunc_i64_i32(t1, t2); \
7168 tcg_temp_free_i64(t2); \
7169 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7170 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7171 ~(CRF_CH | CRF_CH_AND_CL)); \
7172 tcg_gen_br(l4); \
7173 gen_set_label(l3); \
7174 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7175 CRF_CH | CRF_CH_OR_CL); \
7176 gen_set_label(l4); \
7177 tcg_temp_free_i32(t0); \
7178 tcg_temp_free_i32(t1); \
7179 }
7180 #else
7181 #define GEN_SPEOP_COMP(name, tcg_cond) \
7182 static inline void gen_##name(DisasContext *ctx) \
7183 { \
7184 if (unlikely(!ctx->spe_enabled)) { \
7185 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7186 return; \
7187 } \
7188 int l1 = gen_new_label(); \
7189 int l2 = gen_new_label(); \
7190 int l3 = gen_new_label(); \
7191 int l4 = gen_new_label(); \
7192 \
7193 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7194 cpu_gpr[rB(ctx->opcode)], l1); \
7195 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7196 tcg_gen_br(l2); \
7197 gen_set_label(l1); \
7198 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7199 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7200 gen_set_label(l2); \
7201 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7202 cpu_gprh[rB(ctx->opcode)], l3); \
7203 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7204 ~(CRF_CH | CRF_CH_AND_CL)); \
7205 tcg_gen_br(l4); \
7206 gen_set_label(l3); \
7207 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7208 CRF_CH | CRF_CH_OR_CL); \
7209 gen_set_label(l4); \
7210 }
7211 #endif
7212 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7213 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7214 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7215 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7216 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7217
7218 /* SPE misc */
7219 static inline void gen_brinc(DisasContext *ctx)
7220 {
7221 /* Note: brinc is usable even if SPE is disabled */
7222 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7223 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7224 }
7225 static inline void gen_evmergelo(DisasContext *ctx)
7226 {
7227 if (unlikely(!ctx->spe_enabled)) {
7228 gen_exception(ctx, POWERPC_EXCP_SPEU);
7229 return;
7230 }
7231 #if defined(TARGET_PPC64)
7232 TCGv t0 = tcg_temp_new();
7233 TCGv t1 = tcg_temp_new();
7234 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7235 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7236 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7237 tcg_temp_free(t0);
7238 tcg_temp_free(t1);
7239 #else
7240 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7241 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7242 #endif
7243 }
7244 static inline void gen_evmergehilo(DisasContext *ctx)
7245 {
7246 if (unlikely(!ctx->spe_enabled)) {
7247 gen_exception(ctx, POWERPC_EXCP_SPEU);
7248 return;
7249 }
7250 #if defined(TARGET_PPC64)
7251 TCGv t0 = tcg_temp_new();
7252 TCGv t1 = tcg_temp_new();
7253 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7254 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7255 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7256 tcg_temp_free(t0);
7257 tcg_temp_free(t1);
7258 #else
7259 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7260 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7261 #endif
7262 }
7263 static inline void gen_evmergelohi(DisasContext *ctx)
7264 {
7265 if (unlikely(!ctx->spe_enabled)) {
7266 gen_exception(ctx, POWERPC_EXCP_SPEU);
7267 return;
7268 }
7269 #if defined(TARGET_PPC64)
7270 TCGv t0 = tcg_temp_new();
7271 TCGv t1 = tcg_temp_new();
7272 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7273 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7274 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7275 tcg_temp_free(t0);
7276 tcg_temp_free(t1);
7277 #else
7278 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7279 TCGv_i32 tmp = tcg_temp_new_i32();
7280 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7281 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7282 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7283 tcg_temp_free_i32(tmp);
7284 } else {
7285 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7286 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7287 }
7288 #endif
7289 }
7290 static inline void gen_evsplati(DisasContext *ctx)
7291 {
7292 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7293
7294 #if defined(TARGET_PPC64)
7295 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7296 #else
7297 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7298 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7299 #endif
7300 }
7301 static inline void gen_evsplatfi(DisasContext *ctx)
7302 {
7303 uint64_t imm = rA(ctx->opcode) << 27;
7304
7305 #if defined(TARGET_PPC64)
7306 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7307 #else
7308 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7309 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7310 #endif
7311 }
7312
7313 static inline void gen_evsel(DisasContext *ctx)
7314 {
7315 int l1 = gen_new_label();
7316 int l2 = gen_new_label();
7317 int l3 = gen_new_label();
7318 int l4 = gen_new_label();
7319 TCGv_i32 t0 = tcg_temp_local_new_i32();
7320 #if defined(TARGET_PPC64)
7321 TCGv t1 = tcg_temp_local_new();
7322 TCGv t2 = tcg_temp_local_new();
7323 #endif
7324 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7325 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7326 #if defined(TARGET_PPC64)
7327 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7328 #else
7329 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7330 #endif
7331 tcg_gen_br(l2);
7332 gen_set_label(l1);
7333 #if defined(TARGET_PPC64)
7334 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7335 #else
7336 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7337 #endif
7338 gen_set_label(l2);
7339 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7340 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7341 #if defined(TARGET_PPC64)
7342 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7343 #else
7344 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7345 #endif
7346 tcg_gen_br(l4);
7347 gen_set_label(l3);
7348 #if defined(TARGET_PPC64)
7349 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7350 #else
7351 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7352 #endif
7353 gen_set_label(l4);
7354 tcg_temp_free_i32(t0);
7355 #if defined(TARGET_PPC64)
7356 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7357 tcg_temp_free(t1);
7358 tcg_temp_free(t2);
7359 #endif
7360 }
7361
7362 static void gen_evsel0(DisasContext *ctx)
7363 {
7364 gen_evsel(ctx);
7365 }
7366
7367 static void gen_evsel1(DisasContext *ctx)
7368 {
7369 gen_evsel(ctx);
7370 }
7371
7372 static void gen_evsel2(DisasContext *ctx)
7373 {
7374 gen_evsel(ctx);
7375 }
7376
7377 static void gen_evsel3(DisasContext *ctx)
7378 {
7379 gen_evsel(ctx);
7380 }
7381
7382 /* Multiply */
7383
7384 static inline void gen_evmwumi(DisasContext *ctx)
7385 {
7386 TCGv_i64 t0, t1;
7387
7388 if (unlikely(!ctx->spe_enabled)) {
7389 gen_exception(ctx, POWERPC_EXCP_SPEU);
7390 return;
7391 }
7392
7393 t0 = tcg_temp_new_i64();
7394 t1 = tcg_temp_new_i64();
7395
7396 /* t0 := rA; t1 := rB */
7397 #if defined(TARGET_PPC64)
7398 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7399 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7400 #else
7401 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7402 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7403 #endif
7404
7405 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7406
7407 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7408
7409 tcg_temp_free_i64(t0);
7410 tcg_temp_free_i64(t1);
7411 }
7412
7413 static inline void gen_evmwumia(DisasContext *ctx)
7414 {
7415 TCGv_i64 tmp;
7416
7417 if (unlikely(!ctx->spe_enabled)) {
7418 gen_exception(ctx, POWERPC_EXCP_SPEU);
7419 return;
7420 }
7421
7422 gen_evmwumi(ctx); /* rD := rA * rB */
7423
7424 tmp = tcg_temp_new_i64();
7425
7426 /* acc := rD */
7427 gen_load_gpr64(tmp, rD(ctx->opcode));
7428 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7429 tcg_temp_free_i64(tmp);
7430 }
7431
7432 static inline void gen_evmwumiaa(DisasContext *ctx)
7433 {
7434 TCGv_i64 acc;
7435 TCGv_i64 tmp;
7436
7437 if (unlikely(!ctx->spe_enabled)) {
7438 gen_exception(ctx, POWERPC_EXCP_SPEU);
7439 return;
7440 }
7441
7442 gen_evmwumi(ctx); /* rD := rA * rB */
7443
7444 acc = tcg_temp_new_i64();
7445 tmp = tcg_temp_new_i64();
7446
7447 /* tmp := rD */
7448 gen_load_gpr64(tmp, rD(ctx->opcode));
7449
7450 /* Load acc */
7451 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7452
7453 /* acc := tmp + acc */
7454 tcg_gen_add_i64(acc, acc, tmp);
7455
7456 /* Store acc */
7457 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7458
7459 /* rD := acc */
7460 gen_store_gpr64(rD(ctx->opcode), acc);
7461
7462 tcg_temp_free_i64(acc);
7463 tcg_temp_free_i64(tmp);
7464 }
7465
7466 static inline void gen_evmwsmi(DisasContext *ctx)
7467 {
7468 TCGv_i64 t0, t1;
7469
7470 if (unlikely(!ctx->spe_enabled)) {
7471 gen_exception(ctx, POWERPC_EXCP_SPEU);
7472 return;
7473 }
7474
7475 t0 = tcg_temp_new_i64();
7476 t1 = tcg_temp_new_i64();
7477
7478 /* t0 := rA; t1 := rB */
7479 #if defined(TARGET_PPC64)
7480 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7481 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7482 #else
7483 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7484 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7485 #endif
7486
7487 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7488
7489 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7490
7491 tcg_temp_free_i64(t0);
7492 tcg_temp_free_i64(t1);
7493 }
7494
7495 static inline void gen_evmwsmia(DisasContext *ctx)
7496 {
7497 TCGv_i64 tmp;
7498
7499 gen_evmwsmi(ctx); /* rD := rA * rB */
7500
7501 tmp = tcg_temp_new_i64();
7502
7503 /* acc := rD */
7504 gen_load_gpr64(tmp, rD(ctx->opcode));
7505 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7506
7507 tcg_temp_free_i64(tmp);
7508 }
7509
7510 static inline void gen_evmwsmiaa(DisasContext *ctx)
7511 {
7512 TCGv_i64 acc = tcg_temp_new_i64();
7513 TCGv_i64 tmp = tcg_temp_new_i64();
7514
7515 gen_evmwsmi(ctx); /* rD := rA * rB */
7516
7517 acc = tcg_temp_new_i64();
7518 tmp = tcg_temp_new_i64();
7519
7520 /* tmp := rD */
7521 gen_load_gpr64(tmp, rD(ctx->opcode));
7522
7523 /* Load acc */
7524 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7525
7526 /* acc := tmp + acc */
7527 tcg_gen_add_i64(acc, acc, tmp);
7528
7529 /* Store acc */
7530 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7531
7532 /* rD := acc */
7533 gen_store_gpr64(rD(ctx->opcode), acc);
7534
7535 tcg_temp_free_i64(acc);
7536 tcg_temp_free_i64(tmp);
7537 }
7538
7539 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7540 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7541 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7542 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7543 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7544 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7545 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7546 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7547 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7548 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7549 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7550 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7551 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7552 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7553 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7554 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7555 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7556 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7557 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7558 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7559 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7560 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7561 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7562 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7563 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7564 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7565 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7566 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7567 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7568
7569 /* SPE load and stores */
7570 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7571 {
7572 target_ulong uimm = rB(ctx->opcode);
7573
7574 if (rA(ctx->opcode) == 0) {
7575 tcg_gen_movi_tl(EA, uimm << sh);
7576 } else {
7577 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7578 #if defined(TARGET_PPC64)
7579 if (!ctx->sf_mode) {
7580 tcg_gen_ext32u_tl(EA, EA);
7581 }
7582 #endif
7583 }
7584 }
7585
7586 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7587 {
7588 #if defined(TARGET_PPC64)
7589 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7590 #else
7591 TCGv_i64 t0 = tcg_temp_new_i64();
7592 gen_qemu_ld64(ctx, t0, addr);
7593 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7594 tcg_gen_shri_i64(t0, t0, 32);
7595 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7596 tcg_temp_free_i64(t0);
7597 #endif
7598 }
7599
7600 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7601 {
7602 #if defined(TARGET_PPC64)
7603 TCGv t0 = tcg_temp_new();
7604 gen_qemu_ld32u(ctx, t0, addr);
7605 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7606 gen_addr_add(ctx, addr, addr, 4);
7607 gen_qemu_ld32u(ctx, t0, addr);
7608 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7609 tcg_temp_free(t0);
7610 #else
7611 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7612 gen_addr_add(ctx, addr, addr, 4);
7613 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7614 #endif
7615 }
7616
7617 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7618 {
7619 TCGv t0 = tcg_temp_new();
7620 #if defined(TARGET_PPC64)
7621 gen_qemu_ld16u(ctx, t0, addr);
7622 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7623 gen_addr_add(ctx, addr, addr, 2);
7624 gen_qemu_ld16u(ctx, t0, addr);
7625 tcg_gen_shli_tl(t0, t0, 32);
7626 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7627 gen_addr_add(ctx, addr, addr, 2);
7628 gen_qemu_ld16u(ctx, t0, addr);
7629 tcg_gen_shli_tl(t0, t0, 16);
7630 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7631 gen_addr_add(ctx, addr, addr, 2);
7632 gen_qemu_ld16u(ctx, t0, addr);
7633 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7634 #else
7635 gen_qemu_ld16u(ctx, t0, addr);
7636 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7637 gen_addr_add(ctx, addr, addr, 2);
7638 gen_qemu_ld16u(ctx, t0, addr);
7639 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7640 gen_addr_add(ctx, addr, addr, 2);
7641 gen_qemu_ld16u(ctx, t0, addr);
7642 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7643 gen_addr_add(ctx, addr, addr, 2);
7644 gen_qemu_ld16u(ctx, t0, addr);
7645 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7646 #endif
7647 tcg_temp_free(t0);
7648 }
7649
7650 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7651 {
7652 TCGv t0 = tcg_temp_new();
7653 gen_qemu_ld16u(ctx, t0, addr);
7654 #if defined(TARGET_PPC64)
7655 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7656 tcg_gen_shli_tl(t0, t0, 16);
7657 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7658 #else
7659 tcg_gen_shli_tl(t0, t0, 16);
7660 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7661 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7662 #endif
7663 tcg_temp_free(t0);
7664 }
7665
7666 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7667 {
7668 TCGv t0 = tcg_temp_new();
7669 gen_qemu_ld16u(ctx, t0, addr);
7670 #if defined(TARGET_PPC64)
7671 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7672 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7673 #else
7674 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7675 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7676 #endif
7677 tcg_temp_free(t0);
7678 }
7679
7680 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7681 {
7682 TCGv t0 = tcg_temp_new();
7683 gen_qemu_ld16s(ctx, t0, addr);
7684 #if defined(TARGET_PPC64)
7685 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7686 tcg_gen_ext32u_tl(t0, t0);
7687 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7688 #else
7689 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7690 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7691 #endif
7692 tcg_temp_free(t0);
7693 }
7694
7695 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7696 {
7697 TCGv t0 = tcg_temp_new();
7698 #if defined(TARGET_PPC64)
7699 gen_qemu_ld16u(ctx, t0, addr);
7700 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7701 gen_addr_add(ctx, addr, addr, 2);
7702 gen_qemu_ld16u(ctx, t0, addr);
7703 tcg_gen_shli_tl(t0, t0, 16);
7704 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7705 #else
7706 gen_qemu_ld16u(ctx, t0, addr);
7707 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7708 gen_addr_add(ctx, addr, addr, 2);
7709 gen_qemu_ld16u(ctx, t0, addr);
7710 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7711 #endif
7712 tcg_temp_free(t0);
7713 }
7714
7715 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7716 {
7717 #if defined(TARGET_PPC64)
7718 TCGv t0 = tcg_temp_new();
7719 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7720 gen_addr_add(ctx, addr, addr, 2);
7721 gen_qemu_ld16u(ctx, t0, addr);
7722 tcg_gen_shli_tl(t0, t0, 32);
7723 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7724 tcg_temp_free(t0);
7725 #else
7726 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7727 gen_addr_add(ctx, addr, addr, 2);
7728 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7729 #endif
7730 }
7731
7732 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7733 {
7734 #if defined(TARGET_PPC64)
7735 TCGv t0 = tcg_temp_new();
7736 gen_qemu_ld16s(ctx, t0, addr);
7737 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7738 gen_addr_add(ctx, addr, addr, 2);
7739 gen_qemu_ld16s(ctx, t0, addr);
7740 tcg_gen_shli_tl(t0, t0, 32);
7741 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7742 tcg_temp_free(t0);
7743 #else
7744 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7745 gen_addr_add(ctx, addr, addr, 2);
7746 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7747 #endif
7748 }
7749
7750 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7751 {
7752 TCGv t0 = tcg_temp_new();
7753 gen_qemu_ld32u(ctx, t0, addr);
7754 #if defined(TARGET_PPC64)
7755 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7756 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7757 #else
7758 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7759 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7760 #endif
7761 tcg_temp_free(t0);
7762 }
7763
7764 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7765 {
7766 TCGv t0 = tcg_temp_new();
7767 #if defined(TARGET_PPC64)
7768 gen_qemu_ld16u(ctx, t0, addr);
7769 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7770 tcg_gen_shli_tl(t0, t0, 32);
7771 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7772 gen_addr_add(ctx, addr, addr, 2);
7773 gen_qemu_ld16u(ctx, t0, addr);
7774 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7775 tcg_gen_shli_tl(t0, t0, 16);
7776 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7777 #else
7778 gen_qemu_ld16u(ctx, t0, addr);
7779 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7780 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7781 gen_addr_add(ctx, addr, addr, 2);
7782 gen_qemu_ld16u(ctx, t0, addr);
7783 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7784 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7785 #endif
7786 tcg_temp_free(t0);
7787 }
7788
7789 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7790 {
7791 #if defined(TARGET_PPC64)
7792 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7793 #else
7794 TCGv_i64 t0 = tcg_temp_new_i64();
7795 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7796 gen_qemu_st64(ctx, t0, addr);
7797 tcg_temp_free_i64(t0);
7798 #endif
7799 }
7800
7801 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7802 {
7803 #if defined(TARGET_PPC64)
7804 TCGv t0 = tcg_temp_new();
7805 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7806 gen_qemu_st32(ctx, t0, addr);
7807 tcg_temp_free(t0);
7808 #else
7809 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7810 #endif
7811 gen_addr_add(ctx, addr, addr, 4);
7812 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7813 }
7814
7815 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7816 {
7817 TCGv t0 = tcg_temp_new();
7818 #if defined(TARGET_PPC64)
7819 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7820 #else
7821 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7822 #endif
7823 gen_qemu_st16(ctx, t0, addr);
7824 gen_addr_add(ctx, addr, addr, 2);
7825 #if defined(TARGET_PPC64)
7826 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7827 gen_qemu_st16(ctx, t0, addr);
7828 #else
7829 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7830 #endif
7831 gen_addr_add(ctx, addr, addr, 2);
7832 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7833 gen_qemu_st16(ctx, t0, addr);
7834 tcg_temp_free(t0);
7835 gen_addr_add(ctx, addr, addr, 2);
7836 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7837 }
7838
7839 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7840 {
7841 TCGv t0 = tcg_temp_new();
7842 #if defined(TARGET_PPC64)
7843 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7844 #else
7845 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7846 #endif
7847 gen_qemu_st16(ctx, t0, addr);
7848 gen_addr_add(ctx, addr, addr, 2);
7849 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7850 gen_qemu_st16(ctx, t0, addr);
7851 tcg_temp_free(t0);
7852 }
7853
7854 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7855 {
7856 #if defined(TARGET_PPC64)
7857 TCGv t0 = tcg_temp_new();
7858 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7859 gen_qemu_st16(ctx, t0, addr);
7860 tcg_temp_free(t0);
7861 #else
7862 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7863 #endif
7864 gen_addr_add(ctx, addr, addr, 2);
7865 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7866 }
7867
7868 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7869 {
7870 #if defined(TARGET_PPC64)
7871 TCGv t0 = tcg_temp_new();
7872 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7873 gen_qemu_st32(ctx, t0, addr);
7874 tcg_temp_free(t0);
7875 #else
7876 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7877 #endif
7878 }
7879
7880 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7881 {
7882 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7883 }
7884
7885 #define GEN_SPEOP_LDST(name, opc2, sh) \
7886 static void glue(gen_, name)(DisasContext *ctx) \
7887 { \
7888 TCGv t0; \
7889 if (unlikely(!ctx->spe_enabled)) { \
7890 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7891 return; \
7892 } \
7893 gen_set_access_type(ctx, ACCESS_INT); \
7894 t0 = tcg_temp_new(); \
7895 if (Rc(ctx->opcode)) { \
7896 gen_addr_spe_imm_index(ctx, t0, sh); \
7897 } else { \
7898 gen_addr_reg_index(ctx, t0); \
7899 } \
7900 gen_op_##name(ctx, t0); \
7901 tcg_temp_free(t0); \
7902 }
7903
7904 GEN_SPEOP_LDST(evldd, 0x00, 3);
7905 GEN_SPEOP_LDST(evldw, 0x01, 3);
7906 GEN_SPEOP_LDST(evldh, 0x02, 3);
7907 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7908 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7909 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7910 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7911 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7912 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7913 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7914 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7915
7916 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7917 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7918 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7919 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7920 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7921 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7922 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7923
7924 /* Multiply and add - TODO */
7925 #if 0
7926 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7927 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7928 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7929 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7930 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7931 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7932 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7933 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7934 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7935 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7936 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7937 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7938
7939 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7940 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7941 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7942 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7943 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7944 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7945 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7946 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7947 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7948 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7949 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7950 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7951
7952 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7953 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7954 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7955 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7956 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7957
7958 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7959 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7960 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7961 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7962 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7963 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7964 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7965 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7966 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7967 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7968 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7969 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7970
7971 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7972 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7973 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7974 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7975
7976 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7977 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7978 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7979 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7980 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7981 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7982 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7983 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7984 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7985 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7986 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7987 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7988
7989 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7990 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7991 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7992 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7993 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7994 #endif
7995
7996 /*** SPE floating-point extension ***/
7997 #if defined(TARGET_PPC64)
7998 #define GEN_SPEFPUOP_CONV_32_32(name) \
7999 static inline void gen_##name(DisasContext *ctx) \
8000 { \
8001 TCGv_i32 t0; \
8002 TCGv t1; \
8003 t0 = tcg_temp_new_i32(); \
8004 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8005 gen_helper_##name(t0, cpu_env, t0); \
8006 t1 = tcg_temp_new(); \
8007 tcg_gen_extu_i32_tl(t1, t0); \
8008 tcg_temp_free_i32(t0); \
8009 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8010 0xFFFFFFFF00000000ULL); \
8011 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8012 tcg_temp_free(t1); \
8013 }
8014 #define GEN_SPEFPUOP_CONV_32_64(name) \
8015 static inline void gen_##name(DisasContext *ctx) \
8016 { \
8017 TCGv_i32 t0; \
8018 TCGv t1; \
8019 t0 = tcg_temp_new_i32(); \
8020 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8021 t1 = tcg_temp_new(); \
8022 tcg_gen_extu_i32_tl(t1, t0); \
8023 tcg_temp_free_i32(t0); \
8024 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8025 0xFFFFFFFF00000000ULL); \
8026 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8027 tcg_temp_free(t1); \
8028 }
8029 #define GEN_SPEFPUOP_CONV_64_32(name) \
8030 static inline void gen_##name(DisasContext *ctx) \
8031 { \
8032 TCGv_i32 t0 = tcg_temp_new_i32(); \
8033 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8034 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8035 tcg_temp_free_i32(t0); \
8036 }
8037 #define GEN_SPEFPUOP_CONV_64_64(name) \
8038 static inline void gen_##name(DisasContext *ctx) \
8039 { \
8040 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8041 cpu_gpr[rB(ctx->opcode)]); \
8042 }
8043 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8044 static inline void gen_##name(DisasContext *ctx) \
8045 { \
8046 TCGv_i32 t0, t1; \
8047 TCGv_i64 t2; \
8048 if (unlikely(!ctx->spe_enabled)) { \
8049 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8050 return; \
8051 } \
8052 t0 = tcg_temp_new_i32(); \
8053 t1 = tcg_temp_new_i32(); \
8054 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8055 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8056 gen_helper_##name(t0, cpu_env, t0, t1); \
8057 tcg_temp_free_i32(t1); \
8058 t2 = tcg_temp_new(); \
8059 tcg_gen_extu_i32_tl(t2, t0); \
8060 tcg_temp_free_i32(t0); \
8061 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8062 0xFFFFFFFF00000000ULL); \
8063 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8064 tcg_temp_free(t2); \
8065 }
8066 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8067 static inline void gen_##name(DisasContext *ctx) \
8068 { \
8069 if (unlikely(!ctx->spe_enabled)) { \
8070 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8071 return; \
8072 } \
8073 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8074 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8075 }
8076 #define GEN_SPEFPUOP_COMP_32(name) \
8077 static inline void gen_##name(DisasContext *ctx) \
8078 { \
8079 TCGv_i32 t0, t1; \
8080 if (unlikely(!ctx->spe_enabled)) { \
8081 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8082 return; \
8083 } \
8084 t0 = tcg_temp_new_i32(); \
8085 t1 = tcg_temp_new_i32(); \
8086 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8087 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8088 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8089 tcg_temp_free_i32(t0); \
8090 tcg_temp_free_i32(t1); \
8091 }
8092 #define GEN_SPEFPUOP_COMP_64(name) \
8093 static inline void gen_##name(DisasContext *ctx) \
8094 { \
8095 if (unlikely(!ctx->spe_enabled)) { \
8096 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8097 return; \
8098 } \
8099 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8100 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8101 }
8102 #else
8103 #define GEN_SPEFPUOP_CONV_32_32(name) \
8104 static inline void gen_##name(DisasContext *ctx) \
8105 { \
8106 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8107 cpu_gpr[rB(ctx->opcode)]); \
8108 }
8109 #define GEN_SPEFPUOP_CONV_32_64(name) \
8110 static inline void gen_##name(DisasContext *ctx) \
8111 { \
8112 TCGv_i64 t0 = tcg_temp_new_i64(); \
8113 gen_load_gpr64(t0, rB(ctx->opcode)); \
8114 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8115 tcg_temp_free_i64(t0); \
8116 }
8117 #define GEN_SPEFPUOP_CONV_64_32(name) \
8118 static inline void gen_##name(DisasContext *ctx) \
8119 { \
8120 TCGv_i64 t0 = tcg_temp_new_i64(); \
8121 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8122 gen_store_gpr64(rD(ctx->opcode), t0); \
8123 tcg_temp_free_i64(t0); \
8124 }
8125 #define GEN_SPEFPUOP_CONV_64_64(name) \
8126 static inline void gen_##name(DisasContext *ctx) \
8127 { \
8128 TCGv_i64 t0 = tcg_temp_new_i64(); \
8129 gen_load_gpr64(t0, rB(ctx->opcode)); \
8130 gen_helper_##name(t0, cpu_env, t0); \
8131 gen_store_gpr64(rD(ctx->opcode), t0); \
8132 tcg_temp_free_i64(t0); \
8133 }
8134 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8135 static inline void gen_##name(DisasContext *ctx) \
8136 { \
8137 if (unlikely(!ctx->spe_enabled)) { \
8138 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8139 return; \
8140 } \
8141 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8142 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8143 }
8144 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8145 static inline void gen_##name(DisasContext *ctx) \
8146 { \
8147 TCGv_i64 t0, t1; \
8148 if (unlikely(!ctx->spe_enabled)) { \
8149 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8150 return; \
8151 } \
8152 t0 = tcg_temp_new_i64(); \
8153 t1 = tcg_temp_new_i64(); \
8154 gen_load_gpr64(t0, rA(ctx->opcode)); \
8155 gen_load_gpr64(t1, rB(ctx->opcode)); \
8156 gen_helper_##name(t0, cpu_env, t0, t1); \
8157 gen_store_gpr64(rD(ctx->opcode), t0); \
8158 tcg_temp_free_i64(t0); \
8159 tcg_temp_free_i64(t1); \
8160 }
8161 #define GEN_SPEFPUOP_COMP_32(name) \
8162 static inline void gen_##name(DisasContext *ctx) \
8163 { \
8164 if (unlikely(!ctx->spe_enabled)) { \
8165 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8166 return; \
8167 } \
8168 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8169 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8170 }
8171 #define GEN_SPEFPUOP_COMP_64(name) \
8172 static inline void gen_##name(DisasContext *ctx) \
8173 { \
8174 TCGv_i64 t0, t1; \
8175 if (unlikely(!ctx->spe_enabled)) { \
8176 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8177 return; \
8178 } \
8179 t0 = tcg_temp_new_i64(); \
8180 t1 = tcg_temp_new_i64(); \
8181 gen_load_gpr64(t0, rA(ctx->opcode)); \
8182 gen_load_gpr64(t1, rB(ctx->opcode)); \
8183 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8184 tcg_temp_free_i64(t0); \
8185 tcg_temp_free_i64(t1); \
8186 }
8187 #endif
8188
8189 /* Single precision floating-point vectors operations */
8190 /* Arithmetic */
8191 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8192 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8193 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8194 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8195 static inline void gen_evfsabs(DisasContext *ctx)
8196 {
8197 if (unlikely(!ctx->spe_enabled)) {
8198 gen_exception(ctx, POWERPC_EXCP_SPEU);
8199 return;
8200 }
8201 #if defined(TARGET_PPC64)
8202 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8203 #else
8204 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8205 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8206 #endif
8207 }
8208 static inline void gen_evfsnabs(DisasContext *ctx)
8209 {
8210 if (unlikely(!ctx->spe_enabled)) {
8211 gen_exception(ctx, POWERPC_EXCP_SPEU);
8212 return;
8213 }
8214 #if defined(TARGET_PPC64)
8215 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8216 #else
8217 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8218 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8219 #endif
8220 }
8221 static inline void gen_evfsneg(DisasContext *ctx)
8222 {
8223 if (unlikely(!ctx->spe_enabled)) {
8224 gen_exception(ctx, POWERPC_EXCP_SPEU);
8225 return;
8226 }
8227 #if defined(TARGET_PPC64)
8228 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8229 #else
8230 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8231 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8232 #endif
8233 }
8234
8235 /* Conversion */
8236 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8237 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8238 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8239 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8240 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8241 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8242 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8243 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8244 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8245 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8246
8247 /* Comparison */
8248 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8249 GEN_SPEFPUOP_COMP_64(evfscmplt);
8250 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8251 GEN_SPEFPUOP_COMP_64(evfststgt);
8252 GEN_SPEFPUOP_COMP_64(evfststlt);
8253 GEN_SPEFPUOP_COMP_64(evfststeq);
8254
8255 /* Opcodes definitions */
8256 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8257 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8258 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8259 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8260 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8261 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8262 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8263 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8264 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8265 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8266 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8267 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8268 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8269 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8270
8271 /* Single precision floating-point operations */
8272 /* Arithmetic */
8273 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8274 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8275 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8276 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8277 static inline void gen_efsabs(DisasContext *ctx)
8278 {
8279 if (unlikely(!ctx->spe_enabled)) {
8280 gen_exception(ctx, POWERPC_EXCP_SPEU);
8281 return;
8282 }
8283 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8284 }
8285 static inline void gen_efsnabs(DisasContext *ctx)
8286 {
8287 if (unlikely(!ctx->spe_enabled)) {
8288 gen_exception(ctx, POWERPC_EXCP_SPEU);
8289 return;
8290 }
8291 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8292 }
8293 static inline void gen_efsneg(DisasContext *ctx)
8294 {
8295 if (unlikely(!ctx->spe_enabled)) {
8296 gen_exception(ctx, POWERPC_EXCP_SPEU);
8297 return;
8298 }
8299 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8300 }
8301
8302 /* Conversion */
8303 GEN_SPEFPUOP_CONV_32_32(efscfui);
8304 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8305 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8306 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8307 GEN_SPEFPUOP_CONV_32_32(efsctui);
8308 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8309 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8310 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8311 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8312 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8313 GEN_SPEFPUOP_CONV_32_64(efscfd);
8314
8315 /* Comparison */
8316 GEN_SPEFPUOP_COMP_32(efscmpgt);
8317 GEN_SPEFPUOP_COMP_32(efscmplt);
8318 GEN_SPEFPUOP_COMP_32(efscmpeq);
8319 GEN_SPEFPUOP_COMP_32(efststgt);
8320 GEN_SPEFPUOP_COMP_32(efststlt);
8321 GEN_SPEFPUOP_COMP_32(efststeq);
8322
8323 /* Opcodes definitions */
8324 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8325 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8326 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8327 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8328 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8329 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8330 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8331 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8332 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8333 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8334 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8335 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8336 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8337 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8338
8339 /* Double precision floating-point operations */
8340 /* Arithmetic */
8341 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8342 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8343 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8344 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8345 static inline void gen_efdabs(DisasContext *ctx)
8346 {
8347 if (unlikely(!ctx->spe_enabled)) {
8348 gen_exception(ctx, POWERPC_EXCP_SPEU);
8349 return;
8350 }
8351 #if defined(TARGET_PPC64)
8352 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8353 #else
8354 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8355 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8356 #endif
8357 }
8358 static inline void gen_efdnabs(DisasContext *ctx)
8359 {
8360 if (unlikely(!ctx->spe_enabled)) {
8361 gen_exception(ctx, POWERPC_EXCP_SPEU);
8362 return;
8363 }
8364 #if defined(TARGET_PPC64)
8365 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8366 #else
8367 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8368 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8369 #endif
8370 }
8371 static inline void gen_efdneg(DisasContext *ctx)
8372 {
8373 if (unlikely(!ctx->spe_enabled)) {
8374 gen_exception(ctx, POWERPC_EXCP_SPEU);
8375 return;
8376 }
8377 #if defined(TARGET_PPC64)
8378 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8379 #else
8380 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8381 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8382 #endif
8383 }
8384
8385 /* Conversion */
8386 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8387 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8388 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8389 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8390 GEN_SPEFPUOP_CONV_32_64(efdctui);
8391 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8392 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8393 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8394 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8395 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8396 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8397 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8398 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8399 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8400 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8401
8402 /* Comparison */
8403 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8404 GEN_SPEFPUOP_COMP_64(efdcmplt);
8405 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8406 GEN_SPEFPUOP_COMP_64(efdtstgt);
8407 GEN_SPEFPUOP_COMP_64(efdtstlt);
8408 GEN_SPEFPUOP_COMP_64(efdtsteq);
8409
8410 /* Opcodes definitions */
8411 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8412 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8413 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8414 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8415 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8416 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8417 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8418 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8419 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8420 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8421 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8422 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8423 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8424 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8425 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8426 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8427
8428 static opcode_t opcodes[] = {
8429 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8430 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8431 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8432 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8433 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8434 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8435 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8436 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8437 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8438 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8439 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8440 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8441 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8442 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8443 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8444 #if defined(TARGET_PPC64)
8445 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8446 #endif
8447 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8448 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8449 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8450 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8451 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8452 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8453 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8454 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8455 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8456 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8457 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8458 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8459 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8460 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8461 #if defined(TARGET_PPC64)
8462 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8463 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8464 #endif
8465 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8466 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8467 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8468 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8469 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8470 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8471 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8472 #if defined(TARGET_PPC64)
8473 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8474 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8475 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8476 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8477 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8478 #endif
8479 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8480 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8481 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8482 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8483 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8484 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8485 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8486 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8487 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8488 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8489 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8490 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8491 #if defined(TARGET_PPC64)
8492 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8493 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8494 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8495 #endif
8496 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8497 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8498 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8499 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8500 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8501 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8502 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8503 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8504 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8505 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8506 #if defined(TARGET_PPC64)
8507 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8508 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8509 #endif
8510 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8511 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8512 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8513 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8514 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8515 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8516 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8517 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8518 #if defined(TARGET_PPC64)
8519 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8520 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8521 #endif
8522 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8523 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8524 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8525 #if defined(TARGET_PPC64)
8526 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8527 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8528 #endif
8529 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8530 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8531 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8532 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8533 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8534 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8535 #if defined(TARGET_PPC64)
8536 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8537 #endif
8538 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8539 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8540 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8541 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8542 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8543 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8544 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8545 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8546 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8547 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8548 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8549 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8550 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8551 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8552 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8553 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8554 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8555 #if defined(TARGET_PPC64)
8556 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8557 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8558 PPC_SEGMENT_64B),
8559 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8560 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8561 PPC_SEGMENT_64B),
8562 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8563 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8564 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8565 #endif
8566 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8567 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8568 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8569 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8570 #if defined(TARGET_PPC64)
8571 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8572 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8573 #endif
8574 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8575 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8576 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8577 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8578 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8579 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8580 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8581 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8582 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8583 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8584 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8585 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8586 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8587 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8588 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8589 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8590 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8591 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8592 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8593 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8594 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8595 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8596 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8597 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8598 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8599 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8600 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8601 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8602 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8603 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8604 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8605 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8606 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8607 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8608 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8609 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8610 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8611 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8612 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8613 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8614 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8615 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8616 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8617 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8618 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8619 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8620 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8621 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8622 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8623 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8624 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8625 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8626 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8627 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8628 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8629 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8630 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8631 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8632 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8633 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8634 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8635 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8636 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8637 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8638 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8639 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8640 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8641 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8642 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8643 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8644 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8645 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8646 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8647 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8648 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8649 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8650 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8651 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8652 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8653 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8654 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8655 PPC_NONE, PPC2_BOOKE206),
8656 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8657 PPC_NONE, PPC2_BOOKE206),
8658 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8659 PPC_NONE, PPC2_BOOKE206),
8660 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8661 PPC_NONE, PPC2_BOOKE206),
8662 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8663 PPC_NONE, PPC2_BOOKE206),
8664 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8665 PPC_NONE, PPC2_PRCNTL),
8666 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8667 PPC_NONE, PPC2_PRCNTL),
8668 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8669 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8670 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8671 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8672 PPC_BOOKE, PPC2_BOOKE206),
8673 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8674 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8675 PPC_BOOKE, PPC2_BOOKE206),
8676 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8677 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8678 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8679 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8680 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8681 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8682 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8683 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8684 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8685 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8686
8687 #undef GEN_INT_ARITH_ADD
8688 #undef GEN_INT_ARITH_ADD_CONST
8689 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8690 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8691 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8692 add_ca, compute_ca, compute_ov) \
8693 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8694 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8695 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8696 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8697 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8698 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8699 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8700 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8701 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8702 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8703 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8704
8705 #undef GEN_INT_ARITH_DIVW
8706 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8707 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8708 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8709 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8710 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8711 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8712
8713 #if defined(TARGET_PPC64)
8714 #undef GEN_INT_ARITH_DIVD
8715 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8716 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8717 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8718 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8719 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8720 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8721
8722 #undef GEN_INT_ARITH_MUL_HELPER
8723 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8724 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8725 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8726 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8727 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8728 #endif
8729
8730 #undef GEN_INT_ARITH_SUBF
8731 #undef GEN_INT_ARITH_SUBF_CONST
8732 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8733 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8734 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8735 add_ca, compute_ca, compute_ov) \
8736 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8737 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8738 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8739 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8740 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8741 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8742 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8743 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8744 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8745 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8746 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8747
8748 #undef GEN_LOGICAL1
8749 #undef GEN_LOGICAL2
8750 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8751 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8752 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8753 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8754 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8755 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8756 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8757 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8758 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8759 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8760 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8761 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8762 #if defined(TARGET_PPC64)
8763 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8764 #endif
8765
8766 #if defined(TARGET_PPC64)
8767 #undef GEN_PPC64_R2
8768 #undef GEN_PPC64_R4
8769 #define GEN_PPC64_R2(name, opc1, opc2) \
8770 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8771 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8772 PPC_64B)
8773 #define GEN_PPC64_R4(name, opc1, opc2) \
8774 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8775 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8776 PPC_64B), \
8777 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8778 PPC_64B), \
8779 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8780 PPC_64B)
8781 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8782 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8783 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8784 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8785 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8786 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8787 #endif
8788
8789 #undef _GEN_FLOAT_ACB
8790 #undef GEN_FLOAT_ACB
8791 #undef _GEN_FLOAT_AB
8792 #undef GEN_FLOAT_AB
8793 #undef _GEN_FLOAT_AC
8794 #undef GEN_FLOAT_AC
8795 #undef GEN_FLOAT_B
8796 #undef GEN_FLOAT_BS
8797 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8798 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8799 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8800 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8801 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8802 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8803 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8804 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8805 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8806 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8807 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8808 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8809 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8810 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8811 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8812 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8813 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8814 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8815 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8816
8817 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8818 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8819 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8820 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8821 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8822 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8823 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8824 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8825 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8826 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8827 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8828 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8829 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8830 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8831 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8832 #if defined(TARGET_PPC64)
8833 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8834 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8835 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8836 #endif
8837 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8838 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8839 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8840 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8841 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8842 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8843 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8844
8845 #undef GEN_LD
8846 #undef GEN_LDU
8847 #undef GEN_LDUX
8848 #undef GEN_LDX_E
8849 #undef GEN_LDS
8850 #define GEN_LD(name, ldop, opc, type) \
8851 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8852 #define GEN_LDU(name, ldop, opc, type) \
8853 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8854 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8855 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8856 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8857 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8858 #define GEN_LDS(name, ldop, op, type) \
8859 GEN_LD(name, ldop, op | 0x20, type) \
8860 GEN_LDU(name, ldop, op | 0x21, type) \
8861 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8862 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8863
8864 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8865 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8866 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8867 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8868 #if defined(TARGET_PPC64)
8869 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8870 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8871 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8872 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8873 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8874 #endif
8875 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8876 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8877
8878 #undef GEN_ST
8879 #undef GEN_STU
8880 #undef GEN_STUX
8881 #undef GEN_STX_E
8882 #undef GEN_STS
8883 #define GEN_ST(name, stop, opc, type) \
8884 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8885 #define GEN_STU(name, stop, opc, type) \
8886 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8887 #define GEN_STUX(name, stop, opc2, opc3, type) \
8888 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8889 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8890 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8891 #define GEN_STS(name, stop, op, type) \
8892 GEN_ST(name, stop, op | 0x20, type) \
8893 GEN_STU(name, stop, op | 0x21, type) \
8894 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8895 GEN_STX(name, stop, 0x17, op | 0x00, type)
8896
8897 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8898 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8899 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8900 #if defined(TARGET_PPC64)
8901 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8902 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8903 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8904 #endif
8905 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8906 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8907
8908 #undef GEN_LDF
8909 #undef GEN_LDUF
8910 #undef GEN_LDUXF
8911 #undef GEN_LDXF
8912 #undef GEN_LDFS
8913 #define GEN_LDF(name, ldop, opc, type) \
8914 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8915 #define GEN_LDUF(name, ldop, opc, type) \
8916 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8917 #define GEN_LDUXF(name, ldop, opc, type) \
8918 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8919 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8920 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8921 #define GEN_LDFS(name, ldop, op, type) \
8922 GEN_LDF(name, ldop, op | 0x20, type) \
8923 GEN_LDUF(name, ldop, op | 0x21, type) \
8924 GEN_LDUXF(name, ldop, op | 0x01, type) \
8925 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8926
8927 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8928 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8929
8930 #undef GEN_STF
8931 #undef GEN_STUF
8932 #undef GEN_STUXF
8933 #undef GEN_STXF
8934 #undef GEN_STFS
8935 #define GEN_STF(name, stop, opc, type) \
8936 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8937 #define GEN_STUF(name, stop, opc, type) \
8938 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8939 #define GEN_STUXF(name, stop, opc, type) \
8940 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8941 #define GEN_STXF(name, stop, opc2, opc3, type) \
8942 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8943 #define GEN_STFS(name, stop, op, type) \
8944 GEN_STF(name, stop, op | 0x20, type) \
8945 GEN_STUF(name, stop, op | 0x21, type) \
8946 GEN_STUXF(name, stop, op | 0x01, type) \
8947 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8948
8949 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8950 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8951 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8952
8953 #undef GEN_CRLOGIC
8954 #define GEN_CRLOGIC(name, tcg_op, opc) \
8955 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8956 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8957 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8958 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8959 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8960 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8961 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8962 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8963 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8964
8965 #undef GEN_MAC_HANDLER
8966 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8967 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8968 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8969 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8970 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8971 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8972 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8973 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8974 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8975 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8976 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8977 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8978 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8979 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8980 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8981 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8982 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8983 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8984 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8985 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8986 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8987 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8988 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8989 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8990 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8991 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8992 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8993 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8994 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8995 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8996 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8997 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8998 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8999 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9000 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9001 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9002 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9003 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9004 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9005 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9006 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9007 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9008 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9009 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9010
9011 #undef GEN_VR_LDX
9012 #undef GEN_VR_STX
9013 #undef GEN_VR_LVE
9014 #undef GEN_VR_STVE
9015 #define GEN_VR_LDX(name, opc2, opc3) \
9016 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9017 #define GEN_VR_STX(name, opc2, opc3) \
9018 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9019 #define GEN_VR_LVE(name, opc2, opc3) \
9020 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9021 #define GEN_VR_STVE(name, opc2, opc3) \
9022 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9023 GEN_VR_LDX(lvx, 0x07, 0x03),
9024 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9025 GEN_VR_LVE(bx, 0x07, 0x00),
9026 GEN_VR_LVE(hx, 0x07, 0x01),
9027 GEN_VR_LVE(wx, 0x07, 0x02),
9028 GEN_VR_STX(svx, 0x07, 0x07),
9029 GEN_VR_STX(svxl, 0x07, 0x0F),
9030 GEN_VR_STVE(bx, 0x07, 0x04),
9031 GEN_VR_STVE(hx, 0x07, 0x05),
9032 GEN_VR_STVE(wx, 0x07, 0x06),
9033
9034 #undef GEN_VX_LOGICAL
9035 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9036 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9037 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9038 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9039 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9040 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9041 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9042
9043 #undef GEN_VXFORM
9044 #define GEN_VXFORM(name, opc2, opc3) \
9045 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9046 GEN_VXFORM(vaddubm, 0, 0),
9047 GEN_VXFORM(vadduhm, 0, 1),
9048 GEN_VXFORM(vadduwm, 0, 2),
9049 GEN_VXFORM(vsububm, 0, 16),
9050 GEN_VXFORM(vsubuhm, 0, 17),
9051 GEN_VXFORM(vsubuwm, 0, 18),
9052 GEN_VXFORM(vmaxub, 1, 0),
9053 GEN_VXFORM(vmaxuh, 1, 1),
9054 GEN_VXFORM(vmaxuw, 1, 2),
9055 GEN_VXFORM(vmaxsb, 1, 4),
9056 GEN_VXFORM(vmaxsh, 1, 5),
9057 GEN_VXFORM(vmaxsw, 1, 6),
9058 GEN_VXFORM(vminub, 1, 8),
9059 GEN_VXFORM(vminuh, 1, 9),
9060 GEN_VXFORM(vminuw, 1, 10),
9061 GEN_VXFORM(vminsb, 1, 12),
9062 GEN_VXFORM(vminsh, 1, 13),
9063 GEN_VXFORM(vminsw, 1, 14),
9064 GEN_VXFORM(vavgub, 1, 16),
9065 GEN_VXFORM(vavguh, 1, 17),
9066 GEN_VXFORM(vavguw, 1, 18),
9067 GEN_VXFORM(vavgsb, 1, 20),
9068 GEN_VXFORM(vavgsh, 1, 21),
9069 GEN_VXFORM(vavgsw, 1, 22),
9070 GEN_VXFORM(vmrghb, 6, 0),
9071 GEN_VXFORM(vmrghh, 6, 1),
9072 GEN_VXFORM(vmrghw, 6, 2),
9073 GEN_VXFORM(vmrglb, 6, 4),
9074 GEN_VXFORM(vmrglh, 6, 5),
9075 GEN_VXFORM(vmrglw, 6, 6),
9076 GEN_VXFORM(vmuloub, 4, 0),
9077 GEN_VXFORM(vmulouh, 4, 1),
9078 GEN_VXFORM(vmulosb, 4, 4),
9079 GEN_VXFORM(vmulosh, 4, 5),
9080 GEN_VXFORM(vmuleub, 4, 8),
9081 GEN_VXFORM(vmuleuh, 4, 9),
9082 GEN_VXFORM(vmulesb, 4, 12),
9083 GEN_VXFORM(vmulesh, 4, 13),
9084 GEN_VXFORM(vslb, 2, 4),
9085 GEN_VXFORM(vslh, 2, 5),
9086 GEN_VXFORM(vslw, 2, 6),
9087 GEN_VXFORM(vsrb, 2, 8),
9088 GEN_VXFORM(vsrh, 2, 9),
9089 GEN_VXFORM(vsrw, 2, 10),
9090 GEN_VXFORM(vsrab, 2, 12),
9091 GEN_VXFORM(vsrah, 2, 13),
9092 GEN_VXFORM(vsraw, 2, 14),
9093 GEN_VXFORM(vslo, 6, 16),
9094 GEN_VXFORM(vsro, 6, 17),
9095 GEN_VXFORM(vaddcuw, 0, 6),
9096 GEN_VXFORM(vsubcuw, 0, 22),
9097 GEN_VXFORM(vaddubs, 0, 8),
9098 GEN_VXFORM(vadduhs, 0, 9),
9099 GEN_VXFORM(vadduws, 0, 10),
9100 GEN_VXFORM(vaddsbs, 0, 12),
9101 GEN_VXFORM(vaddshs, 0, 13),
9102 GEN_VXFORM(vaddsws, 0, 14),
9103 GEN_VXFORM(vsububs, 0, 24),
9104 GEN_VXFORM(vsubuhs, 0, 25),
9105 GEN_VXFORM(vsubuws, 0, 26),
9106 GEN_VXFORM(vsubsbs, 0, 28),
9107 GEN_VXFORM(vsubshs, 0, 29),
9108 GEN_VXFORM(vsubsws, 0, 30),
9109 GEN_VXFORM(vrlb, 2, 0),
9110 GEN_VXFORM(vrlh, 2, 1),
9111 GEN_VXFORM(vrlw, 2, 2),
9112 GEN_VXFORM(vsl, 2, 7),
9113 GEN_VXFORM(vsr, 2, 11),
9114 GEN_VXFORM(vpkuhum, 7, 0),
9115 GEN_VXFORM(vpkuwum, 7, 1),
9116 GEN_VXFORM(vpkuhus, 7, 2),
9117 GEN_VXFORM(vpkuwus, 7, 3),
9118 GEN_VXFORM(vpkshus, 7, 4),
9119 GEN_VXFORM(vpkswus, 7, 5),
9120 GEN_VXFORM(vpkshss, 7, 6),
9121 GEN_VXFORM(vpkswss, 7, 7),
9122 GEN_VXFORM(vpkpx, 7, 12),
9123 GEN_VXFORM(vsum4ubs, 4, 24),
9124 GEN_VXFORM(vsum4sbs, 4, 28),
9125 GEN_VXFORM(vsum4shs, 4, 25),
9126 GEN_VXFORM(vsum2sws, 4, 26),
9127 GEN_VXFORM(vsumsws, 4, 30),
9128 GEN_VXFORM(vaddfp, 5, 0),
9129 GEN_VXFORM(vsubfp, 5, 1),
9130 GEN_VXFORM(vmaxfp, 5, 16),
9131 GEN_VXFORM(vminfp, 5, 17),
9132
9133 #undef GEN_VXRFORM1
9134 #undef GEN_VXRFORM
9135 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9136 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9137 #define GEN_VXRFORM(name, opc2, opc3) \
9138 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9139 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9140 GEN_VXRFORM(vcmpequb, 3, 0)
9141 GEN_VXRFORM(vcmpequh, 3, 1)
9142 GEN_VXRFORM(vcmpequw, 3, 2)
9143 GEN_VXRFORM(vcmpgtsb, 3, 12)
9144 GEN_VXRFORM(vcmpgtsh, 3, 13)
9145 GEN_VXRFORM(vcmpgtsw, 3, 14)
9146 GEN_VXRFORM(vcmpgtub, 3, 8)
9147 GEN_VXRFORM(vcmpgtuh, 3, 9)
9148 GEN_VXRFORM(vcmpgtuw, 3, 10)
9149 GEN_VXRFORM(vcmpeqfp, 3, 3)
9150 GEN_VXRFORM(vcmpgefp, 3, 7)
9151 GEN_VXRFORM(vcmpgtfp, 3, 11)
9152 GEN_VXRFORM(vcmpbfp, 3, 15)
9153
9154 #undef GEN_VXFORM_SIMM
9155 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9156 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9157 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9158 GEN_VXFORM_SIMM(vspltish, 6, 13),
9159 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9160
9161 #undef GEN_VXFORM_NOA
9162 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9163 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9164 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9165 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9166 GEN_VXFORM_NOA(vupklsb, 7, 10),
9167 GEN_VXFORM_NOA(vupklsh, 7, 11),
9168 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9169 GEN_VXFORM_NOA(vupklpx, 7, 15),
9170 GEN_VXFORM_NOA(vrefp, 5, 4),
9171 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9172 GEN_VXFORM_NOA(vexptefp, 5, 6),
9173 GEN_VXFORM_NOA(vlogefp, 5, 7),
9174 GEN_VXFORM_NOA(vrfim, 5, 8),
9175 GEN_VXFORM_NOA(vrfin, 5, 9),
9176 GEN_VXFORM_NOA(vrfip, 5, 10),
9177 GEN_VXFORM_NOA(vrfiz, 5, 11),
9178
9179 #undef GEN_VXFORM_UIMM
9180 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9181 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9182 GEN_VXFORM_UIMM(vspltb, 6, 8),
9183 GEN_VXFORM_UIMM(vsplth, 6, 9),
9184 GEN_VXFORM_UIMM(vspltw, 6, 10),
9185 GEN_VXFORM_UIMM(vcfux, 5, 12),
9186 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9187 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9188 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9189
9190 #undef GEN_VAFORM_PAIRED
9191 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9192 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9193 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9194 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9195 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9196 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9197 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9198 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9199
9200 #undef GEN_SPE
9201 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9202 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9203 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9204 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9205 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9206 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9207 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9208 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9209 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9210 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9211 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9212 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9213 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9214 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9215 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9216 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9217 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9218 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9219 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9220 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9221 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9222 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9223 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9224 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9225 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9226 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9227 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9228 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9229 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9230 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9231 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9232
9233 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9234 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9235 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9236 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9237 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9238 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9239 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9240 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9241 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9242 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9243 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9244 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9245 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9246 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9247
9248 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9249 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9250 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9251 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9252 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9253 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9254 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9255 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9256 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9257 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9258 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9259 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9260 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9261 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9262
9263 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9264 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9265 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9266 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9267 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9268 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9269 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9270 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9271 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9272 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9273 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9274 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9275 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9276 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9277 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9278 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9279
9280 #undef GEN_SPEOP_LDST
9281 #define GEN_SPEOP_LDST(name, opc2, sh) \
9282 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9283 GEN_SPEOP_LDST(evldd, 0x00, 3),
9284 GEN_SPEOP_LDST(evldw, 0x01, 3),
9285 GEN_SPEOP_LDST(evldh, 0x02, 3),
9286 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9287 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9288 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9289 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9290 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9291 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9292 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9293 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9294
9295 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9296 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9297 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9298 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9299 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9300 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9301 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9302 };
9303
9304 #include "helper_regs.h"
9305 #include "translate_init.c"
9306
9307 /*****************************************************************************/
9308 /* Misc PowerPC helpers */
9309 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9310 int flags)
9311 {
9312 #define RGPL 4
9313 #define RFPL 4
9314
9315 int i;
9316
9317 cpu_synchronize_state(env);
9318
9319 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9320 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9321 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9322 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9323 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9324 env->hflags, env->mmu_idx);
9325 #if !defined(NO_TIMER_DUMP)
9326 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9327 #if !defined(CONFIG_USER_ONLY)
9328 " DECR %08" PRIu32
9329 #endif
9330 "\n",
9331 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9332 #if !defined(CONFIG_USER_ONLY)
9333 , cpu_ppc_load_decr(env)
9334 #endif
9335 );
9336 #endif
9337 for (i = 0; i < 32; i++) {
9338 if ((i & (RGPL - 1)) == 0)
9339 cpu_fprintf(f, "GPR%02d", i);
9340 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9341 if ((i & (RGPL - 1)) == (RGPL - 1))
9342 cpu_fprintf(f, "\n");
9343 }
9344 cpu_fprintf(f, "CR ");
9345 for (i = 0; i < 8; i++)
9346 cpu_fprintf(f, "%01x", env->crf[i]);
9347 cpu_fprintf(f, " [");
9348 for (i = 0; i < 8; i++) {
9349 char a = '-';
9350 if (env->crf[i] & 0x08)
9351 a = 'L';
9352 else if (env->crf[i] & 0x04)
9353 a = 'G';
9354 else if (env->crf[i] & 0x02)
9355 a = 'E';
9356 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9357 }
9358 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9359 env->reserve_addr);
9360 for (i = 0; i < 32; i++) {
9361 if ((i & (RFPL - 1)) == 0)
9362 cpu_fprintf(f, "FPR%02d", i);
9363 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9364 if ((i & (RFPL - 1)) == (RFPL - 1))
9365 cpu_fprintf(f, "\n");
9366 }
9367 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9368 #if !defined(CONFIG_USER_ONLY)
9369 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9370 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9371 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9372 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9373
9374 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9375 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9376 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9377 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9378
9379 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9380 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9381 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9382 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9383
9384 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9385 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9386 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9387 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9388 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9389
9390 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9391 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9392 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9393 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9394
9395 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9396 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9397 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9398 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9399
9400 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9401 " EPR " TARGET_FMT_lx "\n",
9402 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9403 env->spr[SPR_BOOKE_EPR]);
9404
9405 /* FSL-specific */
9406 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9407 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9408 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9409 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9410
9411 /*
9412 * IVORs are left out as they are large and do not change often --
9413 * they can be read with "p $ivor0", "p $ivor1", etc.
9414 */
9415 }
9416
9417 #if defined(TARGET_PPC64)
9418 if (env->flags & POWERPC_FLAG_CFAR) {
9419 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9420 }
9421 #endif
9422
9423 switch (env->mmu_model) {
9424 case POWERPC_MMU_32B:
9425 case POWERPC_MMU_601:
9426 case POWERPC_MMU_SOFT_6xx:
9427 case POWERPC_MMU_SOFT_74xx:
9428 #if defined(TARGET_PPC64)
9429 case POWERPC_MMU_620:
9430 case POWERPC_MMU_64B:
9431 #endif
9432 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9433 break;
9434 case POWERPC_MMU_BOOKE206:
9435 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9436 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9437 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9438 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9439
9440 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9441 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9442 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9443 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9444
9445 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9446 " TLB1CFG " TARGET_FMT_lx "\n",
9447 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9448 env->spr[SPR_BOOKE_TLB1CFG]);
9449 break;
9450 default:
9451 break;
9452 }
9453 #endif
9454
9455 #undef RGPL
9456 #undef RFPL
9457 }
9458
9459 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9460 int flags)
9461 {
9462 #if defined(DO_PPC_STATISTICS)
9463 opc_handler_t **t1, **t2, **t3, *handler;
9464 int op1, op2, op3;
9465
9466 t1 = env->opcodes;
9467 for (op1 = 0; op1 < 64; op1++) {
9468 handler = t1[op1];
9469 if (is_indirect_opcode(handler)) {
9470 t2 = ind_table(handler);
9471 for (op2 = 0; op2 < 32; op2++) {
9472 handler = t2[op2];
9473 if (is_indirect_opcode(handler)) {
9474 t3 = ind_table(handler);
9475 for (op3 = 0; op3 < 32; op3++) {
9476 handler = t3[op3];
9477 if (handler->count == 0)
9478 continue;
9479 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9480 "%016" PRIx64 " %" PRId64 "\n",
9481 op1, op2, op3, op1, (op3 << 5) | op2,
9482 handler->oname,
9483 handler->count, handler->count);
9484 }
9485 } else {
9486 if (handler->count == 0)
9487 continue;
9488 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9489 "%016" PRIx64 " %" PRId64 "\n",
9490 op1, op2, op1, op2, handler->oname,
9491 handler->count, handler->count);
9492 }
9493 }
9494 } else {
9495 if (handler->count == 0)
9496 continue;
9497 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9498 " %" PRId64 "\n",
9499 op1, op1, handler->oname,
9500 handler->count, handler->count);
9501 }
9502 }
9503 #endif
9504 }
9505
9506 /*****************************************************************************/
9507 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9508 TranslationBlock *tb,
9509 int search_pc)
9510 {
9511 DisasContext ctx, *ctxp = &ctx;
9512 opc_handler_t **table, *handler;
9513 target_ulong pc_start;
9514 uint16_t *gen_opc_end;
9515 CPUBreakpoint *bp;
9516 int j, lj = -1;
9517 int num_insns;
9518 int max_insns;
9519
9520 pc_start = tb->pc;
9521 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9522 ctx.nip = pc_start;
9523 ctx.tb = tb;
9524 ctx.exception = POWERPC_EXCP_NONE;
9525 ctx.spr_cb = env->spr_cb;
9526 ctx.mem_idx = env->mmu_idx;
9527 ctx.access_type = -1;
9528 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9529 #if defined(TARGET_PPC64)
9530 ctx.sf_mode = msr_is_64bit(env, env->msr);
9531 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9532 #endif
9533 ctx.fpu_enabled = msr_fp;
9534 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9535 ctx.spe_enabled = msr_spe;
9536 else
9537 ctx.spe_enabled = 0;
9538 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9539 ctx.altivec_enabled = msr_vr;
9540 else
9541 ctx.altivec_enabled = 0;
9542 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9543 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9544 else
9545 ctx.singlestep_enabled = 0;
9546 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9547 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9548 if (unlikely(env->singlestep_enabled))
9549 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9550 #if defined (DO_SINGLE_STEP) && 0
9551 /* Single step trace mode */
9552 msr_se = 1;
9553 #endif
9554 num_insns = 0;
9555 max_insns = tb->cflags & CF_COUNT_MASK;
9556 if (max_insns == 0)
9557 max_insns = CF_COUNT_MASK;
9558
9559 gen_icount_start();
9560 /* Set env in case of segfault during code fetch */
9561 while (ctx.exception == POWERPC_EXCP_NONE
9562 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9563 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9564 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9565 if (bp->pc == ctx.nip) {
9566 gen_debug_exception(ctxp);
9567 break;
9568 }
9569 }
9570 }
9571 if (unlikely(search_pc)) {
9572 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9573 if (lj < j) {
9574 lj++;
9575 while (lj < j)
9576 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9577 }
9578 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9579 tcg_ctx.gen_opc_instr_start[lj] = 1;
9580 tcg_ctx.gen_opc_icount[lj] = num_insns;
9581 }
9582 LOG_DISAS("----------------\n");
9583 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9584 ctx.nip, ctx.mem_idx, (int)msr_ir);
9585 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9586 gen_io_start();
9587 if (unlikely(ctx.le_mode)) {
9588 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9589 } else {
9590 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9591 }
9592 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9593 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9594 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9595 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9596 tcg_gen_debug_insn_start(ctx.nip);
9597 }
9598 ctx.nip += 4;
9599 table = env->opcodes;
9600 num_insns++;
9601 handler = table[opc1(ctx.opcode)];
9602 if (is_indirect_opcode(handler)) {
9603 table = ind_table(handler);
9604 handler = table[opc2(ctx.opcode)];
9605 if (is_indirect_opcode(handler)) {
9606 table = ind_table(handler);
9607 handler = table[opc3(ctx.opcode)];
9608 }
9609 }
9610 /* Is opcode *REALLY* valid ? */
9611 if (unlikely(handler->handler == &gen_invalid)) {
9612 if (qemu_log_enabled()) {
9613 qemu_log("invalid/unsupported opcode: "
9614 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9615 opc1(ctx.opcode), opc2(ctx.opcode),
9616 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9617 }
9618 } else {
9619 uint32_t inval;
9620
9621 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9622 inval = handler->inval2;
9623 } else {
9624 inval = handler->inval1;
9625 }
9626
9627 if (unlikely((ctx.opcode & inval) != 0)) {
9628 if (qemu_log_enabled()) {
9629 qemu_log("invalid bits: %08x for opcode: "
9630 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9631 ctx.opcode & inval, opc1(ctx.opcode),
9632 opc2(ctx.opcode), opc3(ctx.opcode),
9633 ctx.opcode, ctx.nip - 4);
9634 }
9635 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9636 break;
9637 }
9638 }
9639 (*(handler->handler))(&ctx);
9640 #if defined(DO_PPC_STATISTICS)
9641 handler->count++;
9642 #endif
9643 /* Check trace mode exceptions */
9644 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9645 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9646 ctx.exception != POWERPC_SYSCALL &&
9647 ctx.exception != POWERPC_EXCP_TRAP &&
9648 ctx.exception != POWERPC_EXCP_BRANCH)) {
9649 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9650 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9651 (env->singlestep_enabled) ||
9652 singlestep ||
9653 num_insns >= max_insns)) {
9654 /* if we reach a page boundary or are single stepping, stop
9655 * generation
9656 */
9657 break;
9658 }
9659 }
9660 if (tb->cflags & CF_LAST_IO)
9661 gen_io_end();
9662 if (ctx.exception == POWERPC_EXCP_NONE) {
9663 gen_goto_tb(&ctx, 0, ctx.nip);
9664 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9665 if (unlikely(env->singlestep_enabled)) {
9666 gen_debug_exception(ctxp);
9667 }
9668 /* Generate the return instruction */
9669 tcg_gen_exit_tb(0);
9670 }
9671 gen_icount_end(tb, num_insns);
9672 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9673 if (unlikely(search_pc)) {
9674 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9675 lj++;
9676 while (lj <= j)
9677 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9678 } else {
9679 tb->size = ctx.nip - pc_start;
9680 tb->icount = num_insns;
9681 }
9682 #if defined(DEBUG_DISAS)
9683 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9684 int flags;
9685 flags = env->bfd_mach;
9686 flags |= ctx.le_mode << 16;
9687 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9688 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9689 qemu_log("\n");
9690 }
9691 #endif
9692 }
9693
9694 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9695 {
9696 gen_intermediate_code_internal(env, tb, 0);
9697 }
9698
9699 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9700 {
9701 gen_intermediate_code_internal(env, tb, 1);
9702 }
9703
9704 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9705 {
9706 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9707 }
Qemu copy for testing