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target-ppc: emulate fcpsgn instruction
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 /* True when active word size < size of target_long. */
208 #ifdef TARGET_PPC64
209 # define NARROW_MODE(C) (!(C)->sf_mode)
210 #else
211 # define NARROW_MODE(C) 0
212 #endif
213
214 struct opc_handler_t {
215 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
216 uint32_t inval1;
217 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
218 uint32_t inval2;
219 /* instruction type */
220 uint64_t type;
221 /* extended instruction type */
222 uint64_t type2;
223 /* handler */
224 void (*handler)(DisasContext *ctx);
225 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
226 const char *oname;
227 #endif
228 #if defined(DO_PPC_STATISTICS)
229 uint64_t count;
230 #endif
231 };
232
233 static inline void gen_reset_fpstatus(void)
234 {
235 gen_helper_reset_fpstatus(cpu_env);
236 }
237
238 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
239 {
240 TCGv_i32 t0 = tcg_temp_new_i32();
241
242 if (set_fprf != 0) {
243 /* This case might be optimized later */
244 tcg_gen_movi_i32(t0, 1);
245 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
246 if (unlikely(set_rc)) {
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249 gen_helper_float_check_status(cpu_env);
250 } else if (unlikely(set_rc)) {
251 /* We always need to compute fpcc */
252 tcg_gen_movi_i32(t0, 0);
253 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
254 tcg_gen_mov_i32(cpu_crf[1], t0);
255 }
256
257 tcg_temp_free_i32(t0);
258 }
259
260 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
261 {
262 if (ctx->access_type != access_type) {
263 tcg_gen_movi_i32(cpu_access_type, access_type);
264 ctx->access_type = access_type;
265 }
266 }
267
268 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
269 {
270 if (NARROW_MODE(ctx)) {
271 nip = (uint32_t)nip;
272 }
273 tcg_gen_movi_tl(cpu_nip, nip);
274 }
275
276 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
277 {
278 TCGv_i32 t0, t1;
279 if (ctx->exception == POWERPC_EXCP_NONE) {
280 gen_update_nip(ctx, ctx->nip);
281 }
282 t0 = tcg_const_i32(excp);
283 t1 = tcg_const_i32(error);
284 gen_helper_raise_exception_err(cpu_env, t0, t1);
285 tcg_temp_free_i32(t0);
286 tcg_temp_free_i32(t1);
287 ctx->exception = (excp);
288 }
289
290 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
291 {
292 TCGv_i32 t0;
293 if (ctx->exception == POWERPC_EXCP_NONE) {
294 gen_update_nip(ctx, ctx->nip);
295 }
296 t0 = tcg_const_i32(excp);
297 gen_helper_raise_exception(cpu_env, t0);
298 tcg_temp_free_i32(t0);
299 ctx->exception = (excp);
300 }
301
302 static inline void gen_debug_exception(DisasContext *ctx)
303 {
304 TCGv_i32 t0;
305
306 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
307 (ctx->exception != POWERPC_EXCP_SYNC)) {
308 gen_update_nip(ctx, ctx->nip);
309 }
310 t0 = tcg_const_i32(EXCP_DEBUG);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 }
314
315 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
316 {
317 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
318 }
319
320 /* Stop translation */
321 static inline void gen_stop_exception(DisasContext *ctx)
322 {
323 gen_update_nip(ctx, ctx->nip);
324 ctx->exception = POWERPC_EXCP_STOP;
325 }
326
327 /* No need to update nip here, as execution flow will change */
328 static inline void gen_sync_exception(DisasContext *ctx)
329 {
330 ctx->exception = POWERPC_EXCP_SYNC;
331 }
332
333 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
334 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
335
336 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
337 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
338
339 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
344
345 typedef struct opcode_t {
346 unsigned char opc1, opc2, opc3;
347 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
348 unsigned char pad[5];
349 #else
350 unsigned char pad[1];
351 #endif
352 opc_handler_t handler;
353 const char *oname;
354 } opcode_t;
355
356 /*****************************************************************************/
357 /*** Instruction decoding ***/
358 #define EXTRACT_HELPER(name, shift, nb) \
359 static inline uint32_t name(uint32_t opcode) \
360 { \
361 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
362 }
363
364 #define EXTRACT_SHELPER(name, shift, nb) \
365 static inline int32_t name(uint32_t opcode) \
366 { \
367 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
368 }
369
370 /* Opcode part 1 */
371 EXTRACT_HELPER(opc1, 26, 6);
372 /* Opcode part 2 */
373 EXTRACT_HELPER(opc2, 1, 5);
374 /* Opcode part 3 */
375 EXTRACT_HELPER(opc3, 6, 5);
376 /* Update Cr0 flags */
377 EXTRACT_HELPER(Rc, 0, 1);
378 /* Destination */
379 EXTRACT_HELPER(rD, 21, 5);
380 /* Source */
381 EXTRACT_HELPER(rS, 21, 5);
382 /* First operand */
383 EXTRACT_HELPER(rA, 16, 5);
384 /* Second operand */
385 EXTRACT_HELPER(rB, 11, 5);
386 /* Third operand */
387 EXTRACT_HELPER(rC, 6, 5);
388 /*** Get CRn ***/
389 EXTRACT_HELPER(crfD, 23, 3);
390 EXTRACT_HELPER(crfS, 18, 3);
391 EXTRACT_HELPER(crbD, 21, 5);
392 EXTRACT_HELPER(crbA, 16, 5);
393 EXTRACT_HELPER(crbB, 11, 5);
394 /* SPR / TBL */
395 EXTRACT_HELPER(_SPR, 11, 10);
396 static inline uint32_t SPR(uint32_t opcode)
397 {
398 uint32_t sprn = _SPR(opcode);
399
400 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
401 }
402 /*** Get constants ***/
403 EXTRACT_HELPER(IMM, 12, 8);
404 /* 16 bits signed immediate value */
405 EXTRACT_SHELPER(SIMM, 0, 16);
406 /* 16 bits unsigned immediate value */
407 EXTRACT_HELPER(UIMM, 0, 16);
408 /* 5 bits signed immediate value */
409 EXTRACT_HELPER(SIMM5, 16, 5);
410 /* 5 bits signed immediate value */
411 EXTRACT_HELPER(UIMM5, 16, 5);
412 /* Bit count */
413 EXTRACT_HELPER(NB, 11, 5);
414 /* Shift count */
415 EXTRACT_HELPER(SH, 11, 5);
416 /* Vector shift count */
417 EXTRACT_HELPER(VSH, 6, 4);
418 /* Mask start */
419 EXTRACT_HELPER(MB, 6, 5);
420 /* Mask end */
421 EXTRACT_HELPER(ME, 1, 5);
422 /* Trap operand */
423 EXTRACT_HELPER(TO, 21, 5);
424
425 EXTRACT_HELPER(CRM, 12, 8);
426 EXTRACT_HELPER(FM, 17, 8);
427 EXTRACT_HELPER(SR, 16, 4);
428 EXTRACT_HELPER(FPIMM, 12, 4);
429
430 /*** Jump target decoding ***/
431 /* Displacement */
432 EXTRACT_SHELPER(d, 0, 16);
433 /* Immediate address */
434 static inline target_ulong LI(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0x03FFFFFC;
437 }
438
439 static inline uint32_t BD(uint32_t opcode)
440 {
441 return (opcode >> 0) & 0xFFFC;
442 }
443
444 EXTRACT_HELPER(BO, 21, 5);
445 EXTRACT_HELPER(BI, 16, 5);
446 /* Absolute/relative address */
447 EXTRACT_HELPER(AA, 1, 1);
448 /* Link */
449 EXTRACT_HELPER(LK, 0, 1);
450
451 /* Create a mask between <start> and <end> bits */
452 static inline target_ulong MASK(uint32_t start, uint32_t end)
453 {
454 target_ulong ret;
455
456 #if defined(TARGET_PPC64)
457 if (likely(start == 0)) {
458 ret = UINT64_MAX << (63 - end);
459 } else if (likely(end == 63)) {
460 ret = UINT64_MAX >> start;
461 }
462 #else
463 if (likely(start == 0)) {
464 ret = UINT32_MAX << (31 - end);
465 } else if (likely(end == 31)) {
466 ret = UINT32_MAX >> start;
467 }
468 #endif
469 else {
470 ret = (((target_ulong)(-1ULL)) >> (start)) ^
471 (((target_ulong)(-1ULL) >> (end)) >> 1);
472 if (unlikely(start > end))
473 return ~ret;
474 }
475
476 return ret;
477 }
478
479 /*****************************************************************************/
480 /* PowerPC instructions table */
481
482 #if defined(DO_PPC_STATISTICS)
483 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
484 { \
485 .opc1 = op1, \
486 .opc2 = op2, \
487 .opc3 = op3, \
488 .pad = { 0, }, \
489 .handler = { \
490 .inval1 = invl, \
491 .type = _typ, \
492 .type2 = _typ2, \
493 .handler = &gen_##name, \
494 .oname = stringify(name), \
495 }, \
496 .oname = stringify(name), \
497 }
498 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
499 { \
500 .opc1 = op1, \
501 .opc2 = op2, \
502 .opc3 = op3, \
503 .pad = { 0, }, \
504 .handler = { \
505 .inval1 = invl1, \
506 .inval2 = invl2, \
507 .type = _typ, \
508 .type2 = _typ2, \
509 .handler = &gen_##name, \
510 .oname = stringify(name), \
511 }, \
512 .oname = stringify(name), \
513 }
514 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
515 { \
516 .opc1 = op1, \
517 .opc2 = op2, \
518 .opc3 = op3, \
519 .pad = { 0, }, \
520 .handler = { \
521 .inval1 = invl, \
522 .type = _typ, \
523 .type2 = _typ2, \
524 .handler = &gen_##name, \
525 .oname = onam, \
526 }, \
527 .oname = onam, \
528 }
529 #else
530 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
531 { \
532 .opc1 = op1, \
533 .opc2 = op2, \
534 .opc3 = op3, \
535 .pad = { 0, }, \
536 .handler = { \
537 .inval1 = invl, \
538 .type = _typ, \
539 .type2 = _typ2, \
540 .handler = &gen_##name, \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .pad = { 0, }, \
550 .handler = { \
551 .inval1 = invl1, \
552 .inval2 = invl2, \
553 .type = _typ, \
554 .type2 = _typ2, \
555 .handler = &gen_##name, \
556 }, \
557 .oname = stringify(name), \
558 }
559 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
560 { \
561 .opc1 = op1, \
562 .opc2 = op2, \
563 .opc3 = op3, \
564 .pad = { 0, }, \
565 .handler = { \
566 .inval1 = invl, \
567 .type = _typ, \
568 .type2 = _typ2, \
569 .handler = &gen_##name, \
570 }, \
571 .oname = onam, \
572 }
573 #endif
574
575 /* SPR load/store helpers */
576 static inline void gen_load_spr(TCGv t, int reg)
577 {
578 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 static inline void gen_store_spr(int reg, TCGv t)
582 {
583 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
584 }
585
586 /* Invalid instruction */
587 static void gen_invalid(DisasContext *ctx)
588 {
589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
590 }
591
592 static opc_handler_t invalid_handler = {
593 .inval1 = 0xFFFFFFFF,
594 .inval2 = 0xFFFFFFFF,
595 .type = PPC_NONE,
596 .type2 = PPC_NONE,
597 .handler = gen_invalid,
598 };
599
600 /*** Integer comparison ***/
601
602 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
603 {
604 TCGv t0 = tcg_temp_new();
605 TCGv_i32 t1 = tcg_temp_new_i32();
606
607 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_LT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_GT);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
620 tcg_gen_trunc_tl_i32(t1, t0);
621 tcg_gen_shli_i32(t1, t1, CRF_EQ);
622 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
623
624 tcg_temp_free(t0);
625 tcg_temp_free_i32(t1);
626 }
627
628 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
629 {
630 TCGv t0 = tcg_const_tl(arg1);
631 gen_op_cmp(arg0, t0, s, crf);
632 tcg_temp_free(t0);
633 }
634
635 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
636 {
637 TCGv t0, t1;
638 t0 = tcg_temp_new();
639 t1 = tcg_temp_new();
640 if (s) {
641 tcg_gen_ext32s_tl(t0, arg0);
642 tcg_gen_ext32s_tl(t1, arg1);
643 } else {
644 tcg_gen_ext32u_tl(t0, arg0);
645 tcg_gen_ext32u_tl(t1, arg1);
646 }
647 gen_op_cmp(t0, t1, s, crf);
648 tcg_temp_free(t1);
649 tcg_temp_free(t0);
650 }
651
652 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
653 {
654 TCGv t0 = tcg_const_tl(arg1);
655 gen_op_cmp32(arg0, t0, s, crf);
656 tcg_temp_free(t0);
657 }
658
659 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
660 {
661 if (NARROW_MODE(ctx)) {
662 gen_op_cmpi32(reg, 0, 1, 0);
663 } else {
664 gen_op_cmpi(reg, 0, 1, 0);
665 }
666 }
667
668 /* cmp */
669 static void gen_cmp(DisasContext *ctx)
670 {
671 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
672 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
673 1, crfD(ctx->opcode));
674 } else {
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678 }
679
680 /* cmpi */
681 static void gen_cmpi(DisasContext *ctx)
682 {
683 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 } else {
687 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
688 1, crfD(ctx->opcode));
689 }
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
696 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
697 0, crfD(ctx->opcode));
698 } else {
699 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
700 0, crfD(ctx->opcode));
701 }
702 }
703
704 /* cmpli */
705 static void gen_cmpli(DisasContext *ctx)
706 {
707 if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
708 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
709 0, crfD(ctx->opcode));
710 } else {
711 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
712 0, crfD(ctx->opcode));
713 }
714 }
715
716 /* isel (PowerPC 2.03 specification) */
717 static void gen_isel(DisasContext *ctx)
718 {
719 int l1, l2;
720 uint32_t bi = rC(ctx->opcode);
721 uint32_t mask;
722 TCGv_i32 t0;
723
724 l1 = gen_new_label();
725 l2 = gen_new_label();
726
727 mask = 1 << (3 - (bi & 0x03));
728 t0 = tcg_temp_new_i32();
729 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
730 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
731 if (rA(ctx->opcode) == 0)
732 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
733 else
734 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
735 tcg_gen_br(l2);
736 gen_set_label(l1);
737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
738 gen_set_label(l2);
739 tcg_temp_free_i32(t0);
740 }
741
742 /* cmpb: PowerPC 2.05 specification */
743 static void gen_cmpb(DisasContext *ctx)
744 {
745 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
746 cpu_gpr[rB(ctx->opcode)]);
747 }
748
749 /*** Integer arithmetic ***/
750
751 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
752 TCGv arg1, TCGv arg2, int sub)
753 {
754 TCGv t0 = tcg_temp_new();
755
756 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
757 tcg_gen_xor_tl(t0, arg1, arg2);
758 if (sub) {
759 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
760 } else {
761 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
762 }
763 tcg_temp_free(t0);
764 if (NARROW_MODE(ctx)) {
765 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
766 }
767 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
768 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
769 }
770
771 /* Common add function */
772 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
773 TCGv arg2, bool add_ca, bool compute_ca,
774 bool compute_ov, bool compute_rc0)
775 {
776 TCGv t0 = ret;
777
778 if (compute_ca || compute_ov) {
779 t0 = tcg_temp_new();
780 }
781
782 if (compute_ca) {
783 if (NARROW_MODE(ctx)) {
784 /* Caution: a non-obvious corner case of the spec is that we
785 must produce the *entire* 64-bit addition, but produce the
786 carry into bit 32. */
787 TCGv t1 = tcg_temp_new();
788 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
789 tcg_gen_add_tl(t0, arg1, arg2);
790 if (add_ca) {
791 tcg_gen_add_tl(t0, t0, cpu_ca);
792 }
793 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
794 tcg_temp_free(t1);
795 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
796 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
797 } else {
798 TCGv zero = tcg_const_tl(0);
799 if (add_ca) {
800 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
801 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
802 } else {
803 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
804 }
805 tcg_temp_free(zero);
806 }
807 } else {
808 tcg_gen_add_tl(t0, arg1, arg2);
809 if (add_ca) {
810 tcg_gen_add_tl(t0, t0, cpu_ca);
811 }
812 }
813
814 if (compute_ov) {
815 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
816 }
817 if (unlikely(compute_rc0)) {
818 gen_set_Rc0(ctx, t0);
819 }
820
821 if (!TCGV_EQUAL(t0, ret)) {
822 tcg_gen_mov_tl(ret, t0);
823 tcg_temp_free(t0);
824 }
825 }
826 /* Add functions with two operands */
827 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
828 static void glue(gen_, name)(DisasContext *ctx) \
829 { \
830 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
831 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
832 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
833 }
834 /* Add functions with one operand and one immediate */
835 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
836 add_ca, compute_ca, compute_ov) \
837 static void glue(gen_, name)(DisasContext *ctx) \
838 { \
839 TCGv t0 = tcg_const_tl(const_val); \
840 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
841 cpu_gpr[rA(ctx->opcode)], t0, \
842 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
843 tcg_temp_free(t0); \
844 }
845
846 /* add add. addo addo. */
847 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
848 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
849 /* addc addc. addco addco. */
850 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
851 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
852 /* adde adde. addeo addeo. */
853 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
854 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
855 /* addme addme. addmeo addmeo. */
856 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
857 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
858 /* addze addze. addzeo addzeo.*/
859 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
860 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
861 /* addi */
862 static void gen_addi(DisasContext *ctx)
863 {
864 target_long simm = SIMM(ctx->opcode);
865
866 if (rA(ctx->opcode) == 0) {
867 /* li case */
868 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
869 } else {
870 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
871 cpu_gpr[rA(ctx->opcode)], simm);
872 }
873 }
874 /* addic addic.*/
875 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
876 {
877 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
878 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
879 c, 0, 1, 0, compute_rc0);
880 tcg_temp_free(c);
881 }
882
883 static void gen_addic(DisasContext *ctx)
884 {
885 gen_op_addic(ctx, 0);
886 }
887
888 static void gen_addic_(DisasContext *ctx)
889 {
890 gen_op_addic(ctx, 1);
891 }
892
893 /* addis */
894 static void gen_addis(DisasContext *ctx)
895 {
896 target_long simm = SIMM(ctx->opcode);
897
898 if (rA(ctx->opcode) == 0) {
899 /* lis case */
900 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
901 } else {
902 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
903 cpu_gpr[rA(ctx->opcode)], simm << 16);
904 }
905 }
906
907 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
908 TCGv arg2, int sign, int compute_ov)
909 {
910 int l1 = gen_new_label();
911 int l2 = gen_new_label();
912 TCGv_i32 t0 = tcg_temp_local_new_i32();
913 TCGv_i32 t1 = tcg_temp_local_new_i32();
914
915 tcg_gen_trunc_tl_i32(t0, arg1);
916 tcg_gen_trunc_tl_i32(t1, arg2);
917 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
918 if (sign) {
919 int l3 = gen_new_label();
920 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
921 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
922 gen_set_label(l3);
923 tcg_gen_div_i32(t0, t0, t1);
924 } else {
925 tcg_gen_divu_i32(t0, t0, t1);
926 }
927 if (compute_ov) {
928 tcg_gen_movi_tl(cpu_ov, 0);
929 }
930 tcg_gen_br(l2);
931 gen_set_label(l1);
932 if (sign) {
933 tcg_gen_sari_i32(t0, t0, 31);
934 } else {
935 tcg_gen_movi_i32(t0, 0);
936 }
937 if (compute_ov) {
938 tcg_gen_movi_tl(cpu_ov, 1);
939 tcg_gen_movi_tl(cpu_so, 1);
940 }
941 gen_set_label(l2);
942 tcg_gen_extu_i32_tl(ret, t0);
943 tcg_temp_free_i32(t0);
944 tcg_temp_free_i32(t1);
945 if (unlikely(Rc(ctx->opcode) != 0))
946 gen_set_Rc0(ctx, ret);
947 }
948 /* Div functions */
949 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
950 static void glue(gen_, name)(DisasContext *ctx) \
951 { \
952 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
953 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
954 sign, compute_ov); \
955 }
956 /* divwu divwu. divwuo divwuo. */
957 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
958 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
959 /* divw divw. divwo divwo. */
960 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
961 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
962 #if defined(TARGET_PPC64)
963 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
964 TCGv arg2, int sign, int compute_ov)
965 {
966 int l1 = gen_new_label();
967 int l2 = gen_new_label();
968
969 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
970 if (sign) {
971 int l3 = gen_new_label();
972 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
973 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
974 gen_set_label(l3);
975 tcg_gen_div_i64(ret, arg1, arg2);
976 } else {
977 tcg_gen_divu_i64(ret, arg1, arg2);
978 }
979 if (compute_ov) {
980 tcg_gen_movi_tl(cpu_ov, 0);
981 }
982 tcg_gen_br(l2);
983 gen_set_label(l1);
984 if (sign) {
985 tcg_gen_sari_i64(ret, arg1, 63);
986 } else {
987 tcg_gen_movi_i64(ret, 0);
988 }
989 if (compute_ov) {
990 tcg_gen_movi_tl(cpu_ov, 1);
991 tcg_gen_movi_tl(cpu_so, 1);
992 }
993 gen_set_label(l2);
994 if (unlikely(Rc(ctx->opcode) != 0))
995 gen_set_Rc0(ctx, ret);
996 }
997 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
998 static void glue(gen_, name)(DisasContext *ctx) \
999 { \
1000 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1001 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1002 sign, compute_ov); \
1003 }
1004 /* divwu divwu. divwuo divwuo. */
1005 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1006 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1007 /* divw divw. divwo divwo. */
1008 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1009 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1010 #endif
1011
1012 /* mulhw mulhw. */
1013 static void gen_mulhw(DisasContext *ctx)
1014 {
1015 TCGv_i32 t0 = tcg_temp_new_i32();
1016 TCGv_i32 t1 = tcg_temp_new_i32();
1017
1018 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1019 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1020 tcg_gen_muls2_i32(t0, t1, t0, t1);
1021 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1022 tcg_temp_free_i32(t0);
1023 tcg_temp_free_i32(t1);
1024 if (unlikely(Rc(ctx->opcode) != 0))
1025 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1026 }
1027
1028 /* mulhwu mulhwu. */
1029 static void gen_mulhwu(DisasContext *ctx)
1030 {
1031 TCGv_i32 t0 = tcg_temp_new_i32();
1032 TCGv_i32 t1 = tcg_temp_new_i32();
1033
1034 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1035 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1036 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1037 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1038 tcg_temp_free_i32(t0);
1039 tcg_temp_free_i32(t1);
1040 if (unlikely(Rc(ctx->opcode) != 0))
1041 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1042 }
1043
1044 /* mullw mullw. */
1045 static void gen_mullw(DisasContext *ctx)
1046 {
1047 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1048 cpu_gpr[rB(ctx->opcode)]);
1049 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1050 if (unlikely(Rc(ctx->opcode) != 0))
1051 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1052 }
1053
1054 /* mullwo mullwo. */
1055 static void gen_mullwo(DisasContext *ctx)
1056 {
1057 TCGv_i32 t0 = tcg_temp_new_i32();
1058 TCGv_i32 t1 = tcg_temp_new_i32();
1059
1060 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1061 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1062 tcg_gen_muls2_i32(t0, t1, t0, t1);
1063 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1064
1065 tcg_gen_sari_i32(t0, t0, 31);
1066 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1067 tcg_gen_extu_i32_tl(cpu_ov, t0);
1068 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1069
1070 tcg_temp_free_i32(t0);
1071 tcg_temp_free_i32(t1);
1072 if (unlikely(Rc(ctx->opcode) != 0))
1073 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1074 }
1075
1076 /* mulli */
1077 static void gen_mulli(DisasContext *ctx)
1078 {
1079 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1080 SIMM(ctx->opcode));
1081 }
1082
1083 #if defined(TARGET_PPC64)
1084 /* mulhd mulhd. */
1085 static void gen_mulhd(DisasContext *ctx)
1086 {
1087 TCGv lo = tcg_temp_new();
1088 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1089 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1090 tcg_temp_free(lo);
1091 if (unlikely(Rc(ctx->opcode) != 0)) {
1092 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1093 }
1094 }
1095
1096 /* mulhdu mulhdu. */
1097 static void gen_mulhdu(DisasContext *ctx)
1098 {
1099 TCGv lo = tcg_temp_new();
1100 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1101 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1102 tcg_temp_free(lo);
1103 if (unlikely(Rc(ctx->opcode) != 0)) {
1104 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1105 }
1106 }
1107
1108 /* mulld mulld. */
1109 static void gen_mulld(DisasContext *ctx)
1110 {
1111 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1112 cpu_gpr[rB(ctx->opcode)]);
1113 if (unlikely(Rc(ctx->opcode) != 0))
1114 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1115 }
1116
1117 /* mulldo mulldo. */
1118 static void gen_mulldo(DisasContext *ctx)
1119 {
1120 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1121 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1122 if (unlikely(Rc(ctx->opcode) != 0)) {
1123 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1124 }
1125 }
1126 #endif
1127
1128 /* Common subf function */
1129 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1130 TCGv arg2, bool add_ca, bool compute_ca,
1131 bool compute_ov, bool compute_rc0)
1132 {
1133 TCGv t0 = ret;
1134
1135 if (compute_ca || compute_ov) {
1136 t0 = tcg_temp_new();
1137 }
1138
1139 if (compute_ca) {
1140 /* dest = ~arg1 + arg2 [+ ca]. */
1141 if (NARROW_MODE(ctx)) {
1142 /* Caution: a non-obvious corner case of the spec is that we
1143 must produce the *entire* 64-bit addition, but produce the
1144 carry into bit 32. */
1145 TCGv inv1 = tcg_temp_new();
1146 TCGv t1 = tcg_temp_new();
1147 tcg_gen_not_tl(inv1, arg1);
1148 if (add_ca) {
1149 tcg_gen_add_tl(t0, arg2, cpu_ca);
1150 } else {
1151 tcg_gen_addi_tl(t0, arg2, 1);
1152 }
1153 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1154 tcg_gen_add_tl(t0, t0, inv1);
1155 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1156 tcg_temp_free(t1);
1157 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1158 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1159 } else if (add_ca) {
1160 TCGv zero, inv1 = tcg_temp_new();
1161 tcg_gen_not_tl(inv1, arg1);
1162 zero = tcg_const_tl(0);
1163 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1164 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1165 tcg_temp_free(zero);
1166 tcg_temp_free(inv1);
1167 } else {
1168 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1169 tcg_gen_sub_tl(t0, arg2, arg1);
1170 }
1171 } else if (add_ca) {
1172 /* Since we're ignoring carry-out, we can simplify the
1173 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1174 tcg_gen_sub_tl(t0, arg2, arg1);
1175 tcg_gen_add_tl(t0, t0, cpu_ca);
1176 tcg_gen_subi_tl(t0, t0, 1);
1177 } else {
1178 tcg_gen_sub_tl(t0, arg2, arg1);
1179 }
1180
1181 if (compute_ov) {
1182 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1183 }
1184 if (unlikely(compute_rc0)) {
1185 gen_set_Rc0(ctx, t0);
1186 }
1187
1188 if (!TCGV_EQUAL(t0, ret)) {
1189 tcg_gen_mov_tl(ret, t0);
1190 tcg_temp_free(t0);
1191 }
1192 }
1193 /* Sub functions with Two operands functions */
1194 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1195 static void glue(gen_, name)(DisasContext *ctx) \
1196 { \
1197 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1198 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1199 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1200 }
1201 /* Sub functions with one operand and one immediate */
1202 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1203 add_ca, compute_ca, compute_ov) \
1204 static void glue(gen_, name)(DisasContext *ctx) \
1205 { \
1206 TCGv t0 = tcg_const_tl(const_val); \
1207 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1208 cpu_gpr[rA(ctx->opcode)], t0, \
1209 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1210 tcg_temp_free(t0); \
1211 }
1212 /* subf subf. subfo subfo. */
1213 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1214 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1215 /* subfc subfc. subfco subfco. */
1216 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1217 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1218 /* subfe subfe. subfeo subfo. */
1219 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1220 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1221 /* subfme subfme. subfmeo subfmeo. */
1222 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1223 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1224 /* subfze subfze. subfzeo subfzeo.*/
1225 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1226 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1227
1228 /* subfic */
1229 static void gen_subfic(DisasContext *ctx)
1230 {
1231 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1232 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1233 c, 0, 1, 0, 0);
1234 tcg_temp_free(c);
1235 }
1236
1237 /* neg neg. nego nego. */
1238 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1239 {
1240 TCGv zero = tcg_const_tl(0);
1241 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1242 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1243 tcg_temp_free(zero);
1244 }
1245
1246 static void gen_neg(DisasContext *ctx)
1247 {
1248 gen_op_arith_neg(ctx, 0);
1249 }
1250
1251 static void gen_nego(DisasContext *ctx)
1252 {
1253 gen_op_arith_neg(ctx, 1);
1254 }
1255
1256 /*** Integer logical ***/
1257 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1258 static void glue(gen_, name)(DisasContext *ctx) \
1259 { \
1260 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1261 cpu_gpr[rB(ctx->opcode)]); \
1262 if (unlikely(Rc(ctx->opcode) != 0)) \
1263 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1264 }
1265
1266 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1267 static void glue(gen_, name)(DisasContext *ctx) \
1268 { \
1269 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1270 if (unlikely(Rc(ctx->opcode) != 0)) \
1271 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1272 }
1273
1274 /* and & and. */
1275 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1276 /* andc & andc. */
1277 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1278
1279 /* andi. */
1280 static void gen_andi_(DisasContext *ctx)
1281 {
1282 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1283 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1284 }
1285
1286 /* andis. */
1287 static void gen_andis_(DisasContext *ctx)
1288 {
1289 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1290 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1291 }
1292
1293 /* cntlzw */
1294 static void gen_cntlzw(DisasContext *ctx)
1295 {
1296 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1297 if (unlikely(Rc(ctx->opcode) != 0))
1298 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1299 }
1300 /* eqv & eqv. */
1301 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1302 /* extsb & extsb. */
1303 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1304 /* extsh & extsh. */
1305 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1306 /* nand & nand. */
1307 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1308 /* nor & nor. */
1309 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1310
1311 /* or & or. */
1312 static void gen_or(DisasContext *ctx)
1313 {
1314 int rs, ra, rb;
1315
1316 rs = rS(ctx->opcode);
1317 ra = rA(ctx->opcode);
1318 rb = rB(ctx->opcode);
1319 /* Optimisation for mr. ri case */
1320 if (rs != ra || rs != rb) {
1321 if (rs != rb)
1322 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1323 else
1324 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1325 if (unlikely(Rc(ctx->opcode) != 0))
1326 gen_set_Rc0(ctx, cpu_gpr[ra]);
1327 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1328 gen_set_Rc0(ctx, cpu_gpr[rs]);
1329 #if defined(TARGET_PPC64)
1330 } else {
1331 int prio = 0;
1332
1333 switch (rs) {
1334 case 1:
1335 /* Set process priority to low */
1336 prio = 2;
1337 break;
1338 case 6:
1339 /* Set process priority to medium-low */
1340 prio = 3;
1341 break;
1342 case 2:
1343 /* Set process priority to normal */
1344 prio = 4;
1345 break;
1346 #if !defined(CONFIG_USER_ONLY)
1347 case 31:
1348 if (ctx->mem_idx > 0) {
1349 /* Set process priority to very low */
1350 prio = 1;
1351 }
1352 break;
1353 case 5:
1354 if (ctx->mem_idx > 0) {
1355 /* Set process priority to medium-hight */
1356 prio = 5;
1357 }
1358 break;
1359 case 3:
1360 if (ctx->mem_idx > 0) {
1361 /* Set process priority to high */
1362 prio = 6;
1363 }
1364 break;
1365 case 7:
1366 if (ctx->mem_idx > 1) {
1367 /* Set process priority to very high */
1368 prio = 7;
1369 }
1370 break;
1371 #endif
1372 default:
1373 /* nop */
1374 break;
1375 }
1376 if (prio) {
1377 TCGv t0 = tcg_temp_new();
1378 gen_load_spr(t0, SPR_PPR);
1379 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1380 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1381 gen_store_spr(SPR_PPR, t0);
1382 tcg_temp_free(t0);
1383 }
1384 #endif
1385 }
1386 }
1387 /* orc & orc. */
1388 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1389
1390 /* xor & xor. */
1391 static void gen_xor(DisasContext *ctx)
1392 {
1393 /* Optimisation for "set to zero" case */
1394 if (rS(ctx->opcode) != rB(ctx->opcode))
1395 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1396 else
1397 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1398 if (unlikely(Rc(ctx->opcode) != 0))
1399 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1400 }
1401
1402 /* ori */
1403 static void gen_ori(DisasContext *ctx)
1404 {
1405 target_ulong uimm = UIMM(ctx->opcode);
1406
1407 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1408 /* NOP */
1409 /* XXX: should handle special NOPs for POWER series */
1410 return;
1411 }
1412 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1413 }
1414
1415 /* oris */
1416 static void gen_oris(DisasContext *ctx)
1417 {
1418 target_ulong uimm = UIMM(ctx->opcode);
1419
1420 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1421 /* NOP */
1422 return;
1423 }
1424 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1425 }
1426
1427 /* xori */
1428 static void gen_xori(DisasContext *ctx)
1429 {
1430 target_ulong uimm = UIMM(ctx->opcode);
1431
1432 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1433 /* NOP */
1434 return;
1435 }
1436 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1437 }
1438
1439 /* xoris */
1440 static void gen_xoris(DisasContext *ctx)
1441 {
1442 target_ulong uimm = UIMM(ctx->opcode);
1443
1444 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1445 /* NOP */
1446 return;
1447 }
1448 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1449 }
1450
1451 /* popcntb : PowerPC 2.03 specification */
1452 static void gen_popcntb(DisasContext *ctx)
1453 {
1454 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1455 }
1456
1457 static void gen_popcntw(DisasContext *ctx)
1458 {
1459 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1460 }
1461
1462 #if defined(TARGET_PPC64)
1463 /* popcntd: PowerPC 2.06 specification */
1464 static void gen_popcntd(DisasContext *ctx)
1465 {
1466 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1467 }
1468 #endif
1469
1470 /* prtyw: PowerPC 2.05 specification */
1471 static void gen_prtyw(DisasContext *ctx)
1472 {
1473 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1474 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1475 TCGv t0 = tcg_temp_new();
1476 tcg_gen_shri_tl(t0, rs, 16);
1477 tcg_gen_xor_tl(ra, rs, t0);
1478 tcg_gen_shri_tl(t0, ra, 8);
1479 tcg_gen_xor_tl(ra, ra, t0);
1480 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1481 tcg_temp_free(t0);
1482 }
1483
1484 #if defined(TARGET_PPC64)
1485 /* prtyd: PowerPC 2.05 specification */
1486 static void gen_prtyd(DisasContext *ctx)
1487 {
1488 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1489 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1490 TCGv t0 = tcg_temp_new();
1491 tcg_gen_shri_tl(t0, rs, 32);
1492 tcg_gen_xor_tl(ra, rs, t0);
1493 tcg_gen_shri_tl(t0, ra, 16);
1494 tcg_gen_xor_tl(ra, ra, t0);
1495 tcg_gen_shri_tl(t0, ra, 8);
1496 tcg_gen_xor_tl(ra, ra, t0);
1497 tcg_gen_andi_tl(ra, ra, 1);
1498 tcg_temp_free(t0);
1499 }
1500 #endif
1501
1502 #if defined(TARGET_PPC64)
1503 /* extsw & extsw. */
1504 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1505
1506 /* cntlzd */
1507 static void gen_cntlzd(DisasContext *ctx)
1508 {
1509 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1510 if (unlikely(Rc(ctx->opcode) != 0))
1511 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1512 }
1513 #endif
1514
1515 /*** Integer rotate ***/
1516
1517 /* rlwimi & rlwimi. */
1518 static void gen_rlwimi(DisasContext *ctx)
1519 {
1520 uint32_t mb, me, sh;
1521
1522 mb = MB(ctx->opcode);
1523 me = ME(ctx->opcode);
1524 sh = SH(ctx->opcode);
1525 if (likely(sh == 0 && mb == 0 && me == 31)) {
1526 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1527 } else {
1528 target_ulong mask;
1529 TCGv t1;
1530 TCGv t0 = tcg_temp_new();
1531 #if defined(TARGET_PPC64)
1532 TCGv_i32 t2 = tcg_temp_new_i32();
1533 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1534 tcg_gen_rotli_i32(t2, t2, sh);
1535 tcg_gen_extu_i32_i64(t0, t2);
1536 tcg_temp_free_i32(t2);
1537 #else
1538 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1539 #endif
1540 #if defined(TARGET_PPC64)
1541 mb += 32;
1542 me += 32;
1543 #endif
1544 mask = MASK(mb, me);
1545 t1 = tcg_temp_new();
1546 tcg_gen_andi_tl(t0, t0, mask);
1547 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1548 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1549 tcg_temp_free(t0);
1550 tcg_temp_free(t1);
1551 }
1552 if (unlikely(Rc(ctx->opcode) != 0))
1553 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1554 }
1555
1556 /* rlwinm & rlwinm. */
1557 static void gen_rlwinm(DisasContext *ctx)
1558 {
1559 uint32_t mb, me, sh;
1560
1561 sh = SH(ctx->opcode);
1562 mb = MB(ctx->opcode);
1563 me = ME(ctx->opcode);
1564
1565 if (likely(mb == 0 && me == (31 - sh))) {
1566 if (likely(sh == 0)) {
1567 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1568 } else {
1569 TCGv t0 = tcg_temp_new();
1570 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1571 tcg_gen_shli_tl(t0, t0, sh);
1572 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1573 tcg_temp_free(t0);
1574 }
1575 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1576 TCGv t0 = tcg_temp_new();
1577 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1578 tcg_gen_shri_tl(t0, t0, mb);
1579 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1580 tcg_temp_free(t0);
1581 } else {
1582 TCGv t0 = tcg_temp_new();
1583 #if defined(TARGET_PPC64)
1584 TCGv_i32 t1 = tcg_temp_new_i32();
1585 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1586 tcg_gen_rotli_i32(t1, t1, sh);
1587 tcg_gen_extu_i32_i64(t0, t1);
1588 tcg_temp_free_i32(t1);
1589 #else
1590 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1591 #endif
1592 #if defined(TARGET_PPC64)
1593 mb += 32;
1594 me += 32;
1595 #endif
1596 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1597 tcg_temp_free(t0);
1598 }
1599 if (unlikely(Rc(ctx->opcode) != 0))
1600 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1601 }
1602
1603 /* rlwnm & rlwnm. */
1604 static void gen_rlwnm(DisasContext *ctx)
1605 {
1606 uint32_t mb, me;
1607 TCGv t0;
1608 #if defined(TARGET_PPC64)
1609 TCGv_i32 t1, t2;
1610 #endif
1611
1612 mb = MB(ctx->opcode);
1613 me = ME(ctx->opcode);
1614 t0 = tcg_temp_new();
1615 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1616 #if defined(TARGET_PPC64)
1617 t1 = tcg_temp_new_i32();
1618 t2 = tcg_temp_new_i32();
1619 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1620 tcg_gen_trunc_i64_i32(t2, t0);
1621 tcg_gen_rotl_i32(t1, t1, t2);
1622 tcg_gen_extu_i32_i64(t0, t1);
1623 tcg_temp_free_i32(t1);
1624 tcg_temp_free_i32(t2);
1625 #else
1626 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1627 #endif
1628 if (unlikely(mb != 0 || me != 31)) {
1629 #if defined(TARGET_PPC64)
1630 mb += 32;
1631 me += 32;
1632 #endif
1633 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1634 } else {
1635 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1636 }
1637 tcg_temp_free(t0);
1638 if (unlikely(Rc(ctx->opcode) != 0))
1639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1640 }
1641
1642 #if defined(TARGET_PPC64)
1643 #define GEN_PPC64_R2(name, opc1, opc2) \
1644 static void glue(gen_, name##0)(DisasContext *ctx) \
1645 { \
1646 gen_##name(ctx, 0); \
1647 } \
1648 \
1649 static void glue(gen_, name##1)(DisasContext *ctx) \
1650 { \
1651 gen_##name(ctx, 1); \
1652 }
1653 #define GEN_PPC64_R4(name, opc1, opc2) \
1654 static void glue(gen_, name##0)(DisasContext *ctx) \
1655 { \
1656 gen_##name(ctx, 0, 0); \
1657 } \
1658 \
1659 static void glue(gen_, name##1)(DisasContext *ctx) \
1660 { \
1661 gen_##name(ctx, 0, 1); \
1662 } \
1663 \
1664 static void glue(gen_, name##2)(DisasContext *ctx) \
1665 { \
1666 gen_##name(ctx, 1, 0); \
1667 } \
1668 \
1669 static void glue(gen_, name##3)(DisasContext *ctx) \
1670 { \
1671 gen_##name(ctx, 1, 1); \
1672 }
1673
1674 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1675 uint32_t sh)
1676 {
1677 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1678 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1679 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1680 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1681 } else {
1682 TCGv t0 = tcg_temp_new();
1683 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1684 if (likely(mb == 0 && me == 63)) {
1685 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1686 } else {
1687 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1688 }
1689 tcg_temp_free(t0);
1690 }
1691 if (unlikely(Rc(ctx->opcode) != 0))
1692 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1693 }
1694 /* rldicl - rldicl. */
1695 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1696 {
1697 uint32_t sh, mb;
1698
1699 sh = SH(ctx->opcode) | (shn << 5);
1700 mb = MB(ctx->opcode) | (mbn << 5);
1701 gen_rldinm(ctx, mb, 63, sh);
1702 }
1703 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1704 /* rldicr - rldicr. */
1705 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1706 {
1707 uint32_t sh, me;
1708
1709 sh = SH(ctx->opcode) | (shn << 5);
1710 me = MB(ctx->opcode) | (men << 5);
1711 gen_rldinm(ctx, 0, me, sh);
1712 }
1713 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1714 /* rldic - rldic. */
1715 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1716 {
1717 uint32_t sh, mb;
1718
1719 sh = SH(ctx->opcode) | (shn << 5);
1720 mb = MB(ctx->opcode) | (mbn << 5);
1721 gen_rldinm(ctx, mb, 63 - sh, sh);
1722 }
1723 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1724
1725 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1726 {
1727 TCGv t0;
1728
1729 mb = MB(ctx->opcode);
1730 me = ME(ctx->opcode);
1731 t0 = tcg_temp_new();
1732 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1733 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1734 if (unlikely(mb != 0 || me != 63)) {
1735 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1736 } else {
1737 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1738 }
1739 tcg_temp_free(t0);
1740 if (unlikely(Rc(ctx->opcode) != 0))
1741 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1742 }
1743
1744 /* rldcl - rldcl. */
1745 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1746 {
1747 uint32_t mb;
1748
1749 mb = MB(ctx->opcode) | (mbn << 5);
1750 gen_rldnm(ctx, mb, 63);
1751 }
1752 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1753 /* rldcr - rldcr. */
1754 static inline void gen_rldcr(DisasContext *ctx, int men)
1755 {
1756 uint32_t me;
1757
1758 me = MB(ctx->opcode) | (men << 5);
1759 gen_rldnm(ctx, 0, me);
1760 }
1761 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1762 /* rldimi - rldimi. */
1763 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1764 {
1765 uint32_t sh, mb, me;
1766
1767 sh = SH(ctx->opcode) | (shn << 5);
1768 mb = MB(ctx->opcode) | (mbn << 5);
1769 me = 63 - sh;
1770 if (unlikely(sh == 0 && mb == 0)) {
1771 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1772 } else {
1773 TCGv t0, t1;
1774 target_ulong mask;
1775
1776 t0 = tcg_temp_new();
1777 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1778 t1 = tcg_temp_new();
1779 mask = MASK(mb, me);
1780 tcg_gen_andi_tl(t0, t0, mask);
1781 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1782 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1783 tcg_temp_free(t0);
1784 tcg_temp_free(t1);
1785 }
1786 if (unlikely(Rc(ctx->opcode) != 0))
1787 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1788 }
1789 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1790 #endif
1791
1792 /*** Integer shift ***/
1793
1794 /* slw & slw. */
1795 static void gen_slw(DisasContext *ctx)
1796 {
1797 TCGv t0, t1;
1798
1799 t0 = tcg_temp_new();
1800 /* AND rS with a mask that is 0 when rB >= 0x20 */
1801 #if defined(TARGET_PPC64)
1802 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1803 tcg_gen_sari_tl(t0, t0, 0x3f);
1804 #else
1805 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1806 tcg_gen_sari_tl(t0, t0, 0x1f);
1807 #endif
1808 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1809 t1 = tcg_temp_new();
1810 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1811 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1812 tcg_temp_free(t1);
1813 tcg_temp_free(t0);
1814 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1815 if (unlikely(Rc(ctx->opcode) != 0))
1816 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1817 }
1818
1819 /* sraw & sraw. */
1820 static void gen_sraw(DisasContext *ctx)
1821 {
1822 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1823 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1824 if (unlikely(Rc(ctx->opcode) != 0))
1825 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1826 }
1827
1828 /* srawi & srawi. */
1829 static void gen_srawi(DisasContext *ctx)
1830 {
1831 int sh = SH(ctx->opcode);
1832 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1833 TCGv src = cpu_gpr[rS(ctx->opcode)];
1834 if (sh == 0) {
1835 tcg_gen_mov_tl(dst, src);
1836 tcg_gen_movi_tl(cpu_ca, 0);
1837 } else {
1838 TCGv t0;
1839 tcg_gen_ext32s_tl(dst, src);
1840 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1841 t0 = tcg_temp_new();
1842 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1843 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1844 tcg_temp_free(t0);
1845 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1846 tcg_gen_sari_tl(dst, dst, sh);
1847 }
1848 if (unlikely(Rc(ctx->opcode) != 0)) {
1849 gen_set_Rc0(ctx, dst);
1850 }
1851 }
1852
1853 /* srw & srw. */
1854 static void gen_srw(DisasContext *ctx)
1855 {
1856 TCGv t0, t1;
1857
1858 t0 = tcg_temp_new();
1859 /* AND rS with a mask that is 0 when rB >= 0x20 */
1860 #if defined(TARGET_PPC64)
1861 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1862 tcg_gen_sari_tl(t0, t0, 0x3f);
1863 #else
1864 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1865 tcg_gen_sari_tl(t0, t0, 0x1f);
1866 #endif
1867 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1868 tcg_gen_ext32u_tl(t0, t0);
1869 t1 = tcg_temp_new();
1870 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1871 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1872 tcg_temp_free(t1);
1873 tcg_temp_free(t0);
1874 if (unlikely(Rc(ctx->opcode) != 0))
1875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1876 }
1877
1878 #if defined(TARGET_PPC64)
1879 /* sld & sld. */
1880 static void gen_sld(DisasContext *ctx)
1881 {
1882 TCGv t0, t1;
1883
1884 t0 = tcg_temp_new();
1885 /* AND rS with a mask that is 0 when rB >= 0x40 */
1886 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1887 tcg_gen_sari_tl(t0, t0, 0x3f);
1888 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1889 t1 = tcg_temp_new();
1890 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1891 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1892 tcg_temp_free(t1);
1893 tcg_temp_free(t0);
1894 if (unlikely(Rc(ctx->opcode) != 0))
1895 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1896 }
1897
1898 /* srad & srad. */
1899 static void gen_srad(DisasContext *ctx)
1900 {
1901 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1902 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1903 if (unlikely(Rc(ctx->opcode) != 0))
1904 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1905 }
1906 /* sradi & sradi. */
1907 static inline void gen_sradi(DisasContext *ctx, int n)
1908 {
1909 int sh = SH(ctx->opcode) + (n << 5);
1910 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1911 TCGv src = cpu_gpr[rS(ctx->opcode)];
1912 if (sh == 0) {
1913 tcg_gen_mov_tl(dst, src);
1914 tcg_gen_movi_tl(cpu_ca, 0);
1915 } else {
1916 TCGv t0;
1917 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1918 t0 = tcg_temp_new();
1919 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1920 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1921 tcg_temp_free(t0);
1922 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1923 tcg_gen_sari_tl(dst, src, sh);
1924 }
1925 if (unlikely(Rc(ctx->opcode) != 0)) {
1926 gen_set_Rc0(ctx, dst);
1927 }
1928 }
1929
1930 static void gen_sradi0(DisasContext *ctx)
1931 {
1932 gen_sradi(ctx, 0);
1933 }
1934
1935 static void gen_sradi1(DisasContext *ctx)
1936 {
1937 gen_sradi(ctx, 1);
1938 }
1939
1940 /* srd & srd. */
1941 static void gen_srd(DisasContext *ctx)
1942 {
1943 TCGv t0, t1;
1944
1945 t0 = tcg_temp_new();
1946 /* AND rS with a mask that is 0 when rB >= 0x40 */
1947 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1948 tcg_gen_sari_tl(t0, t0, 0x3f);
1949 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1950 t1 = tcg_temp_new();
1951 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1952 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1953 tcg_temp_free(t1);
1954 tcg_temp_free(t0);
1955 if (unlikely(Rc(ctx->opcode) != 0))
1956 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1957 }
1958 #endif
1959
1960 /*** Floating-Point arithmetic ***/
1961 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1962 static void gen_f##name(DisasContext *ctx) \
1963 { \
1964 if (unlikely(!ctx->fpu_enabled)) { \
1965 gen_exception(ctx, POWERPC_EXCP_FPU); \
1966 return; \
1967 } \
1968 /* NIP cannot be restored if the memory exception comes from an helper */ \
1969 gen_update_nip(ctx, ctx->nip - 4); \
1970 gen_reset_fpstatus(); \
1971 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1972 cpu_fpr[rA(ctx->opcode)], \
1973 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1974 if (isfloat) { \
1975 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1976 cpu_fpr[rD(ctx->opcode)]); \
1977 } \
1978 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1979 Rc(ctx->opcode) != 0); \
1980 }
1981
1982 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1983 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1984 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1985
1986 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1987 static void gen_f##name(DisasContext *ctx) \
1988 { \
1989 if (unlikely(!ctx->fpu_enabled)) { \
1990 gen_exception(ctx, POWERPC_EXCP_FPU); \
1991 return; \
1992 } \
1993 /* NIP cannot be restored if the memory exception comes from an helper */ \
1994 gen_update_nip(ctx, ctx->nip - 4); \
1995 gen_reset_fpstatus(); \
1996 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1997 cpu_fpr[rA(ctx->opcode)], \
1998 cpu_fpr[rB(ctx->opcode)]); \
1999 if (isfloat) { \
2000 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2001 cpu_fpr[rD(ctx->opcode)]); \
2002 } \
2003 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2004 set_fprf, Rc(ctx->opcode) != 0); \
2005 }
2006 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2007 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2008 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2009
2010 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2011 static void gen_f##name(DisasContext *ctx) \
2012 { \
2013 if (unlikely(!ctx->fpu_enabled)) { \
2014 gen_exception(ctx, POWERPC_EXCP_FPU); \
2015 return; \
2016 } \
2017 /* NIP cannot be restored if the memory exception comes from an helper */ \
2018 gen_update_nip(ctx, ctx->nip - 4); \
2019 gen_reset_fpstatus(); \
2020 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2021 cpu_fpr[rA(ctx->opcode)], \
2022 cpu_fpr[rC(ctx->opcode)]); \
2023 if (isfloat) { \
2024 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2025 cpu_fpr[rD(ctx->opcode)]); \
2026 } \
2027 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2028 set_fprf, Rc(ctx->opcode) != 0); \
2029 }
2030 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2031 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2032 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2033
2034 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2035 static void gen_f##name(DisasContext *ctx) \
2036 { \
2037 if (unlikely(!ctx->fpu_enabled)) { \
2038 gen_exception(ctx, POWERPC_EXCP_FPU); \
2039 return; \
2040 } \
2041 /* NIP cannot be restored if the memory exception comes from an helper */ \
2042 gen_update_nip(ctx, ctx->nip - 4); \
2043 gen_reset_fpstatus(); \
2044 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2045 cpu_fpr[rB(ctx->opcode)]); \
2046 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2047 set_fprf, Rc(ctx->opcode) != 0); \
2048 }
2049
2050 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2051 static void gen_f##name(DisasContext *ctx) \
2052 { \
2053 if (unlikely(!ctx->fpu_enabled)) { \
2054 gen_exception(ctx, POWERPC_EXCP_FPU); \
2055 return; \
2056 } \
2057 /* NIP cannot be restored if the memory exception comes from an helper */ \
2058 gen_update_nip(ctx, ctx->nip - 4); \
2059 gen_reset_fpstatus(); \
2060 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2061 cpu_fpr[rB(ctx->opcode)]); \
2062 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2063 set_fprf, Rc(ctx->opcode) != 0); \
2064 }
2065
2066 /* fadd - fadds */
2067 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2068 /* fdiv - fdivs */
2069 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2070 /* fmul - fmuls */
2071 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2072
2073 /* fre */
2074 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2075
2076 /* fres */
2077 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2078
2079 /* frsqrte */
2080 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2081
2082 /* frsqrtes */
2083 static void gen_frsqrtes(DisasContext *ctx)
2084 {
2085 if (unlikely(!ctx->fpu_enabled)) {
2086 gen_exception(ctx, POWERPC_EXCP_FPU);
2087 return;
2088 }
2089 /* NIP cannot be restored if the memory exception comes from an helper */
2090 gen_update_nip(ctx, ctx->nip - 4);
2091 gen_reset_fpstatus();
2092 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2093 cpu_fpr[rB(ctx->opcode)]);
2094 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2095 cpu_fpr[rD(ctx->opcode)]);
2096 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2097 }
2098
2099 /* fsel */
2100 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2101 /* fsub - fsubs */
2102 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2103 /* Optional: */
2104
2105 /* fsqrt */
2106 static void gen_fsqrt(DisasContext *ctx)
2107 {
2108 if (unlikely(!ctx->fpu_enabled)) {
2109 gen_exception(ctx, POWERPC_EXCP_FPU);
2110 return;
2111 }
2112 /* NIP cannot be restored if the memory exception comes from an helper */
2113 gen_update_nip(ctx, ctx->nip - 4);
2114 gen_reset_fpstatus();
2115 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2116 cpu_fpr[rB(ctx->opcode)]);
2117 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2118 }
2119
2120 static void gen_fsqrts(DisasContext *ctx)
2121 {
2122 if (unlikely(!ctx->fpu_enabled)) {
2123 gen_exception(ctx, POWERPC_EXCP_FPU);
2124 return;
2125 }
2126 /* NIP cannot be restored if the memory exception comes from an helper */
2127 gen_update_nip(ctx, ctx->nip - 4);
2128 gen_reset_fpstatus();
2129 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2130 cpu_fpr[rB(ctx->opcode)]);
2131 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2132 cpu_fpr[rD(ctx->opcode)]);
2133 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2134 }
2135
2136 /*** Floating-Point multiply-and-add ***/
2137 /* fmadd - fmadds */
2138 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2139 /* fmsub - fmsubs */
2140 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2141 /* fnmadd - fnmadds */
2142 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2143 /* fnmsub - fnmsubs */
2144 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2145
2146 /*** Floating-Point round & convert ***/
2147 /* fctiw */
2148 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2149 /* fctiwz */
2150 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2151 /* frsp */
2152 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2153 #if defined(TARGET_PPC64)
2154 /* fcfid */
2155 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2156 /* fctid */
2157 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2158 /* fctidz */
2159 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2160 #endif
2161
2162 /* frin */
2163 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2164 /* friz */
2165 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2166 /* frip */
2167 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2168 /* frim */
2169 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2170
2171 /*** Floating-Point compare ***/
2172
2173 /* fcmpo */
2174 static void gen_fcmpo(DisasContext *ctx)
2175 {
2176 TCGv_i32 crf;
2177 if (unlikely(!ctx->fpu_enabled)) {
2178 gen_exception(ctx, POWERPC_EXCP_FPU);
2179 return;
2180 }
2181 /* NIP cannot be restored if the memory exception comes from an helper */
2182 gen_update_nip(ctx, ctx->nip - 4);
2183 gen_reset_fpstatus();
2184 crf = tcg_const_i32(crfD(ctx->opcode));
2185 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2186 cpu_fpr[rB(ctx->opcode)], crf);
2187 tcg_temp_free_i32(crf);
2188 gen_helper_float_check_status(cpu_env);
2189 }
2190
2191 /* fcmpu */
2192 static void gen_fcmpu(DisasContext *ctx)
2193 {
2194 TCGv_i32 crf;
2195 if (unlikely(!ctx->fpu_enabled)) {
2196 gen_exception(ctx, POWERPC_EXCP_FPU);
2197 return;
2198 }
2199 /* NIP cannot be restored if the memory exception comes from an helper */
2200 gen_update_nip(ctx, ctx->nip - 4);
2201 gen_reset_fpstatus();
2202 crf = tcg_const_i32(crfD(ctx->opcode));
2203 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2204 cpu_fpr[rB(ctx->opcode)], crf);
2205 tcg_temp_free_i32(crf);
2206 gen_helper_float_check_status(cpu_env);
2207 }
2208
2209 /*** Floating-point move ***/
2210 /* fabs */
2211 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2212 static void gen_fabs(DisasContext *ctx)
2213 {
2214 if (unlikely(!ctx->fpu_enabled)) {
2215 gen_exception(ctx, POWERPC_EXCP_FPU);
2216 return;
2217 }
2218 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2219 ~(1ULL << 63));
2220 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2221 }
2222
2223 /* fmr - fmr. */
2224 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2225 static void gen_fmr(DisasContext *ctx)
2226 {
2227 if (unlikely(!ctx->fpu_enabled)) {
2228 gen_exception(ctx, POWERPC_EXCP_FPU);
2229 return;
2230 }
2231 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2232 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2233 }
2234
2235 /* fnabs */
2236 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2237 static void gen_fnabs(DisasContext *ctx)
2238 {
2239 if (unlikely(!ctx->fpu_enabled)) {
2240 gen_exception(ctx, POWERPC_EXCP_FPU);
2241 return;
2242 }
2243 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2244 1ULL << 63);
2245 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2246 }
2247
2248 /* fneg */
2249 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2250 static void gen_fneg(DisasContext *ctx)
2251 {
2252 if (unlikely(!ctx->fpu_enabled)) {
2253 gen_exception(ctx, POWERPC_EXCP_FPU);
2254 return;
2255 }
2256 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2257 1ULL << 63);
2258 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2259 }
2260
2261 /* fcpsgn: PowerPC 2.05 specification */
2262 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2263 static void gen_fcpsgn(DisasContext *ctx)
2264 {
2265 if (unlikely(!ctx->fpu_enabled)) {
2266 gen_exception(ctx, POWERPC_EXCP_FPU);
2267 return;
2268 }
2269 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2270 cpu_fpr[rB(ctx->opcode)], 0, 63);
2271 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2272 }
2273
2274 /*** Floating-Point status & ctrl register ***/
2275
2276 /* mcrfs */
2277 static void gen_mcrfs(DisasContext *ctx)
2278 {
2279 TCGv tmp = tcg_temp_new();
2280 int bfa;
2281
2282 if (unlikely(!ctx->fpu_enabled)) {
2283 gen_exception(ctx, POWERPC_EXCP_FPU);
2284 return;
2285 }
2286 bfa = 4 * (7 - crfS(ctx->opcode));
2287 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2288 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2289 tcg_temp_free(tmp);
2290 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2291 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2292 }
2293
2294 /* mffs */
2295 static void gen_mffs(DisasContext *ctx)
2296 {
2297 if (unlikely(!ctx->fpu_enabled)) {
2298 gen_exception(ctx, POWERPC_EXCP_FPU);
2299 return;
2300 }
2301 gen_reset_fpstatus();
2302 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2303 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2304 }
2305
2306 /* mtfsb0 */
2307 static void gen_mtfsb0(DisasContext *ctx)
2308 {
2309 uint8_t crb;
2310
2311 if (unlikely(!ctx->fpu_enabled)) {
2312 gen_exception(ctx, POWERPC_EXCP_FPU);
2313 return;
2314 }
2315 crb = 31 - crbD(ctx->opcode);
2316 gen_reset_fpstatus();
2317 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2318 TCGv_i32 t0;
2319 /* NIP cannot be restored if the memory exception comes from an helper */
2320 gen_update_nip(ctx, ctx->nip - 4);
2321 t0 = tcg_const_i32(crb);
2322 gen_helper_fpscr_clrbit(cpu_env, t0);
2323 tcg_temp_free_i32(t0);
2324 }
2325 if (unlikely(Rc(ctx->opcode) != 0)) {
2326 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2327 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2328 }
2329 }
2330
2331 /* mtfsb1 */
2332 static void gen_mtfsb1(DisasContext *ctx)
2333 {
2334 uint8_t crb;
2335
2336 if (unlikely(!ctx->fpu_enabled)) {
2337 gen_exception(ctx, POWERPC_EXCP_FPU);
2338 return;
2339 }
2340 crb = 31 - crbD(ctx->opcode);
2341 gen_reset_fpstatus();
2342 /* XXX: we pretend we can only do IEEE floating-point computations */
2343 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2344 TCGv_i32 t0;
2345 /* NIP cannot be restored if the memory exception comes from an helper */
2346 gen_update_nip(ctx, ctx->nip - 4);
2347 t0 = tcg_const_i32(crb);
2348 gen_helper_fpscr_setbit(cpu_env, t0);
2349 tcg_temp_free_i32(t0);
2350 }
2351 if (unlikely(Rc(ctx->opcode) != 0)) {
2352 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2353 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2354 }
2355 /* We can raise a differed exception */
2356 gen_helper_float_check_status(cpu_env);
2357 }
2358
2359 /* mtfsf */
2360 static void gen_mtfsf(DisasContext *ctx)
2361 {
2362 TCGv_i32 t0;
2363 int L = ctx->opcode & 0x02000000;
2364
2365 if (unlikely(!ctx->fpu_enabled)) {
2366 gen_exception(ctx, POWERPC_EXCP_FPU);
2367 return;
2368 }
2369 /* NIP cannot be restored if the memory exception comes from an helper */
2370 gen_update_nip(ctx, ctx->nip - 4);
2371 gen_reset_fpstatus();
2372 if (L)
2373 t0 = tcg_const_i32(0xff);
2374 else
2375 t0 = tcg_const_i32(FM(ctx->opcode));
2376 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2377 tcg_temp_free_i32(t0);
2378 if (unlikely(Rc(ctx->opcode) != 0)) {
2379 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2380 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2381 }
2382 /* We can raise a differed exception */
2383 gen_helper_float_check_status(cpu_env);
2384 }
2385
2386 /* mtfsfi */
2387 static void gen_mtfsfi(DisasContext *ctx)
2388 {
2389 int bf, sh;
2390 TCGv_i64 t0;
2391 TCGv_i32 t1;
2392
2393 if (unlikely(!ctx->fpu_enabled)) {
2394 gen_exception(ctx, POWERPC_EXCP_FPU);
2395 return;
2396 }
2397 bf = crbD(ctx->opcode) >> 2;
2398 sh = 7 - bf;
2399 /* NIP cannot be restored if the memory exception comes from an helper */
2400 gen_update_nip(ctx, ctx->nip - 4);
2401 gen_reset_fpstatus();
2402 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2403 t1 = tcg_const_i32(1 << sh);
2404 gen_helper_store_fpscr(cpu_env, t0, t1);
2405 tcg_temp_free_i64(t0);
2406 tcg_temp_free_i32(t1);
2407 if (unlikely(Rc(ctx->opcode) != 0)) {
2408 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2409 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2410 }
2411 /* We can raise a differed exception */
2412 gen_helper_float_check_status(cpu_env);
2413 }
2414
2415 /*** Addressing modes ***/
2416 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2417 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2418 target_long maskl)
2419 {
2420 target_long simm = SIMM(ctx->opcode);
2421
2422 simm &= ~maskl;
2423 if (rA(ctx->opcode) == 0) {
2424 if (NARROW_MODE(ctx)) {
2425 simm = (uint32_t)simm;
2426 }
2427 tcg_gen_movi_tl(EA, simm);
2428 } else if (likely(simm != 0)) {
2429 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2430 if (NARROW_MODE(ctx)) {
2431 tcg_gen_ext32u_tl(EA, EA);
2432 }
2433 } else {
2434 if (NARROW_MODE(ctx)) {
2435 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2436 } else {
2437 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2438 }
2439 }
2440 }
2441
2442 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2443 {
2444 if (rA(ctx->opcode) == 0) {
2445 if (NARROW_MODE(ctx)) {
2446 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2447 } else {
2448 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2449 }
2450 } else {
2451 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2452 if (NARROW_MODE(ctx)) {
2453 tcg_gen_ext32u_tl(EA, EA);
2454 }
2455 }
2456 }
2457
2458 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2459 {
2460 if (rA(ctx->opcode) == 0) {
2461 tcg_gen_movi_tl(EA, 0);
2462 } else if (NARROW_MODE(ctx)) {
2463 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2464 } else {
2465 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2466 }
2467 }
2468
2469 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2470 target_long val)
2471 {
2472 tcg_gen_addi_tl(ret, arg1, val);
2473 if (NARROW_MODE(ctx)) {
2474 tcg_gen_ext32u_tl(ret, ret);
2475 }
2476 }
2477
2478 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2479 {
2480 int l1 = gen_new_label();
2481 TCGv t0 = tcg_temp_new();
2482 TCGv_i32 t1, t2;
2483 /* NIP cannot be restored if the memory exception comes from an helper */
2484 gen_update_nip(ctx, ctx->nip - 4);
2485 tcg_gen_andi_tl(t0, EA, mask);
2486 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2487 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2488 t2 = tcg_const_i32(0);
2489 gen_helper_raise_exception_err(cpu_env, t1, t2);
2490 tcg_temp_free_i32(t1);
2491 tcg_temp_free_i32(t2);
2492 gen_set_label(l1);
2493 tcg_temp_free(t0);
2494 }
2495
2496 /*** Integer load ***/
2497 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2498 {
2499 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2500 }
2501
2502 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2503 {
2504 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2505 }
2506
2507 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2508 {
2509 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2510 if (unlikely(ctx->le_mode)) {
2511 tcg_gen_bswap16_tl(arg1, arg1);
2512 }
2513 }
2514
2515 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2516 {
2517 if (unlikely(ctx->le_mode)) {
2518 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2519 tcg_gen_bswap16_tl(arg1, arg1);
2520 tcg_gen_ext16s_tl(arg1, arg1);
2521 } else {
2522 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2523 }
2524 }
2525
2526 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2527 {
2528 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2529 if (unlikely(ctx->le_mode)) {
2530 tcg_gen_bswap32_tl(arg1, arg1);
2531 }
2532 }
2533
2534 #if defined(TARGET_PPC64)
2535 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2536 {
2537 if (unlikely(ctx->le_mode)) {
2538 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2539 tcg_gen_bswap32_tl(arg1, arg1);
2540 tcg_gen_ext32s_tl(arg1, arg1);
2541 } else
2542 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2543 }
2544 #endif
2545
2546 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2547 {
2548 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2549 if (unlikely(ctx->le_mode)) {
2550 tcg_gen_bswap64_i64(arg1, arg1);
2551 }
2552 }
2553
2554 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2555 {
2556 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2557 }
2558
2559 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2560 {
2561 if (unlikely(ctx->le_mode)) {
2562 TCGv t0 = tcg_temp_new();
2563 tcg_gen_ext16u_tl(t0, arg1);
2564 tcg_gen_bswap16_tl(t0, t0);
2565 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2566 tcg_temp_free(t0);
2567 } else {
2568 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2569 }
2570 }
2571
2572 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2573 {
2574 if (unlikely(ctx->le_mode)) {
2575 TCGv t0 = tcg_temp_new();
2576 tcg_gen_ext32u_tl(t0, arg1);
2577 tcg_gen_bswap32_tl(t0, t0);
2578 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2579 tcg_temp_free(t0);
2580 } else {
2581 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2582 }
2583 }
2584
2585 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2586 {
2587 if (unlikely(ctx->le_mode)) {
2588 TCGv_i64 t0 = tcg_temp_new_i64();
2589 tcg_gen_bswap64_i64(t0, arg1);
2590 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2591 tcg_temp_free_i64(t0);
2592 } else
2593 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2594 }
2595
2596 #define GEN_LD(name, ldop, opc, type) \
2597 static void glue(gen_, name)(DisasContext *ctx) \
2598 { \
2599 TCGv EA; \
2600 gen_set_access_type(ctx, ACCESS_INT); \
2601 EA = tcg_temp_new(); \
2602 gen_addr_imm_index(ctx, EA, 0); \
2603 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2604 tcg_temp_free(EA); \
2605 }
2606
2607 #define GEN_LDU(name, ldop, opc, type) \
2608 static void glue(gen_, name##u)(DisasContext *ctx) \
2609 { \
2610 TCGv EA; \
2611 if (unlikely(rA(ctx->opcode) == 0 || \
2612 rA(ctx->opcode) == rD(ctx->opcode))) { \
2613 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2614 return; \
2615 } \
2616 gen_set_access_type(ctx, ACCESS_INT); \
2617 EA = tcg_temp_new(); \
2618 if (type == PPC_64B) \
2619 gen_addr_imm_index(ctx, EA, 0x03); \
2620 else \
2621 gen_addr_imm_index(ctx, EA, 0); \
2622 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2623 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2624 tcg_temp_free(EA); \
2625 }
2626
2627 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2628 static void glue(gen_, name##ux)(DisasContext *ctx) \
2629 { \
2630 TCGv EA; \
2631 if (unlikely(rA(ctx->opcode) == 0 || \
2632 rA(ctx->opcode) == rD(ctx->opcode))) { \
2633 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2634 return; \
2635 } \
2636 gen_set_access_type(ctx, ACCESS_INT); \
2637 EA = tcg_temp_new(); \
2638 gen_addr_reg_index(ctx, EA); \
2639 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2640 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2641 tcg_temp_free(EA); \
2642 }
2643
2644 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2645 static void glue(gen_, name##x)(DisasContext *ctx) \
2646 { \
2647 TCGv EA; \
2648 gen_set_access_type(ctx, ACCESS_INT); \
2649 EA = tcg_temp_new(); \
2650 gen_addr_reg_index(ctx, EA); \
2651 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2652 tcg_temp_free(EA); \
2653 }
2654 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2655 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2656
2657 #define GEN_LDS(name, ldop, op, type) \
2658 GEN_LD(name, ldop, op | 0x20, type); \
2659 GEN_LDU(name, ldop, op | 0x21, type); \
2660 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2661 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2662
2663 /* lbz lbzu lbzux lbzx */
2664 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2665 /* lha lhau lhaux lhax */
2666 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2667 /* lhz lhzu lhzux lhzx */
2668 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2669 /* lwz lwzu lwzux lwzx */
2670 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2671 #if defined(TARGET_PPC64)
2672 /* lwaux */
2673 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2674 /* lwax */
2675 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2676 /* ldux */
2677 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2678 /* ldx */
2679 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2680
2681 static void gen_ld(DisasContext *ctx)
2682 {
2683 TCGv EA;
2684 if (Rc(ctx->opcode)) {
2685 if (unlikely(rA(ctx->opcode) == 0 ||
2686 rA(ctx->opcode) == rD(ctx->opcode))) {
2687 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2688 return;
2689 }
2690 }
2691 gen_set_access_type(ctx, ACCESS_INT);
2692 EA = tcg_temp_new();
2693 gen_addr_imm_index(ctx, EA, 0x03);
2694 if (ctx->opcode & 0x02) {
2695 /* lwa (lwau is undefined) */
2696 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2697 } else {
2698 /* ld - ldu */
2699 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2700 }
2701 if (Rc(ctx->opcode))
2702 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2703 tcg_temp_free(EA);
2704 }
2705
2706 /* lq */
2707 static void gen_lq(DisasContext *ctx)
2708 {
2709 #if defined(CONFIG_USER_ONLY)
2710 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2711 #else
2712 int ra, rd;
2713 TCGv EA;
2714
2715 /* Restore CPU state */
2716 if (unlikely(ctx->mem_idx == 0)) {
2717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2718 return;
2719 }
2720 ra = rA(ctx->opcode);
2721 rd = rD(ctx->opcode);
2722 if (unlikely((rd & 1) || rd == ra)) {
2723 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2724 return;
2725 }
2726 if (unlikely(ctx->le_mode)) {
2727 /* Little-endian mode is not handled */
2728 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2729 return;
2730 }
2731 gen_set_access_type(ctx, ACCESS_INT);
2732 EA = tcg_temp_new();
2733 gen_addr_imm_index(ctx, EA, 0x0F);
2734 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2735 gen_addr_add(ctx, EA, EA, 8);
2736 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2737 tcg_temp_free(EA);
2738 #endif
2739 }
2740 #endif
2741
2742 /*** Integer store ***/
2743 #define GEN_ST(name, stop, opc, type) \
2744 static void glue(gen_, name)(DisasContext *ctx) \
2745 { \
2746 TCGv EA; \
2747 gen_set_access_type(ctx, ACCESS_INT); \
2748 EA = tcg_temp_new(); \
2749 gen_addr_imm_index(ctx, EA, 0); \
2750 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2751 tcg_temp_free(EA); \
2752 }
2753
2754 #define GEN_STU(name, stop, opc, type) \
2755 static void glue(gen_, stop##u)(DisasContext *ctx) \
2756 { \
2757 TCGv EA; \
2758 if (unlikely(rA(ctx->opcode) == 0)) { \
2759 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2760 return; \
2761 } \
2762 gen_set_access_type(ctx, ACCESS_INT); \
2763 EA = tcg_temp_new(); \
2764 if (type == PPC_64B) \
2765 gen_addr_imm_index(ctx, EA, 0x03); \
2766 else \
2767 gen_addr_imm_index(ctx, EA, 0); \
2768 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2770 tcg_temp_free(EA); \
2771 }
2772
2773 #define GEN_STUX(name, stop, opc2, opc3, type) \
2774 static void glue(gen_, name##ux)(DisasContext *ctx) \
2775 { \
2776 TCGv EA; \
2777 if (unlikely(rA(ctx->opcode) == 0)) { \
2778 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2779 return; \
2780 } \
2781 gen_set_access_type(ctx, ACCESS_INT); \
2782 EA = tcg_temp_new(); \
2783 gen_addr_reg_index(ctx, EA); \
2784 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2785 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2786 tcg_temp_free(EA); \
2787 }
2788
2789 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2790 static void glue(gen_, name##x)(DisasContext *ctx) \
2791 { \
2792 TCGv EA; \
2793 gen_set_access_type(ctx, ACCESS_INT); \
2794 EA = tcg_temp_new(); \
2795 gen_addr_reg_index(ctx, EA); \
2796 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2797 tcg_temp_free(EA); \
2798 }
2799 #define GEN_STX(name, stop, opc2, opc3, type) \
2800 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2801
2802 #define GEN_STS(name, stop, op, type) \
2803 GEN_ST(name, stop, op | 0x20, type); \
2804 GEN_STU(name, stop, op | 0x21, type); \
2805 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2806 GEN_STX(name, stop, 0x17, op | 0x00, type)
2807
2808 /* stb stbu stbux stbx */
2809 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2810 /* sth sthu sthux sthx */
2811 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2812 /* stw stwu stwux stwx */
2813 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2814 #if defined(TARGET_PPC64)
2815 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2816 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2817
2818 static void gen_std(DisasContext *ctx)
2819 {
2820 int rs;
2821 TCGv EA;
2822
2823 rs = rS(ctx->opcode);
2824 if ((ctx->opcode & 0x3) == 0x2) {
2825 #if defined(CONFIG_USER_ONLY)
2826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2827 #else
2828 /* stq */
2829 if (unlikely(ctx->mem_idx == 0)) {
2830 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2831 return;
2832 }
2833 if (unlikely(rs & 1)) {
2834 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2835 return;
2836 }
2837 if (unlikely(ctx->le_mode)) {
2838 /* Little-endian mode is not handled */
2839 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2840 return;
2841 }
2842 gen_set_access_type(ctx, ACCESS_INT);
2843 EA = tcg_temp_new();
2844 gen_addr_imm_index(ctx, EA, 0x03);
2845 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2846 gen_addr_add(ctx, EA, EA, 8);
2847 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2848 tcg_temp_free(EA);
2849 #endif
2850 } else {
2851 /* std / stdu */
2852 if (Rc(ctx->opcode)) {
2853 if (unlikely(rA(ctx->opcode) == 0)) {
2854 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2855 return;
2856 }
2857 }
2858 gen_set_access_type(ctx, ACCESS_INT);
2859 EA = tcg_temp_new();
2860 gen_addr_imm_index(ctx, EA, 0x03);
2861 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2862 if (Rc(ctx->opcode))
2863 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2864 tcg_temp_free(EA);
2865 }
2866 }
2867 #endif
2868 /*** Integer load and store with byte reverse ***/
2869 /* lhbrx */
2870 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2871 {
2872 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2873 if (likely(!ctx->le_mode)) {
2874 tcg_gen_bswap16_tl(arg1, arg1);
2875 }
2876 }
2877 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2878
2879 /* lwbrx */
2880 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2881 {
2882 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2883 if (likely(!ctx->le_mode)) {
2884 tcg_gen_bswap32_tl(arg1, arg1);
2885 }
2886 }
2887 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2888
2889 #if defined(TARGET_PPC64)
2890 /* ldbrx */
2891 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2892 {
2893 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2894 if (likely(!ctx->le_mode)) {
2895 tcg_gen_bswap64_tl(arg1, arg1);
2896 }
2897 }
2898 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2899 #endif /* TARGET_PPC64 */
2900
2901 /* sthbrx */
2902 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2903 {
2904 if (likely(!ctx->le_mode)) {
2905 TCGv t0 = tcg_temp_new();
2906 tcg_gen_ext16u_tl(t0, arg1);
2907 tcg_gen_bswap16_tl(t0, t0);
2908 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2909 tcg_temp_free(t0);
2910 } else {
2911 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2912 }
2913 }
2914 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2915
2916 /* stwbrx */
2917 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2918 {
2919 if (likely(!ctx->le_mode)) {
2920 TCGv t0 = tcg_temp_new();
2921 tcg_gen_ext32u_tl(t0, arg1);
2922 tcg_gen_bswap32_tl(t0, t0);
2923 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2924 tcg_temp_free(t0);
2925 } else {
2926 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2927 }
2928 }
2929 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2930
2931 #if defined(TARGET_PPC64)
2932 /* stdbrx */
2933 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2934 {
2935 if (likely(!ctx->le_mode)) {
2936 TCGv t0 = tcg_temp_new();
2937 tcg_gen_bswap64_tl(t0, arg1);
2938 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2939 tcg_temp_free(t0);
2940 } else {
2941 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2942 }
2943 }
2944 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2945 #endif /* TARGET_PPC64 */
2946
2947 /*** Integer load and store multiple ***/
2948
2949 /* lmw */
2950 static void gen_lmw(DisasContext *ctx)
2951 {
2952 TCGv t0;
2953 TCGv_i32 t1;
2954 gen_set_access_type(ctx, ACCESS_INT);
2955 /* NIP cannot be restored if the memory exception comes from an helper */
2956 gen_update_nip(ctx, ctx->nip - 4);
2957 t0 = tcg_temp_new();
2958 t1 = tcg_const_i32(rD(ctx->opcode));
2959 gen_addr_imm_index(ctx, t0, 0);
2960 gen_helper_lmw(cpu_env, t0, t1);
2961 tcg_temp_free(t0);
2962 tcg_temp_free_i32(t1);
2963 }
2964
2965 /* stmw */
2966 static void gen_stmw(DisasContext *ctx)
2967 {
2968 TCGv t0;
2969 TCGv_i32 t1;
2970 gen_set_access_type(ctx, ACCESS_INT);
2971 /* NIP cannot be restored if the memory exception comes from an helper */
2972 gen_update_nip(ctx, ctx->nip - 4);
2973 t0 = tcg_temp_new();
2974 t1 = tcg_const_i32(rS(ctx->opcode));
2975 gen_addr_imm_index(ctx, t0, 0);
2976 gen_helper_stmw(cpu_env, t0, t1);
2977 tcg_temp_free(t0);
2978 tcg_temp_free_i32(t1);
2979 }
2980
2981 /*** Integer load and store strings ***/
2982
2983 /* lswi */
2984 /* PowerPC32 specification says we must generate an exception if
2985 * rA is in the range of registers to be loaded.
2986 * In an other hand, IBM says this is valid, but rA won't be loaded.
2987 * For now, I'll follow the spec...
2988 */
2989 static void gen_lswi(DisasContext *ctx)
2990 {
2991 TCGv t0;
2992 TCGv_i32 t1, t2;
2993 int nb = NB(ctx->opcode);
2994 int start = rD(ctx->opcode);
2995 int ra = rA(ctx->opcode);
2996 int nr;
2997
2998 if (nb == 0)
2999 nb = 32;
3000 nr = nb / 4;
3001 if (unlikely(((start + nr) > 32 &&
3002 start <= ra && (start + nr - 32) > ra) ||
3003 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3004 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3005 return;
3006 }
3007 gen_set_access_type(ctx, ACCESS_INT);
3008 /* NIP cannot be restored if the memory exception comes from an helper */
3009 gen_update_nip(ctx, ctx->nip - 4);
3010 t0 = tcg_temp_new();
3011 gen_addr_register(ctx, t0);
3012 t1 = tcg_const_i32(nb);
3013 t2 = tcg_const_i32(start);
3014 gen_helper_lsw(cpu_env, t0, t1, t2);
3015 tcg_temp_free(t0);
3016 tcg_temp_free_i32(t1);
3017 tcg_temp_free_i32(t2);
3018 }
3019
3020 /* lswx */
3021 static void gen_lswx(DisasContext *ctx)
3022 {
3023 TCGv t0;
3024 TCGv_i32 t1, t2, t3;
3025 gen_set_access_type(ctx, ACCESS_INT);
3026 /* NIP cannot be restored if the memory exception comes from an helper */
3027 gen_update_nip(ctx, ctx->nip - 4);
3028 t0 = tcg_temp_new();
3029 gen_addr_reg_index(ctx, t0);
3030 t1 = tcg_const_i32(rD(ctx->opcode));
3031 t2 = tcg_const_i32(rA(ctx->opcode));
3032 t3 = tcg_const_i32(rB(ctx->opcode));
3033 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3034 tcg_temp_free(t0);
3035 tcg_temp_free_i32(t1);
3036 tcg_temp_free_i32(t2);
3037 tcg_temp_free_i32(t3);
3038 }
3039
3040 /* stswi */
3041 static void gen_stswi(DisasContext *ctx)
3042 {
3043 TCGv t0;
3044 TCGv_i32 t1, t2;
3045 int nb = NB(ctx->opcode);
3046 gen_set_access_type(ctx, ACCESS_INT);
3047 /* NIP cannot be restored if the memory exception comes from an helper */
3048 gen_update_nip(ctx, ctx->nip - 4);
3049 t0 = tcg_temp_new();
3050 gen_addr_register(ctx, t0);
3051 if (nb == 0)
3052 nb = 32;
3053 t1 = tcg_const_i32(nb);
3054 t2 = tcg_const_i32(rS(ctx->opcode));
3055 gen_helper_stsw(cpu_env, t0, t1, t2);
3056 tcg_temp_free(t0);
3057 tcg_temp_free_i32(t1);
3058 tcg_temp_free_i32(t2);
3059 }
3060
3061 /* stswx */
3062 static void gen_stswx(DisasContext *ctx)
3063 {
3064 TCGv t0;
3065 TCGv_i32 t1, t2;
3066 gen_set_access_type(ctx, ACCESS_INT);
3067 /* NIP cannot be restored if the memory exception comes from an helper */
3068 gen_update_nip(ctx, ctx->nip - 4);
3069 t0 = tcg_temp_new();
3070 gen_addr_reg_index(ctx, t0);
3071 t1 = tcg_temp_new_i32();
3072 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3073 tcg_gen_andi_i32(t1, t1, 0x7F);
3074 t2 = tcg_const_i32(rS(ctx->opcode));
3075 gen_helper_stsw(cpu_env, t0, t1, t2);
3076 tcg_temp_free(t0);
3077 tcg_temp_free_i32(t1);
3078 tcg_temp_free_i32(t2);
3079 }
3080
3081 /*** Memory synchronisation ***/
3082 /* eieio */
3083 static void gen_eieio(DisasContext *ctx)
3084 {
3085 }
3086
3087 /* isync */
3088 static void gen_isync(DisasContext *ctx)
3089 {
3090 gen_stop_exception(ctx);
3091 }
3092
3093 /* lwarx */
3094 static void gen_lwarx(DisasContext *ctx)
3095 {
3096 TCGv t0;
3097 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3098 gen_set_access_type(ctx, ACCESS_RES);
3099 t0 = tcg_temp_local_new();
3100 gen_addr_reg_index(ctx, t0);
3101 gen_check_align(ctx, t0, 0x03);
3102 gen_qemu_ld32u(ctx, gpr, t0);
3103 tcg_gen_mov_tl(cpu_reserve, t0);
3104 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3105 tcg_temp_free(t0);
3106 }
3107
3108 #if defined(CONFIG_USER_ONLY)
3109 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3110 int reg, int size)
3111 {
3112 TCGv t0 = tcg_temp_new();
3113 uint32_t save_exception = ctx->exception;
3114
3115 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3116 tcg_gen_movi_tl(t0, (size << 5) | reg);
3117 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3118 tcg_temp_free(t0);
3119 gen_update_nip(ctx, ctx->nip-4);
3120 ctx->exception = POWERPC_EXCP_BRANCH;
3121 gen_exception(ctx, POWERPC_EXCP_STCX);
3122 ctx->exception = save_exception;
3123 }
3124 #endif
3125
3126 /* stwcx. */
3127 static void gen_stwcx_(DisasContext *ctx)
3128 {
3129 TCGv t0;
3130 gen_set_access_type(ctx, ACCESS_RES);
3131 t0 = tcg_temp_local_new();
3132 gen_addr_reg_index(ctx, t0);
3133 gen_check_align(ctx, t0, 0x03);
3134 #if defined(CONFIG_USER_ONLY)
3135 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3136 #else
3137 {
3138 int l1;
3139
3140 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3141 l1 = gen_new_label();
3142 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3143 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3144 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3145 gen_set_label(l1);
3146 tcg_gen_movi_tl(cpu_reserve, -1);
3147 }
3148 #endif
3149 tcg_temp_free(t0);
3150 }
3151
3152 #if defined(TARGET_PPC64)
3153 /* ldarx */
3154 static void gen_ldarx(DisasContext *ctx)
3155 {
3156 TCGv t0;
3157 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3158 gen_set_access_type(ctx, ACCESS_RES);
3159 t0 = tcg_temp_local_new();
3160 gen_addr_reg_index(ctx, t0);
3161 gen_check_align(ctx, t0, 0x07);
3162 gen_qemu_ld64(ctx, gpr, t0);
3163 tcg_gen_mov_tl(cpu_reserve, t0);
3164 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3165 tcg_temp_free(t0);
3166 }
3167
3168 /* stdcx. */
3169 static void gen_stdcx_(DisasContext *ctx)
3170 {
3171 TCGv t0;
3172 gen_set_access_type(ctx, ACCESS_RES);
3173 t0 = tcg_temp_local_new();
3174 gen_addr_reg_index(ctx, t0);
3175 gen_check_align(ctx, t0, 0x07);
3176 #if defined(CONFIG_USER_ONLY)
3177 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3178 #else
3179 {
3180 int l1;
3181 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3182 l1 = gen_new_label();
3183 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3184 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3185 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3186 gen_set_label(l1);
3187 tcg_gen_movi_tl(cpu_reserve, -1);
3188 }
3189 #endif
3190 tcg_temp_free(t0);
3191 }
3192 #endif /* defined(TARGET_PPC64) */
3193
3194 /* sync */
3195 static void gen_sync(DisasContext *ctx)
3196 {
3197 }
3198
3199 /* wait */
3200 static void gen_wait(DisasContext *ctx)
3201 {
3202 TCGv_i32 t0 = tcg_temp_new_i32();
3203 tcg_gen_st_i32(t0, cpu_env,
3204 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3205 tcg_temp_free_i32(t0);
3206 /* Stop translation, as the CPU is supposed to sleep from now */
3207 gen_exception_err(ctx, EXCP_HLT, 1);
3208 }
3209
3210 /*** Floating-point load ***/
3211 #define GEN_LDF(name, ldop, opc, type) \
3212 static void glue(gen_, name)(DisasContext *ctx) \
3213 { \
3214 TCGv EA; \
3215 if (unlikely(!ctx->fpu_enabled)) { \
3216 gen_exception(ctx, POWERPC_EXCP_FPU); \
3217 return; \
3218 } \
3219 gen_set_access_type(ctx, ACCESS_FLOAT); \
3220 EA = tcg_temp_new(); \
3221 gen_addr_imm_index(ctx, EA, 0); \
3222 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3223 tcg_temp_free(EA); \
3224 }
3225
3226 #define GEN_LDUF(name, ldop, opc, type) \
3227 static void glue(gen_, name##u)(DisasContext *ctx) \
3228 { \
3229 TCGv EA; \
3230 if (unlikely(!ctx->fpu_enabled)) { \
3231 gen_exception(ctx, POWERPC_EXCP_FPU); \
3232 return; \
3233 } \
3234 if (unlikely(rA(ctx->opcode) == 0)) { \
3235 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3236 return; \
3237 } \
3238 gen_set_access_type(ctx, ACCESS_FLOAT); \
3239 EA = tcg_temp_new(); \
3240 gen_addr_imm_index(ctx, EA, 0); \
3241 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3242 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3243 tcg_temp_free(EA); \
3244 }
3245
3246 #define GEN_LDUXF(name, ldop, opc, type) \
3247 static void glue(gen_, name##ux)(DisasContext *ctx) \
3248 { \
3249 TCGv EA; \
3250 if (unlikely(!ctx->fpu_enabled)) { \
3251 gen_exception(ctx, POWERPC_EXCP_FPU); \
3252 return; \
3253 } \
3254 if (unlikely(rA(ctx->opcode) == 0)) { \
3255 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3256 return; \
3257 } \
3258 gen_set_access_type(ctx, ACCESS_FLOAT); \
3259 EA = tcg_temp_new(); \
3260 gen_addr_reg_index(ctx, EA); \
3261 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3262 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3263 tcg_temp_free(EA); \
3264 }
3265
3266 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3267 static void glue(gen_, name##x)(DisasContext *ctx) \
3268 { \
3269 TCGv EA; \
3270 if (unlikely(!ctx->fpu_enabled)) { \
3271 gen_exception(ctx, POWERPC_EXCP_FPU); \
3272 return; \
3273 } \
3274 gen_set_access_type(ctx, ACCESS_FLOAT); \
3275 EA = tcg_temp_new(); \
3276 gen_addr_reg_index(ctx, EA); \
3277 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3278 tcg_temp_free(EA); \
3279 }
3280
3281 #define GEN_LDFS(name, ldop, op, type) \
3282 GEN_LDF(name, ldop, op | 0x20, type); \
3283 GEN_LDUF(name, ldop, op | 0x21, type); \
3284 GEN_LDUXF(name, ldop, op | 0x01, type); \
3285 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3286
3287 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3288 {
3289 TCGv t0 = tcg_temp_new();
3290 TCGv_i32 t1 = tcg_temp_new_i32();
3291 gen_qemu_ld32u(ctx, t0, arg2);
3292 tcg_gen_trunc_tl_i32(t1, t0);
3293 tcg_temp_free(t0);
3294 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3295 tcg_temp_free_i32(t1);
3296 }
3297
3298 /* lfd lfdu lfdux lfdx */
3299 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3300 /* lfs lfsu lfsux lfsx */
3301 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3302
3303 /*** Floating-point store ***/
3304 #define GEN_STF(name, stop, opc, type) \
3305 static void glue(gen_, name)(DisasContext *ctx) \
3306 { \
3307 TCGv EA; \
3308 if (unlikely(!ctx->fpu_enabled)) { \
3309 gen_exception(ctx, POWERPC_EXCP_FPU); \
3310 return; \
3311 } \
3312 gen_set_access_type(ctx, ACCESS_FLOAT); \
3313 EA = tcg_temp_new(); \
3314 gen_addr_imm_index(ctx, EA, 0); \
3315 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3316 tcg_temp_free(EA); \
3317 }
3318
3319 #define GEN_STUF(name, stop, opc, type) \
3320 static void glue(gen_, name##u)(DisasContext *ctx) \
3321 { \
3322 TCGv EA; \
3323 if (unlikely(!ctx->fpu_enabled)) { \
3324 gen_exception(ctx, POWERPC_EXCP_FPU); \
3325 return; \
3326 } \
3327 if (unlikely(rA(ctx->opcode) == 0)) { \
3328 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3329 return; \
3330 } \
3331 gen_set_access_type(ctx, ACCESS_FLOAT); \
3332 EA = tcg_temp_new(); \
3333 gen_addr_imm_index(ctx, EA, 0); \
3334 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3335 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3336 tcg_temp_free(EA); \
3337 }
3338
3339 #define GEN_STUXF(name, stop, opc, type) \
3340 static void glue(gen_, name##ux)(DisasContext *ctx) \
3341 { \
3342 TCGv EA; \
3343 if (unlikely(!ctx->fpu_enabled)) { \
3344 gen_exception(ctx, POWERPC_EXCP_FPU); \
3345 return; \
3346 } \
3347 if (unlikely(rA(ctx->opcode) == 0)) { \
3348 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3349 return; \
3350 } \
3351 gen_set_access_type(ctx, ACCESS_FLOAT); \
3352 EA = tcg_temp_new(); \
3353 gen_addr_reg_index(ctx, EA); \
3354 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3355 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3356 tcg_temp_free(EA); \
3357 }
3358
3359 #define GEN_STXF(name, stop, opc2, opc3, type) \
3360 static void glue(gen_, name##x)(DisasContext *ctx) \
3361 { \
3362 TCGv EA; \
3363 if (unlikely(!ctx->fpu_enabled)) { \
3364 gen_exception(ctx, POWERPC_EXCP_FPU); \
3365 return; \
3366 } \
3367 gen_set_access_type(ctx, ACCESS_FLOAT); \
3368 EA = tcg_temp_new(); \
3369 gen_addr_reg_index(ctx, EA); \
3370 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3371 tcg_temp_free(EA); \
3372 }
3373
3374 #define GEN_STFS(name, stop, op, type) \
3375 GEN_STF(name, stop, op | 0x20, type); \
3376 GEN_STUF(name, stop, op | 0x21, type); \
3377 GEN_STUXF(name, stop, op | 0x01, type); \
3378 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3379
3380 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3381 {
3382 TCGv_i32 t0 = tcg_temp_new_i32();
3383 TCGv t1 = tcg_temp_new();
3384 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3385 tcg_gen_extu_i32_tl(t1, t0);
3386 tcg_temp_free_i32(t0);
3387 gen_qemu_st32(ctx, t1, arg2);
3388 tcg_temp_free(t1);
3389 }
3390
3391 /* stfd stfdu stfdux stfdx */
3392 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3393 /* stfs stfsu stfsux stfsx */
3394 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3395
3396 /* Optional: */
3397 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3398 {
3399 TCGv t0 = tcg_temp_new();
3400 tcg_gen_trunc_i64_tl(t0, arg1),
3401 gen_qemu_st32(ctx, t0, arg2);
3402 tcg_temp_free(t0);
3403 }
3404 /* stfiwx */
3405 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3406
3407 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3408 {
3409 #if defined(TARGET_PPC64)
3410 if (ctx->has_cfar)
3411 tcg_gen_movi_tl(cpu_cfar, nip);
3412 #endif
3413 }
3414
3415 /*** Branch ***/
3416 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3417 {
3418 TranslationBlock *tb;
3419 tb = ctx->tb;
3420 if (NARROW_MODE(ctx)) {
3421 dest = (uint32_t) dest;
3422 }
3423 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3424 likely(!ctx->singlestep_enabled)) {
3425 tcg_gen_goto_tb(n);
3426 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3427 tcg_gen_exit_tb((tcg_target_long)tb + n);
3428 } else {
3429 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3430 if (unlikely(ctx->singlestep_enabled)) {
3431 if ((ctx->singlestep_enabled &
3432 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3433 (ctx->exception == POWERPC_EXCP_BRANCH ||
3434 ctx->exception == POWERPC_EXCP_TRACE)) {
3435 target_ulong tmp = ctx->nip;
3436 ctx->nip = dest;
3437 gen_exception(ctx, POWERPC_EXCP_TRACE);
3438 ctx->nip = tmp;
3439 }
3440 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3441 gen_debug_exception(ctx);
3442 }
3443 }
3444 tcg_gen_exit_tb(0);
3445 }
3446 }
3447
3448 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3449 {
3450 if (NARROW_MODE(ctx)) {
3451 nip = (uint32_t)nip;
3452 }
3453 tcg_gen_movi_tl(cpu_lr, nip);
3454 }
3455
3456 /* b ba bl bla */
3457 static void gen_b(DisasContext *ctx)
3458 {
3459 target_ulong li, target;
3460
3461 ctx->exception = POWERPC_EXCP_BRANCH;
3462 /* sign extend LI */
3463 li = LI(ctx->opcode);
3464 li = (li ^ 0x02000000) - 0x02000000;
3465 if (likely(AA(ctx->opcode) == 0)) {
3466 target = ctx->nip + li - 4;
3467 } else {
3468 target = li;
3469 }
3470 if (LK(ctx->opcode)) {
3471 gen_setlr(ctx, ctx->nip);
3472 }
3473 gen_update_cfar(ctx, ctx->nip);
3474 gen_goto_tb(ctx, 0, target);
3475 }
3476
3477 #define BCOND_IM 0
3478 #define BCOND_LR 1
3479 #define BCOND_CTR 2
3480
3481 static inline void gen_bcond(DisasContext *ctx, int type)
3482 {
3483 uint32_t bo = BO(ctx->opcode);
3484 int l1;
3485 TCGv target;
3486
3487 ctx->exception = POWERPC_EXCP_BRANCH;
3488 if (type == BCOND_LR || type == BCOND_CTR) {
3489 target = tcg_temp_local_new();
3490 if (type == BCOND_CTR)
3491 tcg_gen_mov_tl(target, cpu_ctr);
3492 else
3493 tcg_gen_mov_tl(target, cpu_lr);
3494 } else {
3495 TCGV_UNUSED(target);
3496 }
3497 if (LK(ctx->opcode))
3498 gen_setlr(ctx, ctx->nip);
3499 l1 = gen_new_label();
3500 if ((bo & 0x4) == 0) {
3501 /* Decrement and test CTR */
3502 TCGv temp = tcg_temp_new();
3503 if (unlikely(type == BCOND_CTR)) {
3504 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3505 return;
3506 }
3507 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3508 if (NARROW_MODE(ctx)) {
3509 tcg_gen_ext32u_tl(temp, cpu_ctr);
3510 } else {
3511 tcg_gen_mov_tl(temp, cpu_ctr);
3512 }
3513 if (bo & 0x2) {
3514 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3515 } else {
3516 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3517 }
3518 tcg_temp_free(temp);
3519 }
3520 if ((bo & 0x10) == 0) {
3521 /* Test CR */
3522 uint32_t bi = BI(ctx->opcode);
3523 uint32_t mask = 1 << (3 - (bi & 0x03));
3524 TCGv_i32 temp = tcg_temp_new_i32();
3525
3526 if (bo & 0x8) {
3527 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3528 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3529 } else {
3530 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3531 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3532 }
3533 tcg_temp_free_i32(temp);
3534 }
3535 gen_update_cfar(ctx, ctx->nip);
3536 if (type == BCOND_IM) {
3537 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3538 if (likely(AA(ctx->opcode) == 0)) {
3539 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3540 } else {
3541 gen_goto_tb(ctx, 0, li);
3542 }
3543 gen_set_label(l1);
3544 gen_goto_tb(ctx, 1, ctx->nip);
3545 } else {
3546 if (NARROW_MODE(ctx)) {
3547 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3548 } else {
3549 tcg_gen_andi_tl(cpu_nip, target, ~3);
3550 }
3551 tcg_gen_exit_tb(0);
3552 gen_set_label(l1);
3553 gen_update_nip(ctx, ctx->nip);
3554 tcg_gen_exit_tb(0);
3555 }
3556 }
3557
3558 static void gen_bc(DisasContext *ctx)
3559 {
3560 gen_bcond(ctx, BCOND_IM);
3561 }
3562
3563 static void gen_bcctr(DisasContext *ctx)
3564 {
3565 gen_bcond(ctx, BCOND_CTR);
3566 }
3567
3568 static void gen_bclr(DisasContext *ctx)
3569 {
3570 gen_bcond(ctx, BCOND_LR);
3571 }
3572
3573 /*** Condition register logical ***/
3574 #define GEN_CRLOGIC(name, tcg_op, opc) \
3575 static void glue(gen_, name)(DisasContext *ctx) \
3576 { \
3577 uint8_t bitmask; \
3578 int sh; \
3579 TCGv_i32 t0, t1; \
3580 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3581 t0 = tcg_temp_new_i32(); \
3582 if (sh > 0) \
3583 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3584 else if (sh < 0) \
3585 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3586 else \
3587 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3588 t1 = tcg_temp_new_i32(); \
3589 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3590 if (sh > 0) \
3591 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3592 else if (sh < 0) \
3593 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3594 else \
3595 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3596 tcg_op(t0, t0, t1); \
3597 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3598 tcg_gen_andi_i32(t0, t0, bitmask); \
3599 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3600 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3601 tcg_temp_free_i32(t0); \
3602 tcg_temp_free_i32(t1); \
3603 }
3604
3605 /* crand */
3606 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3607 /* crandc */
3608 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3609 /* creqv */
3610 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3611 /* crnand */
3612 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3613 /* crnor */
3614 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3615 /* cror */
3616 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3617 /* crorc */
3618 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3619 /* crxor */
3620 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3621
3622 /* mcrf */
3623 static void gen_mcrf(DisasContext *ctx)
3624 {
3625 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3626 }
3627
3628 /*** System linkage ***/
3629
3630 /* rfi (mem_idx only) */
3631 static void gen_rfi(DisasContext *ctx)
3632 {
3633 #if defined(CONFIG_USER_ONLY)
3634 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3635 #else
3636 /* Restore CPU state */
3637 if (unlikely(!ctx->mem_idx)) {
3638 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3639 return;
3640 }
3641 gen_update_cfar(ctx, ctx->nip);
3642 gen_helper_rfi(cpu_env);
3643 gen_sync_exception(ctx);
3644 #endif
3645 }
3646
3647 #if defined(TARGET_PPC64)
3648 static void gen_rfid(DisasContext *ctx)
3649 {
3650 #if defined(CONFIG_USER_ONLY)
3651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3652 #else
3653 /* Restore CPU state */
3654 if (unlikely(!ctx->mem_idx)) {
3655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3656 return;
3657 }
3658 gen_update_cfar(ctx, ctx->nip);
3659 gen_helper_rfid(cpu_env);
3660 gen_sync_exception(ctx);
3661 #endif
3662 }
3663
3664 static void gen_hrfid(DisasContext *ctx)
3665 {
3666 #if defined(CONFIG_USER_ONLY)
3667 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3668 #else
3669 /* Restore CPU state */
3670 if (unlikely(ctx->mem_idx <= 1)) {
3671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3672 return;
3673 }
3674 gen_helper_hrfid(cpu_env);
3675 gen_sync_exception(ctx);
3676 #endif
3677 }
3678 #endif
3679
3680 /* sc */
3681 #if defined(CONFIG_USER_ONLY)
3682 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3683 #else
3684 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3685 #endif
3686 static void gen_sc(DisasContext *ctx)
3687 {
3688 uint32_t lev;
3689
3690 lev = (ctx->opcode >> 5) & 0x7F;
3691 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3692 }
3693
3694 /*** Trap ***/
3695
3696 /* tw */
3697 static void gen_tw(DisasContext *ctx)
3698 {
3699 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3700 /* Update the nip since this might generate a trap exception */
3701 gen_update_nip(ctx, ctx->nip);
3702 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3703 t0);
3704 tcg_temp_free_i32(t0);
3705 }
3706
3707 /* twi */
3708 static void gen_twi(DisasContext *ctx)
3709 {
3710 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3711 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3712 /* Update the nip since this might generate a trap exception */
3713 gen_update_nip(ctx, ctx->nip);
3714 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3715 tcg_temp_free(t0);
3716 tcg_temp_free_i32(t1);
3717 }
3718
3719 #if defined(TARGET_PPC64)
3720 /* td */
3721 static void gen_td(DisasContext *ctx)
3722 {
3723 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3724 /* Update the nip since this might generate a trap exception */
3725 gen_update_nip(ctx, ctx->nip);
3726 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3727 t0);
3728 tcg_temp_free_i32(t0);
3729 }
3730
3731 /* tdi */
3732 static void gen_tdi(DisasContext *ctx)
3733 {
3734 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3735 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3736 /* Update the nip since this might generate a trap exception */
3737 gen_update_nip(ctx, ctx->nip);
3738 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3739 tcg_temp_free(t0);
3740 tcg_temp_free_i32(t1);
3741 }
3742 #endif
3743
3744 /*** Processor control ***/
3745
3746 static void gen_read_xer(TCGv dst)
3747 {
3748 TCGv t0 = tcg_temp_new();
3749 TCGv t1 = tcg_temp_new();
3750 TCGv t2 = tcg_temp_new();
3751 tcg_gen_mov_tl(dst, cpu_xer);
3752 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3753 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3754 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3755 tcg_gen_or_tl(t0, t0, t1);
3756 tcg_gen_or_tl(dst, dst, t2);
3757 tcg_gen_or_tl(dst, dst, t0);
3758 tcg_temp_free(t0);
3759 tcg_temp_free(t1);
3760 tcg_temp_free(t2);
3761 }
3762
3763 static void gen_write_xer(TCGv src)
3764 {
3765 tcg_gen_andi_tl(cpu_xer, src,
3766 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3767 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3768 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3769 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3770 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3771 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3772 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3773 }
3774
3775 /* mcrxr */
3776 static void gen_mcrxr(DisasContext *ctx)
3777 {
3778 TCGv_i32 t0 = tcg_temp_new_i32();
3779 TCGv_i32 t1 = tcg_temp_new_i32();
3780 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3781
3782 tcg_gen_trunc_tl_i32(t0, cpu_so);
3783 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3784 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3785 tcg_gen_shri_i32(t0, t0, 2);
3786 tcg_gen_shri_i32(t1, t1, 1);
3787 tcg_gen_or_i32(dst, dst, t0);
3788 tcg_gen_or_i32(dst, dst, t1);
3789 tcg_temp_free_i32(t0);
3790 tcg_temp_free_i32(t1);
3791
3792 tcg_gen_movi_tl(cpu_so, 0);
3793 tcg_gen_movi_tl(cpu_ov, 0);
3794 tcg_gen_movi_tl(cpu_ca, 0);
3795 }
3796
3797 /* mfcr mfocrf */
3798 static void gen_mfcr(DisasContext *ctx)
3799 {
3800 uint32_t crm, crn;
3801
3802 if (likely(ctx->opcode & 0x00100000)) {
3803 crm = CRM(ctx->opcode);
3804 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3805 crn = ctz32 (crm);
3806 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3807 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3808 cpu_gpr[rD(ctx->opcode)], crn * 4);
3809 }
3810 } else {
3811 TCGv_i32 t0 = tcg_temp_new_i32();
3812 tcg_gen_mov_i32(t0, cpu_crf[0]);
3813 tcg_gen_shli_i32(t0, t0, 4);
3814 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3815 tcg_gen_shli_i32(t0, t0, 4);
3816 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3817 tcg_gen_shli_i32(t0, t0, 4);
3818 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3819 tcg_gen_shli_i32(t0, t0, 4);
3820 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3821 tcg_gen_shli_i32(t0, t0, 4);
3822 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3823 tcg_gen_shli_i32(t0, t0, 4);
3824 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3825 tcg_gen_shli_i32(t0, t0, 4);
3826 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3827 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3828 tcg_temp_free_i32(t0);
3829 }
3830 }
3831
3832 /* mfmsr */
3833 static void gen_mfmsr(DisasContext *ctx)
3834 {
3835 #if defined(CONFIG_USER_ONLY)
3836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3837 #else
3838 if (unlikely(!ctx->mem_idx)) {
3839 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3840 return;
3841 }
3842 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3843 #endif
3844 }
3845
3846 static void spr_noaccess(void *opaque, int gprn, int sprn)
3847 {
3848 #if 0
3849 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3850 printf("ERROR: try to access SPR %d !\n", sprn);
3851 #endif
3852 }
3853 #define SPR_NOACCESS (&spr_noaccess)
3854
3855 /* mfspr */
3856 static inline void gen_op_mfspr(DisasContext *ctx)
3857 {
3858 void (*read_cb)(void *opaque, int gprn, int sprn);
3859 uint32_t sprn = SPR(ctx->opcode);
3860
3861 #if !defined(CONFIG_USER_ONLY)
3862 if (ctx->mem_idx == 2)
3863 read_cb = ctx->spr_cb[sprn].hea_read;
3864 else if (ctx->mem_idx)
3865 read_cb = ctx->spr_cb[sprn].oea_read;
3866 else
3867 #endif
3868 read_cb = ctx->spr_cb[sprn].uea_read;
3869 if (likely(read_cb != NULL)) {
3870 if (likely(read_cb != SPR_NOACCESS)) {
3871 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3872 } else {
3873 /* Privilege exception */
3874 /* This is a hack to avoid warnings when running Linux:
3875 * this OS breaks the PowerPC virtualisation model,
3876 * allowing userland application to read the PVR
3877 */
3878 if (sprn != SPR_PVR) {
3879 qemu_log("Trying to read privileged spr %d %03x at "
3880 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3881 printf("Trying to read privileged spr %d %03x at "
3882 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3883 }
3884 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3885 }
3886 } else {
3887 /* Not defined */
3888 qemu_log("Trying to read invalid spr %d %03x at "
3889 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3890 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3891 sprn, sprn, ctx->nip);
3892 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3893 }
3894 }
3895
3896 static void gen_mfspr(DisasContext *ctx)
3897 {
3898 gen_op_mfspr(ctx);
3899 }
3900
3901 /* mftb */
3902 static void gen_mftb(DisasContext *ctx)
3903 {
3904 gen_op_mfspr(ctx);
3905 }
3906
3907 /* mtcrf mtocrf*/
3908 static void gen_mtcrf(DisasContext *ctx)
3909 {
3910 uint32_t crm, crn;
3911
3912 crm = CRM(ctx->opcode);
3913 if (likely((ctx->opcode & 0x00100000))) {
3914 if (crm && ((crm & (crm - 1)) == 0)) {
3915 TCGv_i32 temp = tcg_temp_new_i32();
3916 crn = ctz32 (crm);
3917 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3918 tcg_gen_shri_i32(temp, temp, crn * 4);
3919 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3920 tcg_temp_free_i32(temp);
3921 }
3922 } else {
3923 TCGv_i32 temp = tcg_temp_new_i32();
3924 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3925 for (crn = 0 ; crn < 8 ; crn++) {
3926 if (crm & (1 << crn)) {
3927 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3928 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3929 }
3930 }
3931 tcg_temp_free_i32(temp);
3932 }
3933 }
3934
3935 /* mtmsr */
3936 #if defined(TARGET_PPC64)
3937 static void gen_mtmsrd(DisasContext *ctx)
3938 {
3939 #if defined(CONFIG_USER_ONLY)
3940 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3941 #else
3942 if (unlikely(!ctx->mem_idx)) {
3943 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3944 return;
3945 }
3946 if (ctx->opcode & 0x00010000) {
3947 /* Special form that does not need any synchronisation */
3948 TCGv t0 = tcg_temp_new();
3949 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3950 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3951 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3952 tcg_temp_free(t0);
3953 } else {
3954 /* XXX: we need to update nip before the store
3955 * if we enter power saving mode, we will exit the loop
3956 * directly from ppc_store_msr
3957 */
3958 gen_update_nip(ctx, ctx->nip);
3959 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3960 /* Must stop the translation as machine state (may have) changed */
3961 /* Note that mtmsr is not always defined as context-synchronizing */
3962 gen_stop_exception(ctx);
3963 }
3964 #endif
3965 }
3966 #endif
3967
3968 static void gen_mtmsr(DisasContext *ctx)
3969 {
3970 #if defined(CONFIG_USER_ONLY)
3971 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3972 #else
3973 if (unlikely(!ctx->mem_idx)) {
3974 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3975 return;
3976 }
3977 if (ctx->opcode & 0x00010000) {
3978 /* Special form that does not need any synchronisation */
3979 TCGv t0 = tcg_temp_new();
3980 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3981 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3982 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3983 tcg_temp_free(t0);
3984 } else {
3985 TCGv msr = tcg_temp_new();
3986
3987 /* XXX: we need to update nip before the store
3988 * if we enter power saving mode, we will exit the loop
3989 * directly from ppc_store_msr
3990 */
3991 gen_update_nip(ctx, ctx->nip);
3992 #if defined(TARGET_PPC64)
3993 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3994 #else
3995 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3996 #endif
3997 gen_helper_store_msr(cpu_env, msr);
3998 /* Must stop the translation as machine state (may have) changed */
3999 /* Note that mtmsr is not always defined as context-synchronizing */
4000 gen_stop_exception(ctx);
4001 }
4002 #endif
4003 }
4004
4005 /* mtspr */
4006 static void gen_mtspr(DisasContext *ctx)
4007 {
4008 void (*write_cb)(void *opaque, int sprn, int gprn);
4009 uint32_t sprn = SPR(ctx->opcode);
4010
4011 #if !defined(CONFIG_USER_ONLY)
4012 if (ctx->mem_idx == 2)
4013 write_cb = ctx->spr_cb[sprn].hea_write;
4014 else if (ctx->mem_idx)
4015 write_cb = ctx->spr_cb[sprn].oea_write;
4016 else
4017 #endif
4018 write_cb = ctx->spr_cb[sprn].uea_write;
4019 if (likely(write_cb != NULL)) {
4020 if (likely(write_cb != SPR_NOACCESS)) {
4021 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4022 } else {
4023 /* Privilege exception */
4024 qemu_log("Trying to write privileged spr %d %03x at "
4025 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4026 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
4027 "\n", sprn, sprn, ctx->nip);
4028 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4029 }
4030 } else {
4031 /* Not defined */
4032 qemu_log("Trying to write invalid spr %d %03x at "
4033 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4034 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
4035 sprn, sprn, ctx->nip);
4036 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4037 }
4038 }
4039
4040 /*** Cache management ***/
4041
4042 /* dcbf */
4043 static void gen_dcbf(DisasContext *ctx)
4044 {
4045 /* XXX: specification says this is treated as a load by the MMU */
4046 TCGv t0;
4047 gen_set_access_type(ctx, ACCESS_CACHE);
4048 t0 = tcg_temp_new();
4049 gen_addr_reg_index(ctx, t0);
4050 gen_qemu_ld8u(ctx, t0, t0);
4051 tcg_temp_free(t0);
4052 }
4053
4054 /* dcbi (Supervisor only) */
4055 static void gen_dcbi(DisasContext *ctx)
4056 {
4057 #if defined(CONFIG_USER_ONLY)
4058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4059 #else
4060 TCGv EA, val;
4061 if (unlikely(!ctx->mem_idx)) {
4062 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4063 return;
4064 }
4065 EA = tcg_temp_new();
4066 gen_set_access_type(ctx, ACCESS_CACHE);
4067 gen_addr_reg_index(ctx, EA);
4068 val = tcg_temp_new();
4069 /* XXX: specification says this should be treated as a store by the MMU */
4070 gen_qemu_ld8u(ctx, val, EA);
4071 gen_qemu_st8(ctx, val, EA);
4072 tcg_temp_free(val);
4073 tcg_temp_free(EA);
4074 #endif
4075 }
4076
4077 /* dcdst */
4078 static void gen_dcbst(DisasContext *ctx)
4079 {
4080 /* XXX: specification say this is treated as a load by the MMU */
4081 TCGv t0;
4082 gen_set_access_type(ctx, ACCESS_CACHE);
4083 t0 = tcg_temp_new();
4084 gen_addr_reg_index(ctx, t0);
4085 gen_qemu_ld8u(ctx, t0, t0);
4086 tcg_temp_free(t0);
4087 }
4088
4089 /* dcbt */
4090 static void gen_dcbt(DisasContext *ctx)
4091 {
4092 /* interpreted as no-op */
4093 /* XXX: specification say this is treated as a load by the MMU
4094 * but does not generate any exception
4095 */
4096 }
4097
4098 /* dcbtst */
4099 static void gen_dcbtst(DisasContext *ctx)
4100 {
4101 /* interpreted as no-op */
4102 /* XXX: specification say this is treated as a load by the MMU
4103 * but does not generate any exception
4104 */
4105 }
4106
4107 /* dcbz */
4108 static void gen_dcbz(DisasContext *ctx)
4109 {
4110 TCGv tcgv_addr;
4111 TCGv_i32 tcgv_is_dcbzl;
4112 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4113
4114 gen_set_access_type(ctx, ACCESS_CACHE);
4115 /* NIP cannot be restored if the memory exception comes from an helper */
4116 gen_update_nip(ctx, ctx->nip - 4);
4117 tcgv_addr = tcg_temp_new();
4118 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4119
4120 gen_addr_reg_index(ctx, tcgv_addr);
4121 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4122
4123 tcg_temp_free(tcgv_addr);
4124 tcg_temp_free_i32(tcgv_is_dcbzl);
4125 }
4126
4127 /* dst / dstt */
4128 static void gen_dst(DisasContext *ctx)
4129 {
4130 if (rA(ctx->opcode) == 0) {
4131 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4132 } else {
4133 /* interpreted as no-op */
4134 }
4135 }
4136
4137 /* dstst /dststt */
4138 static void gen_dstst(DisasContext *ctx)
4139 {
4140 if (rA(ctx->opcode) == 0) {
4141 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4142 } else {
4143 /* interpreted as no-op */
4144 }
4145
4146 }
4147
4148 /* dss / dssall */
4149 static void gen_dss(DisasContext *ctx)
4150 {
4151 /* interpreted as no-op */
4152 }
4153
4154 /* icbi */
4155 static void gen_icbi(DisasContext *ctx)
4156 {
4157 TCGv t0;
4158 gen_set_access_type(ctx, ACCESS_CACHE);
4159 /* NIP cannot be restored if the memory exception comes from an helper */
4160 gen_update_nip(ctx, ctx->nip - 4);
4161 t0 = tcg_temp_new();
4162 gen_addr_reg_index(ctx, t0);
4163 gen_helper_icbi(cpu_env, t0);
4164 tcg_temp_free(t0);
4165 }
4166
4167 /* Optional: */
4168 /* dcba */
4169 static void gen_dcba(DisasContext *ctx)
4170 {
4171 /* interpreted as no-op */
4172 /* XXX: specification say this is treated as a store by the MMU
4173 * but does not generate any exception
4174 */
4175 }
4176
4177 /*** Segment register manipulation ***/
4178 /* Supervisor only: */
4179
4180 /* mfsr */
4181 static void gen_mfsr(DisasContext *ctx)
4182 {
4183 #if defined(CONFIG_USER_ONLY)
4184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4185 #else
4186 TCGv t0;
4187 if (unlikely(!ctx->mem_idx)) {
4188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4189 return;
4190 }
4191 t0 = tcg_const_tl(SR(ctx->opcode));
4192 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4193 tcg_temp_free(t0);
4194 #endif
4195 }
4196
4197 /* mfsrin */
4198 static void gen_mfsrin(DisasContext *ctx)
4199 {
4200 #if defined(CONFIG_USER_ONLY)
4201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4202 #else
4203 TCGv t0;
4204 if (unlikely(!ctx->mem_idx)) {
4205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4206 return;
4207 }
4208 t0 = tcg_temp_new();
4209 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4210 tcg_gen_andi_tl(t0, t0, 0xF);
4211 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4212 tcg_temp_free(t0);
4213 #endif
4214 }
4215
4216 /* mtsr */
4217 static void gen_mtsr(DisasContext *ctx)
4218 {
4219 #if defined(CONFIG_USER_ONLY)
4220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4221 #else
4222 TCGv t0;
4223 if (unlikely(!ctx->mem_idx)) {
4224 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4225 return;
4226 }
4227 t0 = tcg_const_tl(SR(ctx->opcode));
4228 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4229 tcg_temp_free(t0);
4230 #endif
4231 }
4232
4233 /* mtsrin */
4234 static void gen_mtsrin(DisasContext *ctx)
4235 {
4236 #if defined(CONFIG_USER_ONLY)
4237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4238 #else
4239 TCGv t0;
4240 if (unlikely(!ctx->mem_idx)) {
4241 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4242 return;
4243 }
4244 t0 = tcg_temp_new();
4245 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4246 tcg_gen_andi_tl(t0, t0, 0xF);
4247 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4248 tcg_temp_free(t0);
4249 #endif
4250 }
4251
4252 #if defined(TARGET_PPC64)
4253 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4254
4255 /* mfsr */
4256 static void gen_mfsr_64b(DisasContext *ctx)
4257 {
4258 #if defined(CONFIG_USER_ONLY)
4259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4260 #else
4261 TCGv t0;
4262 if (unlikely(!ctx->mem_idx)) {
4263 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4264 return;
4265 }
4266 t0 = tcg_const_tl(SR(ctx->opcode));
4267 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4268 tcg_temp_free(t0);
4269 #endif
4270 }
4271
4272 /* mfsrin */
4273 static void gen_mfsrin_64b(DisasContext *ctx)
4274 {
4275 #if defined(CONFIG_USER_ONLY)
4276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4277 #else
4278 TCGv t0;
4279 if (unlikely(!ctx->mem_idx)) {
4280 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4281 return;
4282 }
4283 t0 = tcg_temp_new();
4284 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4285 tcg_gen_andi_tl(t0, t0, 0xF);
4286 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4287 tcg_temp_free(t0);
4288 #endif
4289 }
4290
4291 /* mtsr */
4292 static void gen_mtsr_64b(DisasContext *ctx)
4293 {
4294 #if defined(CONFIG_USER_ONLY)
4295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4296 #else
4297 TCGv t0;
4298 if (unlikely(!ctx->mem_idx)) {
4299 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4300 return;
4301 }
4302 t0 = tcg_const_tl(SR(ctx->opcode));
4303 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4304 tcg_temp_free(t0);
4305 #endif
4306 }
4307
4308 /* mtsrin */
4309 static void gen_mtsrin_64b(DisasContext *ctx)
4310 {
4311 #if defined(CONFIG_USER_ONLY)
4312 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4313 #else
4314 TCGv t0;
4315 if (unlikely(!ctx->mem_idx)) {
4316 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4317 return;
4318 }
4319 t0 = tcg_temp_new();
4320 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4321 tcg_gen_andi_tl(t0, t0, 0xF);
4322 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4323 tcg_temp_free(t0);
4324 #endif
4325 }
4326
4327 /* slbmte */
4328 static void gen_slbmte(DisasContext *ctx)
4329 {
4330 #if defined(CONFIG_USER_ONLY)
4331 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4332 #else
4333 if (unlikely(!ctx->mem_idx)) {
4334 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4335 return;
4336 }
4337 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4338 cpu_gpr[rS(ctx->opcode)]);
4339 #endif
4340 }
4341
4342 static void gen_slbmfee(DisasContext *ctx)
4343 {
4344 #if defined(CONFIG_USER_ONLY)
4345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4346 #else
4347 if (unlikely(!ctx->mem_idx)) {
4348 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4349 return;
4350 }
4351 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4352 cpu_gpr[rB(ctx->opcode)]);
4353 #endif
4354 }
4355
4356 static void gen_slbmfev(DisasContext *ctx)
4357 {
4358 #if defined(CONFIG_USER_ONLY)
4359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4360 #else
4361 if (unlikely(!ctx->mem_idx)) {
4362 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4363 return;
4364 }
4365 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4366 cpu_gpr[rB(ctx->opcode)]);
4367 #endif
4368 }
4369 #endif /* defined(TARGET_PPC64) */
4370
4371 /*** Lookaside buffer management ***/
4372 /* Optional & mem_idx only: */
4373
4374 /* tlbia */
4375 static void gen_tlbia(DisasContext *ctx)
4376 {
4377 #if defined(CONFIG_USER_ONLY)
4378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4379 #else
4380 if (unlikely(!ctx->mem_idx)) {
4381 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4382 return;
4383 }
4384 gen_helper_tlbia(cpu_env);
4385 #endif
4386 }
4387
4388 /* tlbiel */
4389 static void gen_tlbiel(DisasContext *ctx)
4390 {
4391 #if defined(CONFIG_USER_ONLY)
4392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4393 #else
4394 if (unlikely(!ctx->mem_idx)) {
4395 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4396 return;
4397 }
4398 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4399 #endif
4400 }
4401
4402 /* tlbie */
4403 static void gen_tlbie(DisasContext *ctx)
4404 {
4405 #if defined(CONFIG_USER_ONLY)
4406 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4407 #else
4408 if (unlikely(!ctx->mem_idx)) {
4409 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4410 return;
4411 }
4412 if (NARROW_MODE(ctx)) {
4413 TCGv t0 = tcg_temp_new();
4414 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4415 gen_helper_tlbie(cpu_env, t0);
4416 tcg_temp_free(t0);
4417 } else {
4418 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4419 }
4420 #endif
4421 }
4422
4423 /* tlbsync */
4424 static void gen_tlbsync(DisasContext *ctx)
4425 {
4426 #if defined(CONFIG_USER_ONLY)
4427 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4428 #else
4429 if (unlikely(!ctx->mem_idx)) {
4430 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4431 return;
4432 }
4433 /* This has no effect: it should ensure that all previous
4434 * tlbie have completed
4435 */
4436 gen_stop_exception(ctx);
4437 #endif
4438 }
4439
4440 #if defined(TARGET_PPC64)
4441 /* slbia */
4442 static void gen_slbia(DisasContext *ctx)
4443 {
4444 #if defined(CONFIG_USER_ONLY)
4445 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4446 #else
4447 if (unlikely(!ctx->mem_idx)) {
4448 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4449 return;
4450 }
4451 gen_helper_slbia(cpu_env);
4452 #endif
4453 }
4454
4455 /* slbie */
4456 static void gen_slbie(DisasContext *ctx)
4457 {
4458 #if defined(CONFIG_USER_ONLY)
4459 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4460 #else
4461 if (unlikely(!ctx->mem_idx)) {
4462 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4463 return;
4464 }
4465 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4466 #endif
4467 }
4468 #endif
4469
4470 /*** External control ***/
4471 /* Optional: */
4472
4473 /* eciwx */
4474 static void gen_eciwx(DisasContext *ctx)
4475 {
4476 TCGv t0;
4477 /* Should check EAR[E] ! */
4478 gen_set_access_type(ctx, ACCESS_EXT);
4479 t0 = tcg_temp_new();
4480 gen_addr_reg_index(ctx, t0);
4481 gen_check_align(ctx, t0, 0x03);
4482 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4483 tcg_temp_free(t0);
4484 }
4485
4486 /* ecowx */
4487 static void gen_ecowx(DisasContext *ctx)
4488 {
4489 TCGv t0;
4490 /* Should check EAR[E] ! */
4491 gen_set_access_type(ctx, ACCESS_EXT);
4492 t0 = tcg_temp_new();
4493 gen_addr_reg_index(ctx, t0);
4494 gen_check_align(ctx, t0, 0x03);
4495 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4496 tcg_temp_free(t0);
4497 }
4498
4499 /* PowerPC 601 specific instructions */
4500
4501 /* abs - abs. */
4502 static void gen_abs(DisasContext *ctx)
4503 {
4504 int l1 = gen_new_label();
4505 int l2 = gen_new_label();
4506 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4507 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4508 tcg_gen_br(l2);
4509 gen_set_label(l1);
4510 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4511 gen_set_label(l2);
4512 if (unlikely(Rc(ctx->opcode) != 0))
4513 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4514 }
4515
4516 /* abso - abso. */
4517 static void gen_abso(DisasContext *ctx)
4518 {
4519 int l1 = gen_new_label();
4520 int l2 = gen_new_label();
4521 int l3 = gen_new_label();
4522 /* Start with XER OV disabled, the most likely case */
4523 tcg_gen_movi_tl(cpu_ov, 0);
4524 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4525 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4526 tcg_gen_movi_tl(cpu_ov, 1);
4527 tcg_gen_movi_tl(cpu_so, 1);
4528 tcg_gen_br(l2);
4529 gen_set_label(l1);
4530 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4531 tcg_gen_br(l3);
4532 gen_set_label(l2);
4533 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4534 gen_set_label(l3);
4535 if (unlikely(Rc(ctx->opcode) != 0))
4536 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4537 }
4538
4539 /* clcs */
4540 static void gen_clcs(DisasContext *ctx)
4541 {
4542 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4543 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4544 tcg_temp_free_i32(t0);
4545 /* Rc=1 sets CR0 to an undefined state */
4546 }
4547
4548 /* div - div. */
4549 static void gen_div(DisasContext *ctx)
4550 {
4551 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4552 cpu_gpr[rB(ctx->opcode)]);
4553 if (unlikely(Rc(ctx->opcode) != 0))
4554 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4555 }
4556
4557 /* divo - divo. */
4558 static void gen_divo(DisasContext *ctx)
4559 {
4560 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4561 cpu_gpr[rB(ctx->opcode)]);
4562 if (unlikely(Rc(ctx->opcode) != 0))
4563 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4564 }
4565
4566 /* divs - divs. */
4567 static void gen_divs(DisasContext *ctx)
4568 {
4569 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4570 cpu_gpr[rB(ctx->opcode)]);
4571 if (unlikely(Rc(ctx->opcode) != 0))
4572 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4573 }
4574
4575 /* divso - divso. */
4576 static void gen_divso(DisasContext *ctx)
4577 {
4578 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4579 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4580 if (unlikely(Rc(ctx->opcode) != 0))
4581 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4582 }
4583
4584 /* doz - doz. */
4585 static void gen_doz(DisasContext *ctx)
4586 {
4587 int l1 = gen_new_label();
4588 int l2 = gen_new_label();
4589 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4590 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4591 tcg_gen_br(l2);
4592 gen_set_label(l1);
4593 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4594 gen_set_label(l2);
4595 if (unlikely(Rc(ctx->opcode) != 0))
4596 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4597 }
4598
4599 /* dozo - dozo. */
4600 static void gen_dozo(DisasContext *ctx)
4601 {
4602 int l1 = gen_new_label();
4603 int l2 = gen_new_label();
4604 TCGv t0 = tcg_temp_new();
4605 TCGv t1 = tcg_temp_new();
4606 TCGv t2 = tcg_temp_new();
4607 /* Start with XER OV disabled, the most likely case */
4608 tcg_gen_movi_tl(cpu_ov, 0);
4609 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4610 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4611 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4612 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4613 tcg_gen_andc_tl(t1, t1, t2);
4614 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4615 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4616 tcg_gen_movi_tl(cpu_ov, 1);
4617 tcg_gen_movi_tl(cpu_so, 1);
4618 tcg_gen_br(l2);
4619 gen_set_label(l1);
4620 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4621 gen_set_label(l2);
4622 tcg_temp_free(t0);
4623 tcg_temp_free(t1);
4624 tcg_temp_free(t2);
4625 if (unlikely(Rc(ctx->opcode) != 0))
4626 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4627 }
4628
4629 /* dozi */
4630 static void gen_dozi(DisasContext *ctx)
4631 {
4632 target_long simm = SIMM(ctx->opcode);
4633 int l1 = gen_new_label();
4634 int l2 = gen_new_label();
4635 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4636 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4637 tcg_gen_br(l2);
4638 gen_set_label(l1);
4639 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4640 gen_set_label(l2);
4641 if (unlikely(Rc(ctx->opcode) != 0))
4642 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4643 }
4644
4645 /* lscbx - lscbx. */
4646 static void gen_lscbx(DisasContext *ctx)
4647 {
4648 TCGv t0 = tcg_temp_new();
4649 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4650 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4651 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4652
4653 gen_addr_reg_index(ctx, t0);
4654 /* NIP cannot be restored if the memory exception comes from an helper */
4655 gen_update_nip(ctx, ctx->nip - 4);
4656 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4657 tcg_temp_free_i32(t1);
4658 tcg_temp_free_i32(t2);
4659 tcg_temp_free_i32(t3);
4660 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4661 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4662 if (unlikely(Rc(ctx->opcode) != 0))
4663 gen_set_Rc0(ctx, t0);
4664 tcg_temp_free(t0);
4665 }
4666
4667 /* maskg - maskg. */
4668 static void gen_maskg(DisasContext *ctx)
4669 {
4670 int l1 = gen_new_label();
4671 TCGv t0 = tcg_temp_new();
4672 TCGv t1 = tcg_temp_new();
4673 TCGv t2 = tcg_temp_new();
4674 TCGv t3 = tcg_temp_new();
4675 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4676 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4677 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4678 tcg_gen_addi_tl(t2, t0, 1);
4679 tcg_gen_shr_tl(t2, t3, t2);
4680 tcg_gen_shr_tl(t3, t3, t1);
4681 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4682 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4683 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4684 gen_set_label(l1);
4685 tcg_temp_free(t0);
4686 tcg_temp_free(t1);
4687 tcg_temp_free(t2);
4688 tcg_temp_free(t3);
4689 if (unlikely(Rc(ctx->opcode) != 0))
4690 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4691 }
4692
4693 /* maskir - maskir. */
4694 static void gen_maskir(DisasContext *ctx)
4695 {
4696 TCGv t0 = tcg_temp_new();
4697 TCGv t1 = tcg_temp_new();
4698 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4699 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4700 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4701 tcg_temp_free(t0);
4702 tcg_temp_free(t1);
4703 if (unlikely(Rc(ctx->opcode) != 0))
4704 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4705 }
4706
4707 /* mul - mul. */
4708 static void gen_mul(DisasContext *ctx)
4709 {
4710 TCGv_i64 t0 = tcg_temp_new_i64();
4711 TCGv_i64 t1 = tcg_temp_new_i64();
4712 TCGv t2 = tcg_temp_new();
4713 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4714 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4715 tcg_gen_mul_i64(t0, t0, t1);
4716 tcg_gen_trunc_i64_tl(t2, t0);
4717 gen_store_spr(SPR_MQ, t2);
4718 tcg_gen_shri_i64(t1, t0, 32);
4719 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4720 tcg_temp_free_i64(t0);
4721 tcg_temp_free_i64(t1);
4722 tcg_temp_free(t2);
4723 if (unlikely(Rc(ctx->opcode) != 0))
4724 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4725 }
4726
4727 /* mulo - mulo. */
4728 static void gen_mulo(DisasContext *ctx)
4729 {
4730 int l1 = gen_new_label();
4731 TCGv_i64 t0 = tcg_temp_new_i64();
4732 TCGv_i64 t1 = tcg_temp_new_i64();
4733 TCGv t2 = tcg_temp_new();
4734 /* Start with XER OV disabled, the most likely case */
4735 tcg_gen_movi_tl(cpu_ov, 0);
4736 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4737 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4738 tcg_gen_mul_i64(t0, t0, t1);
4739 tcg_gen_trunc_i64_tl(t2, t0);
4740 gen_store_spr(SPR_MQ, t2);
4741 tcg_gen_shri_i64(t1, t0, 32);
4742 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4743 tcg_gen_ext32s_i64(t1, t0);
4744 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4745 tcg_gen_movi_tl(cpu_ov, 1);
4746 tcg_gen_movi_tl(cpu_so, 1);
4747 gen_set_label(l1);
4748 tcg_temp_free_i64(t0);
4749 tcg_temp_free_i64(t1);
4750 tcg_temp_free(t2);
4751 if (unlikely(Rc(ctx->opcode) != 0))
4752 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4753 }
4754
4755 /* nabs - nabs. */
4756 static void gen_nabs(DisasContext *ctx)
4757 {
4758 int l1 = gen_new_label();
4759 int l2 = gen_new_label();
4760 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4761 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4762 tcg_gen_br(l2);
4763 gen_set_label(l1);
4764 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4765 gen_set_label(l2);
4766 if (unlikely(Rc(ctx->opcode) != 0))
4767 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4768 }
4769
4770 /* nabso - nabso. */
4771 static void gen_nabso(DisasContext *ctx)
4772 {
4773 int l1 = gen_new_label();
4774 int l2 = gen_new_label();
4775 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4776 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4777 tcg_gen_br(l2);
4778 gen_set_label(l1);
4779 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4780 gen_set_label(l2);
4781 /* nabs never overflows */
4782 tcg_gen_movi_tl(cpu_ov, 0);
4783 if (unlikely(Rc(ctx->opcode) != 0))
4784 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4785 }
4786
4787 /* rlmi - rlmi. */
4788 static void gen_rlmi(DisasContext *ctx)
4789 {
4790 uint32_t mb = MB(ctx->opcode);
4791 uint32_t me = ME(ctx->opcode);
4792 TCGv t0 = tcg_temp_new();
4793 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4794 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4795 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4796 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4797 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4798 tcg_temp_free(t0);
4799 if (unlikely(Rc(ctx->opcode) != 0))
4800 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4801 }
4802
4803 /* rrib - rrib. */
4804 static void gen_rrib(DisasContext *ctx)
4805 {
4806 TCGv t0 = tcg_temp_new();
4807 TCGv t1 = tcg_temp_new();
4808 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4809 tcg_gen_movi_tl(t1, 0x80000000);
4810 tcg_gen_shr_tl(t1, t1, t0);
4811 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4812 tcg_gen_and_tl(t0, t0, t1);
4813 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4814 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4815 tcg_temp_free(t0);
4816 tcg_temp_free(t1);
4817 if (unlikely(Rc(ctx->opcode) != 0))
4818 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4819 }
4820
4821 /* sle - sle. */
4822 static void gen_sle(DisasContext *ctx)
4823 {
4824 TCGv t0 = tcg_temp_new();
4825 TCGv t1 = tcg_temp_new();
4826 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4827 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4828 tcg_gen_subfi_tl(t1, 32, t1);
4829 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4830 tcg_gen_or_tl(t1, t0, t1);
4831 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4832 gen_store_spr(SPR_MQ, t1);
4833 tcg_temp_free(t0);
4834 tcg_temp_free(t1);
4835 if (unlikely(Rc(ctx->opcode) != 0))
4836 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4837 }
4838
4839 /* sleq - sleq. */
4840 static void gen_sleq(DisasContext *ctx)
4841 {
4842 TCGv t0 = tcg_temp_new();
4843 TCGv t1 = tcg_temp_new();
4844 TCGv t2 = tcg_temp_new();
4845 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4846 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4847 tcg_gen_shl_tl(t2, t2, t0);
4848 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4849 gen_load_spr(t1, SPR_MQ);
4850 gen_store_spr(SPR_MQ, t0);
4851 tcg_gen_and_tl(t0, t0, t2);
4852 tcg_gen_andc_tl(t1, t1, t2);
4853 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4854 tcg_temp_free(t0);
4855 tcg_temp_free(t1);
4856 tcg_temp_free(t2);
4857 if (unlikely(Rc(ctx->opcode) != 0))
4858 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4859 }
4860
4861 /* sliq - sliq. */
4862 static void gen_sliq(DisasContext *ctx)
4863 {
4864 int sh = SH(ctx->opcode);
4865 TCGv t0 = tcg_temp_new();
4866 TCGv t1 = tcg_temp_new();
4867 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4868 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4869 tcg_gen_or_tl(t1, t0, t1);
4870 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4871 gen_store_spr(SPR_MQ, t1);
4872 tcg_temp_free(t0);
4873 tcg_temp_free(t1);
4874 if (unlikely(Rc(ctx->opcode) != 0))
4875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4876 }
4877
4878 /* slliq - slliq. */
4879 static void gen_slliq(DisasContext *ctx)
4880 {
4881 int sh = SH(ctx->opcode);
4882 TCGv t0 = tcg_temp_new();
4883 TCGv t1 = tcg_temp_new();
4884 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4885 gen_load_spr(t1, SPR_MQ);
4886 gen_store_spr(SPR_MQ, t0);
4887 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4888 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4889 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4890 tcg_temp_free(t0);
4891 tcg_temp_free(t1);
4892 if (unlikely(Rc(ctx->opcode) != 0))
4893 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4894 }
4895
4896 /* sllq - sllq. */
4897 static void gen_sllq(DisasContext *ctx)
4898 {
4899 int l1 = gen_new_label();
4900 int l2 = gen_new_label();
4901 TCGv t0 = tcg_temp_local_new();
4902 TCGv t1 = tcg_temp_local_new();
4903 TCGv t2 = tcg_temp_local_new();
4904 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4905 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4906 tcg_gen_shl_tl(t1, t1, t2);
4907 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4908 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4909 gen_load_spr(t0, SPR_MQ);
4910 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4911 tcg_gen_br(l2);
4912 gen_set_label(l1);
4913 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4914 gen_load_spr(t2, SPR_MQ);
4915 tcg_gen_andc_tl(t1, t2, t1);
4916 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4917 gen_set_label(l2);
4918 tcg_temp_free(t0);
4919 tcg_temp_free(t1);
4920 tcg_temp_free(t2);
4921 if (unlikely(Rc(ctx->opcode) != 0))
4922 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4923 }
4924
4925 /* slq - slq. */
4926 static void gen_slq(DisasContext *ctx)
4927 {
4928 int l1 = gen_new_label();
4929 TCGv t0 = tcg_temp_new();
4930 TCGv t1 = tcg_temp_new();
4931 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4932 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4933 tcg_gen_subfi_tl(t1, 32, t1);
4934 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4935 tcg_gen_or_tl(t1, t0, t1);
4936 gen_store_spr(SPR_MQ, t1);
4937 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4938 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4939 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4940 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4941 gen_set_label(l1);
4942 tcg_temp_free(t0);
4943 tcg_temp_free(t1);
4944 if (unlikely(Rc(ctx->opcode) != 0))
4945 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4946 }
4947
4948 /* sraiq - sraiq. */
4949 static void gen_sraiq(DisasContext *ctx)
4950 {
4951 int sh = SH(ctx->opcode);
4952 int l1 = gen_new_label();
4953 TCGv t0 = tcg_temp_new();
4954 TCGv t1 = tcg_temp_new();
4955 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4956 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4957 tcg_gen_or_tl(t0, t0, t1);
4958 gen_store_spr(SPR_MQ, t0);
4959 tcg_gen_movi_tl(cpu_ca, 0);
4960 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4961 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4962 tcg_gen_movi_tl(cpu_ca, 1);
4963 gen_set_label(l1);
4964 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4965 tcg_temp_free(t0);
4966 tcg_temp_free(t1);
4967 if (unlikely(Rc(ctx->opcode) != 0))
4968 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4969 }
4970
4971 /* sraq - sraq. */
4972 static void gen_sraq(DisasContext *ctx)
4973 {
4974 int l1 = gen_new_label();
4975 int l2 = gen_new_label();
4976 TCGv t0 = tcg_temp_new();
4977 TCGv t1 = tcg_temp_local_new();
4978 TCGv t2 = tcg_temp_local_new();
4979 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4980 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4981 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4982 tcg_gen_subfi_tl(t2, 32, t2);
4983 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4984 tcg_gen_or_tl(t0, t0, t2);
4985 gen_store_spr(SPR_MQ, t0);
4986 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4987 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4988 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4989 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4990 gen_set_label(l1);
4991 tcg_temp_free(t0);
4992 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4993 tcg_gen_movi_tl(cpu_ca, 0);
4994 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4995 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4996 tcg_gen_movi_tl(cpu_ca, 1);
4997 gen_set_label(l2);
4998 tcg_temp_free(t1);
4999 tcg_temp_free(t2);
5000 if (unlikely(Rc(ctx->opcode) != 0))
5001 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5002 }
5003
5004 /* sre - sre. */
5005 static void gen_sre(DisasContext *ctx)
5006 {
5007 TCGv t0 = tcg_temp_new();
5008 TCGv t1 = tcg_temp_new();
5009 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5010 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5011 tcg_gen_subfi_tl(t1, 32, t1);
5012 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5013 tcg_gen_or_tl(t1, t0, t1);
5014 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5015 gen_store_spr(SPR_MQ, t1);
5016 tcg_temp_free(t0);
5017 tcg_temp_free(t1);
5018 if (unlikely(Rc(ctx->opcode) != 0))
5019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5020 }
5021
5022 /* srea - srea. */
5023 static void gen_srea(DisasContext *ctx)
5024 {
5025 TCGv t0 = tcg_temp_new();
5026 TCGv t1 = tcg_temp_new();
5027 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5028 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5029 gen_store_spr(SPR_MQ, t0);
5030 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5031 tcg_temp_free(t0);
5032 tcg_temp_free(t1);
5033 if (unlikely(Rc(ctx->opcode) != 0))
5034 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5035 }
5036
5037 /* sreq */
5038 static void gen_sreq(DisasContext *ctx)
5039 {
5040 TCGv t0 = tcg_temp_new();
5041 TCGv t1 = tcg_temp_new();
5042 TCGv t2 = tcg_temp_new();
5043 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5044 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5045 tcg_gen_shr_tl(t1, t1, t0);
5046 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5047 gen_load_spr(t2, SPR_MQ);
5048 gen_store_spr(SPR_MQ, t0);
5049 tcg_gen_and_tl(t0, t0, t1);
5050 tcg_gen_andc_tl(t2, t2, t1);
5051 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5052 tcg_temp_free(t0);
5053 tcg_temp_free(t1);
5054 tcg_temp_free(t2);
5055 if (unlikely(Rc(ctx->opcode) != 0))
5056 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5057 }
5058
5059 /* sriq */
5060 static void gen_sriq(DisasContext *ctx)
5061 {
5062 int sh = SH(ctx->opcode);
5063 TCGv t0 = tcg_temp_new();
5064 TCGv t1 = tcg_temp_new();
5065 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5066 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5067 tcg_gen_or_tl(t1, t0, t1);
5068 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5069 gen_store_spr(SPR_MQ, t1);
5070 tcg_temp_free(t0);
5071 tcg_temp_free(t1);
5072 if (unlikely(Rc(ctx->opcode) != 0))
5073 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5074 }
5075
5076 /* srliq */
5077 static void gen_srliq(DisasContext *ctx)
5078 {
5079 int sh = SH(ctx->opcode);
5080 TCGv t0 = tcg_temp_new();
5081 TCGv t1 = tcg_temp_new();
5082 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5083 gen_load_spr(t1, SPR_MQ);
5084 gen_store_spr(SPR_MQ, t0);
5085 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5086 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5087 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5088 tcg_temp_free(t0);
5089 tcg_temp_free(t1);
5090 if (unlikely(Rc(ctx->opcode) != 0))
5091 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5092 }
5093
5094 /* srlq */
5095 static void gen_srlq(DisasContext *ctx)
5096 {
5097 int l1 = gen_new_label();
5098 int l2 = gen_new_label();
5099 TCGv t0 = tcg_temp_local_new();
5100 TCGv t1 = tcg_temp_local_new();
5101 TCGv t2 = tcg_temp_local_new();
5102 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5103 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5104 tcg_gen_shr_tl(t2, t1, t2);
5105 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5106 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5107 gen_load_spr(t0, SPR_MQ);
5108 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5109 tcg_gen_br(l2);
5110 gen_set_label(l1);
5111 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5112 tcg_gen_and_tl(t0, t0, t2);
5113 gen_load_spr(t1, SPR_MQ);
5114 tcg_gen_andc_tl(t1, t1, t2);
5115 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5116 gen_set_label(l2);
5117 tcg_temp_free(t0);
5118 tcg_temp_free(t1);
5119 tcg_temp_free(t2);
5120 if (unlikely(Rc(ctx->opcode) != 0))
5121 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5122 }
5123
5124 /* srq */
5125 static void gen_srq(DisasContext *ctx)
5126 {
5127 int l1 = gen_new_label();
5128 TCGv t0 = tcg_temp_new();
5129 TCGv t1 = tcg_temp_new();
5130 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5131 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5132 tcg_gen_subfi_tl(t1, 32, t1);
5133 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5134 tcg_gen_or_tl(t1, t0, t1);
5135 gen_store_spr(SPR_MQ, t1);
5136 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5137 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5138 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5139 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5140 gen_set_label(l1);
5141 tcg_temp_free(t0);
5142 tcg_temp_free(t1);
5143 if (unlikely(Rc(ctx->opcode) != 0))
5144 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5145 }
5146
5147 /* PowerPC 602 specific instructions */
5148
5149 /* dsa */
5150 static void gen_dsa(DisasContext *ctx)
5151 {
5152 /* XXX: TODO */
5153 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5154 }
5155
5156 /* esa */
5157 static void gen_esa(DisasContext *ctx)
5158 {
5159 /* XXX: TODO */
5160 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5161 }
5162
5163 /* mfrom */
5164 static void gen_mfrom(DisasContext *ctx)
5165 {
5166 #if defined(CONFIG_USER_ONLY)
5167 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5168 #else
5169 if (unlikely(!ctx->mem_idx)) {
5170 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5171 return;
5172 }
5173 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5174 #endif
5175 }
5176
5177 /* 602 - 603 - G2 TLB management */
5178
5179 /* tlbld */
5180 static void gen_tlbld_6xx(DisasContext *ctx)
5181 {
5182 #if defined(CONFIG_USER_ONLY)
5183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5184 #else
5185 if (unlikely(!ctx->mem_idx)) {
5186 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5187 return;
5188 }
5189 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5190 #endif
5191 }
5192
5193 /* tlbli */
5194 static void gen_tlbli_6xx(DisasContext *ctx)
5195 {
5196 #if defined(CONFIG_USER_ONLY)
5197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5198 #else
5199 if (unlikely(!ctx->mem_idx)) {
5200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5201 return;
5202 }
5203 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5204 #endif
5205 }
5206
5207 /* 74xx TLB management */
5208
5209 /* tlbld */
5210 static void gen_tlbld_74xx(DisasContext *ctx)
5211 {
5212 #if defined(CONFIG_USER_ONLY)
5213 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5214 #else
5215 if (unlikely(!ctx->mem_idx)) {
5216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5217 return;
5218 }
5219 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5220 #endif
5221 }
5222
5223 /* tlbli */
5224 static void gen_tlbli_74xx(DisasContext *ctx)
5225 {
5226 #if defined(CONFIG_USER_ONLY)
5227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5228 #else
5229 if (unlikely(!ctx->mem_idx)) {
5230 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5231 return;
5232 }
5233 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5234 #endif
5235 }
5236
5237 /* POWER instructions not in PowerPC 601 */
5238
5239 /* clf */
5240 static void gen_clf(DisasContext *ctx)
5241 {
5242 /* Cache line flush: implemented as no-op */
5243 }
5244
5245 /* cli */
5246 static void gen_cli(DisasContext *ctx)
5247 {
5248 /* Cache line invalidate: privileged and treated as no-op */
5249 #if defined(CONFIG_USER_ONLY)
5250 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5251 #else
5252 if (unlikely(!ctx->mem_idx)) {
5253 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5254 return;
5255 }
5256 #endif
5257 }
5258
5259 /* dclst */
5260 static void gen_dclst(DisasContext *ctx)
5261 {
5262 /* Data cache line store: treated as no-op */
5263 }
5264
5265 static void gen_mfsri(DisasContext *ctx)
5266 {
5267 #if defined(CONFIG_USER_ONLY)
5268 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5269 #else
5270 int ra = rA(ctx->opcode);
5271 int rd = rD(ctx->opcode);
5272 TCGv t0;
5273 if (unlikely(!ctx->mem_idx)) {
5274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5275 return;
5276 }
5277 t0 = tcg_temp_new();
5278 gen_addr_reg_index(ctx, t0);
5279 tcg_gen_shri_tl(t0, t0, 28);
5280 tcg_gen_andi_tl(t0, t0, 0xF);
5281 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5282 tcg_temp_free(t0);
5283 if (ra != 0 && ra != rd)
5284 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5285 #endif
5286 }
5287
5288 static void gen_rac(DisasContext *ctx)
5289 {
5290 #if defined(CONFIG_USER_ONLY)
5291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5292 #else
5293 TCGv t0;
5294 if (unlikely(!ctx->mem_idx)) {
5295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5296 return;
5297 }
5298 t0 = tcg_temp_new();
5299 gen_addr_reg_index(ctx, t0);
5300 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5301 tcg_temp_free(t0);
5302 #endif
5303 }
5304
5305 static void gen_rfsvc(DisasContext *ctx)
5306 {
5307 #if defined(CONFIG_USER_ONLY)
5308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5309 #else
5310 if (unlikely(!ctx->mem_idx)) {
5311 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5312 return;
5313 }
5314 gen_helper_rfsvc(cpu_env);
5315 gen_sync_exception(ctx);
5316 #endif
5317 }
5318
5319 /* svc is not implemented for now */
5320
5321 /* POWER2 specific instructions */
5322 /* Quad manipulation (load/store two floats at a time) */
5323
5324 /* lfq */
5325 static void gen_lfq(DisasContext *ctx)
5326 {
5327 int rd = rD(ctx->opcode);
5328 TCGv t0;
5329 gen_set_access_type(ctx, ACCESS_FLOAT);
5330 t0 = tcg_temp_new();
5331 gen_addr_imm_index(ctx, t0, 0);
5332 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5333 gen_addr_add(ctx, t0, t0, 8);
5334 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5335 tcg_temp_free(t0);
5336 }
5337
5338 /* lfqu */
5339 static void gen_lfqu(DisasContext *ctx)
5340 {
5341 int ra = rA(ctx->opcode);
5342 int rd = rD(ctx->opcode);
5343 TCGv t0, t1;
5344 gen_set_access_type(ctx, ACCESS_FLOAT);
5345 t0 = tcg_temp_new();
5346 t1 = tcg_temp_new();
5347 gen_addr_imm_index(ctx, t0, 0);
5348 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5349 gen_addr_add(ctx, t1, t0, 8);
5350 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5351 if (ra != 0)
5352 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5353 tcg_temp_free(t0);
5354 tcg_temp_free(t1);
5355 }
5356
5357 /* lfqux */
5358 static void gen_lfqux(DisasContext *ctx)
5359 {
5360 int ra = rA(ctx->opcode);
5361 int rd = rD(ctx->opcode);
5362 gen_set_access_type(ctx, ACCESS_FLOAT);
5363 TCGv t0, t1;
5364 t0 = tcg_temp_new();
5365 gen_addr_reg_index(ctx, t0);
5366 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5367 t1 = tcg_temp_new();
5368 gen_addr_add(ctx, t1, t0, 8);
5369 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5370 tcg_temp_free(t1);
5371 if (ra != 0)
5372 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5373 tcg_temp_free(t0);
5374 }
5375
5376 /* lfqx */
5377 static void gen_lfqx(DisasContext *ctx)
5378 {
5379 int rd = rD(ctx->opcode);
5380 TCGv t0;
5381 gen_set_access_type(ctx, ACCESS_FLOAT);
5382 t0 = tcg_temp_new();
5383 gen_addr_reg_index(ctx, t0);
5384 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5385 gen_addr_add(ctx, t0, t0, 8);
5386 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5387 tcg_temp_free(t0);
5388 }
5389
5390 /* stfq */
5391 static void gen_stfq(DisasContext *ctx)
5392 {
5393 int rd = rD(ctx->opcode);
5394 TCGv t0;
5395 gen_set_access_type(ctx, ACCESS_FLOAT);
5396 t0 = tcg_temp_new();
5397 gen_addr_imm_index(ctx, t0, 0);
5398 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5399 gen_addr_add(ctx, t0, t0, 8);
5400 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5401 tcg_temp_free(t0);
5402 }
5403
5404 /* stfqu */
5405 static void gen_stfqu(DisasContext *ctx)
5406 {
5407 int ra = rA(ctx->opcode);
5408 int rd = rD(ctx->opcode);
5409 TCGv t0, t1;
5410 gen_set_access_type(ctx, ACCESS_FLOAT);
5411 t0 = tcg_temp_new();
5412 gen_addr_imm_index(ctx, t0, 0);
5413 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5414 t1 = tcg_temp_new();
5415 gen_addr_add(ctx, t1, t0, 8);
5416 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5417 tcg_temp_free(t1);
5418 if (ra != 0)
5419 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5420 tcg_temp_free(t0);
5421 }
5422
5423 /* stfqux */
5424 static void gen_stfqux(DisasContext *ctx)
5425 {
5426 int ra = rA(ctx->opcode);
5427 int rd = rD(ctx->opcode);
5428 TCGv t0, t1;
5429 gen_set_access_type(ctx, ACCESS_FLOAT);
5430 t0 = tcg_temp_new();
5431 gen_addr_reg_index(ctx, t0);
5432 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5433 t1 = tcg_temp_new();
5434 gen_addr_add(ctx, t1, t0, 8);
5435 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5436 tcg_temp_free(t1);
5437 if (ra != 0)
5438 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5439 tcg_temp_free(t0);
5440 }
5441
5442 /* stfqx */
5443 static void gen_stfqx(DisasContext *ctx)
5444 {
5445 int rd = rD(ctx->opcode);
5446 TCGv t0;
5447 gen_set_access_type(ctx, ACCESS_FLOAT);
5448 t0 = tcg_temp_new();
5449 gen_addr_reg_index(ctx, t0);
5450 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5451 gen_addr_add(ctx, t0, t0, 8);
5452 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5453 tcg_temp_free(t0);
5454 }
5455
5456 /* BookE specific instructions */
5457
5458 /* XXX: not implemented on 440 ? */
5459 static void gen_mfapidi(DisasContext *ctx)
5460 {
5461 /* XXX: TODO */
5462 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5463 }
5464
5465 /* XXX: not implemented on 440 ? */
5466 static void gen_tlbiva(DisasContext *ctx)
5467 {
5468 #if defined(CONFIG_USER_ONLY)
5469 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5470 #else
5471 TCGv t0;
5472 if (unlikely(!ctx->mem_idx)) {
5473 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5474 return;
5475 }
5476 t0 = tcg_temp_new();
5477 gen_addr_reg_index(ctx, t0);
5478 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5479 tcg_temp_free(t0);
5480 #endif
5481 }
5482
5483 /* All 405 MAC instructions are translated here */
5484 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5485 int ra, int rb, int rt, int Rc)
5486 {
5487 TCGv t0, t1;
5488
5489 t0 = tcg_temp_local_new();
5490 t1 = tcg_temp_local_new();
5491
5492 switch (opc3 & 0x0D) {
5493 case 0x05:
5494 /* macchw - macchw. - macchwo - macchwo. */
5495 /* macchws - macchws. - macchwso - macchwso. */
5496 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5497 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5498 /* mulchw - mulchw. */
5499 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5500 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5501 tcg_gen_ext16s_tl(t1, t1);
5502 break;
5503 case 0x04:
5504 /* macchwu - macchwu. - macchwuo - macchwuo. */
5505 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5506 /* mulchwu - mulchwu. */
5507 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5508 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5509 tcg_gen_ext16u_tl(t1, t1);
5510 break;
5511 case 0x01:
5512 /* machhw - machhw. - machhwo - machhwo. */
5513 /* machhws - machhws. - machhwso - machhwso. */
5514 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5515 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5516 /* mulhhw - mulhhw. */
5517 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5518 tcg_gen_ext16s_tl(t0, t0);
5519 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5520 tcg_gen_ext16s_tl(t1, t1);
5521 break;
5522 case 0x00:
5523 /* machhwu - machhwu. - machhwuo - machhwuo. */
5524 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5525 /* mulhhwu - mulhhwu. */
5526 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5527 tcg_gen_ext16u_tl(t0, t0);
5528 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5529 tcg_gen_ext16u_tl(t1, t1);
5530 break;
5531 case 0x0D:
5532 /* maclhw - maclhw. - maclhwo - maclhwo. */
5533 /* maclhws - maclhws. - maclhwso - maclhwso. */
5534 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5535 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5536 /* mullhw - mullhw. */
5537 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5538 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5539 break;
5540 case 0x0C:
5541 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5542 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5543 /* mullhwu - mullhwu. */
5544 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5545 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5546 break;
5547 }
5548 if (opc2 & 0x04) {
5549 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5550 tcg_gen_mul_tl(t1, t0, t1);
5551 if (opc2 & 0x02) {
5552 /* nmultiply-and-accumulate (0x0E) */
5553 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5554 } else {
5555 /* multiply-and-accumulate (0x0C) */
5556 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5557 }
5558
5559 if (opc3 & 0x12) {
5560 /* Check overflow and/or saturate */
5561 int l1 = gen_new_label();
5562
5563 if (opc3 & 0x10) {
5564 /* Start with XER OV disabled, the most likely case */
5565 tcg_gen_movi_tl(cpu_ov, 0);
5566 }
5567 if (opc3 & 0x01) {
5568 /* Signed */
5569 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5570 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5571 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5572 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5573 if (opc3 & 0x02) {
5574 /* Saturate */
5575 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5576 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5577 }
5578 } else {
5579 /* Unsigned */
5580 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5581 if (opc3 & 0x02) {
5582 /* Saturate */
5583 tcg_gen_movi_tl(t0, UINT32_MAX);
5584 }
5585 }
5586 if (opc3 & 0x10) {
5587 /* Check overflow */
5588 tcg_gen_movi_tl(cpu_ov, 1);
5589 tcg_gen_movi_tl(cpu_so, 1);
5590 }
5591 gen_set_label(l1);
5592 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5593 }
5594 } else {
5595 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5596 }
5597 tcg_temp_free(t0);
5598 tcg_temp_free(t1);
5599 if (unlikely(Rc) != 0) {
5600 /* Update Rc0 */
5601 gen_set_Rc0(ctx, cpu_gpr[rt]);
5602 }
5603 }
5604
5605 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5606 static void glue(gen_, name)(DisasContext *ctx) \
5607 { \
5608 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5609 rD(ctx->opcode), Rc(ctx->opcode)); \
5610 }
5611
5612 /* macchw - macchw. */
5613 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5614 /* macchwo - macchwo. */
5615 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5616 /* macchws - macchws. */
5617 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5618 /* macchwso - macchwso. */
5619 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5620 /* macchwsu - macchwsu. */
5621 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5622 /* macchwsuo - macchwsuo. */
5623 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5624 /* macchwu - macchwu. */
5625 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5626 /* macchwuo - macchwuo. */
5627 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5628 /* machhw - machhw. */
5629 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5630 /* machhwo - machhwo. */
5631 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5632 /* machhws - machhws. */
5633 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5634 /* machhwso - machhwso. */
5635 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5636 /* machhwsu - machhwsu. */
5637 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5638 /* machhwsuo - machhwsuo. */
5639 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5640 /* machhwu - machhwu. */
5641 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5642 /* machhwuo - machhwuo. */
5643 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5644 /* maclhw - maclhw. */
5645 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5646 /* maclhwo - maclhwo. */
5647 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5648 /* maclhws - maclhws. */
5649 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5650 /* maclhwso - maclhwso. */
5651 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5652 /* maclhwu - maclhwu. */
5653 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5654 /* maclhwuo - maclhwuo. */
5655 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5656 /* maclhwsu - maclhwsu. */
5657 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5658 /* maclhwsuo - maclhwsuo. */
5659 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5660 /* nmacchw - nmacchw. */
5661 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5662 /* nmacchwo - nmacchwo. */
5663 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5664 /* nmacchws - nmacchws. */
5665 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5666 /* nmacchwso - nmacchwso. */
5667 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5668 /* nmachhw - nmachhw. */
5669 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5670 /* nmachhwo - nmachhwo. */
5671 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5672 /* nmachhws - nmachhws. */
5673 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5674 /* nmachhwso - nmachhwso. */
5675 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5676 /* nmaclhw - nmaclhw. */
5677 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5678 /* nmaclhwo - nmaclhwo. */
5679 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5680 /* nmaclhws - nmaclhws. */
5681 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5682 /* nmaclhwso - nmaclhwso. */
5683 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5684
5685 /* mulchw - mulchw. */
5686 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5687 /* mulchwu - mulchwu. */
5688 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5689 /* mulhhw - mulhhw. */
5690 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5691 /* mulhhwu - mulhhwu. */
5692 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5693 /* mullhw - mullhw. */
5694 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5695 /* mullhwu - mullhwu. */
5696 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5697
5698 /* mfdcr */
5699 static void gen_mfdcr(DisasContext *ctx)
5700 {
5701 #if defined(CONFIG_USER_ONLY)
5702 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5703 #else
5704 TCGv dcrn;
5705 if (unlikely(!ctx->mem_idx)) {
5706 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5707 return;
5708 }
5709 /* NIP cannot be restored if the memory exception comes from an helper */
5710 gen_update_nip(ctx, ctx->nip - 4);
5711 dcrn = tcg_const_tl(SPR(ctx->opcode));
5712 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5713 tcg_temp_free(dcrn);
5714 #endif
5715 }
5716
5717 /* mtdcr */
5718 static void gen_mtdcr(DisasContext *ctx)
5719 {
5720 #if defined(CONFIG_USER_ONLY)
5721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5722 #else
5723 TCGv dcrn;
5724 if (unlikely(!ctx->mem_idx)) {
5725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5726 return;
5727 }
5728 /* NIP cannot be restored if the memory exception comes from an helper */
5729 gen_update_nip(ctx, ctx->nip - 4);
5730 dcrn = tcg_const_tl(SPR(ctx->opcode));
5731 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5732 tcg_temp_free(dcrn);
5733 #endif
5734 }
5735
5736 /* mfdcrx */
5737 /* XXX: not implemented on 440 ? */
5738 static void gen_mfdcrx(DisasContext *ctx)
5739 {
5740 #if defined(CONFIG_USER_ONLY)
5741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5742 #else
5743 if (unlikely(!ctx->mem_idx)) {
5744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5745 return;
5746 }
5747 /* NIP cannot be restored if the memory exception comes from an helper */
5748 gen_update_nip(ctx, ctx->nip - 4);
5749 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5750 cpu_gpr[rA(ctx->opcode)]);
5751 /* Note: Rc update flag set leads to undefined state of Rc0 */
5752 #endif
5753 }
5754
5755 /* mtdcrx */
5756 /* XXX: not implemented on 440 ? */
5757 static void gen_mtdcrx(DisasContext *ctx)
5758 {
5759 #if defined(CONFIG_USER_ONLY)
5760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5761 #else
5762 if (unlikely(!ctx->mem_idx)) {
5763 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5764 return;
5765 }
5766 /* NIP cannot be restored if the memory exception comes from an helper */
5767 gen_update_nip(ctx, ctx->nip - 4);
5768 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5769 cpu_gpr[rS(ctx->opcode)]);
5770 /* Note: Rc update flag set leads to undefined state of Rc0 */
5771 #endif
5772 }
5773
5774 /* mfdcrux (PPC 460) : user-mode access to DCR */
5775 static void gen_mfdcrux(DisasContext *ctx)
5776 {
5777 /* NIP cannot be restored if the memory exception comes from an helper */
5778 gen_update_nip(ctx, ctx->nip - 4);
5779 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5780 cpu_gpr[rA(ctx->opcode)]);
5781 /* Note: Rc update flag set leads to undefined state of Rc0 */
5782 }
5783
5784 /* mtdcrux (PPC 460) : user-mode access to DCR */
5785 static void gen_mtdcrux(DisasContext *ctx)
5786 {
5787 /* NIP cannot be restored if the memory exception comes from an helper */
5788 gen_update_nip(ctx, ctx->nip - 4);
5789 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5790 cpu_gpr[rS(ctx->opcode)]);
5791 /* Note: Rc update flag set leads to undefined state of Rc0 */
5792 }
5793
5794 /* dccci */
5795 static void gen_dccci(DisasContext *ctx)
5796 {
5797 #if defined(CONFIG_USER_ONLY)
5798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5799 #else
5800 if (unlikely(!ctx->mem_idx)) {
5801 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5802 return;
5803 }
5804 /* interpreted as no-op */
5805 #endif
5806 }
5807
5808 /* dcread */
5809 static void gen_dcread(DisasContext *ctx)
5810 {
5811 #if defined(CONFIG_USER_ONLY)
5812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5813 #else
5814 TCGv EA, val;
5815 if (unlikely(!ctx->mem_idx)) {
5816 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5817 return;
5818 }
5819 gen_set_access_type(ctx, ACCESS_CACHE);
5820 EA = tcg_temp_new();
5821 gen_addr_reg_index(ctx, EA);
5822 val = tcg_temp_new();
5823 gen_qemu_ld32u(ctx, val, EA);
5824 tcg_temp_free(val);
5825 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5826 tcg_temp_free(EA);
5827 #endif
5828 }
5829
5830 /* icbt */
5831 static void gen_icbt_40x(DisasContext *ctx)
5832 {
5833 /* interpreted as no-op */
5834 /* XXX: specification say this is treated as a load by the MMU
5835 * but does not generate any exception
5836 */
5837 }
5838
5839 /* iccci */
5840 static void gen_iccci(DisasContext *ctx)
5841 {
5842 #if defined(CONFIG_USER_ONLY)
5843 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5844 #else
5845 if (unlikely(!ctx->mem_idx)) {
5846 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5847 return;
5848 }
5849 /* interpreted as no-op */
5850 #endif
5851 }
5852
5853 /* icread */
5854 static void gen_icread(DisasContext *ctx)
5855 {
5856 #if defined(CONFIG_USER_ONLY)
5857 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5858 #else
5859 if (unlikely(!ctx->mem_idx)) {
5860 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5861 return;
5862 }
5863 /* interpreted as no-op */
5864 #endif
5865 }
5866
5867 /* rfci (mem_idx only) */
5868 static void gen_rfci_40x(DisasContext *ctx)
5869 {
5870 #if defined(CONFIG_USER_ONLY)
5871 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5872 #else
5873 if (unlikely(!ctx->mem_idx)) {
5874 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5875 return;
5876 }
5877 /* Restore CPU state */
5878 gen_helper_40x_rfci(cpu_env);
5879 gen_sync_exception(ctx);
5880 #endif
5881 }
5882
5883 static void gen_rfci(DisasContext *ctx)
5884 {
5885 #if defined(CONFIG_USER_ONLY)
5886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5887 #else
5888 if (unlikely(!ctx->mem_idx)) {
5889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5890 return;
5891 }
5892 /* Restore CPU state */
5893 gen_helper_rfci(cpu_env);
5894 gen_sync_exception(ctx);
5895 #endif
5896 }
5897
5898 /* BookE specific */
5899
5900 /* XXX: not implemented on 440 ? */
5901 static void gen_rfdi(DisasContext *ctx)
5902 {
5903 #if defined(CONFIG_USER_ONLY)
5904 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5905 #else
5906 if (unlikely(!ctx->mem_idx)) {
5907 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5908 return;
5909 }
5910 /* Restore CPU state */
5911 gen_helper_rfdi(cpu_env);
5912 gen_sync_exception(ctx);
5913 #endif
5914 }
5915
5916 /* XXX: not implemented on 440 ? */
5917 static void gen_rfmci(DisasContext *ctx)
5918 {
5919 #if defined(CONFIG_USER_ONLY)
5920 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5921 #else
5922 if (unlikely(!ctx->mem_idx)) {
5923 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5924 return;
5925 }
5926 /* Restore CPU state */
5927 gen_helper_rfmci(cpu_env);
5928 gen_sync_exception(ctx);
5929 #endif
5930 }
5931
5932 /* TLB management - PowerPC 405 implementation */
5933
5934 /* tlbre */
5935 static void gen_tlbre_40x(DisasContext *ctx)
5936 {
5937 #if defined(CONFIG_USER_ONLY)
5938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5939 #else
5940 if (unlikely(!ctx->mem_idx)) {
5941 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5942 return;
5943 }
5944 switch (rB(ctx->opcode)) {
5945 case 0:
5946 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5947 cpu_gpr[rA(ctx->opcode)]);
5948 break;
5949 case 1:
5950 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5951 cpu_gpr[rA(ctx->opcode)]);
5952 break;
5953 default:
5954 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5955 break;
5956 }
5957 #endif
5958 }
5959
5960 /* tlbsx - tlbsx. */
5961 static void gen_tlbsx_40x(DisasContext *ctx)
5962 {
5963 #if defined(CONFIG_USER_ONLY)
5964 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5965 #else
5966 TCGv t0;
5967 if (unlikely(!ctx->mem_idx)) {
5968 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5969 return;
5970 }
5971 t0 = tcg_temp_new();
5972 gen_addr_reg_index(ctx, t0);
5973 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5974 tcg_temp_free(t0);
5975 if (Rc(ctx->opcode)) {
5976 int l1 = gen_new_label();
5977 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5978 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5979 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5980 gen_set_label(l1);
5981 }
5982 #endif
5983 }
5984
5985 /* tlbwe */
5986 static void gen_tlbwe_40x(DisasContext *ctx)
5987 {
5988 #if defined(CONFIG_USER_ONLY)
5989 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5990 #else
5991 if (unlikely(!ctx->mem_idx)) {
5992 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5993 return;
5994 }
5995 switch (rB(ctx->opcode)) {
5996 case 0:
5997 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5998 cpu_gpr[rS(ctx->opcode)]);
5999 break;
6000 case 1:
6001 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6002 cpu_gpr[rS(ctx->opcode)]);
6003 break;
6004 default:
6005 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6006 break;
6007 }
6008 #endif
6009 }
6010
6011 /* TLB management - PowerPC 440 implementation */
6012
6013 /* tlbre */
6014 static void gen_tlbre_440(DisasContext *ctx)
6015 {
6016 #if defined(CONFIG_USER_ONLY)
6017 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6018 #else
6019 if (unlikely(!ctx->mem_idx)) {
6020 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6021 return;
6022 }
6023 switch (rB(ctx->opcode)) {
6024 case 0:
6025 case 1:
6026 case 2:
6027 {
6028 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6029 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6030 t0, cpu_gpr[rA(ctx->opcode)]);
6031 tcg_temp_free_i32(t0);
6032 }
6033 break;
6034 default:
6035 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6036 break;
6037 }
6038 #endif
6039 }
6040
6041 /* tlbsx - tlbsx. */
6042 static void gen_tlbsx_440(DisasContext *ctx)
6043 {
6044 #if defined(CONFIG_USER_ONLY)
6045 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6046 #else
6047 TCGv t0;
6048 if (unlikely(!ctx->mem_idx)) {
6049 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6050 return;
6051 }
6052 t0 = tcg_temp_new();
6053 gen_addr_reg_index(ctx, t0);
6054 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6055 tcg_temp_free(t0);
6056 if (Rc(ctx->opcode)) {
6057 int l1 = gen_new_label();
6058 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6059 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6060 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6061 gen_set_label(l1);
6062 }
6063 #endif
6064 }
6065
6066 /* tlbwe */
6067 static void gen_tlbwe_440(DisasContext *ctx)
6068 {
6069 #if defined(CONFIG_USER_ONLY)
6070 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6071 #else
6072 if (unlikely(!ctx->mem_idx)) {
6073 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6074 return;
6075 }
6076 switch (rB(ctx->opcode)) {
6077 case 0:
6078 case 1:
6079 case 2:
6080 {
6081 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6082 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6083 cpu_gpr[rS(ctx->opcode)]);
6084 tcg_temp_free_i32(t0);
6085 }
6086 break;
6087 default:
6088 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6089 break;
6090 }
6091 #endif
6092 }
6093
6094 /* TLB management - PowerPC BookE 2.06 implementation */
6095
6096 /* tlbre */
6097 static void gen_tlbre_booke206(DisasContext *ctx)
6098 {
6099 #if defined(CONFIG_USER_ONLY)
6100 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6101 #else
6102 if (unlikely(!ctx->mem_idx)) {
6103 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6104 return;
6105 }
6106
6107 gen_helper_booke206_tlbre(cpu_env);
6108 #endif
6109 }
6110
6111 /* tlbsx - tlbsx. */
6112 static void gen_tlbsx_booke206(DisasContext *ctx)
6113 {
6114 #if defined(CONFIG_USER_ONLY)
6115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6116 #else
6117 TCGv t0;
6118 if (unlikely(!ctx->mem_idx)) {
6119 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6120 return;
6121 }
6122
6123 if (rA(ctx->opcode)) {
6124 t0 = tcg_temp_new();
6125 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6126 } else {
6127 t0 = tcg_const_tl(0);
6128 }
6129
6130 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6131 gen_helper_booke206_tlbsx(cpu_env, t0);
6132 #endif
6133 }
6134
6135 /* tlbwe */
6136 static void gen_tlbwe_booke206(DisasContext *ctx)
6137 {
6138 #if defined(CONFIG_USER_ONLY)
6139 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6140 #else
6141 if (unlikely(!ctx->mem_idx)) {
6142 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6143 return;
6144 }
6145 gen_update_nip(ctx, ctx->nip - 4);
6146 gen_helper_booke206_tlbwe(cpu_env);
6147 #endif
6148 }
6149
6150 static void gen_tlbivax_booke206(DisasContext *ctx)
6151 {
6152 #if defined(CONFIG_USER_ONLY)
6153 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6154 #else
6155 TCGv t0;
6156 if (unlikely(!ctx->mem_idx)) {
6157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6158 return;
6159 }
6160
6161 t0 = tcg_temp_new();
6162 gen_addr_reg_index(ctx, t0);
6163
6164 gen_helper_booke206_tlbivax(cpu_env, t0);
6165 #endif
6166 }
6167
6168 static void gen_tlbilx_booke206(DisasContext *ctx)
6169 {
6170 #if defined(CONFIG_USER_ONLY)
6171 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6172 #else
6173 TCGv t0;
6174 if (unlikely(!ctx->mem_idx)) {
6175 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6176 return;
6177 }
6178
6179 t0 = tcg_temp_new();
6180 gen_addr_reg_index(ctx, t0);
6181
6182 switch((ctx->opcode >> 21) & 0x3) {
6183 case 0:
6184 gen_helper_booke206_tlbilx0(cpu_env, t0);
6185 break;
6186 case 1:
6187 gen_helper_booke206_tlbilx1(cpu_env, t0);
6188 break;
6189 case 3:
6190 gen_helper_booke206_tlbilx3(cpu_env, t0);
6191 break;
6192 default:
6193 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6194 break;
6195 }
6196
6197 tcg_temp_free(t0);
6198 #endif
6199 }
6200
6201
6202 /* wrtee */
6203 static void gen_wrtee(DisasContext *ctx)
6204 {
6205 #if defined(CONFIG_USER_ONLY)
6206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6207 #else
6208 TCGv t0;
6209 if (unlikely(!ctx->mem_idx)) {
6210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6211 return;
6212 }
6213 t0 = tcg_temp_new();
6214 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6215 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6216 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6217 tcg_temp_free(t0);
6218 /* Stop translation to have a chance to raise an exception
6219 * if we just set msr_ee to 1
6220 */
6221 gen_stop_exception(ctx);
6222 #endif
6223 }
6224
6225 /* wrteei */
6226 static void gen_wrteei(DisasContext *ctx)
6227 {
6228 #if defined(CONFIG_USER_ONLY)
6229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6230 #else
6231 if (unlikely(!ctx->mem_idx)) {
6232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6233 return;
6234 }
6235 if (ctx->opcode & 0x00008000) {
6236 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6237 /* Stop translation to have a chance to raise an exception */
6238 gen_stop_exception(ctx);
6239 } else {
6240 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6241 }
6242 #endif
6243 }
6244
6245 /* PowerPC 440 specific instructions */
6246
6247 /* dlmzb */
6248 static void gen_dlmzb(DisasContext *ctx)
6249 {
6250 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6251 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6252 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6253 tcg_temp_free_i32(t0);
6254 }
6255
6256 /* mbar replaces eieio on 440 */
6257 static void gen_mbar(DisasContext *ctx)
6258 {
6259 /* interpreted as no-op */
6260 }
6261
6262 /* msync replaces sync on 440 */
6263 static void gen_msync_4xx(DisasContext *ctx)
6264 {
6265 /* interpreted as no-op */
6266 }
6267
6268 /* icbt */
6269 static void gen_icbt_440(DisasContext *ctx)
6270 {
6271 /* interpreted as no-op */
6272 /* XXX: specification say this is treated as a load by the MMU
6273 * but does not generate any exception
6274 */
6275 }
6276
6277 /* Embedded.Processor Control */
6278
6279 static void gen_msgclr(DisasContext *ctx)
6280 {
6281 #if defined(CONFIG_USER_ONLY)
6282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6283 #else
6284 if (unlikely(ctx->mem_idx == 0)) {
6285 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6286 return;
6287 }
6288
6289 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6290 #endif
6291 }
6292
6293 static void gen_msgsnd(DisasContext *ctx)
6294 {
6295 #if defined(CONFIG_USER_ONLY)
6296 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6297 #else
6298 if (unlikely(ctx->mem_idx == 0)) {
6299 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6300 return;
6301 }
6302
6303 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6304 #endif
6305 }
6306
6307 /*** Altivec vector extension ***/
6308 /* Altivec registers moves */
6309
6310 static inline TCGv_ptr gen_avr_ptr(int reg)
6311 {
6312 TCGv_ptr r = tcg_temp_new_ptr();
6313 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6314 return r;
6315 }
6316
6317 #define GEN_VR_LDX(name, opc2, opc3) \
6318 static void glue(gen_, name)(DisasContext *ctx) \
6319 { \
6320 TCGv EA; \
6321 if (unlikely(!ctx->altivec_enabled)) { \
6322 gen_exception(ctx, POWERPC_EXCP_VPU); \
6323 return; \
6324 } \
6325 gen_set_access_type(ctx, ACCESS_INT); \
6326 EA = tcg_temp_new(); \
6327 gen_addr_reg_index(ctx, EA); \
6328 tcg_gen_andi_tl(EA, EA, ~0xf); \
6329 if (ctx->le_mode) { \
6330 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6331 tcg_gen_addi_tl(EA, EA, 8); \
6332 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6333 } else { \
6334 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6335 tcg_gen_addi_tl(EA, EA, 8); \
6336 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6337 } \
6338 tcg_temp_free(EA); \
6339 }
6340
6341 #define GEN_VR_STX(name, opc2, opc3) \
6342 static void gen_st##name(DisasContext *ctx) \
6343 { \
6344 TCGv EA; \
6345 if (unlikely(!ctx->altivec_enabled)) { \
6346 gen_exception(ctx, POWERPC_EXCP_VPU); \
6347 return; \
6348 } \
6349 gen_set_access_type(ctx, ACCESS_INT); \
6350 EA = tcg_temp_new(); \
6351 gen_addr_reg_index(ctx, EA); \
6352 tcg_gen_andi_tl(EA, EA, ~0xf); \
6353 if (ctx->le_mode) { \
6354 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6355 tcg_gen_addi_tl(EA, EA, 8); \
6356 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6357 } else { \
6358 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6359 tcg_gen_addi_tl(EA, EA, 8); \
6360 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6361 } \
6362 tcg_temp_free(EA); \
6363 }
6364
6365 #define GEN_VR_LVE(name, opc2, opc3) \
6366 static void gen_lve##name(DisasContext *ctx) \
6367 { \
6368 TCGv EA; \
6369 TCGv_ptr rs; \
6370 if (unlikely(!ctx->altivec_enabled)) { \
6371 gen_exception(ctx, POWERPC_EXCP_VPU); \
6372 return; \
6373 } \
6374 gen_set_access_type(ctx, ACCESS_INT); \
6375 EA = tcg_temp_new(); \
6376 gen_addr_reg_index(ctx, EA); \
6377 rs = gen_avr_ptr(rS(ctx->opcode)); \
6378 gen_helper_lve##name(cpu_env, rs, EA); \
6379 tcg_temp_free(EA); \
6380 tcg_temp_free_ptr(rs); \
6381 }
6382
6383 #define GEN_VR_STVE(name, opc2, opc3) \
6384 static void gen_stve##name(DisasContext *ctx) \
6385 { \
6386 TCGv EA; \
6387 TCGv_ptr rs; \
6388 if (unlikely(!ctx->altivec_enabled)) { \
6389 gen_exception(ctx, POWERPC_EXCP_VPU); \
6390 return; \
6391 } \
6392 gen_set_access_type(ctx, ACCESS_INT); \
6393 EA = tcg_temp_new(); \
6394 gen_addr_reg_index(ctx, EA); \
6395 rs = gen_avr_ptr(rS(ctx->opcode)); \
6396 gen_helper_stve##name(cpu_env, rs, EA); \
6397 tcg_temp_free(EA); \
6398 tcg_temp_free_ptr(rs); \
6399 }
6400
6401 GEN_VR_LDX(lvx, 0x07, 0x03);
6402 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6403 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6404
6405 GEN_VR_LVE(bx, 0x07, 0x00);
6406 GEN_VR_LVE(hx, 0x07, 0x01);
6407 GEN_VR_LVE(wx, 0x07, 0x02);
6408
6409 GEN_VR_STX(svx, 0x07, 0x07);
6410 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6411 GEN_VR_STX(svxl, 0x07, 0x0F);
6412
6413 GEN_VR_STVE(bx, 0x07, 0x04);
6414 GEN_VR_STVE(hx, 0x07, 0x05);
6415 GEN_VR_STVE(wx, 0x07, 0x06);
6416
6417 static void gen_lvsl(DisasContext *ctx)
6418 {
6419 TCGv_ptr rd;
6420 TCGv EA;
6421 if (unlikely(!ctx->altivec_enabled)) {
6422 gen_exception(ctx, POWERPC_EXCP_VPU);
6423 return;
6424 }
6425 EA = tcg_temp_new();
6426 gen_addr_reg_index(ctx, EA);
6427 rd = gen_avr_ptr(rD(ctx->opcode));
6428 gen_helper_lvsl(rd, EA);
6429 tcg_temp_free(EA);
6430 tcg_temp_free_ptr(rd);
6431 }
6432
6433 static void gen_lvsr(DisasContext *ctx)
6434 {
6435 TCGv_ptr rd;
6436 TCGv EA;
6437 if (unlikely(!ctx->altivec_enabled)) {
6438 gen_exception(ctx, POWERPC_EXCP_VPU);
6439 return;
6440 }
6441 EA = tcg_temp_new();
6442 gen_addr_reg_index(ctx, EA);
6443 rd = gen_avr_ptr(rD(ctx->opcode));
6444 gen_helper_lvsr(rd, EA);
6445 tcg_temp_free(EA);
6446 tcg_temp_free_ptr(rd);
6447 }
6448
6449 static void gen_mfvscr(DisasContext *ctx)
6450 {
6451 TCGv_i32 t;
6452 if (unlikely(!ctx->altivec_enabled)) {
6453 gen_exception(ctx, POWERPC_EXCP_VPU);
6454 return;
6455 }
6456 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6457 t = tcg_temp_new_i32();
6458 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6459 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6460 tcg_temp_free_i32(t);
6461 }
6462
6463 static void gen_mtvscr(DisasContext *ctx)
6464 {
6465 TCGv_ptr p;
6466 if (unlikely(!ctx->altivec_enabled)) {
6467 gen_exception(ctx, POWERPC_EXCP_VPU);
6468 return;
6469 }
6470 p = gen_avr_ptr(rD(ctx->opcode));
6471 gen_helper_mtvscr(cpu_env, p);
6472 tcg_temp_free_ptr(p);
6473 }
6474
6475 /* Logical operations */
6476 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6477 static void glue(gen_, name)(DisasContext *ctx) \
6478 { \
6479 if (unlikely(!ctx->altivec_enabled)) { \
6480 gen_exception(ctx, POWERPC_EXCP_VPU); \
6481 return; \
6482 } \
6483 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6484 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6485 }
6486
6487 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6488 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6489 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6490 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6491 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6492
6493 #define GEN_VXFORM(name, opc2, opc3) \
6494 static void glue(gen_, name)(DisasContext *ctx) \
6495 { \
6496 TCGv_ptr ra, rb, rd; \
6497 if (unlikely(!ctx->altivec_enabled)) { \
6498 gen_exception(ctx, POWERPC_EXCP_VPU); \
6499 return; \
6500 } \
6501 ra = gen_avr_ptr(rA(ctx->opcode)); \
6502 rb = gen_avr_ptr(rB(ctx->opcode)); \
6503 rd = gen_avr_ptr(rD(ctx->opcode)); \
6504 gen_helper_##name (rd, ra, rb); \
6505 tcg_temp_free_ptr(ra); \
6506 tcg_temp_free_ptr(rb); \
6507 tcg_temp_free_ptr(rd); \
6508 }
6509
6510 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6511 static void glue(gen_, name)(DisasContext *ctx) \
6512 { \
6513 TCGv_ptr ra, rb, rd; \
6514 if (unlikely(!ctx->altivec_enabled)) { \
6515 gen_exception(ctx, POWERPC_EXCP_VPU); \
6516 return; \
6517 } \
6518 ra = gen_avr_ptr(rA(ctx->opcode)); \
6519 rb = gen_avr_ptr(rB(ctx->opcode)); \
6520 rd = gen_avr_ptr(rD(ctx->opcode)); \
6521 gen_helper_##name(cpu_env, rd, ra, rb); \
6522 tcg_temp_free_ptr(ra); \
6523 tcg_temp_free_ptr(rb); \
6524 tcg_temp_free_ptr(rd); \
6525 }
6526
6527 GEN_VXFORM(vaddubm, 0, 0);
6528 GEN_VXFORM(vadduhm, 0, 1);
6529 GEN_VXFORM(vadduwm, 0, 2);
6530 GEN_VXFORM(vsububm, 0, 16);
6531 GEN_VXFORM(vsubuhm, 0, 17);
6532 GEN_VXFORM(vsubuwm, 0, 18);
6533 GEN_VXFORM(vmaxub, 1, 0);
6534 GEN_VXFORM(vmaxuh, 1, 1);
6535 GEN_VXFORM(vmaxuw, 1, 2);
6536 GEN_VXFORM(vmaxsb, 1, 4);
6537 GEN_VXFORM(vmaxsh, 1, 5);
6538 GEN_VXFORM(vmaxsw, 1, 6);
6539 GEN_VXFORM(vminub, 1, 8);
6540 GEN_VXFORM(vminuh, 1, 9);
6541 GEN_VXFORM(vminuw, 1, 10);
6542 GEN_VXFORM(vminsb, 1, 12);
6543 GEN_VXFORM(vminsh, 1, 13);
6544 GEN_VXFORM(vminsw, 1, 14);
6545 GEN_VXFORM(vavgub, 1, 16);
6546 GEN_VXFORM(vavguh, 1, 17);
6547 GEN_VXFORM(vavguw, 1, 18);
6548 GEN_VXFORM(vavgsb, 1, 20);
6549 GEN_VXFORM(vavgsh, 1, 21);
6550 GEN_VXFORM(vavgsw, 1, 22);
6551 GEN_VXFORM(vmrghb, 6, 0);
6552 GEN_VXFORM(vmrghh, 6, 1);
6553 GEN_VXFORM(vmrghw, 6, 2);
6554 GEN_VXFORM(vmrglb, 6, 4);
6555 GEN_VXFORM(vmrglh, 6, 5);
6556 GEN_VXFORM(vmrglw, 6, 6);
6557 GEN_VXFORM(vmuloub, 4, 0);
6558 GEN_VXFORM(vmulouh, 4, 1);
6559 GEN_VXFORM(vmulosb, 4, 4);
6560 GEN_VXFORM(vmulosh, 4, 5);
6561 GEN_VXFORM(vmuleub, 4, 8);
6562 GEN_VXFORM(vmuleuh, 4, 9);
6563 GEN_VXFORM(vmulesb, 4, 12);
6564 GEN_VXFORM(vmulesh, 4, 13);
6565 GEN_VXFORM(vslb, 2, 4);
6566 GEN_VXFORM(vslh, 2, 5);
6567 GEN_VXFORM(vslw, 2, 6);
6568 GEN_VXFORM(vsrb, 2, 8);
6569 GEN_VXFORM(vsrh, 2, 9);
6570 GEN_VXFORM(vsrw, 2, 10);
6571 GEN_VXFORM(vsrab, 2, 12);
6572 GEN_VXFORM(vsrah, 2, 13);
6573 GEN_VXFORM(vsraw, 2, 14);
6574 GEN_VXFORM(vslo, 6, 16);
6575 GEN_VXFORM(vsro, 6, 17);
6576 GEN_VXFORM(vaddcuw, 0, 6);
6577 GEN_VXFORM(vsubcuw, 0, 22);
6578 GEN_VXFORM_ENV(vaddubs, 0, 8);
6579 GEN_VXFORM_ENV(vadduhs, 0, 9);
6580 GEN_VXFORM_ENV(vadduws, 0, 10);
6581 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6582 GEN_VXFORM_ENV(vaddshs, 0, 13);
6583 GEN_VXFORM_ENV(vaddsws, 0, 14);
6584 GEN_VXFORM_ENV(vsububs, 0, 24);
6585 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6586 GEN_VXFORM_ENV(vsubuws, 0, 26);
6587 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6588 GEN_VXFORM_ENV(vsubshs, 0, 29);
6589 GEN_VXFORM_ENV(vsubsws, 0, 30);
6590 GEN_VXFORM(vrlb, 2, 0);
6591 GEN_VXFORM(vrlh, 2, 1);
6592 GEN_VXFORM(vrlw, 2, 2);
6593 GEN_VXFORM(vsl, 2, 7);
6594 GEN_VXFORM(vsr, 2, 11);
6595 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6596 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6597 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6598 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6599 GEN_VXFORM_ENV(vpkshus, 7, 4);
6600 GEN_VXFORM_ENV(vpkswus, 7, 5);
6601 GEN_VXFORM_ENV(vpkshss, 7, 6);
6602 GEN_VXFORM_ENV(vpkswss, 7, 7);
6603 GEN_VXFORM(vpkpx, 7, 12);
6604 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6605 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6606 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6607 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6608 GEN_VXFORM_ENV(vsumsws, 4, 30);
6609 GEN_VXFORM_ENV(vaddfp, 5, 0);
6610 GEN_VXFORM_ENV(vsubfp, 5, 1);
6611 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6612 GEN_VXFORM_ENV(vminfp, 5, 17);
6613
6614 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6615 static void glue(gen_, name)(DisasContext *ctx) \
6616 { \
6617 TCGv_ptr ra, rb, rd; \
6618 if (unlikely(!ctx->altivec_enabled)) { \
6619 gen_exception(ctx, POWERPC_EXCP_VPU); \
6620 return; \
6621 } \
6622 ra = gen_avr_ptr(rA(ctx->opcode)); \
6623 rb = gen_avr_ptr(rB(ctx->opcode)); \
6624 rd = gen_avr_ptr(rD(ctx->opcode)); \
6625 gen_helper_##opname(cpu_env, rd, ra, rb); \
6626 tcg_temp_free_ptr(ra); \
6627 tcg_temp_free_ptr(rb); \
6628 tcg_temp_free_ptr(rd); \
6629 }
6630
6631 #define GEN_VXRFORM(name, opc2, opc3) \
6632 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6633 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6634
6635 GEN_VXRFORM(vcmpequb, 3, 0)
6636 GEN_VXRFORM(vcmpequh, 3, 1)
6637 GEN_VXRFORM(vcmpequw, 3, 2)
6638 GEN_VXRFORM(vcmpgtsb, 3, 12)
6639 GEN_VXRFORM(vcmpgtsh, 3, 13)
6640 GEN_VXRFORM(vcmpgtsw, 3, 14)
6641 GEN_VXRFORM(vcmpgtub, 3, 8)
6642 GEN_VXRFORM(vcmpgtuh, 3, 9)
6643 GEN_VXRFORM(vcmpgtuw, 3, 10)
6644 GEN_VXRFORM(vcmpeqfp, 3, 3)
6645 GEN_VXRFORM(vcmpgefp, 3, 7)
6646 GEN_VXRFORM(vcmpgtfp, 3, 11)
6647 GEN_VXRFORM(vcmpbfp, 3, 15)
6648
6649 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6650 static void glue(gen_, name)(DisasContext *ctx) \
6651 { \
6652 TCGv_ptr rd; \
6653 TCGv_i32 simm; \
6654 if (unlikely(!ctx->altivec_enabled)) { \
6655 gen_exception(ctx, POWERPC_EXCP_VPU); \
6656 return; \
6657 } \
6658 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6659 rd = gen_avr_ptr(rD(ctx->opcode)); \
6660 gen_helper_##name (rd, simm); \
6661 tcg_temp_free_i32(simm); \
6662 tcg_temp_free_ptr(rd); \
6663 }
6664
6665 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6666 GEN_VXFORM_SIMM(vspltish, 6, 13);
6667 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6668
6669 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6670 static void glue(gen_, name)(DisasContext *ctx) \
6671 { \
6672 TCGv_ptr rb, rd; \
6673 if (unlikely(!ctx->altivec_enabled)) { \
6674 gen_exception(ctx, POWERPC_EXCP_VPU); \
6675 return; \
6676 } \
6677 rb = gen_avr_ptr(rB(ctx->opcode)); \
6678 rd = gen_avr_ptr(rD(ctx->opcode)); \
6679 gen_helper_##name (rd, rb); \
6680 tcg_temp_free_ptr(rb); \
6681 tcg_temp_free_ptr(rd); \
6682 }
6683
6684 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6685 static void glue(gen_, name)(DisasContext *ctx) \
6686 { \
6687 TCGv_ptr rb, rd; \
6688 \
6689 if (unlikely(!ctx->altivec_enabled)) { \
6690 gen_exception(ctx, POWERPC_EXCP_VPU); \
6691 return; \
6692 } \
6693 rb = gen_avr_ptr(rB(ctx->opcode)); \
6694 rd = gen_avr_ptr(rD(ctx->opcode)); \
6695 gen_helper_##name(cpu_env, rd, rb); \
6696 tcg_temp_free_ptr(rb); \
6697 tcg_temp_free_ptr(rd); \
6698 }
6699
6700 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6701 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6702 GEN_VXFORM_NOA(vupklsb, 7, 10);
6703 GEN_VXFORM_NOA(vupklsh, 7, 11);
6704 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6705 GEN_VXFORM_NOA(vupklpx, 7, 15);
6706 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6707 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6708 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6709 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6710 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6711 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6712 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6713 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6714
6715 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6716 static void glue(gen_, name)(DisasContext *ctx) \
6717 { \
6718 TCGv_ptr rd; \
6719 TCGv_i32 simm; \
6720 if (unlikely(!ctx->altivec_enabled)) { \
6721 gen_exception(ctx, POWERPC_EXCP_VPU); \
6722 return; \
6723 } \
6724 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6725 rd = gen_avr_ptr(rD(ctx->opcode)); \
6726 gen_helper_##name (rd, simm); \
6727 tcg_temp_free_i32(simm); \
6728 tcg_temp_free_ptr(rd); \
6729 }
6730
6731 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6732 static void glue(gen_, name)(DisasContext *ctx) \
6733 { \
6734 TCGv_ptr rb, rd; \
6735 TCGv_i32 uimm; \
6736 if (unlikely(!ctx->altivec_enabled)) { \
6737 gen_exception(ctx, POWERPC_EXCP_VPU); \
6738 return; \
6739 } \
6740 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6741 rb = gen_avr_ptr(rB(ctx->opcode)); \
6742 rd = gen_avr_ptr(rD(ctx->opcode)); \
6743 gen_helper_##name (rd, rb, uimm); \
6744 tcg_temp_free_i32(uimm); \
6745 tcg_temp_free_ptr(rb); \
6746 tcg_temp_free_ptr(rd); \
6747 }
6748
6749 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6750 static void glue(gen_, name)(DisasContext *ctx) \
6751 { \
6752 TCGv_ptr rb, rd; \
6753 TCGv_i32 uimm; \
6754 \
6755 if (unlikely(!ctx->altivec_enabled)) { \
6756 gen_exception(ctx, POWERPC_EXCP_VPU); \
6757 return; \
6758 } \
6759 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6760 rb = gen_avr_ptr(rB(ctx->opcode)); \
6761 rd = gen_avr_ptr(rD(ctx->opcode)); \
6762 gen_helper_##name(cpu_env, rd, rb, uimm); \
6763 tcg_temp_free_i32(uimm); \
6764 tcg_temp_free_ptr(rb); \
6765 tcg_temp_free_ptr(rd); \
6766 }
6767
6768 GEN_VXFORM_UIMM(vspltb, 6, 8);
6769 GEN_VXFORM_UIMM(vsplth, 6, 9);
6770 GEN_VXFORM_UIMM(vspltw, 6, 10);
6771 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6772 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6773 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6774 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6775
6776 static void gen_vsldoi(DisasContext *ctx)
6777 {
6778 TCGv_ptr ra, rb, rd;
6779 TCGv_i32 sh;
6780 if (unlikely(!ctx->altivec_enabled)) {
6781 gen_exception(ctx, POWERPC_EXCP_VPU);
6782 return;
6783 }
6784 ra = gen_avr_ptr(rA(ctx->opcode));
6785 rb = gen_avr_ptr(rB(ctx->opcode));
6786 rd = gen_avr_ptr(rD(ctx->opcode));
6787 sh = tcg_const_i32(VSH(ctx->opcode));
6788 gen_helper_vsldoi (rd, ra, rb, sh);
6789 tcg_temp_free_ptr(ra);
6790 tcg_temp_free_ptr(rb);
6791 tcg_temp_free_ptr(rd);
6792 tcg_temp_free_i32(sh);
6793 }
6794
6795 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6796 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6797 { \
6798 TCGv_ptr ra, rb, rc, rd; \
6799 if (unlikely(!ctx->altivec_enabled)) { \
6800 gen_exception(ctx, POWERPC_EXCP_VPU); \
6801 return; \
6802 } \
6803 ra = gen_avr_ptr(rA(ctx->opcode)); \
6804 rb = gen_avr_ptr(rB(ctx->opcode)); \
6805 rc = gen_avr_ptr(rC(ctx->opcode)); \
6806 rd = gen_avr_ptr(rD(ctx->opcode)); \
6807 if (Rc(ctx->opcode)) { \
6808 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6809 } else { \
6810 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6811 } \
6812 tcg_temp_free_ptr(ra); \
6813 tcg_temp_free_ptr(rb); \
6814 tcg_temp_free_ptr(rc); \
6815 tcg_temp_free_ptr(rd); \
6816 }
6817
6818 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6819
6820 static void gen_vmladduhm(DisasContext *ctx)
6821 {
6822 TCGv_ptr ra, rb, rc, rd;
6823 if (unlikely(!ctx->altivec_enabled)) {
6824 gen_exception(ctx, POWERPC_EXCP_VPU);
6825 return;
6826 }
6827 ra = gen_avr_ptr(rA(ctx->opcode));
6828 rb = gen_avr_ptr(rB(ctx->opcode));
6829 rc = gen_avr_ptr(rC(ctx->opcode));
6830 rd = gen_avr_ptr(rD(ctx->opcode));
6831 gen_helper_vmladduhm(rd, ra, rb, rc);
6832 tcg_temp_free_ptr(ra);
6833 tcg_temp_free_ptr(rb);
6834 tcg_temp_free_ptr(rc);
6835 tcg_temp_free_ptr(rd);
6836 }
6837
6838 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6839 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6840 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6841 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6842 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6843
6844 /*** SPE extension ***/
6845 /* Register moves */
6846
6847
6848 static inline void gen_evmra(DisasContext *ctx)
6849 {
6850
6851 if (unlikely(!ctx->spe_enabled)) {
6852 gen_exception(ctx, POWERPC_EXCP_SPEU);
6853 return;
6854 }
6855
6856 #if defined(TARGET_PPC64)
6857 /* rD := rA */
6858 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6859
6860 /* spe_acc := rA */
6861 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6862 cpu_env,
6863 offsetof(CPUPPCState, spe_acc));
6864 #else
6865 TCGv_i64 tmp = tcg_temp_new_i64();
6866
6867 /* tmp := rA_lo + rA_hi << 32 */
6868 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6869
6870 /* spe_acc := tmp */
6871 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6872 tcg_temp_free_i64(tmp);
6873
6874 /* rD := rA */
6875 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6876 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6877 #endif
6878 }
6879
6880 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6881 {
6882 #if defined(TARGET_PPC64)
6883 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6884 #else
6885 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6886 #endif
6887 }
6888
6889 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6890 {
6891 #if defined(TARGET_PPC64)
6892 tcg_gen_mov_i64(cpu_gpr[reg], t);
6893 #else
6894 TCGv_i64 tmp = tcg_temp_new_i64();
6895 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6896 tcg_gen_shri_i64(tmp, t, 32);
6897 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6898 tcg_temp_free_i64(tmp);
6899 #endif
6900 }
6901
6902 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6903 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6904 { \
6905 if (Rc(ctx->opcode)) \
6906 gen_##name1(ctx); \
6907 else \
6908 gen_##name0(ctx); \
6909 }
6910
6911 /* Handler for undefined SPE opcodes */
6912 static inline void gen_speundef(DisasContext *ctx)
6913 {
6914 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6915 }
6916
6917 /* SPE logic */
6918 #if defined(TARGET_PPC64)
6919 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6920 static inline void gen_##name(DisasContext *ctx) \
6921 { \
6922 if (unlikely(!ctx->spe_enabled)) { \
6923 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6924 return; \
6925 } \
6926 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6927 cpu_gpr[rB(ctx->opcode)]); \
6928 }
6929 #else
6930 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6931 static inline void gen_##name(DisasContext *ctx) \
6932 { \
6933 if (unlikely(!ctx->spe_enabled)) { \
6934 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6935 return; \
6936 } \
6937 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6938 cpu_gpr[rB(ctx->opcode)]); \
6939 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6940 cpu_gprh[rB(ctx->opcode)]); \
6941 }
6942 #endif
6943
6944 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6945 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6946 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6947 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6948 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6949 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6950 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6951 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6952
6953 /* SPE logic immediate */
6954 #if defined(TARGET_PPC64)
6955 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6956 static inline void gen_##name(DisasContext *ctx) \
6957 { \
6958 if (unlikely(!ctx->spe_enabled)) { \
6959 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6960 return; \
6961 } \
6962 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6963 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6964 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6965 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6966 tcg_opi(t0, t0, rB(ctx->opcode)); \
6967 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6968 tcg_gen_trunc_i64_i32(t1, t2); \
6969 tcg_temp_free_i64(t2); \
6970 tcg_opi(t1, t1, rB(ctx->opcode)); \
6971 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6972 tcg_temp_free_i32(t0); \
6973 tcg_temp_free_i32(t1); \
6974 }
6975 #else
6976 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6977 static inline void gen_##name(DisasContext *ctx) \
6978 { \
6979 if (unlikely(!ctx->spe_enabled)) { \
6980 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6981 return; \
6982 } \
6983 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6984 rB(ctx->opcode)); \
6985 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6986 rB(ctx->opcode)); \
6987 }
6988 #endif
6989 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6990 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6991 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6992 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6993
6994 /* SPE arithmetic */
6995 #if defined(TARGET_PPC64)
6996 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6997 static inline void gen_##name(DisasContext *ctx) \
6998 { \
6999 if (unlikely(!ctx->spe_enabled)) { \
7000 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7001 return; \
7002 } \
7003 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7004 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7005 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7006 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7007 tcg_op(t0, t0); \
7008 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7009 tcg_gen_trunc_i64_i32(t1, t2); \
7010 tcg_temp_free_i64(t2); \
7011 tcg_op(t1, t1); \
7012 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7013 tcg_temp_free_i32(t0); \
7014 tcg_temp_free_i32(t1); \
7015 }
7016 #else
7017 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7018 static inline void gen_##name(DisasContext *ctx) \
7019 { \
7020 if (unlikely(!ctx->spe_enabled)) { \
7021 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7022 return; \
7023 } \
7024 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7025 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7026 }
7027 #endif
7028
7029 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
7030 {
7031 int l1 = gen_new_label();
7032 int l2 = gen_new_label();
7033
7034 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
7035 tcg_gen_neg_i32(ret, arg1);
7036 tcg_gen_br(l2);
7037 gen_set_label(l1);
7038 tcg_gen_mov_i32(ret, arg1);
7039 gen_set_label(l2);
7040 }
7041 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7042 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7043 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7044 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7045 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7046 {
7047 tcg_gen_addi_i32(ret, arg1, 0x8000);
7048 tcg_gen_ext16u_i32(ret, ret);
7049 }
7050 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7051 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7052 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7053
7054 #if defined(TARGET_PPC64)
7055 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7056 static inline void gen_##name(DisasContext *ctx) \
7057 { \
7058 if (unlikely(!ctx->spe_enabled)) { \
7059 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7060 return; \
7061 } \
7062 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7063 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7064 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7065 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7066 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7067 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7068 tcg_op(t0, t0, t2); \
7069 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7070 tcg_gen_trunc_i64_i32(t1, t3); \
7071 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7072 tcg_gen_trunc_i64_i32(t2, t3); \
7073 tcg_temp_free_i64(t3); \
7074 tcg_op(t1, t1, t2); \
7075 tcg_temp_free_i32(t2); \
7076 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7077 tcg_temp_free_i32(t0); \
7078 tcg_temp_free_i32(t1); \
7079 }
7080 #else
7081 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7082 static inline void gen_##name(DisasContext *ctx) \
7083 { \
7084 if (unlikely(!ctx->spe_enabled)) { \
7085 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7086 return; \
7087 } \
7088 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7089 cpu_gpr[rB(ctx->opcode)]); \
7090 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7091 cpu_gprh[rB(ctx->opcode)]); \
7092 }
7093 #endif
7094
7095 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7096 {
7097 TCGv_i32 t0;
7098 int l1, l2;
7099
7100 l1 = gen_new_label();
7101 l2 = gen_new_label();
7102 t0 = tcg_temp_local_new_i32();
7103 /* No error here: 6 bits are used */
7104 tcg_gen_andi_i32(t0, arg2, 0x3F);
7105 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7106 tcg_gen_shr_i32(ret, arg1, t0);
7107 tcg_gen_br(l2);
7108 gen_set_label(l1);
7109 tcg_gen_movi_i32(ret, 0);
7110 gen_set_label(l2);
7111 tcg_temp_free_i32(t0);
7112 }
7113 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7114 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7115 {
7116 TCGv_i32 t0;
7117 int l1, l2;
7118
7119 l1 = gen_new_label();
7120 l2 = gen_new_label();
7121 t0 = tcg_temp_local_new_i32();
7122 /* No error here: 6 bits are used */
7123 tcg_gen_andi_i32(t0, arg2, 0x3F);
7124 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7125 tcg_gen_sar_i32(ret, arg1, t0);
7126 tcg_gen_br(l2);
7127 gen_set_label(l1);
7128 tcg_gen_movi_i32(ret, 0);
7129 gen_set_label(l2);
7130 tcg_temp_free_i32(t0);
7131 }
7132 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7133 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7134 {
7135 TCGv_i32 t0;
7136 int l1, l2;
7137
7138 l1 = gen_new_label();
7139 l2 = gen_new_label();
7140 t0 = tcg_temp_local_new_i32();
7141 /* No error here: 6 bits are used */
7142 tcg_gen_andi_i32(t0, arg2, 0x3F);
7143 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7144 tcg_gen_shl_i32(ret, arg1, t0);
7145 tcg_gen_br(l2);
7146 gen_set_label(l1);
7147 tcg_gen_movi_i32(ret, 0);
7148 gen_set_label(l2);
7149 tcg_temp_free_i32(t0);
7150 }
7151 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7152 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7153 {
7154 TCGv_i32 t0 = tcg_temp_new_i32();
7155 tcg_gen_andi_i32(t0, arg2, 0x1F);
7156 tcg_gen_rotl_i32(ret, arg1, t0);
7157 tcg_temp_free_i32(t0);
7158 }
7159 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7160 static inline void gen_evmergehi(DisasContext *ctx)
7161 {
7162 if (unlikely(!ctx->spe_enabled)) {
7163 gen_exception(ctx, POWERPC_EXCP_SPEU);
7164 return;
7165 }
7166 #if defined(TARGET_PPC64)
7167 TCGv t0 = tcg_temp_new();
7168 TCGv t1 = tcg_temp_new();
7169 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7170 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7171 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7172 tcg_temp_free(t0);
7173 tcg_temp_free(t1);
7174 #else
7175 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7176 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7177 #endif
7178 }
7179 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7180 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7181 {
7182 tcg_gen_sub_i32(ret, arg2, arg1);
7183 }
7184 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7185
7186 /* SPE arithmetic immediate */
7187 #if defined(TARGET_PPC64)
7188 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7189 static inline void gen_##name(DisasContext *ctx) \
7190 { \
7191 if (unlikely(!ctx->spe_enabled)) { \
7192 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7193 return; \
7194 } \
7195 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7196 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7197 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7198 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7199 tcg_op(t0, t0, rA(ctx->opcode)); \
7200 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7201 tcg_gen_trunc_i64_i32(t1, t2); \
7202 tcg_temp_free_i64(t2); \
7203 tcg_op(t1, t1, rA(ctx->opcode)); \
7204 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7205 tcg_temp_free_i32(t0); \
7206 tcg_temp_free_i32(t1); \
7207 }
7208 #else
7209 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7210 static inline void gen_##name(DisasContext *ctx) \
7211 { \
7212 if (unlikely(!ctx->spe_enabled)) { \
7213 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7214 return; \
7215 } \
7216 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7217 rA(ctx->opcode)); \
7218 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7219 rA(ctx->opcode)); \
7220 }
7221 #endif
7222 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7223 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7224
7225 /* SPE comparison */
7226 #if defined(TARGET_PPC64)
7227 #define GEN_SPEOP_COMP(name, tcg_cond) \
7228 static inline void gen_##name(DisasContext *ctx) \
7229 { \
7230 if (unlikely(!ctx->spe_enabled)) { \
7231 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7232 return; \
7233 } \
7234 int l1 = gen_new_label(); \
7235 int l2 = gen_new_label(); \
7236 int l3 = gen_new_label(); \
7237 int l4 = gen_new_label(); \
7238 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7239 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7240 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7241 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7242 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7243 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7244 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7245 tcg_gen_br(l2); \
7246 gen_set_label(l1); \
7247 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7248 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7249 gen_set_label(l2); \
7250 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7251 tcg_gen_trunc_i64_i32(t0, t2); \
7252 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7253 tcg_gen_trunc_i64_i32(t1, t2); \
7254 tcg_temp_free_i64(t2); \
7255 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7256 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7257 ~(CRF_CH | CRF_CH_AND_CL)); \
7258 tcg_gen_br(l4); \
7259 gen_set_label(l3); \
7260 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7261 CRF_CH | CRF_CH_OR_CL); \
7262 gen_set_label(l4); \
7263 tcg_temp_free_i32(t0); \
7264 tcg_temp_free_i32(t1); \
7265 }
7266 #else
7267 #define GEN_SPEOP_COMP(name, tcg_cond) \
7268 static inline void gen_##name(DisasContext *ctx) \
7269 { \
7270 if (unlikely(!ctx->spe_enabled)) { \
7271 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7272 return; \
7273 } \
7274 int l1 = gen_new_label(); \
7275 int l2 = gen_new_label(); \
7276 int l3 = gen_new_label(); \
7277 int l4 = gen_new_label(); \
7278 \
7279 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7280 cpu_gpr[rB(ctx->opcode)], l1); \
7281 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7282 tcg_gen_br(l2); \
7283 gen_set_label(l1); \
7284 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7285 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7286 gen_set_label(l2); \
7287 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7288 cpu_gprh[rB(ctx->opcode)], l3); \
7289 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7290 ~(CRF_CH | CRF_CH_AND_CL)); \
7291 tcg_gen_br(l4); \
7292 gen_set_label(l3); \
7293 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7294 CRF_CH | CRF_CH_OR_CL); \
7295 gen_set_label(l4); \
7296 }
7297 #endif
7298 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7299 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7300 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7301 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7302 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7303
7304 /* SPE misc */
7305 static inline void gen_brinc(DisasContext *ctx)
7306 {
7307 /* Note: brinc is usable even if SPE is disabled */
7308 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7309 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7310 }
7311 static inline void gen_evmergelo(DisasContext *ctx)
7312 {
7313 if (unlikely(!ctx->spe_enabled)) {
7314 gen_exception(ctx, POWERPC_EXCP_SPEU);
7315 return;
7316 }
7317 #if defined(TARGET_PPC64)
7318 TCGv t0 = tcg_temp_new();
7319 TCGv t1 = tcg_temp_new();
7320 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7321 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7322 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7323 tcg_temp_free(t0);
7324 tcg_temp_free(t1);
7325 #else
7326 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7327 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7328 #endif
7329 }
7330 static inline void gen_evmergehilo(DisasContext *ctx)
7331 {
7332 if (unlikely(!ctx->spe_enabled)) {
7333 gen_exception(ctx, POWERPC_EXCP_SPEU);
7334 return;
7335 }
7336 #if defined(TARGET_PPC64)
7337 TCGv t0 = tcg_temp_new();
7338 TCGv t1 = tcg_temp_new();
7339 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7340 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7341 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7342 tcg_temp_free(t0);
7343 tcg_temp_free(t1);
7344 #else
7345 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7346 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7347 #endif
7348 }
7349 static inline void gen_evmergelohi(DisasContext *ctx)
7350 {
7351 if (unlikely(!ctx->spe_enabled)) {
7352 gen_exception(ctx, POWERPC_EXCP_SPEU);
7353 return;
7354 }
7355 #if defined(TARGET_PPC64)
7356 TCGv t0 = tcg_temp_new();
7357 TCGv t1 = tcg_temp_new();
7358 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7359 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7360 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7361 tcg_temp_free(t0);
7362 tcg_temp_free(t1);
7363 #else
7364 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7365 TCGv_i32 tmp = tcg_temp_new_i32();
7366 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7367 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7368 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7369 tcg_temp_free_i32(tmp);
7370 } else {
7371 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7372 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7373 }
7374 #endif
7375 }
7376 static inline void gen_evsplati(DisasContext *ctx)
7377 {
7378 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7379
7380 #if defined(TARGET_PPC64)
7381 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7382 #else
7383 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7384 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7385 #endif
7386 }
7387 static inline void gen_evsplatfi(DisasContext *ctx)
7388 {
7389 uint64_t imm = rA(ctx->opcode) << 27;
7390
7391 #if defined(TARGET_PPC64)
7392 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7393 #else
7394 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7395 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7396 #endif
7397 }
7398
7399 static inline void gen_evsel(DisasContext *ctx)
7400 {
7401 int l1 = gen_new_label();
7402 int l2 = gen_new_label();
7403 int l3 = gen_new_label();
7404 int l4 = gen_new_label();
7405 TCGv_i32 t0 = tcg_temp_local_new_i32();
7406 #if defined(TARGET_PPC64)
7407 TCGv t1 = tcg_temp_local_new();
7408 TCGv t2 = tcg_temp_local_new();
7409 #endif
7410 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7411 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7412 #if defined(TARGET_PPC64)
7413 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7414 #else
7415 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7416 #endif
7417 tcg_gen_br(l2);
7418 gen_set_label(l1);
7419 #if defined(TARGET_PPC64)
7420 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7421 #else
7422 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7423 #endif
7424 gen_set_label(l2);
7425 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7426 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7427 #if defined(TARGET_PPC64)
7428 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7429 #else
7430 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7431 #endif
7432 tcg_gen_br(l4);
7433 gen_set_label(l3);
7434 #if defined(TARGET_PPC64)
7435 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7436 #else
7437 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7438 #endif
7439 gen_set_label(l4);
7440 tcg_temp_free_i32(t0);
7441 #if defined(TARGET_PPC64)
7442 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7443 tcg_temp_free(t1);
7444 tcg_temp_free(t2);
7445 #endif
7446 }
7447
7448 static void gen_evsel0(DisasContext *ctx)
7449 {
7450 gen_evsel(ctx);
7451 }
7452
7453 static void gen_evsel1(DisasContext *ctx)
7454 {
7455 gen_evsel(ctx);
7456 }
7457
7458 static void gen_evsel2(DisasContext *ctx)
7459 {
7460 gen_evsel(ctx);
7461 }
7462
7463 static void gen_evsel3(DisasContext *ctx)
7464 {
7465 gen_evsel(ctx);
7466 }
7467
7468 /* Multiply */
7469
7470 static inline void gen_evmwumi(DisasContext *ctx)
7471 {
7472 TCGv_i64 t0, t1;
7473
7474 if (unlikely(!ctx->spe_enabled)) {
7475 gen_exception(ctx, POWERPC_EXCP_SPEU);
7476 return;
7477 }
7478
7479 t0 = tcg_temp_new_i64();
7480 t1 = tcg_temp_new_i64();
7481
7482 /* t0 := rA; t1 := rB */
7483 #if defined(TARGET_PPC64)
7484 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7485 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7486 #else
7487 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7488 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7489 #endif
7490
7491 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7492
7493 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7494
7495 tcg_temp_free_i64(t0);
7496 tcg_temp_free_i64(t1);
7497 }
7498
7499 static inline void gen_evmwumia(DisasContext *ctx)
7500 {
7501 TCGv_i64 tmp;
7502
7503 if (unlikely(!ctx->spe_enabled)) {
7504 gen_exception(ctx, POWERPC_EXCP_SPEU);
7505 return;
7506 }
7507
7508 gen_evmwumi(ctx); /* rD := rA * rB */
7509
7510 tmp = tcg_temp_new_i64();
7511
7512 /* acc := rD */
7513 gen_load_gpr64(tmp, rD(ctx->opcode));
7514 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7515 tcg_temp_free_i64(tmp);
7516 }
7517
7518 static inline void gen_evmwumiaa(DisasContext *ctx)
7519 {
7520 TCGv_i64 acc;
7521 TCGv_i64 tmp;
7522
7523 if (unlikely(!ctx->spe_enabled)) {
7524 gen_exception(ctx, POWERPC_EXCP_SPEU);
7525 return;
7526 }
7527
7528 gen_evmwumi(ctx); /* rD := rA * rB */
7529
7530 acc = tcg_temp_new_i64();
7531 tmp = tcg_temp_new_i64();
7532
7533 /* tmp := rD */
7534 gen_load_gpr64(tmp, rD(ctx->opcode));
7535
7536 /* Load acc */
7537 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7538
7539 /* acc := tmp + acc */
7540 tcg_gen_add_i64(acc, acc, tmp);
7541
7542 /* Store acc */
7543 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7544
7545 /* rD := acc */
7546 gen_store_gpr64(rD(ctx->opcode), acc);
7547
7548 tcg_temp_free_i64(acc);
7549 tcg_temp_free_i64(tmp);
7550 }
7551
7552 static inline void gen_evmwsmi(DisasContext *ctx)
7553 {
7554 TCGv_i64 t0, t1;
7555
7556 if (unlikely(!ctx->spe_enabled)) {
7557 gen_exception(ctx, POWERPC_EXCP_SPEU);
7558 return;
7559 }
7560
7561 t0 = tcg_temp_new_i64();
7562 t1 = tcg_temp_new_i64();
7563
7564 /* t0 := rA; t1 := rB */
7565 #if defined(TARGET_PPC64)
7566 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7567 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7568 #else
7569 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7570 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7571 #endif
7572
7573 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7574
7575 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7576
7577 tcg_temp_free_i64(t0);
7578 tcg_temp_free_i64(t1);
7579 }
7580
7581 static inline void gen_evmwsmia(DisasContext *ctx)
7582 {
7583 TCGv_i64 tmp;
7584
7585 gen_evmwsmi(ctx); /* rD := rA * rB */
7586
7587 tmp = tcg_temp_new_i64();
7588
7589 /* acc := rD */
7590 gen_load_gpr64(tmp, rD(ctx->opcode));
7591 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7592
7593 tcg_temp_free_i64(tmp);
7594 }
7595
7596 static inline void gen_evmwsmiaa(DisasContext *ctx)
7597 {
7598 TCGv_i64 acc = tcg_temp_new_i64();
7599 TCGv_i64 tmp = tcg_temp_new_i64();
7600
7601 gen_evmwsmi(ctx); /* rD := rA * rB */
7602
7603 acc = tcg_temp_new_i64();
7604 tmp = tcg_temp_new_i64();
7605
7606 /* tmp := rD */
7607 gen_load_gpr64(tmp, rD(ctx->opcode));
7608
7609 /* Load acc */
7610 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7611
7612 /* acc := tmp + acc */
7613 tcg_gen_add_i64(acc, acc, tmp);
7614
7615 /* Store acc */
7616 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7617
7618 /* rD := acc */
7619 gen_store_gpr64(rD(ctx->opcode), acc);
7620
7621 tcg_temp_free_i64(acc);
7622 tcg_temp_free_i64(tmp);
7623 }
7624
7625 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7626 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7627 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7628 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7629 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7630 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7631 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7632 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7633 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7634 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7635 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7636 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7637 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7638 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7639 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7640 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7641 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7642 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7643 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7644 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7645 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7646 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7647 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7648 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7649 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7650 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7651 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7652 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7653 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7654
7655 /* SPE load and stores */
7656 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7657 {
7658 target_ulong uimm = rB(ctx->opcode);
7659
7660 if (rA(ctx->opcode) == 0) {
7661 tcg_gen_movi_tl(EA, uimm << sh);
7662 } else {
7663 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7664 if (NARROW_MODE(ctx)) {
7665 tcg_gen_ext32u_tl(EA, EA);
7666 }
7667 }
7668 }
7669
7670 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7671 {
7672 #if defined(TARGET_PPC64)
7673 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7674 #else
7675 TCGv_i64 t0 = tcg_temp_new_i64();
7676 gen_qemu_ld64(ctx, t0, addr);
7677 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7678 tcg_gen_shri_i64(t0, t0, 32);
7679 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7680 tcg_temp_free_i64(t0);
7681 #endif
7682 }
7683
7684 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7685 {
7686 #if defined(TARGET_PPC64)
7687 TCGv t0 = tcg_temp_new();
7688 gen_qemu_ld32u(ctx, t0, addr);
7689 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7690 gen_addr_add(ctx, addr, addr, 4);
7691 gen_qemu_ld32u(ctx, t0, addr);
7692 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7693 tcg_temp_free(t0);
7694 #else
7695 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7696 gen_addr_add(ctx, addr, addr, 4);
7697 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7698 #endif
7699 }
7700
7701 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7702 {
7703 TCGv t0 = tcg_temp_new();
7704 #if defined(TARGET_PPC64)
7705 gen_qemu_ld16u(ctx, t0, addr);
7706 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7707 gen_addr_add(ctx, addr, addr, 2);
7708 gen_qemu_ld16u(ctx, t0, addr);
7709 tcg_gen_shli_tl(t0, t0, 32);
7710 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7711 gen_addr_add(ctx, addr, addr, 2);
7712 gen_qemu_ld16u(ctx, t0, addr);
7713 tcg_gen_shli_tl(t0, t0, 16);
7714 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7715 gen_addr_add(ctx, addr, addr, 2);
7716 gen_qemu_ld16u(ctx, t0, addr);
7717 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7718 #else
7719 gen_qemu_ld16u(ctx, t0, addr);
7720 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7721 gen_addr_add(ctx, addr, addr, 2);
7722 gen_qemu_ld16u(ctx, t0, addr);
7723 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7724 gen_addr_add(ctx, addr, addr, 2);
7725 gen_qemu_ld16u(ctx, t0, addr);
7726 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7727 gen_addr_add(ctx, addr, addr, 2);
7728 gen_qemu_ld16u(ctx, t0, addr);
7729 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7730 #endif
7731 tcg_temp_free(t0);
7732 }
7733
7734 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7735 {
7736 TCGv t0 = tcg_temp_new();
7737 gen_qemu_ld16u(ctx, t0, addr);
7738 #if defined(TARGET_PPC64)
7739 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7740 tcg_gen_shli_tl(t0, t0, 16);
7741 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7742 #else
7743 tcg_gen_shli_tl(t0, t0, 16);
7744 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7745 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7746 #endif
7747 tcg_temp_free(t0);
7748 }
7749
7750 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7751 {
7752 TCGv t0 = tcg_temp_new();
7753 gen_qemu_ld16u(ctx, t0, addr);
7754 #if defined(TARGET_PPC64)
7755 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7756 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7757 #else
7758 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7759 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7760 #endif
7761 tcg_temp_free(t0);
7762 }
7763
7764 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7765 {
7766 TCGv t0 = tcg_temp_new();
7767 gen_qemu_ld16s(ctx, t0, addr);
7768 #if defined(TARGET_PPC64)
7769 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7770 tcg_gen_ext32u_tl(t0, t0);
7771 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7772 #else
7773 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7774 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7775 #endif
7776 tcg_temp_free(t0);
7777 }
7778
7779 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7780 {
7781 TCGv t0 = tcg_temp_new();
7782 #if defined(TARGET_PPC64)
7783 gen_qemu_ld16u(ctx, t0, addr);
7784 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7785 gen_addr_add(ctx, addr, addr, 2);
7786 gen_qemu_ld16u(ctx, t0, addr);
7787 tcg_gen_shli_tl(t0, t0, 16);
7788 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7789 #else
7790 gen_qemu_ld16u(ctx, t0, addr);
7791 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7792 gen_addr_add(ctx, addr, addr, 2);
7793 gen_qemu_ld16u(ctx, t0, addr);
7794 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7795 #endif
7796 tcg_temp_free(t0);
7797 }
7798
7799 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7800 {
7801 #if defined(TARGET_PPC64)
7802 TCGv t0 = tcg_temp_new();
7803 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7804 gen_addr_add(ctx, addr, addr, 2);
7805 gen_qemu_ld16u(ctx, t0, addr);
7806 tcg_gen_shli_tl(t0, t0, 32);
7807 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7808 tcg_temp_free(t0);
7809 #else
7810 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7811 gen_addr_add(ctx, addr, addr, 2);
7812 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7813 #endif
7814 }
7815
7816 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7817 {
7818 #if defined(TARGET_PPC64)
7819 TCGv t0 = tcg_temp_new();
7820 gen_qemu_ld16s(ctx, t0, addr);
7821 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7822 gen_addr_add(ctx, addr, addr, 2);
7823 gen_qemu_ld16s(ctx, t0, addr);
7824 tcg_gen_shli_tl(t0, t0, 32);
7825 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7826 tcg_temp_free(t0);
7827 #else
7828 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7829 gen_addr_add(ctx, addr, addr, 2);
7830 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7831 #endif
7832 }
7833
7834 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7835 {
7836 TCGv t0 = tcg_temp_new();
7837 gen_qemu_ld32u(ctx, t0, addr);
7838 #if defined(TARGET_PPC64)
7839 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7840 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7841 #else
7842 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7843 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7844 #endif
7845 tcg_temp_free(t0);
7846 }
7847
7848 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7849 {
7850 TCGv t0 = tcg_temp_new();
7851 #if defined(TARGET_PPC64)
7852 gen_qemu_ld16u(ctx, t0, addr);
7853 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7854 tcg_gen_shli_tl(t0, t0, 32);
7855 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7856 gen_addr_add(ctx, addr, addr, 2);
7857 gen_qemu_ld16u(ctx, t0, addr);
7858 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7859 tcg_gen_shli_tl(t0, t0, 16);
7860 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7861 #else
7862 gen_qemu_ld16u(ctx, t0, addr);
7863 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7864 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7865 gen_addr_add(ctx, addr, addr, 2);
7866 gen_qemu_ld16u(ctx, t0, addr);
7867 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7868 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7869 #endif
7870 tcg_temp_free(t0);
7871 }
7872
7873 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7874 {
7875 #if defined(TARGET_PPC64)
7876 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7877 #else
7878 TCGv_i64 t0 = tcg_temp_new_i64();
7879 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7880 gen_qemu_st64(ctx, t0, addr);
7881 tcg_temp_free_i64(t0);
7882 #endif
7883 }
7884
7885 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7886 {
7887 #if defined(TARGET_PPC64)
7888 TCGv t0 = tcg_temp_new();
7889 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7890 gen_qemu_st32(ctx, t0, addr);
7891 tcg_temp_free(t0);
7892 #else
7893 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7894 #endif
7895 gen_addr_add(ctx, addr, addr, 4);
7896 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7897 }
7898
7899 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7900 {
7901 TCGv t0 = tcg_temp_new();
7902 #if defined(TARGET_PPC64)
7903 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7904 #else
7905 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7906 #endif
7907 gen_qemu_st16(ctx, t0, addr);
7908 gen_addr_add(ctx, addr, addr, 2);
7909 #if defined(TARGET_PPC64)
7910 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7911 gen_qemu_st16(ctx, t0, addr);
7912 #else
7913 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7914 #endif
7915 gen_addr_add(ctx, addr, addr, 2);
7916 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7917 gen_qemu_st16(ctx, t0, addr);
7918 tcg_temp_free(t0);
7919 gen_addr_add(ctx, addr, addr, 2);
7920 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7921 }
7922
7923 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7924 {
7925 TCGv t0 = tcg_temp_new();
7926 #if defined(TARGET_PPC64)
7927 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7928 #else
7929 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7930 #endif
7931 gen_qemu_st16(ctx, t0, addr);
7932 gen_addr_add(ctx, addr, addr, 2);
7933 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7934 gen_qemu_st16(ctx, t0, addr);
7935 tcg_temp_free(t0);
7936 }
7937
7938 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7939 {
7940 #if defined(TARGET_PPC64)
7941 TCGv t0 = tcg_temp_new();
7942 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7943 gen_qemu_st16(ctx, t0, addr);
7944 tcg_temp_free(t0);
7945 #else
7946 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7947 #endif
7948 gen_addr_add(ctx, addr, addr, 2);
7949 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7950 }
7951
7952 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7953 {
7954 #if defined(TARGET_PPC64)
7955 TCGv t0 = tcg_temp_new();
7956 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7957 gen_qemu_st32(ctx, t0, addr);
7958 tcg_temp_free(t0);
7959 #else
7960 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7961 #endif
7962 }
7963
7964 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7965 {
7966 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7967 }
7968
7969 #define GEN_SPEOP_LDST(name, opc2, sh) \
7970 static void glue(gen_, name)(DisasContext *ctx) \
7971 { \
7972 TCGv t0; \
7973 if (unlikely(!ctx->spe_enabled)) { \
7974 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7975 return; \
7976 } \
7977 gen_set_access_type(ctx, ACCESS_INT); \
7978 t0 = tcg_temp_new(); \
7979 if (Rc(ctx->opcode)) { \
7980 gen_addr_spe_imm_index(ctx, t0, sh); \
7981 } else { \
7982 gen_addr_reg_index(ctx, t0); \
7983 } \
7984 gen_op_##name(ctx, t0); \
7985 tcg_temp_free(t0); \
7986 }
7987
7988 GEN_SPEOP_LDST(evldd, 0x00, 3);
7989 GEN_SPEOP_LDST(evldw, 0x01, 3);
7990 GEN_SPEOP_LDST(evldh, 0x02, 3);
7991 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7992 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7993 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7994 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7995 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7996 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7997 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7998 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7999
8000 GEN_SPEOP_LDST(evstdd, 0x10, 3);
8001 GEN_SPEOP_LDST(evstdw, 0x11, 3);
8002 GEN_SPEOP_LDST(evstdh, 0x12, 3);
8003 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
8004 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
8005 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
8006 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
8007
8008 /* Multiply and add - TODO */
8009 #if 0
8010 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
8011 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8012 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8013 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8014 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8015 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8016 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8017 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8018 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8019 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8020 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8021 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8022
8023 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8024 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8025 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8026 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8027 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8028 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8029 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8030 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8031 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8032 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8033 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8034 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8035
8036 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8037 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8038 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8039 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8040 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8041
8042 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8043 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8044 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8045 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8046 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8047 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8048 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8049 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8050 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8051 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8052 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8053 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8054
8055 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8056 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8057 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8058 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8059
8060 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8061 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8062 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8063 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8064 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8065 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8066 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8067 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8068 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8069 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8070 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8071 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8072
8073 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8074 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8075 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8076 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8077 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8078 #endif
8079
8080 /*** SPE floating-point extension ***/
8081 #if defined(TARGET_PPC64)
8082 #define GEN_SPEFPUOP_CONV_32_32(name) \
8083 static inline void gen_##name(DisasContext *ctx) \
8084 { \
8085 TCGv_i32 t0; \
8086 TCGv t1; \
8087 t0 = tcg_temp_new_i32(); \
8088 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8089 gen_helper_##name(t0, cpu_env, t0); \
8090 t1 = tcg_temp_new(); \
8091 tcg_gen_extu_i32_tl(t1, t0); \
8092 tcg_temp_free_i32(t0); \
8093 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8094 0xFFFFFFFF00000000ULL); \
8095 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8096 tcg_temp_free(t1); \
8097 }
8098 #define GEN_SPEFPUOP_CONV_32_64(name) \
8099 static inline void gen_##name(DisasContext *ctx) \
8100 { \
8101 TCGv_i32 t0; \
8102 TCGv t1; \
8103 t0 = tcg_temp_new_i32(); \
8104 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8105 t1 = tcg_temp_new(); \
8106 tcg_gen_extu_i32_tl(t1, t0); \
8107 tcg_temp_free_i32(t0); \
8108 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8109 0xFFFFFFFF00000000ULL); \
8110 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8111 tcg_temp_free(t1); \
8112 }
8113 #define GEN_SPEFPUOP_CONV_64_32(name) \
8114 static inline void gen_##name(DisasContext *ctx) \
8115 { \
8116 TCGv_i32 t0 = tcg_temp_new_i32(); \
8117 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8118 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8119 tcg_temp_free_i32(t0); \
8120 }
8121 #define GEN_SPEFPUOP_CONV_64_64(name) \
8122 static inline void gen_##name(DisasContext *ctx) \
8123 { \
8124 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8125 cpu_gpr[rB(ctx->opcode)]); \
8126 }
8127 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8128 static inline void gen_##name(DisasContext *ctx) \
8129 { \
8130 TCGv_i32 t0, t1; \
8131 TCGv_i64 t2; \
8132 if (unlikely(!ctx->spe_enabled)) { \
8133 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8134 return; \
8135 } \
8136 t0 = tcg_temp_new_i32(); \
8137 t1 = tcg_temp_new_i32(); \
8138 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8139 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8140 gen_helper_##name(t0, cpu_env, t0, t1); \
8141 tcg_temp_free_i32(t1); \
8142 t2 = tcg_temp_new(); \
8143 tcg_gen_extu_i32_tl(t2, t0); \
8144 tcg_temp_free_i32(t0); \
8145 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8146 0xFFFFFFFF00000000ULL); \
8147 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8148 tcg_temp_free(t2); \
8149 }
8150 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8151 static inline void gen_##name(DisasContext *ctx) \
8152 { \
8153 if (unlikely(!ctx->spe_enabled)) { \
8154 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8155 return; \
8156 } \
8157 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8158 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8159 }
8160 #define GEN_SPEFPUOP_COMP_32(name) \
8161 static inline void gen_##name(DisasContext *ctx) \
8162 { \
8163 TCGv_i32 t0, t1; \
8164 if (unlikely(!ctx->spe_enabled)) { \
8165 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8166 return; \
8167 } \
8168 t0 = tcg_temp_new_i32(); \
8169 t1 = tcg_temp_new_i32(); \
8170 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8171 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8172 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8173 tcg_temp_free_i32(t0); \
8174 tcg_temp_free_i32(t1); \
8175 }
8176 #define GEN_SPEFPUOP_COMP_64(name) \
8177 static inline void gen_##name(DisasContext *ctx) \
8178 { \
8179 if (unlikely(!ctx->spe_enabled)) { \
8180 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8181 return; \
8182 } \
8183 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8184 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8185 }
8186 #else
8187 #define GEN_SPEFPUOP_CONV_32_32(name) \
8188 static inline void gen_##name(DisasContext *ctx) \
8189 { \
8190 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8191 cpu_gpr[rB(ctx->opcode)]); \
8192 }
8193 #define GEN_SPEFPUOP_CONV_32_64(name) \
8194 static inline void gen_##name(DisasContext *ctx) \
8195 { \
8196 TCGv_i64 t0 = tcg_temp_new_i64(); \
8197 gen_load_gpr64(t0, rB(ctx->opcode)); \
8198 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8199 tcg_temp_free_i64(t0); \
8200 }
8201 #define GEN_SPEFPUOP_CONV_64_32(name) \
8202 static inline void gen_##name(DisasContext *ctx) \
8203 { \
8204 TCGv_i64 t0 = tcg_temp_new_i64(); \
8205 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8206 gen_store_gpr64(rD(ctx->opcode), t0); \
8207 tcg_temp_free_i64(t0); \
8208 }
8209 #define GEN_SPEFPUOP_CONV_64_64(name) \
8210 static inline void gen_##name(DisasContext *ctx) \
8211 { \
8212 TCGv_i64 t0 = tcg_temp_new_i64(); \
8213 gen_load_gpr64(t0, rB(ctx->opcode)); \
8214 gen_helper_##name(t0, cpu_env, t0); \
8215 gen_store_gpr64(rD(ctx->opcode), t0); \
8216 tcg_temp_free_i64(t0); \
8217 }
8218 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8219 static inline void gen_##name(DisasContext *ctx) \
8220 { \
8221 if (unlikely(!ctx->spe_enabled)) { \
8222 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8223 return; \
8224 } \
8225 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8226 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8227 }
8228 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8229 static inline void gen_##name(DisasContext *ctx) \
8230 { \
8231 TCGv_i64 t0, t1; \
8232 if (unlikely(!ctx->spe_enabled)) { \
8233 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8234 return; \
8235 } \
8236 t0 = tcg_temp_new_i64(); \
8237 t1 = tcg_temp_new_i64(); \
8238 gen_load_gpr64(t0, rA(ctx->opcode)); \
8239 gen_load_gpr64(t1, rB(ctx->opcode)); \
8240 gen_helper_##name(t0, cpu_env, t0, t1); \
8241 gen_store_gpr64(rD(ctx->opcode), t0); \
8242 tcg_temp_free_i64(t0); \
8243 tcg_temp_free_i64(t1); \
8244 }
8245 #define GEN_SPEFPUOP_COMP_32(name) \
8246 static inline void gen_##name(DisasContext *ctx) \
8247 { \
8248 if (unlikely(!ctx->spe_enabled)) { \
8249 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8250 return; \
8251 } \
8252 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8253 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8254 }
8255 #define GEN_SPEFPUOP_COMP_64(name) \
8256 static inline void gen_##name(DisasContext *ctx) \
8257 { \
8258 TCGv_i64 t0, t1; \
8259 if (unlikely(!ctx->spe_enabled)) { \
8260 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8261 return; \
8262 } \
8263 t0 = tcg_temp_new_i64(); \
8264 t1 = tcg_temp_new_i64(); \
8265 gen_load_gpr64(t0, rA(ctx->opcode)); \
8266 gen_load_gpr64(t1, rB(ctx->opcode)); \
8267 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8268 tcg_temp_free_i64(t0); \
8269 tcg_temp_free_i64(t1); \
8270 }
8271 #endif
8272
8273 /* Single precision floating-point vectors operations */
8274 /* Arithmetic */
8275 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8276 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8277 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8278 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8279 static inline void gen_evfsabs(DisasContext *ctx)
8280 {
8281 if (unlikely(!ctx->spe_enabled)) {
8282 gen_exception(ctx, POWERPC_EXCP_SPEU);
8283 return;
8284 }
8285 #if defined(TARGET_PPC64)
8286 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8287 #else
8288 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8289 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8290 #endif
8291 }
8292 static inline void gen_evfsnabs(DisasContext *ctx)
8293 {
8294 if (unlikely(!ctx->spe_enabled)) {
8295 gen_exception(ctx, POWERPC_EXCP_SPEU);
8296 return;
8297 }
8298 #if defined(TARGET_PPC64)
8299 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8300 #else
8301 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8302 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8303 #endif
8304 }
8305 static inline void gen_evfsneg(DisasContext *ctx)
8306 {
8307 if (unlikely(!ctx->spe_enabled)) {
8308 gen_exception(ctx, POWERPC_EXCP_SPEU);
8309 return;
8310 }
8311 #if defined(TARGET_PPC64)
8312 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8313 #else
8314 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8315 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8316 #endif
8317 }
8318
8319 /* Conversion */
8320 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8321 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8322 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8323 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8324 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8325 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8326 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8327 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8328 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8329 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8330
8331 /* Comparison */
8332 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8333 GEN_SPEFPUOP_COMP_64(evfscmplt);
8334 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8335 GEN_SPEFPUOP_COMP_64(evfststgt);
8336 GEN_SPEFPUOP_COMP_64(evfststlt);
8337 GEN_SPEFPUOP_COMP_64(evfststeq);
8338
8339 /* Opcodes definitions */
8340 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8341 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8342 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8343 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8344 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8345 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8346 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8347 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8348 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8349 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8350 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8351 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8352 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8353 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8354
8355 /* Single precision floating-point operations */
8356 /* Arithmetic */
8357 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8358 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8359 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8360 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8361 static inline void gen_efsabs(DisasContext *ctx)
8362 {
8363 if (unlikely(!ctx->spe_enabled)) {
8364 gen_exception(ctx, POWERPC_EXCP_SPEU);
8365 return;
8366 }
8367 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8368 }
8369 static inline void gen_efsnabs(DisasContext *ctx)
8370 {
8371 if (unlikely(!ctx->spe_enabled)) {
8372 gen_exception(ctx, POWERPC_EXCP_SPEU);
8373 return;
8374 }
8375 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8376 }
8377 static inline void gen_efsneg(DisasContext *ctx)
8378 {
8379 if (unlikely(!ctx->spe_enabled)) {
8380 gen_exception(ctx, POWERPC_EXCP_SPEU);
8381 return;
8382 }
8383 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8384 }
8385
8386 /* Conversion */
8387 GEN_SPEFPUOP_CONV_32_32(efscfui);
8388 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8389 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8390 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8391 GEN_SPEFPUOP_CONV_32_32(efsctui);
8392 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8393 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8394 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8395 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8396 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8397 GEN_SPEFPUOP_CONV_32_64(efscfd);
8398
8399 /* Comparison */
8400 GEN_SPEFPUOP_COMP_32(efscmpgt);
8401 GEN_SPEFPUOP_COMP_32(efscmplt);
8402 GEN_SPEFPUOP_COMP_32(efscmpeq);
8403 GEN_SPEFPUOP_COMP_32(efststgt);
8404 GEN_SPEFPUOP_COMP_32(efststlt);
8405 GEN_SPEFPUOP_COMP_32(efststeq);
8406
8407 /* Opcodes definitions */
8408 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8409 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8410 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8411 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8412 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8413 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8414 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8415 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8416 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8417 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8418 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8419 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8420 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8421 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8422
8423 /* Double precision floating-point operations */
8424 /* Arithmetic */
8425 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8426 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8427 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8428 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8429 static inline void gen_efdabs(DisasContext *ctx)
8430 {
8431 if (unlikely(!ctx->spe_enabled)) {
8432 gen_exception(ctx, POWERPC_EXCP_SPEU);
8433 return;
8434 }
8435 #if defined(TARGET_PPC64)
8436 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8437 #else
8438 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8439 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8440 #endif
8441 }
8442 static inline void gen_efdnabs(DisasContext *ctx)
8443 {
8444 if (unlikely(!ctx->spe_enabled)) {
8445 gen_exception(ctx, POWERPC_EXCP_SPEU);
8446 return;
8447 }
8448 #if defined(TARGET_PPC64)
8449 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8450 #else
8451 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8452 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8453 #endif
8454 }
8455 static inline void gen_efdneg(DisasContext *ctx)
8456 {
8457 if (unlikely(!ctx->spe_enabled)) {
8458 gen_exception(ctx, POWERPC_EXCP_SPEU);
8459 return;
8460 }
8461 #if defined(TARGET_PPC64)
8462 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8463 #else
8464 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8465 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8466 #endif
8467 }
8468
8469 /* Conversion */
8470 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8471 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8472 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8473 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8474 GEN_SPEFPUOP_CONV_32_64(efdctui);
8475 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8476 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8477 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8478 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8479 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8480 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8481 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8482 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8483 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8484 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8485
8486 /* Comparison */
8487 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8488 GEN_SPEFPUOP_COMP_64(efdcmplt);
8489 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8490 GEN_SPEFPUOP_COMP_64(efdtstgt);
8491 GEN_SPEFPUOP_COMP_64(efdtstlt);
8492 GEN_SPEFPUOP_COMP_64(efdtsteq);
8493
8494 /* Opcodes definitions */
8495 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8496 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8497 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8498 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8499 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8500 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8501 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8502 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8503 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8504 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8505 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8506 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8507 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8508 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8509 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8510 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8511
8512 static opcode_t opcodes[] = {
8513 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8514 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8515 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8516 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8517 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8518 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
8519 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8520 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8521 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8522 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8523 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8524 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8525 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8526 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8527 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8528 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8529 #if defined(TARGET_PPC64)
8530 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8531 #endif
8532 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8533 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8534 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8535 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8536 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8537 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8538 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8539 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8540 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8541 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8542 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8543 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8544 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8545 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8546 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
8547 #if defined(TARGET_PPC64)
8548 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8549 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8550 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
8551 #endif
8552 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8553 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8554 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8555 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8556 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8557 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8558 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8559 #if defined(TARGET_PPC64)
8560 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8561 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8562 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8563 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8564 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8565 #endif
8566 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8567 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8568 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8569 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8570 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8571 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
8572 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8573 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
8574 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
8575 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
8576 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8577 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8578 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8579 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8580 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8581 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8582 #if defined(TARGET_PPC64)
8583 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8584 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8585 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8586 #endif
8587 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8588 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8589 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8590 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8591 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8592 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8593 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8594 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8595 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8596 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8597 #if defined(TARGET_PPC64)
8598 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8599 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8600 #endif
8601 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8602 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8603 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8604 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8605 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8606 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8607 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8608 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8609 #if defined(TARGET_PPC64)
8610 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8611 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8612 #endif
8613 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8614 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8615 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8616 #if defined(TARGET_PPC64)
8617 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8618 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8619 #endif
8620 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8621 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8622 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8623 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8624 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8625 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8626 #if defined(TARGET_PPC64)
8627 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8628 #endif
8629 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8630 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8631 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8632 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8633 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8634 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8635 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8636 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8637 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8638 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8639 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8640 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8641 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8642 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8643 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8644 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8645 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8646 #if defined(TARGET_PPC64)
8647 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8648 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8649 PPC_SEGMENT_64B),
8650 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8651 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8652 PPC_SEGMENT_64B),
8653 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8654 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8655 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8656 #endif
8657 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8658 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8659 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8660 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8661 #if defined(TARGET_PPC64)
8662 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8663 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8664 #endif
8665 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8666 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8667 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8668 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8669 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8670 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8671 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8672 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8673 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8674 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8675 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8676 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8677 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8678 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8679 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8680 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8681 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8682 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8683 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8684 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8685 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8686 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8687 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8688 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8689 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8690 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8691 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8692 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8693 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8694 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8695 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8696 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8697 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8698 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8699 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8700 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8701 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8702 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8703 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8704 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8705 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8706 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8707 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8708 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8709 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8710 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8711 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8712 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8713 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8714 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8715 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8716 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8717 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8718 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8719 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8720 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8721 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8722 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8723 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8724 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8725 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8726 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8727 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8728 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8729 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8730 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8731 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8732 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8733 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8734 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8735 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8736 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8737 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8738 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8739 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8740 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8741 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8742 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8743 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8744 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8745 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8746 PPC_NONE, PPC2_BOOKE206),
8747 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8748 PPC_NONE, PPC2_BOOKE206),
8749 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8750 PPC_NONE, PPC2_BOOKE206),
8751 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8752 PPC_NONE, PPC2_BOOKE206),
8753 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8754 PPC_NONE, PPC2_BOOKE206),
8755 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8756 PPC_NONE, PPC2_PRCNTL),
8757 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8758 PPC_NONE, PPC2_PRCNTL),
8759 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8760 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8761 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8762 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8763 PPC_BOOKE, PPC2_BOOKE206),
8764 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8765 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8766 PPC_BOOKE, PPC2_BOOKE206),
8767 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8768 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8769 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8770 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8771 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8772 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8773 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8774 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8775 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8776 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8777
8778 #undef GEN_INT_ARITH_ADD
8779 #undef GEN_INT_ARITH_ADD_CONST
8780 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8781 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8782 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8783 add_ca, compute_ca, compute_ov) \
8784 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8785 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8786 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8787 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8788 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8789 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8790 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8791 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8792 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8793 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8794 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8795
8796 #undef GEN_INT_ARITH_DIVW
8797 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8798 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8799 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8800 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8801 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8802 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8803
8804 #if defined(TARGET_PPC64)
8805 #undef GEN_INT_ARITH_DIVD
8806 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8807 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8808 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8809 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8810 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8811 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8812
8813 #undef GEN_INT_ARITH_MUL_HELPER
8814 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8815 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8816 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8817 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8818 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8819 #endif
8820
8821 #undef GEN_INT_ARITH_SUBF
8822 #undef GEN_INT_ARITH_SUBF_CONST
8823 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8824 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8825 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8826 add_ca, compute_ca, compute_ov) \
8827 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8828 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8829 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8830 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8831 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8832 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8833 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8834 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8835 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8836 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8837 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8838
8839 #undef GEN_LOGICAL1
8840 #undef GEN_LOGICAL2
8841 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8842 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8843 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8844 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8845 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8846 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8847 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8848 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8849 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8850 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8851 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8852 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8853 #if defined(TARGET_PPC64)
8854 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8855 #endif
8856
8857 #if defined(TARGET_PPC64)
8858 #undef GEN_PPC64_R2
8859 #undef GEN_PPC64_R4
8860 #define GEN_PPC64_R2(name, opc1, opc2) \
8861 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8862 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8863 PPC_64B)
8864 #define GEN_PPC64_R4(name, opc1, opc2) \
8865 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8866 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8867 PPC_64B), \
8868 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8869 PPC_64B), \
8870 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8871 PPC_64B)
8872 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8873 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8874 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8875 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8876 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8877 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8878 #endif
8879
8880 #undef _GEN_FLOAT_ACB
8881 #undef GEN_FLOAT_ACB
8882 #undef _GEN_FLOAT_AB
8883 #undef GEN_FLOAT_AB
8884 #undef _GEN_FLOAT_AC
8885 #undef GEN_FLOAT_AC
8886 #undef GEN_FLOAT_B
8887 #undef GEN_FLOAT_BS
8888 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8889 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8890 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8891 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8892 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8893 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8894 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8895 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8896 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8897 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8898 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8899 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8900 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8901 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8902 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8903 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8904 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8905 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8906 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8907
8908 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8909 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8910 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8911 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8912 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8913 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8914 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8915 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8916 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8917 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8918 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8919 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8920 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8921 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8922 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8923 #if defined(TARGET_PPC64)
8924 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8925 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8926 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8927 #endif
8928 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8929 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8930 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8931 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8932
8933 #undef GEN_LD
8934 #undef GEN_LDU
8935 #undef GEN_LDUX
8936 #undef GEN_LDX_E
8937 #undef GEN_LDS
8938 #define GEN_LD(name, ldop, opc, type) \
8939 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8940 #define GEN_LDU(name, ldop, opc, type) \
8941 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8942 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8943 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8944 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8945 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8946 #define GEN_LDS(name, ldop, op, type) \
8947 GEN_LD(name, ldop, op | 0x20, type) \
8948 GEN_LDU(name, ldop, op | 0x21, type) \
8949 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8950 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8951
8952 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8953 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8954 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8955 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8956 #if defined(TARGET_PPC64)
8957 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8958 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8959 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8960 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8961 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8962 #endif
8963 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8964 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8965
8966 #undef GEN_ST
8967 #undef GEN_STU
8968 #undef GEN_STUX
8969 #undef GEN_STX_E
8970 #undef GEN_STS
8971 #define GEN_ST(name, stop, opc, type) \
8972 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8973 #define GEN_STU(name, stop, opc, type) \
8974 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8975 #define GEN_STUX(name, stop, opc2, opc3, type) \
8976 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8977 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8978 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8979 #define GEN_STS(name, stop, op, type) \
8980 GEN_ST(name, stop, op | 0x20, type) \
8981 GEN_STU(name, stop, op | 0x21, type) \
8982 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8983 GEN_STX(name, stop, 0x17, op | 0x00, type)
8984
8985 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8986 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8987 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8988 #if defined(TARGET_PPC64)
8989 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8990 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8991 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8992 #endif
8993 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8994 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8995
8996 #undef GEN_LDF
8997 #undef GEN_LDUF
8998 #undef GEN_LDUXF
8999 #undef GEN_LDXF
9000 #undef GEN_LDFS
9001 #define GEN_LDF(name, ldop, opc, type) \
9002 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9003 #define GEN_LDUF(name, ldop, opc, type) \
9004 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9005 #define GEN_LDUXF(name, ldop, opc, type) \
9006 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9007 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9008 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9009 #define GEN_LDFS(name, ldop, op, type) \
9010 GEN_LDF(name, ldop, op | 0x20, type) \
9011 GEN_LDUF(name, ldop, op | 0x21, type) \
9012 GEN_LDUXF(name, ldop, op | 0x01, type) \
9013 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9014
9015 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
9016 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
9017
9018 #undef GEN_STF
9019 #undef GEN_STUF
9020 #undef GEN_STUXF
9021 #undef GEN_STXF
9022 #undef GEN_STFS
9023 #define GEN_STF(name, stop, opc, type) \
9024 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9025 #define GEN_STUF(name, stop, opc, type) \
9026 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9027 #define GEN_STUXF(name, stop, opc, type) \
9028 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9029 #define GEN_STXF(name, stop, opc2, opc3, type) \
9030 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9031 #define GEN_STFS(name, stop, op, type) \
9032 GEN_STF(name, stop, op | 0x20, type) \
9033 GEN_STUF(name, stop, op | 0x21, type) \
9034 GEN_STUXF(name, stop, op | 0x01, type) \
9035 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9036
9037 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
9038 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
9039 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
9040
9041 #undef GEN_CRLOGIC
9042 #define GEN_CRLOGIC(name, tcg_op, opc) \
9043 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9044 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
9045 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
9046 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
9047 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9048 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9049 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9050 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9051 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9052
9053 #undef GEN_MAC_HANDLER
9054 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9055 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9056 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9057 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9058 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9059 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9060 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9061 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9062 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9063 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9064 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9065 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9066 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9067 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9068 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9069 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9070 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9071 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9072 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9073 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9074 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9075 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9076 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9077 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9078 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9079 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9080 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9081 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9082 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9083 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9084 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9085 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9086 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9087 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9088 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9089 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9090 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9091 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9092 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9093 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9094 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9095 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9096 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9097 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9098
9099 #undef GEN_VR_LDX
9100 #undef GEN_VR_STX
9101 #undef GEN_VR_LVE
9102 #undef GEN_VR_STVE
9103 #define GEN_VR_LDX(name, opc2, opc3) \
9104 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9105 #define GEN_VR_STX(name, opc2, opc3) \
9106 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9107 #define GEN_VR_LVE(name, opc2, opc3) \
9108 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9109 #define GEN_VR_STVE(name, opc2, opc3) \
9110 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9111 GEN_VR_LDX(lvx, 0x07, 0x03),
9112 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9113 GEN_VR_LVE(bx, 0x07, 0x00),
9114 GEN_VR_LVE(hx, 0x07, 0x01),
9115 GEN_VR_LVE(wx, 0x07, 0x02),
9116 GEN_VR_STX(svx, 0x07, 0x07),
9117 GEN_VR_STX(svxl, 0x07, 0x0F),
9118 GEN_VR_STVE(bx, 0x07, 0x04),
9119 GEN_VR_STVE(hx, 0x07, 0x05),
9120 GEN_VR_STVE(wx, 0x07, 0x06),
9121
9122 #undef GEN_VX_LOGICAL
9123 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9124 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9125 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9126 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9127 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9128 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9129 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9130
9131 #undef GEN_VXFORM
9132 #define GEN_VXFORM(name, opc2, opc3) \
9133 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9134 GEN_VXFORM(vaddubm, 0, 0),
9135 GEN_VXFORM(vadduhm, 0, 1),
9136 GEN_VXFORM(vadduwm, 0, 2),
9137 GEN_VXFORM(vsububm, 0, 16),
9138 GEN_VXFORM(vsubuhm, 0, 17),
9139 GEN_VXFORM(vsubuwm, 0, 18),
9140 GEN_VXFORM(vmaxub, 1, 0),
9141 GEN_VXFORM(vmaxuh, 1, 1),
9142 GEN_VXFORM(vmaxuw, 1, 2),
9143 GEN_VXFORM(vmaxsb, 1, 4),
9144 GEN_VXFORM(vmaxsh, 1, 5),
9145 GEN_VXFORM(vmaxsw, 1, 6),
9146 GEN_VXFORM(vminub, 1, 8),
9147 GEN_VXFORM(vminuh, 1, 9),
9148 GEN_VXFORM(vminuw, 1, 10),
9149 GEN_VXFORM(vminsb, 1, 12),
9150 GEN_VXFORM(vminsh, 1, 13),
9151 GEN_VXFORM(vminsw, 1, 14),
9152 GEN_VXFORM(vavgub, 1, 16),
9153 GEN_VXFORM(vavguh, 1, 17),
9154 GEN_VXFORM(vavguw, 1, 18),
9155 GEN_VXFORM(vavgsb, 1, 20),
9156 GEN_VXFORM(vavgsh, 1, 21),
9157 GEN_VXFORM(vavgsw, 1, 22),
9158 GEN_VXFORM(vmrghb, 6, 0),
9159 GEN_VXFORM(vmrghh, 6, 1),
9160 GEN_VXFORM(vmrghw, 6, 2),
9161 GEN_VXFORM(vmrglb, 6, 4),
9162 GEN_VXFORM(vmrglh, 6, 5),
9163 GEN_VXFORM(vmrglw, 6, 6),
9164 GEN_VXFORM(vmuloub, 4, 0),
9165 GEN_VXFORM(vmulouh, 4, 1),
9166 GEN_VXFORM(vmulosb, 4, 4),
9167 GEN_VXFORM(vmulosh, 4, 5),
9168 GEN_VXFORM(vmuleub, 4, 8),
9169 GEN_VXFORM(vmuleuh, 4, 9),
9170 GEN_VXFORM(vmulesb, 4, 12),
9171 GEN_VXFORM(vmulesh, 4, 13),
9172 GEN_VXFORM(vslb, 2, 4),
9173 GEN_VXFORM(vslh, 2, 5),
9174 GEN_VXFORM(vslw, 2, 6),
9175 GEN_VXFORM(vsrb, 2, 8),
9176 GEN_VXFORM(vsrh, 2, 9),
9177 GEN_VXFORM(vsrw, 2, 10),
9178 GEN_VXFORM(vsrab, 2, 12),
9179 GEN_VXFORM(vsrah, 2, 13),
9180 GEN_VXFORM(vsraw, 2, 14),
9181 GEN_VXFORM(vslo, 6, 16),
9182 GEN_VXFORM(vsro, 6, 17),
9183 GEN_VXFORM(vaddcuw, 0, 6),
9184 GEN_VXFORM(vsubcuw, 0, 22),
9185 GEN_VXFORM(vaddubs, 0, 8),
9186 GEN_VXFORM(vadduhs, 0, 9),
9187 GEN_VXFORM(vadduws, 0, 10),
9188 GEN_VXFORM(vaddsbs, 0, 12),
9189 GEN_VXFORM(vaddshs, 0, 13),
9190 GEN_VXFORM(vaddsws, 0, 14),
9191 GEN_VXFORM(vsububs, 0, 24),
9192 GEN_VXFORM(vsubuhs, 0, 25),
9193 GEN_VXFORM(vsubuws, 0, 26),
9194 GEN_VXFORM(vsubsbs, 0, 28),
9195 GEN_VXFORM(vsubshs, 0, 29),
9196 GEN_VXFORM(vsubsws, 0, 30),
9197 GEN_VXFORM(vrlb, 2, 0),
9198 GEN_VXFORM(vrlh, 2, 1),
9199 GEN_VXFORM(vrlw, 2, 2),
9200 GEN_VXFORM(vsl, 2, 7),
9201 GEN_VXFORM(vsr, 2, 11),
9202 GEN_VXFORM(vpkuhum, 7, 0),
9203 GEN_VXFORM(vpkuwum, 7, 1),
9204 GEN_VXFORM(vpkuhus, 7, 2),
9205 GEN_VXFORM(vpkuwus, 7, 3),
9206 GEN_VXFORM(vpkshus, 7, 4),
9207 GEN_VXFORM(vpkswus, 7, 5),
9208 GEN_VXFORM(vpkshss, 7, 6),
9209 GEN_VXFORM(vpkswss, 7, 7),
9210 GEN_VXFORM(vpkpx, 7, 12),
9211 GEN_VXFORM(vsum4ubs, 4, 24),
9212 GEN_VXFORM(vsum4sbs, 4, 28),
9213 GEN_VXFORM(vsum4shs, 4, 25),
9214 GEN_VXFORM(vsum2sws, 4, 26),
9215 GEN_VXFORM(vsumsws, 4, 30),
9216 GEN_VXFORM(vaddfp, 5, 0),
9217 GEN_VXFORM(vsubfp, 5, 1),
9218 GEN_VXFORM(vmaxfp, 5, 16),
9219 GEN_VXFORM(vminfp, 5, 17),
9220
9221 #undef GEN_VXRFORM1
9222 #undef GEN_VXRFORM
9223 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9224 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9225 #define GEN_VXRFORM(name, opc2, opc3) \
9226 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9227 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9228 GEN_VXRFORM(vcmpequb, 3, 0)
9229 GEN_VXRFORM(vcmpequh, 3, 1)
9230 GEN_VXRFORM(vcmpequw, 3, 2)
9231 GEN_VXRFORM(vcmpgtsb, 3, 12)
9232 GEN_VXRFORM(vcmpgtsh, 3, 13)
9233 GEN_VXRFORM(vcmpgtsw, 3, 14)
9234 GEN_VXRFORM(vcmpgtub, 3, 8)
9235 GEN_VXRFORM(vcmpgtuh, 3, 9)
9236 GEN_VXRFORM(vcmpgtuw, 3, 10)
9237 GEN_VXRFORM(vcmpeqfp, 3, 3)
9238 GEN_VXRFORM(vcmpgefp, 3, 7)
9239 GEN_VXRFORM(vcmpgtfp, 3, 11)
9240 GEN_VXRFORM(vcmpbfp, 3, 15)
9241
9242 #undef GEN_VXFORM_SIMM
9243 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9244 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9245 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9246 GEN_VXFORM_SIMM(vspltish, 6, 13),
9247 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9248
9249 #undef GEN_VXFORM_NOA
9250 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9251 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9252 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9253 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9254 GEN_VXFORM_NOA(vupklsb, 7, 10),
9255 GEN_VXFORM_NOA(vupklsh, 7, 11),
9256 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9257 GEN_VXFORM_NOA(vupklpx, 7, 15),
9258 GEN_VXFORM_NOA(vrefp, 5, 4),
9259 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9260 GEN_VXFORM_NOA(vexptefp, 5, 6),
9261 GEN_VXFORM_NOA(vlogefp, 5, 7),
9262 GEN_VXFORM_NOA(vrfim, 5, 8),
9263 GEN_VXFORM_NOA(vrfin, 5, 9),
9264 GEN_VXFORM_NOA(vrfip, 5, 10),
9265 GEN_VXFORM_NOA(vrfiz, 5, 11),
9266
9267 #undef GEN_VXFORM_UIMM
9268 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9269 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9270 GEN_VXFORM_UIMM(vspltb, 6, 8),
9271 GEN_VXFORM_UIMM(vsplth, 6, 9),
9272 GEN_VXFORM_UIMM(vspltw, 6, 10),
9273 GEN_VXFORM_UIMM(vcfux, 5, 12),
9274 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9275 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9276 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9277
9278 #undef GEN_VAFORM_PAIRED
9279 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9280 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9281 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9282 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9283 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9284 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9285 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9286 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9287
9288 #undef GEN_SPE
9289 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9290 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9291 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9292 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9293 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9294 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9295 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9296 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9297 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9298 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9299 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9300 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9301 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9302 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9303 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9304 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9305 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9306 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9307 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9308 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9309 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9310 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9311 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9312 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9313 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9314 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9315 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9316 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9317 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9318 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9319 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9320
9321 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9322 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9323 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9324 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9325 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9326 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9327 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9328 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9329 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9330 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9331 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9332 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9333 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9334 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9335
9336 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9337 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9338 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9339 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9340 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9341 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9342 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9343 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9344 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9345 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9346 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9347 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9348 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9349 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9350
9351 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9352 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9353 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9354 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9355 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9356 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9357 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9358 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9359 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9360 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9361 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9362 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9363 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9364 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9365 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9366 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9367
9368 #undef GEN_SPEOP_LDST
9369 #define GEN_SPEOP_LDST(name, opc2, sh) \
9370 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9371 GEN_SPEOP_LDST(evldd, 0x00, 3),
9372 GEN_SPEOP_LDST(evldw, 0x01, 3),
9373 GEN_SPEOP_LDST(evldh, 0x02, 3),
9374 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9375 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9376 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9377 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9378 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9379 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9380 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9381 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9382
9383 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9384 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9385 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9386 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9387 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9388 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9389 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9390 };
9391
9392 #include "helper_regs.h"
9393 #include "translate_init.c"
9394
9395 /*****************************************************************************/
9396 /* Misc PowerPC helpers */
9397 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9398 int flags)
9399 {
9400 #define RGPL 4
9401 #define RFPL 4
9402
9403 int i;
9404
9405 cpu_synchronize_state(env);
9406
9407 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9408 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9409 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9410 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9411 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9412 env->hflags, env->mmu_idx);
9413 #if !defined(NO_TIMER_DUMP)
9414 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9415 #if !defined(CONFIG_USER_ONLY)
9416 " DECR %08" PRIu32
9417 #endif
9418 "\n",
9419 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9420 #if !defined(CONFIG_USER_ONLY)
9421 , cpu_ppc_load_decr(env)
9422 #endif
9423 );
9424 #endif
9425 for (i = 0; i < 32; i++) {
9426 if ((i & (RGPL - 1)) == 0)
9427 cpu_fprintf(f, "GPR%02d", i);
9428 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9429 if ((i & (RGPL - 1)) == (RGPL - 1))
9430 cpu_fprintf(f, "\n");
9431 }
9432 cpu_fprintf(f, "CR ");
9433 for (i = 0; i < 8; i++)
9434 cpu_fprintf(f, "%01x", env->crf[i]);
9435 cpu_fprintf(f, " [");
9436 for (i = 0; i < 8; i++) {
9437 char a = '-';
9438 if (env->crf[i] & 0x08)
9439 a = 'L';
9440 else if (env->crf[i] & 0x04)
9441 a = 'G';
9442 else if (env->crf[i] & 0x02)
9443 a = 'E';
9444 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9445 }
9446 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9447 env->reserve_addr);
9448 for (i = 0; i < 32; i++) {
9449 if ((i & (RFPL - 1)) == 0)
9450 cpu_fprintf(f, "FPR%02d", i);
9451 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9452 if ((i & (RFPL - 1)) == (RFPL - 1))
9453 cpu_fprintf(f, "\n");
9454 }
9455 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9456 #if !defined(CONFIG_USER_ONLY)
9457 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9458 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9459 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9460 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9461
9462 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9463 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9464 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9465 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9466
9467 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9468 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9469 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9470 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9471
9472 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9473 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9474 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9475 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9476 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9477
9478 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9479 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9480 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9481 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9482
9483 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9484 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9485 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9486 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9487
9488 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9489 " EPR " TARGET_FMT_lx "\n",
9490 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9491 env->spr[SPR_BOOKE_EPR]);
9492
9493 /* FSL-specific */
9494 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9495 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9496 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9497 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9498
9499 /*
9500 * IVORs are left out as they are large and do not change often --
9501 * they can be read with "p $ivor0", "p $ivor1", etc.
9502 */
9503 }
9504
9505 #if defined(TARGET_PPC64)
9506 if (env->flags & POWERPC_FLAG_CFAR) {
9507 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9508 }
9509 #endif
9510
9511 switch (env->mmu_model) {
9512 case POWERPC_MMU_32B:
9513 case POWERPC_MMU_601:
9514 case POWERPC_MMU_SOFT_6xx:
9515 case POWERPC_MMU_SOFT_74xx:
9516 #if defined(TARGET_PPC64)
9517 case POWERPC_MMU_64B:
9518 #endif
9519 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9520 break;
9521 case POWERPC_MMU_BOOKE206:
9522 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9523 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9524 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9525 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9526
9527 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9528 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9529 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9530 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9531
9532 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9533 " TLB1CFG " TARGET_FMT_lx "\n",
9534 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9535 env->spr[SPR_BOOKE_TLB1CFG]);
9536 break;
9537 default:
9538 break;
9539 }
9540 #endif
9541
9542 #undef RGPL
9543 #undef RFPL
9544 }
9545
9546 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9547 int flags)
9548 {
9549 #if defined(DO_PPC_STATISTICS)
9550 opc_handler_t **t1, **t2, **t3, *handler;
9551 int op1, op2, op3;
9552
9553 t1 = env->opcodes;
9554 for (op1 = 0; op1 < 64; op1++) {
9555 handler = t1[op1];
9556 if (is_indirect_opcode(handler)) {
9557 t2 = ind_table(handler);
9558 for (op2 = 0; op2 < 32; op2++) {
9559 handler = t2[op2];
9560 if (is_indirect_opcode(handler)) {
9561 t3 = ind_table(handler);
9562 for (op3 = 0; op3 < 32; op3++) {
9563 handler = t3[op3];
9564 if (handler->count == 0)
9565 continue;
9566 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9567 "%016" PRIx64 " %" PRId64 "\n",
9568 op1, op2, op3, op1, (op3 << 5) | op2,
9569 handler->oname,
9570 handler->count, handler->count);
9571 }
9572 } else {
9573 if (handler->count == 0)
9574 continue;
9575 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9576 "%016" PRIx64 " %" PRId64 "\n",
9577 op1, op2, op1, op2, handler->oname,
9578 handler->count, handler->count);
9579 }
9580 }
9581 } else {
9582 if (handler->count == 0)
9583 continue;
9584 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9585 " %" PRId64 "\n",
9586 op1, op1, handler->oname,
9587 handler->count, handler->count);
9588 }
9589 }
9590 #endif
9591 }
9592
9593 /*****************************************************************************/
9594 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9595 TranslationBlock *tb,
9596 int search_pc)
9597 {
9598 DisasContext ctx, *ctxp = &ctx;
9599 opc_handler_t **table, *handler;
9600 target_ulong pc_start;
9601 uint16_t *gen_opc_end;
9602 CPUBreakpoint *bp;
9603 int j, lj = -1;
9604 int num_insns;
9605 int max_insns;
9606
9607 pc_start = tb->pc;
9608 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9609 ctx.nip = pc_start;
9610 ctx.tb = tb;
9611 ctx.exception = POWERPC_EXCP_NONE;
9612 ctx.spr_cb = env->spr_cb;
9613 ctx.mem_idx = env->mmu_idx;
9614 ctx.access_type = -1;
9615 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9616 #if defined(TARGET_PPC64)
9617 ctx.sf_mode = msr_is_64bit(env, env->msr);
9618 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9619 #endif
9620 ctx.fpu_enabled = msr_fp;
9621 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9622 ctx.spe_enabled = msr_spe;
9623 else
9624 ctx.spe_enabled = 0;
9625 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9626 ctx.altivec_enabled = msr_vr;
9627 else
9628 ctx.altivec_enabled = 0;
9629 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9630 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9631 else
9632 ctx.singlestep_enabled = 0;
9633 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9634 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9635 if (unlikely(env->singlestep_enabled))
9636 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9637 #if defined (DO_SINGLE_STEP) && 0
9638 /* Single step trace mode */
9639 msr_se = 1;
9640 #endif
9641 num_insns = 0;
9642 max_insns = tb->cflags & CF_COUNT_MASK;
9643 if (max_insns == 0)
9644 max_insns = CF_COUNT_MASK;
9645
9646 gen_tb_start();
9647 /* Set env in case of segfault during code fetch */
9648 while (ctx.exception == POWERPC_EXCP_NONE
9649 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9650 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9651 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9652 if (bp->pc == ctx.nip) {
9653 gen_debug_exception(ctxp);
9654 break;
9655 }
9656 }
9657 }
9658 if (unlikely(search_pc)) {
9659 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9660 if (lj < j) {
9661 lj++;
9662 while (lj < j)
9663 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9664 }
9665 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9666 tcg_ctx.gen_opc_instr_start[lj] = 1;
9667 tcg_ctx.gen_opc_icount[lj] = num_insns;
9668 }
9669 LOG_DISAS("----------------\n");
9670 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9671 ctx.nip, ctx.mem_idx, (int)msr_ir);
9672 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9673 gen_io_start();
9674 if (unlikely(ctx.le_mode)) {
9675 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9676 } else {
9677 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9678 }
9679 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9680 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9681 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9682 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9683 tcg_gen_debug_insn_start(ctx.nip);
9684 }
9685 ctx.nip += 4;
9686 table = env->opcodes;
9687 num_insns++;
9688 handler = table[opc1(ctx.opcode)];
9689 if (is_indirect_opcode(handler)) {
9690 table = ind_table(handler);
9691 handler = table[opc2(ctx.opcode)];
9692 if (is_indirect_opcode(handler)) {
9693 table = ind_table(handler);
9694 handler = table[opc3(ctx.opcode)];
9695 }
9696 }
9697 /* Is opcode *REALLY* valid ? */
9698 if (unlikely(handler->handler == &gen_invalid)) {
9699 if (qemu_log_enabled()) {
9700 qemu_log("invalid/unsupported opcode: "
9701 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9702 opc1(ctx.opcode), opc2(ctx.opcode),
9703 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9704 }
9705 } else {
9706 uint32_t inval;
9707
9708 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9709 inval = handler->inval2;
9710 } else {
9711 inval = handler->inval1;
9712 }
9713
9714 if (unlikely((ctx.opcode & inval) != 0)) {
9715 if (qemu_log_enabled()) {
9716 qemu_log("invalid bits: %08x for opcode: "
9717 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9718 ctx.opcode & inval, opc1(ctx.opcode),
9719 opc2(ctx.opcode), opc3(ctx.opcode),
9720 ctx.opcode, ctx.nip - 4);
9721 }
9722 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9723 break;
9724 }
9725 }
9726 (*(handler->handler))(&ctx);
9727 #if defined(DO_PPC_STATISTICS)
9728 handler->count++;
9729 #endif
9730 /* Check trace mode exceptions */
9731 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9732 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9733 ctx.exception != POWERPC_SYSCALL &&
9734 ctx.exception != POWERPC_EXCP_TRAP &&
9735 ctx.exception != POWERPC_EXCP_BRANCH)) {
9736 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9737 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9738 (env->singlestep_enabled) ||
9739 singlestep ||
9740 num_insns >= max_insns)) {
9741 /* if we reach a page boundary or are single stepping, stop
9742 * generation
9743 */
9744 break;
9745 }
9746 }
9747 if (tb->cflags & CF_LAST_IO)
9748 gen_io_end();
9749 if (ctx.exception == POWERPC_EXCP_NONE) {
9750 gen_goto_tb(&ctx, 0, ctx.nip);
9751 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9752 if (unlikely(env->singlestep_enabled)) {
9753 gen_debug_exception(ctxp);
9754 }
9755 /* Generate the return instruction */
9756 tcg_gen_exit_tb(0);
9757 }
9758 gen_tb_end(tb, num_insns);
9759 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9760 if (unlikely(search_pc)) {
9761 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9762 lj++;
9763 while (lj <= j)
9764 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9765 } else {
9766 tb->size = ctx.nip - pc_start;
9767 tb->icount = num_insns;
9768 }
9769 #if defined(DEBUG_DISAS)
9770 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9771 int flags;
9772 flags = env->bfd_mach;
9773 flags |= ctx.le_mode << 16;
9774 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9775 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9776 qemu_log("\n");
9777 }
9778 #endif
9779 }
9780
9781 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9782 {
9783 gen_intermediate_code_internal(env, tb, 0);
9784 }
9785
9786 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9787 {
9788 gen_intermediate_code_internal(env, tb, 1);
9789 }
9790
9791 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9792 {
9793 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9794 }
Qemu copy for testing