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ppc tcg: fix wrong bit/mask of wrteei
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31 #include "host-utils.h"
32
33 #include "helper.h"
34 #define GEN_HELPER 1
35 #include "helper.h"
36
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
40
41 /* Include definitions for instructions classes and implementations flags */
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DISAS(...) do { } while (0)
49 #endif
50 /*****************************************************************************/
51 /* Code translation helpers */
52
53 /* global register indexes */
54 static TCGv_ptr cpu_env;
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 #if !defined(TARGET_PPC64)
57 + 10*4 + 22*5 /* SPE GPRh */
58 #endif
59 + 10*4 + 22*5 /* FPR */
60 + 2*(10*6 + 22*7) /* AVRh, AVRl */
61 + 8*5 /* CRF */];
62 static TCGv cpu_gpr[32];
63 #if !defined(TARGET_PPC64)
64 static TCGv cpu_gprh[32];
65 #endif
66 static TCGv_i64 cpu_fpr[32];
67 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
68 static TCGv_i32 cpu_crf[8];
69 static TCGv cpu_nip;
70 static TCGv cpu_msr;
71 static TCGv cpu_ctr;
72 static TCGv cpu_lr;
73 static TCGv cpu_xer;
74 static TCGv cpu_reserve;
75 static TCGv_i32 cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91
92 p = cpu_reg_names;
93 cpu_reg_names_size = sizeof(cpu_reg_names);
94
95 for (i = 0; i < 8; i++) {
96 snprintf(p, cpu_reg_names_size, "crf%d", i);
97 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
98 offsetof(CPUState, crf[i]), p);
99 p += 5;
100 cpu_reg_names_size -= 5;
101 }
102
103 for (i = 0; i < 32; i++) {
104 snprintf(p, cpu_reg_names_size, "r%d", i);
105 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
106 offsetof(CPUState, gpr[i]), p);
107 p += (i < 10) ? 3 : 4;
108 cpu_reg_names_size -= (i < 10) ? 3 : 4;
109 #if !defined(TARGET_PPC64)
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
112 offsetof(CPUState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115 #endif
116
117 snprintf(p, cpu_reg_names_size, "fp%d", i);
118 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
119 offsetof(CPUState, fpr[i]), p);
120 p += (i < 10) ? 4 : 5;
121 cpu_reg_names_size -= (i < 10) ? 4 : 5;
122
123 snprintf(p, cpu_reg_names_size, "avr%dH", i);
124 #ifdef WORDS_BIGENDIAN
125 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
126 offsetof(CPUState, avr[i].u64[0]), p);
127 #else
128 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
129 offsetof(CPUState, avr[i].u64[1]), p);
130 #endif
131 p += (i < 10) ? 6 : 7;
132 cpu_reg_names_size -= (i < 10) ? 6 : 7;
133
134 snprintf(p, cpu_reg_names_size, "avr%dL", i);
135 #ifdef WORDS_BIGENDIAN
136 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
137 offsetof(CPUState, avr[i].u64[1]), p);
138 #else
139 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
140 offsetof(CPUState, avr[i].u64[0]), p);
141 #endif
142 p += (i < 10) ? 6 : 7;
143 cpu_reg_names_size -= (i < 10) ? 6 : 7;
144 }
145
146 cpu_nip = tcg_global_mem_new(TCG_AREG0,
147 offsetof(CPUState, nip), "nip");
148
149 cpu_msr = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUState, msr), "msr");
151
152 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUState, ctr), "ctr");
154
155 cpu_lr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUState, lr), "lr");
157
158 cpu_xer = tcg_global_mem_new(TCG_AREG0,
159 offsetof(CPUState, xer), "xer");
160
161 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUState, reserve), "reserve");
163
164 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
165 offsetof(CPUState, fpscr), "fpscr");
166
167 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
168 offsetof(CPUState, access_type), "access_type");
169
170 /* register helpers */
171 #define GEN_HELPER 2
172 #include "helper.h"
173
174 done_init = 1;
175 }
176
177 /* internal defines */
178 typedef struct DisasContext {
179 struct TranslationBlock *tb;
180 target_ulong nip;
181 uint32_t opcode;
182 uint32_t exception;
183 /* Routine used to access memory */
184 int mem_idx;
185 int access_type;
186 /* Translation flags */
187 int le_mode;
188 #if defined(TARGET_PPC64)
189 int sf_mode;
190 #endif
191 int fpu_enabled;
192 int altivec_enabled;
193 int spe_enabled;
194 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
195 int singlestep_enabled;
196 } DisasContext;
197
198 struct opc_handler_t {
199 /* invalid bits */
200 uint32_t inval;
201 /* instruction type */
202 uint64_t type;
203 /* handler */
204 void (*handler)(DisasContext *ctx);
205 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
206 const char *oname;
207 #endif
208 #if defined(DO_PPC_STATISTICS)
209 uint64_t count;
210 #endif
211 };
212
213 static always_inline void gen_reset_fpstatus (void)
214 {
215 #ifdef CONFIG_SOFTFLOAT
216 gen_helper_reset_fpstatus();
217 #endif
218 }
219
220 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
221 {
222 TCGv_i32 t0 = tcg_temp_new_i32();
223
224 if (set_fprf != 0) {
225 /* This case might be optimized later */
226 tcg_gen_movi_i32(t0, 1);
227 gen_helper_compute_fprf(t0, arg, t0);
228 if (unlikely(set_rc)) {
229 tcg_gen_mov_i32(cpu_crf[1], t0);
230 }
231 gen_helper_float_check_status();
232 } else if (unlikely(set_rc)) {
233 /* We always need to compute fpcc */
234 tcg_gen_movi_i32(t0, 0);
235 gen_helper_compute_fprf(t0, arg, t0);
236 tcg_gen_mov_i32(cpu_crf[1], t0);
237 }
238
239 tcg_temp_free_i32(t0);
240 }
241
242 static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
243 {
244 if (ctx->access_type != access_type) {
245 tcg_gen_movi_i32(cpu_access_type, access_type);
246 ctx->access_type = access_type;
247 }
248 }
249
250 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
251 {
252 #if defined(TARGET_PPC64)
253 if (ctx->sf_mode)
254 tcg_gen_movi_tl(cpu_nip, nip);
255 else
256 #endif
257 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
258 }
259
260 static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
261 {
262 TCGv_i32 t0, t1;
263 if (ctx->exception == POWERPC_EXCP_NONE) {
264 gen_update_nip(ctx, ctx->nip);
265 }
266 t0 = tcg_const_i32(excp);
267 t1 = tcg_const_i32(error);
268 gen_helper_raise_exception_err(t0, t1);
269 tcg_temp_free_i32(t0);
270 tcg_temp_free_i32(t1);
271 ctx->exception = (excp);
272 }
273
274 static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
275 {
276 TCGv_i32 t0;
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->nip);
279 }
280 t0 = tcg_const_i32(excp);
281 gen_helper_raise_exception(t0);
282 tcg_temp_free_i32(t0);
283 ctx->exception = (excp);
284 }
285
286 static always_inline void gen_debug_exception (DisasContext *ctx)
287 {
288 TCGv_i32 t0;
289
290 if (ctx->exception != POWERPC_EXCP_BRANCH)
291 gen_update_nip(ctx, ctx->nip);
292 t0 = tcg_const_i32(EXCP_DEBUG);
293 gen_helper_raise_exception(t0);
294 tcg_temp_free_i32(t0);
295 }
296
297 static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
298 {
299 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
300 }
301
302 /* Stop translation */
303 static always_inline void gen_stop_exception (DisasContext *ctx)
304 {
305 gen_update_nip(ctx, ctx->nip);
306 ctx->exception = POWERPC_EXCP_STOP;
307 }
308
309 /* No need to update nip here, as execution flow will change */
310 static always_inline void gen_sync_exception (DisasContext *ctx)
311 {
312 ctx->exception = POWERPC_EXCP_SYNC;
313 }
314
315 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
316 GEN_OPCODE(name, opc1, opc2, opc3, inval, type)
317
318 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
319 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type)
320
321 typedef struct opcode_t {
322 unsigned char opc1, opc2, opc3;
323 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
324 unsigned char pad[5];
325 #else
326 unsigned char pad[1];
327 #endif
328 opc_handler_t handler;
329 const char *oname;
330 } opcode_t;
331
332 /*****************************************************************************/
333 /*** Instruction decoding ***/
334 #define EXTRACT_HELPER(name, shift, nb) \
335 static always_inline uint32_t name (uint32_t opcode) \
336 { \
337 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
338 }
339
340 #define EXTRACT_SHELPER(name, shift, nb) \
341 static always_inline int32_t name (uint32_t opcode) \
342 { \
343 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
344 }
345
346 /* Opcode part 1 */
347 EXTRACT_HELPER(opc1, 26, 6);
348 /* Opcode part 2 */
349 EXTRACT_HELPER(opc2, 1, 5);
350 /* Opcode part 3 */
351 EXTRACT_HELPER(opc3, 6, 5);
352 /* Update Cr0 flags */
353 EXTRACT_HELPER(Rc, 0, 1);
354 /* Destination */
355 EXTRACT_HELPER(rD, 21, 5);
356 /* Source */
357 EXTRACT_HELPER(rS, 21, 5);
358 /* First operand */
359 EXTRACT_HELPER(rA, 16, 5);
360 /* Second operand */
361 EXTRACT_HELPER(rB, 11, 5);
362 /* Third operand */
363 EXTRACT_HELPER(rC, 6, 5);
364 /*** Get CRn ***/
365 EXTRACT_HELPER(crfD, 23, 3);
366 EXTRACT_HELPER(crfS, 18, 3);
367 EXTRACT_HELPER(crbD, 21, 5);
368 EXTRACT_HELPER(crbA, 16, 5);
369 EXTRACT_HELPER(crbB, 11, 5);
370 /* SPR / TBL */
371 EXTRACT_HELPER(_SPR, 11, 10);
372 static always_inline uint32_t SPR (uint32_t opcode)
373 {
374 uint32_t sprn = _SPR(opcode);
375
376 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
377 }
378 /*** Get constants ***/
379 EXTRACT_HELPER(IMM, 12, 8);
380 /* 16 bits signed immediate value */
381 EXTRACT_SHELPER(SIMM, 0, 16);
382 /* 16 bits unsigned immediate value */
383 EXTRACT_HELPER(UIMM, 0, 16);
384 /* 5 bits signed immediate value */
385 EXTRACT_HELPER(SIMM5, 16, 5);
386 /* 5 bits signed immediate value */
387 EXTRACT_HELPER(UIMM5, 16, 5);
388 /* Bit count */
389 EXTRACT_HELPER(NB, 11, 5);
390 /* Shift count */
391 EXTRACT_HELPER(SH, 11, 5);
392 /* Vector shift count */
393 EXTRACT_HELPER(VSH, 6, 4);
394 /* Mask start */
395 EXTRACT_HELPER(MB, 6, 5);
396 /* Mask end */
397 EXTRACT_HELPER(ME, 1, 5);
398 /* Trap operand */
399 EXTRACT_HELPER(TO, 21, 5);
400
401 EXTRACT_HELPER(CRM, 12, 8);
402 EXTRACT_HELPER(FM, 17, 8);
403 EXTRACT_HELPER(SR, 16, 4);
404 EXTRACT_HELPER(FPIMM, 12, 4);
405
406 /*** Jump target decoding ***/
407 /* Displacement */
408 EXTRACT_SHELPER(d, 0, 16);
409 /* Immediate address */
410 static always_inline target_ulong LI (uint32_t opcode)
411 {
412 return (opcode >> 0) & 0x03FFFFFC;
413 }
414
415 static always_inline uint32_t BD (uint32_t opcode)
416 {
417 return (opcode >> 0) & 0xFFFC;
418 }
419
420 EXTRACT_HELPER(BO, 21, 5);
421 EXTRACT_HELPER(BI, 16, 5);
422 /* Absolute/relative address */
423 EXTRACT_HELPER(AA, 1, 1);
424 /* Link */
425 EXTRACT_HELPER(LK, 0, 1);
426
427 /* Create a mask between <start> and <end> bits */
428 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
429 {
430 target_ulong ret;
431
432 #if defined(TARGET_PPC64)
433 if (likely(start == 0)) {
434 ret = UINT64_MAX << (63 - end);
435 } else if (likely(end == 63)) {
436 ret = UINT64_MAX >> start;
437 }
438 #else
439 if (likely(start == 0)) {
440 ret = UINT32_MAX << (31 - end);
441 } else if (likely(end == 31)) {
442 ret = UINT32_MAX >> start;
443 }
444 #endif
445 else {
446 ret = (((target_ulong)(-1ULL)) >> (start)) ^
447 (((target_ulong)(-1ULL) >> (end)) >> 1);
448 if (unlikely(start > end))
449 return ~ret;
450 }
451
452 return ret;
453 }
454
455 /*****************************************************************************/
456 /* PowerPC instructions table */
457
458 #if defined(DO_PPC_STATISTICS)
459 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
460 { \
461 .opc1 = op1, \
462 .opc2 = op2, \
463 .opc3 = op3, \
464 .pad = { 0, }, \
465 .handler = { \
466 .inval = invl, \
467 .type = _typ, \
468 .handler = &gen_##name, \
469 .oname = stringify(name), \
470 }, \
471 .oname = stringify(name), \
472 }
473 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
474 { \
475 .opc1 = op1, \
476 .opc2 = op2, \
477 .opc3 = op3, \
478 .pad = { 0, }, \
479 .handler = { \
480 .inval = invl, \
481 .type = _typ, \
482 .handler = &gen_##name, \
483 .oname = onam, \
484 }, \
485 .oname = onam, \
486 }
487 #else
488 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
489 { \
490 .opc1 = op1, \
491 .opc2 = op2, \
492 .opc3 = op3, \
493 .pad = { 0, }, \
494 .handler = { \
495 .inval = invl, \
496 .type = _typ, \
497 .handler = &gen_##name, \
498 }, \
499 .oname = stringify(name), \
500 }
501 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
502 { \
503 .opc1 = op1, \
504 .opc2 = op2, \
505 .opc3 = op3, \
506 .pad = { 0, }, \
507 .handler = { \
508 .inval = invl, \
509 .type = _typ, \
510 .handler = &gen_##name, \
511 }, \
512 .oname = onam, \
513 }
514 #endif
515
516 /* SPR load/store helpers */
517 static always_inline void gen_load_spr(TCGv t, int reg)
518 {
519 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
520 }
521
522 static always_inline void gen_store_spr(int reg, TCGv t)
523 {
524 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
525 }
526
527 /* Invalid instruction */
528 static void gen_invalid(DisasContext *ctx)
529 {
530 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
531 }
532
533 static opc_handler_t invalid_handler = {
534 .inval = 0xFFFFFFFF,
535 .type = PPC_NONE,
536 .handler = gen_invalid,
537 };
538
539 /*** Integer comparison ***/
540
541 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
542 {
543 int l1, l2, l3;
544
545 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
546 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
547 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
548
549 l1 = gen_new_label();
550 l2 = gen_new_label();
551 l3 = gen_new_label();
552 if (s) {
553 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
554 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
555 } else {
556 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
557 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
558 }
559 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
560 tcg_gen_br(l3);
561 gen_set_label(l1);
562 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
563 tcg_gen_br(l3);
564 gen_set_label(l2);
565 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
566 gen_set_label(l3);
567 }
568
569 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
570 {
571 TCGv t0 = tcg_const_local_tl(arg1);
572 gen_op_cmp(arg0, t0, s, crf);
573 tcg_temp_free(t0);
574 }
575
576 #if defined(TARGET_PPC64)
577 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
578 {
579 TCGv t0, t1;
580 t0 = tcg_temp_local_new();
581 t1 = tcg_temp_local_new();
582 if (s) {
583 tcg_gen_ext32s_tl(t0, arg0);
584 tcg_gen_ext32s_tl(t1, arg1);
585 } else {
586 tcg_gen_ext32u_tl(t0, arg0);
587 tcg_gen_ext32u_tl(t1, arg1);
588 }
589 gen_op_cmp(t0, t1, s, crf);
590 tcg_temp_free(t1);
591 tcg_temp_free(t0);
592 }
593
594 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
595 {
596 TCGv t0 = tcg_const_local_tl(arg1);
597 gen_op_cmp32(arg0, t0, s, crf);
598 tcg_temp_free(t0);
599 }
600 #endif
601
602 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
603 {
604 #if defined(TARGET_PPC64)
605 if (!(ctx->sf_mode))
606 gen_op_cmpi32(reg, 0, 1, 0);
607 else
608 #endif
609 gen_op_cmpi(reg, 0, 1, 0);
610 }
611
612 /* cmp */
613 static void gen_cmp(DisasContext *ctx)
614 {
615 #if defined(TARGET_PPC64)
616 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
617 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
618 1, crfD(ctx->opcode));
619 else
620 #endif
621 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
622 1, crfD(ctx->opcode));
623 }
624
625 /* cmpi */
626 static void gen_cmpi(DisasContext *ctx)
627 {
628 #if defined(TARGET_PPC64)
629 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
630 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
631 1, crfD(ctx->opcode));
632 else
633 #endif
634 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
635 1, crfD(ctx->opcode));
636 }
637
638 /* cmpl */
639 static void gen_cmpl(DisasContext *ctx)
640 {
641 #if defined(TARGET_PPC64)
642 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
643 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
644 0, crfD(ctx->opcode));
645 else
646 #endif
647 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
648 0, crfD(ctx->opcode));
649 }
650
651 /* cmpli */
652 static void gen_cmpli(DisasContext *ctx)
653 {
654 #if defined(TARGET_PPC64)
655 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
656 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
657 0, crfD(ctx->opcode));
658 else
659 #endif
660 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
661 0, crfD(ctx->opcode));
662 }
663
664 /* isel (PowerPC 2.03 specification) */
665 static void gen_isel(DisasContext *ctx)
666 {
667 int l1, l2;
668 uint32_t bi = rC(ctx->opcode);
669 uint32_t mask;
670 TCGv_i32 t0;
671
672 l1 = gen_new_label();
673 l2 = gen_new_label();
674
675 mask = 1 << (3 - (bi & 0x03));
676 t0 = tcg_temp_new_i32();
677 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
678 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
679 if (rA(ctx->opcode) == 0)
680 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
681 else
682 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
683 tcg_gen_br(l2);
684 gen_set_label(l1);
685 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
686 gen_set_label(l2);
687 tcg_temp_free_i32(t0);
688 }
689
690 /*** Integer arithmetic ***/
691
692 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
693 {
694 int l1;
695 TCGv t0;
696
697 l1 = gen_new_label();
698 /* Start with XER OV disabled, the most likely case */
699 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
700 t0 = tcg_temp_local_new();
701 tcg_gen_xor_tl(t0, arg0, arg1);
702 #if defined(TARGET_PPC64)
703 if (!ctx->sf_mode)
704 tcg_gen_ext32s_tl(t0, t0);
705 #endif
706 if (sub)
707 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
708 else
709 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
710 tcg_gen_xor_tl(t0, arg1, arg2);
711 #if defined(TARGET_PPC64)
712 if (!ctx->sf_mode)
713 tcg_gen_ext32s_tl(t0, t0);
714 #endif
715 if (sub)
716 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
717 else
718 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
719 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
720 gen_set_label(l1);
721 tcg_temp_free(t0);
722 }
723
724 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
725 {
726 int l1 = gen_new_label();
727
728 #if defined(TARGET_PPC64)
729 if (!(ctx->sf_mode)) {
730 TCGv t0, t1;
731 t0 = tcg_temp_new();
732 t1 = tcg_temp_new();
733
734 tcg_gen_ext32u_tl(t0, arg1);
735 tcg_gen_ext32u_tl(t1, arg2);
736 if (sub) {
737 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
738 } else {
739 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
740 }
741 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
742 gen_set_label(l1);
743 tcg_temp_free(t0);
744 tcg_temp_free(t1);
745 } else
746 #endif
747 {
748 if (sub) {
749 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
750 } else {
751 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
752 }
753 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
754 gen_set_label(l1);
755 }
756 }
757
758 /* Common add function */
759 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
760 int add_ca, int compute_ca, int compute_ov)
761 {
762 TCGv t0, t1;
763
764 if ((!compute_ca && !compute_ov) ||
765 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
766 t0 = ret;
767 } else {
768 t0 = tcg_temp_local_new();
769 }
770
771 if (add_ca) {
772 t1 = tcg_temp_local_new();
773 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
774 tcg_gen_shri_tl(t1, t1, XER_CA);
775 } else {
776 TCGV_UNUSED(t1);
777 }
778
779 if (compute_ca && compute_ov) {
780 /* Start with XER CA and OV disabled, the most likely case */
781 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
782 } else if (compute_ca) {
783 /* Start with XER CA disabled, the most likely case */
784 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
785 } else if (compute_ov) {
786 /* Start with XER OV disabled, the most likely case */
787 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
788 }
789
790 tcg_gen_add_tl(t0, arg1, arg2);
791
792 if (compute_ca) {
793 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
794 }
795 if (add_ca) {
796 tcg_gen_add_tl(t0, t0, t1);
797 gen_op_arith_compute_ca(ctx, t0, t1, 0);
798 tcg_temp_free(t1);
799 }
800 if (compute_ov) {
801 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
802 }
803
804 if (unlikely(Rc(ctx->opcode) != 0))
805 gen_set_Rc0(ctx, t0);
806
807 if (!TCGV_EQUAL(t0, ret)) {
808 tcg_gen_mov_tl(ret, t0);
809 tcg_temp_free(t0);
810 }
811 }
812 /* Add functions with two operands */
813 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
814 static void glue(gen_, name)(DisasContext *ctx) \
815 { \
816 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
817 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
818 add_ca, compute_ca, compute_ov); \
819 }
820 /* Add functions with one operand and one immediate */
821 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
822 add_ca, compute_ca, compute_ov) \
823 static void glue(gen_, name)(DisasContext *ctx) \
824 { \
825 TCGv t0 = tcg_const_local_tl(const_val); \
826 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
827 cpu_gpr[rA(ctx->opcode)], t0, \
828 add_ca, compute_ca, compute_ov); \
829 tcg_temp_free(t0); \
830 }
831
832 /* add add. addo addo. */
833 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
834 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
835 /* addc addc. addco addco. */
836 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
837 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
838 /* adde adde. addeo addeo. */
839 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
840 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
841 /* addme addme. addmeo addmeo. */
842 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
843 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
844 /* addze addze. addzeo addzeo.*/
845 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
846 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
847 /* addi */
848 static void gen_addi(DisasContext *ctx)
849 {
850 target_long simm = SIMM(ctx->opcode);
851
852 if (rA(ctx->opcode) == 0) {
853 /* li case */
854 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
855 } else {
856 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
857 }
858 }
859 /* addic addic.*/
860 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
861 int compute_Rc0)
862 {
863 target_long simm = SIMM(ctx->opcode);
864
865 /* Start with XER CA and OV disabled, the most likely case */
866 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
867
868 if (likely(simm != 0)) {
869 TCGv t0 = tcg_temp_local_new();
870 tcg_gen_addi_tl(t0, arg1, simm);
871 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
872 tcg_gen_mov_tl(ret, t0);
873 tcg_temp_free(t0);
874 } else {
875 tcg_gen_mov_tl(ret, arg1);
876 }
877 if (compute_Rc0) {
878 gen_set_Rc0(ctx, ret);
879 }
880 }
881
882 static void gen_addic(DisasContext *ctx)
883 {
884 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
885 }
886
887 static void gen_addic_(DisasContext *ctx)
888 {
889 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
890 }
891
892 /* addis */
893 static void gen_addis(DisasContext *ctx)
894 {
895 target_long simm = SIMM(ctx->opcode);
896
897 if (rA(ctx->opcode) == 0) {
898 /* lis case */
899 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
900 } else {
901 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
902 }
903 }
904
905 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
906 int sign, int compute_ov)
907 {
908 int l1 = gen_new_label();
909 int l2 = gen_new_label();
910 TCGv_i32 t0 = tcg_temp_local_new_i32();
911 TCGv_i32 t1 = tcg_temp_local_new_i32();
912
913 tcg_gen_trunc_tl_i32(t0, arg1);
914 tcg_gen_trunc_tl_i32(t1, arg2);
915 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
916 if (sign) {
917 int l3 = gen_new_label();
918 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
919 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
920 gen_set_label(l3);
921 tcg_gen_div_i32(t0, t0, t1);
922 } else {
923 tcg_gen_divu_i32(t0, t0, t1);
924 }
925 if (compute_ov) {
926 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
927 }
928 tcg_gen_br(l2);
929 gen_set_label(l1);
930 if (sign) {
931 tcg_gen_sari_i32(t0, t0, 31);
932 } else {
933 tcg_gen_movi_i32(t0, 0);
934 }
935 if (compute_ov) {
936 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
937 }
938 gen_set_label(l2);
939 tcg_gen_extu_i32_tl(ret, t0);
940 tcg_temp_free_i32(t0);
941 tcg_temp_free_i32(t1);
942 if (unlikely(Rc(ctx->opcode) != 0))
943 gen_set_Rc0(ctx, ret);
944 }
945 /* Div functions */
946 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
947 static void glue(gen_, name)(DisasContext *ctx) \
948 { \
949 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
950 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
951 sign, compute_ov); \
952 }
953 /* divwu divwu. divwuo divwuo. */
954 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
955 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
956 /* divw divw. divwo divwo. */
957 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
958 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
959 #if defined(TARGET_PPC64)
960 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
961 int sign, int compute_ov)
962 {
963 int l1 = gen_new_label();
964 int l2 = gen_new_label();
965
966 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
967 if (sign) {
968 int l3 = gen_new_label();
969 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
970 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
971 gen_set_label(l3);
972 tcg_gen_div_i64(ret, arg1, arg2);
973 } else {
974 tcg_gen_divu_i64(ret, arg1, arg2);
975 }
976 if (compute_ov) {
977 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
978 }
979 tcg_gen_br(l2);
980 gen_set_label(l1);
981 if (sign) {
982 tcg_gen_sari_i64(ret, arg1, 63);
983 } else {
984 tcg_gen_movi_i64(ret, 0);
985 }
986 if (compute_ov) {
987 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
988 }
989 gen_set_label(l2);
990 if (unlikely(Rc(ctx->opcode) != 0))
991 gen_set_Rc0(ctx, ret);
992 }
993 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
994 static void glue(gen_, name)(DisasContext *ctx) \
995 { \
996 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
997 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
998 sign, compute_ov); \
999 }
1000 /* divwu divwu. divwuo divwuo. */
1001 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1002 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1003 /* divw divw. divwo divwo. */
1004 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1005 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1006 #endif
1007
1008 /* mulhw mulhw. */
1009 static void gen_mulhw(DisasContext *ctx)
1010 {
1011 TCGv_i64 t0, t1;
1012
1013 t0 = tcg_temp_new_i64();
1014 t1 = tcg_temp_new_i64();
1015 #if defined(TARGET_PPC64)
1016 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1017 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1018 tcg_gen_mul_i64(t0, t0, t1);
1019 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1020 #else
1021 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1022 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1023 tcg_gen_mul_i64(t0, t0, t1);
1024 tcg_gen_shri_i64(t0, t0, 32);
1025 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1026 #endif
1027 tcg_temp_free_i64(t0);
1028 tcg_temp_free_i64(t1);
1029 if (unlikely(Rc(ctx->opcode) != 0))
1030 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1031 }
1032
1033 /* mulhwu mulhwu. */
1034 static void gen_mulhwu(DisasContext *ctx)
1035 {
1036 TCGv_i64 t0, t1;
1037
1038 t0 = tcg_temp_new_i64();
1039 t1 = tcg_temp_new_i64();
1040 #if defined(TARGET_PPC64)
1041 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1042 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1043 tcg_gen_mul_i64(t0, t0, t1);
1044 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1045 #else
1046 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1047 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1048 tcg_gen_mul_i64(t0, t0, t1);
1049 tcg_gen_shri_i64(t0, t0, 32);
1050 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1051 #endif
1052 tcg_temp_free_i64(t0);
1053 tcg_temp_free_i64(t1);
1054 if (unlikely(Rc(ctx->opcode) != 0))
1055 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1056 }
1057
1058 /* mullw mullw. */
1059 static void gen_mullw(DisasContext *ctx)
1060 {
1061 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1062 cpu_gpr[rB(ctx->opcode)]);
1063 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1064 if (unlikely(Rc(ctx->opcode) != 0))
1065 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1066 }
1067
1068 /* mullwo mullwo. */
1069 static void gen_mullwo(DisasContext *ctx)
1070 {
1071 int l1;
1072 TCGv_i64 t0, t1;
1073
1074 t0 = tcg_temp_new_i64();
1075 t1 = tcg_temp_new_i64();
1076 l1 = gen_new_label();
1077 /* Start with XER OV disabled, the most likely case */
1078 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1079 #if defined(TARGET_PPC64)
1080 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1081 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1082 #else
1083 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1084 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1085 #endif
1086 tcg_gen_mul_i64(t0, t0, t1);
1087 #if defined(TARGET_PPC64)
1088 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1089 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1090 #else
1091 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1092 tcg_gen_ext32s_i64(t1, t0);
1093 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1094 #endif
1095 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1096 gen_set_label(l1);
1097 tcg_temp_free_i64(t0);
1098 tcg_temp_free_i64(t1);
1099 if (unlikely(Rc(ctx->opcode) != 0))
1100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1101 }
1102
1103 /* mulli */
1104 static void gen_mulli(DisasContext *ctx)
1105 {
1106 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1107 SIMM(ctx->opcode));
1108 }
1109 #if defined(TARGET_PPC64)
1110 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1111 static void glue(gen_, name)(DisasContext *ctx) \
1112 { \
1113 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1114 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1115 if (unlikely(Rc(ctx->opcode) != 0)) \
1116 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1117 }
1118 /* mulhd mulhd. */
1119 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1120 /* mulhdu mulhdu. */
1121 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1122
1123 /* mulld mulld. */
1124 static void gen_mulld(DisasContext *ctx)
1125 {
1126 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1127 cpu_gpr[rB(ctx->opcode)]);
1128 if (unlikely(Rc(ctx->opcode) != 0))
1129 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1130 }
1131 /* mulldo mulldo. */
1132 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1133 #endif
1134
1135 /* neg neg. nego nego. */
1136 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1137 {
1138 int l1 = gen_new_label();
1139 int l2 = gen_new_label();
1140 TCGv t0 = tcg_temp_local_new();
1141 #if defined(TARGET_PPC64)
1142 if (ctx->sf_mode) {
1143 tcg_gen_mov_tl(t0, arg1);
1144 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1145 } else
1146 #endif
1147 {
1148 tcg_gen_ext32s_tl(t0, arg1);
1149 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1150 }
1151 tcg_gen_neg_tl(ret, arg1);
1152 if (ov_check) {
1153 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1154 }
1155 tcg_gen_br(l2);
1156 gen_set_label(l1);
1157 tcg_gen_mov_tl(ret, t0);
1158 if (ov_check) {
1159 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1160 }
1161 gen_set_label(l2);
1162 tcg_temp_free(t0);
1163 if (unlikely(Rc(ctx->opcode) != 0))
1164 gen_set_Rc0(ctx, ret);
1165 }
1166
1167 static void gen_neg(DisasContext *ctx)
1168 {
1169 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1170 }
1171
1172 static void gen_nego(DisasContext *ctx)
1173 {
1174 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1175 }
1176
1177 /* Common subf function */
1178 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1179 int add_ca, int compute_ca, int compute_ov)
1180 {
1181 TCGv t0, t1;
1182
1183 if ((!compute_ca && !compute_ov) ||
1184 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1185 t0 = ret;
1186 } else {
1187 t0 = tcg_temp_local_new();
1188 }
1189
1190 if (add_ca) {
1191 t1 = tcg_temp_local_new();
1192 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1193 tcg_gen_shri_tl(t1, t1, XER_CA);
1194 } else {
1195 TCGV_UNUSED(t1);
1196 }
1197
1198 if (compute_ca && compute_ov) {
1199 /* Start with XER CA and OV disabled, the most likely case */
1200 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1201 } else if (compute_ca) {
1202 /* Start with XER CA disabled, the most likely case */
1203 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1204 } else if (compute_ov) {
1205 /* Start with XER OV disabled, the most likely case */
1206 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1207 }
1208
1209 if (add_ca) {
1210 tcg_gen_not_tl(t0, arg1);
1211 tcg_gen_add_tl(t0, t0, arg2);
1212 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1213 tcg_gen_add_tl(t0, t0, t1);
1214 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1215 tcg_temp_free(t1);
1216 } else {
1217 tcg_gen_sub_tl(t0, arg2, arg1);
1218 if (compute_ca) {
1219 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1220 }
1221 }
1222 if (compute_ov) {
1223 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1224 }
1225
1226 if (unlikely(Rc(ctx->opcode) != 0))
1227 gen_set_Rc0(ctx, t0);
1228
1229 if (!TCGV_EQUAL(t0, ret)) {
1230 tcg_gen_mov_tl(ret, t0);
1231 tcg_temp_free(t0);
1232 }
1233 }
1234 /* Sub functions with Two operands functions */
1235 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1236 static void glue(gen_, name)(DisasContext *ctx) \
1237 { \
1238 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1239 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1240 add_ca, compute_ca, compute_ov); \
1241 }
1242 /* Sub functions with one operand and one immediate */
1243 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1244 add_ca, compute_ca, compute_ov) \
1245 static void glue(gen_, name)(DisasContext *ctx) \
1246 { \
1247 TCGv t0 = tcg_const_local_tl(const_val); \
1248 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1249 cpu_gpr[rA(ctx->opcode)], t0, \
1250 add_ca, compute_ca, compute_ov); \
1251 tcg_temp_free(t0); \
1252 }
1253 /* subf subf. subfo subfo. */
1254 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1255 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1256 /* subfc subfc. subfco subfco. */
1257 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1258 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1259 /* subfe subfe. subfeo subfo. */
1260 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1261 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1262 /* subfme subfme. subfmeo subfmeo. */
1263 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1264 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1265 /* subfze subfze. subfzeo subfzeo.*/
1266 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1267 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1268
1269 /* subfic */
1270 static void gen_subfic(DisasContext *ctx)
1271 {
1272 /* Start with XER CA and OV disabled, the most likely case */
1273 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1274 TCGv t0 = tcg_temp_local_new();
1275 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1276 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1277 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1278 tcg_temp_free(t1);
1279 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1280 tcg_temp_free(t0);
1281 }
1282
1283 /*** Integer logical ***/
1284 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1285 static void glue(gen_, name)(DisasContext *ctx) \
1286 { \
1287 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1288 cpu_gpr[rB(ctx->opcode)]); \
1289 if (unlikely(Rc(ctx->opcode) != 0)) \
1290 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1291 }
1292
1293 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1294 static void glue(gen_, name)(DisasContext *ctx) \
1295 { \
1296 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1297 if (unlikely(Rc(ctx->opcode) != 0)) \
1298 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1299 }
1300
1301 /* and & and. */
1302 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1303 /* andc & andc. */
1304 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1305
1306 /* andi. */
1307 static void gen_andi_(DisasContext *ctx)
1308 {
1309 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1310 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1311 }
1312
1313 /* andis. */
1314 static void gen_andis_(DisasContext *ctx)
1315 {
1316 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1317 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1318 }
1319
1320 /* cntlzw */
1321 static void gen_cntlzw(DisasContext *ctx)
1322 {
1323 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1324 if (unlikely(Rc(ctx->opcode) != 0))
1325 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1326 }
1327 /* eqv & eqv. */
1328 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1329 /* extsb & extsb. */
1330 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1331 /* extsh & extsh. */
1332 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1333 /* nand & nand. */
1334 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1335 /* nor & nor. */
1336 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1337
1338 /* or & or. */
1339 static void gen_or(DisasContext *ctx)
1340 {
1341 int rs, ra, rb;
1342
1343 rs = rS(ctx->opcode);
1344 ra = rA(ctx->opcode);
1345 rb = rB(ctx->opcode);
1346 /* Optimisation for mr. ri case */
1347 if (rs != ra || rs != rb) {
1348 if (rs != rb)
1349 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1350 else
1351 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1352 if (unlikely(Rc(ctx->opcode) != 0))
1353 gen_set_Rc0(ctx, cpu_gpr[ra]);
1354 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1355 gen_set_Rc0(ctx, cpu_gpr[rs]);
1356 #if defined(TARGET_PPC64)
1357 } else {
1358 int prio = 0;
1359
1360 switch (rs) {
1361 case 1:
1362 /* Set process priority to low */
1363 prio = 2;
1364 break;
1365 case 6:
1366 /* Set process priority to medium-low */
1367 prio = 3;
1368 break;
1369 case 2:
1370 /* Set process priority to normal */
1371 prio = 4;
1372 break;
1373 #if !defined(CONFIG_USER_ONLY)
1374 case 31:
1375 if (ctx->mem_idx > 0) {
1376 /* Set process priority to very low */
1377 prio = 1;
1378 }
1379 break;
1380 case 5:
1381 if (ctx->mem_idx > 0) {
1382 /* Set process priority to medium-hight */
1383 prio = 5;
1384 }
1385 break;
1386 case 3:
1387 if (ctx->mem_idx > 0) {
1388 /* Set process priority to high */
1389 prio = 6;
1390 }
1391 break;
1392 case 7:
1393 if (ctx->mem_idx > 1) {
1394 /* Set process priority to very high */
1395 prio = 7;
1396 }
1397 break;
1398 #endif
1399 default:
1400 /* nop */
1401 break;
1402 }
1403 if (prio) {
1404 TCGv t0 = tcg_temp_new();
1405 gen_load_spr(t0, SPR_PPR);
1406 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1407 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1408 gen_store_spr(SPR_PPR, t0);
1409 tcg_temp_free(t0);
1410 }
1411 #endif
1412 }
1413 }
1414 /* orc & orc. */
1415 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1416
1417 /* xor & xor. */
1418 static void gen_xor(DisasContext *ctx)
1419 {
1420 /* Optimisation for "set to zero" case */
1421 if (rS(ctx->opcode) != rB(ctx->opcode))
1422 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1423 else
1424 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1425 if (unlikely(Rc(ctx->opcode) != 0))
1426 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1427 }
1428
1429 /* ori */
1430 static void gen_ori(DisasContext *ctx)
1431 {
1432 target_ulong uimm = UIMM(ctx->opcode);
1433
1434 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1435 /* NOP */
1436 /* XXX: should handle special NOPs for POWER series */
1437 return;
1438 }
1439 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1440 }
1441
1442 /* oris */
1443 static void gen_oris(DisasContext *ctx)
1444 {
1445 target_ulong uimm = UIMM(ctx->opcode);
1446
1447 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1448 /* NOP */
1449 return;
1450 }
1451 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1452 }
1453
1454 /* xori */
1455 static void gen_xori(DisasContext *ctx)
1456 {
1457 target_ulong uimm = UIMM(ctx->opcode);
1458
1459 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1460 /* NOP */
1461 return;
1462 }
1463 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1464 }
1465
1466 /* xoris */
1467 static void gen_xoris(DisasContext *ctx)
1468 {
1469 target_ulong uimm = UIMM(ctx->opcode);
1470
1471 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1472 /* NOP */
1473 return;
1474 }
1475 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1476 }
1477
1478 /* popcntb : PowerPC 2.03 specification */
1479 static void gen_popcntb(DisasContext *ctx)
1480 {
1481 #if defined(TARGET_PPC64)
1482 if (ctx->sf_mode)
1483 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1484 else
1485 #endif
1486 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1487 }
1488
1489 #if defined(TARGET_PPC64)
1490 /* extsw & extsw. */
1491 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1492
1493 /* cntlzd */
1494 static void gen_cntlzd(DisasContext *ctx)
1495 {
1496 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1497 if (unlikely(Rc(ctx->opcode) != 0))
1498 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1499 }
1500 #endif
1501
1502 /*** Integer rotate ***/
1503
1504 /* rlwimi & rlwimi. */
1505 static void gen_rlwimi(DisasContext *ctx)
1506 {
1507 uint32_t mb, me, sh;
1508
1509 mb = MB(ctx->opcode);
1510 me = ME(ctx->opcode);
1511 sh = SH(ctx->opcode);
1512 if (likely(sh == 0 && mb == 0 && me == 31)) {
1513 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1514 } else {
1515 target_ulong mask;
1516 TCGv t1;
1517 TCGv t0 = tcg_temp_new();
1518 #if defined(TARGET_PPC64)
1519 TCGv_i32 t2 = tcg_temp_new_i32();
1520 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1521 tcg_gen_rotli_i32(t2, t2, sh);
1522 tcg_gen_extu_i32_i64(t0, t2);
1523 tcg_temp_free_i32(t2);
1524 #else
1525 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1526 #endif
1527 #if defined(TARGET_PPC64)
1528 mb += 32;
1529 me += 32;
1530 #endif
1531 mask = MASK(mb, me);
1532 t1 = tcg_temp_new();
1533 tcg_gen_andi_tl(t0, t0, mask);
1534 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1535 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1536 tcg_temp_free(t0);
1537 tcg_temp_free(t1);
1538 }
1539 if (unlikely(Rc(ctx->opcode) != 0))
1540 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1541 }
1542
1543 /* rlwinm & rlwinm. */
1544 static void gen_rlwinm(DisasContext *ctx)
1545 {
1546 uint32_t mb, me, sh;
1547
1548 sh = SH(ctx->opcode);
1549 mb = MB(ctx->opcode);
1550 me = ME(ctx->opcode);
1551
1552 if (likely(mb == 0 && me == (31 - sh))) {
1553 if (likely(sh == 0)) {
1554 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1555 } else {
1556 TCGv t0 = tcg_temp_new();
1557 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1558 tcg_gen_shli_tl(t0, t0, sh);
1559 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1560 tcg_temp_free(t0);
1561 }
1562 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1563 TCGv t0 = tcg_temp_new();
1564 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1565 tcg_gen_shri_tl(t0, t0, mb);
1566 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1567 tcg_temp_free(t0);
1568 } else {
1569 TCGv t0 = tcg_temp_new();
1570 #if defined(TARGET_PPC64)
1571 TCGv_i32 t1 = tcg_temp_new_i32();
1572 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1573 tcg_gen_rotli_i32(t1, t1, sh);
1574 tcg_gen_extu_i32_i64(t0, t1);
1575 tcg_temp_free_i32(t1);
1576 #else
1577 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1578 #endif
1579 #if defined(TARGET_PPC64)
1580 mb += 32;
1581 me += 32;
1582 #endif
1583 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1584 tcg_temp_free(t0);
1585 }
1586 if (unlikely(Rc(ctx->opcode) != 0))
1587 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1588 }
1589
1590 /* rlwnm & rlwnm. */
1591 static void gen_rlwnm(DisasContext *ctx)
1592 {
1593 uint32_t mb, me;
1594 TCGv t0;
1595 #if defined(TARGET_PPC64)
1596 TCGv_i32 t1, t2;
1597 #endif
1598
1599 mb = MB(ctx->opcode);
1600 me = ME(ctx->opcode);
1601 t0 = tcg_temp_new();
1602 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1603 #if defined(TARGET_PPC64)
1604 t1 = tcg_temp_new_i32();
1605 t2 = tcg_temp_new_i32();
1606 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1607 tcg_gen_trunc_i64_i32(t2, t0);
1608 tcg_gen_rotl_i32(t1, t1, t2);
1609 tcg_gen_extu_i32_i64(t0, t1);
1610 tcg_temp_free_i32(t1);
1611 tcg_temp_free_i32(t2);
1612 #else
1613 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1614 #endif
1615 if (unlikely(mb != 0 || me != 31)) {
1616 #if defined(TARGET_PPC64)
1617 mb += 32;
1618 me += 32;
1619 #endif
1620 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1621 } else {
1622 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1623 }
1624 tcg_temp_free(t0);
1625 if (unlikely(Rc(ctx->opcode) != 0))
1626 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1627 }
1628
1629 #if defined(TARGET_PPC64)
1630 #define GEN_PPC64_R2(name, opc1, opc2) \
1631 static void glue(gen_, name##0)(DisasContext *ctx) \
1632 { \
1633 gen_##name(ctx, 0); \
1634 } \
1635 \
1636 static void glue(gen_, name##1)(DisasContext *ctx) \
1637 { \
1638 gen_##name(ctx, 1); \
1639 }
1640 #define GEN_PPC64_R4(name, opc1, opc2) \
1641 static void glue(gen_, name##0)(DisasContext *ctx) \
1642 { \
1643 gen_##name(ctx, 0, 0); \
1644 } \
1645 \
1646 static void glue(gen_, name##1)(DisasContext *ctx) \
1647 { \
1648 gen_##name(ctx, 0, 1); \
1649 } \
1650 \
1651 static void glue(gen_, name##2)(DisasContext *ctx) \
1652 { \
1653 gen_##name(ctx, 1, 0); \
1654 } \
1655 \
1656 static void glue(gen_, name##3)(DisasContext *ctx) \
1657 { \
1658 gen_##name(ctx, 1, 1); \
1659 }
1660
1661 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1662 uint32_t me, uint32_t sh)
1663 {
1664 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1665 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1666 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1667 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1668 } else {
1669 TCGv t0 = tcg_temp_new();
1670 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1671 if (likely(mb == 0 && me == 63)) {
1672 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1673 } else {
1674 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1675 }
1676 tcg_temp_free(t0);
1677 }
1678 if (unlikely(Rc(ctx->opcode) != 0))
1679 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1680 }
1681 /* rldicl - rldicl. */
1682 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1683 {
1684 uint32_t sh, mb;
1685
1686 sh = SH(ctx->opcode) | (shn << 5);
1687 mb = MB(ctx->opcode) | (mbn << 5);
1688 gen_rldinm(ctx, mb, 63, sh);
1689 }
1690 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1691 /* rldicr - rldicr. */
1692 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1693 {
1694 uint32_t sh, me;
1695
1696 sh = SH(ctx->opcode) | (shn << 5);
1697 me = MB(ctx->opcode) | (men << 5);
1698 gen_rldinm(ctx, 0, me, sh);
1699 }
1700 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1701 /* rldic - rldic. */
1702 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1703 {
1704 uint32_t sh, mb;
1705
1706 sh = SH(ctx->opcode) | (shn << 5);
1707 mb = MB(ctx->opcode) | (mbn << 5);
1708 gen_rldinm(ctx, mb, 63 - sh, sh);
1709 }
1710 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1711
1712 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1713 uint32_t me)
1714 {
1715 TCGv t0;
1716
1717 mb = MB(ctx->opcode);
1718 me = ME(ctx->opcode);
1719 t0 = tcg_temp_new();
1720 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1721 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1722 if (unlikely(mb != 0 || me != 63)) {
1723 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1724 } else {
1725 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1726 }
1727 tcg_temp_free(t0);
1728 if (unlikely(Rc(ctx->opcode) != 0))
1729 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1730 }
1731
1732 /* rldcl - rldcl. */
1733 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1734 {
1735 uint32_t mb;
1736
1737 mb = MB(ctx->opcode) | (mbn << 5);
1738 gen_rldnm(ctx, mb, 63);
1739 }
1740 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1741 /* rldcr - rldcr. */
1742 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1743 {
1744 uint32_t me;
1745
1746 me = MB(ctx->opcode) | (men << 5);
1747 gen_rldnm(ctx, 0, me);
1748 }
1749 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1750 /* rldimi - rldimi. */
1751 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1752 {
1753 uint32_t sh, mb, me;
1754
1755 sh = SH(ctx->opcode) | (shn << 5);
1756 mb = MB(ctx->opcode) | (mbn << 5);
1757 me = 63 - sh;
1758 if (unlikely(sh == 0 && mb == 0)) {
1759 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1760 } else {
1761 TCGv t0, t1;
1762 target_ulong mask;
1763
1764 t0 = tcg_temp_new();
1765 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1766 t1 = tcg_temp_new();
1767 mask = MASK(mb, me);
1768 tcg_gen_andi_tl(t0, t0, mask);
1769 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1770 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1771 tcg_temp_free(t0);
1772 tcg_temp_free(t1);
1773 }
1774 if (unlikely(Rc(ctx->opcode) != 0))
1775 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1776 }
1777 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1778 #endif
1779
1780 /*** Integer shift ***/
1781
1782 /* slw & slw. */
1783 static void gen_slw(DisasContext *ctx)
1784 {
1785 TCGv t0;
1786 int l1, l2;
1787 l1 = gen_new_label();
1788 l2 = gen_new_label();
1789
1790 t0 = tcg_temp_local_new();
1791 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1792 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1793 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1794 tcg_gen_br(l2);
1795 gen_set_label(l1);
1796 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1797 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1798 gen_set_label(l2);
1799 tcg_temp_free(t0);
1800 if (unlikely(Rc(ctx->opcode) != 0))
1801 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1802 }
1803
1804 /* sraw & sraw. */
1805 static void gen_sraw(DisasContext *ctx)
1806 {
1807 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1808 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1809 if (unlikely(Rc(ctx->opcode) != 0))
1810 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1811 }
1812
1813 /* srawi & srawi. */
1814 static void gen_srawi(DisasContext *ctx)
1815 {
1816 int sh = SH(ctx->opcode);
1817 if (sh != 0) {
1818 int l1, l2;
1819 TCGv t0;
1820 l1 = gen_new_label();
1821 l2 = gen_new_label();
1822 t0 = tcg_temp_local_new();
1823 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1824 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1825 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1826 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1827 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1828 tcg_gen_br(l2);
1829 gen_set_label(l1);
1830 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1831 gen_set_label(l2);
1832 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1833 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1834 tcg_temp_free(t0);
1835 } else {
1836 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1837 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1838 }
1839 if (unlikely(Rc(ctx->opcode) != 0))
1840 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1841 }
1842
1843 /* srw & srw. */
1844 static void gen_srw(DisasContext *ctx)
1845 {
1846 TCGv t0, t1;
1847 int l1, l2;
1848 l1 = gen_new_label();
1849 l2 = gen_new_label();
1850
1851 t0 = tcg_temp_local_new();
1852 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1853 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1854 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1855 tcg_gen_br(l2);
1856 gen_set_label(l1);
1857 t1 = tcg_temp_new();
1858 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1859 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1860 tcg_temp_free(t1);
1861 gen_set_label(l2);
1862 tcg_temp_free(t0);
1863 if (unlikely(Rc(ctx->opcode) != 0))
1864 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1865 }
1866
1867 #if defined(TARGET_PPC64)
1868 /* sld & sld. */
1869 static void gen_sld(DisasContext *ctx)
1870 {
1871 TCGv t0;
1872 int l1, l2;
1873 l1 = gen_new_label();
1874 l2 = gen_new_label();
1875
1876 t0 = tcg_temp_local_new();
1877 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
1878 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
1879 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1880 tcg_gen_br(l2);
1881 gen_set_label(l1);
1882 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1883 gen_set_label(l2);
1884 tcg_temp_free(t0);
1885 if (unlikely(Rc(ctx->opcode) != 0))
1886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1887 }
1888
1889 /* srad & srad. */
1890 static void gen_srad(DisasContext *ctx)
1891 {
1892 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
1893 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1894 if (unlikely(Rc(ctx->opcode) != 0))
1895 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1896 }
1897 /* sradi & sradi. */
1898 static always_inline void gen_sradi (DisasContext *ctx, int n)
1899 {
1900 int sh = SH(ctx->opcode) + (n << 5);
1901 if (sh != 0) {
1902 int l1, l2;
1903 TCGv t0;
1904 l1 = gen_new_label();
1905 l2 = gen_new_label();
1906 t0 = tcg_temp_local_new();
1907 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1908 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1909 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1910 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1911 tcg_gen_br(l2);
1912 gen_set_label(l1);
1913 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1914 gen_set_label(l2);
1915 tcg_temp_free(t0);
1916 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1917 } else {
1918 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1919 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1920 }
1921 if (unlikely(Rc(ctx->opcode) != 0))
1922 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1923 }
1924
1925 static void gen_sradi0(DisasContext *ctx)
1926 {
1927 gen_sradi(ctx, 0);
1928 }
1929
1930 static void gen_sradi1(DisasContext *ctx)
1931 {
1932 gen_sradi(ctx, 1);
1933 }
1934
1935 /* srd & srd. */
1936 static void gen_srd(DisasContext *ctx)
1937 {
1938 TCGv t0;
1939 int l1, l2;
1940 l1 = gen_new_label();
1941 l2 = gen_new_label();
1942
1943 t0 = tcg_temp_local_new();
1944 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
1945 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
1946 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1947 tcg_gen_br(l2);
1948 gen_set_label(l1);
1949 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1950 gen_set_label(l2);
1951 tcg_temp_free(t0);
1952 if (unlikely(Rc(ctx->opcode) != 0))
1953 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1954 }
1955 #endif
1956
1957 /*** Floating-Point arithmetic ***/
1958 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1959 static void gen_f##name(DisasContext *ctx) \
1960 { \
1961 if (unlikely(!ctx->fpu_enabled)) { \
1962 gen_exception(ctx, POWERPC_EXCP_FPU); \
1963 return; \
1964 } \
1965 /* NIP cannot be restored if the memory exception comes from an helper */ \
1966 gen_update_nip(ctx, ctx->nip - 4); \
1967 gen_reset_fpstatus(); \
1968 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
1969 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1970 if (isfloat) { \
1971 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
1972 } \
1973 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1974 Rc(ctx->opcode) != 0); \
1975 }
1976
1977 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1978 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1979 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1980
1981 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1982 static void gen_f##name(DisasContext *ctx) \
1983 { \
1984 if (unlikely(!ctx->fpu_enabled)) { \
1985 gen_exception(ctx, POWERPC_EXCP_FPU); \
1986 return; \
1987 } \
1988 /* NIP cannot be restored if the memory exception comes from an helper */ \
1989 gen_update_nip(ctx, ctx->nip - 4); \
1990 gen_reset_fpstatus(); \
1991 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
1992 cpu_fpr[rB(ctx->opcode)]); \
1993 if (isfloat) { \
1994 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
1995 } \
1996 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1997 set_fprf, Rc(ctx->opcode) != 0); \
1998 }
1999 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2000 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2001 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2002
2003 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2004 static void gen_f##name(DisasContext *ctx) \
2005 { \
2006 if (unlikely(!ctx->fpu_enabled)) { \
2007 gen_exception(ctx, POWERPC_EXCP_FPU); \
2008 return; \
2009 } \
2010 /* NIP cannot be restored if the memory exception comes from an helper */ \
2011 gen_update_nip(ctx, ctx->nip - 4); \
2012 gen_reset_fpstatus(); \
2013 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2014 cpu_fpr[rC(ctx->opcode)]); \
2015 if (isfloat) { \
2016 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2017 } \
2018 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2019 set_fprf, Rc(ctx->opcode) != 0); \
2020 }
2021 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2022 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2023 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2024
2025 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2026 static void gen_f##name(DisasContext *ctx) \
2027 { \
2028 if (unlikely(!ctx->fpu_enabled)) { \
2029 gen_exception(ctx, POWERPC_EXCP_FPU); \
2030 return; \
2031 } \
2032 /* NIP cannot be restored if the memory exception comes from an helper */ \
2033 gen_update_nip(ctx, ctx->nip - 4); \
2034 gen_reset_fpstatus(); \
2035 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2036 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2037 set_fprf, Rc(ctx->opcode) != 0); \
2038 }
2039
2040 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2041 static void gen_f##name(DisasContext *ctx) \
2042 { \
2043 if (unlikely(!ctx->fpu_enabled)) { \
2044 gen_exception(ctx, POWERPC_EXCP_FPU); \
2045 return; \
2046 } \
2047 /* NIP cannot be restored if the memory exception comes from an helper */ \
2048 gen_update_nip(ctx, ctx->nip - 4); \
2049 gen_reset_fpstatus(); \
2050 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2051 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2052 set_fprf, Rc(ctx->opcode) != 0); \
2053 }
2054
2055 /* fadd - fadds */
2056 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2057 /* fdiv - fdivs */
2058 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2059 /* fmul - fmuls */
2060 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2061
2062 /* fre */
2063 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2064
2065 /* fres */
2066 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2067
2068 /* frsqrte */
2069 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2070
2071 /* frsqrtes */
2072 static void gen_frsqrtes(DisasContext *ctx)
2073 {
2074 if (unlikely(!ctx->fpu_enabled)) {
2075 gen_exception(ctx, POWERPC_EXCP_FPU);
2076 return;
2077 }
2078 /* NIP cannot be restored if the memory exception comes from an helper */
2079 gen_update_nip(ctx, ctx->nip - 4);
2080 gen_reset_fpstatus();
2081 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2082 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2083 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2084 }
2085
2086 /* fsel */
2087 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2088 /* fsub - fsubs */
2089 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2090 /* Optional: */
2091
2092 /* fsqrt */
2093 static void gen_fsqrt(DisasContext *ctx)
2094 {
2095 if (unlikely(!ctx->fpu_enabled)) {
2096 gen_exception(ctx, POWERPC_EXCP_FPU);
2097 return;
2098 }
2099 /* NIP cannot be restored if the memory exception comes from an helper */
2100 gen_update_nip(ctx, ctx->nip - 4);
2101 gen_reset_fpstatus();
2102 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2103 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2104 }
2105
2106 static void gen_fsqrts(DisasContext *ctx)
2107 {
2108 if (unlikely(!ctx->fpu_enabled)) {
2109 gen_exception(ctx, POWERPC_EXCP_FPU);
2110 return;
2111 }
2112 /* NIP cannot be restored if the memory exception comes from an helper */
2113 gen_update_nip(ctx, ctx->nip - 4);
2114 gen_reset_fpstatus();
2115 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2116 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2117 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2118 }
2119
2120 /*** Floating-Point multiply-and-add ***/
2121 /* fmadd - fmadds */
2122 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2123 /* fmsub - fmsubs */
2124 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2125 /* fnmadd - fnmadds */
2126 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2127 /* fnmsub - fnmsubs */
2128 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2129
2130 /*** Floating-Point round & convert ***/
2131 /* fctiw */
2132 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2133 /* fctiwz */
2134 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2135 /* frsp */
2136 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2137 #if defined(TARGET_PPC64)
2138 /* fcfid */
2139 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2140 /* fctid */
2141 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2142 /* fctidz */
2143 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2144 #endif
2145
2146 /* frin */
2147 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2148 /* friz */
2149 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2150 /* frip */
2151 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2152 /* frim */
2153 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2154
2155 /*** Floating-Point compare ***/
2156
2157 /* fcmpo */
2158 static void gen_fcmpo(DisasContext *ctx)
2159 {
2160 TCGv_i32 crf;
2161 if (unlikely(!ctx->fpu_enabled)) {
2162 gen_exception(ctx, POWERPC_EXCP_FPU);
2163 return;
2164 }
2165 /* NIP cannot be restored if the memory exception comes from an helper */
2166 gen_update_nip(ctx, ctx->nip - 4);
2167 gen_reset_fpstatus();
2168 crf = tcg_const_i32(crfD(ctx->opcode));
2169 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2170 tcg_temp_free_i32(crf);
2171 gen_helper_float_check_status();
2172 }
2173
2174 /* fcmpu */
2175 static void gen_fcmpu(DisasContext *ctx)
2176 {
2177 TCGv_i32 crf;
2178 if (unlikely(!ctx->fpu_enabled)) {
2179 gen_exception(ctx, POWERPC_EXCP_FPU);
2180 return;
2181 }
2182 /* NIP cannot be restored if the memory exception comes from an helper */
2183 gen_update_nip(ctx, ctx->nip - 4);
2184 gen_reset_fpstatus();
2185 crf = tcg_const_i32(crfD(ctx->opcode));
2186 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2187 tcg_temp_free_i32(crf);
2188 gen_helper_float_check_status();
2189 }
2190
2191 /*** Floating-point move ***/
2192 /* fabs */
2193 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2194 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2195
2196 /* fmr - fmr. */
2197 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2198 static void gen_fmr(DisasContext *ctx)
2199 {
2200 if (unlikely(!ctx->fpu_enabled)) {
2201 gen_exception(ctx, POWERPC_EXCP_FPU);
2202 return;
2203 }
2204 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2205 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2206 }
2207
2208 /* fnabs */
2209 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2210 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2211 /* fneg */
2212 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2213 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2214
2215 /*** Floating-Point status & ctrl register ***/
2216
2217 /* mcrfs */
2218 static void gen_mcrfs(DisasContext *ctx)
2219 {
2220 int bfa;
2221
2222 if (unlikely(!ctx->fpu_enabled)) {
2223 gen_exception(ctx, POWERPC_EXCP_FPU);
2224 return;
2225 }
2226 bfa = 4 * (7 - crfS(ctx->opcode));
2227 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2228 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2229 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2230 }
2231
2232 /* mffs */
2233 static void gen_mffs(DisasContext *ctx)
2234 {
2235 if (unlikely(!ctx->fpu_enabled)) {
2236 gen_exception(ctx, POWERPC_EXCP_FPU);
2237 return;
2238 }
2239 gen_reset_fpstatus();
2240 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2241 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2242 }
2243
2244 /* mtfsb0 */
2245 static void gen_mtfsb0(DisasContext *ctx)
2246 {
2247 uint8_t crb;
2248
2249 if (unlikely(!ctx->fpu_enabled)) {
2250 gen_exception(ctx, POWERPC_EXCP_FPU);
2251 return;
2252 }
2253 crb = 31 - crbD(ctx->opcode);
2254 gen_reset_fpstatus();
2255 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2256 TCGv_i32 t0;
2257 /* NIP cannot be restored if the memory exception comes from an helper */
2258 gen_update_nip(ctx, ctx->nip - 4);
2259 t0 = tcg_const_i32(crb);
2260 gen_helper_fpscr_clrbit(t0);
2261 tcg_temp_free_i32(t0);
2262 }
2263 if (unlikely(Rc(ctx->opcode) != 0)) {
2264 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2265 }
2266 }
2267
2268 /* mtfsb1 */
2269 static void gen_mtfsb1(DisasContext *ctx)
2270 {
2271 uint8_t crb;
2272
2273 if (unlikely(!ctx->fpu_enabled)) {
2274 gen_exception(ctx, POWERPC_EXCP_FPU);
2275 return;
2276 }
2277 crb = 31 - crbD(ctx->opcode);
2278 gen_reset_fpstatus();
2279 /* XXX: we pretend we can only do IEEE floating-point computations */
2280 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2281 TCGv_i32 t0;
2282 /* NIP cannot be restored if the memory exception comes from an helper */
2283 gen_update_nip(ctx, ctx->nip - 4);
2284 t0 = tcg_const_i32(crb);
2285 gen_helper_fpscr_setbit(t0);
2286 tcg_temp_free_i32(t0);
2287 }
2288 if (unlikely(Rc(ctx->opcode) != 0)) {
2289 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2290 }
2291 /* We can raise a differed exception */
2292 gen_helper_float_check_status();
2293 }
2294
2295 /* mtfsf */
2296 static void gen_mtfsf(DisasContext *ctx)
2297 {
2298 TCGv_i32 t0;
2299 int L = ctx->opcode & 0x02000000;
2300
2301 if (unlikely(!ctx->fpu_enabled)) {
2302 gen_exception(ctx, POWERPC_EXCP_FPU);
2303 return;
2304 }
2305 /* NIP cannot be restored if the memory exception comes from an helper */
2306 gen_update_nip(ctx, ctx->nip - 4);
2307 gen_reset_fpstatus();
2308 if (L)
2309 t0 = tcg_const_i32(0xff);
2310 else
2311 t0 = tcg_const_i32(FM(ctx->opcode));
2312 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2313 tcg_temp_free_i32(t0);
2314 if (unlikely(Rc(ctx->opcode) != 0)) {
2315 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2316 }
2317 /* We can raise a differed exception */
2318 gen_helper_float_check_status();
2319 }
2320
2321 /* mtfsfi */
2322 static void gen_mtfsfi(DisasContext *ctx)
2323 {
2324 int bf, sh;
2325 TCGv_i64 t0;
2326 TCGv_i32 t1;
2327
2328 if (unlikely(!ctx->fpu_enabled)) {
2329 gen_exception(ctx, POWERPC_EXCP_FPU);
2330 return;
2331 }
2332 bf = crbD(ctx->opcode) >> 2;
2333 sh = 7 - bf;
2334 /* NIP cannot be restored if the memory exception comes from an helper */
2335 gen_update_nip(ctx, ctx->nip - 4);
2336 gen_reset_fpstatus();
2337 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2338 t1 = tcg_const_i32(1 << sh);
2339 gen_helper_store_fpscr(t0, t1);
2340 tcg_temp_free_i64(t0);
2341 tcg_temp_free_i32(t1);
2342 if (unlikely(Rc(ctx->opcode) != 0)) {
2343 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2344 }
2345 /* We can raise a differed exception */
2346 gen_helper_float_check_status();
2347 }
2348
2349 /*** Addressing modes ***/
2350 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2351 static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2352 {
2353 target_long simm = SIMM(ctx->opcode);
2354
2355 simm &= ~maskl;
2356 if (rA(ctx->opcode) == 0) {
2357 #if defined(TARGET_PPC64)
2358 if (!ctx->sf_mode) {
2359 tcg_gen_movi_tl(EA, (uint32_t)simm);
2360 } else
2361 #endif
2362 tcg_gen_movi_tl(EA, simm);
2363 } else if (likely(simm != 0)) {
2364 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2365 #if defined(TARGET_PPC64)
2366 if (!ctx->sf_mode) {
2367 tcg_gen_ext32u_tl(EA, EA);
2368 }
2369 #endif
2370 } else {
2371 #if defined(TARGET_PPC64)
2372 if (!ctx->sf_mode) {
2373 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2374 } else
2375 #endif
2376 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2377 }
2378 }
2379
2380 static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2381 {
2382 if (rA(ctx->opcode) == 0) {
2383 #if defined(TARGET_PPC64)
2384 if (!ctx->sf_mode) {
2385 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2386 } else
2387 #endif
2388 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2389 } else {
2390 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2391 #if defined(TARGET_PPC64)
2392 if (!ctx->sf_mode) {
2393 tcg_gen_ext32u_tl(EA, EA);
2394 }
2395 #endif
2396 }
2397 }
2398
2399 static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2400 {
2401 if (rA(ctx->opcode) == 0) {
2402 tcg_gen_movi_tl(EA, 0);
2403 } else {
2404 #if defined(TARGET_PPC64)
2405 if (!ctx->sf_mode) {
2406 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2407 } else
2408 #endif
2409 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2410 }
2411 }
2412
2413 static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2414 {
2415 tcg_gen_addi_tl(ret, arg1, val);
2416 #if defined(TARGET_PPC64)
2417 if (!ctx->sf_mode) {
2418 tcg_gen_ext32u_tl(ret, ret);
2419 }
2420 #endif
2421 }
2422
2423 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2424 {
2425 int l1 = gen_new_label();
2426 TCGv t0 = tcg_temp_new();
2427 TCGv_i32 t1, t2;
2428 /* NIP cannot be restored if the memory exception comes from an helper */
2429 gen_update_nip(ctx, ctx->nip - 4);
2430 tcg_gen_andi_tl(t0, EA, mask);
2431 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2432 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2433 t2 = tcg_const_i32(0);
2434 gen_helper_raise_exception_err(t1, t2);
2435 tcg_temp_free_i32(t1);
2436 tcg_temp_free_i32(t2);
2437 gen_set_label(l1);
2438 tcg_temp_free(t0);
2439 }
2440
2441 /*** Integer load ***/
2442 static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2443 {
2444 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2445 }
2446
2447 static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2448 {
2449 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2450 }
2451
2452 static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2453 {
2454 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2455 if (unlikely(ctx->le_mode)) {
2456 tcg_gen_bswap16_tl(arg1, arg1);
2457 }
2458 }
2459
2460 static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2461 {
2462 if (unlikely(ctx->le_mode)) {
2463 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2464 tcg_gen_bswap16_tl(arg1, arg1);
2465 tcg_gen_ext16s_tl(arg1, arg1);
2466 } else {
2467 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2468 }
2469 }
2470
2471 static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2472 {
2473 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2474 if (unlikely(ctx->le_mode)) {
2475 tcg_gen_bswap32_tl(arg1, arg1);
2476 }
2477 }
2478
2479 #if defined(TARGET_PPC64)
2480 static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2481 {
2482 if (unlikely(ctx->le_mode)) {
2483 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2484 tcg_gen_bswap32_tl(arg1, arg1);
2485 tcg_gen_ext32s_tl(arg1, arg1);
2486 } else
2487 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2488 }
2489 #endif
2490
2491 static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2492 {
2493 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2494 if (unlikely(ctx->le_mode)) {
2495 tcg_gen_bswap64_i64(arg1, arg1);
2496 }
2497 }
2498
2499 static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2500 {
2501 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2502 }
2503
2504 static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2505 {
2506 if (unlikely(ctx->le_mode)) {
2507 TCGv t0 = tcg_temp_new();
2508 tcg_gen_ext16u_tl(t0, arg1);
2509 tcg_gen_bswap16_tl(t0, t0);
2510 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2511 tcg_temp_free(t0);
2512 } else {
2513 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2514 }
2515 }
2516
2517 static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2518 {
2519 if (unlikely(ctx->le_mode)) {
2520 TCGv t0 = tcg_temp_new();
2521 tcg_gen_ext32u_tl(t0, arg1);
2522 tcg_gen_bswap32_tl(t0, t0);
2523 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2524 tcg_temp_free(t0);
2525 } else {
2526 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2527 }
2528 }
2529
2530 static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2531 {
2532 if (unlikely(ctx->le_mode)) {
2533 TCGv_i64 t0 = tcg_temp_new_i64();
2534 tcg_gen_bswap64_i64(t0, arg1);
2535 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2536 tcg_temp_free_i64(t0);
2537 } else
2538 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2539 }
2540
2541 #define GEN_LD(name, ldop, opc, type) \
2542 static void glue(gen_, name)(DisasContext *ctx) \
2543 { \
2544 TCGv EA; \
2545 gen_set_access_type(ctx, ACCESS_INT); \
2546 EA = tcg_temp_new(); \
2547 gen_addr_imm_index(ctx, EA, 0); \
2548 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2549 tcg_temp_free(EA); \
2550 }
2551
2552 #define GEN_LDU(name, ldop, opc, type) \
2553 static void glue(gen_, name##u)(DisasContext *ctx) \
2554 { \
2555 TCGv EA; \
2556 if (unlikely(rA(ctx->opcode) == 0 || \
2557 rA(ctx->opcode) == rD(ctx->opcode))) { \
2558 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2559 return; \
2560 } \
2561 gen_set_access_type(ctx, ACCESS_INT); \
2562 EA = tcg_temp_new(); \
2563 if (type == PPC_64B) \
2564 gen_addr_imm_index(ctx, EA, 0x03); \
2565 else \
2566 gen_addr_imm_index(ctx, EA, 0); \
2567 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2568 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2569 tcg_temp_free(EA); \
2570 }
2571
2572 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2573 static void glue(gen_, name##ux)(DisasContext *ctx) \
2574 { \
2575 TCGv EA; \
2576 if (unlikely(rA(ctx->opcode) == 0 || \
2577 rA(ctx->opcode) == rD(ctx->opcode))) { \
2578 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2579 return; \
2580 } \
2581 gen_set_access_type(ctx, ACCESS_INT); \
2582 EA = tcg_temp_new(); \
2583 gen_addr_reg_index(ctx, EA); \
2584 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2585 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2586 tcg_temp_free(EA); \
2587 }
2588
2589 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2590 static void glue(gen_, name##x)(DisasContext *ctx) \
2591 { \
2592 TCGv EA; \
2593 gen_set_access_type(ctx, ACCESS_INT); \
2594 EA = tcg_temp_new(); \
2595 gen_addr_reg_index(ctx, EA); \
2596 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2597 tcg_temp_free(EA); \
2598 }
2599
2600 #define GEN_LDS(name, ldop, op, type) \
2601 GEN_LD(name, ldop, op | 0x20, type); \
2602 GEN_LDU(name, ldop, op | 0x21, type); \
2603 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2604 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2605
2606 /* lbz lbzu lbzux lbzx */
2607 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2608 /* lha lhau lhaux lhax */
2609 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2610 /* lhz lhzu lhzux lhzx */
2611 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2612 /* lwz lwzu lwzux lwzx */
2613 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2614 #if defined(TARGET_PPC64)
2615 /* lwaux */
2616 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2617 /* lwax */
2618 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2619 /* ldux */
2620 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2621 /* ldx */
2622 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2623
2624 static void gen_ld(DisasContext *ctx)
2625 {
2626 TCGv EA;
2627 if (Rc(ctx->opcode)) {
2628 if (unlikely(rA(ctx->opcode) == 0 ||
2629 rA(ctx->opcode) == rD(ctx->opcode))) {
2630 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2631 return;
2632 }
2633 }
2634 gen_set_access_type(ctx, ACCESS_INT);
2635 EA = tcg_temp_new();
2636 gen_addr_imm_index(ctx, EA, 0x03);
2637 if (ctx->opcode & 0x02) {
2638 /* lwa (lwau is undefined) */
2639 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2640 } else {
2641 /* ld - ldu */
2642 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2643 }
2644 if (Rc(ctx->opcode))
2645 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2646 tcg_temp_free(EA);
2647 }
2648
2649 /* lq */
2650 static void gen_lq(DisasContext *ctx)
2651 {
2652 #if defined(CONFIG_USER_ONLY)
2653 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2654 #else
2655 int ra, rd;
2656 TCGv EA;
2657
2658 /* Restore CPU state */
2659 if (unlikely(ctx->mem_idx == 0)) {
2660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2661 return;
2662 }
2663 ra = rA(ctx->opcode);
2664 rd = rD(ctx->opcode);
2665 if (unlikely((rd & 1) || rd == ra)) {
2666 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2667 return;
2668 }
2669 if (unlikely(ctx->le_mode)) {
2670 /* Little-endian mode is not handled */
2671 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2672 return;
2673 }
2674 gen_set_access_type(ctx, ACCESS_INT);
2675 EA = tcg_temp_new();
2676 gen_addr_imm_index(ctx, EA, 0x0F);
2677 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2678 gen_addr_add(ctx, EA, EA, 8);
2679 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2680 tcg_temp_free(EA);
2681 #endif
2682 }
2683 #endif
2684
2685 /*** Integer store ***/
2686 #define GEN_ST(name, stop, opc, type) \
2687 static void glue(gen_, name)(DisasContext *ctx) \
2688 { \
2689 TCGv EA; \
2690 gen_set_access_type(ctx, ACCESS_INT); \
2691 EA = tcg_temp_new(); \
2692 gen_addr_imm_index(ctx, EA, 0); \
2693 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2694 tcg_temp_free(EA); \
2695 }
2696
2697 #define GEN_STU(name, stop, opc, type) \
2698 static void glue(gen_, stop##u)(DisasContext *ctx) \
2699 { \
2700 TCGv EA; \
2701 if (unlikely(rA(ctx->opcode) == 0)) { \
2702 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2703 return; \
2704 } \
2705 gen_set_access_type(ctx, ACCESS_INT); \
2706 EA = tcg_temp_new(); \
2707 if (type == PPC_64B) \
2708 gen_addr_imm_index(ctx, EA, 0x03); \
2709 else \
2710 gen_addr_imm_index(ctx, EA, 0); \
2711 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2712 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2713 tcg_temp_free(EA); \
2714 }
2715
2716 #define GEN_STUX(name, stop, opc2, opc3, type) \
2717 static void glue(gen_, name##ux)(DisasContext *ctx) \
2718 { \
2719 TCGv EA; \
2720 if (unlikely(rA(ctx->opcode) == 0)) { \
2721 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2722 return; \
2723 } \
2724 gen_set_access_type(ctx, ACCESS_INT); \
2725 EA = tcg_temp_new(); \
2726 gen_addr_reg_index(ctx, EA); \
2727 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2728 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2729 tcg_temp_free(EA); \
2730 }
2731
2732 #define GEN_STX(name, stop, opc2, opc3, type) \
2733 static void glue(gen_, name##x)(DisasContext *ctx) \
2734 { \
2735 TCGv EA; \
2736 gen_set_access_type(ctx, ACCESS_INT); \
2737 EA = tcg_temp_new(); \
2738 gen_addr_reg_index(ctx, EA); \
2739 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2740 tcg_temp_free(EA); \
2741 }
2742
2743 #define GEN_STS(name, stop, op, type) \
2744 GEN_ST(name, stop, op | 0x20, type); \
2745 GEN_STU(name, stop, op | 0x21, type); \
2746 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2747 GEN_STX(name, stop, 0x17, op | 0x00, type)
2748
2749 /* stb stbu stbux stbx */
2750 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2751 /* sth sthu sthux sthx */
2752 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2753 /* stw stwu stwux stwx */
2754 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2755 #if defined(TARGET_PPC64)
2756 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2757 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2758
2759 static void gen_std(DisasContext *ctx)
2760 {
2761 int rs;
2762 TCGv EA;
2763
2764 rs = rS(ctx->opcode);
2765 if ((ctx->opcode & 0x3) == 0x2) {
2766 #if defined(CONFIG_USER_ONLY)
2767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2768 #else
2769 /* stq */
2770 if (unlikely(ctx->mem_idx == 0)) {
2771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2772 return;
2773 }
2774 if (unlikely(rs & 1)) {
2775 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2776 return;
2777 }
2778 if (unlikely(ctx->le_mode)) {
2779 /* Little-endian mode is not handled */
2780 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2781 return;
2782 }
2783 gen_set_access_type(ctx, ACCESS_INT);
2784 EA = tcg_temp_new();
2785 gen_addr_imm_index(ctx, EA, 0x03);
2786 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2787 gen_addr_add(ctx, EA, EA, 8);
2788 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2789 tcg_temp_free(EA);
2790 #endif
2791 } else {
2792 /* std / stdu */
2793 if (Rc(ctx->opcode)) {
2794 if (unlikely(rA(ctx->opcode) == 0)) {
2795 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2796 return;
2797 }
2798 }
2799 gen_set_access_type(ctx, ACCESS_INT);
2800 EA = tcg_temp_new();
2801 gen_addr_imm_index(ctx, EA, 0x03);
2802 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2803 if (Rc(ctx->opcode))
2804 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2805 tcg_temp_free(EA);
2806 }
2807 }
2808 #endif
2809 /*** Integer load and store with byte reverse ***/
2810 /* lhbrx */
2811 static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2812 {
2813 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2814 if (likely(!ctx->le_mode)) {
2815 tcg_gen_bswap16_tl(arg1, arg1);
2816 }
2817 }
2818 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2819
2820 /* lwbrx */
2821 static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2822 {
2823 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2824 if (likely(!ctx->le_mode)) {
2825 tcg_gen_bswap32_tl(arg1, arg1);
2826 }
2827 }
2828 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2829
2830 /* sthbrx */
2831 static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2832 {
2833 if (likely(!ctx->le_mode)) {
2834 TCGv t0 = tcg_temp_new();
2835 tcg_gen_ext16u_tl(t0, arg1);
2836 tcg_gen_bswap16_tl(t0, t0);
2837 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2838 tcg_temp_free(t0);
2839 } else {
2840 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2841 }
2842 }
2843 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2844
2845 /* stwbrx */
2846 static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2847 {
2848 if (likely(!ctx->le_mode)) {
2849 TCGv t0 = tcg_temp_new();
2850 tcg_gen_ext32u_tl(t0, arg1);
2851 tcg_gen_bswap32_tl(t0, t0);
2852 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2853 tcg_temp_free(t0);
2854 } else {
2855 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2856 }
2857 }
2858 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2859
2860 /*** Integer load and store multiple ***/
2861
2862 /* lmw */
2863 static void gen_lmw(DisasContext *ctx)
2864 {
2865 TCGv t0;
2866 TCGv_i32 t1;
2867 gen_set_access_type(ctx, ACCESS_INT);
2868 /* NIP cannot be restored if the memory exception comes from an helper */
2869 gen_update_nip(ctx, ctx->nip - 4);
2870 t0 = tcg_temp_new();
2871 t1 = tcg_const_i32(rD(ctx->opcode));
2872 gen_addr_imm_index(ctx, t0, 0);
2873 gen_helper_lmw(t0, t1);
2874 tcg_temp_free(t0);
2875 tcg_temp_free_i32(t1);
2876 }
2877
2878 /* stmw */
2879 static void gen_stmw(DisasContext *ctx)
2880 {
2881 TCGv t0;
2882 TCGv_i32 t1;
2883 gen_set_access_type(ctx, ACCESS_INT);
2884 /* NIP cannot be restored if the memory exception comes from an helper */
2885 gen_update_nip(ctx, ctx->nip - 4);
2886 t0 = tcg_temp_new();
2887 t1 = tcg_const_i32(rS(ctx->opcode));
2888 gen_addr_imm_index(ctx, t0, 0);
2889 gen_helper_stmw(t0, t1);
2890 tcg_temp_free(t0);
2891 tcg_temp_free_i32(t1);
2892 }
2893
2894 /*** Integer load and store strings ***/
2895
2896 /* lswi */
2897 /* PowerPC32 specification says we must generate an exception if
2898 * rA is in the range of registers to be loaded.
2899 * In an other hand, IBM says this is valid, but rA won't be loaded.
2900 * For now, I'll follow the spec...
2901 */
2902 static void gen_lswi(DisasContext *ctx)
2903 {
2904 TCGv t0;
2905 TCGv_i32 t1, t2;
2906 int nb = NB(ctx->opcode);
2907 int start = rD(ctx->opcode);
2908 int ra = rA(ctx->opcode);
2909 int nr;
2910
2911 if (nb == 0)
2912 nb = 32;
2913 nr = nb / 4;
2914 if (unlikely(((start + nr) > 32 &&
2915 start <= ra && (start + nr - 32) > ra) ||
2916 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2917 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2918 return;
2919 }
2920 gen_set_access_type(ctx, ACCESS_INT);
2921 /* NIP cannot be restored if the memory exception comes from an helper */
2922 gen_update_nip(ctx, ctx->nip - 4);
2923 t0 = tcg_temp_new();
2924 gen_addr_register(ctx, t0);
2925 t1 = tcg_const_i32(nb);
2926 t2 = tcg_const_i32(start);
2927 gen_helper_lsw(t0, t1, t2);
2928 tcg_temp_free(t0);
2929 tcg_temp_free_i32(t1);
2930 tcg_temp_free_i32(t2);
2931 }
2932
2933 /* lswx */
2934 static void gen_lswx(DisasContext *ctx)
2935 {
2936 TCGv t0;
2937 TCGv_i32 t1, t2, t3;
2938 gen_set_access_type(ctx, ACCESS_INT);
2939 /* NIP cannot be restored if the memory exception comes from an helper */
2940 gen_update_nip(ctx, ctx->nip - 4);
2941 t0 = tcg_temp_new();
2942 gen_addr_reg_index(ctx, t0);
2943 t1 = tcg_const_i32(rD(ctx->opcode));
2944 t2 = tcg_const_i32(rA(ctx->opcode));
2945 t3 = tcg_const_i32(rB(ctx->opcode));
2946 gen_helper_lswx(t0, t1, t2, t3);
2947 tcg_temp_free(t0);
2948 tcg_temp_free_i32(t1);
2949 tcg_temp_free_i32(t2);
2950 tcg_temp_free_i32(t3);
2951 }
2952
2953 /* stswi */
2954 static void gen_stswi(DisasContext *ctx)
2955 {
2956 TCGv t0;
2957 TCGv_i32 t1, t2;
2958 int nb = NB(ctx->opcode);
2959 gen_set_access_type(ctx, ACCESS_INT);
2960 /* NIP cannot be restored if the memory exception comes from an helper */
2961 gen_update_nip(ctx, ctx->nip - 4);
2962 t0 = tcg_temp_new();
2963 gen_addr_register(ctx, t0);
2964 if (nb == 0)
2965 nb = 32;
2966 t1 = tcg_const_i32(nb);
2967 t2 = tcg_const_i32(rS(ctx->opcode));
2968 gen_helper_stsw(t0, t1, t2);
2969 tcg_temp_free(t0);
2970 tcg_temp_free_i32(t1);
2971 tcg_temp_free_i32(t2);
2972 }
2973
2974 /* stswx */
2975 static void gen_stswx(DisasContext *ctx)
2976 {
2977 TCGv t0;
2978 TCGv_i32 t1, t2;
2979 gen_set_access_type(ctx, ACCESS_INT);
2980 /* NIP cannot be restored if the memory exception comes from an helper */
2981 gen_update_nip(ctx, ctx->nip - 4);
2982 t0 = tcg_temp_new();
2983 gen_addr_reg_index(ctx, t0);
2984 t1 = tcg_temp_new_i32();
2985 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2986 tcg_gen_andi_i32(t1, t1, 0x7F);
2987 t2 = tcg_const_i32(rS(ctx->opcode));
2988 gen_helper_stsw(t0, t1, t2);
2989 tcg_temp_free(t0);
2990 tcg_temp_free_i32(t1);
2991 tcg_temp_free_i32(t2);
2992 }
2993
2994 /*** Memory synchronisation ***/
2995 /* eieio */
2996 static void gen_eieio(DisasContext *ctx)
2997 {
2998 }
2999
3000 /* isync */
3001 static void gen_isync(DisasContext *ctx)
3002 {
3003 gen_stop_exception(ctx);
3004 }
3005
3006 /* lwarx */
3007 static void gen_lwarx(DisasContext *ctx)
3008 {
3009 TCGv t0;
3010 gen_set_access_type(ctx, ACCESS_RES);
3011 t0 = tcg_temp_local_new();
3012 gen_addr_reg_index(ctx, t0);
3013 gen_check_align(ctx, t0, 0x03);
3014 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3015 tcg_gen_mov_tl(cpu_reserve, t0);
3016 tcg_temp_free(t0);
3017 }
3018
3019 /* stwcx. */
3020 static void gen_stwcx_(DisasContext *ctx)
3021 {
3022 int l1;
3023 TCGv t0;
3024 gen_set_access_type(ctx, ACCESS_RES);
3025 t0 = tcg_temp_local_new();
3026 gen_addr_reg_index(ctx, t0);
3027 gen_check_align(ctx, t0, 0x03);
3028 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3029 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3030 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3031 l1 = gen_new_label();
3032 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3033 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3034 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3035 gen_set_label(l1);
3036 tcg_gen_movi_tl(cpu_reserve, -1);
3037 tcg_temp_free(t0);
3038 }
3039
3040 #if defined(TARGET_PPC64)
3041 /* ldarx */
3042 static void gen_ldarx(DisasContext *ctx)
3043 {
3044 TCGv t0;
3045 gen_set_access_type(ctx, ACCESS_RES);
3046 t0 = tcg_temp_local_new();
3047 gen_addr_reg_index(ctx, t0);
3048 gen_check_align(ctx, t0, 0x07);
3049 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3050 tcg_gen_mov_tl(cpu_reserve, t0);
3051 tcg_temp_free(t0);
3052 }
3053
3054 /* stdcx. */
3055 static void gen_stdcx_(DisasContext *ctx)
3056 {
3057 int l1;
3058 TCGv t0;
3059 gen_set_access_type(ctx, ACCESS_RES);
3060 t0 = tcg_temp_local_new();
3061 gen_addr_reg_index(ctx, t0);
3062 gen_check_align(ctx, t0, 0x07);
3063 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3064 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3065 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3066 l1 = gen_new_label();
3067 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3068 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3069 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3070 gen_set_label(l1);
3071 tcg_gen_movi_tl(cpu_reserve, -1);
3072 tcg_temp_free(t0);
3073 }
3074 #endif /* defined(TARGET_PPC64) */
3075
3076 /* sync */
3077 static void gen_sync(DisasContext *ctx)
3078 {
3079 }
3080
3081 /* wait */
3082 static void gen_wait(DisasContext *ctx)
3083 {
3084 TCGv_i32 t0 = tcg_temp_new_i32();
3085 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3086 tcg_temp_free_i32(t0);
3087 /* Stop translation, as the CPU is supposed to sleep from now */
3088 gen_exception_err(ctx, EXCP_HLT, 1);
3089 }
3090
3091 /*** Floating-point load ***/
3092 #define GEN_LDF(name, ldop, opc, type) \
3093 static void glue(gen_, name)(DisasContext *ctx) \
3094 { \
3095 TCGv EA; \
3096 if (unlikely(!ctx->fpu_enabled)) { \
3097 gen_exception(ctx, POWERPC_EXCP_FPU); \
3098 return; \
3099 } \
3100 gen_set_access_type(ctx, ACCESS_FLOAT); \
3101 EA = tcg_temp_new(); \
3102 gen_addr_imm_index(ctx, EA, 0); \
3103 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3104 tcg_temp_free(EA); \
3105 }
3106
3107 #define GEN_LDUF(name, ldop, opc, type) \
3108 static void glue(gen_, name##u)(DisasContext *ctx) \
3109 { \
3110 TCGv EA; \
3111 if (unlikely(!ctx->fpu_enabled)) { \
3112 gen_exception(ctx, POWERPC_EXCP_FPU); \
3113 return; \
3114 } \
3115 if (unlikely(rA(ctx->opcode) == 0)) { \
3116 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3117 return; \
3118 } \
3119 gen_set_access_type(ctx, ACCESS_FLOAT); \
3120 EA = tcg_temp_new(); \
3121 gen_addr_imm_index(ctx, EA, 0); \
3122 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3123 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3124 tcg_temp_free(EA); \
3125 }
3126
3127 #define GEN_LDUXF(name, ldop, opc, type) \
3128 static void glue(gen_, name##ux)(DisasContext *ctx) \
3129 { \
3130 TCGv EA; \
3131 if (unlikely(!ctx->fpu_enabled)) { \
3132 gen_exception(ctx, POWERPC_EXCP_FPU); \
3133 return; \
3134 } \
3135 if (unlikely(rA(ctx->opcode) == 0)) { \
3136 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3137 return; \
3138 } \
3139 gen_set_access_type(ctx, ACCESS_FLOAT); \
3140 EA = tcg_temp_new(); \
3141 gen_addr_reg_index(ctx, EA); \
3142 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3143 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3144 tcg_temp_free(EA); \
3145 }
3146
3147 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3148 static void glue(gen_, name##x)(DisasContext *ctx) \
3149 { \
3150 TCGv EA; \
3151 if (unlikely(!ctx->fpu_enabled)) { \
3152 gen_exception(ctx, POWERPC_EXCP_FPU); \
3153 return; \
3154 } \
3155 gen_set_access_type(ctx, ACCESS_FLOAT); \
3156 EA = tcg_temp_new(); \
3157 gen_addr_reg_index(ctx, EA); \
3158 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3159 tcg_temp_free(EA); \
3160 }
3161
3162 #define GEN_LDFS(name, ldop, op, type) \
3163 GEN_LDF(name, ldop, op | 0x20, type); \
3164 GEN_LDUF(name, ldop, op | 0x21, type); \
3165 GEN_LDUXF(name, ldop, op | 0x01, type); \
3166 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3167
3168 static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3169 {
3170 TCGv t0 = tcg_temp_new();
3171 TCGv_i32 t1 = tcg_temp_new_i32();
3172 gen_qemu_ld32u(ctx, t0, arg2);
3173 tcg_gen_trunc_tl_i32(t1, t0);
3174 tcg_temp_free(t0);
3175 gen_helper_float32_to_float64(arg1, t1);
3176 tcg_temp_free_i32(t1);
3177 }
3178
3179 /* lfd lfdu lfdux lfdx */
3180 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3181 /* lfs lfsu lfsux lfsx */
3182 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3183
3184 /*** Floating-point store ***/
3185 #define GEN_STF(name, stop, opc, type) \
3186 static void glue(gen_, name)(DisasContext *ctx) \
3187 { \
3188 TCGv EA; \
3189 if (unlikely(!ctx->fpu_enabled)) { \
3190 gen_exception(ctx, POWERPC_EXCP_FPU); \
3191 return; \
3192 } \
3193 gen_set_access_type(ctx, ACCESS_FLOAT); \
3194 EA = tcg_temp_new(); \
3195 gen_addr_imm_index(ctx, EA, 0); \
3196 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3197 tcg_temp_free(EA); \
3198 }
3199
3200 #define GEN_STUF(name, stop, opc, type) \
3201 static void glue(gen_, name##u)(DisasContext *ctx) \
3202 { \
3203 TCGv EA; \
3204 if (unlikely(!ctx->fpu_enabled)) { \
3205 gen_exception(ctx, POWERPC_EXCP_FPU); \
3206 return; \
3207 } \
3208 if (unlikely(rA(ctx->opcode) == 0)) { \
3209 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3210 return; \
3211 } \
3212 gen_set_access_type(ctx, ACCESS_FLOAT); \
3213 EA = tcg_temp_new(); \
3214 gen_addr_imm_index(ctx, EA, 0); \
3215 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3216 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3217 tcg_temp_free(EA); \
3218 }
3219
3220 #define GEN_STUXF(name, stop, opc, type) \
3221 static void glue(gen_, name##ux)(DisasContext *ctx) \
3222 { \
3223 TCGv EA; \
3224 if (unlikely(!ctx->fpu_enabled)) { \
3225 gen_exception(ctx, POWERPC_EXCP_FPU); \
3226 return; \
3227 } \
3228 if (unlikely(rA(ctx->opcode) == 0)) { \
3229 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3230 return; \
3231 } \
3232 gen_set_access_type(ctx, ACCESS_FLOAT); \
3233 EA = tcg_temp_new(); \
3234 gen_addr_reg_index(ctx, EA); \
3235 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3236 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3237 tcg_temp_free(EA); \
3238 }
3239
3240 #define GEN_STXF(name, stop, opc2, opc3, type) \
3241 static void glue(gen_, name##x)(DisasContext *ctx) \
3242 { \
3243 TCGv EA; \
3244 if (unlikely(!ctx->fpu_enabled)) { \
3245 gen_exception(ctx, POWERPC_EXCP_FPU); \
3246 return; \
3247 } \
3248 gen_set_access_type(ctx, ACCESS_FLOAT); \
3249 EA = tcg_temp_new(); \
3250 gen_addr_reg_index(ctx, EA); \
3251 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3252 tcg_temp_free(EA); \
3253 }
3254
3255 #define GEN_STFS(name, stop, op, type) \
3256 GEN_STF(name, stop, op | 0x20, type); \
3257 GEN_STUF(name, stop, op | 0x21, type); \
3258 GEN_STUXF(name, stop, op | 0x01, type); \
3259 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3260
3261 static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3262 {
3263 TCGv_i32 t0 = tcg_temp_new_i32();
3264 TCGv t1 = tcg_temp_new();
3265 gen_helper_float64_to_float32(t0, arg1);
3266 tcg_gen_extu_i32_tl(t1, t0);
3267 tcg_temp_free_i32(t0);
3268 gen_qemu_st32(ctx, t1, arg2);
3269 tcg_temp_free(t1);
3270 }
3271
3272 /* stfd stfdu stfdux stfdx */
3273 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3274 /* stfs stfsu stfsux stfsx */
3275 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3276
3277 /* Optional: */
3278 static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3279 {
3280 TCGv t0 = tcg_temp_new();
3281 tcg_gen_trunc_i64_tl(t0, arg1),
3282 gen_qemu_st32(ctx, t0, arg2);
3283 tcg_temp_free(t0);
3284 }
3285 /* stfiwx */
3286 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3287
3288 /*** Branch ***/
3289 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3290 target_ulong dest)
3291 {
3292 TranslationBlock *tb;
3293 tb = ctx->tb;
3294 #if defined(TARGET_PPC64)
3295 if (!ctx->sf_mode)
3296 dest = (uint32_t) dest;
3297 #endif
3298 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3299 likely(!ctx->singlestep_enabled)) {
3300 tcg_gen_goto_tb(n);
3301 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3302 tcg_gen_exit_tb((long)tb + n);
3303 } else {
3304 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3305 if (unlikely(ctx->singlestep_enabled)) {
3306 if ((ctx->singlestep_enabled &
3307 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3308 ctx->exception == POWERPC_EXCP_BRANCH) {
3309 target_ulong tmp = ctx->nip;
3310 ctx->nip = dest;
3311 gen_exception(ctx, POWERPC_EXCP_TRACE);
3312 ctx->nip = tmp;
3313 }
3314 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3315 gen_debug_exception(ctx);
3316 }
3317 }
3318 tcg_gen_exit_tb(0);
3319 }
3320 }
3321
3322 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3323 {
3324 #if defined(TARGET_PPC64)
3325 if (ctx->sf_mode == 0)
3326 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3327 else
3328 #endif
3329 tcg_gen_movi_tl(cpu_lr, nip);
3330 }
3331
3332 /* b ba bl bla */
3333 static void gen_b(DisasContext *ctx)
3334 {
3335 target_ulong li, target;
3336
3337 ctx->exception = POWERPC_EXCP_BRANCH;
3338 /* sign extend LI */
3339 #if defined(TARGET_PPC64)
3340 if (ctx->sf_mode)
3341 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3342 else
3343 #endif
3344 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3345 if (likely(AA(ctx->opcode) == 0))
3346 target = ctx->nip + li - 4;
3347 else
3348 target = li;
3349 if (LK(ctx->opcode))
3350 gen_setlr(ctx, ctx->nip);
3351 gen_goto_tb(ctx, 0, target);
3352 }
3353
3354 #define BCOND_IM 0
3355 #define BCOND_LR 1
3356 #define BCOND_CTR 2
3357
3358 static always_inline void gen_bcond (DisasContext *ctx, int type)
3359 {
3360 uint32_t bo = BO(ctx->opcode);
3361 int l1 = gen_new_label();
3362 TCGv target;
3363
3364 ctx->exception = POWERPC_EXCP_BRANCH;
3365 if (type == BCOND_LR || type == BCOND_CTR) {
3366 target = tcg_temp_local_new();
3367 if (type == BCOND_CTR)
3368 tcg_gen_mov_tl(target, cpu_ctr);
3369 else
3370 tcg_gen_mov_tl(target, cpu_lr);
3371 } else {
3372 TCGV_UNUSED(target);
3373 }
3374 if (LK(ctx->opcode))
3375 gen_setlr(ctx, ctx->nip);
3376 l1 = gen_new_label();
3377 if ((bo & 0x4) == 0) {
3378 /* Decrement and test CTR */
3379 TCGv temp = tcg_temp_new();
3380 if (unlikely(type == BCOND_CTR)) {
3381 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3382 return;
3383 }
3384 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3385 #if defined(TARGET_PPC64)
3386 if (!ctx->sf_mode)
3387 tcg_gen_ext32u_tl(temp, cpu_ctr);
3388 else
3389 #endif
3390 tcg_gen_mov_tl(temp, cpu_ctr);
3391 if (bo & 0x2) {
3392 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3393 } else {
3394 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3395 }
3396 tcg_temp_free(temp);
3397 }
3398 if ((bo & 0x10) == 0) {
3399 /* Test CR */
3400 uint32_t bi = BI(ctx->opcode);
3401 uint32_t mask = 1 << (3 - (bi & 0x03));
3402 TCGv_i32 temp = tcg_temp_new_i32();
3403
3404 if (bo & 0x8) {
3405 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3406 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3407 } else {
3408 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3409 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3410 }
3411 tcg_temp_free_i32(temp);
3412 }
3413 if (type == BCOND_IM) {
3414 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3415 if (likely(AA(ctx->opcode) == 0)) {
3416 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3417 } else {
3418 gen_goto_tb(ctx, 0, li);
3419 }
3420 gen_set_label(l1);
3421 gen_goto_tb(ctx, 1, ctx->nip);
3422 } else {
3423 #if defined(TARGET_PPC64)
3424 if (!(ctx->sf_mode))
3425 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3426 else
3427 #endif
3428 tcg_gen_andi_tl(cpu_nip, target, ~3);
3429 tcg_gen_exit_tb(0);
3430 gen_set_label(l1);
3431 #if defined(TARGET_PPC64)
3432 if (!(ctx->sf_mode))
3433 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3434 else
3435 #endif
3436 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3437 tcg_gen_exit_tb(0);
3438 }
3439 }
3440
3441 static void gen_bc(DisasContext *ctx)
3442 {
3443 gen_bcond(ctx, BCOND_IM);
3444 }
3445
3446 static void gen_bcctr(DisasContext *ctx)
3447 {
3448 gen_bcond(ctx, BCOND_CTR);
3449 }
3450
3451 static void gen_bclr(DisasContext *ctx)
3452 {
3453 gen_bcond(ctx, BCOND_LR);
3454 }
3455
3456 /*** Condition register logical ***/
3457 #define GEN_CRLOGIC(name, tcg_op, opc) \
3458 static void glue(gen_, name)(DisasContext *ctx) \
3459 { \
3460 uint8_t bitmask; \
3461 int sh; \
3462 TCGv_i32 t0, t1; \
3463 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3464 t0 = tcg_temp_new_i32(); \
3465 if (sh > 0) \
3466 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3467 else if (sh < 0) \
3468 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3469 else \
3470 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3471 t1 = tcg_temp_new_i32(); \
3472 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3473 if (sh > 0) \
3474 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3475 else if (sh < 0) \
3476 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3477 else \
3478 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3479 tcg_op(t0, t0, t1); \
3480 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3481 tcg_gen_andi_i32(t0, t0, bitmask); \
3482 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3483 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3484 tcg_temp_free_i32(t0); \
3485 tcg_temp_free_i32(t1); \
3486 }
3487
3488 /* crand */
3489 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3490 /* crandc */
3491 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3492 /* creqv */
3493 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3494 /* crnand */
3495 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3496 /* crnor */
3497 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3498 /* cror */
3499 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3500 /* crorc */
3501 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3502 /* crxor */
3503 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3504
3505 /* mcrf */
3506 static void gen_mcrf(DisasContext *ctx)
3507 {
3508 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3509 }
3510
3511 /*** System linkage ***/
3512
3513 /* rfi (mem_idx only) */
3514 static void gen_rfi(DisasContext *ctx)
3515 {
3516 #if defined(CONFIG_USER_ONLY)
3517 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3518 #else
3519 /* Restore CPU state */
3520 if (unlikely(!ctx->mem_idx)) {
3521 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3522 return;
3523 }
3524 gen_helper_rfi();
3525 gen_sync_exception(ctx);
3526 #endif
3527 }
3528
3529 #if defined(TARGET_PPC64)
3530 static void gen_rfid(DisasContext *ctx)
3531 {
3532 #if defined(CONFIG_USER_ONLY)
3533 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3534 #else
3535 /* Restore CPU state */
3536 if (unlikely(!ctx->mem_idx)) {
3537 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3538 return;
3539 }
3540 gen_helper_rfid();
3541 gen_sync_exception(ctx);
3542 #endif
3543 }
3544
3545 static void gen_hrfid(DisasContext *ctx)
3546 {
3547 #if defined(CONFIG_USER_ONLY)
3548 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3549 #else
3550 /* Restore CPU state */
3551 if (unlikely(ctx->mem_idx <= 1)) {
3552 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3553 return;
3554 }
3555 gen_helper_hrfid();
3556 gen_sync_exception(ctx);
3557 #endif
3558 }
3559 #endif
3560
3561 /* sc */
3562 #if defined(CONFIG_USER_ONLY)
3563 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3564 #else
3565 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3566 #endif
3567 static void gen_sc(DisasContext *ctx)
3568 {
3569 uint32_t lev;
3570
3571 lev = (ctx->opcode >> 5) & 0x7F;
3572 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3573 }
3574
3575 /*** Trap ***/
3576
3577 /* tw */
3578 static void gen_tw(DisasContext *ctx)
3579 {
3580 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3581 /* Update the nip since this might generate a trap exception */
3582 gen_update_nip(ctx, ctx->nip);
3583 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3584 tcg_temp_free_i32(t0);
3585 }
3586
3587 /* twi */
3588 static void gen_twi(DisasContext *ctx)
3589 {
3590 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3591 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3592 /* Update the nip since this might generate a trap exception */
3593 gen_update_nip(ctx, ctx->nip);
3594 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3595 tcg_temp_free(t0);
3596 tcg_temp_free_i32(t1);
3597 }
3598
3599 #if defined(TARGET_PPC64)
3600 /* td */
3601 static void gen_td(DisasContext *ctx)
3602 {
3603 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3604 /* Update the nip since this might generate a trap exception */
3605 gen_update_nip(ctx, ctx->nip);
3606 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3607 tcg_temp_free_i32(t0);
3608 }
3609
3610 /* tdi */
3611 static void gen_tdi(DisasContext *ctx)
3612 {
3613 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3614 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3615 /* Update the nip since this might generate a trap exception */
3616 gen_update_nip(ctx, ctx->nip);
3617 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3618 tcg_temp_free(t0);
3619 tcg_temp_free_i32(t1);
3620 }
3621 #endif
3622
3623 /*** Processor control ***/
3624
3625 /* mcrxr */
3626 static void gen_mcrxr(DisasContext *ctx)
3627 {
3628 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3629 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3630 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3631 }
3632
3633 /* mfcr mfocrf */
3634 static void gen_mfcr(DisasContext *ctx)
3635 {
3636 uint32_t crm, crn;
3637
3638 if (likely(ctx->opcode & 0x00100000)) {
3639 crm = CRM(ctx->opcode);
3640 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3641 crn = ctz32 (crm);
3642 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3643 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3644 cpu_gpr[rD(ctx->opcode)], crn * 4);
3645 }
3646 } else {
3647 TCGv_i32 t0 = tcg_temp_new_i32();
3648 tcg_gen_mov_i32(t0, cpu_crf[0]);
3649 tcg_gen_shli_i32(t0, t0, 4);
3650 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3651 tcg_gen_shli_i32(t0, t0, 4);
3652 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3653 tcg_gen_shli_i32(t0, t0, 4);
3654 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3655 tcg_gen_shli_i32(t0, t0, 4);
3656 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3657 tcg_gen_shli_i32(t0, t0, 4);
3658 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3659 tcg_gen_shli_i32(t0, t0, 4);
3660 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3661 tcg_gen_shli_i32(t0, t0, 4);
3662 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3663 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3664 tcg_temp_free_i32(t0);
3665 }
3666 }
3667
3668 /* mfmsr */
3669 static void gen_mfmsr(DisasContext *ctx)
3670 {
3671 #if defined(CONFIG_USER_ONLY)
3672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3673 #else
3674 if (unlikely(!ctx->mem_idx)) {
3675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3676 return;
3677 }
3678 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3679 #endif
3680 }
3681
3682 #if 1
3683 #define SPR_NOACCESS ((void *)(-1UL))
3684 #else
3685 static void spr_noaccess (void *opaque, int sprn)
3686 {
3687 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3688 printf("ERROR: try to access SPR %d !\n", sprn);
3689 }
3690 #define SPR_NOACCESS (&spr_noaccess)
3691 #endif
3692
3693 /* mfspr */
3694 static always_inline void gen_op_mfspr (DisasContext *ctx)
3695 {
3696 void (*read_cb)(void *opaque, int gprn, int sprn);
3697 uint32_t sprn = SPR(ctx->opcode);
3698
3699 #if !defined(CONFIG_USER_ONLY)
3700 if (ctx->mem_idx == 2)
3701 read_cb = ctx->spr_cb[sprn].hea_read;
3702 else if (ctx->mem_idx)
3703 read_cb = ctx->spr_cb[sprn].oea_read;
3704 else
3705 #endif
3706 read_cb = ctx->spr_cb[sprn].uea_read;
3707 if (likely(read_cb != NULL)) {
3708 if (likely(read_cb != SPR_NOACCESS)) {
3709 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3710 } else {
3711 /* Privilege exception */
3712 /* This is a hack to avoid warnings when running Linux:
3713 * this OS breaks the PowerPC virtualisation model,
3714 * allowing userland application to read the PVR
3715 */
3716 if (sprn != SPR_PVR) {
3717 qemu_log("Trying to read privileged spr %d %03x at "
3718 ADDRX "\n", sprn, sprn, ctx->nip);
3719 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3720 sprn, sprn, ctx->nip);
3721 }
3722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3723 }
3724 } else {
3725 /* Not defined */
3726 qemu_log("Trying to read invalid spr %d %03x at "
3727 ADDRX "\n", sprn, sprn, ctx->nip);
3728 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3729 sprn, sprn, ctx->nip);
3730 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3731 }
3732 }
3733
3734 static void gen_mfspr(DisasContext *ctx)
3735 {
3736 gen_op_mfspr(ctx);
3737 }
3738
3739 /* mftb */
3740 static void gen_mftb(DisasContext *ctx)
3741 {
3742 gen_op_mfspr(ctx);
3743 }
3744
3745 /* mtcrf mtocrf*/
3746 static void gen_mtcrf(DisasContext *ctx)
3747 {
3748 uint32_t crm, crn;
3749
3750 crm = CRM(ctx->opcode);
3751 if (likely((ctx->opcode & 0x00100000))) {
3752 if (crm && ((crm & (crm - 1)) == 0)) {
3753 TCGv_i32 temp = tcg_temp_new_i32();
3754 crn = ctz32 (crm);
3755 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3756 tcg_gen_shri_i32(temp, temp, crn * 4);
3757 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3758 tcg_temp_free_i32(temp);
3759 }
3760 } else {
3761 TCGv_i32 temp = tcg_temp_new_i32();
3762 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3763 for (crn = 0 ; crn < 8 ; crn++) {
3764 if (crm & (1 << crn)) {
3765 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3766 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3767 }
3768 }
3769 tcg_temp_free_i32(temp);
3770 }
3771 }
3772
3773 /* mtmsr */
3774 #if defined(TARGET_PPC64)
3775 static void gen_mtmsrd(DisasContext *ctx)
3776 {
3777 #if defined(CONFIG_USER_ONLY)
3778 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3779 #else
3780 if (unlikely(!ctx->mem_idx)) {
3781 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3782 return;
3783 }
3784 if (ctx->opcode & 0x00010000) {
3785 /* Special form that does not need any synchronisation */
3786 TCGv t0 = tcg_temp_new();
3787 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3788 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3789 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3790 tcg_temp_free(t0);
3791 } else {
3792 /* XXX: we need to update nip before the store
3793 * if we enter power saving mode, we will exit the loop
3794 * directly from ppc_store_msr
3795 */
3796 gen_update_nip(ctx, ctx->nip);
3797 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3798 /* Must stop the translation as machine state (may have) changed */
3799 /* Note that mtmsr is not always defined as context-synchronizing */
3800 gen_stop_exception(ctx);
3801 }
3802 #endif
3803 }
3804 #endif
3805
3806 static void gen_mtmsr(DisasContext *ctx)
3807 {
3808 #if defined(CONFIG_USER_ONLY)
3809 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3810 #else
3811 if (unlikely(!ctx->mem_idx)) {
3812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3813 return;
3814 }
3815 if (ctx->opcode & 0x00010000) {
3816 /* Special form that does not need any synchronisation */
3817 TCGv t0 = tcg_temp_new();
3818 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3819 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3820 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3821 tcg_temp_free(t0);
3822 } else {
3823 /* XXX: we need to update nip before the store
3824 * if we enter power saving mode, we will exit the loop
3825 * directly from ppc_store_msr
3826 */
3827 gen_update_nip(ctx, ctx->nip);
3828 #if defined(TARGET_PPC64)
3829 if (!ctx->sf_mode) {
3830 TCGv t0 = tcg_temp_new();
3831 TCGv t1 = tcg_temp_new();
3832 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
3833 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
3834 tcg_gen_or_tl(t0, t0, t1);
3835 tcg_temp_free(t1);
3836 gen_helper_store_msr(t0);
3837 tcg_temp_free(t0);
3838 } else
3839 #endif
3840 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3841 /* Must stop the translation as machine state (may have) changed */
3842 /* Note that mtmsr is not always defined as context-synchronizing */
3843 gen_stop_exception(ctx);
3844 }
3845 #endif
3846 }
3847
3848 /* mtspr */
3849 static void gen_mtspr(DisasContext *ctx)
3850 {
3851 void (*write_cb)(void *opaque, int sprn, int gprn);
3852 uint32_t sprn = SPR(ctx->opcode);
3853
3854 #if !defined(CONFIG_USER_ONLY)
3855 if (ctx->mem_idx == 2)
3856 write_cb = ctx->spr_cb[sprn].hea_write;
3857 else if (ctx->mem_idx)
3858 write_cb = ctx->spr_cb[sprn].oea_write;
3859 else
3860 #endif
3861 write_cb = ctx->spr_cb[sprn].uea_write;
3862 if (likely(write_cb != NULL)) {
3863 if (likely(write_cb != SPR_NOACCESS)) {
3864 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3865 } else {
3866 /* Privilege exception */
3867 qemu_log("Trying to write privileged spr %d %03x at "
3868 ADDRX "\n", sprn, sprn, ctx->nip);
3869 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3870 sprn, sprn, ctx->nip);
3871 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3872 }
3873 } else {
3874 /* Not defined */
3875 qemu_log("Trying to write invalid spr %d %03x at "
3876 ADDRX "\n", sprn, sprn, ctx->nip);
3877 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3878 sprn, sprn, ctx->nip);
3879 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3880 }
3881 }
3882
3883 /*** Cache management ***/
3884
3885 /* dcbf */
3886 static void gen_dcbf(DisasContext *ctx)
3887 {
3888 /* XXX: specification says this is treated as a load by the MMU */
3889 TCGv t0;
3890 gen_set_access_type(ctx, ACCESS_CACHE);
3891 t0 = tcg_temp_new();
3892 gen_addr_reg_index(ctx, t0);
3893 gen_qemu_ld8u(ctx, t0, t0);
3894 tcg_temp_free(t0);
3895 }
3896
3897 /* dcbi (Supervisor only) */
3898 static void gen_dcbi(DisasContext *ctx)
3899 {
3900 #if defined(CONFIG_USER_ONLY)
3901 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3902 #else
3903 TCGv EA, val;
3904 if (unlikely(!ctx->mem_idx)) {
3905 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3906 return;
3907 }
3908 EA = tcg_temp_new();
3909 gen_set_access_type(ctx, ACCESS_CACHE);
3910 gen_addr_reg_index(ctx, EA);
3911 val = tcg_temp_new();
3912 /* XXX: specification says this should be treated as a store by the MMU */
3913 gen_qemu_ld8u(ctx, val, EA);
3914 gen_qemu_st8(ctx, val, EA);
3915 tcg_temp_free(val);
3916 tcg_temp_free(EA);
3917 #endif
3918 }
3919
3920 /* dcdst */
3921 static void gen_dcbst(DisasContext *ctx)
3922 {
3923 /* XXX: specification say this is treated as a load by the MMU */
3924 TCGv t0;
3925 gen_set_access_type(ctx, ACCESS_CACHE);
3926 t0 = tcg_temp_new();
3927 gen_addr_reg_index(ctx, t0);
3928 gen_qemu_ld8u(ctx, t0, t0);
3929 tcg_temp_free(t0);
3930 }
3931
3932 /* dcbt */
3933 static void gen_dcbt(DisasContext *ctx)
3934 {
3935 /* interpreted as no-op */
3936 /* XXX: specification say this is treated as a load by the MMU
3937 * but does not generate any exception
3938 */
3939 }
3940
3941 /* dcbtst */
3942 static void gen_dcbtst(DisasContext *ctx)
3943 {
3944 /* interpreted as no-op */
3945 /* XXX: specification say this is treated as a load by the MMU
3946 * but does not generate any exception
3947 */
3948 }
3949
3950 /* dcbz */
3951 static void gen_dcbz(DisasContext *ctx)
3952 {
3953 TCGv t0;
3954 gen_set_access_type(ctx, ACCESS_CACHE);
3955 /* NIP cannot be restored if the memory exception comes from an helper */
3956 gen_update_nip(ctx, ctx->nip - 4);
3957 t0 = tcg_temp_new();
3958 gen_addr_reg_index(ctx, t0);
3959 gen_helper_dcbz(t0);
3960 tcg_temp_free(t0);
3961 }
3962
3963 static void gen_dcbz_970(DisasContext *ctx)
3964 {
3965 TCGv t0;
3966 gen_set_access_type(ctx, ACCESS_CACHE);
3967 /* NIP cannot be restored if the memory exception comes from an helper */
3968 gen_update_nip(ctx, ctx->nip - 4);
3969 t0 = tcg_temp_new();
3970 gen_addr_reg_index(ctx, t0);
3971 if (ctx->opcode & 0x00200000)
3972 gen_helper_dcbz(t0);
3973 else
3974 gen_helper_dcbz_970(t0);
3975 tcg_temp_free(t0);
3976 }
3977
3978 /* dst / dstt */
3979 static void gen_dst(DisasContext *ctx)
3980 {
3981 if (rA(ctx->opcode) == 0) {
3982 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3983 } else {
3984 /* interpreted as no-op */
3985 }
3986 }
3987
3988 /* dstst /dststt */
3989 static void gen_dstst(DisasContext *ctx)
3990 {
3991 if (rA(ctx->opcode) == 0) {
3992 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3993 } else {
3994 /* interpreted as no-op */
3995 }
3996
3997 }
3998
3999 /* dss / dssall */
4000 static void gen_dss(DisasContext *ctx)
4001 {
4002 /* interpreted as no-op */
4003 }
4004
4005 /* icbi */
4006 static void gen_icbi(DisasContext *ctx)
4007 {
4008 TCGv t0;
4009 gen_set_access_type(ctx, ACCESS_CACHE);
4010 /* NIP cannot be restored if the memory exception comes from an helper */
4011 gen_update_nip(ctx, ctx->nip - 4);
4012 t0 = tcg_temp_new();
4013 gen_addr_reg_index(ctx, t0);
4014 gen_helper_icbi(t0);
4015 tcg_temp_free(t0);
4016 }
4017
4018 /* Optional: */
4019 /* dcba */
4020 static void gen_dcba(DisasContext *ctx)
4021 {
4022 /* interpreted as no-op */
4023 /* XXX: specification say this is treated as a store by the MMU
4024 * but does not generate any exception
4025 */
4026 }
4027
4028 /*** Segment register manipulation ***/
4029 /* Supervisor only: */
4030
4031 /* mfsr */
4032 static void gen_mfsr(DisasContext *ctx)
4033 {
4034 #if defined(CONFIG_USER_ONLY)
4035 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4036 #else
4037 TCGv t0;
4038 if (unlikely(!ctx->mem_idx)) {
4039 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4040 return;
4041 }
4042 t0 = tcg_const_tl(SR(ctx->opcode));
4043 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4044 tcg_temp_free(t0);
4045 #endif
4046 }
4047
4048 /* mfsrin */
4049 static void gen_mfsrin(DisasContext *ctx)
4050 {
4051 #if defined(CONFIG_USER_ONLY)
4052 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4053 #else
4054 TCGv t0;
4055 if (unlikely(!ctx->mem_idx)) {
4056 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4057 return;
4058 }
4059 t0 = tcg_temp_new();
4060 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4061 tcg_gen_andi_tl(t0, t0, 0xF);
4062 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4063 tcg_temp_free(t0);
4064 #endif
4065 }
4066
4067 /* mtsr */
4068 static void gen_mtsr(DisasContext *ctx)
4069 {
4070 #if defined(CONFIG_USER_ONLY)
4071 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4072 #else
4073 TCGv t0;
4074 if (unlikely(!ctx->mem_idx)) {
4075 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4076 return;
4077 }
4078 t0 = tcg_const_tl(SR(ctx->opcode));
4079 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4080 tcg_temp_free(t0);
4081 #endif
4082 }
4083
4084 /* mtsrin */
4085 static void gen_mtsrin(DisasContext *ctx)
4086 {
4087 #if defined(CONFIG_USER_ONLY)
4088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4089 #else
4090 TCGv t0;
4091 if (unlikely(!ctx->mem_idx)) {
4092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4093 return;
4094 }
4095 t0 = tcg_temp_new();
4096 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4097 tcg_gen_andi_tl(t0, t0, 0xF);
4098 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4099 tcg_temp_free(t0);
4100 #endif
4101 }
4102
4103 #if defined(TARGET_PPC64)
4104 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4105
4106 /* mfsr */
4107 static void gen_mfsr_64b(DisasContext *ctx)
4108 {
4109 #if defined(CONFIG_USER_ONLY)
4110 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4111 #else
4112 TCGv t0;
4113 if (unlikely(!ctx->mem_idx)) {
4114 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4115 return;
4116 }
4117 t0 = tcg_const_tl(SR(ctx->opcode));
4118 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4119 tcg_temp_free(t0);
4120 #endif
4121 }
4122
4123 /* mfsrin */
4124 static void gen_mfsrin_64b(DisasContext *ctx)
4125 {
4126 #if defined(CONFIG_USER_ONLY)
4127 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4128 #else
4129 TCGv t0;
4130 if (unlikely(!ctx->mem_idx)) {
4131 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4132 return;
4133 }
4134 t0 = tcg_temp_new();
4135 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4136 tcg_gen_andi_tl(t0, t0, 0xF);
4137 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4138 tcg_temp_free(t0);
4139 #endif
4140 }
4141
4142 /* mtsr */
4143 static void gen_mtsr_64b(DisasContext *ctx)
4144 {
4145 #if defined(CONFIG_USER_ONLY)
4146 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4147 #else
4148 TCGv t0;
4149 if (unlikely(!ctx->mem_idx)) {
4150 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4151 return;
4152 }
4153 t0 = tcg_const_tl(SR(ctx->opcode));
4154 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4155 tcg_temp_free(t0);
4156 #endif
4157 }
4158
4159 /* mtsrin */
4160 static void gen_mtsrin_64b(DisasContext *ctx)
4161 {
4162 #if defined(CONFIG_USER_ONLY)
4163 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4164 #else
4165 TCGv t0;
4166 if (unlikely(!ctx->mem_idx)) {
4167 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4168 return;
4169 }
4170 t0 = tcg_temp_new();
4171 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4172 tcg_gen_andi_tl(t0, t0, 0xF);
4173 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4174 tcg_temp_free(t0);
4175 #endif
4176 }
4177
4178 /* slbmte */
4179 static void gen_slbmte(DisasContext *ctx)
4180 {
4181 #if defined(CONFIG_USER_ONLY)
4182 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4183 #else
4184 if (unlikely(!ctx->mem_idx)) {
4185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4186 return;
4187 }
4188 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4189 #endif
4190 }
4191
4192 #endif /* defined(TARGET_PPC64) */
4193
4194 /*** Lookaside buffer management ***/
4195 /* Optional & mem_idx only: */
4196
4197 /* tlbia */
4198 static void gen_tlbia(DisasContext *ctx)
4199 {
4200 #if defined(CONFIG_USER_ONLY)
4201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4202 #else
4203 if (unlikely(!ctx->mem_idx)) {
4204 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4205 return;
4206 }
4207 gen_helper_tlbia();
4208 #endif
4209 }
4210
4211 /* tlbiel */
4212 static void gen_tlbiel(DisasContext *ctx)
4213 {
4214 #if defined(CONFIG_USER_ONLY)
4215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4216 #else
4217 if (unlikely(!ctx->mem_idx)) {
4218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4219 return;
4220 }
4221 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4222 #endif
4223 }
4224
4225 /* tlbie */
4226 static void gen_tlbie(DisasContext *ctx)
4227 {
4228 #if defined(CONFIG_USER_ONLY)
4229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4230 #else
4231 if (unlikely(!ctx->mem_idx)) {
4232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4233 return;
4234 }
4235 #if defined(TARGET_PPC64)
4236 if (!ctx->sf_mode) {
4237 TCGv t0 = tcg_temp_new();
4238 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4239 gen_helper_tlbie(t0);
4240 tcg_temp_free(t0);
4241 } else
4242 #endif
4243 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4244 #endif
4245 }
4246
4247 /* tlbsync */
4248 static void gen_tlbsync(DisasContext *ctx)
4249 {
4250 #if defined(CONFIG_USER_ONLY)
4251 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4252 #else
4253 if (unlikely(!ctx->mem_idx)) {
4254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4255 return;
4256 }
4257 /* This has no effect: it should ensure that all previous
4258 * tlbie have completed
4259 */
4260 gen_stop_exception(ctx);
4261 #endif
4262 }
4263
4264 #if defined(TARGET_PPC64)
4265 /* slbia */
4266 static void gen_slbia(DisasContext *ctx)
4267 {
4268 #if defined(CONFIG_USER_ONLY)
4269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4270 #else
4271 if (unlikely(!ctx->mem_idx)) {
4272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4273 return;
4274 }
4275 gen_helper_slbia();
4276 #endif
4277 }
4278
4279 /* slbie */
4280 static void gen_slbie(DisasContext *ctx)
4281 {
4282 #if defined(CONFIG_USER_ONLY)
4283 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4284 #else
4285 if (unlikely(!ctx->mem_idx)) {
4286 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4287 return;
4288 }
4289 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4290 #endif
4291 }
4292 #endif
4293
4294 /*** External control ***/
4295 /* Optional: */
4296
4297 /* eciwx */
4298 static void gen_eciwx(DisasContext *ctx)
4299 {
4300 TCGv t0;
4301 /* Should check EAR[E] ! */
4302 gen_set_access_type(ctx, ACCESS_EXT);
4303 t0 = tcg_temp_new();
4304 gen_addr_reg_index(ctx, t0);
4305 gen_check_align(ctx, t0, 0x03);
4306 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4307 tcg_temp_free(t0);
4308 }
4309
4310 /* ecowx */
4311 static void gen_ecowx(DisasContext *ctx)
4312 {
4313 TCGv t0;
4314 /* Should check EAR[E] ! */
4315 gen_set_access_type(ctx, ACCESS_EXT);
4316 t0 = tcg_temp_new();
4317 gen_addr_reg_index(ctx, t0);
4318 gen_check_align(ctx, t0, 0x03);
4319 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4320 tcg_temp_free(t0);
4321 }
4322
4323 /* PowerPC 601 specific instructions */
4324
4325 /* abs - abs. */
4326 static void gen_abs(DisasContext *ctx)
4327 {
4328 int l1 = gen_new_label();
4329 int l2 = gen_new_label();
4330 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4331 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4332 tcg_gen_br(l2);
4333 gen_set_label(l1);
4334 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4335 gen_set_label(l2);
4336 if (unlikely(Rc(ctx->opcode) != 0))
4337 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4338 }
4339
4340 /* abso - abso. */
4341 static void gen_abso(DisasContext *ctx)
4342 {
4343 int l1 = gen_new_label();
4344 int l2 = gen_new_label();
4345 int l3 = gen_new_label();
4346 /* Start with XER OV disabled, the most likely case */
4347 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4348 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4349 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4350 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4351 tcg_gen_br(l2);
4352 gen_set_label(l1);
4353 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4354 tcg_gen_br(l3);
4355 gen_set_label(l2);
4356 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4357 gen_set_label(l3);
4358 if (unlikely(Rc(ctx->opcode) != 0))
4359 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4360 }
4361
4362 /* clcs */
4363 static void gen_clcs(DisasContext *ctx)
4364 {
4365 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4366 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4367 tcg_temp_free_i32(t0);
4368 /* Rc=1 sets CR0 to an undefined state */
4369 }
4370
4371 /* div - div. */
4372 static void gen_div(DisasContext *ctx)
4373 {
4374 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4375 if (unlikely(Rc(ctx->opcode) != 0))
4376 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4377 }
4378
4379 /* divo - divo. */
4380 static void gen_divo(DisasContext *ctx)
4381 {
4382 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4383 if (unlikely(Rc(ctx->opcode) != 0))
4384 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4385 }
4386
4387 /* divs - divs. */
4388 static void gen_divs(DisasContext *ctx)
4389 {
4390 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4391 if (unlikely(Rc(ctx->opcode) != 0))
4392 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4393 }
4394
4395 /* divso - divso. */
4396 static void gen_divso(DisasContext *ctx)
4397 {
4398 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4399 if (unlikely(Rc(ctx->opcode) != 0))
4400 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4401 }
4402
4403 /* doz - doz. */
4404 static void gen_doz(DisasContext *ctx)
4405 {
4406 int l1 = gen_new_label();
4407 int l2 = gen_new_label();
4408 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4409 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4410 tcg_gen_br(l2);
4411 gen_set_label(l1);
4412 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4413 gen_set_label(l2);
4414 if (unlikely(Rc(ctx->opcode) != 0))
4415 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4416 }
4417
4418 /* dozo - dozo. */
4419 static void gen_dozo(DisasContext *ctx)
4420 {
4421 int l1 = gen_new_label();
4422 int l2 = gen_new_label();
4423 TCGv t0 = tcg_temp_new();
4424 TCGv t1 = tcg_temp_new();
4425 TCGv t2 = tcg_temp_new();
4426 /* Start with XER OV disabled, the most likely case */
4427 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4428 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4429 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4430 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4431 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4432 tcg_gen_andc_tl(t1, t1, t2);
4433 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4434 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4435 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4436 tcg_gen_br(l2);
4437 gen_set_label(l1);
4438 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4439 gen_set_label(l2);
4440 tcg_temp_free(t0);
4441 tcg_temp_free(t1);
4442 tcg_temp_free(t2);
4443 if (unlikely(Rc(ctx->opcode) != 0))
4444 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4445 }
4446
4447 /* dozi */
4448 static void gen_dozi(DisasContext *ctx)
4449 {
4450 target_long simm = SIMM(ctx->opcode);
4451 int l1 = gen_new_label();
4452 int l2 = gen_new_label();
4453 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4454 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4455 tcg_gen_br(l2);
4456 gen_set_label(l1);
4457 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4458 gen_set_label(l2);
4459 if (unlikely(Rc(ctx->opcode) != 0))
4460 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4461 }
4462
4463 /* lscbx - lscbx. */
4464 static void gen_lscbx(DisasContext *ctx)
4465 {
4466 TCGv t0 = tcg_temp_new();
4467 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4468 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4469 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4470
4471 gen_addr_reg_index(ctx, t0);
4472 /* NIP cannot be restored if the memory exception comes from an helper */
4473 gen_update_nip(ctx, ctx->nip - 4);
4474 gen_helper_lscbx(t0, t0, t1, t2, t3);
4475 tcg_temp_free_i32(t1);
4476 tcg_temp_free_i32(t2);
4477 tcg_temp_free_i32(t3);
4478 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4479 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4480 if (unlikely(Rc(ctx->opcode) != 0))
4481 gen_set_Rc0(ctx, t0);
4482 tcg_temp_free(t0);
4483 }
4484
4485 /* maskg - maskg. */
4486 static void gen_maskg(DisasContext *ctx)
4487 {
4488 int l1 = gen_new_label();
4489 TCGv t0 = tcg_temp_new();
4490 TCGv t1 = tcg_temp_new();
4491 TCGv t2 = tcg_temp_new();
4492 TCGv t3 = tcg_temp_new();
4493 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4494 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4495 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4496 tcg_gen_addi_tl(t2, t0, 1);
4497 tcg_gen_shr_tl(t2, t3, t2);
4498 tcg_gen_shr_tl(t3, t3, t1);
4499 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4500 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4501 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4502 gen_set_label(l1);
4503 tcg_temp_free(t0);
4504 tcg_temp_free(t1);
4505 tcg_temp_free(t2);
4506 tcg_temp_free(t3);
4507 if (unlikely(Rc(ctx->opcode) != 0))
4508 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4509 }
4510
4511 /* maskir - maskir. */
4512 static void gen_maskir(DisasContext *ctx)
4513 {
4514 TCGv t0 = tcg_temp_new();
4515 TCGv t1 = tcg_temp_new();
4516 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4517 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4518 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4519 tcg_temp_free(t0);
4520 tcg_temp_free(t1);
4521 if (unlikely(Rc(ctx->opcode) != 0))
4522 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4523 }
4524
4525 /* mul - mul. */
4526 static void gen_mul(DisasContext *ctx)
4527 {
4528 TCGv_i64 t0 = tcg_temp_new_i64();
4529 TCGv_i64 t1 = tcg_temp_new_i64();
4530 TCGv t2 = tcg_temp_new();
4531 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4532 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4533 tcg_gen_mul_i64(t0, t0, t1);
4534 tcg_gen_trunc_i64_tl(t2, t0);
4535 gen_store_spr(SPR_MQ, t2);
4536 tcg_gen_shri_i64(t1, t0, 32);
4537 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4538 tcg_temp_free_i64(t0);
4539 tcg_temp_free_i64(t1);
4540 tcg_temp_free(t2);
4541 if (unlikely(Rc(ctx->opcode) != 0))
4542 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4543 }
4544
4545 /* mulo - mulo. */
4546 static void gen_mulo(DisasContext *ctx)
4547 {
4548 int l1 = gen_new_label();
4549 TCGv_i64 t0 = tcg_temp_new_i64();
4550 TCGv_i64 t1 = tcg_temp_new_i64();
4551 TCGv t2 = tcg_temp_new();
4552 /* Start with XER OV disabled, the most likely case */
4553 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4554 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4555 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4556 tcg_gen_mul_i64(t0, t0, t1);
4557 tcg_gen_trunc_i64_tl(t2, t0);
4558 gen_store_spr(SPR_MQ, t2);
4559 tcg_gen_shri_i64(t1, t0, 32);
4560 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4561 tcg_gen_ext32s_i64(t1, t0);
4562 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4563 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4564 gen_set_label(l1);
4565 tcg_temp_free_i64(t0);
4566 tcg_temp_free_i64(t1);
4567 tcg_temp_free(t2);
4568 if (unlikely(Rc(ctx->opcode) != 0))
4569 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4570 }
4571
4572 /* nabs - nabs. */
4573 static void gen_nabs(DisasContext *ctx)
4574 {
4575 int l1 = gen_new_label();
4576 int l2 = gen_new_label();
4577 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4578 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4579 tcg_gen_br(l2);
4580 gen_set_label(l1);
4581 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4582 gen_set_label(l2);
4583 if (unlikely(Rc(ctx->opcode) != 0))
4584 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4585 }
4586
4587 /* nabso - nabso. */
4588 static void gen_nabso(DisasContext *ctx)
4589 {
4590 int l1 = gen_new_label();
4591 int l2 = gen_new_label();
4592 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4593 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4594 tcg_gen_br(l2);
4595 gen_set_label(l1);
4596 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4597 gen_set_label(l2);
4598 /* nabs never overflows */
4599 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4600 if (unlikely(Rc(ctx->opcode) != 0))
4601 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4602 }
4603
4604 /* rlmi - rlmi. */
4605 static void gen_rlmi(DisasContext *ctx)
4606 {
4607 uint32_t mb = MB(ctx->opcode);
4608 uint32_t me = ME(ctx->opcode);
4609 TCGv t0 = tcg_temp_new();
4610 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4611 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4612 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4613 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4614 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4615 tcg_temp_free(t0);
4616 if (unlikely(Rc(ctx->opcode) != 0))
4617 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4618 }
4619
4620 /* rrib - rrib. */
4621 static void gen_rrib(DisasContext *ctx)
4622 {
4623 TCGv t0 = tcg_temp_new();
4624 TCGv t1 = tcg_temp_new();
4625 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4626 tcg_gen_movi_tl(t1, 0x80000000);
4627 tcg_gen_shr_tl(t1, t1, t0);
4628 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4629 tcg_gen_and_tl(t0, t0, t1);
4630 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4631 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4632 tcg_temp_free(t0);
4633 tcg_temp_free(t1);
4634 if (unlikely(Rc(ctx->opcode) != 0))
4635 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4636 }
4637
4638 /* sle - sle. */
4639 static void gen_sle(DisasContext *ctx)
4640 {
4641 TCGv t0 = tcg_temp_new();
4642 TCGv t1 = tcg_temp_new();
4643 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4644 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4645 tcg_gen_subfi_tl(t1, 32, t1);
4646 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4647 tcg_gen_or_tl(t1, t0, t1);
4648 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4649 gen_store_spr(SPR_MQ, t1);
4650 tcg_temp_free(t0);
4651 tcg_temp_free(t1);
4652 if (unlikely(Rc(ctx->opcode) != 0))
4653 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4654 }
4655
4656 /* sleq - sleq. */
4657 static void gen_sleq(DisasContext *ctx)
4658 {
4659 TCGv t0 = tcg_temp_new();
4660 TCGv t1 = tcg_temp_new();
4661 TCGv t2 = tcg_temp_new();
4662 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4663 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4664 tcg_gen_shl_tl(t2, t2, t0);
4665 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4666 gen_load_spr(t1, SPR_MQ);
4667 gen_store_spr(SPR_MQ, t0);
4668 tcg_gen_and_tl(t0, t0, t2);
4669 tcg_gen_andc_tl(t1, t1, t2);
4670 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4671 tcg_temp_free(t0);
4672 tcg_temp_free(t1);
4673 tcg_temp_free(t2);
4674 if (unlikely(Rc(ctx->opcode) != 0))
4675 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4676 }
4677
4678 /* sliq - sliq. */
4679 static void gen_sliq(DisasContext *ctx)
4680 {
4681 int sh = SH(ctx->opcode);
4682 TCGv t0 = tcg_temp_new();
4683 TCGv t1 = tcg_temp_new();
4684 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4685 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4686 tcg_gen_or_tl(t1, t0, t1);
4687 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4688 gen_store_spr(SPR_MQ, t1);
4689 tcg_temp_free(t0);
4690 tcg_temp_free(t1);
4691 if (unlikely(Rc(ctx->opcode) != 0))
4692 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4693 }
4694
4695 /* slliq - slliq. */
4696 static void gen_slliq(DisasContext *ctx)
4697 {
4698 int sh = SH(ctx->opcode);
4699 TCGv t0 = tcg_temp_new();
4700 TCGv t1 = tcg_temp_new();
4701 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4702 gen_load_spr(t1, SPR_MQ);
4703 gen_store_spr(SPR_MQ, t0);
4704 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4705 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4706 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4707 tcg_temp_free(t0);
4708 tcg_temp_free(t1);
4709 if (unlikely(Rc(ctx->opcode) != 0))
4710 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4711 }
4712
4713 /* sllq - sllq. */
4714 static void gen_sllq(DisasContext *ctx)
4715 {
4716 int l1 = gen_new_label();
4717 int l2 = gen_new_label();
4718 TCGv t0 = tcg_temp_local_new();
4719 TCGv t1 = tcg_temp_local_new();
4720 TCGv t2 = tcg_temp_local_new();
4721 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4722 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4723 tcg_gen_shl_tl(t1, t1, t2);
4724 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4725 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4726 gen_load_spr(t0, SPR_MQ);
4727 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4728 tcg_gen_br(l2);
4729 gen_set_label(l1);
4730 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4731 gen_load_spr(t2, SPR_MQ);
4732 tcg_gen_andc_tl(t1, t2, t1);
4733 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4734 gen_set_label(l2);
4735 tcg_temp_free(t0);
4736 tcg_temp_free(t1);
4737 tcg_temp_free(t2);
4738 if (unlikely(Rc(ctx->opcode) != 0))
4739 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4740 }
4741
4742 /* slq - slq. */
4743 static void gen_slq(DisasContext *ctx)
4744 {
4745 int l1 = gen_new_label();
4746 TCGv t0 = tcg_temp_new();
4747 TCGv t1 = tcg_temp_new();
4748 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4749 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4750 tcg_gen_subfi_tl(t1, 32, t1);
4751 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4752 tcg_gen_or_tl(t1, t0, t1);
4753 gen_store_spr(SPR_MQ, t1);
4754 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4755 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4756 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4757 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4758 gen_set_label(l1);
4759 tcg_temp_free(t0);
4760 tcg_temp_free(t1);
4761 if (unlikely(Rc(ctx->opcode) != 0))
4762 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4763 }
4764
4765 /* sraiq - sraiq. */
4766 static void gen_sraiq(DisasContext *ctx)
4767 {
4768 int sh = SH(ctx->opcode);
4769 int l1 = gen_new_label();
4770 TCGv t0 = tcg_temp_new();
4771 TCGv t1 = tcg_temp_new();
4772 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4773 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4774 tcg_gen_or_tl(t0, t0, t1);
4775 gen_store_spr(SPR_MQ, t0);
4776 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4777 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4778 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4779 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4780 gen_set_label(l1);
4781 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4782 tcg_temp_free(t0);
4783 tcg_temp_free(t1);
4784 if (unlikely(Rc(ctx->opcode) != 0))
4785 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4786 }
4787
4788 /* sraq - sraq. */
4789 static void gen_sraq(DisasContext *ctx)
4790 {
4791 int l1 = gen_new_label();
4792 int l2 = gen_new_label();
4793 TCGv t0 = tcg_temp_new();
4794 TCGv t1 = tcg_temp_local_new();
4795 TCGv t2 = tcg_temp_local_new();
4796 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4797 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4798 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4799 tcg_gen_subfi_tl(t2, 32, t2);
4800 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4801 tcg_gen_or_tl(t0, t0, t2);
4802 gen_store_spr(SPR_MQ, t0);
4803 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4804 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4805 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4806 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4807 gen_set_label(l1);
4808 tcg_temp_free(t0);
4809 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4810 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4811 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4812 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4813 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4814 gen_set_label(l2);
4815 tcg_temp_free(t1);
4816 tcg_temp_free(t2);
4817 if (unlikely(Rc(ctx->opcode) != 0))
4818 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4819 }
4820
4821 /* sre - sre. */
4822 static void gen_sre(DisasContext *ctx)
4823 {
4824 TCGv t0 = tcg_temp_new();
4825 TCGv t1 = tcg_temp_new();
4826 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4827 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4828 tcg_gen_subfi_tl(t1, 32, t1);
4829 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4830 tcg_gen_or_tl(t1, t0, t1);
4831 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4832 gen_store_spr(SPR_MQ, t1);
4833 tcg_temp_free(t0);
4834 tcg_temp_free(t1);
4835 if (unlikely(Rc(ctx->opcode) != 0))
4836 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4837 }
4838
4839 /* srea - srea. */
4840 static void gen_srea(DisasContext *ctx)
4841 {
4842 TCGv t0 = tcg_temp_new();
4843 TCGv t1 = tcg_temp_new();
4844 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4845 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4846 gen_store_spr(SPR_MQ, t0);
4847 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4848 tcg_temp_free(t0);
4849 tcg_temp_free(t1);
4850 if (unlikely(Rc(ctx->opcode) != 0))
4851 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4852 }
4853
4854 /* sreq */
4855 static void gen_sreq(DisasContext *ctx)
4856 {
4857 TCGv t0 = tcg_temp_new();
4858 TCGv t1 = tcg_temp_new();
4859 TCGv t2 = tcg_temp_new();
4860 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4861 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4862 tcg_gen_shr_tl(t1, t1, t0);
4863 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4864 gen_load_spr(t2, SPR_MQ);
4865 gen_store_spr(SPR_MQ, t0);
4866 tcg_gen_and_tl(t0, t0, t1);
4867 tcg_gen_andc_tl(t2, t2, t1);
4868 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4869 tcg_temp_free(t0);
4870 tcg_temp_free(t1);
4871 tcg_temp_free(t2);
4872 if (unlikely(Rc(ctx->opcode) != 0))
4873 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4874 }
4875
4876 /* sriq */
4877 static void gen_sriq(DisasContext *ctx)
4878 {
4879 int sh = SH(ctx->opcode);
4880 TCGv t0 = tcg_temp_new();
4881 TCGv t1 = tcg_temp_new();
4882 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4883 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4884 tcg_gen_or_tl(t1, t0, t1);
4885 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4886 gen_store_spr(SPR_MQ, t1);
4887 tcg_temp_free(t0);
4888 tcg_temp_free(t1);
4889 if (unlikely(Rc(ctx->opcode) != 0))
4890 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4891 }
4892
4893 /* srliq */
4894 static void gen_srliq(DisasContext *ctx)
4895 {
4896 int sh = SH(ctx->opcode);
4897 TCGv t0 = tcg_temp_new();
4898 TCGv t1 = tcg_temp_new();
4899 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4900 gen_load_spr(t1, SPR_MQ);
4901 gen_store_spr(SPR_MQ, t0);
4902 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
4903 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
4904 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4905 tcg_temp_free(t0);
4906 tcg_temp_free(t1);
4907 if (unlikely(Rc(ctx->opcode) != 0))
4908 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4909 }
4910
4911 /* srlq */
4912 static void gen_srlq(DisasContext *ctx)
4913 {
4914 int l1 = gen_new_label();
4915 int l2 = gen_new_label();
4916 TCGv t0 = tcg_temp_local_new();
4917 TCGv t1 = tcg_temp_local_new();
4918 TCGv t2 = tcg_temp_local_new();
4919 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4920 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4921 tcg_gen_shr_tl(t2, t1, t2);
4922 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4923 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4924 gen_load_spr(t0, SPR_MQ);
4925 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4926 tcg_gen_br(l2);
4927 gen_set_label(l1);
4928 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4929 tcg_gen_and_tl(t0, t0, t2);
4930 gen_load_spr(t1, SPR_MQ);
4931 tcg_gen_andc_tl(t1, t1, t2);
4932 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4933 gen_set_label(l2);
4934 tcg_temp_free(t0);
4935 tcg_temp_free(t1);
4936 tcg_temp_free(t2);
4937 if (unlikely(Rc(ctx->opcode) != 0))
4938 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4939 }
4940
4941 /* srq */
4942 static void gen_srq(DisasContext *ctx)
4943 {
4944 int l1 = gen_new_label();
4945 TCGv t0 = tcg_temp_new();
4946 TCGv t1 = tcg_temp_new();
4947 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4948 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4949 tcg_gen_subfi_tl(t1, 32, t1);
4950 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4951 tcg_gen_or_tl(t1, t0, t1);
4952 gen_store_spr(SPR_MQ, t1);
4953 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4954 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4955 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4956 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4957 gen_set_label(l1);
4958 tcg_temp_free(t0);
4959 tcg_temp_free(t1);
4960 if (unlikely(Rc(ctx->opcode) != 0))
4961 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4962 }
4963
4964 /* PowerPC 602 specific instructions */
4965
4966 /* dsa */
4967 static void gen_dsa(DisasContext *ctx)
4968 {
4969 /* XXX: TODO */
4970 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4971 }
4972
4973 /* esa */
4974 static void gen_esa(DisasContext *ctx)
4975 {
4976 /* XXX: TODO */
4977 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4978 }
4979
4980 /* mfrom */
4981 static void gen_mfrom(DisasContext *ctx)
4982 {
4983 #if defined(CONFIG_USER_ONLY)
4984 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4985 #else
4986 if (unlikely(!ctx->mem_idx)) {
4987 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4988 return;
4989 }
4990 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4991 #endif
4992 }
4993
4994 /* 602 - 603 - G2 TLB management */
4995
4996 /* tlbld */
4997 static void gen_tlbld_6xx(DisasContext *ctx)
4998 {
4999 #if defined(CONFIG_USER_ONLY)
5000 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5001 #else
5002 if (unlikely(!ctx->mem_idx)) {
5003 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5004 return;
5005 }
5006 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5007 #endif
5008 }
5009
5010 /* tlbli */
5011 static void gen_tlbli_6xx(DisasContext *ctx)
5012 {
5013 #if defined(CONFIG_USER_ONLY)
5014 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5015 #else
5016 if (unlikely(!ctx->mem_idx)) {
5017 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5018 return;
5019 }
5020 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5021 #endif
5022 }
5023
5024 /* 74xx TLB management */
5025
5026 /* tlbld */
5027 static void gen_tlbld_74xx(DisasContext *ctx)
5028 {
5029 #if defined(CONFIG_USER_ONLY)
5030 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5031 #else
5032 if (unlikely(!ctx->mem_idx)) {
5033 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5034 return;
5035 }
5036 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5037 #endif
5038 }
5039
5040 /* tlbli */
5041 static void gen_tlbli_74xx(DisasContext *ctx)
5042 {
5043 #if defined(CONFIG_USER_ONLY)
5044 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5045 #else
5046 if (unlikely(!ctx->mem_idx)) {
5047 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5048 return;
5049 }
5050 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5051 #endif
5052 }
5053
5054 /* POWER instructions not in PowerPC 601 */
5055
5056 /* clf */
5057 static void gen_clf(DisasContext *ctx)
5058 {
5059 /* Cache line flush: implemented as no-op */
5060 }
5061
5062 /* cli */
5063 static void gen_cli(DisasContext *ctx)
5064 {
5065 /* Cache line invalidate: privileged and treated as no-op */
5066 #if defined(CONFIG_USER_ONLY)
5067 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5068 #else
5069 if (unlikely(!ctx->mem_idx)) {
5070 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5071 return;
5072 }
5073 #endif
5074 }
5075
5076 /* dclst */
5077 static void gen_dclst(DisasContext *ctx)
5078 {
5079 /* Data cache line store: treated as no-op */
5080 }
5081
5082 static void gen_mfsri(DisasContext *ctx)
5083 {
5084 #if defined(CONFIG_USER_ONLY)
5085 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5086 #else
5087 int ra = rA(ctx->opcode);
5088 int rd = rD(ctx->opcode);
5089 TCGv t0;
5090 if (unlikely(!ctx->mem_idx)) {
5091 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5092 return;
5093 }
5094 t0 = tcg_temp_new();
5095 gen_addr_reg_index(ctx, t0);
5096 tcg_gen_shri_tl(t0, t0, 28);
5097 tcg_gen_andi_tl(t0, t0, 0xF);
5098 gen_helper_load_sr(cpu_gpr[rd], t0);
5099 tcg_temp_free(t0);
5100 if (ra != 0 && ra != rd)
5101 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5102 #endif
5103 }
5104
5105 static void gen_rac(DisasContext *ctx)
5106 {
5107 #if defined(CONFIG_USER_ONLY)
5108 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5109 #else
5110 TCGv t0;
5111 if (unlikely(!ctx->mem_idx)) {
5112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5113 return;
5114 }
5115 t0 = tcg_temp_new();
5116 gen_addr_reg_index(ctx, t0);
5117 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5118 tcg_temp_free(t0);
5119 #endif
5120 }
5121
5122 static void gen_rfsvc(DisasContext *ctx)
5123 {
5124 #if defined(CONFIG_USER_ONLY)
5125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5126 #else
5127 if (unlikely(!ctx->mem_idx)) {
5128 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5129 return;
5130 }
5131 gen_helper_rfsvc();
5132 gen_sync_exception(ctx);
5133 #endif
5134 }
5135
5136 /* svc is not implemented for now */
5137
5138 /* POWER2 specific instructions */
5139 /* Quad manipulation (load/store two floats at a time) */
5140
5141 /* lfq */
5142 static void gen_lfq(DisasContext *ctx)
5143 {
5144 int rd = rD(ctx->opcode);
5145 TCGv t0;
5146 gen_set_access_type(ctx, ACCESS_FLOAT);
5147 t0 = tcg_temp_new();
5148 gen_addr_imm_index(ctx, t0, 0);
5149 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5150 gen_addr_add(ctx, t0, t0, 8);
5151 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5152 tcg_temp_free(t0);
5153 }
5154
5155 /* lfqu */
5156 static void gen_lfqu(DisasContext *ctx)
5157 {
5158 int ra = rA(ctx->opcode);
5159 int rd = rD(ctx->opcode);
5160 TCGv t0, t1;
5161 gen_set_access_type(ctx, ACCESS_FLOAT);
5162 t0 = tcg_temp_new();
5163 t1 = tcg_temp_new();
5164 gen_addr_imm_index(ctx, t0, 0);
5165 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5166 gen_addr_add(ctx, t1, t0, 8);
5167 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5168 if (ra != 0)
5169 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5170 tcg_temp_free(t0);
5171 tcg_temp_free(t1);
5172 }
5173
5174 /* lfqux */
5175 static void gen_lfqux(DisasContext *ctx)
5176 {
5177 int ra = rA(ctx->opcode);
5178 int rd = rD(ctx->opcode);
5179 gen_set_access_type(ctx, ACCESS_FLOAT);
5180 TCGv t0, t1;
5181 t0 = tcg_temp_new();
5182 gen_addr_reg_index(ctx, t0);
5183 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5184 t1 = tcg_temp_new();
5185 gen_addr_add(ctx, t1, t0, 8);
5186 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5187 tcg_temp_free(t1);
5188 if (ra != 0)
5189 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5190 tcg_temp_free(t0);
5191 }
5192
5193 /* lfqx */
5194 static void gen_lfqx(DisasContext *ctx)
5195 {
5196 int rd = rD(ctx->opcode);
5197 TCGv t0;
5198 gen_set_access_type(ctx, ACCESS_FLOAT);
5199 t0 = tcg_temp_new();
5200 gen_addr_reg_index(ctx, t0);
5201 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5202 gen_addr_add(ctx, t0, t0, 8);
5203 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5204 tcg_temp_free(t0);
5205 }
5206
5207 /* stfq */
5208 static void gen_stfq(DisasContext *ctx)
5209 {
5210 int rd = rD(ctx->opcode);
5211 TCGv t0;
5212 gen_set_access_type(ctx, ACCESS_FLOAT);
5213 t0 = tcg_temp_new();
5214 gen_addr_imm_index(ctx, t0, 0);
5215 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5216 gen_addr_add(ctx, t0, t0, 8);
5217 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5218 tcg_temp_free(t0);
5219 }
5220
5221 /* stfqu */
5222 static void gen_stfqu(DisasContext *ctx)
5223 {
5224 int ra = rA(ctx->opcode);
5225 int rd = rD(ctx->opcode);
5226 TCGv t0, t1;
5227 gen_set_access_type(ctx, ACCESS_FLOAT);
5228 t0 = tcg_temp_new();
5229 gen_addr_imm_index(ctx, t0, 0);
5230 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5231 t1 = tcg_temp_new();
5232 gen_addr_add(ctx, t1, t0, 8);
5233 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5234 tcg_temp_free(t1);
5235 if (ra != 0)
5236 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5237 tcg_temp_free(t0);
5238 }
5239
5240 /* stfqux */
5241 static void gen_stfqux(DisasContext *ctx)
5242 {
5243 int ra = rA(ctx->opcode);
5244 int rd = rD(ctx->opcode);
5245 TCGv t0, t1;
5246 gen_set_access_type(ctx, ACCESS_FLOAT);
5247 t0 = tcg_temp_new();
5248 gen_addr_reg_index(ctx, t0);
5249 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5250 t1 = tcg_temp_new();
5251 gen_addr_add(ctx, t1, t0, 8);
5252 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5253 tcg_temp_free(t1);
5254 if (ra != 0)
5255 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5256 tcg_temp_free(t0);
5257 }
5258
5259 /* stfqx */
5260 static void gen_stfqx(DisasContext *ctx)
5261 {
5262 int rd = rD(ctx->opcode);
5263 TCGv t0;
5264 gen_set_access_type(ctx, ACCESS_FLOAT);
5265 t0 = tcg_temp_new();
5266 gen_addr_reg_index(ctx, t0);
5267 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5268 gen_addr_add(ctx, t0, t0, 8);
5269 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5270 tcg_temp_free(t0);
5271 }
5272
5273 /* BookE specific instructions */
5274
5275 /* XXX: not implemented on 440 ? */
5276 static void gen_mfapidi(DisasContext *ctx)
5277 {
5278 /* XXX: TODO */
5279 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5280 }
5281
5282 /* XXX: not implemented on 440 ? */
5283 static void gen_tlbiva(DisasContext *ctx)
5284 {
5285 #if defined(CONFIG_USER_ONLY)
5286 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5287 #else
5288 TCGv t0;
5289 if (unlikely(!ctx->mem_idx)) {
5290 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5291 return;
5292 }
5293 t0 = tcg_temp_new();
5294 gen_addr_reg_index(ctx, t0);
5295 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5296 tcg_temp_free(t0);
5297 #endif
5298 }
5299
5300 /* All 405 MAC instructions are translated here */
5301 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5302 int opc2, int opc3,
5303 int ra, int rb, int rt, int Rc)
5304 {
5305 TCGv t0, t1;
5306
5307 t0 = tcg_temp_local_new();
5308 t1 = tcg_temp_local_new();
5309
5310 switch (opc3 & 0x0D) {
5311 case 0x05:
5312 /* macchw - macchw. - macchwo - macchwo. */
5313 /* macchws - macchws. - macchwso - macchwso. */
5314 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5315 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5316 /* mulchw - mulchw. */
5317 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5318 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5319 tcg_gen_ext16s_tl(t1, t1);
5320 break;
5321 case 0x04:
5322 /* macchwu - macchwu. - macchwuo - macchwuo. */
5323 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5324 /* mulchwu - mulchwu. */
5325 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5326 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5327 tcg_gen_ext16u_tl(t1, t1);
5328 break;
5329 case 0x01:
5330 /* machhw - machhw. - machhwo - machhwo. */
5331 /* machhws - machhws. - machhwso - machhwso. */
5332 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5333 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5334 /* mulhhw - mulhhw. */
5335 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5336 tcg_gen_ext16s_tl(t0, t0);
5337 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5338 tcg_gen_ext16s_tl(t1, t1);
5339 break;
5340 case 0x00:
5341 /* machhwu - machhwu. - machhwuo - machhwuo. */
5342 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5343 /* mulhhwu - mulhhwu. */
5344 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5345 tcg_gen_ext16u_tl(t0, t0);
5346 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5347 tcg_gen_ext16u_tl(t1, t1);
5348 break;
5349 case 0x0D:
5350 /* maclhw - maclhw. - maclhwo - maclhwo. */
5351 /* maclhws - maclhws. - maclhwso - maclhwso. */
5352 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5353 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5354 /* mullhw - mullhw. */
5355 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5356 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5357 break;
5358 case 0x0C:
5359 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5360 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5361 /* mullhwu - mullhwu. */
5362 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5363 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5364 break;
5365 }
5366 if (opc2 & 0x04) {
5367 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5368 tcg_gen_mul_tl(t1, t0, t1);
5369 if (opc2 & 0x02) {
5370 /* nmultiply-and-accumulate (0x0E) */
5371 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5372 } else {
5373 /* multiply-and-accumulate (0x0C) */
5374 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5375 }
5376
5377 if (opc3 & 0x12) {
5378 /* Check overflow and/or saturate */
5379 int l1 = gen_new_label();
5380
5381 if (opc3 & 0x10) {
5382 /* Start with XER OV disabled, the most likely case */
5383 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5384 }
5385 if (opc3 & 0x01) {
5386 /* Signed */
5387 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5388 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5389 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5390 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5391 if (opc3 & 0x02) {
5392 /* Saturate */
5393 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5394 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5395 }
5396 } else {
5397 /* Unsigned */
5398 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5399 if (opc3 & 0x02) {
5400 /* Saturate */
5401 tcg_gen_movi_tl(t0, UINT32_MAX);
5402 }
5403 }
5404 if (opc3 & 0x10) {
5405 /* Check overflow */
5406 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5407 }
5408 gen_set_label(l1);
5409 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5410 }
5411 } else {
5412 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5413 }
5414 tcg_temp_free(t0);
5415 tcg_temp_free(t1);
5416 if (unlikely(Rc) != 0) {
5417 /* Update Rc0 */
5418 gen_set_Rc0(ctx, cpu_gpr[rt]);
5419 }
5420 }
5421
5422 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5423 static void glue(gen_, name)(DisasContext *ctx) \
5424 { \
5425 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5426 rD(ctx->opcode), Rc(ctx->opcode)); \
5427 }
5428
5429 /* macchw - macchw. */
5430 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5431 /* macchwo - macchwo. */
5432 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5433 /* macchws - macchws. */
5434 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5435 /* macchwso - macchwso. */
5436 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5437 /* macchwsu - macchwsu. */
5438 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5439 /* macchwsuo - macchwsuo. */
5440 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5441 /* macchwu - macchwu. */
5442 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5443 /* macchwuo - macchwuo. */
5444 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5445 /* machhw - machhw. */
5446 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5447 /* machhwo - machhwo. */
5448 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5449 /* machhws - machhws. */
5450 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5451 /* machhwso - machhwso. */
5452 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5453 /* machhwsu - machhwsu. */
5454 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5455 /* machhwsuo - machhwsuo. */
5456 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5457 /* machhwu - machhwu. */
5458 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5459 /* machhwuo - machhwuo. */
5460 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5461 /* maclhw - maclhw. */
5462 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5463 /* maclhwo - maclhwo. */
5464 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5465 /* maclhws - maclhws. */
5466 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5467 /* maclhwso - maclhwso. */
5468 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5469 /* maclhwu - maclhwu. */
5470 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5471 /* maclhwuo - maclhwuo. */
5472 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5473 /* maclhwsu - maclhwsu. */
5474 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5475 /* maclhwsuo - maclhwsuo. */
5476 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5477 /* nmacchw - nmacchw. */
5478 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5479 /* nmacchwo - nmacchwo. */
5480 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5481 /* nmacchws - nmacchws. */
5482 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5483 /* nmacchwso - nmacchwso. */
5484 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5485 /* nmachhw - nmachhw. */
5486 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5487 /* nmachhwo - nmachhwo. */
5488 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5489 /* nmachhws - nmachhws. */
5490 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5491 /* nmachhwso - nmachhwso. */
5492 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5493 /* nmaclhw - nmaclhw. */
5494 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5495 /* nmaclhwo - nmaclhwo. */
5496 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5497 /* nmaclhws - nmaclhws. */
5498 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5499 /* nmaclhwso - nmaclhwso. */
5500 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5501
5502 /* mulchw - mulchw. */
5503 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5504 /* mulchwu - mulchwu. */
5505 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5506 /* mulhhw - mulhhw. */
5507 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5508 /* mulhhwu - mulhhwu. */
5509 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5510 /* mullhw - mullhw. */
5511 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5512 /* mullhwu - mullhwu. */
5513 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5514
5515 /* mfdcr */
5516 static void gen_mfdcr(DisasContext *ctx)
5517 {
5518 #if defined(CONFIG_USER_ONLY)
5519 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5520 #else
5521 TCGv dcrn;
5522 if (unlikely(!ctx->mem_idx)) {
5523 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5524 return;
5525 }
5526 /* NIP cannot be restored if the memory exception comes from an helper */
5527 gen_update_nip(ctx, ctx->nip - 4);
5528 dcrn = tcg_const_tl(SPR(ctx->opcode));
5529 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5530 tcg_temp_free(dcrn);
5531 #endif
5532 }
5533
5534 /* mtdcr */
5535 static void gen_mtdcr(DisasContext *ctx)
5536 {
5537 #if defined(CONFIG_USER_ONLY)
5538 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5539 #else
5540 TCGv dcrn;
5541 if (unlikely(!ctx->mem_idx)) {
5542 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5543 return;
5544 }
5545 /* NIP cannot be restored if the memory exception comes from an helper */
5546 gen_update_nip(ctx, ctx->nip - 4);
5547 dcrn = tcg_const_tl(SPR(ctx->opcode));
5548 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5549 tcg_temp_free(dcrn);
5550 #endif
5551 }
5552
5553 /* mfdcrx */
5554 /* XXX: not implemented on 440 ? */
5555 static void gen_mfdcrx(DisasContext *ctx)
5556 {
5557 #if defined(CONFIG_USER_ONLY)
5558 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5559 #else
5560 if (unlikely(!ctx->mem_idx)) {
5561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5562 return;
5563 }
5564 /* NIP cannot be restored if the memory exception comes from an helper */
5565 gen_update_nip(ctx, ctx->nip - 4);
5566 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5567 /* Note: Rc update flag set leads to undefined state of Rc0 */
5568 #endif
5569 }
5570
5571 /* mtdcrx */
5572 /* XXX: not implemented on 440 ? */
5573 static void gen_mtdcrx(DisasContext *ctx)
5574 {
5575 #if defined(CONFIG_USER_ONLY)
5576 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5577 #else
5578 if (unlikely(!ctx->mem_idx)) {
5579 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5580 return;
5581 }
5582 /* NIP cannot be restored if the memory exception comes from an helper */
5583 gen_update_nip(ctx, ctx->nip - 4);
5584 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5585 /* Note: Rc update flag set leads to undefined state of Rc0 */
5586 #endif
5587 }
5588
5589 /* mfdcrux (PPC 460) : user-mode access to DCR */
5590 static void gen_mfdcrux(DisasContext *ctx)
5591 {
5592 /* NIP cannot be restored if the memory exception comes from an helper */
5593 gen_update_nip(ctx, ctx->nip - 4);
5594 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5595 /* Note: Rc update flag set leads to undefined state of Rc0 */
5596 }
5597
5598 /* mtdcrux (PPC 460) : user-mode access to DCR */
5599 static void gen_mtdcrux(DisasContext *ctx)
5600 {
5601 /* NIP cannot be restored if the memory exception comes from an helper */
5602 gen_update_nip(ctx, ctx->nip - 4);
5603 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5604 /* Note: Rc update flag set leads to undefined state of Rc0 */
5605 }
5606
5607 /* dccci */
5608 static void gen_dccci(DisasContext *ctx)
5609 {
5610 #if defined(CONFIG_USER_ONLY)
5611 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5612 #else
5613 if (unlikely(!ctx->mem_idx)) {
5614 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5615 return;
5616 }
5617 /* interpreted as no-op */
5618 #endif
5619 }
5620
5621 /* dcread */
5622 static void gen_dcread(DisasContext *ctx)
5623 {
5624 #if defined(CONFIG_USER_ONLY)
5625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5626 #else
5627 TCGv EA, val;
5628 if (unlikely(!ctx->mem_idx)) {
5629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5630 return;
5631 }
5632 gen_set_access_type(ctx, ACCESS_CACHE);
5633 EA = tcg_temp_new();
5634 gen_addr_reg_index(ctx, EA);
5635 val = tcg_temp_new();
5636 gen_qemu_ld32u(ctx, val, EA);
5637 tcg_temp_free(val);
5638 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5639 tcg_temp_free(EA);
5640 #endif
5641 }
5642
5643 /* icbt */
5644 static void gen_icbt_40x(DisasContext *ctx)
5645 {
5646 /* interpreted as no-op */
5647 /* XXX: specification say this is treated as a load by the MMU
5648 * but does not generate any exception
5649 */
5650 }
5651
5652 /* iccci */
5653 static void gen_iccci(DisasContext *ctx)
5654 {
5655 #if defined(CONFIG_USER_ONLY)
5656 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5657 #else
5658 if (unlikely(!ctx->mem_idx)) {
5659 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5660 return;
5661 }
5662 /* interpreted as no-op */
5663 #endif
5664 }
5665
5666 /* icread */
5667 static void gen_icread(DisasContext *ctx)
5668 {
5669 #if defined(CONFIG_USER_ONLY)
5670 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5671 #else
5672 if (unlikely(!ctx->mem_idx)) {
5673 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5674 return;
5675 }
5676 /* interpreted as no-op */
5677 #endif
5678 }
5679
5680 /* rfci (mem_idx only) */
5681 static void gen_rfci_40x(DisasContext *ctx)
5682 {
5683 #if defined(CONFIG_USER_ONLY)
5684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5685 #else
5686 if (unlikely(!ctx->mem_idx)) {
5687 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5688 return;
5689 }
5690 /* Restore CPU state */
5691 gen_helper_40x_rfci();
5692 gen_sync_exception(ctx);
5693 #endif
5694 }
5695
5696 static void gen_rfci(DisasContext *ctx)
5697 {
5698 #if defined(CONFIG_USER_ONLY)
5699 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5700 #else
5701 if (unlikely(!ctx->mem_idx)) {
5702 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5703 return;
5704 }
5705 /* Restore CPU state */
5706 gen_helper_rfci();
5707 gen_sync_exception(ctx);
5708 #endif
5709 }
5710
5711 /* BookE specific */
5712
5713 /* XXX: not implemented on 440 ? */
5714 static void gen_rfdi(DisasContext *ctx)
5715 {
5716 #if defined(CONFIG_USER_ONLY)
5717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5718 #else
5719 if (unlikely(!ctx->mem_idx)) {
5720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5721 return;
5722 }
5723 /* Restore CPU state */
5724 gen_helper_rfdi();
5725 gen_sync_exception(ctx);
5726 #endif
5727 }
5728
5729 /* XXX: not implemented on 440 ? */
5730 static void gen_rfmci(DisasContext *ctx)
5731 {
5732 #if defined(CONFIG_USER_ONLY)
5733 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5734 #else
5735 if (unlikely(!ctx->mem_idx)) {
5736 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5737 return;
5738 }
5739 /* Restore CPU state */
5740 gen_helper_rfmci();
5741 gen_sync_exception(ctx);
5742 #endif
5743 }
5744
5745 /* TLB management - PowerPC 405 implementation */
5746
5747 /* tlbre */
5748 static void gen_tlbre_40x(DisasContext *ctx)
5749 {
5750 #if defined(CONFIG_USER_ONLY)
5751 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5752 #else
5753 if (unlikely(!ctx->mem_idx)) {
5754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5755 return;
5756 }
5757 switch (rB(ctx->opcode)) {
5758 case 0:
5759 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5760 break;
5761 case 1:
5762 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5763 break;
5764 default:
5765 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5766 break;
5767 }
5768 #endif
5769 }
5770
5771 /* tlbsx - tlbsx. */
5772 static void gen_tlbsx_40x(DisasContext *ctx)
5773 {
5774 #if defined(CONFIG_USER_ONLY)
5775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5776 #else
5777 TCGv t0;
5778 if (unlikely(!ctx->mem_idx)) {
5779 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5780 return;
5781 }
5782 t0 = tcg_temp_new();
5783 gen_addr_reg_index(ctx, t0);
5784 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5785 tcg_temp_free(t0);
5786 if (Rc(ctx->opcode)) {
5787 int l1 = gen_new_label();
5788 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5789 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5790 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5791 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5792 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5793 gen_set_label(l1);
5794 }
5795 #endif
5796 }
5797
5798 /* tlbwe */
5799 static void gen_tlbwe_40x(DisasContext *ctx)
5800 {
5801 #if defined(CONFIG_USER_ONLY)
5802 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5803 #else
5804 if (unlikely(!ctx->mem_idx)) {
5805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5806 return;
5807 }
5808 switch (rB(ctx->opcode)) {
5809 case 0:
5810 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5811 break;
5812 case 1:
5813 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5814 break;
5815 default:
5816 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5817 break;
5818 }
5819 #endif
5820 }
5821
5822 /* TLB management - PowerPC 440 implementation */
5823
5824 /* tlbre */
5825 static void gen_tlbre_440(DisasContext *ctx)
5826 {
5827 #if defined(CONFIG_USER_ONLY)
5828 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5829 #else
5830 if (unlikely(!ctx->mem_idx)) {
5831 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5832 return;
5833 }
5834 switch (rB(ctx->opcode)) {
5835 case 0:
5836 case 1:
5837 case 2:
5838 {
5839 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5840 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5841 tcg_temp_free_i32(t0);
5842 }
5843 break;
5844 default:
5845 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5846 break;
5847 }
5848 #endif
5849 }
5850
5851 /* tlbsx - tlbsx. */
5852 static void gen_tlbsx_440(DisasContext *ctx)
5853 {
5854 #if defined(CONFIG_USER_ONLY)
5855 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5856 #else
5857 TCGv t0;
5858 if (unlikely(!ctx->mem_idx)) {
5859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5860 return;
5861 }
5862 t0 = tcg_temp_new();
5863 gen_addr_reg_index(ctx, t0);
5864 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5865 tcg_temp_free(t0);
5866 if (Rc(ctx->opcode)) {
5867 int l1 = gen_new_label();
5868 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5869 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5870 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5871 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5872 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5873 gen_set_label(l1);
5874 }
5875 #endif
5876 }
5877
5878 /* tlbwe */
5879 static void gen_tlbwe_440(DisasContext *ctx)
5880 {
5881 #if defined(CONFIG_USER_ONLY)
5882 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5883 #else
5884 if (unlikely(!ctx->mem_idx)) {
5885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5886 return;
5887 }
5888 switch (rB(ctx->opcode)) {
5889 case 0:
5890 case 1:
5891 case 2:
5892 {
5893 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5894 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5895 tcg_temp_free_i32(t0);
5896 }
5897 break;
5898 default:
5899 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5900 break;
5901 }
5902 #endif
5903 }
5904
5905 /* wrtee */
5906 static void gen_wrtee(DisasContext *ctx)
5907 {
5908 #if defined(CONFIG_USER_ONLY)
5909 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5910 #else
5911 TCGv t0;
5912 if (unlikely(!ctx->mem_idx)) {
5913 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5914 return;
5915 }
5916 t0 = tcg_temp_new();
5917 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5918 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5919 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5920 tcg_temp_free(t0);
5921 /* Stop translation to have a chance to raise an exception
5922 * if we just set msr_ee to 1
5923 */
5924 gen_stop_exception(ctx);
5925 #endif
5926 }
5927
5928 /* wrteei */
5929 static void gen_wrteei(DisasContext *ctx)
5930 {
5931 #if defined(CONFIG_USER_ONLY)
5932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5933 #else
5934 if (unlikely(!ctx->mem_idx)) {
5935 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5936 return;
5937 }
5938 if (ctx->opcode & 0x00008000) {
5939 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5940 /* Stop translation to have a chance to raise an exception */
5941 gen_stop_exception(ctx);
5942 } else {
5943 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5944 }
5945 #endif
5946 }
5947
5948 /* PowerPC 440 specific instructions */
5949
5950 /* dlmzb */
5951 static void gen_dlmzb(DisasContext *ctx)
5952 {
5953 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
5954 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
5955 cpu_gpr[rB(ctx->opcode)], t0);
5956 tcg_temp_free_i32(t0);
5957 }
5958
5959 /* mbar replaces eieio on 440 */
5960 static void gen_mbar(DisasContext *ctx)
5961 {
5962 /* interpreted as no-op */
5963 }
5964
5965 /* msync replaces sync on 440 */
5966 static void gen_msync(DisasContext *ctx)
5967 {
5968 /* interpreted as no-op */
5969 }
5970
5971 /* icbt */
5972 static void gen_icbt_440(DisasContext *ctx)
5973 {
5974 /* interpreted as no-op */
5975 /* XXX: specification say this is treated as a load by the MMU
5976 * but does not generate any exception
5977 */
5978 }
5979
5980 /*** Altivec vector extension ***/
5981 /* Altivec registers moves */
5982
5983 static always_inline TCGv_ptr gen_avr_ptr(int reg)
5984 {
5985 TCGv_ptr r = tcg_temp_new_ptr();
5986 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
5987 return r;
5988 }
5989
5990 #define GEN_VR_LDX(name, opc2, opc3) \
5991 static void glue(gen_, name)(DisasContext *ctx) \
5992 { \
5993 TCGv EA; \
5994 if (unlikely(!ctx->altivec_enabled)) { \
5995 gen_exception(ctx, POWERPC_EXCP_VPU); \
5996 return; \
5997 } \
5998 gen_set_access_type(ctx, ACCESS_INT); \
5999 EA = tcg_temp_new(); \
6000 gen_addr_reg_index(ctx, EA); \
6001 tcg_gen_andi_tl(EA, EA, ~0xf); \
6002 if (ctx->le_mode) { \
6003 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6004 tcg_gen_addi_tl(EA, EA, 8); \
6005 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6006 } else { \
6007 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6008 tcg_gen_addi_tl(EA, EA, 8); \
6009 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6010 } \
6011 tcg_temp_free(EA); \
6012 }
6013
6014 #define GEN_VR_STX(name, opc2, opc3) \
6015 static void gen_st##name(DisasContext *ctx) \
6016 { \
6017 TCGv EA; \
6018 if (unlikely(!ctx->altivec_enabled)) { \
6019 gen_exception(ctx, POWERPC_EXCP_VPU); \
6020 return; \
6021 } \
6022 gen_set_access_type(ctx, ACCESS_INT); \
6023 EA = tcg_temp_new(); \
6024 gen_addr_reg_index(ctx, EA); \
6025 tcg_gen_andi_tl(EA, EA, ~0xf); \
6026 if (ctx->le_mode) { \
6027 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6028 tcg_gen_addi_tl(EA, EA, 8); \
6029 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6030 } else { \
6031 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6032 tcg_gen_addi_tl(EA, EA, 8); \
6033 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6034 } \
6035 tcg_temp_free(EA); \
6036 }
6037
6038 #define GEN_VR_LVE(name, opc2, opc3) \
6039 static void gen_lve##name(DisasContext *ctx) \
6040 { \
6041 TCGv EA; \
6042 TCGv_ptr rs; \
6043 if (unlikely(!ctx->altivec_enabled)) { \
6044 gen_exception(ctx, POWERPC_EXCP_VPU); \
6045 return; \
6046 } \
6047 gen_set_access_type(ctx, ACCESS_INT); \
6048 EA = tcg_temp_new(); \
6049 gen_addr_reg_index(ctx, EA); \
6050 rs = gen_avr_ptr(rS(ctx->opcode)); \
6051 gen_helper_lve##name (rs, EA); \
6052 tcg_temp_free(EA); \
6053 tcg_temp_free_ptr(rs); \
6054 }
6055
6056 #define GEN_VR_STVE(name, opc2, opc3) \
6057 static void gen_stve##name(DisasContext *ctx) \
6058 { \
6059 TCGv EA; \
6060 TCGv_ptr rs; \
6061 if (unlikely(!ctx->altivec_enabled)) { \
6062 gen_exception(ctx, POWERPC_EXCP_VPU); \
6063 return; \
6064 } \
6065 gen_set_access_type(ctx, ACCESS_INT); \
6066 EA = tcg_temp_new(); \
6067 gen_addr_reg_index(ctx, EA); \
6068 rs = gen_avr_ptr(rS(ctx->opcode)); \
6069 gen_helper_stve##name (rs, EA); \
6070 tcg_temp_free(EA); \
6071 tcg_temp_free_ptr(rs); \
6072 }
6073
6074 GEN_VR_LDX(lvx, 0x07, 0x03);
6075 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6076 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6077
6078 GEN_VR_LVE(bx, 0x07, 0x00);
6079 GEN_VR_LVE(hx, 0x07, 0x01);
6080 GEN_VR_LVE(wx, 0x07, 0x02);
6081
6082 GEN_VR_STX(svx, 0x07, 0x07);
6083 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6084 GEN_VR_STX(svxl, 0x07, 0x0F);
6085
6086 GEN_VR_STVE(bx, 0x07, 0x04);
6087 GEN_VR_STVE(hx, 0x07, 0x05);
6088 GEN_VR_STVE(wx, 0x07, 0x06);
6089
6090 static void gen_lvsl(DisasContext *ctx)
6091 {
6092 TCGv_ptr rd;
6093 TCGv EA;
6094 if (unlikely(!ctx->altivec_enabled)) {
6095 gen_exception(ctx, POWERPC_EXCP_VPU);
6096 return;
6097 }
6098 EA = tcg_temp_new();
6099 gen_addr_reg_index(ctx, EA);
6100 rd = gen_avr_ptr(rD(ctx->opcode));
6101 gen_helper_lvsl(rd, EA);
6102 tcg_temp_free(EA);
6103 tcg_temp_free_ptr(rd);
6104 }
6105
6106 static void gen_lvsr(DisasContext *ctx)
6107 {
6108 TCGv_ptr rd;
6109 TCGv EA;
6110 if (unlikely(!ctx->altivec_enabled)) {
6111 gen_exception(ctx, POWERPC_EXCP_VPU);
6112 return;
6113 }
6114 EA = tcg_temp_new();
6115 gen_addr_reg_index(ctx, EA);
6116 rd = gen_avr_ptr(rD(ctx->opcode));
6117 gen_helper_lvsr(rd, EA);
6118 tcg_temp_free(EA);
6119 tcg_temp_free_ptr(rd);
6120 }
6121
6122 static void gen_mfvscr(DisasContext *ctx)
6123 {
6124 TCGv_i32 t;
6125 if (unlikely(!ctx->altivec_enabled)) {
6126 gen_exception(ctx, POWERPC_EXCP_VPU);
6127 return;
6128 }
6129 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6130 t = tcg_temp_new_i32();
6131 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6132 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6133 tcg_temp_free_i32(t);
6134 }
6135
6136 static void gen_mtvscr(DisasContext *ctx)
6137 {
6138 TCGv_ptr p;
6139 if (unlikely(!ctx->altivec_enabled)) {
6140 gen_exception(ctx, POWERPC_EXCP_VPU);
6141 return;
6142 }
6143 p = gen_avr_ptr(rD(ctx->opcode));
6144 gen_helper_mtvscr(p);
6145 tcg_temp_free_ptr(p);
6146 }
6147
6148 /* Logical operations */
6149 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6150 static void glue(gen_, name)(DisasContext *ctx) \
6151 { \
6152 if (unlikely(!ctx->altivec_enabled)) { \
6153 gen_exception(ctx, POWERPC_EXCP_VPU); \
6154 return; \
6155 } \
6156 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6157 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6158 }
6159
6160 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6161 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6162 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6163 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6164 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6165
6166 #define GEN_VXFORM(name, opc2, opc3) \
6167 static void glue(gen_, name)(DisasContext *ctx) \
6168 { \
6169 TCGv_ptr ra, rb, rd; \
6170 if (unlikely(!ctx->altivec_enabled)) { \
6171 gen_exception(ctx, POWERPC_EXCP_VPU); \
6172 return; \
6173 } \
6174 ra = gen_avr_ptr(rA(ctx->opcode)); \
6175 rb = gen_avr_ptr(rB(ctx->opcode)); \
6176 rd = gen_avr_ptr(rD(ctx->opcode)); \
6177 gen_helper_##name (rd, ra, rb); \
6178 tcg_temp_free_ptr(ra); \
6179 tcg_temp_free_ptr(rb); \
6180 tcg_temp_free_ptr(rd); \
6181 }
6182
6183 GEN_VXFORM(vaddubm, 0, 0);
6184 GEN_VXFORM(vadduhm, 0, 1);
6185 GEN_VXFORM(vadduwm, 0, 2);
6186 GEN_VXFORM(vsububm, 0, 16);
6187 GEN_VXFORM(vsubuhm, 0, 17);
6188 GEN_VXFORM(vsubuwm, 0, 18);
6189 GEN_VXFORM(vmaxub, 1, 0);
6190 GEN_VXFORM(vmaxuh, 1, 1);
6191 GEN_VXFORM(vmaxuw, 1, 2);
6192 GEN_VXFORM(vmaxsb, 1, 4);
6193 GEN_VXFORM(vmaxsh, 1, 5);
6194 GEN_VXFORM(vmaxsw, 1, 6);
6195 GEN_VXFORM(vminub, 1, 8);
6196 GEN_VXFORM(vminuh, 1, 9);
6197 GEN_VXFORM(vminuw, 1, 10);
6198 GEN_VXFORM(vminsb, 1, 12);
6199 GEN_VXFORM(vminsh, 1, 13);
6200 GEN_VXFORM(vminsw, 1, 14);
6201 GEN_VXFORM(vavgub, 1, 16);
6202 GEN_VXFORM(vavguh, 1, 17);
6203 GEN_VXFORM(vavguw, 1, 18);
6204 GEN_VXFORM(vavgsb, 1, 20);
6205 GEN_VXFORM(vavgsh, 1, 21);
6206 GEN_VXFORM(vavgsw, 1, 22);
6207 GEN_VXFORM(vmrghb, 6, 0);
6208 GEN_VXFORM(vmrghh, 6, 1);
6209 GEN_VXFORM(vmrghw, 6, 2);
6210 GEN_VXFORM(vmrglb, 6, 4);
6211 GEN_VXFORM(vmrglh, 6, 5);
6212 GEN_VXFORM(vmrglw, 6, 6);
6213 GEN_VXFORM(vmuloub, 4, 0);
6214 GEN_VXFORM(vmulouh, 4, 1);
6215 GEN_VXFORM(vmulosb, 4, 4);
6216 GEN_VXFORM(vmulosh, 4, 5);
6217 GEN_VXFORM(vmuleub, 4, 8);
6218 GEN_VXFORM(vmuleuh, 4, 9);
6219 GEN_VXFORM(vmulesb, 4, 12);
6220 GEN_VXFORM(vmulesh, 4, 13);
6221 GEN_VXFORM(vslb, 2, 4);
6222 GEN_VXFORM(vslh, 2, 5);
6223 GEN_VXFORM(vslw, 2, 6);
6224 GEN_VXFORM(vsrb, 2, 8);
6225 GEN_VXFORM(vsrh, 2, 9);
6226 GEN_VXFORM(vsrw, 2, 10);
6227 GEN_VXFORM(vsrab, 2, 12);
6228 GEN_VXFORM(vsrah, 2, 13);
6229 GEN_VXFORM(vsraw, 2, 14);
6230 GEN_VXFORM(vslo, 6, 16);
6231 GEN_VXFORM(vsro, 6, 17);
6232 GEN_VXFORM(vaddcuw, 0, 6);
6233 GEN_VXFORM(vsubcuw, 0, 22);
6234 GEN_VXFORM(vaddubs, 0, 8);
6235 GEN_VXFORM(vadduhs, 0, 9);
6236 GEN_VXFORM(vadduws, 0, 10);
6237 GEN_VXFORM(vaddsbs, 0, 12);
6238 GEN_VXFORM(vaddshs, 0, 13);
6239 GEN_VXFORM(vaddsws, 0, 14);
6240 GEN_VXFORM(vsububs, 0, 24);
6241 GEN_VXFORM(vsubuhs, 0, 25);
6242 GEN_VXFORM(vsubuws, 0, 26);
6243 GEN_VXFORM(vsubsbs, 0, 28);
6244 GEN_VXFORM(vsubshs, 0, 29);
6245 GEN_VXFORM(vsubsws, 0, 30);
6246 GEN_VXFORM(vrlb, 2, 0);
6247 GEN_VXFORM(vrlh, 2, 1);
6248 GEN_VXFORM(vrlw, 2, 2);
6249 GEN_VXFORM(vsl, 2, 7);
6250 GEN_VXFORM(vsr, 2, 11);
6251 GEN_VXFORM(vpkuhum, 7, 0);
6252 GEN_VXFORM(vpkuwum, 7, 1);
6253 GEN_VXFORM(vpkuhus, 7, 2);
6254 GEN_VXFORM(vpkuwus, 7, 3);
6255 GEN_VXFORM(vpkshus, 7, 4);
6256 GEN_VXFORM(vpkswus, 7, 5);
6257 GEN_VXFORM(vpkshss, 7, 6);
6258 GEN_VXFORM(vpkswss, 7, 7);
6259 GEN_VXFORM(vpkpx, 7, 12);
6260 GEN_VXFORM(vsum4ubs, 4, 24);
6261 GEN_VXFORM(vsum4sbs, 4, 28);
6262 GEN_VXFORM(vsum4shs, 4, 25);
6263 GEN_VXFORM(vsum2sws, 4, 26);
6264 GEN_VXFORM(vsumsws, 4, 30);
6265 GEN_VXFORM(vaddfp, 5, 0);
6266 GEN_VXFORM(vsubfp, 5, 1);
6267 GEN_VXFORM(vmaxfp, 5, 16);
6268 GEN_VXFORM(vminfp, 5, 17);
6269
6270 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6271 static void glue(gen_, name)(DisasContext *ctx) \
6272 { \
6273 TCGv_ptr ra, rb, rd; \
6274 if (unlikely(!ctx->altivec_enabled)) { \
6275 gen_exception(ctx, POWERPC_EXCP_VPU); \
6276 return; \
6277 } \
6278 ra = gen_avr_ptr(rA(ctx->opcode)); \
6279 rb = gen_avr_ptr(rB(ctx->opcode)); \
6280 rd = gen_avr_ptr(rD(ctx->opcode)); \
6281 gen_helper_##opname (rd, ra, rb); \
6282 tcg_temp_free_ptr(ra); \
6283 tcg_temp_free_ptr(rb); \
6284 tcg_temp_free_ptr(rd); \
6285 }
6286
6287 #define GEN_VXRFORM(name, opc2, opc3) \
6288 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6289 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6290
6291 GEN_VXRFORM(vcmpequb, 3, 0)
6292 GEN_VXRFORM(vcmpequh, 3, 1)
6293 GEN_VXRFORM(vcmpequw, 3, 2)
6294 GEN_VXRFORM(vcmpgtsb, 3, 12)
6295 GEN_VXRFORM(vcmpgtsh, 3, 13)
6296 GEN_VXRFORM(vcmpgtsw, 3, 14)
6297 GEN_VXRFORM(vcmpgtub, 3, 8)
6298 GEN_VXRFORM(vcmpgtuh, 3, 9)
6299 GEN_VXRFORM(vcmpgtuw, 3, 10)
6300 GEN_VXRFORM(vcmpeqfp, 3, 3)
6301 GEN_VXRFORM(vcmpgefp, 3, 7)
6302 GEN_VXRFORM(vcmpgtfp, 3, 11)
6303 GEN_VXRFORM(vcmpbfp, 3, 15)
6304
6305 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6306 static void glue(gen_, name)(DisasContext *ctx) \
6307 { \
6308 TCGv_ptr rd; \
6309 TCGv_i32 simm; \
6310 if (unlikely(!ctx->altivec_enabled)) { \
6311 gen_exception(ctx, POWERPC_EXCP_VPU); \
6312 return; \
6313 } \
6314 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6315 rd = gen_avr_ptr(rD(ctx->opcode)); \
6316 gen_helper_##name (rd, simm); \
6317 tcg_temp_free_i32(simm); \
6318 tcg_temp_free_ptr(rd); \
6319 }
6320
6321 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6322 GEN_VXFORM_SIMM(vspltish, 6, 13);
6323 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6324
6325 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6326 static void glue(gen_, name)(DisasContext *ctx) \
6327 { \
6328 TCGv_ptr rb, rd; \
6329 if (unlikely(!ctx->altivec_enabled)) { \
6330 gen_exception(ctx, POWERPC_EXCP_VPU); \
6331 return; \
6332 } \
6333 rb = gen_avr_ptr(rB(ctx->opcode)); \
6334 rd = gen_avr_ptr(rD(ctx->opcode)); \
6335 gen_helper_##name (rd, rb); \
6336 tcg_temp_free_ptr(rb); \
6337 tcg_temp_free_ptr(rd); \
6338 }
6339
6340 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6341 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6342 GEN_VXFORM_NOA(vupklsb, 7, 10);
6343 GEN_VXFORM_NOA(vupklsh, 7, 11);
6344 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6345 GEN_VXFORM_NOA(vupklpx, 7, 15);
6346 GEN_VXFORM_NOA(vrefp, 5, 4);
6347 GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
6348 GEN_VXFORM_NOA(vlogefp, 5, 7);
6349 GEN_VXFORM_NOA(vrfim, 5, 8);
6350 GEN_VXFORM_NOA(vrfin, 5, 9);
6351 GEN_VXFORM_NOA(vrfip, 5, 10);
6352 GEN_VXFORM_NOA(vrfiz, 5, 11);
6353
6354 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6355 static void glue(gen_, name)(DisasContext *ctx) \
6356 { \
6357 TCGv_ptr rd; \
6358 TCGv_i32 simm; \
6359 if (unlikely(!ctx->altivec_enabled)) { \
6360 gen_exception(ctx, POWERPC_EXCP_VPU); \
6361 return; \
6362 } \
6363 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6364 rd = gen_avr_ptr(rD(ctx->opcode)); \
6365 gen_helper_##name (rd, simm); \
6366 tcg_temp_free_i32(simm); \
6367 tcg_temp_free_ptr(rd); \
6368 }
6369
6370 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6371 static void glue(gen_, name)(DisasContext *ctx) \
6372 { \
6373 TCGv_ptr rb, rd; \
6374 TCGv_i32 uimm; \
6375 if (unlikely(!ctx->altivec_enabled)) { \
6376 gen_exception(ctx, POWERPC_EXCP_VPU); \
6377 return; \
6378 } \
6379 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6380 rb = gen_avr_ptr(rB(ctx->opcode)); \
6381 rd = gen_avr_ptr(rD(ctx->opcode)); \
6382 gen_helper_##name (rd, rb, uimm); \
6383 tcg_temp_free_i32(uimm); \
6384 tcg_temp_free_ptr(rb); \
6385 tcg_temp_free_ptr(rd); \
6386 }
6387
6388 GEN_VXFORM_UIMM(vspltb, 6, 8);
6389 GEN_VXFORM_UIMM(vsplth, 6, 9);
6390 GEN_VXFORM_UIMM(vspltw, 6, 10);
6391 GEN_VXFORM_UIMM(vcfux, 5, 12);
6392 GEN_VXFORM_UIMM(vcfsx, 5, 13);
6393 GEN_VXFORM_UIMM(vctuxs, 5, 14);
6394 GEN_VXFORM_UIMM(vctsxs, 5, 15);
6395
6396 static void gen_vsldoi(DisasContext *ctx)
6397 {
6398 TCGv_ptr ra, rb, rd;
6399 TCGv_i32 sh;
6400 if (unlikely(!ctx->altivec_enabled)) {
6401 gen_exception(ctx, POWERPC_EXCP_VPU);
6402 return;
6403 }
6404 ra = gen_avr_ptr(rA(ctx->opcode));
6405 rb = gen_avr_ptr(rB(ctx->opcode));
6406 rd = gen_avr_ptr(rD(ctx->opcode));
6407 sh = tcg_const_i32(VSH(ctx->opcode));
6408 gen_helper_vsldoi (rd, ra, rb, sh);
6409 tcg_temp_free_ptr(ra);
6410 tcg_temp_free_ptr(rb);
6411 tcg_temp_free_ptr(rd);
6412 tcg_temp_free_i32(sh);
6413 }
6414
6415 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6416 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6417 { \
6418 TCGv_ptr ra, rb, rc, rd; \
6419 if (unlikely(!ctx->altivec_enabled)) { \
6420 gen_exception(ctx, POWERPC_EXCP_VPU); \
6421 return; \
6422 } \
6423 ra = gen_avr_ptr(rA(ctx->opcode)); \
6424 rb = gen_avr_ptr(rB(ctx->opcode)); \
6425 rc = gen_avr_ptr(rC(ctx->opcode)); \
6426 rd = gen_avr_ptr(rD(ctx->opcode)); \
6427 if (Rc(ctx->opcode)) { \
6428 gen_helper_##name1 (rd, ra, rb, rc); \
6429 } else { \
6430 gen_helper_##name0 (rd, ra, rb, rc); \
6431 } \
6432 tcg_temp_free_ptr(ra); \
6433 tcg_temp_free_ptr(rb); \
6434 tcg_temp_free_ptr(rc); \
6435 tcg_temp_free_ptr(rd); \
6436 }
6437
6438 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6439
6440 static void gen_vmladduhm(DisasContext *ctx)
6441 {
6442 TCGv_ptr ra, rb, rc, rd;
6443 if (unlikely(!ctx->altivec_enabled)) {
6444 gen_exception(ctx, POWERPC_EXCP_VPU);
6445 return;
6446 }
6447 ra = gen_avr_ptr(rA(ctx->opcode));
6448 rb = gen_avr_ptr(rB(ctx->opcode));
6449 rc = gen_avr_ptr(rC(ctx->opcode));
6450 rd = gen_avr_ptr(rD(ctx->opcode));
6451 gen_helper_vmladduhm(rd, ra, rb, rc);
6452 tcg_temp_free_ptr(ra);
6453 tcg_temp_free_ptr(rb);
6454 tcg_temp_free_ptr(rc);
6455 tcg_temp_free_ptr(rd);
6456 }
6457
6458 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6459 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6460 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6461 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6462 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6463
6464 /*** SPE extension ***/
6465 /* Register moves */
6466
6467 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
6468 #if defined(TARGET_PPC64)
6469 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6470 #else
6471 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6472 #endif
6473 }
6474
6475 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
6476 #if defined(TARGET_PPC64)
6477 tcg_gen_mov_i64(cpu_gpr[reg], t);
6478 #else
6479 TCGv_i64 tmp = tcg_temp_new_i64();
6480 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6481 tcg_gen_shri_i64(tmp, t, 32);
6482 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6483 tcg_temp_free_i64(tmp);
6484 #endif
6485 }
6486
6487 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6488 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6489 { \
6490 if (Rc(ctx->opcode)) \
6491 gen_##name1(ctx); \
6492 else \
6493 gen_##name0(ctx); \
6494 }
6495
6496 /* Handler for undefined SPE opcodes */
6497 static always_inline void gen_speundef (DisasContext *ctx)
6498 {
6499 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6500 }
6501
6502 /* SPE logic */
6503 #if defined(TARGET_PPC64)
6504 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6505 static always_inline void gen_##name (DisasContext *ctx) \
6506 { \
6507 if (unlikely(!ctx->spe_enabled)) { \
6508 gen_exception(ctx, POWERPC_EXCP_APU); \
6509 return; \
6510 } \
6511 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6512 cpu_gpr[rB(ctx->opcode)]); \
6513 }
6514 #else
6515 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6516 static always_inline void gen_##name (DisasContext *ctx) \
6517 { \
6518 if (unlikely(!ctx->spe_enabled)) { \
6519 gen_exception(ctx, POWERPC_EXCP_APU); \
6520 return; \
6521 } \
6522 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6523 cpu_gpr[rB(ctx->opcode)]); \
6524 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6525 cpu_gprh[rB(ctx->opcode)]); \
6526 }
6527 #endif
6528
6529 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6530 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6531 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6532 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6533 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6534 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6535 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6536 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6537
6538 /* SPE logic immediate */
6539 #if defined(TARGET_PPC64)
6540 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6541 static always_inline void gen_##name (DisasContext *ctx) \
6542 { \
6543 if (unlikely(!ctx->spe_enabled)) { \
6544 gen_exception(ctx, POWERPC_EXCP_APU); \
6545 return; \
6546 } \
6547 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6548 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6549 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6550 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6551 tcg_opi(t0, t0, rB(ctx->opcode)); \
6552 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6553 tcg_gen_trunc_i64_i32(t1, t2); \
6554 tcg_temp_free_i64(t2); \
6555 tcg_opi(t1, t1, rB(ctx->opcode)); \
6556 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6557 tcg_temp_free_i32(t0); \
6558 tcg_temp_free_i32(t1); \
6559 }
6560 #else
6561 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6562 static always_inline void gen_##name (DisasContext *ctx) \
6563 { \
6564 if (unlikely(!ctx->spe_enabled)) { \
6565 gen_exception(ctx, POWERPC_EXCP_APU); \
6566 return; \
6567 } \
6568 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6569 rB(ctx->opcode)); \
6570 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6571 rB(ctx->opcode)); \
6572 }
6573 #endif
6574 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6575 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6576 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6577 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6578
6579 /* SPE arithmetic */
6580 #if defined(TARGET_PPC64)
6581 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6582 static always_inline void gen_##name (DisasContext *ctx) \
6583 { \
6584 if (unlikely(!ctx->spe_enabled)) { \
6585 gen_exception(ctx, POWERPC_EXCP_APU); \
6586 return; \
6587 } \
6588 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6589 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6590 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6591 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6592 tcg_op(t0, t0); \
6593 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6594 tcg_gen_trunc_i64_i32(t1, t2); \
6595 tcg_temp_free_i64(t2); \
6596 tcg_op(t1, t1); \
6597 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6598 tcg_temp_free_i32(t0); \
6599 tcg_temp_free_i32(t1); \
6600 }
6601 #else
6602 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6603 static always_inline void gen_##name (DisasContext *ctx) \
6604 { \
6605 if (unlikely(!ctx->spe_enabled)) { \
6606 gen_exception(ctx, POWERPC_EXCP_APU); \
6607 return; \
6608 } \
6609 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6610 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6611 }
6612 #endif
6613
6614 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6615 {
6616 int l1 = gen_new_label();
6617 int l2 = gen_new_label();
6618
6619 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6620 tcg_gen_neg_i32(ret, arg1);
6621 tcg_gen_br(l2);
6622 gen_set_label(l1);
6623 tcg_gen_mov_i32(ret, arg1);
6624 gen_set_label(l2);
6625 }
6626 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6627 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6628 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6629 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6630 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6631 {
6632 tcg_gen_addi_i32(ret, arg1, 0x8000);
6633 tcg_gen_ext16u_i32(ret, ret);
6634 }
6635 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6636 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6637 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6638
6639 #if defined(TARGET_PPC64)
6640 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6641 static always_inline void gen_##name (DisasContext *ctx) \
6642 { \
6643 if (unlikely(!ctx->spe_enabled)) { \
6644 gen_exception(ctx, POWERPC_EXCP_APU); \
6645 return; \
6646 } \
6647 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6648 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6649 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6650 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6651 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6652 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6653 tcg_op(t0, t0, t2); \
6654 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6655 tcg_gen_trunc_i64_i32(t1, t3); \
6656 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6657 tcg_gen_trunc_i64_i32(t2, t3); \
6658 tcg_temp_free_i64(t3); \
6659 tcg_op(t1, t1, t2); \
6660 tcg_temp_free_i32(t2); \
6661 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6662 tcg_temp_free_i32(t0); \
6663 tcg_temp_free_i32(t1); \
6664 }
6665 #else
6666 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6667 static always_inline void gen_##name (DisasContext *ctx) \
6668 { \
6669 if (unlikely(!ctx->spe_enabled)) { \
6670 gen_exception(ctx, POWERPC_EXCP_APU); \
6671 return; \
6672 } \
6673 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6674 cpu_gpr[rB(ctx->opcode)]); \
6675 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6676 cpu_gprh[rB(ctx->opcode)]); \
6677 }
6678 #endif
6679
6680 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6681 {
6682 TCGv_i32 t0;
6683 int l1, l2;
6684
6685 l1 = gen_new_label();
6686 l2 = gen_new_label();
6687 t0 = tcg_temp_local_new_i32();
6688 /* No error here: 6 bits are used */
6689 tcg_gen_andi_i32(t0, arg2, 0x3F);
6690 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6691 tcg_gen_shr_i32(ret, arg1, t0);
6692 tcg_gen_br(l2);
6693 gen_set_label(l1);
6694 tcg_gen_movi_i32(ret, 0);
6695 tcg_gen_br(l2);
6696 tcg_temp_free_i32(t0);
6697 }
6698 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6699 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6700 {
6701 TCGv_i32 t0;
6702 int l1, l2;
6703
6704 l1 = gen_new_label();
6705 l2 = gen_new_label();
6706 t0 = tcg_temp_local_new_i32();
6707 /* No error here: 6 bits are used */
6708 tcg_gen_andi_i32(t0, arg2, 0x3F);
6709 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6710 tcg_gen_sar_i32(ret, arg1, t0);
6711 tcg_gen_br(l2);
6712 gen_set_label(l1);
6713 tcg_gen_movi_i32(ret, 0);
6714 tcg_gen_br(l2);
6715 tcg_temp_free_i32(t0);
6716 }
6717 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6718 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6719 {
6720 TCGv_i32 t0;
6721 int l1, l2;
6722
6723 l1 = gen_new_label();
6724 l2 = gen_new_label();
6725 t0 = tcg_temp_local_new_i32();
6726 /* No error here: 6 bits are used */
6727 tcg_gen_andi_i32(t0, arg2, 0x3F);
6728 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6729 tcg_gen_shl_i32(ret, arg1, t0);
6730 tcg_gen_br(l2);
6731 gen_set_label(l1);
6732 tcg_gen_movi_i32(ret, 0);
6733 tcg_gen_br(l2);
6734 tcg_temp_free_i32(t0);
6735 }
6736 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6737 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6738 {
6739 TCGv_i32 t0 = tcg_temp_new_i32();
6740 tcg_gen_andi_i32(t0, arg2, 0x1F);
6741 tcg_gen_rotl_i32(ret, arg1, t0);
6742 tcg_temp_free_i32(t0);
6743 }
6744 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6745 static always_inline void gen_evmergehi (DisasContext *ctx)
6746 {
6747 if (unlikely(!ctx->spe_enabled)) {
6748 gen_exception(ctx, POWERPC_EXCP_APU);
6749 return;
6750 }
6751 #if defined(TARGET_PPC64)
6752 TCGv t0 = tcg_temp_new();
6753 TCGv t1 = tcg_temp_new();
6754 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6755 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6756 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6757 tcg_temp_free(t0);
6758 tcg_temp_free(t1);
6759 #else
6760 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6761 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6762 #endif
6763 }
6764 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6765 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6766 {
6767 tcg_gen_sub_i32(ret, arg2, arg1);
6768 }
6769 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6770
6771 /* SPE arithmetic immediate */
6772 #if defined(TARGET_PPC64)
6773 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6774 static always_inline void gen_##name (DisasContext *ctx) \
6775 { \
6776 if (unlikely(!ctx->spe_enabled)) { \
6777 gen_exception(ctx, POWERPC_EXCP_APU); \
6778 return; \
6779 } \
6780 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6781 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6782 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6783 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6784 tcg_op(t0, t0, rA(ctx->opcode)); \
6785 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6786 tcg_gen_trunc_i64_i32(t1, t2); \
6787 tcg_temp_free_i64(t2); \
6788 tcg_op(t1, t1, rA(ctx->opcode)); \
6789 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6790 tcg_temp_free_i32(t0); \
6791 tcg_temp_free_i32(t1); \
6792 }
6793 #else
6794 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6795 static always_inline void gen_##name (DisasContext *ctx) \
6796 { \
6797 if (unlikely(!ctx->spe_enabled)) { \
6798 gen_exception(ctx, POWERPC_EXCP_APU); \
6799 return; \
6800 } \
6801 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6802 rA(ctx->opcode)); \
6803 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6804 rA(ctx->opcode)); \
6805 }
6806 #endif
6807 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6808 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6809
6810 /* SPE comparison */
6811 #if defined(TARGET_PPC64)
6812 #define GEN_SPEOP_COMP(name, tcg_cond) \
6813 static always_inline void gen_##name (DisasContext *ctx) \
6814 { \
6815 if (unlikely(!ctx->spe_enabled)) { \
6816 gen_exception(ctx, POWERPC_EXCP_APU); \
6817 return; \
6818 } \
6819 int l1 = gen_new_label(); \
6820 int l2 = gen_new_label(); \
6821 int l3 = gen_new_label(); \
6822 int l4 = gen_new_label(); \
6823 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6824 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6825 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6826 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6827 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6828 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6829 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6830 tcg_gen_br(l2); \
6831 gen_set_label(l1); \
6832 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6833 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6834 gen_set_label(l2); \
6835 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6836 tcg_gen_trunc_i64_i32(t0, t2); \
6837 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6838 tcg_gen_trunc_i64_i32(t1, t2); \
6839 tcg_temp_free_i64(t2); \
6840 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6841 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6842 ~(CRF_CH | CRF_CH_AND_CL)); \
6843 tcg_gen_br(l4); \
6844 gen_set_label(l3); \
6845 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6846 CRF_CH | CRF_CH_OR_CL); \
6847 gen_set_label(l4); \
6848 tcg_temp_free_i32(t0); \
6849 tcg_temp_free_i32(t1); \
6850 }
6851 #else
6852 #define GEN_SPEOP_COMP(name, tcg_cond) \
6853 static always_inline void gen_##name (DisasContext *ctx) \
6854 { \
6855 if (unlikely(!ctx->spe_enabled)) { \
6856 gen_exception(ctx, POWERPC_EXCP_APU); \
6857 return; \
6858 } \
6859 int l1 = gen_new_label(); \
6860 int l2 = gen_new_label(); \
6861 int l3 = gen_new_label(); \
6862 int l4 = gen_new_label(); \
6863 \
6864 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6865 cpu_gpr[rB(ctx->opcode)], l1); \
6866 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6867 tcg_gen_br(l2); \
6868 gen_set_label(l1); \
6869 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6870 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6871 gen_set_label(l2); \
6872 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6873 cpu_gprh[rB(ctx->opcode)], l3); \
6874 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6875 ~(CRF_CH | CRF_CH_AND_CL)); \
6876 tcg_gen_br(l4); \
6877 gen_set_label(l3); \
6878 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6879 CRF_CH | CRF_CH_OR_CL); \
6880 gen_set_label(l4); \
6881 }
6882 #endif
6883 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6884 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6885 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6886 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6887 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6888
6889 /* SPE misc */
6890 static always_inline void gen_brinc (DisasContext *ctx)
6891 {
6892 /* Note: brinc is usable even if SPE is disabled */
6893 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6894 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6895 }
6896 static always_inline void gen_evmergelo (DisasContext *ctx)
6897 {
6898 if (unlikely(!ctx->spe_enabled)) {
6899 gen_exception(ctx, POWERPC_EXCP_APU);
6900 return;
6901 }
6902 #if defined(TARGET_PPC64)
6903 TCGv t0 = tcg_temp_new();
6904 TCGv t1 = tcg_temp_new();
6905 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6906 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6907 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6908 tcg_temp_free(t0);
6909 tcg_temp_free(t1);
6910 #else
6911 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6912 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6913 #endif
6914 }
6915 static always_inline void gen_evmergehilo (DisasContext *ctx)
6916 {
6917 if (unlikely(!ctx->spe_enabled)) {
6918 gen_exception(ctx, POWERPC_EXCP_APU);
6919 return;
6920 }
6921 #if defined(TARGET_PPC64)
6922 TCGv t0 = tcg_temp_new();
6923 TCGv t1 = tcg_temp_new();
6924 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6925 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6926 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6927 tcg_temp_free(t0);
6928 tcg_temp_free(t1);
6929 #else
6930 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6931 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6932 #endif
6933 }
6934 static always_inline void gen_evmergelohi (DisasContext *ctx)
6935 {
6936 if (unlikely(!ctx->spe_enabled)) {
6937 gen_exception(ctx, POWERPC_EXCP_APU);
6938 return;
6939 }
6940 #if defined(TARGET_PPC64)
6941 TCGv t0 = tcg_temp_new();
6942 TCGv t1 = tcg_temp_new();
6943 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6944 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6945 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6946 tcg_temp_free(t0);
6947 tcg_temp_free(t1);
6948 #else
6949 if (rD(ctx->opcode) == rA(ctx->opcode)) {
6950 TCGv_i32 tmp = tcg_temp_new_i32();
6951 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
6952 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6953 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
6954 tcg_temp_free_i32(tmp);
6955 } else {
6956 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6957 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6958 }
6959 #endif
6960 }
6961 static always_inline void gen_evsplati (DisasContext *ctx)
6962 {
6963 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
6964
6965 #if defined(TARGET_PPC64)
6966 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
6967 #else
6968 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6969 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6970 #endif
6971 }
6972 static always_inline void gen_evsplatfi (DisasContext *ctx)
6973 {
6974 uint64_t imm = rA(ctx->opcode) << 11;
6975
6976 #if defined(TARGET_PPC64)
6977 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
6978 #else
6979 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6980 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6981 #endif
6982 }
6983
6984 static always_inline void gen_evsel (DisasContext *ctx)
6985 {
6986 int l1 = gen_new_label();
6987 int l2 = gen_new_label();
6988 int l3 = gen_new_label();
6989 int l4 = gen_new_label();
6990 TCGv_i32 t0 = tcg_temp_local_new_i32();
6991 #if defined(TARGET_PPC64)
6992 TCGv t1 = tcg_temp_local_new();
6993 TCGv t2 = tcg_temp_local_new();
6994 #endif
6995 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6996 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6997 #if defined(TARGET_PPC64)
6998 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6999 #else
7000 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7001 #endif
7002 tcg_gen_br(l2);
7003 gen_set_label(l1);
7004 #if defined(TARGET_PPC64)
7005 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7006 #else
7007 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7008 #endif
7009 gen_set_label(l2);
7010 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7011 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7012 #if defined(TARGET_PPC64)
7013 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7014 #else
7015 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7016 #endif
7017 tcg_gen_br(l4);
7018 gen_set_label(l3);
7019 #if defined(TARGET_PPC64)
7020 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7021 #else
7022 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7023 #endif
7024 gen_set_label(l4);
7025 tcg_temp_free_i32(t0);
7026 #if defined(TARGET_PPC64)
7027 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7028 tcg_temp_free(t1);
7029 tcg_temp_free(t2);
7030 #endif
7031 }
7032
7033 static void gen_evsel0(DisasContext *ctx)
7034 {
7035 gen_evsel(ctx);
7036 }
7037
7038 static void gen_evsel1(DisasContext *ctx)
7039 {
7040 gen_evsel(ctx);
7041 }
7042
7043 static void gen_evsel2(DisasContext *ctx)
7044 {
7045 gen_evsel(ctx);
7046 }
7047
7048 static void gen_evsel3(DisasContext *ctx)
7049 {
7050 gen_evsel(ctx);
7051 }
7052
7053 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7054 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7055 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7056 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7057 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7058 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7059 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7060 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7061 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7062 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7063 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7064 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7065 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7066 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7067 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7068 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7069 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7070 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7071 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7072 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7073 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7074 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7075 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7076 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7077 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7078
7079 /* SPE load and stores */
7080 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
7081 {
7082 target_ulong uimm = rB(ctx->opcode);
7083
7084 if (rA(ctx->opcode) == 0) {
7085 tcg_gen_movi_tl(EA, uimm << sh);
7086 } else {
7087 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7088 #if defined(TARGET_PPC64)
7089 if (!ctx->sf_mode) {
7090 tcg_gen_ext32u_tl(EA, EA);
7091 }
7092 #endif
7093 }
7094 }
7095
7096 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7097 {
7098 #if defined(TARGET_PPC64)
7099 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7100 #else
7101 TCGv_i64 t0 = tcg_temp_new_i64();
7102 gen_qemu_ld64(ctx, t0, addr);
7103 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7104 tcg_gen_shri_i64(t0, t0, 32);
7105 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7106 tcg_temp_free_i64(t0);
7107 #endif
7108 }
7109
7110 static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7111 {
7112 #if defined(TARGET_PPC64)
7113 TCGv t0 = tcg_temp_new();
7114 gen_qemu_ld32u(ctx, t0, addr);
7115 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7116 gen_addr_add(ctx, addr, addr, 4);
7117 gen_qemu_ld32u(ctx, t0, addr);
7118 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7119 tcg_temp_free(t0);
7120 #else
7121 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7122 gen_addr_add(ctx, addr, addr, 4);
7123 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7124 #endif
7125 }
7126
7127 static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7128 {
7129 TCGv t0 = tcg_temp_new();
7130 #if defined(TARGET_PPC64)
7131 gen_qemu_ld16u(ctx, t0, addr);
7132 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7133 gen_addr_add(ctx, addr, addr, 2);
7134 gen_qemu_ld16u(ctx, t0, addr);
7135 tcg_gen_shli_tl(t0, t0, 32);
7136 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7137 gen_addr_add(ctx, addr, addr, 2);
7138 gen_qemu_ld16u(ctx, t0, addr);
7139 tcg_gen_shli_tl(t0, t0, 16);
7140 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7141 gen_addr_add(ctx, addr, addr, 2);
7142 gen_qemu_ld16u(ctx, t0, addr);
7143 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7144 #else
7145 gen_qemu_ld16u(ctx, t0, addr);
7146 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7147 gen_addr_add(ctx, addr, addr, 2);
7148 gen_qemu_ld16u(ctx, t0, addr);
7149 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7150 gen_addr_add(ctx, addr, addr, 2);
7151 gen_qemu_ld16u(ctx, t0, addr);
7152 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7153 gen_addr_add(ctx, addr, addr, 2);
7154 gen_qemu_ld16u(ctx, t0, addr);
7155 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7156 #endif
7157 tcg_temp_free(t0);
7158 }
7159
7160 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7161 {
7162 TCGv t0 = tcg_temp_new();
7163 gen_qemu_ld16u(ctx, t0, addr);
7164 #if defined(TARGET_PPC64)
7165 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7166 tcg_gen_shli_tl(t0, t0, 16);
7167 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7168 #else
7169 tcg_gen_shli_tl(t0, t0, 16);
7170 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7171 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7172 #endif
7173 tcg_temp_free(t0);
7174 }
7175
7176 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7177 {
7178 TCGv t0 = tcg_temp_new();
7179 gen_qemu_ld16u(ctx, t0, addr);
7180 #if defined(TARGET_PPC64)
7181 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7182 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7183 #else
7184 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7185 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7186 #endif
7187 tcg_temp_free(t0);
7188 }
7189
7190 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7191 {
7192 TCGv t0 = tcg_temp_new();
7193 gen_qemu_ld16s(ctx, t0, addr);
7194 #if defined(TARGET_PPC64)
7195 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7196 tcg_gen_ext32u_tl(t0, t0);
7197 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7198 #else
7199 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7200 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7201 #endif
7202 tcg_temp_free(t0);
7203 }
7204
7205 static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7206 {
7207 TCGv t0 = tcg_temp_new();
7208 #if defined(TARGET_PPC64)
7209 gen_qemu_ld16u(ctx, t0, addr);
7210 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7211 gen_addr_add(ctx, addr, addr, 2);
7212 gen_qemu_ld16u(ctx, t0, addr);
7213 tcg_gen_shli_tl(t0, t0, 16);
7214 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7215 #else
7216 gen_qemu_ld16u(ctx, t0, addr);
7217 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7218 gen_addr_add(ctx, addr, addr, 2);
7219 gen_qemu_ld16u(ctx, t0, addr);
7220 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7221 #endif
7222 tcg_temp_free(t0);
7223 }
7224
7225 static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7226 {
7227 #if defined(TARGET_PPC64)
7228 TCGv t0 = tcg_temp_new();
7229 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7230 gen_addr_add(ctx, addr, addr, 2);
7231 gen_qemu_ld16u(ctx, t0, addr);
7232 tcg_gen_shli_tl(t0, t0, 32);
7233 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7234 tcg_temp_free(t0);
7235 #else
7236 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7237 gen_addr_add(ctx, addr, addr, 2);
7238 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7239 #endif
7240 }
7241
7242 static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7243 {
7244 #if defined(TARGET_PPC64)
7245 TCGv t0 = tcg_temp_new();
7246 gen_qemu_ld16s(ctx, t0, addr);
7247 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7248 gen_addr_add(ctx, addr, addr, 2);
7249 gen_qemu_ld16s(ctx, t0, addr);
7250 tcg_gen_shli_tl(t0, t0, 32);
7251 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7252 tcg_temp_free(t0);
7253 #else
7254 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7255 gen_addr_add(ctx, addr, addr, 2);
7256 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7257 #endif
7258 }
7259
7260 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7261 {
7262 TCGv t0 = tcg_temp_new();
7263 gen_qemu_ld32u(ctx, t0, addr);
7264 #if defined(TARGET_PPC64)
7265 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7266 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7267 #else
7268 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7269 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7270 #endif
7271 tcg_temp_free(t0);
7272 }
7273
7274 static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7275 {
7276 TCGv t0 = tcg_temp_new();
7277 #if defined(TARGET_PPC64)
7278 gen_qemu_ld16u(ctx, t0, addr);
7279 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7280 tcg_gen_shli_tl(t0, t0, 32);
7281 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7282 gen_addr_add(ctx, addr, addr, 2);
7283 gen_qemu_ld16u(ctx, t0, addr);
7284 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7285 tcg_gen_shli_tl(t0, t0, 16);
7286 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7287 #else
7288 gen_qemu_ld16u(ctx, t0, addr);
7289 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7290 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7291 gen_addr_add(ctx, addr, addr, 2);
7292 gen_qemu_ld16u(ctx, t0, addr);
7293 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7294 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7295 #endif
7296 tcg_temp_free(t0);
7297 }
7298
7299 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7300 {
7301 #if defined(TARGET_PPC64)
7302 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7303 #else
7304 TCGv_i64 t0 = tcg_temp_new_i64();
7305 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7306 gen_qemu_st64(ctx, t0, addr);
7307 tcg_temp_free_i64(t0);
7308 #endif
7309 }
7310
7311 static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7312 {
7313 #if defined(TARGET_PPC64)
7314 TCGv t0 = tcg_temp_new();
7315 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7316 gen_qemu_st32(ctx, t0, addr);
7317 tcg_temp_free(t0);
7318 #else
7319 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7320 #endif
7321 gen_addr_add(ctx, addr, addr, 4);
7322 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7323 }
7324
7325 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7326 {
7327 TCGv t0 = tcg_temp_new();
7328 #if defined(TARGET_PPC64)
7329 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7330 #else
7331 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7332 #endif
7333 gen_qemu_st16(ctx, t0, addr);
7334 gen_addr_add(ctx, addr, addr, 2);
7335 #if defined(TARGET_PPC64)
7336 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7337 gen_qemu_st16(ctx, t0, addr);
7338 #else
7339 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7340 #endif
7341 gen_addr_add(ctx, addr, addr, 2);
7342 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7343 gen_qemu_st16(ctx, t0, addr);
7344 tcg_temp_free(t0);
7345 gen_addr_add(ctx, addr, addr, 2);
7346 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7347 }
7348
7349 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7350 {
7351 TCGv t0 = tcg_temp_new();
7352 #if defined(TARGET_PPC64)
7353 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7354 #else
7355 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7356 #endif
7357 gen_qemu_st16(ctx, t0, addr);
7358 gen_addr_add(ctx, addr, addr, 2);
7359 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7360 gen_qemu_st16(ctx, t0, addr);
7361 tcg_temp_free(t0);
7362 }
7363
7364 static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7365 {
7366 #if defined(TARGET_PPC64)
7367 TCGv t0 = tcg_temp_new();
7368 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7369 gen_qemu_st16(ctx, t0, addr);
7370 tcg_temp_free(t0);
7371 #else
7372 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7373 #endif
7374 gen_addr_add(ctx, addr, addr, 2);
7375 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7376 }
7377
7378 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7379 {
7380 #if defined(TARGET_PPC64)
7381 TCGv t0 = tcg_temp_new();
7382 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7383 gen_qemu_st32(ctx, t0, addr);
7384 tcg_temp_free(t0);
7385 #else
7386 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7387 #endif
7388 }
7389
7390 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7391 {
7392 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7393 }
7394
7395 #define GEN_SPEOP_LDST(name, opc2, sh) \
7396 static void glue(gen_, name)(DisasContext *ctx) \
7397 { \
7398 TCGv t0; \
7399 if (unlikely(!ctx->spe_enabled)) { \
7400 gen_exception(ctx, POWERPC_EXCP_APU); \
7401 return; \
7402 } \
7403 gen_set_access_type(ctx, ACCESS_INT); \
7404 t0 = tcg_temp_new(); \
7405 if (Rc(ctx->opcode)) { \
7406 gen_addr_spe_imm_index(ctx, t0, sh); \
7407 } else { \
7408 gen_addr_reg_index(ctx, t0); \
7409 } \
7410 gen_op_##name(ctx, t0); \
7411 tcg_temp_free(t0); \
7412 }
7413
7414 GEN_SPEOP_LDST(evldd, 0x00, 3);
7415 GEN_SPEOP_LDST(evldw, 0x01, 3);
7416 GEN_SPEOP_LDST(evldh, 0x02, 3);
7417 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7418 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7419 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7420 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7421 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7422 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7423 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7424 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7425
7426 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7427 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7428 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7429 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7430 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7431 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7432 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7433
7434 /* Multiply and add - TODO */
7435 #if 0
7436 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7437 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7438 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7439 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7440 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7441 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7442 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7443 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7444 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7445 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7446 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7447 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7448
7449 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7450 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7451 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7452 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7453 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7454 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7455 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7456 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7457 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7458 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7459 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7460 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7461 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7462 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7463
7464 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7465 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7466 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7467 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7468 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7469 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7470
7471 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7472 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7473 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7474 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7475 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7476 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7477 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7478 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7479 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7480 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7481 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7482 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7483
7484 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7485 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7486 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7487 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7488 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7489
7490 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7491 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7492 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7493 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7494 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7495 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7496 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7497 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7498 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7499 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7500 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7501 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7502
7503 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7504 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7505 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7506 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7507 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7508 #endif
7509
7510 /*** SPE floating-point extension ***/
7511 #if defined(TARGET_PPC64)
7512 #define GEN_SPEFPUOP_CONV_32_32(name) \
7513 static always_inline void gen_##name (DisasContext *ctx) \
7514 { \
7515 TCGv_i32 t0; \
7516 TCGv t1; \
7517 t0 = tcg_temp_new_i32(); \
7518 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7519 gen_helper_##name(t0, t0); \
7520 t1 = tcg_temp_new(); \
7521 tcg_gen_extu_i32_tl(t1, t0); \
7522 tcg_temp_free_i32(t0); \
7523 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7524 0xFFFFFFFF00000000ULL); \
7525 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7526 tcg_temp_free(t1); \
7527 }
7528 #define GEN_SPEFPUOP_CONV_32_64(name) \
7529 static always_inline void gen_##name (DisasContext *ctx) \
7530 { \
7531 TCGv_i32 t0; \
7532 TCGv t1; \
7533 t0 = tcg_temp_new_i32(); \
7534 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7535 t1 = tcg_temp_new(); \
7536 tcg_gen_extu_i32_tl(t1, t0); \
7537 tcg_temp_free_i32(t0); \
7538 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7539 0xFFFFFFFF00000000ULL); \
7540 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7541 tcg_temp_free(t1); \
7542 }
7543 #define GEN_SPEFPUOP_CONV_64_32(name) \
7544 static always_inline void gen_##name (DisasContext *ctx) \
7545 { \
7546 TCGv_i32 t0 = tcg_temp_new_i32(); \
7547 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7548 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7549 tcg_temp_free_i32(t0); \
7550 }
7551 #define GEN_SPEFPUOP_CONV_64_64(name) \
7552 static always_inline void gen_##name (DisasContext *ctx) \
7553 { \
7554 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7555 }
7556 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7557 static always_inline void gen_##name (DisasContext *ctx) \
7558 { \
7559 TCGv_i32 t0, t1; \
7560 TCGv_i64 t2; \
7561 if (unlikely(!ctx->spe_enabled)) { \
7562 gen_exception(ctx, POWERPC_EXCP_APU); \
7563 return; \
7564 } \
7565 t0 = tcg_temp_new_i32(); \
7566 t1 = tcg_temp_new_i32(); \
7567 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7568 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7569 gen_helper_##name(t0, t0, t1); \
7570 tcg_temp_free_i32(t1); \
7571 t2 = tcg_temp_new(); \
7572 tcg_gen_extu_i32_tl(t2, t0); \
7573 tcg_temp_free_i32(t0); \
7574 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7575 0xFFFFFFFF00000000ULL); \
7576 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7577 tcg_temp_free(t2); \
7578 }
7579 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7580 static always_inline void gen_##name (DisasContext *ctx) \
7581 { \
7582 if (unlikely(!ctx->spe_enabled)) { \
7583 gen_exception(ctx, POWERPC_EXCP_APU); \
7584 return; \
7585 } \
7586 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7587 cpu_gpr[rB(ctx->opcode)]); \
7588 }
7589 #define GEN_SPEFPUOP_COMP_32(name) \
7590 static always_inline void gen_##name (DisasContext *ctx) \
7591 { \
7592 TCGv_i32 t0, t1; \
7593 if (unlikely(!ctx->spe_enabled)) { \
7594 gen_exception(ctx, POWERPC_EXCP_APU); \
7595 return; \
7596 } \
7597 t0 = tcg_temp_new_i32(); \
7598 t1 = tcg_temp_new_i32(); \
7599 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7600 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7601 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7602 tcg_temp_free_i32(t0); \
7603 tcg_temp_free_i32(t1); \
7604 }
7605 #define GEN_SPEFPUOP_COMP_64(name) \
7606 static always_inline void gen_##name (DisasContext *ctx) \
7607 { \
7608 if (unlikely(!ctx->spe_enabled)) { \
7609 gen_exception(ctx, POWERPC_EXCP_APU); \
7610 return; \
7611 } \
7612 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7613 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7614 }
7615 #else
7616 #define GEN_SPEFPUOP_CONV_32_32(name) \
7617 static always_inline void gen_##name (DisasContext *ctx) \
7618 { \
7619 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7620 }
7621 #define GEN_SPEFPUOP_CONV_32_64(name) \
7622 static always_inline void gen_##name (DisasContext *ctx) \
7623 { \
7624 TCGv_i64 t0 = tcg_temp_new_i64(); \
7625 gen_load_gpr64(t0, rB(ctx->opcode)); \
7626 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7627 tcg_temp_free_i64(t0); \
7628 }
7629 #define GEN_SPEFPUOP_CONV_64_32(name) \
7630 static always_inline void gen_##name (DisasContext *ctx) \
7631 { \
7632 TCGv_i64 t0 = tcg_temp_new_i64(); \
7633 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7634 gen_store_gpr64(rD(ctx->opcode), t0); \
7635 tcg_temp_free_i64(t0); \
7636 }
7637 #define GEN_SPEFPUOP_CONV_64_64(name) \
7638 static always_inline void gen_##name (DisasContext *ctx) \
7639 { \
7640 TCGv_i64 t0 = tcg_temp_new_i64(); \
7641 gen_load_gpr64(t0, rB(ctx->opcode)); \
7642 gen_helper_##name(t0, t0); \
7643 gen_store_gpr64(rD(ctx->opcode), t0); \
7644 tcg_temp_free_i64(t0); \
7645 }
7646 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7647 static always_inline void gen_##name (DisasContext *ctx) \
7648 { \
7649 if (unlikely(!ctx->spe_enabled)) { \
7650 gen_exception(ctx, POWERPC_EXCP_APU); \
7651 return; \
7652 } \
7653 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7654 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7655 }
7656 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7657 static always_inline void gen_##name (DisasContext *ctx) \
7658 { \
7659 TCGv_i64 t0, t1; \
7660 if (unlikely(!ctx->spe_enabled)) { \
7661 gen_exception(ctx, POWERPC_EXCP_APU); \
7662 return; \
7663 } \
7664 t0 = tcg_temp_new_i64(); \
7665 t1 = tcg_temp_new_i64(); \
7666 gen_load_gpr64(t0, rA(ctx->opcode)); \
7667 gen_load_gpr64(t1, rB(ctx->opcode)); \
7668 gen_helper_##name(t0, t0, t1); \
7669 gen_store_gpr64(rD(ctx->opcode), t0); \
7670 tcg_temp_free_i64(t0); \
7671 tcg_temp_free_i64(t1); \
7672 }
7673 #define GEN_SPEFPUOP_COMP_32(name) \
7674 static always_inline void gen_##name (DisasContext *ctx) \
7675 { \
7676 if (unlikely(!ctx->spe_enabled)) { \
7677 gen_exception(ctx, POWERPC_EXCP_APU); \
7678 return; \
7679 } \
7680 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7681 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7682 }
7683 #define GEN_SPEFPUOP_COMP_64(name) \
7684 static always_inline void gen_##name (DisasContext *ctx) \
7685 { \
7686 TCGv_i64 t0, t1; \
7687 if (unlikely(!ctx->spe_enabled)) { \
7688 gen_exception(ctx, POWERPC_EXCP_APU); \
7689 return; \
7690 } \
7691 t0 = tcg_temp_new_i64(); \
7692 t1 = tcg_temp_new_i64(); \
7693 gen_load_gpr64(t0, rA(ctx->opcode)); \
7694 gen_load_gpr64(t1, rB(ctx->opcode)); \
7695 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7696 tcg_temp_free_i64(t0); \
7697 tcg_temp_free_i64(t1); \
7698 }
7699 #endif
7700
7701 /* Single precision floating-point vectors operations */
7702 /* Arithmetic */
7703 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7704 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7705 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7706 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7707 static always_inline void gen_evfsabs (DisasContext *ctx)
7708 {
7709 if (unlikely(!ctx->spe_enabled)) {
7710 gen_exception(ctx, POWERPC_EXCP_APU);
7711 return;
7712 }
7713 #if defined(TARGET_PPC64)
7714 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7715 #else
7716 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7717 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7718 #endif
7719 }
7720 static always_inline void gen_evfsnabs (DisasContext *ctx)
7721 {
7722 if (unlikely(!ctx->spe_enabled)) {
7723 gen_exception(ctx, POWERPC_EXCP_APU);
7724 return;
7725 }
7726 #if defined(TARGET_PPC64)
7727 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7728 #else
7729 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7730 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7731 #endif
7732 }
7733 static always_inline void gen_evfsneg (DisasContext *ctx)
7734 {
7735 if (unlikely(!ctx->spe_enabled)) {
7736 gen_exception(ctx, POWERPC_EXCP_APU);
7737 return;
7738 }
7739 #if defined(TARGET_PPC64)
7740 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7741 #else
7742 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7743 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7744 #endif
7745 }
7746
7747 /* Conversion */
7748 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7749 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7750 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7751 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7752 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7753 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7754 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7755 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7756 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7757 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7758
7759 /* Comparison */
7760 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7761 GEN_SPEFPUOP_COMP_64(evfscmplt);
7762 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7763 GEN_SPEFPUOP_COMP_64(evfststgt);
7764 GEN_SPEFPUOP_COMP_64(evfststlt);
7765 GEN_SPEFPUOP_COMP_64(evfststeq);
7766
7767 /* Opcodes definitions */
7768 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7769 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7770 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7771 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7772 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7773 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7774 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7775 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7776 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7777 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7778 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7779 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7780 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7781 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7782
7783 /* Single precision floating-point operations */
7784 /* Arithmetic */
7785 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7786 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7787 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7788 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7789 static always_inline void gen_efsabs (DisasContext *ctx)
7790 {
7791 if (unlikely(!ctx->spe_enabled)) {
7792 gen_exception(ctx, POWERPC_EXCP_APU);
7793 return;
7794 }
7795 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7796 }
7797 static always_inline void gen_efsnabs (DisasContext *ctx)
7798 {
7799 if (unlikely(!ctx->spe_enabled)) {
7800 gen_exception(ctx, POWERPC_EXCP_APU);
7801 return;
7802 }
7803 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7804 }
7805 static always_inline void gen_efsneg (DisasContext *ctx)
7806 {
7807 if (unlikely(!ctx->spe_enabled)) {
7808 gen_exception(ctx, POWERPC_EXCP_APU);
7809 return;
7810 }
7811 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7812 }
7813
7814 /* Conversion */
7815 GEN_SPEFPUOP_CONV_32_32(efscfui);
7816 GEN_SPEFPUOP_CONV_32_32(efscfsi);
7817 GEN_SPEFPUOP_CONV_32_32(efscfuf);
7818 GEN_SPEFPUOP_CONV_32_32(efscfsf);
7819 GEN_SPEFPUOP_CONV_32_32(efsctui);
7820 GEN_SPEFPUOP_CONV_32_32(efsctsi);
7821 GEN_SPEFPUOP_CONV_32_32(efsctuf);
7822 GEN_SPEFPUOP_CONV_32_32(efsctsf);
7823 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7824 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7825 GEN_SPEFPUOP_CONV_32_64(efscfd);
7826
7827 /* Comparison */
7828 GEN_SPEFPUOP_COMP_32(efscmpgt);
7829 GEN_SPEFPUOP_COMP_32(efscmplt);
7830 GEN_SPEFPUOP_COMP_32(efscmpeq);
7831 GEN_SPEFPUOP_COMP_32(efststgt);
7832 GEN_SPEFPUOP_COMP_32(efststlt);
7833 GEN_SPEFPUOP_COMP_32(efststeq);
7834
7835 /* Opcodes definitions */
7836 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7837 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7838 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
7839 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
7840 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7841 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7842 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7843 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7844 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7845 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7846 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7847 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
7848 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7849 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
7850
7851 /* Double precision floating-point operations */
7852 /* Arithmetic */
7853 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7854 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7855 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7856 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7857 static always_inline void gen_efdabs (DisasContext *ctx)
7858 {
7859 if (unlikely(!ctx->spe_enabled)) {
7860 gen_exception(ctx, POWERPC_EXCP_APU);
7861 return;
7862 }
7863 #if defined(TARGET_PPC64)
7864 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7865 #else
7866 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7867 #endif
7868 }
7869 static always_inline void gen_efdnabs (DisasContext *ctx)
7870 {
7871 if (unlikely(!ctx->spe_enabled)) {
7872 gen_exception(ctx, POWERPC_EXCP_APU);
7873 return;
7874 }
7875 #if defined(TARGET_PPC64)
7876 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7877 #else
7878 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7879 #endif
7880 }
7881 static always_inline void gen_efdneg (DisasContext *ctx)
7882 {
7883 if (unlikely(!ctx->spe_enabled)) {
7884 gen_exception(ctx, POWERPC_EXCP_APU);
7885 return;
7886 }
7887 #if defined(TARGET_PPC64)
7888 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7889 #else
7890 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7891 #endif
7892 }
7893
7894 /* Conversion */
7895 GEN_SPEFPUOP_CONV_64_32(efdcfui);
7896 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7897 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7898 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7899 GEN_SPEFPUOP_CONV_32_64(efdctui);
7900 GEN_SPEFPUOP_CONV_32_64(efdctsi);
7901 GEN_SPEFPUOP_CONV_32_64(efdctuf);
7902 GEN_SPEFPUOP_CONV_32_64(efdctsf);
7903 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7904 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7905 GEN_SPEFPUOP_CONV_64_32(efdcfs);
7906 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7907 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7908 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7909 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
7910
7911 /* Comparison */
7912 GEN_SPEFPUOP_COMP_64(efdcmpgt);
7913 GEN_SPEFPUOP_COMP_64(efdcmplt);
7914 GEN_SPEFPUOP_COMP_64(efdcmpeq);
7915 GEN_SPEFPUOP_COMP_64(efdtstgt);
7916 GEN_SPEFPUOP_COMP_64(efdtstlt);
7917 GEN_SPEFPUOP_COMP_64(efdtsteq);
7918
7919 /* Opcodes definitions */
7920 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
7921 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7922 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
7923 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
7924 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
7925 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7926 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
7927 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
7928 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7929 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7930 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7931 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7932 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7933 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
7934 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
7935 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
7936
7937 static opcode_t opcodes[] = {
7938 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
7939 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
7940 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
7941 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
7942 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
7943 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
7944 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7945 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7946 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7947 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7948 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
7949 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
7950 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
7951 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
7952 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7953 #if defined(TARGET_PPC64)
7954 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
7955 #endif
7956 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
7957 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
7958 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7959 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7960 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7961 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
7962 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
7963 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
7964 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7965 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7966 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7967 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7968 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
7969 #if defined(TARGET_PPC64)
7970 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
7971 #endif
7972 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7973 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7974 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
7975 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
7976 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
7977 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
7978 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
7979 #if defined(TARGET_PPC64)
7980 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
7981 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
7982 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
7983 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
7984 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
7985 #endif
7986 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
7987 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
7988 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
7989 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
7990 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
7991 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
7992 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
7993 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
7994 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
7995 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
7996 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
7997 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
7998 #if defined(TARGET_PPC64)
7999 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8000 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8001 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8002 #endif
8003 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8004 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8005 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8006 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8007 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8008 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8009 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8010 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8011 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES),
8012 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8013 #if defined(TARGET_PPC64)
8014 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B),
8015 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8016 #endif
8017 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8018 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8019 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8020 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8021 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8022 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8023 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8024 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8025 #if defined(TARGET_PPC64)
8026 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8027 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8028 #endif
8029 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8030 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8031 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8032 #if defined(TARGET_PPC64)
8033 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8034 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8035 #endif
8036 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8037 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8038 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8039 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8040 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8041 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8042 #if defined(TARGET_PPC64)
8043 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8044 #endif
8045 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8046 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8047 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8048 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8049 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8050 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8051 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8052 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ),
8053 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT),
8054 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8055 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8056 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8057 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8058 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8059 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8060 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8061 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8062 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8063 #if defined(TARGET_PPC64)
8064 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8065 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8066 PPC_SEGMENT_64B),
8067 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8068 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8069 PPC_SEGMENT_64B),
8070 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B),
8071 #endif
8072 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8073 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8074 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8075 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8076 #if defined(TARGET_PPC64)
8077 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8078 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8079 #endif
8080 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8081 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8082 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8083 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8084 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8085 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8086 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8087 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8088 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8089 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8090 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8091 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8092 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8093 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8094 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8095 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8096 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8097 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8098 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8099 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8100 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8101 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8102 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8103 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8104 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8105 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8106 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8107 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8108 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8109 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8110 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8111 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8112 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8113 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8114 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8115 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8116 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8117 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8118 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8119 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8120 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8121 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8122 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8123 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8124 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8125 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8126 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8127 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8128 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8129 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8130 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8131 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8132 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8133 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8134 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8135 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8136 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8137 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8138 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8139 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8140 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8141 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8142 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8143 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8144 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8145 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8146 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8147 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8148 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8149 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8150 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8151 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE),
8152 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8153 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8154 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8155 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8156 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8157 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8158 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8159 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8160 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8161 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8162 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8163 GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE),
8164 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8165 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE),
8166 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8167 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8168 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8169 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8170 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8171 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8172 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8173 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8174 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8175 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8176
8177 #undef GEN_INT_ARITH_ADD
8178 #undef GEN_INT_ARITH_ADD_CONST
8179 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8180 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8181 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8182 add_ca, compute_ca, compute_ov) \
8183 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8184 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8185 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8186 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8187 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8188 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8189 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8190 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8191 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8192 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8193 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8194
8195 #undef GEN_INT_ARITH_DIVW
8196 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8197 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8198 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8199 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8200 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8201 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8202
8203 #if defined(TARGET_PPC64)
8204 #undef GEN_INT_ARITH_DIVD
8205 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8206 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8207 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8208 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8209 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8210 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8211
8212 #undef GEN_INT_ARITH_MUL_HELPER
8213 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8214 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8215 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8216 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8217 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8218 #endif
8219
8220 #undef GEN_INT_ARITH_SUBF
8221 #undef GEN_INT_ARITH_SUBF_CONST
8222 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8223 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8224 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8225 add_ca, compute_ca, compute_ov) \
8226 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8227 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8228 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8229 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8230 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8231 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8232 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8233 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8234 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8235 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8236 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8237
8238 #undef GEN_LOGICAL1
8239 #undef GEN_LOGICAL2
8240 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8241 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8242 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8243 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8244 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8245 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8246 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8247 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8248 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8249 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8250 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8251 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8252 #if defined(TARGET_PPC64)
8253 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8254 #endif
8255
8256 #if defined(TARGET_PPC64)
8257 #undef GEN_PPC64_R2
8258 #undef GEN_PPC64_R4
8259 #define GEN_PPC64_R2(name, opc1, opc2) \
8260 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8261 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8262 PPC_64B)
8263 #define GEN_PPC64_R4(name, opc1, opc2) \
8264 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8265 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8266 PPC_64B), \
8267 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8268 PPC_64B), \
8269 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8270 PPC_64B)
8271 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8272 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8273 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8274 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8275 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8276 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8277 #endif
8278
8279 #undef _GEN_FLOAT_ACB
8280 #undef GEN_FLOAT_ACB
8281 #undef _GEN_FLOAT_AB
8282 #undef GEN_FLOAT_AB
8283 #undef _GEN_FLOAT_AC
8284 #undef GEN_FLOAT_AC
8285 #undef GEN_FLOAT_B
8286 #undef GEN_FLOAT_BS
8287 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8288 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8289 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8290 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8291 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8292 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8293 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8294 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8295 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8296 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8297 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8298 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8299 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8300 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8301 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8302 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8303 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8304 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8305 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8306
8307 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8308 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8309 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8310 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8311 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8312 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8313 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8314 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8315 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8316 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8317 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8318 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8319 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8320 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8321 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8322 #if defined(TARGET_PPC64)
8323 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8324 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8325 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8326 #endif
8327 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8328 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8329 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8330 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8331 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8332 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8333 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8334
8335 #undef GEN_LD
8336 #undef GEN_LDU
8337 #undef GEN_LDUX
8338 #undef GEN_LDX
8339 #undef GEN_LDS
8340 #define GEN_LD(name, ldop, opc, type) \
8341 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8342 #define GEN_LDU(name, ldop, opc, type) \
8343 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8344 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8345 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8346 #define GEN_LDX(name, ldop, opc2, opc3, type) \
8347 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8348 #define GEN_LDS(name, ldop, op, type) \
8349 GEN_LD(name, ldop, op | 0x20, type) \
8350 GEN_LDU(name, ldop, op | 0x21, type) \
8351 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8352 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8353
8354 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8355 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8356 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8357 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8358 #if defined(TARGET_PPC64)
8359 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8360 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8361 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8362 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8363 #endif
8364 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8365 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8366
8367 #undef GEN_ST
8368 #undef GEN_STU
8369 #undef GEN_STUX
8370 #undef GEN_STX
8371 #undef GEN_STS
8372 #define GEN_ST(name, stop, opc, type) \
8373 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8374 #define GEN_STU(name, stop, opc, type) \
8375 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8376 #define GEN_STUX(name, stop, opc2, opc3, type) \
8377 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8378 #define GEN_STX(name, stop, opc2, opc3, type) \
8379 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8380 #define GEN_STS(name, stop, op, type) \
8381 GEN_ST(name, stop, op | 0x20, type) \
8382 GEN_STU(name, stop, op | 0x21, type) \
8383 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8384 GEN_STX(name, stop, 0x17, op | 0x00, type)
8385
8386 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8387 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8388 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8389 #if defined(TARGET_PPC64)
8390 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8391 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8392 #endif
8393 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8394 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8395
8396 #undef GEN_LDF
8397 #undef GEN_LDUF
8398 #undef GEN_LDUXF
8399 #undef GEN_LDXF
8400 #undef GEN_LDFS
8401 #define GEN_LDF(name, ldop, opc, type) \
8402 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8403 #define GEN_LDUF(name, ldop, opc, type) \
8404 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8405 #define GEN_LDUXF(name, ldop, opc, type) \
8406 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8407 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8408 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8409 #define GEN_LDFS(name, ldop, op, type) \
8410 GEN_LDF(name, ldop, op | 0x20, type) \
8411 GEN_LDUF(name, ldop, op | 0x21, type) \
8412 GEN_LDUXF(name, ldop, op | 0x01, type) \
8413 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8414
8415 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8416 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8417
8418 #undef GEN_STF
8419 #undef GEN_STUF
8420 #undef GEN_STUXF
8421 #undef GEN_STXF
8422 #undef GEN_STFS
8423 #define GEN_STF(name, stop, opc, type) \
8424 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8425 #define GEN_STUF(name, stop, opc, type) \
8426 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8427 #define GEN_STUXF(name, stop, opc, type) \
8428 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8429 #define GEN_STXF(name, stop, opc2, opc3, type) \
8430 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8431 #define GEN_STFS(name, stop, op, type) \
8432 GEN_STF(name, stop, op | 0x20, type) \
8433 GEN_STUF(name, stop, op | 0x21, type) \
8434 GEN_STUXF(name, stop, op | 0x01, type) \
8435 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8436
8437 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8438 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8439 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8440
8441 #undef GEN_CRLOGIC
8442 #define GEN_CRLOGIC(name, tcg_op, opc) \
8443 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8444 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8445 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8446 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8447 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8448 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8449 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8450 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8451 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8452
8453 #undef GEN_MAC_HANDLER
8454 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8455 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8456 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8457 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8458 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8459 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8460 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8461 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8462 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8463 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8464 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8465 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8466 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8467 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8468 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8469 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8470 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8471 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8472 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8473 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8474 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8475 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8476 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8477 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8478 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8479 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8480 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8481 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8482 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8483 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8484 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8485 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8486 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8487 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
8488 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
8489 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
8490 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
8491 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
8492 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
8493 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
8494 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
8495 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
8496 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
8497 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
8498
8499 #undef GEN_VR_LDX
8500 #undef GEN_VR_STX
8501 #undef GEN_VR_LVE
8502 #undef GEN_VR_STVE
8503 #define GEN_VR_LDX(name, opc2, opc3) \
8504 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8505 #define GEN_VR_STX(name, opc2, opc3) \
8506 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8507 #define GEN_VR_LVE(name, opc2, opc3) \
8508 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8509 #define GEN_VR_STVE(name, opc2, opc3) \
8510 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8511 GEN_VR_LDX(lvx, 0x07, 0x03),
8512 GEN_VR_LDX(lvxl, 0x07, 0x0B),
8513 GEN_VR_LVE(bx, 0x07, 0x00),
8514 GEN_VR_LVE(hx, 0x07, 0x01),
8515 GEN_VR_LVE(wx, 0x07, 0x02),
8516 GEN_VR_STX(svx, 0x07, 0x07),
8517 GEN_VR_STX(svxl, 0x07, 0x0F),
8518 GEN_VR_STVE(bx, 0x07, 0x04),
8519 GEN_VR_STVE(hx, 0x07, 0x05),
8520 GEN_VR_STVE(wx, 0x07, 0x06),
8521
8522 #undef GEN_VX_LOGICAL
8523 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
8524 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8525 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
8526 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
8527 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
8528 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
8529 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
8530
8531 #undef GEN_VXFORM
8532 #define GEN_VXFORM(name, opc2, opc3) \
8533 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8534 GEN_VXFORM(vaddubm, 0, 0),
8535 GEN_VXFORM(vadduhm, 0, 1),
8536 GEN_VXFORM(vadduwm, 0, 2),
8537 GEN_VXFORM(vsububm, 0, 16),
8538 GEN_VXFORM(vsubuhm, 0, 17),
8539 GEN_VXFORM(vsubuwm, 0, 18),
8540 GEN_VXFORM(vmaxub, 1, 0),
8541 GEN_VXFORM(vmaxuh, 1, 1),
8542 GEN_VXFORM(vmaxuw, 1, 2),
8543 GEN_VXFORM(vmaxsb, 1, 4),
8544 GEN_VXFORM(vmaxsh, 1, 5),
8545 GEN_VXFORM(vmaxsw, 1, 6),
8546 GEN_VXFORM(vminub, 1, 8),
8547 GEN_VXFORM(vminuh, 1, 9),
8548 GEN_VXFORM(vminuw, 1, 10),
8549 GEN_VXFORM(vminsb, 1, 12),
8550 GEN_VXFORM(vminsh, 1, 13),
8551 GEN_VXFORM(vminsw, 1, 14),
8552 GEN_VXFORM(vavgub, 1, 16),
8553 GEN_VXFORM(vavguh, 1, 17),
8554 GEN_VXFORM(vavguw, 1, 18),
8555 GEN_VXFORM(vavgsb, 1, 20),
8556 GEN_VXFORM(vavgsh, 1, 21),
8557 GEN_VXFORM(vavgsw, 1, 22),
8558 GEN_VXFORM(vmrghb, 6, 0),
8559 GEN_VXFORM(vmrghh, 6, 1),
8560 GEN_VXFORM(vmrghw, 6, 2),
8561 GEN_VXFORM(vmrglb, 6, 4),
8562 GEN_VXFORM(vmrglh, 6, 5),
8563 GEN_VXFORM(vmrglw, 6, 6),
8564 GEN_VXFORM(vmuloub, 4, 0),
8565 GEN_VXFORM(vmulouh, 4, 1),
8566 GEN_VXFORM(vmulosb, 4, 4),
8567 GEN_VXFORM(vmulosh, 4, 5),
8568 GEN_VXFORM(vmuleub, 4, 8),
8569 GEN_VXFORM(vmuleuh, 4, 9),
8570 GEN_VXFORM(vmulesb, 4, 12),
8571 GEN_VXFORM(vmulesh, 4, 13),
8572 GEN_VXFORM(vslb, 2, 4),
8573 GEN_VXFORM(vslh, 2, 5),
8574 GEN_VXFORM(vslw, 2, 6),
8575 GEN_VXFORM(vsrb, 2, 8),
8576 GEN_VXFORM(vsrh, 2, 9),
8577 GEN_VXFORM(vsrw, 2, 10),
8578 GEN_VXFORM(vsrab, 2, 12),
8579 GEN_VXFORM(vsrah, 2, 13),
8580 GEN_VXFORM(vsraw, 2, 14),
8581 GEN_VXFORM(vslo, 6, 16),
8582 GEN_VXFORM(vsro, 6, 17),
8583 GEN_VXFORM(vaddcuw, 0, 6),
8584 GEN_VXFORM(vsubcuw, 0, 22),
8585 GEN_VXFORM(vaddubs, 0, 8),
8586 GEN_VXFORM(vadduhs, 0, 9),
8587 GEN_VXFORM(vadduws, 0, 10),
8588 GEN_VXFORM(vaddsbs, 0, 12),
8589 GEN_VXFORM(vaddshs, 0, 13),
8590 GEN_VXFORM(vaddsws, 0, 14),
8591 GEN_VXFORM(vsububs, 0, 24),
8592 GEN_VXFORM(vsubuhs, 0, 25),
8593 GEN_VXFORM(vsubuws, 0, 26),
8594 GEN_VXFORM(vsubsbs, 0, 28),
8595 GEN_VXFORM(vsubshs, 0, 29),
8596 GEN_VXFORM(vsubsws, 0, 30),
8597 GEN_VXFORM(vrlb, 2, 0),
8598 GEN_VXFORM(vrlh, 2, 1),
8599 GEN_VXFORM(vrlw, 2, 2),
8600 GEN_VXFORM(vsl, 2, 7),
8601 GEN_VXFORM(vsr, 2, 11),
8602 GEN_VXFORM(vpkuhum, 7, 0),
8603 GEN_VXFORM(vpkuwum, 7, 1),
8604 GEN_VXFORM(vpkuhus, 7, 2),
8605 GEN_VXFORM(vpkuwus, 7, 3),
8606 GEN_VXFORM(vpkshus, 7, 4),
8607 GEN_VXFORM(vpkswus, 7, 5),
8608 GEN_VXFORM(vpkshss, 7, 6),
8609 GEN_VXFORM(vpkswss, 7, 7),
8610 GEN_VXFORM(vpkpx, 7, 12),
8611 GEN_VXFORM(vsum4ubs, 4, 24),
8612 GEN_VXFORM(vsum4sbs, 4, 28),
8613 GEN_VXFORM(vsum4shs, 4, 25),
8614 GEN_VXFORM(vsum2sws, 4, 26),
8615 GEN_VXFORM(vsumsws, 4, 30),
8616 GEN_VXFORM(vaddfp, 5, 0),
8617 GEN_VXFORM(vsubfp, 5, 1),
8618 GEN_VXFORM(vmaxfp, 5, 16),
8619 GEN_VXFORM(vminfp, 5, 17),
8620
8621 #undef GEN_VXRFORM1
8622 #undef GEN_VXRFORM
8623 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
8624 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
8625 #define GEN_VXRFORM(name, opc2, opc3) \
8626 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
8627 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
8628 GEN_VXRFORM(vcmpequb, 3, 0)
8629 GEN_VXRFORM(vcmpequh, 3, 1)
8630 GEN_VXRFORM(vcmpequw, 3, 2)
8631 GEN_VXRFORM(vcmpgtsb, 3, 12)
8632 GEN_VXRFORM(vcmpgtsh, 3, 13)
8633 GEN_VXRFORM(vcmpgtsw, 3, 14)
8634 GEN_VXRFORM(vcmpgtub, 3, 8)
8635 GEN_VXRFORM(vcmpgtuh, 3, 9)
8636 GEN_VXRFORM(vcmpgtuw, 3, 10)
8637 GEN_VXRFORM(vcmpeqfp, 3, 3)
8638 GEN_VXRFORM(vcmpgefp, 3, 7)
8639 GEN_VXRFORM(vcmpgtfp, 3, 11)
8640 GEN_VXRFORM(vcmpbfp, 3, 15)
8641
8642 #undef GEN_VXFORM_SIMM
8643 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
8644 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8645 GEN_VXFORM_SIMM(vspltisb, 6, 12),
8646 GEN_VXFORM_SIMM(vspltish, 6, 13),
8647 GEN_VXFORM_SIMM(vspltisw, 6, 14),
8648
8649 #undef GEN_VXFORM_NOA
8650 #define GEN_VXFORM_NOA(name, opc2, opc3) \
8651 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
8652 GEN_VXFORM_NOA(vupkhsb, 7, 8),
8653 GEN_VXFORM_NOA(vupkhsh, 7, 9),
8654 GEN_VXFORM_NOA(vupklsb, 7, 10),
8655 GEN_VXFORM_NOA(vupklsh, 7, 11),
8656 GEN_VXFORM_NOA(vupkhpx, 7, 13),
8657 GEN_VXFORM_NOA(vupklpx, 7, 15),
8658 GEN_VXFORM_NOA(vrefp, 5, 4),
8659 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
8660 GEN_VXFORM_NOA(vlogefp, 5, 7),
8661 GEN_VXFORM_NOA(vrfim, 5, 8),
8662 GEN_VXFORM_NOA(vrfin, 5, 9),
8663 GEN_VXFORM_NOA(vrfip, 5, 10),
8664 GEN_VXFORM_NOA(vrfiz, 5, 11),
8665
8666 #undef GEN_VXFORM_UIMM
8667 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
8668 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
8669 GEN_VXFORM_UIMM(vspltb, 6, 8),
8670 GEN_VXFORM_UIMM(vsplth, 6, 9),
8671 GEN_VXFORM_UIMM(vspltw, 6, 10),
8672 GEN_VXFORM_UIMM(vcfux, 5, 12),
8673 GEN_VXFORM_UIMM(vcfsx, 5, 13),
8674 GEN_VXFORM_UIMM(vctuxs, 5, 14),
8675 GEN_VXFORM_UIMM(vctsxs, 5, 15),
8676
8677 #undef GEN_VAFORM_PAIRED
8678 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
8679 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
8680 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
8681 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
8682 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
8683 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
8684 GEN_VAFORM_PAIRED(vsel, vperm, 21),
8685 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
8686
8687 #undef GEN_SPE
8688 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
8689 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type)
8690 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE),
8691 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE),
8692 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE),
8693 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE),
8694 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE),
8695 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE),
8696 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE),
8697 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE),
8698 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE),
8699 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE),
8700 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE),
8701 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE),
8702 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE),
8703 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE),
8704 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE),
8705 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE),
8706 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE),
8707 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE),
8708 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE),
8709 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE),
8710 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE),
8711 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE),
8712 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE),
8713 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE),
8714 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE),
8715
8716 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE),
8717 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE),
8718 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE),
8719 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE),
8720 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE),
8721 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE),
8722 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE),
8723 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE),
8724 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE),
8725 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE),
8726 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE),
8727 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE),
8728 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE),
8729 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE),
8730
8731 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE),
8732 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE),
8733 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE),
8734 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE),
8735 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE),
8736 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE),
8737 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE),
8738 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE),
8739 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE),
8740 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE),
8741 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE),
8742 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE),
8743 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE),
8744 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE),
8745
8746 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE),
8747 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8748 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE),
8749 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE),
8750 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE),
8751 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8752 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
8753 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
8754 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8755 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8756 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8757 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8758 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8759 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE),
8760 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
8761 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE),
8762
8763 #undef GEN_SPEOP_LDST
8764 #define GEN_SPEOP_LDST(name, opc2, sh) \
8765 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
8766 GEN_SPEOP_LDST(evldd, 0x00, 3),
8767 GEN_SPEOP_LDST(evldw, 0x01, 3),
8768 GEN_SPEOP_LDST(evldh, 0x02, 3),
8769 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
8770 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
8771 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
8772 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
8773 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
8774 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
8775 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
8776 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
8777
8778 GEN_SPEOP_LDST(evstdd, 0x10, 3),
8779 GEN_SPEOP_LDST(evstdw, 0x11, 3),
8780 GEN_SPEOP_LDST(evstdh, 0x12, 3),
8781 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
8782 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
8783 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
8784 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
8785 };
8786
8787 #include "translate_init.c"
8788 #include "helper_regs.h"
8789
8790 /*****************************************************************************/
8791 /* Misc PowerPC helpers */
8792 void cpu_dump_state (CPUState *env, FILE *f,
8793 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8794 int flags)
8795 {
8796 #define RGPL 4
8797 #define RFPL 4
8798
8799 int i;
8800
8801 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
8802 env->nip, env->lr, env->ctr, env->xer);
8803 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8804 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
8805 #if !defined(NO_TIMER_DUMP)
8806 cpu_fprintf(f, "TB %08x %08x "
8807 #if !defined(CONFIG_USER_ONLY)
8808 "DECR %08x"
8809 #endif
8810 "\n",
8811 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8812 #if !defined(CONFIG_USER_ONLY)
8813 , cpu_ppc_load_decr(env)
8814 #endif
8815 );
8816 #endif
8817 for (i = 0; i < 32; i++) {
8818 if ((i & (RGPL - 1)) == 0)
8819 cpu_fprintf(f, "GPR%02d", i);
8820 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
8821 if ((i & (RGPL - 1)) == (RGPL - 1))
8822 cpu_fprintf(f, "\n");
8823 }
8824 cpu_fprintf(f, "CR ");
8825 for (i = 0; i < 8; i++)
8826 cpu_fprintf(f, "%01x", env->crf[i]);
8827 cpu_fprintf(f, " [");
8828 for (i = 0; i < 8; i++) {
8829 char a = '-';
8830 if (env->crf[i] & 0x08)
8831 a = 'L';
8832 else if (env->crf[i] & 0x04)
8833 a = 'G';
8834 else if (env->crf[i] & 0x02)
8835 a = 'E';
8836 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8837 }
8838 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
8839 for (i = 0; i < 32; i++) {
8840 if ((i & (RFPL - 1)) == 0)
8841 cpu_fprintf(f, "FPR%02d", i);
8842 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
8843 if ((i & (RFPL - 1)) == (RFPL - 1))
8844 cpu_fprintf(f, "\n");
8845 }
8846 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
8847 #if !defined(CONFIG_USER_ONLY)
8848 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
8849 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
8850 #endif
8851
8852 #undef RGPL
8853 #undef RFPL
8854 }
8855
8856 void cpu_dump_statistics (CPUState *env, FILE*f,
8857 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8858 int flags)
8859 {
8860 #if defined(DO_PPC_STATISTICS)
8861 opc_handler_t **t1, **t2, **t3, *handler;
8862 int op1, op2, op3;
8863
8864 t1 = env->opcodes;
8865 for (op1 = 0; op1 < 64; op1++) {
8866 handler = t1[op1];
8867 if (is_indirect_opcode(handler)) {
8868 t2 = ind_table(handler);
8869 for (op2 = 0; op2 < 32; op2++) {
8870 handler = t2[op2];
8871 if (is_indirect_opcode(handler)) {
8872 t3 = ind_table(handler);
8873 for (op3 = 0; op3 < 32; op3++) {
8874 handler = t3[op3];
8875 if (handler->count == 0)
8876 continue;
8877 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8878 "%016llx %lld\n",
8879 op1, op2, op3, op1, (op3 << 5) | op2,
8880 handler->oname,
8881 handler->count, handler->count);
8882 }
8883 } else {
8884 if (handler->count == 0)
8885 continue;
8886 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8887 "%016llx %lld\n",
8888 op1, op2, op1, op2, handler->oname,
8889 handler->count, handler->count);
8890 }
8891 }
8892 } else {
8893 if (handler->count == 0)
8894 continue;
8895 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8896 op1, op1, handler->oname,
8897 handler->count, handler->count);
8898 }
8899 }
8900 #endif
8901 }
8902
8903 /*****************************************************************************/
8904 static always_inline void gen_intermediate_code_internal (CPUState *env,
8905 TranslationBlock *tb,
8906 int search_pc)
8907 {
8908 DisasContext ctx, *ctxp = &ctx;
8909 opc_handler_t **table, *handler;
8910 target_ulong pc_start;
8911 uint16_t *gen_opc_end;
8912 CPUBreakpoint *bp;
8913 int j, lj = -1;
8914 int num_insns;
8915 int max_insns;
8916
8917 pc_start = tb->pc;
8918 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
8919 ctx.nip = pc_start;
8920 ctx.tb = tb;
8921 ctx.exception = POWERPC_EXCP_NONE;
8922 ctx.spr_cb = env->spr_cb;
8923 ctx.mem_idx = env->mmu_idx;
8924 ctx.access_type = -1;
8925 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
8926 #if defined(TARGET_PPC64)
8927 ctx.sf_mode = msr_sf;
8928 #endif
8929 ctx.fpu_enabled = msr_fp;
8930 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
8931 ctx.spe_enabled = msr_spe;
8932 else
8933 ctx.spe_enabled = 0;
8934 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8935 ctx.altivec_enabled = msr_vr;
8936 else
8937 ctx.altivec_enabled = 0;
8938 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8939 ctx.singlestep_enabled = CPU_SINGLE_STEP;
8940 else
8941 ctx.singlestep_enabled = 0;
8942 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8943 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8944 if (unlikely(env->singlestep_enabled))
8945 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
8946 #if defined (DO_SINGLE_STEP) && 0
8947 /* Single step trace mode */
8948 msr_se = 1;
8949 #endif
8950 num_insns = 0;
8951 max_insns = tb->cflags & CF_COUNT_MASK;
8952 if (max_insns == 0)
8953 max_insns = CF_COUNT_MASK;
8954
8955 gen_icount_start();
8956 /* Set env in case of segfault during code fetch */
8957 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
8958 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8959 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
8960 if (bp->pc == ctx.nip) {
8961 gen_debug_exception(ctxp);
8962 break;
8963 }
8964 }
8965 }
8966 if (unlikely(search_pc)) {
8967 j = gen_opc_ptr - gen_opc_buf;
8968 if (lj < j) {
8969 lj++;
8970 while (lj < j)
8971 gen_opc_instr_start[lj++] = 0;
8972 }
8973 gen_opc_pc[lj] = ctx.nip;
8974 gen_opc_instr_start[lj] = 1;
8975 gen_opc_icount[lj] = num_insns;
8976 }
8977 LOG_DISAS("----------------\n");
8978 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8979 ctx.nip, ctx.mem_idx, (int)msr_ir);
8980 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8981 gen_io_start();
8982 if (unlikely(ctx.le_mode)) {
8983 ctx.opcode = bswap32(ldl_code(ctx.nip));
8984 } else {
8985 ctx.opcode = ldl_code(ctx.nip);
8986 }
8987 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
8988 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
8989 opc3(ctx.opcode), little_endian ? "little" : "big");
8990 ctx.nip += 4;
8991 table = env->opcodes;
8992 num_insns++;
8993 handler = table[opc1(ctx.opcode)];
8994 if (is_indirect_opcode(handler)) {
8995 table = ind_table(handler);
8996 handler = table[opc2(ctx.opcode)];
8997 if (is_indirect_opcode(handler)) {
8998 table = ind_table(handler);
8999 handler = table[opc3(ctx.opcode)];
9000 }
9001 }
9002 /* Is opcode *REALLY* valid ? */
9003 if (unlikely(handler->handler == &gen_invalid)) {
9004 if (qemu_log_enabled()) {
9005 qemu_log("invalid/unsupported opcode: "
9006 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
9007 opc1(ctx.opcode), opc2(ctx.opcode),
9008 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9009 } else {
9010 printf("invalid/unsupported opcode: "
9011 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
9012 opc1(ctx.opcode), opc2(ctx.opcode),
9013 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9014 }
9015 } else {
9016 if (unlikely((ctx.opcode & handler->inval) != 0)) {
9017 if (qemu_log_enabled()) {
9018 qemu_log("invalid bits: %08x for opcode: "
9019 "%02x - %02x - %02x (%08x) " ADDRX "\n",
9020 ctx.opcode & handler->inval, opc1(ctx.opcode),
9021 opc2(ctx.opcode), opc3(ctx.opcode),
9022 ctx.opcode, ctx.nip - 4);
9023 } else {
9024 printf("invalid bits: %08x for opcode: "
9025 "%02x - %02x - %02x (%08x) " ADDRX "\n",
9026 ctx.opcode & handler->inval, opc1(ctx.opcode),
9027 opc2(ctx.opcode), opc3(ctx.opcode),
9028 ctx.opcode, ctx.nip - 4);
9029 }
9030 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9031 break;
9032 }
9033 }
9034 (*(handler->handler))(&ctx);
9035 #if defined(DO_PPC_STATISTICS)
9036 handler->count++;
9037 #endif
9038 /* Check trace mode exceptions */
9039 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9040 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9041 ctx.exception != POWERPC_SYSCALL &&
9042 ctx.exception != POWERPC_EXCP_TRAP &&
9043 ctx.exception != POWERPC_EXCP_BRANCH)) {
9044 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9045 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9046 (env->singlestep_enabled) ||
9047 singlestep ||
9048 num_insns >= max_insns)) {
9049 /* if we reach a page boundary or are single stepping, stop
9050 * generation
9051 */
9052 break;
9053 }
9054 }
9055 if (tb->cflags & CF_LAST_IO)
9056 gen_io_end();
9057 if (ctx.exception == POWERPC_EXCP_NONE) {
9058 gen_goto_tb(&ctx, 0, ctx.nip);
9059 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9060 if (unlikely(env->singlestep_enabled)) {
9061 gen_debug_exception(ctxp);
9062 }
9063 /* Generate the return instruction */
9064 tcg_gen_exit_tb(0);
9065 }
9066 gen_icount_end(tb, num_insns);
9067 *gen_opc_ptr = INDEX_op_end;
9068 if (unlikely(search_pc)) {
9069 j = gen_opc_ptr - gen_opc_buf;
9070 lj++;
9071 while (lj <= j)
9072 gen_opc_instr_start[lj++] = 0;
9073 } else {
9074 tb->size = ctx.nip - pc_start;
9075 tb->icount = num_insns;
9076 }
9077 #if defined(DEBUG_DISAS)
9078 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
9079 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
9080 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9081 int flags;
9082 flags = env->bfd_mach;
9083 flags |= ctx.le_mode << 16;
9084 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9085 log_target_disas(pc_start, ctx.nip - pc_start, flags);
9086 qemu_log("\n");
9087 }
9088 #endif
9089 }
9090
9091 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
9092 {
9093 gen_intermediate_code_internal(env, tb, 0);
9094 }
9095
9096 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
9097 {
9098 gen_intermediate_code_internal(env, tb, 1);
9099 }
9100
9101 void gen_pc_load(CPUState *env, TranslationBlock *tb,
9102 unsigned long searched_pc, int pc_pos, void *puc)
9103 {
9104 env->nip = gen_opc_pc[pc_pos];
9105 }
Qemu copy for testing