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target-ppc: Implement neg in terms of subf
[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 struct opc_handler_t {
208 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
209 uint32_t inval1;
210 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
211 uint32_t inval2;
212 /* instruction type */
213 uint64_t type;
214 /* extended instruction type */
215 uint64_t type2;
216 /* handler */
217 void (*handler)(DisasContext *ctx);
218 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
219 const char *oname;
220 #endif
221 #if defined(DO_PPC_STATISTICS)
222 uint64_t count;
223 #endif
224 };
225
226 static inline void gen_reset_fpstatus(void)
227 {
228 gen_helper_reset_fpstatus(cpu_env);
229 }
230
231 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
232 {
233 TCGv_i32 t0 = tcg_temp_new_i32();
234
235 if (set_fprf != 0) {
236 /* This case might be optimized later */
237 tcg_gen_movi_i32(t0, 1);
238 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
239 if (unlikely(set_rc)) {
240 tcg_gen_mov_i32(cpu_crf[1], t0);
241 }
242 gen_helper_float_check_status(cpu_env);
243 } else if (unlikely(set_rc)) {
244 /* We always need to compute fpcc */
245 tcg_gen_movi_i32(t0, 0);
246 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249
250 tcg_temp_free_i32(t0);
251 }
252
253 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
254 {
255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
259 }
260
261 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
262 {
263 #if defined(TARGET_PPC64)
264 if (ctx->sf_mode)
265 tcg_gen_movi_tl(cpu_nip, nip);
266 else
267 #endif
268 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
269 }
270
271 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
272 {
273 TCGv_i32 t0, t1;
274 if (ctx->exception == POWERPC_EXCP_NONE) {
275 gen_update_nip(ctx, ctx->nip);
276 }
277 t0 = tcg_const_i32(excp);
278 t1 = tcg_const_i32(error);
279 gen_helper_raise_exception_err(cpu_env, t0, t1);
280 tcg_temp_free_i32(t0);
281 tcg_temp_free_i32(t1);
282 ctx->exception = (excp);
283 }
284
285 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
286 {
287 TCGv_i32 t0;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 gen_helper_raise_exception(cpu_env, t0);
293 tcg_temp_free_i32(t0);
294 ctx->exception = (excp);
295 }
296
297 static inline void gen_debug_exception(DisasContext *ctx)
298 {
299 TCGv_i32 t0;
300
301 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
302 (ctx->exception != POWERPC_EXCP_SYNC)) {
303 gen_update_nip(ctx, ctx->nip);
304 }
305 t0 = tcg_const_i32(EXCP_DEBUG);
306 gen_helper_raise_exception(cpu_env, t0);
307 tcg_temp_free_i32(t0);
308 }
309
310 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
311 {
312 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
313 }
314
315 /* Stop translation */
316 static inline void gen_stop_exception(DisasContext *ctx)
317 {
318 gen_update_nip(ctx, ctx->nip);
319 ctx->exception = POWERPC_EXCP_STOP;
320 }
321
322 /* No need to update nip here, as execution flow will change */
323 static inline void gen_sync_exception(DisasContext *ctx)
324 {
325 ctx->exception = POWERPC_EXCP_SYNC;
326 }
327
328 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
333
334 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
335 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
336
337 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
338 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
339
340 typedef struct opcode_t {
341 unsigned char opc1, opc2, opc3;
342 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
343 unsigned char pad[5];
344 #else
345 unsigned char pad[1];
346 #endif
347 opc_handler_t handler;
348 const char *oname;
349 } opcode_t;
350
351 /*****************************************************************************/
352 /*** Instruction decoding ***/
353 #define EXTRACT_HELPER(name, shift, nb) \
354 static inline uint32_t name(uint32_t opcode) \
355 { \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
357 }
358
359 #define EXTRACT_SHELPER(name, shift, nb) \
360 static inline int32_t name(uint32_t opcode) \
361 { \
362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
363 }
364
365 /* Opcode part 1 */
366 EXTRACT_HELPER(opc1, 26, 6);
367 /* Opcode part 2 */
368 EXTRACT_HELPER(opc2, 1, 5);
369 /* Opcode part 3 */
370 EXTRACT_HELPER(opc3, 6, 5);
371 /* Update Cr0 flags */
372 EXTRACT_HELPER(Rc, 0, 1);
373 /* Destination */
374 EXTRACT_HELPER(rD, 21, 5);
375 /* Source */
376 EXTRACT_HELPER(rS, 21, 5);
377 /* First operand */
378 EXTRACT_HELPER(rA, 16, 5);
379 /* Second operand */
380 EXTRACT_HELPER(rB, 11, 5);
381 /* Third operand */
382 EXTRACT_HELPER(rC, 6, 5);
383 /*** Get CRn ***/
384 EXTRACT_HELPER(crfD, 23, 3);
385 EXTRACT_HELPER(crfS, 18, 3);
386 EXTRACT_HELPER(crbD, 21, 5);
387 EXTRACT_HELPER(crbA, 16, 5);
388 EXTRACT_HELPER(crbB, 11, 5);
389 /* SPR / TBL */
390 EXTRACT_HELPER(_SPR, 11, 10);
391 static inline uint32_t SPR(uint32_t opcode)
392 {
393 uint32_t sprn = _SPR(opcode);
394
395 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
396 }
397 /*** Get constants ***/
398 EXTRACT_HELPER(IMM, 12, 8);
399 /* 16 bits signed immediate value */
400 EXTRACT_SHELPER(SIMM, 0, 16);
401 /* 16 bits unsigned immediate value */
402 EXTRACT_HELPER(UIMM, 0, 16);
403 /* 5 bits signed immediate value */
404 EXTRACT_HELPER(SIMM5, 16, 5);
405 /* 5 bits signed immediate value */
406 EXTRACT_HELPER(UIMM5, 16, 5);
407 /* Bit count */
408 EXTRACT_HELPER(NB, 11, 5);
409 /* Shift count */
410 EXTRACT_HELPER(SH, 11, 5);
411 /* Vector shift count */
412 EXTRACT_HELPER(VSH, 6, 4);
413 /* Mask start */
414 EXTRACT_HELPER(MB, 6, 5);
415 /* Mask end */
416 EXTRACT_HELPER(ME, 1, 5);
417 /* Trap operand */
418 EXTRACT_HELPER(TO, 21, 5);
419
420 EXTRACT_HELPER(CRM, 12, 8);
421 EXTRACT_HELPER(FM, 17, 8);
422 EXTRACT_HELPER(SR, 16, 4);
423 EXTRACT_HELPER(FPIMM, 12, 4);
424
425 /*** Jump target decoding ***/
426 /* Displacement */
427 EXTRACT_SHELPER(d, 0, 16);
428 /* Immediate address */
429 static inline target_ulong LI(uint32_t opcode)
430 {
431 return (opcode >> 0) & 0x03FFFFFC;
432 }
433
434 static inline uint32_t BD(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0xFFFC;
437 }
438
439 EXTRACT_HELPER(BO, 21, 5);
440 EXTRACT_HELPER(BI, 16, 5);
441 /* Absolute/relative address */
442 EXTRACT_HELPER(AA, 1, 1);
443 /* Link */
444 EXTRACT_HELPER(LK, 0, 1);
445
446 /* Create a mask between <start> and <end> bits */
447 static inline target_ulong MASK(uint32_t start, uint32_t end)
448 {
449 target_ulong ret;
450
451 #if defined(TARGET_PPC64)
452 if (likely(start == 0)) {
453 ret = UINT64_MAX << (63 - end);
454 } else if (likely(end == 63)) {
455 ret = UINT64_MAX >> start;
456 }
457 #else
458 if (likely(start == 0)) {
459 ret = UINT32_MAX << (31 - end);
460 } else if (likely(end == 31)) {
461 ret = UINT32_MAX >> start;
462 }
463 #endif
464 else {
465 ret = (((target_ulong)(-1ULL)) >> (start)) ^
466 (((target_ulong)(-1ULL) >> (end)) >> 1);
467 if (unlikely(start > end))
468 return ~ret;
469 }
470
471 return ret;
472 }
473
474 /*****************************************************************************/
475 /* PowerPC instructions table */
476
477 #if defined(DO_PPC_STATISTICS)
478 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
479 { \
480 .opc1 = op1, \
481 .opc2 = op2, \
482 .opc3 = op3, \
483 .pad = { 0, }, \
484 .handler = { \
485 .inval1 = invl, \
486 .type = _typ, \
487 .type2 = _typ2, \
488 .handler = &gen_##name, \
489 .oname = stringify(name), \
490 }, \
491 .oname = stringify(name), \
492 }
493 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
494 { \
495 .opc1 = op1, \
496 .opc2 = op2, \
497 .opc3 = op3, \
498 .pad = { 0, }, \
499 .handler = { \
500 .inval1 = invl1, \
501 .inval2 = invl2, \
502 .type = _typ, \
503 .type2 = _typ2, \
504 .handler = &gen_##name, \
505 .oname = stringify(name), \
506 }, \
507 .oname = stringify(name), \
508 }
509 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
510 { \
511 .opc1 = op1, \
512 .opc2 = op2, \
513 .opc3 = op3, \
514 .pad = { 0, }, \
515 .handler = { \
516 .inval1 = invl, \
517 .type = _typ, \
518 .type2 = _typ2, \
519 .handler = &gen_##name, \
520 .oname = onam, \
521 }, \
522 .oname = onam, \
523 }
524 #else
525 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
526 { \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl, \
533 .type = _typ, \
534 .type2 = _typ2, \
535 .handler = &gen_##name, \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
548 .type = _typ, \
549 .type2 = _typ2, \
550 .handler = &gen_##name, \
551 }, \
552 .oname = stringify(name), \
553 }
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555 { \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 }, \
566 .oname = onam, \
567 }
568 #endif
569
570 /* SPR load/store helpers */
571 static inline void gen_load_spr(TCGv t, int reg)
572 {
573 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
574 }
575
576 static inline void gen_store_spr(int reg, TCGv t)
577 {
578 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 /* Invalid instruction */
582 static void gen_invalid(DisasContext *ctx)
583 {
584 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
585 }
586
587 static opc_handler_t invalid_handler = {
588 .inval1 = 0xFFFFFFFF,
589 .inval2 = 0xFFFFFFFF,
590 .type = PPC_NONE,
591 .type2 = PPC_NONE,
592 .handler = gen_invalid,
593 };
594
595 /*** Integer comparison ***/
596
597 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
598 {
599 TCGv t0 = tcg_temp_new();
600 TCGv_i32 t1 = tcg_temp_new_i32();
601
602 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
603
604 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
605 tcg_gen_trunc_tl_i32(t1, t0);
606 tcg_gen_shli_i32(t1, t1, CRF_LT);
607 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_GT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_EQ);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_temp_free(t0);
620 tcg_temp_free_i32(t1);
621 }
622
623 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
624 {
625 TCGv t0 = tcg_const_tl(arg1);
626 gen_op_cmp(arg0, t0, s, crf);
627 tcg_temp_free(t0);
628 }
629
630 #if defined(TARGET_PPC64)
631 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
632 {
633 TCGv t0, t1;
634 t0 = tcg_temp_new();
635 t1 = tcg_temp_new();
636 if (s) {
637 tcg_gen_ext32s_tl(t0, arg0);
638 tcg_gen_ext32s_tl(t1, arg1);
639 } else {
640 tcg_gen_ext32u_tl(t0, arg0);
641 tcg_gen_ext32u_tl(t1, arg1);
642 }
643 gen_op_cmp(t0, t1, s, crf);
644 tcg_temp_free(t1);
645 tcg_temp_free(t0);
646 }
647
648 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
649 {
650 TCGv t0 = tcg_const_tl(arg1);
651 gen_op_cmp32(arg0, t0, s, crf);
652 tcg_temp_free(t0);
653 }
654 #endif
655
656 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
657 {
658 #if defined(TARGET_PPC64)
659 if (!(ctx->sf_mode))
660 gen_op_cmpi32(reg, 0, 1, 0);
661 else
662 #endif
663 gen_op_cmpi(reg, 0, 1, 0);
664 }
665
666 /* cmp */
667 static void gen_cmp(DisasContext *ctx)
668 {
669 #if defined(TARGET_PPC64)
670 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
671 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 else
674 #endif
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678
679 /* cmpi */
680 static void gen_cmpi(DisasContext *ctx)
681 {
682 #if defined(TARGET_PPC64)
683 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 else
687 #endif
688 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
689 1, crfD(ctx->opcode));
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 #if defined(TARGET_PPC64)
696 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 else
700 #endif
701 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
702 0, crfD(ctx->opcode));
703 }
704
705 /* cmpli */
706 static void gen_cmpli(DisasContext *ctx)
707 {
708 #if defined(TARGET_PPC64)
709 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
710 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712 else
713 #endif
714 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
715 0, crfD(ctx->opcode));
716 }
717
718 /* isel (PowerPC 2.03 specification) */
719 static void gen_isel(DisasContext *ctx)
720 {
721 int l1, l2;
722 uint32_t bi = rC(ctx->opcode);
723 uint32_t mask;
724 TCGv_i32 t0;
725
726 l1 = gen_new_label();
727 l2 = gen_new_label();
728
729 mask = 1 << (3 - (bi & 0x03));
730 t0 = tcg_temp_new_i32();
731 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
732 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
733 if (rA(ctx->opcode) == 0)
734 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
735 else
736 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
737 tcg_gen_br(l2);
738 gen_set_label(l1);
739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
740 gen_set_label(l2);
741 tcg_temp_free_i32(t0);
742 }
743
744 /*** Integer arithmetic ***/
745
746 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
747 TCGv arg1, TCGv arg2, int sub)
748 {
749 TCGv t0 = tcg_temp_new();
750
751 tcg_gen_xor_tl(cpu_ov, arg0, arg1);
752 tcg_gen_xor_tl(t0, arg1, arg2);
753 if (sub) {
754 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
755 } else {
756 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
757 }
758 tcg_temp_free(t0);
759 #if defined(TARGET_PPC64)
760 if (!ctx->sf_mode) {
761 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
762 }
763 #endif
764 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
765 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
766 }
767
768 /* Common add function */
769 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
770 TCGv arg2, bool add_ca, bool compute_ca,
771 bool compute_ov, bool compute_rc0)
772 {
773 TCGv t0 = ret;
774
775 if (((compute_ca && add_ca) || compute_ov)
776 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
777 t0 = tcg_temp_new();
778 }
779
780 if (compute_ca) {
781 TCGv zero = tcg_const_tl(0);
782 if (add_ca) {
783 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
784 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
785 } else {
786 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
787 }
788 tcg_temp_free(zero);
789 } else {
790 tcg_gen_add_tl(t0, arg1, arg2);
791 if (add_ca) {
792 tcg_gen_add_tl(t0, t0, cpu_ca);
793 }
794 }
795
796 if (compute_ov) {
797 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
798 }
799 if (unlikely(compute_rc0)) {
800 gen_set_Rc0(ctx, t0);
801 }
802
803 if (!TCGV_EQUAL(t0, ret)) {
804 tcg_gen_mov_tl(ret, t0);
805 tcg_temp_free(t0);
806 }
807 }
808 /* Add functions with two operands */
809 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
810 static void glue(gen_, name)(DisasContext *ctx) \
811 { \
812 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
813 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
814 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
815 }
816 /* Add functions with one operand and one immediate */
817 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
818 add_ca, compute_ca, compute_ov) \
819 static void glue(gen_, name)(DisasContext *ctx) \
820 { \
821 TCGv t0 = tcg_const_tl(const_val); \
822 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
823 cpu_gpr[rA(ctx->opcode)], t0, \
824 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
825 tcg_temp_free(t0); \
826 }
827
828 /* add add. addo addo. */
829 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
830 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
831 /* addc addc. addco addco. */
832 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
833 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
834 /* adde adde. addeo addeo. */
835 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
836 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
837 /* addme addme. addmeo addmeo. */
838 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
839 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
840 /* addze addze. addzeo addzeo.*/
841 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
842 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
843 /* addi */
844 static void gen_addi(DisasContext *ctx)
845 {
846 target_long simm = SIMM(ctx->opcode);
847
848 if (rA(ctx->opcode) == 0) {
849 /* li case */
850 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
851 } else {
852 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
853 cpu_gpr[rA(ctx->opcode)], simm);
854 }
855 }
856 /* addic addic.*/
857 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
858 {
859 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
860 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
861 c, 0, 1, 0, compute_rc0);
862 tcg_temp_free(c);
863 }
864
865 static void gen_addic(DisasContext *ctx)
866 {
867 gen_op_addic(ctx, 0);
868 }
869
870 static void gen_addic_(DisasContext *ctx)
871 {
872 gen_op_addic(ctx, 1);
873 }
874
875 /* addis */
876 static void gen_addis(DisasContext *ctx)
877 {
878 target_long simm = SIMM(ctx->opcode);
879
880 if (rA(ctx->opcode) == 0) {
881 /* lis case */
882 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
883 } else {
884 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
885 cpu_gpr[rA(ctx->opcode)], simm << 16);
886 }
887 }
888
889 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
890 TCGv arg2, int sign, int compute_ov)
891 {
892 int l1 = gen_new_label();
893 int l2 = gen_new_label();
894 TCGv_i32 t0 = tcg_temp_local_new_i32();
895 TCGv_i32 t1 = tcg_temp_local_new_i32();
896
897 tcg_gen_trunc_tl_i32(t0, arg1);
898 tcg_gen_trunc_tl_i32(t1, arg2);
899 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
900 if (sign) {
901 int l3 = gen_new_label();
902 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
903 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
904 gen_set_label(l3);
905 tcg_gen_div_i32(t0, t0, t1);
906 } else {
907 tcg_gen_divu_i32(t0, t0, t1);
908 }
909 if (compute_ov) {
910 tcg_gen_movi_tl(cpu_ov, 0);
911 }
912 tcg_gen_br(l2);
913 gen_set_label(l1);
914 if (sign) {
915 tcg_gen_sari_i32(t0, t0, 31);
916 } else {
917 tcg_gen_movi_i32(t0, 0);
918 }
919 if (compute_ov) {
920 tcg_gen_movi_tl(cpu_ov, 1);
921 tcg_gen_movi_tl(cpu_so, 1);
922 }
923 gen_set_label(l2);
924 tcg_gen_extu_i32_tl(ret, t0);
925 tcg_temp_free_i32(t0);
926 tcg_temp_free_i32(t1);
927 if (unlikely(Rc(ctx->opcode) != 0))
928 gen_set_Rc0(ctx, ret);
929 }
930 /* Div functions */
931 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
932 static void glue(gen_, name)(DisasContext *ctx) \
933 { \
934 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
935 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
936 sign, compute_ov); \
937 }
938 /* divwu divwu. divwuo divwuo. */
939 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
940 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
941 /* divw divw. divwo divwo. */
942 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
943 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
944 #if defined(TARGET_PPC64)
945 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
946 TCGv arg2, int sign, int compute_ov)
947 {
948 int l1 = gen_new_label();
949 int l2 = gen_new_label();
950
951 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
952 if (sign) {
953 int l3 = gen_new_label();
954 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
955 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
956 gen_set_label(l3);
957 tcg_gen_div_i64(ret, arg1, arg2);
958 } else {
959 tcg_gen_divu_i64(ret, arg1, arg2);
960 }
961 if (compute_ov) {
962 tcg_gen_movi_tl(cpu_ov, 0);
963 }
964 tcg_gen_br(l2);
965 gen_set_label(l1);
966 if (sign) {
967 tcg_gen_sari_i64(ret, arg1, 63);
968 } else {
969 tcg_gen_movi_i64(ret, 0);
970 }
971 if (compute_ov) {
972 tcg_gen_movi_tl(cpu_ov, 1);
973 tcg_gen_movi_tl(cpu_so, 1);
974 }
975 gen_set_label(l2);
976 if (unlikely(Rc(ctx->opcode) != 0))
977 gen_set_Rc0(ctx, ret);
978 }
979 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
980 static void glue(gen_, name)(DisasContext *ctx) \
981 { \
982 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
984 sign, compute_ov); \
985 }
986 /* divwu divwu. divwuo divwuo. */
987 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
988 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
989 /* divw divw. divwo divwo. */
990 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
991 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
992 #endif
993
994 /* mulhw mulhw. */
995 static void gen_mulhw(DisasContext *ctx)
996 {
997 TCGv_i32 t0 = tcg_temp_new_i32();
998 TCGv_i32 t1 = tcg_temp_new_i32();
999
1000 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1001 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1002 tcg_gen_muls2_i32(t0, t1, t0, t1);
1003 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1004 tcg_temp_free_i32(t0);
1005 tcg_temp_free_i32(t1);
1006 if (unlikely(Rc(ctx->opcode) != 0))
1007 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1008 }
1009
1010 /* mulhwu mulhwu. */
1011 static void gen_mulhwu(DisasContext *ctx)
1012 {
1013 TCGv_i32 t0 = tcg_temp_new_i32();
1014 TCGv_i32 t1 = tcg_temp_new_i32();
1015
1016 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1017 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1018 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1019 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1020 tcg_temp_free_i32(t0);
1021 tcg_temp_free_i32(t1);
1022 if (unlikely(Rc(ctx->opcode) != 0))
1023 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1024 }
1025
1026 /* mullw mullw. */
1027 static void gen_mullw(DisasContext *ctx)
1028 {
1029 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1030 cpu_gpr[rB(ctx->opcode)]);
1031 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1032 if (unlikely(Rc(ctx->opcode) != 0))
1033 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1034 }
1035
1036 /* mullwo mullwo. */
1037 static void gen_mullwo(DisasContext *ctx)
1038 {
1039 int l1;
1040 TCGv_i64 t0, t1;
1041
1042 t0 = tcg_temp_new_i64();
1043 t1 = tcg_temp_new_i64();
1044 l1 = gen_new_label();
1045 /* Start with XER OV disabled, the most likely case */
1046 tcg_gen_movi_tl(cpu_ov, 0);
1047 #if defined(TARGET_PPC64)
1048 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1049 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1050 #else
1051 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1052 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1053 #endif
1054 tcg_gen_mul_i64(t0, t0, t1);
1055 #if defined(TARGET_PPC64)
1056 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1057 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1058 #else
1059 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1060 tcg_gen_ext32s_i64(t1, t0);
1061 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1062 #endif
1063 tcg_gen_movi_tl(cpu_ov, 1);
1064 tcg_gen_movi_tl(cpu_so, 1);
1065 gen_set_label(l1);
1066 tcg_temp_free_i64(t0);
1067 tcg_temp_free_i64(t1);
1068 if (unlikely(Rc(ctx->opcode) != 0))
1069 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1070 }
1071
1072 /* mulli */
1073 static void gen_mulli(DisasContext *ctx)
1074 {
1075 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1076 SIMM(ctx->opcode));
1077 }
1078
1079 #if defined(TARGET_PPC64)
1080 /* mulhd mulhd. */
1081 static void gen_mulhd(DisasContext *ctx)
1082 {
1083 TCGv lo = tcg_temp_new();
1084 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1085 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1086 tcg_temp_free(lo);
1087 if (unlikely(Rc(ctx->opcode) != 0)) {
1088 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1089 }
1090 }
1091
1092 /* mulhdu mulhdu. */
1093 static void gen_mulhdu(DisasContext *ctx)
1094 {
1095 TCGv lo = tcg_temp_new();
1096 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1097 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1098 tcg_temp_free(lo);
1099 if (unlikely(Rc(ctx->opcode) != 0)) {
1100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1101 }
1102 }
1103
1104 /* mulld mulld. */
1105 static void gen_mulld(DisasContext *ctx)
1106 {
1107 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1108 cpu_gpr[rB(ctx->opcode)]);
1109 if (unlikely(Rc(ctx->opcode) != 0))
1110 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1111 }
1112
1113 /* mulldo mulldo. */
1114 static void gen_mulldo(DisasContext *ctx)
1115 {
1116 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1117 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1118 if (unlikely(Rc(ctx->opcode) != 0)) {
1119 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1120 }
1121 }
1122 #endif
1123
1124 /* Common subf function */
1125 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1126 TCGv arg2, bool add_ca, bool compute_ca,
1127 bool compute_ov, bool compute_rc0)
1128 {
1129 TCGv t0 = ret;
1130
1131 if (((add_ca && compute_ca) || compute_ov)
1132 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
1133 t0 = tcg_temp_new();
1134 }
1135
1136 if (add_ca) {
1137 /* dest = ~arg1 + arg2 + ca = arg2 - arg1 + ca - 1. */
1138 if (compute_ca) {
1139 TCGv zero;
1140 tcg_gen_subi_tl(cpu_ca, cpu_ca, 1);
1141 zero = tcg_const_tl(0);
1142 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1143 tcg_gen_sub2_tl(t0, cpu_ca, t0, cpu_ca, arg1, zero);
1144 tcg_temp_free(zero);
1145 } else {
1146 tcg_gen_sub_tl(t0, arg2, arg1);
1147 tcg_gen_add_tl(t0, t0, cpu_ca);
1148 tcg_gen_subi_tl(t0, t0, 1);
1149 }
1150 } else {
1151 if (compute_ca) {
1152 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1153 }
1154 tcg_gen_sub_tl(t0, arg2, arg1);
1155 }
1156
1157 if (compute_ov) {
1158 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1159 }
1160 if (unlikely(compute_rc0)) {
1161 gen_set_Rc0(ctx, t0);
1162 }
1163
1164 if (!TCGV_EQUAL(t0, ret)) {
1165 tcg_gen_mov_tl(ret, t0);
1166 tcg_temp_free(t0);
1167 }
1168 }
1169 /* Sub functions with Two operands functions */
1170 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1171 static void glue(gen_, name)(DisasContext *ctx) \
1172 { \
1173 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1174 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1175 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1176 }
1177 /* Sub functions with one operand and one immediate */
1178 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1179 add_ca, compute_ca, compute_ov) \
1180 static void glue(gen_, name)(DisasContext *ctx) \
1181 { \
1182 TCGv t0 = tcg_const_tl(const_val); \
1183 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1184 cpu_gpr[rA(ctx->opcode)], t0, \
1185 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1186 tcg_temp_free(t0); \
1187 }
1188 /* subf subf. subfo subfo. */
1189 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1190 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1191 /* subfc subfc. subfco subfco. */
1192 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1193 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1194 /* subfe subfe. subfeo subfo. */
1195 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1196 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1197 /* subfme subfme. subfmeo subfmeo. */
1198 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1199 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1200 /* subfze subfze. subfzeo subfzeo.*/
1201 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1202 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1203
1204 /* subfic */
1205 static void gen_subfic(DisasContext *ctx)
1206 {
1207 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1208 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1209 c, 0, 1, 0, 0);
1210 tcg_temp_free(c);
1211 }
1212
1213 /* neg neg. nego nego. */
1214 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1215 {
1216 TCGv zero = tcg_const_tl(0);
1217 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1218 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1219 tcg_temp_free(zero);
1220 }
1221
1222 static void gen_neg(DisasContext *ctx)
1223 {
1224 gen_op_arith_neg(ctx, 0);
1225 }
1226
1227 static void gen_nego(DisasContext *ctx)
1228 {
1229 gen_op_arith_neg(ctx, 1);
1230 }
1231
1232 /*** Integer logical ***/
1233 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1234 static void glue(gen_, name)(DisasContext *ctx) \
1235 { \
1236 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1237 cpu_gpr[rB(ctx->opcode)]); \
1238 if (unlikely(Rc(ctx->opcode) != 0)) \
1239 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1240 }
1241
1242 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1243 static void glue(gen_, name)(DisasContext *ctx) \
1244 { \
1245 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1246 if (unlikely(Rc(ctx->opcode) != 0)) \
1247 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1248 }
1249
1250 /* and & and. */
1251 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1252 /* andc & andc. */
1253 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1254
1255 /* andi. */
1256 static void gen_andi_(DisasContext *ctx)
1257 {
1258 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1259 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1260 }
1261
1262 /* andis. */
1263 static void gen_andis_(DisasContext *ctx)
1264 {
1265 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1266 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1267 }
1268
1269 /* cntlzw */
1270 static void gen_cntlzw(DisasContext *ctx)
1271 {
1272 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1273 if (unlikely(Rc(ctx->opcode) != 0))
1274 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1275 }
1276 /* eqv & eqv. */
1277 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1278 /* extsb & extsb. */
1279 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1280 /* extsh & extsh. */
1281 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1282 /* nand & nand. */
1283 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1284 /* nor & nor. */
1285 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1286
1287 /* or & or. */
1288 static void gen_or(DisasContext *ctx)
1289 {
1290 int rs, ra, rb;
1291
1292 rs = rS(ctx->opcode);
1293 ra = rA(ctx->opcode);
1294 rb = rB(ctx->opcode);
1295 /* Optimisation for mr. ri case */
1296 if (rs != ra || rs != rb) {
1297 if (rs != rb)
1298 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1299 else
1300 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1301 if (unlikely(Rc(ctx->opcode) != 0))
1302 gen_set_Rc0(ctx, cpu_gpr[ra]);
1303 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1304 gen_set_Rc0(ctx, cpu_gpr[rs]);
1305 #if defined(TARGET_PPC64)
1306 } else {
1307 int prio = 0;
1308
1309 switch (rs) {
1310 case 1:
1311 /* Set process priority to low */
1312 prio = 2;
1313 break;
1314 case 6:
1315 /* Set process priority to medium-low */
1316 prio = 3;
1317 break;
1318 case 2:
1319 /* Set process priority to normal */
1320 prio = 4;
1321 break;
1322 #if !defined(CONFIG_USER_ONLY)
1323 case 31:
1324 if (ctx->mem_idx > 0) {
1325 /* Set process priority to very low */
1326 prio = 1;
1327 }
1328 break;
1329 case 5:
1330 if (ctx->mem_idx > 0) {
1331 /* Set process priority to medium-hight */
1332 prio = 5;
1333 }
1334 break;
1335 case 3:
1336 if (ctx->mem_idx > 0) {
1337 /* Set process priority to high */
1338 prio = 6;
1339 }
1340 break;
1341 case 7:
1342 if (ctx->mem_idx > 1) {
1343 /* Set process priority to very high */
1344 prio = 7;
1345 }
1346 break;
1347 #endif
1348 default:
1349 /* nop */
1350 break;
1351 }
1352 if (prio) {
1353 TCGv t0 = tcg_temp_new();
1354 gen_load_spr(t0, SPR_PPR);
1355 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1356 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1357 gen_store_spr(SPR_PPR, t0);
1358 tcg_temp_free(t0);
1359 }
1360 #endif
1361 }
1362 }
1363 /* orc & orc. */
1364 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1365
1366 /* xor & xor. */
1367 static void gen_xor(DisasContext *ctx)
1368 {
1369 /* Optimisation for "set to zero" case */
1370 if (rS(ctx->opcode) != rB(ctx->opcode))
1371 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1372 else
1373 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1374 if (unlikely(Rc(ctx->opcode) != 0))
1375 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1376 }
1377
1378 /* ori */
1379 static void gen_ori(DisasContext *ctx)
1380 {
1381 target_ulong uimm = UIMM(ctx->opcode);
1382
1383 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1384 /* NOP */
1385 /* XXX: should handle special NOPs for POWER series */
1386 return;
1387 }
1388 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1389 }
1390
1391 /* oris */
1392 static void gen_oris(DisasContext *ctx)
1393 {
1394 target_ulong uimm = UIMM(ctx->opcode);
1395
1396 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1397 /* NOP */
1398 return;
1399 }
1400 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1401 }
1402
1403 /* xori */
1404 static void gen_xori(DisasContext *ctx)
1405 {
1406 target_ulong uimm = UIMM(ctx->opcode);
1407
1408 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1409 /* NOP */
1410 return;
1411 }
1412 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1413 }
1414
1415 /* xoris */
1416 static void gen_xoris(DisasContext *ctx)
1417 {
1418 target_ulong uimm = UIMM(ctx->opcode);
1419
1420 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1421 /* NOP */
1422 return;
1423 }
1424 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1425 }
1426
1427 /* popcntb : PowerPC 2.03 specification */
1428 static void gen_popcntb(DisasContext *ctx)
1429 {
1430 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1431 }
1432
1433 static void gen_popcntw(DisasContext *ctx)
1434 {
1435 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1436 }
1437
1438 #if defined(TARGET_PPC64)
1439 /* popcntd: PowerPC 2.06 specification */
1440 static void gen_popcntd(DisasContext *ctx)
1441 {
1442 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1443 }
1444 #endif
1445
1446 #if defined(TARGET_PPC64)
1447 /* extsw & extsw. */
1448 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1449
1450 /* cntlzd */
1451 static void gen_cntlzd(DisasContext *ctx)
1452 {
1453 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1454 if (unlikely(Rc(ctx->opcode) != 0))
1455 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1456 }
1457 #endif
1458
1459 /*** Integer rotate ***/
1460
1461 /* rlwimi & rlwimi. */
1462 static void gen_rlwimi(DisasContext *ctx)
1463 {
1464 uint32_t mb, me, sh;
1465
1466 mb = MB(ctx->opcode);
1467 me = ME(ctx->opcode);
1468 sh = SH(ctx->opcode);
1469 if (likely(sh == 0 && mb == 0 && me == 31)) {
1470 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1471 } else {
1472 target_ulong mask;
1473 TCGv t1;
1474 TCGv t0 = tcg_temp_new();
1475 #if defined(TARGET_PPC64)
1476 TCGv_i32 t2 = tcg_temp_new_i32();
1477 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1478 tcg_gen_rotli_i32(t2, t2, sh);
1479 tcg_gen_extu_i32_i64(t0, t2);
1480 tcg_temp_free_i32(t2);
1481 #else
1482 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1483 #endif
1484 #if defined(TARGET_PPC64)
1485 mb += 32;
1486 me += 32;
1487 #endif
1488 mask = MASK(mb, me);
1489 t1 = tcg_temp_new();
1490 tcg_gen_andi_tl(t0, t0, mask);
1491 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1492 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1493 tcg_temp_free(t0);
1494 tcg_temp_free(t1);
1495 }
1496 if (unlikely(Rc(ctx->opcode) != 0))
1497 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1498 }
1499
1500 /* rlwinm & rlwinm. */
1501 static void gen_rlwinm(DisasContext *ctx)
1502 {
1503 uint32_t mb, me, sh;
1504
1505 sh = SH(ctx->opcode);
1506 mb = MB(ctx->opcode);
1507 me = ME(ctx->opcode);
1508
1509 if (likely(mb == 0 && me == (31 - sh))) {
1510 if (likely(sh == 0)) {
1511 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1512 } else {
1513 TCGv t0 = tcg_temp_new();
1514 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1515 tcg_gen_shli_tl(t0, t0, sh);
1516 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1517 tcg_temp_free(t0);
1518 }
1519 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1520 TCGv t0 = tcg_temp_new();
1521 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1522 tcg_gen_shri_tl(t0, t0, mb);
1523 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1524 tcg_temp_free(t0);
1525 } else {
1526 TCGv t0 = tcg_temp_new();
1527 #if defined(TARGET_PPC64)
1528 TCGv_i32 t1 = tcg_temp_new_i32();
1529 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1530 tcg_gen_rotli_i32(t1, t1, sh);
1531 tcg_gen_extu_i32_i64(t0, t1);
1532 tcg_temp_free_i32(t1);
1533 #else
1534 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1535 #endif
1536 #if defined(TARGET_PPC64)
1537 mb += 32;
1538 me += 32;
1539 #endif
1540 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1541 tcg_temp_free(t0);
1542 }
1543 if (unlikely(Rc(ctx->opcode) != 0))
1544 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1545 }
1546
1547 /* rlwnm & rlwnm. */
1548 static void gen_rlwnm(DisasContext *ctx)
1549 {
1550 uint32_t mb, me;
1551 TCGv t0;
1552 #if defined(TARGET_PPC64)
1553 TCGv_i32 t1, t2;
1554 #endif
1555
1556 mb = MB(ctx->opcode);
1557 me = ME(ctx->opcode);
1558 t0 = tcg_temp_new();
1559 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1560 #if defined(TARGET_PPC64)
1561 t1 = tcg_temp_new_i32();
1562 t2 = tcg_temp_new_i32();
1563 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1564 tcg_gen_trunc_i64_i32(t2, t0);
1565 tcg_gen_rotl_i32(t1, t1, t2);
1566 tcg_gen_extu_i32_i64(t0, t1);
1567 tcg_temp_free_i32(t1);
1568 tcg_temp_free_i32(t2);
1569 #else
1570 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1571 #endif
1572 if (unlikely(mb != 0 || me != 31)) {
1573 #if defined(TARGET_PPC64)
1574 mb += 32;
1575 me += 32;
1576 #endif
1577 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1578 } else {
1579 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1580 }
1581 tcg_temp_free(t0);
1582 if (unlikely(Rc(ctx->opcode) != 0))
1583 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1584 }
1585
1586 #if defined(TARGET_PPC64)
1587 #define GEN_PPC64_R2(name, opc1, opc2) \
1588 static void glue(gen_, name##0)(DisasContext *ctx) \
1589 { \
1590 gen_##name(ctx, 0); \
1591 } \
1592 \
1593 static void glue(gen_, name##1)(DisasContext *ctx) \
1594 { \
1595 gen_##name(ctx, 1); \
1596 }
1597 #define GEN_PPC64_R4(name, opc1, opc2) \
1598 static void glue(gen_, name##0)(DisasContext *ctx) \
1599 { \
1600 gen_##name(ctx, 0, 0); \
1601 } \
1602 \
1603 static void glue(gen_, name##1)(DisasContext *ctx) \
1604 { \
1605 gen_##name(ctx, 0, 1); \
1606 } \
1607 \
1608 static void glue(gen_, name##2)(DisasContext *ctx) \
1609 { \
1610 gen_##name(ctx, 1, 0); \
1611 } \
1612 \
1613 static void glue(gen_, name##3)(DisasContext *ctx) \
1614 { \
1615 gen_##name(ctx, 1, 1); \
1616 }
1617
1618 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1619 uint32_t sh)
1620 {
1621 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1622 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1623 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1624 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1625 } else {
1626 TCGv t0 = tcg_temp_new();
1627 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1628 if (likely(mb == 0 && me == 63)) {
1629 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1630 } else {
1631 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1632 }
1633 tcg_temp_free(t0);
1634 }
1635 if (unlikely(Rc(ctx->opcode) != 0))
1636 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1637 }
1638 /* rldicl - rldicl. */
1639 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1640 {
1641 uint32_t sh, mb;
1642
1643 sh = SH(ctx->opcode) | (shn << 5);
1644 mb = MB(ctx->opcode) | (mbn << 5);
1645 gen_rldinm(ctx, mb, 63, sh);
1646 }
1647 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1648 /* rldicr - rldicr. */
1649 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1650 {
1651 uint32_t sh, me;
1652
1653 sh = SH(ctx->opcode) | (shn << 5);
1654 me = MB(ctx->opcode) | (men << 5);
1655 gen_rldinm(ctx, 0, me, sh);
1656 }
1657 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1658 /* rldic - rldic. */
1659 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1660 {
1661 uint32_t sh, mb;
1662
1663 sh = SH(ctx->opcode) | (shn << 5);
1664 mb = MB(ctx->opcode) | (mbn << 5);
1665 gen_rldinm(ctx, mb, 63 - sh, sh);
1666 }
1667 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1668
1669 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1670 {
1671 TCGv t0;
1672
1673 mb = MB(ctx->opcode);
1674 me = ME(ctx->opcode);
1675 t0 = tcg_temp_new();
1676 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1677 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1678 if (unlikely(mb != 0 || me != 63)) {
1679 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1680 } else {
1681 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1682 }
1683 tcg_temp_free(t0);
1684 if (unlikely(Rc(ctx->opcode) != 0))
1685 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1686 }
1687
1688 /* rldcl - rldcl. */
1689 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1690 {
1691 uint32_t mb;
1692
1693 mb = MB(ctx->opcode) | (mbn << 5);
1694 gen_rldnm(ctx, mb, 63);
1695 }
1696 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1697 /* rldcr - rldcr. */
1698 static inline void gen_rldcr(DisasContext *ctx, int men)
1699 {
1700 uint32_t me;
1701
1702 me = MB(ctx->opcode) | (men << 5);
1703 gen_rldnm(ctx, 0, me);
1704 }
1705 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1706 /* rldimi - rldimi. */
1707 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1708 {
1709 uint32_t sh, mb, me;
1710
1711 sh = SH(ctx->opcode) | (shn << 5);
1712 mb = MB(ctx->opcode) | (mbn << 5);
1713 me = 63 - sh;
1714 if (unlikely(sh == 0 && mb == 0)) {
1715 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1716 } else {
1717 TCGv t0, t1;
1718 target_ulong mask;
1719
1720 t0 = tcg_temp_new();
1721 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1722 t1 = tcg_temp_new();
1723 mask = MASK(mb, me);
1724 tcg_gen_andi_tl(t0, t0, mask);
1725 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1726 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1727 tcg_temp_free(t0);
1728 tcg_temp_free(t1);
1729 }
1730 if (unlikely(Rc(ctx->opcode) != 0))
1731 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1732 }
1733 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1734 #endif
1735
1736 /*** Integer shift ***/
1737
1738 /* slw & slw. */
1739 static void gen_slw(DisasContext *ctx)
1740 {
1741 TCGv t0, t1;
1742
1743 t0 = tcg_temp_new();
1744 /* AND rS with a mask that is 0 when rB >= 0x20 */
1745 #if defined(TARGET_PPC64)
1746 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1747 tcg_gen_sari_tl(t0, t0, 0x3f);
1748 #else
1749 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1750 tcg_gen_sari_tl(t0, t0, 0x1f);
1751 #endif
1752 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1753 t1 = tcg_temp_new();
1754 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1755 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1756 tcg_temp_free(t1);
1757 tcg_temp_free(t0);
1758 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1759 if (unlikely(Rc(ctx->opcode) != 0))
1760 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1761 }
1762
1763 /* sraw & sraw. */
1764 static void gen_sraw(DisasContext *ctx)
1765 {
1766 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1767 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1768 if (unlikely(Rc(ctx->opcode) != 0))
1769 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1770 }
1771
1772 /* srawi & srawi. */
1773 static void gen_srawi(DisasContext *ctx)
1774 {
1775 int sh = SH(ctx->opcode);
1776 if (sh != 0) {
1777 int l1, l2;
1778 TCGv t0;
1779 l1 = gen_new_label();
1780 l2 = gen_new_label();
1781 t0 = tcg_temp_local_new();
1782 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1783 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1784 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1785 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1786 tcg_gen_movi_tl(cpu_ca, 1);
1787 tcg_gen_br(l2);
1788 gen_set_label(l1);
1789 tcg_gen_movi_tl(cpu_ca, 0);
1790 gen_set_label(l2);
1791 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1792 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1793 tcg_temp_free(t0);
1794 } else {
1795 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1796 tcg_gen_movi_tl(cpu_ca, 0);
1797 }
1798 if (unlikely(Rc(ctx->opcode) != 0))
1799 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1800 }
1801
1802 /* srw & srw. */
1803 static void gen_srw(DisasContext *ctx)
1804 {
1805 TCGv t0, t1;
1806
1807 t0 = tcg_temp_new();
1808 /* AND rS with a mask that is 0 when rB >= 0x20 */
1809 #if defined(TARGET_PPC64)
1810 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1811 tcg_gen_sari_tl(t0, t0, 0x3f);
1812 #else
1813 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1814 tcg_gen_sari_tl(t0, t0, 0x1f);
1815 #endif
1816 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1817 tcg_gen_ext32u_tl(t0, t0);
1818 t1 = tcg_temp_new();
1819 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1820 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1821 tcg_temp_free(t1);
1822 tcg_temp_free(t0);
1823 if (unlikely(Rc(ctx->opcode) != 0))
1824 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1825 }
1826
1827 #if defined(TARGET_PPC64)
1828 /* sld & sld. */
1829 static void gen_sld(DisasContext *ctx)
1830 {
1831 TCGv t0, t1;
1832
1833 t0 = tcg_temp_new();
1834 /* AND rS with a mask that is 0 when rB >= 0x40 */
1835 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1836 tcg_gen_sari_tl(t0, t0, 0x3f);
1837 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1838 t1 = tcg_temp_new();
1839 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1840 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1841 tcg_temp_free(t1);
1842 tcg_temp_free(t0);
1843 if (unlikely(Rc(ctx->opcode) != 0))
1844 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1845 }
1846
1847 /* srad & srad. */
1848 static void gen_srad(DisasContext *ctx)
1849 {
1850 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1851 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1852 if (unlikely(Rc(ctx->opcode) != 0))
1853 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1854 }
1855 /* sradi & sradi. */
1856 static inline void gen_sradi(DisasContext *ctx, int n)
1857 {
1858 int sh = SH(ctx->opcode) + (n << 5);
1859 if (sh != 0) {
1860 int l1, l2;
1861 TCGv t0;
1862 l1 = gen_new_label();
1863 l2 = gen_new_label();
1864 t0 = tcg_temp_local_new();
1865 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1866 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1867 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1868 tcg_gen_movi_tl(cpu_ca, 1);
1869 tcg_gen_br(l2);
1870 gen_set_label(l1);
1871 tcg_gen_movi_tl(cpu_ca, 0);
1872 gen_set_label(l2);
1873 tcg_temp_free(t0);
1874 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1875 } else {
1876 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1877 tcg_gen_movi_tl(cpu_ca, 0);
1878 }
1879 if (unlikely(Rc(ctx->opcode) != 0))
1880 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1881 }
1882
1883 static void gen_sradi0(DisasContext *ctx)
1884 {
1885 gen_sradi(ctx, 0);
1886 }
1887
1888 static void gen_sradi1(DisasContext *ctx)
1889 {
1890 gen_sradi(ctx, 1);
1891 }
1892
1893 /* srd & srd. */
1894 static void gen_srd(DisasContext *ctx)
1895 {
1896 TCGv t0, t1;
1897
1898 t0 = tcg_temp_new();
1899 /* AND rS with a mask that is 0 when rB >= 0x40 */
1900 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1901 tcg_gen_sari_tl(t0, t0, 0x3f);
1902 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1903 t1 = tcg_temp_new();
1904 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1905 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1906 tcg_temp_free(t1);
1907 tcg_temp_free(t0);
1908 if (unlikely(Rc(ctx->opcode) != 0))
1909 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1910 }
1911 #endif
1912
1913 /*** Floating-Point arithmetic ***/
1914 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1915 static void gen_f##name(DisasContext *ctx) \
1916 { \
1917 if (unlikely(!ctx->fpu_enabled)) { \
1918 gen_exception(ctx, POWERPC_EXCP_FPU); \
1919 return; \
1920 } \
1921 /* NIP cannot be restored if the memory exception comes from an helper */ \
1922 gen_update_nip(ctx, ctx->nip - 4); \
1923 gen_reset_fpstatus(); \
1924 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1925 cpu_fpr[rA(ctx->opcode)], \
1926 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1927 if (isfloat) { \
1928 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1929 cpu_fpr[rD(ctx->opcode)]); \
1930 } \
1931 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1932 Rc(ctx->opcode) != 0); \
1933 }
1934
1935 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1936 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1937 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1938
1939 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1940 static void gen_f##name(DisasContext *ctx) \
1941 { \
1942 if (unlikely(!ctx->fpu_enabled)) { \
1943 gen_exception(ctx, POWERPC_EXCP_FPU); \
1944 return; \
1945 } \
1946 /* NIP cannot be restored if the memory exception comes from an helper */ \
1947 gen_update_nip(ctx, ctx->nip - 4); \
1948 gen_reset_fpstatus(); \
1949 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1950 cpu_fpr[rA(ctx->opcode)], \
1951 cpu_fpr[rB(ctx->opcode)]); \
1952 if (isfloat) { \
1953 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1954 cpu_fpr[rD(ctx->opcode)]); \
1955 } \
1956 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1957 set_fprf, Rc(ctx->opcode) != 0); \
1958 }
1959 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1960 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1961 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1962
1963 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1964 static void gen_f##name(DisasContext *ctx) \
1965 { \
1966 if (unlikely(!ctx->fpu_enabled)) { \
1967 gen_exception(ctx, POWERPC_EXCP_FPU); \
1968 return; \
1969 } \
1970 /* NIP cannot be restored if the memory exception comes from an helper */ \
1971 gen_update_nip(ctx, ctx->nip - 4); \
1972 gen_reset_fpstatus(); \
1973 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1974 cpu_fpr[rA(ctx->opcode)], \
1975 cpu_fpr[rC(ctx->opcode)]); \
1976 if (isfloat) { \
1977 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1978 cpu_fpr[rD(ctx->opcode)]); \
1979 } \
1980 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1981 set_fprf, Rc(ctx->opcode) != 0); \
1982 }
1983 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1984 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1985 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1986
1987 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1988 static void gen_f##name(DisasContext *ctx) \
1989 { \
1990 if (unlikely(!ctx->fpu_enabled)) { \
1991 gen_exception(ctx, POWERPC_EXCP_FPU); \
1992 return; \
1993 } \
1994 /* NIP cannot be restored if the memory exception comes from an helper */ \
1995 gen_update_nip(ctx, ctx->nip - 4); \
1996 gen_reset_fpstatus(); \
1997 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1998 cpu_fpr[rB(ctx->opcode)]); \
1999 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2000 set_fprf, Rc(ctx->opcode) != 0); \
2001 }
2002
2003 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2004 static void gen_f##name(DisasContext *ctx) \
2005 { \
2006 if (unlikely(!ctx->fpu_enabled)) { \
2007 gen_exception(ctx, POWERPC_EXCP_FPU); \
2008 return; \
2009 } \
2010 /* NIP cannot be restored if the memory exception comes from an helper */ \
2011 gen_update_nip(ctx, ctx->nip - 4); \
2012 gen_reset_fpstatus(); \
2013 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2014 cpu_fpr[rB(ctx->opcode)]); \
2015 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2016 set_fprf, Rc(ctx->opcode) != 0); \
2017 }
2018
2019 /* fadd - fadds */
2020 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2021 /* fdiv - fdivs */
2022 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2023 /* fmul - fmuls */
2024 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2025
2026 /* fre */
2027 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2028
2029 /* fres */
2030 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2031
2032 /* frsqrte */
2033 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2034
2035 /* frsqrtes */
2036 static void gen_frsqrtes(DisasContext *ctx)
2037 {
2038 if (unlikely(!ctx->fpu_enabled)) {
2039 gen_exception(ctx, POWERPC_EXCP_FPU);
2040 return;
2041 }
2042 /* NIP cannot be restored if the memory exception comes from an helper */
2043 gen_update_nip(ctx, ctx->nip - 4);
2044 gen_reset_fpstatus();
2045 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2046 cpu_fpr[rB(ctx->opcode)]);
2047 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2048 cpu_fpr[rD(ctx->opcode)]);
2049 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2050 }
2051
2052 /* fsel */
2053 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2054 /* fsub - fsubs */
2055 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2056 /* Optional: */
2057
2058 /* fsqrt */
2059 static void gen_fsqrt(DisasContext *ctx)
2060 {
2061 if (unlikely(!ctx->fpu_enabled)) {
2062 gen_exception(ctx, POWERPC_EXCP_FPU);
2063 return;
2064 }
2065 /* NIP cannot be restored if the memory exception comes from an helper */
2066 gen_update_nip(ctx, ctx->nip - 4);
2067 gen_reset_fpstatus();
2068 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2069 cpu_fpr[rB(ctx->opcode)]);
2070 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2071 }
2072
2073 static void gen_fsqrts(DisasContext *ctx)
2074 {
2075 if (unlikely(!ctx->fpu_enabled)) {
2076 gen_exception(ctx, POWERPC_EXCP_FPU);
2077 return;
2078 }
2079 /* NIP cannot be restored if the memory exception comes from an helper */
2080 gen_update_nip(ctx, ctx->nip - 4);
2081 gen_reset_fpstatus();
2082 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2083 cpu_fpr[rB(ctx->opcode)]);
2084 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2085 cpu_fpr[rD(ctx->opcode)]);
2086 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2087 }
2088
2089 /*** Floating-Point multiply-and-add ***/
2090 /* fmadd - fmadds */
2091 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2092 /* fmsub - fmsubs */
2093 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2094 /* fnmadd - fnmadds */
2095 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2096 /* fnmsub - fnmsubs */
2097 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2098
2099 /*** Floating-Point round & convert ***/
2100 /* fctiw */
2101 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2102 /* fctiwz */
2103 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2104 /* frsp */
2105 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2106 #if defined(TARGET_PPC64)
2107 /* fcfid */
2108 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2109 /* fctid */
2110 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2111 /* fctidz */
2112 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2113 #endif
2114
2115 /* frin */
2116 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2117 /* friz */
2118 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2119 /* frip */
2120 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2121 /* frim */
2122 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2123
2124 /*** Floating-Point compare ***/
2125
2126 /* fcmpo */
2127 static void gen_fcmpo(DisasContext *ctx)
2128 {
2129 TCGv_i32 crf;
2130 if (unlikely(!ctx->fpu_enabled)) {
2131 gen_exception(ctx, POWERPC_EXCP_FPU);
2132 return;
2133 }
2134 /* NIP cannot be restored if the memory exception comes from an helper */
2135 gen_update_nip(ctx, ctx->nip - 4);
2136 gen_reset_fpstatus();
2137 crf = tcg_const_i32(crfD(ctx->opcode));
2138 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2139 cpu_fpr[rB(ctx->opcode)], crf);
2140 tcg_temp_free_i32(crf);
2141 gen_helper_float_check_status(cpu_env);
2142 }
2143
2144 /* fcmpu */
2145 static void gen_fcmpu(DisasContext *ctx)
2146 {
2147 TCGv_i32 crf;
2148 if (unlikely(!ctx->fpu_enabled)) {
2149 gen_exception(ctx, POWERPC_EXCP_FPU);
2150 return;
2151 }
2152 /* NIP cannot be restored if the memory exception comes from an helper */
2153 gen_update_nip(ctx, ctx->nip - 4);
2154 gen_reset_fpstatus();
2155 crf = tcg_const_i32(crfD(ctx->opcode));
2156 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2157 cpu_fpr[rB(ctx->opcode)], crf);
2158 tcg_temp_free_i32(crf);
2159 gen_helper_float_check_status(cpu_env);
2160 }
2161
2162 /*** Floating-point move ***/
2163 /* fabs */
2164 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2165 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2166
2167 /* fmr - fmr. */
2168 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2169 static void gen_fmr(DisasContext *ctx)
2170 {
2171 if (unlikely(!ctx->fpu_enabled)) {
2172 gen_exception(ctx, POWERPC_EXCP_FPU);
2173 return;
2174 }
2175 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2176 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2177 }
2178
2179 /* fnabs */
2180 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2181 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2182 /* fneg */
2183 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2184 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2185
2186 /*** Floating-Point status & ctrl register ***/
2187
2188 /* mcrfs */
2189 static void gen_mcrfs(DisasContext *ctx)
2190 {
2191 TCGv tmp = tcg_temp_new();
2192 int bfa;
2193
2194 if (unlikely(!ctx->fpu_enabled)) {
2195 gen_exception(ctx, POWERPC_EXCP_FPU);
2196 return;
2197 }
2198 bfa = 4 * (7 - crfS(ctx->opcode));
2199 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2200 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2201 tcg_temp_free(tmp);
2202 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2203 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2204 }
2205
2206 /* mffs */
2207 static void gen_mffs(DisasContext *ctx)
2208 {
2209 if (unlikely(!ctx->fpu_enabled)) {
2210 gen_exception(ctx, POWERPC_EXCP_FPU);
2211 return;
2212 }
2213 gen_reset_fpstatus();
2214 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2215 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2216 }
2217
2218 /* mtfsb0 */
2219 static void gen_mtfsb0(DisasContext *ctx)
2220 {
2221 uint8_t crb;
2222
2223 if (unlikely(!ctx->fpu_enabled)) {
2224 gen_exception(ctx, POWERPC_EXCP_FPU);
2225 return;
2226 }
2227 crb = 31 - crbD(ctx->opcode);
2228 gen_reset_fpstatus();
2229 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2230 TCGv_i32 t0;
2231 /* NIP cannot be restored if the memory exception comes from an helper */
2232 gen_update_nip(ctx, ctx->nip - 4);
2233 t0 = tcg_const_i32(crb);
2234 gen_helper_fpscr_clrbit(cpu_env, t0);
2235 tcg_temp_free_i32(t0);
2236 }
2237 if (unlikely(Rc(ctx->opcode) != 0)) {
2238 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2239 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2240 }
2241 }
2242
2243 /* mtfsb1 */
2244 static void gen_mtfsb1(DisasContext *ctx)
2245 {
2246 uint8_t crb;
2247
2248 if (unlikely(!ctx->fpu_enabled)) {
2249 gen_exception(ctx, POWERPC_EXCP_FPU);
2250 return;
2251 }
2252 crb = 31 - crbD(ctx->opcode);
2253 gen_reset_fpstatus();
2254 /* XXX: we pretend we can only do IEEE floating-point computations */
2255 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2256 TCGv_i32 t0;
2257 /* NIP cannot be restored if the memory exception comes from an helper */
2258 gen_update_nip(ctx, ctx->nip - 4);
2259 t0 = tcg_const_i32(crb);
2260 gen_helper_fpscr_setbit(cpu_env, t0);
2261 tcg_temp_free_i32(t0);
2262 }
2263 if (unlikely(Rc(ctx->opcode) != 0)) {
2264 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2265 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2266 }
2267 /* We can raise a differed exception */
2268 gen_helper_float_check_status(cpu_env);
2269 }
2270
2271 /* mtfsf */
2272 static void gen_mtfsf(DisasContext *ctx)
2273 {
2274 TCGv_i32 t0;
2275 int L = ctx->opcode & 0x02000000;
2276
2277 if (unlikely(!ctx->fpu_enabled)) {
2278 gen_exception(ctx, POWERPC_EXCP_FPU);
2279 return;
2280 }
2281 /* NIP cannot be restored if the memory exception comes from an helper */
2282 gen_update_nip(ctx, ctx->nip - 4);
2283 gen_reset_fpstatus();
2284 if (L)
2285 t0 = tcg_const_i32(0xff);
2286 else
2287 t0 = tcg_const_i32(FM(ctx->opcode));
2288 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2289 tcg_temp_free_i32(t0);
2290 if (unlikely(Rc(ctx->opcode) != 0)) {
2291 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2292 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2293 }
2294 /* We can raise a differed exception */
2295 gen_helper_float_check_status(cpu_env);
2296 }
2297
2298 /* mtfsfi */
2299 static void gen_mtfsfi(DisasContext *ctx)
2300 {
2301 int bf, sh;
2302 TCGv_i64 t0;
2303 TCGv_i32 t1;
2304
2305 if (unlikely(!ctx->fpu_enabled)) {
2306 gen_exception(ctx, POWERPC_EXCP_FPU);
2307 return;
2308 }
2309 bf = crbD(ctx->opcode) >> 2;
2310 sh = 7 - bf;
2311 /* NIP cannot be restored if the memory exception comes from an helper */
2312 gen_update_nip(ctx, ctx->nip - 4);
2313 gen_reset_fpstatus();
2314 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2315 t1 = tcg_const_i32(1 << sh);
2316 gen_helper_store_fpscr(cpu_env, t0, t1);
2317 tcg_temp_free_i64(t0);
2318 tcg_temp_free_i32(t1);
2319 if (unlikely(Rc(ctx->opcode) != 0)) {
2320 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2321 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2322 }
2323 /* We can raise a differed exception */
2324 gen_helper_float_check_status(cpu_env);
2325 }
2326
2327 /*** Addressing modes ***/
2328 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2329 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2330 target_long maskl)
2331 {
2332 target_long simm = SIMM(ctx->opcode);
2333
2334 simm &= ~maskl;
2335 if (rA(ctx->opcode) == 0) {
2336 #if defined(TARGET_PPC64)
2337 if (!ctx->sf_mode) {
2338 tcg_gen_movi_tl(EA, (uint32_t)simm);
2339 } else
2340 #endif
2341 tcg_gen_movi_tl(EA, simm);
2342 } else if (likely(simm != 0)) {
2343 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2344 #if defined(TARGET_PPC64)
2345 if (!ctx->sf_mode) {
2346 tcg_gen_ext32u_tl(EA, EA);
2347 }
2348 #endif
2349 } else {
2350 #if defined(TARGET_PPC64)
2351 if (!ctx->sf_mode) {
2352 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2353 } else
2354 #endif
2355 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2356 }
2357 }
2358
2359 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2360 {
2361 if (rA(ctx->opcode) == 0) {
2362 #if defined(TARGET_PPC64)
2363 if (!ctx->sf_mode) {
2364 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2365 } else
2366 #endif
2367 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2368 } else {
2369 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2370 #if defined(TARGET_PPC64)
2371 if (!ctx->sf_mode) {
2372 tcg_gen_ext32u_tl(EA, EA);
2373 }
2374 #endif
2375 }
2376 }
2377
2378 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2379 {
2380 if (rA(ctx->opcode) == 0) {
2381 tcg_gen_movi_tl(EA, 0);
2382 } else {
2383 #if defined(TARGET_PPC64)
2384 if (!ctx->sf_mode) {
2385 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2386 } else
2387 #endif
2388 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2389 }
2390 }
2391
2392 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2393 target_long val)
2394 {
2395 tcg_gen_addi_tl(ret, arg1, val);
2396 #if defined(TARGET_PPC64)
2397 if (!ctx->sf_mode) {
2398 tcg_gen_ext32u_tl(ret, ret);
2399 }
2400 #endif
2401 }
2402
2403 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2404 {
2405 int l1 = gen_new_label();
2406 TCGv t0 = tcg_temp_new();
2407 TCGv_i32 t1, t2;
2408 /* NIP cannot be restored if the memory exception comes from an helper */
2409 gen_update_nip(ctx, ctx->nip - 4);
2410 tcg_gen_andi_tl(t0, EA, mask);
2411 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2412 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2413 t2 = tcg_const_i32(0);
2414 gen_helper_raise_exception_err(cpu_env, t1, t2);
2415 tcg_temp_free_i32(t1);
2416 tcg_temp_free_i32(t2);
2417 gen_set_label(l1);
2418 tcg_temp_free(t0);
2419 }
2420
2421 /*** Integer load ***/
2422 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2423 {
2424 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2425 }
2426
2427 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2428 {
2429 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2430 }
2431
2432 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2433 {
2434 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2435 if (unlikely(ctx->le_mode)) {
2436 tcg_gen_bswap16_tl(arg1, arg1);
2437 }
2438 }
2439
2440 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2441 {
2442 if (unlikely(ctx->le_mode)) {
2443 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2444 tcg_gen_bswap16_tl(arg1, arg1);
2445 tcg_gen_ext16s_tl(arg1, arg1);
2446 } else {
2447 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2448 }
2449 }
2450
2451 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2452 {
2453 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2454 if (unlikely(ctx->le_mode)) {
2455 tcg_gen_bswap32_tl(arg1, arg1);
2456 }
2457 }
2458
2459 #if defined(TARGET_PPC64)
2460 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2461 {
2462 if (unlikely(ctx->le_mode)) {
2463 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2464 tcg_gen_bswap32_tl(arg1, arg1);
2465 tcg_gen_ext32s_tl(arg1, arg1);
2466 } else
2467 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2468 }
2469 #endif
2470
2471 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2472 {
2473 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2474 if (unlikely(ctx->le_mode)) {
2475 tcg_gen_bswap64_i64(arg1, arg1);
2476 }
2477 }
2478
2479 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2480 {
2481 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2482 }
2483
2484 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2485 {
2486 if (unlikely(ctx->le_mode)) {
2487 TCGv t0 = tcg_temp_new();
2488 tcg_gen_ext16u_tl(t0, arg1);
2489 tcg_gen_bswap16_tl(t0, t0);
2490 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2491 tcg_temp_free(t0);
2492 } else {
2493 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2494 }
2495 }
2496
2497 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2498 {
2499 if (unlikely(ctx->le_mode)) {
2500 TCGv t0 = tcg_temp_new();
2501 tcg_gen_ext32u_tl(t0, arg1);
2502 tcg_gen_bswap32_tl(t0, t0);
2503 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2504 tcg_temp_free(t0);
2505 } else {
2506 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2507 }
2508 }
2509
2510 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2511 {
2512 if (unlikely(ctx->le_mode)) {
2513 TCGv_i64 t0 = tcg_temp_new_i64();
2514 tcg_gen_bswap64_i64(t0, arg1);
2515 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2516 tcg_temp_free_i64(t0);
2517 } else
2518 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2519 }
2520
2521 #define GEN_LD(name, ldop, opc, type) \
2522 static void glue(gen_, name)(DisasContext *ctx) \
2523 { \
2524 TCGv EA; \
2525 gen_set_access_type(ctx, ACCESS_INT); \
2526 EA = tcg_temp_new(); \
2527 gen_addr_imm_index(ctx, EA, 0); \
2528 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2529 tcg_temp_free(EA); \
2530 }
2531
2532 #define GEN_LDU(name, ldop, opc, type) \
2533 static void glue(gen_, name##u)(DisasContext *ctx) \
2534 { \
2535 TCGv EA; \
2536 if (unlikely(rA(ctx->opcode) == 0 || \
2537 rA(ctx->opcode) == rD(ctx->opcode))) { \
2538 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2539 return; \
2540 } \
2541 gen_set_access_type(ctx, ACCESS_INT); \
2542 EA = tcg_temp_new(); \
2543 if (type == PPC_64B) \
2544 gen_addr_imm_index(ctx, EA, 0x03); \
2545 else \
2546 gen_addr_imm_index(ctx, EA, 0); \
2547 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2548 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2549 tcg_temp_free(EA); \
2550 }
2551
2552 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2553 static void glue(gen_, name##ux)(DisasContext *ctx) \
2554 { \
2555 TCGv EA; \
2556 if (unlikely(rA(ctx->opcode) == 0 || \
2557 rA(ctx->opcode) == rD(ctx->opcode))) { \
2558 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2559 return; \
2560 } \
2561 gen_set_access_type(ctx, ACCESS_INT); \
2562 EA = tcg_temp_new(); \
2563 gen_addr_reg_index(ctx, EA); \
2564 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2565 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2566 tcg_temp_free(EA); \
2567 }
2568
2569 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2570 static void glue(gen_, name##x)(DisasContext *ctx) \
2571 { \
2572 TCGv EA; \
2573 gen_set_access_type(ctx, ACCESS_INT); \
2574 EA = tcg_temp_new(); \
2575 gen_addr_reg_index(ctx, EA); \
2576 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2577 tcg_temp_free(EA); \
2578 }
2579 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2580 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2581
2582 #define GEN_LDS(name, ldop, op, type) \
2583 GEN_LD(name, ldop, op | 0x20, type); \
2584 GEN_LDU(name, ldop, op | 0x21, type); \
2585 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2586 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2587
2588 /* lbz lbzu lbzux lbzx */
2589 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2590 /* lha lhau lhaux lhax */
2591 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2592 /* lhz lhzu lhzux lhzx */
2593 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2594 /* lwz lwzu lwzux lwzx */
2595 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2596 #if defined(TARGET_PPC64)
2597 /* lwaux */
2598 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2599 /* lwax */
2600 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2601 /* ldux */
2602 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2603 /* ldx */
2604 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2605
2606 static void gen_ld(DisasContext *ctx)
2607 {
2608 TCGv EA;
2609 if (Rc(ctx->opcode)) {
2610 if (unlikely(rA(ctx->opcode) == 0 ||
2611 rA(ctx->opcode) == rD(ctx->opcode))) {
2612 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2613 return;
2614 }
2615 }
2616 gen_set_access_type(ctx, ACCESS_INT);
2617 EA = tcg_temp_new();
2618 gen_addr_imm_index(ctx, EA, 0x03);
2619 if (ctx->opcode & 0x02) {
2620 /* lwa (lwau is undefined) */
2621 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2622 } else {
2623 /* ld - ldu */
2624 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2625 }
2626 if (Rc(ctx->opcode))
2627 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2628 tcg_temp_free(EA);
2629 }
2630
2631 /* lq */
2632 static void gen_lq(DisasContext *ctx)
2633 {
2634 #if defined(CONFIG_USER_ONLY)
2635 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2636 #else
2637 int ra, rd;
2638 TCGv EA;
2639
2640 /* Restore CPU state */
2641 if (unlikely(ctx->mem_idx == 0)) {
2642 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2643 return;
2644 }
2645 ra = rA(ctx->opcode);
2646 rd = rD(ctx->opcode);
2647 if (unlikely((rd & 1) || rd == ra)) {
2648 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2649 return;
2650 }
2651 if (unlikely(ctx->le_mode)) {
2652 /* Little-endian mode is not handled */
2653 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2654 return;
2655 }
2656 gen_set_access_type(ctx, ACCESS_INT);
2657 EA = tcg_temp_new();
2658 gen_addr_imm_index(ctx, EA, 0x0F);
2659 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2660 gen_addr_add(ctx, EA, EA, 8);
2661 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2662 tcg_temp_free(EA);
2663 #endif
2664 }
2665 #endif
2666
2667 /*** Integer store ***/
2668 #define GEN_ST(name, stop, opc, type) \
2669 static void glue(gen_, name)(DisasContext *ctx) \
2670 { \
2671 TCGv EA; \
2672 gen_set_access_type(ctx, ACCESS_INT); \
2673 EA = tcg_temp_new(); \
2674 gen_addr_imm_index(ctx, EA, 0); \
2675 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2676 tcg_temp_free(EA); \
2677 }
2678
2679 #define GEN_STU(name, stop, opc, type) \
2680 static void glue(gen_, stop##u)(DisasContext *ctx) \
2681 { \
2682 TCGv EA; \
2683 if (unlikely(rA(ctx->opcode) == 0)) { \
2684 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2685 return; \
2686 } \
2687 gen_set_access_type(ctx, ACCESS_INT); \
2688 EA = tcg_temp_new(); \
2689 if (type == PPC_64B) \
2690 gen_addr_imm_index(ctx, EA, 0x03); \
2691 else \
2692 gen_addr_imm_index(ctx, EA, 0); \
2693 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2694 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2695 tcg_temp_free(EA); \
2696 }
2697
2698 #define GEN_STUX(name, stop, opc2, opc3, type) \
2699 static void glue(gen_, name##ux)(DisasContext *ctx) \
2700 { \
2701 TCGv EA; \
2702 if (unlikely(rA(ctx->opcode) == 0)) { \
2703 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2704 return; \
2705 } \
2706 gen_set_access_type(ctx, ACCESS_INT); \
2707 EA = tcg_temp_new(); \
2708 gen_addr_reg_index(ctx, EA); \
2709 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2710 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2711 tcg_temp_free(EA); \
2712 }
2713
2714 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2715 static void glue(gen_, name##x)(DisasContext *ctx) \
2716 { \
2717 TCGv EA; \
2718 gen_set_access_type(ctx, ACCESS_INT); \
2719 EA = tcg_temp_new(); \
2720 gen_addr_reg_index(ctx, EA); \
2721 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2722 tcg_temp_free(EA); \
2723 }
2724 #define GEN_STX(name, stop, opc2, opc3, type) \
2725 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2726
2727 #define GEN_STS(name, stop, op, type) \
2728 GEN_ST(name, stop, op | 0x20, type); \
2729 GEN_STU(name, stop, op | 0x21, type); \
2730 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2731 GEN_STX(name, stop, 0x17, op | 0x00, type)
2732
2733 /* stb stbu stbux stbx */
2734 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2735 /* sth sthu sthux sthx */
2736 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2737 /* stw stwu stwux stwx */
2738 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2739 #if defined(TARGET_PPC64)
2740 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2741 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2742
2743 static void gen_std(DisasContext *ctx)
2744 {
2745 int rs;
2746 TCGv EA;
2747
2748 rs = rS(ctx->opcode);
2749 if ((ctx->opcode & 0x3) == 0x2) {
2750 #if defined(CONFIG_USER_ONLY)
2751 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2752 #else
2753 /* stq */
2754 if (unlikely(ctx->mem_idx == 0)) {
2755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2756 return;
2757 }
2758 if (unlikely(rs & 1)) {
2759 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2760 return;
2761 }
2762 if (unlikely(ctx->le_mode)) {
2763 /* Little-endian mode is not handled */
2764 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2765 return;
2766 }
2767 gen_set_access_type(ctx, ACCESS_INT);
2768 EA = tcg_temp_new();
2769 gen_addr_imm_index(ctx, EA, 0x03);
2770 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2771 gen_addr_add(ctx, EA, EA, 8);
2772 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2773 tcg_temp_free(EA);
2774 #endif
2775 } else {
2776 /* std / stdu */
2777 if (Rc(ctx->opcode)) {
2778 if (unlikely(rA(ctx->opcode) == 0)) {
2779 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2780 return;
2781 }
2782 }
2783 gen_set_access_type(ctx, ACCESS_INT);
2784 EA = tcg_temp_new();
2785 gen_addr_imm_index(ctx, EA, 0x03);
2786 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2787 if (Rc(ctx->opcode))
2788 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2789 tcg_temp_free(EA);
2790 }
2791 }
2792 #endif
2793 /*** Integer load and store with byte reverse ***/
2794 /* lhbrx */
2795 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2796 {
2797 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2798 if (likely(!ctx->le_mode)) {
2799 tcg_gen_bswap16_tl(arg1, arg1);
2800 }
2801 }
2802 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2803
2804 /* lwbrx */
2805 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2806 {
2807 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2808 if (likely(!ctx->le_mode)) {
2809 tcg_gen_bswap32_tl(arg1, arg1);
2810 }
2811 }
2812 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2813
2814 #if defined(TARGET_PPC64)
2815 /* ldbrx */
2816 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2817 {
2818 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2819 if (likely(!ctx->le_mode)) {
2820 tcg_gen_bswap64_tl(arg1, arg1);
2821 }
2822 }
2823 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2824 #endif /* TARGET_PPC64 */
2825
2826 /* sthbrx */
2827 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2828 {
2829 if (likely(!ctx->le_mode)) {
2830 TCGv t0 = tcg_temp_new();
2831 tcg_gen_ext16u_tl(t0, arg1);
2832 tcg_gen_bswap16_tl(t0, t0);
2833 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2834 tcg_temp_free(t0);
2835 } else {
2836 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2837 }
2838 }
2839 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2840
2841 /* stwbrx */
2842 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2843 {
2844 if (likely(!ctx->le_mode)) {
2845 TCGv t0 = tcg_temp_new();
2846 tcg_gen_ext32u_tl(t0, arg1);
2847 tcg_gen_bswap32_tl(t0, t0);
2848 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2849 tcg_temp_free(t0);
2850 } else {
2851 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2852 }
2853 }
2854 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2855
2856 #if defined(TARGET_PPC64)
2857 /* stdbrx */
2858 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2859 {
2860 if (likely(!ctx->le_mode)) {
2861 TCGv t0 = tcg_temp_new();
2862 tcg_gen_bswap64_tl(t0, arg1);
2863 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2864 tcg_temp_free(t0);
2865 } else {
2866 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2867 }
2868 }
2869 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2870 #endif /* TARGET_PPC64 */
2871
2872 /*** Integer load and store multiple ***/
2873
2874 /* lmw */
2875 static void gen_lmw(DisasContext *ctx)
2876 {
2877 TCGv t0;
2878 TCGv_i32 t1;
2879 gen_set_access_type(ctx, ACCESS_INT);
2880 /* NIP cannot be restored if the memory exception comes from an helper */
2881 gen_update_nip(ctx, ctx->nip - 4);
2882 t0 = tcg_temp_new();
2883 t1 = tcg_const_i32(rD(ctx->opcode));
2884 gen_addr_imm_index(ctx, t0, 0);
2885 gen_helper_lmw(cpu_env, t0, t1);
2886 tcg_temp_free(t0);
2887 tcg_temp_free_i32(t1);
2888 }
2889
2890 /* stmw */
2891 static void gen_stmw(DisasContext *ctx)
2892 {
2893 TCGv t0;
2894 TCGv_i32 t1;
2895 gen_set_access_type(ctx, ACCESS_INT);
2896 /* NIP cannot be restored if the memory exception comes from an helper */
2897 gen_update_nip(ctx, ctx->nip - 4);
2898 t0 = tcg_temp_new();
2899 t1 = tcg_const_i32(rS(ctx->opcode));
2900 gen_addr_imm_index(ctx, t0, 0);
2901 gen_helper_stmw(cpu_env, t0, t1);
2902 tcg_temp_free(t0);
2903 tcg_temp_free_i32(t1);
2904 }
2905
2906 /*** Integer load and store strings ***/
2907
2908 /* lswi */
2909 /* PowerPC32 specification says we must generate an exception if
2910 * rA is in the range of registers to be loaded.
2911 * In an other hand, IBM says this is valid, but rA won't be loaded.
2912 * For now, I'll follow the spec...
2913 */
2914 static void gen_lswi(DisasContext *ctx)
2915 {
2916 TCGv t0;
2917 TCGv_i32 t1, t2;
2918 int nb = NB(ctx->opcode);
2919 int start = rD(ctx->opcode);
2920 int ra = rA(ctx->opcode);
2921 int nr;
2922
2923 if (nb == 0)
2924 nb = 32;
2925 nr = nb / 4;
2926 if (unlikely(((start + nr) > 32 &&
2927 start <= ra && (start + nr - 32) > ra) ||
2928 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2929 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2930 return;
2931 }
2932 gen_set_access_type(ctx, ACCESS_INT);
2933 /* NIP cannot be restored if the memory exception comes from an helper */
2934 gen_update_nip(ctx, ctx->nip - 4);
2935 t0 = tcg_temp_new();
2936 gen_addr_register(ctx, t0);
2937 t1 = tcg_const_i32(nb);
2938 t2 = tcg_const_i32(start);
2939 gen_helper_lsw(cpu_env, t0, t1, t2);
2940 tcg_temp_free(t0);
2941 tcg_temp_free_i32(t1);
2942 tcg_temp_free_i32(t2);
2943 }
2944
2945 /* lswx */
2946 static void gen_lswx(DisasContext *ctx)
2947 {
2948 TCGv t0;
2949 TCGv_i32 t1, t2, t3;
2950 gen_set_access_type(ctx, ACCESS_INT);
2951 /* NIP cannot be restored if the memory exception comes from an helper */
2952 gen_update_nip(ctx, ctx->nip - 4);
2953 t0 = tcg_temp_new();
2954 gen_addr_reg_index(ctx, t0);
2955 t1 = tcg_const_i32(rD(ctx->opcode));
2956 t2 = tcg_const_i32(rA(ctx->opcode));
2957 t3 = tcg_const_i32(rB(ctx->opcode));
2958 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2959 tcg_temp_free(t0);
2960 tcg_temp_free_i32(t1);
2961 tcg_temp_free_i32(t2);
2962 tcg_temp_free_i32(t3);
2963 }
2964
2965 /* stswi */
2966 static void gen_stswi(DisasContext *ctx)
2967 {
2968 TCGv t0;
2969 TCGv_i32 t1, t2;
2970 int nb = NB(ctx->opcode);
2971 gen_set_access_type(ctx, ACCESS_INT);
2972 /* NIP cannot be restored if the memory exception comes from an helper */
2973 gen_update_nip(ctx, ctx->nip - 4);
2974 t0 = tcg_temp_new();
2975 gen_addr_register(ctx, t0);
2976 if (nb == 0)
2977 nb = 32;
2978 t1 = tcg_const_i32(nb);
2979 t2 = tcg_const_i32(rS(ctx->opcode));
2980 gen_helper_stsw(cpu_env, t0, t1, t2);
2981 tcg_temp_free(t0);
2982 tcg_temp_free_i32(t1);
2983 tcg_temp_free_i32(t2);
2984 }
2985
2986 /* stswx */
2987 static void gen_stswx(DisasContext *ctx)
2988 {
2989 TCGv t0;
2990 TCGv_i32 t1, t2;
2991 gen_set_access_type(ctx, ACCESS_INT);
2992 /* NIP cannot be restored if the memory exception comes from an helper */
2993 gen_update_nip(ctx, ctx->nip - 4);
2994 t0 = tcg_temp_new();
2995 gen_addr_reg_index(ctx, t0);
2996 t1 = tcg_temp_new_i32();
2997 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2998 tcg_gen_andi_i32(t1, t1, 0x7F);
2999 t2 = tcg_const_i32(rS(ctx->opcode));
3000 gen_helper_stsw(cpu_env, t0, t1, t2);
3001 tcg_temp_free(t0);
3002 tcg_temp_free_i32(t1);
3003 tcg_temp_free_i32(t2);
3004 }
3005
3006 /*** Memory synchronisation ***/
3007 /* eieio */
3008 static void gen_eieio(DisasContext *ctx)
3009 {
3010 }
3011
3012 /* isync */
3013 static void gen_isync(DisasContext *ctx)
3014 {
3015 gen_stop_exception(ctx);
3016 }
3017
3018 /* lwarx */
3019 static void gen_lwarx(DisasContext *ctx)
3020 {
3021 TCGv t0;
3022 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3023 gen_set_access_type(ctx, ACCESS_RES);
3024 t0 = tcg_temp_local_new();
3025 gen_addr_reg_index(ctx, t0);
3026 gen_check_align(ctx, t0, 0x03);
3027 gen_qemu_ld32u(ctx, gpr, t0);
3028 tcg_gen_mov_tl(cpu_reserve, t0);
3029 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3030 tcg_temp_free(t0);
3031 }
3032
3033 #if defined(CONFIG_USER_ONLY)
3034 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3035 int reg, int size)
3036 {
3037 TCGv t0 = tcg_temp_new();
3038 uint32_t save_exception = ctx->exception;
3039
3040 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3041 tcg_gen_movi_tl(t0, (size << 5) | reg);
3042 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3043 tcg_temp_free(t0);
3044 gen_update_nip(ctx, ctx->nip-4);
3045 ctx->exception = POWERPC_EXCP_BRANCH;
3046 gen_exception(ctx, POWERPC_EXCP_STCX);
3047 ctx->exception = save_exception;
3048 }
3049 #endif
3050
3051 /* stwcx. */
3052 static void gen_stwcx_(DisasContext *ctx)
3053 {
3054 TCGv t0;
3055 gen_set_access_type(ctx, ACCESS_RES);
3056 t0 = tcg_temp_local_new();
3057 gen_addr_reg_index(ctx, t0);
3058 gen_check_align(ctx, t0, 0x03);
3059 #if defined(CONFIG_USER_ONLY)
3060 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3061 #else
3062 {
3063 int l1;
3064
3065 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3066 l1 = gen_new_label();
3067 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3068 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3069 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3070 gen_set_label(l1);
3071 tcg_gen_movi_tl(cpu_reserve, -1);
3072 }
3073 #endif
3074 tcg_temp_free(t0);
3075 }
3076
3077 #if defined(TARGET_PPC64)
3078 /* ldarx */
3079 static void gen_ldarx(DisasContext *ctx)
3080 {
3081 TCGv t0;
3082 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3083 gen_set_access_type(ctx, ACCESS_RES);
3084 t0 = tcg_temp_local_new();
3085 gen_addr_reg_index(ctx, t0);
3086 gen_check_align(ctx, t0, 0x07);
3087 gen_qemu_ld64(ctx, gpr, t0);
3088 tcg_gen_mov_tl(cpu_reserve, t0);
3089 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3090 tcg_temp_free(t0);
3091 }
3092
3093 /* stdcx. */
3094 static void gen_stdcx_(DisasContext *ctx)
3095 {
3096 TCGv t0;
3097 gen_set_access_type(ctx, ACCESS_RES);
3098 t0 = tcg_temp_local_new();
3099 gen_addr_reg_index(ctx, t0);
3100 gen_check_align(ctx, t0, 0x07);
3101 #if defined(CONFIG_USER_ONLY)
3102 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3103 #else
3104 {
3105 int l1;
3106 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3107 l1 = gen_new_label();
3108 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3109 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3110 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3111 gen_set_label(l1);
3112 tcg_gen_movi_tl(cpu_reserve, -1);
3113 }
3114 #endif
3115 tcg_temp_free(t0);
3116 }
3117 #endif /* defined(TARGET_PPC64) */
3118
3119 /* sync */
3120 static void gen_sync(DisasContext *ctx)
3121 {
3122 }
3123
3124 /* wait */
3125 static void gen_wait(DisasContext *ctx)
3126 {
3127 TCGv_i32 t0 = tcg_temp_new_i32();
3128 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
3129 tcg_temp_free_i32(t0);
3130 /* Stop translation, as the CPU is supposed to sleep from now */
3131 gen_exception_err(ctx, EXCP_HLT, 1);
3132 }
3133
3134 /*** Floating-point load ***/
3135 #define GEN_LDF(name, ldop, opc, type) \
3136 static void glue(gen_, name)(DisasContext *ctx) \
3137 { \
3138 TCGv EA; \
3139 if (unlikely(!ctx->fpu_enabled)) { \
3140 gen_exception(ctx, POWERPC_EXCP_FPU); \
3141 return; \
3142 } \
3143 gen_set_access_type(ctx, ACCESS_FLOAT); \
3144 EA = tcg_temp_new(); \
3145 gen_addr_imm_index(ctx, EA, 0); \
3146 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3147 tcg_temp_free(EA); \
3148 }
3149
3150 #define GEN_LDUF(name, ldop, opc, type) \
3151 static void glue(gen_, name##u)(DisasContext *ctx) \
3152 { \
3153 TCGv EA; \
3154 if (unlikely(!ctx->fpu_enabled)) { \
3155 gen_exception(ctx, POWERPC_EXCP_FPU); \
3156 return; \
3157 } \
3158 if (unlikely(rA(ctx->opcode) == 0)) { \
3159 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3160 return; \
3161 } \
3162 gen_set_access_type(ctx, ACCESS_FLOAT); \
3163 EA = tcg_temp_new(); \
3164 gen_addr_imm_index(ctx, EA, 0); \
3165 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3166 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3167 tcg_temp_free(EA); \
3168 }
3169
3170 #define GEN_LDUXF(name, ldop, opc, type) \
3171 static void glue(gen_, name##ux)(DisasContext *ctx) \
3172 { \
3173 TCGv EA; \
3174 if (unlikely(!ctx->fpu_enabled)) { \
3175 gen_exception(ctx, POWERPC_EXCP_FPU); \
3176 return; \
3177 } \
3178 if (unlikely(rA(ctx->opcode) == 0)) { \
3179 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3180 return; \
3181 } \
3182 gen_set_access_type(ctx, ACCESS_FLOAT); \
3183 EA = tcg_temp_new(); \
3184 gen_addr_reg_index(ctx, EA); \
3185 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3186 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3187 tcg_temp_free(EA); \
3188 }
3189
3190 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3191 static void glue(gen_, name##x)(DisasContext *ctx) \
3192 { \
3193 TCGv EA; \
3194 if (unlikely(!ctx->fpu_enabled)) { \
3195 gen_exception(ctx, POWERPC_EXCP_FPU); \
3196 return; \
3197 } \
3198 gen_set_access_type(ctx, ACCESS_FLOAT); \
3199 EA = tcg_temp_new(); \
3200 gen_addr_reg_index(ctx, EA); \
3201 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3202 tcg_temp_free(EA); \
3203 }
3204
3205 #define GEN_LDFS(name, ldop, op, type) \
3206 GEN_LDF(name, ldop, op | 0x20, type); \
3207 GEN_LDUF(name, ldop, op | 0x21, type); \
3208 GEN_LDUXF(name, ldop, op | 0x01, type); \
3209 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3210
3211 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3212 {
3213 TCGv t0 = tcg_temp_new();
3214 TCGv_i32 t1 = tcg_temp_new_i32();
3215 gen_qemu_ld32u(ctx, t0, arg2);
3216 tcg_gen_trunc_tl_i32(t1, t0);
3217 tcg_temp_free(t0);
3218 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3219 tcg_temp_free_i32(t1);
3220 }
3221
3222 /* lfd lfdu lfdux lfdx */
3223 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3224 /* lfs lfsu lfsux lfsx */
3225 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3226
3227 /*** Floating-point store ***/
3228 #define GEN_STF(name, stop, opc, type) \
3229 static void glue(gen_, name)(DisasContext *ctx) \
3230 { \
3231 TCGv EA; \
3232 if (unlikely(!ctx->fpu_enabled)) { \
3233 gen_exception(ctx, POWERPC_EXCP_FPU); \
3234 return; \
3235 } \
3236 gen_set_access_type(ctx, ACCESS_FLOAT); \
3237 EA = tcg_temp_new(); \
3238 gen_addr_imm_index(ctx, EA, 0); \
3239 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3240 tcg_temp_free(EA); \
3241 }
3242
3243 #define GEN_STUF(name, stop, opc, type) \
3244 static void glue(gen_, name##u)(DisasContext *ctx) \
3245 { \
3246 TCGv EA; \
3247 if (unlikely(!ctx->fpu_enabled)) { \
3248 gen_exception(ctx, POWERPC_EXCP_FPU); \
3249 return; \
3250 } \
3251 if (unlikely(rA(ctx->opcode) == 0)) { \
3252 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3253 return; \
3254 } \
3255 gen_set_access_type(ctx, ACCESS_FLOAT); \
3256 EA = tcg_temp_new(); \
3257 gen_addr_imm_index(ctx, EA, 0); \
3258 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3259 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3260 tcg_temp_free(EA); \
3261 }
3262
3263 #define GEN_STUXF(name, stop, opc, type) \
3264 static void glue(gen_, name##ux)(DisasContext *ctx) \
3265 { \
3266 TCGv EA; \
3267 if (unlikely(!ctx->fpu_enabled)) { \
3268 gen_exception(ctx, POWERPC_EXCP_FPU); \
3269 return; \
3270 } \
3271 if (unlikely(rA(ctx->opcode) == 0)) { \
3272 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3273 return; \
3274 } \
3275 gen_set_access_type(ctx, ACCESS_FLOAT); \
3276 EA = tcg_temp_new(); \
3277 gen_addr_reg_index(ctx, EA); \
3278 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3279 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3280 tcg_temp_free(EA); \
3281 }
3282
3283 #define GEN_STXF(name, stop, opc2, opc3, type) \
3284 static void glue(gen_, name##x)(DisasContext *ctx) \
3285 { \
3286 TCGv EA; \
3287 if (unlikely(!ctx->fpu_enabled)) { \
3288 gen_exception(ctx, POWERPC_EXCP_FPU); \
3289 return; \
3290 } \
3291 gen_set_access_type(ctx, ACCESS_FLOAT); \
3292 EA = tcg_temp_new(); \
3293 gen_addr_reg_index(ctx, EA); \
3294 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3295 tcg_temp_free(EA); \
3296 }
3297
3298 #define GEN_STFS(name, stop, op, type) \
3299 GEN_STF(name, stop, op | 0x20, type); \
3300 GEN_STUF(name, stop, op | 0x21, type); \
3301 GEN_STUXF(name, stop, op | 0x01, type); \
3302 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3303
3304 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3305 {
3306 TCGv_i32 t0 = tcg_temp_new_i32();
3307 TCGv t1 = tcg_temp_new();
3308 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3309 tcg_gen_extu_i32_tl(t1, t0);
3310 tcg_temp_free_i32(t0);
3311 gen_qemu_st32(ctx, t1, arg2);
3312 tcg_temp_free(t1);
3313 }
3314
3315 /* stfd stfdu stfdux stfdx */
3316 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3317 /* stfs stfsu stfsux stfsx */
3318 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3319
3320 /* Optional: */
3321 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3322 {
3323 TCGv t0 = tcg_temp_new();
3324 tcg_gen_trunc_i64_tl(t0, arg1),
3325 gen_qemu_st32(ctx, t0, arg2);
3326 tcg_temp_free(t0);
3327 }
3328 /* stfiwx */
3329 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3330
3331 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3332 {
3333 #if defined(TARGET_PPC64)
3334 if (ctx->has_cfar)
3335 tcg_gen_movi_tl(cpu_cfar, nip);
3336 #endif
3337 }
3338
3339 /*** Branch ***/
3340 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3341 {
3342 TranslationBlock *tb;
3343 tb = ctx->tb;
3344 #if defined(TARGET_PPC64)
3345 if (!ctx->sf_mode)
3346 dest = (uint32_t) dest;
3347 #endif
3348 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3349 likely(!ctx->singlestep_enabled)) {
3350 tcg_gen_goto_tb(n);
3351 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3352 tcg_gen_exit_tb((tcg_target_long)tb + n);
3353 } else {
3354 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3355 if (unlikely(ctx->singlestep_enabled)) {
3356 if ((ctx->singlestep_enabled &
3357 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3358 (ctx->exception == POWERPC_EXCP_BRANCH ||
3359 ctx->exception == POWERPC_EXCP_TRACE)) {
3360 target_ulong tmp = ctx->nip;
3361 ctx->nip = dest;
3362 gen_exception(ctx, POWERPC_EXCP_TRACE);
3363 ctx->nip = tmp;
3364 }
3365 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3366 gen_debug_exception(ctx);
3367 }
3368 }
3369 tcg_gen_exit_tb(0);
3370 }
3371 }
3372
3373 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3374 {
3375 #if defined(TARGET_PPC64)
3376 if (ctx->sf_mode == 0)
3377 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3378 else
3379 #endif
3380 tcg_gen_movi_tl(cpu_lr, nip);
3381 }
3382
3383 /* b ba bl bla */
3384 static void gen_b(DisasContext *ctx)
3385 {
3386 target_ulong li, target;
3387
3388 ctx->exception = POWERPC_EXCP_BRANCH;
3389 /* sign extend LI */
3390 #if defined(TARGET_PPC64)
3391 if (ctx->sf_mode)
3392 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3393 else
3394 #endif
3395 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3396 if (likely(AA(ctx->opcode) == 0))
3397 target = ctx->nip + li - 4;
3398 else
3399 target = li;
3400 if (LK(ctx->opcode))
3401 gen_setlr(ctx, ctx->nip);
3402 gen_update_cfar(ctx, ctx->nip);
3403 gen_goto_tb(ctx, 0, target);
3404 }
3405
3406 #define BCOND_IM 0
3407 #define BCOND_LR 1
3408 #define BCOND_CTR 2
3409
3410 static inline void gen_bcond(DisasContext *ctx, int type)
3411 {
3412 uint32_t bo = BO(ctx->opcode);
3413 int l1;
3414 TCGv target;
3415
3416 ctx->exception = POWERPC_EXCP_BRANCH;
3417 if (type == BCOND_LR || type == BCOND_CTR) {
3418 target = tcg_temp_local_new();
3419 if (type == BCOND_CTR)
3420 tcg_gen_mov_tl(target, cpu_ctr);
3421 else
3422 tcg_gen_mov_tl(target, cpu_lr);
3423 } else {
3424 TCGV_UNUSED(target);
3425 }
3426 if (LK(ctx->opcode))
3427 gen_setlr(ctx, ctx->nip);
3428 l1 = gen_new_label();
3429 if ((bo & 0x4) == 0) {
3430 /* Decrement and test CTR */
3431 TCGv temp = tcg_temp_new();
3432 if (unlikely(type == BCOND_CTR)) {
3433 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3434 return;
3435 }
3436 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3437 #if defined(TARGET_PPC64)
3438 if (!ctx->sf_mode)
3439 tcg_gen_ext32u_tl(temp, cpu_ctr);
3440 else
3441 #endif
3442 tcg_gen_mov_tl(temp, cpu_ctr);
3443 if (bo & 0x2) {
3444 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3445 } else {
3446 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3447 }
3448 tcg_temp_free(temp);
3449 }
3450 if ((bo & 0x10) == 0) {
3451 /* Test CR */
3452 uint32_t bi = BI(ctx->opcode);
3453 uint32_t mask = 1 << (3 - (bi & 0x03));
3454 TCGv_i32 temp = tcg_temp_new_i32();
3455
3456 if (bo & 0x8) {
3457 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3458 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3459 } else {
3460 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3461 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3462 }
3463 tcg_temp_free_i32(temp);
3464 }
3465 gen_update_cfar(ctx, ctx->nip);
3466 if (type == BCOND_IM) {
3467 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3468 if (likely(AA(ctx->opcode) == 0)) {
3469 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3470 } else {
3471 gen_goto_tb(ctx, 0, li);
3472 }
3473 gen_set_label(l1);
3474 gen_goto_tb(ctx, 1, ctx->nip);
3475 } else {
3476 #if defined(TARGET_PPC64)
3477 if (!(ctx->sf_mode))
3478 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3479 else
3480 #endif
3481 tcg_gen_andi_tl(cpu_nip, target, ~3);
3482 tcg_gen_exit_tb(0);
3483 gen_set_label(l1);
3484 #if defined(TARGET_PPC64)
3485 if (!(ctx->sf_mode))
3486 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3487 else
3488 #endif
3489 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3490 tcg_gen_exit_tb(0);
3491 }
3492 }
3493
3494 static void gen_bc(DisasContext *ctx)
3495 {
3496 gen_bcond(ctx, BCOND_IM);
3497 }
3498
3499 static void gen_bcctr(DisasContext *ctx)
3500 {
3501 gen_bcond(ctx, BCOND_CTR);
3502 }
3503
3504 static void gen_bclr(DisasContext *ctx)
3505 {
3506 gen_bcond(ctx, BCOND_LR);
3507 }
3508
3509 /*** Condition register logical ***/
3510 #define GEN_CRLOGIC(name, tcg_op, opc) \
3511 static void glue(gen_, name)(DisasContext *ctx) \
3512 { \
3513 uint8_t bitmask; \
3514 int sh; \
3515 TCGv_i32 t0, t1; \
3516 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3517 t0 = tcg_temp_new_i32(); \
3518 if (sh > 0) \
3519 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3520 else if (sh < 0) \
3521 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3522 else \
3523 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3524 t1 = tcg_temp_new_i32(); \
3525 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3526 if (sh > 0) \
3527 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3528 else if (sh < 0) \
3529 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3530 else \
3531 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3532 tcg_op(t0, t0, t1); \
3533 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3534 tcg_gen_andi_i32(t0, t0, bitmask); \
3535 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3536 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3537 tcg_temp_free_i32(t0); \
3538 tcg_temp_free_i32(t1); \
3539 }
3540
3541 /* crand */
3542 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3543 /* crandc */
3544 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3545 /* creqv */
3546 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3547 /* crnand */
3548 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3549 /* crnor */
3550 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3551 /* cror */
3552 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3553 /* crorc */
3554 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3555 /* crxor */
3556 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3557
3558 /* mcrf */
3559 static void gen_mcrf(DisasContext *ctx)
3560 {
3561 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3562 }
3563
3564 /*** System linkage ***/
3565
3566 /* rfi (mem_idx only) */
3567 static void gen_rfi(DisasContext *ctx)
3568 {
3569 #if defined(CONFIG_USER_ONLY)
3570 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3571 #else
3572 /* Restore CPU state */
3573 if (unlikely(!ctx->mem_idx)) {
3574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3575 return;
3576 }
3577 gen_update_cfar(ctx, ctx->nip);
3578 gen_helper_rfi(cpu_env);
3579 gen_sync_exception(ctx);
3580 #endif
3581 }
3582
3583 #if defined(TARGET_PPC64)
3584 static void gen_rfid(DisasContext *ctx)
3585 {
3586 #if defined(CONFIG_USER_ONLY)
3587 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3588 #else
3589 /* Restore CPU state */
3590 if (unlikely(!ctx->mem_idx)) {
3591 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3592 return;
3593 }
3594 gen_update_cfar(ctx, ctx->nip);
3595 gen_helper_rfid(cpu_env);
3596 gen_sync_exception(ctx);
3597 #endif
3598 }
3599
3600 static void gen_hrfid(DisasContext *ctx)
3601 {
3602 #if defined(CONFIG_USER_ONLY)
3603 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3604 #else
3605 /* Restore CPU state */
3606 if (unlikely(ctx->mem_idx <= 1)) {
3607 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3608 return;
3609 }
3610 gen_helper_hrfid(cpu_env);
3611 gen_sync_exception(ctx);
3612 #endif
3613 }
3614 #endif
3615
3616 /* sc */
3617 #if defined(CONFIG_USER_ONLY)
3618 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3619 #else
3620 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3621 #endif
3622 static void gen_sc(DisasContext *ctx)
3623 {
3624 uint32_t lev;
3625
3626 lev = (ctx->opcode >> 5) & 0x7F;
3627 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3628 }
3629
3630 /*** Trap ***/
3631
3632 /* tw */
3633 static void gen_tw(DisasContext *ctx)
3634 {
3635 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3636 /* Update the nip since this might generate a trap exception */
3637 gen_update_nip(ctx, ctx->nip);
3638 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3639 t0);
3640 tcg_temp_free_i32(t0);
3641 }
3642
3643 /* twi */
3644 static void gen_twi(DisasContext *ctx)
3645 {
3646 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3647 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3648 /* Update the nip since this might generate a trap exception */
3649 gen_update_nip(ctx, ctx->nip);
3650 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3651 tcg_temp_free(t0);
3652 tcg_temp_free_i32(t1);
3653 }
3654
3655 #if defined(TARGET_PPC64)
3656 /* td */
3657 static void gen_td(DisasContext *ctx)
3658 {
3659 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3660 /* Update the nip since this might generate a trap exception */
3661 gen_update_nip(ctx, ctx->nip);
3662 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3663 t0);
3664 tcg_temp_free_i32(t0);
3665 }
3666
3667 /* tdi */
3668 static void gen_tdi(DisasContext *ctx)
3669 {
3670 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3671 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3672 /* Update the nip since this might generate a trap exception */
3673 gen_update_nip(ctx, ctx->nip);
3674 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3675 tcg_temp_free(t0);
3676 tcg_temp_free_i32(t1);
3677 }
3678 #endif
3679
3680 /*** Processor control ***/
3681
3682 static void gen_read_xer(TCGv dst)
3683 {
3684 TCGv t0 = tcg_temp_new();
3685 TCGv t1 = tcg_temp_new();
3686 TCGv t2 = tcg_temp_new();
3687 tcg_gen_mov_tl(dst, cpu_xer);
3688 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3689 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3690 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3691 tcg_gen_or_tl(t0, t0, t1);
3692 tcg_gen_or_tl(dst, dst, t2);
3693 tcg_gen_or_tl(dst, dst, t0);
3694 tcg_temp_free(t0);
3695 tcg_temp_free(t1);
3696 tcg_temp_free(t2);
3697 }
3698
3699 static void gen_write_xer(TCGv src)
3700 {
3701 tcg_gen_andi_tl(cpu_xer, src,
3702 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3703 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3704 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3705 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3706 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3707 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3708 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3709 }
3710
3711 /* mcrxr */
3712 static void gen_mcrxr(DisasContext *ctx)
3713 {
3714 TCGv_i32 t0 = tcg_temp_new_i32();
3715 TCGv_i32 t1 = tcg_temp_new_i32();
3716 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3717
3718 tcg_gen_trunc_tl_i32(t0, cpu_so);
3719 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3720 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3721 tcg_gen_shri_i32(t0, t0, 2);
3722 tcg_gen_shri_i32(t1, t1, 1);
3723 tcg_gen_or_i32(dst, dst, t0);
3724 tcg_gen_or_i32(dst, dst, t1);
3725 tcg_temp_free_i32(t0);
3726 tcg_temp_free_i32(t1);
3727
3728 tcg_gen_movi_tl(cpu_so, 0);
3729 tcg_gen_movi_tl(cpu_ov, 0);
3730 tcg_gen_movi_tl(cpu_ca, 0);
3731 }
3732
3733 /* mfcr mfocrf */
3734 static void gen_mfcr(DisasContext *ctx)
3735 {
3736 uint32_t crm, crn;
3737
3738 if (likely(ctx->opcode & 0x00100000)) {
3739 crm = CRM(ctx->opcode);
3740 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3741 crn = ctz32 (crm);
3742 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3743 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3744 cpu_gpr[rD(ctx->opcode)], crn * 4);
3745 }
3746 } else {
3747 TCGv_i32 t0 = tcg_temp_new_i32();
3748 tcg_gen_mov_i32(t0, cpu_crf[0]);
3749 tcg_gen_shli_i32(t0, t0, 4);
3750 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3751 tcg_gen_shli_i32(t0, t0, 4);
3752 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3753 tcg_gen_shli_i32(t0, t0, 4);
3754 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3755 tcg_gen_shli_i32(t0, t0, 4);
3756 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3757 tcg_gen_shli_i32(t0, t0, 4);
3758 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3759 tcg_gen_shli_i32(t0, t0, 4);
3760 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3761 tcg_gen_shli_i32(t0, t0, 4);
3762 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3763 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3764 tcg_temp_free_i32(t0);
3765 }
3766 }
3767
3768 /* mfmsr */
3769 static void gen_mfmsr(DisasContext *ctx)
3770 {
3771 #if defined(CONFIG_USER_ONLY)
3772 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3773 #else
3774 if (unlikely(!ctx->mem_idx)) {
3775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3776 return;
3777 }
3778 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3779 #endif
3780 }
3781
3782 static void spr_noaccess(void *opaque, int gprn, int sprn)
3783 {
3784 #if 0
3785 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3786 printf("ERROR: try to access SPR %d !\n", sprn);
3787 #endif
3788 }
3789 #define SPR_NOACCESS (&spr_noaccess)
3790
3791 /* mfspr */
3792 static inline void gen_op_mfspr(DisasContext *ctx)
3793 {
3794 void (*read_cb)(void *opaque, int gprn, int sprn);
3795 uint32_t sprn = SPR(ctx->opcode);
3796
3797 #if !defined(CONFIG_USER_ONLY)
3798 if (ctx->mem_idx == 2)
3799 read_cb = ctx->spr_cb[sprn].hea_read;
3800 else if (ctx->mem_idx)
3801 read_cb = ctx->spr_cb[sprn].oea_read;
3802 else
3803 #endif
3804 read_cb = ctx->spr_cb[sprn].uea_read;
3805 if (likely(read_cb != NULL)) {
3806 if (likely(read_cb != SPR_NOACCESS)) {
3807 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3808 } else {
3809 /* Privilege exception */
3810 /* This is a hack to avoid warnings when running Linux:
3811 * this OS breaks the PowerPC virtualisation model,
3812 * allowing userland application to read the PVR
3813 */
3814 if (sprn != SPR_PVR) {
3815 qemu_log("Trying to read privileged spr %d %03x at "
3816 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3817 printf("Trying to read privileged spr %d %03x at "
3818 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3819 }
3820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3821 }
3822 } else {
3823 /* Not defined */
3824 qemu_log("Trying to read invalid spr %d %03x at "
3825 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3826 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3827 sprn, sprn, ctx->nip);
3828 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3829 }
3830 }
3831
3832 static void gen_mfspr(DisasContext *ctx)
3833 {
3834 gen_op_mfspr(ctx);
3835 }
3836
3837 /* mftb */
3838 static void gen_mftb(DisasContext *ctx)
3839 {
3840 gen_op_mfspr(ctx);
3841 }
3842
3843 /* mtcrf mtocrf*/
3844 static void gen_mtcrf(DisasContext *ctx)
3845 {
3846 uint32_t crm, crn;
3847
3848 crm = CRM(ctx->opcode);
3849 if (likely((ctx->opcode & 0x00100000))) {
3850 if (crm && ((crm & (crm - 1)) == 0)) {
3851 TCGv_i32 temp = tcg_temp_new_i32();
3852 crn = ctz32 (crm);
3853 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3854 tcg_gen_shri_i32(temp, temp, crn * 4);
3855 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3856 tcg_temp_free_i32(temp);
3857 }
3858 } else {
3859 TCGv_i32 temp = tcg_temp_new_i32();
3860 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3861 for (crn = 0 ; crn < 8 ; crn++) {
3862 if (crm & (1 << crn)) {
3863 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3864 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3865 }
3866 }
3867 tcg_temp_free_i32(temp);
3868 }
3869 }
3870
3871 /* mtmsr */
3872 #if defined(TARGET_PPC64)
3873 static void gen_mtmsrd(DisasContext *ctx)
3874 {
3875 #if defined(CONFIG_USER_ONLY)
3876 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3877 #else
3878 if (unlikely(!ctx->mem_idx)) {
3879 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3880 return;
3881 }
3882 if (ctx->opcode & 0x00010000) {
3883 /* Special form that does not need any synchronisation */
3884 TCGv t0 = tcg_temp_new();
3885 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3886 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3887 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3888 tcg_temp_free(t0);
3889 } else {
3890 /* XXX: we need to update nip before the store
3891 * if we enter power saving mode, we will exit the loop
3892 * directly from ppc_store_msr
3893 */
3894 gen_update_nip(ctx, ctx->nip);
3895 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3896 /* Must stop the translation as machine state (may have) changed */
3897 /* Note that mtmsr is not always defined as context-synchronizing */
3898 gen_stop_exception(ctx);
3899 }
3900 #endif
3901 }
3902 #endif
3903
3904 static void gen_mtmsr(DisasContext *ctx)
3905 {
3906 #if defined(CONFIG_USER_ONLY)
3907 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3908 #else
3909 if (unlikely(!ctx->mem_idx)) {
3910 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3911 return;
3912 }
3913 if (ctx->opcode & 0x00010000) {
3914 /* Special form that does not need any synchronisation */
3915 TCGv t0 = tcg_temp_new();
3916 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3917 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3918 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3919 tcg_temp_free(t0);
3920 } else {
3921 TCGv msr = tcg_temp_new();
3922
3923 /* XXX: we need to update nip before the store
3924 * if we enter power saving mode, we will exit the loop
3925 * directly from ppc_store_msr
3926 */
3927 gen_update_nip(ctx, ctx->nip);
3928 #if defined(TARGET_PPC64)
3929 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3930 #else
3931 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3932 #endif
3933 gen_helper_store_msr(cpu_env, msr);
3934 /* Must stop the translation as machine state (may have) changed */
3935 /* Note that mtmsr is not always defined as context-synchronizing */
3936 gen_stop_exception(ctx);
3937 }
3938 #endif
3939 }
3940
3941 /* mtspr */
3942 static void gen_mtspr(DisasContext *ctx)
3943 {
3944 void (*write_cb)(void *opaque, int sprn, int gprn);
3945 uint32_t sprn = SPR(ctx->opcode);
3946
3947 #if !defined(CONFIG_USER_ONLY)
3948 if (ctx->mem_idx == 2)
3949 write_cb = ctx->spr_cb[sprn].hea_write;
3950 else if (ctx->mem_idx)
3951 write_cb = ctx->spr_cb[sprn].oea_write;
3952 else
3953 #endif
3954 write_cb = ctx->spr_cb[sprn].uea_write;
3955 if (likely(write_cb != NULL)) {
3956 if (likely(write_cb != SPR_NOACCESS)) {
3957 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3958 } else {
3959 /* Privilege exception */
3960 qemu_log("Trying to write privileged spr %d %03x at "
3961 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3962 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3963 "\n", sprn, sprn, ctx->nip);
3964 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3965 }
3966 } else {
3967 /* Not defined */
3968 qemu_log("Trying to write invalid spr %d %03x at "
3969 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3970 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3971 sprn, sprn, ctx->nip);
3972 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3973 }
3974 }
3975
3976 /*** Cache management ***/
3977
3978 /* dcbf */
3979 static void gen_dcbf(DisasContext *ctx)
3980 {
3981 /* XXX: specification says this is treated as a load by the MMU */
3982 TCGv t0;
3983 gen_set_access_type(ctx, ACCESS_CACHE);
3984 t0 = tcg_temp_new();
3985 gen_addr_reg_index(ctx, t0);
3986 gen_qemu_ld8u(ctx, t0, t0);
3987 tcg_temp_free(t0);
3988 }
3989
3990 /* dcbi (Supervisor only) */
3991 static void gen_dcbi(DisasContext *ctx)
3992 {
3993 #if defined(CONFIG_USER_ONLY)
3994 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3995 #else
3996 TCGv EA, val;
3997 if (unlikely(!ctx->mem_idx)) {
3998 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3999 return;
4000 }
4001 EA = tcg_temp_new();
4002 gen_set_access_type(ctx, ACCESS_CACHE);
4003 gen_addr_reg_index(ctx, EA);
4004 val = tcg_temp_new();
4005 /* XXX: specification says this should be treated as a store by the MMU */
4006 gen_qemu_ld8u(ctx, val, EA);
4007 gen_qemu_st8(ctx, val, EA);
4008 tcg_temp_free(val);
4009 tcg_temp_free(EA);
4010 #endif
4011 }
4012
4013 /* dcdst */
4014 static void gen_dcbst(DisasContext *ctx)
4015 {
4016 /* XXX: specification say this is treated as a load by the MMU */
4017 TCGv t0;
4018 gen_set_access_type(ctx, ACCESS_CACHE);
4019 t0 = tcg_temp_new();
4020 gen_addr_reg_index(ctx, t0);
4021 gen_qemu_ld8u(ctx, t0, t0);
4022 tcg_temp_free(t0);
4023 }
4024
4025 /* dcbt */
4026 static void gen_dcbt(DisasContext *ctx)
4027 {
4028 /* interpreted as no-op */
4029 /* XXX: specification say this is treated as a load by the MMU
4030 * but does not generate any exception
4031 */
4032 }
4033
4034 /* dcbtst */
4035 static void gen_dcbtst(DisasContext *ctx)
4036 {
4037 /* interpreted as no-op */
4038 /* XXX: specification say this is treated as a load by the MMU
4039 * but does not generate any exception
4040 */
4041 }
4042
4043 /* dcbz */
4044 static void gen_dcbz(DisasContext *ctx)
4045 {
4046 TCGv tcgv_addr;
4047 TCGv_i32 tcgv_is_dcbzl;
4048 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4049
4050 gen_set_access_type(ctx, ACCESS_CACHE);
4051 /* NIP cannot be restored if the memory exception comes from an helper */
4052 gen_update_nip(ctx, ctx->nip - 4);
4053 tcgv_addr = tcg_temp_new();
4054 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4055
4056 gen_addr_reg_index(ctx, tcgv_addr);
4057 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4058
4059 tcg_temp_free(tcgv_addr);
4060 tcg_temp_free_i32(tcgv_is_dcbzl);
4061 }
4062
4063 /* dst / dstt */
4064 static void gen_dst(DisasContext *ctx)
4065 {
4066 if (rA(ctx->opcode) == 0) {
4067 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4068 } else {
4069 /* interpreted as no-op */
4070 }
4071 }
4072
4073 /* dstst /dststt */
4074 static void gen_dstst(DisasContext *ctx)
4075 {
4076 if (rA(ctx->opcode) == 0) {
4077 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4078 } else {
4079 /* interpreted as no-op */
4080 }
4081
4082 }
4083
4084 /* dss / dssall */
4085 static void gen_dss(DisasContext *ctx)
4086 {
4087 /* interpreted as no-op */
4088 }
4089
4090 /* icbi */
4091 static void gen_icbi(DisasContext *ctx)
4092 {
4093 TCGv t0;
4094 gen_set_access_type(ctx, ACCESS_CACHE);
4095 /* NIP cannot be restored if the memory exception comes from an helper */
4096 gen_update_nip(ctx, ctx->nip - 4);
4097 t0 = tcg_temp_new();
4098 gen_addr_reg_index(ctx, t0);
4099 gen_helper_icbi(cpu_env, t0);
4100 tcg_temp_free(t0);
4101 }
4102
4103 /* Optional: */
4104 /* dcba */
4105 static void gen_dcba(DisasContext *ctx)
4106 {
4107 /* interpreted as no-op */
4108 /* XXX: specification say this is treated as a store by the MMU
4109 * but does not generate any exception
4110 */
4111 }
4112
4113 /*** Segment register manipulation ***/
4114 /* Supervisor only: */
4115
4116 /* mfsr */
4117 static void gen_mfsr(DisasContext *ctx)
4118 {
4119 #if defined(CONFIG_USER_ONLY)
4120 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4121 #else
4122 TCGv t0;
4123 if (unlikely(!ctx->mem_idx)) {
4124 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4125 return;
4126 }
4127 t0 = tcg_const_tl(SR(ctx->opcode));
4128 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4129 tcg_temp_free(t0);
4130 #endif
4131 }
4132
4133 /* mfsrin */
4134 static void gen_mfsrin(DisasContext *ctx)
4135 {
4136 #if defined(CONFIG_USER_ONLY)
4137 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4138 #else
4139 TCGv t0;
4140 if (unlikely(!ctx->mem_idx)) {
4141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4142 return;
4143 }
4144 t0 = tcg_temp_new();
4145 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4146 tcg_gen_andi_tl(t0, t0, 0xF);
4147 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4148 tcg_temp_free(t0);
4149 #endif
4150 }
4151
4152 /* mtsr */
4153 static void gen_mtsr(DisasContext *ctx)
4154 {
4155 #if defined(CONFIG_USER_ONLY)
4156 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4157 #else
4158 TCGv t0;
4159 if (unlikely(!ctx->mem_idx)) {
4160 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4161 return;
4162 }
4163 t0 = tcg_const_tl(SR(ctx->opcode));
4164 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4165 tcg_temp_free(t0);
4166 #endif
4167 }
4168
4169 /* mtsrin */
4170 static void gen_mtsrin(DisasContext *ctx)
4171 {
4172 #if defined(CONFIG_USER_ONLY)
4173 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4174 #else
4175 TCGv t0;
4176 if (unlikely(!ctx->mem_idx)) {
4177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4178 return;
4179 }
4180 t0 = tcg_temp_new();
4181 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4182 tcg_gen_andi_tl(t0, t0, 0xF);
4183 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4184 tcg_temp_free(t0);
4185 #endif
4186 }
4187
4188 #if defined(TARGET_PPC64)
4189 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4190
4191 /* mfsr */
4192 static void gen_mfsr_64b(DisasContext *ctx)
4193 {
4194 #if defined(CONFIG_USER_ONLY)
4195 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4196 #else
4197 TCGv t0;
4198 if (unlikely(!ctx->mem_idx)) {
4199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4200 return;
4201 }
4202 t0 = tcg_const_tl(SR(ctx->opcode));
4203 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4204 tcg_temp_free(t0);
4205 #endif
4206 }
4207
4208 /* mfsrin */
4209 static void gen_mfsrin_64b(DisasContext *ctx)
4210 {
4211 #if defined(CONFIG_USER_ONLY)
4212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4213 #else
4214 TCGv t0;
4215 if (unlikely(!ctx->mem_idx)) {
4216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4217 return;
4218 }
4219 t0 = tcg_temp_new();
4220 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4221 tcg_gen_andi_tl(t0, t0, 0xF);
4222 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4223 tcg_temp_free(t0);
4224 #endif
4225 }
4226
4227 /* mtsr */
4228 static void gen_mtsr_64b(DisasContext *ctx)
4229 {
4230 #if defined(CONFIG_USER_ONLY)
4231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4232 #else
4233 TCGv t0;
4234 if (unlikely(!ctx->mem_idx)) {
4235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4236 return;
4237 }
4238 t0 = tcg_const_tl(SR(ctx->opcode));
4239 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4240 tcg_temp_free(t0);
4241 #endif
4242 }
4243
4244 /* mtsrin */
4245 static void gen_mtsrin_64b(DisasContext *ctx)
4246 {
4247 #if defined(CONFIG_USER_ONLY)
4248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4249 #else
4250 TCGv t0;
4251 if (unlikely(!ctx->mem_idx)) {
4252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4253 return;
4254 }
4255 t0 = tcg_temp_new();
4256 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4257 tcg_gen_andi_tl(t0, t0, 0xF);
4258 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4259 tcg_temp_free(t0);
4260 #endif
4261 }
4262
4263 /* slbmte */
4264 static void gen_slbmte(DisasContext *ctx)
4265 {
4266 #if defined(CONFIG_USER_ONLY)
4267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4268 #else
4269 if (unlikely(!ctx->mem_idx)) {
4270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4271 return;
4272 }
4273 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4274 cpu_gpr[rS(ctx->opcode)]);
4275 #endif
4276 }
4277
4278 static void gen_slbmfee(DisasContext *ctx)
4279 {
4280 #if defined(CONFIG_USER_ONLY)
4281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4282 #else
4283 if (unlikely(!ctx->mem_idx)) {
4284 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4285 return;
4286 }
4287 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4288 cpu_gpr[rB(ctx->opcode)]);
4289 #endif
4290 }
4291
4292 static void gen_slbmfev(DisasContext *ctx)
4293 {
4294 #if defined(CONFIG_USER_ONLY)
4295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4296 #else
4297 if (unlikely(!ctx->mem_idx)) {
4298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4299 return;
4300 }
4301 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4302 cpu_gpr[rB(ctx->opcode)]);
4303 #endif
4304 }
4305 #endif /* defined(TARGET_PPC64) */
4306
4307 /*** Lookaside buffer management ***/
4308 /* Optional & mem_idx only: */
4309
4310 /* tlbia */
4311 static void gen_tlbia(DisasContext *ctx)
4312 {
4313 #if defined(CONFIG_USER_ONLY)
4314 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4315 #else
4316 if (unlikely(!ctx->mem_idx)) {
4317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4318 return;
4319 }
4320 gen_helper_tlbia(cpu_env);
4321 #endif
4322 }
4323
4324 /* tlbiel */
4325 static void gen_tlbiel(DisasContext *ctx)
4326 {
4327 #if defined(CONFIG_USER_ONLY)
4328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4329 #else
4330 if (unlikely(!ctx->mem_idx)) {
4331 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4332 return;
4333 }
4334 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4335 #endif
4336 }
4337
4338 /* tlbie */
4339 static void gen_tlbie(DisasContext *ctx)
4340 {
4341 #if defined(CONFIG_USER_ONLY)
4342 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4343 #else
4344 if (unlikely(!ctx->mem_idx)) {
4345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4346 return;
4347 }
4348 #if defined(TARGET_PPC64)
4349 if (!ctx->sf_mode) {
4350 TCGv t0 = tcg_temp_new();
4351 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4352 gen_helper_tlbie(cpu_env, t0);
4353 tcg_temp_free(t0);
4354 } else
4355 #endif
4356 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4357 #endif
4358 }
4359
4360 /* tlbsync */
4361 static void gen_tlbsync(DisasContext *ctx)
4362 {
4363 #if defined(CONFIG_USER_ONLY)
4364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4365 #else
4366 if (unlikely(!ctx->mem_idx)) {
4367 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4368 return;
4369 }
4370 /* This has no effect: it should ensure that all previous
4371 * tlbie have completed
4372 */
4373 gen_stop_exception(ctx);
4374 #endif
4375 }
4376
4377 #if defined(TARGET_PPC64)
4378 /* slbia */
4379 static void gen_slbia(DisasContext *ctx)
4380 {
4381 #if defined(CONFIG_USER_ONLY)
4382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4383 #else
4384 if (unlikely(!ctx->mem_idx)) {
4385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4386 return;
4387 }
4388 gen_helper_slbia(cpu_env);
4389 #endif
4390 }
4391
4392 /* slbie */
4393 static void gen_slbie(DisasContext *ctx)
4394 {
4395 #if defined(CONFIG_USER_ONLY)
4396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4397 #else
4398 if (unlikely(!ctx->mem_idx)) {
4399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4400 return;
4401 }
4402 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4403 #endif
4404 }
4405 #endif
4406
4407 /*** External control ***/
4408 /* Optional: */
4409
4410 /* eciwx */
4411 static void gen_eciwx(DisasContext *ctx)
4412 {
4413 TCGv t0;
4414 /* Should check EAR[E] ! */
4415 gen_set_access_type(ctx, ACCESS_EXT);
4416 t0 = tcg_temp_new();
4417 gen_addr_reg_index(ctx, t0);
4418 gen_check_align(ctx, t0, 0x03);
4419 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4420 tcg_temp_free(t0);
4421 }
4422
4423 /* ecowx */
4424 static void gen_ecowx(DisasContext *ctx)
4425 {
4426 TCGv t0;
4427 /* Should check EAR[E] ! */
4428 gen_set_access_type(ctx, ACCESS_EXT);
4429 t0 = tcg_temp_new();
4430 gen_addr_reg_index(ctx, t0);
4431 gen_check_align(ctx, t0, 0x03);
4432 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4433 tcg_temp_free(t0);
4434 }
4435
4436 /* PowerPC 601 specific instructions */
4437
4438 /* abs - abs. */
4439 static void gen_abs(DisasContext *ctx)
4440 {
4441 int l1 = gen_new_label();
4442 int l2 = gen_new_label();
4443 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4444 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4445 tcg_gen_br(l2);
4446 gen_set_label(l1);
4447 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4448 gen_set_label(l2);
4449 if (unlikely(Rc(ctx->opcode) != 0))
4450 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4451 }
4452
4453 /* abso - abso. */
4454 static void gen_abso(DisasContext *ctx)
4455 {
4456 int l1 = gen_new_label();
4457 int l2 = gen_new_label();
4458 int l3 = gen_new_label();
4459 /* Start with XER OV disabled, the most likely case */
4460 tcg_gen_movi_tl(cpu_ov, 0);
4461 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4462 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4463 tcg_gen_movi_tl(cpu_ov, 1);
4464 tcg_gen_movi_tl(cpu_so, 1);
4465 tcg_gen_br(l2);
4466 gen_set_label(l1);
4467 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4468 tcg_gen_br(l3);
4469 gen_set_label(l2);
4470 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4471 gen_set_label(l3);
4472 if (unlikely(Rc(ctx->opcode) != 0))
4473 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4474 }
4475
4476 /* clcs */
4477 static void gen_clcs(DisasContext *ctx)
4478 {
4479 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4480 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4481 tcg_temp_free_i32(t0);
4482 /* Rc=1 sets CR0 to an undefined state */
4483 }
4484
4485 /* div - div. */
4486 static void gen_div(DisasContext *ctx)
4487 {
4488 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4489 cpu_gpr[rB(ctx->opcode)]);
4490 if (unlikely(Rc(ctx->opcode) != 0))
4491 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4492 }
4493
4494 /* divo - divo. */
4495 static void gen_divo(DisasContext *ctx)
4496 {
4497 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4498 cpu_gpr[rB(ctx->opcode)]);
4499 if (unlikely(Rc(ctx->opcode) != 0))
4500 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4501 }
4502
4503 /* divs - divs. */
4504 static void gen_divs(DisasContext *ctx)
4505 {
4506 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4507 cpu_gpr[rB(ctx->opcode)]);
4508 if (unlikely(Rc(ctx->opcode) != 0))
4509 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4510 }
4511
4512 /* divso - divso. */
4513 static void gen_divso(DisasContext *ctx)
4514 {
4515 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4516 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4517 if (unlikely(Rc(ctx->opcode) != 0))
4518 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4519 }
4520
4521 /* doz - doz. */
4522 static void gen_doz(DisasContext *ctx)
4523 {
4524 int l1 = gen_new_label();
4525 int l2 = gen_new_label();
4526 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4527 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4528 tcg_gen_br(l2);
4529 gen_set_label(l1);
4530 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4531 gen_set_label(l2);
4532 if (unlikely(Rc(ctx->opcode) != 0))
4533 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4534 }
4535
4536 /* dozo - dozo. */
4537 static void gen_dozo(DisasContext *ctx)
4538 {
4539 int l1 = gen_new_label();
4540 int l2 = gen_new_label();
4541 TCGv t0 = tcg_temp_new();
4542 TCGv t1 = tcg_temp_new();
4543 TCGv t2 = tcg_temp_new();
4544 /* Start with XER OV disabled, the most likely case */
4545 tcg_gen_movi_tl(cpu_ov, 0);
4546 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4547 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4548 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4549 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4550 tcg_gen_andc_tl(t1, t1, t2);
4551 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4552 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4553 tcg_gen_movi_tl(cpu_ov, 1);
4554 tcg_gen_movi_tl(cpu_so, 1);
4555 tcg_gen_br(l2);
4556 gen_set_label(l1);
4557 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4558 gen_set_label(l2);
4559 tcg_temp_free(t0);
4560 tcg_temp_free(t1);
4561 tcg_temp_free(t2);
4562 if (unlikely(Rc(ctx->opcode) != 0))
4563 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4564 }
4565
4566 /* dozi */
4567 static void gen_dozi(DisasContext *ctx)
4568 {
4569 target_long simm = SIMM(ctx->opcode);
4570 int l1 = gen_new_label();
4571 int l2 = gen_new_label();
4572 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4573 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4574 tcg_gen_br(l2);
4575 gen_set_label(l1);
4576 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4577 gen_set_label(l2);
4578 if (unlikely(Rc(ctx->opcode) != 0))
4579 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4580 }
4581
4582 /* lscbx - lscbx. */
4583 static void gen_lscbx(DisasContext *ctx)
4584 {
4585 TCGv t0 = tcg_temp_new();
4586 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4587 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4588 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4589
4590 gen_addr_reg_index(ctx, t0);
4591 /* NIP cannot be restored if the memory exception comes from an helper */
4592 gen_update_nip(ctx, ctx->nip - 4);
4593 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4594 tcg_temp_free_i32(t1);
4595 tcg_temp_free_i32(t2);
4596 tcg_temp_free_i32(t3);
4597 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4598 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4599 if (unlikely(Rc(ctx->opcode) != 0))
4600 gen_set_Rc0(ctx, t0);
4601 tcg_temp_free(t0);
4602 }
4603
4604 /* maskg - maskg. */
4605 static void gen_maskg(DisasContext *ctx)
4606 {
4607 int l1 = gen_new_label();
4608 TCGv t0 = tcg_temp_new();
4609 TCGv t1 = tcg_temp_new();
4610 TCGv t2 = tcg_temp_new();
4611 TCGv t3 = tcg_temp_new();
4612 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4613 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4614 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4615 tcg_gen_addi_tl(t2, t0, 1);
4616 tcg_gen_shr_tl(t2, t3, t2);
4617 tcg_gen_shr_tl(t3, t3, t1);
4618 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4619 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4620 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4621 gen_set_label(l1);
4622 tcg_temp_free(t0);
4623 tcg_temp_free(t1);
4624 tcg_temp_free(t2);
4625 tcg_temp_free(t3);
4626 if (unlikely(Rc(ctx->opcode) != 0))
4627 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4628 }
4629
4630 /* maskir - maskir. */
4631 static void gen_maskir(DisasContext *ctx)
4632 {
4633 TCGv t0 = tcg_temp_new();
4634 TCGv t1 = tcg_temp_new();
4635 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4636 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4637 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4638 tcg_temp_free(t0);
4639 tcg_temp_free(t1);
4640 if (unlikely(Rc(ctx->opcode) != 0))
4641 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4642 }
4643
4644 /* mul - mul. */
4645 static void gen_mul(DisasContext *ctx)
4646 {
4647 TCGv_i64 t0 = tcg_temp_new_i64();
4648 TCGv_i64 t1 = tcg_temp_new_i64();
4649 TCGv t2 = tcg_temp_new();
4650 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4651 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4652 tcg_gen_mul_i64(t0, t0, t1);
4653 tcg_gen_trunc_i64_tl(t2, t0);
4654 gen_store_spr(SPR_MQ, t2);
4655 tcg_gen_shri_i64(t1, t0, 32);
4656 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4657 tcg_temp_free_i64(t0);
4658 tcg_temp_free_i64(t1);
4659 tcg_temp_free(t2);
4660 if (unlikely(Rc(ctx->opcode) != 0))
4661 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4662 }
4663
4664 /* mulo - mulo. */
4665 static void gen_mulo(DisasContext *ctx)
4666 {
4667 int l1 = gen_new_label();
4668 TCGv_i64 t0 = tcg_temp_new_i64();
4669 TCGv_i64 t1 = tcg_temp_new_i64();
4670 TCGv t2 = tcg_temp_new();
4671 /* Start with XER OV disabled, the most likely case */
4672 tcg_gen_movi_tl(cpu_ov, 0);
4673 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4674 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4675 tcg_gen_mul_i64(t0, t0, t1);
4676 tcg_gen_trunc_i64_tl(t2, t0);
4677 gen_store_spr(SPR_MQ, t2);
4678 tcg_gen_shri_i64(t1, t0, 32);
4679 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4680 tcg_gen_ext32s_i64(t1, t0);
4681 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4682 tcg_gen_movi_tl(cpu_ov, 1);
4683 tcg_gen_movi_tl(cpu_so, 1);
4684 gen_set_label(l1);
4685 tcg_temp_free_i64(t0);
4686 tcg_temp_free_i64(t1);
4687 tcg_temp_free(t2);
4688 if (unlikely(Rc(ctx->opcode) != 0))
4689 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4690 }
4691
4692 /* nabs - nabs. */
4693 static void gen_nabs(DisasContext *ctx)
4694 {
4695 int l1 = gen_new_label();
4696 int l2 = gen_new_label();
4697 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4698 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4699 tcg_gen_br(l2);
4700 gen_set_label(l1);
4701 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4702 gen_set_label(l2);
4703 if (unlikely(Rc(ctx->opcode) != 0))
4704 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4705 }
4706
4707 /* nabso - nabso. */
4708 static void gen_nabso(DisasContext *ctx)
4709 {
4710 int l1 = gen_new_label();
4711 int l2 = gen_new_label();
4712 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4713 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4714 tcg_gen_br(l2);
4715 gen_set_label(l1);
4716 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4717 gen_set_label(l2);
4718 /* nabs never overflows */
4719 tcg_gen_movi_tl(cpu_ov, 0);
4720 if (unlikely(Rc(ctx->opcode) != 0))
4721 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4722 }
4723
4724 /* rlmi - rlmi. */
4725 static void gen_rlmi(DisasContext *ctx)
4726 {
4727 uint32_t mb = MB(ctx->opcode);
4728 uint32_t me = ME(ctx->opcode);
4729 TCGv t0 = tcg_temp_new();
4730 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4731 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4732 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4733 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4734 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4735 tcg_temp_free(t0);
4736 if (unlikely(Rc(ctx->opcode) != 0))
4737 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4738 }
4739
4740 /* rrib - rrib. */
4741 static void gen_rrib(DisasContext *ctx)
4742 {
4743 TCGv t0 = tcg_temp_new();
4744 TCGv t1 = tcg_temp_new();
4745 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4746 tcg_gen_movi_tl(t1, 0x80000000);
4747 tcg_gen_shr_tl(t1, t1, t0);
4748 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4749 tcg_gen_and_tl(t0, t0, t1);
4750 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4751 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4752 tcg_temp_free(t0);
4753 tcg_temp_free(t1);
4754 if (unlikely(Rc(ctx->opcode) != 0))
4755 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4756 }
4757
4758 /* sle - sle. */
4759 static void gen_sle(DisasContext *ctx)
4760 {
4761 TCGv t0 = tcg_temp_new();
4762 TCGv t1 = tcg_temp_new();
4763 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4764 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4765 tcg_gen_subfi_tl(t1, 32, t1);
4766 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4767 tcg_gen_or_tl(t1, t0, t1);
4768 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4769 gen_store_spr(SPR_MQ, t1);
4770 tcg_temp_free(t0);
4771 tcg_temp_free(t1);
4772 if (unlikely(Rc(ctx->opcode) != 0))
4773 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4774 }
4775
4776 /* sleq - sleq. */
4777 static void gen_sleq(DisasContext *ctx)
4778 {
4779 TCGv t0 = tcg_temp_new();
4780 TCGv t1 = tcg_temp_new();
4781 TCGv t2 = tcg_temp_new();
4782 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4783 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4784 tcg_gen_shl_tl(t2, t2, t0);
4785 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4786 gen_load_spr(t1, SPR_MQ);
4787 gen_store_spr(SPR_MQ, t0);
4788 tcg_gen_and_tl(t0, t0, t2);
4789 tcg_gen_andc_tl(t1, t1, t2);
4790 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4791 tcg_temp_free(t0);
4792 tcg_temp_free(t1);
4793 tcg_temp_free(t2);
4794 if (unlikely(Rc(ctx->opcode) != 0))
4795 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4796 }
4797
4798 /* sliq - sliq. */
4799 static void gen_sliq(DisasContext *ctx)
4800 {
4801 int sh = SH(ctx->opcode);
4802 TCGv t0 = tcg_temp_new();
4803 TCGv t1 = tcg_temp_new();
4804 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4805 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4806 tcg_gen_or_tl(t1, t0, t1);
4807 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4808 gen_store_spr(SPR_MQ, t1);
4809 tcg_temp_free(t0);
4810 tcg_temp_free(t1);
4811 if (unlikely(Rc(ctx->opcode) != 0))
4812 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4813 }
4814
4815 /* slliq - slliq. */
4816 static void gen_slliq(DisasContext *ctx)
4817 {
4818 int sh = SH(ctx->opcode);
4819 TCGv t0 = tcg_temp_new();
4820 TCGv t1 = tcg_temp_new();
4821 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4822 gen_load_spr(t1, SPR_MQ);
4823 gen_store_spr(SPR_MQ, t0);
4824 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4825 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4826 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4827 tcg_temp_free(t0);
4828 tcg_temp_free(t1);
4829 if (unlikely(Rc(ctx->opcode) != 0))
4830 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4831 }
4832
4833 /* sllq - sllq. */
4834 static void gen_sllq(DisasContext *ctx)
4835 {
4836 int l1 = gen_new_label();
4837 int l2 = gen_new_label();
4838 TCGv t0 = tcg_temp_local_new();
4839 TCGv t1 = tcg_temp_local_new();
4840 TCGv t2 = tcg_temp_local_new();
4841 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4842 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4843 tcg_gen_shl_tl(t1, t1, t2);
4844 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4845 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4846 gen_load_spr(t0, SPR_MQ);
4847 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4848 tcg_gen_br(l2);
4849 gen_set_label(l1);
4850 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4851 gen_load_spr(t2, SPR_MQ);
4852 tcg_gen_andc_tl(t1, t2, t1);
4853 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4854 gen_set_label(l2);
4855 tcg_temp_free(t0);
4856 tcg_temp_free(t1);
4857 tcg_temp_free(t2);
4858 if (unlikely(Rc(ctx->opcode) != 0))
4859 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4860 }
4861
4862 /* slq - slq. */
4863 static void gen_slq(DisasContext *ctx)
4864 {
4865 int l1 = gen_new_label();
4866 TCGv t0 = tcg_temp_new();
4867 TCGv t1 = tcg_temp_new();
4868 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4869 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4870 tcg_gen_subfi_tl(t1, 32, t1);
4871 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4872 tcg_gen_or_tl(t1, t0, t1);
4873 gen_store_spr(SPR_MQ, t1);
4874 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4875 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4876 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4877 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4878 gen_set_label(l1);
4879 tcg_temp_free(t0);
4880 tcg_temp_free(t1);
4881 if (unlikely(Rc(ctx->opcode) != 0))
4882 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4883 }
4884
4885 /* sraiq - sraiq. */
4886 static void gen_sraiq(DisasContext *ctx)
4887 {
4888 int sh = SH(ctx->opcode);
4889 int l1 = gen_new_label();
4890 TCGv t0 = tcg_temp_new();
4891 TCGv t1 = tcg_temp_new();
4892 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4893 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4894 tcg_gen_or_tl(t0, t0, t1);
4895 gen_store_spr(SPR_MQ, t0);
4896 tcg_gen_movi_tl(cpu_ca, 0);
4897 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4898 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4899 tcg_gen_movi_tl(cpu_ca, 1);
4900 gen_set_label(l1);
4901 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4902 tcg_temp_free(t0);
4903 tcg_temp_free(t1);
4904 if (unlikely(Rc(ctx->opcode) != 0))
4905 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4906 }
4907
4908 /* sraq - sraq. */
4909 static void gen_sraq(DisasContext *ctx)
4910 {
4911 int l1 = gen_new_label();
4912 int l2 = gen_new_label();
4913 TCGv t0 = tcg_temp_new();
4914 TCGv t1 = tcg_temp_local_new();
4915 TCGv t2 = tcg_temp_local_new();
4916 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4917 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4918 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4919 tcg_gen_subfi_tl(t2, 32, t2);
4920 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4921 tcg_gen_or_tl(t0, t0, t2);
4922 gen_store_spr(SPR_MQ, t0);
4923 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4924 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4925 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4926 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4927 gen_set_label(l1);
4928 tcg_temp_free(t0);
4929 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4930 tcg_gen_movi_tl(cpu_ca, 0);
4931 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4932 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4933 tcg_gen_movi_tl(cpu_ca, 1);
4934 gen_set_label(l2);
4935 tcg_temp_free(t1);
4936 tcg_temp_free(t2);
4937 if (unlikely(Rc(ctx->opcode) != 0))
4938 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4939 }
4940
4941 /* sre - sre. */
4942 static void gen_sre(DisasContext *ctx)
4943 {
4944 TCGv t0 = tcg_temp_new();
4945 TCGv t1 = tcg_temp_new();
4946 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4947 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4948 tcg_gen_subfi_tl(t1, 32, t1);
4949 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4950 tcg_gen_or_tl(t1, t0, t1);
4951 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4952 gen_store_spr(SPR_MQ, t1);
4953 tcg_temp_free(t0);
4954 tcg_temp_free(t1);
4955 if (unlikely(Rc(ctx->opcode) != 0))
4956 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4957 }
4958
4959 /* srea - srea. */
4960 static void gen_srea(DisasContext *ctx)
4961 {
4962 TCGv t0 = tcg_temp_new();
4963 TCGv t1 = tcg_temp_new();
4964 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4965 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4966 gen_store_spr(SPR_MQ, t0);
4967 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4968 tcg_temp_free(t0);
4969 tcg_temp_free(t1);
4970 if (unlikely(Rc(ctx->opcode) != 0))
4971 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4972 }
4973
4974 /* sreq */
4975 static void gen_sreq(DisasContext *ctx)
4976 {
4977 TCGv t0 = tcg_temp_new();
4978 TCGv t1 = tcg_temp_new();
4979 TCGv t2 = tcg_temp_new();
4980 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4981 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4982 tcg_gen_shr_tl(t1, t1, t0);
4983 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4984 gen_load_spr(t2, SPR_MQ);
4985 gen_store_spr(SPR_MQ, t0);
4986 tcg_gen_and_tl(t0, t0, t1);
4987 tcg_gen_andc_tl(t2, t2, t1);
4988 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4989 tcg_temp_free(t0);
4990 tcg_temp_free(t1);
4991 tcg_temp_free(t2);
4992 if (unlikely(Rc(ctx->opcode) != 0))
4993 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4994 }
4995
4996 /* sriq */
4997 static void gen_sriq(DisasContext *ctx)
4998 {
4999 int sh = SH(ctx->opcode);
5000 TCGv t0 = tcg_temp_new();
5001 TCGv t1 = tcg_temp_new();
5002 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5003 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5004 tcg_gen_or_tl(t1, t0, t1);
5005 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5006 gen_store_spr(SPR_MQ, t1);
5007 tcg_temp_free(t0);
5008 tcg_temp_free(t1);
5009 if (unlikely(Rc(ctx->opcode) != 0))
5010 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5011 }
5012
5013 /* srliq */
5014 static void gen_srliq(DisasContext *ctx)
5015 {
5016 int sh = SH(ctx->opcode);
5017 TCGv t0 = tcg_temp_new();
5018 TCGv t1 = tcg_temp_new();
5019 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5020 gen_load_spr(t1, SPR_MQ);
5021 gen_store_spr(SPR_MQ, t0);
5022 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5023 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5024 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5025 tcg_temp_free(t0);
5026 tcg_temp_free(t1);
5027 if (unlikely(Rc(ctx->opcode) != 0))
5028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5029 }
5030
5031 /* srlq */
5032 static void gen_srlq(DisasContext *ctx)
5033 {
5034 int l1 = gen_new_label();
5035 int l2 = gen_new_label();
5036 TCGv t0 = tcg_temp_local_new();
5037 TCGv t1 = tcg_temp_local_new();
5038 TCGv t2 = tcg_temp_local_new();
5039 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5040 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5041 tcg_gen_shr_tl(t2, t1, t2);
5042 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5043 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5044 gen_load_spr(t0, SPR_MQ);
5045 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5046 tcg_gen_br(l2);
5047 gen_set_label(l1);
5048 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5049 tcg_gen_and_tl(t0, t0, t2);
5050 gen_load_spr(t1, SPR_MQ);
5051 tcg_gen_andc_tl(t1, t1, t2);
5052 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5053 gen_set_label(l2);
5054 tcg_temp_free(t0);
5055 tcg_temp_free(t1);
5056 tcg_temp_free(t2);
5057 if (unlikely(Rc(ctx->opcode) != 0))
5058 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5059 }
5060
5061 /* srq */
5062 static void gen_srq(DisasContext *ctx)
5063 {
5064 int l1 = gen_new_label();
5065 TCGv t0 = tcg_temp_new();
5066 TCGv t1 = tcg_temp_new();
5067 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5068 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5069 tcg_gen_subfi_tl(t1, 32, t1);
5070 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5071 tcg_gen_or_tl(t1, t0, t1);
5072 gen_store_spr(SPR_MQ, t1);
5073 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5074 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5075 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5076 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5077 gen_set_label(l1);
5078 tcg_temp_free(t0);
5079 tcg_temp_free(t1);
5080 if (unlikely(Rc(ctx->opcode) != 0))
5081 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5082 }
5083
5084 /* PowerPC 602 specific instructions */
5085
5086 /* dsa */
5087 static void gen_dsa(DisasContext *ctx)
5088 {
5089 /* XXX: TODO */
5090 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5091 }
5092
5093 /* esa */
5094 static void gen_esa(DisasContext *ctx)
5095 {
5096 /* XXX: TODO */
5097 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5098 }
5099
5100 /* mfrom */
5101 static void gen_mfrom(DisasContext *ctx)
5102 {
5103 #if defined(CONFIG_USER_ONLY)
5104 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5105 #else
5106 if (unlikely(!ctx->mem_idx)) {
5107 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5108 return;
5109 }
5110 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5111 #endif
5112 }
5113
5114 /* 602 - 603 - G2 TLB management */
5115
5116 /* tlbld */
5117 static void gen_tlbld_6xx(DisasContext *ctx)
5118 {
5119 #if defined(CONFIG_USER_ONLY)
5120 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5121 #else
5122 if (unlikely(!ctx->mem_idx)) {
5123 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5124 return;
5125 }
5126 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5127 #endif
5128 }
5129
5130 /* tlbli */
5131 static void gen_tlbli_6xx(DisasContext *ctx)
5132 {
5133 #if defined(CONFIG_USER_ONLY)
5134 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5135 #else
5136 if (unlikely(!ctx->mem_idx)) {
5137 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5138 return;
5139 }
5140 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5141 #endif
5142 }
5143
5144 /* 74xx TLB management */
5145
5146 /* tlbld */
5147 static void gen_tlbld_74xx(DisasContext *ctx)
5148 {
5149 #if defined(CONFIG_USER_ONLY)
5150 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5151 #else
5152 if (unlikely(!ctx->mem_idx)) {
5153 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5154 return;
5155 }
5156 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5157 #endif
5158 }
5159
5160 /* tlbli */
5161 static void gen_tlbli_74xx(DisasContext *ctx)
5162 {
5163 #if defined(CONFIG_USER_ONLY)
5164 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5165 #else
5166 if (unlikely(!ctx->mem_idx)) {
5167 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5168 return;
5169 }
5170 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5171 #endif
5172 }
5173
5174 /* POWER instructions not in PowerPC 601 */
5175
5176 /* clf */
5177 static void gen_clf(DisasContext *ctx)
5178 {
5179 /* Cache line flush: implemented as no-op */
5180 }
5181
5182 /* cli */
5183 static void gen_cli(DisasContext *ctx)
5184 {
5185 /* Cache line invalidate: privileged and treated as no-op */
5186 #if defined(CONFIG_USER_ONLY)
5187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5188 #else
5189 if (unlikely(!ctx->mem_idx)) {
5190 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5191 return;
5192 }
5193 #endif
5194 }
5195
5196 /* dclst */
5197 static void gen_dclst(DisasContext *ctx)
5198 {
5199 /* Data cache line store: treated as no-op */
5200 }
5201
5202 static void gen_mfsri(DisasContext *ctx)
5203 {
5204 #if defined(CONFIG_USER_ONLY)
5205 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5206 #else
5207 int ra = rA(ctx->opcode);
5208 int rd = rD(ctx->opcode);
5209 TCGv t0;
5210 if (unlikely(!ctx->mem_idx)) {
5211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5212 return;
5213 }
5214 t0 = tcg_temp_new();
5215 gen_addr_reg_index(ctx, t0);
5216 tcg_gen_shri_tl(t0, t0, 28);
5217 tcg_gen_andi_tl(t0, t0, 0xF);
5218 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5219 tcg_temp_free(t0);
5220 if (ra != 0 && ra != rd)
5221 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5222 #endif
5223 }
5224
5225 static void gen_rac(DisasContext *ctx)
5226 {
5227 #if defined(CONFIG_USER_ONLY)
5228 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5229 #else
5230 TCGv t0;
5231 if (unlikely(!ctx->mem_idx)) {
5232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5233 return;
5234 }
5235 t0 = tcg_temp_new();
5236 gen_addr_reg_index(ctx, t0);
5237 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5238 tcg_temp_free(t0);
5239 #endif
5240 }
5241
5242 static void gen_rfsvc(DisasContext *ctx)
5243 {
5244 #if defined(CONFIG_USER_ONLY)
5245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5246 #else
5247 if (unlikely(!ctx->mem_idx)) {
5248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5249 return;
5250 }
5251 gen_helper_rfsvc(cpu_env);
5252 gen_sync_exception(ctx);
5253 #endif
5254 }
5255
5256 /* svc is not implemented for now */
5257
5258 /* POWER2 specific instructions */
5259 /* Quad manipulation (load/store two floats at a time) */
5260
5261 /* lfq */
5262 static void gen_lfq(DisasContext *ctx)
5263 {
5264 int rd = rD(ctx->opcode);
5265 TCGv t0;
5266 gen_set_access_type(ctx, ACCESS_FLOAT);
5267 t0 = tcg_temp_new();
5268 gen_addr_imm_index(ctx, t0, 0);
5269 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5270 gen_addr_add(ctx, t0, t0, 8);
5271 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5272 tcg_temp_free(t0);
5273 }
5274
5275 /* lfqu */
5276 static void gen_lfqu(DisasContext *ctx)
5277 {
5278 int ra = rA(ctx->opcode);
5279 int rd = rD(ctx->opcode);
5280 TCGv t0, t1;
5281 gen_set_access_type(ctx, ACCESS_FLOAT);
5282 t0 = tcg_temp_new();
5283 t1 = tcg_temp_new();
5284 gen_addr_imm_index(ctx, t0, 0);
5285 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5286 gen_addr_add(ctx, t1, t0, 8);
5287 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5288 if (ra != 0)
5289 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5290 tcg_temp_free(t0);
5291 tcg_temp_free(t1);
5292 }
5293
5294 /* lfqux */
5295 static void gen_lfqux(DisasContext *ctx)
5296 {
5297 int ra = rA(ctx->opcode);
5298 int rd = rD(ctx->opcode);
5299 gen_set_access_type(ctx, ACCESS_FLOAT);
5300 TCGv t0, t1;
5301 t0 = tcg_temp_new();
5302 gen_addr_reg_index(ctx, t0);
5303 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5304 t1 = tcg_temp_new();
5305 gen_addr_add(ctx, t1, t0, 8);
5306 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5307 tcg_temp_free(t1);
5308 if (ra != 0)
5309 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5310 tcg_temp_free(t0);
5311 }
5312
5313 /* lfqx */
5314 static void gen_lfqx(DisasContext *ctx)
5315 {
5316 int rd = rD(ctx->opcode);
5317 TCGv t0;
5318 gen_set_access_type(ctx, ACCESS_FLOAT);
5319 t0 = tcg_temp_new();
5320 gen_addr_reg_index(ctx, t0);
5321 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5322 gen_addr_add(ctx, t0, t0, 8);
5323 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5324 tcg_temp_free(t0);
5325 }
5326
5327 /* stfq */
5328 static void gen_stfq(DisasContext *ctx)
5329 {
5330 int rd = rD(ctx->opcode);
5331 TCGv t0;
5332 gen_set_access_type(ctx, ACCESS_FLOAT);
5333 t0 = tcg_temp_new();
5334 gen_addr_imm_index(ctx, t0, 0);
5335 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5336 gen_addr_add(ctx, t0, t0, 8);
5337 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5338 tcg_temp_free(t0);
5339 }
5340
5341 /* stfqu */
5342 static void gen_stfqu(DisasContext *ctx)
5343 {
5344 int ra = rA(ctx->opcode);
5345 int rd = rD(ctx->opcode);
5346 TCGv t0, t1;
5347 gen_set_access_type(ctx, ACCESS_FLOAT);
5348 t0 = tcg_temp_new();
5349 gen_addr_imm_index(ctx, t0, 0);
5350 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5351 t1 = tcg_temp_new();
5352 gen_addr_add(ctx, t1, t0, 8);
5353 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5354 tcg_temp_free(t1);
5355 if (ra != 0)
5356 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5357 tcg_temp_free(t0);
5358 }
5359
5360 /* stfqux */
5361 static void gen_stfqux(DisasContext *ctx)
5362 {
5363 int ra = rA(ctx->opcode);
5364 int rd = rD(ctx->opcode);
5365 TCGv t0, t1;
5366 gen_set_access_type(ctx, ACCESS_FLOAT);
5367 t0 = tcg_temp_new();
5368 gen_addr_reg_index(ctx, t0);
5369 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5370 t1 = tcg_temp_new();
5371 gen_addr_add(ctx, t1, t0, 8);
5372 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5373 tcg_temp_free(t1);
5374 if (ra != 0)
5375 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5376 tcg_temp_free(t0);
5377 }
5378
5379 /* stfqx */
5380 static void gen_stfqx(DisasContext *ctx)
5381 {
5382 int rd = rD(ctx->opcode);
5383 TCGv t0;
5384 gen_set_access_type(ctx, ACCESS_FLOAT);
5385 t0 = tcg_temp_new();
5386 gen_addr_reg_index(ctx, t0);
5387 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5388 gen_addr_add(ctx, t0, t0, 8);
5389 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5390 tcg_temp_free(t0);
5391 }
5392
5393 /* BookE specific instructions */
5394
5395 /* XXX: not implemented on 440 ? */
5396 static void gen_mfapidi(DisasContext *ctx)
5397 {
5398 /* XXX: TODO */
5399 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5400 }
5401
5402 /* XXX: not implemented on 440 ? */
5403 static void gen_tlbiva(DisasContext *ctx)
5404 {
5405 #if defined(CONFIG_USER_ONLY)
5406 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5407 #else
5408 TCGv t0;
5409 if (unlikely(!ctx->mem_idx)) {
5410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5411 return;
5412 }
5413 t0 = tcg_temp_new();
5414 gen_addr_reg_index(ctx, t0);
5415 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5416 tcg_temp_free(t0);
5417 #endif
5418 }
5419
5420 /* All 405 MAC instructions are translated here */
5421 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5422 int ra, int rb, int rt, int Rc)
5423 {
5424 TCGv t0, t1;
5425
5426 t0 = tcg_temp_local_new();
5427 t1 = tcg_temp_local_new();
5428
5429 switch (opc3 & 0x0D) {
5430 case 0x05:
5431 /* macchw - macchw. - macchwo - macchwo. */
5432 /* macchws - macchws. - macchwso - macchwso. */
5433 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5434 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5435 /* mulchw - mulchw. */
5436 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5437 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5438 tcg_gen_ext16s_tl(t1, t1);
5439 break;
5440 case 0x04:
5441 /* macchwu - macchwu. - macchwuo - macchwuo. */
5442 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5443 /* mulchwu - mulchwu. */
5444 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5445 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5446 tcg_gen_ext16u_tl(t1, t1);
5447 break;
5448 case 0x01:
5449 /* machhw - machhw. - machhwo - machhwo. */
5450 /* machhws - machhws. - machhwso - machhwso. */
5451 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5452 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5453 /* mulhhw - mulhhw. */
5454 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5455 tcg_gen_ext16s_tl(t0, t0);
5456 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5457 tcg_gen_ext16s_tl(t1, t1);
5458 break;
5459 case 0x00:
5460 /* machhwu - machhwu. - machhwuo - machhwuo. */
5461 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5462 /* mulhhwu - mulhhwu. */
5463 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5464 tcg_gen_ext16u_tl(t0, t0);
5465 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5466 tcg_gen_ext16u_tl(t1, t1);
5467 break;
5468 case 0x0D:
5469 /* maclhw - maclhw. - maclhwo - maclhwo. */
5470 /* maclhws - maclhws. - maclhwso - maclhwso. */
5471 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5472 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5473 /* mullhw - mullhw. */
5474 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5475 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5476 break;
5477 case 0x0C:
5478 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5479 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5480 /* mullhwu - mullhwu. */
5481 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5482 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5483 break;
5484 }
5485 if (opc2 & 0x04) {
5486 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5487 tcg_gen_mul_tl(t1, t0, t1);
5488 if (opc2 & 0x02) {
5489 /* nmultiply-and-accumulate (0x0E) */
5490 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5491 } else {
5492 /* multiply-and-accumulate (0x0C) */
5493 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5494 }
5495
5496 if (opc3 & 0x12) {
5497 /* Check overflow and/or saturate */
5498 int l1 = gen_new_label();
5499
5500 if (opc3 & 0x10) {
5501 /* Start with XER OV disabled, the most likely case */
5502 tcg_gen_movi_tl(cpu_ov, 0);
5503 }
5504 if (opc3 & 0x01) {
5505 /* Signed */
5506 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5507 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5508 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5509 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5510 if (opc3 & 0x02) {
5511 /* Saturate */
5512 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5513 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5514 }
5515 } else {
5516 /* Unsigned */
5517 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5518 if (opc3 & 0x02) {
5519 /* Saturate */
5520 tcg_gen_movi_tl(t0, UINT32_MAX);
5521 }
5522 }
5523 if (opc3 & 0x10) {
5524 /* Check overflow */
5525 tcg_gen_movi_tl(cpu_ov, 1);
5526 tcg_gen_movi_tl(cpu_so, 1);
5527 }
5528 gen_set_label(l1);
5529 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5530 }
5531 } else {
5532 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5533 }
5534 tcg_temp_free(t0);
5535 tcg_temp_free(t1);
5536 if (unlikely(Rc) != 0) {
5537 /* Update Rc0 */
5538 gen_set_Rc0(ctx, cpu_gpr[rt]);
5539 }
5540 }
5541
5542 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5543 static void glue(gen_, name)(DisasContext *ctx) \
5544 { \
5545 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5546 rD(ctx->opcode), Rc(ctx->opcode)); \
5547 }
5548
5549 /* macchw - macchw. */
5550 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5551 /* macchwo - macchwo. */
5552 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5553 /* macchws - macchws. */
5554 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5555 /* macchwso - macchwso. */
5556 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5557 /* macchwsu - macchwsu. */
5558 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5559 /* macchwsuo - macchwsuo. */
5560 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5561 /* macchwu - macchwu. */
5562 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5563 /* macchwuo - macchwuo. */
5564 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5565 /* machhw - machhw. */
5566 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5567 /* machhwo - machhwo. */
5568 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5569 /* machhws - machhws. */
5570 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5571 /* machhwso - machhwso. */
5572 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5573 /* machhwsu - machhwsu. */
5574 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5575 /* machhwsuo - machhwsuo. */
5576 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5577 /* machhwu - machhwu. */
5578 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5579 /* machhwuo - machhwuo. */
5580 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5581 /* maclhw - maclhw. */
5582 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5583 /* maclhwo - maclhwo. */
5584 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5585 /* maclhws - maclhws. */
5586 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5587 /* maclhwso - maclhwso. */
5588 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5589 /* maclhwu - maclhwu. */
5590 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5591 /* maclhwuo - maclhwuo. */
5592 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5593 /* maclhwsu - maclhwsu. */
5594 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5595 /* maclhwsuo - maclhwsuo. */
5596 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5597 /* nmacchw - nmacchw. */
5598 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5599 /* nmacchwo - nmacchwo. */
5600 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5601 /* nmacchws - nmacchws. */
5602 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5603 /* nmacchwso - nmacchwso. */
5604 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5605 /* nmachhw - nmachhw. */
5606 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5607 /* nmachhwo - nmachhwo. */
5608 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5609 /* nmachhws - nmachhws. */
5610 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5611 /* nmachhwso - nmachhwso. */
5612 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5613 /* nmaclhw - nmaclhw. */
5614 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5615 /* nmaclhwo - nmaclhwo. */
5616 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5617 /* nmaclhws - nmaclhws. */
5618 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5619 /* nmaclhwso - nmaclhwso. */
5620 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5621
5622 /* mulchw - mulchw. */
5623 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5624 /* mulchwu - mulchwu. */
5625 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5626 /* mulhhw - mulhhw. */
5627 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5628 /* mulhhwu - mulhhwu. */
5629 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5630 /* mullhw - mullhw. */
5631 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5632 /* mullhwu - mullhwu. */
5633 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5634
5635 /* mfdcr */
5636 static void gen_mfdcr(DisasContext *ctx)
5637 {
5638 #if defined(CONFIG_USER_ONLY)
5639 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5640 #else
5641 TCGv dcrn;
5642 if (unlikely(!ctx->mem_idx)) {
5643 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5644 return;
5645 }
5646 /* NIP cannot be restored if the memory exception comes from an helper */
5647 gen_update_nip(ctx, ctx->nip - 4);
5648 dcrn = tcg_const_tl(SPR(ctx->opcode));
5649 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5650 tcg_temp_free(dcrn);
5651 #endif
5652 }
5653
5654 /* mtdcr */
5655 static void gen_mtdcr(DisasContext *ctx)
5656 {
5657 #if defined(CONFIG_USER_ONLY)
5658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5659 #else
5660 TCGv dcrn;
5661 if (unlikely(!ctx->mem_idx)) {
5662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5663 return;
5664 }
5665 /* NIP cannot be restored if the memory exception comes from an helper */
5666 gen_update_nip(ctx, ctx->nip - 4);
5667 dcrn = tcg_const_tl(SPR(ctx->opcode));
5668 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5669 tcg_temp_free(dcrn);
5670 #endif
5671 }
5672
5673 /* mfdcrx */
5674 /* XXX: not implemented on 440 ? */
5675 static void gen_mfdcrx(DisasContext *ctx)
5676 {
5677 #if defined(CONFIG_USER_ONLY)
5678 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5679 #else
5680 if (unlikely(!ctx->mem_idx)) {
5681 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5682 return;
5683 }
5684 /* NIP cannot be restored if the memory exception comes from an helper */
5685 gen_update_nip(ctx, ctx->nip - 4);
5686 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5687 cpu_gpr[rA(ctx->opcode)]);
5688 /* Note: Rc update flag set leads to undefined state of Rc0 */
5689 #endif
5690 }
5691
5692 /* mtdcrx */
5693 /* XXX: not implemented on 440 ? */
5694 static void gen_mtdcrx(DisasContext *ctx)
5695 {
5696 #if defined(CONFIG_USER_ONLY)
5697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5698 #else
5699 if (unlikely(!ctx->mem_idx)) {
5700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5701 return;
5702 }
5703 /* NIP cannot be restored if the memory exception comes from an helper */
5704 gen_update_nip(ctx, ctx->nip - 4);
5705 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5706 cpu_gpr[rS(ctx->opcode)]);
5707 /* Note: Rc update flag set leads to undefined state of Rc0 */
5708 #endif
5709 }
5710
5711 /* mfdcrux (PPC 460) : user-mode access to DCR */
5712 static void gen_mfdcrux(DisasContext *ctx)
5713 {
5714 /* NIP cannot be restored if the memory exception comes from an helper */
5715 gen_update_nip(ctx, ctx->nip - 4);
5716 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5717 cpu_gpr[rA(ctx->opcode)]);
5718 /* Note: Rc update flag set leads to undefined state of Rc0 */
5719 }
5720
5721 /* mtdcrux (PPC 460) : user-mode access to DCR */
5722 static void gen_mtdcrux(DisasContext *ctx)
5723 {
5724 /* NIP cannot be restored if the memory exception comes from an helper */
5725 gen_update_nip(ctx, ctx->nip - 4);
5726 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5727 cpu_gpr[rS(ctx->opcode)]);
5728 /* Note: Rc update flag set leads to undefined state of Rc0 */
5729 }
5730
5731 /* dccci */
5732 static void gen_dccci(DisasContext *ctx)
5733 {
5734 #if defined(CONFIG_USER_ONLY)
5735 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5736 #else
5737 if (unlikely(!ctx->mem_idx)) {
5738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5739 return;
5740 }
5741 /* interpreted as no-op */
5742 #endif
5743 }
5744
5745 /* dcread */
5746 static void gen_dcread(DisasContext *ctx)
5747 {
5748 #if defined(CONFIG_USER_ONLY)
5749 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5750 #else
5751 TCGv EA, val;
5752 if (unlikely(!ctx->mem_idx)) {
5753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5754 return;
5755 }
5756 gen_set_access_type(ctx, ACCESS_CACHE);
5757 EA = tcg_temp_new();
5758 gen_addr_reg_index(ctx, EA);
5759 val = tcg_temp_new();
5760 gen_qemu_ld32u(ctx, val, EA);
5761 tcg_temp_free(val);
5762 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5763 tcg_temp_free(EA);
5764 #endif
5765 }
5766
5767 /* icbt */
5768 static void gen_icbt_40x(DisasContext *ctx)
5769 {
5770 /* interpreted as no-op */
5771 /* XXX: specification say this is treated as a load by the MMU
5772 * but does not generate any exception
5773 */
5774 }
5775
5776 /* iccci */
5777 static void gen_iccci(DisasContext *ctx)
5778 {
5779 #if defined(CONFIG_USER_ONLY)
5780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5781 #else
5782 if (unlikely(!ctx->mem_idx)) {
5783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5784 return;
5785 }
5786 /* interpreted as no-op */
5787 #endif
5788 }
5789
5790 /* icread */
5791 static void gen_icread(DisasContext *ctx)
5792 {
5793 #if defined(CONFIG_USER_ONLY)
5794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5795 #else
5796 if (unlikely(!ctx->mem_idx)) {
5797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5798 return;
5799 }
5800 /* interpreted as no-op */
5801 #endif
5802 }
5803
5804 /* rfci (mem_idx only) */
5805 static void gen_rfci_40x(DisasContext *ctx)
5806 {
5807 #if defined(CONFIG_USER_ONLY)
5808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5809 #else
5810 if (unlikely(!ctx->mem_idx)) {
5811 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5812 return;
5813 }
5814 /* Restore CPU state */
5815 gen_helper_40x_rfci(cpu_env);
5816 gen_sync_exception(ctx);
5817 #endif
5818 }
5819
5820 static void gen_rfci(DisasContext *ctx)
5821 {
5822 #if defined(CONFIG_USER_ONLY)
5823 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5824 #else
5825 if (unlikely(!ctx->mem_idx)) {
5826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5827 return;
5828 }
5829 /* Restore CPU state */
5830 gen_helper_rfci(cpu_env);
5831 gen_sync_exception(ctx);
5832 #endif
5833 }
5834
5835 /* BookE specific */
5836
5837 /* XXX: not implemented on 440 ? */
5838 static void gen_rfdi(DisasContext *ctx)
5839 {
5840 #if defined(CONFIG_USER_ONLY)
5841 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5842 #else
5843 if (unlikely(!ctx->mem_idx)) {
5844 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5845 return;
5846 }
5847 /* Restore CPU state */
5848 gen_helper_rfdi(cpu_env);
5849 gen_sync_exception(ctx);
5850 #endif
5851 }
5852
5853 /* XXX: not implemented on 440 ? */
5854 static void gen_rfmci(DisasContext *ctx)
5855 {
5856 #if defined(CONFIG_USER_ONLY)
5857 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5858 #else
5859 if (unlikely(!ctx->mem_idx)) {
5860 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5861 return;
5862 }
5863 /* Restore CPU state */
5864 gen_helper_rfmci(cpu_env);
5865 gen_sync_exception(ctx);
5866 #endif
5867 }
5868
5869 /* TLB management - PowerPC 405 implementation */
5870
5871 /* tlbre */
5872 static void gen_tlbre_40x(DisasContext *ctx)
5873 {
5874 #if defined(CONFIG_USER_ONLY)
5875 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5876 #else
5877 if (unlikely(!ctx->mem_idx)) {
5878 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5879 return;
5880 }
5881 switch (rB(ctx->opcode)) {
5882 case 0:
5883 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5884 cpu_gpr[rA(ctx->opcode)]);
5885 break;
5886 case 1:
5887 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5888 cpu_gpr[rA(ctx->opcode)]);
5889 break;
5890 default:
5891 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5892 break;
5893 }
5894 #endif
5895 }
5896
5897 /* tlbsx - tlbsx. */
5898 static void gen_tlbsx_40x(DisasContext *ctx)
5899 {
5900 #if defined(CONFIG_USER_ONLY)
5901 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5902 #else
5903 TCGv t0;
5904 if (unlikely(!ctx->mem_idx)) {
5905 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5906 return;
5907 }
5908 t0 = tcg_temp_new();
5909 gen_addr_reg_index(ctx, t0);
5910 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5911 tcg_temp_free(t0);
5912 if (Rc(ctx->opcode)) {
5913 int l1 = gen_new_label();
5914 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5915 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5916 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5917 gen_set_label(l1);
5918 }
5919 #endif
5920 }
5921
5922 /* tlbwe */
5923 static void gen_tlbwe_40x(DisasContext *ctx)
5924 {
5925 #if defined(CONFIG_USER_ONLY)
5926 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5927 #else
5928 if (unlikely(!ctx->mem_idx)) {
5929 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5930 return;
5931 }
5932 switch (rB(ctx->opcode)) {
5933 case 0:
5934 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5935 cpu_gpr[rS(ctx->opcode)]);
5936 break;
5937 case 1:
5938 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5939 cpu_gpr[rS(ctx->opcode)]);
5940 break;
5941 default:
5942 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5943 break;
5944 }
5945 #endif
5946 }
5947
5948 /* TLB management - PowerPC 440 implementation */
5949
5950 /* tlbre */
5951 static void gen_tlbre_440(DisasContext *ctx)
5952 {
5953 #if defined(CONFIG_USER_ONLY)
5954 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5955 #else
5956 if (unlikely(!ctx->mem_idx)) {
5957 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5958 return;
5959 }
5960 switch (rB(ctx->opcode)) {
5961 case 0:
5962 case 1:
5963 case 2:
5964 {
5965 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5966 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5967 t0, cpu_gpr[rA(ctx->opcode)]);
5968 tcg_temp_free_i32(t0);
5969 }
5970 break;
5971 default:
5972 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5973 break;
5974 }
5975 #endif
5976 }
5977
5978 /* tlbsx - tlbsx. */
5979 static void gen_tlbsx_440(DisasContext *ctx)
5980 {
5981 #if defined(CONFIG_USER_ONLY)
5982 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5983 #else
5984 TCGv t0;
5985 if (unlikely(!ctx->mem_idx)) {
5986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5987 return;
5988 }
5989 t0 = tcg_temp_new();
5990 gen_addr_reg_index(ctx, t0);
5991 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5992 tcg_temp_free(t0);
5993 if (Rc(ctx->opcode)) {
5994 int l1 = gen_new_label();
5995 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5996 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5997 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5998 gen_set_label(l1);
5999 }
6000 #endif
6001 }
6002
6003 /* tlbwe */
6004 static void gen_tlbwe_440(DisasContext *ctx)
6005 {
6006 #if defined(CONFIG_USER_ONLY)
6007 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6008 #else
6009 if (unlikely(!ctx->mem_idx)) {
6010 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6011 return;
6012 }
6013 switch (rB(ctx->opcode)) {
6014 case 0:
6015 case 1:
6016 case 2:
6017 {
6018 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6019 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6020 cpu_gpr[rS(ctx->opcode)]);
6021 tcg_temp_free_i32(t0);
6022 }
6023 break;
6024 default:
6025 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6026 break;
6027 }
6028 #endif
6029 }
6030
6031 /* TLB management - PowerPC BookE 2.06 implementation */
6032
6033 /* tlbre */
6034 static void gen_tlbre_booke206(DisasContext *ctx)
6035 {
6036 #if defined(CONFIG_USER_ONLY)
6037 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6038 #else
6039 if (unlikely(!ctx->mem_idx)) {
6040 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6041 return;
6042 }
6043
6044 gen_helper_booke206_tlbre(cpu_env);
6045 #endif
6046 }
6047
6048 /* tlbsx - tlbsx. */
6049 static void gen_tlbsx_booke206(DisasContext *ctx)
6050 {
6051 #if defined(CONFIG_USER_ONLY)
6052 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6053 #else
6054 TCGv t0;
6055 if (unlikely(!ctx->mem_idx)) {
6056 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6057 return;
6058 }
6059
6060 if (rA(ctx->opcode)) {
6061 t0 = tcg_temp_new();
6062 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6063 } else {
6064 t0 = tcg_const_tl(0);
6065 }
6066
6067 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6068 gen_helper_booke206_tlbsx(cpu_env, t0);
6069 #endif
6070 }
6071
6072 /* tlbwe */
6073 static void gen_tlbwe_booke206(DisasContext *ctx)
6074 {
6075 #if defined(CONFIG_USER_ONLY)
6076 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6077 #else
6078 if (unlikely(!ctx->mem_idx)) {
6079 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6080 return;
6081 }
6082 gen_update_nip(ctx, ctx->nip - 4);
6083 gen_helper_booke206_tlbwe(cpu_env);
6084 #endif
6085 }
6086
6087 static void gen_tlbivax_booke206(DisasContext *ctx)
6088 {
6089 #if defined(CONFIG_USER_ONLY)
6090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6091 #else
6092 TCGv t0;
6093 if (unlikely(!ctx->mem_idx)) {
6094 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6095 return;
6096 }
6097
6098 t0 = tcg_temp_new();
6099 gen_addr_reg_index(ctx, t0);
6100
6101 gen_helper_booke206_tlbivax(cpu_env, t0);
6102 #endif
6103 }
6104
6105 static void gen_tlbilx_booke206(DisasContext *ctx)
6106 {
6107 #if defined(CONFIG_USER_ONLY)
6108 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6109 #else
6110 TCGv t0;
6111 if (unlikely(!ctx->mem_idx)) {
6112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6113 return;
6114 }
6115
6116 t0 = tcg_temp_new();
6117 gen_addr_reg_index(ctx, t0);
6118
6119 switch((ctx->opcode >> 21) & 0x3) {
6120 case 0:
6121 gen_helper_booke206_tlbilx0(cpu_env, t0);
6122 break;
6123 case 1:
6124 gen_helper_booke206_tlbilx1(cpu_env, t0);
6125 break;
6126 case 3:
6127 gen_helper_booke206_tlbilx3(cpu_env, t0);
6128 break;
6129 default:
6130 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6131 break;
6132 }
6133
6134 tcg_temp_free(t0);
6135 #endif
6136 }
6137
6138
6139 /* wrtee */
6140 static void gen_wrtee(DisasContext *ctx)
6141 {
6142 #if defined(CONFIG_USER_ONLY)
6143 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6144 #else
6145 TCGv t0;
6146 if (unlikely(!ctx->mem_idx)) {
6147 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6148 return;
6149 }
6150 t0 = tcg_temp_new();
6151 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6152 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6153 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6154 tcg_temp_free(t0);
6155 /* Stop translation to have a chance to raise an exception
6156 * if we just set msr_ee to 1
6157 */
6158 gen_stop_exception(ctx);
6159 #endif
6160 }
6161
6162 /* wrteei */
6163 static void gen_wrteei(DisasContext *ctx)
6164 {
6165 #if defined(CONFIG_USER_ONLY)
6166 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6167 #else
6168 if (unlikely(!ctx->mem_idx)) {
6169 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6170 return;
6171 }
6172 if (ctx->opcode & 0x00008000) {
6173 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6174 /* Stop translation to have a chance to raise an exception */
6175 gen_stop_exception(ctx);
6176 } else {
6177 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6178 }
6179 #endif
6180 }
6181
6182 /* PowerPC 440 specific instructions */
6183
6184 /* dlmzb */
6185 static void gen_dlmzb(DisasContext *ctx)
6186 {
6187 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6188 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6189 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6190 tcg_temp_free_i32(t0);
6191 }
6192
6193 /* mbar replaces eieio on 440 */
6194 static void gen_mbar(DisasContext *ctx)
6195 {
6196 /* interpreted as no-op */
6197 }
6198
6199 /* msync replaces sync on 440 */
6200 static void gen_msync_4xx(DisasContext *ctx)
6201 {
6202 /* interpreted as no-op */
6203 }
6204
6205 /* icbt */
6206 static void gen_icbt_440(DisasContext *ctx)
6207 {
6208 /* interpreted as no-op */
6209 /* XXX: specification say this is treated as a load by the MMU
6210 * but does not generate any exception
6211 */
6212 }
6213
6214 /* Embedded.Processor Control */
6215
6216 static void gen_msgclr(DisasContext *ctx)
6217 {
6218 #if defined(CONFIG_USER_ONLY)
6219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6220 #else
6221 if (unlikely(ctx->mem_idx == 0)) {
6222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6223 return;
6224 }
6225
6226 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6227 #endif
6228 }
6229
6230 static void gen_msgsnd(DisasContext *ctx)
6231 {
6232 #if defined(CONFIG_USER_ONLY)
6233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6234 #else
6235 if (unlikely(ctx->mem_idx == 0)) {
6236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6237 return;
6238 }
6239
6240 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6241 #endif
6242 }
6243
6244 /*** Altivec vector extension ***/
6245 /* Altivec registers moves */
6246
6247 static inline TCGv_ptr gen_avr_ptr(int reg)
6248 {
6249 TCGv_ptr r = tcg_temp_new_ptr();
6250 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6251 return r;
6252 }
6253
6254 #define GEN_VR_LDX(name, opc2, opc3) \
6255 static void glue(gen_, name)(DisasContext *ctx) \
6256 { \
6257 TCGv EA; \
6258 if (unlikely(!ctx->altivec_enabled)) { \
6259 gen_exception(ctx, POWERPC_EXCP_VPU); \
6260 return; \
6261 } \
6262 gen_set_access_type(ctx, ACCESS_INT); \
6263 EA = tcg_temp_new(); \
6264 gen_addr_reg_index(ctx, EA); \
6265 tcg_gen_andi_tl(EA, EA, ~0xf); \
6266 if (ctx->le_mode) { \
6267 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6268 tcg_gen_addi_tl(EA, EA, 8); \
6269 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6270 } else { \
6271 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6272 tcg_gen_addi_tl(EA, EA, 8); \
6273 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6274 } \
6275 tcg_temp_free(EA); \
6276 }
6277
6278 #define GEN_VR_STX(name, opc2, opc3) \
6279 static void gen_st##name(DisasContext *ctx) \
6280 { \
6281 TCGv EA; \
6282 if (unlikely(!ctx->altivec_enabled)) { \
6283 gen_exception(ctx, POWERPC_EXCP_VPU); \
6284 return; \
6285 } \
6286 gen_set_access_type(ctx, ACCESS_INT); \
6287 EA = tcg_temp_new(); \
6288 gen_addr_reg_index(ctx, EA); \
6289 tcg_gen_andi_tl(EA, EA, ~0xf); \
6290 if (ctx->le_mode) { \
6291 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6292 tcg_gen_addi_tl(EA, EA, 8); \
6293 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6294 } else { \
6295 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6296 tcg_gen_addi_tl(EA, EA, 8); \
6297 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6298 } \
6299 tcg_temp_free(EA); \
6300 }
6301
6302 #define GEN_VR_LVE(name, opc2, opc3) \
6303 static void gen_lve##name(DisasContext *ctx) \
6304 { \
6305 TCGv EA; \
6306 TCGv_ptr rs; \
6307 if (unlikely(!ctx->altivec_enabled)) { \
6308 gen_exception(ctx, POWERPC_EXCP_VPU); \
6309 return; \
6310 } \
6311 gen_set_access_type(ctx, ACCESS_INT); \
6312 EA = tcg_temp_new(); \
6313 gen_addr_reg_index(ctx, EA); \
6314 rs = gen_avr_ptr(rS(ctx->opcode)); \
6315 gen_helper_lve##name(cpu_env, rs, EA); \
6316 tcg_temp_free(EA); \
6317 tcg_temp_free_ptr(rs); \
6318 }
6319
6320 #define GEN_VR_STVE(name, opc2, opc3) \
6321 static void gen_stve##name(DisasContext *ctx) \
6322 { \
6323 TCGv EA; \
6324 TCGv_ptr rs; \
6325 if (unlikely(!ctx->altivec_enabled)) { \
6326 gen_exception(ctx, POWERPC_EXCP_VPU); \
6327 return; \
6328 } \
6329 gen_set_access_type(ctx, ACCESS_INT); \
6330 EA = tcg_temp_new(); \
6331 gen_addr_reg_index(ctx, EA); \
6332 rs = gen_avr_ptr(rS(ctx->opcode)); \
6333 gen_helper_stve##name(cpu_env, rs, EA); \
6334 tcg_temp_free(EA); \
6335 tcg_temp_free_ptr(rs); \
6336 }
6337
6338 GEN_VR_LDX(lvx, 0x07, 0x03);
6339 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6340 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6341
6342 GEN_VR_LVE(bx, 0x07, 0x00);
6343 GEN_VR_LVE(hx, 0x07, 0x01);
6344 GEN_VR_LVE(wx, 0x07, 0x02);
6345
6346 GEN_VR_STX(svx, 0x07, 0x07);
6347 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6348 GEN_VR_STX(svxl, 0x07, 0x0F);
6349
6350 GEN_VR_STVE(bx, 0x07, 0x04);
6351 GEN_VR_STVE(hx, 0x07, 0x05);
6352 GEN_VR_STVE(wx, 0x07, 0x06);
6353
6354 static void gen_lvsl(DisasContext *ctx)
6355 {
6356 TCGv_ptr rd;
6357 TCGv EA;
6358 if (unlikely(!ctx->altivec_enabled)) {
6359 gen_exception(ctx, POWERPC_EXCP_VPU);
6360 return;
6361 }
6362 EA = tcg_temp_new();
6363 gen_addr_reg_index(ctx, EA);
6364 rd = gen_avr_ptr(rD(ctx->opcode));
6365 gen_helper_lvsl(rd, EA);
6366 tcg_temp_free(EA);
6367 tcg_temp_free_ptr(rd);
6368 }
6369
6370 static void gen_lvsr(DisasContext *ctx)
6371 {
6372 TCGv_ptr rd;
6373 TCGv EA;
6374 if (unlikely(!ctx->altivec_enabled)) {
6375 gen_exception(ctx, POWERPC_EXCP_VPU);
6376 return;
6377 }
6378 EA = tcg_temp_new();
6379 gen_addr_reg_index(ctx, EA);
6380 rd = gen_avr_ptr(rD(ctx->opcode));
6381 gen_helper_lvsr(rd, EA);
6382 tcg_temp_free(EA);
6383 tcg_temp_free_ptr(rd);
6384 }
6385
6386 static void gen_mfvscr(DisasContext *ctx)
6387 {
6388 TCGv_i32 t;
6389 if (unlikely(!ctx->altivec_enabled)) {
6390 gen_exception(ctx, POWERPC_EXCP_VPU);
6391 return;
6392 }
6393 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6394 t = tcg_temp_new_i32();
6395 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6396 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6397 tcg_temp_free_i32(t);
6398 }
6399
6400 static void gen_mtvscr(DisasContext *ctx)
6401 {
6402 TCGv_ptr p;
6403 if (unlikely(!ctx->altivec_enabled)) {
6404 gen_exception(ctx, POWERPC_EXCP_VPU);
6405 return;
6406 }
6407 p = gen_avr_ptr(rD(ctx->opcode));
6408 gen_helper_mtvscr(cpu_env, p);
6409 tcg_temp_free_ptr(p);
6410 }
6411
6412 /* Logical operations */
6413 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6414 static void glue(gen_, name)(DisasContext *ctx) \
6415 { \
6416 if (unlikely(!ctx->altivec_enabled)) { \
6417 gen_exception(ctx, POWERPC_EXCP_VPU); \
6418 return; \
6419 } \
6420 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6421 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6422 }
6423
6424 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6425 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6426 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6427 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6428 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6429
6430 #define GEN_VXFORM(name, opc2, opc3) \
6431 static void glue(gen_, name)(DisasContext *ctx) \
6432 { \
6433 TCGv_ptr ra, rb, rd; \
6434 if (unlikely(!ctx->altivec_enabled)) { \
6435 gen_exception(ctx, POWERPC_EXCP_VPU); \
6436 return; \
6437 } \
6438 ra = gen_avr_ptr(rA(ctx->opcode)); \
6439 rb = gen_avr_ptr(rB(ctx->opcode)); \
6440 rd = gen_avr_ptr(rD(ctx->opcode)); \
6441 gen_helper_##name (rd, ra, rb); \
6442 tcg_temp_free_ptr(ra); \
6443 tcg_temp_free_ptr(rb); \
6444 tcg_temp_free_ptr(rd); \
6445 }
6446
6447 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6448 static void glue(gen_, name)(DisasContext *ctx) \
6449 { \
6450 TCGv_ptr ra, rb, rd; \
6451 if (unlikely(!ctx->altivec_enabled)) { \
6452 gen_exception(ctx, POWERPC_EXCP_VPU); \
6453 return; \
6454 } \
6455 ra = gen_avr_ptr(rA(ctx->opcode)); \
6456 rb = gen_avr_ptr(rB(ctx->opcode)); \
6457 rd = gen_avr_ptr(rD(ctx->opcode)); \
6458 gen_helper_##name(cpu_env, rd, ra, rb); \
6459 tcg_temp_free_ptr(ra); \
6460 tcg_temp_free_ptr(rb); \
6461 tcg_temp_free_ptr(rd); \
6462 }
6463
6464 GEN_VXFORM(vaddubm, 0, 0);
6465 GEN_VXFORM(vadduhm, 0, 1);
6466 GEN_VXFORM(vadduwm, 0, 2);
6467 GEN_VXFORM(vsububm, 0, 16);
6468 GEN_VXFORM(vsubuhm, 0, 17);
6469 GEN_VXFORM(vsubuwm, 0, 18);
6470 GEN_VXFORM(vmaxub, 1, 0);
6471 GEN_VXFORM(vmaxuh, 1, 1);
6472 GEN_VXFORM(vmaxuw, 1, 2);
6473 GEN_VXFORM(vmaxsb, 1, 4);
6474 GEN_VXFORM(vmaxsh, 1, 5);
6475 GEN_VXFORM(vmaxsw, 1, 6);
6476 GEN_VXFORM(vminub, 1, 8);
6477 GEN_VXFORM(vminuh, 1, 9);
6478 GEN_VXFORM(vminuw, 1, 10);
6479 GEN_VXFORM(vminsb, 1, 12);
6480 GEN_VXFORM(vminsh, 1, 13);
6481 GEN_VXFORM(vminsw, 1, 14);
6482 GEN_VXFORM(vavgub, 1, 16);
6483 GEN_VXFORM(vavguh, 1, 17);
6484 GEN_VXFORM(vavguw, 1, 18);
6485 GEN_VXFORM(vavgsb, 1, 20);
6486 GEN_VXFORM(vavgsh, 1, 21);
6487 GEN_VXFORM(vavgsw, 1, 22);
6488 GEN_VXFORM(vmrghb, 6, 0);
6489 GEN_VXFORM(vmrghh, 6, 1);
6490 GEN_VXFORM(vmrghw, 6, 2);
6491 GEN_VXFORM(vmrglb, 6, 4);
6492 GEN_VXFORM(vmrglh, 6, 5);
6493 GEN_VXFORM(vmrglw, 6, 6);
6494 GEN_VXFORM(vmuloub, 4, 0);
6495 GEN_VXFORM(vmulouh, 4, 1);
6496 GEN_VXFORM(vmulosb, 4, 4);
6497 GEN_VXFORM(vmulosh, 4, 5);
6498 GEN_VXFORM(vmuleub, 4, 8);
6499 GEN_VXFORM(vmuleuh, 4, 9);
6500 GEN_VXFORM(vmulesb, 4, 12);
6501 GEN_VXFORM(vmulesh, 4, 13);
6502 GEN_VXFORM(vslb, 2, 4);
6503 GEN_VXFORM(vslh, 2, 5);
6504 GEN_VXFORM(vslw, 2, 6);
6505 GEN_VXFORM(vsrb, 2, 8);
6506 GEN_VXFORM(vsrh, 2, 9);
6507 GEN_VXFORM(vsrw, 2, 10);
6508 GEN_VXFORM(vsrab, 2, 12);
6509 GEN_VXFORM(vsrah, 2, 13);
6510 GEN_VXFORM(vsraw, 2, 14);
6511 GEN_VXFORM(vslo, 6, 16);
6512 GEN_VXFORM(vsro, 6, 17);
6513 GEN_VXFORM(vaddcuw, 0, 6);
6514 GEN_VXFORM(vsubcuw, 0, 22);
6515 GEN_VXFORM_ENV(vaddubs, 0, 8);
6516 GEN_VXFORM_ENV(vadduhs, 0, 9);
6517 GEN_VXFORM_ENV(vadduws, 0, 10);
6518 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6519 GEN_VXFORM_ENV(vaddshs, 0, 13);
6520 GEN_VXFORM_ENV(vaddsws, 0, 14);
6521 GEN_VXFORM_ENV(vsububs, 0, 24);
6522 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6523 GEN_VXFORM_ENV(vsubuws, 0, 26);
6524 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6525 GEN_VXFORM_ENV(vsubshs, 0, 29);
6526 GEN_VXFORM_ENV(vsubsws, 0, 30);
6527 GEN_VXFORM(vrlb, 2, 0);
6528 GEN_VXFORM(vrlh, 2, 1);
6529 GEN_VXFORM(vrlw, 2, 2);
6530 GEN_VXFORM(vsl, 2, 7);
6531 GEN_VXFORM(vsr, 2, 11);
6532 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6533 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6534 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6535 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6536 GEN_VXFORM_ENV(vpkshus, 7, 4);
6537 GEN_VXFORM_ENV(vpkswus, 7, 5);
6538 GEN_VXFORM_ENV(vpkshss, 7, 6);
6539 GEN_VXFORM_ENV(vpkswss, 7, 7);
6540 GEN_VXFORM(vpkpx, 7, 12);
6541 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6542 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6543 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6544 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6545 GEN_VXFORM_ENV(vsumsws, 4, 30);
6546 GEN_VXFORM_ENV(vaddfp, 5, 0);
6547 GEN_VXFORM_ENV(vsubfp, 5, 1);
6548 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6549 GEN_VXFORM_ENV(vminfp, 5, 17);
6550
6551 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6552 static void glue(gen_, name)(DisasContext *ctx) \
6553 { \
6554 TCGv_ptr ra, rb, rd; \
6555 if (unlikely(!ctx->altivec_enabled)) { \
6556 gen_exception(ctx, POWERPC_EXCP_VPU); \
6557 return; \
6558 } \
6559 ra = gen_avr_ptr(rA(ctx->opcode)); \
6560 rb = gen_avr_ptr(rB(ctx->opcode)); \
6561 rd = gen_avr_ptr(rD(ctx->opcode)); \
6562 gen_helper_##opname(cpu_env, rd, ra, rb); \
6563 tcg_temp_free_ptr(ra); \
6564 tcg_temp_free_ptr(rb); \
6565 tcg_temp_free_ptr(rd); \
6566 }
6567
6568 #define GEN_VXRFORM(name, opc2, opc3) \
6569 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6570 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6571
6572 GEN_VXRFORM(vcmpequb, 3, 0)
6573 GEN_VXRFORM(vcmpequh, 3, 1)
6574 GEN_VXRFORM(vcmpequw, 3, 2)
6575 GEN_VXRFORM(vcmpgtsb, 3, 12)
6576 GEN_VXRFORM(vcmpgtsh, 3, 13)
6577 GEN_VXRFORM(vcmpgtsw, 3, 14)
6578 GEN_VXRFORM(vcmpgtub, 3, 8)
6579 GEN_VXRFORM(vcmpgtuh, 3, 9)
6580 GEN_VXRFORM(vcmpgtuw, 3, 10)
6581 GEN_VXRFORM(vcmpeqfp, 3, 3)
6582 GEN_VXRFORM(vcmpgefp, 3, 7)
6583 GEN_VXRFORM(vcmpgtfp, 3, 11)
6584 GEN_VXRFORM(vcmpbfp, 3, 15)
6585
6586 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6587 static void glue(gen_, name)(DisasContext *ctx) \
6588 { \
6589 TCGv_ptr rd; \
6590 TCGv_i32 simm; \
6591 if (unlikely(!ctx->altivec_enabled)) { \
6592 gen_exception(ctx, POWERPC_EXCP_VPU); \
6593 return; \
6594 } \
6595 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6596 rd = gen_avr_ptr(rD(ctx->opcode)); \
6597 gen_helper_##name (rd, simm); \
6598 tcg_temp_free_i32(simm); \
6599 tcg_temp_free_ptr(rd); \
6600 }
6601
6602 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6603 GEN_VXFORM_SIMM(vspltish, 6, 13);
6604 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6605
6606 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6607 static void glue(gen_, name)(DisasContext *ctx) \
6608 { \
6609 TCGv_ptr rb, rd; \
6610 if (unlikely(!ctx->altivec_enabled)) { \
6611 gen_exception(ctx, POWERPC_EXCP_VPU); \
6612 return; \
6613 } \
6614 rb = gen_avr_ptr(rB(ctx->opcode)); \
6615 rd = gen_avr_ptr(rD(ctx->opcode)); \
6616 gen_helper_##name (rd, rb); \
6617 tcg_temp_free_ptr(rb); \
6618 tcg_temp_free_ptr(rd); \
6619 }
6620
6621 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6622 static void glue(gen_, name)(DisasContext *ctx) \
6623 { \
6624 TCGv_ptr rb, rd; \
6625 \
6626 if (unlikely(!ctx->altivec_enabled)) { \
6627 gen_exception(ctx, POWERPC_EXCP_VPU); \
6628 return; \
6629 } \
6630 rb = gen_avr_ptr(rB(ctx->opcode)); \
6631 rd = gen_avr_ptr(rD(ctx->opcode)); \
6632 gen_helper_##name(cpu_env, rd, rb); \
6633 tcg_temp_free_ptr(rb); \
6634 tcg_temp_free_ptr(rd); \
6635 }
6636
6637 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6638 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6639 GEN_VXFORM_NOA(vupklsb, 7, 10);
6640 GEN_VXFORM_NOA(vupklsh, 7, 11);
6641 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6642 GEN_VXFORM_NOA(vupklpx, 7, 15);
6643 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6644 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6645 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6646 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6647 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6648 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6649 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6650 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6651
6652 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6653 static void glue(gen_, name)(DisasContext *ctx) \
6654 { \
6655 TCGv_ptr rd; \
6656 TCGv_i32 simm; \
6657 if (unlikely(!ctx->altivec_enabled)) { \
6658 gen_exception(ctx, POWERPC_EXCP_VPU); \
6659 return; \
6660 } \
6661 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6662 rd = gen_avr_ptr(rD(ctx->opcode)); \
6663 gen_helper_##name (rd, simm); \
6664 tcg_temp_free_i32(simm); \
6665 tcg_temp_free_ptr(rd); \
6666 }
6667
6668 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6669 static void glue(gen_, name)(DisasContext *ctx) \
6670 { \
6671 TCGv_ptr rb, rd; \
6672 TCGv_i32 uimm; \
6673 if (unlikely(!ctx->altivec_enabled)) { \
6674 gen_exception(ctx, POWERPC_EXCP_VPU); \
6675 return; \
6676 } \
6677 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6678 rb = gen_avr_ptr(rB(ctx->opcode)); \
6679 rd = gen_avr_ptr(rD(ctx->opcode)); \
6680 gen_helper_##name (rd, rb, uimm); \
6681 tcg_temp_free_i32(uimm); \
6682 tcg_temp_free_ptr(rb); \
6683 tcg_temp_free_ptr(rd); \
6684 }
6685
6686 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6687 static void glue(gen_, name)(DisasContext *ctx) \
6688 { \
6689 TCGv_ptr rb, rd; \
6690 TCGv_i32 uimm; \
6691 \
6692 if (unlikely(!ctx->altivec_enabled)) { \
6693 gen_exception(ctx, POWERPC_EXCP_VPU); \
6694 return; \
6695 } \
6696 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6697 rb = gen_avr_ptr(rB(ctx->opcode)); \
6698 rd = gen_avr_ptr(rD(ctx->opcode)); \
6699 gen_helper_##name(cpu_env, rd, rb, uimm); \
6700 tcg_temp_free_i32(uimm); \
6701 tcg_temp_free_ptr(rb); \
6702 tcg_temp_free_ptr(rd); \
6703 }
6704
6705 GEN_VXFORM_UIMM(vspltb, 6, 8);
6706 GEN_VXFORM_UIMM(vsplth, 6, 9);
6707 GEN_VXFORM_UIMM(vspltw, 6, 10);
6708 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6709 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6710 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6711 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6712
6713 static void gen_vsldoi(DisasContext *ctx)
6714 {
6715 TCGv_ptr ra, rb, rd;
6716 TCGv_i32 sh;
6717 if (unlikely(!ctx->altivec_enabled)) {
6718 gen_exception(ctx, POWERPC_EXCP_VPU);
6719 return;
6720 }
6721 ra = gen_avr_ptr(rA(ctx->opcode));
6722 rb = gen_avr_ptr(rB(ctx->opcode));
6723 rd = gen_avr_ptr(rD(ctx->opcode));
6724 sh = tcg_const_i32(VSH(ctx->opcode));
6725 gen_helper_vsldoi (rd, ra, rb, sh);
6726 tcg_temp_free_ptr(ra);
6727 tcg_temp_free_ptr(rb);
6728 tcg_temp_free_ptr(rd);
6729 tcg_temp_free_i32(sh);
6730 }
6731
6732 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6733 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6734 { \
6735 TCGv_ptr ra, rb, rc, rd; \
6736 if (unlikely(!ctx->altivec_enabled)) { \
6737 gen_exception(ctx, POWERPC_EXCP_VPU); \
6738 return; \
6739 } \
6740 ra = gen_avr_ptr(rA(ctx->opcode)); \
6741 rb = gen_avr_ptr(rB(ctx->opcode)); \
6742 rc = gen_avr_ptr(rC(ctx->opcode)); \
6743 rd = gen_avr_ptr(rD(ctx->opcode)); \
6744 if (Rc(ctx->opcode)) { \
6745 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6746 } else { \
6747 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6748 } \
6749 tcg_temp_free_ptr(ra); \
6750 tcg_temp_free_ptr(rb); \
6751 tcg_temp_free_ptr(rc); \
6752 tcg_temp_free_ptr(rd); \
6753 }
6754
6755 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6756
6757 static void gen_vmladduhm(DisasContext *ctx)
6758 {
6759 TCGv_ptr ra, rb, rc, rd;
6760 if (unlikely(!ctx->altivec_enabled)) {
6761 gen_exception(ctx, POWERPC_EXCP_VPU);
6762 return;
6763 }
6764 ra = gen_avr_ptr(rA(ctx->opcode));
6765 rb = gen_avr_ptr(rB(ctx->opcode));
6766 rc = gen_avr_ptr(rC(ctx->opcode));
6767 rd = gen_avr_ptr(rD(ctx->opcode));
6768 gen_helper_vmladduhm(rd, ra, rb, rc);
6769 tcg_temp_free_ptr(ra);
6770 tcg_temp_free_ptr(rb);
6771 tcg_temp_free_ptr(rc);
6772 tcg_temp_free_ptr(rd);
6773 }
6774
6775 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6776 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6777 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6778 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6779 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6780
6781 /*** SPE extension ***/
6782 /* Register moves */
6783
6784
6785 static inline void gen_evmra(DisasContext *ctx)
6786 {
6787
6788 if (unlikely(!ctx->spe_enabled)) {
6789 gen_exception(ctx, POWERPC_EXCP_SPEU);
6790 return;
6791 }
6792
6793 #if defined(TARGET_PPC64)
6794 /* rD := rA */
6795 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6796
6797 /* spe_acc := rA */
6798 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6799 cpu_env,
6800 offsetof(CPUPPCState, spe_acc));
6801 #else
6802 TCGv_i64 tmp = tcg_temp_new_i64();
6803
6804 /* tmp := rA_lo + rA_hi << 32 */
6805 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6806
6807 /* spe_acc := tmp */
6808 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6809 tcg_temp_free_i64(tmp);
6810
6811 /* rD := rA */
6812 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6813 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6814 #endif
6815 }
6816
6817 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6818 {
6819 #if defined(TARGET_PPC64)
6820 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6821 #else
6822 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6823 #endif
6824 }
6825
6826 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6827 {
6828 #if defined(TARGET_PPC64)
6829 tcg_gen_mov_i64(cpu_gpr[reg], t);
6830 #else
6831 TCGv_i64 tmp = tcg_temp_new_i64();
6832 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6833 tcg_gen_shri_i64(tmp, t, 32);
6834 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6835 tcg_temp_free_i64(tmp);
6836 #endif
6837 }
6838
6839 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6840 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6841 { \
6842 if (Rc(ctx->opcode)) \
6843 gen_##name1(ctx); \
6844 else \
6845 gen_##name0(ctx); \
6846 }
6847
6848 /* Handler for undefined SPE opcodes */
6849 static inline void gen_speundef(DisasContext *ctx)
6850 {
6851 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6852 }
6853
6854 /* SPE logic */
6855 #if defined(TARGET_PPC64)
6856 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6857 static inline void gen_##name(DisasContext *ctx) \
6858 { \
6859 if (unlikely(!ctx->spe_enabled)) { \
6860 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6861 return; \
6862 } \
6863 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6864 cpu_gpr[rB(ctx->opcode)]); \
6865 }
6866 #else
6867 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6868 static inline void gen_##name(DisasContext *ctx) \
6869 { \
6870 if (unlikely(!ctx->spe_enabled)) { \
6871 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6872 return; \
6873 } \
6874 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6875 cpu_gpr[rB(ctx->opcode)]); \
6876 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6877 cpu_gprh[rB(ctx->opcode)]); \
6878 }
6879 #endif
6880
6881 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6882 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6883 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6884 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6885 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6886 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6887 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6888 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6889
6890 /* SPE logic immediate */
6891 #if defined(TARGET_PPC64)
6892 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6893 static inline void gen_##name(DisasContext *ctx) \
6894 { \
6895 if (unlikely(!ctx->spe_enabled)) { \
6896 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6897 return; \
6898 } \
6899 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6900 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6901 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6902 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6903 tcg_opi(t0, t0, rB(ctx->opcode)); \
6904 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6905 tcg_gen_trunc_i64_i32(t1, t2); \
6906 tcg_temp_free_i64(t2); \
6907 tcg_opi(t1, t1, rB(ctx->opcode)); \
6908 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6909 tcg_temp_free_i32(t0); \
6910 tcg_temp_free_i32(t1); \
6911 }
6912 #else
6913 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6914 static inline void gen_##name(DisasContext *ctx) \
6915 { \
6916 if (unlikely(!ctx->spe_enabled)) { \
6917 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6918 return; \
6919 } \
6920 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6921 rB(ctx->opcode)); \
6922 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6923 rB(ctx->opcode)); \
6924 }
6925 #endif
6926 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6927 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6928 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6929 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6930
6931 /* SPE arithmetic */
6932 #if defined(TARGET_PPC64)
6933 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6934 static inline void gen_##name(DisasContext *ctx) \
6935 { \
6936 if (unlikely(!ctx->spe_enabled)) { \
6937 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6938 return; \
6939 } \
6940 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6941 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6942 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6943 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6944 tcg_op(t0, t0); \
6945 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6946 tcg_gen_trunc_i64_i32(t1, t2); \
6947 tcg_temp_free_i64(t2); \
6948 tcg_op(t1, t1); \
6949 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6950 tcg_temp_free_i32(t0); \
6951 tcg_temp_free_i32(t1); \
6952 }
6953 #else
6954 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6955 static inline void gen_##name(DisasContext *ctx) \
6956 { \
6957 if (unlikely(!ctx->spe_enabled)) { \
6958 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6959 return; \
6960 } \
6961 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6962 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6963 }
6964 #endif
6965
6966 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6967 {
6968 int l1 = gen_new_label();
6969 int l2 = gen_new_label();
6970
6971 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6972 tcg_gen_neg_i32(ret, arg1);
6973 tcg_gen_br(l2);
6974 gen_set_label(l1);
6975 tcg_gen_mov_i32(ret, arg1);
6976 gen_set_label(l2);
6977 }
6978 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6979 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6980 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6981 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6982 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6983 {
6984 tcg_gen_addi_i32(ret, arg1, 0x8000);
6985 tcg_gen_ext16u_i32(ret, ret);
6986 }
6987 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6988 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6989 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6990
6991 #if defined(TARGET_PPC64)
6992 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6993 static inline void gen_##name(DisasContext *ctx) \
6994 { \
6995 if (unlikely(!ctx->spe_enabled)) { \
6996 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6997 return; \
6998 } \
6999 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7000 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7001 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7002 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7003 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7004 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7005 tcg_op(t0, t0, t2); \
7006 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7007 tcg_gen_trunc_i64_i32(t1, t3); \
7008 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7009 tcg_gen_trunc_i64_i32(t2, t3); \
7010 tcg_temp_free_i64(t3); \
7011 tcg_op(t1, t1, t2); \
7012 tcg_temp_free_i32(t2); \
7013 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7014 tcg_temp_free_i32(t0); \
7015 tcg_temp_free_i32(t1); \
7016 }
7017 #else
7018 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7019 static inline void gen_##name(DisasContext *ctx) \
7020 { \
7021 if (unlikely(!ctx->spe_enabled)) { \
7022 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7023 return; \
7024 } \
7025 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7026 cpu_gpr[rB(ctx->opcode)]); \
7027 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7028 cpu_gprh[rB(ctx->opcode)]); \
7029 }
7030 #endif
7031
7032 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7033 {
7034 TCGv_i32 t0;
7035 int l1, l2;
7036
7037 l1 = gen_new_label();
7038 l2 = gen_new_label();
7039 t0 = tcg_temp_local_new_i32();
7040 /* No error here: 6 bits are used */
7041 tcg_gen_andi_i32(t0, arg2, 0x3F);
7042 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7043 tcg_gen_shr_i32(ret, arg1, t0);
7044 tcg_gen_br(l2);
7045 gen_set_label(l1);
7046 tcg_gen_movi_i32(ret, 0);
7047 gen_set_label(l2);
7048 tcg_temp_free_i32(t0);
7049 }
7050 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7051 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7052 {
7053 TCGv_i32 t0;
7054 int l1, l2;
7055
7056 l1 = gen_new_label();
7057 l2 = gen_new_label();
7058 t0 = tcg_temp_local_new_i32();
7059 /* No error here: 6 bits are used */
7060 tcg_gen_andi_i32(t0, arg2, 0x3F);
7061 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7062 tcg_gen_sar_i32(ret, arg1, t0);
7063 tcg_gen_br(l2);
7064 gen_set_label(l1);
7065 tcg_gen_movi_i32(ret, 0);
7066 gen_set_label(l2);
7067 tcg_temp_free_i32(t0);
7068 }
7069 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7070 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7071 {
7072 TCGv_i32 t0;
7073 int l1, l2;
7074
7075 l1 = gen_new_label();
7076 l2 = gen_new_label();
7077 t0 = tcg_temp_local_new_i32();
7078 /* No error here: 6 bits are used */
7079 tcg_gen_andi_i32(t0, arg2, 0x3F);
7080 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7081 tcg_gen_shl_i32(ret, arg1, t0);
7082 tcg_gen_br(l2);
7083 gen_set_label(l1);
7084 tcg_gen_movi_i32(ret, 0);
7085 gen_set_label(l2);
7086 tcg_temp_free_i32(t0);
7087 }
7088 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7089 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7090 {
7091 TCGv_i32 t0 = tcg_temp_new_i32();
7092 tcg_gen_andi_i32(t0, arg2, 0x1F);
7093 tcg_gen_rotl_i32(ret, arg1, t0);
7094 tcg_temp_free_i32(t0);
7095 }
7096 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7097 static inline void gen_evmergehi(DisasContext *ctx)
7098 {
7099 if (unlikely(!ctx->spe_enabled)) {
7100 gen_exception(ctx, POWERPC_EXCP_SPEU);
7101 return;
7102 }
7103 #if defined(TARGET_PPC64)
7104 TCGv t0 = tcg_temp_new();
7105 TCGv t1 = tcg_temp_new();
7106 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7107 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7108 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7109 tcg_temp_free(t0);
7110 tcg_temp_free(t1);
7111 #else
7112 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7113 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7114 #endif
7115 }
7116 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7117 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7118 {
7119 tcg_gen_sub_i32(ret, arg2, arg1);
7120 }
7121 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7122
7123 /* SPE arithmetic immediate */
7124 #if defined(TARGET_PPC64)
7125 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7126 static inline void gen_##name(DisasContext *ctx) \
7127 { \
7128 if (unlikely(!ctx->spe_enabled)) { \
7129 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7130 return; \
7131 } \
7132 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7133 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7134 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7135 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7136 tcg_op(t0, t0, rA(ctx->opcode)); \
7137 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7138 tcg_gen_trunc_i64_i32(t1, t2); \
7139 tcg_temp_free_i64(t2); \
7140 tcg_op(t1, t1, rA(ctx->opcode)); \
7141 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7142 tcg_temp_free_i32(t0); \
7143 tcg_temp_free_i32(t1); \
7144 }
7145 #else
7146 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7147 static inline void gen_##name(DisasContext *ctx) \
7148 { \
7149 if (unlikely(!ctx->spe_enabled)) { \
7150 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7151 return; \
7152 } \
7153 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7154 rA(ctx->opcode)); \
7155 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7156 rA(ctx->opcode)); \
7157 }
7158 #endif
7159 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7160 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7161
7162 /* SPE comparison */
7163 #if defined(TARGET_PPC64)
7164 #define GEN_SPEOP_COMP(name, tcg_cond) \
7165 static inline void gen_##name(DisasContext *ctx) \
7166 { \
7167 if (unlikely(!ctx->spe_enabled)) { \
7168 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7169 return; \
7170 } \
7171 int l1 = gen_new_label(); \
7172 int l2 = gen_new_label(); \
7173 int l3 = gen_new_label(); \
7174 int l4 = gen_new_label(); \
7175 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7176 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7177 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7178 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7179 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7180 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7181 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7182 tcg_gen_br(l2); \
7183 gen_set_label(l1); \
7184 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7185 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7186 gen_set_label(l2); \
7187 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7188 tcg_gen_trunc_i64_i32(t0, t2); \
7189 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7190 tcg_gen_trunc_i64_i32(t1, t2); \
7191 tcg_temp_free_i64(t2); \
7192 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7193 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7194 ~(CRF_CH | CRF_CH_AND_CL)); \
7195 tcg_gen_br(l4); \
7196 gen_set_label(l3); \
7197 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7198 CRF_CH | CRF_CH_OR_CL); \
7199 gen_set_label(l4); \
7200 tcg_temp_free_i32(t0); \
7201 tcg_temp_free_i32(t1); \
7202 }
7203 #else
7204 #define GEN_SPEOP_COMP(name, tcg_cond) \
7205 static inline void gen_##name(DisasContext *ctx) \
7206 { \
7207 if (unlikely(!ctx->spe_enabled)) { \
7208 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7209 return; \
7210 } \
7211 int l1 = gen_new_label(); \
7212 int l2 = gen_new_label(); \
7213 int l3 = gen_new_label(); \
7214 int l4 = gen_new_label(); \
7215 \
7216 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7217 cpu_gpr[rB(ctx->opcode)], l1); \
7218 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7219 tcg_gen_br(l2); \
7220 gen_set_label(l1); \
7221 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7222 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7223 gen_set_label(l2); \
7224 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7225 cpu_gprh[rB(ctx->opcode)], l3); \
7226 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7227 ~(CRF_CH | CRF_CH_AND_CL)); \
7228 tcg_gen_br(l4); \
7229 gen_set_label(l3); \
7230 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7231 CRF_CH | CRF_CH_OR_CL); \
7232 gen_set_label(l4); \
7233 }
7234 #endif
7235 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7236 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7237 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7238 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7239 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7240
7241 /* SPE misc */
7242 static inline void gen_brinc(DisasContext *ctx)
7243 {
7244 /* Note: brinc is usable even if SPE is disabled */
7245 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7246 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7247 }
7248 static inline void gen_evmergelo(DisasContext *ctx)
7249 {
7250 if (unlikely(!ctx->spe_enabled)) {
7251 gen_exception(ctx, POWERPC_EXCP_SPEU);
7252 return;
7253 }
7254 #if defined(TARGET_PPC64)
7255 TCGv t0 = tcg_temp_new();
7256 TCGv t1 = tcg_temp_new();
7257 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7258 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7259 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7260 tcg_temp_free(t0);
7261 tcg_temp_free(t1);
7262 #else
7263 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7264 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7265 #endif
7266 }
7267 static inline void gen_evmergehilo(DisasContext *ctx)
7268 {
7269 if (unlikely(!ctx->spe_enabled)) {
7270 gen_exception(ctx, POWERPC_EXCP_SPEU);
7271 return;
7272 }
7273 #if defined(TARGET_PPC64)
7274 TCGv t0 = tcg_temp_new();
7275 TCGv t1 = tcg_temp_new();
7276 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7277 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7278 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7279 tcg_temp_free(t0);
7280 tcg_temp_free(t1);
7281 #else
7282 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7283 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7284 #endif
7285 }
7286 static inline void gen_evmergelohi(DisasContext *ctx)
7287 {
7288 if (unlikely(!ctx->spe_enabled)) {
7289 gen_exception(ctx, POWERPC_EXCP_SPEU);
7290 return;
7291 }
7292 #if defined(TARGET_PPC64)
7293 TCGv t0 = tcg_temp_new();
7294 TCGv t1 = tcg_temp_new();
7295 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7296 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7297 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7298 tcg_temp_free(t0);
7299 tcg_temp_free(t1);
7300 #else
7301 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7302 TCGv_i32 tmp = tcg_temp_new_i32();
7303 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7304 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7305 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7306 tcg_temp_free_i32(tmp);
7307 } else {
7308 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7309 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7310 }
7311 #endif
7312 }
7313 static inline void gen_evsplati(DisasContext *ctx)
7314 {
7315 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7316
7317 #if defined(TARGET_PPC64)
7318 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7319 #else
7320 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7321 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7322 #endif
7323 }
7324 static inline void gen_evsplatfi(DisasContext *ctx)
7325 {
7326 uint64_t imm = rA(ctx->opcode) << 27;
7327
7328 #if defined(TARGET_PPC64)
7329 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7330 #else
7331 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7332 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7333 #endif
7334 }
7335
7336 static inline void gen_evsel(DisasContext *ctx)
7337 {
7338 int l1 = gen_new_label();
7339 int l2 = gen_new_label();
7340 int l3 = gen_new_label();
7341 int l4 = gen_new_label();
7342 TCGv_i32 t0 = tcg_temp_local_new_i32();
7343 #if defined(TARGET_PPC64)
7344 TCGv t1 = tcg_temp_local_new();
7345 TCGv t2 = tcg_temp_local_new();
7346 #endif
7347 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7348 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7349 #if defined(TARGET_PPC64)
7350 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7351 #else
7352 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7353 #endif
7354 tcg_gen_br(l2);
7355 gen_set_label(l1);
7356 #if defined(TARGET_PPC64)
7357 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7358 #else
7359 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7360 #endif
7361 gen_set_label(l2);
7362 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7363 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7364 #if defined(TARGET_PPC64)
7365 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7366 #else
7367 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7368 #endif
7369 tcg_gen_br(l4);
7370 gen_set_label(l3);
7371 #if defined(TARGET_PPC64)
7372 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7373 #else
7374 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7375 #endif
7376 gen_set_label(l4);
7377 tcg_temp_free_i32(t0);
7378 #if defined(TARGET_PPC64)
7379 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7380 tcg_temp_free(t1);
7381 tcg_temp_free(t2);
7382 #endif
7383 }
7384
7385 static void gen_evsel0(DisasContext *ctx)
7386 {
7387 gen_evsel(ctx);
7388 }
7389
7390 static void gen_evsel1(DisasContext *ctx)
7391 {
7392 gen_evsel(ctx);
7393 }
7394
7395 static void gen_evsel2(DisasContext *ctx)
7396 {
7397 gen_evsel(ctx);
7398 }
7399
7400 static void gen_evsel3(DisasContext *ctx)
7401 {
7402 gen_evsel(ctx);
7403 }
7404
7405 /* Multiply */
7406
7407 static inline void gen_evmwumi(DisasContext *ctx)
7408 {
7409 TCGv_i64 t0, t1;
7410
7411 if (unlikely(!ctx->spe_enabled)) {
7412 gen_exception(ctx, POWERPC_EXCP_SPEU);
7413 return;
7414 }
7415
7416 t0 = tcg_temp_new_i64();
7417 t1 = tcg_temp_new_i64();
7418
7419 /* t0 := rA; t1 := rB */
7420 #if defined(TARGET_PPC64)
7421 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7422 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7423 #else
7424 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7425 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7426 #endif
7427
7428 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7429
7430 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7431
7432 tcg_temp_free_i64(t0);
7433 tcg_temp_free_i64(t1);
7434 }
7435
7436 static inline void gen_evmwumia(DisasContext *ctx)
7437 {
7438 TCGv_i64 tmp;
7439
7440 if (unlikely(!ctx->spe_enabled)) {
7441 gen_exception(ctx, POWERPC_EXCP_SPEU);
7442 return;
7443 }
7444
7445 gen_evmwumi(ctx); /* rD := rA * rB */
7446
7447 tmp = tcg_temp_new_i64();
7448
7449 /* acc := rD */
7450 gen_load_gpr64(tmp, rD(ctx->opcode));
7451 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7452 tcg_temp_free_i64(tmp);
7453 }
7454
7455 static inline void gen_evmwumiaa(DisasContext *ctx)
7456 {
7457 TCGv_i64 acc;
7458 TCGv_i64 tmp;
7459
7460 if (unlikely(!ctx->spe_enabled)) {
7461 gen_exception(ctx, POWERPC_EXCP_SPEU);
7462 return;
7463 }
7464
7465 gen_evmwumi(ctx); /* rD := rA * rB */
7466
7467 acc = tcg_temp_new_i64();
7468 tmp = tcg_temp_new_i64();
7469
7470 /* tmp := rD */
7471 gen_load_gpr64(tmp, rD(ctx->opcode));
7472
7473 /* Load acc */
7474 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7475
7476 /* acc := tmp + acc */
7477 tcg_gen_add_i64(acc, acc, tmp);
7478
7479 /* Store acc */
7480 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7481
7482 /* rD := acc */
7483 gen_store_gpr64(rD(ctx->opcode), acc);
7484
7485 tcg_temp_free_i64(acc);
7486 tcg_temp_free_i64(tmp);
7487 }
7488
7489 static inline void gen_evmwsmi(DisasContext *ctx)
7490 {
7491 TCGv_i64 t0, t1;
7492
7493 if (unlikely(!ctx->spe_enabled)) {
7494 gen_exception(ctx, POWERPC_EXCP_SPEU);
7495 return;
7496 }
7497
7498 t0 = tcg_temp_new_i64();
7499 t1 = tcg_temp_new_i64();
7500
7501 /* t0 := rA; t1 := rB */
7502 #if defined(TARGET_PPC64)
7503 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7504 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7505 #else
7506 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7507 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7508 #endif
7509
7510 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7511
7512 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7513
7514 tcg_temp_free_i64(t0);
7515 tcg_temp_free_i64(t1);
7516 }
7517
7518 static inline void gen_evmwsmia(DisasContext *ctx)
7519 {
7520 TCGv_i64 tmp;
7521
7522 gen_evmwsmi(ctx); /* rD := rA * rB */
7523
7524 tmp = tcg_temp_new_i64();
7525
7526 /* acc := rD */
7527 gen_load_gpr64(tmp, rD(ctx->opcode));
7528 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7529
7530 tcg_temp_free_i64(tmp);
7531 }
7532
7533 static inline void gen_evmwsmiaa(DisasContext *ctx)
7534 {
7535 TCGv_i64 acc = tcg_temp_new_i64();
7536 TCGv_i64 tmp = tcg_temp_new_i64();
7537
7538 gen_evmwsmi(ctx); /* rD := rA * rB */
7539
7540 acc = tcg_temp_new_i64();
7541 tmp = tcg_temp_new_i64();
7542
7543 /* tmp := rD */
7544 gen_load_gpr64(tmp, rD(ctx->opcode));
7545
7546 /* Load acc */
7547 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7548
7549 /* acc := tmp + acc */
7550 tcg_gen_add_i64(acc, acc, tmp);
7551
7552 /* Store acc */
7553 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7554
7555 /* rD := acc */
7556 gen_store_gpr64(rD(ctx->opcode), acc);
7557
7558 tcg_temp_free_i64(acc);
7559 tcg_temp_free_i64(tmp);
7560 }
7561
7562 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7563 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7564 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7565 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7566 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7567 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7568 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7569 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7570 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7571 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7572 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7573 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7574 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7575 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7576 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7577 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7578 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7579 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7580 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7581 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7582 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7583 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7584 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7585 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7586 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7587 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7588 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7589 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7590 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7591
7592 /* SPE load and stores */
7593 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7594 {
7595 target_ulong uimm = rB(ctx->opcode);
7596
7597 if (rA(ctx->opcode) == 0) {
7598 tcg_gen_movi_tl(EA, uimm << sh);
7599 } else {
7600 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7601 #if defined(TARGET_PPC64)
7602 if (!ctx->sf_mode) {
7603 tcg_gen_ext32u_tl(EA, EA);
7604 }
7605 #endif
7606 }
7607 }
7608
7609 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7610 {
7611 #if defined(TARGET_PPC64)
7612 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7613 #else
7614 TCGv_i64 t0 = tcg_temp_new_i64();
7615 gen_qemu_ld64(ctx, t0, addr);
7616 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7617 tcg_gen_shri_i64(t0, t0, 32);
7618 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7619 tcg_temp_free_i64(t0);
7620 #endif
7621 }
7622
7623 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7624 {
7625 #if defined(TARGET_PPC64)
7626 TCGv t0 = tcg_temp_new();
7627 gen_qemu_ld32u(ctx, t0, addr);
7628 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7629 gen_addr_add(ctx, addr, addr, 4);
7630 gen_qemu_ld32u(ctx, t0, addr);
7631 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7632 tcg_temp_free(t0);
7633 #else
7634 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7635 gen_addr_add(ctx, addr, addr, 4);
7636 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7637 #endif
7638 }
7639
7640 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7641 {
7642 TCGv t0 = tcg_temp_new();
7643 #if defined(TARGET_PPC64)
7644 gen_qemu_ld16u(ctx, t0, addr);
7645 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7646 gen_addr_add(ctx, addr, addr, 2);
7647 gen_qemu_ld16u(ctx, t0, addr);
7648 tcg_gen_shli_tl(t0, t0, 32);
7649 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7650 gen_addr_add(ctx, addr, addr, 2);
7651 gen_qemu_ld16u(ctx, t0, addr);
7652 tcg_gen_shli_tl(t0, t0, 16);
7653 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7654 gen_addr_add(ctx, addr, addr, 2);
7655 gen_qemu_ld16u(ctx, t0, addr);
7656 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7657 #else
7658 gen_qemu_ld16u(ctx, t0, addr);
7659 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7660 gen_addr_add(ctx, addr, addr, 2);
7661 gen_qemu_ld16u(ctx, t0, addr);
7662 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7663 gen_addr_add(ctx, addr, addr, 2);
7664 gen_qemu_ld16u(ctx, t0, addr);
7665 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7666 gen_addr_add(ctx, addr, addr, 2);
7667 gen_qemu_ld16u(ctx, t0, addr);
7668 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7669 #endif
7670 tcg_temp_free(t0);
7671 }
7672
7673 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7674 {
7675 TCGv t0 = tcg_temp_new();
7676 gen_qemu_ld16u(ctx, t0, addr);
7677 #if defined(TARGET_PPC64)
7678 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7679 tcg_gen_shli_tl(t0, t0, 16);
7680 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7681 #else
7682 tcg_gen_shli_tl(t0, t0, 16);
7683 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7684 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7685 #endif
7686 tcg_temp_free(t0);
7687 }
7688
7689 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7690 {
7691 TCGv t0 = tcg_temp_new();
7692 gen_qemu_ld16u(ctx, t0, addr);
7693 #if defined(TARGET_PPC64)
7694 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7695 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7696 #else
7697 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7698 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7699 #endif
7700 tcg_temp_free(t0);
7701 }
7702
7703 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7704 {
7705 TCGv t0 = tcg_temp_new();
7706 gen_qemu_ld16s(ctx, t0, addr);
7707 #if defined(TARGET_PPC64)
7708 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7709 tcg_gen_ext32u_tl(t0, t0);
7710 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7711 #else
7712 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7713 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7714 #endif
7715 tcg_temp_free(t0);
7716 }
7717
7718 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7719 {
7720 TCGv t0 = tcg_temp_new();
7721 #if defined(TARGET_PPC64)
7722 gen_qemu_ld16u(ctx, t0, addr);
7723 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7724 gen_addr_add(ctx, addr, addr, 2);
7725 gen_qemu_ld16u(ctx, t0, addr);
7726 tcg_gen_shli_tl(t0, t0, 16);
7727 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7728 #else
7729 gen_qemu_ld16u(ctx, t0, addr);
7730 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7731 gen_addr_add(ctx, addr, addr, 2);
7732 gen_qemu_ld16u(ctx, t0, addr);
7733 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7734 #endif
7735 tcg_temp_free(t0);
7736 }
7737
7738 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7739 {
7740 #if defined(TARGET_PPC64)
7741 TCGv t0 = tcg_temp_new();
7742 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7743 gen_addr_add(ctx, addr, addr, 2);
7744 gen_qemu_ld16u(ctx, t0, addr);
7745 tcg_gen_shli_tl(t0, t0, 32);
7746 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7747 tcg_temp_free(t0);
7748 #else
7749 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7750 gen_addr_add(ctx, addr, addr, 2);
7751 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7752 #endif
7753 }
7754
7755 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7756 {
7757 #if defined(TARGET_PPC64)
7758 TCGv t0 = tcg_temp_new();
7759 gen_qemu_ld16s(ctx, t0, addr);
7760 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7761 gen_addr_add(ctx, addr, addr, 2);
7762 gen_qemu_ld16s(ctx, t0, addr);
7763 tcg_gen_shli_tl(t0, t0, 32);
7764 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7765 tcg_temp_free(t0);
7766 #else
7767 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7768 gen_addr_add(ctx, addr, addr, 2);
7769 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7770 #endif
7771 }
7772
7773 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7774 {
7775 TCGv t0 = tcg_temp_new();
7776 gen_qemu_ld32u(ctx, t0, addr);
7777 #if defined(TARGET_PPC64)
7778 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7779 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7780 #else
7781 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7782 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7783 #endif
7784 tcg_temp_free(t0);
7785 }
7786
7787 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7788 {
7789 TCGv t0 = tcg_temp_new();
7790 #if defined(TARGET_PPC64)
7791 gen_qemu_ld16u(ctx, t0, addr);
7792 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7793 tcg_gen_shli_tl(t0, t0, 32);
7794 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7795 gen_addr_add(ctx, addr, addr, 2);
7796 gen_qemu_ld16u(ctx, t0, addr);
7797 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7798 tcg_gen_shli_tl(t0, t0, 16);
7799 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7800 #else
7801 gen_qemu_ld16u(ctx, t0, addr);
7802 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7803 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7804 gen_addr_add(ctx, addr, addr, 2);
7805 gen_qemu_ld16u(ctx, t0, addr);
7806 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7807 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7808 #endif
7809 tcg_temp_free(t0);
7810 }
7811
7812 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7813 {
7814 #if defined(TARGET_PPC64)
7815 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7816 #else
7817 TCGv_i64 t0 = tcg_temp_new_i64();
7818 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7819 gen_qemu_st64(ctx, t0, addr);
7820 tcg_temp_free_i64(t0);
7821 #endif
7822 }
7823
7824 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7825 {
7826 #if defined(TARGET_PPC64)
7827 TCGv t0 = tcg_temp_new();
7828 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7829 gen_qemu_st32(ctx, t0, addr);
7830 tcg_temp_free(t0);
7831 #else
7832 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7833 #endif
7834 gen_addr_add(ctx, addr, addr, 4);
7835 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7836 }
7837
7838 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7839 {
7840 TCGv t0 = tcg_temp_new();
7841 #if defined(TARGET_PPC64)
7842 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7843 #else
7844 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7845 #endif
7846 gen_qemu_st16(ctx, t0, addr);
7847 gen_addr_add(ctx, addr, addr, 2);
7848 #if defined(TARGET_PPC64)
7849 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7850 gen_qemu_st16(ctx, t0, addr);
7851 #else
7852 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7853 #endif
7854 gen_addr_add(ctx, addr, addr, 2);
7855 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7856 gen_qemu_st16(ctx, t0, addr);
7857 tcg_temp_free(t0);
7858 gen_addr_add(ctx, addr, addr, 2);
7859 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7860 }
7861
7862 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7863 {
7864 TCGv t0 = tcg_temp_new();
7865 #if defined(TARGET_PPC64)
7866 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7867 #else
7868 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7869 #endif
7870 gen_qemu_st16(ctx, t0, addr);
7871 gen_addr_add(ctx, addr, addr, 2);
7872 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7873 gen_qemu_st16(ctx, t0, addr);
7874 tcg_temp_free(t0);
7875 }
7876
7877 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7878 {
7879 #if defined(TARGET_PPC64)
7880 TCGv t0 = tcg_temp_new();
7881 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7882 gen_qemu_st16(ctx, t0, addr);
7883 tcg_temp_free(t0);
7884 #else
7885 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7886 #endif
7887 gen_addr_add(ctx, addr, addr, 2);
7888 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7889 }
7890
7891 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7892 {
7893 #if defined(TARGET_PPC64)
7894 TCGv t0 = tcg_temp_new();
7895 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7896 gen_qemu_st32(ctx, t0, addr);
7897 tcg_temp_free(t0);
7898 #else
7899 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7900 #endif
7901 }
7902
7903 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7904 {
7905 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7906 }
7907
7908 #define GEN_SPEOP_LDST(name, opc2, sh) \
7909 static void glue(gen_, name)(DisasContext *ctx) \
7910 { \
7911 TCGv t0; \
7912 if (unlikely(!ctx->spe_enabled)) { \
7913 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7914 return; \
7915 } \
7916 gen_set_access_type(ctx, ACCESS_INT); \
7917 t0 = tcg_temp_new(); \
7918 if (Rc(ctx->opcode)) { \
7919 gen_addr_spe_imm_index(ctx, t0, sh); \
7920 } else { \
7921 gen_addr_reg_index(ctx, t0); \
7922 } \
7923 gen_op_##name(ctx, t0); \
7924 tcg_temp_free(t0); \
7925 }
7926
7927 GEN_SPEOP_LDST(evldd, 0x00, 3);
7928 GEN_SPEOP_LDST(evldw, 0x01, 3);
7929 GEN_SPEOP_LDST(evldh, 0x02, 3);
7930 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7931 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7932 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7933 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7934 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7935 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7936 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7937 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7938
7939 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7940 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7941 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7942 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7943 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7944 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7945 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7946
7947 /* Multiply and add - TODO */
7948 #if 0
7949 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7950 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7951 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7952 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7953 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7954 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7955 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7956 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7957 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7958 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7959 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7960 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7961
7962 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7963 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7964 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7965 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7966 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7967 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7968 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7969 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7970 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7971 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7972 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7973 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7974
7975 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7976 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7977 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7978 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7979 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7980
7981 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7982 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7983 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7984 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7985 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7986 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7987 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7988 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7989 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7990 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7991 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7992 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7993
7994 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7995 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7996 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7997 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7998
7999 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8000 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8001 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8002 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8003 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8004 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8005 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8006 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8007 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8008 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8009 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8010 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8011
8012 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8013 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8014 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8015 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8016 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8017 #endif
8018
8019 /*** SPE floating-point extension ***/
8020 #if defined(TARGET_PPC64)
8021 #define GEN_SPEFPUOP_CONV_32_32(name) \
8022 static inline void gen_##name(DisasContext *ctx) \
8023 { \
8024 TCGv_i32 t0; \
8025 TCGv t1; \
8026 t0 = tcg_temp_new_i32(); \
8027 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8028 gen_helper_##name(t0, cpu_env, t0); \
8029 t1 = tcg_temp_new(); \
8030 tcg_gen_extu_i32_tl(t1, t0); \
8031 tcg_temp_free_i32(t0); \
8032 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8033 0xFFFFFFFF00000000ULL); \
8034 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8035 tcg_temp_free(t1); \
8036 }
8037 #define GEN_SPEFPUOP_CONV_32_64(name) \
8038 static inline void gen_##name(DisasContext *ctx) \
8039 { \
8040 TCGv_i32 t0; \
8041 TCGv t1; \
8042 t0 = tcg_temp_new_i32(); \
8043 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8044 t1 = tcg_temp_new(); \
8045 tcg_gen_extu_i32_tl(t1, t0); \
8046 tcg_temp_free_i32(t0); \
8047 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8048 0xFFFFFFFF00000000ULL); \
8049 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8050 tcg_temp_free(t1); \
8051 }
8052 #define GEN_SPEFPUOP_CONV_64_32(name) \
8053 static inline void gen_##name(DisasContext *ctx) \
8054 { \
8055 TCGv_i32 t0 = tcg_temp_new_i32(); \
8056 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8057 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8058 tcg_temp_free_i32(t0); \
8059 }
8060 #define GEN_SPEFPUOP_CONV_64_64(name) \
8061 static inline void gen_##name(DisasContext *ctx) \
8062 { \
8063 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8064 cpu_gpr[rB(ctx->opcode)]); \
8065 }
8066 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8067 static inline void gen_##name(DisasContext *ctx) \
8068 { \
8069 TCGv_i32 t0, t1; \
8070 TCGv_i64 t2; \
8071 if (unlikely(!ctx->spe_enabled)) { \
8072 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8073 return; \
8074 } \
8075 t0 = tcg_temp_new_i32(); \
8076 t1 = tcg_temp_new_i32(); \
8077 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8078 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8079 gen_helper_##name(t0, cpu_env, t0, t1); \
8080 tcg_temp_free_i32(t1); \
8081 t2 = tcg_temp_new(); \
8082 tcg_gen_extu_i32_tl(t2, t0); \
8083 tcg_temp_free_i32(t0); \
8084 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8085 0xFFFFFFFF00000000ULL); \
8086 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8087 tcg_temp_free(t2); \
8088 }
8089 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8090 static inline void gen_##name(DisasContext *ctx) \
8091 { \
8092 if (unlikely(!ctx->spe_enabled)) { \
8093 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8094 return; \
8095 } \
8096 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8097 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8098 }
8099 #define GEN_SPEFPUOP_COMP_32(name) \
8100 static inline void gen_##name(DisasContext *ctx) \
8101 { \
8102 TCGv_i32 t0, t1; \
8103 if (unlikely(!ctx->spe_enabled)) { \
8104 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8105 return; \
8106 } \
8107 t0 = tcg_temp_new_i32(); \
8108 t1 = tcg_temp_new_i32(); \
8109 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8110 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8111 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8112 tcg_temp_free_i32(t0); \
8113 tcg_temp_free_i32(t1); \
8114 }
8115 #define GEN_SPEFPUOP_COMP_64(name) \
8116 static inline void gen_##name(DisasContext *ctx) \
8117 { \
8118 if (unlikely(!ctx->spe_enabled)) { \
8119 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8120 return; \
8121 } \
8122 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8123 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8124 }
8125 #else
8126 #define GEN_SPEFPUOP_CONV_32_32(name) \
8127 static inline void gen_##name(DisasContext *ctx) \
8128 { \
8129 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8130 cpu_gpr[rB(ctx->opcode)]); \
8131 }
8132 #define GEN_SPEFPUOP_CONV_32_64(name) \
8133 static inline void gen_##name(DisasContext *ctx) \
8134 { \
8135 TCGv_i64 t0 = tcg_temp_new_i64(); \
8136 gen_load_gpr64(t0, rB(ctx->opcode)); \
8137 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8138 tcg_temp_free_i64(t0); \
8139 }
8140 #define GEN_SPEFPUOP_CONV_64_32(name) \
8141 static inline void gen_##name(DisasContext *ctx) \
8142 { \
8143 TCGv_i64 t0 = tcg_temp_new_i64(); \
8144 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8145 gen_store_gpr64(rD(ctx->opcode), t0); \
8146 tcg_temp_free_i64(t0); \
8147 }
8148 #define GEN_SPEFPUOP_CONV_64_64(name) \
8149 static inline void gen_##name(DisasContext *ctx) \
8150 { \
8151 TCGv_i64 t0 = tcg_temp_new_i64(); \
8152 gen_load_gpr64(t0, rB(ctx->opcode)); \
8153 gen_helper_##name(t0, cpu_env, t0); \
8154 gen_store_gpr64(rD(ctx->opcode), t0); \
8155 tcg_temp_free_i64(t0); \
8156 }
8157 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8158 static inline void gen_##name(DisasContext *ctx) \
8159 { \
8160 if (unlikely(!ctx->spe_enabled)) { \
8161 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8162 return; \
8163 } \
8164 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8165 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8166 }
8167 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8168 static inline void gen_##name(DisasContext *ctx) \
8169 { \
8170 TCGv_i64 t0, t1; \
8171 if (unlikely(!ctx->spe_enabled)) { \
8172 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8173 return; \
8174 } \
8175 t0 = tcg_temp_new_i64(); \
8176 t1 = tcg_temp_new_i64(); \
8177 gen_load_gpr64(t0, rA(ctx->opcode)); \
8178 gen_load_gpr64(t1, rB(ctx->opcode)); \
8179 gen_helper_##name(t0, cpu_env, t0, t1); \
8180 gen_store_gpr64(rD(ctx->opcode), t0); \
8181 tcg_temp_free_i64(t0); \
8182 tcg_temp_free_i64(t1); \
8183 }
8184 #define GEN_SPEFPUOP_COMP_32(name) \
8185 static inline void gen_##name(DisasContext *ctx) \
8186 { \
8187 if (unlikely(!ctx->spe_enabled)) { \
8188 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8189 return; \
8190 } \
8191 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8192 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8193 }
8194 #define GEN_SPEFPUOP_COMP_64(name) \
8195 static inline void gen_##name(DisasContext *ctx) \
8196 { \
8197 TCGv_i64 t0, t1; \
8198 if (unlikely(!ctx->spe_enabled)) { \
8199 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8200 return; \
8201 } \
8202 t0 = tcg_temp_new_i64(); \
8203 t1 = tcg_temp_new_i64(); \
8204 gen_load_gpr64(t0, rA(ctx->opcode)); \
8205 gen_load_gpr64(t1, rB(ctx->opcode)); \
8206 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8207 tcg_temp_free_i64(t0); \
8208 tcg_temp_free_i64(t1); \
8209 }
8210 #endif
8211
8212 /* Single precision floating-point vectors operations */
8213 /* Arithmetic */
8214 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8215 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8216 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8217 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8218 static inline void gen_evfsabs(DisasContext *ctx)
8219 {
8220 if (unlikely(!ctx->spe_enabled)) {
8221 gen_exception(ctx, POWERPC_EXCP_SPEU);
8222 return;
8223 }
8224 #if defined(TARGET_PPC64)
8225 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8226 #else
8227 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8228 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8229 #endif
8230 }
8231 static inline void gen_evfsnabs(DisasContext *ctx)
8232 {
8233 if (unlikely(!ctx->spe_enabled)) {
8234 gen_exception(ctx, POWERPC_EXCP_SPEU);
8235 return;
8236 }
8237 #if defined(TARGET_PPC64)
8238 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8239 #else
8240 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8241 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8242 #endif
8243 }
8244 static inline void gen_evfsneg(DisasContext *ctx)
8245 {
8246 if (unlikely(!ctx->spe_enabled)) {
8247 gen_exception(ctx, POWERPC_EXCP_SPEU);
8248 return;
8249 }
8250 #if defined(TARGET_PPC64)
8251 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8252 #else
8253 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8254 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8255 #endif
8256 }
8257
8258 /* Conversion */
8259 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8260 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8261 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8262 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8263 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8264 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8265 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8266 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8267 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8268 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8269
8270 /* Comparison */
8271 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8272 GEN_SPEFPUOP_COMP_64(evfscmplt);
8273 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8274 GEN_SPEFPUOP_COMP_64(evfststgt);
8275 GEN_SPEFPUOP_COMP_64(evfststlt);
8276 GEN_SPEFPUOP_COMP_64(evfststeq);
8277
8278 /* Opcodes definitions */
8279 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8280 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8281 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8282 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8283 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8284 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8285 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8286 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8287 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8288 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8289 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8290 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8291 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8292 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8293
8294 /* Single precision floating-point operations */
8295 /* Arithmetic */
8296 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8297 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8298 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8299 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8300 static inline void gen_efsabs(DisasContext *ctx)
8301 {
8302 if (unlikely(!ctx->spe_enabled)) {
8303 gen_exception(ctx, POWERPC_EXCP_SPEU);
8304 return;
8305 }
8306 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8307 }
8308 static inline void gen_efsnabs(DisasContext *ctx)
8309 {
8310 if (unlikely(!ctx->spe_enabled)) {
8311 gen_exception(ctx, POWERPC_EXCP_SPEU);
8312 return;
8313 }
8314 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8315 }
8316 static inline void gen_efsneg(DisasContext *ctx)
8317 {
8318 if (unlikely(!ctx->spe_enabled)) {
8319 gen_exception(ctx, POWERPC_EXCP_SPEU);
8320 return;
8321 }
8322 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8323 }
8324
8325 /* Conversion */
8326 GEN_SPEFPUOP_CONV_32_32(efscfui);
8327 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8328 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8329 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8330 GEN_SPEFPUOP_CONV_32_32(efsctui);
8331 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8332 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8333 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8334 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8335 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8336 GEN_SPEFPUOP_CONV_32_64(efscfd);
8337
8338 /* Comparison */
8339 GEN_SPEFPUOP_COMP_32(efscmpgt);
8340 GEN_SPEFPUOP_COMP_32(efscmplt);
8341 GEN_SPEFPUOP_COMP_32(efscmpeq);
8342 GEN_SPEFPUOP_COMP_32(efststgt);
8343 GEN_SPEFPUOP_COMP_32(efststlt);
8344 GEN_SPEFPUOP_COMP_32(efststeq);
8345
8346 /* Opcodes definitions */
8347 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8348 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8349 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8350 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8351 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8352 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8353 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8354 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8355 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8356 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8357 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8358 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8359 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8360 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8361
8362 /* Double precision floating-point operations */
8363 /* Arithmetic */
8364 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8365 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8366 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8367 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8368 static inline void gen_efdabs(DisasContext *ctx)
8369 {
8370 if (unlikely(!ctx->spe_enabled)) {
8371 gen_exception(ctx, POWERPC_EXCP_SPEU);
8372 return;
8373 }
8374 #if defined(TARGET_PPC64)
8375 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8376 #else
8377 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8378 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8379 #endif
8380 }
8381 static inline void gen_efdnabs(DisasContext *ctx)
8382 {
8383 if (unlikely(!ctx->spe_enabled)) {
8384 gen_exception(ctx, POWERPC_EXCP_SPEU);
8385 return;
8386 }
8387 #if defined(TARGET_PPC64)
8388 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8389 #else
8390 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8391 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8392 #endif
8393 }
8394 static inline void gen_efdneg(DisasContext *ctx)
8395 {
8396 if (unlikely(!ctx->spe_enabled)) {
8397 gen_exception(ctx, POWERPC_EXCP_SPEU);
8398 return;
8399 }
8400 #if defined(TARGET_PPC64)
8401 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8402 #else
8403 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8404 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8405 #endif
8406 }
8407
8408 /* Conversion */
8409 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8410 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8411 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8412 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8413 GEN_SPEFPUOP_CONV_32_64(efdctui);
8414 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8415 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8416 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8417 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8418 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8419 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8420 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8421 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8422 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8423 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8424
8425 /* Comparison */
8426 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8427 GEN_SPEFPUOP_COMP_64(efdcmplt);
8428 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8429 GEN_SPEFPUOP_COMP_64(efdtstgt);
8430 GEN_SPEFPUOP_COMP_64(efdtstlt);
8431 GEN_SPEFPUOP_COMP_64(efdtsteq);
8432
8433 /* Opcodes definitions */
8434 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8435 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8436 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8437 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8438 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8439 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8440 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8441 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8442 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8443 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8444 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8445 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8446 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8447 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8448 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8449 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8450
8451 static opcode_t opcodes[] = {
8452 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8453 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8454 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8455 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8456 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8457 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8458 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8459 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8460 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8461 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8462 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8463 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8464 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8465 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8466 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8467 #if defined(TARGET_PPC64)
8468 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8469 #endif
8470 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8471 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8472 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8473 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8474 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8475 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8476 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8477 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8478 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8479 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8480 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8481 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8482 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8483 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8484 #if defined(TARGET_PPC64)
8485 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8486 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8487 #endif
8488 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8489 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8490 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8491 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8492 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8493 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8494 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8495 #if defined(TARGET_PPC64)
8496 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8497 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8498 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8499 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8500 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8501 #endif
8502 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8503 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8504 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8505 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8506 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8507 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8508 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8509 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8510 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8511 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8512 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8513 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8514 #if defined(TARGET_PPC64)
8515 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8516 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8517 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8518 #endif
8519 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8520 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8521 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8522 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8523 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8524 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8525 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8526 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8527 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8528 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8529 #if defined(TARGET_PPC64)
8530 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8531 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8532 #endif
8533 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8534 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8535 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8536 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8537 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8538 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8539 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8540 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8541 #if defined(TARGET_PPC64)
8542 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8543 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8544 #endif
8545 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8546 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8547 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8548 #if defined(TARGET_PPC64)
8549 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8550 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8551 #endif
8552 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8553 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8554 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8555 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8556 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8557 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8558 #if defined(TARGET_PPC64)
8559 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8560 #endif
8561 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8562 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8563 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8564 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8565 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8566 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8567 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8568 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8569 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8570 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8571 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8572 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8573 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8574 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8575 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8576 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8577 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8578 #if defined(TARGET_PPC64)
8579 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8580 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8581 PPC_SEGMENT_64B),
8582 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8583 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8584 PPC_SEGMENT_64B),
8585 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8586 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8587 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8588 #endif
8589 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8590 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8591 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8592 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8593 #if defined(TARGET_PPC64)
8594 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8595 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8596 #endif
8597 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8598 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8599 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8600 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8601 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8602 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8603 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8604 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8605 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8606 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8607 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8608 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8609 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8610 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8611 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8612 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8613 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8614 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8615 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8616 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8617 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8618 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8619 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8620 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8621 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8622 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8623 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8624 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8625 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8626 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8627 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8628 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8629 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8630 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8631 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8632 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8633 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8634 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8635 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8636 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8637 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8638 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8639 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8640 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8641 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8642 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8643 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8644 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8645 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8646 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8647 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8648 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8649 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8650 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8651 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8652 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8653 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8654 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8655 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8656 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8657 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8658 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8659 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8660 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8661 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8662 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8663 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8664 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8665 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8666 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8667 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8668 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8669 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8670 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8671 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8672 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8673 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8674 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8675 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8676 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8677 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8678 PPC_NONE, PPC2_BOOKE206),
8679 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8680 PPC_NONE, PPC2_BOOKE206),
8681 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8682 PPC_NONE, PPC2_BOOKE206),
8683 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8684 PPC_NONE, PPC2_BOOKE206),
8685 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8686 PPC_NONE, PPC2_BOOKE206),
8687 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8688 PPC_NONE, PPC2_PRCNTL),
8689 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8690 PPC_NONE, PPC2_PRCNTL),
8691 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8692 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8693 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8694 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8695 PPC_BOOKE, PPC2_BOOKE206),
8696 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8697 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8698 PPC_BOOKE, PPC2_BOOKE206),
8699 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8700 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8701 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8702 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8703 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8704 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8705 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8706 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8707 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8708 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8709
8710 #undef GEN_INT_ARITH_ADD
8711 #undef GEN_INT_ARITH_ADD_CONST
8712 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8713 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8714 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8715 add_ca, compute_ca, compute_ov) \
8716 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8717 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8718 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8719 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8720 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8721 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8722 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8723 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8724 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8725 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8726 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8727
8728 #undef GEN_INT_ARITH_DIVW
8729 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8730 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8731 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8732 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8733 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8734 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8735
8736 #if defined(TARGET_PPC64)
8737 #undef GEN_INT_ARITH_DIVD
8738 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8739 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8740 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8741 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8742 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8743 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8744
8745 #undef GEN_INT_ARITH_MUL_HELPER
8746 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8747 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8748 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8749 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8750 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8751 #endif
8752
8753 #undef GEN_INT_ARITH_SUBF
8754 #undef GEN_INT_ARITH_SUBF_CONST
8755 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8756 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8757 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8758 add_ca, compute_ca, compute_ov) \
8759 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8760 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8761 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8762 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8763 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8764 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8765 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8766 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8767 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8768 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8769 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8770
8771 #undef GEN_LOGICAL1
8772 #undef GEN_LOGICAL2
8773 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8774 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8775 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8776 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8777 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8778 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8779 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8780 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8781 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8782 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8783 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8784 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8785 #if defined(TARGET_PPC64)
8786 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8787 #endif
8788
8789 #if defined(TARGET_PPC64)
8790 #undef GEN_PPC64_R2
8791 #undef GEN_PPC64_R4
8792 #define GEN_PPC64_R2(name, opc1, opc2) \
8793 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8794 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8795 PPC_64B)
8796 #define GEN_PPC64_R4(name, opc1, opc2) \
8797 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8798 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8799 PPC_64B), \
8800 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8801 PPC_64B), \
8802 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8803 PPC_64B)
8804 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8805 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8806 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8807 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8808 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8809 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8810 #endif
8811
8812 #undef _GEN_FLOAT_ACB
8813 #undef GEN_FLOAT_ACB
8814 #undef _GEN_FLOAT_AB
8815 #undef GEN_FLOAT_AB
8816 #undef _GEN_FLOAT_AC
8817 #undef GEN_FLOAT_AC
8818 #undef GEN_FLOAT_B
8819 #undef GEN_FLOAT_BS
8820 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8821 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8822 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8823 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8824 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8825 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8826 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8827 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8828 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8829 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8830 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8831 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8832 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8833 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8834 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8835 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8836 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8837 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8838 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8839
8840 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8841 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8842 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8843 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8844 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8845 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8846 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8847 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8848 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8849 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8850 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8851 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8852 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8853 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8854 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8855 #if defined(TARGET_PPC64)
8856 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8857 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8858 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8859 #endif
8860 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8861 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8862 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8863 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8864 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8865 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8866 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8867
8868 #undef GEN_LD
8869 #undef GEN_LDU
8870 #undef GEN_LDUX
8871 #undef GEN_LDX_E
8872 #undef GEN_LDS
8873 #define GEN_LD(name, ldop, opc, type) \
8874 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8875 #define GEN_LDU(name, ldop, opc, type) \
8876 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8877 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8878 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8879 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8880 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8881 #define GEN_LDS(name, ldop, op, type) \
8882 GEN_LD(name, ldop, op | 0x20, type) \
8883 GEN_LDU(name, ldop, op | 0x21, type) \
8884 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8885 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8886
8887 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8888 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8889 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8890 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8891 #if defined(TARGET_PPC64)
8892 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8893 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8894 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8895 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8896 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8897 #endif
8898 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8899 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8900
8901 #undef GEN_ST
8902 #undef GEN_STU
8903 #undef GEN_STUX
8904 #undef GEN_STX_E
8905 #undef GEN_STS
8906 #define GEN_ST(name, stop, opc, type) \
8907 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8908 #define GEN_STU(name, stop, opc, type) \
8909 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8910 #define GEN_STUX(name, stop, opc2, opc3, type) \
8911 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8912 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8913 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8914 #define GEN_STS(name, stop, op, type) \
8915 GEN_ST(name, stop, op | 0x20, type) \
8916 GEN_STU(name, stop, op | 0x21, type) \
8917 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8918 GEN_STX(name, stop, 0x17, op | 0x00, type)
8919
8920 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8921 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8922 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8923 #if defined(TARGET_PPC64)
8924 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8925 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8926 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8927 #endif
8928 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8929 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8930
8931 #undef GEN_LDF
8932 #undef GEN_LDUF
8933 #undef GEN_LDUXF
8934 #undef GEN_LDXF
8935 #undef GEN_LDFS
8936 #define GEN_LDF(name, ldop, opc, type) \
8937 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8938 #define GEN_LDUF(name, ldop, opc, type) \
8939 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8940 #define GEN_LDUXF(name, ldop, opc, type) \
8941 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8942 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8943 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8944 #define GEN_LDFS(name, ldop, op, type) \
8945 GEN_LDF(name, ldop, op | 0x20, type) \
8946 GEN_LDUF(name, ldop, op | 0x21, type) \
8947 GEN_LDUXF(name, ldop, op | 0x01, type) \
8948 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8949
8950 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8951 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8952
8953 #undef GEN_STF
8954 #undef GEN_STUF
8955 #undef GEN_STUXF
8956 #undef GEN_STXF
8957 #undef GEN_STFS
8958 #define GEN_STF(name, stop, opc, type) \
8959 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8960 #define GEN_STUF(name, stop, opc, type) \
8961 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8962 #define GEN_STUXF(name, stop, opc, type) \
8963 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8964 #define GEN_STXF(name, stop, opc2, opc3, type) \
8965 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8966 #define GEN_STFS(name, stop, op, type) \
8967 GEN_STF(name, stop, op | 0x20, type) \
8968 GEN_STUF(name, stop, op | 0x21, type) \
8969 GEN_STUXF(name, stop, op | 0x01, type) \
8970 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8971
8972 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8973 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8974 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8975
8976 #undef GEN_CRLOGIC
8977 #define GEN_CRLOGIC(name, tcg_op, opc) \
8978 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8979 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8980 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8981 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8982 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8983 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8984 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8985 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8986 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8987
8988 #undef GEN_MAC_HANDLER
8989 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8990 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8991 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8992 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8993 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8994 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8995 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8996 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8997 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8998 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8999 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9000 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9001 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9002 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9003 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9004 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9005 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9006 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9007 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9008 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9009 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9010 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9011 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9012 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9013 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9014 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9015 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9016 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9017 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9018 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9019 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9020 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9021 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9022 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9023 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9024 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9025 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9026 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9027 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9028 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9029 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9030 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9031 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9032 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9033
9034 #undef GEN_VR_LDX
9035 #undef GEN_VR_STX
9036 #undef GEN_VR_LVE
9037 #undef GEN_VR_STVE
9038 #define GEN_VR_LDX(name, opc2, opc3) \
9039 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9040 #define GEN_VR_STX(name, opc2, opc3) \
9041 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9042 #define GEN_VR_LVE(name, opc2, opc3) \
9043 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9044 #define GEN_VR_STVE(name, opc2, opc3) \
9045 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9046 GEN_VR_LDX(lvx, 0x07, 0x03),
9047 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9048 GEN_VR_LVE(bx, 0x07, 0x00),
9049 GEN_VR_LVE(hx, 0x07, 0x01),
9050 GEN_VR_LVE(wx, 0x07, 0x02),
9051 GEN_VR_STX(svx, 0x07, 0x07),
9052 GEN_VR_STX(svxl, 0x07, 0x0F),
9053 GEN_VR_STVE(bx, 0x07, 0x04),
9054 GEN_VR_STVE(hx, 0x07, 0x05),
9055 GEN_VR_STVE(wx, 0x07, 0x06),
9056
9057 #undef GEN_VX_LOGICAL
9058 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9059 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9060 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9061 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9062 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9063 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9064 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9065
9066 #undef GEN_VXFORM
9067 #define GEN_VXFORM(name, opc2, opc3) \
9068 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9069 GEN_VXFORM(vaddubm, 0, 0),
9070 GEN_VXFORM(vadduhm, 0, 1),
9071 GEN_VXFORM(vadduwm, 0, 2),
9072 GEN_VXFORM(vsububm, 0, 16),
9073 GEN_VXFORM(vsubuhm, 0, 17),
9074 GEN_VXFORM(vsubuwm, 0, 18),
9075 GEN_VXFORM(vmaxub, 1, 0),
9076 GEN_VXFORM(vmaxuh, 1, 1),
9077 GEN_VXFORM(vmaxuw, 1, 2),
9078 GEN_VXFORM(vmaxsb, 1, 4),
9079 GEN_VXFORM(vmaxsh, 1, 5),
9080 GEN_VXFORM(vmaxsw, 1, 6),
9081 GEN_VXFORM(vminub, 1, 8),
9082 GEN_VXFORM(vminuh, 1, 9),
9083 GEN_VXFORM(vminuw, 1, 10),
9084 GEN_VXFORM(vminsb, 1, 12),
9085 GEN_VXFORM(vminsh, 1, 13),
9086 GEN_VXFORM(vminsw, 1, 14),
9087 GEN_VXFORM(vavgub, 1, 16),
9088 GEN_VXFORM(vavguh, 1, 17),
9089 GEN_VXFORM(vavguw, 1, 18),
9090 GEN_VXFORM(vavgsb, 1, 20),
9091 GEN_VXFORM(vavgsh, 1, 21),
9092 GEN_VXFORM(vavgsw, 1, 22),
9093 GEN_VXFORM(vmrghb, 6, 0),
9094 GEN_VXFORM(vmrghh, 6, 1),
9095 GEN_VXFORM(vmrghw, 6, 2),
9096 GEN_VXFORM(vmrglb, 6, 4),
9097 GEN_VXFORM(vmrglh, 6, 5),
9098 GEN_VXFORM(vmrglw, 6, 6),
9099 GEN_VXFORM(vmuloub, 4, 0),
9100 GEN_VXFORM(vmulouh, 4, 1),
9101 GEN_VXFORM(vmulosb, 4, 4),
9102 GEN_VXFORM(vmulosh, 4, 5),
9103 GEN_VXFORM(vmuleub, 4, 8),
9104 GEN_VXFORM(vmuleuh, 4, 9),
9105 GEN_VXFORM(vmulesb, 4, 12),
9106 GEN_VXFORM(vmulesh, 4, 13),
9107 GEN_VXFORM(vslb, 2, 4),
9108 GEN_VXFORM(vslh, 2, 5),
9109 GEN_VXFORM(vslw, 2, 6),
9110 GEN_VXFORM(vsrb, 2, 8),
9111 GEN_VXFORM(vsrh, 2, 9),
9112 GEN_VXFORM(vsrw, 2, 10),
9113 GEN_VXFORM(vsrab, 2, 12),
9114 GEN_VXFORM(vsrah, 2, 13),
9115 GEN_VXFORM(vsraw, 2, 14),
9116 GEN_VXFORM(vslo, 6, 16),
9117 GEN_VXFORM(vsro, 6, 17),
9118 GEN_VXFORM(vaddcuw, 0, 6),
9119 GEN_VXFORM(vsubcuw, 0, 22),
9120 GEN_VXFORM(vaddubs, 0, 8),
9121 GEN_VXFORM(vadduhs, 0, 9),
9122 GEN_VXFORM(vadduws, 0, 10),
9123 GEN_VXFORM(vaddsbs, 0, 12),
9124 GEN_VXFORM(vaddshs, 0, 13),
9125 GEN_VXFORM(vaddsws, 0, 14),
9126 GEN_VXFORM(vsububs, 0, 24),
9127 GEN_VXFORM(vsubuhs, 0, 25),
9128 GEN_VXFORM(vsubuws, 0, 26),
9129 GEN_VXFORM(vsubsbs, 0, 28),
9130 GEN_VXFORM(vsubshs, 0, 29),
9131 GEN_VXFORM(vsubsws, 0, 30),
9132 GEN_VXFORM(vrlb, 2, 0),
9133 GEN_VXFORM(vrlh, 2, 1),
9134 GEN_VXFORM(vrlw, 2, 2),
9135 GEN_VXFORM(vsl, 2, 7),
9136 GEN_VXFORM(vsr, 2, 11),
9137 GEN_VXFORM(vpkuhum, 7, 0),
9138 GEN_VXFORM(vpkuwum, 7, 1),
9139 GEN_VXFORM(vpkuhus, 7, 2),
9140 GEN_VXFORM(vpkuwus, 7, 3),
9141 GEN_VXFORM(vpkshus, 7, 4),
9142 GEN_VXFORM(vpkswus, 7, 5),
9143 GEN_VXFORM(vpkshss, 7, 6),
9144 GEN_VXFORM(vpkswss, 7, 7),
9145 GEN_VXFORM(vpkpx, 7, 12),
9146 GEN_VXFORM(vsum4ubs, 4, 24),
9147 GEN_VXFORM(vsum4sbs, 4, 28),
9148 GEN_VXFORM(vsum4shs, 4, 25),
9149 GEN_VXFORM(vsum2sws, 4, 26),
9150 GEN_VXFORM(vsumsws, 4, 30),
9151 GEN_VXFORM(vaddfp, 5, 0),
9152 GEN_VXFORM(vsubfp, 5, 1),
9153 GEN_VXFORM(vmaxfp, 5, 16),
9154 GEN_VXFORM(vminfp, 5, 17),
9155
9156 #undef GEN_VXRFORM1
9157 #undef GEN_VXRFORM
9158 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9159 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9160 #define GEN_VXRFORM(name, opc2, opc3) \
9161 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9162 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9163 GEN_VXRFORM(vcmpequb, 3, 0)
9164 GEN_VXRFORM(vcmpequh, 3, 1)
9165 GEN_VXRFORM(vcmpequw, 3, 2)
9166 GEN_VXRFORM(vcmpgtsb, 3, 12)
9167 GEN_VXRFORM(vcmpgtsh, 3, 13)
9168 GEN_VXRFORM(vcmpgtsw, 3, 14)
9169 GEN_VXRFORM(vcmpgtub, 3, 8)
9170 GEN_VXRFORM(vcmpgtuh, 3, 9)
9171 GEN_VXRFORM(vcmpgtuw, 3, 10)
9172 GEN_VXRFORM(vcmpeqfp, 3, 3)
9173 GEN_VXRFORM(vcmpgefp, 3, 7)
9174 GEN_VXRFORM(vcmpgtfp, 3, 11)
9175 GEN_VXRFORM(vcmpbfp, 3, 15)
9176
9177 #undef GEN_VXFORM_SIMM
9178 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9179 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9180 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9181 GEN_VXFORM_SIMM(vspltish, 6, 13),
9182 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9183
9184 #undef GEN_VXFORM_NOA
9185 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9186 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9187 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9188 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9189 GEN_VXFORM_NOA(vupklsb, 7, 10),
9190 GEN_VXFORM_NOA(vupklsh, 7, 11),
9191 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9192 GEN_VXFORM_NOA(vupklpx, 7, 15),
9193 GEN_VXFORM_NOA(vrefp, 5, 4),
9194 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9195 GEN_VXFORM_NOA(vexptefp, 5, 6),
9196 GEN_VXFORM_NOA(vlogefp, 5, 7),
9197 GEN_VXFORM_NOA(vrfim, 5, 8),
9198 GEN_VXFORM_NOA(vrfin, 5, 9),
9199 GEN_VXFORM_NOA(vrfip, 5, 10),
9200 GEN_VXFORM_NOA(vrfiz, 5, 11),
9201
9202 #undef GEN_VXFORM_UIMM
9203 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9204 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9205 GEN_VXFORM_UIMM(vspltb, 6, 8),
9206 GEN_VXFORM_UIMM(vsplth, 6, 9),
9207 GEN_VXFORM_UIMM(vspltw, 6, 10),
9208 GEN_VXFORM_UIMM(vcfux, 5, 12),
9209 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9210 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9211 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9212
9213 #undef GEN_VAFORM_PAIRED
9214 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9215 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9216 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9217 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9218 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9219 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9220 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9221 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9222
9223 #undef GEN_SPE
9224 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9225 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9226 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9227 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9228 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9229 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9230 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9231 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9232 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9233 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9234 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9235 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9236 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9237 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9238 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9239 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9240 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9241 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9242 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9243 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9244 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9245 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9246 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9247 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9248 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9249 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9250 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9251 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9252 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9253 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9254 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9255
9256 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9257 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9258 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9259 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9260 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9261 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9262 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9263 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9264 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9265 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9266 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9267 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9268 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9269 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9270
9271 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9272 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9273 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9274 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9275 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9276 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9277 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9278 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9279 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9280 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9281 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9282 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9283 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9284 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9285
9286 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9287 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9288 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9289 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9290 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9291 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9292 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9293 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9294 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9295 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9296 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9297 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9298 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9299 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9300 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9301 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9302
9303 #undef GEN_SPEOP_LDST
9304 #define GEN_SPEOP_LDST(name, opc2, sh) \
9305 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9306 GEN_SPEOP_LDST(evldd, 0x00, 3),
9307 GEN_SPEOP_LDST(evldw, 0x01, 3),
9308 GEN_SPEOP_LDST(evldh, 0x02, 3),
9309 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9310 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9311 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9312 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9313 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9314 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9315 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9316 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9317
9318 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9319 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9320 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9321 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9322 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9323 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9324 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9325 };
9326
9327 #include "helper_regs.h"
9328 #include "translate_init.c"
9329
9330 /*****************************************************************************/
9331 /* Misc PowerPC helpers */
9332 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9333 int flags)
9334 {
9335 #define RGPL 4
9336 #define RFPL 4
9337
9338 int i;
9339
9340 cpu_synchronize_state(env);
9341
9342 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9343 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9344 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9345 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9346 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9347 env->hflags, env->mmu_idx);
9348 #if !defined(NO_TIMER_DUMP)
9349 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9350 #if !defined(CONFIG_USER_ONLY)
9351 " DECR %08" PRIu32
9352 #endif
9353 "\n",
9354 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9355 #if !defined(CONFIG_USER_ONLY)
9356 , cpu_ppc_load_decr(env)
9357 #endif
9358 );
9359 #endif
9360 for (i = 0; i < 32; i++) {
9361 if ((i & (RGPL - 1)) == 0)
9362 cpu_fprintf(f, "GPR%02d", i);
9363 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9364 if ((i & (RGPL - 1)) == (RGPL - 1))
9365 cpu_fprintf(f, "\n");
9366 }
9367 cpu_fprintf(f, "CR ");
9368 for (i = 0; i < 8; i++)
9369 cpu_fprintf(f, "%01x", env->crf[i]);
9370 cpu_fprintf(f, " [");
9371 for (i = 0; i < 8; i++) {
9372 char a = '-';
9373 if (env->crf[i] & 0x08)
9374 a = 'L';
9375 else if (env->crf[i] & 0x04)
9376 a = 'G';
9377 else if (env->crf[i] & 0x02)
9378 a = 'E';
9379 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9380 }
9381 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9382 env->reserve_addr);
9383 for (i = 0; i < 32; i++) {
9384 if ((i & (RFPL - 1)) == 0)
9385 cpu_fprintf(f, "FPR%02d", i);
9386 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9387 if ((i & (RFPL - 1)) == (RFPL - 1))
9388 cpu_fprintf(f, "\n");
9389 }
9390 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9391 #if !defined(CONFIG_USER_ONLY)
9392 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9393 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9394 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9395 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9396
9397 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9398 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9399 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9400 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9401
9402 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9403 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9404 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9405 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9406
9407 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9408 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9409 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9410 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9411 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9412
9413 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9414 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9415 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9416 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9417
9418 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9419 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9420 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9421 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9422
9423 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9424 " EPR " TARGET_FMT_lx "\n",
9425 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9426 env->spr[SPR_BOOKE_EPR]);
9427
9428 /* FSL-specific */
9429 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9430 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9431 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9432 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9433
9434 /*
9435 * IVORs are left out as they are large and do not change often --
9436 * they can be read with "p $ivor0", "p $ivor1", etc.
9437 */
9438 }
9439
9440 #if defined(TARGET_PPC64)
9441 if (env->flags & POWERPC_FLAG_CFAR) {
9442 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9443 }
9444 #endif
9445
9446 switch (env->mmu_model) {
9447 case POWERPC_MMU_32B:
9448 case POWERPC_MMU_601:
9449 case POWERPC_MMU_SOFT_6xx:
9450 case POWERPC_MMU_SOFT_74xx:
9451 #if defined(TARGET_PPC64)
9452 case POWERPC_MMU_620:
9453 case POWERPC_MMU_64B:
9454 #endif
9455 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9456 break;
9457 case POWERPC_MMU_BOOKE206:
9458 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9459 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9460 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9461 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9462
9463 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9464 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9465 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9466 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9467
9468 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9469 " TLB1CFG " TARGET_FMT_lx "\n",
9470 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9471 env->spr[SPR_BOOKE_TLB1CFG]);
9472 break;
9473 default:
9474 break;
9475 }
9476 #endif
9477
9478 #undef RGPL
9479 #undef RFPL
9480 }
9481
9482 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9483 int flags)
9484 {
9485 #if defined(DO_PPC_STATISTICS)
9486 opc_handler_t **t1, **t2, **t3, *handler;
9487 int op1, op2, op3;
9488
9489 t1 = env->opcodes;
9490 for (op1 = 0; op1 < 64; op1++) {
9491 handler = t1[op1];
9492 if (is_indirect_opcode(handler)) {
9493 t2 = ind_table(handler);
9494 for (op2 = 0; op2 < 32; op2++) {
9495 handler = t2[op2];
9496 if (is_indirect_opcode(handler)) {
9497 t3 = ind_table(handler);
9498 for (op3 = 0; op3 < 32; op3++) {
9499 handler = t3[op3];
9500 if (handler->count == 0)
9501 continue;
9502 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9503 "%016" PRIx64 " %" PRId64 "\n",
9504 op1, op2, op3, op1, (op3 << 5) | op2,
9505 handler->oname,
9506 handler->count, handler->count);
9507 }
9508 } else {
9509 if (handler->count == 0)
9510 continue;
9511 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9512 "%016" PRIx64 " %" PRId64 "\n",
9513 op1, op2, op1, op2, handler->oname,
9514 handler->count, handler->count);
9515 }
9516 }
9517 } else {
9518 if (handler->count == 0)
9519 continue;
9520 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9521 " %" PRId64 "\n",
9522 op1, op1, handler->oname,
9523 handler->count, handler->count);
9524 }
9525 }
9526 #endif
9527 }
9528
9529 /*****************************************************************************/
9530 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9531 TranslationBlock *tb,
9532 int search_pc)
9533 {
9534 DisasContext ctx, *ctxp = &ctx;
9535 opc_handler_t **table, *handler;
9536 target_ulong pc_start;
9537 uint16_t *gen_opc_end;
9538 CPUBreakpoint *bp;
9539 int j, lj = -1;
9540 int num_insns;
9541 int max_insns;
9542
9543 pc_start = tb->pc;
9544 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9545 ctx.nip = pc_start;
9546 ctx.tb = tb;
9547 ctx.exception = POWERPC_EXCP_NONE;
9548 ctx.spr_cb = env->spr_cb;
9549 ctx.mem_idx = env->mmu_idx;
9550 ctx.access_type = -1;
9551 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9552 #if defined(TARGET_PPC64)
9553 ctx.sf_mode = msr_is_64bit(env, env->msr);
9554 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9555 #endif
9556 ctx.fpu_enabled = msr_fp;
9557 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9558 ctx.spe_enabled = msr_spe;
9559 else
9560 ctx.spe_enabled = 0;
9561 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9562 ctx.altivec_enabled = msr_vr;
9563 else
9564 ctx.altivec_enabled = 0;
9565 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9566 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9567 else
9568 ctx.singlestep_enabled = 0;
9569 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9570 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9571 if (unlikely(env->singlestep_enabled))
9572 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9573 #if defined (DO_SINGLE_STEP) && 0
9574 /* Single step trace mode */
9575 msr_se = 1;
9576 #endif
9577 num_insns = 0;
9578 max_insns = tb->cflags & CF_COUNT_MASK;
9579 if (max_insns == 0)
9580 max_insns = CF_COUNT_MASK;
9581
9582 gen_icount_start();
9583 /* Set env in case of segfault during code fetch */
9584 while (ctx.exception == POWERPC_EXCP_NONE
9585 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9586 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9587 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9588 if (bp->pc == ctx.nip) {
9589 gen_debug_exception(ctxp);
9590 break;
9591 }
9592 }
9593 }
9594 if (unlikely(search_pc)) {
9595 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9596 if (lj < j) {
9597 lj++;
9598 while (lj < j)
9599 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9600 }
9601 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9602 tcg_ctx.gen_opc_instr_start[lj] = 1;
9603 tcg_ctx.gen_opc_icount[lj] = num_insns;
9604 }
9605 LOG_DISAS("----------------\n");
9606 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9607 ctx.nip, ctx.mem_idx, (int)msr_ir);
9608 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9609 gen_io_start();
9610 if (unlikely(ctx.le_mode)) {
9611 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9612 } else {
9613 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9614 }
9615 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9616 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9617 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9618 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9619 tcg_gen_debug_insn_start(ctx.nip);
9620 }
9621 ctx.nip += 4;
9622 table = env->opcodes;
9623 num_insns++;
9624 handler = table[opc1(ctx.opcode)];
9625 if (is_indirect_opcode(handler)) {
9626 table = ind_table(handler);
9627 handler = table[opc2(ctx.opcode)];
9628 if (is_indirect_opcode(handler)) {
9629 table = ind_table(handler);
9630 handler = table[opc3(ctx.opcode)];
9631 }
9632 }
9633 /* Is opcode *REALLY* valid ? */
9634 if (unlikely(handler->handler == &gen_invalid)) {
9635 if (qemu_log_enabled()) {
9636 qemu_log("invalid/unsupported opcode: "
9637 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9638 opc1(ctx.opcode), opc2(ctx.opcode),
9639 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9640 }
9641 } else {
9642 uint32_t inval;
9643
9644 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9645 inval = handler->inval2;
9646 } else {
9647 inval = handler->inval1;
9648 }
9649
9650 if (unlikely((ctx.opcode & inval) != 0)) {
9651 if (qemu_log_enabled()) {
9652 qemu_log("invalid bits: %08x for opcode: "
9653 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9654 ctx.opcode & inval, opc1(ctx.opcode),
9655 opc2(ctx.opcode), opc3(ctx.opcode),
9656 ctx.opcode, ctx.nip - 4);
9657 }
9658 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9659 break;
9660 }
9661 }
9662 (*(handler->handler))(&ctx);
9663 #if defined(DO_PPC_STATISTICS)
9664 handler->count++;
9665 #endif
9666 /* Check trace mode exceptions */
9667 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9668 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9669 ctx.exception != POWERPC_SYSCALL &&
9670 ctx.exception != POWERPC_EXCP_TRAP &&
9671 ctx.exception != POWERPC_EXCP_BRANCH)) {
9672 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9673 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9674 (env->singlestep_enabled) ||
9675 singlestep ||
9676 num_insns >= max_insns)) {
9677 /* if we reach a page boundary or are single stepping, stop
9678 * generation
9679 */
9680 break;
9681 }
9682 }
9683 if (tb->cflags & CF_LAST_IO)
9684 gen_io_end();
9685 if (ctx.exception == POWERPC_EXCP_NONE) {
9686 gen_goto_tb(&ctx, 0, ctx.nip);
9687 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9688 if (unlikely(env->singlestep_enabled)) {
9689 gen_debug_exception(ctxp);
9690 }
9691 /* Generate the return instruction */
9692 tcg_gen_exit_tb(0);
9693 }
9694 gen_icount_end(tb, num_insns);
9695 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9696 if (unlikely(search_pc)) {
9697 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9698 lj++;
9699 while (lj <= j)
9700 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9701 } else {
9702 tb->size = ctx.nip - pc_start;
9703 tb->icount = num_insns;
9704 }
9705 #if defined(DEBUG_DISAS)
9706 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9707 int flags;
9708 flags = env->bfd_mach;
9709 flags |= ctx.le_mode << 16;
9710 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9711 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9712 qemu_log("\n");
9713 }
9714 #endif
9715 }
9716
9717 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9718 {
9719 gen_intermediate_code_internal(env, tb, 0);
9720 }
9721
9722 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9723 {
9724 gen_intermediate_code_internal(env, tb, 1);
9725 }
9726
9727 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9728 {
9729 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9730 }
Qemu copy for testing