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[qemu.git] / target-ppc / translate.c
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 struct opc_handler_t {
208 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
209 uint32_t inval1;
210 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
211 uint32_t inval2;
212 /* instruction type */
213 uint64_t type;
214 /* extended instruction type */
215 uint64_t type2;
216 /* handler */
217 void (*handler)(DisasContext *ctx);
218 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
219 const char *oname;
220 #endif
221 #if defined(DO_PPC_STATISTICS)
222 uint64_t count;
223 #endif
224 };
225
226 static inline void gen_reset_fpstatus(void)
227 {
228 gen_helper_reset_fpstatus(cpu_env);
229 }
230
231 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
232 {
233 TCGv_i32 t0 = tcg_temp_new_i32();
234
235 if (set_fprf != 0) {
236 /* This case might be optimized later */
237 tcg_gen_movi_i32(t0, 1);
238 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
239 if (unlikely(set_rc)) {
240 tcg_gen_mov_i32(cpu_crf[1], t0);
241 }
242 gen_helper_float_check_status(cpu_env);
243 } else if (unlikely(set_rc)) {
244 /* We always need to compute fpcc */
245 tcg_gen_movi_i32(t0, 0);
246 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249
250 tcg_temp_free_i32(t0);
251 }
252
253 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
254 {
255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
259 }
260
261 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
262 {
263 #if defined(TARGET_PPC64)
264 if (ctx->sf_mode)
265 tcg_gen_movi_tl(cpu_nip, nip);
266 else
267 #endif
268 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
269 }
270
271 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
272 {
273 TCGv_i32 t0, t1;
274 if (ctx->exception == POWERPC_EXCP_NONE) {
275 gen_update_nip(ctx, ctx->nip);
276 }
277 t0 = tcg_const_i32(excp);
278 t1 = tcg_const_i32(error);
279 gen_helper_raise_exception_err(cpu_env, t0, t1);
280 tcg_temp_free_i32(t0);
281 tcg_temp_free_i32(t1);
282 ctx->exception = (excp);
283 }
284
285 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
286 {
287 TCGv_i32 t0;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 gen_helper_raise_exception(cpu_env, t0);
293 tcg_temp_free_i32(t0);
294 ctx->exception = (excp);
295 }
296
297 static inline void gen_debug_exception(DisasContext *ctx)
298 {
299 TCGv_i32 t0;
300
301 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
302 (ctx->exception != POWERPC_EXCP_SYNC)) {
303 gen_update_nip(ctx, ctx->nip);
304 }
305 t0 = tcg_const_i32(EXCP_DEBUG);
306 gen_helper_raise_exception(cpu_env, t0);
307 tcg_temp_free_i32(t0);
308 }
309
310 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
311 {
312 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
313 }
314
315 /* Stop translation */
316 static inline void gen_stop_exception(DisasContext *ctx)
317 {
318 gen_update_nip(ctx, ctx->nip);
319 ctx->exception = POWERPC_EXCP_STOP;
320 }
321
322 /* No need to update nip here, as execution flow will change */
323 static inline void gen_sync_exception(DisasContext *ctx)
324 {
325 ctx->exception = POWERPC_EXCP_SYNC;
326 }
327
328 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
333
334 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
335 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
336
337 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
338 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
339
340 typedef struct opcode_t {
341 unsigned char opc1, opc2, opc3;
342 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
343 unsigned char pad[5];
344 #else
345 unsigned char pad[1];
346 #endif
347 opc_handler_t handler;
348 const char *oname;
349 } opcode_t;
350
351 /*****************************************************************************/
352 /*** Instruction decoding ***/
353 #define EXTRACT_HELPER(name, shift, nb) \
354 static inline uint32_t name(uint32_t opcode) \
355 { \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
357 }
358
359 #define EXTRACT_SHELPER(name, shift, nb) \
360 static inline int32_t name(uint32_t opcode) \
361 { \
362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
363 }
364
365 /* Opcode part 1 */
366 EXTRACT_HELPER(opc1, 26, 6);
367 /* Opcode part 2 */
368 EXTRACT_HELPER(opc2, 1, 5);
369 /* Opcode part 3 */
370 EXTRACT_HELPER(opc3, 6, 5);
371 /* Update Cr0 flags */
372 EXTRACT_HELPER(Rc, 0, 1);
373 /* Destination */
374 EXTRACT_HELPER(rD, 21, 5);
375 /* Source */
376 EXTRACT_HELPER(rS, 21, 5);
377 /* First operand */
378 EXTRACT_HELPER(rA, 16, 5);
379 /* Second operand */
380 EXTRACT_HELPER(rB, 11, 5);
381 /* Third operand */
382 EXTRACT_HELPER(rC, 6, 5);
383 /*** Get CRn ***/
384 EXTRACT_HELPER(crfD, 23, 3);
385 EXTRACT_HELPER(crfS, 18, 3);
386 EXTRACT_HELPER(crbD, 21, 5);
387 EXTRACT_HELPER(crbA, 16, 5);
388 EXTRACT_HELPER(crbB, 11, 5);
389 /* SPR / TBL */
390 EXTRACT_HELPER(_SPR, 11, 10);
391 static inline uint32_t SPR(uint32_t opcode)
392 {
393 uint32_t sprn = _SPR(opcode);
394
395 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
396 }
397 /*** Get constants ***/
398 EXTRACT_HELPER(IMM, 12, 8);
399 /* 16 bits signed immediate value */
400 EXTRACT_SHELPER(SIMM, 0, 16);
401 /* 16 bits unsigned immediate value */
402 EXTRACT_HELPER(UIMM, 0, 16);
403 /* 5 bits signed immediate value */
404 EXTRACT_HELPER(SIMM5, 16, 5);
405 /* 5 bits signed immediate value */
406 EXTRACT_HELPER(UIMM5, 16, 5);
407 /* Bit count */
408 EXTRACT_HELPER(NB, 11, 5);
409 /* Shift count */
410 EXTRACT_HELPER(SH, 11, 5);
411 /* Vector shift count */
412 EXTRACT_HELPER(VSH, 6, 4);
413 /* Mask start */
414 EXTRACT_HELPER(MB, 6, 5);
415 /* Mask end */
416 EXTRACT_HELPER(ME, 1, 5);
417 /* Trap operand */
418 EXTRACT_HELPER(TO, 21, 5);
419
420 EXTRACT_HELPER(CRM, 12, 8);
421 EXTRACT_HELPER(FM, 17, 8);
422 EXTRACT_HELPER(SR, 16, 4);
423 EXTRACT_HELPER(FPIMM, 12, 4);
424
425 /*** Jump target decoding ***/
426 /* Displacement */
427 EXTRACT_SHELPER(d, 0, 16);
428 /* Immediate address */
429 static inline target_ulong LI(uint32_t opcode)
430 {
431 return (opcode >> 0) & 0x03FFFFFC;
432 }
433
434 static inline uint32_t BD(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0xFFFC;
437 }
438
439 EXTRACT_HELPER(BO, 21, 5);
440 EXTRACT_HELPER(BI, 16, 5);
441 /* Absolute/relative address */
442 EXTRACT_HELPER(AA, 1, 1);
443 /* Link */
444 EXTRACT_HELPER(LK, 0, 1);
445
446 /* Create a mask between <start> and <end> bits */
447 static inline target_ulong MASK(uint32_t start, uint32_t end)
448 {
449 target_ulong ret;
450
451 #if defined(TARGET_PPC64)
452 if (likely(start == 0)) {
453 ret = UINT64_MAX << (63 - end);
454 } else if (likely(end == 63)) {
455 ret = UINT64_MAX >> start;
456 }
457 #else
458 if (likely(start == 0)) {
459 ret = UINT32_MAX << (31 - end);
460 } else if (likely(end == 31)) {
461 ret = UINT32_MAX >> start;
462 }
463 #endif
464 else {
465 ret = (((target_ulong)(-1ULL)) >> (start)) ^
466 (((target_ulong)(-1ULL) >> (end)) >> 1);
467 if (unlikely(start > end))
468 return ~ret;
469 }
470
471 return ret;
472 }
473
474 /*****************************************************************************/
475 /* PowerPC instructions table */
476
477 #if defined(DO_PPC_STATISTICS)
478 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
479 { \
480 .opc1 = op1, \
481 .opc2 = op2, \
482 .opc3 = op3, \
483 .pad = { 0, }, \
484 .handler = { \
485 .inval1 = invl, \
486 .type = _typ, \
487 .type2 = _typ2, \
488 .handler = &gen_##name, \
489 .oname = stringify(name), \
490 }, \
491 .oname = stringify(name), \
492 }
493 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
494 { \
495 .opc1 = op1, \
496 .opc2 = op2, \
497 .opc3 = op3, \
498 .pad = { 0, }, \
499 .handler = { \
500 .inval1 = invl1, \
501 .inval2 = invl2, \
502 .type = _typ, \
503 .type2 = _typ2, \
504 .handler = &gen_##name, \
505 .oname = stringify(name), \
506 }, \
507 .oname = stringify(name), \
508 }
509 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
510 { \
511 .opc1 = op1, \
512 .opc2 = op2, \
513 .opc3 = op3, \
514 .pad = { 0, }, \
515 .handler = { \
516 .inval1 = invl, \
517 .type = _typ, \
518 .type2 = _typ2, \
519 .handler = &gen_##name, \
520 .oname = onam, \
521 }, \
522 .oname = onam, \
523 }
524 #else
525 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
526 { \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl, \
533 .type = _typ, \
534 .type2 = _typ2, \
535 .handler = &gen_##name, \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
548 .type = _typ, \
549 .type2 = _typ2, \
550 .handler = &gen_##name, \
551 }, \
552 .oname = stringify(name), \
553 }
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555 { \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 }, \
566 .oname = onam, \
567 }
568 #endif
569
570 /* SPR load/store helpers */
571 static inline void gen_load_spr(TCGv t, int reg)
572 {
573 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
574 }
575
576 static inline void gen_store_spr(int reg, TCGv t)
577 {
578 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 /* Invalid instruction */
582 static void gen_invalid(DisasContext *ctx)
583 {
584 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
585 }
586
587 static opc_handler_t invalid_handler = {
588 .inval1 = 0xFFFFFFFF,
589 .inval2 = 0xFFFFFFFF,
590 .type = PPC_NONE,
591 .type2 = PPC_NONE,
592 .handler = gen_invalid,
593 };
594
595 /*** Integer comparison ***/
596
597 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
598 {
599 TCGv t0 = tcg_temp_new();
600 TCGv_i32 t1 = tcg_temp_new_i32();
601
602 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
603
604 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
605 tcg_gen_trunc_tl_i32(t1, t0);
606 tcg_gen_shli_i32(t1, t1, CRF_LT);
607 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_GT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_EQ);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_temp_free(t0);
620 tcg_temp_free_i32(t1);
621 }
622
623 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
624 {
625 TCGv t0 = tcg_const_tl(arg1);
626 gen_op_cmp(arg0, t0, s, crf);
627 tcg_temp_free(t0);
628 }
629
630 #if defined(TARGET_PPC64)
631 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
632 {
633 TCGv t0, t1;
634 t0 = tcg_temp_new();
635 t1 = tcg_temp_new();
636 if (s) {
637 tcg_gen_ext32s_tl(t0, arg0);
638 tcg_gen_ext32s_tl(t1, arg1);
639 } else {
640 tcg_gen_ext32u_tl(t0, arg0);
641 tcg_gen_ext32u_tl(t1, arg1);
642 }
643 gen_op_cmp(t0, t1, s, crf);
644 tcg_temp_free(t1);
645 tcg_temp_free(t0);
646 }
647
648 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
649 {
650 TCGv t0 = tcg_const_tl(arg1);
651 gen_op_cmp32(arg0, t0, s, crf);
652 tcg_temp_free(t0);
653 }
654 #endif
655
656 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
657 {
658 #if defined(TARGET_PPC64)
659 if (!(ctx->sf_mode))
660 gen_op_cmpi32(reg, 0, 1, 0);
661 else
662 #endif
663 gen_op_cmpi(reg, 0, 1, 0);
664 }
665
666 /* cmp */
667 static void gen_cmp(DisasContext *ctx)
668 {
669 #if defined(TARGET_PPC64)
670 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
671 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 else
674 #endif
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678
679 /* cmpi */
680 static void gen_cmpi(DisasContext *ctx)
681 {
682 #if defined(TARGET_PPC64)
683 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 else
687 #endif
688 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
689 1, crfD(ctx->opcode));
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 #if defined(TARGET_PPC64)
696 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 else
700 #endif
701 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
702 0, crfD(ctx->opcode));
703 }
704
705 /* cmpli */
706 static void gen_cmpli(DisasContext *ctx)
707 {
708 #if defined(TARGET_PPC64)
709 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
710 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712 else
713 #endif
714 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
715 0, crfD(ctx->opcode));
716 }
717
718 /* isel (PowerPC 2.03 specification) */
719 static void gen_isel(DisasContext *ctx)
720 {
721 int l1, l2;
722 uint32_t bi = rC(ctx->opcode);
723 uint32_t mask;
724 TCGv_i32 t0;
725
726 l1 = gen_new_label();
727 l2 = gen_new_label();
728
729 mask = 1 << (3 - (bi & 0x03));
730 t0 = tcg_temp_new_i32();
731 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
732 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
733 if (rA(ctx->opcode) == 0)
734 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
735 else
736 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
737 tcg_gen_br(l2);
738 gen_set_label(l1);
739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
740 gen_set_label(l2);
741 tcg_temp_free_i32(t0);
742 }
743
744 /*** Integer arithmetic ***/
745
746 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
747 TCGv arg1, TCGv arg2, int sub)
748 {
749 TCGv t0 = tcg_temp_new();
750
751 tcg_gen_xor_tl(cpu_ov, arg0, arg1);
752 tcg_gen_xor_tl(t0, arg1, arg2);
753 if (sub) {
754 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
755 } else {
756 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
757 }
758 tcg_temp_free(t0);
759 #if defined(TARGET_PPC64)
760 if (!ctx->sf_mode) {
761 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
762 }
763 #endif
764 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
765 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
766 }
767
768 static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
769 TCGv arg2, int sub)
770 {
771 int l1 = gen_new_label();
772
773 #if defined(TARGET_PPC64)
774 if (!(ctx->sf_mode)) {
775 TCGv t0, t1;
776 t0 = tcg_temp_new();
777 t1 = tcg_temp_new();
778
779 tcg_gen_ext32u_tl(t0, arg1);
780 tcg_gen_ext32u_tl(t1, arg2);
781 if (sub) {
782 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
783 } else {
784 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
785 }
786 tcg_gen_movi_tl(cpu_ca, 1);
787 gen_set_label(l1);
788 tcg_temp_free(t0);
789 tcg_temp_free(t1);
790 } else
791 #endif
792 {
793 if (sub) {
794 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
795 } else {
796 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
797 }
798 tcg_gen_movi_tl(cpu_ca, 1);
799 gen_set_label(l1);
800 }
801 }
802
803 /* Common add function */
804 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
805 TCGv arg2, int add_ca, int compute_ca,
806 int compute_ov)
807 {
808 TCGv t0, t1;
809
810 if ((!compute_ca && !compute_ov) ||
811 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
812 t0 = ret;
813 } else {
814 t0 = tcg_temp_local_new();
815 }
816
817 if (add_ca) {
818 t1 = tcg_temp_local_new();
819 tcg_gen_mov_tl(t1, cpu_ca);
820 } else {
821 TCGV_UNUSED(t1);
822 }
823
824 if (compute_ca) {
825 /* Start with XER CA disabled, the most likely case */
826 tcg_gen_movi_tl(cpu_ca, 0);
827 }
828
829 tcg_gen_add_tl(t0, arg1, arg2);
830
831 if (compute_ca) {
832 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
833 }
834 if (add_ca) {
835 tcg_gen_add_tl(t0, t0, t1);
836 gen_op_arith_compute_ca(ctx, t0, t1, 0);
837 tcg_temp_free(t1);
838 }
839 if (compute_ov) {
840 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
841 }
842
843 if (unlikely(Rc(ctx->opcode) != 0))
844 gen_set_Rc0(ctx, t0);
845
846 if (!TCGV_EQUAL(t0, ret)) {
847 tcg_gen_mov_tl(ret, t0);
848 tcg_temp_free(t0);
849 }
850 }
851 /* Add functions with two operands */
852 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
853 static void glue(gen_, name)(DisasContext *ctx) \
854 { \
855 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
856 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
857 add_ca, compute_ca, compute_ov); \
858 }
859 /* Add functions with one operand and one immediate */
860 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
861 add_ca, compute_ca, compute_ov) \
862 static void glue(gen_, name)(DisasContext *ctx) \
863 { \
864 TCGv t0 = tcg_const_local_tl(const_val); \
865 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
866 cpu_gpr[rA(ctx->opcode)], t0, \
867 add_ca, compute_ca, compute_ov); \
868 tcg_temp_free(t0); \
869 }
870
871 /* add add. addo addo. */
872 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
873 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
874 /* addc addc. addco addco. */
875 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
876 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
877 /* adde adde. addeo addeo. */
878 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
879 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
880 /* addme addme. addmeo addmeo. */
881 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
882 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
883 /* addze addze. addzeo addzeo.*/
884 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
885 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
886 /* addi */
887 static void gen_addi(DisasContext *ctx)
888 {
889 target_long simm = SIMM(ctx->opcode);
890
891 if (rA(ctx->opcode) == 0) {
892 /* li case */
893 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
894 } else {
895 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
896 }
897 }
898 /* addic addic.*/
899 static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
900 int compute_Rc0)
901 {
902 target_long simm = SIMM(ctx->opcode);
903
904 /* Start with XER CA disabled, the most likely case */
905 tcg_gen_movi_tl(cpu_ca, 0);
906
907 if (likely(simm != 0)) {
908 TCGv t0 = tcg_temp_local_new();
909 tcg_gen_addi_tl(t0, arg1, simm);
910 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
911 tcg_gen_mov_tl(ret, t0);
912 tcg_temp_free(t0);
913 } else {
914 tcg_gen_mov_tl(ret, arg1);
915 }
916 if (compute_Rc0) {
917 gen_set_Rc0(ctx, ret);
918 }
919 }
920
921 static void gen_addic(DisasContext *ctx)
922 {
923 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
924 }
925
926 static void gen_addic_(DisasContext *ctx)
927 {
928 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
929 }
930
931 /* addis */
932 static void gen_addis(DisasContext *ctx)
933 {
934 target_long simm = SIMM(ctx->opcode);
935
936 if (rA(ctx->opcode) == 0) {
937 /* lis case */
938 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
939 } else {
940 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
941 }
942 }
943
944 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
945 TCGv arg2, int sign, int compute_ov)
946 {
947 int l1 = gen_new_label();
948 int l2 = gen_new_label();
949 TCGv_i32 t0 = tcg_temp_local_new_i32();
950 TCGv_i32 t1 = tcg_temp_local_new_i32();
951
952 tcg_gen_trunc_tl_i32(t0, arg1);
953 tcg_gen_trunc_tl_i32(t1, arg2);
954 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
955 if (sign) {
956 int l3 = gen_new_label();
957 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
958 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
959 gen_set_label(l3);
960 tcg_gen_div_i32(t0, t0, t1);
961 } else {
962 tcg_gen_divu_i32(t0, t0, t1);
963 }
964 if (compute_ov) {
965 tcg_gen_movi_tl(cpu_ov, 0);
966 }
967 tcg_gen_br(l2);
968 gen_set_label(l1);
969 if (sign) {
970 tcg_gen_sari_i32(t0, t0, 31);
971 } else {
972 tcg_gen_movi_i32(t0, 0);
973 }
974 if (compute_ov) {
975 tcg_gen_movi_tl(cpu_ov, 1);
976 tcg_gen_movi_tl(cpu_so, 1);
977 }
978 gen_set_label(l2);
979 tcg_gen_extu_i32_tl(ret, t0);
980 tcg_temp_free_i32(t0);
981 tcg_temp_free_i32(t1);
982 if (unlikely(Rc(ctx->opcode) != 0))
983 gen_set_Rc0(ctx, ret);
984 }
985 /* Div functions */
986 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
987 static void glue(gen_, name)(DisasContext *ctx) \
988 { \
989 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
990 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
991 sign, compute_ov); \
992 }
993 /* divwu divwu. divwuo divwuo. */
994 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
995 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
996 /* divw divw. divwo divwo. */
997 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
998 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
999 #if defined(TARGET_PPC64)
1000 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1001 TCGv arg2, int sign, int compute_ov)
1002 {
1003 int l1 = gen_new_label();
1004 int l2 = gen_new_label();
1005
1006 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1007 if (sign) {
1008 int l3 = gen_new_label();
1009 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1010 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1011 gen_set_label(l3);
1012 tcg_gen_div_i64(ret, arg1, arg2);
1013 } else {
1014 tcg_gen_divu_i64(ret, arg1, arg2);
1015 }
1016 if (compute_ov) {
1017 tcg_gen_movi_tl(cpu_ov, 0);
1018 }
1019 tcg_gen_br(l2);
1020 gen_set_label(l1);
1021 if (sign) {
1022 tcg_gen_sari_i64(ret, arg1, 63);
1023 } else {
1024 tcg_gen_movi_i64(ret, 0);
1025 }
1026 if (compute_ov) {
1027 tcg_gen_movi_tl(cpu_ov, 1);
1028 tcg_gen_movi_tl(cpu_so, 1);
1029 }
1030 gen_set_label(l2);
1031 if (unlikely(Rc(ctx->opcode) != 0))
1032 gen_set_Rc0(ctx, ret);
1033 }
1034 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1035 static void glue(gen_, name)(DisasContext *ctx) \
1036 { \
1037 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1038 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1039 sign, compute_ov); \
1040 }
1041 /* divwu divwu. divwuo divwuo. */
1042 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1043 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1044 /* divw divw. divwo divwo. */
1045 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1046 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1047 #endif
1048
1049 /* mulhw mulhw. */
1050 static void gen_mulhw(DisasContext *ctx)
1051 {
1052 TCGv_i32 t0 = tcg_temp_new_i32();
1053 TCGv_i32 t1 = tcg_temp_new_i32();
1054
1055 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1056 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1057 tcg_gen_muls2_i32(t0, t1, t0, t1);
1058 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1059 tcg_temp_free_i32(t0);
1060 tcg_temp_free_i32(t1);
1061 if (unlikely(Rc(ctx->opcode) != 0))
1062 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1063 }
1064
1065 /* mulhwu mulhwu. */
1066 static void gen_mulhwu(DisasContext *ctx)
1067 {
1068 TCGv_i32 t0 = tcg_temp_new_i32();
1069 TCGv_i32 t1 = tcg_temp_new_i32();
1070
1071 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1072 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1073 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1074 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1075 tcg_temp_free_i32(t0);
1076 tcg_temp_free_i32(t1);
1077 if (unlikely(Rc(ctx->opcode) != 0))
1078 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1079 }
1080
1081 /* mullw mullw. */
1082 static void gen_mullw(DisasContext *ctx)
1083 {
1084 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1085 cpu_gpr[rB(ctx->opcode)]);
1086 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1087 if (unlikely(Rc(ctx->opcode) != 0))
1088 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1089 }
1090
1091 /* mullwo mullwo. */
1092 static void gen_mullwo(DisasContext *ctx)
1093 {
1094 int l1;
1095 TCGv_i64 t0, t1;
1096
1097 t0 = tcg_temp_new_i64();
1098 t1 = tcg_temp_new_i64();
1099 l1 = gen_new_label();
1100 /* Start with XER OV disabled, the most likely case */
1101 tcg_gen_movi_tl(cpu_ov, 0);
1102 #if defined(TARGET_PPC64)
1103 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1104 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1105 #else
1106 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1107 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1108 #endif
1109 tcg_gen_mul_i64(t0, t0, t1);
1110 #if defined(TARGET_PPC64)
1111 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1112 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1113 #else
1114 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1115 tcg_gen_ext32s_i64(t1, t0);
1116 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1117 #endif
1118 tcg_gen_movi_tl(cpu_ov, 1);
1119 tcg_gen_movi_tl(cpu_so, 1);
1120 gen_set_label(l1);
1121 tcg_temp_free_i64(t0);
1122 tcg_temp_free_i64(t1);
1123 if (unlikely(Rc(ctx->opcode) != 0))
1124 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1125 }
1126
1127 /* mulli */
1128 static void gen_mulli(DisasContext *ctx)
1129 {
1130 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1131 SIMM(ctx->opcode));
1132 }
1133
1134 #if defined(TARGET_PPC64)
1135 /* mulhd mulhd. */
1136 static void gen_mulhd(DisasContext *ctx)
1137 {
1138 TCGv lo = tcg_temp_new();
1139 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1140 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1141 tcg_temp_free(lo);
1142 if (unlikely(Rc(ctx->opcode) != 0)) {
1143 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1144 }
1145 }
1146
1147 /* mulhdu mulhdu. */
1148 static void gen_mulhdu(DisasContext *ctx)
1149 {
1150 TCGv lo = tcg_temp_new();
1151 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1152 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1153 tcg_temp_free(lo);
1154 if (unlikely(Rc(ctx->opcode) != 0)) {
1155 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1156 }
1157 }
1158
1159 /* mulld mulld. */
1160 static void gen_mulld(DisasContext *ctx)
1161 {
1162 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1163 cpu_gpr[rB(ctx->opcode)]);
1164 if (unlikely(Rc(ctx->opcode) != 0))
1165 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1166 }
1167
1168 /* mulldo mulldo. */
1169 static void gen_mulldo(DisasContext *ctx)
1170 {
1171 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1172 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1173 if (unlikely(Rc(ctx->opcode) != 0)) {
1174 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1175 }
1176 }
1177 #endif
1178
1179 /* neg neg. nego nego. */
1180 static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1181 int ov_check)
1182 {
1183 int l1 = gen_new_label();
1184 int l2 = gen_new_label();
1185 TCGv t0 = tcg_temp_local_new();
1186 #if defined(TARGET_PPC64)
1187 if (ctx->sf_mode) {
1188 tcg_gen_mov_tl(t0, arg1);
1189 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1190 } else
1191 #endif
1192 {
1193 tcg_gen_ext32s_tl(t0, arg1);
1194 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1195 }
1196 tcg_gen_neg_tl(ret, arg1);
1197 if (ov_check) {
1198 tcg_gen_movi_tl(cpu_ov, 0);
1199 }
1200 tcg_gen_br(l2);
1201 gen_set_label(l1);
1202 tcg_gen_mov_tl(ret, t0);
1203 if (ov_check) {
1204 tcg_gen_movi_tl(cpu_ov, 1);
1205 tcg_gen_movi_tl(cpu_so, 1);
1206 }
1207 gen_set_label(l2);
1208 tcg_temp_free(t0);
1209 if (unlikely(Rc(ctx->opcode) != 0))
1210 gen_set_Rc0(ctx, ret);
1211 }
1212
1213 static void gen_neg(DisasContext *ctx)
1214 {
1215 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1216 }
1217
1218 static void gen_nego(DisasContext *ctx)
1219 {
1220 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1221 }
1222
1223 /* Common subf function */
1224 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1225 TCGv arg2, int add_ca, int compute_ca,
1226 int compute_ov)
1227 {
1228 TCGv t0, t1;
1229
1230 if ((!compute_ca && !compute_ov) ||
1231 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1232 t0 = ret;
1233 } else {
1234 t0 = tcg_temp_local_new();
1235 }
1236
1237 if (add_ca) {
1238 t1 = tcg_temp_local_new();
1239 tcg_gen_mov_tl(t1, cpu_ca);
1240 } else {
1241 TCGV_UNUSED(t1);
1242 }
1243
1244 if (compute_ca) {
1245 /* Start with XER CA disabled, the most likely case */
1246 tcg_gen_movi_tl(cpu_ca, 0);
1247 }
1248
1249 if (add_ca) {
1250 tcg_gen_not_tl(t0, arg1);
1251 tcg_gen_add_tl(t0, t0, arg2);
1252 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1253 tcg_gen_add_tl(t0, t0, t1);
1254 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1255 tcg_temp_free(t1);
1256 } else {
1257 tcg_gen_sub_tl(t0, arg2, arg1);
1258 if (compute_ca) {
1259 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1260 }
1261 }
1262 if (compute_ov) {
1263 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1264 }
1265
1266 if (unlikely(Rc(ctx->opcode) != 0))
1267 gen_set_Rc0(ctx, t0);
1268
1269 if (!TCGV_EQUAL(t0, ret)) {
1270 tcg_gen_mov_tl(ret, t0);
1271 tcg_temp_free(t0);
1272 }
1273 }
1274 /* Sub functions with Two operands functions */
1275 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1276 static void glue(gen_, name)(DisasContext *ctx) \
1277 { \
1278 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1279 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1280 add_ca, compute_ca, compute_ov); \
1281 }
1282 /* Sub functions with one operand and one immediate */
1283 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1284 add_ca, compute_ca, compute_ov) \
1285 static void glue(gen_, name)(DisasContext *ctx) \
1286 { \
1287 TCGv t0 = tcg_const_local_tl(const_val); \
1288 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1289 cpu_gpr[rA(ctx->opcode)], t0, \
1290 add_ca, compute_ca, compute_ov); \
1291 tcg_temp_free(t0); \
1292 }
1293 /* subf subf. subfo subfo. */
1294 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1295 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1296 /* subfc subfc. subfco subfco. */
1297 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1298 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1299 /* subfe subfe. subfeo subfo. */
1300 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1301 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1302 /* subfme subfme. subfmeo subfmeo. */
1303 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1304 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1305 /* subfze subfze. subfzeo subfzeo.*/
1306 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1307 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1308
1309 /* subfic */
1310 static void gen_subfic(DisasContext *ctx)
1311 {
1312 /* Start with XER CA disabled, the most likely case */
1313 tcg_gen_movi_tl(cpu_ca, 0);
1314 TCGv t0 = tcg_temp_local_new();
1315 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1316 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1317 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1318 tcg_temp_free(t1);
1319 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1320 tcg_temp_free(t0);
1321 }
1322
1323 /*** Integer logical ***/
1324 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1325 static void glue(gen_, name)(DisasContext *ctx) \
1326 { \
1327 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1328 cpu_gpr[rB(ctx->opcode)]); \
1329 if (unlikely(Rc(ctx->opcode) != 0)) \
1330 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1331 }
1332
1333 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1334 static void glue(gen_, name)(DisasContext *ctx) \
1335 { \
1336 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1337 if (unlikely(Rc(ctx->opcode) != 0)) \
1338 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1339 }
1340
1341 /* and & and. */
1342 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1343 /* andc & andc. */
1344 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1345
1346 /* andi. */
1347 static void gen_andi_(DisasContext *ctx)
1348 {
1349 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1350 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1351 }
1352
1353 /* andis. */
1354 static void gen_andis_(DisasContext *ctx)
1355 {
1356 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1357 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1358 }
1359
1360 /* cntlzw */
1361 static void gen_cntlzw(DisasContext *ctx)
1362 {
1363 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1364 if (unlikely(Rc(ctx->opcode) != 0))
1365 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1366 }
1367 /* eqv & eqv. */
1368 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1369 /* extsb & extsb. */
1370 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1371 /* extsh & extsh. */
1372 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1373 /* nand & nand. */
1374 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1375 /* nor & nor. */
1376 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1377
1378 /* or & or. */
1379 static void gen_or(DisasContext *ctx)
1380 {
1381 int rs, ra, rb;
1382
1383 rs = rS(ctx->opcode);
1384 ra = rA(ctx->opcode);
1385 rb = rB(ctx->opcode);
1386 /* Optimisation for mr. ri case */
1387 if (rs != ra || rs != rb) {
1388 if (rs != rb)
1389 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1390 else
1391 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1392 if (unlikely(Rc(ctx->opcode) != 0))
1393 gen_set_Rc0(ctx, cpu_gpr[ra]);
1394 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1395 gen_set_Rc0(ctx, cpu_gpr[rs]);
1396 #if defined(TARGET_PPC64)
1397 } else {
1398 int prio = 0;
1399
1400 switch (rs) {
1401 case 1:
1402 /* Set process priority to low */
1403 prio = 2;
1404 break;
1405 case 6:
1406 /* Set process priority to medium-low */
1407 prio = 3;
1408 break;
1409 case 2:
1410 /* Set process priority to normal */
1411 prio = 4;
1412 break;
1413 #if !defined(CONFIG_USER_ONLY)
1414 case 31:
1415 if (ctx->mem_idx > 0) {
1416 /* Set process priority to very low */
1417 prio = 1;
1418 }
1419 break;
1420 case 5:
1421 if (ctx->mem_idx > 0) {
1422 /* Set process priority to medium-hight */
1423 prio = 5;
1424 }
1425 break;
1426 case 3:
1427 if (ctx->mem_idx > 0) {
1428 /* Set process priority to high */
1429 prio = 6;
1430 }
1431 break;
1432 case 7:
1433 if (ctx->mem_idx > 1) {
1434 /* Set process priority to very high */
1435 prio = 7;
1436 }
1437 break;
1438 #endif
1439 default:
1440 /* nop */
1441 break;
1442 }
1443 if (prio) {
1444 TCGv t0 = tcg_temp_new();
1445 gen_load_spr(t0, SPR_PPR);
1446 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1447 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1448 gen_store_spr(SPR_PPR, t0);
1449 tcg_temp_free(t0);
1450 }
1451 #endif
1452 }
1453 }
1454 /* orc & orc. */
1455 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1456
1457 /* xor & xor. */
1458 static void gen_xor(DisasContext *ctx)
1459 {
1460 /* Optimisation for "set to zero" case */
1461 if (rS(ctx->opcode) != rB(ctx->opcode))
1462 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1463 else
1464 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1465 if (unlikely(Rc(ctx->opcode) != 0))
1466 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1467 }
1468
1469 /* ori */
1470 static void gen_ori(DisasContext *ctx)
1471 {
1472 target_ulong uimm = UIMM(ctx->opcode);
1473
1474 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1475 /* NOP */
1476 /* XXX: should handle special NOPs for POWER series */
1477 return;
1478 }
1479 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1480 }
1481
1482 /* oris */
1483 static void gen_oris(DisasContext *ctx)
1484 {
1485 target_ulong uimm = UIMM(ctx->opcode);
1486
1487 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1488 /* NOP */
1489 return;
1490 }
1491 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1492 }
1493
1494 /* xori */
1495 static void gen_xori(DisasContext *ctx)
1496 {
1497 target_ulong uimm = UIMM(ctx->opcode);
1498
1499 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1500 /* NOP */
1501 return;
1502 }
1503 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1504 }
1505
1506 /* xoris */
1507 static void gen_xoris(DisasContext *ctx)
1508 {
1509 target_ulong uimm = UIMM(ctx->opcode);
1510
1511 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1512 /* NOP */
1513 return;
1514 }
1515 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1516 }
1517
1518 /* popcntb : PowerPC 2.03 specification */
1519 static void gen_popcntb(DisasContext *ctx)
1520 {
1521 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1522 }
1523
1524 static void gen_popcntw(DisasContext *ctx)
1525 {
1526 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1527 }
1528
1529 #if defined(TARGET_PPC64)
1530 /* popcntd: PowerPC 2.06 specification */
1531 static void gen_popcntd(DisasContext *ctx)
1532 {
1533 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1534 }
1535 #endif
1536
1537 #if defined(TARGET_PPC64)
1538 /* extsw & extsw. */
1539 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1540
1541 /* cntlzd */
1542 static void gen_cntlzd(DisasContext *ctx)
1543 {
1544 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1545 if (unlikely(Rc(ctx->opcode) != 0))
1546 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1547 }
1548 #endif
1549
1550 /*** Integer rotate ***/
1551
1552 /* rlwimi & rlwimi. */
1553 static void gen_rlwimi(DisasContext *ctx)
1554 {
1555 uint32_t mb, me, sh;
1556
1557 mb = MB(ctx->opcode);
1558 me = ME(ctx->opcode);
1559 sh = SH(ctx->opcode);
1560 if (likely(sh == 0 && mb == 0 && me == 31)) {
1561 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1562 } else {
1563 target_ulong mask;
1564 TCGv t1;
1565 TCGv t0 = tcg_temp_new();
1566 #if defined(TARGET_PPC64)
1567 TCGv_i32 t2 = tcg_temp_new_i32();
1568 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1569 tcg_gen_rotli_i32(t2, t2, sh);
1570 tcg_gen_extu_i32_i64(t0, t2);
1571 tcg_temp_free_i32(t2);
1572 #else
1573 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1574 #endif
1575 #if defined(TARGET_PPC64)
1576 mb += 32;
1577 me += 32;
1578 #endif
1579 mask = MASK(mb, me);
1580 t1 = tcg_temp_new();
1581 tcg_gen_andi_tl(t0, t0, mask);
1582 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1583 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1584 tcg_temp_free(t0);
1585 tcg_temp_free(t1);
1586 }
1587 if (unlikely(Rc(ctx->opcode) != 0))
1588 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1589 }
1590
1591 /* rlwinm & rlwinm. */
1592 static void gen_rlwinm(DisasContext *ctx)
1593 {
1594 uint32_t mb, me, sh;
1595
1596 sh = SH(ctx->opcode);
1597 mb = MB(ctx->opcode);
1598 me = ME(ctx->opcode);
1599
1600 if (likely(mb == 0 && me == (31 - sh))) {
1601 if (likely(sh == 0)) {
1602 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1603 } else {
1604 TCGv t0 = tcg_temp_new();
1605 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1606 tcg_gen_shli_tl(t0, t0, sh);
1607 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1608 tcg_temp_free(t0);
1609 }
1610 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1611 TCGv t0 = tcg_temp_new();
1612 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1613 tcg_gen_shri_tl(t0, t0, mb);
1614 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1615 tcg_temp_free(t0);
1616 } else {
1617 TCGv t0 = tcg_temp_new();
1618 #if defined(TARGET_PPC64)
1619 TCGv_i32 t1 = tcg_temp_new_i32();
1620 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1621 tcg_gen_rotli_i32(t1, t1, sh);
1622 tcg_gen_extu_i32_i64(t0, t1);
1623 tcg_temp_free_i32(t1);
1624 #else
1625 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1626 #endif
1627 #if defined(TARGET_PPC64)
1628 mb += 32;
1629 me += 32;
1630 #endif
1631 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1632 tcg_temp_free(t0);
1633 }
1634 if (unlikely(Rc(ctx->opcode) != 0))
1635 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1636 }
1637
1638 /* rlwnm & rlwnm. */
1639 static void gen_rlwnm(DisasContext *ctx)
1640 {
1641 uint32_t mb, me;
1642 TCGv t0;
1643 #if defined(TARGET_PPC64)
1644 TCGv_i32 t1, t2;
1645 #endif
1646
1647 mb = MB(ctx->opcode);
1648 me = ME(ctx->opcode);
1649 t0 = tcg_temp_new();
1650 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1651 #if defined(TARGET_PPC64)
1652 t1 = tcg_temp_new_i32();
1653 t2 = tcg_temp_new_i32();
1654 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1655 tcg_gen_trunc_i64_i32(t2, t0);
1656 tcg_gen_rotl_i32(t1, t1, t2);
1657 tcg_gen_extu_i32_i64(t0, t1);
1658 tcg_temp_free_i32(t1);
1659 tcg_temp_free_i32(t2);
1660 #else
1661 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1662 #endif
1663 if (unlikely(mb != 0 || me != 31)) {
1664 #if defined(TARGET_PPC64)
1665 mb += 32;
1666 me += 32;
1667 #endif
1668 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1669 } else {
1670 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1671 }
1672 tcg_temp_free(t0);
1673 if (unlikely(Rc(ctx->opcode) != 0))
1674 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1675 }
1676
1677 #if defined(TARGET_PPC64)
1678 #define GEN_PPC64_R2(name, opc1, opc2) \
1679 static void glue(gen_, name##0)(DisasContext *ctx) \
1680 { \
1681 gen_##name(ctx, 0); \
1682 } \
1683 \
1684 static void glue(gen_, name##1)(DisasContext *ctx) \
1685 { \
1686 gen_##name(ctx, 1); \
1687 }
1688 #define GEN_PPC64_R4(name, opc1, opc2) \
1689 static void glue(gen_, name##0)(DisasContext *ctx) \
1690 { \
1691 gen_##name(ctx, 0, 0); \
1692 } \
1693 \
1694 static void glue(gen_, name##1)(DisasContext *ctx) \
1695 { \
1696 gen_##name(ctx, 0, 1); \
1697 } \
1698 \
1699 static void glue(gen_, name##2)(DisasContext *ctx) \
1700 { \
1701 gen_##name(ctx, 1, 0); \
1702 } \
1703 \
1704 static void glue(gen_, name##3)(DisasContext *ctx) \
1705 { \
1706 gen_##name(ctx, 1, 1); \
1707 }
1708
1709 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1710 uint32_t sh)
1711 {
1712 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1713 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1714 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1715 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1716 } else {
1717 TCGv t0 = tcg_temp_new();
1718 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1719 if (likely(mb == 0 && me == 63)) {
1720 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1721 } else {
1722 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1723 }
1724 tcg_temp_free(t0);
1725 }
1726 if (unlikely(Rc(ctx->opcode) != 0))
1727 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1728 }
1729 /* rldicl - rldicl. */
1730 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1731 {
1732 uint32_t sh, mb;
1733
1734 sh = SH(ctx->opcode) | (shn << 5);
1735 mb = MB(ctx->opcode) | (mbn << 5);
1736 gen_rldinm(ctx, mb, 63, sh);
1737 }
1738 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1739 /* rldicr - rldicr. */
1740 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1741 {
1742 uint32_t sh, me;
1743
1744 sh = SH(ctx->opcode) | (shn << 5);
1745 me = MB(ctx->opcode) | (men << 5);
1746 gen_rldinm(ctx, 0, me, sh);
1747 }
1748 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1749 /* rldic - rldic. */
1750 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1751 {
1752 uint32_t sh, mb;
1753
1754 sh = SH(ctx->opcode) | (shn << 5);
1755 mb = MB(ctx->opcode) | (mbn << 5);
1756 gen_rldinm(ctx, mb, 63 - sh, sh);
1757 }
1758 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1759
1760 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1761 {
1762 TCGv t0;
1763
1764 mb = MB(ctx->opcode);
1765 me = ME(ctx->opcode);
1766 t0 = tcg_temp_new();
1767 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1768 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1769 if (unlikely(mb != 0 || me != 63)) {
1770 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1771 } else {
1772 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1773 }
1774 tcg_temp_free(t0);
1775 if (unlikely(Rc(ctx->opcode) != 0))
1776 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1777 }
1778
1779 /* rldcl - rldcl. */
1780 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1781 {
1782 uint32_t mb;
1783
1784 mb = MB(ctx->opcode) | (mbn << 5);
1785 gen_rldnm(ctx, mb, 63);
1786 }
1787 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1788 /* rldcr - rldcr. */
1789 static inline void gen_rldcr(DisasContext *ctx, int men)
1790 {
1791 uint32_t me;
1792
1793 me = MB(ctx->opcode) | (men << 5);
1794 gen_rldnm(ctx, 0, me);
1795 }
1796 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1797 /* rldimi - rldimi. */
1798 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1799 {
1800 uint32_t sh, mb, me;
1801
1802 sh = SH(ctx->opcode) | (shn << 5);
1803 mb = MB(ctx->opcode) | (mbn << 5);
1804 me = 63 - sh;
1805 if (unlikely(sh == 0 && mb == 0)) {
1806 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1807 } else {
1808 TCGv t0, t1;
1809 target_ulong mask;
1810
1811 t0 = tcg_temp_new();
1812 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1813 t1 = tcg_temp_new();
1814 mask = MASK(mb, me);
1815 tcg_gen_andi_tl(t0, t0, mask);
1816 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1817 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1818 tcg_temp_free(t0);
1819 tcg_temp_free(t1);
1820 }
1821 if (unlikely(Rc(ctx->opcode) != 0))
1822 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1823 }
1824 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1825 #endif
1826
1827 /*** Integer shift ***/
1828
1829 /* slw & slw. */
1830 static void gen_slw(DisasContext *ctx)
1831 {
1832 TCGv t0, t1;
1833
1834 t0 = tcg_temp_new();
1835 /* AND rS with a mask that is 0 when rB >= 0x20 */
1836 #if defined(TARGET_PPC64)
1837 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1838 tcg_gen_sari_tl(t0, t0, 0x3f);
1839 #else
1840 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1841 tcg_gen_sari_tl(t0, t0, 0x1f);
1842 #endif
1843 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1844 t1 = tcg_temp_new();
1845 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1846 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1847 tcg_temp_free(t1);
1848 tcg_temp_free(t0);
1849 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1850 if (unlikely(Rc(ctx->opcode) != 0))
1851 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1852 }
1853
1854 /* sraw & sraw. */
1855 static void gen_sraw(DisasContext *ctx)
1856 {
1857 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1858 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1859 if (unlikely(Rc(ctx->opcode) != 0))
1860 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1861 }
1862
1863 /* srawi & srawi. */
1864 static void gen_srawi(DisasContext *ctx)
1865 {
1866 int sh = SH(ctx->opcode);
1867 if (sh != 0) {
1868 int l1, l2;
1869 TCGv t0;
1870 l1 = gen_new_label();
1871 l2 = gen_new_label();
1872 t0 = tcg_temp_local_new();
1873 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1874 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1875 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1876 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1877 tcg_gen_movi_tl(cpu_ca, 1);
1878 tcg_gen_br(l2);
1879 gen_set_label(l1);
1880 tcg_gen_movi_tl(cpu_ca, 0);
1881 gen_set_label(l2);
1882 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1883 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1884 tcg_temp_free(t0);
1885 } else {
1886 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1887 tcg_gen_movi_tl(cpu_ca, 0);
1888 }
1889 if (unlikely(Rc(ctx->opcode) != 0))
1890 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1891 }
1892
1893 /* srw & srw. */
1894 static void gen_srw(DisasContext *ctx)
1895 {
1896 TCGv t0, t1;
1897
1898 t0 = tcg_temp_new();
1899 /* AND rS with a mask that is 0 when rB >= 0x20 */
1900 #if defined(TARGET_PPC64)
1901 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1902 tcg_gen_sari_tl(t0, t0, 0x3f);
1903 #else
1904 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1905 tcg_gen_sari_tl(t0, t0, 0x1f);
1906 #endif
1907 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1908 tcg_gen_ext32u_tl(t0, t0);
1909 t1 = tcg_temp_new();
1910 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1911 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1912 tcg_temp_free(t1);
1913 tcg_temp_free(t0);
1914 if (unlikely(Rc(ctx->opcode) != 0))
1915 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1916 }
1917
1918 #if defined(TARGET_PPC64)
1919 /* sld & sld. */
1920 static void gen_sld(DisasContext *ctx)
1921 {
1922 TCGv t0, t1;
1923
1924 t0 = tcg_temp_new();
1925 /* AND rS with a mask that is 0 when rB >= 0x40 */
1926 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1927 tcg_gen_sari_tl(t0, t0, 0x3f);
1928 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1929 t1 = tcg_temp_new();
1930 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1931 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1932 tcg_temp_free(t1);
1933 tcg_temp_free(t0);
1934 if (unlikely(Rc(ctx->opcode) != 0))
1935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1936 }
1937
1938 /* srad & srad. */
1939 static void gen_srad(DisasContext *ctx)
1940 {
1941 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1942 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1943 if (unlikely(Rc(ctx->opcode) != 0))
1944 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1945 }
1946 /* sradi & sradi. */
1947 static inline void gen_sradi(DisasContext *ctx, int n)
1948 {
1949 int sh = SH(ctx->opcode) + (n << 5);
1950 if (sh != 0) {
1951 int l1, l2;
1952 TCGv t0;
1953 l1 = gen_new_label();
1954 l2 = gen_new_label();
1955 t0 = tcg_temp_local_new();
1956 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1957 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1958 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1959 tcg_gen_movi_tl(cpu_ca, 1);
1960 tcg_gen_br(l2);
1961 gen_set_label(l1);
1962 tcg_gen_movi_tl(cpu_ca, 0);
1963 gen_set_label(l2);
1964 tcg_temp_free(t0);
1965 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1966 } else {
1967 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1968 tcg_gen_movi_tl(cpu_ca, 0);
1969 }
1970 if (unlikely(Rc(ctx->opcode) != 0))
1971 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1972 }
1973
1974 static void gen_sradi0(DisasContext *ctx)
1975 {
1976 gen_sradi(ctx, 0);
1977 }
1978
1979 static void gen_sradi1(DisasContext *ctx)
1980 {
1981 gen_sradi(ctx, 1);
1982 }
1983
1984 /* srd & srd. */
1985 static void gen_srd(DisasContext *ctx)
1986 {
1987 TCGv t0, t1;
1988
1989 t0 = tcg_temp_new();
1990 /* AND rS with a mask that is 0 when rB >= 0x40 */
1991 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1992 tcg_gen_sari_tl(t0, t0, 0x3f);
1993 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1994 t1 = tcg_temp_new();
1995 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1996 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1997 tcg_temp_free(t1);
1998 tcg_temp_free(t0);
1999 if (unlikely(Rc(ctx->opcode) != 0))
2000 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2001 }
2002 #endif
2003
2004 /*** Floating-Point arithmetic ***/
2005 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2006 static void gen_f##name(DisasContext *ctx) \
2007 { \
2008 if (unlikely(!ctx->fpu_enabled)) { \
2009 gen_exception(ctx, POWERPC_EXCP_FPU); \
2010 return; \
2011 } \
2012 /* NIP cannot be restored if the memory exception comes from an helper */ \
2013 gen_update_nip(ctx, ctx->nip - 4); \
2014 gen_reset_fpstatus(); \
2015 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2016 cpu_fpr[rA(ctx->opcode)], \
2017 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2018 if (isfloat) { \
2019 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2020 cpu_fpr[rD(ctx->opcode)]); \
2021 } \
2022 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2023 Rc(ctx->opcode) != 0); \
2024 }
2025
2026 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2027 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2028 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2029
2030 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2031 static void gen_f##name(DisasContext *ctx) \
2032 { \
2033 if (unlikely(!ctx->fpu_enabled)) { \
2034 gen_exception(ctx, POWERPC_EXCP_FPU); \
2035 return; \
2036 } \
2037 /* NIP cannot be restored if the memory exception comes from an helper */ \
2038 gen_update_nip(ctx, ctx->nip - 4); \
2039 gen_reset_fpstatus(); \
2040 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2041 cpu_fpr[rA(ctx->opcode)], \
2042 cpu_fpr[rB(ctx->opcode)]); \
2043 if (isfloat) { \
2044 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2045 cpu_fpr[rD(ctx->opcode)]); \
2046 } \
2047 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2048 set_fprf, Rc(ctx->opcode) != 0); \
2049 }
2050 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2051 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2052 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2053
2054 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2055 static void gen_f##name(DisasContext *ctx) \
2056 { \
2057 if (unlikely(!ctx->fpu_enabled)) { \
2058 gen_exception(ctx, POWERPC_EXCP_FPU); \
2059 return; \
2060 } \
2061 /* NIP cannot be restored if the memory exception comes from an helper */ \
2062 gen_update_nip(ctx, ctx->nip - 4); \
2063 gen_reset_fpstatus(); \
2064 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2065 cpu_fpr[rA(ctx->opcode)], \
2066 cpu_fpr[rC(ctx->opcode)]); \
2067 if (isfloat) { \
2068 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2069 cpu_fpr[rD(ctx->opcode)]); \
2070 } \
2071 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2072 set_fprf, Rc(ctx->opcode) != 0); \
2073 }
2074 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2075 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2076 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2077
2078 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2079 static void gen_f##name(DisasContext *ctx) \
2080 { \
2081 if (unlikely(!ctx->fpu_enabled)) { \
2082 gen_exception(ctx, POWERPC_EXCP_FPU); \
2083 return; \
2084 } \
2085 /* NIP cannot be restored if the memory exception comes from an helper */ \
2086 gen_update_nip(ctx, ctx->nip - 4); \
2087 gen_reset_fpstatus(); \
2088 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2089 cpu_fpr[rB(ctx->opcode)]); \
2090 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2091 set_fprf, Rc(ctx->opcode) != 0); \
2092 }
2093
2094 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2095 static void gen_f##name(DisasContext *ctx) \
2096 { \
2097 if (unlikely(!ctx->fpu_enabled)) { \
2098 gen_exception(ctx, POWERPC_EXCP_FPU); \
2099 return; \
2100 } \
2101 /* NIP cannot be restored if the memory exception comes from an helper */ \
2102 gen_update_nip(ctx, ctx->nip - 4); \
2103 gen_reset_fpstatus(); \
2104 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2105 cpu_fpr[rB(ctx->opcode)]); \
2106 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2107 set_fprf, Rc(ctx->opcode) != 0); \
2108 }
2109
2110 /* fadd - fadds */
2111 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2112 /* fdiv - fdivs */
2113 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2114 /* fmul - fmuls */
2115 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2116
2117 /* fre */
2118 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2119
2120 /* fres */
2121 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2122
2123 /* frsqrte */
2124 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2125
2126 /* frsqrtes */
2127 static void gen_frsqrtes(DisasContext *ctx)
2128 {
2129 if (unlikely(!ctx->fpu_enabled)) {
2130 gen_exception(ctx, POWERPC_EXCP_FPU);
2131 return;
2132 }
2133 /* NIP cannot be restored if the memory exception comes from an helper */
2134 gen_update_nip(ctx, ctx->nip - 4);
2135 gen_reset_fpstatus();
2136 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2137 cpu_fpr[rB(ctx->opcode)]);
2138 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2139 cpu_fpr[rD(ctx->opcode)]);
2140 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2141 }
2142
2143 /* fsel */
2144 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2145 /* fsub - fsubs */
2146 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2147 /* Optional: */
2148
2149 /* fsqrt */
2150 static void gen_fsqrt(DisasContext *ctx)
2151 {
2152 if (unlikely(!ctx->fpu_enabled)) {
2153 gen_exception(ctx, POWERPC_EXCP_FPU);
2154 return;
2155 }
2156 /* NIP cannot be restored if the memory exception comes from an helper */
2157 gen_update_nip(ctx, ctx->nip - 4);
2158 gen_reset_fpstatus();
2159 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2160 cpu_fpr[rB(ctx->opcode)]);
2161 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2162 }
2163
2164 static void gen_fsqrts(DisasContext *ctx)
2165 {
2166 if (unlikely(!ctx->fpu_enabled)) {
2167 gen_exception(ctx, POWERPC_EXCP_FPU);
2168 return;
2169 }
2170 /* NIP cannot be restored if the memory exception comes from an helper */
2171 gen_update_nip(ctx, ctx->nip - 4);
2172 gen_reset_fpstatus();
2173 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2174 cpu_fpr[rB(ctx->opcode)]);
2175 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2176 cpu_fpr[rD(ctx->opcode)]);
2177 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2178 }
2179
2180 /*** Floating-Point multiply-and-add ***/
2181 /* fmadd - fmadds */
2182 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2183 /* fmsub - fmsubs */
2184 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2185 /* fnmadd - fnmadds */
2186 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2187 /* fnmsub - fnmsubs */
2188 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2189
2190 /*** Floating-Point round & convert ***/
2191 /* fctiw */
2192 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2193 /* fctiwz */
2194 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2195 /* frsp */
2196 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2197 #if defined(TARGET_PPC64)
2198 /* fcfid */
2199 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2200 /* fctid */
2201 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2202 /* fctidz */
2203 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2204 #endif
2205
2206 /* frin */
2207 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2208 /* friz */
2209 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2210 /* frip */
2211 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2212 /* frim */
2213 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2214
2215 /*** Floating-Point compare ***/
2216
2217 /* fcmpo */
2218 static void gen_fcmpo(DisasContext *ctx)
2219 {
2220 TCGv_i32 crf;
2221 if (unlikely(!ctx->fpu_enabled)) {
2222 gen_exception(ctx, POWERPC_EXCP_FPU);
2223 return;
2224 }
2225 /* NIP cannot be restored if the memory exception comes from an helper */
2226 gen_update_nip(ctx, ctx->nip - 4);
2227 gen_reset_fpstatus();
2228 crf = tcg_const_i32(crfD(ctx->opcode));
2229 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2230 cpu_fpr[rB(ctx->opcode)], crf);
2231 tcg_temp_free_i32(crf);
2232 gen_helper_float_check_status(cpu_env);
2233 }
2234
2235 /* fcmpu */
2236 static void gen_fcmpu(DisasContext *ctx)
2237 {
2238 TCGv_i32 crf;
2239 if (unlikely(!ctx->fpu_enabled)) {
2240 gen_exception(ctx, POWERPC_EXCP_FPU);
2241 return;
2242 }
2243 /* NIP cannot be restored if the memory exception comes from an helper */
2244 gen_update_nip(ctx, ctx->nip - 4);
2245 gen_reset_fpstatus();
2246 crf = tcg_const_i32(crfD(ctx->opcode));
2247 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2248 cpu_fpr[rB(ctx->opcode)], crf);
2249 tcg_temp_free_i32(crf);
2250 gen_helper_float_check_status(cpu_env);
2251 }
2252
2253 /*** Floating-point move ***/
2254 /* fabs */
2255 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2256 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2257
2258 /* fmr - fmr. */
2259 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2260 static void gen_fmr(DisasContext *ctx)
2261 {
2262 if (unlikely(!ctx->fpu_enabled)) {
2263 gen_exception(ctx, POWERPC_EXCP_FPU);
2264 return;
2265 }
2266 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2267 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2268 }
2269
2270 /* fnabs */
2271 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2272 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2273 /* fneg */
2274 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2275 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2276
2277 /*** Floating-Point status & ctrl register ***/
2278
2279 /* mcrfs */
2280 static void gen_mcrfs(DisasContext *ctx)
2281 {
2282 TCGv tmp = tcg_temp_new();
2283 int bfa;
2284
2285 if (unlikely(!ctx->fpu_enabled)) {
2286 gen_exception(ctx, POWERPC_EXCP_FPU);
2287 return;
2288 }
2289 bfa = 4 * (7 - crfS(ctx->opcode));
2290 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2291 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2292 tcg_temp_free(tmp);
2293 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2294 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2295 }
2296
2297 /* mffs */
2298 static void gen_mffs(DisasContext *ctx)
2299 {
2300 if (unlikely(!ctx->fpu_enabled)) {
2301 gen_exception(ctx, POWERPC_EXCP_FPU);
2302 return;
2303 }
2304 gen_reset_fpstatus();
2305 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2306 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2307 }
2308
2309 /* mtfsb0 */
2310 static void gen_mtfsb0(DisasContext *ctx)
2311 {
2312 uint8_t crb;
2313
2314 if (unlikely(!ctx->fpu_enabled)) {
2315 gen_exception(ctx, POWERPC_EXCP_FPU);
2316 return;
2317 }
2318 crb = 31 - crbD(ctx->opcode);
2319 gen_reset_fpstatus();
2320 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2321 TCGv_i32 t0;
2322 /* NIP cannot be restored if the memory exception comes from an helper */
2323 gen_update_nip(ctx, ctx->nip - 4);
2324 t0 = tcg_const_i32(crb);
2325 gen_helper_fpscr_clrbit(cpu_env, t0);
2326 tcg_temp_free_i32(t0);
2327 }
2328 if (unlikely(Rc(ctx->opcode) != 0)) {
2329 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2330 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2331 }
2332 }
2333
2334 /* mtfsb1 */
2335 static void gen_mtfsb1(DisasContext *ctx)
2336 {
2337 uint8_t crb;
2338
2339 if (unlikely(!ctx->fpu_enabled)) {
2340 gen_exception(ctx, POWERPC_EXCP_FPU);
2341 return;
2342 }
2343 crb = 31 - crbD(ctx->opcode);
2344 gen_reset_fpstatus();
2345 /* XXX: we pretend we can only do IEEE floating-point computations */
2346 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2347 TCGv_i32 t0;
2348 /* NIP cannot be restored if the memory exception comes from an helper */
2349 gen_update_nip(ctx, ctx->nip - 4);
2350 t0 = tcg_const_i32(crb);
2351 gen_helper_fpscr_setbit(cpu_env, t0);
2352 tcg_temp_free_i32(t0);
2353 }
2354 if (unlikely(Rc(ctx->opcode) != 0)) {
2355 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2356 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2357 }
2358 /* We can raise a differed exception */
2359 gen_helper_float_check_status(cpu_env);
2360 }
2361
2362 /* mtfsf */
2363 static void gen_mtfsf(DisasContext *ctx)
2364 {
2365 TCGv_i32 t0;
2366 int L = ctx->opcode & 0x02000000;
2367
2368 if (unlikely(!ctx->fpu_enabled)) {
2369 gen_exception(ctx, POWERPC_EXCP_FPU);
2370 return;
2371 }
2372 /* NIP cannot be restored if the memory exception comes from an helper */
2373 gen_update_nip(ctx, ctx->nip - 4);
2374 gen_reset_fpstatus();
2375 if (L)
2376 t0 = tcg_const_i32(0xff);
2377 else
2378 t0 = tcg_const_i32(FM(ctx->opcode));
2379 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2380 tcg_temp_free_i32(t0);
2381 if (unlikely(Rc(ctx->opcode) != 0)) {
2382 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2383 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2384 }
2385 /* We can raise a differed exception */
2386 gen_helper_float_check_status(cpu_env);
2387 }
2388
2389 /* mtfsfi */
2390 static void gen_mtfsfi(DisasContext *ctx)
2391 {
2392 int bf, sh;
2393 TCGv_i64 t0;
2394 TCGv_i32 t1;
2395
2396 if (unlikely(!ctx->fpu_enabled)) {
2397 gen_exception(ctx, POWERPC_EXCP_FPU);
2398 return;
2399 }
2400 bf = crbD(ctx->opcode) >> 2;
2401 sh = 7 - bf;
2402 /* NIP cannot be restored if the memory exception comes from an helper */
2403 gen_update_nip(ctx, ctx->nip - 4);
2404 gen_reset_fpstatus();
2405 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2406 t1 = tcg_const_i32(1 << sh);
2407 gen_helper_store_fpscr(cpu_env, t0, t1);
2408 tcg_temp_free_i64(t0);
2409 tcg_temp_free_i32(t1);
2410 if (unlikely(Rc(ctx->opcode) != 0)) {
2411 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2412 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2413 }
2414 /* We can raise a differed exception */
2415 gen_helper_float_check_status(cpu_env);
2416 }
2417
2418 /*** Addressing modes ***/
2419 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2420 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2421 target_long maskl)
2422 {
2423 target_long simm = SIMM(ctx->opcode);
2424
2425 simm &= ~maskl;
2426 if (rA(ctx->opcode) == 0) {
2427 #if defined(TARGET_PPC64)
2428 if (!ctx->sf_mode) {
2429 tcg_gen_movi_tl(EA, (uint32_t)simm);
2430 } else
2431 #endif
2432 tcg_gen_movi_tl(EA, simm);
2433 } else if (likely(simm != 0)) {
2434 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2435 #if defined(TARGET_PPC64)
2436 if (!ctx->sf_mode) {
2437 tcg_gen_ext32u_tl(EA, EA);
2438 }
2439 #endif
2440 } else {
2441 #if defined(TARGET_PPC64)
2442 if (!ctx->sf_mode) {
2443 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2444 } else
2445 #endif
2446 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2447 }
2448 }
2449
2450 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2451 {
2452 if (rA(ctx->opcode) == 0) {
2453 #if defined(TARGET_PPC64)
2454 if (!ctx->sf_mode) {
2455 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2456 } else
2457 #endif
2458 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2459 } else {
2460 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2461 #if defined(TARGET_PPC64)
2462 if (!ctx->sf_mode) {
2463 tcg_gen_ext32u_tl(EA, EA);
2464 }
2465 #endif
2466 }
2467 }
2468
2469 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2470 {
2471 if (rA(ctx->opcode) == 0) {
2472 tcg_gen_movi_tl(EA, 0);
2473 } else {
2474 #if defined(TARGET_PPC64)
2475 if (!ctx->sf_mode) {
2476 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2477 } else
2478 #endif
2479 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2480 }
2481 }
2482
2483 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2484 target_long val)
2485 {
2486 tcg_gen_addi_tl(ret, arg1, val);
2487 #if defined(TARGET_PPC64)
2488 if (!ctx->sf_mode) {
2489 tcg_gen_ext32u_tl(ret, ret);
2490 }
2491 #endif
2492 }
2493
2494 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2495 {
2496 int l1 = gen_new_label();
2497 TCGv t0 = tcg_temp_new();
2498 TCGv_i32 t1, t2;
2499 /* NIP cannot be restored if the memory exception comes from an helper */
2500 gen_update_nip(ctx, ctx->nip - 4);
2501 tcg_gen_andi_tl(t0, EA, mask);
2502 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2503 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2504 t2 = tcg_const_i32(0);
2505 gen_helper_raise_exception_err(cpu_env, t1, t2);
2506 tcg_temp_free_i32(t1);
2507 tcg_temp_free_i32(t2);
2508 gen_set_label(l1);
2509 tcg_temp_free(t0);
2510 }
2511
2512 /*** Integer load ***/
2513 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2514 {
2515 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2516 }
2517
2518 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2519 {
2520 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2521 }
2522
2523 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2524 {
2525 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2526 if (unlikely(ctx->le_mode)) {
2527 tcg_gen_bswap16_tl(arg1, arg1);
2528 }
2529 }
2530
2531 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2532 {
2533 if (unlikely(ctx->le_mode)) {
2534 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2535 tcg_gen_bswap16_tl(arg1, arg1);
2536 tcg_gen_ext16s_tl(arg1, arg1);
2537 } else {
2538 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2539 }
2540 }
2541
2542 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2543 {
2544 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2545 if (unlikely(ctx->le_mode)) {
2546 tcg_gen_bswap32_tl(arg1, arg1);
2547 }
2548 }
2549
2550 #if defined(TARGET_PPC64)
2551 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2552 {
2553 if (unlikely(ctx->le_mode)) {
2554 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2555 tcg_gen_bswap32_tl(arg1, arg1);
2556 tcg_gen_ext32s_tl(arg1, arg1);
2557 } else
2558 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2559 }
2560 #endif
2561
2562 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2563 {
2564 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2565 if (unlikely(ctx->le_mode)) {
2566 tcg_gen_bswap64_i64(arg1, arg1);
2567 }
2568 }
2569
2570 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2571 {
2572 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2573 }
2574
2575 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2576 {
2577 if (unlikely(ctx->le_mode)) {
2578 TCGv t0 = tcg_temp_new();
2579 tcg_gen_ext16u_tl(t0, arg1);
2580 tcg_gen_bswap16_tl(t0, t0);
2581 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2582 tcg_temp_free(t0);
2583 } else {
2584 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2585 }
2586 }
2587
2588 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2589 {
2590 if (unlikely(ctx->le_mode)) {
2591 TCGv t0 = tcg_temp_new();
2592 tcg_gen_ext32u_tl(t0, arg1);
2593 tcg_gen_bswap32_tl(t0, t0);
2594 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2595 tcg_temp_free(t0);
2596 } else {
2597 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2598 }
2599 }
2600
2601 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2602 {
2603 if (unlikely(ctx->le_mode)) {
2604 TCGv_i64 t0 = tcg_temp_new_i64();
2605 tcg_gen_bswap64_i64(t0, arg1);
2606 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2607 tcg_temp_free_i64(t0);
2608 } else
2609 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2610 }
2611
2612 #define GEN_LD(name, ldop, opc, type) \
2613 static void glue(gen_, name)(DisasContext *ctx) \
2614 { \
2615 TCGv EA; \
2616 gen_set_access_type(ctx, ACCESS_INT); \
2617 EA = tcg_temp_new(); \
2618 gen_addr_imm_index(ctx, EA, 0); \
2619 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2620 tcg_temp_free(EA); \
2621 }
2622
2623 #define GEN_LDU(name, ldop, opc, type) \
2624 static void glue(gen_, name##u)(DisasContext *ctx) \
2625 { \
2626 TCGv EA; \
2627 if (unlikely(rA(ctx->opcode) == 0 || \
2628 rA(ctx->opcode) == rD(ctx->opcode))) { \
2629 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2630 return; \
2631 } \
2632 gen_set_access_type(ctx, ACCESS_INT); \
2633 EA = tcg_temp_new(); \
2634 if (type == PPC_64B) \
2635 gen_addr_imm_index(ctx, EA, 0x03); \
2636 else \
2637 gen_addr_imm_index(ctx, EA, 0); \
2638 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2639 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2640 tcg_temp_free(EA); \
2641 }
2642
2643 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2644 static void glue(gen_, name##ux)(DisasContext *ctx) \
2645 { \
2646 TCGv EA; \
2647 if (unlikely(rA(ctx->opcode) == 0 || \
2648 rA(ctx->opcode) == rD(ctx->opcode))) { \
2649 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2650 return; \
2651 } \
2652 gen_set_access_type(ctx, ACCESS_INT); \
2653 EA = tcg_temp_new(); \
2654 gen_addr_reg_index(ctx, EA); \
2655 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2656 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2657 tcg_temp_free(EA); \
2658 }
2659
2660 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2661 static void glue(gen_, name##x)(DisasContext *ctx) \
2662 { \
2663 TCGv EA; \
2664 gen_set_access_type(ctx, ACCESS_INT); \
2665 EA = tcg_temp_new(); \
2666 gen_addr_reg_index(ctx, EA); \
2667 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2668 tcg_temp_free(EA); \
2669 }
2670 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2671 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2672
2673 #define GEN_LDS(name, ldop, op, type) \
2674 GEN_LD(name, ldop, op | 0x20, type); \
2675 GEN_LDU(name, ldop, op | 0x21, type); \
2676 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2677 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2678
2679 /* lbz lbzu lbzux lbzx */
2680 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2681 /* lha lhau lhaux lhax */
2682 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2683 /* lhz lhzu lhzux lhzx */
2684 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2685 /* lwz lwzu lwzux lwzx */
2686 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2687 #if defined(TARGET_PPC64)
2688 /* lwaux */
2689 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2690 /* lwax */
2691 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2692 /* ldux */
2693 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2694 /* ldx */
2695 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2696
2697 static void gen_ld(DisasContext *ctx)
2698 {
2699 TCGv EA;
2700 if (Rc(ctx->opcode)) {
2701 if (unlikely(rA(ctx->opcode) == 0 ||
2702 rA(ctx->opcode) == rD(ctx->opcode))) {
2703 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2704 return;
2705 }
2706 }
2707 gen_set_access_type(ctx, ACCESS_INT);
2708 EA = tcg_temp_new();
2709 gen_addr_imm_index(ctx, EA, 0x03);
2710 if (ctx->opcode & 0x02) {
2711 /* lwa (lwau is undefined) */
2712 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2713 } else {
2714 /* ld - ldu */
2715 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2716 }
2717 if (Rc(ctx->opcode))
2718 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2719 tcg_temp_free(EA);
2720 }
2721
2722 /* lq */
2723 static void gen_lq(DisasContext *ctx)
2724 {
2725 #if defined(CONFIG_USER_ONLY)
2726 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2727 #else
2728 int ra, rd;
2729 TCGv EA;
2730
2731 /* Restore CPU state */
2732 if (unlikely(ctx->mem_idx == 0)) {
2733 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2734 return;
2735 }
2736 ra = rA(ctx->opcode);
2737 rd = rD(ctx->opcode);
2738 if (unlikely((rd & 1) || rd == ra)) {
2739 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2740 return;
2741 }
2742 if (unlikely(ctx->le_mode)) {
2743 /* Little-endian mode is not handled */
2744 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2745 return;
2746 }
2747 gen_set_access_type(ctx, ACCESS_INT);
2748 EA = tcg_temp_new();
2749 gen_addr_imm_index(ctx, EA, 0x0F);
2750 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2751 gen_addr_add(ctx, EA, EA, 8);
2752 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2753 tcg_temp_free(EA);
2754 #endif
2755 }
2756 #endif
2757
2758 /*** Integer store ***/
2759 #define GEN_ST(name, stop, opc, type) \
2760 static void glue(gen_, name)(DisasContext *ctx) \
2761 { \
2762 TCGv EA; \
2763 gen_set_access_type(ctx, ACCESS_INT); \
2764 EA = tcg_temp_new(); \
2765 gen_addr_imm_index(ctx, EA, 0); \
2766 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2767 tcg_temp_free(EA); \
2768 }
2769
2770 #define GEN_STU(name, stop, opc, type) \
2771 static void glue(gen_, stop##u)(DisasContext *ctx) \
2772 { \
2773 TCGv EA; \
2774 if (unlikely(rA(ctx->opcode) == 0)) { \
2775 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2776 return; \
2777 } \
2778 gen_set_access_type(ctx, ACCESS_INT); \
2779 EA = tcg_temp_new(); \
2780 if (type == PPC_64B) \
2781 gen_addr_imm_index(ctx, EA, 0x03); \
2782 else \
2783 gen_addr_imm_index(ctx, EA, 0); \
2784 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2785 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2786 tcg_temp_free(EA); \
2787 }
2788
2789 #define GEN_STUX(name, stop, opc2, opc3, type) \
2790 static void glue(gen_, name##ux)(DisasContext *ctx) \
2791 { \
2792 TCGv EA; \
2793 if (unlikely(rA(ctx->opcode) == 0)) { \
2794 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2795 return; \
2796 } \
2797 gen_set_access_type(ctx, ACCESS_INT); \
2798 EA = tcg_temp_new(); \
2799 gen_addr_reg_index(ctx, EA); \
2800 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2801 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2802 tcg_temp_free(EA); \
2803 }
2804
2805 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2806 static void glue(gen_, name##x)(DisasContext *ctx) \
2807 { \
2808 TCGv EA; \
2809 gen_set_access_type(ctx, ACCESS_INT); \
2810 EA = tcg_temp_new(); \
2811 gen_addr_reg_index(ctx, EA); \
2812 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2813 tcg_temp_free(EA); \
2814 }
2815 #define GEN_STX(name, stop, opc2, opc3, type) \
2816 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2817
2818 #define GEN_STS(name, stop, op, type) \
2819 GEN_ST(name, stop, op | 0x20, type); \
2820 GEN_STU(name, stop, op | 0x21, type); \
2821 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2822 GEN_STX(name, stop, 0x17, op | 0x00, type)
2823
2824 /* stb stbu stbux stbx */
2825 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2826 /* sth sthu sthux sthx */
2827 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2828 /* stw stwu stwux stwx */
2829 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2830 #if defined(TARGET_PPC64)
2831 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2832 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2833
2834 static void gen_std(DisasContext *ctx)
2835 {
2836 int rs;
2837 TCGv EA;
2838
2839 rs = rS(ctx->opcode);
2840 if ((ctx->opcode & 0x3) == 0x2) {
2841 #if defined(CONFIG_USER_ONLY)
2842 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2843 #else
2844 /* stq */
2845 if (unlikely(ctx->mem_idx == 0)) {
2846 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2847 return;
2848 }
2849 if (unlikely(rs & 1)) {
2850 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2851 return;
2852 }
2853 if (unlikely(ctx->le_mode)) {
2854 /* Little-endian mode is not handled */
2855 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2856 return;
2857 }
2858 gen_set_access_type(ctx, ACCESS_INT);
2859 EA = tcg_temp_new();
2860 gen_addr_imm_index(ctx, EA, 0x03);
2861 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2862 gen_addr_add(ctx, EA, EA, 8);
2863 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2864 tcg_temp_free(EA);
2865 #endif
2866 } else {
2867 /* std / stdu */
2868 if (Rc(ctx->opcode)) {
2869 if (unlikely(rA(ctx->opcode) == 0)) {
2870 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2871 return;
2872 }
2873 }
2874 gen_set_access_type(ctx, ACCESS_INT);
2875 EA = tcg_temp_new();
2876 gen_addr_imm_index(ctx, EA, 0x03);
2877 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2878 if (Rc(ctx->opcode))
2879 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2880 tcg_temp_free(EA);
2881 }
2882 }
2883 #endif
2884 /*** Integer load and store with byte reverse ***/
2885 /* lhbrx */
2886 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2887 {
2888 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2889 if (likely(!ctx->le_mode)) {
2890 tcg_gen_bswap16_tl(arg1, arg1);
2891 }
2892 }
2893 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2894
2895 /* lwbrx */
2896 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2897 {
2898 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2899 if (likely(!ctx->le_mode)) {
2900 tcg_gen_bswap32_tl(arg1, arg1);
2901 }
2902 }
2903 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2904
2905 #if defined(TARGET_PPC64)
2906 /* ldbrx */
2907 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2908 {
2909 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2910 if (likely(!ctx->le_mode)) {
2911 tcg_gen_bswap64_tl(arg1, arg1);
2912 }
2913 }
2914 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2915 #endif /* TARGET_PPC64 */
2916
2917 /* sthbrx */
2918 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2919 {
2920 if (likely(!ctx->le_mode)) {
2921 TCGv t0 = tcg_temp_new();
2922 tcg_gen_ext16u_tl(t0, arg1);
2923 tcg_gen_bswap16_tl(t0, t0);
2924 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2925 tcg_temp_free(t0);
2926 } else {
2927 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2928 }
2929 }
2930 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2931
2932 /* stwbrx */
2933 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2934 {
2935 if (likely(!ctx->le_mode)) {
2936 TCGv t0 = tcg_temp_new();
2937 tcg_gen_ext32u_tl(t0, arg1);
2938 tcg_gen_bswap32_tl(t0, t0);
2939 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2940 tcg_temp_free(t0);
2941 } else {
2942 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2943 }
2944 }
2945 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2946
2947 #if defined(TARGET_PPC64)
2948 /* stdbrx */
2949 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2950 {
2951 if (likely(!ctx->le_mode)) {
2952 TCGv t0 = tcg_temp_new();
2953 tcg_gen_bswap64_tl(t0, arg1);
2954 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2955 tcg_temp_free(t0);
2956 } else {
2957 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2958 }
2959 }
2960 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2961 #endif /* TARGET_PPC64 */
2962
2963 /*** Integer load and store multiple ***/
2964
2965 /* lmw */
2966 static void gen_lmw(DisasContext *ctx)
2967 {
2968 TCGv t0;
2969 TCGv_i32 t1;
2970 gen_set_access_type(ctx, ACCESS_INT);
2971 /* NIP cannot be restored if the memory exception comes from an helper */
2972 gen_update_nip(ctx, ctx->nip - 4);
2973 t0 = tcg_temp_new();
2974 t1 = tcg_const_i32(rD(ctx->opcode));
2975 gen_addr_imm_index(ctx, t0, 0);
2976 gen_helper_lmw(cpu_env, t0, t1);
2977 tcg_temp_free(t0);
2978 tcg_temp_free_i32(t1);
2979 }
2980
2981 /* stmw */
2982 static void gen_stmw(DisasContext *ctx)
2983 {
2984 TCGv t0;
2985 TCGv_i32 t1;
2986 gen_set_access_type(ctx, ACCESS_INT);
2987 /* NIP cannot be restored if the memory exception comes from an helper */
2988 gen_update_nip(ctx, ctx->nip - 4);
2989 t0 = tcg_temp_new();
2990 t1 = tcg_const_i32(rS(ctx->opcode));
2991 gen_addr_imm_index(ctx, t0, 0);
2992 gen_helper_stmw(cpu_env, t0, t1);
2993 tcg_temp_free(t0);
2994 tcg_temp_free_i32(t1);
2995 }
2996
2997 /*** Integer load and store strings ***/
2998
2999 /* lswi */
3000 /* PowerPC32 specification says we must generate an exception if
3001 * rA is in the range of registers to be loaded.
3002 * In an other hand, IBM says this is valid, but rA won't be loaded.
3003 * For now, I'll follow the spec...
3004 */
3005 static void gen_lswi(DisasContext *ctx)
3006 {
3007 TCGv t0;
3008 TCGv_i32 t1, t2;
3009 int nb = NB(ctx->opcode);
3010 int start = rD(ctx->opcode);
3011 int ra = rA(ctx->opcode);
3012 int nr;
3013
3014 if (nb == 0)
3015 nb = 32;
3016 nr = nb / 4;
3017 if (unlikely(((start + nr) > 32 &&
3018 start <= ra && (start + nr - 32) > ra) ||
3019 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3020 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3021 return;
3022 }
3023 gen_set_access_type(ctx, ACCESS_INT);
3024 /* NIP cannot be restored if the memory exception comes from an helper */
3025 gen_update_nip(ctx, ctx->nip - 4);
3026 t0 = tcg_temp_new();
3027 gen_addr_register(ctx, t0);
3028 t1 = tcg_const_i32(nb);
3029 t2 = tcg_const_i32(start);
3030 gen_helper_lsw(cpu_env, t0, t1, t2);
3031 tcg_temp_free(t0);
3032 tcg_temp_free_i32(t1);
3033 tcg_temp_free_i32(t2);
3034 }
3035
3036 /* lswx */
3037 static void gen_lswx(DisasContext *ctx)
3038 {
3039 TCGv t0;
3040 TCGv_i32 t1, t2, t3;
3041 gen_set_access_type(ctx, ACCESS_INT);
3042 /* NIP cannot be restored if the memory exception comes from an helper */
3043 gen_update_nip(ctx, ctx->nip - 4);
3044 t0 = tcg_temp_new();
3045 gen_addr_reg_index(ctx, t0);
3046 t1 = tcg_const_i32(rD(ctx->opcode));
3047 t2 = tcg_const_i32(rA(ctx->opcode));
3048 t3 = tcg_const_i32(rB(ctx->opcode));
3049 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3050 tcg_temp_free(t0);
3051 tcg_temp_free_i32(t1);
3052 tcg_temp_free_i32(t2);
3053 tcg_temp_free_i32(t3);
3054 }
3055
3056 /* stswi */
3057 static void gen_stswi(DisasContext *ctx)
3058 {
3059 TCGv t0;
3060 TCGv_i32 t1, t2;
3061 int nb = NB(ctx->opcode);
3062 gen_set_access_type(ctx, ACCESS_INT);
3063 /* NIP cannot be restored if the memory exception comes from an helper */
3064 gen_update_nip(ctx, ctx->nip - 4);
3065 t0 = tcg_temp_new();
3066 gen_addr_register(ctx, t0);
3067 if (nb == 0)
3068 nb = 32;
3069 t1 = tcg_const_i32(nb);
3070 t2 = tcg_const_i32(rS(ctx->opcode));
3071 gen_helper_stsw(cpu_env, t0, t1, t2);
3072 tcg_temp_free(t0);
3073 tcg_temp_free_i32(t1);
3074 tcg_temp_free_i32(t2);
3075 }
3076
3077 /* stswx */
3078 static void gen_stswx(DisasContext *ctx)
3079 {
3080 TCGv t0;
3081 TCGv_i32 t1, t2;
3082 gen_set_access_type(ctx, ACCESS_INT);
3083 /* NIP cannot be restored if the memory exception comes from an helper */
3084 gen_update_nip(ctx, ctx->nip - 4);
3085 t0 = tcg_temp_new();
3086 gen_addr_reg_index(ctx, t0);
3087 t1 = tcg_temp_new_i32();
3088 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3089 tcg_gen_andi_i32(t1, t1, 0x7F);
3090 t2 = tcg_const_i32(rS(ctx->opcode));
3091 gen_helper_stsw(cpu_env, t0, t1, t2);
3092 tcg_temp_free(t0);
3093 tcg_temp_free_i32(t1);
3094 tcg_temp_free_i32(t2);
3095 }
3096
3097 /*** Memory synchronisation ***/
3098 /* eieio */
3099 static void gen_eieio(DisasContext *ctx)
3100 {
3101 }
3102
3103 /* isync */
3104 static void gen_isync(DisasContext *ctx)
3105 {
3106 gen_stop_exception(ctx);
3107 }
3108
3109 /* lwarx */
3110 static void gen_lwarx(DisasContext *ctx)
3111 {
3112 TCGv t0;
3113 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3114 gen_set_access_type(ctx, ACCESS_RES);
3115 t0 = tcg_temp_local_new();
3116 gen_addr_reg_index(ctx, t0);
3117 gen_check_align(ctx, t0, 0x03);
3118 gen_qemu_ld32u(ctx, gpr, t0);
3119 tcg_gen_mov_tl(cpu_reserve, t0);
3120 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3121 tcg_temp_free(t0);
3122 }
3123
3124 #if defined(CONFIG_USER_ONLY)
3125 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3126 int reg, int size)
3127 {
3128 TCGv t0 = tcg_temp_new();
3129 uint32_t save_exception = ctx->exception;
3130
3131 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3132 tcg_gen_movi_tl(t0, (size << 5) | reg);
3133 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3134 tcg_temp_free(t0);
3135 gen_update_nip(ctx, ctx->nip-4);
3136 ctx->exception = POWERPC_EXCP_BRANCH;
3137 gen_exception(ctx, POWERPC_EXCP_STCX);
3138 ctx->exception = save_exception;
3139 }
3140 #endif
3141
3142 /* stwcx. */
3143 static void gen_stwcx_(DisasContext *ctx)
3144 {
3145 TCGv t0;
3146 gen_set_access_type(ctx, ACCESS_RES);
3147 t0 = tcg_temp_local_new();
3148 gen_addr_reg_index(ctx, t0);
3149 gen_check_align(ctx, t0, 0x03);
3150 #if defined(CONFIG_USER_ONLY)
3151 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3152 #else
3153 {
3154 int l1;
3155
3156 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3157 l1 = gen_new_label();
3158 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3159 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3160 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3161 gen_set_label(l1);
3162 tcg_gen_movi_tl(cpu_reserve, -1);
3163 }
3164 #endif
3165 tcg_temp_free(t0);
3166 }
3167
3168 #if defined(TARGET_PPC64)
3169 /* ldarx */
3170 static void gen_ldarx(DisasContext *ctx)
3171 {
3172 TCGv t0;
3173 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3174 gen_set_access_type(ctx, ACCESS_RES);
3175 t0 = tcg_temp_local_new();
3176 gen_addr_reg_index(ctx, t0);
3177 gen_check_align(ctx, t0, 0x07);
3178 gen_qemu_ld64(ctx, gpr, t0);
3179 tcg_gen_mov_tl(cpu_reserve, t0);
3180 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3181 tcg_temp_free(t0);
3182 }
3183
3184 /* stdcx. */
3185 static void gen_stdcx_(DisasContext *ctx)
3186 {
3187 TCGv t0;
3188 gen_set_access_type(ctx, ACCESS_RES);
3189 t0 = tcg_temp_local_new();
3190 gen_addr_reg_index(ctx, t0);
3191 gen_check_align(ctx, t0, 0x07);
3192 #if defined(CONFIG_USER_ONLY)
3193 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3194 #else
3195 {
3196 int l1;
3197 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3198 l1 = gen_new_label();
3199 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3200 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3201 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3202 gen_set_label(l1);
3203 tcg_gen_movi_tl(cpu_reserve, -1);
3204 }
3205 #endif
3206 tcg_temp_free(t0);
3207 }
3208 #endif /* defined(TARGET_PPC64) */
3209
3210 /* sync */
3211 static void gen_sync(DisasContext *ctx)
3212 {
3213 }
3214
3215 /* wait */
3216 static void gen_wait(DisasContext *ctx)
3217 {
3218 TCGv_i32 t0 = tcg_temp_new_i32();
3219 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
3220 tcg_temp_free_i32(t0);
3221 /* Stop translation, as the CPU is supposed to sleep from now */
3222 gen_exception_err(ctx, EXCP_HLT, 1);
3223 }
3224
3225 /*** Floating-point load ***/
3226 #define GEN_LDF(name, ldop, opc, type) \
3227 static void glue(gen_, name)(DisasContext *ctx) \
3228 { \
3229 TCGv EA; \
3230 if (unlikely(!ctx->fpu_enabled)) { \
3231 gen_exception(ctx, POWERPC_EXCP_FPU); \
3232 return; \
3233 } \
3234 gen_set_access_type(ctx, ACCESS_FLOAT); \
3235 EA = tcg_temp_new(); \
3236 gen_addr_imm_index(ctx, EA, 0); \
3237 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3238 tcg_temp_free(EA); \
3239 }
3240
3241 #define GEN_LDUF(name, ldop, opc, type) \
3242 static void glue(gen_, name##u)(DisasContext *ctx) \
3243 { \
3244 TCGv EA; \
3245 if (unlikely(!ctx->fpu_enabled)) { \
3246 gen_exception(ctx, POWERPC_EXCP_FPU); \
3247 return; \
3248 } \
3249 if (unlikely(rA(ctx->opcode) == 0)) { \
3250 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3251 return; \
3252 } \
3253 gen_set_access_type(ctx, ACCESS_FLOAT); \
3254 EA = tcg_temp_new(); \
3255 gen_addr_imm_index(ctx, EA, 0); \
3256 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3257 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3258 tcg_temp_free(EA); \
3259 }
3260
3261 #define GEN_LDUXF(name, ldop, opc, type) \
3262 static void glue(gen_, name##ux)(DisasContext *ctx) \
3263 { \
3264 TCGv EA; \
3265 if (unlikely(!ctx->fpu_enabled)) { \
3266 gen_exception(ctx, POWERPC_EXCP_FPU); \
3267 return; \
3268 } \
3269 if (unlikely(rA(ctx->opcode) == 0)) { \
3270 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3271 return; \
3272 } \
3273 gen_set_access_type(ctx, ACCESS_FLOAT); \
3274 EA = tcg_temp_new(); \
3275 gen_addr_reg_index(ctx, EA); \
3276 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3277 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3278 tcg_temp_free(EA); \
3279 }
3280
3281 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3282 static void glue(gen_, name##x)(DisasContext *ctx) \
3283 { \
3284 TCGv EA; \
3285 if (unlikely(!ctx->fpu_enabled)) { \
3286 gen_exception(ctx, POWERPC_EXCP_FPU); \
3287 return; \
3288 } \
3289 gen_set_access_type(ctx, ACCESS_FLOAT); \
3290 EA = tcg_temp_new(); \
3291 gen_addr_reg_index(ctx, EA); \
3292 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3293 tcg_temp_free(EA); \
3294 }
3295
3296 #define GEN_LDFS(name, ldop, op, type) \
3297 GEN_LDF(name, ldop, op | 0x20, type); \
3298 GEN_LDUF(name, ldop, op | 0x21, type); \
3299 GEN_LDUXF(name, ldop, op | 0x01, type); \
3300 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3301
3302 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3303 {
3304 TCGv t0 = tcg_temp_new();
3305 TCGv_i32 t1 = tcg_temp_new_i32();
3306 gen_qemu_ld32u(ctx, t0, arg2);
3307 tcg_gen_trunc_tl_i32(t1, t0);
3308 tcg_temp_free(t0);
3309 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3310 tcg_temp_free_i32(t1);
3311 }
3312
3313 /* lfd lfdu lfdux lfdx */
3314 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3315 /* lfs lfsu lfsux lfsx */
3316 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3317
3318 /*** Floating-point store ***/
3319 #define GEN_STF(name, stop, opc, type) \
3320 static void glue(gen_, name)(DisasContext *ctx) \
3321 { \
3322 TCGv EA; \
3323 if (unlikely(!ctx->fpu_enabled)) { \
3324 gen_exception(ctx, POWERPC_EXCP_FPU); \
3325 return; \
3326 } \
3327 gen_set_access_type(ctx, ACCESS_FLOAT); \
3328 EA = tcg_temp_new(); \
3329 gen_addr_imm_index(ctx, EA, 0); \
3330 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3331 tcg_temp_free(EA); \
3332 }
3333
3334 #define GEN_STUF(name, stop, opc, type) \
3335 static void glue(gen_, name##u)(DisasContext *ctx) \
3336 { \
3337 TCGv EA; \
3338 if (unlikely(!ctx->fpu_enabled)) { \
3339 gen_exception(ctx, POWERPC_EXCP_FPU); \
3340 return; \
3341 } \
3342 if (unlikely(rA(ctx->opcode) == 0)) { \
3343 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3344 return; \
3345 } \
3346 gen_set_access_type(ctx, ACCESS_FLOAT); \
3347 EA = tcg_temp_new(); \
3348 gen_addr_imm_index(ctx, EA, 0); \
3349 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3350 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3351 tcg_temp_free(EA); \
3352 }
3353
3354 #define GEN_STUXF(name, stop, opc, type) \
3355 static void glue(gen_, name##ux)(DisasContext *ctx) \
3356 { \
3357 TCGv EA; \
3358 if (unlikely(!ctx->fpu_enabled)) { \
3359 gen_exception(ctx, POWERPC_EXCP_FPU); \
3360 return; \
3361 } \
3362 if (unlikely(rA(ctx->opcode) == 0)) { \
3363 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3364 return; \
3365 } \
3366 gen_set_access_type(ctx, ACCESS_FLOAT); \
3367 EA = tcg_temp_new(); \
3368 gen_addr_reg_index(ctx, EA); \
3369 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3370 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3371 tcg_temp_free(EA); \
3372 }
3373
3374 #define GEN_STXF(name, stop, opc2, opc3, type) \
3375 static void glue(gen_, name##x)(DisasContext *ctx) \
3376 { \
3377 TCGv EA; \
3378 if (unlikely(!ctx->fpu_enabled)) { \
3379 gen_exception(ctx, POWERPC_EXCP_FPU); \
3380 return; \
3381 } \
3382 gen_set_access_type(ctx, ACCESS_FLOAT); \
3383 EA = tcg_temp_new(); \
3384 gen_addr_reg_index(ctx, EA); \
3385 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3386 tcg_temp_free(EA); \
3387 }
3388
3389 #define GEN_STFS(name, stop, op, type) \
3390 GEN_STF(name, stop, op | 0x20, type); \
3391 GEN_STUF(name, stop, op | 0x21, type); \
3392 GEN_STUXF(name, stop, op | 0x01, type); \
3393 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3394
3395 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3396 {
3397 TCGv_i32 t0 = tcg_temp_new_i32();
3398 TCGv t1 = tcg_temp_new();
3399 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3400 tcg_gen_extu_i32_tl(t1, t0);
3401 tcg_temp_free_i32(t0);
3402 gen_qemu_st32(ctx, t1, arg2);
3403 tcg_temp_free(t1);
3404 }
3405
3406 /* stfd stfdu stfdux stfdx */
3407 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3408 /* stfs stfsu stfsux stfsx */
3409 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3410
3411 /* Optional: */
3412 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3413 {
3414 TCGv t0 = tcg_temp_new();
3415 tcg_gen_trunc_i64_tl(t0, arg1),
3416 gen_qemu_st32(ctx, t0, arg2);
3417 tcg_temp_free(t0);
3418 }
3419 /* stfiwx */
3420 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3421
3422 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3423 {
3424 #if defined(TARGET_PPC64)
3425 if (ctx->has_cfar)
3426 tcg_gen_movi_tl(cpu_cfar, nip);
3427 #endif
3428 }
3429
3430 /*** Branch ***/
3431 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3432 {
3433 TranslationBlock *tb;
3434 tb = ctx->tb;
3435 #if defined(TARGET_PPC64)
3436 if (!ctx->sf_mode)
3437 dest = (uint32_t) dest;
3438 #endif
3439 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3440 likely(!ctx->singlestep_enabled)) {
3441 tcg_gen_goto_tb(n);
3442 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3443 tcg_gen_exit_tb((tcg_target_long)tb + n);
3444 } else {
3445 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3446 if (unlikely(ctx->singlestep_enabled)) {
3447 if ((ctx->singlestep_enabled &
3448 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3449 (ctx->exception == POWERPC_EXCP_BRANCH ||
3450 ctx->exception == POWERPC_EXCP_TRACE)) {
3451 target_ulong tmp = ctx->nip;
3452 ctx->nip = dest;
3453 gen_exception(ctx, POWERPC_EXCP_TRACE);
3454 ctx->nip = tmp;
3455 }
3456 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3457 gen_debug_exception(ctx);
3458 }
3459 }
3460 tcg_gen_exit_tb(0);
3461 }
3462 }
3463
3464 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3465 {
3466 #if defined(TARGET_PPC64)
3467 if (ctx->sf_mode == 0)
3468 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3469 else
3470 #endif
3471 tcg_gen_movi_tl(cpu_lr, nip);
3472 }
3473
3474 /* b ba bl bla */
3475 static void gen_b(DisasContext *ctx)
3476 {
3477 target_ulong li, target;
3478
3479 ctx->exception = POWERPC_EXCP_BRANCH;
3480 /* sign extend LI */
3481 #if defined(TARGET_PPC64)
3482 if (ctx->sf_mode)
3483 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3484 else
3485 #endif
3486 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3487 if (likely(AA(ctx->opcode) == 0))
3488 target = ctx->nip + li - 4;
3489 else
3490 target = li;
3491 if (LK(ctx->opcode))
3492 gen_setlr(ctx, ctx->nip);
3493 gen_update_cfar(ctx, ctx->nip);
3494 gen_goto_tb(ctx, 0, target);
3495 }
3496
3497 #define BCOND_IM 0
3498 #define BCOND_LR 1
3499 #define BCOND_CTR 2
3500
3501 static inline void gen_bcond(DisasContext *ctx, int type)
3502 {
3503 uint32_t bo = BO(ctx->opcode);
3504 int l1;
3505 TCGv target;
3506
3507 ctx->exception = POWERPC_EXCP_BRANCH;
3508 if (type == BCOND_LR || type == BCOND_CTR) {
3509 target = tcg_temp_local_new();
3510 if (type == BCOND_CTR)
3511 tcg_gen_mov_tl(target, cpu_ctr);
3512 else
3513 tcg_gen_mov_tl(target, cpu_lr);
3514 } else {
3515 TCGV_UNUSED(target);
3516 }
3517 if (LK(ctx->opcode))
3518 gen_setlr(ctx, ctx->nip);
3519 l1 = gen_new_label();
3520 if ((bo & 0x4) == 0) {
3521 /* Decrement and test CTR */
3522 TCGv temp = tcg_temp_new();
3523 if (unlikely(type == BCOND_CTR)) {
3524 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3525 return;
3526 }
3527 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3528 #if defined(TARGET_PPC64)
3529 if (!ctx->sf_mode)
3530 tcg_gen_ext32u_tl(temp, cpu_ctr);
3531 else
3532 #endif
3533 tcg_gen_mov_tl(temp, cpu_ctr);
3534 if (bo & 0x2) {
3535 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3536 } else {
3537 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3538 }
3539 tcg_temp_free(temp);
3540 }
3541 if ((bo & 0x10) == 0) {
3542 /* Test CR */
3543 uint32_t bi = BI(ctx->opcode);
3544 uint32_t mask = 1 << (3 - (bi & 0x03));
3545 TCGv_i32 temp = tcg_temp_new_i32();
3546
3547 if (bo & 0x8) {
3548 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3549 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3550 } else {
3551 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3552 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3553 }
3554 tcg_temp_free_i32(temp);
3555 }
3556 gen_update_cfar(ctx, ctx->nip);
3557 if (type == BCOND_IM) {
3558 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3559 if (likely(AA(ctx->opcode) == 0)) {
3560 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3561 } else {
3562 gen_goto_tb(ctx, 0, li);
3563 }
3564 gen_set_label(l1);
3565 gen_goto_tb(ctx, 1, ctx->nip);
3566 } else {
3567 #if defined(TARGET_PPC64)
3568 if (!(ctx->sf_mode))
3569 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3570 else
3571 #endif
3572 tcg_gen_andi_tl(cpu_nip, target, ~3);
3573 tcg_gen_exit_tb(0);
3574 gen_set_label(l1);
3575 #if defined(TARGET_PPC64)
3576 if (!(ctx->sf_mode))
3577 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3578 else
3579 #endif
3580 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3581 tcg_gen_exit_tb(0);
3582 }
3583 }
3584
3585 static void gen_bc(DisasContext *ctx)
3586 {
3587 gen_bcond(ctx, BCOND_IM);
3588 }
3589
3590 static void gen_bcctr(DisasContext *ctx)
3591 {
3592 gen_bcond(ctx, BCOND_CTR);
3593 }
3594
3595 static void gen_bclr(DisasContext *ctx)
3596 {
3597 gen_bcond(ctx, BCOND_LR);
3598 }
3599
3600 /*** Condition register logical ***/
3601 #define GEN_CRLOGIC(name, tcg_op, opc) \
3602 static void glue(gen_, name)(DisasContext *ctx) \
3603 { \
3604 uint8_t bitmask; \
3605 int sh; \
3606 TCGv_i32 t0, t1; \
3607 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3608 t0 = tcg_temp_new_i32(); \
3609 if (sh > 0) \
3610 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3611 else if (sh < 0) \
3612 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3613 else \
3614 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3615 t1 = tcg_temp_new_i32(); \
3616 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3617 if (sh > 0) \
3618 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3619 else if (sh < 0) \
3620 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3621 else \
3622 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3623 tcg_op(t0, t0, t1); \
3624 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3625 tcg_gen_andi_i32(t0, t0, bitmask); \
3626 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3627 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3628 tcg_temp_free_i32(t0); \
3629 tcg_temp_free_i32(t1); \
3630 }
3631
3632 /* crand */
3633 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3634 /* crandc */
3635 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3636 /* creqv */
3637 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3638 /* crnand */
3639 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3640 /* crnor */
3641 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3642 /* cror */
3643 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3644 /* crorc */
3645 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3646 /* crxor */
3647 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3648
3649 /* mcrf */
3650 static void gen_mcrf(DisasContext *ctx)
3651 {
3652 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3653 }
3654
3655 /*** System linkage ***/
3656
3657 /* rfi (mem_idx only) */
3658 static void gen_rfi(DisasContext *ctx)
3659 {
3660 #if defined(CONFIG_USER_ONLY)
3661 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3662 #else
3663 /* Restore CPU state */
3664 if (unlikely(!ctx->mem_idx)) {
3665 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3666 return;
3667 }
3668 gen_update_cfar(ctx, ctx->nip);
3669 gen_helper_rfi(cpu_env);
3670 gen_sync_exception(ctx);
3671 #endif
3672 }
3673
3674 #if defined(TARGET_PPC64)
3675 static void gen_rfid(DisasContext *ctx)
3676 {
3677 #if defined(CONFIG_USER_ONLY)
3678 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3679 #else
3680 /* Restore CPU state */
3681 if (unlikely(!ctx->mem_idx)) {
3682 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3683 return;
3684 }
3685 gen_update_cfar(ctx, ctx->nip);
3686 gen_helper_rfid(cpu_env);
3687 gen_sync_exception(ctx);
3688 #endif
3689 }
3690
3691 static void gen_hrfid(DisasContext *ctx)
3692 {
3693 #if defined(CONFIG_USER_ONLY)
3694 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3695 #else
3696 /* Restore CPU state */
3697 if (unlikely(ctx->mem_idx <= 1)) {
3698 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3699 return;
3700 }
3701 gen_helper_hrfid(cpu_env);
3702 gen_sync_exception(ctx);
3703 #endif
3704 }
3705 #endif
3706
3707 /* sc */
3708 #if defined(CONFIG_USER_ONLY)
3709 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3710 #else
3711 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3712 #endif
3713 static void gen_sc(DisasContext *ctx)
3714 {
3715 uint32_t lev;
3716
3717 lev = (ctx->opcode >> 5) & 0x7F;
3718 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3719 }
3720
3721 /*** Trap ***/
3722
3723 /* tw */
3724 static void gen_tw(DisasContext *ctx)
3725 {
3726 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3727 /* Update the nip since this might generate a trap exception */
3728 gen_update_nip(ctx, ctx->nip);
3729 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3730 t0);
3731 tcg_temp_free_i32(t0);
3732 }
3733
3734 /* twi */
3735 static void gen_twi(DisasContext *ctx)
3736 {
3737 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3738 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3739 /* Update the nip since this might generate a trap exception */
3740 gen_update_nip(ctx, ctx->nip);
3741 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3742 tcg_temp_free(t0);
3743 tcg_temp_free_i32(t1);
3744 }
3745
3746 #if defined(TARGET_PPC64)
3747 /* td */
3748 static void gen_td(DisasContext *ctx)
3749 {
3750 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3751 /* Update the nip since this might generate a trap exception */
3752 gen_update_nip(ctx, ctx->nip);
3753 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3754 t0);
3755 tcg_temp_free_i32(t0);
3756 }
3757
3758 /* tdi */
3759 static void gen_tdi(DisasContext *ctx)
3760 {
3761 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3762 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3763 /* Update the nip since this might generate a trap exception */
3764 gen_update_nip(ctx, ctx->nip);
3765 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3766 tcg_temp_free(t0);
3767 tcg_temp_free_i32(t1);
3768 }
3769 #endif
3770
3771 /*** Processor control ***/
3772
3773 static void gen_read_xer(TCGv dst)
3774 {
3775 TCGv t0 = tcg_temp_new();
3776 TCGv t1 = tcg_temp_new();
3777 TCGv t2 = tcg_temp_new();
3778 tcg_gen_mov_tl(dst, cpu_xer);
3779 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3780 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3781 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3782 tcg_gen_or_tl(t0, t0, t1);
3783 tcg_gen_or_tl(dst, dst, t2);
3784 tcg_gen_or_tl(dst, dst, t0);
3785 tcg_temp_free(t0);
3786 tcg_temp_free(t1);
3787 tcg_temp_free(t2);
3788 }
3789
3790 static void gen_write_xer(TCGv src)
3791 {
3792 tcg_gen_andi_tl(cpu_xer, src,
3793 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3794 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3795 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3796 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3797 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3798 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3799 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3800 }
3801
3802 /* mcrxr */
3803 static void gen_mcrxr(DisasContext *ctx)
3804 {
3805 TCGv_i32 t0 = tcg_temp_new_i32();
3806 TCGv_i32 t1 = tcg_temp_new_i32();
3807 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3808
3809 tcg_gen_trunc_tl_i32(t0, cpu_so);
3810 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3811 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3812 tcg_gen_shri_i32(t0, t0, 2);
3813 tcg_gen_shri_i32(t1, t1, 1);
3814 tcg_gen_or_i32(dst, dst, t0);
3815 tcg_gen_or_i32(dst, dst, t1);
3816 tcg_temp_free_i32(t0);
3817 tcg_temp_free_i32(t1);
3818
3819 tcg_gen_movi_tl(cpu_so, 0);
3820 tcg_gen_movi_tl(cpu_ov, 0);
3821 tcg_gen_movi_tl(cpu_ca, 0);
3822 }
3823
3824 /* mfcr mfocrf */
3825 static void gen_mfcr(DisasContext *ctx)
3826 {
3827 uint32_t crm, crn;
3828
3829 if (likely(ctx->opcode & 0x00100000)) {
3830 crm = CRM(ctx->opcode);
3831 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3832 crn = ctz32 (crm);
3833 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3834 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3835 cpu_gpr[rD(ctx->opcode)], crn * 4);
3836 }
3837 } else {
3838 TCGv_i32 t0 = tcg_temp_new_i32();
3839 tcg_gen_mov_i32(t0, cpu_crf[0]);
3840 tcg_gen_shli_i32(t0, t0, 4);
3841 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3842 tcg_gen_shli_i32(t0, t0, 4);
3843 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3844 tcg_gen_shli_i32(t0, t0, 4);
3845 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3846 tcg_gen_shli_i32(t0, t0, 4);
3847 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3848 tcg_gen_shli_i32(t0, t0, 4);
3849 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3850 tcg_gen_shli_i32(t0, t0, 4);
3851 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3852 tcg_gen_shli_i32(t0, t0, 4);
3853 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3854 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3855 tcg_temp_free_i32(t0);
3856 }
3857 }
3858
3859 /* mfmsr */
3860 static void gen_mfmsr(DisasContext *ctx)
3861 {
3862 #if defined(CONFIG_USER_ONLY)
3863 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3864 #else
3865 if (unlikely(!ctx->mem_idx)) {
3866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3867 return;
3868 }
3869 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3870 #endif
3871 }
3872
3873 static void spr_noaccess(void *opaque, int gprn, int sprn)
3874 {
3875 #if 0
3876 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3877 printf("ERROR: try to access SPR %d !\n", sprn);
3878 #endif
3879 }
3880 #define SPR_NOACCESS (&spr_noaccess)
3881
3882 /* mfspr */
3883 static inline void gen_op_mfspr(DisasContext *ctx)
3884 {
3885 void (*read_cb)(void *opaque, int gprn, int sprn);
3886 uint32_t sprn = SPR(ctx->opcode);
3887
3888 #if !defined(CONFIG_USER_ONLY)
3889 if (ctx->mem_idx == 2)
3890 read_cb = ctx->spr_cb[sprn].hea_read;
3891 else if (ctx->mem_idx)
3892 read_cb = ctx->spr_cb[sprn].oea_read;
3893 else
3894 #endif
3895 read_cb = ctx->spr_cb[sprn].uea_read;
3896 if (likely(read_cb != NULL)) {
3897 if (likely(read_cb != SPR_NOACCESS)) {
3898 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3899 } else {
3900 /* Privilege exception */
3901 /* This is a hack to avoid warnings when running Linux:
3902 * this OS breaks the PowerPC virtualisation model,
3903 * allowing userland application to read the PVR
3904 */
3905 if (sprn != SPR_PVR) {
3906 qemu_log("Trying to read privileged spr %d %03x at "
3907 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3908 printf("Trying to read privileged spr %d %03x at "
3909 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3910 }
3911 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3912 }
3913 } else {
3914 /* Not defined */
3915 qemu_log("Trying to read invalid spr %d %03x at "
3916 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3917 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3918 sprn, sprn, ctx->nip);
3919 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3920 }
3921 }
3922
3923 static void gen_mfspr(DisasContext *ctx)
3924 {
3925 gen_op_mfspr(ctx);
3926 }
3927
3928 /* mftb */
3929 static void gen_mftb(DisasContext *ctx)
3930 {
3931 gen_op_mfspr(ctx);
3932 }
3933
3934 /* mtcrf mtocrf*/
3935 static void gen_mtcrf(DisasContext *ctx)
3936 {
3937 uint32_t crm, crn;
3938
3939 crm = CRM(ctx->opcode);
3940 if (likely((ctx->opcode & 0x00100000))) {
3941 if (crm && ((crm & (crm - 1)) == 0)) {
3942 TCGv_i32 temp = tcg_temp_new_i32();
3943 crn = ctz32 (crm);
3944 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3945 tcg_gen_shri_i32(temp, temp, crn * 4);
3946 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3947 tcg_temp_free_i32(temp);
3948 }
3949 } else {
3950 TCGv_i32 temp = tcg_temp_new_i32();
3951 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3952 for (crn = 0 ; crn < 8 ; crn++) {
3953 if (crm & (1 << crn)) {
3954 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3955 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3956 }
3957 }
3958 tcg_temp_free_i32(temp);
3959 }
3960 }
3961
3962 /* mtmsr */
3963 #if defined(TARGET_PPC64)
3964 static void gen_mtmsrd(DisasContext *ctx)
3965 {
3966 #if defined(CONFIG_USER_ONLY)
3967 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3968 #else
3969 if (unlikely(!ctx->mem_idx)) {
3970 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3971 return;
3972 }
3973 if (ctx->opcode & 0x00010000) {
3974 /* Special form that does not need any synchronisation */
3975 TCGv t0 = tcg_temp_new();
3976 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3977 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3978 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3979 tcg_temp_free(t0);
3980 } else {
3981 /* XXX: we need to update nip before the store
3982 * if we enter power saving mode, we will exit the loop
3983 * directly from ppc_store_msr
3984 */
3985 gen_update_nip(ctx, ctx->nip);
3986 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3987 /* Must stop the translation as machine state (may have) changed */
3988 /* Note that mtmsr is not always defined as context-synchronizing */
3989 gen_stop_exception(ctx);
3990 }
3991 #endif
3992 }
3993 #endif
3994
3995 static void gen_mtmsr(DisasContext *ctx)
3996 {
3997 #if defined(CONFIG_USER_ONLY)
3998 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3999 #else
4000 if (unlikely(!ctx->mem_idx)) {
4001 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4002 return;
4003 }
4004 if (ctx->opcode & 0x00010000) {
4005 /* Special form that does not need any synchronisation */
4006 TCGv t0 = tcg_temp_new();
4007 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4008 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4009 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4010 tcg_temp_free(t0);
4011 } else {
4012 TCGv msr = tcg_temp_new();
4013
4014 /* XXX: we need to update nip before the store
4015 * if we enter power saving mode, we will exit the loop
4016 * directly from ppc_store_msr
4017 */
4018 gen_update_nip(ctx, ctx->nip);
4019 #if defined(TARGET_PPC64)
4020 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4021 #else
4022 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4023 #endif
4024 gen_helper_store_msr(cpu_env, msr);
4025 /* Must stop the translation as machine state (may have) changed */
4026 /* Note that mtmsr is not always defined as context-synchronizing */
4027 gen_stop_exception(ctx);
4028 }
4029 #endif
4030 }
4031
4032 /* mtspr */
4033 static void gen_mtspr(DisasContext *ctx)
4034 {
4035 void (*write_cb)(void *opaque, int sprn, int gprn);
4036 uint32_t sprn = SPR(ctx->opcode);
4037
4038 #if !defined(CONFIG_USER_ONLY)
4039 if (ctx->mem_idx == 2)
4040 write_cb = ctx->spr_cb[sprn].hea_write;
4041 else if (ctx->mem_idx)
4042 write_cb = ctx->spr_cb[sprn].oea_write;
4043 else
4044 #endif
4045 write_cb = ctx->spr_cb[sprn].uea_write;
4046 if (likely(write_cb != NULL)) {
4047 if (likely(write_cb != SPR_NOACCESS)) {
4048 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4049 } else {
4050 /* Privilege exception */
4051 qemu_log("Trying to write privileged spr %d %03x at "
4052 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4053 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
4054 "\n", sprn, sprn, ctx->nip);
4055 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4056 }
4057 } else {
4058 /* Not defined */
4059 qemu_log("Trying to write invalid spr %d %03x at "
4060 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4061 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
4062 sprn, sprn, ctx->nip);
4063 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4064 }
4065 }
4066
4067 /*** Cache management ***/
4068
4069 /* dcbf */
4070 static void gen_dcbf(DisasContext *ctx)
4071 {
4072 /* XXX: specification says this is treated as a load by the MMU */
4073 TCGv t0;
4074 gen_set_access_type(ctx, ACCESS_CACHE);
4075 t0 = tcg_temp_new();
4076 gen_addr_reg_index(ctx, t0);
4077 gen_qemu_ld8u(ctx, t0, t0);
4078 tcg_temp_free(t0);
4079 }
4080
4081 /* dcbi (Supervisor only) */
4082 static void gen_dcbi(DisasContext *ctx)
4083 {
4084 #if defined(CONFIG_USER_ONLY)
4085 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4086 #else
4087 TCGv EA, val;
4088 if (unlikely(!ctx->mem_idx)) {
4089 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4090 return;
4091 }
4092 EA = tcg_temp_new();
4093 gen_set_access_type(ctx, ACCESS_CACHE);
4094 gen_addr_reg_index(ctx, EA);
4095 val = tcg_temp_new();
4096 /* XXX: specification says this should be treated as a store by the MMU */
4097 gen_qemu_ld8u(ctx, val, EA);
4098 gen_qemu_st8(ctx, val, EA);
4099 tcg_temp_free(val);
4100 tcg_temp_free(EA);
4101 #endif
4102 }
4103
4104 /* dcdst */
4105 static void gen_dcbst(DisasContext *ctx)
4106 {
4107 /* XXX: specification say this is treated as a load by the MMU */
4108 TCGv t0;
4109 gen_set_access_type(ctx, ACCESS_CACHE);
4110 t0 = tcg_temp_new();
4111 gen_addr_reg_index(ctx, t0);
4112 gen_qemu_ld8u(ctx, t0, t0);
4113 tcg_temp_free(t0);
4114 }
4115
4116 /* dcbt */
4117 static void gen_dcbt(DisasContext *ctx)
4118 {
4119 /* interpreted as no-op */
4120 /* XXX: specification say this is treated as a load by the MMU
4121 * but does not generate any exception
4122 */
4123 }
4124
4125 /* dcbtst */
4126 static void gen_dcbtst(DisasContext *ctx)
4127 {
4128 /* interpreted as no-op */
4129 /* XXX: specification say this is treated as a load by the MMU
4130 * but does not generate any exception
4131 */
4132 }
4133
4134 /* dcbz */
4135 static void gen_dcbz(DisasContext *ctx)
4136 {
4137 TCGv tcgv_addr;
4138 TCGv_i32 tcgv_is_dcbzl;
4139 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4140
4141 gen_set_access_type(ctx, ACCESS_CACHE);
4142 /* NIP cannot be restored if the memory exception comes from an helper */
4143 gen_update_nip(ctx, ctx->nip - 4);
4144 tcgv_addr = tcg_temp_new();
4145 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4146
4147 gen_addr_reg_index(ctx, tcgv_addr);
4148 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4149
4150 tcg_temp_free(tcgv_addr);
4151 tcg_temp_free_i32(tcgv_is_dcbzl);
4152 }
4153
4154 /* dst / dstt */
4155 static void gen_dst(DisasContext *ctx)
4156 {
4157 if (rA(ctx->opcode) == 0) {
4158 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4159 } else {
4160 /* interpreted as no-op */
4161 }
4162 }
4163
4164 /* dstst /dststt */
4165 static void gen_dstst(DisasContext *ctx)
4166 {
4167 if (rA(ctx->opcode) == 0) {
4168 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4169 } else {
4170 /* interpreted as no-op */
4171 }
4172
4173 }
4174
4175 /* dss / dssall */
4176 static void gen_dss(DisasContext *ctx)
4177 {
4178 /* interpreted as no-op */
4179 }
4180
4181 /* icbi */
4182 static void gen_icbi(DisasContext *ctx)
4183 {
4184 TCGv t0;
4185 gen_set_access_type(ctx, ACCESS_CACHE);
4186 /* NIP cannot be restored if the memory exception comes from an helper */
4187 gen_update_nip(ctx, ctx->nip - 4);
4188 t0 = tcg_temp_new();
4189 gen_addr_reg_index(ctx, t0);
4190 gen_helper_icbi(cpu_env, t0);
4191 tcg_temp_free(t0);
4192 }
4193
4194 /* Optional: */
4195 /* dcba */
4196 static void gen_dcba(DisasContext *ctx)
4197 {
4198 /* interpreted as no-op */
4199 /* XXX: specification say this is treated as a store by the MMU
4200 * but does not generate any exception
4201 */
4202 }
4203
4204 /*** Segment register manipulation ***/
4205 /* Supervisor only: */
4206
4207 /* mfsr */
4208 static void gen_mfsr(DisasContext *ctx)
4209 {
4210 #if defined(CONFIG_USER_ONLY)
4211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4212 #else
4213 TCGv t0;
4214 if (unlikely(!ctx->mem_idx)) {
4215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4216 return;
4217 }
4218 t0 = tcg_const_tl(SR(ctx->opcode));
4219 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4220 tcg_temp_free(t0);
4221 #endif
4222 }
4223
4224 /* mfsrin */
4225 static void gen_mfsrin(DisasContext *ctx)
4226 {
4227 #if defined(CONFIG_USER_ONLY)
4228 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4229 #else
4230 TCGv t0;
4231 if (unlikely(!ctx->mem_idx)) {
4232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4233 return;
4234 }
4235 t0 = tcg_temp_new();
4236 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4237 tcg_gen_andi_tl(t0, t0, 0xF);
4238 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4239 tcg_temp_free(t0);
4240 #endif
4241 }
4242
4243 /* mtsr */
4244 static void gen_mtsr(DisasContext *ctx)
4245 {
4246 #if defined(CONFIG_USER_ONLY)
4247 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4248 #else
4249 TCGv t0;
4250 if (unlikely(!ctx->mem_idx)) {
4251 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4252 return;
4253 }
4254 t0 = tcg_const_tl(SR(ctx->opcode));
4255 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4256 tcg_temp_free(t0);
4257 #endif
4258 }
4259
4260 /* mtsrin */
4261 static void gen_mtsrin(DisasContext *ctx)
4262 {
4263 #if defined(CONFIG_USER_ONLY)
4264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4265 #else
4266 TCGv t0;
4267 if (unlikely(!ctx->mem_idx)) {
4268 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4269 return;
4270 }
4271 t0 = tcg_temp_new();
4272 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4273 tcg_gen_andi_tl(t0, t0, 0xF);
4274 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4275 tcg_temp_free(t0);
4276 #endif
4277 }
4278
4279 #if defined(TARGET_PPC64)
4280 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4281
4282 /* mfsr */
4283 static void gen_mfsr_64b(DisasContext *ctx)
4284 {
4285 #if defined(CONFIG_USER_ONLY)
4286 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4287 #else
4288 TCGv t0;
4289 if (unlikely(!ctx->mem_idx)) {
4290 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4291 return;
4292 }
4293 t0 = tcg_const_tl(SR(ctx->opcode));
4294 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4295 tcg_temp_free(t0);
4296 #endif
4297 }
4298
4299 /* mfsrin */
4300 static void gen_mfsrin_64b(DisasContext *ctx)
4301 {
4302 #if defined(CONFIG_USER_ONLY)
4303 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4304 #else
4305 TCGv t0;
4306 if (unlikely(!ctx->mem_idx)) {
4307 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4308 return;
4309 }
4310 t0 = tcg_temp_new();
4311 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4312 tcg_gen_andi_tl(t0, t0, 0xF);
4313 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4314 tcg_temp_free(t0);
4315 #endif
4316 }
4317
4318 /* mtsr */
4319 static void gen_mtsr_64b(DisasContext *ctx)
4320 {
4321 #if defined(CONFIG_USER_ONLY)
4322 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4323 #else
4324 TCGv t0;
4325 if (unlikely(!ctx->mem_idx)) {
4326 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4327 return;
4328 }
4329 t0 = tcg_const_tl(SR(ctx->opcode));
4330 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4331 tcg_temp_free(t0);
4332 #endif
4333 }
4334
4335 /* mtsrin */
4336 static void gen_mtsrin_64b(DisasContext *ctx)
4337 {
4338 #if defined(CONFIG_USER_ONLY)
4339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4340 #else
4341 TCGv t0;
4342 if (unlikely(!ctx->mem_idx)) {
4343 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4344 return;
4345 }
4346 t0 = tcg_temp_new();
4347 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4348 tcg_gen_andi_tl(t0, t0, 0xF);
4349 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4350 tcg_temp_free(t0);
4351 #endif
4352 }
4353
4354 /* slbmte */
4355 static void gen_slbmte(DisasContext *ctx)
4356 {
4357 #if defined(CONFIG_USER_ONLY)
4358 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4359 #else
4360 if (unlikely(!ctx->mem_idx)) {
4361 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4362 return;
4363 }
4364 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4365 cpu_gpr[rS(ctx->opcode)]);
4366 #endif
4367 }
4368
4369 static void gen_slbmfee(DisasContext *ctx)
4370 {
4371 #if defined(CONFIG_USER_ONLY)
4372 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4373 #else
4374 if (unlikely(!ctx->mem_idx)) {
4375 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4376 return;
4377 }
4378 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4379 cpu_gpr[rB(ctx->opcode)]);
4380 #endif
4381 }
4382
4383 static void gen_slbmfev(DisasContext *ctx)
4384 {
4385 #if defined(CONFIG_USER_ONLY)
4386 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4387 #else
4388 if (unlikely(!ctx->mem_idx)) {
4389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4390 return;
4391 }
4392 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4393 cpu_gpr[rB(ctx->opcode)]);
4394 #endif
4395 }
4396 #endif /* defined(TARGET_PPC64) */
4397
4398 /*** Lookaside buffer management ***/
4399 /* Optional & mem_idx only: */
4400
4401 /* tlbia */
4402 static void gen_tlbia(DisasContext *ctx)
4403 {
4404 #if defined(CONFIG_USER_ONLY)
4405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4406 #else
4407 if (unlikely(!ctx->mem_idx)) {
4408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4409 return;
4410 }
4411 gen_helper_tlbia(cpu_env);
4412 #endif
4413 }
4414
4415 /* tlbiel */
4416 static void gen_tlbiel(DisasContext *ctx)
4417 {
4418 #if defined(CONFIG_USER_ONLY)
4419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4420 #else
4421 if (unlikely(!ctx->mem_idx)) {
4422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4423 return;
4424 }
4425 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4426 #endif
4427 }
4428
4429 /* tlbie */
4430 static void gen_tlbie(DisasContext *ctx)
4431 {
4432 #if defined(CONFIG_USER_ONLY)
4433 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4434 #else
4435 if (unlikely(!ctx->mem_idx)) {
4436 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4437 return;
4438 }
4439 #if defined(TARGET_PPC64)
4440 if (!ctx->sf_mode) {
4441 TCGv t0 = tcg_temp_new();
4442 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4443 gen_helper_tlbie(cpu_env, t0);
4444 tcg_temp_free(t0);
4445 } else
4446 #endif
4447 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4448 #endif
4449 }
4450
4451 /* tlbsync */
4452 static void gen_tlbsync(DisasContext *ctx)
4453 {
4454 #if defined(CONFIG_USER_ONLY)
4455 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4456 #else
4457 if (unlikely(!ctx->mem_idx)) {
4458 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4459 return;
4460 }
4461 /* This has no effect: it should ensure that all previous
4462 * tlbie have completed
4463 */
4464 gen_stop_exception(ctx);
4465 #endif
4466 }
4467
4468 #if defined(TARGET_PPC64)
4469 /* slbia */
4470 static void gen_slbia(DisasContext *ctx)
4471 {
4472 #if defined(CONFIG_USER_ONLY)
4473 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4474 #else
4475 if (unlikely(!ctx->mem_idx)) {
4476 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4477 return;
4478 }
4479 gen_helper_slbia(cpu_env);
4480 #endif
4481 }
4482
4483 /* slbie */
4484 static void gen_slbie(DisasContext *ctx)
4485 {
4486 #if defined(CONFIG_USER_ONLY)
4487 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4488 #else
4489 if (unlikely(!ctx->mem_idx)) {
4490 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4491 return;
4492 }
4493 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4494 #endif
4495 }
4496 #endif
4497
4498 /*** External control ***/
4499 /* Optional: */
4500
4501 /* eciwx */
4502 static void gen_eciwx(DisasContext *ctx)
4503 {
4504 TCGv t0;
4505 /* Should check EAR[E] ! */
4506 gen_set_access_type(ctx, ACCESS_EXT);
4507 t0 = tcg_temp_new();
4508 gen_addr_reg_index(ctx, t0);
4509 gen_check_align(ctx, t0, 0x03);
4510 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4511 tcg_temp_free(t0);
4512 }
4513
4514 /* ecowx */
4515 static void gen_ecowx(DisasContext *ctx)
4516 {
4517 TCGv t0;
4518 /* Should check EAR[E] ! */
4519 gen_set_access_type(ctx, ACCESS_EXT);
4520 t0 = tcg_temp_new();
4521 gen_addr_reg_index(ctx, t0);
4522 gen_check_align(ctx, t0, 0x03);
4523 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4524 tcg_temp_free(t0);
4525 }
4526
4527 /* PowerPC 601 specific instructions */
4528
4529 /* abs - abs. */
4530 static void gen_abs(DisasContext *ctx)
4531 {
4532 int l1 = gen_new_label();
4533 int l2 = gen_new_label();
4534 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4535 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4536 tcg_gen_br(l2);
4537 gen_set_label(l1);
4538 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4539 gen_set_label(l2);
4540 if (unlikely(Rc(ctx->opcode) != 0))
4541 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4542 }
4543
4544 /* abso - abso. */
4545 static void gen_abso(DisasContext *ctx)
4546 {
4547 int l1 = gen_new_label();
4548 int l2 = gen_new_label();
4549 int l3 = gen_new_label();
4550 /* Start with XER OV disabled, the most likely case */
4551 tcg_gen_movi_tl(cpu_ov, 0);
4552 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4553 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4554 tcg_gen_movi_tl(cpu_ov, 1);
4555 tcg_gen_movi_tl(cpu_so, 1);
4556 tcg_gen_br(l2);
4557 gen_set_label(l1);
4558 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4559 tcg_gen_br(l3);
4560 gen_set_label(l2);
4561 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4562 gen_set_label(l3);
4563 if (unlikely(Rc(ctx->opcode) != 0))
4564 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4565 }
4566
4567 /* clcs */
4568 static void gen_clcs(DisasContext *ctx)
4569 {
4570 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4571 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4572 tcg_temp_free_i32(t0);
4573 /* Rc=1 sets CR0 to an undefined state */
4574 }
4575
4576 /* div - div. */
4577 static void gen_div(DisasContext *ctx)
4578 {
4579 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4580 cpu_gpr[rB(ctx->opcode)]);
4581 if (unlikely(Rc(ctx->opcode) != 0))
4582 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4583 }
4584
4585 /* divo - divo. */
4586 static void gen_divo(DisasContext *ctx)
4587 {
4588 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4589 cpu_gpr[rB(ctx->opcode)]);
4590 if (unlikely(Rc(ctx->opcode) != 0))
4591 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4592 }
4593
4594 /* divs - divs. */
4595 static void gen_divs(DisasContext *ctx)
4596 {
4597 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4598 cpu_gpr[rB(ctx->opcode)]);
4599 if (unlikely(Rc(ctx->opcode) != 0))
4600 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4601 }
4602
4603 /* divso - divso. */
4604 static void gen_divso(DisasContext *ctx)
4605 {
4606 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4607 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4608 if (unlikely(Rc(ctx->opcode) != 0))
4609 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4610 }
4611
4612 /* doz - doz. */
4613 static void gen_doz(DisasContext *ctx)
4614 {
4615 int l1 = gen_new_label();
4616 int l2 = gen_new_label();
4617 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4618 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4619 tcg_gen_br(l2);
4620 gen_set_label(l1);
4621 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4622 gen_set_label(l2);
4623 if (unlikely(Rc(ctx->opcode) != 0))
4624 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4625 }
4626
4627 /* dozo - dozo. */
4628 static void gen_dozo(DisasContext *ctx)
4629 {
4630 int l1 = gen_new_label();
4631 int l2 = gen_new_label();
4632 TCGv t0 = tcg_temp_new();
4633 TCGv t1 = tcg_temp_new();
4634 TCGv t2 = tcg_temp_new();
4635 /* Start with XER OV disabled, the most likely case */
4636 tcg_gen_movi_tl(cpu_ov, 0);
4637 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4638 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4639 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4640 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4641 tcg_gen_andc_tl(t1, t1, t2);
4642 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4643 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4644 tcg_gen_movi_tl(cpu_ov, 1);
4645 tcg_gen_movi_tl(cpu_so, 1);
4646 tcg_gen_br(l2);
4647 gen_set_label(l1);
4648 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4649 gen_set_label(l2);
4650 tcg_temp_free(t0);
4651 tcg_temp_free(t1);
4652 tcg_temp_free(t2);
4653 if (unlikely(Rc(ctx->opcode) != 0))
4654 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4655 }
4656
4657 /* dozi */
4658 static void gen_dozi(DisasContext *ctx)
4659 {
4660 target_long simm = SIMM(ctx->opcode);
4661 int l1 = gen_new_label();
4662 int l2 = gen_new_label();
4663 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4664 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4665 tcg_gen_br(l2);
4666 gen_set_label(l1);
4667 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4668 gen_set_label(l2);
4669 if (unlikely(Rc(ctx->opcode) != 0))
4670 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4671 }
4672
4673 /* lscbx - lscbx. */
4674 static void gen_lscbx(DisasContext *ctx)
4675 {
4676 TCGv t0 = tcg_temp_new();
4677 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4678 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4679 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4680
4681 gen_addr_reg_index(ctx, t0);
4682 /* NIP cannot be restored if the memory exception comes from an helper */
4683 gen_update_nip(ctx, ctx->nip - 4);
4684 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4685 tcg_temp_free_i32(t1);
4686 tcg_temp_free_i32(t2);
4687 tcg_temp_free_i32(t3);
4688 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4689 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4690 if (unlikely(Rc(ctx->opcode) != 0))
4691 gen_set_Rc0(ctx, t0);
4692 tcg_temp_free(t0);
4693 }
4694
4695 /* maskg - maskg. */
4696 static void gen_maskg(DisasContext *ctx)
4697 {
4698 int l1 = gen_new_label();
4699 TCGv t0 = tcg_temp_new();
4700 TCGv t1 = tcg_temp_new();
4701 TCGv t2 = tcg_temp_new();
4702 TCGv t3 = tcg_temp_new();
4703 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4704 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4705 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4706 tcg_gen_addi_tl(t2, t0, 1);
4707 tcg_gen_shr_tl(t2, t3, t2);
4708 tcg_gen_shr_tl(t3, t3, t1);
4709 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4710 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4711 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4712 gen_set_label(l1);
4713 tcg_temp_free(t0);
4714 tcg_temp_free(t1);
4715 tcg_temp_free(t2);
4716 tcg_temp_free(t3);
4717 if (unlikely(Rc(ctx->opcode) != 0))
4718 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4719 }
4720
4721 /* maskir - maskir. */
4722 static void gen_maskir(DisasContext *ctx)
4723 {
4724 TCGv t0 = tcg_temp_new();
4725 TCGv t1 = tcg_temp_new();
4726 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4727 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4728 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4729 tcg_temp_free(t0);
4730 tcg_temp_free(t1);
4731 if (unlikely(Rc(ctx->opcode) != 0))
4732 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4733 }
4734
4735 /* mul - mul. */
4736 static void gen_mul(DisasContext *ctx)
4737 {
4738 TCGv_i64 t0 = tcg_temp_new_i64();
4739 TCGv_i64 t1 = tcg_temp_new_i64();
4740 TCGv t2 = tcg_temp_new();
4741 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4742 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4743 tcg_gen_mul_i64(t0, t0, t1);
4744 tcg_gen_trunc_i64_tl(t2, t0);
4745 gen_store_spr(SPR_MQ, t2);
4746 tcg_gen_shri_i64(t1, t0, 32);
4747 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4748 tcg_temp_free_i64(t0);
4749 tcg_temp_free_i64(t1);
4750 tcg_temp_free(t2);
4751 if (unlikely(Rc(ctx->opcode) != 0))
4752 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4753 }
4754
4755 /* mulo - mulo. */
4756 static void gen_mulo(DisasContext *ctx)
4757 {
4758 int l1 = gen_new_label();
4759 TCGv_i64 t0 = tcg_temp_new_i64();
4760 TCGv_i64 t1 = tcg_temp_new_i64();
4761 TCGv t2 = tcg_temp_new();
4762 /* Start with XER OV disabled, the most likely case */
4763 tcg_gen_movi_tl(cpu_ov, 0);
4764 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4765 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4766 tcg_gen_mul_i64(t0, t0, t1);
4767 tcg_gen_trunc_i64_tl(t2, t0);
4768 gen_store_spr(SPR_MQ, t2);
4769 tcg_gen_shri_i64(t1, t0, 32);
4770 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4771 tcg_gen_ext32s_i64(t1, t0);
4772 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4773 tcg_gen_movi_tl(cpu_ov, 1);
4774 tcg_gen_movi_tl(cpu_so, 1);
4775 gen_set_label(l1);
4776 tcg_temp_free_i64(t0);
4777 tcg_temp_free_i64(t1);
4778 tcg_temp_free(t2);
4779 if (unlikely(Rc(ctx->opcode) != 0))
4780 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4781 }
4782
4783 /* nabs - nabs. */
4784 static void gen_nabs(DisasContext *ctx)
4785 {
4786 int l1 = gen_new_label();
4787 int l2 = gen_new_label();
4788 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4789 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4790 tcg_gen_br(l2);
4791 gen_set_label(l1);
4792 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4793 gen_set_label(l2);
4794 if (unlikely(Rc(ctx->opcode) != 0))
4795 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4796 }
4797
4798 /* nabso - nabso. */
4799 static void gen_nabso(DisasContext *ctx)
4800 {
4801 int l1 = gen_new_label();
4802 int l2 = gen_new_label();
4803 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4804 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4805 tcg_gen_br(l2);
4806 gen_set_label(l1);
4807 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4808 gen_set_label(l2);
4809 /* nabs never overflows */
4810 tcg_gen_movi_tl(cpu_ov, 0);
4811 if (unlikely(Rc(ctx->opcode) != 0))
4812 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4813 }
4814
4815 /* rlmi - rlmi. */
4816 static void gen_rlmi(DisasContext *ctx)
4817 {
4818 uint32_t mb = MB(ctx->opcode);
4819 uint32_t me = ME(ctx->opcode);
4820 TCGv t0 = tcg_temp_new();
4821 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4822 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4823 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4824 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4825 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4826 tcg_temp_free(t0);
4827 if (unlikely(Rc(ctx->opcode) != 0))
4828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4829 }
4830
4831 /* rrib - rrib. */
4832 static void gen_rrib(DisasContext *ctx)
4833 {
4834 TCGv t0 = tcg_temp_new();
4835 TCGv t1 = tcg_temp_new();
4836 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4837 tcg_gen_movi_tl(t1, 0x80000000);
4838 tcg_gen_shr_tl(t1, t1, t0);
4839 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4840 tcg_gen_and_tl(t0, t0, t1);
4841 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4842 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4843 tcg_temp_free(t0);
4844 tcg_temp_free(t1);
4845 if (unlikely(Rc(ctx->opcode) != 0))
4846 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4847 }
4848
4849 /* sle - sle. */
4850 static void gen_sle(DisasContext *ctx)
4851 {
4852 TCGv t0 = tcg_temp_new();
4853 TCGv t1 = tcg_temp_new();
4854 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4855 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4856 tcg_gen_subfi_tl(t1, 32, t1);
4857 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4858 tcg_gen_or_tl(t1, t0, t1);
4859 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4860 gen_store_spr(SPR_MQ, t1);
4861 tcg_temp_free(t0);
4862 tcg_temp_free(t1);
4863 if (unlikely(Rc(ctx->opcode) != 0))
4864 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4865 }
4866
4867 /* sleq - sleq. */
4868 static void gen_sleq(DisasContext *ctx)
4869 {
4870 TCGv t0 = tcg_temp_new();
4871 TCGv t1 = tcg_temp_new();
4872 TCGv t2 = tcg_temp_new();
4873 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4874 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4875 tcg_gen_shl_tl(t2, t2, t0);
4876 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4877 gen_load_spr(t1, SPR_MQ);
4878 gen_store_spr(SPR_MQ, t0);
4879 tcg_gen_and_tl(t0, t0, t2);
4880 tcg_gen_andc_tl(t1, t1, t2);
4881 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4882 tcg_temp_free(t0);
4883 tcg_temp_free(t1);
4884 tcg_temp_free(t2);
4885 if (unlikely(Rc(ctx->opcode) != 0))
4886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4887 }
4888
4889 /* sliq - sliq. */
4890 static void gen_sliq(DisasContext *ctx)
4891 {
4892 int sh = SH(ctx->opcode);
4893 TCGv t0 = tcg_temp_new();
4894 TCGv t1 = tcg_temp_new();
4895 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4896 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4897 tcg_gen_or_tl(t1, t0, t1);
4898 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4899 gen_store_spr(SPR_MQ, t1);
4900 tcg_temp_free(t0);
4901 tcg_temp_free(t1);
4902 if (unlikely(Rc(ctx->opcode) != 0))
4903 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4904 }
4905
4906 /* slliq - slliq. */
4907 static void gen_slliq(DisasContext *ctx)
4908 {
4909 int sh = SH(ctx->opcode);
4910 TCGv t0 = tcg_temp_new();
4911 TCGv t1 = tcg_temp_new();
4912 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4913 gen_load_spr(t1, SPR_MQ);
4914 gen_store_spr(SPR_MQ, t0);
4915 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4916 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4917 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4918 tcg_temp_free(t0);
4919 tcg_temp_free(t1);
4920 if (unlikely(Rc(ctx->opcode) != 0))
4921 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4922 }
4923
4924 /* sllq - sllq. */
4925 static void gen_sllq(DisasContext *ctx)
4926 {
4927 int l1 = gen_new_label();
4928 int l2 = gen_new_label();
4929 TCGv t0 = tcg_temp_local_new();
4930 TCGv t1 = tcg_temp_local_new();
4931 TCGv t2 = tcg_temp_local_new();
4932 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4933 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4934 tcg_gen_shl_tl(t1, t1, t2);
4935 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4936 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4937 gen_load_spr(t0, SPR_MQ);
4938 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4939 tcg_gen_br(l2);
4940 gen_set_label(l1);
4941 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4942 gen_load_spr(t2, SPR_MQ);
4943 tcg_gen_andc_tl(t1, t2, t1);
4944 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4945 gen_set_label(l2);
4946 tcg_temp_free(t0);
4947 tcg_temp_free(t1);
4948 tcg_temp_free(t2);
4949 if (unlikely(Rc(ctx->opcode) != 0))
4950 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4951 }
4952
4953 /* slq - slq. */
4954 static void gen_slq(DisasContext *ctx)
4955 {
4956 int l1 = gen_new_label();
4957 TCGv t0 = tcg_temp_new();
4958 TCGv t1 = tcg_temp_new();
4959 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4960 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4961 tcg_gen_subfi_tl(t1, 32, t1);
4962 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4963 tcg_gen_or_tl(t1, t0, t1);
4964 gen_store_spr(SPR_MQ, t1);
4965 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4966 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4967 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4968 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4969 gen_set_label(l1);
4970 tcg_temp_free(t0);
4971 tcg_temp_free(t1);
4972 if (unlikely(Rc(ctx->opcode) != 0))
4973 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4974 }
4975
4976 /* sraiq - sraiq. */
4977 static void gen_sraiq(DisasContext *ctx)
4978 {
4979 int sh = SH(ctx->opcode);
4980 int l1 = gen_new_label();
4981 TCGv t0 = tcg_temp_new();
4982 TCGv t1 = tcg_temp_new();
4983 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4984 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4985 tcg_gen_or_tl(t0, t0, t1);
4986 gen_store_spr(SPR_MQ, t0);
4987 tcg_gen_movi_tl(cpu_ca, 0);
4988 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4989 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4990 tcg_gen_movi_tl(cpu_ca, 1);
4991 gen_set_label(l1);
4992 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4993 tcg_temp_free(t0);
4994 tcg_temp_free(t1);
4995 if (unlikely(Rc(ctx->opcode) != 0))
4996 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4997 }
4998
4999 /* sraq - sraq. */
5000 static void gen_sraq(DisasContext *ctx)
5001 {
5002 int l1 = gen_new_label();
5003 int l2 = gen_new_label();
5004 TCGv t0 = tcg_temp_new();
5005 TCGv t1 = tcg_temp_local_new();
5006 TCGv t2 = tcg_temp_local_new();
5007 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5008 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5009 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5010 tcg_gen_subfi_tl(t2, 32, t2);
5011 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5012 tcg_gen_or_tl(t0, t0, t2);
5013 gen_store_spr(SPR_MQ, t0);
5014 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5015 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5016 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5017 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5018 gen_set_label(l1);
5019 tcg_temp_free(t0);
5020 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5021 tcg_gen_movi_tl(cpu_ca, 0);
5022 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5023 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5024 tcg_gen_movi_tl(cpu_ca, 1);
5025 gen_set_label(l2);
5026 tcg_temp_free(t1);
5027 tcg_temp_free(t2);
5028 if (unlikely(Rc(ctx->opcode) != 0))
5029 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5030 }
5031
5032 /* sre - sre. */
5033 static void gen_sre(DisasContext *ctx)
5034 {
5035 TCGv t0 = tcg_temp_new();
5036 TCGv t1 = tcg_temp_new();
5037 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5038 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5039 tcg_gen_subfi_tl(t1, 32, t1);
5040 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5041 tcg_gen_or_tl(t1, t0, t1);
5042 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5043 gen_store_spr(SPR_MQ, t1);
5044 tcg_temp_free(t0);
5045 tcg_temp_free(t1);
5046 if (unlikely(Rc(ctx->opcode) != 0))
5047 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5048 }
5049
5050 /* srea - srea. */
5051 static void gen_srea(DisasContext *ctx)
5052 {
5053 TCGv t0 = tcg_temp_new();
5054 TCGv t1 = tcg_temp_new();
5055 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5056 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5057 gen_store_spr(SPR_MQ, t0);
5058 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5059 tcg_temp_free(t0);
5060 tcg_temp_free(t1);
5061 if (unlikely(Rc(ctx->opcode) != 0))
5062 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5063 }
5064
5065 /* sreq */
5066 static void gen_sreq(DisasContext *ctx)
5067 {
5068 TCGv t0 = tcg_temp_new();
5069 TCGv t1 = tcg_temp_new();
5070 TCGv t2 = tcg_temp_new();
5071 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5072 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5073 tcg_gen_shr_tl(t1, t1, t0);
5074 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5075 gen_load_spr(t2, SPR_MQ);
5076 gen_store_spr(SPR_MQ, t0);
5077 tcg_gen_and_tl(t0, t0, t1);
5078 tcg_gen_andc_tl(t2, t2, t1);
5079 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5080 tcg_temp_free(t0);
5081 tcg_temp_free(t1);
5082 tcg_temp_free(t2);
5083 if (unlikely(Rc(ctx->opcode) != 0))
5084 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5085 }
5086
5087 /* sriq */
5088 static void gen_sriq(DisasContext *ctx)
5089 {
5090 int sh = SH(ctx->opcode);
5091 TCGv t0 = tcg_temp_new();
5092 TCGv t1 = tcg_temp_new();
5093 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5094 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5095 tcg_gen_or_tl(t1, t0, t1);
5096 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5097 gen_store_spr(SPR_MQ, t1);
5098 tcg_temp_free(t0);
5099 tcg_temp_free(t1);
5100 if (unlikely(Rc(ctx->opcode) != 0))
5101 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5102 }
5103
5104 /* srliq */
5105 static void gen_srliq(DisasContext *ctx)
5106 {
5107 int sh = SH(ctx->opcode);
5108 TCGv t0 = tcg_temp_new();
5109 TCGv t1 = tcg_temp_new();
5110 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5111 gen_load_spr(t1, SPR_MQ);
5112 gen_store_spr(SPR_MQ, t0);
5113 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5114 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5115 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5116 tcg_temp_free(t0);
5117 tcg_temp_free(t1);
5118 if (unlikely(Rc(ctx->opcode) != 0))
5119 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5120 }
5121
5122 /* srlq */
5123 static void gen_srlq(DisasContext *ctx)
5124 {
5125 int l1 = gen_new_label();
5126 int l2 = gen_new_label();
5127 TCGv t0 = tcg_temp_local_new();
5128 TCGv t1 = tcg_temp_local_new();
5129 TCGv t2 = tcg_temp_local_new();
5130 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5131 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5132 tcg_gen_shr_tl(t2, t1, t2);
5133 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5134 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5135 gen_load_spr(t0, SPR_MQ);
5136 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5137 tcg_gen_br(l2);
5138 gen_set_label(l1);
5139 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5140 tcg_gen_and_tl(t0, t0, t2);
5141 gen_load_spr(t1, SPR_MQ);
5142 tcg_gen_andc_tl(t1, t1, t2);
5143 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5144 gen_set_label(l2);
5145 tcg_temp_free(t0);
5146 tcg_temp_free(t1);
5147 tcg_temp_free(t2);
5148 if (unlikely(Rc(ctx->opcode) != 0))
5149 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5150 }
5151
5152 /* srq */
5153 static void gen_srq(DisasContext *ctx)
5154 {
5155 int l1 = gen_new_label();
5156 TCGv t0 = tcg_temp_new();
5157 TCGv t1 = tcg_temp_new();
5158 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5159 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5160 tcg_gen_subfi_tl(t1, 32, t1);
5161 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5162 tcg_gen_or_tl(t1, t0, t1);
5163 gen_store_spr(SPR_MQ, t1);
5164 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5165 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5166 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5167 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5168 gen_set_label(l1);
5169 tcg_temp_free(t0);
5170 tcg_temp_free(t1);
5171 if (unlikely(Rc(ctx->opcode) != 0))
5172 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5173 }
5174
5175 /* PowerPC 602 specific instructions */
5176
5177 /* dsa */
5178 static void gen_dsa(DisasContext *ctx)
5179 {
5180 /* XXX: TODO */
5181 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5182 }
5183
5184 /* esa */
5185 static void gen_esa(DisasContext *ctx)
5186 {
5187 /* XXX: TODO */
5188 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5189 }
5190
5191 /* mfrom */
5192 static void gen_mfrom(DisasContext *ctx)
5193 {
5194 #if defined(CONFIG_USER_ONLY)
5195 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5196 #else
5197 if (unlikely(!ctx->mem_idx)) {
5198 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5199 return;
5200 }
5201 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5202 #endif
5203 }
5204
5205 /* 602 - 603 - G2 TLB management */
5206
5207 /* tlbld */
5208 static void gen_tlbld_6xx(DisasContext *ctx)
5209 {
5210 #if defined(CONFIG_USER_ONLY)
5211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5212 #else
5213 if (unlikely(!ctx->mem_idx)) {
5214 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5215 return;
5216 }
5217 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5218 #endif
5219 }
5220
5221 /* tlbli */
5222 static void gen_tlbli_6xx(DisasContext *ctx)
5223 {
5224 #if defined(CONFIG_USER_ONLY)
5225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5226 #else
5227 if (unlikely(!ctx->mem_idx)) {
5228 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5229 return;
5230 }
5231 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5232 #endif
5233 }
5234
5235 /* 74xx TLB management */
5236
5237 /* tlbld */
5238 static void gen_tlbld_74xx(DisasContext *ctx)
5239 {
5240 #if defined(CONFIG_USER_ONLY)
5241 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5242 #else
5243 if (unlikely(!ctx->mem_idx)) {
5244 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5245 return;
5246 }
5247 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5248 #endif
5249 }
5250
5251 /* tlbli */
5252 static void gen_tlbli_74xx(DisasContext *ctx)
5253 {
5254 #if defined(CONFIG_USER_ONLY)
5255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5256 #else
5257 if (unlikely(!ctx->mem_idx)) {
5258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5259 return;
5260 }
5261 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5262 #endif
5263 }
5264
5265 /* POWER instructions not in PowerPC 601 */
5266
5267 /* clf */
5268 static void gen_clf(DisasContext *ctx)
5269 {
5270 /* Cache line flush: implemented as no-op */
5271 }
5272
5273 /* cli */
5274 static void gen_cli(DisasContext *ctx)
5275 {
5276 /* Cache line invalidate: privileged and treated as no-op */
5277 #if defined(CONFIG_USER_ONLY)
5278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5279 #else
5280 if (unlikely(!ctx->mem_idx)) {
5281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5282 return;
5283 }
5284 #endif
5285 }
5286
5287 /* dclst */
5288 static void gen_dclst(DisasContext *ctx)
5289 {
5290 /* Data cache line store: treated as no-op */
5291 }
5292
5293 static void gen_mfsri(DisasContext *ctx)
5294 {
5295 #if defined(CONFIG_USER_ONLY)
5296 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5297 #else
5298 int ra = rA(ctx->opcode);
5299 int rd = rD(ctx->opcode);
5300 TCGv t0;
5301 if (unlikely(!ctx->mem_idx)) {
5302 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5303 return;
5304 }
5305 t0 = tcg_temp_new();
5306 gen_addr_reg_index(ctx, t0);
5307 tcg_gen_shri_tl(t0, t0, 28);
5308 tcg_gen_andi_tl(t0, t0, 0xF);
5309 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5310 tcg_temp_free(t0);
5311 if (ra != 0 && ra != rd)
5312 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5313 #endif
5314 }
5315
5316 static void gen_rac(DisasContext *ctx)
5317 {
5318 #if defined(CONFIG_USER_ONLY)
5319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5320 #else
5321 TCGv t0;
5322 if (unlikely(!ctx->mem_idx)) {
5323 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5324 return;
5325 }
5326 t0 = tcg_temp_new();
5327 gen_addr_reg_index(ctx, t0);
5328 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5329 tcg_temp_free(t0);
5330 #endif
5331 }
5332
5333 static void gen_rfsvc(DisasContext *ctx)
5334 {
5335 #if defined(CONFIG_USER_ONLY)
5336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5337 #else
5338 if (unlikely(!ctx->mem_idx)) {
5339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5340 return;
5341 }
5342 gen_helper_rfsvc(cpu_env);
5343 gen_sync_exception(ctx);
5344 #endif
5345 }
5346
5347 /* svc is not implemented for now */
5348
5349 /* POWER2 specific instructions */
5350 /* Quad manipulation (load/store two floats at a time) */
5351
5352 /* lfq */
5353 static void gen_lfq(DisasContext *ctx)
5354 {
5355 int rd = rD(ctx->opcode);
5356 TCGv t0;
5357 gen_set_access_type(ctx, ACCESS_FLOAT);
5358 t0 = tcg_temp_new();
5359 gen_addr_imm_index(ctx, t0, 0);
5360 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5361 gen_addr_add(ctx, t0, t0, 8);
5362 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5363 tcg_temp_free(t0);
5364 }
5365
5366 /* lfqu */
5367 static void gen_lfqu(DisasContext *ctx)
5368 {
5369 int ra = rA(ctx->opcode);
5370 int rd = rD(ctx->opcode);
5371 TCGv t0, t1;
5372 gen_set_access_type(ctx, ACCESS_FLOAT);
5373 t0 = tcg_temp_new();
5374 t1 = tcg_temp_new();
5375 gen_addr_imm_index(ctx, t0, 0);
5376 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5377 gen_addr_add(ctx, t1, t0, 8);
5378 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5379 if (ra != 0)
5380 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5381 tcg_temp_free(t0);
5382 tcg_temp_free(t1);
5383 }
5384
5385 /* lfqux */
5386 static void gen_lfqux(DisasContext *ctx)
5387 {
5388 int ra = rA(ctx->opcode);
5389 int rd = rD(ctx->opcode);
5390 gen_set_access_type(ctx, ACCESS_FLOAT);
5391 TCGv t0, t1;
5392 t0 = tcg_temp_new();
5393 gen_addr_reg_index(ctx, t0);
5394 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5395 t1 = tcg_temp_new();
5396 gen_addr_add(ctx, t1, t0, 8);
5397 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5398 tcg_temp_free(t1);
5399 if (ra != 0)
5400 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5401 tcg_temp_free(t0);
5402 }
5403
5404 /* lfqx */
5405 static void gen_lfqx(DisasContext *ctx)
5406 {
5407 int rd = rD(ctx->opcode);
5408 TCGv t0;
5409 gen_set_access_type(ctx, ACCESS_FLOAT);
5410 t0 = tcg_temp_new();
5411 gen_addr_reg_index(ctx, t0);
5412 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5413 gen_addr_add(ctx, t0, t0, 8);
5414 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5415 tcg_temp_free(t0);
5416 }
5417
5418 /* stfq */
5419 static void gen_stfq(DisasContext *ctx)
5420 {
5421 int rd = rD(ctx->opcode);
5422 TCGv t0;
5423 gen_set_access_type(ctx, ACCESS_FLOAT);
5424 t0 = tcg_temp_new();
5425 gen_addr_imm_index(ctx, t0, 0);
5426 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5427 gen_addr_add(ctx, t0, t0, 8);
5428 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5429 tcg_temp_free(t0);
5430 }
5431
5432 /* stfqu */
5433 static void gen_stfqu(DisasContext *ctx)
5434 {
5435 int ra = rA(ctx->opcode);
5436 int rd = rD(ctx->opcode);
5437 TCGv t0, t1;
5438 gen_set_access_type(ctx, ACCESS_FLOAT);
5439 t0 = tcg_temp_new();
5440 gen_addr_imm_index(ctx, t0, 0);
5441 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5442 t1 = tcg_temp_new();
5443 gen_addr_add(ctx, t1, t0, 8);
5444 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5445 tcg_temp_free(t1);
5446 if (ra != 0)
5447 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5448 tcg_temp_free(t0);
5449 }
5450
5451 /* stfqux */
5452 static void gen_stfqux(DisasContext *ctx)
5453 {
5454 int ra = rA(ctx->opcode);
5455 int rd = rD(ctx->opcode);
5456 TCGv t0, t1;
5457 gen_set_access_type(ctx, ACCESS_FLOAT);
5458 t0 = tcg_temp_new();
5459 gen_addr_reg_index(ctx, t0);
5460 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5461 t1 = tcg_temp_new();
5462 gen_addr_add(ctx, t1, t0, 8);
5463 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5464 tcg_temp_free(t1);
5465 if (ra != 0)
5466 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5467 tcg_temp_free(t0);
5468 }
5469
5470 /* stfqx */
5471 static void gen_stfqx(DisasContext *ctx)
5472 {
5473 int rd = rD(ctx->opcode);
5474 TCGv t0;
5475 gen_set_access_type(ctx, ACCESS_FLOAT);
5476 t0 = tcg_temp_new();
5477 gen_addr_reg_index(ctx, t0);
5478 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5479 gen_addr_add(ctx, t0, t0, 8);
5480 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5481 tcg_temp_free(t0);
5482 }
5483
5484 /* BookE specific instructions */
5485
5486 /* XXX: not implemented on 440 ? */
5487 static void gen_mfapidi(DisasContext *ctx)
5488 {
5489 /* XXX: TODO */
5490 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5491 }
5492
5493 /* XXX: not implemented on 440 ? */
5494 static void gen_tlbiva(DisasContext *ctx)
5495 {
5496 #if defined(CONFIG_USER_ONLY)
5497 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5498 #else
5499 TCGv t0;
5500 if (unlikely(!ctx->mem_idx)) {
5501 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5502 return;
5503 }
5504 t0 = tcg_temp_new();
5505 gen_addr_reg_index(ctx, t0);
5506 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5507 tcg_temp_free(t0);
5508 #endif
5509 }
5510
5511 /* All 405 MAC instructions are translated here */
5512 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5513 int ra, int rb, int rt, int Rc)
5514 {
5515 TCGv t0, t1;
5516
5517 t0 = tcg_temp_local_new();
5518 t1 = tcg_temp_local_new();
5519
5520 switch (opc3 & 0x0D) {
5521 case 0x05:
5522 /* macchw - macchw. - macchwo - macchwo. */
5523 /* macchws - macchws. - macchwso - macchwso. */
5524 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5525 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5526 /* mulchw - mulchw. */
5527 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5528 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5529 tcg_gen_ext16s_tl(t1, t1);
5530 break;
5531 case 0x04:
5532 /* macchwu - macchwu. - macchwuo - macchwuo. */
5533 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5534 /* mulchwu - mulchwu. */
5535 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5536 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5537 tcg_gen_ext16u_tl(t1, t1);
5538 break;
5539 case 0x01:
5540 /* machhw - machhw. - machhwo - machhwo. */
5541 /* machhws - machhws. - machhwso - machhwso. */
5542 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5543 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5544 /* mulhhw - mulhhw. */
5545 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5546 tcg_gen_ext16s_tl(t0, t0);
5547 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5548 tcg_gen_ext16s_tl(t1, t1);
5549 break;
5550 case 0x00:
5551 /* machhwu - machhwu. - machhwuo - machhwuo. */
5552 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5553 /* mulhhwu - mulhhwu. */
5554 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5555 tcg_gen_ext16u_tl(t0, t0);
5556 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5557 tcg_gen_ext16u_tl(t1, t1);
5558 break;
5559 case 0x0D:
5560 /* maclhw - maclhw. - maclhwo - maclhwo. */
5561 /* maclhws - maclhws. - maclhwso - maclhwso. */
5562 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5563 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5564 /* mullhw - mullhw. */
5565 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5566 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5567 break;
5568 case 0x0C:
5569 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5570 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5571 /* mullhwu - mullhwu. */
5572 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5573 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5574 break;
5575 }
5576 if (opc2 & 0x04) {
5577 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5578 tcg_gen_mul_tl(t1, t0, t1);
5579 if (opc2 & 0x02) {
5580 /* nmultiply-and-accumulate (0x0E) */
5581 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5582 } else {
5583 /* multiply-and-accumulate (0x0C) */
5584 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5585 }
5586
5587 if (opc3 & 0x12) {
5588 /* Check overflow and/or saturate */
5589 int l1 = gen_new_label();
5590
5591 if (opc3 & 0x10) {
5592 /* Start with XER OV disabled, the most likely case */
5593 tcg_gen_movi_tl(cpu_ov, 0);
5594 }
5595 if (opc3 & 0x01) {
5596 /* Signed */
5597 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5598 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5599 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5600 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5601 if (opc3 & 0x02) {
5602 /* Saturate */
5603 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5604 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5605 }
5606 } else {
5607 /* Unsigned */
5608 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5609 if (opc3 & 0x02) {
5610 /* Saturate */
5611 tcg_gen_movi_tl(t0, UINT32_MAX);
5612 }
5613 }
5614 if (opc3 & 0x10) {
5615 /* Check overflow */
5616 tcg_gen_movi_tl(cpu_ov, 1);
5617 tcg_gen_movi_tl(cpu_so, 1);
5618 }
5619 gen_set_label(l1);
5620 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5621 }
5622 } else {
5623 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5624 }
5625 tcg_temp_free(t0);
5626 tcg_temp_free(t1);
5627 if (unlikely(Rc) != 0) {
5628 /* Update Rc0 */
5629 gen_set_Rc0(ctx, cpu_gpr[rt]);
5630 }
5631 }
5632
5633 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5634 static void glue(gen_, name)(DisasContext *ctx) \
5635 { \
5636 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5637 rD(ctx->opcode), Rc(ctx->opcode)); \
5638 }
5639
5640 /* macchw - macchw. */
5641 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5642 /* macchwo - macchwo. */
5643 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5644 /* macchws - macchws. */
5645 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5646 /* macchwso - macchwso. */
5647 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5648 /* macchwsu - macchwsu. */
5649 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5650 /* macchwsuo - macchwsuo. */
5651 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5652 /* macchwu - macchwu. */
5653 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5654 /* macchwuo - macchwuo. */
5655 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5656 /* machhw - machhw. */
5657 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5658 /* machhwo - machhwo. */
5659 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5660 /* machhws - machhws. */
5661 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5662 /* machhwso - machhwso. */
5663 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5664 /* machhwsu - machhwsu. */
5665 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5666 /* machhwsuo - machhwsuo. */
5667 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5668 /* machhwu - machhwu. */
5669 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5670 /* machhwuo - machhwuo. */
5671 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5672 /* maclhw - maclhw. */
5673 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5674 /* maclhwo - maclhwo. */
5675 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5676 /* maclhws - maclhws. */
5677 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5678 /* maclhwso - maclhwso. */
5679 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5680 /* maclhwu - maclhwu. */
5681 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5682 /* maclhwuo - maclhwuo. */
5683 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5684 /* maclhwsu - maclhwsu. */
5685 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5686 /* maclhwsuo - maclhwsuo. */
5687 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5688 /* nmacchw - nmacchw. */
5689 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5690 /* nmacchwo - nmacchwo. */
5691 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5692 /* nmacchws - nmacchws. */
5693 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5694 /* nmacchwso - nmacchwso. */
5695 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5696 /* nmachhw - nmachhw. */
5697 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5698 /* nmachhwo - nmachhwo. */
5699 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5700 /* nmachhws - nmachhws. */
5701 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5702 /* nmachhwso - nmachhwso. */
5703 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5704 /* nmaclhw - nmaclhw. */
5705 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5706 /* nmaclhwo - nmaclhwo. */
5707 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5708 /* nmaclhws - nmaclhws. */
5709 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5710 /* nmaclhwso - nmaclhwso. */
5711 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5712
5713 /* mulchw - mulchw. */
5714 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5715 /* mulchwu - mulchwu. */
5716 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5717 /* mulhhw - mulhhw. */
5718 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5719 /* mulhhwu - mulhhwu. */
5720 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5721 /* mullhw - mullhw. */
5722 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5723 /* mullhwu - mullhwu. */
5724 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5725
5726 /* mfdcr */
5727 static void gen_mfdcr(DisasContext *ctx)
5728 {
5729 #if defined(CONFIG_USER_ONLY)
5730 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5731 #else
5732 TCGv dcrn;
5733 if (unlikely(!ctx->mem_idx)) {
5734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5735 return;
5736 }
5737 /* NIP cannot be restored if the memory exception comes from an helper */
5738 gen_update_nip(ctx, ctx->nip - 4);
5739 dcrn = tcg_const_tl(SPR(ctx->opcode));
5740 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5741 tcg_temp_free(dcrn);
5742 #endif
5743 }
5744
5745 /* mtdcr */
5746 static void gen_mtdcr(DisasContext *ctx)
5747 {
5748 #if defined(CONFIG_USER_ONLY)
5749 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5750 #else
5751 TCGv dcrn;
5752 if (unlikely(!ctx->mem_idx)) {
5753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5754 return;
5755 }
5756 /* NIP cannot be restored if the memory exception comes from an helper */
5757 gen_update_nip(ctx, ctx->nip - 4);
5758 dcrn = tcg_const_tl(SPR(ctx->opcode));
5759 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5760 tcg_temp_free(dcrn);
5761 #endif
5762 }
5763
5764 /* mfdcrx */
5765 /* XXX: not implemented on 440 ? */
5766 static void gen_mfdcrx(DisasContext *ctx)
5767 {
5768 #if defined(CONFIG_USER_ONLY)
5769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5770 #else
5771 if (unlikely(!ctx->mem_idx)) {
5772 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5773 return;
5774 }
5775 /* NIP cannot be restored if the memory exception comes from an helper */
5776 gen_update_nip(ctx, ctx->nip - 4);
5777 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5778 cpu_gpr[rA(ctx->opcode)]);
5779 /* Note: Rc update flag set leads to undefined state of Rc0 */
5780 #endif
5781 }
5782
5783 /* mtdcrx */
5784 /* XXX: not implemented on 440 ? */
5785 static void gen_mtdcrx(DisasContext *ctx)
5786 {
5787 #if defined(CONFIG_USER_ONLY)
5788 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5789 #else
5790 if (unlikely(!ctx->mem_idx)) {
5791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5792 return;
5793 }
5794 /* NIP cannot be restored if the memory exception comes from an helper */
5795 gen_update_nip(ctx, ctx->nip - 4);
5796 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5797 cpu_gpr[rS(ctx->opcode)]);
5798 /* Note: Rc update flag set leads to undefined state of Rc0 */
5799 #endif
5800 }
5801
5802 /* mfdcrux (PPC 460) : user-mode access to DCR */
5803 static void gen_mfdcrux(DisasContext *ctx)
5804 {
5805 /* NIP cannot be restored if the memory exception comes from an helper */
5806 gen_update_nip(ctx, ctx->nip - 4);
5807 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5808 cpu_gpr[rA(ctx->opcode)]);
5809 /* Note: Rc update flag set leads to undefined state of Rc0 */
5810 }
5811
5812 /* mtdcrux (PPC 460) : user-mode access to DCR */
5813 static void gen_mtdcrux(DisasContext *ctx)
5814 {
5815 /* NIP cannot be restored if the memory exception comes from an helper */
5816 gen_update_nip(ctx, ctx->nip - 4);
5817 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5818 cpu_gpr[rS(ctx->opcode)]);
5819 /* Note: Rc update flag set leads to undefined state of Rc0 */
5820 }
5821
5822 /* dccci */
5823 static void gen_dccci(DisasContext *ctx)
5824 {
5825 #if defined(CONFIG_USER_ONLY)
5826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5827 #else
5828 if (unlikely(!ctx->mem_idx)) {
5829 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5830 return;
5831 }
5832 /* interpreted as no-op */
5833 #endif
5834 }
5835
5836 /* dcread */
5837 static void gen_dcread(DisasContext *ctx)
5838 {
5839 #if defined(CONFIG_USER_ONLY)
5840 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5841 #else
5842 TCGv EA, val;
5843 if (unlikely(!ctx->mem_idx)) {
5844 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5845 return;
5846 }
5847 gen_set_access_type(ctx, ACCESS_CACHE);
5848 EA = tcg_temp_new();
5849 gen_addr_reg_index(ctx, EA);
5850 val = tcg_temp_new();
5851 gen_qemu_ld32u(ctx, val, EA);
5852 tcg_temp_free(val);
5853 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5854 tcg_temp_free(EA);
5855 #endif
5856 }
5857
5858 /* icbt */
5859 static void gen_icbt_40x(DisasContext *ctx)
5860 {
5861 /* interpreted as no-op */
5862 /* XXX: specification say this is treated as a load by the MMU
5863 * but does not generate any exception
5864 */
5865 }
5866
5867 /* iccci */
5868 static void gen_iccci(DisasContext *ctx)
5869 {
5870 #if defined(CONFIG_USER_ONLY)
5871 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5872 #else
5873 if (unlikely(!ctx->mem_idx)) {
5874 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5875 return;
5876 }
5877 /* interpreted as no-op */
5878 #endif
5879 }
5880
5881 /* icread */
5882 static void gen_icread(DisasContext *ctx)
5883 {
5884 #if defined(CONFIG_USER_ONLY)
5885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5886 #else
5887 if (unlikely(!ctx->mem_idx)) {
5888 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5889 return;
5890 }
5891 /* interpreted as no-op */
5892 #endif
5893 }
5894
5895 /* rfci (mem_idx only) */
5896 static void gen_rfci_40x(DisasContext *ctx)
5897 {
5898 #if defined(CONFIG_USER_ONLY)
5899 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5900 #else
5901 if (unlikely(!ctx->mem_idx)) {
5902 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5903 return;
5904 }
5905 /* Restore CPU state */
5906 gen_helper_40x_rfci(cpu_env);
5907 gen_sync_exception(ctx);
5908 #endif
5909 }
5910
5911 static void gen_rfci(DisasContext *ctx)
5912 {
5913 #if defined(CONFIG_USER_ONLY)
5914 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5915 #else
5916 if (unlikely(!ctx->mem_idx)) {
5917 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5918 return;
5919 }
5920 /* Restore CPU state */
5921 gen_helper_rfci(cpu_env);
5922 gen_sync_exception(ctx);
5923 #endif
5924 }
5925
5926 /* BookE specific */
5927
5928 /* XXX: not implemented on 440 ? */
5929 static void gen_rfdi(DisasContext *ctx)
5930 {
5931 #if defined(CONFIG_USER_ONLY)
5932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5933 #else
5934 if (unlikely(!ctx->mem_idx)) {
5935 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5936 return;
5937 }
5938 /* Restore CPU state */
5939 gen_helper_rfdi(cpu_env);
5940 gen_sync_exception(ctx);
5941 #endif
5942 }
5943
5944 /* XXX: not implemented on 440 ? */
5945 static void gen_rfmci(DisasContext *ctx)
5946 {
5947 #if defined(CONFIG_USER_ONLY)
5948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5949 #else
5950 if (unlikely(!ctx->mem_idx)) {
5951 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5952 return;
5953 }
5954 /* Restore CPU state */
5955 gen_helper_rfmci(cpu_env);
5956 gen_sync_exception(ctx);
5957 #endif
5958 }
5959
5960 /* TLB management - PowerPC 405 implementation */
5961
5962 /* tlbre */
5963 static void gen_tlbre_40x(DisasContext *ctx)
5964 {
5965 #if defined(CONFIG_USER_ONLY)
5966 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5967 #else
5968 if (unlikely(!ctx->mem_idx)) {
5969 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5970 return;
5971 }
5972 switch (rB(ctx->opcode)) {
5973 case 0:
5974 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5975 cpu_gpr[rA(ctx->opcode)]);
5976 break;
5977 case 1:
5978 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5979 cpu_gpr[rA(ctx->opcode)]);
5980 break;
5981 default:
5982 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5983 break;
5984 }
5985 #endif
5986 }
5987
5988 /* tlbsx - tlbsx. */
5989 static void gen_tlbsx_40x(DisasContext *ctx)
5990 {
5991 #if defined(CONFIG_USER_ONLY)
5992 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5993 #else
5994 TCGv t0;
5995 if (unlikely(!ctx->mem_idx)) {
5996 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5997 return;
5998 }
5999 t0 = tcg_temp_new();
6000 gen_addr_reg_index(ctx, t0);
6001 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6002 tcg_temp_free(t0);
6003 if (Rc(ctx->opcode)) {
6004 int l1 = gen_new_label();
6005 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6006 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6007 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6008 gen_set_label(l1);
6009 }
6010 #endif
6011 }
6012
6013 /* tlbwe */
6014 static void gen_tlbwe_40x(DisasContext *ctx)
6015 {
6016 #if defined(CONFIG_USER_ONLY)
6017 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6018 #else
6019 if (unlikely(!ctx->mem_idx)) {
6020 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6021 return;
6022 }
6023 switch (rB(ctx->opcode)) {
6024 case 0:
6025 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6026 cpu_gpr[rS(ctx->opcode)]);
6027 break;
6028 case 1:
6029 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6030 cpu_gpr[rS(ctx->opcode)]);
6031 break;
6032 default:
6033 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6034 break;
6035 }
6036 #endif
6037 }
6038
6039 /* TLB management - PowerPC 440 implementation */
6040
6041 /* tlbre */
6042 static void gen_tlbre_440(DisasContext *ctx)
6043 {
6044 #if defined(CONFIG_USER_ONLY)
6045 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6046 #else
6047 if (unlikely(!ctx->mem_idx)) {
6048 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6049 return;
6050 }
6051 switch (rB(ctx->opcode)) {
6052 case 0:
6053 case 1:
6054 case 2:
6055 {
6056 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6057 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6058 t0, cpu_gpr[rA(ctx->opcode)]);
6059 tcg_temp_free_i32(t0);
6060 }
6061 break;
6062 default:
6063 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6064 break;
6065 }
6066 #endif
6067 }
6068
6069 /* tlbsx - tlbsx. */
6070 static void gen_tlbsx_440(DisasContext *ctx)
6071 {
6072 #if defined(CONFIG_USER_ONLY)
6073 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6074 #else
6075 TCGv t0;
6076 if (unlikely(!ctx->mem_idx)) {
6077 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6078 return;
6079 }
6080 t0 = tcg_temp_new();
6081 gen_addr_reg_index(ctx, t0);
6082 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6083 tcg_temp_free(t0);
6084 if (Rc(ctx->opcode)) {
6085 int l1 = gen_new_label();
6086 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6087 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6088 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6089 gen_set_label(l1);
6090 }
6091 #endif
6092 }
6093
6094 /* tlbwe */
6095 static void gen_tlbwe_440(DisasContext *ctx)
6096 {
6097 #if defined(CONFIG_USER_ONLY)
6098 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6099 #else
6100 if (unlikely(!ctx->mem_idx)) {
6101 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6102 return;
6103 }
6104 switch (rB(ctx->opcode)) {
6105 case 0:
6106 case 1:
6107 case 2:
6108 {
6109 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6110 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6111 cpu_gpr[rS(ctx->opcode)]);
6112 tcg_temp_free_i32(t0);
6113 }
6114 break;
6115 default:
6116 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6117 break;
6118 }
6119 #endif
6120 }
6121
6122 /* TLB management - PowerPC BookE 2.06 implementation */
6123
6124 /* tlbre */
6125 static void gen_tlbre_booke206(DisasContext *ctx)
6126 {
6127 #if defined(CONFIG_USER_ONLY)
6128 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6129 #else
6130 if (unlikely(!ctx->mem_idx)) {
6131 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6132 return;
6133 }
6134
6135 gen_helper_booke206_tlbre(cpu_env);
6136 #endif
6137 }
6138
6139 /* tlbsx - tlbsx. */
6140 static void gen_tlbsx_booke206(DisasContext *ctx)
6141 {
6142 #if defined(CONFIG_USER_ONLY)
6143 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6144 #else
6145 TCGv t0;
6146 if (unlikely(!ctx->mem_idx)) {
6147 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6148 return;
6149 }
6150
6151 if (rA(ctx->opcode)) {
6152 t0 = tcg_temp_new();
6153 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6154 } else {
6155 t0 = tcg_const_tl(0);
6156 }
6157
6158 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6159 gen_helper_booke206_tlbsx(cpu_env, t0);
6160 #endif
6161 }
6162
6163 /* tlbwe */
6164 static void gen_tlbwe_booke206(DisasContext *ctx)
6165 {
6166 #if defined(CONFIG_USER_ONLY)
6167 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6168 #else
6169 if (unlikely(!ctx->mem_idx)) {
6170 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6171 return;
6172 }
6173 gen_update_nip(ctx, ctx->nip - 4);
6174 gen_helper_booke206_tlbwe(cpu_env);
6175 #endif
6176 }
6177
6178 static void gen_tlbivax_booke206(DisasContext *ctx)
6179 {
6180 #if defined(CONFIG_USER_ONLY)
6181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6182 #else
6183 TCGv t0;
6184 if (unlikely(!ctx->mem_idx)) {
6185 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6186 return;
6187 }
6188
6189 t0 = tcg_temp_new();
6190 gen_addr_reg_index(ctx, t0);
6191
6192 gen_helper_booke206_tlbivax(cpu_env, t0);
6193 #endif
6194 }
6195
6196 static void gen_tlbilx_booke206(DisasContext *ctx)
6197 {
6198 #if defined(CONFIG_USER_ONLY)
6199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6200 #else
6201 TCGv t0;
6202 if (unlikely(!ctx->mem_idx)) {
6203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6204 return;
6205 }
6206
6207 t0 = tcg_temp_new();
6208 gen_addr_reg_index(ctx, t0);
6209
6210 switch((ctx->opcode >> 21) & 0x3) {
6211 case 0:
6212 gen_helper_booke206_tlbilx0(cpu_env, t0);
6213 break;
6214 case 1:
6215 gen_helper_booke206_tlbilx1(cpu_env, t0);
6216 break;
6217 case 3:
6218 gen_helper_booke206_tlbilx3(cpu_env, t0);
6219 break;
6220 default:
6221 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6222 break;
6223 }
6224
6225 tcg_temp_free(t0);
6226 #endif
6227 }
6228
6229
6230 /* wrtee */
6231 static void gen_wrtee(DisasContext *ctx)
6232 {
6233 #if defined(CONFIG_USER_ONLY)
6234 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6235 #else
6236 TCGv t0;
6237 if (unlikely(!ctx->mem_idx)) {
6238 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6239 return;
6240 }
6241 t0 = tcg_temp_new();
6242 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6243 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6244 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6245 tcg_temp_free(t0);
6246 /* Stop translation to have a chance to raise an exception
6247 * if we just set msr_ee to 1
6248 */
6249 gen_stop_exception(ctx);
6250 #endif
6251 }
6252
6253 /* wrteei */
6254 static void gen_wrteei(DisasContext *ctx)
6255 {
6256 #if defined(CONFIG_USER_ONLY)
6257 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6258 #else
6259 if (unlikely(!ctx->mem_idx)) {
6260 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6261 return;
6262 }
6263 if (ctx->opcode & 0x00008000) {
6264 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6265 /* Stop translation to have a chance to raise an exception */
6266 gen_stop_exception(ctx);
6267 } else {
6268 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6269 }
6270 #endif
6271 }
6272
6273 /* PowerPC 440 specific instructions */
6274
6275 /* dlmzb */
6276 static void gen_dlmzb(DisasContext *ctx)
6277 {
6278 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6279 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6280 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6281 tcg_temp_free_i32(t0);
6282 }
6283
6284 /* mbar replaces eieio on 440 */
6285 static void gen_mbar(DisasContext *ctx)
6286 {
6287 /* interpreted as no-op */
6288 }
6289
6290 /* msync replaces sync on 440 */
6291 static void gen_msync_4xx(DisasContext *ctx)
6292 {
6293 /* interpreted as no-op */
6294 }
6295
6296 /* icbt */
6297 static void gen_icbt_440(DisasContext *ctx)
6298 {
6299 /* interpreted as no-op */
6300 /* XXX: specification say this is treated as a load by the MMU
6301 * but does not generate any exception
6302 */
6303 }
6304
6305 /* Embedded.Processor Control */
6306
6307 static void gen_msgclr(DisasContext *ctx)
6308 {
6309 #if defined(CONFIG_USER_ONLY)
6310 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6311 #else
6312 if (unlikely(ctx->mem_idx == 0)) {
6313 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6314 return;
6315 }
6316
6317 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6318 #endif
6319 }
6320
6321 static void gen_msgsnd(DisasContext *ctx)
6322 {
6323 #if defined(CONFIG_USER_ONLY)
6324 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6325 #else
6326 if (unlikely(ctx->mem_idx == 0)) {
6327 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6328 return;
6329 }
6330
6331 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6332 #endif
6333 }
6334
6335 /*** Altivec vector extension ***/
6336 /* Altivec registers moves */
6337
6338 static inline TCGv_ptr gen_avr_ptr(int reg)
6339 {
6340 TCGv_ptr r = tcg_temp_new_ptr();
6341 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6342 return r;
6343 }
6344
6345 #define GEN_VR_LDX(name, opc2, opc3) \
6346 static void glue(gen_, name)(DisasContext *ctx) \
6347 { \
6348 TCGv EA; \
6349 if (unlikely(!ctx->altivec_enabled)) { \
6350 gen_exception(ctx, POWERPC_EXCP_VPU); \
6351 return; \
6352 } \
6353 gen_set_access_type(ctx, ACCESS_INT); \
6354 EA = tcg_temp_new(); \
6355 gen_addr_reg_index(ctx, EA); \
6356 tcg_gen_andi_tl(EA, EA, ~0xf); \
6357 if (ctx->le_mode) { \
6358 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6359 tcg_gen_addi_tl(EA, EA, 8); \
6360 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6361 } else { \
6362 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6363 tcg_gen_addi_tl(EA, EA, 8); \
6364 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6365 } \
6366 tcg_temp_free(EA); \
6367 }
6368
6369 #define GEN_VR_STX(name, opc2, opc3) \
6370 static void gen_st##name(DisasContext *ctx) \
6371 { \
6372 TCGv EA; \
6373 if (unlikely(!ctx->altivec_enabled)) { \
6374 gen_exception(ctx, POWERPC_EXCP_VPU); \
6375 return; \
6376 } \
6377 gen_set_access_type(ctx, ACCESS_INT); \
6378 EA = tcg_temp_new(); \
6379 gen_addr_reg_index(ctx, EA); \
6380 tcg_gen_andi_tl(EA, EA, ~0xf); \
6381 if (ctx->le_mode) { \
6382 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6383 tcg_gen_addi_tl(EA, EA, 8); \
6384 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6385 } else { \
6386 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6387 tcg_gen_addi_tl(EA, EA, 8); \
6388 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6389 } \
6390 tcg_temp_free(EA); \
6391 }
6392
6393 #define GEN_VR_LVE(name, opc2, opc3) \
6394 static void gen_lve##name(DisasContext *ctx) \
6395 { \
6396 TCGv EA; \
6397 TCGv_ptr rs; \
6398 if (unlikely(!ctx->altivec_enabled)) { \
6399 gen_exception(ctx, POWERPC_EXCP_VPU); \
6400 return; \
6401 } \
6402 gen_set_access_type(ctx, ACCESS_INT); \
6403 EA = tcg_temp_new(); \
6404 gen_addr_reg_index(ctx, EA); \
6405 rs = gen_avr_ptr(rS(ctx->opcode)); \
6406 gen_helper_lve##name(cpu_env, rs, EA); \
6407 tcg_temp_free(EA); \
6408 tcg_temp_free_ptr(rs); \
6409 }
6410
6411 #define GEN_VR_STVE(name, opc2, opc3) \
6412 static void gen_stve##name(DisasContext *ctx) \
6413 { \
6414 TCGv EA; \
6415 TCGv_ptr rs; \
6416 if (unlikely(!ctx->altivec_enabled)) { \
6417 gen_exception(ctx, POWERPC_EXCP_VPU); \
6418 return; \
6419 } \
6420 gen_set_access_type(ctx, ACCESS_INT); \
6421 EA = tcg_temp_new(); \
6422 gen_addr_reg_index(ctx, EA); \
6423 rs = gen_avr_ptr(rS(ctx->opcode)); \
6424 gen_helper_stve##name(cpu_env, rs, EA); \
6425 tcg_temp_free(EA); \
6426 tcg_temp_free_ptr(rs); \
6427 }
6428
6429 GEN_VR_LDX(lvx, 0x07, 0x03);
6430 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6431 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6432
6433 GEN_VR_LVE(bx, 0x07, 0x00);
6434 GEN_VR_LVE(hx, 0x07, 0x01);
6435 GEN_VR_LVE(wx, 0x07, 0x02);
6436
6437 GEN_VR_STX(svx, 0x07, 0x07);
6438 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6439 GEN_VR_STX(svxl, 0x07, 0x0F);
6440
6441 GEN_VR_STVE(bx, 0x07, 0x04);
6442 GEN_VR_STVE(hx, 0x07, 0x05);
6443 GEN_VR_STVE(wx, 0x07, 0x06);
6444
6445 static void gen_lvsl(DisasContext *ctx)
6446 {
6447 TCGv_ptr rd;
6448 TCGv EA;
6449 if (unlikely(!ctx->altivec_enabled)) {
6450 gen_exception(ctx, POWERPC_EXCP_VPU);
6451 return;
6452 }
6453 EA = tcg_temp_new();
6454 gen_addr_reg_index(ctx, EA);
6455 rd = gen_avr_ptr(rD(ctx->opcode));
6456 gen_helper_lvsl(rd, EA);
6457 tcg_temp_free(EA);
6458 tcg_temp_free_ptr(rd);
6459 }
6460
6461 static void gen_lvsr(DisasContext *ctx)
6462 {
6463 TCGv_ptr rd;
6464 TCGv EA;
6465 if (unlikely(!ctx->altivec_enabled)) {
6466 gen_exception(ctx, POWERPC_EXCP_VPU);
6467 return;
6468 }
6469 EA = tcg_temp_new();
6470 gen_addr_reg_index(ctx, EA);
6471 rd = gen_avr_ptr(rD(ctx->opcode));
6472 gen_helper_lvsr(rd, EA);
6473 tcg_temp_free(EA);
6474 tcg_temp_free_ptr(rd);
6475 }
6476
6477 static void gen_mfvscr(DisasContext *ctx)
6478 {
6479 TCGv_i32 t;
6480 if (unlikely(!ctx->altivec_enabled)) {
6481 gen_exception(ctx, POWERPC_EXCP_VPU);
6482 return;
6483 }
6484 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6485 t = tcg_temp_new_i32();
6486 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6487 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6488 tcg_temp_free_i32(t);
6489 }
6490
6491 static void gen_mtvscr(DisasContext *ctx)
6492 {
6493 TCGv_ptr p;
6494 if (unlikely(!ctx->altivec_enabled)) {
6495 gen_exception(ctx, POWERPC_EXCP_VPU);
6496 return;
6497 }
6498 p = gen_avr_ptr(rD(ctx->opcode));
6499 gen_helper_mtvscr(cpu_env, p);
6500 tcg_temp_free_ptr(p);
6501 }
6502
6503 /* Logical operations */
6504 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6505 static void glue(gen_, name)(DisasContext *ctx) \
6506 { \
6507 if (unlikely(!ctx->altivec_enabled)) { \
6508 gen_exception(ctx, POWERPC_EXCP_VPU); \
6509 return; \
6510 } \
6511 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6512 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6513 }
6514
6515 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6516 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6517 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6518 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6519 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6520
6521 #define GEN_VXFORM(name, opc2, opc3) \
6522 static void glue(gen_, name)(DisasContext *ctx) \
6523 { \
6524 TCGv_ptr ra, rb, rd; \
6525 if (unlikely(!ctx->altivec_enabled)) { \
6526 gen_exception(ctx, POWERPC_EXCP_VPU); \
6527 return; \
6528 } \
6529 ra = gen_avr_ptr(rA(ctx->opcode)); \
6530 rb = gen_avr_ptr(rB(ctx->opcode)); \
6531 rd = gen_avr_ptr(rD(ctx->opcode)); \
6532 gen_helper_##name (rd, ra, rb); \
6533 tcg_temp_free_ptr(ra); \
6534 tcg_temp_free_ptr(rb); \
6535 tcg_temp_free_ptr(rd); \
6536 }
6537
6538 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6539 static void glue(gen_, name)(DisasContext *ctx) \
6540 { \
6541 TCGv_ptr ra, rb, rd; \
6542 if (unlikely(!ctx->altivec_enabled)) { \
6543 gen_exception(ctx, POWERPC_EXCP_VPU); \
6544 return; \
6545 } \
6546 ra = gen_avr_ptr(rA(ctx->opcode)); \
6547 rb = gen_avr_ptr(rB(ctx->opcode)); \
6548 rd = gen_avr_ptr(rD(ctx->opcode)); \
6549 gen_helper_##name(cpu_env, rd, ra, rb); \
6550 tcg_temp_free_ptr(ra); \
6551 tcg_temp_free_ptr(rb); \
6552 tcg_temp_free_ptr(rd); \
6553 }
6554
6555 GEN_VXFORM(vaddubm, 0, 0);
6556 GEN_VXFORM(vadduhm, 0, 1);
6557 GEN_VXFORM(vadduwm, 0, 2);
6558 GEN_VXFORM(vsububm, 0, 16);
6559 GEN_VXFORM(vsubuhm, 0, 17);
6560 GEN_VXFORM(vsubuwm, 0, 18);
6561 GEN_VXFORM(vmaxub, 1, 0);
6562 GEN_VXFORM(vmaxuh, 1, 1);
6563 GEN_VXFORM(vmaxuw, 1, 2);
6564 GEN_VXFORM(vmaxsb, 1, 4);
6565 GEN_VXFORM(vmaxsh, 1, 5);
6566 GEN_VXFORM(vmaxsw, 1, 6);
6567 GEN_VXFORM(vminub, 1, 8);
6568 GEN_VXFORM(vminuh, 1, 9);
6569 GEN_VXFORM(vminuw, 1, 10);
6570 GEN_VXFORM(vminsb, 1, 12);
6571 GEN_VXFORM(vminsh, 1, 13);
6572 GEN_VXFORM(vminsw, 1, 14);
6573 GEN_VXFORM(vavgub, 1, 16);
6574 GEN_VXFORM(vavguh, 1, 17);
6575 GEN_VXFORM(vavguw, 1, 18);
6576 GEN_VXFORM(vavgsb, 1, 20);
6577 GEN_VXFORM(vavgsh, 1, 21);
6578 GEN_VXFORM(vavgsw, 1, 22);
6579 GEN_VXFORM(vmrghb, 6, 0);
6580 GEN_VXFORM(vmrghh, 6, 1);
6581 GEN_VXFORM(vmrghw, 6, 2);
6582 GEN_VXFORM(vmrglb, 6, 4);
6583 GEN_VXFORM(vmrglh, 6, 5);
6584 GEN_VXFORM(vmrglw, 6, 6);
6585 GEN_VXFORM(vmuloub, 4, 0);
6586 GEN_VXFORM(vmulouh, 4, 1);
6587 GEN_VXFORM(vmulosb, 4, 4);
6588 GEN_VXFORM(vmulosh, 4, 5);
6589 GEN_VXFORM(vmuleub, 4, 8);
6590 GEN_VXFORM(vmuleuh, 4, 9);
6591 GEN_VXFORM(vmulesb, 4, 12);
6592 GEN_VXFORM(vmulesh, 4, 13);
6593 GEN_VXFORM(vslb, 2, 4);
6594 GEN_VXFORM(vslh, 2, 5);
6595 GEN_VXFORM(vslw, 2, 6);
6596 GEN_VXFORM(vsrb, 2, 8);
6597 GEN_VXFORM(vsrh, 2, 9);
6598 GEN_VXFORM(vsrw, 2, 10);
6599 GEN_VXFORM(vsrab, 2, 12);
6600 GEN_VXFORM(vsrah, 2, 13);
6601 GEN_VXFORM(vsraw, 2, 14);
6602 GEN_VXFORM(vslo, 6, 16);
6603 GEN_VXFORM(vsro, 6, 17);
6604 GEN_VXFORM(vaddcuw, 0, 6);
6605 GEN_VXFORM(vsubcuw, 0, 22);
6606 GEN_VXFORM_ENV(vaddubs, 0, 8);
6607 GEN_VXFORM_ENV(vadduhs, 0, 9);
6608 GEN_VXFORM_ENV(vadduws, 0, 10);
6609 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6610 GEN_VXFORM_ENV(vaddshs, 0, 13);
6611 GEN_VXFORM_ENV(vaddsws, 0, 14);
6612 GEN_VXFORM_ENV(vsububs, 0, 24);
6613 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6614 GEN_VXFORM_ENV(vsubuws, 0, 26);
6615 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6616 GEN_VXFORM_ENV(vsubshs, 0, 29);
6617 GEN_VXFORM_ENV(vsubsws, 0, 30);
6618 GEN_VXFORM(vrlb, 2, 0);
6619 GEN_VXFORM(vrlh, 2, 1);
6620 GEN_VXFORM(vrlw, 2, 2);
6621 GEN_VXFORM(vsl, 2, 7);
6622 GEN_VXFORM(vsr, 2, 11);
6623 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6624 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6625 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6626 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6627 GEN_VXFORM_ENV(vpkshus, 7, 4);
6628 GEN_VXFORM_ENV(vpkswus, 7, 5);
6629 GEN_VXFORM_ENV(vpkshss, 7, 6);
6630 GEN_VXFORM_ENV(vpkswss, 7, 7);
6631 GEN_VXFORM(vpkpx, 7, 12);
6632 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6633 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6634 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6635 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6636 GEN_VXFORM_ENV(vsumsws, 4, 30);
6637 GEN_VXFORM_ENV(vaddfp, 5, 0);
6638 GEN_VXFORM_ENV(vsubfp, 5, 1);
6639 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6640 GEN_VXFORM_ENV(vminfp, 5, 17);
6641
6642 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6643 static void glue(gen_, name)(DisasContext *ctx) \
6644 { \
6645 TCGv_ptr ra, rb, rd; \
6646 if (unlikely(!ctx->altivec_enabled)) { \
6647 gen_exception(ctx, POWERPC_EXCP_VPU); \
6648 return; \
6649 } \
6650 ra = gen_avr_ptr(rA(ctx->opcode)); \
6651 rb = gen_avr_ptr(rB(ctx->opcode)); \
6652 rd = gen_avr_ptr(rD(ctx->opcode)); \
6653 gen_helper_##opname(cpu_env, rd, ra, rb); \
6654 tcg_temp_free_ptr(ra); \
6655 tcg_temp_free_ptr(rb); \
6656 tcg_temp_free_ptr(rd); \
6657 }
6658
6659 #define GEN_VXRFORM(name, opc2, opc3) \
6660 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6661 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6662
6663 GEN_VXRFORM(vcmpequb, 3, 0)
6664 GEN_VXRFORM(vcmpequh, 3, 1)
6665 GEN_VXRFORM(vcmpequw, 3, 2)
6666 GEN_VXRFORM(vcmpgtsb, 3, 12)
6667 GEN_VXRFORM(vcmpgtsh, 3, 13)
6668 GEN_VXRFORM(vcmpgtsw, 3, 14)
6669 GEN_VXRFORM(vcmpgtub, 3, 8)
6670 GEN_VXRFORM(vcmpgtuh, 3, 9)
6671 GEN_VXRFORM(vcmpgtuw, 3, 10)
6672 GEN_VXRFORM(vcmpeqfp, 3, 3)
6673 GEN_VXRFORM(vcmpgefp, 3, 7)
6674 GEN_VXRFORM(vcmpgtfp, 3, 11)
6675 GEN_VXRFORM(vcmpbfp, 3, 15)
6676
6677 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6678 static void glue(gen_, name)(DisasContext *ctx) \
6679 { \
6680 TCGv_ptr rd; \
6681 TCGv_i32 simm; \
6682 if (unlikely(!ctx->altivec_enabled)) { \
6683 gen_exception(ctx, POWERPC_EXCP_VPU); \
6684 return; \
6685 } \
6686 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6687 rd = gen_avr_ptr(rD(ctx->opcode)); \
6688 gen_helper_##name (rd, simm); \
6689 tcg_temp_free_i32(simm); \
6690 tcg_temp_free_ptr(rd); \
6691 }
6692
6693 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6694 GEN_VXFORM_SIMM(vspltish, 6, 13);
6695 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6696
6697 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6698 static void glue(gen_, name)(DisasContext *ctx) \
6699 { \
6700 TCGv_ptr rb, rd; \
6701 if (unlikely(!ctx->altivec_enabled)) { \
6702 gen_exception(ctx, POWERPC_EXCP_VPU); \
6703 return; \
6704 } \
6705 rb = gen_avr_ptr(rB(ctx->opcode)); \
6706 rd = gen_avr_ptr(rD(ctx->opcode)); \
6707 gen_helper_##name (rd, rb); \
6708 tcg_temp_free_ptr(rb); \
6709 tcg_temp_free_ptr(rd); \
6710 }
6711
6712 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6713 static void glue(gen_, name)(DisasContext *ctx) \
6714 { \
6715 TCGv_ptr rb, rd; \
6716 \
6717 if (unlikely(!ctx->altivec_enabled)) { \
6718 gen_exception(ctx, POWERPC_EXCP_VPU); \
6719 return; \
6720 } \
6721 rb = gen_avr_ptr(rB(ctx->opcode)); \
6722 rd = gen_avr_ptr(rD(ctx->opcode)); \
6723 gen_helper_##name(cpu_env, rd, rb); \
6724 tcg_temp_free_ptr(rb); \
6725 tcg_temp_free_ptr(rd); \
6726 }
6727
6728 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6729 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6730 GEN_VXFORM_NOA(vupklsb, 7, 10);
6731 GEN_VXFORM_NOA(vupklsh, 7, 11);
6732 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6733 GEN_VXFORM_NOA(vupklpx, 7, 15);
6734 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6735 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6736 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6737 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6738 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6739 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6740 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6741 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6742
6743 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6744 static void glue(gen_, name)(DisasContext *ctx) \
6745 { \
6746 TCGv_ptr rd; \
6747 TCGv_i32 simm; \
6748 if (unlikely(!ctx->altivec_enabled)) { \
6749 gen_exception(ctx, POWERPC_EXCP_VPU); \
6750 return; \
6751 } \
6752 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6753 rd = gen_avr_ptr(rD(ctx->opcode)); \
6754 gen_helper_##name (rd, simm); \
6755 tcg_temp_free_i32(simm); \
6756 tcg_temp_free_ptr(rd); \
6757 }
6758
6759 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6760 static void glue(gen_, name)(DisasContext *ctx) \
6761 { \
6762 TCGv_ptr rb, rd; \
6763 TCGv_i32 uimm; \
6764 if (unlikely(!ctx->altivec_enabled)) { \
6765 gen_exception(ctx, POWERPC_EXCP_VPU); \
6766 return; \
6767 } \
6768 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6769 rb = gen_avr_ptr(rB(ctx->opcode)); \
6770 rd = gen_avr_ptr(rD(ctx->opcode)); \
6771 gen_helper_##name (rd, rb, uimm); \
6772 tcg_temp_free_i32(uimm); \
6773 tcg_temp_free_ptr(rb); \
6774 tcg_temp_free_ptr(rd); \
6775 }
6776
6777 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6778 static void glue(gen_, name)(DisasContext *ctx) \
6779 { \
6780 TCGv_ptr rb, rd; \
6781 TCGv_i32 uimm; \
6782 \
6783 if (unlikely(!ctx->altivec_enabled)) { \
6784 gen_exception(ctx, POWERPC_EXCP_VPU); \
6785 return; \
6786 } \
6787 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6788 rb = gen_avr_ptr(rB(ctx->opcode)); \
6789 rd = gen_avr_ptr(rD(ctx->opcode)); \
6790 gen_helper_##name(cpu_env, rd, rb, uimm); \
6791 tcg_temp_free_i32(uimm); \
6792 tcg_temp_free_ptr(rb); \
6793 tcg_temp_free_ptr(rd); \
6794 }
6795
6796 GEN_VXFORM_UIMM(vspltb, 6, 8);
6797 GEN_VXFORM_UIMM(vsplth, 6, 9);
6798 GEN_VXFORM_UIMM(vspltw, 6, 10);
6799 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6800 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6801 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6802 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6803
6804 static void gen_vsldoi(DisasContext *ctx)
6805 {
6806 TCGv_ptr ra, rb, rd;
6807 TCGv_i32 sh;
6808 if (unlikely(!ctx->altivec_enabled)) {
6809 gen_exception(ctx, POWERPC_EXCP_VPU);
6810 return;
6811 }
6812 ra = gen_avr_ptr(rA(ctx->opcode));
6813 rb = gen_avr_ptr(rB(ctx->opcode));
6814 rd = gen_avr_ptr(rD(ctx->opcode));
6815 sh = tcg_const_i32(VSH(ctx->opcode));
6816 gen_helper_vsldoi (rd, ra, rb, sh);
6817 tcg_temp_free_ptr(ra);
6818 tcg_temp_free_ptr(rb);
6819 tcg_temp_free_ptr(rd);
6820 tcg_temp_free_i32(sh);
6821 }
6822
6823 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6824 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6825 { \
6826 TCGv_ptr ra, rb, rc, rd; \
6827 if (unlikely(!ctx->altivec_enabled)) { \
6828 gen_exception(ctx, POWERPC_EXCP_VPU); \
6829 return; \
6830 } \
6831 ra = gen_avr_ptr(rA(ctx->opcode)); \
6832 rb = gen_avr_ptr(rB(ctx->opcode)); \
6833 rc = gen_avr_ptr(rC(ctx->opcode)); \
6834 rd = gen_avr_ptr(rD(ctx->opcode)); \
6835 if (Rc(ctx->opcode)) { \
6836 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6837 } else { \
6838 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6839 } \
6840 tcg_temp_free_ptr(ra); \
6841 tcg_temp_free_ptr(rb); \
6842 tcg_temp_free_ptr(rc); \
6843 tcg_temp_free_ptr(rd); \
6844 }
6845
6846 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6847
6848 static void gen_vmladduhm(DisasContext *ctx)
6849 {
6850 TCGv_ptr ra, rb, rc, rd;
6851 if (unlikely(!ctx->altivec_enabled)) {
6852 gen_exception(ctx, POWERPC_EXCP_VPU);
6853 return;
6854 }
6855 ra = gen_avr_ptr(rA(ctx->opcode));
6856 rb = gen_avr_ptr(rB(ctx->opcode));
6857 rc = gen_avr_ptr(rC(ctx->opcode));
6858 rd = gen_avr_ptr(rD(ctx->opcode));
6859 gen_helper_vmladduhm(rd, ra, rb, rc);
6860 tcg_temp_free_ptr(ra);
6861 tcg_temp_free_ptr(rb);
6862 tcg_temp_free_ptr(rc);
6863 tcg_temp_free_ptr(rd);
6864 }
6865
6866 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6867 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6868 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6869 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6870 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6871
6872 /*** SPE extension ***/
6873 /* Register moves */
6874
6875
6876 static inline void gen_evmra(DisasContext *ctx)
6877 {
6878
6879 if (unlikely(!ctx->spe_enabled)) {
6880 gen_exception(ctx, POWERPC_EXCP_SPEU);
6881 return;
6882 }
6883
6884 #if defined(TARGET_PPC64)
6885 /* rD := rA */
6886 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6887
6888 /* spe_acc := rA */
6889 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6890 cpu_env,
6891 offsetof(CPUPPCState, spe_acc));
6892 #else
6893 TCGv_i64 tmp = tcg_temp_new_i64();
6894
6895 /* tmp := rA_lo + rA_hi << 32 */
6896 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6897
6898 /* spe_acc := tmp */
6899 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6900 tcg_temp_free_i64(tmp);
6901
6902 /* rD := rA */
6903 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6904 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6905 #endif
6906 }
6907
6908 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6909 {
6910 #if defined(TARGET_PPC64)
6911 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6912 #else
6913 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6914 #endif
6915 }
6916
6917 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6918 {
6919 #if defined(TARGET_PPC64)
6920 tcg_gen_mov_i64(cpu_gpr[reg], t);
6921 #else
6922 TCGv_i64 tmp = tcg_temp_new_i64();
6923 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6924 tcg_gen_shri_i64(tmp, t, 32);
6925 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6926 tcg_temp_free_i64(tmp);
6927 #endif
6928 }
6929
6930 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6931 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6932 { \
6933 if (Rc(ctx->opcode)) \
6934 gen_##name1(ctx); \
6935 else \
6936 gen_##name0(ctx); \
6937 }
6938
6939 /* Handler for undefined SPE opcodes */
6940 static inline void gen_speundef(DisasContext *ctx)
6941 {
6942 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6943 }
6944
6945 /* SPE logic */
6946 #if defined(TARGET_PPC64)
6947 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6948 static inline void gen_##name(DisasContext *ctx) \
6949 { \
6950 if (unlikely(!ctx->spe_enabled)) { \
6951 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6952 return; \
6953 } \
6954 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6955 cpu_gpr[rB(ctx->opcode)]); \
6956 }
6957 #else
6958 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6959 static inline void gen_##name(DisasContext *ctx) \
6960 { \
6961 if (unlikely(!ctx->spe_enabled)) { \
6962 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6963 return; \
6964 } \
6965 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6966 cpu_gpr[rB(ctx->opcode)]); \
6967 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6968 cpu_gprh[rB(ctx->opcode)]); \
6969 }
6970 #endif
6971
6972 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6973 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6974 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6975 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6976 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6977 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6978 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6979 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6980
6981 /* SPE logic immediate */
6982 #if defined(TARGET_PPC64)
6983 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6984 static inline void gen_##name(DisasContext *ctx) \
6985 { \
6986 if (unlikely(!ctx->spe_enabled)) { \
6987 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6988 return; \
6989 } \
6990 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6991 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6992 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6993 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6994 tcg_opi(t0, t0, rB(ctx->opcode)); \
6995 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6996 tcg_gen_trunc_i64_i32(t1, t2); \
6997 tcg_temp_free_i64(t2); \
6998 tcg_opi(t1, t1, rB(ctx->opcode)); \
6999 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7000 tcg_temp_free_i32(t0); \
7001 tcg_temp_free_i32(t1); \
7002 }
7003 #else
7004 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7005 static inline void gen_##name(DisasContext *ctx) \
7006 { \
7007 if (unlikely(!ctx->spe_enabled)) { \
7008 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7009 return; \
7010 } \
7011 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7012 rB(ctx->opcode)); \
7013 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7014 rB(ctx->opcode)); \
7015 }
7016 #endif
7017 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
7018 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
7019 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
7020 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
7021
7022 /* SPE arithmetic */
7023 #if defined(TARGET_PPC64)
7024 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7025 static inline void gen_##name(DisasContext *ctx) \
7026 { \
7027 if (unlikely(!ctx->spe_enabled)) { \
7028 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7029 return; \
7030 } \
7031 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7032 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7033 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7034 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7035 tcg_op(t0, t0); \
7036 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7037 tcg_gen_trunc_i64_i32(t1, t2); \
7038 tcg_temp_free_i64(t2); \
7039 tcg_op(t1, t1); \
7040 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7041 tcg_temp_free_i32(t0); \
7042 tcg_temp_free_i32(t1); \
7043 }
7044 #else
7045 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7046 static inline void gen_##name(DisasContext *ctx) \
7047 { \
7048 if (unlikely(!ctx->spe_enabled)) { \
7049 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7050 return; \
7051 } \
7052 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7053 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7054 }
7055 #endif
7056
7057 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
7058 {
7059 int l1 = gen_new_label();
7060 int l2 = gen_new_label();
7061
7062 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
7063 tcg_gen_neg_i32(ret, arg1);
7064 tcg_gen_br(l2);
7065 gen_set_label(l1);
7066 tcg_gen_mov_i32(ret, arg1);
7067 gen_set_label(l2);
7068 }
7069 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7070 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7071 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7072 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7073 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7074 {
7075 tcg_gen_addi_i32(ret, arg1, 0x8000);
7076 tcg_gen_ext16u_i32(ret, ret);
7077 }
7078 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7079 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7080 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7081
7082 #if defined(TARGET_PPC64)
7083 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7084 static inline void gen_##name(DisasContext *ctx) \
7085 { \
7086 if (unlikely(!ctx->spe_enabled)) { \
7087 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7088 return; \
7089 } \
7090 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7091 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7092 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7093 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7094 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7095 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7096 tcg_op(t0, t0, t2); \
7097 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7098 tcg_gen_trunc_i64_i32(t1, t3); \
7099 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7100 tcg_gen_trunc_i64_i32(t2, t3); \
7101 tcg_temp_free_i64(t3); \
7102 tcg_op(t1, t1, t2); \
7103 tcg_temp_free_i32(t2); \
7104 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7105 tcg_temp_free_i32(t0); \
7106 tcg_temp_free_i32(t1); \
7107 }
7108 #else
7109 #define GEN_SPEOP_ARITH2(name, tcg_op) \
7110 static inline void gen_##name(DisasContext *ctx) \
7111 { \
7112 if (unlikely(!ctx->spe_enabled)) { \
7113 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7114 return; \
7115 } \
7116 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7117 cpu_gpr[rB(ctx->opcode)]); \
7118 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7119 cpu_gprh[rB(ctx->opcode)]); \
7120 }
7121 #endif
7122
7123 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7124 {
7125 TCGv_i32 t0;
7126 int l1, l2;
7127
7128 l1 = gen_new_label();
7129 l2 = gen_new_label();
7130 t0 = tcg_temp_local_new_i32();
7131 /* No error here: 6 bits are used */
7132 tcg_gen_andi_i32(t0, arg2, 0x3F);
7133 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7134 tcg_gen_shr_i32(ret, arg1, t0);
7135 tcg_gen_br(l2);
7136 gen_set_label(l1);
7137 tcg_gen_movi_i32(ret, 0);
7138 gen_set_label(l2);
7139 tcg_temp_free_i32(t0);
7140 }
7141 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7142 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7143 {
7144 TCGv_i32 t0;
7145 int l1, l2;
7146
7147 l1 = gen_new_label();
7148 l2 = gen_new_label();
7149 t0 = tcg_temp_local_new_i32();
7150 /* No error here: 6 bits are used */
7151 tcg_gen_andi_i32(t0, arg2, 0x3F);
7152 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7153 tcg_gen_sar_i32(ret, arg1, t0);
7154 tcg_gen_br(l2);
7155 gen_set_label(l1);
7156 tcg_gen_movi_i32(ret, 0);
7157 gen_set_label(l2);
7158 tcg_temp_free_i32(t0);
7159 }
7160 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7161 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7162 {
7163 TCGv_i32 t0;
7164 int l1, l2;
7165
7166 l1 = gen_new_label();
7167 l2 = gen_new_label();
7168 t0 = tcg_temp_local_new_i32();
7169 /* No error here: 6 bits are used */
7170 tcg_gen_andi_i32(t0, arg2, 0x3F);
7171 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7172 tcg_gen_shl_i32(ret, arg1, t0);
7173 tcg_gen_br(l2);
7174 gen_set_label(l1);
7175 tcg_gen_movi_i32(ret, 0);
7176 gen_set_label(l2);
7177 tcg_temp_free_i32(t0);
7178 }
7179 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7180 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7181 {
7182 TCGv_i32 t0 = tcg_temp_new_i32();
7183 tcg_gen_andi_i32(t0, arg2, 0x1F);
7184 tcg_gen_rotl_i32(ret, arg1, t0);
7185 tcg_temp_free_i32(t0);
7186 }
7187 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7188 static inline void gen_evmergehi(DisasContext *ctx)
7189 {
7190 if (unlikely(!ctx->spe_enabled)) {
7191 gen_exception(ctx, POWERPC_EXCP_SPEU);
7192 return;
7193 }
7194 #if defined(TARGET_PPC64)
7195 TCGv t0 = tcg_temp_new();
7196 TCGv t1 = tcg_temp_new();
7197 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7198 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7199 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7200 tcg_temp_free(t0);
7201 tcg_temp_free(t1);
7202 #else
7203 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7204 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7205 #endif
7206 }
7207 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7208 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7209 {
7210 tcg_gen_sub_i32(ret, arg2, arg1);
7211 }
7212 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7213
7214 /* SPE arithmetic immediate */
7215 #if defined(TARGET_PPC64)
7216 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7217 static inline void gen_##name(DisasContext *ctx) \
7218 { \
7219 if (unlikely(!ctx->spe_enabled)) { \
7220 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7221 return; \
7222 } \
7223 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7224 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7225 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7226 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7227 tcg_op(t0, t0, rA(ctx->opcode)); \
7228 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7229 tcg_gen_trunc_i64_i32(t1, t2); \
7230 tcg_temp_free_i64(t2); \
7231 tcg_op(t1, t1, rA(ctx->opcode)); \
7232 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7233 tcg_temp_free_i32(t0); \
7234 tcg_temp_free_i32(t1); \
7235 }
7236 #else
7237 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7238 static inline void gen_##name(DisasContext *ctx) \
7239 { \
7240 if (unlikely(!ctx->spe_enabled)) { \
7241 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7242 return; \
7243 } \
7244 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7245 rA(ctx->opcode)); \
7246 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7247 rA(ctx->opcode)); \
7248 }
7249 #endif
7250 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7251 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7252
7253 /* SPE comparison */
7254 #if defined(TARGET_PPC64)
7255 #define GEN_SPEOP_COMP(name, tcg_cond) \
7256 static inline void gen_##name(DisasContext *ctx) \
7257 { \
7258 if (unlikely(!ctx->spe_enabled)) { \
7259 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7260 return; \
7261 } \
7262 int l1 = gen_new_label(); \
7263 int l2 = gen_new_label(); \
7264 int l3 = gen_new_label(); \
7265 int l4 = gen_new_label(); \
7266 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7267 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7268 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7269 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7270 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7271 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7272 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7273 tcg_gen_br(l2); \
7274 gen_set_label(l1); \
7275 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7276 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7277 gen_set_label(l2); \
7278 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7279 tcg_gen_trunc_i64_i32(t0, t2); \
7280 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7281 tcg_gen_trunc_i64_i32(t1, t2); \
7282 tcg_temp_free_i64(t2); \
7283 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7284 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7285 ~(CRF_CH | CRF_CH_AND_CL)); \
7286 tcg_gen_br(l4); \
7287 gen_set_label(l3); \
7288 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7289 CRF_CH | CRF_CH_OR_CL); \
7290 gen_set_label(l4); \
7291 tcg_temp_free_i32(t0); \
7292 tcg_temp_free_i32(t1); \
7293 }
7294 #else
7295 #define GEN_SPEOP_COMP(name, tcg_cond) \
7296 static inline void gen_##name(DisasContext *ctx) \
7297 { \
7298 if (unlikely(!ctx->spe_enabled)) { \
7299 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7300 return; \
7301 } \
7302 int l1 = gen_new_label(); \
7303 int l2 = gen_new_label(); \
7304 int l3 = gen_new_label(); \
7305 int l4 = gen_new_label(); \
7306 \
7307 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7308 cpu_gpr[rB(ctx->opcode)], l1); \
7309 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7310 tcg_gen_br(l2); \
7311 gen_set_label(l1); \
7312 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7313 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7314 gen_set_label(l2); \
7315 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7316 cpu_gprh[rB(ctx->opcode)], l3); \
7317 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7318 ~(CRF_CH | CRF_CH_AND_CL)); \
7319 tcg_gen_br(l4); \
7320 gen_set_label(l3); \
7321 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7322 CRF_CH | CRF_CH_OR_CL); \
7323 gen_set_label(l4); \
7324 }
7325 #endif
7326 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7327 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7328 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7329 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7330 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7331
7332 /* SPE misc */
7333 static inline void gen_brinc(DisasContext *ctx)
7334 {
7335 /* Note: brinc is usable even if SPE is disabled */
7336 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7337 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7338 }
7339 static inline void gen_evmergelo(DisasContext *ctx)
7340 {
7341 if (unlikely(!ctx->spe_enabled)) {
7342 gen_exception(ctx, POWERPC_EXCP_SPEU);
7343 return;
7344 }
7345 #if defined(TARGET_PPC64)
7346 TCGv t0 = tcg_temp_new();
7347 TCGv t1 = tcg_temp_new();
7348 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7349 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7350 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7351 tcg_temp_free(t0);
7352 tcg_temp_free(t1);
7353 #else
7354 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7355 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7356 #endif
7357 }
7358 static inline void gen_evmergehilo(DisasContext *ctx)
7359 {
7360 if (unlikely(!ctx->spe_enabled)) {
7361 gen_exception(ctx, POWERPC_EXCP_SPEU);
7362 return;
7363 }
7364 #if defined(TARGET_PPC64)
7365 TCGv t0 = tcg_temp_new();
7366 TCGv t1 = tcg_temp_new();
7367 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7368 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7369 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7370 tcg_temp_free(t0);
7371 tcg_temp_free(t1);
7372 #else
7373 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7374 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7375 #endif
7376 }
7377 static inline void gen_evmergelohi(DisasContext *ctx)
7378 {
7379 if (unlikely(!ctx->spe_enabled)) {
7380 gen_exception(ctx, POWERPC_EXCP_SPEU);
7381 return;
7382 }
7383 #if defined(TARGET_PPC64)
7384 TCGv t0 = tcg_temp_new();
7385 TCGv t1 = tcg_temp_new();
7386 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7387 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7388 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7389 tcg_temp_free(t0);
7390 tcg_temp_free(t1);
7391 #else
7392 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7393 TCGv_i32 tmp = tcg_temp_new_i32();
7394 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7395 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7396 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7397 tcg_temp_free_i32(tmp);
7398 } else {
7399 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7400 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7401 }
7402 #endif
7403 }
7404 static inline void gen_evsplati(DisasContext *ctx)
7405 {
7406 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7407
7408 #if defined(TARGET_PPC64)
7409 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7410 #else
7411 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7412 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7413 #endif
7414 }
7415 static inline void gen_evsplatfi(DisasContext *ctx)
7416 {
7417 uint64_t imm = rA(ctx->opcode) << 27;
7418
7419 #if defined(TARGET_PPC64)
7420 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7421 #else
7422 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7423 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7424 #endif
7425 }
7426
7427 static inline void gen_evsel(DisasContext *ctx)
7428 {
7429 int l1 = gen_new_label();
7430 int l2 = gen_new_label();
7431 int l3 = gen_new_label();
7432 int l4 = gen_new_label();
7433 TCGv_i32 t0 = tcg_temp_local_new_i32();
7434 #if defined(TARGET_PPC64)
7435 TCGv t1 = tcg_temp_local_new();
7436 TCGv t2 = tcg_temp_local_new();
7437 #endif
7438 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7439 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7440 #if defined(TARGET_PPC64)
7441 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7442 #else
7443 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7444 #endif
7445 tcg_gen_br(l2);
7446 gen_set_label(l1);
7447 #if defined(TARGET_PPC64)
7448 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7449 #else
7450 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7451 #endif
7452 gen_set_label(l2);
7453 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7454 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7455 #if defined(TARGET_PPC64)
7456 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7457 #else
7458 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7459 #endif
7460 tcg_gen_br(l4);
7461 gen_set_label(l3);
7462 #if defined(TARGET_PPC64)
7463 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7464 #else
7465 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7466 #endif
7467 gen_set_label(l4);
7468 tcg_temp_free_i32(t0);
7469 #if defined(TARGET_PPC64)
7470 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7471 tcg_temp_free(t1);
7472 tcg_temp_free(t2);
7473 #endif
7474 }
7475
7476 static void gen_evsel0(DisasContext *ctx)
7477 {
7478 gen_evsel(ctx);
7479 }
7480
7481 static void gen_evsel1(DisasContext *ctx)
7482 {
7483 gen_evsel(ctx);
7484 }
7485
7486 static void gen_evsel2(DisasContext *ctx)
7487 {
7488 gen_evsel(ctx);
7489 }
7490
7491 static void gen_evsel3(DisasContext *ctx)
7492 {
7493 gen_evsel(ctx);
7494 }
7495
7496 /* Multiply */
7497
7498 static inline void gen_evmwumi(DisasContext *ctx)
7499 {
7500 TCGv_i64 t0, t1;
7501
7502 if (unlikely(!ctx->spe_enabled)) {
7503 gen_exception(ctx, POWERPC_EXCP_SPEU);
7504 return;
7505 }
7506
7507 t0 = tcg_temp_new_i64();
7508 t1 = tcg_temp_new_i64();
7509
7510 /* t0 := rA; t1 := rB */
7511 #if defined(TARGET_PPC64)
7512 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7513 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7514 #else
7515 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7516 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7517 #endif
7518
7519 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7520
7521 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7522
7523 tcg_temp_free_i64(t0);
7524 tcg_temp_free_i64(t1);
7525 }
7526
7527 static inline void gen_evmwumia(DisasContext *ctx)
7528 {
7529 TCGv_i64 tmp;
7530
7531 if (unlikely(!ctx->spe_enabled)) {
7532 gen_exception(ctx, POWERPC_EXCP_SPEU);
7533 return;
7534 }
7535
7536 gen_evmwumi(ctx); /* rD := rA * rB */
7537
7538 tmp = tcg_temp_new_i64();
7539
7540 /* acc := rD */
7541 gen_load_gpr64(tmp, rD(ctx->opcode));
7542 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7543 tcg_temp_free_i64(tmp);
7544 }
7545
7546 static inline void gen_evmwumiaa(DisasContext *ctx)
7547 {
7548 TCGv_i64 acc;
7549 TCGv_i64 tmp;
7550
7551 if (unlikely(!ctx->spe_enabled)) {
7552 gen_exception(ctx, POWERPC_EXCP_SPEU);
7553 return;
7554 }
7555
7556 gen_evmwumi(ctx); /* rD := rA * rB */
7557
7558 acc = tcg_temp_new_i64();
7559 tmp = tcg_temp_new_i64();
7560
7561 /* tmp := rD */
7562 gen_load_gpr64(tmp, rD(ctx->opcode));
7563
7564 /* Load acc */
7565 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7566
7567 /* acc := tmp + acc */
7568 tcg_gen_add_i64(acc, acc, tmp);
7569
7570 /* Store acc */
7571 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7572
7573 /* rD := acc */
7574 gen_store_gpr64(rD(ctx->opcode), acc);
7575
7576 tcg_temp_free_i64(acc);
7577 tcg_temp_free_i64(tmp);
7578 }
7579
7580 static inline void gen_evmwsmi(DisasContext *ctx)
7581 {
7582 TCGv_i64 t0, t1;
7583
7584 if (unlikely(!ctx->spe_enabled)) {
7585 gen_exception(ctx, POWERPC_EXCP_SPEU);
7586 return;
7587 }
7588
7589 t0 = tcg_temp_new_i64();
7590 t1 = tcg_temp_new_i64();
7591
7592 /* t0 := rA; t1 := rB */
7593 #if defined(TARGET_PPC64)
7594 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7595 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7596 #else
7597 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7598 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7599 #endif
7600
7601 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7602
7603 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7604
7605 tcg_temp_free_i64(t0);
7606 tcg_temp_free_i64(t1);
7607 }
7608
7609 static inline void gen_evmwsmia(DisasContext *ctx)
7610 {
7611 TCGv_i64 tmp;
7612
7613 gen_evmwsmi(ctx); /* rD := rA * rB */
7614
7615 tmp = tcg_temp_new_i64();
7616
7617 /* acc := rD */
7618 gen_load_gpr64(tmp, rD(ctx->opcode));
7619 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7620
7621 tcg_temp_free_i64(tmp);
7622 }
7623
7624 static inline void gen_evmwsmiaa(DisasContext *ctx)
7625 {
7626 TCGv_i64 acc = tcg_temp_new_i64();
7627 TCGv_i64 tmp = tcg_temp_new_i64();
7628
7629 gen_evmwsmi(ctx); /* rD := rA * rB */
7630
7631 acc = tcg_temp_new_i64();
7632 tmp = tcg_temp_new_i64();
7633
7634 /* tmp := rD */
7635 gen_load_gpr64(tmp, rD(ctx->opcode));
7636
7637 /* Load acc */
7638 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7639
7640 /* acc := tmp + acc */
7641 tcg_gen_add_i64(acc, acc, tmp);
7642
7643 /* Store acc */
7644 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7645
7646 /* rD := acc */
7647 gen_store_gpr64(rD(ctx->opcode), acc);
7648
7649 tcg_temp_free_i64(acc);
7650 tcg_temp_free_i64(tmp);
7651 }
7652
7653 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7654 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7655 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7656 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7657 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7658 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7659 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7660 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7661 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7662 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7663 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7664 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7665 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7666 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7667 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7668 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7669 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7670 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7671 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7672 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7673 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7674 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7675 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7676 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7677 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7678 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7679 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7680 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7681 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7682
7683 /* SPE load and stores */
7684 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7685 {
7686 target_ulong uimm = rB(ctx->opcode);
7687
7688 if (rA(ctx->opcode) == 0) {
7689 tcg_gen_movi_tl(EA, uimm << sh);
7690 } else {
7691 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7692 #if defined(TARGET_PPC64)
7693 if (!ctx->sf_mode) {
7694 tcg_gen_ext32u_tl(EA, EA);
7695 }
7696 #endif
7697 }
7698 }
7699
7700 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7701 {
7702 #if defined(TARGET_PPC64)
7703 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7704 #else
7705 TCGv_i64 t0 = tcg_temp_new_i64();
7706 gen_qemu_ld64(ctx, t0, addr);
7707 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7708 tcg_gen_shri_i64(t0, t0, 32);
7709 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7710 tcg_temp_free_i64(t0);
7711 #endif
7712 }
7713
7714 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7715 {
7716 #if defined(TARGET_PPC64)
7717 TCGv t0 = tcg_temp_new();
7718 gen_qemu_ld32u(ctx, t0, addr);
7719 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7720 gen_addr_add(ctx, addr, addr, 4);
7721 gen_qemu_ld32u(ctx, t0, addr);
7722 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7723 tcg_temp_free(t0);
7724 #else
7725 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7726 gen_addr_add(ctx, addr, addr, 4);
7727 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7728 #endif
7729 }
7730
7731 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7732 {
7733 TCGv t0 = tcg_temp_new();
7734 #if defined(TARGET_PPC64)
7735 gen_qemu_ld16u(ctx, t0, addr);
7736 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7737 gen_addr_add(ctx, addr, addr, 2);
7738 gen_qemu_ld16u(ctx, t0, addr);
7739 tcg_gen_shli_tl(t0, t0, 32);
7740 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7741 gen_addr_add(ctx, addr, addr, 2);
7742 gen_qemu_ld16u(ctx, t0, addr);
7743 tcg_gen_shli_tl(t0, t0, 16);
7744 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7745 gen_addr_add(ctx, addr, addr, 2);
7746 gen_qemu_ld16u(ctx, t0, addr);
7747 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7748 #else
7749 gen_qemu_ld16u(ctx, t0, addr);
7750 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7751 gen_addr_add(ctx, addr, addr, 2);
7752 gen_qemu_ld16u(ctx, t0, addr);
7753 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7754 gen_addr_add(ctx, addr, addr, 2);
7755 gen_qemu_ld16u(ctx, t0, addr);
7756 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7757 gen_addr_add(ctx, addr, addr, 2);
7758 gen_qemu_ld16u(ctx, t0, addr);
7759 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7760 #endif
7761 tcg_temp_free(t0);
7762 }
7763
7764 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7765 {
7766 TCGv t0 = tcg_temp_new();
7767 gen_qemu_ld16u(ctx, t0, addr);
7768 #if defined(TARGET_PPC64)
7769 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7770 tcg_gen_shli_tl(t0, t0, 16);
7771 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7772 #else
7773 tcg_gen_shli_tl(t0, t0, 16);
7774 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7775 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7776 #endif
7777 tcg_temp_free(t0);
7778 }
7779
7780 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7781 {
7782 TCGv t0 = tcg_temp_new();
7783 gen_qemu_ld16u(ctx, t0, addr);
7784 #if defined(TARGET_PPC64)
7785 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7786 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7787 #else
7788 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7789 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7790 #endif
7791 tcg_temp_free(t0);
7792 }
7793
7794 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7795 {
7796 TCGv t0 = tcg_temp_new();
7797 gen_qemu_ld16s(ctx, t0, addr);
7798 #if defined(TARGET_PPC64)
7799 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7800 tcg_gen_ext32u_tl(t0, t0);
7801 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7802 #else
7803 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7804 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7805 #endif
7806 tcg_temp_free(t0);
7807 }
7808
7809 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7810 {
7811 TCGv t0 = tcg_temp_new();
7812 #if defined(TARGET_PPC64)
7813 gen_qemu_ld16u(ctx, t0, addr);
7814 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7815 gen_addr_add(ctx, addr, addr, 2);
7816 gen_qemu_ld16u(ctx, t0, addr);
7817 tcg_gen_shli_tl(t0, t0, 16);
7818 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7819 #else
7820 gen_qemu_ld16u(ctx, t0, addr);
7821 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7822 gen_addr_add(ctx, addr, addr, 2);
7823 gen_qemu_ld16u(ctx, t0, addr);
7824 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7825 #endif
7826 tcg_temp_free(t0);
7827 }
7828
7829 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7830 {
7831 #if defined(TARGET_PPC64)
7832 TCGv t0 = tcg_temp_new();
7833 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7834 gen_addr_add(ctx, addr, addr, 2);
7835 gen_qemu_ld16u(ctx, t0, addr);
7836 tcg_gen_shli_tl(t0, t0, 32);
7837 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7838 tcg_temp_free(t0);
7839 #else
7840 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7841 gen_addr_add(ctx, addr, addr, 2);
7842 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7843 #endif
7844 }
7845
7846 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7847 {
7848 #if defined(TARGET_PPC64)
7849 TCGv t0 = tcg_temp_new();
7850 gen_qemu_ld16s(ctx, t0, addr);
7851 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7852 gen_addr_add(ctx, addr, addr, 2);
7853 gen_qemu_ld16s(ctx, t0, addr);
7854 tcg_gen_shli_tl(t0, t0, 32);
7855 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7856 tcg_temp_free(t0);
7857 #else
7858 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7859 gen_addr_add(ctx, addr, addr, 2);
7860 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7861 #endif
7862 }
7863
7864 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7865 {
7866 TCGv t0 = tcg_temp_new();
7867 gen_qemu_ld32u(ctx, t0, addr);
7868 #if defined(TARGET_PPC64)
7869 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7870 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7871 #else
7872 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7873 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7874 #endif
7875 tcg_temp_free(t0);
7876 }
7877
7878 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7879 {
7880 TCGv t0 = tcg_temp_new();
7881 #if defined(TARGET_PPC64)
7882 gen_qemu_ld16u(ctx, t0, addr);
7883 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7884 tcg_gen_shli_tl(t0, t0, 32);
7885 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7886 gen_addr_add(ctx, addr, addr, 2);
7887 gen_qemu_ld16u(ctx, t0, addr);
7888 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7889 tcg_gen_shli_tl(t0, t0, 16);
7890 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7891 #else
7892 gen_qemu_ld16u(ctx, t0, addr);
7893 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7894 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7895 gen_addr_add(ctx, addr, addr, 2);
7896 gen_qemu_ld16u(ctx, t0, addr);
7897 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7898 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7899 #endif
7900 tcg_temp_free(t0);
7901 }
7902
7903 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7904 {
7905 #if defined(TARGET_PPC64)
7906 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7907 #else
7908 TCGv_i64 t0 = tcg_temp_new_i64();
7909 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7910 gen_qemu_st64(ctx, t0, addr);
7911 tcg_temp_free_i64(t0);
7912 #endif
7913 }
7914
7915 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7916 {
7917 #if defined(TARGET_PPC64)
7918 TCGv t0 = tcg_temp_new();
7919 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7920 gen_qemu_st32(ctx, t0, addr);
7921 tcg_temp_free(t0);
7922 #else
7923 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7924 #endif
7925 gen_addr_add(ctx, addr, addr, 4);
7926 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7927 }
7928
7929 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7930 {
7931 TCGv t0 = tcg_temp_new();
7932 #if defined(TARGET_PPC64)
7933 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7934 #else
7935 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7936 #endif
7937 gen_qemu_st16(ctx, t0, addr);
7938 gen_addr_add(ctx, addr, addr, 2);
7939 #if defined(TARGET_PPC64)
7940 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7941 gen_qemu_st16(ctx, t0, addr);
7942 #else
7943 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7944 #endif
7945 gen_addr_add(ctx, addr, addr, 2);
7946 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7947 gen_qemu_st16(ctx, t0, addr);
7948 tcg_temp_free(t0);
7949 gen_addr_add(ctx, addr, addr, 2);
7950 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7951 }
7952
7953 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7954 {
7955 TCGv t0 = tcg_temp_new();
7956 #if defined(TARGET_PPC64)
7957 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7958 #else
7959 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7960 #endif
7961 gen_qemu_st16(ctx, t0, addr);
7962 gen_addr_add(ctx, addr, addr, 2);
7963 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7964 gen_qemu_st16(ctx, t0, addr);
7965 tcg_temp_free(t0);
7966 }
7967
7968 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7969 {
7970 #if defined(TARGET_PPC64)
7971 TCGv t0 = tcg_temp_new();
7972 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7973 gen_qemu_st16(ctx, t0, addr);
7974 tcg_temp_free(t0);
7975 #else
7976 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7977 #endif
7978 gen_addr_add(ctx, addr, addr, 2);
7979 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7980 }
7981
7982 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7983 {
7984 #if defined(TARGET_PPC64)
7985 TCGv t0 = tcg_temp_new();
7986 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7987 gen_qemu_st32(ctx, t0, addr);
7988 tcg_temp_free(t0);
7989 #else
7990 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7991 #endif
7992 }
7993
7994 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7995 {
7996 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7997 }
7998
7999 #define GEN_SPEOP_LDST(name, opc2, sh) \
8000 static void glue(gen_, name)(DisasContext *ctx) \
8001 { \
8002 TCGv t0; \
8003 if (unlikely(!ctx->spe_enabled)) { \
8004 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8005 return; \
8006 } \
8007 gen_set_access_type(ctx, ACCESS_INT); \
8008 t0 = tcg_temp_new(); \
8009 if (Rc(ctx->opcode)) { \
8010 gen_addr_spe_imm_index(ctx, t0, sh); \
8011 } else { \
8012 gen_addr_reg_index(ctx, t0); \
8013 } \
8014 gen_op_##name(ctx, t0); \
8015 tcg_temp_free(t0); \
8016 }
8017
8018 GEN_SPEOP_LDST(evldd, 0x00, 3);
8019 GEN_SPEOP_LDST(evldw, 0x01, 3);
8020 GEN_SPEOP_LDST(evldh, 0x02, 3);
8021 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
8022 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
8023 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
8024 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
8025 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
8026 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
8027 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
8028 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
8029
8030 GEN_SPEOP_LDST(evstdd, 0x10, 3);
8031 GEN_SPEOP_LDST(evstdw, 0x11, 3);
8032 GEN_SPEOP_LDST(evstdh, 0x12, 3);
8033 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
8034 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
8035 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
8036 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
8037
8038 /* Multiply and add - TODO */
8039 #if 0
8040 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
8041 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8042 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8043 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8044 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8045 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8046 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8047 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8048 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8049 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8050 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8051 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8052
8053 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8054 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8055 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8056 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8057 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8058 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8059 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8060 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8061 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8062 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8063 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8064 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8065
8066 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8067 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8068 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8069 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8070 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8071
8072 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8073 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8074 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8075 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8076 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8077 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8078 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8079 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8080 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8081 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8082 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8083 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8084
8085 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8086 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8087 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8088 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8089
8090 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8091 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8092 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8093 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8094 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8095 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8096 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8097 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8098 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8099 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8100 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8101 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8102
8103 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8104 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8105 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8106 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8107 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8108 #endif
8109
8110 /*** SPE floating-point extension ***/
8111 #if defined(TARGET_PPC64)
8112 #define GEN_SPEFPUOP_CONV_32_32(name) \
8113 static inline void gen_##name(DisasContext *ctx) \
8114 { \
8115 TCGv_i32 t0; \
8116 TCGv t1; \
8117 t0 = tcg_temp_new_i32(); \
8118 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8119 gen_helper_##name(t0, cpu_env, t0); \
8120 t1 = tcg_temp_new(); \
8121 tcg_gen_extu_i32_tl(t1, t0); \
8122 tcg_temp_free_i32(t0); \
8123 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8124 0xFFFFFFFF00000000ULL); \
8125 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8126 tcg_temp_free(t1); \
8127 }
8128 #define GEN_SPEFPUOP_CONV_32_64(name) \
8129 static inline void gen_##name(DisasContext *ctx) \
8130 { \
8131 TCGv_i32 t0; \
8132 TCGv t1; \
8133 t0 = tcg_temp_new_i32(); \
8134 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8135 t1 = tcg_temp_new(); \
8136 tcg_gen_extu_i32_tl(t1, t0); \
8137 tcg_temp_free_i32(t0); \
8138 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8139 0xFFFFFFFF00000000ULL); \
8140 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8141 tcg_temp_free(t1); \
8142 }
8143 #define GEN_SPEFPUOP_CONV_64_32(name) \
8144 static inline void gen_##name(DisasContext *ctx) \
8145 { \
8146 TCGv_i32 t0 = tcg_temp_new_i32(); \
8147 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8148 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8149 tcg_temp_free_i32(t0); \
8150 }
8151 #define GEN_SPEFPUOP_CONV_64_64(name) \
8152 static inline void gen_##name(DisasContext *ctx) \
8153 { \
8154 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8155 cpu_gpr[rB(ctx->opcode)]); \
8156 }
8157 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8158 static inline void gen_##name(DisasContext *ctx) \
8159 { \
8160 TCGv_i32 t0, t1; \
8161 TCGv_i64 t2; \
8162 if (unlikely(!ctx->spe_enabled)) { \
8163 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8164 return; \
8165 } \
8166 t0 = tcg_temp_new_i32(); \
8167 t1 = tcg_temp_new_i32(); \
8168 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8169 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8170 gen_helper_##name(t0, cpu_env, t0, t1); \
8171 tcg_temp_free_i32(t1); \
8172 t2 = tcg_temp_new(); \
8173 tcg_gen_extu_i32_tl(t2, t0); \
8174 tcg_temp_free_i32(t0); \
8175 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8176 0xFFFFFFFF00000000ULL); \
8177 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8178 tcg_temp_free(t2); \
8179 }
8180 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8181 static inline void gen_##name(DisasContext *ctx) \
8182 { \
8183 if (unlikely(!ctx->spe_enabled)) { \
8184 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8185 return; \
8186 } \
8187 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8188 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8189 }
8190 #define GEN_SPEFPUOP_COMP_32(name) \
8191 static inline void gen_##name(DisasContext *ctx) \
8192 { \
8193 TCGv_i32 t0, t1; \
8194 if (unlikely(!ctx->spe_enabled)) { \
8195 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8196 return; \
8197 } \
8198 t0 = tcg_temp_new_i32(); \
8199 t1 = tcg_temp_new_i32(); \
8200 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8201 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8202 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8203 tcg_temp_free_i32(t0); \
8204 tcg_temp_free_i32(t1); \
8205 }
8206 #define GEN_SPEFPUOP_COMP_64(name) \
8207 static inline void gen_##name(DisasContext *ctx) \
8208 { \
8209 if (unlikely(!ctx->spe_enabled)) { \
8210 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8211 return; \
8212 } \
8213 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8214 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8215 }
8216 #else
8217 #define GEN_SPEFPUOP_CONV_32_32(name) \
8218 static inline void gen_##name(DisasContext *ctx) \
8219 { \
8220 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8221 cpu_gpr[rB(ctx->opcode)]); \
8222 }
8223 #define GEN_SPEFPUOP_CONV_32_64(name) \
8224 static inline void gen_##name(DisasContext *ctx) \
8225 { \
8226 TCGv_i64 t0 = tcg_temp_new_i64(); \
8227 gen_load_gpr64(t0, rB(ctx->opcode)); \
8228 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8229 tcg_temp_free_i64(t0); \
8230 }
8231 #define GEN_SPEFPUOP_CONV_64_32(name) \
8232 static inline void gen_##name(DisasContext *ctx) \
8233 { \
8234 TCGv_i64 t0 = tcg_temp_new_i64(); \
8235 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8236 gen_store_gpr64(rD(ctx->opcode), t0); \
8237 tcg_temp_free_i64(t0); \
8238 }
8239 #define GEN_SPEFPUOP_CONV_64_64(name) \
8240 static inline void gen_##name(DisasContext *ctx) \
8241 { \
8242 TCGv_i64 t0 = tcg_temp_new_i64(); \
8243 gen_load_gpr64(t0, rB(ctx->opcode)); \
8244 gen_helper_##name(t0, cpu_env, t0); \
8245 gen_store_gpr64(rD(ctx->opcode), t0); \
8246 tcg_temp_free_i64(t0); \
8247 }
8248 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8249 static inline void gen_##name(DisasContext *ctx) \
8250 { \
8251 if (unlikely(!ctx->spe_enabled)) { \
8252 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8253 return; \
8254 } \
8255 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8256 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8257 }
8258 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8259 static inline void gen_##name(DisasContext *ctx) \
8260 { \
8261 TCGv_i64 t0, t1; \
8262 if (unlikely(!ctx->spe_enabled)) { \
8263 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8264 return; \
8265 } \
8266 t0 = tcg_temp_new_i64(); \
8267 t1 = tcg_temp_new_i64(); \
8268 gen_load_gpr64(t0, rA(ctx->opcode)); \
8269 gen_load_gpr64(t1, rB(ctx->opcode)); \
8270 gen_helper_##name(t0, cpu_env, t0, t1); \
8271 gen_store_gpr64(rD(ctx->opcode), t0); \
8272 tcg_temp_free_i64(t0); \
8273 tcg_temp_free_i64(t1); \
8274 }
8275 #define GEN_SPEFPUOP_COMP_32(name) \
8276 static inline void gen_##name(DisasContext *ctx) \
8277 { \
8278 if (unlikely(!ctx->spe_enabled)) { \
8279 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8280 return; \
8281 } \
8282 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8283 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8284 }
8285 #define GEN_SPEFPUOP_COMP_64(name) \
8286 static inline void gen_##name(DisasContext *ctx) \
8287 { \
8288 TCGv_i64 t0, t1; \
8289 if (unlikely(!ctx->spe_enabled)) { \
8290 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8291 return; \
8292 } \
8293 t0 = tcg_temp_new_i64(); \
8294 t1 = tcg_temp_new_i64(); \
8295 gen_load_gpr64(t0, rA(ctx->opcode)); \
8296 gen_load_gpr64(t1, rB(ctx->opcode)); \
8297 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8298 tcg_temp_free_i64(t0); \
8299 tcg_temp_free_i64(t1); \
8300 }
8301 #endif
8302
8303 /* Single precision floating-point vectors operations */
8304 /* Arithmetic */
8305 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8306 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8307 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8308 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8309 static inline void gen_evfsabs(DisasContext *ctx)
8310 {
8311 if (unlikely(!ctx->spe_enabled)) {
8312 gen_exception(ctx, POWERPC_EXCP_SPEU);
8313 return;
8314 }
8315 #if defined(TARGET_PPC64)
8316 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8317 #else
8318 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8319 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8320 #endif
8321 }
8322 static inline void gen_evfsnabs(DisasContext *ctx)
8323 {
8324 if (unlikely(!ctx->spe_enabled)) {
8325 gen_exception(ctx, POWERPC_EXCP_SPEU);
8326 return;
8327 }
8328 #if defined(TARGET_PPC64)
8329 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8330 #else
8331 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8332 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8333 #endif
8334 }
8335 static inline void gen_evfsneg(DisasContext *ctx)
8336 {
8337 if (unlikely(!ctx->spe_enabled)) {
8338 gen_exception(ctx, POWERPC_EXCP_SPEU);
8339 return;
8340 }
8341 #if defined(TARGET_PPC64)
8342 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8343 #else
8344 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8345 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8346 #endif
8347 }
8348
8349 /* Conversion */
8350 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8351 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8352 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8353 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8354 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8355 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8356 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8357 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8358 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8359 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8360
8361 /* Comparison */
8362 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8363 GEN_SPEFPUOP_COMP_64(evfscmplt);
8364 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8365 GEN_SPEFPUOP_COMP_64(evfststgt);
8366 GEN_SPEFPUOP_COMP_64(evfststlt);
8367 GEN_SPEFPUOP_COMP_64(evfststeq);
8368
8369 /* Opcodes definitions */
8370 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8371 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8372 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8373 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8374 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8375 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8376 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8377 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8378 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8379 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8380 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8381 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8382 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8383 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8384
8385 /* Single precision floating-point operations */
8386 /* Arithmetic */
8387 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8388 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8389 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8390 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8391 static inline void gen_efsabs(DisasContext *ctx)
8392 {
8393 if (unlikely(!ctx->spe_enabled)) {
8394 gen_exception(ctx, POWERPC_EXCP_SPEU);
8395 return;
8396 }
8397 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8398 }
8399 static inline void gen_efsnabs(DisasContext *ctx)
8400 {
8401 if (unlikely(!ctx->spe_enabled)) {
8402 gen_exception(ctx, POWERPC_EXCP_SPEU);
8403 return;
8404 }
8405 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8406 }
8407 static inline void gen_efsneg(DisasContext *ctx)
8408 {
8409 if (unlikely(!ctx->spe_enabled)) {
8410 gen_exception(ctx, POWERPC_EXCP_SPEU);
8411 return;
8412 }
8413 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8414 }
8415
8416 /* Conversion */
8417 GEN_SPEFPUOP_CONV_32_32(efscfui);
8418 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8419 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8420 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8421 GEN_SPEFPUOP_CONV_32_32(efsctui);
8422 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8423 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8424 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8425 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8426 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8427 GEN_SPEFPUOP_CONV_32_64(efscfd);
8428
8429 /* Comparison */
8430 GEN_SPEFPUOP_COMP_32(efscmpgt);
8431 GEN_SPEFPUOP_COMP_32(efscmplt);
8432 GEN_SPEFPUOP_COMP_32(efscmpeq);
8433 GEN_SPEFPUOP_COMP_32(efststgt);
8434 GEN_SPEFPUOP_COMP_32(efststlt);
8435 GEN_SPEFPUOP_COMP_32(efststeq);
8436
8437 /* Opcodes definitions */
8438 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8439 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8440 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8441 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8442 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8443 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8444 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8445 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8446 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8447 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8448 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8449 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8450 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8451 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8452
8453 /* Double precision floating-point operations */
8454 /* Arithmetic */
8455 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8456 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8457 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8458 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8459 static inline void gen_efdabs(DisasContext *ctx)
8460 {
8461 if (unlikely(!ctx->spe_enabled)) {
8462 gen_exception(ctx, POWERPC_EXCP_SPEU);
8463 return;
8464 }
8465 #if defined(TARGET_PPC64)
8466 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8467 #else
8468 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8469 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8470 #endif
8471 }
8472 static inline void gen_efdnabs(DisasContext *ctx)
8473 {
8474 if (unlikely(!ctx->spe_enabled)) {
8475 gen_exception(ctx, POWERPC_EXCP_SPEU);
8476 return;
8477 }
8478 #if defined(TARGET_PPC64)
8479 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8480 #else
8481 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8482 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8483 #endif
8484 }
8485 static inline void gen_efdneg(DisasContext *ctx)
8486 {
8487 if (unlikely(!ctx->spe_enabled)) {
8488 gen_exception(ctx, POWERPC_EXCP_SPEU);
8489 return;
8490 }
8491 #if defined(TARGET_PPC64)
8492 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8493 #else
8494 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8495 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8496 #endif
8497 }
8498
8499 /* Conversion */
8500 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8501 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8502 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8503 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8504 GEN_SPEFPUOP_CONV_32_64(efdctui);
8505 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8506 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8507 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8508 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8509 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8510 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8511 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8512 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8513 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8514 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8515
8516 /* Comparison */
8517 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8518 GEN_SPEFPUOP_COMP_64(efdcmplt);
8519 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8520 GEN_SPEFPUOP_COMP_64(efdtstgt);
8521 GEN_SPEFPUOP_COMP_64(efdtstlt);
8522 GEN_SPEFPUOP_COMP_64(efdtsteq);
8523
8524 /* Opcodes definitions */
8525 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8526 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8527 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8528 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8529 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8530 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8531 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8532 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8533 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8534 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8535 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8536 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8537 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8538 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8539 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8540 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8541
8542 static opcode_t opcodes[] = {
8543 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8544 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8545 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8546 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8547 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8548 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8549 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8550 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8551 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8552 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8553 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8554 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8555 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8556 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8557 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8558 #if defined(TARGET_PPC64)
8559 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8560 #endif
8561 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8562 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8563 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8564 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8565 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8566 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8567 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8568 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8569 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8570 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8571 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8572 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8573 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8574 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8575 #if defined(TARGET_PPC64)
8576 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8577 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8578 #endif
8579 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8580 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8581 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8582 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8583 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8584 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8585 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8586 #if defined(TARGET_PPC64)
8587 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8588 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8589 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8590 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8591 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8592 #endif
8593 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8594 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8595 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8596 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8597 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8598 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8599 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8600 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8601 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8602 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8603 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8604 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8605 #if defined(TARGET_PPC64)
8606 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8607 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8608 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8609 #endif
8610 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8611 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8612 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8613 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8614 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8615 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8616 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8617 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8618 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8619 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8620 #if defined(TARGET_PPC64)
8621 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8622 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8623 #endif
8624 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8625 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8626 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8627 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8628 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8629 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8630 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8631 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8632 #if defined(TARGET_PPC64)
8633 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8634 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8635 #endif
8636 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8637 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8638 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8639 #if defined(TARGET_PPC64)
8640 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8641 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8642 #endif
8643 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8644 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8645 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8646 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8647 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8648 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8649 #if defined(TARGET_PPC64)
8650 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8651 #endif
8652 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8653 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8654 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8655 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8656 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8657 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8658 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8659 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8660 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8661 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8662 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8663 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8664 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8665 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8666 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8667 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8668 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8669 #if defined(TARGET_PPC64)
8670 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8671 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8672 PPC_SEGMENT_64B),
8673 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8674 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8675 PPC_SEGMENT_64B),
8676 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8677 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8678 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8679 #endif
8680 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8681 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8682 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8683 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8684 #if defined(TARGET_PPC64)
8685 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8686 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8687 #endif
8688 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8689 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8690 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8691 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8692 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8693 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8694 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8695 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8696 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8697 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8698 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8699 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8700 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8701 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8702 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8703 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8704 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8705 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8706 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8707 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8708 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8709 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8710 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8711 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8712 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8713 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8714 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8715 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8716 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8717 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8718 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8719 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8720 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8721 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8722 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8723 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8724 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8725 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8726 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8727 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8728 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8729 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8730 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8731 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8732 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8733 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8734 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8735 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8736 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8737 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8738 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8739 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8740 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8741 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8742 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8743 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8744 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8745 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8746 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8747 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8748 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8749 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8750 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8751 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8752 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8753 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8754 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8755 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8756 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8757 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8758 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8759 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8760 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8761 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8762 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8763 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8764 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8765 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8766 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8767 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8768 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8769 PPC_NONE, PPC2_BOOKE206),
8770 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8771 PPC_NONE, PPC2_BOOKE206),
8772 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8773 PPC_NONE, PPC2_BOOKE206),
8774 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8775 PPC_NONE, PPC2_BOOKE206),
8776 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8777 PPC_NONE, PPC2_BOOKE206),
8778 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8779 PPC_NONE, PPC2_PRCNTL),
8780 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8781 PPC_NONE, PPC2_PRCNTL),
8782 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8783 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8784 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8785 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8786 PPC_BOOKE, PPC2_BOOKE206),
8787 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8788 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8789 PPC_BOOKE, PPC2_BOOKE206),
8790 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8791 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8792 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8793 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8794 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8795 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8796 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8797 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8798 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8799 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8800
8801 #undef GEN_INT_ARITH_ADD
8802 #undef GEN_INT_ARITH_ADD_CONST
8803 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8804 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8805 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8806 add_ca, compute_ca, compute_ov) \
8807 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8808 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8809 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8810 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8811 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8812 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8813 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8814 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8815 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8816 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8817 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8818
8819 #undef GEN_INT_ARITH_DIVW
8820 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8821 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8822 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8823 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8824 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8825 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8826
8827 #if defined(TARGET_PPC64)
8828 #undef GEN_INT_ARITH_DIVD
8829 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8830 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8831 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8832 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8833 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8834 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8835
8836 #undef GEN_INT_ARITH_MUL_HELPER
8837 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8838 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8839 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8840 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8841 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8842 #endif
8843
8844 #undef GEN_INT_ARITH_SUBF
8845 #undef GEN_INT_ARITH_SUBF_CONST
8846 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8847 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8848 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8849 add_ca, compute_ca, compute_ov) \
8850 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8851 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8852 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8853 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8854 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8855 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8856 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8857 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8858 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8859 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8860 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8861
8862 #undef GEN_LOGICAL1
8863 #undef GEN_LOGICAL2
8864 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8865 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8866 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8867 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8868 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8869 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8870 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8871 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8872 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8873 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8874 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8875 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8876 #if defined(TARGET_PPC64)
8877 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8878 #endif
8879
8880 #if defined(TARGET_PPC64)
8881 #undef GEN_PPC64_R2
8882 #undef GEN_PPC64_R4
8883 #define GEN_PPC64_R2(name, opc1, opc2) \
8884 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8885 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8886 PPC_64B)
8887 #define GEN_PPC64_R4(name, opc1, opc2) \
8888 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8889 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8890 PPC_64B), \
8891 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8892 PPC_64B), \
8893 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8894 PPC_64B)
8895 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8896 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8897 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8898 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8899 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8900 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8901 #endif
8902
8903 #undef _GEN_FLOAT_ACB
8904 #undef GEN_FLOAT_ACB
8905 #undef _GEN_FLOAT_AB
8906 #undef GEN_FLOAT_AB
8907 #undef _GEN_FLOAT_AC
8908 #undef GEN_FLOAT_AC
8909 #undef GEN_FLOAT_B
8910 #undef GEN_FLOAT_BS
8911 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8912 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8913 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8914 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8915 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8916 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8917 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8918 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8919 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8920 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8921 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8922 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8923 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8924 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8925 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8926 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8927 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8928 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8929 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8930
8931 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8932 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8933 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8934 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8935 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8936 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8937 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8938 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8939 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8940 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8941 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8942 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8943 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8944 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8945 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8946 #if defined(TARGET_PPC64)
8947 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8948 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8949 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8950 #endif
8951 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8952 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8953 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8954 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8955 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8956 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8957 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8958
8959 #undef GEN_LD
8960 #undef GEN_LDU
8961 #undef GEN_LDUX
8962 #undef GEN_LDX_E
8963 #undef GEN_LDS
8964 #define GEN_LD(name, ldop, opc, type) \
8965 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8966 #define GEN_LDU(name, ldop, opc, type) \
8967 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8968 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8969 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8970 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8971 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8972 #define GEN_LDS(name, ldop, op, type) \
8973 GEN_LD(name, ldop, op | 0x20, type) \
8974 GEN_LDU(name, ldop, op | 0x21, type) \
8975 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8976 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8977
8978 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8979 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8980 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8981 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8982 #if defined(TARGET_PPC64)
8983 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8984 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8985 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8986 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8987 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8988 #endif
8989 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8990 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8991
8992 #undef GEN_ST
8993 #undef GEN_STU
8994 #undef GEN_STUX
8995 #undef GEN_STX_E
8996 #undef GEN_STS
8997 #define GEN_ST(name, stop, opc, type) \
8998 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8999 #define GEN_STU(name, stop, opc, type) \
9000 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
9001 #define GEN_STUX(name, stop, opc2, opc3, type) \
9002 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9003 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
9004 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9005 #define GEN_STS(name, stop, op, type) \
9006 GEN_ST(name, stop, op | 0x20, type) \
9007 GEN_STU(name, stop, op | 0x21, type) \
9008 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
9009 GEN_STX(name, stop, 0x17, op | 0x00, type)
9010
9011 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
9012 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
9013 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
9014 #if defined(TARGET_PPC64)
9015 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
9016 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
9017 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
9018 #endif
9019 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
9020 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
9021
9022 #undef GEN_LDF
9023 #undef GEN_LDUF
9024 #undef GEN_LDUXF
9025 #undef GEN_LDXF
9026 #undef GEN_LDFS
9027 #define GEN_LDF(name, ldop, opc, type) \
9028 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9029 #define GEN_LDUF(name, ldop, opc, type) \
9030 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9031 #define GEN_LDUXF(name, ldop, opc, type) \
9032 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9033 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
9034 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9035 #define GEN_LDFS(name, ldop, op, type) \
9036 GEN_LDF(name, ldop, op | 0x20, type) \
9037 GEN_LDUF(name, ldop, op | 0x21, type) \
9038 GEN_LDUXF(name, ldop, op | 0x01, type) \
9039 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9040
9041 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
9042 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
9043
9044 #undef GEN_STF
9045 #undef GEN_STUF
9046 #undef GEN_STUXF
9047 #undef GEN_STXF
9048 #undef GEN_STFS
9049 #define GEN_STF(name, stop, opc, type) \
9050 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9051 #define GEN_STUF(name, stop, opc, type) \
9052 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9053 #define GEN_STUXF(name, stop, opc, type) \
9054 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9055 #define GEN_STXF(name, stop, opc2, opc3, type) \
9056 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9057 #define GEN_STFS(name, stop, op, type) \
9058 GEN_STF(name, stop, op | 0x20, type) \
9059 GEN_STUF(name, stop, op | 0x21, type) \
9060 GEN_STUXF(name, stop, op | 0x01, type) \
9061 GEN_STXF(name, stop, 0x17, op | 0x00, type)
9062
9063 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
9064 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
9065 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
9066
9067 #undef GEN_CRLOGIC
9068 #define GEN_CRLOGIC(name, tcg_op, opc) \
9069 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9070 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
9071 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
9072 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
9073 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9074 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9075 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9076 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9077 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9078
9079 #undef GEN_MAC_HANDLER
9080 #define GEN_MAC_HANDLER(name, opc2, opc3) \
9081 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9082 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9083 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9084 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9085 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9086 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9087 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9088 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9089 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9090 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9091 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9092 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9093 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9094 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9095 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9096 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9097 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9098 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9099 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9100 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9101 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9102 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9103 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9104 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9105 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9106 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9107 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9108 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9109 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9110 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9111 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9112 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9113 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9114 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9115 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9116 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9117 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9118 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9119 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9120 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9121 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9122 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9123 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9124
9125 #undef GEN_VR_LDX
9126 #undef GEN_VR_STX
9127 #undef GEN_VR_LVE
9128 #undef GEN_VR_STVE
9129 #define GEN_VR_LDX(name, opc2, opc3) \
9130 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9131 #define GEN_VR_STX(name, opc2, opc3) \
9132 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9133 #define GEN_VR_LVE(name, opc2, opc3) \
9134 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9135 #define GEN_VR_STVE(name, opc2, opc3) \
9136 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9137 GEN_VR_LDX(lvx, 0x07, 0x03),
9138 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9139 GEN_VR_LVE(bx, 0x07, 0x00),
9140 GEN_VR_LVE(hx, 0x07, 0x01),
9141 GEN_VR_LVE(wx, 0x07, 0x02),
9142 GEN_VR_STX(svx, 0x07, 0x07),
9143 GEN_VR_STX(svxl, 0x07, 0x0F),
9144 GEN_VR_STVE(bx, 0x07, 0x04),
9145 GEN_VR_STVE(hx, 0x07, 0x05),
9146 GEN_VR_STVE(wx, 0x07, 0x06),
9147
9148 #undef GEN_VX_LOGICAL
9149 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9150 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9151 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9152 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9153 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9154 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9155 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9156
9157 #undef GEN_VXFORM
9158 #define GEN_VXFORM(name, opc2, opc3) \
9159 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9160 GEN_VXFORM(vaddubm, 0, 0),
9161 GEN_VXFORM(vadduhm, 0, 1),
9162 GEN_VXFORM(vadduwm, 0, 2),
9163 GEN_VXFORM(vsububm, 0, 16),
9164 GEN_VXFORM(vsubuhm, 0, 17),
9165 GEN_VXFORM(vsubuwm, 0, 18),
9166 GEN_VXFORM(vmaxub, 1, 0),
9167 GEN_VXFORM(vmaxuh, 1, 1),
9168 GEN_VXFORM(vmaxuw, 1, 2),
9169 GEN_VXFORM(vmaxsb, 1, 4),
9170 GEN_VXFORM(vmaxsh, 1, 5),
9171 GEN_VXFORM(vmaxsw, 1, 6),
9172 GEN_VXFORM(vminub, 1, 8),
9173 GEN_VXFORM(vminuh, 1, 9),
9174 GEN_VXFORM(vminuw, 1, 10),
9175 GEN_VXFORM(vminsb, 1, 12),
9176 GEN_VXFORM(vminsh, 1, 13),
9177 GEN_VXFORM(vminsw, 1, 14),
9178 GEN_VXFORM(vavgub, 1, 16),
9179 GEN_VXFORM(vavguh, 1, 17),
9180 GEN_VXFORM(vavguw, 1, 18),
9181 GEN_VXFORM(vavgsb, 1, 20),
9182 GEN_VXFORM(vavgsh, 1, 21),
9183 GEN_VXFORM(vavgsw, 1, 22),
9184 GEN_VXFORM(vmrghb, 6, 0),
9185 GEN_VXFORM(vmrghh, 6, 1),
9186 GEN_VXFORM(vmrghw, 6, 2),
9187 GEN_VXFORM(vmrglb, 6, 4),
9188 GEN_VXFORM(vmrglh, 6, 5),
9189 GEN_VXFORM(vmrglw, 6, 6),
9190 GEN_VXFORM(vmuloub, 4, 0),
9191 GEN_VXFORM(vmulouh, 4, 1),
9192 GEN_VXFORM(vmulosb, 4, 4),
9193 GEN_VXFORM(vmulosh, 4, 5),
9194 GEN_VXFORM(vmuleub, 4, 8),
9195 GEN_VXFORM(vmuleuh, 4, 9),
9196 GEN_VXFORM(vmulesb, 4, 12),
9197 GEN_VXFORM(vmulesh, 4, 13),
9198 GEN_VXFORM(vslb, 2, 4),
9199 GEN_VXFORM(vslh, 2, 5),
9200 GEN_VXFORM(vslw, 2, 6),
9201 GEN_VXFORM(vsrb, 2, 8),
9202 GEN_VXFORM(vsrh, 2, 9),
9203 GEN_VXFORM(vsrw, 2, 10),
9204 GEN_VXFORM(vsrab, 2, 12),
9205 GEN_VXFORM(vsrah, 2, 13),
9206 GEN_VXFORM(vsraw, 2, 14),
9207 GEN_VXFORM(vslo, 6, 16),
9208 GEN_VXFORM(vsro, 6, 17),
9209 GEN_VXFORM(vaddcuw, 0, 6),
9210 GEN_VXFORM(vsubcuw, 0, 22),
9211 GEN_VXFORM(vaddubs, 0, 8),
9212 GEN_VXFORM(vadduhs, 0, 9),
9213 GEN_VXFORM(vadduws, 0, 10),
9214 GEN_VXFORM(vaddsbs, 0, 12),
9215 GEN_VXFORM(vaddshs, 0, 13),
9216 GEN_VXFORM(vaddsws, 0, 14),
9217 GEN_VXFORM(vsububs, 0, 24),
9218 GEN_VXFORM(vsubuhs, 0, 25),
9219 GEN_VXFORM(vsubuws, 0, 26),
9220 GEN_VXFORM(vsubsbs, 0, 28),
9221 GEN_VXFORM(vsubshs, 0, 29),
9222 GEN_VXFORM(vsubsws, 0, 30),
9223 GEN_VXFORM(vrlb, 2, 0),
9224 GEN_VXFORM(vrlh, 2, 1),
9225 GEN_VXFORM(vrlw, 2, 2),
9226 GEN_VXFORM(vsl, 2, 7),
9227 GEN_VXFORM(vsr, 2, 11),
9228 GEN_VXFORM(vpkuhum, 7, 0),
9229 GEN_VXFORM(vpkuwum, 7, 1),
9230 GEN_VXFORM(vpkuhus, 7, 2),
9231 GEN_VXFORM(vpkuwus, 7, 3),
9232 GEN_VXFORM(vpkshus, 7, 4),
9233 GEN_VXFORM(vpkswus, 7, 5),
9234 GEN_VXFORM(vpkshss, 7, 6),
9235 GEN_VXFORM(vpkswss, 7, 7),
9236 GEN_VXFORM(vpkpx, 7, 12),
9237 GEN_VXFORM(vsum4ubs, 4, 24),
9238 GEN_VXFORM(vsum4sbs, 4, 28),
9239 GEN_VXFORM(vsum4shs, 4, 25),
9240 GEN_VXFORM(vsum2sws, 4, 26),
9241 GEN_VXFORM(vsumsws, 4, 30),
9242 GEN_VXFORM(vaddfp, 5, 0),
9243 GEN_VXFORM(vsubfp, 5, 1),
9244 GEN_VXFORM(vmaxfp, 5, 16),
9245 GEN_VXFORM(vminfp, 5, 17),
9246
9247 #undef GEN_VXRFORM1
9248 #undef GEN_VXRFORM
9249 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9250 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9251 #define GEN_VXRFORM(name, opc2, opc3) \
9252 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9253 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9254 GEN_VXRFORM(vcmpequb, 3, 0)
9255 GEN_VXRFORM(vcmpequh, 3, 1)
9256 GEN_VXRFORM(vcmpequw, 3, 2)
9257 GEN_VXRFORM(vcmpgtsb, 3, 12)
9258 GEN_VXRFORM(vcmpgtsh, 3, 13)
9259 GEN_VXRFORM(vcmpgtsw, 3, 14)
9260 GEN_VXRFORM(vcmpgtub, 3, 8)
9261 GEN_VXRFORM(vcmpgtuh, 3, 9)
9262 GEN_VXRFORM(vcmpgtuw, 3, 10)
9263 GEN_VXRFORM(vcmpeqfp, 3, 3)
9264 GEN_VXRFORM(vcmpgefp, 3, 7)
9265 GEN_VXRFORM(vcmpgtfp, 3, 11)
9266 GEN_VXRFORM(vcmpbfp, 3, 15)
9267
9268 #undef GEN_VXFORM_SIMM
9269 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9270 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9271 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9272 GEN_VXFORM_SIMM(vspltish, 6, 13),
9273 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9274
9275 #undef GEN_VXFORM_NOA
9276 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9277 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9278 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9279 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9280 GEN_VXFORM_NOA(vupklsb, 7, 10),
9281 GEN_VXFORM_NOA(vupklsh, 7, 11),
9282 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9283 GEN_VXFORM_NOA(vupklpx, 7, 15),
9284 GEN_VXFORM_NOA(vrefp, 5, 4),
9285 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9286 GEN_VXFORM_NOA(vexptefp, 5, 6),
9287 GEN_VXFORM_NOA(vlogefp, 5, 7),
9288 GEN_VXFORM_NOA(vrfim, 5, 8),
9289 GEN_VXFORM_NOA(vrfin, 5, 9),
9290 GEN_VXFORM_NOA(vrfip, 5, 10),
9291 GEN_VXFORM_NOA(vrfiz, 5, 11),
9292
9293 #undef GEN_VXFORM_UIMM
9294 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9295 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9296 GEN_VXFORM_UIMM(vspltb, 6, 8),
9297 GEN_VXFORM_UIMM(vsplth, 6, 9),
9298 GEN_VXFORM_UIMM(vspltw, 6, 10),
9299 GEN_VXFORM_UIMM(vcfux, 5, 12),
9300 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9301 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9302 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9303
9304 #undef GEN_VAFORM_PAIRED
9305 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9306 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9307 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9308 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9309 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9310 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9311 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9312 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9313
9314 #undef GEN_SPE
9315 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9316 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9317 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9318 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9319 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9320 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9321 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9322 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9323 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9324 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9325 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9326 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9327 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9328 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9329 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9330 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9331 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9332 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9333 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9334 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9335 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9336 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9337 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9338 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9339 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9340 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9341 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9342 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9343 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9344 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9345 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9346
9347 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9348 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9349 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9350 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9351 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9352 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9353 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9354 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9355 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9356 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9357 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9358 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9359 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9360 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9361
9362 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9363 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9364 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9365 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9366 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9367 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9368 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9369 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9370 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9371 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9372 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9373 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9374 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9375 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9376
9377 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9378 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9379 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9380 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9381 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9382 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9383 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9384 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9385 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9386 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9387 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9388 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9389 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9390 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9391 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9392 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9393
9394 #undef GEN_SPEOP_LDST
9395 #define GEN_SPEOP_LDST(name, opc2, sh) \
9396 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9397 GEN_SPEOP_LDST(evldd, 0x00, 3),
9398 GEN_SPEOP_LDST(evldw, 0x01, 3),
9399 GEN_SPEOP_LDST(evldh, 0x02, 3),
9400 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9401 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9402 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9403 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9404 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9405 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9406 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9407 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9408
9409 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9410 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9411 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9412 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9413 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9414 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9415 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9416 };
9417
9418 #include "helper_regs.h"
9419 #include "translate_init.c"
9420
9421 /*****************************************************************************/
9422 /* Misc PowerPC helpers */
9423 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9424 int flags)
9425 {
9426 #define RGPL 4
9427 #define RFPL 4
9428
9429 int i;
9430
9431 cpu_synchronize_state(env);
9432
9433 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9434 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9435 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9436 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9437 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9438 env->hflags, env->mmu_idx);
9439 #if !defined(NO_TIMER_DUMP)
9440 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9441 #if !defined(CONFIG_USER_ONLY)
9442 " DECR %08" PRIu32
9443 #endif
9444 "\n",
9445 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9446 #if !defined(CONFIG_USER_ONLY)
9447 , cpu_ppc_load_decr(env)
9448 #endif
9449 );
9450 #endif
9451 for (i = 0; i < 32; i++) {
9452 if ((i & (RGPL - 1)) == 0)
9453 cpu_fprintf(f, "GPR%02d", i);
9454 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9455 if ((i & (RGPL - 1)) == (RGPL - 1))
9456 cpu_fprintf(f, "\n");
9457 }
9458 cpu_fprintf(f, "CR ");
9459 for (i = 0; i < 8; i++)
9460 cpu_fprintf(f, "%01x", env->crf[i]);
9461 cpu_fprintf(f, " [");
9462 for (i = 0; i < 8; i++) {
9463 char a = '-';
9464 if (env->crf[i] & 0x08)
9465 a = 'L';
9466 else if (env->crf[i] & 0x04)
9467 a = 'G';
9468 else if (env->crf[i] & 0x02)
9469 a = 'E';
9470 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9471 }
9472 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9473 env->reserve_addr);
9474 for (i = 0; i < 32; i++) {
9475 if ((i & (RFPL - 1)) == 0)
9476 cpu_fprintf(f, "FPR%02d", i);
9477 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9478 if ((i & (RFPL - 1)) == (RFPL - 1))
9479 cpu_fprintf(f, "\n");
9480 }
9481 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9482 #if !defined(CONFIG_USER_ONLY)
9483 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9484 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9485 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9486 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9487
9488 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9489 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9490 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9491 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9492
9493 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9494 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9495 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9496 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9497
9498 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9499 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9500 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9501 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9502 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9503
9504 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9505 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9506 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9507 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9508
9509 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9510 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9511 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9512 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9513
9514 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9515 " EPR " TARGET_FMT_lx "\n",
9516 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9517 env->spr[SPR_BOOKE_EPR]);
9518
9519 /* FSL-specific */
9520 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9521 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9522 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9523 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9524
9525 /*
9526 * IVORs are left out as they are large and do not change often --
9527 * they can be read with "p $ivor0", "p $ivor1", etc.
9528 */
9529 }
9530
9531 #if defined(TARGET_PPC64)
9532 if (env->flags & POWERPC_FLAG_CFAR) {
9533 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9534 }
9535 #endif
9536
9537 switch (env->mmu_model) {
9538 case POWERPC_MMU_32B:
9539 case POWERPC_MMU_601:
9540 case POWERPC_MMU_SOFT_6xx:
9541 case POWERPC_MMU_SOFT_74xx:
9542 #if defined(TARGET_PPC64)
9543 case POWERPC_MMU_620:
9544 case POWERPC_MMU_64B:
9545 #endif
9546 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9547 break;
9548 case POWERPC_MMU_BOOKE206:
9549 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9550 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9551 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9552 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9553
9554 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9555 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9556 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9557 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9558
9559 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9560 " TLB1CFG " TARGET_FMT_lx "\n",
9561 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9562 env->spr[SPR_BOOKE_TLB1CFG]);
9563 break;
9564 default:
9565 break;
9566 }
9567 #endif
9568
9569 #undef RGPL
9570 #undef RFPL
9571 }
9572
9573 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9574 int flags)
9575 {
9576 #if defined(DO_PPC_STATISTICS)
9577 opc_handler_t **t1, **t2, **t3, *handler;
9578 int op1, op2, op3;
9579
9580 t1 = env->opcodes;
9581 for (op1 = 0; op1 < 64; op1++) {
9582 handler = t1[op1];
9583 if (is_indirect_opcode(handler)) {
9584 t2 = ind_table(handler);
9585 for (op2 = 0; op2 < 32; op2++) {
9586 handler = t2[op2];
9587 if (is_indirect_opcode(handler)) {
9588 t3 = ind_table(handler);
9589 for (op3 = 0; op3 < 32; op3++) {
9590 handler = t3[op3];
9591 if (handler->count == 0)
9592 continue;
9593 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9594 "%016" PRIx64 " %" PRId64 "\n",
9595 op1, op2, op3, op1, (op3 << 5) | op2,
9596 handler->oname,
9597 handler->count, handler->count);
9598 }
9599 } else {
9600 if (handler->count == 0)
9601 continue;
9602 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9603 "%016" PRIx64 " %" PRId64 "\n",
9604 op1, op2, op1, op2, handler->oname,
9605 handler->count, handler->count);
9606 }
9607 }
9608 } else {
9609 if (handler->count == 0)
9610 continue;
9611 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9612 " %" PRId64 "\n",
9613 op1, op1, handler->oname,
9614 handler->count, handler->count);
9615 }
9616 }
9617 #endif
9618 }
9619
9620 /*****************************************************************************/
9621 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9622 TranslationBlock *tb,
9623 int search_pc)
9624 {
9625 DisasContext ctx, *ctxp = &ctx;
9626 opc_handler_t **table, *handler;
9627 target_ulong pc_start;
9628 uint16_t *gen_opc_end;
9629 CPUBreakpoint *bp;
9630 int j, lj = -1;
9631 int num_insns;
9632 int max_insns;
9633
9634 pc_start = tb->pc;
9635 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9636 ctx.nip = pc_start;
9637 ctx.tb = tb;
9638 ctx.exception = POWERPC_EXCP_NONE;
9639 ctx.spr_cb = env->spr_cb;
9640 ctx.mem_idx = env->mmu_idx;
9641 ctx.access_type = -1;
9642 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9643 #if defined(TARGET_PPC64)
9644 ctx.sf_mode = msr_is_64bit(env, env->msr);
9645 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9646 #endif
9647 ctx.fpu_enabled = msr_fp;
9648 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9649 ctx.spe_enabled = msr_spe;
9650 else
9651 ctx.spe_enabled = 0;
9652 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9653 ctx.altivec_enabled = msr_vr;
9654 else
9655 ctx.altivec_enabled = 0;
9656 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9657 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9658 else
9659 ctx.singlestep_enabled = 0;
9660 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9661 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9662 if (unlikely(env->singlestep_enabled))
9663 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9664 #if defined (DO_SINGLE_STEP) && 0
9665 /* Single step trace mode */
9666 msr_se = 1;
9667 #endif
9668 num_insns = 0;
9669 max_insns = tb->cflags & CF_COUNT_MASK;
9670 if (max_insns == 0)
9671 max_insns = CF_COUNT_MASK;
9672
9673 gen_icount_start();
9674 /* Set env in case of segfault during code fetch */
9675 while (ctx.exception == POWERPC_EXCP_NONE
9676 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9677 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9678 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9679 if (bp->pc == ctx.nip) {
9680 gen_debug_exception(ctxp);
9681 break;
9682 }
9683 }
9684 }
9685 if (unlikely(search_pc)) {
9686 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9687 if (lj < j) {
9688 lj++;
9689 while (lj < j)
9690 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9691 }
9692 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9693 tcg_ctx.gen_opc_instr_start[lj] = 1;
9694 tcg_ctx.gen_opc_icount[lj] = num_insns;
9695 }
9696 LOG_DISAS("----------------\n");
9697 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9698 ctx.nip, ctx.mem_idx, (int)msr_ir);
9699 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9700 gen_io_start();
9701 if (unlikely(ctx.le_mode)) {
9702 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9703 } else {
9704 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9705 }
9706 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9707 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9708 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9709 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9710 tcg_gen_debug_insn_start(ctx.nip);
9711 }
9712 ctx.nip += 4;
9713 table = env->opcodes;
9714 num_insns++;
9715 handler = table[opc1(ctx.opcode)];
9716 if (is_indirect_opcode(handler)) {
9717 table = ind_table(handler);
9718 handler = table[opc2(ctx.opcode)];
9719 if (is_indirect_opcode(handler)) {
9720 table = ind_table(handler);
9721 handler = table[opc3(ctx.opcode)];
9722 }
9723 }
9724 /* Is opcode *REALLY* valid ? */
9725 if (unlikely(handler->handler == &gen_invalid)) {
9726 if (qemu_log_enabled()) {
9727 qemu_log("invalid/unsupported opcode: "
9728 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9729 opc1(ctx.opcode), opc2(ctx.opcode),
9730 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9731 }
9732 } else {
9733 uint32_t inval;
9734
9735 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9736 inval = handler->inval2;
9737 } else {
9738 inval = handler->inval1;
9739 }
9740
9741 if (unlikely((ctx.opcode & inval) != 0)) {
9742 if (qemu_log_enabled()) {
9743 qemu_log("invalid bits: %08x for opcode: "
9744 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9745 ctx.opcode & inval, opc1(ctx.opcode),
9746 opc2(ctx.opcode), opc3(ctx.opcode),
9747 ctx.opcode, ctx.nip - 4);
9748 }
9749 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9750 break;
9751 }
9752 }
9753 (*(handler->handler))(&ctx);
9754 #if defined(DO_PPC_STATISTICS)
9755 handler->count++;
9756 #endif
9757 /* Check trace mode exceptions */
9758 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9759 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9760 ctx.exception != POWERPC_SYSCALL &&
9761 ctx.exception != POWERPC_EXCP_TRAP &&
9762 ctx.exception != POWERPC_EXCP_BRANCH)) {
9763 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9764 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9765 (env->singlestep_enabled) ||
9766 singlestep ||
9767 num_insns >= max_insns)) {
9768 /* if we reach a page boundary or are single stepping, stop
9769 * generation
9770 */
9771 break;
9772 }
9773 }
9774 if (tb->cflags & CF_LAST_IO)
9775 gen_io_end();
9776 if (ctx.exception == POWERPC_EXCP_NONE) {
9777 gen_goto_tb(&ctx, 0, ctx.nip);
9778 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9779 if (unlikely(env->singlestep_enabled)) {
9780 gen_debug_exception(ctxp);
9781 }
9782 /* Generate the return instruction */
9783 tcg_gen_exit_tb(0);
9784 }
9785 gen_icount_end(tb, num_insns);
9786 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9787 if (unlikely(search_pc)) {
9788 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9789 lj++;
9790 while (lj <= j)
9791 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9792 } else {
9793 tb->size = ctx.nip - pc_start;
9794 tb->icount = num_insns;
9795 }
9796 #if defined(DEBUG_DISAS)
9797 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9798 int flags;
9799 flags = env->bfd_mach;
9800 flags |= ctx.le_mode << 16;
9801 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9802 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9803 qemu_log("\n");
9804 }
9805 #endif
9806 }
9807
9808 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9809 {
9810 gen_intermediate_code_internal(env, tb, 0);
9811 }
9812
9813 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9814 {
9815 gen_intermediate_code_internal(env, tb, 1);
9816 }
9817
9818 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9819 {
9820 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9821 }
Qemu copy for testing